diff --git a/.mailmap b/.mailmap index da4afd2b24152..9e9023c8f0f76 100644 --- a/.mailmap +++ b/.mailmap @@ -377,7 +377,9 @@ Jesper Dangaard Brouer Jesper Dangaard Brouer Jesper Dangaard Brouer Jesper Dangaard Brouer -Jessica Zhang +Jessica Zhang +Jessica Zhang +Jessica Zhang Jilai Wang Jiri Kosina Jiri Kosina @@ -490,6 +492,7 @@ Lorenzo Pieralisi Lorenzo Stoakes Luca Ceresoli Luca Weiss +Lucas De Marchi Lukasz Luba Luo Jie Lance Yang diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon index d9e2b17c68720..55ab45f669acf 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon @@ -109,6 +109,22 @@ Description: RO. Package current voltage in millivolt. Only supported for particular Intel Xe graphics platforms. +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp2_crit +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Package critical temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp2_emergency +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Package shutdown temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp2_input Date: March 2025 KernelVersion: 6.15 @@ -117,6 +133,30 @@ Description: RO. Package temperature in millidegree Celsius. Only supported for particular Intel Xe graphics platforms. +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp2_max +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Package maximum temperature limit in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp3_crit +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. VRAM critical temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp3_emergency +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. VRAM shutdown temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp3_input Date: March 2025 KernelVersion: 6.15 @@ -125,6 +165,76 @@ Description: RO. VRAM temperature in millidegree Celsius. Only supported for particular Intel Xe graphics platforms. +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp4_crit +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Memory controller critical temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp4_emergency +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Memory controller shutdown temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp4_input +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. Memory controller average temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp5_crit +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. GPU PCIe critical temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp5_emergency +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. GPU PCIe shutdown temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp5_input +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. GPU PCIe temperature in millidegree Celsius. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp[6-21]_crit +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. VRAM channel critical temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp[6-21]_emergency +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. VRAM channel shutdown temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + +What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/temp[6-21]_input +Date: January 2026 +KernelVersion: 7.0 +Contact: intel-xe@lists.freedesktop.org +Description: RO. VRAM channel temperature in millidegree Celsius. + + Only supported for particular Intel Xe graphics platforms. + What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon/fan1_input Date: March 2025 KernelVersion: 6.16 diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-sriov b/Documentation/ABI/testing/sysfs-driver-intel-xe-sriov index 2fd7e9b7bacc0..7f5ef9eada531 100644 --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-sriov +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-sriov @@ -119,7 +119,7 @@ Description: The GT preemption timeout (PT) in [us] to be applied to all functions. See sriov_admin/{pf,vf}/profile/preempt_timeout_us for more details. - sched_priority: (RW/RO) string + sched_priority: (WO) string The GT scheduling priority to be applied for all functions. See sriov_admin/{pf,vf}/profile/sched_priority for more details. diff --git a/Documentation/ABI/testing/sysfs-kernel-dmabuf-buffers b/Documentation/ABI/testing/sysfs-kernel-dmabuf-buffers deleted file mode 100644 index 5d3bc997dc640..0000000000000 --- a/Documentation/ABI/testing/sysfs-kernel-dmabuf-buffers +++ /dev/null @@ -1,24 +0,0 @@ -What: /sys/kernel/dmabuf/buffers -Date: May 2021 -KernelVersion: v5.13 -Contact: Hridya Valsaraju -Description: The /sys/kernel/dmabuf/buffers directory contains a - snapshot of the internal state of every DMA-BUF. - /sys/kernel/dmabuf/buffers/ will contain the - statistics for the DMA-BUF with the unique inode number - -Users: kernel memory tuning/debugging tools - -What: /sys/kernel/dmabuf/buffers//exporter_name -Date: May 2021 -KernelVersion: v5.13 -Contact: Hridya Valsaraju -Description: This file is read-only and contains the name of the exporter of - the DMA-BUF. - -What: /sys/kernel/dmabuf/buffers//size -Date: May 2021 -KernelVersion: v5.13 -Contact: Hridya Valsaraju -Description: This file is read-only and specifies the size of the DMA-BUF in - bytes. diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index 5a99d9b9635e7..c20625b8425ef 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,21 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: + oneOf: + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi + + - items: + - const: renesas,r9a09g056-mipi-dsi # RZ/V2N + - const: renesas,r9a09g057-mipi-dsi + - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) reg: maxItems: 1 @@ -49,34 +54,56 @@ properties: - const: debug clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL reference clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllrefclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst power-domains: maxItems: 1 @@ -130,6 +157,41 @@ required: unevaluatedProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index 20c7e0a77802f..e6808419f6254 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -27,6 +27,7 @@ properties: - const: adi,adv7123 - enum: - adi,adv7123 + - algoltek,ag6311 - asl-tek,cs5263 - dumb-vga-dac - parade,ps185hdm diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 4400d4cce0722..eb6d38dabb08e 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,apq8064-dsi-ctrl + - qcom,kaanapali-dsi-ctrl - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl @@ -45,6 +46,11 @@ properties: - qcom,sm8650-dsi-ctrl - qcom,sm8750-dsi-ctrl - const: qcom,mdss-dsi-ctrl + - items: + - enum: + - qcom,qcs8300-dsi-ctrl + - const: qcom,sa8775p-dsi-ctrl + - const: qcom,mdss-dsi-ctrl - enum: - qcom,dsi-ctrl-6g-qcm2290 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible @@ -369,6 +375,7 @@ allOf: compatible: contains: enum: + - qcom,kaanapali-dsi-ctrl - qcom,sm8750-dsi-ctrl then: properties: diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 1ca820a500b72..9a9a6c4abf43d 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -14,18 +14,25 @@ allOf: properties: compatible: - enum: - - qcom,dsi-phy-7nm - - qcom,dsi-phy-7nm-8150 - - qcom,sa8775p-dsi-phy-5nm - - qcom,sar2130p-dsi-phy-5nm - - qcom,sc7280-dsi-phy-7nm - - qcom,sm6375-dsi-phy-7nm - - qcom,sm8350-dsi-phy-5nm - - qcom,sm8450-dsi-phy-5nm - - qcom,sm8550-dsi-phy-4nm - - qcom,sm8650-dsi-phy-4nm - - qcom,sm8750-dsi-phy-3nm + oneOf: + - items: + - enum: + - qcom,dsi-phy-7nm + - qcom,dsi-phy-7nm-8150 + - qcom,kaanapali-dsi-phy-3nm + - qcom,sa8775p-dsi-phy-5nm + - qcom,sar2130p-dsi-phy-5nm + - qcom,sc7280-dsi-phy-7nm + - qcom,sm6375-dsi-phy-7nm + - qcom,sm8350-dsi-phy-5nm + - qcom,sm8450-dsi-phy-5nm + - qcom,sm8550-dsi-phy-4nm + - qcom,sm8650-dsi-phy-4nm + - qcom,sm8750-dsi-phy-3nm + - items: + - enum: + - qcom,qcs8300-dsi-phy-5nm + - const: qcom,sa8775p-dsi-phy-5nm reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 826aafdcc20be..ec84b64d4c00b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -45,11 +45,11 @@ properties: - const: amd,imageon clocks: - minItems: 2 + minItems: 1 maxItems: 7 clock-names: - minItems: 2 + minItems: 1 maxItems: 7 reg: @@ -378,35 +378,74 @@ allOf: - const: xo description: GPUCC clocksource clock + required: + - clocks + - clock-names + + - if: + properties: + compatible: + contains: + const: qcom,adreno-612.0 + then: + properties: + clocks: + items: + - description: GPU Core clock + + clock-names: + items: + - const: core + + reg: + minItems: 3 + maxItems: 3 + reg-names: - minItems: 1 items: - const: kgsl_3d0_reg_memory + - const: cx_mem - const: cx_dbgc required: - clocks - clock-names - else: - if: - properties: - compatible: - contains: - oneOf: - - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' - - pattern: '^qcom,adreno-[0-9a-f]{8}$' - - then: # Starting with A6xx, the clocks are usually defined in the GMU node - properties: - clocks: false - clock-names: false - - reg-names: - minItems: 1 - items: - - const: kgsl_3d0_reg_memory - - const: cx_mem - - const: cx_dbgc + + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-615.0 + - qcom,adreno-618.0 + - qcom,adreno-619.0 + - qcom,adreno-621.0 + - qcom,adreno-623.0 + - qcom,adreno-630.2 + - qcom,adreno-635.0 + - qcom,adreno-640.1 + - qcom,adreno-650.2 + - qcom,adreno-660.1 + - qcom,adreno-663.0 + - qcom,adreno-680.1 + - qcom,adreno-690.0 + - qcom,adreno-730.1 + - qcom,adreno-43030c00 + - qcom,adreno-43050a01 + - qcom,adreno-43050c01 + - qcom,adreno-43051401 + + then: # Starting with A6xx, the clocks are usually defined in the GMU node + properties: + clocks: false + clock-names: false + + reg-names: + minItems: 1 + items: + - const: kgsl_3d0_reg_memory + - const: cx_mem + - const: cx_dbgc examples: - | diff --git a/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml new file mode 100644 index 0000000000000..bacc5b32e6d7b --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/display/msm/qcom,adreno-rgmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RGMU attached to certain Adreno GPUs + +maintainers: + - Rob Clark + +description: + RGMU (Reduced Graphics Management Unit) IP is present in some GPUs that + belong to Adreno A6xx family. It is a small state machine that helps to + toggle the GX GDSC (connected to CX rail) to implement IFPC feature and save + power. + +properties: + compatible: + items: + - const: qcom,adreno-rgmu-612.0 + - const: qcom,adreno-rgmu + + reg: + items: + - description: Core RGMU registers + + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU SMMU vote clock + + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: smmu_vote + + power-domains: + items: + - description: CX GDSC power domain + - description: GX GDSC power domain + + power-domain-names: + items: + - const: cx + - const: gx + + interrupts: + items: + - description: GMU OOB interrupt + - description: GMU interrupt + + interrupt-names: + items: + - const: oob + - const: gmu + + operating-points-v2: true + opp-table: + type: object + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - power-domain-names + - interrupts + - interrupt-names + - operating-points-v2 + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + gmu@506a000 { + compatible = "qcom,adreno-rgmu-612.0", "qcom,adreno-rgmu"; + + reg = <0x05000000 0x90000>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "smmu_vote"; + + power-domains = <&gpucc CX_GDSC>, + <&gpucc GX_GDSC>; + power-domain-names = "cx", + "gx"; + + interrupts = , + ; + interrupt-names = "oob", + "gmu"; + + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml new file mode 100644 index 0000000000000..9f935defd6b12 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,kaanapali-mdss.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,kaanapali-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali Display MDSS + +maintainers: + - Yongxing Mou + - Yuanjie Yang + +description: + Kaanapali MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + - description: Display AHB SWI + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dpu + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,kaanapali-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,kaanapali-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@9800000 { + compatible = "qcom,kaanapali-mdss"; + reg = <0x09800000 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_ahb_swi_clk>; + resets = <&disp_cc_mdss_core_bcr>; + + power-domains = <&mdss_gdsc>; + + iommus = <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@9801000 { + compatible = "qcom,kaanapali-dpu"; + reg = <0x09801000 0x1c8000>, + <0x09b16000 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-156000000 { + opp-hz = /bits/ 64 <156000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-207000000 { + opp-hz = /bits/ 64 <207000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz = /bits/ 64 <337000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz = /bits/ 64 <417000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz = /bits/ 64 <532000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@9ac0000 { + compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x09ac0000 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@9ac1000 { + compatible = "qcom,kaanapali-dsi-phy-3nm"; + reg = <0x09ac1000 0x1cc>, + <0x09ac1200 0x80>, + <0x09ac1500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml index e96baaae9ba9e..c41a86203e78a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -53,13 +53,23 @@ patternProperties: contains: const: qcom,qcs8300-dp + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,qcs8300-dsi-ctrl + "^phy@[0-9a-f]+$": type: object additionalProperties: true properties: compatible: contains: - const: qcom,qcs8300-edp-phy + enum: + - qcom,qcs8300-dsi-phy-5nm + - qcom,qcs8300-edp-phy required: - compatible @@ -71,6 +81,7 @@ examples: #include #include #include + #include #include #include #include @@ -142,6 +153,13 @@ examples: remote-endpoint = <&mdss_dp0_in>; }; }; + + port@1 { + reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -169,6 +187,88 @@ examples: }; }; + dsi@ae94000 { + compatible = "qcom,qcs8300-dsi-ctrl", + "qcom,sa8775p-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + phys = <&mdss_dsi0_phy>; + + operating-points-v2 = <&dsi0_opp_table>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + + vdda-supply = <&vreg_l5a>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss0_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss0_dsi0_out: endpoint { }; + }; + }; + + dsi0_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,qcs8300-dsi-phy-5nm", + "qcom,sa8775p-dsi-phy-5nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x27c>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + vdds-supply = <&vreg_l4a>; + }; + mdss_dp0_phy: phy@aec2a00 { compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index fe296e3186d0e..e29c4687c3a2e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -16,6 +16,7 @@ properties: oneOf: - enum: - qcom,glymur-dpu + - qcom,kaanapali-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml index b8783eba3ddc6..5802fb3c9ffe2 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml @@ -16,6 +16,8 @@ properties: compatible: items: - enum: + - anbernic,rg-ds-display-bottom + - anbernic,rg-ds-display-top - chongzhou,cz101b4001 - kingdisplay,kd101ne3-40ti - melfas,lmfbx101117480 diff --git a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml index 2219d3d4ac43b..f641efaeb8b36 100644 --- a/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml +++ b/Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/display/panel/lg,sw43408.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: LG SW43408 1080x2160 DSI panel +title: LG SW43408 AMOLED DDIC maintainers: - Casey Connolly description: - This panel is used on the Pixel 3, it is a 60hz OLED panel which - required DSC (Display Stream Compression) and has rounded corners. + The SW43408 is display driver IC with connected panel. + + LG LH546WF1-ED01 panel is used on the Pixel 3, it is a 60hz OLED panel + which required DSC (Display Stream Compression) and has rounded corners. allOf: - $ref: panel-common.yaml# @@ -19,6 +21,9 @@ allOf: properties: compatible: items: + - enum: + # LG 5.46 inch, 1080x2160 pixels, 18:9 ratio + - lg,sw43408-lh546wf1-ed01 - const: lg,sw43408 reg: @@ -46,7 +51,7 @@ examples: #size-cells = <0>; panel@0 { - compatible = "lg,sw43408"; + compatible = "lg,sw43408-lh546wf1-ed01", "lg,sw43408"; reg = <0>; vddi-supply = <&vreg_l14a_1p88>; diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index 8d668979b62df..2f90c887b7b89 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -55,6 +55,8 @@ properties: - panasonic,vvx10f004b00 # Panasonic 10" WUXGA TFT LCD panel - panasonic,vvx10f034n00 + # Samsung ltl106hl02 10.6" Full HD TFT LCD panel + - samsung,ltl106hl02-001 # Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel - samsung,s6e3fa7-ams559nk06 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 24e277b190941..868edb04989a5 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -154,6 +154,8 @@ properties: - hannstar,hsd070pww1 # HannStar Display Corp. HSD100PXN1 10.1" XGA LVDS panel - hannstar,hsd100pxn1 + # HannStar Display Corp. HSD156JUW2 15.6" FHD (1920x1080) TFT LCD panel + - hannstar,hsd156juw2 # Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel - hit,tx23d38vm0caa # Innolux AT043TN24 4.3" WQVGA TFT LCD panel @@ -176,6 +178,8 @@ properties: - innolux,g121x1-l03 # Innolux Corporation 12.1" G121XCE-L01 XGA (1024x768) TFT LCD panel - innolux,g121xce-l01 + # InnoLux 15.0" G150XGE-L05 XGA (1024x768) TFT LCD panel + - innolux,g150xge-l05 # InnoLux 15.6" FHD (1920x1080) TFT LCD panel - innolux,g156hce-l01 # InnoLux 13.3" FHD (1920x1080) TFT LCD panel @@ -347,7 +351,9 @@ if: properties: compatible: contains: - const: innolux,g101ice-l01 + enum: + - innolux,g101ice-l01 + - yes-optoelectronics,ytc700tlag-05-201c then: properties: data-mapping: false diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml index d48354fb52ea0..fd4388f5fb118 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml @@ -6,11 +6,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung S6E3FC2X01 AMOLED DDIC -description: The S6E3FC2X01 is display driver IC with connected panel. - maintainers: - David Heidelberg +description: The S6E3FC2X01 is display driver IC with connected panel. + allOf: - $ref: panel-common.yaml# @@ -25,25 +25,21 @@ properties: reg: maxItems: 1 - reset-gpios: true - - port: true - - vddio-supply: - description: VDD regulator + poc-supply: + description: POC regulator vci-supply: description: VCI regulator - poc-supply: - description: POC regulator + vddio-supply: + description: VDD regulator required: - compatible - reset-gpios - - vddio-supply - - vci-supply - poc-supply + - vci-supply + - vddio-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml index 9d096856a79a6..29716764413a8 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml @@ -23,6 +23,7 @@ properties: - rockchip,rk3228-dw-hdmi - rockchip,rk3288-dw-hdmi - rockchip,rk3328-dw-hdmi + - rockchip,rk3368-dw-hdmi - rockchip,rk3399-dw-hdmi - rockchip,rk3568-dw-hdmi diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index 632b48bfabb94..b968f2de93f7b 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3288-mipi-dsi - rockchip,rk3368-mipi-dsi - rockchip,rk3399-mipi-dsi + - rockchip,rk3506-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi - const: snps,dw-mipi-dsi @@ -75,6 +76,7 @@ allOf: - rockchip,px30-mipi-dsi - rockchip,rk3128-mipi-dsi - rockchip,rk3368-mipi-dsi + - rockchip,rk3506-mipi-dsi - rockchip,rk3568-mipi-dsi - rockchip,rv1126-mipi-dsi diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml index d649808c59da8..70ac6751bdbaf 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml @@ -69,6 +69,12 @@ properties: - const: main - const: hpd + no-hpd: + type: boolean + description: + The HPD pin is not present or used for another purpose, and the EDID + must be polled instead to determine if a device is attached. + phys: maxItems: 1 description: The HDMI/eDP PHY diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml index 8b5f58103dda9..fdf4b1109da21 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3368-vop - rockchip,rk3399-vop-big - rockchip,rk3399-vop-lit + - rockchip,rk3506-vop - rockchip,rv1126-vop reg: diff --git a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml index b83721eb4b7f8..1931a47c42171 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml +++ b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml @@ -76,3 +76,28 @@ examples: }; }; }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "sitronix,st7571"; + reg = <0>; + reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + width-mm = <37>; + height-mm = <27>; + + panel-timing { + hactive = <128>; + vactive = <96>; + hback-porch = <0>; + vback-porch = <0>; + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/sitronix,st7920.yaml b/Documentation/devicetree/bindings/display/sitronix,st7920.yaml new file mode 100644 index 0000000000000..c4f006fc41e1f --- /dev/null +++ b/Documentation/devicetree/bindings/display/sitronix,st7920.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/sitronix,st7920.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sitronix ST7920 LCD Display Controllers + +maintainers: + - Iker Pedrosa + +description: + The Sitronix ST7920 is a controller for monochrome dot-matrix graphical LCDs, + most commonly used for 128x64 pixel displays. + +properties: + compatible: + const: sitronix,st7920 + + reg: + maxItems: 1 + + vdd-supply: + description: Regulator that provides 5V Vdd power supply + + reset-gpios: + maxItems: 1 + + spi-max-frequency: + maximum: 600000 + +required: + - compatible + - reg + - spi-max-frequency + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + display@0 { + compatible = "sitronix,st7920"; + reg = <0>; + vdd-supply = <®_5v>; + reset-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; + spi-max-frequency = <600000>; + spi-cs-high; + }; + }; diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index bee9faf1d3f82..8eccd4338a2b2 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -51,6 +51,14 @@ properties: - stacks - const: stacks + nvmem-cells: + items: + - description: bitmask of functional shader cores + + nvmem-cell-names: + items: + - const: shader-present + mali-supply: true operating-points-v2: true @@ -108,6 +116,8 @@ allOf: properties: clocks: minItems: 3 + nvmem-cells: false + nvmem-cell-names: false power-domains: maxItems: 1 power-domain-names: false @@ -133,6 +143,8 @@ allOf: - const: core - const: stacks required: + - nvmem-cells + - nvmem-cell-names - power-domains examples: @@ -179,6 +191,8 @@ examples: , ; interrupt-names = "job", "mmu", "gpu"; + nvmem-cells = <&shader_present>; + nvmem-cell-names = "shader-present"; power-domains = <&gpufreq>; }; diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 86ef689853177..a1f54dbae3f31 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -40,6 +40,7 @@ properties: - const: img,img-rogue - items: - enum: + - ti,am62p-gpu - ti,j721s2-gpu - const: img,img-bxs-4-64 - const: img,img-rogue @@ -100,6 +101,7 @@ allOf: contains: enum: - ti,am62-gpu + - ti,am62p-gpu - ti,j721s2-gpu then: properties: diff --git a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml index f3a8b0b745d13..ac93069f48013 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml @@ -26,6 +26,10 @@ properties: - enum: - mediatek,mt7623-hdmi-phy - const: mediatek,mt2701-hdmi-phy + - items: + - enum: + - mediatek,mt8188-hdmi-phy + - const: mediatek,mt8195-hdmi-phy - const: mediatek,mt2701-hdmi-phy - const: mediatek,mt8173-hdmi-phy - const: mediatek,mt8195-hdmi-phy @@ -34,16 +38,23 @@ properties: maxItems: 1 clocks: + minItems: 1 items: - description: PLL reference clock + - description: HDMI 26MHz clock + - description: HDMI PLL1 clock + - description: HDMI PLL2 clock clock-names: + minItems: 1 items: - const: pll_ref + - const: 26m + - const: pll1 + - const: pll2 clock-output-names: - items: - - const: hdmitx_dig_cts + maxItems: 1 "#phy-cells": const: 0 @@ -76,6 +87,20 @@ required: - "#phy-cells" - "#clock-cells" +allOf: + - if: + not: + properties: + compatible: + contains: + const: mediatek,mt8195-hdmi-phy + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index c7591b2aec2a7..d459886e515a6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -86,6 +86,8 @@ patternProperties: description: Aldec, Inc. "^alfa-network,.*": description: ALFA Network Inc. + "^algoltek,.*": + description: AlgolTek, Inc. "^allegro,.*": description: Allegro DVT "^allegromicro,.*": diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 29abf1eebf9fd..2f36c21d9948f 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -125,11 +125,6 @@ Implicit Fence Poll Support .. kernel-doc:: drivers/dma-buf/dma-buf.c :doc: implicit fence polling -DMA-BUF statistics -~~~~~~~~~~~~~~~~~~ -.. kernel-doc:: drivers/dma-buf/dma-buf-sysfs-stats.c - :doc: overview - DMA Buffer ioctls ~~~~~~~~~~~~~~~~~ diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg new file mode 100644 index 0000000000000..cbd705afc9e2d --- /dev/null +++ b/Documentation/gpu/amdgpu/amd_overview_block.svg @@ -0,0 +1,687 @@ + + + + + + + + + + + + + + + + + + + + + + UMC + + + + Memory hub + + + + + PSP + + + + + PCIe (NBIO) + + + SMU + + + + + + + SDMA + + + + + + + + + + Reset + + + + + PSP Interaction + + + + + + + + + + + + + + Firmware + + + + Memory + Memory + Memory + Memory + + + + UMC + + + UMC + + + Graphics & Compute (GC) + + ShaderEngine(SE)#1 + + + + SE #2 + + + + SE #N + + + ... + + + + + VCN + + + + DCN + + + diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index 30812d9d53c64..033167025fcca 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at CP Command Processor + CPC + Command Processor Compute + + CPF + Command Processor Fetch + + CPG + Command Processor Graphics + CPLIB Content Protection Library @@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at GMC Graphic Memory Controller + GPR + General Purpose Register + GPUVM GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple virtual address spaces that can be in flight at any given time. These @@ -92,9 +104,15 @@ we have a dedicated glossary for Display Core at table for use by the kernel driver or into per process GPUVM page tables for application usage. + GWS + Global Wave Sync + IH Interrupt Handler + IV + Interrupt Vector + HQD Hardware Queue Descriptor @@ -143,15 +161,24 @@ we have a dedicated glossary for Display Core at PA Primitive Assembler / Physical Address + PDE + Page Directory Entry + PFP Pre-Fetch Parser (Graphics) PPLib PowerPlay Library - PowerPlay is the power management component. + PRT + Partially Resident Texture (also known as sparse residency) + PSP Platform Security Processor + PTE + Page Table Entry + RB Render Backends. Some people called it ROPs. @@ -206,12 +233,33 @@ we have a dedicated glossary for Display Core at TC Texture Cache + TCP (AMDGPU) + Texture Cache per Pipe. Even though the name "Texture" is part of this + acronym, the TCP represents the path to memory shaders; i.e., it is not + related to texture. The name is a leftover from older designs where shader + stages had different cache designs; it refers to the L1 cache in older + architectures. + + TMR + Trusted Memory Region + + TMZ + Trusted Memory Zone + TOC Table of Contents + UMC + Unified Memory Controller + UMSCH User Mode Scheduler + UTC (AMDGPU) + Unified Translation Cache. UTC is equivalent to TLB. You might see a + variation of this acronym with L at the end, i.e., UTCL followed by a + number; L means the cache level (e.g., UTCL1 and UTCL2). + UVD Unified Video Decoder diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv b/Documentation/gpu/amdgpu/apu-asic-info-table.csv index dee5f663a47fb..f4c0f93c0582e 100644 --- a/Documentation/gpu/amdgpu/apu-asic-info-table.csv +++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv @@ -16,3 +16,6 @@ Ryzen AI 300 series, Strix Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0, 14.0.0 Ryzen AI 330 series, Krackan Point, 3.6.0, 11.5.3, 4.0.5, 6.1.3, 14.0.5, 14.0.5 Ryzen AI 350 series, Krackan Point, 3.5.0, 11.5.2, 4.0.5, 6.1.2, 14.0.4, 14.0.4 Ryzen AI Max 300 series, Strix Halo, 3.5.1, 11.5.1, 4.0.6, 6.1.1, 14.0.1, 14.0.1 +Ryzen AI 9 475 / 470 / 465, Gorgon Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0, 14.0.0 +Ryzen AI 7 450, Gorgon Point, 3.5.0, 11.5.2, 4.0.5, 6.1.2, 14.0.4, 14.0.4 +Ryzen AI 5 440 / 435, Gorgon Point, 3.6.0, 11.5.3, 4.0.5, 6.1.3, 14.0.5, 14.0.5 diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst index cbe737d1fcead..accb7c05308c5 100644 --- a/Documentation/gpu/amdgpu/display/dc-glossary.rst +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst @@ -221,9 +221,6 @@ consider asking on the amd-gfx mailing list and update this page. TMDS Transition-Minimized Differential Signaling - TMZ - Trusted Memory Zone - TTU Time to Underflow diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst index 3ce276272171e..2c2bbf7caf1a0 100644 --- a/Documentation/gpu/amdgpu/driver-core.rst +++ b/Documentation/gpu/amdgpu/driver-core.rst @@ -77,6 +77,37 @@ VCN (Video Core Next) decode. It's exposed to userspace for user mode drivers (VA-API, OpenMAX, etc.) +It is important to note that these blocks can interact with each other. The +picture below illustrates some of the components and their interconnection: + +.. kernel-figure:: amd_overview_block.svg + +In the diagram, memory-related blocks are shown in green. Notice that specific +IPs have a green square that represents a small hardware block named 'hub', +which is responsible for interfacing with memory. All memory hubs are connected +in the UMCs, which in turn are connected to memory blocks. As a note, +pre-vega devices have a dedicated block for the Graphic Memory Controller +(GMC), which was replaced by UMC and hubs in new architectures. In the driver +code, you can identify this component by looking for the suffix hub, for +example: gfxhub, dchub, mmhub, vmhub, etc. Keep in mind that the component's +interaction with the memory block may vary across architectures. For example, +on Navi and newer, GC and SDMA are both attached to GCHUB; on pre-Navi, SDMA +goes through MMHUB; VCN, JPEG, and VPE go through MMHUB; DCN goes through +DCHUB. + +There is some protection for certain memory elements, and the PSP plays an +essential role in this area. When a specific firmware is loaded into memory, +the PSP takes steps to ensure it has a valid signature. It also stores firmware +images in a protected memory area named Trusted Memory Area (TMR), so the OS or +driver can't corrupt them at runtime. Another use of PSP is to support Trusted +Applications (TA), which are basically small applications that run on the +trusted processor and handles a trusted operation (e.g., HDCP). PSP is also +used for encrypted memory for content protection via Trusted Memory Zone (TMZ). + +Another critical IP is the SMU. It handles reset distribution, as well as +clock, thermal, and power management for all IPs on the SoC. SMU also helps to +balance performance and power consumption. + .. _pipes-and-queues-description: GFX, Compute, and SDMA Overall Behavior diff --git a/Documentation/gpu/amdgpu/driver-misc.rst b/Documentation/gpu/amdgpu/driver-misc.rst index 25b0c857816ea..e1a964c3add2a 100644 --- a/Documentation/gpu/amdgpu/driver-misc.rst +++ b/Documentation/gpu/amdgpu/driver-misc.rst @@ -128,3 +128,29 @@ smartshift_bias .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c :doc: smartshift_bias + +UMA Carveout +============ + +Some versions of Atom ROM expose available options for the VRAM carveout sizes, +and allow changes to the carveout size via the ATCS function code 0xA on supported +BIOS implementations. + +For those platforms, users can use the following files under uma/ to set the +carveout size, in a way similar to what Windows users can do in the "Tuning" +tab in AMD Adrenalin. + +Note that for BIOS implementations that don't support this, these files will not +be created at all. + +uma/carveout_options +-------------------- + +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + :doc: uma/carveout_options + +uma/carveout +-------------------- + +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + :doc: uma/carveout diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg new file mode 100644 index 0000000000000..2630681f1cb99 --- /dev/null +++ b/Documentation/gpu/amdgpu/enforce_isolation.svg @@ -0,0 +1,654 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GFX + Compute + + Processes + + + + + + A + + + + B + + A + RingBuffer + + + + + + + + + + + + + + + + + + RingBuffer + + A + A + + A + A + C + C + B + B + B + + + A + A + C + C + C + C + + + + C + + + + Enforce Isolation + + + + + + + + + diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst index ff6e9ef5cbeec..b6b583c9dc6a4 100644 --- a/Documentation/gpu/amdgpu/gc/index.rst +++ b/Documentation/gpu/amdgpu/gc/index.rst @@ -7,19 +7,21 @@ The relationship between the CPU and GPU can be described as the producer-consumer problem, where the CPU fills out a buffer with operations (producer) to be executed by the GPU (consumer). The requested operations in -the buffer are called Command Packets, which can be summarized as a compressed -way of transmitting command information to the graphics controller. +the buffer are called **Command Packets**, which can be summarized as a +compressed way of transmitting command information to the graphics controller. The component that acts as the front end between the CPU and the GPU is called -the Command Processor (CP). This component is responsible for providing greater -flexibility to the GC since CP makes it possible to program various aspects of -the GPU pipeline. CP also coordinates the communication between the CPU and GPU -via a mechanism named **Ring Buffers**, where the CPU appends information to -the buffer while the GPU removes operations. It is relevant to highlight that a -CPU can add a pointer to the Ring Buffer that points to another region of -memory outside the Ring Buffer, and CP can handle it; this mechanism is called -**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and -writes the operations to the correct hardware blocks. +**Command Processor (CP)**. This component is responsible for providing greater +flexibility to the **Graphics and Compute (GC)** since CP makes it possible to +program various aspects of the GPU pipeline. CP also coordinates the +communication between the CPU and GPU via a mechanism named **Ring Buffers**, +where the CPU appends information to the buffer while the GPU removes +operations. CP is also responsible for handling **Indirect Buffers (IB)**. + +For reference, internally the CP consists of several sub-blocks (CPC - CP +compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms +appear in register names, but this is more of an implementation detail and not +something that directly impacts driver programming or debugging. Graphics (GFX) and Compute Microcontrollers ------------------------------------------- diff --git a/Documentation/gpu/amdgpu/gfx_pipeline_seq.svg b/Documentation/gpu/amdgpu/gfx_pipeline_seq.svg new file mode 100644 index 0000000000000..2f2c8fa980594 --- /dev/null +++ b/Documentation/gpu/amdgpu/gfx_pipeline_seq.svg @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IBb + RingBuffer + IBc + + SX + GE + SPI + SC + PA + Cache + + + + + + + + + + + + + + SX + GE + SPI + SC + PA + Cache + + + + + + + + + diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index 45523e9860fc5..8732084186a48 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. .. toctree:: driver-core + ring-buffer amd-hardware-list-info module-parameters gc/index diff --git a/Documentation/gpu/amdgpu/no_enforce_isolation.svg b/Documentation/gpu/amdgpu/no_enforce_isolation.svg new file mode 100644 index 0000000000000..b224615e1611e --- /dev/null +++ b/Documentation/gpu/amdgpu/no_enforce_isolation.svg @@ -0,0 +1,707 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GFX + Compute + + Processes + + + + + + A + + + + B + + A + RingBuffer + + + + + + + + + + + + + + + + + + RingBuffer + + A + A + A + A + A + A + C + C + C + B + B + B + C + C + + + + + + + + + C + + + + + Enforce Isolation + + + + Enforce Isolation + + + + + + + + + + + diff --git a/Documentation/gpu/amdgpu/process-isolation.rst b/Documentation/gpu/amdgpu/process-isolation.rst index 25b06ffefc33a..03c4288aa8b17 100644 --- a/Documentation/gpu/amdgpu/process-isolation.rst +++ b/Documentation/gpu/amdgpu/process-isolation.rst @@ -1,3 +1,4 @@ +.. _amdgpu-process-isolation: .. SPDX-License-Identifier: GPL-2.0 ========================= diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst new file mode 100644 index 0000000000000..cc642c21316ba --- /dev/null +++ b/Documentation/gpu/amdgpu/ring-buffer.rst @@ -0,0 +1,95 @@ +============= + Ring Buffer +============= + +To handle communication between user space and kernel space, AMD GPUs use a +ring buffer design to feed the engines (GFX, Compute, SDMA, UVD, VCE, VCN, VPE, +etc.). See the figure below that illustrates how this communication works: + +.. kernel-figure:: ring_buffers.svg + +Ring buffers in the amdgpu work as a producer-consumer model, where userspace +acts as the producer, constantly filling the ring buffer with GPU commands to +be executed. Meanwhile, the GPU retrieves the information from the ring, parses +it, and distributes the specific set of instructions between the different +amdgpu blocks. + +Notice from the diagram that the ring has a Read Pointer (rptr), which +indicates where the engine is currently reading packets from the ring, and a +Write Pointer (wptr), which indicates how many packets software has added to +the ring. When the rptr and wptr are equal, the ring is idle. When software +adds packets to the ring, it updates the wptr, this causes the engine to start +fetching and processing packets. As the engine processes packets, the rptr gets +updates until the rptr catches up to the wptr and they are equal again. + +Usually, ring buffers in the driver have a limited size (search for occurrences +of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is +that CP (Command Processor) is capable of following addresses inserted into the +ring; this is illustrated in the image by the reference to the IB (Indirect +Buffer). The IB gives userspace the possibility to have an area in memory that +CP can read and feed the hardware with extra instructions. + +All ASICs pre-GFX11 use what is called a kernel queue, which means +the ring is allocated in kernel space and has some restrictions, such as not +being able to be :ref:`preempted directly by the scheduler`. GFX11 +and newer support kernel queues, but also provide a new mechanism named +:ref:`user queues`, where the queue is moved to the user space +and can be mapped and unmapped via the scheduler. In practice, both queues +insert user-space-generated GPU commands from different jobs into the requested +component ring. + +Enforce Isolation +================= + +.. note:: After reading this section, you might want to check the + :ref:`Process Isolation` page for more details. + +Before examining the Enforce Isolation mechanism in the ring buffer context, it +is helpful to briefly discuss how instructions from the ring buffer are +processed in the graphics pipeline. Let’s expand on this topic by checking the +diagram below that illustrates the graphics pipeline: + +.. kernel-figure:: gfx_pipeline_seq.svg + +In terms of executing instructions, the GFX pipeline follows the sequence: +Shader Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan +Converter (SC), Primitive Assembler (PA), and cache manipulation (which may +vary across ASICs). Another common way to describe the pipeline is to use Pixel +Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader stages. +Now, with this pipeline in mind, let's assume that Job B causes a hang issue, +but Job C's instruction might already be executing, leading developers to +incorrectly identify Job C as the problematic one. This problem can be +mitigated on multiple levels; the diagram below illustrates how to minimize +part of this problem: + +.. kernel-figure:: no_enforce_isolation.svg + +Note from the diagram that there is no guarantee of order or a clear separation +between instructions, which is not a problem most of the time, and is also good +for performance. Furthermore, notice some circles between jobs in the diagram +that represent a **fence wait** used to avoid overlapping work in the ring. At +the end of the fence, a cache flush occurs, ensuring that when the next job +starts, it begins in a clean state and, if issues arise, the developer can +pinpoint the problematic process more precisely. + +To increase the level of isolation between jobs, there is the "Enforce +Isolation" method described in the picture below: + +.. kernel-figure:: enforce_isolation.svg + +As shown in the diagram, enforcing isolation introduces ordering between +submissions, since the access to GFX/Compute is serialized, think about it as +single process at a time mode for gfx/compute. Notice that this approach has a +significant performance impact, as it allows only one job to submit commands at +a time. However, this option can help pinpoint the job that caused the problem. +Although enforcing isolation improves the situation, it does not fully resolve +the issue of precisely pinpointing bad jobs, since isolation might mask the +problem. In summary, identifying which job caused the issue may not be precise, +but enforcing isolation might help with the debugging. + +Ring Operations +=============== + +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c + :internal: + diff --git a/Documentation/gpu/amdgpu/ring_buffers.svg b/Documentation/gpu/amdgpu/ring_buffers.svg new file mode 100644 index 0000000000000..7a6fcb19e1511 --- /dev/null +++ b/Documentation/gpu/amdgpu/ring_buffers.svg @@ -0,0 +1,1633 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GFX + Compute + SDMA + ... + + + + + + + + ... + ... + ... + + Kernel + Userspace + KernelQueue + Processes + + + A + + B + + C + + GPU + wptr + rptr + A + A + A + A + A + A + B + B + B + C + C + IBc + C + B + B + B + C + C + IBb + rptr + wptr + wptr + rptr + rptr + wptr + wptr + rptr + + + + + + + + + + + + PM41 + PM42 + PM4n + ... + + + + IBb + + + CP + + + + + RingBuffer + RingBuffer + RingBuffer + RingBuffer + RingBuffer + RingBuffer + RingBuffer + + + CP is capable offollowing theIB address. + + + + + + + + + diff --git a/Documentation/gpu/amdgpu/userq.rst b/Documentation/gpu/amdgpu/userq.rst index ca3ea71f7888b..88f54393b2201 100644 --- a/Documentation/gpu/amdgpu/userq.rst +++ b/Documentation/gpu/amdgpu/userq.rst @@ -1,3 +1,5 @@ +.. _amdgpu-userq: + ================== User Mode Queues ================== diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index d55751cad67cf..f22433470c761 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -155,7 +155,12 @@ drm_gem_object_init() will create an shmfs file of the requested size and store it into the struct :c:type:`struct drm_gem_object ` filp field. The memory is used as either main storage for the object when the graphics hardware -uses system memory directly or as a backing store otherwise. +uses system memory directly or as a backing store otherwise. Drivers +can call drm_gem_huge_mnt_create() to create, mount and use a huge +shmem mountpoint instead of the default one ('shm_mnt'). For builds +with CONFIG_TRANSPARENT_HUGEPAGE enabled, further calls to +drm_gem_object_init() will let shmem allocate huge pages when +possible. Drivers are responsible for the actual physical pages allocation by calling shmem_read_mapping_page_gfp() for each page. @@ -290,15 +295,27 @@ The open and close operations must update the GEM object reference count. Drivers can use the drm_gem_vm_open() and drm_gem_vm_close() helper functions directly as open and close handlers. -The fault operation handler is responsible for mapping individual pages -to userspace when a page fault occurs. Depending on the memory -allocation scheme, drivers can allocate pages at fault time, or can -decide to allocate memory for the GEM object at the time the object is -created. +The fault operation handler is responsible for mapping pages to +userspace when a page fault occurs. Depending on the memory allocation +scheme, drivers can allocate pages at fault time, or can decide to +allocate memory for the GEM object at the time the object is created. Drivers that want to map the GEM object upfront instead of handling page faults can implement their own mmap file operation handler. +In order to reduce page table overhead, if the internal shmem mountpoint +"shm_mnt" is configured to use transparent huge pages (for builds with +CONFIG_TRANSPARENT_HUGEPAGE enabled) and if the shmem backing store +managed to allocate a huge page for a faulty address, the fault handler +will first attempt to insert that huge page into the VMA before falling +back to individual page insertion. mmap() user address alignment for GEM +objects is handled by providing a custom get_unmapped_area file +operation which forwards to the shmem backing store. For most drivers, +which don't create a huge mountpoint by default or through a module +parameter, transparent huge pages can be enabled by either setting the +"transparent_hugepage_shmem" kernel parameter or the +"/sys/kernel/mm/transparent_hugepage/shmem_enabled" sysfs knob. + For platforms without MMU the GEM core provides a helper method drm_gem_dma_get_unmapped_area(). The mmap() routines will call this to get a proposed address for the mapping. diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/core/todo.rst index 35cc7c31d4239..d1964eb645e2d 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -41,8 +41,15 @@ trait [1] from the num crate. Having this generalization also helps with implementing a generic macro that automatically generates the corresponding mappings between a value and a number. +FromPrimitive support has been worked on in the past, but hasn't been followed +since then [1]. + +There also have been considerations of ToPrimitive [2]. + | Complexity: Beginner | Link: https://docs.rs/num/latest/num/trait.FromPrimitive.html +| Link: https://lore.kernel.org/all/cover.1750689857.git.y.j3ms.n@gmail.com/ [1] +| Link: https://rust-for-linux.zulipchat.com/#narrow/channel/288089-General/topic/Implement.20.60FromPrimitive.60.20trait.20.2B.20derive.20macro.20for.20nova-core/with/541971854 [2] Generic register abstraction [REGA] ----------------------------------- @@ -134,21 +141,6 @@ A `num` core kernel module is being designed to provide these operations. | Complexity: Intermediate | Contact: Alexandre Courbot -IRQ abstractions ----------------- - -Rust abstractions for IRQ handling. - -There is active ongoing work from Daniel Almeida [1] for the "core" abstractions -to request IRQs. - -Besides optional review and testing work, the required ``pci::Device`` code -around those core abstractions needs to be worked out. - -| Complexity: Intermediate -| Link: https://lore.kernel.org/lkml/20250122163932.46697-1-daniel.almeida@collabora.com/ [1] -| Contact: Daniel Almeida - Page abstraction for foreign pages ---------------------------------- @@ -161,40 +153,16 @@ There is active onging work from Abdiel Janulgue [1] and Lina [2]. | Link: https://lore.kernel.org/linux-mm/20241119112408.779243-1-abdiel.janulgue@gmail.com/ [1] | Link: https://lore.kernel.org/rust-for-linux/20250202-rust-page-v1-0-e3170d7fe55e@asahilina.net/ [2] -Scatterlist / sg_table abstractions ------------------------------------ - -Rust abstractions for scatterlist / sg_table. - -There is preceding work from Abdiel Janulgue, which hasn't made it to the -mailing list yet. - -| Complexity: Intermediate -| Contact: Abdiel Janulgue - PCI MISC APIs ------------- -Extend the existing PCI device / driver abstractions by SR-IOV, config space, -capability, MSI API abstractions. - -| Complexity: Beginner +Extend the existing PCI device / driver abstractions by SR-IOV, capability, MSI +API abstractions. -XArray bindings [XARR] ----------------------- - -We need bindings for `xa_alloc`/`xa_alloc_cyclic` in order to generate the -auxiliary device IDs. - -| Complexity: Intermediate +SR-IOV [1] is work in progress. -Debugfs abstractions --------------------- - -Rust abstraction for debugfs APIs. - -| Reference: Export GSP log buffers -| Complexity: Intermediate +| Complexity: Beginner +| Link: https://lore.kernel.org/all/20251119-rust-pci-sriov-v1-0-883a94599a97@redhat.com/ [1] GPU (general) ============= @@ -233,7 +201,10 @@ Some possible options: - maple_tree - native Rust collections +There is work in progress for using drm_buddy [1]. + | Complexity: Advanced +| Link: https://lore.kernel.org/all/20251219203805.1246586-4-joelagnelf@nvidia.com/ [1] Instance Memory --------------- diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index 9013ced318cb9..520da44a04a62 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -506,6 +506,22 @@ Contact: Maxime Ripard , Level: Intermediate +Convert users of of_drm_find_bridge() to of_drm_find_and_get_bridge() +--------------------------------------------------------------------- + +Taking a struct drm_bridge pointer requires getting a reference and putting +it after disposing of the pointer. Most functions returning a struct +drm_bridge pointer already call drm_bridge_get() to increment the refcount +and their users have been updated to call drm_bridge_put() when +appropriate. of_drm_find_bridge() does not get a reference and it has been +deprecated in favor of of_drm_find_and_get_bridge() which does, but some +users still need to be converted. + +Contact: Maxime Ripard , + Luca Ceresoli + +Level: Intermediate + Core refactorings ================= @@ -878,6 +894,51 @@ Contact: Christian König Level: Starter +DRM GPU Scheduler +================= + +Provide a universal successor for drm_sched_resubmit_jobs() +----------------------------------------------------------- + +drm_sched_resubmit_jobs() is deprecated. Main reason being that it leads to +reinitializing dma_fences. See that function's docu for details. The better +approach for valid resubmissions by amdgpu and Xe is (apparently) to figure out +which job (and, through association: which entity) caused the hang. Then, the +job's buffer data, together with all other jobs' buffer data currently in the +same hardware ring, must be invalidated. This can for example be done by +overwriting it. amdgpu currently determines which jobs are in the ring and need +to be overwritten by keeping copies of the job. Xe obtains that information by +directly accessing drm_sched's pending_list. + +Tasks: + +1. implement scheduler functionality through which the driver can obtain the + information which *broken* jobs are currently in the hardware ring. +2. Such infrastructure would then typically be used in + drm_sched_backend_ops.timedout_job(). Document that. +3. Port a driver as first user. +4. Document the new alternative in the docu of deprecated + drm_sched_resubmit_jobs(). + +Contact: Christian König + Philipp Stanner + +Level: Advanced + +Add locking for runqueues +------------------------- + +There is an old FIXME by Sima in include/drm/gpu_scheduler.h. It details that +struct drm_sched_rq is read at many places without any locks, not even with a +READ_ONCE. At XDC 2025 no one could really tell why that is the case, whether +locks are needed and whether they could be added. (But for real, that should +probably be locked!). Check whether it's possible to add locks everywhere, and +do so if yes. + +Contact: Philipp Stanner + +Level: Intermediate + Outside DRM =========== diff --git a/Documentation/gpu/xe/xe_exec_queue.rst b/Documentation/gpu/xe/xe_exec_queue.rst index 6076569e311cd..8707806211c9c 100644 --- a/Documentation/gpu/xe/xe_exec_queue.rst +++ b/Documentation/gpu/xe/xe_exec_queue.rst @@ -7,6 +7,20 @@ Execution Queue .. kernel-doc:: drivers/gpu/drm/xe/xe_exec_queue.c :doc: Execution Queue +Multi Queue Group +================= + +.. kernel-doc:: drivers/gpu/drm/xe/xe_exec_queue.c + :doc: Multi Queue Group + +.. _multi-queue-group-guc-interface: + +Multi Queue Group GuC interface +=============================== + +.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_submit.c + :doc: Multi Queue Group GuC interface + Internal API ============ diff --git a/Documentation/process/debugging/kgdb.rst b/Documentation/process/debugging/kgdb.rst index b29b0aac2717d..773b19aa13828 100644 --- a/Documentation/process/debugging/kgdb.rst +++ b/Documentation/process/debugging/kgdb.rst @@ -889,34 +889,6 @@ in the virtual console layer. On resuming kernel execution, the kernel debugger calls kgdboc_post_exp_handler() which in turn calls con_debug_leave(). -Any video driver that wants to be compatible with the kernel debugger -and the atomic kms callbacks must implement the ``mode_set_base_atomic``, -``fb_debug_enter`` and ``fb_debug_leave operations``. For the -``fb_debug_enter`` and ``fb_debug_leave`` the option exists to use the -generic drm fb helper functions or implement something custom for the -hardware. The following example shows the initialization of the -.mode_set_base_atomic operation in -drivers/gpu/drm/i915/intel_display.c:: - - - static const struct drm_crtc_helper_funcs intel_helper_funcs = { - [...] - .mode_set_base_atomic = intel_pipe_set_base_atomic, - [...] - }; - - -Here is an example of how the i915 driver initializes the -fb_debug_enter and fb_debug_leave functions to use the generic drm -helpers in ``drivers/gpu/drm/i915/intel_fb.c``:: - - - static struct fb_ops intelfb_ops = { - [...] - .fb_debug_enter = drm_fb_helper_debug_enter, - .fb_debug_leave = drm_fb_helper_debug_leave, - [...] - }; Credits diff --git a/MAINTAINERS b/MAINTAINERS index e087673237636..7866b42c70bc9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7990,6 +7990,7 @@ S: Maintained B: https://gitlab.freedesktop.org/drm/msm/-/issues T: git https://gitlab.freedesktop.org/drm/msm.git F: Documentation/devicetree/bindings/display/msm/gpu.yaml +F: Documentation/devicetree/bindings/display/msm/qcom,adreno-rgmu.yaml F: Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml F: drivers/gpu/drm/msm/adreno/ F: drivers/gpu/drm/msm/msm_gpu.* @@ -8209,6 +8210,9 @@ S: Maintained F: Documentation/devicetree/bindings/display/sitronix,st7567.yaml F: Documentation/devicetree/bindings/display/sitronix,st7571.yaml F: drivers/gpu/drm/sitronix/st7571-i2c.c +F: drivers/gpu/drm/sitronix/st7571-spi.c +F: drivers/gpu/drm/sitronix/st7571.c +F: drivers/gpu/drm/sitronix/st7571.h DRM DRIVER FOR SITRONIX ST7701 PANELS M: Jagan Teki @@ -8231,6 +8235,13 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: Documentation/devicetree/bindings/display/sitronix,st7735r.yaml F: drivers/gpu/drm/sitronix/st7735r.c +DRM DRIVER FOR SITRONIX ST7920 LCD DISPLAYS +M: Iker Pedrosa +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: Documentation/devicetree/bindings/display/sitronix,st7920.yaml +F: drivers/gpu/drm/sitronix/st7920.c + DRM DRIVER FOR SOLOMON SSD130X OLED DISPLAYS M: Javier Martinez Canillas S: Maintained @@ -8748,6 +8759,7 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: drivers/gpu/drm/drm_draw.c F: drivers/gpu/drm/drm_draw_internal.h F: drivers/gpu/drm/drm_panic*.c +F: drivers/gpu/drm/tests/drm_panic_test.c F: include/drm/drm_panic* DRM PANIC QR CODE @@ -8778,6 +8790,17 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git F: drivers/gpu/drm/ttm/ F: include/drm/ttm/ +DRM BUDDY ALLOCATOR +M: Matthew Auld +M: Arun Pravin +R: Christian Koenig +L: dri-devel@lists.freedesktop.org +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: drivers/gpu/drm/drm_buddy.c +F: drivers/gpu/drm/tests/drm_buddy_test.c +F: include/drm/drm_buddy.h + DRM AUTOMATED TESTING M: Helen Koike M: Vignesh Raman @@ -12461,6 +12484,14 @@ M: Samuel Holland S: Maintained F: drivers/power/supply/ip5xxx_power.c +INNOSILICON HDMI BRIDGE DRIVER +M: Andy Yan +L: dri-devel@lists.freedesktop.org +S: Maintained +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git +F: drivers/gpu/drm/bridge/inno-hdmi.c +F: include/drm/bridge/inno_hdmi.h + INOTIFY M: Jan Kara R: Amir Goldstein @@ -12644,7 +12675,7 @@ F: include/drm/intel/ F: include/uapi/drm/i915_drm.h INTEL DRM XE DRIVER (Lunar Lake and newer) -M: Lucas De Marchi +M: Matthew Brost M: Thomas Hellström M: Rodrigo Vivi L: intel-xe@lists.freedesktop.org diff --git a/Makefile b/Makefile index d3a8482bdbd0d..8d85ccd409d02 100644 --- a/Makefile +++ b/Makefile @@ -1362,7 +1362,12 @@ define filechk_version.h ((c) > 255 ? 255 : (c)))'; \ echo \#define LINUX_VERSION_MAJOR $(VERSION); \ echo \#define LINUX_VERSION_PATCHLEVEL $(PATCHLEVEL); \ - echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL) + echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL); \ + echo '#define DRM_VER $(VERSION)'; \ + echo '#define DRM_PATCH $(PATCHLEVEL)'; \ + echo '#define DRM_SUB $(SUBLEVEL)'; \ + echo \#define DRM_VERSION_CODE LINUX_VERSION_CODE; \ + echo '#define DRM_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))' endef $(version_h): private PATCHLEVEL := $(or $(PATCHLEVEL), 0) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig new file mode 100644 index 0000000000000..565e447c6230b --- /dev/null +++ b/arch/x86/configs/rock-dbg_defconfig @@ -0,0 +1,565 @@ +CONFIG_LOCALVERSION="-kfd" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_CPU_ISOLATION is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_NUMA_BALANCING=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_USERFAULTFD=y +# CONFIG_COMPAT_BRK is not set +CONFIG_PROFILING=y +CONFIG_SMP=y +# CONFIG_RETPOLINE is not set +CONFIG_X86_INTEL_LPSS=y +CONFIG_IOSF_MBI_DEBUG=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_PARAVIRT=y +CONFIG_PARAVIRT_SPINLOCKS=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_GART_IOMMU=y +CONFIG_NR_CPUS=256 +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_I8K=m +CONFIG_MICROCODE_AMD=y +CONFIG_MICROCODE_OLD_INTERFACE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +# CONFIG_X86_5LEVEL is not set +CONFIG_NUMA=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_X86_CHECK_BIOS_CORRUPTION=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 +CONFIG_EFI=y +CONFIG_EFI_STUB=y +CONFIG_EFI_MIXED=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_CRASH_DUMP=y +CONFIG_KEXEC_JUMP=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_LEGACY_VSYSCALL_EMULATE=y +CONFIG_HIBERNATION=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_PM_TRACE_RTC=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_X86_ACPI_CPUFREQ=y +# CONFIG_X86_ACPI_CPUFREQ_CPB is not set +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_IA32_EMULATION=y +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_SIG=y +CONFIG_MODULE_SIG_SHA512=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_BINFMT_MISC=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_MEMORY_FAILURE=y +CONFIG_HWPOISON_INJECT=m +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +CONFIG_CMA_AREAS=7 +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_ZSWAP=y +CONFIG_ZSMALLOC=y +CONFIG_ZONE_DEVICE=y +CONFIG_DEVICE_PRIVATE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM_USER=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +CONFIG_TCP_MD5SIG=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_NETLABEL=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_XFRM=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_NET_EMATCH=y +CONFIG_NET_CLS_ACT=y +CONFIG_NETLINK_DIAG=y +CONFIG_HAMRADIO=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_PCI=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y +CONFIG_PCI_IOV=y +CONFIG_PCI_P2PDMA=y +CONFIG_HOTPLUG_PCI=y +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_DMA_ENGINE=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_EFI_VARS=y +CONFIG_PARPORT=y +CONFIG_PARPORT_PC=y +CONFIG_PARPORT_SERIAL=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_CHR_DEV_SG=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_SATA_SIL24=y +CONFIG_SATA_SX4=y +CONFIG_ATA_PIIX=y +CONFIG_SATA_PROMISE=y +CONFIG_SATA_SIL=y +CONFIG_PATA_AMD=y +CONFIG_PATA_ATIIXP=y +CONFIG_PATA_OLDPIIX=y +CONFIG_PATA_SCH=y +CONFIG_PATA_SERVERWORKS=y +CONFIG_ATA_GENERIC=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_MIRROR=y +CONFIG_DM_ZERO=y +CONFIG_FUSION=y +CONFIG_FUSION_SPI=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_NETCONSOLE=y +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_TUN=y +CONFIG_VETH=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MENU=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_9P_FS=y +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_BLK=y +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_ALX=y +CONFIG_BNX2=y +CONFIG_TIGON3=y +CONFIG_CAVIUM_PTP=y +CONFIG_NET_TULIP=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_IGB=y +CONFIG_IGBVF=y +CONFIG_IXGB=y +CONFIG_IXGBE=y +CONFIG_I40E=y +CONFIG_SKY2=y +CONFIG_FORCEDETH=y +CONFIG_8139CP=y +CONFIG_8139TOO=y +CONFIG_R8169=y +CONFIG_WIZNET_W5100=y +CONFIG_WIZNET_W5300=y +CONFIG_FDDI=y +CONFIG_AMD_PHY=y +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_RTL8152=m +CONFIG_USB_USBNET=m +# CONFIG_USB_ARMLINUX is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_INPUT_SPARSEKMAP=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_MID is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_I801=y +CONFIG_I2C_PIIX4=m +CONFIG_SENSORS_K10TEMP=m +CONFIG_WATCHDOG=y +CONFIG_RC_CORE=y +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +CONFIG_AGP=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +CONFIG_DRM=m +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_P2P=y +CONFIG_DRM_AST=m +CONFIG_FB=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_PLANTRONICS=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_DMADEVICES=y +CONFIG_DMABUF_MOVE_NOTIFY=y +# CONFIG_X86_PLATFORM_DEVICES is not set +CONFIG_AMD_IOMMU=y +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set +CONFIG_DAX=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_XFS_WARN=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_QFMT_V2=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=y +CONFIG_FSCACHE=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_PROC_KCORE=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_CONFIGFS_FS=y +# CONFIG_EFIVAR_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_FSCACHE=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_SECURITY=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_DES=y +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_KGDB=y +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y +CONFIG_DEBUG_RODATA_TEST=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_SCHEDSTATS=y +CONFIG_PROVE_LOCKING=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_MMIOTRACE=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_HIST_TRIGGERS=y +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_X86_VERBOSE_BOOTUP is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile index 6344aaf523fac..3fa0e74fd8f5d 100644 --- a/drivers/accel/amdxdna/Makefile +++ b/drivers/accel/amdxdna/Makefile @@ -18,7 +18,6 @@ amdxdna-y := \ amdxdna_sysfs.o \ amdxdna_ubuf.o \ npu1_regs.o \ - npu2_regs.o \ npu4_regs.o \ npu5_regs.o \ npu6_regs.o diff --git a/drivers/accel/amdxdna/aie2_ctx.c b/drivers/accel/amdxdna/aie2_ctx.c index 42d876a427c59..5511ab2ef242c 100644 --- a/drivers/accel/amdxdna/aie2_ctx.c +++ b/drivers/accel/amdxdna/aie2_ctx.c @@ -468,6 +468,12 @@ static int aie2_alloc_resource(struct amdxdna_hwctx *hwctx) struct alloc_requests *xrs_req; int ret; + if (AIE2_FEATURE_ON(xdna->dev_handle, AIE2_TEMPORAL_ONLY)) { + hwctx->num_unused_col = xdna->dev_handle->total_col - hwctx->num_col; + hwctx->num_col = xdna->dev_handle->total_col; + return aie2_create_context(xdna->dev_handle, hwctx); + } + xrs_req = kzalloc(sizeof(*xrs_req), GFP_KERNEL); if (!xrs_req) return -ENOMEM; @@ -499,9 +505,15 @@ static void aie2_release_resource(struct amdxdna_hwctx *hwctx) struct amdxdna_dev *xdna = hwctx->client->xdna; int ret; - ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx); - if (ret) - XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret); + if (AIE2_FEATURE_ON(xdna->dev_handle, AIE2_TEMPORAL_ONLY)) { + ret = aie2_destroy_context(xdna->dev_handle, hwctx); + if (ret) + XDNA_ERR(xdna, "Destroy temporal only context failed, ret %d", ret); + } else { + ret = xrs_release_resource(xdna->xrs_hdl, (uintptr_t)hwctx); + if (ret) + XDNA_ERR(xdna, "Release AIE resource failed, ret %d", ret); + } } static int aie2_ctx_syncobj_create(struct amdxdna_hwctx *hwctx) diff --git a/drivers/accel/amdxdna/aie2_error.c b/drivers/accel/amdxdna/aie2_error.c index d452008ec4f49..5e82df2b7cf61 100644 --- a/drivers/accel/amdxdna/aie2_error.c +++ b/drivers/accel/amdxdna/aie2_error.c @@ -338,8 +338,7 @@ void aie2_error_async_events_free(struct amdxdna_dev_hdl *ndev) destroy_workqueue(events->wq); mutex_lock(&xdna->dev_lock); - dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf, - events->addr, DMA_FROM_DEVICE); + aie2_free_msg_buffer(ndev, events->size, events->buf, events->addr); kfree(events); } @@ -355,8 +354,8 @@ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev) if (!events) return -ENOMEM; - events->buf = dma_alloc_noncoherent(xdna->ddev.dev, total_size, &events->addr, - DMA_FROM_DEVICE, GFP_KERNEL); + events->buf = aie2_alloc_msg_buffer(ndev, &total_size, &events->addr); + if (!events->buf) { ret = -ENOMEM; goto free_events; @@ -396,8 +395,7 @@ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev) free_wq: destroy_workqueue(events->wq); free_buf: - dma_free_noncoherent(xdna->ddev.dev, events->size, events->buf, - events->addr, DMA_FROM_DEVICE); + aie2_free_msg_buffer(ndev, events->size, events->buf, events->addr); free_events: kfree(events); return ret; diff --git a/drivers/accel/amdxdna/aie2_message.c b/drivers/accel/amdxdna/aie2_message.c index d493bb1c33606..99215328505ea 100644 --- a/drivers/accel/amdxdna/aie2_message.c +++ b/drivers/accel/amdxdna/aie2_message.c @@ -39,7 +39,6 @@ static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev, if (!ndev->mgmt_chann) return -ENODEV; - drm_WARN_ON(&xdna->ddev, xdna->rpm_on && !mutex_is_locked(&xdna->dev_lock)); ret = xdna_send_msg_wait(xdna, ndev->mgmt_chann, msg); if (ret == -ETIME) { xdna_mailbox_stop_channel(ndev->mgmt_chann); @@ -56,11 +55,34 @@ static int aie2_send_mgmt_msg_wait(struct amdxdna_dev_hdl *ndev, return ret; } +void *aie2_alloc_msg_buffer(struct amdxdna_dev_hdl *ndev, u32 *size, + dma_addr_t *dma_addr) +{ + struct amdxdna_dev *xdna = ndev->xdna; + int order; + + *size = max(*size, SZ_8K); + order = get_order(*size); + if (order > MAX_PAGE_ORDER) + return NULL; + *size = PAGE_SIZE << order; + + return dma_alloc_noncoherent(xdna->ddev.dev, *size, dma_addr, + DMA_FROM_DEVICE, GFP_KERNEL); +} + int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev) { DECLARE_AIE2_MSG(suspend, MSG_OP_SUSPEND); + int ret; - return aie2_send_mgmt_msg_wait(ndev, &msg); + ret = aie2_send_mgmt_msg_wait(ndev, &msg); + if (ret) { + XDNA_ERR(ndev->xdna, "Failed to suspend fw, ret %d", ret); + return ret; + } + + return aie2_psp_waitmode_poll(ndev->psp_hdl); } int aie2_resume_fw(struct amdxdna_dev_hdl *ndev) @@ -186,6 +208,40 @@ int aie2_query_firmware_version(struct amdxdna_dev_hdl *ndev, return 0; } +static int aie2_destroy_context_req(struct amdxdna_dev_hdl *ndev, u32 id) +{ + DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); + struct amdxdna_dev *xdna = ndev->xdna; + int ret; + + req.context_id = id; + ret = aie2_send_mgmt_msg_wait(ndev, &msg); + if (ret) + XDNA_WARN(xdna, "Destroy context failed, ret %d", ret); + + return ret; +} + +static u32 aie2_get_context_priority(struct amdxdna_dev_hdl *ndev, + struct amdxdna_hwctx *hwctx) +{ + if (!AIE2_FEATURE_ON(ndev, AIE2_PREEMPT)) + return PRIORITY_HIGH; + + switch (hwctx->qos.priority) { + case AMDXDNA_QOS_REALTIME_PRIORITY: + return PRIORITY_REALTIME; + case AMDXDNA_QOS_HIGH_PRIORITY: + return PRIORITY_HIGH; + case AMDXDNA_QOS_NORMAL_PRIORITY: + return PRIORITY_NORMAL; + case AMDXDNA_QOS_LOW_PRIORITY: + return PRIORITY_LOW; + default: + return PRIORITY_HIGH; + } +} + int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { DECLARE_AIE2_MSG(create_ctx, MSG_OP_CREATE_CONTEXT); @@ -199,22 +255,24 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct req.aie_type = 1; req.start_col = hwctx->start_col; req.num_col = hwctx->num_col; + req.num_unused_col = hwctx->num_unused_col; req.num_cq_pairs_requested = 1; req.pasid = hwctx->client->pasid; - req.context_priority = 2; + req.context_priority = aie2_get_context_priority(ndev, hwctx); ret = aie2_send_mgmt_msg_wait(ndev, &msg); if (ret) return ret; hwctx->fw_ctx_id = resp.context_id; - WARN_ONCE(hwctx->fw_ctx_id == -1, "Unexpected context id"); + if (WARN_ON_ONCE(hwctx->fw_ctx_id == -1)) + return -EINVAL; if (ndev->force_preempt_enabled) { ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_FORCE_PREEMPT, &hwctx->fw_ctx_id); if (ret) { XDNA_ERR(xdna, "failed to enable force preempt %d", ret); - return ret; + goto del_ctx_req; } } @@ -231,51 +289,39 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct ret = pci_irq_vector(to_pci_dev(xdna->ddev.dev), resp.msix_id); if (ret == -EINVAL) { - XDNA_ERR(xdna, "not able to create channel"); - goto out_destroy_context; + XDNA_ERR(xdna, "Alloc IRQ failed %d", ret); + goto del_ctx_req; } intr_reg = i2x.mb_head_ptr_reg + 4; hwctx->priv->mbox_chann = xdna_mailbox_create_channel(ndev->mbox, &x2i, &i2x, intr_reg, ret); if (!hwctx->priv->mbox_chann) { - XDNA_ERR(xdna, "not able to create channel"); + XDNA_ERR(xdna, "Not able to create channel"); ret = -EINVAL; - goto out_destroy_context; + goto del_ctx_req; } ndev->hwctx_num++; - XDNA_DBG(xdna, "%s mailbox channel irq: %d, msix_id: %d", - hwctx->name, ret, resp.msix_id); - XDNA_DBG(xdna, "%s created fw ctx %d pasid %d", hwctx->name, - hwctx->fw_ctx_id, hwctx->client->pasid); + XDNA_DBG(xdna, "Mailbox channel irq: %d, msix_id: %d", ret, resp.msix_id); + XDNA_DBG(xdna, "Created fw ctx %d pasid %d", hwctx->fw_ctx_id, hwctx->client->pasid); return 0; -out_destroy_context: - aie2_destroy_context(ndev, hwctx); +del_ctx_req: + aie2_destroy_context_req(ndev, hwctx->fw_ctx_id); return ret; } int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx) { - DECLARE_AIE2_MSG(destroy_ctx, MSG_OP_DESTROY_CONTEXT); struct amdxdna_dev *xdna = ndev->xdna; int ret; - if (hwctx->fw_ctx_id == -1) - return 0; - xdna_mailbox_stop_channel(hwctx->priv->mbox_chann); - - req.context_id = hwctx->fw_ctx_id; - ret = aie2_send_mgmt_msg_wait(ndev, &msg); - if (ret) - XDNA_WARN(xdna, "%s destroy context failed, ret %d", hwctx->name, ret); - + ret = aie2_destroy_context_req(ndev, hwctx->fw_ctx_id); xdna_mailbox_destroy_channel(hwctx->priv->mbox_chann); - XDNA_DBG(xdna, "%s destroyed fw ctx %d", hwctx->name, - hwctx->fw_ctx_id); + XDNA_DBG(xdna, "Destroyed fw ctx %d", hwctx->fw_ctx_id); hwctx->priv->mbox_chann = NULL; hwctx->fw_ctx_id = -1; ndev->hwctx_num--; @@ -316,14 +362,13 @@ int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, { DECLARE_AIE2_MSG(aie_column_info, MSG_OP_QUERY_COL_STATUS); struct amdxdna_dev *xdna = ndev->xdna; + u32 buf_sz = size, aie_bitmap = 0; struct amdxdna_client *client; dma_addr_t dma_addr; - u32 aie_bitmap = 0; u8 *buff_addr; int ret; - buff_addr = dma_alloc_noncoherent(xdna->ddev.dev, size, &dma_addr, - DMA_FROM_DEVICE, GFP_KERNEL); + buff_addr = aie2_alloc_msg_buffer(ndev, &buf_sz, &dma_addr); if (!buff_addr) return -ENOMEM; @@ -333,7 +378,7 @@ int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, *cols_filled = 0; req.dump_buff_addr = dma_addr; - req.dump_buff_size = size; + req.dump_buff_size = buf_sz; req.num_cols = hweight32(aie_bitmap); req.aie_bitmap = aie_bitmap; @@ -361,7 +406,7 @@ int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, *cols_filled = aie_bitmap; fail: - dma_free_noncoherent(xdna->ddev.dev, size, buff_addr, dma_addr, DMA_FROM_DEVICE); + aie2_free_msg_buffer(ndev, buf_sz, buff_addr, dma_addr); return ret; } @@ -372,19 +417,19 @@ int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, DECLARE_AIE2_MSG(get_telemetry, MSG_OP_GET_TELEMETRY); struct amdxdna_dev *xdna = ndev->xdna; dma_addr_t dma_addr; + u32 buf_sz = size; u8 *addr; int ret; if (header->type >= MAX_TELEMETRY_TYPE) return -EINVAL; - addr = dma_alloc_noncoherent(xdna->ddev.dev, size, &dma_addr, - DMA_FROM_DEVICE, GFP_KERNEL); + addr = aie2_alloc_msg_buffer(ndev, &buf_sz, &dma_addr); if (!addr) return -ENOMEM; req.buf_addr = dma_addr; - req.buf_size = size; + req.buf_size = buf_sz; req.type = header->type; drm_clflush_virt_range(addr, size); /* device can access */ @@ -410,7 +455,7 @@ int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev, header->minor = resp.minor; free_buf: - dma_free_noncoherent(xdna->ddev.dev, size, addr, dma_addr, DMA_FROM_DEVICE); + aie2_free_msg_buffer(ndev, buf_sz, addr, dma_addr); return ret; } @@ -646,6 +691,7 @@ aie2_cmdlist_fill_npu_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *siz u32 cmd_len; void *cmd; + memset(npu_slot, 0, sizeof(*npu_slot)); cmd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); if (*size < sizeof(*npu_slot) + cmd_len) return -EINVAL; @@ -654,7 +700,6 @@ aie2_cmdlist_fill_npu_cf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *siz if (npu_slot->cu_idx == INVALID_CU_IDX) return -EINVAL; - memset(npu_slot, 0, sizeof(*npu_slot)); npu_slot->type = EXEC_NPU_TYPE_NON_ELF; npu_slot->arg_cnt = cmd_len / sizeof(u32); memcpy(npu_slot->args, cmd, cmd_len); @@ -671,6 +716,7 @@ aie2_cmdlist_fill_npu_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *si u32 cmd_len; u32 arg_sz; + memset(npu_slot, 0, sizeof(*npu_slot)); sn = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); arg_sz = cmd_len - sizeof(*sn); if (cmd_len < sizeof(*sn) || arg_sz > MAX_NPU_ARGS_SIZE) @@ -683,7 +729,6 @@ aie2_cmdlist_fill_npu_dpu(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *si if (npu_slot->cu_idx == INVALID_CU_IDX) return -EINVAL; - memset(npu_slot, 0, sizeof(*npu_slot)); npu_slot->type = EXEC_NPU_TYPE_PARTIAL_ELF; npu_slot->inst_buf_addr = sn->buffer; npu_slot->inst_size = sn->buffer_size; @@ -703,6 +748,7 @@ aie2_cmdlist_fill_npu_preempt(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t u32 cmd_len; u32 arg_sz; + memset(npu_slot, 0, sizeof(*npu_slot)); pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); arg_sz = cmd_len - sizeof(*pd); if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE) @@ -715,7 +761,6 @@ aie2_cmdlist_fill_npu_preempt(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t if (npu_slot->cu_idx == INVALID_CU_IDX) return -EINVAL; - memset(npu_slot, 0, sizeof(*npu_slot)); npu_slot->type = EXEC_NPU_TYPE_PREEMPT; npu_slot->inst_buf_addr = pd->inst_buf; npu_slot->save_buf_addr = pd->save_buf; @@ -739,6 +784,7 @@ aie2_cmdlist_fill_npu_elf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *si u32 cmd_len; u32 arg_sz; + memset(npu_slot, 0, sizeof(*npu_slot)); pd = amdxdna_cmd_get_payload(cmd_bo, &cmd_len); arg_sz = cmd_len - sizeof(*pd); if (cmd_len < sizeof(*pd) || arg_sz > MAX_NPU_ARGS_SIZE) @@ -747,7 +793,6 @@ aie2_cmdlist_fill_npu_elf(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *si if (*size < sizeof(*npu_slot) + arg_sz) return -EINVAL; - memset(npu_slot, 0, sizeof(*npu_slot)); npu_slot->type = EXEC_NPU_TYPE_ELF; npu_slot->inst_buf_addr = pd->inst_buf; npu_slot->save_buf_addr = pd->save_buf; diff --git a/drivers/accel/amdxdna/aie2_msg_priv.h b/drivers/accel/amdxdna/aie2_msg_priv.h index 1c957a6298d39..728ef56f7f0ad 100644 --- a/drivers/accel/amdxdna/aie2_msg_priv.h +++ b/drivers/accel/amdxdna/aie2_msg_priv.h @@ -108,11 +108,17 @@ struct cq_pair { struct cq_info i2x_q; }; +#define PRIORITY_REALTIME 1 +#define PRIORITY_HIGH 2 +#define PRIORITY_NORMAL 3 +#define PRIORITY_LOW 4 + struct create_ctx_req { __u32 aie_type; __u8 start_col; __u8 num_col; - __u16 reserved; + __u8 num_unused_col; + __u8 reserved; __u8 num_cq_pairs_requested; __u8 reserved1; __u16 pasid; diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_pci.c index 8141d8e516360..f70ccf0f3c019 100644 --- a/drivers/accel/amdxdna/aie2_pci.c +++ b/drivers/accel/amdxdna/aie2_pci.c @@ -57,41 +57,23 @@ struct mgmt_mbox_chann_info { static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 fw_minor) { const struct aie2_fw_feature_tbl *feature; - struct amdxdna_dev *xdna = ndev->xdna; - - /* - * The driver supported mailbox behavior is defined by - * ndev->priv->protocol_major and protocol_minor. - * - * When protocol_major and fw_major are different, it means driver - * and firmware are incompatible. - */ - if (ndev->priv->protocol_major != fw_major) { - XDNA_ERR(xdna, "Incompatible firmware protocol major %d minor %d", - fw_major, fw_minor); - return -EINVAL; - } + bool found = false; - /* - * When protocol_minor is greater then fw_minor, that means driver - * relies on operation the installed firmware does not support. - */ - if (ndev->priv->protocol_minor > fw_minor) { - XDNA_ERR(xdna, "Firmware minor version smaller than supported"); - return -EINVAL; - } - - for (feature = ndev->priv->fw_feature_tbl; feature && feature->min_minor; - feature++) { + for (feature = ndev->priv->fw_feature_tbl; feature->major; feature++) { + if (feature->major != fw_major) + continue; if (fw_minor < feature->min_minor) continue; if (feature->max_minor > 0 && fw_minor > feature->max_minor) continue; - set_bit(feature->feature, &ndev->feature_mask); + ndev->feature_mask |= feature->features; + + /* firmware version matches one of the driver support entry */ + found = true; } - return 0; + return found ? 0 : -EOPNOTSUPP; } static void aie2_dump_chann_info_debug(struct amdxdna_dev_hdl *ndev) @@ -322,7 +304,7 @@ static int aie2_xrs_set_dft_dpm_level(struct drm_device *ddev, u32 dpm_level) if (ndev->pw_mode != POWER_MODE_DEFAULT || ndev->dpm_level == dpm_level) return 0; - return ndev->priv->hw_ops.set_dpm(ndev, dpm_level); + return aie2_pm_set_dpm(ndev, dpm_level); } static struct xrs_action_ops aie2_xrs_actions = { diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_pci.h index a5f9c42155d17..b20a3661078cc 100644 --- a/drivers/accel/amdxdna/aie2_pci.h +++ b/drivers/accel/amdxdna/aie2_pci.h @@ -70,6 +70,7 @@ enum psp_reg_idx { PSP_INTR_REG = PSP_NUM_IN_REGS, PSP_STATUS_REG, PSP_RESP_REG, + PSP_PWAITMODE_REG, PSP_MAX_REGS /* Keep this at the end */ }; @@ -231,11 +232,13 @@ struct aie2_hw_ops { enum aie2_fw_feature { AIE2_NPU_COMMAND, AIE2_PREEMPT, + AIE2_TEMPORAL_ONLY, AIE2_FEATURE_MAX }; struct aie2_fw_feature_tbl { - enum aie2_fw_feature feature; + u64 features; + u32 major; u32 max_minor; u32 min_minor; }; @@ -244,8 +247,6 @@ struct aie2_fw_feature_tbl { struct amdxdna_dev_priv { const char *fw_path; - u64 protocol_major; - u64 protocol_minor; const struct rt_config *rt_config; const struct dpm_clk_freq *dpm_clk_tbl; const struct aie2_fw_feature_tbl *fw_feature_tbl; @@ -285,11 +286,13 @@ int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); /* aie2_pm.c */ int aie2_pm_init(struct amdxdna_dev_hdl *ndev); int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target); +int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); /* aie2_psp.c */ struct psp_device *aie2m_psp_create(struct drm_device *ddev, struct psp_config *conf); int aie2_psp_start(struct psp_device *psp); void aie2_psp_stop(struct psp_device *psp); +int aie2_psp_waitmode_poll(struct psp_device *psp); /* aie2_error.c */ int aie2_error_async_events_alloc(struct amdxdna_dev_hdl *ndev); @@ -332,6 +335,11 @@ int aie2_sync_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, int (*notify_cb)(void *, void __iomem *, size_t)); int aie2_config_debug_bo(struct amdxdna_hwctx *hwctx, struct amdxdna_sched_job *job, int (*notify_cb)(void *, void __iomem *, size_t)); +void *aie2_alloc_msg_buffer(struct amdxdna_dev_hdl *ndev, u32 *size, + dma_addr_t *dma_addr); +#define aie2_free_msg_buffer(ndev, size, buff_addr, dma_addr) \ + dma_free_noncoherent((ndev)->xdna->ddev.dev, size, buff_addr, \ + dma_addr, DMA_FROM_DEVICE) /* aie2_hwctx.c */ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx); diff --git a/drivers/accel/amdxdna/aie2_pm.c b/drivers/accel/amdxdna/aie2_pm.c index 426c38fce8482..afcd6d4683e56 100644 --- a/drivers/accel/amdxdna/aie2_pm.c +++ b/drivers/accel/amdxdna/aie2_pm.c @@ -10,6 +10,7 @@ #include "aie2_pci.h" #include "amdxdna_pci_drv.h" +#include "amdxdna_pm.h" #define AIE2_CLK_GATING_ENABLE 1 #define AIE2_CLK_GATING_DISABLE 0 @@ -26,6 +27,20 @@ static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val) return 0; } +int aie2_pm_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) +{ + int ret; + + ret = amdxdna_pm_resume_get(ndev->xdna); + if (ret) + return ret; + + ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level); + amdxdna_pm_suspend_put(ndev->xdna); + + return ret; +} + int aie2_pm_init(struct amdxdna_dev_hdl *ndev) { int ret; @@ -94,7 +109,7 @@ int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type return -EOPNOTSUPP; } - ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level); + ret = aie2_pm_set_dpm(ndev, dpm_level); if (ret) return ret; diff --git a/drivers/accel/amdxdna/aie2_psp.c b/drivers/accel/amdxdna/aie2_psp.c index f28a060a88109..3a7130577e3e2 100644 --- a/drivers/accel/amdxdna/aie2_psp.c +++ b/drivers/accel/amdxdna/aie2_psp.c @@ -76,6 +76,21 @@ static int psp_exec(struct psp_device *psp, u32 *reg_vals) return 0; } +int aie2_psp_waitmode_poll(struct psp_device *psp) +{ + struct amdxdna_dev *xdna = to_xdna_dev(psp->ddev); + u32 mode_reg; + int ret; + + ret = readx_poll_timeout(readl, PSP_REG(psp, PSP_PWAITMODE_REG), mode_reg, + (mode_reg & 0x1) == 1, + PSP_POLL_INTERVAL, PSP_POLL_TIMEOUT); + if (ret) + XDNA_ERR(xdna, "fw waitmode reg error, ret %d", ret); + + return ret; +} + void aie2_psp_stop(struct psp_device *psp) { u32 reg_vals[PSP_NUM_IN_REGS] = { PSP_RELEASE_TMR, }; diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_smu.c index bd94ee96c2bc0..2d195e41f83dd 100644 --- a/drivers/accel/amdxdna/aie2_smu.c +++ b/drivers/accel/amdxdna/aie2_smu.c @@ -11,7 +11,6 @@ #include "aie2_pci.h" #include "amdxdna_pci_drv.h" -#include "amdxdna_pm.h" #define SMU_RESULT_OK 1 @@ -67,16 +66,12 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) u32 freq; int ret; - ret = amdxdna_pm_resume_get(ndev->xdna); - if (ret) - return ret; - ret = aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ, ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq); if (ret) { XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n", ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret); - goto suspend_put; + return ret; } ndev->npuclk_freq = freq; @@ -85,10 +80,9 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) if (ret) { XDNA_ERR(ndev->xdna, "Set h clock to %d failed, ret %d\n", ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret); - goto suspend_put; + return ret; } - amdxdna_pm_suspend_put(ndev->xdna); ndev->hclk_freq = freq; ndev->dpm_level = dpm_level; ndev->max_tops = 2 * ndev->total_col; @@ -98,35 +92,26 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) ndev->npuclk_freq, ndev->hclk_freq); return 0; - -suspend_put: - amdxdna_pm_suspend_put(ndev->xdna); - return ret; } int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) { int ret; - ret = amdxdna_pm_resume_get(ndev->xdna); - if (ret) - return ret; - ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL); if (ret) { XDNA_ERR(ndev->xdna, "Set hard dpm level %d failed, ret %d ", dpm_level, ret); - goto suspend_put; + return ret; } ret = aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL); if (ret) { XDNA_ERR(ndev->xdna, "Set soft dpm level %d failed, ret %d", dpm_level, ret); - goto suspend_put; + return ret; } - amdxdna_pm_suspend_put(ndev->xdna); ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk; ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk; ndev->dpm_level = dpm_level; @@ -137,10 +122,6 @@ int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) ndev->npuclk_freq, ndev->hclk_freq); return 0; - -suspend_put: - amdxdna_pm_suspend_put(ndev->xdna); - return ret; } int aie2_smu_init(struct amdxdna_dev_hdl *ndev) diff --git a/drivers/accel/amdxdna/amdxdna_ctx.h b/drivers/accel/amdxdna/amdxdna_ctx.h index b6151244d64fe..b29449a92f607 100644 --- a/drivers/accel/amdxdna/amdxdna_ctx.h +++ b/drivers/accel/amdxdna/amdxdna_ctx.h @@ -98,6 +98,7 @@ struct amdxdna_hwctx { u32 *col_list; u32 start_col; u32 num_col; + u32 num_unused_col; #define HWCTX_STAT_INIT 0 #define HWCTX_STAT_READY 1 #define HWCTX_STAT_STOP 2 diff --git a/drivers/accel/amdxdna/amdxdna_mailbox.c b/drivers/accel/amdxdna/amdxdna_mailbox.c index 858df97cd3fbd..469242ed82246 100644 --- a/drivers/accel/amdxdna/amdxdna_mailbox.c +++ b/drivers/accel/amdxdna/amdxdna_mailbox.c @@ -112,22 +112,6 @@ static u32 mailbox_reg_read(struct mailbox_channel *mb_chann, u32 mbox_reg) return readl(ringbuf_addr); } -static int mailbox_reg_read_non_zero(struct mailbox_channel *mb_chann, u32 mbox_reg, u32 *val) -{ - struct xdna_mailbox_res *mb_res = &mb_chann->mb->res; - void __iomem *ringbuf_addr = mb_res->mbox_base + mbox_reg; - int ret, value; - - /* Poll till value is not zero */ - ret = readx_poll_timeout(readl, ringbuf_addr, value, - value, 1 /* us */, 100); - if (ret < 0) - return ret; - - *val = value; - return 0; -} - static inline void mailbox_set_headptr(struct mailbox_channel *mb_chann, u32 headptr_val) { @@ -207,26 +191,34 @@ mailbox_send_msg(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg) u32 head, tail; u32 start_addr; u32 tmp_tail; + int ret; head = mailbox_get_headptr(mb_chann, CHAN_RES_X2I); tail = mb_chann->x2i_tail; - ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_X2I); + ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_X2I) - sizeof(u32); start_addr = mb_chann->res[CHAN_RES_X2I].rb_start_addr; tmp_tail = tail + mb_msg->pkg_size; - if (tail < head && tmp_tail >= head) - goto no_space; - if (tail >= head && (tmp_tail > ringbuf_size - sizeof(u32) && - mb_msg->pkg_size >= head)) - goto no_space; - - if (tail >= head && tmp_tail > ringbuf_size - sizeof(u32)) { +check_again: + if (tail >= head && tmp_tail > ringbuf_size) { write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail; writel(TOMBSTONE, write_addr); /* tombstone is set. Write from the start of the ringbuf */ tail = 0; + tmp_tail = tail + mb_msg->pkg_size; + } + + if (tail < head && tmp_tail >= head) { + ret = read_poll_timeout(mailbox_get_headptr, head, + tmp_tail < head || tail >= head, + 1, 100, false, mb_chann, CHAN_RES_X2I); + if (ret) + return ret; + + if (tail >= head) + goto check_again; } write_addr = mb_chann->mb->res.ringbuf_base + start_addr + tail; @@ -238,9 +230,6 @@ mailbox_send_msg(struct mailbox_channel *mb_chann, struct mailbox_msg *mb_msg) mb_msg->pkg.header.id); return 0; - -no_space: - return -ENOSPC; } static int @@ -286,8 +275,7 @@ static int mailbox_get_msg(struct mailbox_channel *mb_chann) u32 start_addr; int ret; - if (mailbox_reg_read_non_zero(mb_chann, mb_chann->res[CHAN_RES_I2X].mb_tail_ptr_reg, &tail)) - return -EINVAL; + tail = mailbox_get_tailptr(mb_chann, CHAN_RES_I2X); head = mb_chann->i2x_head; ringbuf_size = mailbox_get_ringbuf_size(mb_chann, CHAN_RES_I2X); start_addr = mb_chann->res[CHAN_RES_I2X].rb_start_addr; diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c index 1973ab67721be..45f5c12fc67fb 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c @@ -51,7 +51,6 @@ MODULE_DEVICE_TABLE(pci, pci_ids); static const struct amdxdna_device_id amdxdna_ids[] = { { 0x1502, 0x0, &dev_npu1_info }, - { 0x17f0, 0x0, &dev_npu2_info }, { 0x17f0, 0x10, &dev_npu4_info }, { 0x17f0, 0x11, &dev_npu5_info }, { 0x17f0, 0x20, &dev_npu6_info }, @@ -105,43 +104,38 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp) return ret; } -static void amdxdna_drm_close(struct drm_device *ddev, struct drm_file *filp) +static void amdxdna_client_cleanup(struct amdxdna_client *client) { - struct amdxdna_client *client = filp->driver_priv; - struct amdxdna_dev *xdna = to_xdna_dev(ddev); - - XDNA_DBG(xdna, "closing pid %d", client->pid); - + list_del(&client->node); + amdxdna_hwctx_remove_all(client); xa_destroy(&client->hwctx_xa); cleanup_srcu_struct(&client->hwctx_srcu); mutex_destroy(&client->mm_lock); + if (client->dev_heap) drm_gem_object_put(to_gobj(client->dev_heap)); iommu_sva_unbind_device(client->sva); - XDNA_DBG(xdna, "pid %d closed", client->pid); kfree(client); } -static int amdxdna_flush(struct file *f, fl_owner_t id) +static void amdxdna_drm_close(struct drm_device *ddev, struct drm_file *filp) { - struct drm_file *filp = f->private_data; struct amdxdna_client *client = filp->driver_priv; - struct amdxdna_dev *xdna = client->xdna; + struct amdxdna_dev *xdna = to_xdna_dev(ddev); int idx; - XDNA_DBG(xdna, "PID %d flushing...", client->pid); + XDNA_DBG(xdna, "closing pid %d", client->pid); + if (!drm_dev_enter(&xdna->ddev, &idx)) - return 0; + return; mutex_lock(&xdna->dev_lock); - list_del_init(&client->node); - amdxdna_hwctx_remove_all(client); + amdxdna_client_cleanup(client); mutex_unlock(&xdna->dev_lock); drm_dev_exit(idx); - return 0; } static int amdxdna_drm_get_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) @@ -217,7 +211,6 @@ static const struct file_operations amdxdna_fops = { .owner = THIS_MODULE, .open = accel_open, .release = drm_release, - .flush = amdxdna_flush, .unlocked_ioctl = drm_ioctl, .compat_ioctl = drm_compat_ioctl, .poll = drm_poll, @@ -282,7 +275,7 @@ static int amdxdna_probe(struct pci_dev *pdev, const struct pci_device_id *id) fs_reclaim_release(GFP_KERNEL); } - xdna->notifier_wq = alloc_ordered_workqueue("notifier_wq", 0); + xdna->notifier_wq = alloc_ordered_workqueue("notifier_wq", WQ_MEM_RECLAIM); if (!xdna->notifier_wq) return -ENOMEM; @@ -333,8 +326,7 @@ static void amdxdna_remove(struct pci_dev *pdev) client = list_first_entry_or_null(&xdna->client_list, struct amdxdna_client, node); while (client) { - list_del_init(&client->node); - amdxdna_hwctx_remove_all(client); + amdxdna_client_cleanup(client); client = list_first_entry_or_null(&xdna->client_list, struct amdxdna_client, node); diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h index c99477f5e454f..6580cb5ec7e2f 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h @@ -101,7 +101,6 @@ struct amdxdna_dev { struct amdxdna_fw_ver fw_ver; struct rw_semaphore notifier_lock; /* for mmu notifier*/ struct workqueue_struct *notifier_wq; - bool rpm_on; }; /* @@ -138,7 +137,6 @@ struct amdxdna_client { /* Add device info below */ extern const struct amdxdna_dev_info dev_npu1_info; -extern const struct amdxdna_dev_info dev_npu2_info; extern const struct amdxdna_dev_info dev_npu4_info; extern const struct amdxdna_dev_info dev_npu5_info; extern const struct amdxdna_dev_info dev_npu6_info; diff --git a/drivers/accel/amdxdna/amdxdna_pm.c b/drivers/accel/amdxdna/amdxdna_pm.c index fa38e65d617c4..d024d480521c4 100644 --- a/drivers/accel/amdxdna/amdxdna_pm.c +++ b/drivers/accel/amdxdna/amdxdna_pm.c @@ -15,14 +15,9 @@ int amdxdna_pm_suspend(struct device *dev) { struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev)); int ret = -EOPNOTSUPP; - bool rpm; - if (xdna->dev_info->ops->suspend) { - rpm = xdna->rpm_on; - xdna->rpm_on = false; + if (xdna->dev_info->ops->suspend) ret = xdna->dev_info->ops->suspend(xdna); - xdna->rpm_on = rpm; - } XDNA_DBG(xdna, "Suspend done ret %d", ret); return ret; @@ -32,14 +27,9 @@ int amdxdna_pm_resume(struct device *dev) { struct amdxdna_dev *xdna = to_xdna_dev(dev_get_drvdata(dev)); int ret = -EOPNOTSUPP; - bool rpm; - if (xdna->dev_info->ops->resume) { - rpm = xdna->rpm_on; - xdna->rpm_on = false; + if (xdna->dev_info->ops->resume) ret = xdna->dev_info->ops->resume(xdna); - xdna->rpm_on = rpm; - } XDNA_DBG(xdna, "Resume done ret %d", ret); return ret; @@ -50,9 +40,6 @@ int amdxdna_pm_resume_get(struct amdxdna_dev *xdna) struct device *dev = xdna->ddev.dev; int ret; - if (!xdna->rpm_on) - return 0; - ret = pm_runtime_resume_and_get(dev); if (ret) { XDNA_ERR(xdna, "Resume failed: %d", ret); @@ -66,9 +53,6 @@ void amdxdna_pm_suspend_put(struct amdxdna_dev *xdna) { struct device *dev = xdna->ddev.dev; - if (!xdna->rpm_on) - return; - pm_runtime_put_autosuspend(dev); } @@ -81,14 +65,12 @@ void amdxdna_pm_init(struct amdxdna_dev *xdna) pm_runtime_use_autosuspend(dev); pm_runtime_allow(dev); pm_runtime_put_autosuspend(dev); - xdna->rpm_on = true; } void amdxdna_pm_fini(struct amdxdna_dev *xdna) { struct device *dev = xdna->ddev.dev; - xdna->rpm_on = false; pm_runtime_get_noresume(dev); pm_runtime_forbid(dev); } diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1_regs.c index ec407f3b48fc7..6f36a27b5a02d 100644 --- a/drivers/accel/amdxdna/npu1_regs.c +++ b/drivers/accel/amdxdna/npu1_regs.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include "aie2_pci.h" @@ -13,6 +14,7 @@ #include "amdxdna_pci_drv.h" /* Address definition from NPU1 docs */ +#define MPNPU_PWAITMODE 0x3010034 #define MPNPU_PUB_SEC_INTR 0x3010090 #define MPNPU_PUB_PWRMGMT_INTR 0x3010094 #define MPNPU_PUB_SCRATCH2 0x30100A0 @@ -64,14 +66,13 @@ const struct dpm_clk_freq npu1_dpm_clk_table[] = { }; static const struct aie2_fw_feature_tbl npu1_fw_feature_table[] = { - { .feature = AIE2_NPU_COMMAND, .min_minor = 8 }, + { .major = 5, .min_minor = 7 }, + { .features = BIT_U64(AIE2_NPU_COMMAND), .min_minor = 8 }, { 0 } }; static const struct amdxdna_dev_priv npu1_dev_priv = { .fw_path = "amdnpu/1502_00/npu.sbin", - .protocol_major = 0x5, - .protocol_minor = 0x7, .rt_config = npu1_default_rt_cfg, .dpm_clk_tbl = npu1_dpm_clk_table, .fw_feature_tbl = npu1_fw_feature_table, @@ -92,6 +93,7 @@ static const struct amdxdna_dev_priv npu1_dev_priv = { DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU1_PSP, MPNPU_PUB_SEC_INTR), DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU1_PSP, MPNPU_PUB_SCRATCH2), DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU1_PSP, MPNPU_PUB_SCRATCH3), + DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU1_PSP, MPNPU_PWAITMODE), }, .smu_regs_off = { DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU1_SMU, MPNPU_PUB_SCRATCH5), diff --git a/drivers/accel/amdxdna/npu2_regs.c b/drivers/accel/amdxdna/npu2_regs.c deleted file mode 100644 index 86f87d0d13540..0000000000000 --- a/drivers/accel/amdxdna/npu2_regs.c +++ /dev/null @@ -1,115 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023-2024, Advanced Micro Devices, Inc. - */ - -#include -#include -#include -#include - -#include "aie2_pci.h" -#include "amdxdna_mailbox.h" -#include "amdxdna_pci_drv.h" - -/* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ -#define MPNPU_PUB_SEC_INTR 0x3010060 -#define MPNPU_PUB_PWRMGMT_INTR 0x3010064 -#define MPNPU_PUB_SCRATCH0 0x301006C -#define MPNPU_PUB_SCRATCH1 0x3010070 -#define MPNPU_PUB_SCRATCH2 0x3010074 -#define MPNPU_PUB_SCRATCH3 0x3010078 -#define MPNPU_PUB_SCRATCH4 0x301007C -#define MPNPU_PUB_SCRATCH5 0x3010080 -#define MPNPU_PUB_SCRATCH6 0x3010084 -#define MPNPU_PUB_SCRATCH7 0x3010088 -#define MPNPU_PUB_SCRATCH8 0x301008C -#define MPNPU_PUB_SCRATCH9 0x3010090 -#define MPNPU_PUB_SCRATCH10 0x3010094 -#define MPNPU_PUB_SCRATCH11 0x3010098 -#define MPNPU_PUB_SCRATCH12 0x301009C -#define MPNPU_PUB_SCRATCH13 0x30100A0 -#define MPNPU_PUB_SCRATCH14 0x30100A4 -#define MPNPU_PUB_SCRATCH15 0x30100A8 -#define MP0_C2PMSG_73 0x3810A24 -#define MP0_C2PMSG_123 0x3810AEC - -#define MP1_C2PMSG_0 0x3B10900 -#define MP1_C2PMSG_60 0x3B109F0 -#define MP1_C2PMSG_61 0x3B109F4 - -#define MPNPU_SRAM_X2I_MAILBOX_0 0x3600000 -#define MPNPU_SRAM_X2I_MAILBOX_15 0x361E000 -#define MPNPU_SRAM_X2I_MAILBOX_31 0x363E000 -#define MPNPU_SRAM_I2X_MAILBOX_31 0x363F000 - -#define MMNPU_APERTURE0_BASE 0x3000000 -#define MMNPU_APERTURE1_BASE 0x3600000 -#define MMNPU_APERTURE3_BASE 0x3810000 -#define MMNPU_APERTURE4_BASE 0x3B10000 - -/* PCIe BAR Index for NPU2 */ -#define NPU2_REG_BAR_INDEX 0 -#define NPU2_MBOX_BAR_INDEX 0 -#define NPU2_PSP_BAR_INDEX 4 -#define NPU2_SMU_BAR_INDEX 5 -#define NPU2_SRAM_BAR_INDEX 2 -/* Associated BARs and Apertures */ -#define NPU2_REG_BAR_BASE MMNPU_APERTURE0_BASE -#define NPU2_MBOX_BAR_BASE MMNPU_APERTURE0_BASE -#define NPU2_PSP_BAR_BASE MMNPU_APERTURE3_BASE -#define NPU2_SMU_BAR_BASE MMNPU_APERTURE4_BASE -#define NPU2_SRAM_BAR_BASE MMNPU_APERTURE1_BASE - -static const struct amdxdna_dev_priv npu2_dev_priv = { - .fw_path = "amdnpu/17f0_00/npu.sbin", - .protocol_major = 0x6, - .protocol_minor = 0x6, - .rt_config = npu4_default_rt_cfg, - .dpm_clk_tbl = npu4_dpm_clk_table, - .fw_feature_tbl = npu4_fw_feature_table, - .col_align = COL_ALIGN_NATURE, - .mbox_dev_addr = NPU2_MBOX_BAR_BASE, - .mbox_size = 0, /* Use BAR size */ - .sram_dev_addr = NPU2_SRAM_BAR_BASE, - .hwctx_limit = 16, - .sram_offs = { - DEFINE_BAR_OFFSET(MBOX_CHANN_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_0), - DEFINE_BAR_OFFSET(FW_ALIVE_OFF, NPU2_SRAM, MPNPU_SRAM_X2I_MAILBOX_15), - }, - .psp_regs_off = { - DEFINE_BAR_OFFSET(PSP_CMD_REG, NPU2_PSP, MP0_C2PMSG_123), - DEFINE_BAR_OFFSET(PSP_ARG0_REG, NPU2_REG, MPNPU_PUB_SCRATCH3), - DEFINE_BAR_OFFSET(PSP_ARG1_REG, NPU2_REG, MPNPU_PUB_SCRATCH4), - DEFINE_BAR_OFFSET(PSP_ARG2_REG, NPU2_REG, MPNPU_PUB_SCRATCH9), - DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU2_PSP, MP0_C2PMSG_73), - DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU2_PSP, MP0_C2PMSG_123), - DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU2_REG, MPNPU_PUB_SCRATCH3), - }, - .smu_regs_off = { - DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU2_SMU, MP1_C2PMSG_0), - DEFINE_BAR_OFFSET(SMU_ARG_REG, NPU2_SMU, MP1_C2PMSG_60), - DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU2_SMU, MMNPU_APERTURE4_BASE), - DEFINE_BAR_OFFSET(SMU_RESP_REG, NPU2_SMU, MP1_C2PMSG_61), - DEFINE_BAR_OFFSET(SMU_OUT_REG, NPU2_SMU, MP1_C2PMSG_60), - }, - .hw_ops = { - .set_dpm = npu4_set_dpm, - }, -}; - -const struct amdxdna_dev_info dev_npu2_info = { - .reg_bar = NPU2_REG_BAR_INDEX, - .mbox_bar = NPU2_MBOX_BAR_INDEX, - .sram_bar = NPU2_SRAM_BAR_INDEX, - .psp_bar = NPU2_PSP_BAR_INDEX, - .smu_bar = NPU2_SMU_BAR_INDEX, - .first_col = 0, - .dev_mem_buf_shift = 15, /* 32 KiB aligned */ - .dev_mem_base = AIE2_DEVM_BASE, - .dev_mem_size = AIE2_DEVM_SIZE, - .vbnv = "RyzenAI-npu2", - .device_type = AMDXDNA_DEV_TYPE_KMQ, - .dev_priv = &npu2_dev_priv, - .ops = &aie2_ops, /* NPU2 can share NPU1's callback */ -}; diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4_regs.c index 986a5f28ba245..a8d6f76dde5f9 100644 --- a/drivers/accel/amdxdna/npu4_regs.c +++ b/drivers/accel/amdxdna/npu4_regs.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include "aie2_pci.h" @@ -13,6 +14,7 @@ #include "amdxdna_pci_drv.h" /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ +#define MPNPU_PWAITMODE 0x301003C #define MPNPU_PUB_SEC_INTR 0x3010060 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 #define MPNPU_PUB_SCRATCH0 0x301006C @@ -87,15 +89,16 @@ const struct dpm_clk_freq npu4_dpm_clk_table[] = { }; const struct aie2_fw_feature_tbl npu4_fw_feature_table[] = { - { .feature = AIE2_NPU_COMMAND, .min_minor = 15 }, - { .feature = AIE2_PREEMPT, .min_minor = 12 }, + { .major = 6, .min_minor = 12 }, + { .features = BIT_U64(AIE2_NPU_COMMAND), .major = 6, .min_minor = 15 }, + { .features = BIT_U64(AIE2_PREEMPT), .major = 6, .min_minor = 12 }, + { .features = BIT_U64(AIE2_TEMPORAL_ONLY), .major = 6, .min_minor = 12 }, + { .features = GENMASK_ULL(AIE2_TEMPORAL_ONLY, AIE2_NPU_COMMAND), .major = 7 }, { 0 } }; static const struct amdxdna_dev_priv npu4_dev_priv = { .fw_path = "amdnpu/17f0_10/npu.sbin", - .protocol_major = 0x6, - .protocol_minor = 12, .rt_config = npu4_default_rt_cfg, .dpm_clk_tbl = npu4_dpm_clk_table, .fw_feature_tbl = npu4_fw_feature_table, @@ -116,6 +119,7 @@ static const struct amdxdna_dev_priv npu4_dev_priv = { DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU4_PSP, MP0_C2PMSG_73), DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU4_PSP, MP0_C2PMSG_123), DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU4_REG, MPNPU_PUB_SCRATCH3), + DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU4_REG, MPNPU_PWAITMODE), }, .smu_regs_off = { DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU4_SMU, MP1_C2PMSG_0), diff --git a/drivers/accel/amdxdna/npu5_regs.c b/drivers/accel/amdxdna/npu5_regs.c index 75ad97f0b9370..c0a35cfd886cc 100644 --- a/drivers/accel/amdxdna/npu5_regs.c +++ b/drivers/accel/amdxdna/npu5_regs.c @@ -13,6 +13,7 @@ #include "amdxdna_pci_drv.h" /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ +#define MPNPU_PWAITMODE 0x301003C #define MPNPU_PUB_SEC_INTR 0x3010060 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 #define MPNPU_PUB_SCRATCH0 0x301006C @@ -63,8 +64,6 @@ static const struct amdxdna_dev_priv npu5_dev_priv = { .fw_path = "amdnpu/17f0_11/npu.sbin", - .protocol_major = 0x6, - .protocol_minor = 12, .rt_config = npu4_default_rt_cfg, .dpm_clk_tbl = npu4_dpm_clk_table, .fw_feature_tbl = npu4_fw_feature_table, @@ -85,6 +84,7 @@ static const struct amdxdna_dev_priv npu5_dev_priv = { DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU5_PSP, MP0_C2PMSG_73), DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU5_PSP, MP0_C2PMSG_123), DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU5_REG, MPNPU_PUB_SCRATCH3), + DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU5_REG, MPNPU_PWAITMODE), }, .smu_regs_off = { DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU5_SMU, MP1_C2PMSG_0), diff --git a/drivers/accel/amdxdna/npu6_regs.c b/drivers/accel/amdxdna/npu6_regs.c index 758dc013fe13b..1fb07df991860 100644 --- a/drivers/accel/amdxdna/npu6_regs.c +++ b/drivers/accel/amdxdna/npu6_regs.c @@ -13,6 +13,7 @@ #include "amdxdna_pci_drv.h" /* NPU Public Registers on MpNPUAxiXbar (refer to Diag npu_registers.h) */ +#define MPNPU_PWAITMODE 0x301003C #define MPNPU_PUB_SEC_INTR 0x3010060 #define MPNPU_PUB_PWRMGMT_INTR 0x3010064 #define MPNPU_PUB_SCRATCH0 0x301006C @@ -63,8 +64,6 @@ static const struct amdxdna_dev_priv npu6_dev_priv = { .fw_path = "amdnpu/17f0_10/npu.sbin", - .protocol_major = 0x6, - .protocol_minor = 12, .rt_config = npu4_default_rt_cfg, .dpm_clk_tbl = npu4_dpm_clk_table, .fw_feature_tbl = npu4_fw_feature_table, @@ -85,6 +84,7 @@ static const struct amdxdna_dev_priv npu6_dev_priv = { DEFINE_BAR_OFFSET(PSP_INTR_REG, NPU6_PSP, MP0_C2PMSG_73), DEFINE_BAR_OFFSET(PSP_STATUS_REG, NPU6_PSP, MP0_C2PMSG_123), DEFINE_BAR_OFFSET(PSP_RESP_REG, NPU6_REG, MPNPU_PUB_SCRATCH3), + DEFINE_BAR_OFFSET(PSP_PWAITMODE_REG, NPU6_REG, MPNPU_PWAITMODE), }, .smu_regs_off = { DEFINE_BAR_OFFSET(SMU_CMD_REG, NPU6_SMU, MP1_C2PMSG_0), diff --git a/drivers/accel/ivpu/ivpu_debugfs.c b/drivers/accel/ivpu/ivpu_debugfs.c index 3bd85ee6c26b7..a09f54fc43020 100644 --- a/drivers/accel/ivpu/ivpu_debugfs.c +++ b/drivers/accel/ivpu/ivpu_debugfs.c @@ -20,6 +20,7 @@ #include "ivpu_hw.h" #include "ivpu_jsm_msg.h" #include "ivpu_pm.h" +#include "vpu_boot_api.h" static inline struct ivpu_device *seq_to_ivpu(struct seq_file *s) { @@ -96,7 +97,8 @@ static int last_bootmode_show(struct seq_file *s, void *v) { struct ivpu_device *vdev = seq_to_ivpu(s); - seq_printf(s, "%s\n", (vdev->pm->is_warmboot) ? "warmboot" : "coldboot"); + seq_printf(s, "%s\n", (vdev->fw->last_boot_mode == VPU_BOOT_TYPE_WARMBOOT) ? + "warm boot" : "cold boot"); return 0; } diff --git a/drivers/accel/ivpu/ivpu_drv.c b/drivers/accel/ivpu/ivpu_drv.c index 3d6fccdefdd64..8ffda57459dfb 100644 --- a/drivers/accel/ivpu/ivpu_drv.c +++ b/drivers/accel/ivpu/ivpu_drv.c @@ -384,6 +384,7 @@ int ivpu_boot(struct ivpu_device *vdev) drm_WARN_ON(&vdev->drm, !xa_empty(&vdev->submitted_jobs_xa)); ivpu_fw_boot_params_setup(vdev, ivpu_bo_vaddr(vdev->fw->mem_bp)); + vdev->fw->last_boot_mode = vdev->fw->next_boot_mode; ret = ivpu_hw_boot_fw(vdev); if (ret) { @@ -396,13 +397,12 @@ int ivpu_boot(struct ivpu_device *vdev) ivpu_err(vdev, "Failed to boot the firmware: %d\n", ret); goto err_diagnose_failure; } - ivpu_hw_irq_clear(vdev); enable_irq(vdev->irq); ivpu_hw_irq_enable(vdev); ivpu_ipc_enable(vdev); - if (ivpu_fw_is_cold_boot(vdev)) { + if (!ivpu_fw_is_warm_boot(vdev)) { ret = ivpu_pm_dct_init(vdev); if (ret) goto err_disable_ipc; diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c index 48386d2cddbb2..107f8ad310500 100644 --- a/drivers/accel/ivpu/ivpu_fw.c +++ b/drivers/accel/ivpu/ivpu_fw.c @@ -300,9 +300,7 @@ static int ivpu_fw_parse(struct ivpu_device *vdev) fw->image_load_offset = image_load_addr - runtime_addr; fw->image_size = image_size; fw->shave_nn_size = PAGE_ALIGN(fw_hdr->shave_nn_fw_size); - fw->cold_boot_entry_point = fw_hdr->entry_point; - fw->entry_point = fw->cold_boot_entry_point; fw->trace_level = min_t(u32, ivpu_fw_log_level, IVPU_FW_LOG_FATAL); fw->trace_destination_mask = VPU_TRACE_DESTINATION_VERBOSE_TRACING; @@ -338,7 +336,7 @@ static int ivpu_fw_parse(struct ivpu_device *vdev) fw->image_load_offset, fw->image_size); ivpu_dbg(vdev, FW_BOOT, "Read-only section: address 0x%llx, size %u\n", fw->read_only_addr, fw->read_only_size); - ivpu_dbg(vdev, FW_BOOT, "FW entry point: 0x%llx\n", fw->entry_point); + ivpu_dbg(vdev, FW_BOOT, "FW cold boot entry point: 0x%llx\n", fw->cold_boot_entry_point); ivpu_dbg(vdev, FW_BOOT, "SHAVE NN size: %u\n", fw->shave_nn_size); return 0; @@ -616,6 +614,7 @@ static void ivpu_fw_boot_params_print(struct ivpu_device *vdev, struct vpu_boot_ boot_params->power_profile); ivpu_dbg(vdev, FW_BOOT, "boot_params.vpu_uses_ecc_mca_signal = 0x%x\n", boot_params->vpu_uses_ecc_mca_signal); + ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", boot_params->boot_type); } void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params) @@ -623,7 +622,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params struct ivpu_bo *ipc_mem_rx = vdev->ipc->mem_rx; /* In case of warm boot only update variable params */ - if (!ivpu_fw_is_cold_boot(vdev)) { + if (ivpu_fw_is_warm_boot(vdev)) { boot_params->d0i3_residency_time_us = ktime_us_delta(ktime_get_boottime(), vdev->hw->d0i3_entry_host_ts); boot_params->d0i3_entry_vpu_ts = vdev->hw->d0i3_entry_vpu_ts; @@ -635,16 +634,16 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params boot_params->d0i3_entry_vpu_ts); ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", boot_params->system_time_us); + ivpu_dbg(vdev, FW_BOOT, "boot_params.boot_type = 0x%x\n", boot_params->boot_type); boot_params->save_restore_ret_address = 0; - vdev->pm->is_warmboot = true; + boot_params->boot_type = VPU_BOOT_TYPE_WARMBOOT; wmb(); /* Flush WC buffers after writing save_restore_ret_address */ return; } memset(boot_params, 0, sizeof(*boot_params)); - vdev->pm->is_warmboot = false; - + boot_params->boot_type = VPU_BOOT_TYPE_COLDBOOT; boot_params->magic = VPU_BOOT_PARAMS_MAGIC; boot_params->vpu_id = to_pci_dev(vdev->drm.dev)->bus->number; diff --git a/drivers/accel/ivpu/ivpu_fw.h b/drivers/accel/ivpu/ivpu_fw.h index 00945892b55ef..d3c410912c9cb 100644 --- a/drivers/accel/ivpu/ivpu_fw.h +++ b/drivers/accel/ivpu/ivpu_fw.h @@ -6,6 +6,7 @@ #ifndef __IVPU_FW_H__ #define __IVPU_FW_H__ +#include "vpu_boot_api.h" #include "vpu_jsm_api.h" #define FW_VERSION_HEADER_SIZE SZ_4K @@ -34,8 +35,10 @@ struct ivpu_fw_info { u64 image_load_offset; u32 image_size; u32 shave_nn_size; - u64 entry_point; /* Cold or warm boot entry point for next boot */ + u64 warm_boot_entry_point; u64 cold_boot_entry_point; + u8 last_boot_mode; + u8 next_boot_mode; u32 trace_level; u32 trace_destination_mask; u64 trace_hw_component_mask; @@ -54,9 +57,9 @@ void ivpu_fw_fini(struct ivpu_device *vdev); void ivpu_fw_load(struct ivpu_device *vdev); void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params *boot_params); -static inline bool ivpu_fw_is_cold_boot(struct ivpu_device *vdev) +static inline bool ivpu_fw_is_warm_boot(struct ivpu_device *vdev) { - return vdev->fw->entry_point == vdev->fw->cold_boot_entry_point; + return vdev->fw->next_boot_mode == VPU_BOOT_TYPE_WARMBOOT; } static inline u32 ivpu_fw_preempt_buf_size(struct ivpu_device *vdev) diff --git a/drivers/accel/ivpu/ivpu_gem.c b/drivers/accel/ivpu/ivpu_gem.c index ece68f570b7ea..98b9ce26962b1 100644 --- a/drivers/accel/ivpu/ivpu_gem.c +++ b/drivers/accel/ivpu/ivpu_gem.c @@ -95,7 +95,7 @@ int __must_check ivpu_bo_bind(struct ivpu_bo *bo) if (!bo->mmu_mapped) { drm_WARN_ON(&vdev->drm, !bo->ctx); - ret = ivpu_mmu_context_map_sgt(vdev, bo->ctx, bo->vpu_addr, sgt, + ret = ivpu_mmu_context_map_sgt(vdev, bo->ctx, bo->vpu_addr, sgt, ivpu_bo_size(bo), ivpu_bo_is_snooped(bo), ivpu_bo_is_read_only(bo)); if (ret) { ivpu_err(vdev, "Failed to map BO in MMU: %d\n", ret); diff --git a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h index fc0ee8d637f96..421242acb1844 100644 --- a/drivers/accel/ivpu/ivpu_hw_40xx_reg.h +++ b/drivers/accel/ivpu/ivpu_hw_40xx_reg.h @@ -121,6 +121,12 @@ #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY 0x0003006cu #define VPU_50XX_HOST_SS_AON_PWR_ISLAND_STATUS_DLY_STATUS_DLY_MASK GENMASK(7, 0) +#define VPU_40XX_HOST_SS_AON_RETENTION0 0x0003000cu +#define VPU_40XX_HOST_SS_AON_RETENTION1 0x00030010u +#define VPU_40XX_HOST_SS_AON_RETENTION2 0x00030014u +#define VPU_40XX_HOST_SS_AON_RETENTION3 0x00030018u +#define VPU_40XX_HOST_SS_AON_RETENTION4 0x0003001cu + #define VPU_40XX_HOST_SS_AON_IDLE_GEN 0x00030200u #define VPU_40XX_HOST_SS_AON_IDLE_GEN_EN_MASK BIT_MASK(0) #define VPU_40XX_HOST_SS_AON_IDLE_GEN_HW_PG_EN_MASK BIT_MASK(1) diff --git a/drivers/accel/ivpu/ivpu_hw_ip.c b/drivers/accel/ivpu/ivpu_hw_ip.c index 06aa1e7dc50b1..959984c54341a 100644 --- a/drivers/accel/ivpu/ivpu_hw_ip.c +++ b/drivers/accel/ivpu/ivpu_hw_ip.c @@ -5,6 +5,7 @@ #include "ivpu_drv.h" #include "ivpu_fw.h" +#include "ivpu_gem.h" #include "ivpu_hw.h" #include "ivpu_hw_37xx_reg.h" #include "ivpu_hw_40xx_reg.h" @@ -816,6 +817,14 @@ void ivpu_hw_ip_tbu_mmu_enable(struct ivpu_device *vdev) return ivpu_hw_ip_tbu_mmu_enable_40xx(vdev); } +static inline u64 get_entry_point_addr(struct ivpu_device *vdev) +{ + if (ivpu_fw_is_warm_boot(vdev)) + return vdev->fw->warm_boot_entry_point; + else + return vdev->fw->cold_boot_entry_point; +} + static int soc_cpu_boot_37xx(struct ivpu_device *vdev) { u32 val; @@ -832,15 +841,12 @@ static int soc_cpu_boot_37xx(struct ivpu_device *vdev) val = REG_CLR_FLD(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, IRQI_RESUME0, val); REGV_WR32(VPU_37XX_CPU_SS_MSSCPU_CPR_LEON_RT_VEC, val); - val = vdev->fw->entry_point >> 9; + val = get_entry_point_addr(vdev) >> 9; REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); val = REG_SET_FLD(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, DONE, val); REGV_WR32(VPU_37XX_HOST_SS_LOADING_ADDRESS_LO, val); - ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", - vdev->fw->entry_point == vdev->fw->cold_boot_entry_point ? "cold boot" : "resume"); - return 0; } @@ -894,46 +900,68 @@ static int soc_cpu_drive_40xx(struct ivpu_device *vdev, bool enable) return ret; } -static int soc_cpu_enable(struct ivpu_device *vdev) +static void soc_cpu_set_entry_point_40xx(struct ivpu_device *vdev, u64 entry_point) { - if (ivpu_hw_ip_gen(vdev) >= IVPU_HW_IP_60XX) - return 0; + u64 val64; + u32 val; + + val64 = entry_point; + val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1; + REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); - return soc_cpu_drive_40xx(vdev, true); + val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO); + val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val); + REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val); } static int soc_cpu_boot_40xx(struct ivpu_device *vdev) { int ret; - u32 val; - u64 val64; - ret = soc_cpu_enable(vdev); + ret = soc_cpu_drive_40xx(vdev, true); if (ret) { ivpu_err(vdev, "Failed to enable SOC CPU: %d\n", ret); return ret; } - val64 = vdev->fw->entry_point; - val64 <<= ffs(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO_IMAGE_LOCATION_MASK) - 1; - REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); + soc_cpu_set_entry_point_40xx(vdev, get_entry_point_addr(vdev)); - val = REGV_RD32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO); - val = REG_SET_FLD(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, DONE, val); - REGV_WR32(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val); + return 0; +} - ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", - ivpu_fw_is_cold_boot(vdev) ? "cold boot" : "resume"); +static int soc_cpu_boot_60xx(struct ivpu_device *vdev) +{ + REGV_WR64(VPU_40XX_HOST_SS_AON_RETENTION1, vdev->fw->mem_bp->vpu_addr); + soc_cpu_set_entry_point_40xx(vdev, vdev->fw->cold_boot_entry_point); return 0; } int ivpu_hw_ip_soc_cpu_boot(struct ivpu_device *vdev) { - if (ivpu_hw_ip_gen(vdev) == IVPU_HW_IP_37XX) - return soc_cpu_boot_37xx(vdev); - else - return soc_cpu_boot_40xx(vdev); + int ret; + + switch (ivpu_hw_ip_gen(vdev)) { + case IVPU_HW_IP_37XX: + ret = soc_cpu_boot_37xx(vdev); + break; + + case IVPU_HW_IP_40XX: + case IVPU_HW_IP_50XX: + ret = soc_cpu_boot_40xx(vdev); + break; + + default: + ret = soc_cpu_boot_60xx(vdev); + } + + if (ret) + return ret; + + ivpu_dbg(vdev, PM, "Booting firmware, mode: %s\n", + ivpu_fw_is_warm_boot(vdev) ? "warm boot" : "cold boot"); + + return 0; } static void wdt_disable_37xx(struct ivpu_device *vdev) diff --git a/drivers/accel/ivpu/ivpu_hw_ip.h b/drivers/accel/ivpu/ivpu_hw_ip.h index 5b1b391aa5772..dbbcdd10a5f8c 100644 --- a/drivers/accel/ivpu/ivpu_hw_ip.h +++ b/drivers/accel/ivpu/ivpu_hw_ip.h @@ -29,7 +29,6 @@ u32 ivpu_hw_ip_ipc_rx_addr_get(struct ivpu_device *vdev); void ivpu_hw_ip_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr); void ivpu_hw_ip_irq_enable(struct ivpu_device *vdev); void ivpu_hw_ip_irq_disable(struct ivpu_device *vdev); -void ivpu_hw_ip_diagnose_failure(struct ivpu_device *vdev); void ivpu_hw_ip_fabric_req_override_enable_50xx(struct ivpu_device *vdev); void ivpu_hw_ip_fabric_req_override_disable_50xx(struct ivpu_device *vdev); diff --git a/drivers/accel/ivpu/ivpu_mmu_context.c b/drivers/accel/ivpu/ivpu_mmu_context.c index 87ad593ef47d3..c4014c83e7271 100644 --- a/drivers/accel/ivpu/ivpu_mmu_context.c +++ b/drivers/accel/ivpu/ivpu_mmu_context.c @@ -429,11 +429,12 @@ static void ivpu_mmu_context_unmap_pages(struct ivpu_mmu_context *ctx, u64 vpu_a } int -ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, - u64 vpu_addr, struct sg_table *sgt, bool llc_coherent, bool read_only) +ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, + struct sg_table *sgt, size_t bo_size, bool llc_coherent, bool read_only) { size_t start_vpu_addr = vpu_addr; struct scatterlist *sg; + size_t sgt_size = 0; int ret; u64 prot; u64 i; @@ -462,12 +463,25 @@ ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, ivpu_dbg(vdev, MMU_MAP, "Map ctx: %u dma_addr: 0x%llx vpu_addr: 0x%llx size: %lu\n", ctx->id, dma_addr, vpu_addr, size); + if (sgt_size + size > bo_size) { + ivpu_err(vdev, "Scatter-gather table size exceeds buffer object size\n"); + ret = -EINVAL; + goto err_unmap_pages; + } + ret = ivpu_mmu_context_map_pages(vdev, ctx, vpu_addr, dma_addr, size, prot); if (ret) { ivpu_err(vdev, "Failed to map context pages\n"); goto err_unmap_pages; } vpu_addr += size; + sgt_size += size; + } + + if (sgt_size < bo_size) { + ivpu_err(vdev, "Scatter-gather table size too small to cover buffer object size\n"); + ret = -EINVAL; + goto err_unmap_pages; } if (!ctx->is_cd_valid) { @@ -493,7 +507,7 @@ ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, return 0; err_unmap_pages: - ivpu_mmu_context_unmap_pages(ctx, start_vpu_addr, vpu_addr - start_vpu_addr); + ivpu_mmu_context_unmap_pages(ctx, start_vpu_addr, sgt_size); mutex_unlock(&ctx->lock); return ret; } diff --git a/drivers/accel/ivpu/ivpu_mmu_context.h b/drivers/accel/ivpu/ivpu_mmu_context.h index 663a11a9db111..cc02e7bab04e6 100644 --- a/drivers/accel/ivpu/ivpu_mmu_context.h +++ b/drivers/accel/ivpu/ivpu_mmu_context.h @@ -41,8 +41,9 @@ int ivpu_mmu_context_insert_node(struct ivpu_mmu_context *ctx, const struct ivpu u64 size, struct drm_mm_node *node); void ivpu_mmu_context_remove_node(struct ivpu_mmu_context *ctx, struct drm_mm_node *node); -int ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, - u64 vpu_addr, struct sg_table *sgt, bool llc_coherent, bool read_only); +int +ivpu_mmu_context_map_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, + struct sg_table *sgt, size_t bo_size, bool llc_coherent, bool read_only); void ivpu_mmu_context_unmap_sgt(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, u64 vpu_addr, struct sg_table *sgt); int ivpu_mmu_context_set_pages_ro(struct ivpu_device *vdev, struct ivpu_mmu_context *ctx, diff --git a/drivers/accel/ivpu/ivpu_pm.c b/drivers/accel/ivpu/ivpu_pm.c index 480c075d87f69..d20144a21e090 100644 --- a/drivers/accel/ivpu/ivpu_pm.c +++ b/drivers/accel/ivpu/ivpu_pm.c @@ -47,8 +47,10 @@ static void ivpu_pm_prepare_cold_boot(struct ivpu_device *vdev) ivpu_ipc_reset(vdev); ivpu_fw_log_reset(vdev); ivpu_fw_load(vdev); - fw->entry_point = fw->cold_boot_entry_point; fw->last_heartbeat = 0; + + ivpu_dbg(vdev, FW_BOOT, "Cold boot entry point 0x%llx", vdev->fw->cold_boot_entry_point); + fw->next_boot_mode = VPU_BOOT_TYPE_COLDBOOT; } static void ivpu_pm_prepare_warm_boot(struct ivpu_device *vdev) @@ -56,13 +58,14 @@ static void ivpu_pm_prepare_warm_boot(struct ivpu_device *vdev) struct ivpu_fw_info *fw = vdev->fw; struct vpu_boot_params *bp = ivpu_bo_vaddr(fw->mem_bp); - if (!bp->save_restore_ret_address) { + fw->warm_boot_entry_point = bp->save_restore_ret_address; + if (!fw->warm_boot_entry_point) { ivpu_pm_prepare_cold_boot(vdev); return; } - ivpu_dbg(vdev, FW_BOOT, "Save/restore entry point %llx", bp->save_restore_ret_address); - fw->entry_point = bp->save_restore_ret_address; + ivpu_dbg(vdev, FW_BOOT, "Warm boot entry point 0x%llx", fw->warm_boot_entry_point); + fw->next_boot_mode = VPU_BOOT_TYPE_WARMBOOT; } static int ivpu_suspend(struct ivpu_device *vdev) @@ -110,7 +113,7 @@ static int ivpu_resume(struct ivpu_device *vdev) ivpu_hw_power_down(vdev); pci_set_power_state(to_pci_dev(vdev->drm.dev), PCI_D3hot); - if (!ivpu_fw_is_cold_boot(vdev)) { + if (ivpu_fw_is_warm_boot(vdev)) { ivpu_pm_prepare_cold_boot(vdev); goto retry; } else { diff --git a/drivers/accel/ivpu/ivpu_pm.h b/drivers/accel/ivpu/ivpu_pm.h index a2aa7a27f32ef..00f2a01e3df66 100644 --- a/drivers/accel/ivpu/ivpu_pm.h +++ b/drivers/accel/ivpu/ivpu_pm.h @@ -18,7 +18,6 @@ struct ivpu_pm_info { struct rw_semaphore reset_lock; atomic_t reset_counter; atomic_t reset_pending; - bool is_warmboot; u8 dct_active_percent; }; diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c index abe7719c1db46..b3b2fa9ba645a 100644 --- a/drivers/accel/rocket/rocket_core.c +++ b/drivers/accel/rocket/rocket_core.c @@ -59,8 +59,11 @@ int rocket_core_init(struct rocket_core *core) core->iommu_group = iommu_group_get(dev); err = rocket_job_init(core); - if (err) + if (err) { + iommu_group_put(core->iommu_group); + core->iommu_group = NULL; return err; + } pm_runtime_use_autosuspend(dev); @@ -76,7 +79,7 @@ int rocket_core_init(struct rocket_core *core) err = pm_runtime_resume_and_get(dev); if (err) { - rocket_job_fini(core); + rocket_core_fini(core); return err; } diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c index 5c0b63f0a8f00..e4cb2efeb55a4 100644 --- a/drivers/accel/rocket/rocket_drv.c +++ b/drivers/accel/rocket/rocket_drv.c @@ -13,6 +13,7 @@ #include #include +#include "rocket_device.h" #include "rocket_drv.h" #include "rocket_gem.h" #include "rocket_job.h" @@ -158,6 +159,8 @@ static const struct drm_driver rocket_drm_driver = { static int rocket_probe(struct platform_device *pdev) { + int ret; + if (rdev == NULL) { /* First core probing, initialize DRM device. */ rdev = rocket_device_init(drm_dev, &rocket_drm_driver); @@ -177,20 +180,31 @@ static int rocket_probe(struct platform_device *pdev) rdev->num_cores++; - return rocket_core_init(&rdev->cores[core]); + ret = rocket_core_init(&rdev->cores[core]); + if (ret) { + rdev->num_cores--; + + if (rdev->num_cores == 0) { + rocket_device_fini(rdev); + rdev = NULL; + } + } + + return ret; } +static int find_core_for_dev(struct device *dev); + static void rocket_remove(struct platform_device *pdev) { struct device *dev = &pdev->dev; + int core = find_core_for_dev(dev); - for (unsigned int core = 0; core < rdev->num_cores; core++) { - if (rdev->cores[core].dev == dev) { - rocket_core_fini(&rdev->cores[core]); - rdev->num_cores--; - break; - } - } + if (core < 0) + return; + + rocket_core_fini(&rdev->cores[core]); + rdev->num_cores--; if (rdev->num_cores == 0) { /* Last core removed, deinitialize DRM device. */ diff --git a/drivers/block/umem.c b/drivers/block/umem.c new file mode 100644 index 0000000000000..664280f23bee1 --- /dev/null +++ b/drivers/block/umem.c @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3 + * + * (C) 2001 San Mehat + * (C) 2001 Johannes Erdfelt + * (C) 2001 NeilBrown + * + * This driver for the Micro Memory PCI Memory Module with Battery Backup + * is Copyright Micro Memory Inc 2001-2002. All rights reserved. + * + * This driver provides a standard block device interface for Micro Memory(tm) + * PCI based RAM boards. + * 10/05/01: Phap Nguyen - Rebuilt the driver + * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning + * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn + * - use stand disk partitioning (so fdisk works). + * 08nov2001:NeilBrown - change driver name from "mm" to "umem" + * - incorporate into main kernel + * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet + * - use spin_lock_bh instead of _irq + * - Never block on make_request. queue + * bh's instead. + * - unregister umem from devfs at mod unload + * - Change version to 2.3 + * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal) + * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA + * 15May2002:NeilBrown - convert to bio for 2.5 + * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect + * - a sequence of writes that cover the card, and + * - set initialised bit then. + */ + +#undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include /* O_ACCMODE */ +#include /* HDIO_GETGEO */ + +#include "umem.h" + +#include +#include + +#define MM_MAXCARDS 4 +#define MM_RAHEAD 2 /* two sectors */ +#define MM_BLKSIZE 1024 /* 1k blocks */ +#define MM_HARDSECT 512 /* 512-byte hardware sectors */ +#define MM_SHIFT 6 /* max 64 partitions on 4 cards */ + +/* + * Version Information + */ + +#define DRIVER_NAME "umem" +#define DRIVER_VERSION "v2.3" +#define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown" +#define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver" + +static int debug; +/* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */ +#define HW_TRACE(x) + +#define DEBUG_LED_ON_TRANSFER 0x01 +#define DEBUG_BATTERY_POLLING 0x02 + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug bitmask"); + +static int pci_read_cmd = 0x0C; /* Read Multiple */ +module_param(pci_read_cmd, int, 0); +MODULE_PARM_DESC(pci_read_cmd, "PCI read command"); + +static int pci_write_cmd = 0x0F; /* Write and Invalidate */ +module_param(pci_write_cmd, int, 0); +MODULE_PARM_DESC(pci_write_cmd, "PCI write command"); + +static int pci_cmds; + +static int major_nr; + +#include +#include + +struct cardinfo { + struct pci_dev *dev; + + unsigned char __iomem *csr_remap; + unsigned int mm_size; /* size in kbytes */ + + unsigned int init_size; /* initial segment, in sectors, + * that we know to + * have been written + */ + struct bio *bio, *currentbio, **biotail; + struct bvec_iter current_iter; + + struct request_queue *queue; + + struct mm_page { + dma_addr_t page_dma; + struct mm_dma_desc *desc; + int cnt, headcnt; + struct bio *bio, **biotail; + struct bvec_iter iter; + } mm_pages[2]; +#define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc)) + + int Active, Ready; + + struct tasklet_struct tasklet; + unsigned int dma_status; + + struct { + int good; + int warned; + unsigned long last_change; + } battery[2]; + + spinlock_t lock; + int check_batteries; + + int flags; +}; + +static struct cardinfo cards[MM_MAXCARDS]; +static struct timer_list battery_timer; + +static int num_cards; + +static struct gendisk *mm_gendisk[MM_MAXCARDS]; + +static void check_batteries(struct cardinfo *card); + +static int get_userbit(struct cardinfo *card, int bit) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + return led & bit; +} + +static int set_userbit(struct cardinfo *card, int bit, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state) + led |= bit; + else + led &= ~bit; + writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL); + + return 0; +} + +/* + * NOTE: For the power LED, use the LED_POWER_* macros since they differ + */ +static void set_led(struct cardinfo *card, int shift, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state == LED_FLIP) + led ^= (1<csr_remap + MEMCTRLCMD_LEDCTRL); + +} + +#ifdef MM_DIAG +static void dump_regs(struct cardinfo *card) +{ + unsigned char *p; + int i, i1; + + p = card->csr_remap; + for (i = 0; i < 8; i++) { + printk(KERN_DEBUG "%p ", p); + + for (i1 = 0; i1 < 16; i1++) + printk("%02x ", *p++); + + printk("\n"); + } +} +#endif + +static void dump_dmastat(struct cardinfo *card, unsigned int dmastat) +{ + dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - "); + if (dmastat & DMASCR_ANY_ERR) + printk(KERN_CONT "ANY_ERR "); + if (dmastat & DMASCR_MBE_ERR) + printk(KERN_CONT "MBE_ERR "); + if (dmastat & DMASCR_PARITY_ERR_REP) + printk(KERN_CONT "PARITY_ERR_REP "); + if (dmastat & DMASCR_PARITY_ERR_DET) + printk(KERN_CONT "PARITY_ERR_DET "); + if (dmastat & DMASCR_SYSTEM_ERR_SIG) + printk(KERN_CONT "SYSTEM_ERR_SIG "); + if (dmastat & DMASCR_TARGET_ABT) + printk(KERN_CONT "TARGET_ABT "); + if (dmastat & DMASCR_MASTER_ABT) + printk(KERN_CONT "MASTER_ABT "); + if (dmastat & DMASCR_CHAIN_COMPLETE) + printk(KERN_CONT "CHAIN_COMPLETE "); + if (dmastat & DMASCR_DMA_COMPLETE) + printk(KERN_CONT "DMA_COMPLETE "); + printk("\n"); +} + +/* + * Theory of request handling + * + * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME + * We have two pages of mm_dma_desc, holding about 64 descriptors + * each. These are allocated at init time. + * One page is "Ready" and is either full, or can have request added. + * The other page might be "Active", which DMA is happening on it. + * + * Whenever IO on the active page completes, the Ready page is activated + * and the ex-Active page is clean out and made Ready. + * Otherwise the Ready page is only activated when it becomes full. + * + * If a request arrives while both pages a full, it is queued, and b_rdev is + * overloaded to record whether it was a read or a write. + * + * The interrupt handler only polls the device to clear the interrupt. + * The processing of the result is done in a tasklet. + */ + +static void mm_start_io(struct cardinfo *card) +{ + /* we have the lock, we know there is + * no IO active, and we know that card->Active + * is set + */ + struct mm_dma_desc *desc; + struct mm_page *page; + int offset; + + /* make the last descriptor end the chain */ + page = &card->mm_pages[card->Active]; + pr_debug("start_io: %d %d->%d\n", + card->Active, page->headcnt, page->cnt - 1); + desc = &page->desc[page->cnt-1]; + + desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN); + desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN); + desc->sem_control_bits = desc->control_bits; + + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_ON); + + desc = &page->desc[page->headcnt]; + writel(0, card->csr_remap + DMA_PCI_ADDR); + writel(0, card->csr_remap + DMA_PCI_ADDR + 4); + + writel(0, card->csr_remap + DMA_LOCAL_ADDR); + writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4); + + writel(0, card->csr_remap + DMA_TRANSFER_SIZE); + writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4); + + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR); + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4); + + offset = ((char *)desc) - ((char *)page->desc); + writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff), + card->csr_remap + DMA_DESCRIPTOR_ADDR); + /* Force the value to u64 before shifting otherwise >> 32 is undefined C + * and on some ports will do nothing ! */ + writel(cpu_to_le32(((u64)page->page_dma)>>32), + card->csr_remap + DMA_DESCRIPTOR_ADDR + 4); + + /* Go, go, go */ + writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds), + card->csr_remap + DMA_STATUS_CTRL); +} + +static int add_bio(struct cardinfo *card); + +static void activate(struct cardinfo *card) +{ + /* if No page is Active, and Ready is + * not empty, then switch Ready page + * to active and start IO. + * Then add any bh's that are available to Ready + */ + + do { + while (add_bio(card)) + ; + + if (card->Active == -1 && + card->mm_pages[card->Ready].cnt > 0) { + card->Active = card->Ready; + card->Ready = 1-card->Ready; + mm_start_io(card); + } + + } while (card->Active == -1 && add_bio(card)); +} + +static inline void reset_page(struct mm_page *page) +{ + page->cnt = 0; + page->headcnt = 0; + page->bio = NULL; + page->biotail = &page->bio; +} + +/* + * If there is room on Ready page, take + * one bh off list and add it. + * return 1 if there was room, else 0. + */ +static int add_bio(struct cardinfo *card) +{ + struct mm_page *p; + struct mm_dma_desc *desc; + dma_addr_t dma_handle; + int offset; + struct bio *bio; + struct bio_vec vec; + + bio = card->currentbio; + if (!bio && card->bio) { + card->currentbio = card->bio; + card->current_iter = card->bio->bi_iter; + card->bio = card->bio->bi_next; + if (card->bio == NULL) + card->biotail = &card->bio; + card->currentbio->bi_next = NULL; + return 1; + } + if (!bio) + return 0; + + if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE) + return 0; + + vec = bio_iter_iovec(bio, card->current_iter); + + dma_handle = dma_map_page(&card->dev->dev, + vec.bv_page, + vec.bv_offset, + vec.bv_len, + bio_op(bio) == REQ_OP_READ ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + + p = &card->mm_pages[card->Ready]; + desc = &p->desc[p->cnt]; + p->cnt++; + if (p->bio == NULL) + p->iter = card->current_iter; + if ((p->biotail) != &bio->bi_next) { + *(p->biotail) = bio; + p->biotail = &(bio->bi_next); + bio->bi_next = NULL; + } + + desc->data_dma_handle = dma_handle; + + desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle); + desc->local_addr = cpu_to_le64(card->current_iter.bi_sector << 9); + desc->transfer_size = cpu_to_le32(vec.bv_len); + offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc)); + desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset)); + desc->zero1 = desc->zero2 = 0; + offset = (((char *)(desc+1)) - ((char *)p->desc)); + desc->next_desc_addr = cpu_to_le64(p->page_dma+offset); + desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN| + DMASCR_PARITY_INT_EN| + DMASCR_CHAIN_EN | + DMASCR_SEM_EN | + pci_cmds); + if (bio_op(bio) == REQ_OP_WRITE) + desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ); + desc->sem_control_bits = desc->control_bits; + + + bio_advance_iter(bio, &card->current_iter, vec.bv_len); + if (!card->current_iter.bi_size) + card->currentbio = NULL; + + return 1; +} + +static void process_page(unsigned long data) +{ + /* check if any of the requests in the page are DMA_COMPLETE, + * and deal with them appropriately. + * If we find a descriptor without DMA_COMPLETE in the semaphore, then + * dma must have hit an error on that descriptor, so use dma_status + * instead and assume that all following descriptors must be re-tried. + */ + struct mm_page *page; + struct bio *return_bio = NULL; + struct cardinfo *card = (struct cardinfo *)data; + unsigned int dma_status = card->dma_status; + + spin_lock(&card->lock); + if (card->Active < 0) + goto out_unlock; + page = &card->mm_pages[card->Active]; + + while (page->headcnt < page->cnt) { + struct bio *bio = page->bio; + struct mm_dma_desc *desc = &page->desc[page->headcnt]; + int control = le32_to_cpu(desc->sem_control_bits); + int last = 0; + struct bio_vec vec; + + if (!(control & DMASCR_DMA_COMPLETE)) { + control = dma_status; + last = 1; + } + + page->headcnt++; + vec = bio_iter_iovec(bio, page->iter); + bio_advance_iter(bio, &page->iter, vec.bv_len); + + if (!page->iter.bi_size) { + page->bio = bio->bi_next; + if (page->bio) + page->iter = page->bio->bi_iter; + } + + dma_unmap_page(&card->dev->dev, desc->data_dma_handle, + vec.bv_len, + (control & DMASCR_TRANSFER_READ) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (control & DMASCR_HARD_ERROR) { + /* error */ + bio->bi_status = BLK_STS_IOERR; + dev_printk(KERN_WARNING, &card->dev->dev, + "I/O error on sector %d/%d\n", + le32_to_cpu(desc->local_addr)>>9, + le32_to_cpu(desc->transfer_size)); + dump_dmastat(card, control); + } else if (op_is_write(bio_op(bio)) && + le32_to_cpu(desc->local_addr) >> 9 == + card->init_size) { + card->init_size += le32_to_cpu(desc->transfer_size) >> 9; + if (card->init_size >> 1 >= card->mm_size) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory now initialised\n"); + set_userbit(card, MEMORY_INITIALIZED, 1); + } + } + if (bio != page->bio) { + bio->bi_next = return_bio; + return_bio = bio; + } + + if (last) + break; + } + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_OFF); + + if (card->check_batteries) { + card->check_batteries = 0; + check_batteries(card); + } + if (page->headcnt >= page->cnt) { + reset_page(page); + card->Active = -1; + activate(card); + } else { + /* haven't finished with this one yet */ + pr_debug("do some more\n"); + mm_start_io(card); + } + out_unlock: + spin_unlock(&card->lock); + + while (return_bio) { + struct bio *bio = return_bio; + + return_bio = bio->bi_next; + bio->bi_next = NULL; + bio_endio(bio); + } +} + +static void mm_unplug(struct blk_plug_cb *cb, bool from_schedule) +{ + struct cardinfo *card = cb->data; + + spin_lock_irq(&card->lock); + activate(card); + spin_unlock_irq(&card->lock); + kfree(cb); +} + +static int mm_check_plugged(struct cardinfo *card) +{ + return !!blk_check_plugged(mm_unplug, card, sizeof(struct blk_plug_cb)); +} + +static blk_qc_t mm_submit_bio(struct bio *bio) +{ + struct cardinfo *card = bio->bi_bdev->bd_disk->private_data; + + pr_debug("mm_make_request %llu %u\n", + (unsigned long long)bio->bi_iter.bi_sector, + bio->bi_iter.bi_size); + + blk_queue_split(&bio); + + spin_lock_irq(&card->lock); + *card->biotail = bio; + bio->bi_next = NULL; + card->biotail = &bio->bi_next; + if (op_is_sync(bio->bi_opf) || !mm_check_plugged(card)) + activate(card); + spin_unlock_irq(&card->lock); + + return BLK_QC_T_NONE; +} + +static irqreturn_t mm_interrupt(int irq, void *__card) +{ + struct cardinfo *card = (struct cardinfo *) __card; + unsigned int dma_status; + unsigned short cfg_status; + +HW_TRACE(0x30); + + dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL)); + + if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) { + /* interrupt wasn't for me ... */ + return IRQ_NONE; + } + + /* clear COMPLETION interrupts */ + if (card->flags & UM_FLAG_NO_BYTE_STATUS) + writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE), + card->csr_remap + DMA_STATUS_CTRL); + else + writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16, + card->csr_remap + DMA_STATUS_CTRL + 2); + + /* log errors and clear interrupt status */ + if (dma_status & DMASCR_ANY_ERR) { + unsigned int data_log1, data_log2; + unsigned int addr_log1, addr_log2; + unsigned char stat, count, syndrome, check; + + stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS); + + data_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG)); + data_log2 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG + 4)); + addr_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_ADDR_LOG)); + addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4); + + count = readb(card->csr_remap + ERROR_COUNT); + syndrome = readb(card->csr_remap + ERROR_SYNDROME); + check = readb(card->csr_remap + ERROR_CHECK); + + dump_dmastat(card, dma_status); + + if (stat & 0x01) + dev_printk(KERN_ERR, &card->dev->dev, + "Memory access error detected (err count %d)\n", + count); + if (stat & 0x02) + dev_printk(KERN_ERR, &card->dev->dev, + "Multi-bit EDC error\n"); + + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n", + addr_log2, addr_log1, data_log2, data_log1); + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Check 0x%02x, Fault Syndrome 0x%02x\n", + check, syndrome); + + writeb(0, card->csr_remap + ERROR_COUNT); + } + + if (dma_status & DMASCR_PARITY_ERR_REP) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR REPORTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_PARITY_ERR_DET) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR DETECTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_SYSTEM_ERR_SIG) { + dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_TARGET_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_MASTER_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + /* and process the DMA descriptors */ + card->dma_status = dma_status; + tasklet_schedule(&card->tasklet); + +HW_TRACE(0x36); + + return IRQ_HANDLED; +} + +/* + * If both batteries are good, no LED + * If either battery has been warned, solid LED + * If both batteries are bad, flash the LED quickly + * If either battery is bad, flash the LED semi quickly + */ +static void set_fault_to_battery_status(struct cardinfo *card) +{ + if (card->battery[0].good && card->battery[1].good) + set_led(card, LED_FAULT, LED_OFF); + else if (card->battery[0].warned || card->battery[1].warned) + set_led(card, LED_FAULT, LED_ON); + else if (!card->battery[0].good && !card->battery[1].good) + set_led(card, LED_FAULT, LED_FLASH_7_0); + else + set_led(card, LED_FAULT, LED_FLASH_3_5); +} + +static void init_battery_timer(void); + +static int check_battery(struct cardinfo *card, int battery, int status) +{ + if (status != card->battery[battery].good) { + card->battery[battery].good = !card->battery[battery].good; + card->battery[battery].last_change = jiffies; + + if (card->battery[battery].good) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now good\n", battery + 1); + card->battery[battery].warned = 0; + } else + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now FAILED\n", battery + 1); + + return 1; + } else if (!card->battery[battery].good && + !card->battery[battery].warned && + time_after_eq(jiffies, card->battery[battery].last_change + + (HZ * 60 * 60 * 5))) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d still FAILED after 5 hours\n", battery + 1); + card->battery[battery].warned = 1; + + return 1; + } + + return 0; +} + +static void check_batteries(struct cardinfo *card) +{ + /* NOTE: this must *never* be called while the card + * is doing (bus-to-card) DMA, or you will need the + * reset switch + */ + unsigned char status; + int ret1, ret2; + + status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + if (debug & DEBUG_BATTERY_POLLING) + dev_printk(KERN_DEBUG, &card->dev->dev, + "checking battery status, 1 = %s, 2 = %s\n", + (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK", + (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK"); + + ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE)); + ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE)); + + if (ret1 || ret2) + set_fault_to_battery_status(card); +} + +static void check_all_batteries(struct timer_list *unused) +{ + int i; + + for (i = 0; i < num_cards; i++) + if (!(cards[i].flags & UM_FLAG_NO_BATT)) { + struct cardinfo *card = &cards[i]; + spin_lock_bh(&card->lock); + if (card->Active >= 0) + card->check_batteries = 1; + else + check_batteries(card); + spin_unlock_bh(&card->lock); + } + + init_battery_timer(); +} + +static void init_battery_timer(void) +{ + timer_setup(&battery_timer, check_all_batteries, 0); + battery_timer.expires = jiffies + (HZ * 60); + add_timer(&battery_timer); +} + +static void del_battery_timer(void) +{ + del_timer(&battery_timer); +} + +/* + * Note no locks taken out here. In a worst case scenario, we could drop + * a chunk of system memory. But that should never happen, since validation + * happens at open or mount time, when locks are held. + * + * That's crap, since doing that while some partitions are opened + * or mounted will give you really nasty results. + */ +static int mm_revalidate(struct gendisk *disk) +{ + struct cardinfo *card = disk->private_data; + set_capacity(disk, card->mm_size << 1); + return 0; +} + +static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct cardinfo *card = bdev->bd_disk->private_data; + int size = card->mm_size * (1024 / MM_HARDSECT); + + /* + * get geometry: we have to fake one... trim the size to a + * multiple of 2048 (1M): tell we have 32 sectors, 64 heads, + * whatever cylinders. + */ + geo->heads = 64; + geo->sectors = 32; + geo->cylinders = size / (geo->heads * geo->sectors); + return 0; +} + +static const struct block_device_operations mm_fops = { + .owner = THIS_MODULE, + .submit_bio = mm_submit_bio, + .getgeo = mm_getgeo, + .revalidate_disk = mm_revalidate, +}; + +static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + int ret; + struct cardinfo *card = &cards[num_cards]; + unsigned char mem_present; + unsigned char batt_status; + unsigned int saved_bar, data; + unsigned long csr_base; + unsigned long csr_len; + int magic_number; + static int printed_version; + + if (!printed_version++) + printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n"); + + ret = pci_enable_device(dev); + if (ret) + return ret; + + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8); + pci_set_master(dev); + + card->dev = dev; + + csr_base = pci_resource_start(dev, 0); + csr_len = pci_resource_len(dev, 0); + if (!csr_base || !csr_len) + return -ENODEV; + + dev_printk(KERN_INFO, &dev->dev, + "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n"); + + if (dma_set_mask(&dev->dev, DMA_BIT_MASK(64)) && + dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) { + dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n"); + return -ENOMEM; + } + + ret = pci_request_regions(dev, DRIVER_NAME); + if (ret) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to request memory region\n"); + goto failed_req_csr; + } + + card->csr_remap = ioremap(csr_base, csr_len); + if (!card->csr_remap) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to remap memory region\n"); + ret = -ENOMEM; + + goto failed_remap_csr; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "CSR 0x%08lx -> 0x%p (0x%lx)\n", + csr_base, card->csr_remap, csr_len); + + switch (card->dev->device) { + case 0x5415: + card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG; + magic_number = 0x59; + break; + + case 0x5425: + card->flags |= UM_FLAG_NO_BYTE_STATUS; + magic_number = 0x5C; + break; + + case 0x6155: + card->flags |= UM_FLAG_NO_BYTE_STATUS | + UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT; + magic_number = 0x99; + break; + + default: + magic_number = 0x100; + break; + } + + if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) { + dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n"); + ret = -ENOMEM; + goto failed_magic; + } + + card->mm_pages[0].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[0].page_dma, GFP_KERNEL); + card->mm_pages[1].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[1].page_dma, GFP_KERNEL); + if (card->mm_pages[0].desc == NULL || + card->mm_pages[1].desc == NULL) { + dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n"); + ret = -ENOMEM; + goto failed_alloc; + } + reset_page(&card->mm_pages[0]); + reset_page(&card->mm_pages[1]); + card->Ready = 0; /* page 0 is ready */ + card->Active = -1; /* no page is active */ + card->bio = NULL; + card->biotail = &card->bio; + spin_lock_init(&card->lock); + + card->queue = blk_alloc_queue(NUMA_NO_NODE); + if (!card->queue) { + ret = -ENOMEM; + goto failed_alloc; + } + + tasklet_init(&card->tasklet, process_page, (unsigned long)card); + + card->check_batteries = 0; + + mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY); + switch (mem_present) { + case MEM_128_MB: + card->mm_size = 1024 * 128; + break; + case MEM_256_MB: + card->mm_size = 1024 * 256; + break; + case MEM_512_MB: + card->mm_size = 1024 * 512; + break; + case MEM_1_GB: + card->mm_size = 1024 * 1024; + break; + case MEM_2_GB: + card->mm_size = 1024 * 2048; + break; + default: + card->mm_size = 0; + break; + } + + /* Clear the LED's we control */ + set_led(card, LED_REMOVE, LED_OFF); + set_led(card, LED_FAULT, LED_OFF); + + batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + + card->battery[0].good = !(batt_status & BATTERY_1_FAILURE); + card->battery[1].good = !(batt_status & BATTERY_2_FAILURE); + card->battery[0].last_change = card->battery[1].last_change = jiffies; + + if (card->flags & UM_FLAG_NO_BATT) + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB\n", card->mm_size); + else { + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n", + card->mm_size, + batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled", + card->battery[0].good ? "OK" : "FAILURE", + batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled", + card->battery[1].good ? "OK" : "FAILURE"); + + set_fault_to_battery_status(card); + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar); + data = 0xffffffff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar); + data &= 0xfffffff0; + data = ~data; + data += 1; + + if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME, + card)) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to allocate IRQ\n"); + ret = -ENODEV; + goto failed_req_irq; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "Window size %d bytes, IRQ %d\n", data, dev->irq); + + pci_set_drvdata(dev, card); + + if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */ + pci_write_cmd = 0x07; /* then Memory Write command */ + + if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */ + unsigned short cfg_command; + pci_read_config_word(dev, PCI_COMMAND, &cfg_command); + cfg_command |= 0x10; /* Memory Write & Invalidate Enable */ + pci_write_config_word(dev, PCI_COMMAND, cfg_command); + } + pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24); + + num_cards++; + + if (!get_userbit(card, MEMORY_INITIALIZED)) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory NOT initialized. Consider over-writing whole device.\n"); + card->init_size = 0; + } else { + dev_printk(KERN_INFO, &card->dev->dev, + "memory already initialized\n"); + card->init_size = card->mm_size; + } + + /* Enable ECC */ + writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL); + + return 0; + + failed_req_irq: + failed_alloc: + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + failed_magic: + iounmap(card->csr_remap); + failed_remap_csr: + pci_release_regions(dev); + failed_req_csr: + + return ret; +} + +static void mm_pci_remove(struct pci_dev *dev) +{ + struct cardinfo *card = pci_get_drvdata(dev); + + tasklet_kill(&card->tasklet); + free_irq(dev->irq, card); + iounmap(card->csr_remap); + + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + blk_cleanup_queue(card->queue); + + pci_release_regions(dev); + pci_disable_device(dev); +} + +static const struct pci_device_id mm_pci_ids[] = { + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)}, + { + .vendor = 0x8086, + .device = 0xB555, + .subvendor = 0x1332, + .subdevice = 0x5460, + .class = 0x050000, + .class_mask = 0, + }, { /* end: all zeroes */ } +}; + +MODULE_DEVICE_TABLE(pci, mm_pci_ids); + +static struct pci_driver mm_pci_driver = { + .name = DRIVER_NAME, + .id_table = mm_pci_ids, + .probe = mm_pci_probe, + .remove = mm_pci_remove, +}; + +static int __init mm_init(void) +{ + int retval, i; + int err; + + retval = pci_register_driver(&mm_pci_driver); + if (retval) + return -ENOMEM; + + err = major_nr = register_blkdev(0, DRIVER_NAME); + if (err < 0) { + pci_unregister_driver(&mm_pci_driver); + return -EIO; + } + + for (i = 0; i < num_cards; i++) { + mm_gendisk[i] = alloc_disk(1 << MM_SHIFT); + if (!mm_gendisk[i]) + goto out; + } + + for (i = 0; i < num_cards; i++) { + struct gendisk *disk = mm_gendisk[i]; + sprintf(disk->disk_name, "umem%c", 'a'+i); + spin_lock_init(&cards[i].lock); + disk->major = major_nr; + disk->first_minor = i << MM_SHIFT; + disk->fops = &mm_fops; + disk->private_data = &cards[i]; + disk->queue = cards[i].queue; + set_capacity(disk, cards[i].mm_size << 1); + add_disk(disk); + } + + init_battery_timer(); + printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE); +/* printk("mm_init: Done. 10-19-01 9:00\n"); */ + return 0; + +out: + pci_unregister_driver(&mm_pci_driver); + unregister_blkdev(major_nr, DRIVER_NAME); + while (i--) + put_disk(mm_gendisk[i]); + return -ENOMEM; +} + +static void __exit mm_cleanup(void) +{ + int i; + + del_battery_timer(); + + for (i = 0; i < num_cards ; i++) { + del_gendisk(mm_gendisk[i]); + put_disk(mm_gendisk[i]); + } + + pci_unregister_driver(&mm_pci_driver); + + unregister_blkdev(major_nr, DRIVER_NAME); +} + +module_init(mm_init); +module_exit(mm_cleanup); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/block/umem.h b/drivers/block/umem.h new file mode 100644 index 0000000000000..58384978ff054 --- /dev/null +++ b/drivers/block/umem.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file contains defines for the + * Micro Memory MM5415 + * family PCI Memory Module with Battery Backup. + * + * Copyright Micro Memory INC 2001. All rights reserved. + */ + +#ifndef _DRIVERS_BLOCK_MM_H +#define _DRIVERS_BLOCK_MM_H + + +#define IRQ_TIMEOUT (1 * HZ) + +/* CSR register definition */ +#define MEMCTRLSTATUS_MAGIC 0x00 +#define MM_MAGIC_VALUE (unsigned char)0x59 + +#define MEMCTRLSTATUS_BATTERY 0x04 +#define BATTERY_1_DISABLED 0x01 +#define BATTERY_1_FAILURE 0x02 +#define BATTERY_2_DISABLED 0x04 +#define BATTERY_2_FAILURE 0x08 + +#define MEMCTRLSTATUS_MEMORY 0x07 +#define MEM_128_MB 0xfe +#define MEM_256_MB 0xfc +#define MEM_512_MB 0xf8 +#define MEM_1_GB 0xf0 +#define MEM_2_GB 0xe0 + +#define MEMCTRLCMD_LEDCTRL 0x08 +#define LED_REMOVE 2 +#define LED_FAULT 4 +#define LED_POWER 6 +#define LED_FLIP 255 +#define LED_OFF 0x00 +#define LED_ON 0x01 +#define LED_FLASH_3_5 0x02 +#define LED_FLASH_7_0 0x03 +#define LED_POWER_ON 0x00 +#define LED_POWER_OFF 0x01 +#define USER_BIT1 0x01 +#define USER_BIT2 0x02 + +#define MEMORY_INITIALIZED USER_BIT1 + +#define MEMCTRLCMD_ERRCTRL 0x0C +#define EDC_NONE_DEFAULT 0x00 +#define EDC_NONE 0x01 +#define EDC_STORE_READ 0x02 +#define EDC_STORE_CORRECT 0x03 + +#define MEMCTRLCMD_ERRCNT 0x0D +#define MEMCTRLCMD_ERRSTATUS 0x0E + +#define ERROR_DATA_LOG 0x20 +#define ERROR_ADDR_LOG 0x28 +#define ERROR_COUNT 0x3D +#define ERROR_SYNDROME 0x3E +#define ERROR_CHECK 0x3F + +#define DMA_PCI_ADDR 0x40 +#define DMA_LOCAL_ADDR 0x48 +#define DMA_TRANSFER_SIZE 0x50 +#define DMA_DESCRIPTOR_ADDR 0x58 +#define DMA_SEMAPHORE_ADDR 0x60 +#define DMA_STATUS_CTRL 0x68 +#define DMASCR_GO 0x00001 +#define DMASCR_TRANSFER_READ 0x00002 +#define DMASCR_CHAIN_EN 0x00004 +#define DMASCR_SEM_EN 0x00010 +#define DMASCR_DMA_COMP_EN 0x00020 +#define DMASCR_CHAIN_COMP_EN 0x00040 +#define DMASCR_ERR_INT_EN 0x00080 +#define DMASCR_PARITY_INT_EN 0x00100 +#define DMASCR_ANY_ERR 0x00800 +#define DMASCR_MBE_ERR 0x01000 +#define DMASCR_PARITY_ERR_REP 0x02000 +#define DMASCR_PARITY_ERR_DET 0x04000 +#define DMASCR_SYSTEM_ERR_SIG 0x08000 +#define DMASCR_TARGET_ABT 0x10000 +#define DMASCR_MASTER_ABT 0x20000 +#define DMASCR_DMA_COMPLETE 0x40000 +#define DMASCR_CHAIN_COMPLETE 0x80000 + +/* +3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE +READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA +TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE +TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS +(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, +AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING +DMA READ OPERATIONS. +*/ +#define DMASCR_READ 0x60000000 +#define DMASCR_READLINE 0xE0000000 +#define DMASCR_READMULTI 0xC0000000 + + +#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) +#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) + +#define WINDOWMAP_WINNUM 0x7B + +#define DMA_READ_FROM_HOST 0 +#define DMA_WRITE_TO_HOST 1 + +struct mm_dma_desc { + __le64 pci_addr; + __le64 local_addr; + __le32 transfer_size; + u32 zero1; + __le64 next_desc_addr; + __le64 sem_addr; + __le32 control_bits; + u32 zero2; + + dma_addr_t data_dma_handle; + + /* Copy of the bits */ + __le64 sem_control_bits; +} __attribute__((aligned(8))); + +/* bits for card->flags */ +#define UM_FLAG_DMA_IN_REGS 1 +#define UM_FLAG_NO_BYTE_STATUS 2 +#define UM_FLAG_NO_BATTREG 4 +#define UM_FLAG_NO_BATT 8 +#endif diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c new file mode 100644 index 0000000000000..eb8ef65778c35 --- /dev/null +++ b/drivers/block/xsysace.c @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Xilinx SystemACE device driver + * + * Copyright 2007 Secret Lab Technologies Ltd. + */ + +/* + * The SystemACE chip is designed to configure FPGAs by loading an FPGA + * bitstream from a file on a CF card and squirting it into FPGAs connected + * to the SystemACE JTAG chain. It also has the advantage of providing an + * MPU interface which can be used to control the FPGA configuration process + * and to use the attached CF card for general purpose storage. + * + * This driver is a block device driver for the SystemACE. + * + * Initialization: + * The driver registers itself as a platform_device driver at module + * load time. The platform bus will take care of calling the + * ace_probe() method for all SystemACE instances in the system. Any + * number of SystemACE instances are supported. ace_probe() calls + * ace_setup() which initialized all data structures, reads the CF + * id structure and registers the device. + * + * Processing: + * Just about all of the heavy lifting in this driver is performed by + * a Finite State Machine (FSM). The driver needs to wait on a number + * of events; some raised by interrupts, some which need to be polled + * for. Describing all of the behaviour in a FSM seems to be the + * easiest way to keep the complexity low and make it easy to + * understand what the driver is doing. If the block ops or the + * request function need to interact with the hardware, then they + * simply need to flag the request and kick of FSM processing. + * + * The FSM itself is atomic-safe code which can be run from any + * context. The general process flow is: + * 1. obtain the ace->lock spinlock. + * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is + * cleared. + * 3. release the lock. + * + * Individual states do not sleep in any way. If a condition needs to + * be waited for then the state much clear the fsm_continue flag and + * either schedule the FSM to be run again at a later time, or expect + * an interrupt to call the FSM when the desired condition is met. + * + * In normal operation, the FSM is processed at interrupt context + * either when the driver's tasklet is scheduled, or when an irq is + * raised by the hardware. The tasklet can be scheduled at any time. + * The request method in particular schedules the tasklet when a new + * request has been indicated by the block layer. Once started, the + * FSM proceeds as far as it can processing the request until it + * needs on a hardware event. At this point, it must yield execution. + * + * A state has two options when yielding execution: + * 1. ace_fsm_yield() + * - Call if need to poll for event. + * - clears the fsm_continue flag to exit the processing loop + * - reschedules the tasklet to run again as soon as possible + * 2. ace_fsm_yieldirq() + * - Call if an irq is expected from the HW + * - clears the fsm_continue flag to exit the processing loop + * - does not reschedule the tasklet so the FSM will not be processed + * again until an irq is received. + * After calling a yield function, the state must return control back + * to the FSM main loop. + * + * Additionally, the driver maintains a kernel timer which can process + * the FSM. If the FSM gets stalled, typically due to a missed + * interrupt, then the kernel timer will expire and the driver can + * continue where it left off. + * + * To Do: + * - Add FPGA configuration control interface. + * - Request major number from lanana + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_OF) +#include +#include +#include +#endif + +MODULE_AUTHOR("Grant Likely "); +MODULE_DESCRIPTION("Xilinx SystemACE device driver"); +MODULE_LICENSE("GPL"); + +/* SystemACE register definitions */ +#define ACE_BUSMODE (0x00) + +#define ACE_STATUS (0x04) +#define ACE_STATUS_CFGLOCK (0x00000001) +#define ACE_STATUS_MPULOCK (0x00000002) +#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ +#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ +#define ACE_STATUS_CFDETECT (0x00000010) +#define ACE_STATUS_DATABUFRDY (0x00000020) +#define ACE_STATUS_DATABUFMODE (0x00000040) +#define ACE_STATUS_CFGDONE (0x00000080) +#define ACE_STATUS_RDYFORCFCMD (0x00000100) +#define ACE_STATUS_CFGMODEPIN (0x00000200) +#define ACE_STATUS_CFGADDR_MASK (0x0000e000) +#define ACE_STATUS_CFBSY (0x00020000) +#define ACE_STATUS_CFRDY (0x00040000) +#define ACE_STATUS_CFDWF (0x00080000) +#define ACE_STATUS_CFDSC (0x00100000) +#define ACE_STATUS_CFDRQ (0x00200000) +#define ACE_STATUS_CFCORR (0x00400000) +#define ACE_STATUS_CFERR (0x00800000) + +#define ACE_ERROR (0x08) +#define ACE_CFGLBA (0x0c) +#define ACE_MPULBA (0x10) + +#define ACE_SECCNTCMD (0x14) +#define ACE_SECCNTCMD_RESET (0x0100) +#define ACE_SECCNTCMD_IDENTIFY (0x0200) +#define ACE_SECCNTCMD_READ_DATA (0x0300) +#define ACE_SECCNTCMD_WRITE_DATA (0x0400) +#define ACE_SECCNTCMD_ABORT (0x0600) + +#define ACE_VERSION (0x16) +#define ACE_VERSION_REVISION_MASK (0x00FF) +#define ACE_VERSION_MINOR_MASK (0x0F00) +#define ACE_VERSION_MAJOR_MASK (0xF000) + +#define ACE_CTRL (0x18) +#define ACE_CTRL_FORCELOCKREQ (0x0001) +#define ACE_CTRL_LOCKREQ (0x0002) +#define ACE_CTRL_FORCECFGADDR (0x0004) +#define ACE_CTRL_FORCECFGMODE (0x0008) +#define ACE_CTRL_CFGMODE (0x0010) +#define ACE_CTRL_CFGSTART (0x0020) +#define ACE_CTRL_CFGSEL (0x0040) +#define ACE_CTRL_CFGRESET (0x0080) +#define ACE_CTRL_DATABUFRDYIRQ (0x0100) +#define ACE_CTRL_ERRORIRQ (0x0200) +#define ACE_CTRL_CFGDONEIRQ (0x0400) +#define ACE_CTRL_RESETIRQ (0x0800) +#define ACE_CTRL_CFGPROG (0x1000) +#define ACE_CTRL_CFGADDR_MASK (0xe000) + +#define ACE_FATSTAT (0x1c) + +#define ACE_NUM_MINORS 16 +#define ACE_SECTOR_SIZE (512) +#define ACE_FIFO_SIZE (32) +#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) + +#define ACE_BUS_WIDTH_8 0 +#define ACE_BUS_WIDTH_16 1 + +struct ace_reg_ops; + +struct ace_device { + /* driver state data */ + int id; + int media_change; + int users; + struct list_head list; + + /* finite state machine data */ + struct tasklet_struct fsm_tasklet; + uint fsm_task; /* Current activity (ACE_TASK_*) */ + uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ + uint fsm_continue_flag; /* cleared to exit FSM mainloop */ + uint fsm_iter_num; + struct timer_list stall_timer; + + /* Transfer state/result, use for both id and block request */ + struct request *req; /* request being processed */ + void *data_ptr; /* pointer to I/O buffer */ + int data_count; /* number of buffers remaining */ + int data_result; /* Result of transfer; 0 := success */ + + int id_req_count; /* count of id requests */ + int id_result; + struct completion id_completion; /* used when id req finishes */ + int in_irq; + + /* Details of hardware device */ + resource_size_t physaddr; + void __iomem *baseaddr; + int irq; + int bus_width; /* 0 := 8 bit; 1 := 16 bit */ + struct ace_reg_ops *reg_ops; + int lock_count; + + /* Block device data structures */ + spinlock_t lock; + struct device *dev; + struct request_queue *queue; + struct gendisk *gd; + struct blk_mq_tag_set tag_set; + struct list_head rq_list; + + /* Inserted CF card parameters */ + u16 cf_id[ATA_ID_WORDS]; +}; + +static DEFINE_MUTEX(xsysace_mutex); +static int ace_major; + +/* --------------------------------------------------------------------- + * Low level register access + */ + +struct ace_reg_ops { + u16(*in) (struct ace_device * ace, int reg); + void (*out) (struct ace_device * ace, int reg, u16 val); + void (*datain) (struct ace_device * ace); + void (*dataout) (struct ace_device * ace); +}; + +/* 8 Bit bus width */ +static u16 ace_in_8(struct ace_device *ace, int reg) +{ + void __iomem *r = ace->baseaddr + reg; + return in_8(r) | (in_8(r + 1) << 8); +} + +static void ace_out_8(struct ace_device *ace, int reg, u16 val) +{ + void __iomem *r = ace->baseaddr + reg; + out_8(r, val); + out_8(r + 1, val >> 8); +} + +static void ace_datain_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *dst = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + *dst++ = in_8(r++); + ace->data_ptr = dst; +} + +static void ace_dataout_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *src = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + out_8(r++, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_8_ops = { + .in = ace_in_8, + .out = ace_out_8, + .datain = ace_datain_8, + .dataout = ace_dataout_8, +}; + +/* 16 bit big endian bus attachment */ +static u16 ace_in_be16(struct ace_device *ace, int reg) +{ + return in_be16(ace->baseaddr + reg); +} + +static void ace_out_be16(struct ace_device *ace, int reg, u16 val) +{ + out_be16(ace->baseaddr + reg, val); +} + +static void ace_datain_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_le16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_le16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +/* 16 bit little endian bus attachment */ +static u16 ace_in_le16(struct ace_device *ace, int reg) +{ + return in_le16(ace->baseaddr + reg); +} + +static void ace_out_le16(struct ace_device *ace, int reg, u16 val) +{ + out_le16(ace->baseaddr + reg, val); +} + +static void ace_datain_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_be16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_be16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_be16_ops = { + .in = ace_in_be16, + .out = ace_out_be16, + .datain = ace_datain_be16, + .dataout = ace_dataout_be16, +}; + +static struct ace_reg_ops ace_reg_le16_ops = { + .in = ace_in_le16, + .out = ace_out_le16, + .datain = ace_datain_le16, + .dataout = ace_dataout_le16, +}; + +static inline u16 ace_in(struct ace_device *ace, int reg) +{ + return ace->reg_ops->in(ace, reg); +} + +static inline u32 ace_in32(struct ace_device *ace, int reg) +{ + return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); +} + +static inline void ace_out(struct ace_device *ace, int reg, u16 val) +{ + ace->reg_ops->out(ace, reg, val); +} + +static inline void ace_out32(struct ace_device *ace, int reg, u32 val) +{ + ace_out(ace, reg, val); + ace_out(ace, reg + 2, val >> 16); +} + +/* --------------------------------------------------------------------- + * Debug support functions + */ + +#if defined(DEBUG) +static void ace_dump_mem(void *base, int len) +{ + const char *ptr = base; + int i, j; + + for (i = 0; i < len; i += 16) { + printk(KERN_INFO "%.8x:", i); + for (j = 0; j < 16; j++) { + if (!(j % 4)) + printk(" "); + printk("%.2x", ptr[i + j]); + } + printk(" "); + for (j = 0; j < 16; j++) + printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); + printk("\n"); + } +} +#else +static inline void ace_dump_mem(void *base, int len) +{ +} +#endif + +static void ace_dump_regs(struct ace_device *ace) +{ + dev_info(ace->dev, + " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" + " status:%.8x mpu_lba:%.8x busmode:%4x\n" + " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", + ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD), + ace_in(ace, ACE_VERSION), + ace_in32(ace, ACE_STATUS), + ace_in32(ace, ACE_MPULBA), + ace_in(ace, ACE_BUSMODE), + ace_in32(ace, ACE_ERROR), + ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); +} + +static void ace_fix_driveid(u16 *id) +{ +#if defined(__BIG_ENDIAN) + int i; + + /* All half words have wrong byte order; swap the bytes */ + for (i = 0; i < ATA_ID_WORDS; i++, id++) + *id = le16_to_cpu(*id); +#endif +} + +/* --------------------------------------------------------------------- + * Finite State Machine (FSM) implementation + */ + +/* FSM tasks; used to direct state transitions */ +#define ACE_TASK_IDLE 0 +#define ACE_TASK_IDENTIFY 1 +#define ACE_TASK_READ 2 +#define ACE_TASK_WRITE 3 +#define ACE_FSM_NUM_TASKS 4 + +/* FSM state definitions */ +#define ACE_FSM_STATE_IDLE 0 +#define ACE_FSM_STATE_REQ_LOCK 1 +#define ACE_FSM_STATE_WAIT_LOCK 2 +#define ACE_FSM_STATE_WAIT_CFREADY 3 +#define ACE_FSM_STATE_IDENTIFY_PREPARE 4 +#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 +#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 +#define ACE_FSM_STATE_REQ_PREPARE 7 +#define ACE_FSM_STATE_REQ_TRANSFER 8 +#define ACE_FSM_STATE_REQ_COMPLETE 9 +#define ACE_FSM_STATE_ERROR 10 +#define ACE_FSM_NUM_STATES 11 + +/* Set flag to exit FSM loop and reschedule tasklet */ +static inline void ace_fsm_yieldpoll(struct ace_device *ace) +{ + tasklet_schedule(&ace->fsm_tasklet); + ace->fsm_continue_flag = 0; +} + +static inline void ace_fsm_yield(struct ace_device *ace) +{ + dev_dbg(ace->dev, "%s()\n", __func__); + ace_fsm_yieldpoll(ace); +} + +/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ +static inline void ace_fsm_yieldirq(struct ace_device *ace) +{ + dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); + + if (ace->irq > 0) + ace->fsm_continue_flag = 0; + else + ace_fsm_yieldpoll(ace); +} + +static bool ace_has_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + + return !list_empty(&ace->rq_list); +} + +/* Get the next read/write request; ending requests that we don't handle */ +static struct request *ace_get_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + struct request *rq; + + rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist); + if (rq) { + list_del_init(&rq->queuelist); + blk_mq_start_request(rq); + } + + return NULL; +} + +static void ace_fsm_dostate(struct ace_device *ace) +{ + struct request *req; + u32 status; + u16 val; + int count; + +#if defined(DEBUG) + dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", + ace->fsm_state, ace->id_req_count); +#endif + + /* Verify that there is actually a CF in the slot. If not, then + * bail out back to the idle state and wake up all the waiters */ + status = ace_in32(ace, ACE_STATUS); + if ((status & ACE_STATUS_CFDETECT) == 0) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_info(ace->dev, "No CF in slot\n"); + + /* Drop all in-flight and pending requests */ + if (ace->req) { + blk_mq_end_request(ace->req, BLK_STS_IOERR); + ace->req = NULL; + } + while ((req = ace_get_next_request(ace->queue)) != NULL) + blk_mq_end_request(req, BLK_STS_IOERR); + + /* Drop back to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = -EIO; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + } + + switch (ace->fsm_state) { + case ACE_FSM_STATE_IDLE: + /* See if there is anything to do */ + if (ace->id_req_count || ace_has_next_request(ace->queue)) { + ace->fsm_iter_num++; + ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; + mod_timer(&ace->stall_timer, jiffies + HZ); + if (!timer_pending(&ace->stall_timer)) + add_timer(&ace->stall_timer); + break; + } + del_timer(&ace->stall_timer); + ace->fsm_continue_flag = 0; + break; + + case ACE_FSM_STATE_REQ_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* Already have the lock, jump to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* Request the lock */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); + ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; + break; + + case ACE_FSM_STATE_WAIT_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* got the lock; move to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* wait a bit for the lock */ + ace_fsm_yield(ace); + break; + + case ACE_FSM_STATE_WAIT_CFREADY: + status = ace_in32(ace, ACE_STATUS); + if (!(status & ACE_STATUS_RDYFORCFCMD) || + (status & ACE_STATUS_CFBSY)) { + /* CF card isn't ready; it needs to be polled */ + ace_fsm_yield(ace); + break; + } + + /* Device is ready for command; determine what to do next */ + if (ace->id_req_count) + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; + else + ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; + break; + + case ACE_FSM_STATE_IDENTIFY_PREPARE: + /* Send identify command */ + ace->fsm_task = ACE_TASK_IDENTIFY; + ace->data_ptr = ace->cf_id; + ace->data_count = ACE_BUF_PER_SECTOR; + ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* irq handler takes over from this point; wait for the + * transfer to complete */ + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; + ace_fsm_yieldirq(ace); + break; + + case ACE_FSM_STATE_IDENTIFY_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", + ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + ace_fsm_yield(ace); + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + ace_fsm_yield(ace); + break; + } + + /* Transfer the next buffer */ + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* transfer finished; kick state machine */ + dev_dbg(ace->dev, "identify finished\n"); + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; + break; + + case ACE_FSM_STATE_IDENTIFY_COMPLETE: + ace_fix_driveid(ace->cf_id); + ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */ + + if (ace->data_result) { + /* Error occurred, disable the disk */ + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_err(ace->dev, "error fetching CF id (%i)\n", + ace->data_result); + } else { + ace->media_change = 0; + + /* Record disk parameters */ + set_capacity(ace->gd, + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + dev_info(ace->dev, "capacity: %i sectors\n", + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + } + + /* We're done, drop to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = ace->data_result; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + break; + + case ACE_FSM_STATE_REQ_PREPARE: + req = ace_get_next_request(ace->queue); + if (!req) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } + + /* Okay, it's a data request, set it up for transfer */ + dev_dbg(ace->dev, + "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n", + (unsigned long long)blk_rq_pos(req), + blk_rq_sectors(req), blk_rq_cur_sectors(req), + rq_data_dir(req)); + + ace->req = req; + ace->data_ptr = bio_data(req->bio); + ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR; + ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF); + + count = blk_rq_sectors(req); + if (rq_data_dir(req)) { + /* Kick off write request */ + dev_dbg(ace->dev, "write data\n"); + ace->fsm_task = ACE_TASK_WRITE; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_WRITE_DATA); + } else { + /* Kick off read request */ + dev_dbg(ace->dev, "read data\n"); + ace->fsm_task = ACE_TASK_READ; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_READ_DATA); + } + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* Move to the transfer state. The systemace will raise + * an interrupt once there is something to do + */ + ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; + if (ace->fsm_task == ACE_TASK_READ) + ace_fsm_yieldirq(ace); /* wait for data ready */ + break; + + case ACE_FSM_STATE_REQ_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, + "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yield(ace); /* need to poll CFBSY bit */ + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + dev_dbg(ace->dev, + "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yieldirq(ace); + break; + } + + /* Transfer the next buffer */ + if (ace->fsm_task == ACE_TASK_WRITE) + ace->reg_ops->dataout(ace); + else + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* bio finished; is there another one? */ + if (blk_update_request(ace->req, BLK_STS_OK, + blk_rq_cur_bytes(ace->req))) { + /* dev_dbg(ace->dev, "next block; h=%u c=%u\n", + * blk_rq_sectors(ace->req), + * blk_rq_cur_sectors(ace->req)); + */ + ace->data_ptr = bio_data(ace->req->bio); + ace->data_count = blk_rq_cur_sectors(ace->req) * 16; + ace_fsm_yieldirq(ace); + break; + } + + ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; + break; + + case ACE_FSM_STATE_REQ_COMPLETE: + ace->req = NULL; + + /* Finished request; go to idle state */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + + default: + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } +} + +static void ace_fsm_tasklet(unsigned long data) +{ + struct ace_device *ace = (void *)data; + unsigned long flags; + + spin_lock_irqsave(&ace->lock, flags); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +static void ace_stall_timer(struct timer_list *t) +{ + struct ace_device *ace = from_timer(ace, t, stall_timer); + unsigned long flags; + + dev_warn(ace->dev, + "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", + ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + spin_lock_irqsave(&ace->lock, flags); + + /* Rearm the stall timer *before* entering FSM (which may then + * delete the timer) */ + mod_timer(&ace->stall_timer, jiffies + HZ); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +/* --------------------------------------------------------------------- + * Interrupt handling routines + */ +static int ace_interrupt_checkstate(struct ace_device *ace) +{ + u32 sreg = ace_in32(ace, ACE_STATUS); + u16 creg = ace_in(ace, ACE_CTRL); + + /* Check for error occurrence */ + if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && + (creg & ACE_CTRL_ERRORIRQ)) { + dev_err(ace->dev, "transfer failure\n"); + ace_dump_regs(ace); + return -EIO; + } + + return 0; +} + +static irqreturn_t ace_interrupt(int irq, void *dev_id) +{ + u16 creg; + struct ace_device *ace = dev_id; + + /* be safe and get the lock */ + spin_lock(&ace->lock); + ace->in_irq = 1; + + /* clear the interrupt */ + creg = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); + ace_out(ace, ACE_CTRL, creg); + + /* check for IO failures */ + if (ace_interrupt_checkstate(ace)) + ace->data_result = -EIO; + + if (ace->fsm_task == 0) { + dev_err(ace->dev, + "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", + ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD)); + dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", + ace->fsm_task, ace->fsm_state, ace->data_count); + } + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + /* done with interrupt; drop the lock */ + ace->in_irq = 0; + spin_unlock(&ace->lock); + + return IRQ_HANDLED; +} + +/* --------------------------------------------------------------------- + * Block ops + */ +static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx, + const struct blk_mq_queue_data *bd) +{ + struct ace_device *ace = hctx->queue->queuedata; + struct request *req = bd->rq; + + if (blk_rq_is_passthrough(req)) { + blk_mq_start_request(req); + return BLK_STS_IOERR; + } + + spin_lock_irq(&ace->lock); + list_add_tail(&req->queuelist, &ace->rq_list); + spin_unlock_irq(&ace->lock); + + tasklet_schedule(&ace->fsm_tasklet); + return BLK_STS_OK; +} + +static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing) +{ + struct ace_device *ace = gd->private_data; + dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change); + + return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0; +} + +static void ace_media_changed(struct ace_device *ace) +{ + unsigned long flags; + + dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); + + spin_lock_irqsave(&ace->lock, flags); + ace->id_req_count++; + spin_unlock_irqrestore(&ace->lock, flags); + + tasklet_schedule(&ace->fsm_tasklet); + wait_for_completion(&ace->id_completion); + + dev_dbg(ace->dev, "revalidate complete\n"); +} + +static int ace_open(struct block_device *bdev, fmode_t mode) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + unsigned long flags; + + dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users++; + spin_unlock_irqrestore(&ace->lock, flags); + + if (bdev_check_media_change(bdev) && ace->media_change) + ace_media_changed(ace); + mutex_unlock(&xsysace_mutex); + + return 0; +} + +static void ace_release(struct gendisk *disk, fmode_t mode) +{ + struct ace_device *ace = disk->private_data; + unsigned long flags; + u16 val; + + dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users--; + if (ace->users == 0) { + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); + } + spin_unlock_irqrestore(&ace->lock, flags); + mutex_unlock(&xsysace_mutex); +} + +static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + u16 *cf_id = ace->cf_id; + + dev_dbg(ace->dev, "ace_getgeo()\n"); + + geo->heads = cf_id[ATA_ID_HEADS]; + geo->sectors = cf_id[ATA_ID_SECTORS]; + geo->cylinders = cf_id[ATA_ID_CYLS]; + + return 0; +} + +static const struct block_device_operations ace_fops = { + .owner = THIS_MODULE, + .open = ace_open, + .release = ace_release, + .check_events = ace_check_events, + .getgeo = ace_getgeo, +}; + +static const struct blk_mq_ops ace_mq_ops = { + .queue_rq = ace_queue_rq, +}; + +/* -------------------------------------------------------------------- + * SystemACE device setup/teardown code + */ +static int ace_setup(struct ace_device *ace) +{ + u16 version; + u16 val; + int rc; + + dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); + dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", + (unsigned long long)ace->physaddr, ace->irq); + + spin_lock_init(&ace->lock); + init_completion(&ace->id_completion); + INIT_LIST_HEAD(&ace->rq_list); + + /* + * Map the device + */ + ace->baseaddr = ioremap(ace->physaddr, 0x80); + if (!ace->baseaddr) + goto err_ioremap; + + /* + * Initialize the state machine tasklet and stall timer + */ + tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); + timer_setup(&ace->stall_timer, ace_stall_timer, 0); + + /* + * Initialize the request queue + */ + ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2, + BLK_MQ_F_SHOULD_MERGE); + if (IS_ERR(ace->queue)) { + rc = PTR_ERR(ace->queue); + ace->queue = NULL; + goto err_blk_initq; + } + ace->queue->queuedata = ace; + + blk_queue_logical_block_size(ace->queue, 512); + blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH); + + /* + * Allocate and initialize GD structure + */ + ace->gd = alloc_disk(ACE_NUM_MINORS); + if (!ace->gd) + goto err_alloc_disk; + + ace->gd->major = ace_major; + ace->gd->first_minor = ace->id * ACE_NUM_MINORS; + ace->gd->fops = &ace_fops; + ace->gd->events = DISK_EVENT_MEDIA_CHANGE; + ace->gd->queue = ace->queue; + ace->gd->private_data = ace; + snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); + + /* set bus width */ + if (ace->bus_width == ACE_BUS_WIDTH_16) { + /* 0x0101 should work regardless of endianess */ + ace_out_le16(ace, ACE_BUSMODE, 0x0101); + + /* read it back to determine endianess */ + if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) + ace->reg_ops = &ace_reg_le16_ops; + else + ace->reg_ops = &ace_reg_be16_ops; + } else { + ace_out_8(ace, ACE_BUSMODE, 0x00); + ace->reg_ops = &ace_reg_8_ops; + } + + /* Make sure version register is sane */ + version = ace_in(ace, ACE_VERSION); + if ((version == 0) || (version == 0xFFFF)) + goto err_read; + + /* Put sysace in a sane state by clearing most control reg bits */ + ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | + ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); + + /* Now we can hook up the irq handler */ + if (ace->irq > 0) { + rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); + if (rc) { + /* Failure - fall back to polled mode */ + dev_err(ace->dev, "request_irq failed\n"); + ace->irq = rc; + } + } + + /* Enable interrupts */ + val = ace_in(ace, ACE_CTRL); + val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; + ace_out(ace, ACE_CTRL, val); + + /* Print the identification */ + dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", + (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); + dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", + (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); + + ace->media_change = 1; + ace_media_changed(ace); + + /* Make the sysace device 'live' */ + add_disk(ace->gd); + + return 0; + +err_read: + /* prevent double queue cleanup */ + ace->gd->queue = NULL; + put_disk(ace->gd); +err_alloc_disk: + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); +err_blk_initq: + iounmap(ace->baseaddr); +err_ioremap: + dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", + (unsigned long long) ace->physaddr); + return -ENOMEM; +} + +static void ace_teardown(struct ace_device *ace) +{ + if (ace->gd) { + del_gendisk(ace->gd); + put_disk(ace->gd); + } + + if (ace->queue) { + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); + } + + tasklet_kill(&ace->fsm_tasklet); + + if (ace->irq > 0) + free_irq(ace->irq, ace); + + iounmap(ace->baseaddr); +} + +static int ace_alloc(struct device *dev, int id, resource_size_t physaddr, + int irq, int bus_width) +{ + struct ace_device *ace; + int rc; + dev_dbg(dev, "ace_alloc(%p)\n", dev); + + /* Allocate and initialize the ace device structure */ + ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); + if (!ace) { + rc = -ENOMEM; + goto err_alloc; + } + + ace->dev = dev; + ace->id = id; + ace->physaddr = physaddr; + ace->irq = irq; + ace->bus_width = bus_width; + + /* Call the setup code */ + rc = ace_setup(ace); + if (rc) + goto err_setup; + + dev_set_drvdata(dev, ace); + return 0; + +err_setup: + dev_set_drvdata(dev, NULL); + kfree(ace); +err_alloc: + dev_err(dev, "could not initialize device, err=%i\n", rc); + return rc; +} + +static void ace_free(struct device *dev) +{ + struct ace_device *ace = dev_get_drvdata(dev); + dev_dbg(dev, "ace_free(%p)\n", dev); + + if (ace) { + ace_teardown(ace); + dev_set_drvdata(dev, NULL); + kfree(ace); + } +} + +/* --------------------------------------------------------------------- + * Platform Bus Support + */ + +static int ace_probe(struct platform_device *dev) +{ + int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ + resource_size_t physaddr; + struct resource *res; + u32 id = dev->id; + int irq; + int i; + + dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); + + /* device id and bus width */ + if (of_property_read_u32(dev->dev.of_node, "port-number", &id)) + id = 0; + if (of_find_property(dev->dev.of_node, "8-bit", NULL)) + bus_width = ACE_BUS_WIDTH_8; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + physaddr = res->start; + if (!physaddr) + return -ENODEV; + + irq = platform_get_irq_optional(dev, 0); + + /* Call the bus-independent setup code */ + return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); +} + +/* + * Platform bus remove() method + */ +static int ace_remove(struct platform_device *dev) +{ + ace_free(&dev->dev); + return 0; +} + +#if defined(CONFIG_OF) +/* Match table for of_platform binding */ +static const struct of_device_id ace_of_match[] = { + { .compatible = "xlnx,opb-sysace-1.00.b", }, + { .compatible = "xlnx,opb-sysace-1.00.c", }, + { .compatible = "xlnx,xps-sysace-1.00.a", }, + { .compatible = "xlnx,sysace", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ace_of_match); +#else /* CONFIG_OF */ +#define ace_of_match NULL +#endif /* CONFIG_OF */ + +static struct platform_driver ace_platform_driver = { + .probe = ace_probe, + .remove = ace_remove, + .driver = { + .name = "xsysace", + .of_match_table = ace_of_match, + }, +}; + +/* --------------------------------------------------------------------- + * Module init/exit routines + */ +static int __init ace_init(void) +{ + int rc; + + ace_major = register_blkdev(ace_major, "xsysace"); + if (ace_major <= 0) { + rc = -ENOMEM; + goto err_blk; + } + + rc = platform_driver_register(&ace_platform_driver); + if (rc) + goto err_plat; + + pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); + return 0; + +err_plat: + unregister_blkdev(ace_major, "xsysace"); +err_blk: + printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); + return rc; +} +module_init(ace_init); + +static void __exit ace_exit(void) +{ + pr_debug("Unregistering Xilinx SystemACE driver\n"); + platform_driver_unregister(&ace_platform_driver); + unregister_blkdev(ace_major, "xsysace"); +} +module_exit(ace_exit); diff --git a/drivers/crypto/tegra/tegra-se-main.c b/drivers/crypto/tegra/tegra-se-main.c index 7237f14eaf5ae..4e7115b247e7f 100644 --- a/drivers/crypto/tegra/tegra-se-main.c +++ b/drivers/crypto/tegra/tegra-se-main.c @@ -401,11 +401,9 @@ static int tegra_se_host1x_probe(struct host1x_device *dev) return host1x_device_init(dev); } -static int tegra_se_host1x_remove(struct host1x_device *dev) +static void tegra_se_host1x_remove(struct host1x_device *dev) { host1x_device_exit(dev); - - return 0; } static struct host1x_driver tegra_se_host1x_driver = { diff --git a/drivers/dma-buf/Kconfig b/drivers/dma-buf/Kconfig index b46eb8a552d7b..012d22e941d6f 100644 --- a/drivers/dma-buf/Kconfig +++ b/drivers/dma-buf/Kconfig @@ -55,7 +55,7 @@ config DMABUF_MOVE_NOTIFY config DMABUF_DEBUG bool "DMA-BUF debug checks" depends on DMA_SHARED_BUFFER - default y if DMA_API_DEBUG + default y if DEBUG help This option enables additional checks for DMA-BUF importers and exporters. Specifically it validates that importers do not peek at the @@ -75,21 +75,6 @@ menuconfig DMABUF_HEAPS allows userspace to allocate dma-bufs that can be shared between drivers. -menuconfig DMABUF_SYSFS_STATS - bool "DMA-BUF sysfs statistics (DEPRECATED)" - depends on DMA_SHARED_BUFFER - help - Choose this option to enable DMA-BUF sysfs statistics - in location /sys/kernel/dmabuf/buffers. - - /sys/kernel/dmabuf/buffers/ will contain - statistics for the DMA-BUF with the unique inode number - . - - This option is deprecated and should sooner or later be removed. - Android is the only user of this and it turned out that this resulted - in quite some performance problems. - source "drivers/dma-buf/heaps/Kconfig" endmenu diff --git a/drivers/dma-buf/Makefile b/drivers/dma-buf/Makefile index 2008fb7481b35..7a85565d906ba 100644 --- a/drivers/dma-buf/Makefile +++ b/drivers/dma-buf/Makefile @@ -6,7 +6,6 @@ obj-$(CONFIG_DMABUF_HEAPS) += heaps/ obj-$(CONFIG_SYNC_FILE) += sync_file.o obj-$(CONFIG_SW_SYNC) += sw_sync.o sync_debug.o obj-$(CONFIG_UDMABUF) += udmabuf.o -obj-$(CONFIG_DMABUF_SYSFS_STATS) += dma-buf-sysfs-stats.o dmabuf_selftests-y := \ selftest.o \ diff --git a/drivers/dma-buf/dma-buf-sysfs-stats.c b/drivers/dma-buf/dma-buf-sysfs-stats.c deleted file mode 100644 index b5b62e40ccc17..0000000000000 --- a/drivers/dma-buf/dma-buf-sysfs-stats.c +++ /dev/null @@ -1,202 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * DMA-BUF sysfs statistics. - * - * Copyright (C) 2021 Google LLC. - */ - -#include -#include -#include -#include -#include -#include - -#include "dma-buf-sysfs-stats.h" - -#define to_dma_buf_entry_from_kobj(x) container_of(x, struct dma_buf_sysfs_entry, kobj) - -/** - * DOC: overview - * - * ``/sys/kernel/debug/dma_buf/bufinfo`` provides an overview of every DMA-BUF - * in the system. However, since debugfs is not safe to be mounted in - * production, procfs and sysfs can be used to gather DMA-BUF statistics on - * production systems. - * - * The ``/proc//fdinfo/`` files in procfs can be used to gather - * information about DMA-BUF fds. Detailed documentation about the interface - * is present in Documentation/filesystems/proc.rst. - * - * Unfortunately, the existing procfs interfaces can only provide information - * about the DMA-BUFs for which processes hold fds or have the buffers mmapped - * into their address space. This necessitated the creation of the DMA-BUF sysfs - * statistics interface to provide per-buffer information on production systems. - * - * The interface at ``/sys/kernel/dmabuf/buffers`` exposes information about - * every DMA-BUF when ``CONFIG_DMABUF_SYSFS_STATS`` is enabled. - * - * The following stats are exposed by the interface: - * - * * ``/sys/kernel/dmabuf/buffers//exporter_name`` - * * ``/sys/kernel/dmabuf/buffers//size`` - * - * The information in the interface can also be used to derive per-exporter - * statistics. The data from the interface can be gathered on error conditions - * or other important events to provide a snapshot of DMA-BUF usage. - * It can also be collected periodically by telemetry to monitor various metrics. - * - * Detailed documentation about the interface is present in - * Documentation/ABI/testing/sysfs-kernel-dmabuf-buffers. - */ - -struct dma_buf_stats_attribute { - struct attribute attr; - ssize_t (*show)(struct dma_buf *dmabuf, - struct dma_buf_stats_attribute *attr, char *buf); -}; -#define to_dma_buf_stats_attr(x) container_of(x, struct dma_buf_stats_attribute, attr) - -static ssize_t dma_buf_stats_attribute_show(struct kobject *kobj, - struct attribute *attr, - char *buf) -{ - struct dma_buf_stats_attribute *attribute; - struct dma_buf_sysfs_entry *sysfs_entry; - struct dma_buf *dmabuf; - - attribute = to_dma_buf_stats_attr(attr); - sysfs_entry = to_dma_buf_entry_from_kobj(kobj); - dmabuf = sysfs_entry->dmabuf; - - if (!dmabuf || !attribute->show) - return -EIO; - - return attribute->show(dmabuf, attribute, buf); -} - -static const struct sysfs_ops dma_buf_stats_sysfs_ops = { - .show = dma_buf_stats_attribute_show, -}; - -static ssize_t exporter_name_show(struct dma_buf *dmabuf, - struct dma_buf_stats_attribute *attr, - char *buf) -{ - return sysfs_emit(buf, "%s\n", dmabuf->exp_name); -} - -static ssize_t size_show(struct dma_buf *dmabuf, - struct dma_buf_stats_attribute *attr, - char *buf) -{ - return sysfs_emit(buf, "%zu\n", dmabuf->size); -} - -static struct dma_buf_stats_attribute exporter_name_attribute = - __ATTR_RO(exporter_name); -static struct dma_buf_stats_attribute size_attribute = __ATTR_RO(size); - -static struct attribute *dma_buf_stats_default_attrs[] = { - &exporter_name_attribute.attr, - &size_attribute.attr, - NULL, -}; -ATTRIBUTE_GROUPS(dma_buf_stats_default); - -static void dma_buf_sysfs_release(struct kobject *kobj) -{ - struct dma_buf_sysfs_entry *sysfs_entry; - - sysfs_entry = to_dma_buf_entry_from_kobj(kobj); - kfree(sysfs_entry); -} - -static const struct kobj_type dma_buf_ktype = { - .sysfs_ops = &dma_buf_stats_sysfs_ops, - .release = dma_buf_sysfs_release, - .default_groups = dma_buf_stats_default_groups, -}; - -void dma_buf_stats_teardown(struct dma_buf *dmabuf) -{ - struct dma_buf_sysfs_entry *sysfs_entry; - - sysfs_entry = dmabuf->sysfs_entry; - if (!sysfs_entry) - return; - - kobject_del(&sysfs_entry->kobj); - kobject_put(&sysfs_entry->kobj); -} - - -/* Statistics files do not need to send uevents. */ -static int dmabuf_sysfs_uevent_filter(const struct kobject *kobj) -{ - return 0; -} - -static const struct kset_uevent_ops dmabuf_sysfs_no_uevent_ops = { - .filter = dmabuf_sysfs_uevent_filter, -}; - -static struct kset *dma_buf_stats_kset; -static struct kset *dma_buf_per_buffer_stats_kset; -int dma_buf_init_sysfs_statistics(void) -{ - dma_buf_stats_kset = kset_create_and_add("dmabuf", - &dmabuf_sysfs_no_uevent_ops, - kernel_kobj); - if (!dma_buf_stats_kset) - return -ENOMEM; - - dma_buf_per_buffer_stats_kset = kset_create_and_add("buffers", - &dmabuf_sysfs_no_uevent_ops, - &dma_buf_stats_kset->kobj); - if (!dma_buf_per_buffer_stats_kset) { - kset_unregister(dma_buf_stats_kset); - return -ENOMEM; - } - - return 0; -} - -void dma_buf_uninit_sysfs_statistics(void) -{ - kset_unregister(dma_buf_per_buffer_stats_kset); - kset_unregister(dma_buf_stats_kset); -} - -int dma_buf_stats_setup(struct dma_buf *dmabuf, struct file *file) -{ - struct dma_buf_sysfs_entry *sysfs_entry; - int ret; - - if (!dmabuf->exp_name) { - pr_err("exporter name must not be empty if stats needed\n"); - return -EINVAL; - } - - sysfs_entry = kzalloc(sizeof(struct dma_buf_sysfs_entry), GFP_KERNEL); - if (!sysfs_entry) - return -ENOMEM; - - sysfs_entry->kobj.kset = dma_buf_per_buffer_stats_kset; - sysfs_entry->dmabuf = dmabuf; - - dmabuf->sysfs_entry = sysfs_entry; - - /* create the directory for buffer stats */ - ret = kobject_init_and_add(&sysfs_entry->kobj, &dma_buf_ktype, NULL, - "%lu", file_inode(file)->i_ino); - if (ret) - goto err_sysfs_dmabuf; - - return 0; - -err_sysfs_dmabuf: - kobject_put(&sysfs_entry->kobj); - dmabuf->sysfs_entry = NULL; - return ret; -} diff --git a/drivers/dma-buf/dma-buf-sysfs-stats.h b/drivers/dma-buf/dma-buf-sysfs-stats.h deleted file mode 100644 index 7a8a995b75bae..0000000000000 --- a/drivers/dma-buf/dma-buf-sysfs-stats.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * DMA-BUF sysfs statistics. - * - * Copyright (C) 2021 Google LLC. - */ - -#ifndef _DMA_BUF_SYSFS_STATS_H -#define _DMA_BUF_SYSFS_STATS_H - -#ifdef CONFIG_DMABUF_SYSFS_STATS - -int dma_buf_init_sysfs_statistics(void); -void dma_buf_uninit_sysfs_statistics(void); - -int dma_buf_stats_setup(struct dma_buf *dmabuf, struct file *file); - -void dma_buf_stats_teardown(struct dma_buf *dmabuf); -#else - -static inline int dma_buf_init_sysfs_statistics(void) -{ - return 0; -} - -static inline void dma_buf_uninit_sysfs_statistics(void) {} - -static inline int dma_buf_stats_setup(struct dma_buf *dmabuf, struct file *file) -{ - return 0; -} - -static inline void dma_buf_stats_teardown(struct dma_buf *dmabuf) {} -#endif -#endif // _DMA_BUF_SYSFS_STATS_H diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index edaa9e4ee4aed..77555096e4c78 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -33,7 +33,31 @@ #include #include -#include "dma-buf-sysfs-stats.h" +#define CREATE_TRACE_POINTS +#include + +/* + * dmabuf->name must be accessed with holding dmabuf->name_lock. + * we need to take the lock around the tracepoint call itself where + * it is called in the code. + * + * Note: FUNC##_enabled() is a static branch that will only + * be set when the trace event is enabled. + */ +#define DMA_BUF_TRACE(FUNC, ...) \ + do { \ + /* Always expose lock if lockdep is enabled */ \ + if (IS_ENABLED(CONFIG_LOCKDEP) || FUNC##_enabled()) { \ + guard(spinlock)(&dmabuf->name_lock); \ + FUNC(__VA_ARGS__); \ + } \ + } while (0) + +/* Wrapper to hide the sg_table page link from the importer */ +struct dma_buf_sg_table_wrapper { + struct sg_table *original; + struct sg_table wrapper; +}; static inline int is_dma_buf_file(struct file *); @@ -156,7 +180,6 @@ static void dma_buf_release(struct dentry *dentry) */ BUG_ON(dmabuf->cb_in.active || dmabuf->cb_out.active); - dma_buf_stats_teardown(dmabuf); dmabuf->ops->release(dmabuf); if (dmabuf->resv == (struct dma_resv *)&dmabuf[1]) @@ -220,6 +243,8 @@ static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma) dmabuf->size >> PAGE_SHIFT) return -EINVAL; + DMA_BUF_TRACE(trace_dma_buf_mmap_internal, dmabuf); + return dmabuf->ops->mmap(dmabuf, vma); } @@ -735,22 +760,16 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info) dmabuf->resv = resv; } - ret = dma_buf_stats_setup(dmabuf, file); - if (ret) - goto err_dmabuf; - file->private_data = dmabuf; file->f_path.dentry->d_fsdata = dmabuf; dmabuf->file = file; __dma_buf_list_add(dmabuf); + DMA_BUF_TRACE(trace_dma_buf_export, dmabuf); + return dmabuf; -err_dmabuf: - if (!resv) - dma_resv_fini(dmabuf->resv); - kfree(dmabuf); err_file: fput(file); err_module: @@ -768,10 +787,15 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_export, "DMA_BUF"); */ int dma_buf_fd(struct dma_buf *dmabuf, int flags) { + int fd; + if (!dmabuf || !dmabuf->file) return -EINVAL; - return FD_ADD(flags, dmabuf->file); + fd = FD_ADD(flags, dmabuf->file); + DMA_BUF_TRACE(trace_dma_buf_fd, dmabuf, fd); + + return fd; } EXPORT_SYMBOL_NS_GPL(dma_buf_fd, "DMA_BUF"); @@ -786,6 +810,7 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_fd, "DMA_BUF"); struct dma_buf *dma_buf_get(int fd) { struct file *file; + struct dma_buf *dmabuf; file = fget(fd); @@ -797,7 +822,11 @@ struct dma_buf *dma_buf_get(int fd) return ERR_PTR(-EINVAL); } - return file->private_data; + dmabuf = file->private_data; + + DMA_BUF_TRACE(trace_dma_buf_get, dmabuf, fd); + + return dmabuf; } EXPORT_SYMBOL_NS_GPL(dma_buf_get, "DMA_BUF"); @@ -817,24 +846,64 @@ void dma_buf_put(struct dma_buf *dmabuf) return; fput(dmabuf->file); + + DMA_BUF_TRACE(trace_dma_buf_put, dmabuf); } EXPORT_SYMBOL_NS_GPL(dma_buf_put, "DMA_BUF"); -static void mangle_sg_table(struct sg_table *sg_table) +static int dma_buf_wrap_sg_table(struct sg_table **sg_table) { -#ifdef CONFIG_DMABUF_DEBUG - int i; - struct scatterlist *sg; - - /* To catch abuse of the underlying struct page by importers mix - * up the bits, but take care to preserve the low SG_ bits to - * not corrupt the sgt. The mixing is undone on unmap - * before passing the sgt back to the exporter. + struct scatterlist *to_sg, *from_sg; + struct sg_table *from = *sg_table; + struct dma_buf_sg_table_wrapper *to; + int i, ret; + + if (!IS_ENABLED(CONFIG_DMABUF_DEBUG)) + return 0; + + /* + * To catch abuse of the underlying struct page by importers copy the + * sg_table without copying the page_link and give only the copy back to + * the importer. */ - for_each_sgtable_sg(sg_table, sg, i) - sg->page_link ^= ~0xffUL; -#endif + to = kzalloc(sizeof(*to), GFP_KERNEL); + if (!to) + return -ENOMEM; + + ret = sg_alloc_table(&to->wrapper, from->nents, GFP_KERNEL); + if (ret) + goto free_to; + + to_sg = to->wrapper.sgl; + for_each_sgtable_dma_sg(from, from_sg, i) { + to_sg->offset = 0; + to_sg->length = 0; + sg_assign_page(to_sg, NULL); + sg_dma_address(to_sg) = sg_dma_address(from_sg); + sg_dma_len(to_sg) = sg_dma_len(from_sg); + to_sg = sg_next(to_sg); + } + + to->original = from; + *sg_table = &to->wrapper; + return 0; +free_to: + kfree(to); + return ret; +} + +static void dma_buf_unwrap_sg_table(struct sg_table **sg_table) +{ + struct dma_buf_sg_table_wrapper *copy; + + if (!IS_ENABLED(CONFIG_DMABUF_DEBUG)) + return; + + copy = container_of(*sg_table, typeof(*copy), wrapper); + *sg_table = copy->original; + sg_free_table(©->wrapper); + kfree(copy); } static inline bool @@ -971,6 +1040,9 @@ dma_buf_dynamic_attach(struct dma_buf *dmabuf, struct device *dev, list_add(&attach->node, &dmabuf->attachments); dma_resv_unlock(dmabuf->resv); + DMA_BUF_TRACE(trace_dma_buf_dynamic_attach, dmabuf, attach, + dma_buf_attachment_is_dynamic(attach), dev); + return attach; err_attach: @@ -1015,6 +1087,9 @@ void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach) if (dmabuf->ops->detach) dmabuf->ops->detach(dmabuf, attach); + DMA_BUF_TRACE(trace_dma_buf_detach, dmabuf, attach, + dma_buf_attachment_is_dynamic(attach), attach->dev); + kfree(attach); } EXPORT_SYMBOL_NS_GPL(dma_buf_detach, "DMA_BUF"); @@ -1131,10 +1206,11 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, if (ret < 0) goto error_unmap; } - mangle_sg_table(sg_table); + ret = dma_buf_wrap_sg_table(&sg_table); + if (ret) + goto error_unmap; -#ifdef CONFIG_DMA_API_DEBUG - { + if (IS_ENABLED(CONFIG_DMA_API_DEBUG)) { struct scatterlist *sg; u64 addr; int len; @@ -1146,10 +1222,10 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(len)) { pr_debug("%s: addr %llx or len %x is not page aligned!\n", __func__, addr, len); + break; } } } -#endif /* CONFIG_DMA_API_DEBUG */ return sg_table; error_unmap: @@ -1213,7 +1289,7 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, dma_resv_assert_held(attach->dmabuf->resv); - mangle_sg_table(sg_table); + dma_buf_unwrap_sg_table(&sg_table); attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction); if (dma_buf_pin_on_map(attach)) @@ -1480,6 +1556,8 @@ int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma, vma_set_file(vma, dmabuf->file); vma->vm_pgoff = pgoff; + DMA_BUF_TRACE(trace_dma_buf_mmap, dmabuf); + return dmabuf->ops->mmap(dmabuf, vma); } EXPORT_SYMBOL_NS_GPL(dma_buf_mmap, "DMA_BUF"); @@ -1710,12 +1788,6 @@ static inline void dma_buf_uninit_debugfs(void) static int __init dma_buf_init(void) { - int ret; - - ret = dma_buf_init_sysfs_statistics(); - if (ret) - return ret; - dma_buf_mnt = kern_mount(&dma_buf_fs_type); if (IS_ERR(dma_buf_mnt)) return PTR_ERR(dma_buf_mnt); @@ -1729,6 +1801,5 @@ static void __exit dma_buf_deinit(void) { dma_buf_uninit_debugfs(); kern_unmount(dma_buf_mnt); - dma_buf_uninit_sysfs_statistics(); } __exitcall(dma_buf_deinit); diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index b4f5c86352764..21c5c30b4f34f 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -358,11 +358,8 @@ void __dma_fence_might_wait(void) * * Unlike dma_fence_signal_timestamp(), this function must be called with * &dma_fence.lock held. - * - * Returns 0 on success and a negative error value when @fence has been - * signalled already. */ -int dma_fence_signal_timestamp_locked(struct dma_fence *fence, +void dma_fence_signal_timestamp_locked(struct dma_fence *fence, ktime_t timestamp) { struct dma_fence_cb *cur, *tmp; @@ -372,7 +369,7 @@ int dma_fence_signal_timestamp_locked(struct dma_fence *fence, if (unlikely(test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) - return -EINVAL; + return; /* Stash the cb_list before replacing it with the timestamp */ list_replace(&fence->cb_list, &cb_list); @@ -385,8 +382,6 @@ int dma_fence_signal_timestamp_locked(struct dma_fence *fence, INIT_LIST_HEAD(&cur->node); cur->func(fence, cur); } - - return 0; } EXPORT_SYMBOL(dma_fence_signal_timestamp_locked); @@ -401,23 +396,17 @@ EXPORT_SYMBOL(dma_fence_signal_timestamp_locked); * can only go from the unsignaled to the signaled state and not back, it will * only be effective the first time. Set the timestamp provided as the fence * signal timestamp. - * - * Returns 0 on success and a negative error value when @fence has been - * signalled already. */ -int dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp) +void dma_fence_signal_timestamp(struct dma_fence *fence, ktime_t timestamp) { unsigned long flags; - int ret; if (WARN_ON(!fence)) - return -EINVAL; + return; spin_lock_irqsave(fence->lock, flags); - ret = dma_fence_signal_timestamp_locked(fence, timestamp); + dma_fence_signal_timestamp_locked(fence, timestamp); spin_unlock_irqrestore(fence->lock, flags); - - return ret; } EXPORT_SYMBOL(dma_fence_signal_timestamp); @@ -433,16 +422,57 @@ EXPORT_SYMBOL(dma_fence_signal_timestamp); * * Unlike dma_fence_signal(), this function must be called with &dma_fence.lock * held. - * - * Returns 0 on success and a negative error value when @fence has been - * signalled already. */ -int dma_fence_signal_locked(struct dma_fence *fence) +void dma_fence_signal_locked(struct dma_fence *fence) { - return dma_fence_signal_timestamp_locked(fence, ktime_get()); + dma_fence_signal_timestamp_locked(fence, ktime_get()); } EXPORT_SYMBOL(dma_fence_signal_locked); +/** + * dma_fence_check_and_signal_locked - signal the fence if it's not yet signaled + * @fence: the fence to check and signal + * + * Checks whether a fence was signaled and signals it if it was not yet signaled. + * + * Unlike dma_fence_check_and_signal(), this function must be called with + * &struct dma_fence.lock being held. + * + * Return: true if fence has been signaled already, false otherwise. + */ +bool dma_fence_check_and_signal_locked(struct dma_fence *fence) +{ + bool ret; + + ret = dma_fence_test_signaled_flag(fence); + dma_fence_signal_locked(fence); + + return ret; +} +EXPORT_SYMBOL(dma_fence_check_and_signal_locked); + +/** + * dma_fence_check_and_signal - signal the fence if it's not yet signaled + * @fence: the fence to check and signal + * + * Checks whether a fence was signaled and signals it if it was not yet signaled. + * All this is done in a race-free manner. + * + * Return: true if fence has been signaled already, false otherwise. + */ +bool dma_fence_check_and_signal(struct dma_fence *fence) +{ + unsigned long flags; + bool ret; + + spin_lock_irqsave(fence->lock, flags); + ret = dma_fence_check_and_signal_locked(fence); + spin_unlock_irqrestore(fence->lock, flags); + + return ret; +} +EXPORT_SYMBOL(dma_fence_check_and_signal); + /** * dma_fence_signal - signal completion of a fence * @fence: the fence to signal @@ -452,28 +482,22 @@ EXPORT_SYMBOL(dma_fence_signal_locked); * dma_fence_add_callback(). Can be called multiple times, but since a fence * can only go from the unsignaled to the signaled state and not back, it will * only be effective the first time. - * - * Returns 0 on success and a negative error value when @fence has been - * signalled already. */ -int dma_fence_signal(struct dma_fence *fence) +void dma_fence_signal(struct dma_fence *fence) { unsigned long flags; - int ret; bool tmp; if (WARN_ON(!fence)) - return -EINVAL; + return; tmp = dma_fence_begin_signalling(); spin_lock_irqsave(fence->lock, flags); - ret = dma_fence_signal_timestamp_locked(fence, ktime_get()); + dma_fence_signal_timestamp_locked(fence, ktime_get()); spin_unlock_irqrestore(fence->lock, flags); dma_fence_end_signalling(tmp); - - return ret; } EXPORT_SYMBOL(dma_fence_signal); @@ -543,7 +567,7 @@ void dma_fence_release(struct kref *kref) trace_dma_fence_destroy(fence); if (!list_empty(&fence->cb_list) && - !test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { + !dma_fence_test_signaled_flag(fence)) { const char __rcu *timeline; const char __rcu *driver; unsigned long flags; @@ -600,7 +624,7 @@ static bool __dma_fence_enable_signaling(struct dma_fence *fence) was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags); - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + if (dma_fence_test_signaled_flag(fence)) return false; if (!was_set && fence->ops->enable_signaling) { @@ -664,7 +688,7 @@ int dma_fence_add_callback(struct dma_fence *fence, struct dma_fence_cb *cb, if (WARN_ON(!fence || !func)) return -EINVAL; - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { + if (dma_fence_test_signaled_flag(fence)) { INIT_LIST_HEAD(&cb->node); return -ENOENT; } @@ -781,7 +805,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) spin_lock_irqsave(fence->lock, flags); - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + if (dma_fence_test_signaled_flag(fence)) goto out; if (intr && signal_pending(current)) { @@ -798,7 +822,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) cb.task = current; list_add(&cb.base.node, &fence->cb_list); - while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { + while (!dma_fence_test_signaled_flag(fence) && ret > 0) { if (intr) __set_current_state(TASK_INTERRUPTIBLE); else @@ -830,7 +854,7 @@ dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, for (i = 0; i < count; ++i) { struct dma_fence *fence = fences[i]; - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { + if (dma_fence_test_signaled_flag(fence)) { if (idx) *idx = i; return true; @@ -1108,7 +1132,7 @@ const char __rcu *dma_fence_driver_name(struct dma_fence *fence) RCU_LOCKDEP_WARN(!rcu_read_lock_held(), "RCU protection is required for safe access to returned string"); - if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + if (!dma_fence_test_signaled_flag(fence)) return fence->ops->get_driver_name(fence); else return "detached-driver"; @@ -1140,7 +1164,7 @@ const char __rcu *dma_fence_timeline_name(struct dma_fence *fence) RCU_LOCKDEP_WARN(!rcu_read_lock_held(), "RCU protection is required for safe access to returned string"); - if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + if (!dma_fence_test_signaled_flag(fence)) return fence->ops->get_timeline_name(fence); else return "signaled-timeline"; diff --git a/drivers/dma-buf/dma-heap.c b/drivers/dma-buf/dma-heap.c index 8ab49924f8b71..d230ddeb24e0f 100644 --- a/drivers/dma-buf/dma-heap.c +++ b/drivers/dma-buf/dma-heap.c @@ -49,6 +49,11 @@ static dev_t dma_heap_devt; static struct class *dma_heap_class; static DEFINE_XARRAY_ALLOC(dma_heap_minors); +bool __read_mostly mem_accounting; +module_param(mem_accounting, bool, 0444); +MODULE_PARM_DESC(mem_accounting, + "Enable cgroup-based memory accounting for dma-buf heap allocations (default=false)."); + static int dma_heap_buffer_alloc(struct dma_heap *heap, size_t len, u32 fd_flags, u64 heap_flags) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index bea3e9858aca5..76bcda500be45 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -40,6 +40,9 @@ #include #include #include +#ifndef HAVE_CONFIG_H +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE +#endif /** * DOC: Reservation Object Overview @@ -708,6 +711,7 @@ EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); * May be called without holding the dma_resv lock. Sets @deadline on * all fences filtered by @usage. */ +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, ktime_t deadline) { @@ -721,6 +725,7 @@ void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, dma_resv_iter_end(&cursor); } EXPORT_SYMBOL_GPL(dma_resv_set_deadline); +#endif /** * dma_resv_test_signaled - Test if a reservation object's fences have been diff --git a/drivers/dma-buf/heaps/cma_heap.c b/drivers/dma-buf/heaps/cma_heap.c index 42f88193eab9f..49cc45fb42dd7 100644 --- a/drivers/dma-buf/heaps/cma_heap.c +++ b/drivers/dma-buf/heaps/cma_heap.c @@ -331,7 +331,7 @@ static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, while (nr_clear_pages > 0) { void *vaddr = kmap_local_page(page); - memset(vaddr, 0, PAGE_SIZE); + clear_page(vaddr); kunmap_local(vaddr); /* * Avoid wasting time zeroing memory if the process diff --git a/drivers/dma-buf/heaps/system_heap.c b/drivers/dma-buf/heaps/system_heap.c index 4c782fe33fd49..4049d042afa14 100644 --- a/drivers/dma-buf/heaps/system_heap.c +++ b/drivers/dma-buf/heaps/system_heap.c @@ -320,14 +320,17 @@ static struct page *alloc_largest_available(unsigned long size, { struct page *page; int i; + gfp_t flags; for (i = 0; i < NUM_ORDERS; i++) { if (size < (PAGE_SIZE << orders[i])) continue; if (max_order < orders[i]) continue; - - page = alloc_pages(order_flags[i], orders[i]); + flags = order_flags[i]; + if (mem_accounting) + flags |= __GFP_ACCOUNT; + page = alloc_pages(flags, orders[i]); if (!page) continue; return page; diff --git a/drivers/dma-buf/st-dma-fence.c b/drivers/dma-buf/st-dma-fence.c index 27a36045410b3..73ed6fd48a13f 100644 --- a/drivers/dma-buf/st-dma-fence.c +++ b/drivers/dma-buf/st-dma-fence.c @@ -33,50 +33,9 @@ static void mock_fence_release(struct dma_fence *f) kmem_cache_free(slab_fences, to_mock_fence(f)); } -struct wait_cb { - struct dma_fence_cb cb; - struct task_struct *task; -}; - -static void mock_wakeup(struct dma_fence *f, struct dma_fence_cb *cb) -{ - wake_up_process(container_of(cb, struct wait_cb, cb)->task); -} - -static long mock_wait(struct dma_fence *f, bool intr, long timeout) -{ - const int state = intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; - struct wait_cb cb = { .task = current }; - - if (dma_fence_add_callback(f, &cb.cb, mock_wakeup)) - return timeout; - - while (timeout) { - set_current_state(state); - - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &f->flags)) - break; - - if (signal_pending_state(state, current)) - break; - - timeout = schedule_timeout(timeout); - } - __set_current_state(TASK_RUNNING); - - if (!dma_fence_remove_callback(f, &cb.cb)) - return timeout; - - if (signal_pending_state(state, current)) - return -ERESTARTSYS; - - return -ETIME; -} - static const struct dma_fence_ops mock_ops = { .get_driver_name = mock_name, .get_timeline_name = mock_name, - .wait = mock_wait, .release = mock_fence_release, }; @@ -126,7 +85,7 @@ static int test_signaling(void *arg) goto err_free; } - if (dma_fence_signal(f)) { + if (dma_fence_check_and_signal(f)) { pr_err("Fence reported being already signaled\n"); goto err_free; } @@ -136,7 +95,7 @@ static int test_signaling(void *arg) goto err_free; } - if (!dma_fence_signal(f)) { + if (!dma_fence_test_signaled_flag(f)) { pr_err("Fence reported not being already signaled\n"); goto err_free; } @@ -349,14 +308,14 @@ static int test_wait(void *arg) dma_fence_enable_sw_signaling(f); - if (dma_fence_wait_timeout(f, false, 0) != -ETIME) { + if (dma_fence_wait_timeout(f, false, 0) != 0) { pr_err("Wait reported complete before being signaled\n"); goto err_free; } dma_fence_signal(f); - if (dma_fence_wait_timeout(f, false, 0) != 0) { + if (dma_fence_wait_timeout(f, false, 0) != 1) { pr_err("Wait reported incomplete after being signaled\n"); goto err_free; } @@ -393,16 +352,16 @@ static int test_wait_timeout(void *arg) dma_fence_enable_sw_signaling(wt.f); - if (dma_fence_wait_timeout(wt.f, false, 1) != -ETIME) { + if (dma_fence_wait_timeout(wt.f, false, 1) != 0) { pr_err("Wait reported complete before being signaled\n"); goto err_free; } mod_timer(&wt.timer, jiffies + 1); - if (dma_fence_wait_timeout(wt.f, false, 2) == -ETIME) { + if (dma_fence_wait_timeout(wt.f, false, HZ) == 0) { if (timer_pending(&wt.timer)) { - pr_notice("Timer did not fire within the jiffy!\n"); + pr_notice("Timer did not fire within one HZ!\n"); err = 0; /* not our fault! */ } else { pr_err("Wait reported incomplete after timeout\n"); diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c new file mode 100644 index 0000000000000..aae82db542a5e --- /dev/null +++ b/drivers/extcon/extcon-arizona.c @@ -0,0 +1,1816 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * extcon-arizona.c - Extcon driver Wolfson Arizona devices + * + * Copyright (C) 2012-2014 Wolfson Microelectronics plc + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define ARIZONA_MAX_MICD_RANGE 8 + +#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4 +#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5 +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9 +#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb + +#define ARIZONA_TST_CAP_DEFAULT 0x3 +#define ARIZONA_TST_CAP_CLAMP 0x1 + +#define ARIZONA_HPDET_MAX 10000 + +#define HPDET_DEBOUNCE 500 +#define DEFAULT_MICD_TIMEOUT 2000 + +#define ARIZONA_HPDET_WAIT_COUNT 15 +#define ARIZONA_HPDET_WAIT_DELAY_MS 20 + +#define QUICK_HEADPHONE_MAX_OHM 3 +#define MICROPHONE_MIN_OHM 1257 +#define MICROPHONE_MAX_OHM 30000 + +#define MICD_DBTIME_TWO_READINGS 2 +#define MICD_DBTIME_FOUR_READINGS 4 + +#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \ + ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \ + ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \ + ARIZONA_MICD_LVL_7) + +#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7) + +#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8) + +struct arizona_extcon_info { + struct device *dev; + struct arizona *arizona; + struct mutex lock; + struct regulator *micvdd; + struct input_dev *input; + + u16 last_jackdet; + + int micd_mode; + const struct arizona_micd_config *micd_modes; + int micd_num_modes; + + const struct arizona_micd_range *micd_ranges; + int num_micd_ranges; + + bool micd_reva; + bool micd_clamp; + + struct delayed_work hpdet_work; + struct delayed_work micd_detect_work; + struct delayed_work micd_timeout_work; + + bool hpdet_active; + bool hpdet_done; + bool hpdet_retried; + + int num_hpdet_res; + unsigned int hpdet_res[3]; + + bool mic; + bool detecting; + int jack_flips; + + int hpdet_ip_version; + + struct extcon_dev *edev; + + struct gpio_desc *micd_pol_gpio; +}; + +static const struct arizona_micd_config micd_default_modes[] = { + { ARIZONA_ACCDET_SRC, 1, 0 }, + { 0, 2, 1 }, +}; + +static const struct arizona_micd_range micd_default_ranges[] = { + { .max = 11, .key = BTN_0 }, + { .max = 28, .key = BTN_1 }, + { .max = 54, .key = BTN_2 }, + { .max = 100, .key = BTN_3 }, + { .max = 186, .key = BTN_4 }, + { .max = 430, .key = BTN_5 }, +}; + +/* The number of levels in arizona_micd_levels valid for button thresholds */ +#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64 + +static const int arizona_micd_levels[] = { + 3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46, + 49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100, + 105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245, + 270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071, + 1257, 30000, +}; + +static const unsigned int arizona_cable[] = { + EXTCON_MECHANICAL, + EXTCON_JACK_MICROPHONE, + EXTCON_JACK_HEADPHONE, + EXTCON_JACK_LINE_OUT, + EXTCON_NONE, +}; + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info); + +static void arizona_extcon_hp_clamp(struct arizona_extcon_info *info, + bool clamp) +{ + struct arizona *arizona = info->arizona; + unsigned int mask = 0, val = 0; + unsigned int cap_sel = 0; + int ret; + + switch (arizona->type) { + case WM8998: + case WM1814: + mask = 0; + break; + case WM5110: + case WM8280: + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) { + val = ARIZONA_HP1L_SHRTO; + cap_sel = ARIZONA_TST_CAP_CLAMP; + } else { + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + cap_sel = ARIZONA_TST_CAP_DEFAULT; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_TEST_CTRL_1, + ARIZONA_HP1_TST_CAP_SEL_MASK, + cap_sel); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to set TST_CAP_SEL: %d\n", ret); + break; + default: + mask = ARIZONA_RMV_SHRT_HP1L; + if (clamp) + val = ARIZONA_RMV_SHRT_HP1L; + break; + } + + snd_soc_dapm_mutex_lock(arizona->dapm); + + arizona->hpdet_clamp = clamp; + + /* Keep the HP output stages disabled while doing the clamp */ + if (clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable headphone outputs: %d\n", + ret); + } + + if (mask) { + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1L, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1R, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + } + + /* Restore the desired state while not doing the clamp */ + if (!clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, arizona->hp_ena); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to restore headphone outputs: %d\n", + ret); + } + + snd_soc_dapm_mutex_unlock(arizona->dapm); +} + +static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) +{ + struct arizona *arizona = info->arizona; + + mode %= info->micd_num_modes; + + gpiod_set_value_cansleep(info->micd_pol_gpio, + info->micd_modes[mode].gpio); + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_SRC_MASK, + info->micd_modes[mode].bias << + ARIZONA_MICD_BIAS_SRC_SHIFT); + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[mode].src); + + info->micd_mode = mode; + + dev_dbg(arizona->dev, "Set jack polarity to %d\n", mode); +} + +static const char *arizona_extcon_get_micbias(struct arizona_extcon_info *info) +{ + switch (info->micd_modes[0].bias) { + case 1: + return "MICBIAS1"; + case 2: + return "MICBIAS2"; + case 3: + return "MICBIAS3"; + default: + return "MICVDD"; + } +} + +static void arizona_extcon_pulse_micbias(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + int ret; + + ret = snd_soc_component_force_enable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to enable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (!arizona->pdata.micd_force_micbias) { + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + } +} + +static void arizona_start_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + bool change; + int ret; + unsigned int mode; + + /* Microphone detection can't use idle mode */ + pm_runtime_get(info->dev); + + if (info->detecting) { + ret = regulator_allow_bypass(info->micvdd, false); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to regulate MICVDD: %d\n", + ret); + } + } + + ret = regulator_enable(info->micvdd); + if (ret != 0) { + dev_err(arizona->dev, "Failed to enable MICVDD: %d\n", + ret); + } + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x0 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + if (info->detecting && arizona->pdata.micd_software_compare) + mode = ARIZONA_ACCDET_MODE_ADC; + else + mode = ARIZONA_ACCDET_MODE_MIC; + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, mode); + + arizona_extcon_pulse_micbias(info); + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA, + &change); + if (ret < 0) { + dev_err(arizona->dev, "Failed to enable micd: %d\n", ret); + } else if (!change) { + regulator_disable(info->micvdd); + pm_runtime_put_autosuspend(info->dev); + } +} + +static void arizona_stop_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + bool change = false; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) + dev_err(arizona->dev, "Failed to disable micd: %d\n", ret); + + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x2 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + if (change) { + regulator_disable(info->micvdd); + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + } +} + +static struct { + unsigned int threshold; + unsigned int factor_a; + unsigned int factor_b; +} arizona_hpdet_b_ranges[] = { + { 100, 5528, 362464 }, + { 169, 11084, 6186851 }, + { 169, 11065, 65460395 }, +}; + +#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb + +static struct { + int min; + int max; +} arizona_hpdet_c_ranges[] = { + { 0, 30 }, + { 8, 100 }, + { 100, 1000 }, + { 1000, 10000 }, +}; + +static int arizona_hpdet_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val, range; + int ret; + + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HPDET status: %d\n", + ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (!(val & ARIZONA_HP_DONE)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_MASK; + break; + + case 1: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP value: %d\n", + ret); + return -EAGAIN; + } + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 && + (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d\n", + range); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + /* If we go out of range report top of range */ + if (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX) { + dev_dbg(arizona->dev, "Measurement out of range\n"); + return ARIZONA_HPDET_MAX; + } + + dev_dbg(arizona->dev, "HPDET read %d in range %d\n", + val, range); + + val = arizona_hpdet_b_ranges[range].factor_b + / ((val * 100) - + arizona_hpdet_b_ranges[range].factor_a); + break; + + case 2: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to ohms, the value is in 0.5 ohm increments */ + val /= 2; + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + /* Skip up a range, or report? */ + if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 && + (val >= arizona_hpdet_c_ranges[range].max)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", + arizona_hpdet_c_ranges[range].min, + arizona_hpdet_c_ranges[range].max); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + if (range && (val < arizona_hpdet_c_ranges[range].min)) { + dev_dbg(arizona->dev, "Reporting range boundary %d\n", + arizona_hpdet_c_ranges[range].min); + val = arizona_hpdet_c_ranges[range].min; + } + break; + + default: + dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", + info->hpdet_ip_version); + return -EINVAL; + } + + dev_dbg(arizona->dev, "HP impedance %d ohms\n", val); + return val; +} + +static int arizona_hpdet_do_id(struct arizona_extcon_info *info, int *reading, + bool *mic) +{ + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + + if (!arizona->pdata.hpdet_acc_id) + return 0; + + /* + * If we're using HPDET for accessory identification we need + * to take multiple measurements, step through them in sequence. + */ + info->hpdet_res[info->num_hpdet_res++] = *reading; + + /* Only check the mic directly if we didn't already ID it */ + if (id_gpio && info->num_hpdet_res == 1) { + dev_dbg(arizona->dev, "Measuring mic\n"); + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK | + ARIZONA_ACCDET_SRC, + ARIZONA_ACCDET_MODE_HPR | + info->micd_modes[0].src); + + gpio_set_value_cansleep(id_gpio, 1); + + regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + return -EAGAIN; + } + + /* OK, got both. Now, compare... */ + dev_dbg(arizona->dev, "HPDET measured %d %d\n", + info->hpdet_res[0], info->hpdet_res[1]); + + /* Take the headphone impedance for the main report */ + *reading = info->hpdet_res[0]; + + /* Sometimes we get false readings due to slow insert */ + if (*reading >= ARIZONA_HPDET_MAX && !info->hpdet_retried) { + dev_dbg(arizona->dev, "Retrying high impedance\n"); + info->num_hpdet_res = 0; + info->hpdet_retried = true; + arizona_start_hpdet_acc_id(info); + pm_runtime_put(info->dev); + return -EAGAIN; + } + + /* + * If we measure the mic as high impedance + */ + if (!id_gpio || info->hpdet_res[1] > 50) { + dev_dbg(arizona->dev, "Detected mic\n"); + *mic = true; + info->detecting = true; + } else { + dev_dbg(arizona->dev, "Detected headphone\n"); + } + + /* Make sure everything is reset back to the real polarity */ + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[0].src); + + return 0; +} + +static irqreturn_t arizona_hpdet_irq(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + unsigned int report = EXTCON_JACK_HEADPHONE; + int ret, reading; + bool mic = false; + + mutex_lock(&info->lock); + + /* If we got a spurious IRQ for some reason then ignore it */ + if (!info->hpdet_active) { + dev_warn(arizona->dev, "Spurious HPDET IRQ\n"); + mutex_unlock(&info->lock); + return IRQ_NONE; + } + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + goto out; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring HPDET for removed cable\n"); + goto done; + } + + ret = arizona_hpdet_read(info); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + reading = ret; + + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + ret = arizona_hpdet_do_id(info, &reading, &mic); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + + /* Report high impedence cables as line outputs */ + if (reading >= 5000) + report = EXTCON_JACK_LINE_OUT; + else + report = EXTCON_JACK_HEADPHONE; + + ret = extcon_set_state_sync(info->edev, report, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report HP/line: %d\n", + ret); + +done: + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + arizona_extcon_hp_clamp(info, false); + + if (id_gpio) + gpio_set_value_cansleep(id_gpio, 0); + + /* If we have a mic then reenable MICDET */ + if (mic || info->mic) + arizona_start_mic(info); + + if (info->hpdet_active) { + pm_runtime_put_autosuspend(info->dev); + info->hpdet_active = false; + } + + info->hpdet_done = true; + +out: + mutex_unlock(&info->lock); + + return IRQ_HANDLED; +} + +static void arizona_identify_headphone(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + if (info->hpdet_done) + return; + + dev_dbg(arizona->dev, "Starting HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get(info->dev); + + info->hpdet_active = true; + + arizona_stop_mic(info); + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + + return; + +err: + arizona_extcon_hp_clamp(info, false); + pm_runtime_put_autosuspend(info->dev); + + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + if (info->mic) + arizona_start_mic(info); + + info->hpdet_active = false; +} + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int hp_reading = 32; + bool mic; + int ret; + + dev_dbg(arizona->dev, "Starting identification via HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get_sync(info->dev); + + info->hpdet_active = true; + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + if (arizona->pdata.hpdet_acc_id_line) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, + "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + } else { + arizona_hpdet_do_id(info, &hp_reading, &mic); + } + + return; + +err: + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + info->hpdet_active = false; +} + +static void arizona_micd_timeout_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_timeout_work.work); + + mutex_lock(&info->lock); + + dev_dbg(info->arizona->dev, "MICD timed out, reporting HP\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + + mutex_unlock(&info->lock); +} + +static int arizona_micd_adc_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int ret; + + /* Must disable MICD before we read the ADCVAL */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET_ADCVAL: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val); + + val &= ARIZONA_MICDET_ADCVAL_MASK; + if (val < ARRAY_SIZE(arizona_micd_levels)) + val = arizona_micd_levels[val]; + else + val = INT_MAX; + + if (val <= QUICK_HEADPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0; + else if (val <= MICROPHONE_MIN_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1; + else if (val <= MICROPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8; + else + val = ARIZONA_MICD_LVL_8; + + return val; +} + +static int arizona_micd_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val = 0; + int ret, i; + + for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET: %x\n", val); + + if (!(val & ARIZONA_MICD_VALID)) { + dev_warn(arizona->dev, + "Microphone detection state invalid\n"); + return -EINVAL; + } + } + + if (i == 10 && !(val & MICD_LVL_0_TO_8)) { + dev_err(arizona->dev, "Failed to get valid MICDET value\n"); + return -EINVAL; + } + + return val; +} + +static int arizona_micdet_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int ret, val; + + if (info->detecting && arizona->pdata.micd_software_compare) + ret = arizona_micd_adc_read(info); + else + ret = arizona_micd_read(info); + if (ret < 0) + return ret; + + val = ret; + + /* Due to jack detect this should never happen */ + if (!(val & ARIZONA_MICD_STS)) { + dev_warn(arizona->dev, "Detected open circuit\n"); + info->mic = false; + info->detecting = false; + arizona_identify_headphone(info); + return 0; + } + + /* If we got a high impedence we should have a headset, report it. */ + if (val & ARIZONA_MICD_LVL_8) { + info->mic = true; + info->detecting = false; + + arizona_identify_headphone(info); + + ret = extcon_set_state_sync(info->edev, + EXTCON_JACK_MICROPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Headset report failed: %d\n", + ret); + + /* Don't need to regulate for button detection */ + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + return 0; + } + + /* If we detected a lower impedence during initial startup + * then we probably have the wrong polarity, flip it. Don't + * do this for the lowest impedences to speed up detection of + * plain headphones. If both polarities report a low + * impedence then give up and report headphones. + */ + if (val & MICD_LVL_1_TO_7) { + if (info->jack_flips >= info->micd_num_modes * 10) { + dev_dbg(arizona->dev, "Detected HP/line\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + } else { + info->micd_mode++; + if (info->micd_mode == info->micd_num_modes) + info->micd_mode = 0; + arizona_extcon_set_mode(info, info->micd_mode); + + info->jack_flips++; + + if (arizona->pdata.micd_software_compare) + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, + ARIZONA_MICD_ENA); + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(arizona->pdata.micd_timeout)); + } + + return 0; + } + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. + */ + dev_dbg(arizona->dev, "Headphone detected\n"); + info->detecting = false; + + arizona_identify_headphone(info); + + return 0; +} + +static int arizona_button_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int val, key, lvl, i; + + val = arizona_micd_read(info); + if (val < 0) + return val; + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. Otherwise it's a button press. + */ + if (val & MICD_LVL_0_TO_7) { + if (info->mic) { + dev_dbg(arizona->dev, "Mic button detected\n"); + + lvl = val & ARIZONA_MICD_LVL_MASK; + lvl >>= ARIZONA_MICD_LVL_SHIFT; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + + if (lvl && ffs(lvl) - 1 < info->num_micd_ranges) { + key = info->micd_ranges[ffs(lvl) - 1].key; + input_report_key(info->input, key, 1); + input_sync(info->input); + } else { + dev_err(arizona->dev, "Button out of range\n"); + } + } else { + dev_warn(arizona->dev, "Button with no mic: %x\n", + val); + } + } else { + dev_dbg(arizona->dev, "Mic button released\n"); + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + arizona_extcon_pulse_micbias(info); + } + + return 0; +} + +static void arizona_micd_detect(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_detect_work.work); + struct arizona *arizona = info->arizona; + int ret; + + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + mutex_unlock(&info->lock); + return; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n"); + mutex_unlock(&info->lock); + return; + } + + if (info->detecting) + arizona_micdet_reading(info); + else + arizona_button_reading(info); + + pm_runtime_mark_last_busy(info->dev); + mutex_unlock(&info->lock); +} + +static irqreturn_t arizona_micdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int debounce = arizona->pdata.micd_detect_debounce; + + cancel_delayed_work_sync(&info->micd_detect_work); + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + if (!info->detecting) + debounce = 0; + mutex_unlock(&info->lock); + + if (debounce) + queue_delayed_work(system_power_efficient_wq, + &info->micd_detect_work, + msecs_to_jiffies(debounce)); + else + arizona_micd_detect(&info->micd_detect_work.work); + + return IRQ_HANDLED; +} + +static void arizona_hpdet_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + hpdet_work.work); + + mutex_lock(&info->lock); + arizona_start_hpdet_acc_id(info); + mutex_unlock(&info->lock); +} + +static int arizona_hpdet_wait(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int i, ret; + + for (i = 0; i < ARIZONA_HPDET_WAIT_COUNT; i++) { + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, + &val); + if (ret) { + dev_err(arizona->dev, + "Failed to read HPDET state: %d\n", ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (val & ARIZONA_HP_DONE) + return 0; + break; + default: + if (val & ARIZONA_HP_DONE_B) + return 0; + break; + } + + msleep(ARIZONA_HPDET_WAIT_DELAY_MS); + } + + dev_warn(arizona->dev, "HPDET did not appear to complete\n"); + + return -ETIMEDOUT; +} + +static irqreturn_t arizona_jackdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + unsigned int val, present, mask; + bool cancelled_hp, cancelled_mic; + int ret, i; + + cancelled_hp = cancel_delayed_work_sync(&info->hpdet_work); + cancelled_mic = cancel_delayed_work_sync(&info->micd_timeout_work); + + pm_runtime_get_sync(info->dev); + + mutex_lock(&info->lock); + + if (info->micd_clamp) { + mask = ARIZONA_MICD_CLAMP_STS; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read jackdet status: %d\n", + ret); + mutex_unlock(&info->lock); + pm_runtime_put_autosuspend(info->dev); + return IRQ_NONE; + } + + val &= mask; + if (val == info->last_jackdet) { + dev_dbg(arizona->dev, "Suppressing duplicate JACKDET\n"); + if (cancelled_hp) + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + + if (cancelled_mic) { + int micd_timeout = arizona->pdata.micd_timeout; + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(micd_timeout)); + } + + goto out; + } + info->last_jackdet = val; + + if (info->last_jackdet == present) { + dev_dbg(arizona->dev, "Detected jack\n"); + ret = extcon_set_state_sync(info->edev, + EXTCON_MECHANICAL, true); + + if (ret != 0) + dev_err(arizona->dev, "Mechanical report failed: %d\n", + ret); + + info->detecting = true; + info->mic = false; + info->jack_flips = 0; + + if (!arizona->pdata.hpdet_acc_id) { + arizona_start_mic(info); + } else { + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + } + + if (info->micd_clamp || !arizona->pdata.jd_invert) + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | + ARIZONA_JD1_DB, 0); + } else { + dev_dbg(arizona->dev, "Detected jack removal\n"); + + arizona_stop_mic(info); + + info->num_hpdet_res = 0; + for (i = 0; i < ARRAY_SIZE(info->hpdet_res); i++) + info->hpdet_res[i] = 0; + info->mic = false; + info->hpdet_done = false; + info->hpdet_retried = false; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + + for (i = 0; i < ARRAY_SIZE(arizona_cable) - 1; i++) { + ret = extcon_set_state_sync(info->edev, + arizona_cable[i], false); + if (ret != 0) + dev_err(arizona->dev, + "Removal report failed: %d\n", ret); + } + + /* + * If the jack was removed during a headphone detection we + * need to wait for the headphone detection to finish, as + * it can not be aborted. We don't want to be able to start + * a new headphone detection from a fresh insert until this + * one is finished. + */ + arizona_hpdet_wait(info); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB); + } + +out: + /* Clear trig_sts to make sure DCVDD is not forced up */ + regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, + ARIZONA_MICD_CLAMP_FALL_TRIG_STS | + ARIZONA_MICD_CLAMP_RISE_TRIG_STS | + ARIZONA_JD1_FALL_TRIG_STS | + ARIZONA_JD1_RISE_TRIG_STS); + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + return IRQ_HANDLED; +} + +/* Map a level onto a slot in the register bank */ +static void arizona_micd_set_level(struct arizona *arizona, int index, + unsigned int level) +{ + int reg; + unsigned int mask; + + reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2); + + if (!(index % 2)) { + mask = 0x3f00; + level <<= 8; + } else { + mask = 0x3f; + } + + /* Program the level itself */ + regmap_update_bits(arizona->regmap, reg, mask, level); +} + +static int arizona_extcon_get_micd_configs(struct device *dev, + struct arizona *arizona) +{ + const char * const prop = "wlf,micd-configs"; + const int entries_per_config = 3; + struct arizona_micd_config *micd_configs; + int nconfs, ret; + int i, j; + u32 *vals; + + nconfs = device_property_count_u32(arizona->dev, prop); + if (nconfs <= 0) + return 0; + + vals = kcalloc(nconfs, sizeof(u32), GFP_KERNEL); + if (!vals) + return -ENOMEM; + + ret = device_property_read_u32_array(arizona->dev, prop, vals, nconfs); + if (ret < 0) + goto out; + + nconfs /= entries_per_config; + micd_configs = devm_kcalloc(dev, nconfs, sizeof(*micd_configs), + GFP_KERNEL); + if (!micd_configs) { + ret = -ENOMEM; + goto out; + } + + for (i = 0, j = 0; i < nconfs; ++i) { + micd_configs[i].src = vals[j++] ? ARIZONA_ACCDET_SRC : 0; + micd_configs[i].bias = vals[j++]; + micd_configs[i].gpio = vals[j++]; + } + + arizona->pdata.micd_configs = micd_configs; + arizona->pdata.num_micd_configs = nconfs; + +out: + kfree(vals); + return ret; +} + +static int arizona_extcon_device_get_pdata(struct device *dev, + struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + unsigned int val = ARIZONA_ACCDET_MODE_HPL; + int ret; + + device_property_read_u32(arizona->dev, "wlf,hpdet-channel", &val); + switch (val) { + case ARIZONA_ACCDET_MODE_HPL: + case ARIZONA_ACCDET_MODE_HPR: + pdata->hpdet_channel = val; + break; + default: + dev_err(arizona->dev, + "Wrong wlf,hpdet-channel DT value %d\n", val); + pdata->hpdet_channel = ARIZONA_ACCDET_MODE_HPL; + } + + device_property_read_u32(arizona->dev, "wlf,micd-detect-debounce", + &pdata->micd_detect_debounce); + + device_property_read_u32(arizona->dev, "wlf,micd-bias-start-time", + &pdata->micd_bias_start_time); + + device_property_read_u32(arizona->dev, "wlf,micd-rate", + &pdata->micd_rate); + + device_property_read_u32(arizona->dev, "wlf,micd-dbtime", + &pdata->micd_dbtime); + + device_property_read_u32(arizona->dev, "wlf,micd-timeout-ms", + &pdata->micd_timeout); + + pdata->micd_force_micbias = device_property_read_bool(arizona->dev, + "wlf,micd-force-micbias"); + + pdata->micd_software_compare = device_property_read_bool(arizona->dev, + "wlf,micd-software-compare"); + + pdata->jd_invert = device_property_read_bool(arizona->dev, + "wlf,jd-invert"); + + device_property_read_u32(arizona->dev, "wlf,gpsw", &pdata->gpsw); + + pdata->jd_gpio5 = device_property_read_bool(arizona->dev, + "wlf,use-jd2"); + pdata->jd_gpio5_nopull = device_property_read_bool(arizona->dev, + "wlf,use-jd2-nopull"); + + ret = arizona_extcon_get_micd_configs(dev, arizona); + if (ret < 0) + dev_err(arizona->dev, "Failed to read micd configs: %d\n", ret); + + return 0; +} + +static int arizona_extcon_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_extcon_info *info; + unsigned int val; + unsigned int clamp_mode; + int jack_irq_fall, jack_irq_rise; + int ret, mode, i, j; + + if (!arizona->dapm || !arizona->dapm->card) + return -EPROBE_DEFER; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (!dev_get_platdata(arizona->dev)) + arizona_extcon_device_get_pdata(&pdev->dev, arizona); + + info->micvdd = devm_regulator_get(&pdev->dev, "MICVDD"); + if (IS_ERR(info->micvdd)) { + ret = PTR_ERR(info->micvdd); + dev_err(arizona->dev, "Failed to get MICVDD: %d\n", ret); + return ret; + } + + mutex_init(&info->lock); + info->arizona = arizona; + info->dev = &pdev->dev; + info->last_jackdet = ~(ARIZONA_MICD_CLAMP_STS | ARIZONA_JD1_STS); + INIT_DELAYED_WORK(&info->hpdet_work, arizona_hpdet_work); + INIT_DELAYED_WORK(&info->micd_detect_work, arizona_micd_detect); + INIT_DELAYED_WORK(&info->micd_timeout_work, arizona_micd_timeout_work); + platform_set_drvdata(pdev, info); + + switch (arizona->type) { + case WM5102: + switch (arizona->rev) { + case 0: + info->micd_reva = true; + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 1; + break; + } + break; + case WM5110: + case WM8280: + switch (arizona->rev) { + case 0 ... 2: + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + } + break; + case WM8998: + case WM1814: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + default: + break; + } + + info->edev = devm_extcon_dev_allocate(&pdev->dev, arizona_cable); + if (IS_ERR(info->edev)) { + dev_err(&pdev->dev, "failed to allocate extcon device\n"); + return -ENOMEM; + } + + ret = devm_extcon_dev_register(&pdev->dev, info->edev); + if (ret < 0) { + dev_err(arizona->dev, "extcon_dev_register() failed: %d\n", + ret); + return ret; + } + + info->input = devm_input_allocate_device(&pdev->dev); + if (!info->input) { + dev_err(arizona->dev, "Can't allocate input dev\n"); + ret = -ENOMEM; + return ret; + } + + info->input->name = "Headset"; + info->input->phys = "arizona/extcon"; + + if (!pdata->micd_timeout) + pdata->micd_timeout = DEFAULT_MICD_TIMEOUT; + + if (pdata->num_micd_configs) { + info->micd_modes = pdata->micd_configs; + info->micd_num_modes = pdata->num_micd_configs; + } else { + info->micd_modes = micd_default_modes; + info->micd_num_modes = ARRAY_SIZE(micd_default_modes); + } + + if (arizona->pdata.gpsw > 0) + regmap_update_bits(arizona->regmap, ARIZONA_GP_SWITCH_1, + ARIZONA_SW1_MODE_MASK, arizona->pdata.gpsw); + + if (pdata->micd_pol_gpio > 0) { + if (info->micd_modes[0].gpio) + mode = GPIOF_OUT_INIT_HIGH; + else + mode = GPIOF_OUT_INIT_LOW; + + ret = devm_gpio_request_one(&pdev->dev, pdata->micd_pol_gpio, + mode, "MICD polarity"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + pdata->micd_pol_gpio, ret); + return ret; + } + + info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio); + } else { + if (info->micd_modes[0].gpio) + mode = GPIOD_OUT_HIGH; + else + mode = GPIOD_OUT_LOW; + + /* We can't use devm here because we need to do the get + * against the MFD device, as that is where the of_node + * will reside, but if we devm against that the GPIO + * will not be freed if the extcon driver is unloaded. + */ + info->micd_pol_gpio = gpiod_get_optional(arizona->dev, + "wlf,micd-pol", + GPIOD_OUT_LOW); + if (IS_ERR(info->micd_pol_gpio)) { + ret = PTR_ERR(info->micd_pol_gpio); + dev_err(arizona->dev, + "Failed to get microphone polarity GPIO: %d\n", + ret); + return ret; + } + } + + if (arizona->pdata.hpdet_id_gpio > 0) { + ret = devm_gpio_request_one(&pdev->dev, + arizona->pdata.hpdet_id_gpio, + GPIOF_OUT_INIT_LOW, + "HPDET"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + arizona->pdata.hpdet_id_gpio, ret); + goto err_gpio; + } + } + + if (arizona->pdata.micd_bias_start_time) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK, + arizona->pdata.micd_bias_start_time + << ARIZONA_MICD_BIAS_STARTTIME_SHIFT); + + if (arizona->pdata.micd_rate) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_RATE_MASK, + arizona->pdata.micd_rate + << ARIZONA_MICD_RATE_SHIFT); + + switch (arizona->pdata.micd_dbtime) { + case MICD_DBTIME_FOUR_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, + ARIZONA_MICD_DBTIME); + break; + case MICD_DBTIME_TWO_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, 0); + break; + default: + break; + } + + BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) < + ARIZONA_NUM_MICD_BUTTON_LEVELS); + + if (arizona->pdata.num_micd_ranges) { + info->micd_ranges = pdata->micd_ranges; + info->num_micd_ranges = pdata->num_micd_ranges; + } else { + info->micd_ranges = micd_default_ranges; + info->num_micd_ranges = ARRAY_SIZE(micd_default_ranges); + } + + if (arizona->pdata.num_micd_ranges > ARIZONA_MAX_MICD_RANGE) { + dev_err(arizona->dev, "Too many MICD ranges: %d\n", + arizona->pdata.num_micd_ranges); + } + + if (info->num_micd_ranges > 1) { + for (i = 1; i < info->num_micd_ranges; i++) { + if (info->micd_ranges[i - 1].max > + info->micd_ranges[i].max) { + dev_err(arizona->dev, + "MICD ranges must be sorted\n"); + ret = -EINVAL; + goto err_gpio; + } + } + } + + /* Disable all buttons by default */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + ARIZONA_MICD_LVL_SEL_MASK, 0x81); + + /* Set up all the buttons the user specified */ + for (i = 0; i < info->num_micd_ranges; i++) { + for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++) + if (arizona_micd_levels[j] >= info->micd_ranges[i].max) + break; + + if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) { + dev_err(arizona->dev, "Unsupported MICD level %d\n", + info->micd_ranges[i].max); + ret = -EINVAL; + goto err_gpio; + } + + dev_dbg(arizona->dev, "%d ohms for MICD threshold %d\n", + arizona_micd_levels[j], i); + + arizona_micd_set_level(arizona, i, j); + input_set_capability(info->input, EV_KEY, + info->micd_ranges[i].key); + + /* Enable reporting of that range */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + 1 << i, 1 << i); + } + + /* Set all the remaining keys to a maximum */ + for (; i < ARIZONA_MAX_MICD_RANGE; i++) + arizona_micd_set_level(arizona, i, 0x3f); + + /* + * If we have a clamp use it, activating in conjunction with + * GPIO5 if that is connected for jack detect operation. + */ + if (info->micd_clamp) { + if (arizona->pdata.jd_gpio5) { + /* Put the GPIO into input mode with optional pull */ + val = 0xc101; + if (arizona->pdata.jd_gpio5_nopull) + val &= ~ARIZONA_GPN_PU; + + regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, + val); + + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL_GP5H; + } else { + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL; + } + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, clamp_mode); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB, + ARIZONA_MICD_CLAMP_DB); + } + + arizona_extcon_set_mode(info, 0); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + ret = arizona_request_irq(arizona, jack_irq_rise, + "JACKDET rise", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", + ret); + goto err_pm; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD rise IRQ wake: %d\n", + ret); + goto err_rise; + } + + ret = arizona_request_irq(arizona, jack_irq_fall, + "JACKDET fall", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JD fall IRQ: %d\n", ret); + goto err_rise_wake; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_fall, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD fall IRQ wake: %d\n", + ret); + goto err_fall; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_MICDET, + "MICDET", arizona_micdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get MICDET IRQ: %d\n", ret); + goto err_fall_wake; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_HPDET, + "HPDET", arizona_hpdet_irq, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get HPDET IRQ: %d\n", ret); + goto err_micdet; + } + + arizona_clk32k_enable(arizona); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_JD1_DB, ARIZONA_JD1_DB); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, ARIZONA_JD1_ENA); + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) + dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", + ret); + + ret = input_register_device(info->input); + if (ret) { + dev_err(&pdev->dev, "Can't register input device: %d\n", ret); + goto err_hpdet; + } + + pm_runtime_put(&pdev->dev); + + return 0; + +err_hpdet: + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); +err_micdet: + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); +err_fall_wake: + arizona_set_irq_wake(arizona, jack_irq_fall, 0); +err_fall: + arizona_free_irq(arizona, jack_irq_fall, info); +err_rise_wake: + arizona_set_irq_wake(arizona, jack_irq_rise, 0); +err_rise: + arizona_free_irq(arizona, jack_irq_rise, info); +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); +err_gpio: + gpiod_put(info->micd_pol_gpio); + return ret; +} + +static int arizona_extcon_remove(struct platform_device *pdev) +{ + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + struct arizona *arizona = info->arizona; + int jack_irq_rise, jack_irq_fall; + bool change; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to disable micd on remove: %d\n", + ret); + } else if (change) { + regulator_disable(info->micvdd); + pm_runtime_put(info->dev); + } + + gpiod_put(info->micd_pol_gpio); + + pm_runtime_disable(&pdev->dev); + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + arizona_set_irq_wake(arizona, jack_irq_rise, 0); + arizona_set_irq_wake(arizona, jack_irq_fall, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); + arizona_free_irq(arizona, jack_irq_rise, info); + arizona_free_irq(arizona, jack_irq_fall, info); + cancel_delayed_work_sync(&info->hpdet_work); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, 0); + arizona_clk32k_disable(arizona); + + return 0; +} + +static struct platform_driver arizona_extcon_driver = { + .driver = { + .name = "arizona-extcon", + }, + .probe = arizona_extcon_probe, + .remove = arizona_extcon_remove, +}; + +module_platform_driver(arizona_extcon_driver); + +MODULE_DESCRIPTION("Arizona Extcon driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:extcon-arizona"); diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index ed85d0ceee3ba..d3d52310c9cc1 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -265,164 +265,83 @@ config DRM_SCHED tristate depends on DRM -source "drivers/gpu/drm/sysfb/Kconfig" +# Separate option as not all DRM drivers use it +config DRM_PANEL_BACKLIGHT_QUIRKS + tristate -source "drivers/gpu/drm/arm/Kconfig" +config DRM_LIB_RANDOM + bool + default n -source "drivers/gpu/drm/radeon/Kconfig" +config DRM_PRIVACY_SCREEN + bool + default n +# DRM driver Kconfig files, sorted +source "drivers/gpu/drm/adp/Kconfig" source "drivers/gpu/drm/amd/amdgpu/Kconfig" - -source "drivers/gpu/drm/nouveau/Kconfig" - -source "drivers/gpu/drm/nova/Kconfig" - -source "drivers/gpu/drm/i915/Kconfig" - -source "drivers/gpu/drm/xe/Kconfig" - -source "drivers/gpu/drm/kmb/Kconfig" - -config DRM_VGEM - tristate "Virtual GEM provider" - depends on DRM && MMU - select DRM_GEM_SHMEM_HELPER - help - Choose this option to get a virtual graphics memory manager, - as used by Mesa's software renderer for enhanced performance. - If M is selected the module will be called vgem. - -source "drivers/gpu/drm/vkms/Kconfig" - -source "drivers/gpu/drm/exynos/Kconfig" - -source "drivers/gpu/drm/rockchip/Kconfig" - -source "drivers/gpu/drm/vmwgfx/Kconfig" - -source "drivers/gpu/drm/gma500/Kconfig" - -source "drivers/gpu/drm/udl/Kconfig" - -source "drivers/gpu/drm/ast/Kconfig" - -source "drivers/gpu/drm/mgag200/Kconfig" - +source "drivers/gpu/drm/arm/Kconfig" source "drivers/gpu/drm/armada/Kconfig" - +source "drivers/gpu/drm/aspeed/Kconfig" +source "drivers/gpu/drm/ast/Kconfig" source "drivers/gpu/drm/atmel-hlcdc/Kconfig" - -source "drivers/gpu/drm/renesas/Kconfig" - -source "drivers/gpu/drm/sun4i/Kconfig" - -source "drivers/gpu/drm/omapdrm/Kconfig" - -source "drivers/gpu/drm/tilcdc/Kconfig" - -source "drivers/gpu/drm/qxl/Kconfig" - -source "drivers/gpu/drm/virtio/Kconfig" - -source "drivers/gpu/drm/msm/Kconfig" - -source "drivers/gpu/drm/fsl-dcu/Kconfig" - -source "drivers/gpu/drm/tegra/Kconfig" - -source "drivers/gpu/drm/stm/Kconfig" - -source "drivers/gpu/drm/panel/Kconfig" - source "drivers/gpu/drm/bridge/Kconfig" - -source "drivers/gpu/drm/sti/Kconfig" - -source "drivers/gpu/drm/imx/Kconfig" - -source "drivers/gpu/drm/ingenic/Kconfig" - -source "drivers/gpu/drm/v3d/Kconfig" - -source "drivers/gpu/drm/vc4/Kconfig" - -source "drivers/gpu/drm/loongson/Kconfig" - source "drivers/gpu/drm/etnaviv/Kconfig" - +source "drivers/gpu/drm/exynos/Kconfig" +source "drivers/gpu/drm/fsl-dcu/Kconfig" +source "drivers/gpu/drm/gma500/Kconfig" +source "drivers/gpu/drm/gud/Kconfig" source "drivers/gpu/drm/hisilicon/Kconfig" - +source "drivers/gpu/drm/hyperv/Kconfig" +source "drivers/gpu/drm/i915/Kconfig" +source "drivers/gpu/drm/imagination/Kconfig" +source "drivers/gpu/drm/imx/Kconfig" +source "drivers/gpu/drm/ingenic/Kconfig" +source "drivers/gpu/drm/kmb/Kconfig" +source "drivers/gpu/drm/lima/Kconfig" source "drivers/gpu/drm/logicvc/Kconfig" - +source "drivers/gpu/drm/loongson/Kconfig" +source "drivers/gpu/drm/mcde/Kconfig" source "drivers/gpu/drm/mediatek/Kconfig" - -source "drivers/gpu/drm/mxsfb/Kconfig" - source "drivers/gpu/drm/meson/Kconfig" - -source "drivers/gpu/drm/tiny/Kconfig" - -source "drivers/gpu/drm/pl111/Kconfig" - -source "drivers/gpu/drm/tve200/Kconfig" - -source "drivers/gpu/drm/xen/Kconfig" - -source "drivers/gpu/drm/vboxvideo/Kconfig" - -source "drivers/gpu/drm/lima/Kconfig" - +source "drivers/gpu/drm/mgag200/Kconfig" +source "drivers/gpu/drm/msm/Kconfig" +source "drivers/gpu/drm/mxsfb/Kconfig" +source "drivers/gpu/drm/nouveau/Kconfig" +source "drivers/gpu/drm/nova/Kconfig" +source "drivers/gpu/drm/omapdrm/Kconfig" +source "drivers/gpu/drm/panel/Kconfig" source "drivers/gpu/drm/panfrost/Kconfig" - source "drivers/gpu/drm/panthor/Kconfig" - -source "drivers/gpu/drm/aspeed/Kconfig" - -source "drivers/gpu/drm/mcde/Kconfig" - -source "drivers/gpu/drm/tidss/Kconfig" - -source "drivers/gpu/drm/adp/Kconfig" - -source "drivers/gpu/drm/xlnx/Kconfig" - -source "drivers/gpu/drm/gud/Kconfig" - +source "drivers/gpu/drm/pl111/Kconfig" +source "drivers/gpu/drm/qxl/Kconfig" +source "drivers/gpu/drm/radeon/Kconfig" +source "drivers/gpu/drm/renesas/Kconfig" +source "drivers/gpu/drm/rockchip/Kconfig" source "drivers/gpu/drm/sitronix/Kconfig" - source "drivers/gpu/drm/solomon/Kconfig" - source "drivers/gpu/drm/sprd/Kconfig" - -source "drivers/gpu/drm/imagination/Kconfig" - +source "drivers/gpu/drm/sti/Kconfig" +source "drivers/gpu/drm/stm/Kconfig" +source "drivers/gpu/drm/sun4i/Kconfig" +source "drivers/gpu/drm/sysfb/Kconfig" +source "drivers/gpu/drm/tegra/Kconfig" +source "drivers/gpu/drm/tidss/Kconfig" +source "drivers/gpu/drm/tilcdc/Kconfig" +source "drivers/gpu/drm/tiny/Kconfig" +source "drivers/gpu/drm/tve200/Kconfig" source "drivers/gpu/drm/tyr/Kconfig" - -config DRM_HYPERV - tristate "DRM Support for Hyper-V synthetic video device" - depends on DRM && PCI && HYPERV_VMBUS - select DRM_CLIENT_SELECTION - select DRM_KMS_HELPER - select DRM_GEM_SHMEM_HELPER - help - This is a KMS driver for Hyper-V synthetic video device. Choose this - option if you would like to enable drm driver for Hyper-V virtual - machine. Unselect Hyper-V framebuffer driver (CONFIG_FB_HYPERV) so - that DRM driver is used by default. - - If M is selected the module will be called hyperv_drm. - -# Separate option as not all DRM drivers use it -config DRM_PANEL_BACKLIGHT_QUIRKS - tristate - -config DRM_LIB_RANDOM - bool - default n - -config DRM_PRIVACY_SCREEN - bool - default n +source "drivers/gpu/drm/udl/Kconfig" +source "drivers/gpu/drm/v3d/Kconfig" +source "drivers/gpu/drm/vboxvideo/Kconfig" +source "drivers/gpu/drm/vc4/Kconfig" +source "drivers/gpu/drm/vgem/Kconfig" +source "drivers/gpu/drm/virtio/Kconfig" +source "drivers/gpu/drm/vkms/Kconfig" +source "drivers/gpu/drm/vmwgfx/Kconfig" +source "drivers/gpu/drm/xe/Kconfig" +source "drivers/gpu/drm/xen/Kconfig" +source "drivers/gpu/drm/xlnx/Kconfig" endif diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index d261917174280..0c21029c446fd 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -110,7 +110,8 @@ obj-$(CONFIG_DRM_GPUVM) += drm_gpuvm.o drm_gpusvm_helper-y := \ drm_gpusvm.o drm_gpusvm_helper-$(CONFIG_ZONE_DEVICE) += \ - drm_pagemap.o + drm_pagemap.o\ + drm_pagemap_util.o obj-$(CONFIG_DRM_GPUSVM) += drm_gpusvm_helper.o diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index c88760fb52ea5..8eb09c66509da 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,9 +23,9 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -FULL_AMD_PATH=$(src)/.. -DISPLAY_FOLDER_NAME=display -FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) +FULL_AMD_PATH := $(src)/.. +DISPLAY_FOLDER_NAME := display +FULL_AMD_DISPLAY_PATH := $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ @@ -47,7 +47,7 @@ subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror amdgpu-y := amdgpu_drv.o # add KMS driver -amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ +amdgpu-y += amdgpu_device.o amdgpu_reg_access.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ @@ -61,7 +61,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \ amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \ amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o amdgpu_hdp.o \ - amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ + amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_sem.o amdgpu_gmc.o \ amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ amdgpu_fw_attestation.o amdgpu_securedisplay.o \ @@ -86,7 +86,7 @@ amdgpu-y += \ nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \ sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \ nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \ - cyan_skillfish_reg_init.o + cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o # add DF block amdgpu-y += \ @@ -104,7 +104,8 @@ amdgpu-y += \ gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \ mmhub_v1_7.o gfxhub_v3_0.o mmhub_v3_0.o mmhub_v3_0_2.o gmc_v11_0.o \ mmhub_v3_0_1.o gfxhub_v3_0_3.o gfxhub_v1_2.o mmhub_v1_8.o mmhub_v3_3.o \ - gfxhub_v11_5_0.o mmhub_v4_1_0.o gfxhub_v12_0.o gmc_v12_0.o + gfxhub_v11_5_0.o mmhub_v4_1_0.o gfxhub_v12_0.o gmc_v12_0.o \ + mmhub_v4_2_0.o gfxhub_v12_1.o gmc_v12_1.o # add UMC block amdgpu-y += \ @@ -134,7 +135,9 @@ amdgpu-y += \ psp_v12_0.o \ psp_v13_0.o \ psp_v13_0_4.o \ - psp_v14_0.o + psp_v14_0.o \ + psp_v15_0.o \ + psp_v15_0_8.o # add DCE block amdgpu-y += \ @@ -156,7 +159,9 @@ amdgpu-y += \ gfx_v11_0_3.o \ imu_v11_0_3.o \ gfx_v12_0.o \ - imu_v12_0.o + gfx_v12_1.o \ + imu_v12_0.o \ + imu_v12_1.o # add async DMA block amdgpu-y += \ @@ -169,13 +174,15 @@ amdgpu-y += \ sdma_v5_0.o \ sdma_v5_2.o \ sdma_v6_0.o \ - sdma_v7_0.o + sdma_v7_0.o \ + sdma_v7_1.o # add MES block amdgpu-y += \ amdgpu_mes.o \ mes_v11_0.o \ mes_v12_0.o \ + mes_v12_1.o # add GFX userqueue support amdgpu-y += mes_userqueue.o @@ -206,6 +213,7 @@ amdgpu-y += \ vcn_v4_0_5.o \ vcn_v5_0_0.o \ vcn_v5_0_1.o \ + vcn_v5_0_2.o \ amdgpu_jpeg.o \ jpeg_v1_0.o \ jpeg_v2_0.o \ @@ -215,7 +223,9 @@ amdgpu-y += \ jpeg_v4_0_3.o \ jpeg_v4_0_5.o \ jpeg_v5_0_0.o \ - jpeg_v5_0_1.o + jpeg_v5_0_1.o \ + jpeg_v5_0_2.o \ + jpeg_v5_3_0.o # add VPE block amdgpu-y += \ @@ -244,7 +254,9 @@ amdgpu-y += \ smuio_v13_0.o \ smuio_v13_0_3.o \ smuio_v13_0_6.o \ - smuio_v14_0_2.o + smuio_v14_0_2.o \ + smuio_v15_0_0.o \ + smuio_v15_0_8.o # add reset block amdgpu-y += \ @@ -275,7 +287,9 @@ amdgpu-y += \ amdgpu_amdkfd_gfx_v10.o \ amdgpu_amdkfd_gfx_v10_3.o \ amdgpu_amdkfd_gfx_v11.o \ - amdgpu_amdkfd_gfx_v12.o + amdgpu_amdkfd_gfx_v12.o \ + amdgpu_amdkfd_gfx_v12_1.o \ + amdgpu_amdkfd_rlc_spm.o ifneq ($(CONFIG_DRM_AMDGPU_CIK),) amdgpu-y += amdgpu_amdkfd_gfx_v7.o @@ -302,7 +316,7 @@ endif amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o -amdgpu-$(CONFIG_HMM_MIRROR) += amdgpu_hmm.o +amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_hmm.o include $(FULL_AMD_PATH)/pm/Makefile @@ -310,7 +324,7 @@ amdgpu-y += $(AMD_POWERPLAY_FILES) ifneq ($(CONFIG_DRM_AMD_DC),) -RELATIVE_AMD_DISPLAY_PATH = ../$(DISPLAY_FOLDER_NAME) +RELATIVE_AMD_DISPLAY_PATH := ../$(DISPLAY_FOLDER_NAME) include $(FULL_AMD_DISPLAY_PATH)/Makefile amdgpu-y += $(AMD_DISPLAY_FILES) @@ -329,5 +343,8 @@ AMD_GPU_RAS_PATH := ../ras AMD_GPU_RAS_FULL_PATH := $(FULL_AMD_PATH)/ras include $(AMD_GPU_RAS_FULL_PATH)/Makefile amdgpu-y += $(AMD_GPU_RAS_FILES) +include $(FULL_AMD_PATH)/backport/Makefile obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o + +CFLAGS_amdgpu_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b20a06abb65dd..f08de86bee0e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -34,12 +34,6 @@ #define pr_fmt(fmt) "amdgpu: " fmt -#ifdef dev_fmt -#undef dev_fmt -#endif - -#define dev_fmt(fmt) "amdgpu: " fmt - #include "amdgpu_ctx.h" #include @@ -74,6 +68,7 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" +#include "amdgpu_sem.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "amdgpu_uvd.h" @@ -87,6 +82,7 @@ #include "amdgpu_sdma.h" #include "amdgpu_lsdma.h" #include "amdgpu_nbio.h" +#include "amdgpu_reg_access.h" #include "amdgpu_hdp.h" #include "amdgpu_dm.h" #include "amdgpu_virt.h" @@ -116,6 +112,7 @@ #include "amdgpu_reg_state.h" #include "amdgpu_userq.h" #include "amdgpu_eviction_fence.h" +#include "amdgpu_ip.h" #if defined(CONFIG_DRM_AMD_ISP) #include "amdgpu_isp.h" #endif @@ -191,6 +188,8 @@ extern int amdgpu_exp_hw_support; extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; +extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; @@ -222,14 +221,13 @@ extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; extern int amdgpu_async_gfx_ring; extern int amdgpu_mcbp; extern int amdgpu_discovery; -extern int amdgpu_mes; extern int amdgpu_mes_log_enable; -extern int amdgpu_mes_kiq; extern int amdgpu_uni_mes; extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; extern int amdgpu_use_xgmi_p2p; +extern bool pcie_p2p; extern int amdgpu_mtype_local; extern int amdgpu_enforce_isolation; #ifdef CONFIG_HSA_AMD @@ -244,9 +242,6 @@ static const bool __maybe_unused debug_evictions; /* = false */ static const bool __maybe_unused no_system_mem_limit; static const int __maybe_unused halt_if_hws_hang; #endif -#ifdef CONFIG_HSA_AMD_P2P -extern bool pcie_p2p; -#endif extern int amdgpu_tmz; extern int amdgpu_reset_method; @@ -333,6 +328,7 @@ struct kfd_vm_fault_info; struct amdgpu_hive_info; struct amdgpu_reset_context; struct amdgpu_reset_control; +struct amdgpu_coredump_info; enum amdgpu_cp_irq { AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, @@ -360,63 +356,11 @@ enum amdgpu_kiq_irq { AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, AMDGPU_CP_KIQ_IRQ_LAST }; +#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */ #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ #define MAX_KIQ_REG_TRY 1000 -int amdgpu_device_ip_set_clockgating_state(void *dev, - enum amd_ip_block_type block_type, - enum amd_clockgating_state state); -int amdgpu_device_ip_set_powergating_state(void *dev, - enum amd_ip_block_type block_type, - enum amd_powergating_state state); -void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, - u64 *flags); -int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type); -bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, - enum amd_ip_block_type block_type); -bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, - enum amd_ip_block_type block_type); -int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); - -int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); - -#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM - -struct amdgpu_ip_block_status { - bool valid; - bool sw; - bool hw; - bool late_initialized; - bool hang; -}; - -struct amdgpu_ip_block_version { - const enum amd_ip_block_type type; - const u32 major; - const u32 minor; - const u32 rev; - const struct amd_ip_funcs *funcs; -}; - -struct amdgpu_ip_block { - struct amdgpu_ip_block_status status; - const struct amdgpu_ip_block_version *version; - struct amdgpu_device *adev; -}; - -int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, - enum amd_ip_block_type type, - u32 major, u32 minor); - -struct amdgpu_ip_block * -amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, - enum amd_ip_block_type type); - -int amdgpu_device_ip_block_add(struct amdgpu_device *adev, - const struct amdgpu_ip_block_version *ip_block_version); - /* * BIOS. */ @@ -443,6 +387,8 @@ struct amdgpu_clock { uint32_t max_pixel_clock; }; +extern const struct dma_buf_ops amdgpu_dmabuf_ops; + /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their @@ -506,6 +452,8 @@ struct amdgpu_fpriv { struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; struct amdgpu_userq_mgr userq_mgr; + spinlock_t sem_handles_lock; + struct idr sem_handles; /* Eviction fence infra */ struct amdgpu_eviction_fence_mgr evf_mgr; @@ -722,6 +670,9 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + /* VRAM scratch page for HDP bug, default vram page */ struct amdgpu_mem_scratch { struct amdgpu_bo *robj; @@ -738,96 +689,26 @@ void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); /* * Core structure, functions and helpers. */ -typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); -typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); - -typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device*, uint64_t); -typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device*, uint64_t, uint32_t); - -typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); -typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); - -typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device*, uint64_t); -typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device*, uint64_t, uint64_t); - -typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); -typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); - struct amdgpu_mmio_remap { u32 reg_offset; resource_size_t bus_addr; struct amdgpu_bo *bo; }; -/* Define the HW IP blocks will be used in driver , add more if necessary */ -enum amd_hw_ip_block_type { - GC_HWIP = 1, - HDP_HWIP, - SDMA0_HWIP, - SDMA1_HWIP, - SDMA2_HWIP, - SDMA3_HWIP, - SDMA4_HWIP, - SDMA5_HWIP, - SDMA6_HWIP, - SDMA7_HWIP, - LSDMA_HWIP, - MMHUB_HWIP, - ATHUB_HWIP, - NBIO_HWIP, - MP0_HWIP, - MP1_HWIP, - UVD_HWIP, - VCN_HWIP = UVD_HWIP, - JPEG_HWIP = VCN_HWIP, - VCN1_HWIP, - VCE_HWIP, - VPE_HWIP, - DF_HWIP, - DCE_HWIP, - OSSSYS_HWIP, - SMUIO_HWIP, - PWR_HWIP, - NBIF_HWIP, - THM_HWIP, - CLK_HWIP, - UMC_HWIP, - RSMU_HWIP, - XGMI_HWIP, - DCI_HWIP, - PCIE_HWIP, - ISP_HWIP, - MAX_HWIP -}; -#define HWIP_MAX_INSTANCE 44 - -#define HW_ID_MAX 300 -#define IP_VERSION_FULL(mj, mn, rv, var, srev) \ - (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) -#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) -#define IP_VERSION_MAJ(ver) ((ver) >> 24) -#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) -#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) -#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) -#define IP_VERSION_SUBREV(ver) ((ver) & 0xF) -#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) - -struct amdgpu_ip_map_info { - /* Map of logical to actual dev instances/mask */ - uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; - int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, - enum amd_hw_ip_block_type block, - int8_t inst); - uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, - enum amd_hw_ip_block_type block, - uint32_t mask); +struct amdgpu_direct_gma { + /* reserved in visible vram*/ + struct amdgpu_bo *dgma_bo; + atomic64_t vram_usage; + /* reserved in gart */ + atomic64_t gart_usage; }; enum amdgpu_uid_type { AMDGPU_UID_TYPE_XCD, AMDGPU_UID_TYPE_AID, AMDGPU_UID_TYPE_SOC, + AMDGPU_UID_TYPE_MID, AMDGPU_UID_TYPE_MAX }; @@ -838,6 +719,38 @@ struct amdgpu_uid { struct amdgpu_device *adev; }; +#define MAX_UMA_OPTION_NAME 28 +#define MAX_UMA_OPTION_ENTRIES 19 + +#define AMDGPU_UMA_FLAG_AUTO BIT(1) +#define AMDGPU_UMA_FLAG_CUSTOM BIT(0) + +/** + * struct amdgpu_uma_carveout_option - single UMA carveout option + * @name: Name of the carveout option + * @memory_carved_mb: Amount of memory carved in MB + * @flags: ATCS flags supported by this option + */ +struct amdgpu_uma_carveout_option { + char name[MAX_UMA_OPTION_NAME]; + uint32_t memory_carved_mb; + uint8_t flags; +}; + +/** + * struct amdgpu_uma_carveout_info - table of available UMA carveout options + * @num_entries: Number of available options + * @uma_option_index: The index of the option currently applied + * @update_lock: Lock to serialize changes to the option + * @entries: The array of carveout options + */ +struct amdgpu_uma_carveout_info { + uint8_t num_entries; + uint8_t uma_option_index; + struct mutex update_lock; + struct amdgpu_uma_carveout_option entries[MAX_UMA_OPTION_ENTRIES]; +}; + struct amd_powerplay { void *pp_handle; const struct amd_pm_funcs *pp_funcs; @@ -882,6 +795,12 @@ struct amd_powerplay { (rid == 0x01) || \ (rid == 0x10)))) +enum amdgpu_mqd_update_flag { + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ +}; + struct amdgpu_mqd_prop { uint64_t mqd_gpu_addr; uint64_t hqd_base_gpu_addr; @@ -893,6 +812,7 @@ struct amdgpu_mqd_prop { uint64_t eop_gpu_addr; uint32_t hqd_pipe_priority; uint32_t hqd_queue_priority; + uint32_t mqd_stride_size; bool allow_tunneling; bool hqd_active; uint64_t shadow_addr; @@ -901,6 +821,10 @@ struct amdgpu_mqd_prop { uint64_t fence_address; bool tmz_queue; bool kernel_queue; + uint32_t *cu_mask; + uint32_t cu_mask_count; + uint32_t cu_flags; + bool is_user_cu_masked; }; struct amdgpu_mqd { @@ -989,6 +913,9 @@ struct amdgpu_device { uint32_t bios_scratch_reg_offset; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; + /* Direct GMA */ + struct amdgpu_direct_gma direct_gma; + /* Register/doorbell mmio */ resource_size_t rmmio_base; resource_size_t rmmio_size; @@ -996,42 +923,8 @@ struct amdgpu_device { /* protects concurrent MM_INDEX/DATA based register access */ spinlock_t mmio_idx_lock; struct amdgpu_mmio_remap rmmio_remap; - /* protects concurrent SMC based register access */ - spinlock_t smc_idx_lock; - amdgpu_rreg_t smc_rreg; - amdgpu_wreg_t smc_wreg; - /* protects concurrent PCIE register access */ - spinlock_t pcie_idx_lock; - amdgpu_rreg_t pcie_rreg; - amdgpu_wreg_t pcie_wreg; - amdgpu_rreg_t pciep_rreg; - amdgpu_wreg_t pciep_wreg; - amdgpu_rreg_ext_t pcie_rreg_ext; - amdgpu_wreg_ext_t pcie_wreg_ext; - amdgpu_rreg64_t pcie_rreg64; - amdgpu_wreg64_t pcie_wreg64; - amdgpu_rreg64_ext_t pcie_rreg64_ext; - amdgpu_wreg64_ext_t pcie_wreg64_ext; - /* protects concurrent UVD register access */ - spinlock_t uvd_ctx_idx_lock; - amdgpu_rreg_t uvd_ctx_rreg; - amdgpu_wreg_t uvd_ctx_wreg; - /* protects concurrent DIDT register access */ - spinlock_t didt_idx_lock; - amdgpu_rreg_t didt_rreg; - amdgpu_wreg_t didt_wreg; - /* protects concurrent gc_cac register access */ - spinlock_t gc_cac_idx_lock; - amdgpu_rreg_t gc_cac_rreg; - amdgpu_wreg_t gc_cac_wreg; - /* protects concurrent se_cac register access */ - spinlock_t se_cac_idx_lock; - amdgpu_rreg_t se_cac_rreg; - amdgpu_wreg_t se_cac_wreg; - /* protects concurrent ENDPOINT (audio) register access */ - spinlock_t audio_endpt_idx_lock; - amdgpu_block_rreg_t audio_endpt_rreg; - amdgpu_block_wreg_t audio_endpt_wreg; + /* Indirect register access blocks */ + struct amdgpu_reg_access reg; struct amdgpu_doorbell doorbell; /* clock/pll info */ @@ -1089,6 +982,7 @@ struct amdgpu_device { bool ib_pool_ready; struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; + struct workqueue_struct *timeout_wq; /* interrupts */ struct amdgpu_irq irq; @@ -1177,6 +1071,7 @@ struct amdgpu_device { * in the EOP interrupt handler to signal the particular user * queue fence. */ +#ifdef HAVE_STRUCT_XARRAY struct xarray userq_xa; /** * @userq_doorbell_xa: Global user queue map (doorbell index → queue) @@ -1184,6 +1079,10 @@ struct amdgpu_device { * Value: struct amdgpu_usermode_queue */ struct xarray userq_doorbell_xa; +#else + struct idr userq_idr; + spinlock_t userq_lock; +#endif /* df */ struct amdgpu_df df; @@ -1231,7 +1130,9 @@ struct amdgpu_device { enum pp_mp1_state mp1_state; struct amdgpu_doorbell_index doorbell_index; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct mutex notifier_lock; +#endif int asic_reset_res; struct work_struct xgmi_reset_work; @@ -1277,6 +1178,11 @@ struct amdgpu_device { struct amdgpu_reset_domain *reset_domain; +#ifdef CONFIG_DEV_COREDUMP + struct amdgpu_coredump_info *coredump; + struct work_struct coredump_work; +#endif + struct mutex benchmark_mutex; bool scpm_enabled; @@ -1321,12 +1227,22 @@ struct amdgpu_device { struct work_struct userq_reset_work; struct amdgpu_uid *uid_info; + struct amdgpu_uma_carveout_info uma_info; + /* KFD * Must be last --ends in a flexible-array member. */ struct amdgpu_kfd_dev kfd; }; +/* + * MES FW uses address(mqd_addr + sizeof(struct mqd) + 3*sizeof(uint32_t)) + * as fence address and writes a 32 bit fence value to this address. + * Driver needs to allocate at least 4 DWs extra memory in addition to + * sizeof(struct mqd). Add 8 DWs and align to AMDGPU_GPU_PAGE_SIZE for safety. + */ +#define AMDGPU_MQD_SIZE_ALIGN(mqd_size) AMDGPU_GPU_PAGE_ALIGN(((mqd_size) + 32)) + static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, uint8_t ip, uint8_t inst) { @@ -1377,42 +1293,6 @@ size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, void *buf, size_t size, bool write); -uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, - uint32_t inst, uint32_t reg_addr, char reg_name[], - uint32_t expected_value, uint32_t mask); -uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags); -u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, - u64 reg_addr); -uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags, - uint32_t xcc_id); -void amdgpu_device_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags); -void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, - u64 reg_addr, u32 reg_data); -void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags, - uint32_t xcc_id); -void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, uint32_t xcc_id); -void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); -uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); - -u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, - u32 reg_addr); -u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, - u32 reg_addr); -u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, - u64 reg_addr); -void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, - u32 reg_addr, u32 reg_data); -void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, - u32 reg_addr, u64 reg_data); -void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, - u64 reg_addr, u64 reg_data); u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev); bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, enum amd_asic_type asic_type); @@ -1452,28 +1332,30 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) #define RREG32_XCC(reg, inst) amdgpu_device_xcc_rreg(adev, (reg), 0, inst) #define WREG32_XCC(reg, v, inst) amdgpu_device_xcc_wreg(adev, (reg), (v), 0, inst) -#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) -#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) -#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) -#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) -#define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg)) -#define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v)) -#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) -#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) -#define RREG64_PCIE_EXT(reg) adev->pcie_rreg64_ext(adev, (reg)) -#define WREG64_PCIE_EXT(reg, v) adev->pcie_wreg64_ext(adev, (reg), (v)) -#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) -#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) -#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) -#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) -#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) -#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) -#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) -#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) -#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) -#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) -#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) -#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) +#define RREG32_PCIE(reg) amdgpu_reg_pcie_rd32(adev, (reg)) +#define WREG32_PCIE(reg, v) amdgpu_reg_pcie_wr32(adev, (reg), (v)) +#define RREG32_PCIE_PORT(reg) amdgpu_reg_pciep_rd32(adev, (reg)) +#define WREG32_PCIE_PORT(reg, v) amdgpu_reg_pciep_wr32(adev, (reg), (v)) +#define RREG32_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd32(adev, (reg)) +#define WREG32_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr32(adev, (reg), (v)) +#define RREG64_PCIE(reg) amdgpu_reg_pcie_rd64(adev, (reg)) +#define WREG64_PCIE(reg, v) amdgpu_reg_pcie_wr64(adev, (reg), (v)) +#define RREG64_PCIE_EXT(reg) amdgpu_reg_pcie_ext_rd64(adev, (reg)) +#define WREG64_PCIE_EXT(reg, v) amdgpu_reg_pcie_ext_wr64(adev, (reg), (v)) +#define RREG32_SMC(reg) amdgpu_reg_smc_rd32(adev, (reg)) +#define WREG32_SMC(reg, v) amdgpu_reg_smc_wr32(adev, (reg), (v)) +#define RREG32_UVD_CTX(reg) amdgpu_reg_uvd_ctx_rd32(adev, (reg)) +#define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) +#define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) +#define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) +#define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) +#define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) +#define RREG32_SE_CAC(reg) amdgpu_reg_se_cac_rd32(adev, (reg)) +#define WREG32_SE_CAC(reg, v) amdgpu_reg_se_cac_wr32(adev, (reg), (v)) +#define RREG32_AUDIO_ENDPT(block, reg) \ + amdgpu_reg_audio_endpt_rd32(adev, (block), (reg)) +#define WREG32_AUDIO_ENDPT(block, reg, v) \ + amdgpu_reg_audio_endpt_wr32(adev, (block), (reg), (v)) #define WREG32_P(reg, val, mask) \ do { \ uint32_t tmp_ = RREG32(reg); \ @@ -1547,8 +1429,13 @@ int emu_soc_asic_init(struct amdgpu_device *adev); #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) -#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) -#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) +#define amdgpu_asic_supports_baco(adev) \ + ((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0) +#define amdgpu_asic_pre_asic_init(adev) \ + { \ + if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \ + (adev)->asic_funcs->pre_asic_init((adev)); \ + } #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) @@ -1574,7 +1461,14 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, u64 num_vis_bytes); +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); +#else +static inline int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) +{ + return 0; +} +#endif void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size); @@ -1598,10 +1492,6 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring); void amdgpu_device_halt(struct amdgpu_device *adev); -u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, - u32 reg); -void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, - u32 reg, u32 v); struct dma_fence *amdgpu_device_get_gang(struct amdgpu_device *adev); struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev, struct dma_fence *gang); @@ -1611,6 +1501,8 @@ struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev, bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev); ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring); ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset); +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, + const struct amdgpu_vm_pte_funcs *vm_pte_funcs); /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) @@ -1647,6 +1539,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); + int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); @@ -1688,12 +1581,14 @@ int amdgpu_acpi_init(struct amdgpu_device *adev); void amdgpu_acpi_fini(struct amdgpu_device *adev); bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); bool amdgpu_acpi_is_power_shift_control_supported(void); +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void); int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, u8 perf_req, bool advertise); int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state); int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, enum amdgpu_ss ss_state); +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type); int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, u64 *tmr_size); @@ -1722,6 +1617,7 @@ static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { re static inline void amdgpu_acpi_detect(void) { } static inline void amdgpu_acpi_release(void) { } static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } +static inline bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) { return false; } static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state) { return 0; } static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, @@ -1729,6 +1625,10 @@ static inline int amdgpu_acpi_smart_shift_update(struct amdgpu_device *adev, { return 0; } +static inline int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) +{ + return -EINVAL; +} static inline void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps) { } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index 9b31804491500..3f9b094e93a29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -641,6 +641,7 @@ static void aca_error_fini(struct aca_error *aerr) aca_bank_error_remove(aerr, bank_error); out_unlock: + mutex_unlock(&aerr->lock); mutex_destroy(&aerr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 381ef205b0dfb..80e0798ed8ec3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -87,9 +87,12 @@ #define ACP_TIMEOUT_LOOP 0x000000FF #define ACP_DEVS 4 #define ACP_SRC_ID 162 - static unsigned long acp_machine_id; +#ifndef DW_I2S_QUIRK_16BIT_IDX_OVERRIDE +#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) +#endif + enum { ACP_TILE_P1 = 0, ACP_TILE_P2, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index d31460a9e9582..11e4c5cbf8bae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -54,7 +54,11 @@ static const guid_t amd_xcc_dsm_guid = GUID_INIT(0x8267f5d5, 0xa556, 0x44f2, #define AMD_XCC_MAX_HID 24 +#ifdef HAVE_STRUCT_XARRAY struct xarray numa_info_xa; +#else +struct idr numa_info_idr; +#endif /* Encapsulates the XCD acpi object information */ struct amdgpu_acpi_xcc_info { @@ -116,7 +120,9 @@ struct amdgpu_atcs_functions { bool pcie_perf_req; bool pcie_dev_rdy; bool pcie_bus_width; + bool get_uma_size; bool power_shift_control; + bool set_uma_allocation_size; }; struct amdgpu_atcs { @@ -241,7 +247,8 @@ static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mas * (all asics). * returns 0 on success, error on failure. */ -static int amdgpu_atif_verify_interface(struct amdgpu_atif *atif) +static noinline_for_stack +int amdgpu_atif_verify_interface(struct amdgpu_atif *atif) { union acpi_object *info; struct atif_verify_interface output; @@ -286,7 +293,8 @@ static int amdgpu_atif_verify_interface(struct amdgpu_atif *atif) * where n is specified in the result if a notifier is used. * Returns 0 on success, error on failure. */ -static int amdgpu_atif_get_notification_params(struct amdgpu_atif *atif) +static noinline_for_stack +int amdgpu_atif_get_notification_params(struct amdgpu_atif *atif) { union acpi_object *info; struct amdgpu_atif_notification_cfg *n = &atif->notification_cfg; @@ -354,7 +362,8 @@ static int amdgpu_atif_get_notification_params(struct amdgpu_atif *atif) * * Returns 0 on success, error on failure. */ -static int amdgpu_atif_query_backlight_caps(struct amdgpu_atif *atif) +static noinline_for_stack +int amdgpu_atif_query_backlight_caps(struct amdgpu_atif *atif) { union acpi_object *info; struct atif_qbtc_output characteristics; @@ -587,7 +596,9 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas f->pcie_perf_req = mask & ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED; f->pcie_dev_rdy = mask & ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED; f->pcie_bus_width = mask & ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED; + f->get_uma_size = mask & ACPI_ATCS_GET_UMA_SIZE_SUPPORTED; f->power_shift_control = mask & ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED; + f->set_uma_allocation_size = mask & ACPI_ATCS_SET_UMA_ALLOCATION_SIZE_SUPPORTED; } /** @@ -600,7 +611,8 @@ static void amdgpu_atcs_parse_functions(struct amdgpu_atcs_functions *f, u32 mas * (all asics). * returns 0 on success, error on failure. */ -static int amdgpu_atcs_verify_interface(struct amdgpu_atcs *atcs) +static noinline_for_stack +int amdgpu_atcs_verify_interface(struct amdgpu_atcs *atcs) { union acpi_object *info; struct atcs_verify_interface output; @@ -664,6 +676,11 @@ bool amdgpu_acpi_is_power_shift_control_supported(void) return amdgpu_acpi_priv.atcs.functions.power_shift_control; } +bool amdgpu_acpi_is_set_uma_allocation_size_supported(void) +{ + return amdgpu_acpi_priv.atcs.functions.set_uma_allocation_size; +} + /** * amdgpu_acpi_pcie_notify_device_ready * @@ -740,7 +757,8 @@ int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, size = *(u16 *) info->buffer.pointer; if (size < 3) { - DRM_INFO("ATCS buffer is too small: %zu\n", size); + drm_info(adev_to_drm(adev), + "ATCS buffer is too small: %zu\n", size); kfree(info); return -EINVAL; } @@ -799,7 +817,7 @@ int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_POWER_SHIFT_CONTROL, ¶ms); if (!info) { - DRM_ERROR("ATCS PSC update failed\n"); + drm_err(adev_to_drm(adev), "ATCS PSC call failed\n"); return -EIO; } @@ -878,7 +896,11 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) struct amdgpu_numa_info *numa_info; int nid; +#ifdef HAVE_STRUCT_XARRAY numa_info = xa_load(&numa_info_xa, pxm); +#else + numa_info = idr_find(&numa_info_idr, pxm); +#endif if (!numa_info) { struct sysinfo info; @@ -897,13 +919,55 @@ static struct amdgpu_numa_info *amdgpu_acpi_get_numa_info(uint32_t pxm) } else { numa_info->size = amdgpu_acpi_get_numa_size(nid); } +#ifdef HAVE_STRUCT_XARRAY xa_store(&numa_info_xa, numa_info->pxm, numa_info, GFP_KERNEL); +#else + idr_alloc(&numa_info_idr, numa_info, numa_info->pxm, numa_info->pxm + 1, GFP_KERNEL); +#endif } return numa_info; } #endif +/** + * amdgpu_acpi_set_uma_allocation_size - Set Unified Memory Architecture allocation size via ACPI + * @adev: Pointer to the amdgpu_device structure + * @index: Index specifying the UMA allocation + * @type: Type of UMA allocation + * + * This function configures the UMA allocation size for the specified device + * using ACPI methods. The allocation is determined by the provided index and type. + * Returns 0 on success or a negative error code on failure. + */ +int amdgpu_acpi_set_uma_allocation_size(struct amdgpu_device *adev, u8 index, u8 type) +{ + struct atcs_set_uma_allocation_size_input atcs_input; + struct amdgpu_atcs *atcs = &amdgpu_acpi_priv.atcs; + struct acpi_buffer params; + union acpi_object *info; + + if (!amdgpu_acpi_is_set_uma_allocation_size_supported()) + return -EINVAL; + + atcs_input.size = sizeof(struct atcs_set_uma_allocation_size_input); + atcs_input.uma_size_index = index; + atcs_input.uma_size_type = type; + + params.length = sizeof(struct atcs_set_uma_allocation_size_input); + params.pointer = &atcs_input; + + info = amdgpu_atcs_call(atcs, ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE, ¶ms); + if (!info) { + drm_err(adev_to_drm(adev), "ATCS UMA allocation size update failed\n"); + return -EIO; + } + + kfree(info); + + return 0; +} + /** * amdgpu_acpi_get_node_id - obtain the NUMA node id for corresponding amdgpu * acpi device handle @@ -1089,7 +1153,8 @@ static int amdgpu_acpi_get_xcc_info(struct amdgpu_acpi_xcc_info *xcc_info, return ret; } -static int amdgpu_acpi_enumerate_xcc(void) +static noinline_for_stack +int amdgpu_acpi_enumerate_xcc(void) { struct amdgpu_acpi_dev_info *dev_info = NULL; struct amdgpu_acpi_xcc_info *xcc_info; @@ -1099,8 +1164,11 @@ static int amdgpu_acpi_enumerate_xcc(void) u32 sbdf; INIT_LIST_HEAD(&amdgpu_acpi_dev_list); +#ifdef HAVE_STRUCT_XARRAY xa_init(&numa_info_xa); - +#else + idr_init(&numa_info_idr); +#endif for (id = 0; id < AMD_XCC_MAX_HID; id++) { sprintf(hid, "%s%d", "AMD", AMD_XCC_HID_START + id); acpi_dev = acpi_dev_get_first_match_dev(hid, NULL, -1); @@ -1108,17 +1176,15 @@ static int amdgpu_acpi_enumerate_xcc(void) * one is not found, no need to check the rest. */ if (!acpi_dev) { - DRM_DEBUG_DRIVER("No matching acpi device found for %s", + DRM_DEBUG_DRIVER("No matching acpi device found for %s\n", hid); break; } xcc_info = kzalloc(sizeof(struct amdgpu_acpi_xcc_info), GFP_KERNEL); - if (!xcc_info) { - DRM_ERROR("Failed to allocate memory for xcc info\n"); + if (!xcc_info) return -ENOMEM; - } INIT_LIST_HEAD(&xcc_info->list); xcc_info->handle = acpi_device_handle(acpi_dev); @@ -1135,8 +1201,10 @@ static int amdgpu_acpi_enumerate_xcc(void) if (!dev_info) ret = amdgpu_acpi_dev_init(&dev_info, xcc_info, sbdf); - if (ret == -ENOMEM) + if (ret == -ENOMEM) { + kfree(xcc_info); return ret; + } if (!dev_info) { kfree(xcc_info); @@ -1387,7 +1455,11 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) return false; #if IS_ENABLED(CONFIG_SUSPEND) +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; +#else + return false; +#endif #else return true; #endif @@ -1456,10 +1528,17 @@ void amdgpu_acpi_release(void) struct amdgpu_numa_info *numa_info; unsigned long index; +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&numa_info_xa, index, numa_info) { kfree(numa_info); xa_erase(&numa_info_xa, index); } +#else + idr_for_each_entry(&numa_info_idr, numa_info, index) { + kfree(numa_info); + idr_remove(&numa_info_idr, index); + } +#endif if (list_empty(&amdgpu_acpi_dev_list)) return; @@ -1487,8 +1566,12 @@ void amdgpu_acpi_release(void) */ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return !(adev->flags & AMD_IS_APU) || (pm_suspend_target_state == PM_SUSPEND_MEM); +#else + return true; +#endif } /** @@ -1500,9 +1583,13 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) */ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE if (!(adev->flags & AMD_IS_APU) || (pm_suspend_target_state != PM_SUSPEND_TO_IDLE)) return false; +#else + return false; +#endif if (adev->asic_type < CHIP_RAVEN) return false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index a2879d2b7c8ec..21633497265a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -42,6 +42,7 @@ */ uint64_t amdgpu_amdkfd_total_mem_size; +extern bool pcie_p2p; static bool kfd_initialized; int amdgpu_amdkfd_init(void) @@ -248,13 +249,18 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); } +void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev) +{ + kgd2kfd_teardown_processes(adev); +} + void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc) { if (adev->kfd.dev) { if (adev->in_s0ix) kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); else - kgd2kfd_suspend(adev->kfd.dev, suspend_proc); + kgd2kfd_suspend(adev->kfd.dev, suspend_proc, true); } } @@ -275,7 +281,7 @@ int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc) void amdgpu_amdkfd_suspend_process(struct amdgpu_device *adev) { if (adev->kfd.dev) - kgd2kfd_suspend_process(adev->kfd.dev); + kgd2kfd_suspend_process(adev->kfd.dev, true); } int amdgpu_amdkfd_resume_process(struct amdgpu_device *adev) @@ -312,13 +318,12 @@ int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) { if (amdgpu_device_should_recover_gpu(adev)) - amdgpu_reset_domain_schedule(adev->reset_domain, - &adev->kfd.reset_work); + (void)amdgpu_reset_domain_schedule(adev->reset_domain, &adev->kfd.reset_work); } -int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, - void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool cp_mqd_gfx9) +int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, + u32 domain, void **mem_obj, uint64_t *gpu_addr, + void **cpu_ptr, bool cp_mqd_gfx9, bool is_uswc_mode) { struct amdgpu_bo *bo = NULL; struct amdgpu_bo_param bp; @@ -328,8 +333,12 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, memset(&bp, 0, sizeof(bp)); bp.size = size; bp.byte_align = PAGE_SIZE; - bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; + bp.domain = domain; + if (is_uswc_mode) + bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_CPU_GTT_USWC; + else + bp.flags = 0; bp.type = ttm_bo_type_kernel; bp.resv = NULL; bp.bo_ptr_size = sizeof(struct amdgpu_bo); @@ -351,7 +360,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, goto allocate_mem_reserve_bo_failed; } - r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + r = amdgpu_bo_pin(bo, domain); if (r) { dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); goto allocate_mem_pin_bo_failed; @@ -388,7 +397,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, return r; } -void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj) +void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj) { struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; @@ -582,6 +591,13 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, return r; } +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) +{ + + return ttm_resource_manager_used(&adev->mman.vram_mgr.manager) ? + ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) : 0; +} + int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) { int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : @@ -683,13 +699,13 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); if (ret) { - DRM_ERROR("amdgpu: failed to schedule IB.\n"); + drm_err(adev_to_drm(adev), "failed to schedule IB.\n"); goto err_ib_sched; } - /* Drop the initial kref_init count (see drm_sched_main as example) */ - dma_fence_put(f); ret = dma_fence_wait(f, false); + /* Drop the returned fence reference after the wait completes */ + dma_fence_put(f); err_ib_sched: amdgpu_job_free(job); @@ -714,9 +730,8 @@ void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) if (gfx_block != NULL) gfx_block->version->funcs->set_powergating_state((void *)gfx_block, state); } - amdgpu_dpm_switch_power_profile(adev, - PP_SMC_POWER_PROFILE_COMPUTE, - !idle); + (void)amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_COMPUTE, !idle); + } bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) @@ -897,7 +912,7 @@ bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) } /* Config CGTT_SQ_CLK_CTRL */ -int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) { int r; @@ -905,7 +920,7 @@ int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, if (!adev->kfd.init_complete) return 0; - r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, + r = psp_config_sq_perfmon(&adev->psp, xcc_id, core_override_enable, reg_override_enable, perfmon_override_enable); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 8bdfcde2029b5..ece4271b58359 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -37,7 +37,7 @@ #include "amdgpu_sync.h" #include "amdgpu_vm.h" #include "amdgpu_xcp.h" - +#include "kfd_topology.h" extern uint64_t amdgpu_amdkfd_total_mem_size; enum TLB_FLUSH_TYPE { @@ -70,8 +70,13 @@ struct kfd_mem_attachment { struct kgd_mem { struct mutex lock; struct amdgpu_bo *bo; + struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct amdgpu_hmm_range *range; +#else + struct page **user_pages; +#endif struct list_head attachments; /* protected by amdkfd_process_info.lock */ struct list_head validate_list; @@ -98,12 +103,14 @@ struct amdgpu_amdkfd_fence { spinlock_t lock; char timeline_name[TASK_COMM_LEN]; struct svm_range_bo *svm_bo; + uint16_t context_id; }; struct amdgpu_kfd_dev { struct kfd_dev *dev; int64_t vram_used[MAX_XCP]; uint64_t vram_used_aligned[MAX_XCP]; + atomic64_t vram_pinned; bool init_complete; struct work_struct reset_work; @@ -148,6 +155,8 @@ struct amdkfd_process_info { /* MMU-notifier related fields */ struct mutex notifier_lock; uint32_t evicted_bos; + /* kfd context id */ + u16 context_id; struct delayed_work restore_userptr_work; struct pid *pid; bool block_mmu_notifications; @@ -155,6 +164,7 @@ struct amdkfd_process_info { int amdgpu_amdkfd_init(void); void amdgpu_amdkfd_fini(void); +void amdgpu_amdkfd_teardown_processes(struct amdgpu_device *adev); void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool suspend_proc); int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool resume_proc); @@ -188,7 +198,8 @@ int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, struct mm_struct *mm, - struct svm_range_bo *svm_bo); + struct svm_range_bo *svm_bo, + u16 context_id); int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev); #if defined(CONFIG_DEBUG_FS) @@ -198,8 +209,12 @@ int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem); +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); +#endif int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, uint32_t domain, struct dma_fence *fence); @@ -222,8 +237,12 @@ void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) } static inline +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) +#endif { return 0; } @@ -236,10 +255,10 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, } #endif /* Shared API */ -int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, - void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool mqd_gfx9); -void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj); +int amdgpu_amdkfd_alloc_kernel_mem(struct amdgpu_device *adev, size_t size, + u32 domain, void **mem_obj, uint64_t *gpu_addr, + void **cpu_ptr, bool mqd_gfx9, bool is_uswc_mode); +void amdgpu_amdkfd_free_kernel_mem(struct amdgpu_device *adev, void **mem_obj); int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, void **mem_obj); void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); @@ -258,6 +277,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t *bo_size, void *metadata_buffer, size_t buffer_size, uint32_t *metadata_size, uint32_t *flags, int8_t *xcp_id); +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev); int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, uint32_t *payload); @@ -265,7 +285,7 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, u32 inst); int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); -int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); @@ -329,12 +349,61 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, struct dma_fence __rcu **ef); int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, struct kfd_vm_fault_info *info); + +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags); +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); + +/** + * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria + * @bo: Handle of buffer object being pinned + * @domain: Domain into which BO should be pinned + * + * - USERPTR BOs are UNPINNABLE and will return error + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count incremented. It is valid to PIN a BO multiple times + * + * Return: ZERO if successful in pinning, Non-Zero in case of error. + */ +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); + +/** + * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria + * @bo: Handle of buffer object being unpinned + * + * - Is a illegal request for USERPTR BOs and is ignored + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count decremented. Calls to UNPIN must balance calls to PIN + */ +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg); +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sg); + +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, + struct dma_buf *dmabuf, + struct kfd_ipc_obj *ipc_obj, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj, + uint32_t flags, + uint32_t *restore_handle); + void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); @@ -393,6 +462,13 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, int xcc_id, bool cntl); +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size); +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr); +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id); + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); #else @@ -404,10 +480,11 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) #endif /* KGD2KFD callbacks */ +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id); int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, - struct dma_fence *fence); + u16 context_id, struct dma_fence *fence); #if IS_ENABLED(CONFIG_HSA_AMD) int kgd2kfd_init(void); void kgd2kfd_exit(void); @@ -415,9 +492,9 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); bool kgd2kfd_device_init(struct kfd_dev *kfd, const struct kgd2kfd_shared_resources *gpu_resources); void kgd2kfd_device_exit(struct kfd_dev *kfd); -void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc); +void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force); int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc); -void kgd2kfd_suspend_process(struct kfd_dev *kfd); +void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force); int kgd2kfd_resume_process(struct kfd_dev *kfd); int kgd2kfd_pre_reset(struct kfd_dev *kfd, struct amdgpu_reset_context *reset_context); @@ -434,6 +511,8 @@ int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd); bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, bool retry_fault); +void kgd2kfd_lock_kfd(void); +void kgd2kfd_teardown_processes(struct amdgpu_device *adev); #else static inline int kgd2kfd_init(void) @@ -462,16 +541,16 @@ static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) { } -static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) +static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force) { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) { return 0; } -static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd) +static inline void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force) { } @@ -546,5 +625,13 @@ static inline bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct return false; } +static inline void kgd2kfd_lock_kfd(void) +{ +} + +static inline void kgd2kfd_teardown_processes(struct amdgpu_device *adev) +{ +} + #endif #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index 7e9f7a280c1b9..31314ed5bb0b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -26,6 +26,7 @@ #include "amdgpu_amdkfd_aldebaran.h" #include "gc/gc_9_4_2_offset.h" #include "gc/gc_9_4_2_sh_mask.h" +#include "soc15.h" #include /* @@ -163,6 +164,17 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch( return watch_address_cntl; } +static uint32_t kgd_aldebaran_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -193,5 +205,7 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 1105a09e55dc1..c9a4ef391f0d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -389,6 +389,18 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev, return 0; } + +static uint32_t kgd_arcturus_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 10, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -420,5 +432,7 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 1ef758ac5076e..31b8fa52b42fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -62,7 +62,8 @@ static atomic_t fence_seq = ATOMIC_INIT(0); struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, struct mm_struct *mm, - struct svm_range_bo *svm_bo) + struct svm_range_bo *svm_bo, + u16 context_id) { struct amdgpu_amdkfd_fence *fence; @@ -76,6 +77,7 @@ struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, get_task_comm(fence->timeline_name, current); spin_lock_init(&fence->lock); fence->svm_bo = svm_bo; + fence->context_id = context_id; dma_fence_init(&fence->base, &amdkfd_fence_ops, &fence->lock, context, atomic_inc_return(&fence_seq)); @@ -105,7 +107,7 @@ static const char *amdkfd_fence_get_timeline_name(struct dma_fence *f) { struct amdgpu_amdkfd_fence *fence = to_amdgpu_amdkfd_fence(f); - return fence->timeline_name; + return fence ? fence->timeline_name : NULL; } /** @@ -126,8 +128,12 @@ static bool amdkfd_fence_enable_signaling(struct dma_fence *f) if (dma_fence_is_signaled(f)) return true; + /* if fence->svm_bo is NULL, means this fence is created through + * init_kfd_vm() or amdgpu_amdkfd_gpuvm_restore_process_bos(). + * Therefore, this fence is amdgpu_amdkfd_fence->eviction_fence. + */ if (!fence->svm_bo) { - if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, f)) + if (!kgd2kfd_schedule_evict_and_restore_process(fence->mm, fence->context_id, f)) return true; } else { if (!svm_range_schedule_evict_svm_bo(fence)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index 89a45a9218f3f..a577e1ff00401 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -520,6 +520,60 @@ static uint32_t kgd_gfx_v9_4_3_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return is_active ? doorbell_off >> 2 : 0; } +static void kgd_gfx_v9_4_3_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) +{ + uint32_t sq_clk_ctrl; + + /* disable/enable SQ core override */ + amdgpu_amdkfd_config_sq_perfmon(adev, GET_INST(GC, inst), value, 0, 0); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + sq_clk_ctrl = RREG32_SOC15(GC, GET_INST(GC, inst), regCGTT_SQ_CLK_CTRL); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + dev_dbg(adev->dev, "sq clock control on instance [%d]: 0x%x\n", + GET_INST(GC, inst), sq_clk_ctrl); +} + +static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + +static uint32_t kgd_v9_4_3_setup_stoch_sampling(struct amdgpu_device *adev, + uint32_t compute_vmid_bitmap, + bool enable, + enum kfd_ioctl_pc_sample_type type, + uint64_t intval, + uint32_t inst) +{ + uint32_t value = 0; + + /* turn on all VMID for this instance */ + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, VMID_MASK, compute_vmid_bitmap); + + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, COUNT_INTVAL, ffs(intval >> 9)); + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, COUNT_SEL, type - 1); + value = REG_SET_FIELD(value, SQ_PERF_SNAPSHOT_CTRL, ENABLE, enable); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), regSQ_PERF_SNAPSHOT_CTRL, value); + mutex_unlock(&adev->grbm_idx_mutex); + + return 0; +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -555,5 +609,8 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v9_4_3_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_4_3_override_core_cg, + .setup_stoch_sampling = kgd_v9_4_3_setup_stoch_sampling, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c index e0ceab400b2da..3396a5bf31147 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12.c @@ -25,6 +25,8 @@ #include "gc/gc_12_0_0_offset.h" #include "gc/gc_12_0_0_sh_mask.h" #include "soc24.h" +#include "navi10_enum.h" + #include static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, @@ -367,6 +369,73 @@ static uint32_t kgd_gfx_v12_hqd_sdma_get_doorbell(struct amdgpu_device *adev, return 0; } +static uint32_t kgd_gfx_v12_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_debug_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_debug_hosttrap_status = + RREG32_SOC15(GC, GET_INST(GC, inst), regSQ_DEBUG_HOST_TRAP_STATUS); + + if (sq_debug_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_debug_hosttrap_status; +} + +/* + * gfx12 has no way to broadcast to all WGPs but only a single SIMD within + * that WGP. Here we broadcast to 1 wave-slot on all 4 SIMDs within all WGPs, + * so target_simd is not really used for gfx12. +*/ +static uint32_t kgd_v12_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t __always_unused *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_gfx_v12_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), regSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= 16; + } else { + dev_dbg(adev->dev, "PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } + return 0; +} + const struct kfd2kgd_calls gfx_v12_kfd2kgd = { .init_interrupts = init_interrupts_v12, .hqd_dump = hqd_dump_v12, @@ -380,5 +449,6 @@ const struct kfd2kgd_calls gfx_v12_kfd2kgd = { .set_wave_launch_mode = kgd_gfx_v12_set_wave_launch_mode, .set_address_watch = kgd_gfx_v12_set_address_watch, .clear_address_watch = kgd_gfx_v12_clear_address_watch, - .hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell + .hqd_sdma_get_doorbell = kgd_gfx_v12_hqd_sdma_get_doorbell, + .trigger_pc_sample_trap = kgd_v12_trigger_pc_sample_trap, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c new file mode 100644 index 0000000000000..bcb180f9d3ff8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v12_1.c @@ -0,0 +1,387 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu.h" +#include "amdgpu_amdkfd.h" +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "soc_v1_0.h" +#include + +static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, + uint32_t queue, uint32_t vmid, uint32_t inst) +{ + mutex_lock(&adev->srbm_mutex); + amdgpu_gfx_select_me_pipe_q(adev, mec, pipe, queue, vmid, inst); +} + +static void unlock_srbm(struct amdgpu_device *adev, uint32_t inst) +{ + amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0, inst); + mutex_unlock(&adev->srbm_mutex); +} + +static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, + uint32_t queue_id, uint32_t inst) +{ + uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); + + lock_srbm(adev, mec, pipe, queue_id, 0, inst); +} + +static void release_queue(struct amdgpu_device *adev, uint32_t inst) +{ + unlock_srbm(adev, inst); +} + +static int init_interrupts_v12_1(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst) +{ + uint32_t mec; + uint32_t pipe; + + mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; + pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); + + lock_srbm(adev, mec, pipe, 0, 0, inst); + + WREG32_SOC15(GC, GET_INST(GC, inst), regCPC_INT_CNTL, + CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | + CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); + + unlock_srbm(adev, inst); + + return 0; +} + +static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, + unsigned int engine_id, + unsigned int queue_id) +{ + uint32_t sdma_engine_reg_base = 0; + uint32_t sdma_rlc_reg_offset; + uint32_t dev_inst = GET_INST(SDMA0, engine_id); + + switch (dev_inst % adev->sdma.num_inst_per_xcc) { + case 0: + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, + dev_inst / adev->sdma.num_inst_per_xcc, + regSDMA0_SDMA_QUEUE0_RB_CNTL) - regSDMA0_SDMA_QUEUE0_RB_CNTL; + break; + case 1: + sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, + dev_inst / adev->sdma.num_inst_per_xcc, + regSDMA1_SDMA_QUEUE0_RB_CNTL) - regSDMA0_SDMA_QUEUE0_RB_CNTL; + break; + default: + BUG(); + } + + sdma_rlc_reg_offset = sdma_engine_reg_base + + queue_id * (regSDMA0_SDMA_QUEUE1_RB_CNTL - regSDMA0_SDMA_QUEUE0_RB_CNTL); + + pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, + queue_id, sdma_rlc_reg_offset); + + return sdma_rlc_reg_offset; +} + +static int hqd_dump_v12_1(struct amdgpu_device *adev, + uint32_t pipe_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) +{ + uint32_t i = 0, reg; +#define HQD_N_REGS 56 +#define DUMP_REG(addr) do { \ + if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ + break; \ + (*dump)[i][0] = (addr) << 2; \ + (*dump)[i++][1] = RREG32(addr); \ + } while (0) + + *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + if (*dump == NULL) + return -ENOMEM; + + acquire_queue(adev, pipe_id, queue_id, inst); + + for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); + reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI); reg++) + DUMP_REG(reg); + + release_queue(adev, inst); + + WARN_ON_ONCE(i != HQD_N_REGS); + *n_regs = i; + + return 0; +} + +static int hqd_sdma_dump_v12_1(struct amdgpu_device *adev, + uint32_t engine_id, uint32_t queue_id, + uint32_t (**dump)[2], uint32_t *n_regs) +{ + uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, + engine_id, queue_id); + uint32_t i = 0, reg; + + const uint32_t first_reg = regSDMA0_SDMA_QUEUE0_RB_CNTL; + const uint32_t last_reg = regSDMA0_SDMA_QUEUE0_CONTEXT_STATUS; +#undef HQD_N_REGS +#define HQD_N_REGS (last_reg - first_reg + 1) + + *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); + if (*dump == NULL) + return -ENOMEM; + + for (reg = first_reg; + reg <= last_reg; reg++) + DUMP_REG(sdma_rlc_reg_offset + reg); + + WARN_ON_ONCE(i != HQD_N_REGS); + *n_regs = i; + + return 0; +} + +static int wave_control_execute_v12_1(struct amdgpu_device *adev, + uint32_t gfx_index_val, + uint32_t sq_cmd, uint32_t inst) +{ + uint32_t data = 0; + + mutex_lock(&adev->grbm_idx_mutex); + + WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), gfx_index_val); + WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regSQ_CMD), sq_cmd); + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, + INSTANCE_BROADCAST_WRITES, 1); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, + SA_BROADCAST_WRITES, 1); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, + SE_BROADCAST_WRITES, 1); + + WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regGRBM_GFX_INDEX), data); + mutex_unlock(&adev->grbm_idx_mutex); + + return 0; +} + +/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ +static uint32_t kgd_gfx_v12_1_enable_debug_trap(struct amdgpu_device *adev, + bool restore_dbg_registers, + uint32_t vmid) +{ + uint32_t data = 0; + + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); + + return data; +} + +/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ +static uint32_t kgd_gfx_v12_1_disable_debug_trap(struct amdgpu_device *adev, + bool keep_trap_enabled, + uint32_t vmid) +{ + uint32_t data = 0; + + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); + + return data; +} + +static int kgd_gfx_v12_1_validate_trap_override_request(struct amdgpu_device *adev, + uint32_t trap_override, + uint32_t *trap_mask_supported) +{ + *trap_mask_supported &= KFD_DBG_TRAP_MASK_FP_INVALID | + KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL | + KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO | + KFD_DBG_TRAP_MASK_FP_OVERFLOW | + KFD_DBG_TRAP_MASK_FP_UNDERFLOW | + KFD_DBG_TRAP_MASK_FP_INEXACT | + KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO | + KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH | + KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION | + KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START | + KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END; + + + if (trap_override != KFD_DBG_TRAP_OVERRIDE_OR && + trap_override != KFD_DBG_TRAP_OVERRIDE_REPLACE) + return -EPERM; + + return 0; +} + +static uint32_t trap_mask_map_sw_to_hw(uint32_t mask) +{ + uint32_t trap_on_start = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START) ? 1 : 0; + uint32_t trap_on_end = (mask & KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END) ? 1 : 0; + uint32_t excp_en = mask & (KFD_DBG_TRAP_MASK_FP_INVALID | + KFD_DBG_TRAP_MASK_FP_INPUT_DENORMAL | + KFD_DBG_TRAP_MASK_FP_DIVIDE_BY_ZERO | + KFD_DBG_TRAP_MASK_FP_OVERFLOW | + KFD_DBG_TRAP_MASK_FP_UNDERFLOW | + KFD_DBG_TRAP_MASK_FP_INEXACT | + KFD_DBG_TRAP_MASK_INT_DIVIDE_BY_ZERO | + KFD_DBG_TRAP_MASK_DBG_ADDRESS_WATCH | + KFD_DBG_TRAP_MASK_DBG_MEMORY_VIOLATION); + uint32_t ret; + + ret = REG_SET_FIELD(0, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, excp_en); + ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START, trap_on_start); + ret = REG_SET_FIELD(ret, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END, trap_on_end); + + return ret; +} + +static uint32_t trap_mask_map_hw_to_sw(uint32_t mask) +{ + uint32_t ret = REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, EXCP_EN); + + if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_START)) + ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_START; + + if (REG_GET_FIELD(mask, SPI_GDBG_PER_VMID_CNTL, TRAP_ON_END)) + ret |= KFD_DBG_TRAP_MASK_TRAP_ON_WAVE_END; + + return ret; +} + +/* returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ +static uint32_t kgd_gfx_v12_1_set_wave_launch_trap_override(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t trap_override, + uint32_t trap_mask_bits, + uint32_t trap_mask_request, + uint32_t *trap_mask_prev, + uint32_t kfd_dbg_trap_cntl_prev) + +{ + uint32_t data = 0; + + *trap_mask_prev = trap_mask_map_hw_to_sw(kfd_dbg_trap_cntl_prev); + + data = (trap_mask_bits & trap_mask_request) | (*trap_mask_prev & ~trap_mask_request); + data = trap_mask_map_sw_to_hw(data); + + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, trap_override); + + return data; +} + +/* returns STALL_VMID or LAUNCH_MODE. */ +static uint32_t kgd_gfx_v12_1_set_wave_launch_mode(struct amdgpu_device *adev, + uint8_t wave_launch_mode, + uint32_t vmid) +{ + uint32_t data = 0; + bool is_stall_mode = wave_launch_mode == 4; + + if (is_stall_mode) + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, STALL_VMID, + 1); + else + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, LAUNCH_MODE, + wave_launch_mode); + + return data; +} + +#define TCP_WATCH_STRIDE (regTCP_WATCH1_ADDR_H - regTCP_WATCH0_ADDR_H) +static uint32_t kgd_gfx_v12_1_set_address_watch(struct amdgpu_device *adev, + uint64_t watch_address, + uint32_t watch_address_mask, + uint32_t watch_id, + uint32_t watch_mode, + uint32_t debug_vmid, + uint32_t inst) +{ + uint32_t watch_address_high; + uint32_t watch_address_low; + uint32_t watch_address_cntl; + + watch_address_cntl = 0; + watch_address_low = lower_32_bits(watch_address); + watch_address_high = upper_32_bits(watch_address) & 0x1ffffff; + + watch_address_cntl = REG_SET_FIELD(watch_address_cntl, + TCP_WATCH0_CNTL, + MODE, + watch_mode); + + watch_address_cntl = REG_SET_FIELD(watch_address_cntl, + TCP_WATCH0_CNTL, + MASK, + watch_address_mask >> 7); + + watch_address_cntl = REG_SET_FIELD(watch_address_cntl, + TCP_WATCH0_CNTL, + VALID, + 1); + + WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_H) + + (watch_id * TCP_WATCH_STRIDE)), + watch_address_high, inst); + + WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regTCP_WATCH0_ADDR_L) + + (watch_id * TCP_WATCH_STRIDE)), + watch_address_low, inst); + + return watch_address_cntl; +} + +static uint32_t kgd_gfx_v12_1_clear_address_watch(struct amdgpu_device *adev, + uint32_t watch_id) +{ + return 0; +} + +static uint32_t kgd_gfx_v12_1_hqd_sdma_get_doorbell(struct amdgpu_device *adev, + int engine, int queue) +{ + return 0; +} + +const struct kfd2kgd_calls gfx_v12_1_kfd2kgd = { + .init_interrupts = init_interrupts_v12_1, + .hqd_dump = hqd_dump_v12_1, + .hqd_sdma_dump = hqd_sdma_dump_v12_1, + .wave_control_execute = wave_control_execute_v12_1, + .get_atc_vmid_pasid_mapping_info = NULL, + .enable_debug_trap = kgd_gfx_v12_1_enable_debug_trap, + .disable_debug_trap = kgd_gfx_v12_1_disable_debug_trap, + .validate_trap_override_request = kgd_gfx_v12_1_validate_trap_override_request, + .set_wave_launch_trap_override = kgd_gfx_v12_1_set_wave_launch_trap_override, + .set_wave_launch_mode = kgd_gfx_v12_1_set_wave_launch_mode, + .set_address_watch = kgd_gfx_v12_1_set_address_watch, + .clear_address_watch = kgd_gfx_v12_1_clear_address_watch, + .hqd_sdma_get_doorbell = kgd_gfx_v12_1_hqd_sdma_get_doorbell +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 088d09cc7a724..ad08db2887687 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1225,8 +1225,98 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, int engine, int queue) +{ + return 0; +} + +static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_hosttrap_status = RREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS); + + if (sq_hosttrap_status & SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK) { + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS, + SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK); + sq_hosttrap_status = 0x0; + continue; + } + if (sq_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_hosttrap_status; +} +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) { + uint32_t clk_cntl = 0; + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + + RREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL); + clk_cntl = REG_SET_FIELD(clk_cntl, CGTT_SQ_CLK_CTRL, CORE_OVERRIDE, value); + WREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL, clk_cntl); + + mutex_unlock(&adev->grbm_idx_mutex); +} + +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_aldebaran_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_simd */ + value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= max_wave_slot; + if (!(*target_wave_slot)) { + (*target_simd)++; + *target_simd %= max_simd; + } + } else { + pr_debug("PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 704452ca62f8e..675054356eca6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -114,3 +114,14 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, unsigned int utimeout); uint32_t kgd_gfx_v9_hqd_sdma_get_doorbell(struct amdgpu_device *adev, int engine, int queue); +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a51e76623bada..c6e2792e64e42 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -35,6 +36,7 @@ #include "amdgpu_hmm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" +#include "kfd_ipc.h" #include #include "amdgpu_xgmi.h" #include "kfd_priv.h" @@ -345,7 +347,7 @@ create_dmamap_sg_bo(struct amdgpu_device *adev, ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1, AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags, - ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0); + ttm_bo_type_sg, amdkcl_ttm_resvp(&mem->bo->tbo), &gem_obj, 0); amdgpu_bo_unreserve(mem->bo); @@ -380,7 +382,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, * table update and TLB flush here directly. */ replacement = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), ef->base.context, replacement, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(replacement); return 0; @@ -397,7 +399,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, */ void amdgpu_amdkfd_remove_all_eviction_fences(struct amdgpu_bo *bo) { - struct dma_resv *resv = &bo->tbo.base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(&bo->tbo); struct dma_fence *fence, *stub; struct dma_resv_iter cursor; @@ -453,11 +455,11 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, if (ret) goto unreserve_out; - ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (ret) goto unreserve_out; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_BOOKKEEP); unreserve_out: @@ -820,12 +822,25 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) if (!mem->dmabuf) { struct amdgpu_device *bo_adev; struct dma_buf *dmabuf; +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF + int r, fd; + bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file, + mem->gem_handle, + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DRM_RDWR : 0, &fd); + if (r) + return r; + dmabuf = dma_buf_get(fd); + close_fd(fd); +#else bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file, mem->gem_handle, mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0); +#endif if (IS_ERR(dmabuf)) return PTR_ERR(dmabuf); mem->dmabuf = dmabuf; @@ -855,6 +870,38 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, return 0; } +/** + * @kfd_mem_attach_vram_bo: Acquires the handle of a VRAM BO that could + * be used to enable a peer GPU access it + * + * Implementation determines if access to VRAM BO would employ DMABUF + * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config + * option HSA_AMD_P2P enabled. Employ Shared BO mechanism if above + * config option is not set. It is important to note that a Shared BO + * cannot be used to enable peer acces if system has IOMMU enabled + * + * @TODO: ADD Check to ensure IOMMU is not enabled. Should this check + * be somewhere as this is information could be useful in other places + */ +static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, + struct kgd_mem *mem, struct amdgpu_bo **bo, + struct kfd_mem_attachment *attachment) +{ + int ret = 0; + +#ifdef CONFIG_HSA_AMD_P2P + attachment->type = KFD_MEM_ATT_DMABUF; + ret = kfd_mem_attach_dmabuf(adev, mem, bo); + pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); +#else + *bo = mem->bo; + attachment->type = KFD_MEM_ATT_SHARED; + drm_gem_object_get(&(*bo)->tbo.base); + pr_debug("Employ Shared BO mechanim to enable peer GPU access\n"); +#endif + return ret; +} + /* kfd_mem_attach - Add a BO to a VM * * Everything that needs to bo done only once when a BO is first added @@ -878,6 +925,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo *bo[2] = {NULL, NULL}; struct amdgpu_bo_va *bo_va; bool same_hive = false; + struct drm_exec exec; int i, ret; if (!va) { @@ -944,33 +992,47 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = create_dmamap_sg_bo(adev, mem, &bo[i]); if (ret) goto unwind; - /* Enable acces to GTT and VRAM BOs of peer devices */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || - mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { + /* Enable acces to GTT BOs of peer devices */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { attachment[i]->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); + /* Enable peer acces to VRAM BO's */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { + ret = kfd_mem_attach_vram_bo(adev, mem, + &bo[i], attachment[i]); + if (ret) + goto unwind; } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; goto unwind; + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); } - /* Add BO to VM internal data structures */ - ret = amdgpu_bo_reserve(bo[i], false); - if (ret) { - pr_debug("Unable to reserve BO during memory attach"); - goto unwind; + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0); + drm_exec_until_all_locked(&exec) { + ret = amdgpu_vm_lock_pd(vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto unwind; + ret = drm_exec_lock_obj(&exec, &bo[i]->tbo.base); + drm_exec_retry_on_contention(&exec); + if (unlikely(ret)) + goto unwind; } + bo_va = amdgpu_vm_bo_find(vm, bo[i]); if (!bo_va) bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]); else ++bo_va->ref_count; attachment[i]->bo_va = bo_va; - amdgpu_bo_unreserve(bo[i]); + drm_exec_fini(&exec); if (unlikely(!attachment[i]->bo_va)) { ret = -ENOMEM; pr_err("Failed to add BO object to VM. ret == %d\n", @@ -1089,6 +1151,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, return 0; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) { ret = -ENOMEM; @@ -1104,6 +1167,29 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto unregister_out; } +#else + /* If no restore worker is running concurrently, user_pages + * should not be allocated + */ + WARN(mem->user_pages, "Leaking user_pages array"); + + mem->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", __func__); + ret = -ENOMEM; + goto unregister_out; + } + + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + pr_err("%s: Failed to get user pages: %d\n", __func__, ret); + goto free_out; + } + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); +#endif ret = amdgpu_bo_reserve(bo, true); if (ret) { @@ -1111,7 +1197,9 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto release_out; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); +#endif amdgpu_bo_placement_from_domain(bo, mem->domain); ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); @@ -1120,7 +1208,15 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_bo_unreserve(bo); release_out: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(range); +#else + if (ret) + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); +free_out: + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif unregister_out: if (ret) amdgpu_hmm_unregister(bo); @@ -1367,7 +1463,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, vm_list_node) { struct amdgpu_bo *pd = peer_vm->root.bo; - ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, + ret = amdgpu_sync_resv(NULL, sync, amdkcl_ttm_resvp(&pd->tbo), AMDGPU_SYNC_NE_OWNER, AMDGPU_FENCE_OWNER_KFD); if (ret) @@ -1397,8 +1493,10 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, struct dma_fence **ef) { struct amdkfd_process_info *info = NULL; + struct kfd_process *process = NULL; int ret; + process = container_of(process_info, struct kfd_process, kgd_process_info); if (!*process_info) { info = kzalloc(sizeof(*info), GFP_KERNEL); if (!info) @@ -1414,7 +1512,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, info->eviction_fence = amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), current->mm, - NULL); + NULL, process->context_id); if (!info->eviction_fence) { pr_err("Failed to create eviction fence\n"); ret = -ENOMEM; @@ -1425,10 +1523,15 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, INIT_DELAYED_WORK(&info->restore_userptr_work, amdgpu_amdkfd_restore_userptr_worker); + info->context_id = process->context_id; + *process_info = info; } - vm->process_info = *process_info; + if (cmpxchg(&vm->process_info, NULL, *process_info) != NULL) { + ret = -EINVAL; + goto already_acquired; + } /* Validate page directory and attach eviction fence */ ret = amdgpu_bo_reserve(vm->root.bo, true); @@ -1443,10 +1546,10 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, AMDGPU_FENCE_OWNER_KFD, false); if (ret) goto wait_pd_fail; - ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(vm->root.bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), &vm->process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(vm->root.bo); @@ -1468,6 +1571,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, amdgpu_bo_unreserve(vm->root.bo); reserve_pd_fail: vm->process_info = NULL; +already_acquired: if (info) { dma_fence_put(&info->eviction_fence->base); *process_info = NULL; @@ -1491,7 +1595,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, * * Return: ZERO if successful in pinning, Non-Zero in case of error. */ -static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) { int ret = 0; @@ -1521,6 +1625,11 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) pr_err("Error in Pinning BO to domain: %d\n", domain); amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); + + if (!ret && bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_add(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + out: amdgpu_bo_unreserve(bo); return ret; @@ -1534,7 +1643,7 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their * PIN count decremented. Calls to UNPIN must balance calls to PIN */ -static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) { int ret = 0; @@ -1543,6 +1652,11 @@ static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) return; amdgpu_bo_unpin(bo); + + if (bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_sub(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + amdgpu_bo_unreserve(bo); } @@ -1664,6 +1778,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) - adev->kfd.vram_used_aligned[xcp_id] - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned) - reserved_for_pt - reserved_for_ras; @@ -1931,8 +2046,19 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Cleanup user pages and MMU notifiers */ if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { amdgpu_hmm_unregister(mem->bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(mem->range); mem->range = NULL; +#else + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, + mem->bo->tbo.ttm->num_pages); + kvfree(mem->user_pages); + } +#endif } amdgpu_amdkfd_remove_eviction_fence(mem->bo, @@ -1971,9 +2097,13 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( *size = 0; } + /* Unreference the ipc_obj if applicable */ + kfd_ipc_obj_put(&mem->ipc_obj); + /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); - drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); + if (!mem->ipc_obj) + drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); if (mem->dmabuf) { dma_buf_put(mem->dmabuf); mem->dmabuf = NULL; @@ -1987,7 +2117,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( drm_gem_object_put(&mem->bo->tbo.base); /* - * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(), + * For kgd_mem allocated in import_obj_create() via + * amdgpu_amdkfd_gpuvm_import_dmabuf_fd(), * explicitly free it here. */ if (!use_release_notifier) @@ -2210,7 +2341,7 @@ int amdgpu_amdkfd_gpuvm_sync_memory( * @bo_gart: Return bo reference * * Before return, bo reference count is incremented. To release the reference and unpin/ - * unmap the BO, call amdgpu_amdkfd_free_gtt_mem. + * unmap the BO, call amdgpu_amdkfd_free_kernel_mem. */ int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart) { @@ -2345,6 +2476,178 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, return 0; } +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags) +{ + struct amdgpu_bo *bo = mem->bo; + + if (flags) + *flags = mem->alloc_flags; + drm_gem_object_get(&bo->tbo.base); + return bo; +} + +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) +{ + drm_gem_object_put(&bo->tbo.base); +} + +#define AMD_GPU_PAGE_SHIFT PAGE_SHIFT +#define AMD_GPU_PAGE_SIZE (_AC(1, UL) << AMD_GPU_PAGE_SHIFT) + +/** + * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance + * of scatter gather table (sg_table) for a MMIO/DOORBELL BO. An example + * of this is the MMIO BO that's used to surface HDP registers. + * + * @note: This method will only work as long as the address encapsulated + * by MMIO/DOORBELL BO is not a DMA mapped address + * + * The method does the following: + * Acquire address to use in building scatterlist nodes + * Acquire size of memory to use in building scatterlist nodes + * Invoke DMA Map service to obtain DMA mapped address + * Access sg_table construction service with above parameters + * Return the handle of scatter gather table + * + * @adev: GPU device whose MMIO/DOORBELL BO is being exported + * @bo: Handle of MMIO/DOORBELL BO e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access + * @dir: Direction of data movement from peer PCIe devices perspective + * + * @sgt: Output parameter that is built and returned + * + * Return: zero if successful, non-zero otherwise + */ +static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **sgt) +{ + dma_addr_t dma_addr; + s32 size, ret; + u64 addr; + + /* Acquire the address of MMIO or DOORBELL BO being + * exported. By policy the entire backing memory is + * encapsulated in one scatterlist node + */ + size = bo->tbo.sg->sgl->length; + addr = bo->tbo.sg->sgl->dma_address; + pr_debug("MMIO/Doorbell address being exported: %llx\n", addr); + + /* DMA map the acquired address - MMIO or DOORBELL */ + dma_addr = dma_map_resource(dma_dev, addr, size, + dir, DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(dma_dev, dma_addr); + if (ret) + return ret; + + /* Update output parameter with a new sg_table */ + pr_debug("MMIO/Doorbell BO size: %d\n", size); + pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); + *sgt = create_sg_table(dma_addr, size); + return (*sgt) ? 0 : -ENOMEM; +} + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg) +{ + struct sg_table *sg = NULL; + struct page **pages; + uint64_t offset_in_page; + unsigned int page_size; + unsigned int cur_page; + size_t max_segment = 0; + int ret; + + /* Determine access does not cross memory boundary */ + if (size + offset > amdgpu_bo_size(bo)) + return -EFAULT; + + /* For GPU memory use VRAM Mgr to build SG Table */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + ret = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, offset, + size, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_sg) that is used to surface + * resources from MMIO address space. The allocation flag of + * BO fall in MMIO_REMAP / DOORBELL domain + */ + if (bo->tbo.type == ttm_bo_type_sg && + ((flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + ret = get_sg_table_of_mmio_or_doorbel_bo(bo, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_device) that is used to surface + * memory resources from GPU's GART aperture. The allocation flag + * of BO falls in GTT domain i.e. the physical backing memory is + * part of system memory + */ + + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) + return -ENOMEM; + + page_size = PAGE_SIZE; + offset_in_page = offset & (page_size - 1); + + pages = bo->tbo.ttm->pages; + cur_page = offset / page_size; + + max_segment = dma_max_mapping_size(dma_dev); + if (!max_segment) + max_segment = UINT_MAX; + + ret = sg_alloc_table_from_pages_segment(sg, &pages[cur_page], + bo->tbo.ttm->num_pages - cur_page, + offset_in_page, size, max_segment, + GFP_KERNEL); + if (ret) + goto out; + + if (dma_dev) { + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + } + + *ret_sg = sg; + return 0; + +out_of_range: + sg_free_table(sg); +out: + kfree(sg); + *ret_sg = NULL; + return ret; +} + +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sgt) +{ + /* Unmap GPU device memory */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + amdgpu_vram_mgr_free_sgt(dma_dev, dir, sgt); + return; + } + + /* Unmap system memory */ + if (dma_dev) + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(sgt); +} + static int import_obj_create(struct amdgpu_device *adev, struct dma_buf *dma_buf, struct drm_gem_object *obj, @@ -2378,12 +2681,14 @@ static int import_obj_create(struct amdgpu_device *adev, INIT_LIST_HEAD(&(*mem)->attachments); mutex_init(&(*mem)->lock); - - (*mem)->alloc_flags = - ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? - KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) - | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE - | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; + if (bo->kfd_bo) + (*mem)->alloc_flags = bo->kfd_bo->alloc_flags; + else + (*mem)->alloc_flags = + ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? + KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) + | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE + | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; @@ -2418,6 +2723,37 @@ static int import_obj_create(struct amdgpu_device *adev, return ret; } +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, + struct dma_buf *dma_buf, + struct kfd_ipc_obj *ipc_obj, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset) +{ + struct drm_gem_object *obj; + int ret; + + if (WARN_ON(!ipc_obj)) + return -EINVAL; + + obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + ret = import_obj_create(adev, dma_buf, obj, va, drm_priv, mem, size, + mmap_offset); + if (ret) + goto err_put_obj; + + (*mem)->ipc_obj = ipc_obj; + + return 0; + +err_put_obj: + drm_gem_object_put(obj); + return ret; +} + int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, @@ -2470,6 +2806,43 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj, + uint32_t flags, + uint32_t *restore_handle) +{ + struct dma_buf *dmabuf; + int r = 0; + + if (!adev || !vm || !mem) + return -EINVAL; + + mutex_lock(&mem->lock); + + if (mem->ipc_obj) { + *ipc_obj = mem->ipc_obj; + goto unlock_out; + } + + r = kfd_mem_export_dmabuf(mem); + if (r) + goto unlock_out; + + get_dma_buf(mem->dmabuf); + dmabuf = mem->dmabuf; + + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); + if (r) + dma_buf_put(dmabuf); + else + *ipc_obj = mem->ipc_obj; + +unlock_out: + mutex_unlock(&mem->lock); + return r; +} + /* Evict a userptr BO by stopping the queues if necessary * * Runs in MMU notifier, may be in RECLAIM_FS context. This means it @@ -2480,9 +2853,16 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, * restore, where we get updated page addresses. This function only * ensures that GPU access to the BO is stopped. */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) { + struct mm_struct *mm = mni->mm; +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, + struct mm_struct *mm) +{ +#endif struct amdkfd_process_info *process_info = mem->process_info; int r = 0; @@ -2493,12 +2873,14 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, return 0; mutex_lock(&process_info->notifier_lock); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mmu_interval_set_seq(mni, cur_seq); +#endif mem->invalid++; if (++process_info->evicted_bos == 1) { /* First eviction, stop the queues */ - r = kgd2kfd_quiesce_mm(mni->mm, + r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR); if (r && r != -ESRCH) @@ -2551,9 +2933,10 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(mem->range); mem->range = NULL; - +#endif /* BO reservations and getting user pages (hmm_range_fault) * must happen outside the notifier lock */ @@ -2574,7 +2957,8 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, return -EAGAIN; } } - + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mem->range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!mem->range)) return -ENOMEM; @@ -2614,11 +2998,43 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = 0; } - amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->range); +#else + if (!mem->user_pages) { + mem->user_pages = + kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", + __func__); + return -ENOMEM; + } + } else if (mem->user_pages[0]) { + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + } - mutex_lock(&process_info->notifier_lock); + /* Get updated user pages */ + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + mem->user_pages[0] = NULL; + pr_debug("%s: Failed to get user pages: %d\n", + __func__, ret); + /* Pretend it succeeded. It will fail later + * with a VM fault if the GPU tries to access + * it. Better than hanging indefinitely with + * stalled user mode queues. + * + * Return other error -EBUSY or -ENOMEM to retry restore + */ + if (ret != -EFAULT) + return ret; + + ret = 0; + } +#endif + mutex_lock(&process_info->notifier_lock); /* Mark the BO as valid unless it was invalidated * again concurrently. */ @@ -2627,7 +3043,9 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, goto unlock_out; } /* set mem valid if mem has hmm range associated */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (mem->range) +#endif mem->invalid = 0; } @@ -2692,6 +3110,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Validate the BO if we got user pages */ if (bo->tbo.ttm->pages[0]) { amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -2702,6 +3121,28 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } } +#else + /* Copy pages array and validate the BO if we got user pages */ + if (mem->user_pages && mem->user_pages[0]) { + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, + mem->user_pages); + amdgpu_bo_placement_from_domain(bo, mem->domain); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) { + pr_err("%s: failed to validate BO\n", __func__); + goto unreserve_out; + } + } + + /* Validate succeeded, now the BO owns the pages, free + * our copy of the pointer array. + */ + if (mem->user_pages) { + kvfree(mem->user_pages); + mem->user_pages = NULL; + } +#endif + /* Update mapping. If the BO was not validated * (because we couldn't get user pages), this will * clear the page table entries, which will result in @@ -2748,6 +3189,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i list_for_each_entry_safe(mem, tmp_mem, &process_info->userptr_inval_list, validate_list) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool valid; /* keep mem without hmm range at userptr_inval_list */ @@ -2764,6 +3206,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i ret = -EAGAIN; continue; } +#endif if (mem->invalid) { WARN(1, "Valid BO is marked invalid"); @@ -2966,7 +3409,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * goto validate_map_fail; } } - dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, + dma_resv_for_each_fence(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, fence) { ret = amdgpu_sync_fence(&sync_obj, fence, GFP_KERNEL); if (ret) { @@ -3066,7 +3509,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * amdgpu_amdkfd_fence_create( process_info->eviction_fence->base.context, process_info->eviction_fence->mm, - NULL); + NULL, process_info->context_id); if (!new_fence) { pr_err("Failed to create eviction fence\n"); @@ -3086,7 +3529,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * if (mem->bo->tbo.pin_count) continue; - dma_resv_add_fence(mem->bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&mem->bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3095,7 +3538,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * vm_list_node) { struct amdgpu_bo *bo = peer_vm->root.bo; - dma_resv_add_fence(bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3147,10 +3590,10 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem * Add process eviction fence to bo so they can * evict each other. */ - ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(gws_bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&gws_bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(gws_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c new file mode 100644 index 0000000000000..3d60abcad5861 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -0,0 +1,101 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu_object.h" +#include "amdgpu_amdkfd.h" +#include +#include "amdgpu_ids.h" + +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, int xcc_id, bool cntl) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + if (cntl) + adev->gfx.spmfuncs->start(adev, xcc_id); + else + adev->gfx.spmfuncs->stop(adev, xcc_id); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); +} + +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_rdptr(adev, xcc_id, rptr); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); +} + +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + int r = 0; + + if (!adev->gfx.rlc.funcs->update_spm_vmid) + return -EINVAL; + + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (r) + return r; + + /* init spm vmid with 0x0 */ + adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0); + + /* set spm ring registers */ + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, xcc_id, gpu_addr, size); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); + return r; +} + +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, int xcc_id, struct amdgpu_vm *vm) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + /* stop spm stream and interrupt */ + spin_lock(&adev->gfx.kiq[xcc_id].ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->stop(adev, xcc_id); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq[xcc_id].ring_lock); + + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); + + /* revert spm vmid with 0xf */ + if (adev->gfx.rlc.funcs->update_spm_vmid) + adev->gfx.rlc.funcs->update_spm_vmid(adev, xcc_id, NULL, 0xf); +} + +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev, int xcc_id) +{ + if (adev->kfd.dev) + kgd2kfd_spm_interrupt(adev->kfd.dev, xcc_id); +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 763f2b8dcf13a..00de8677cf278 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1830,6 +1830,7 @@ static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); static DEVICE_ATTR(vbios_build, 0444, amdgpu_atombios_get_vbios_build, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vbios_version_attrs[] = { &dev_attr_vbios_version.attr, &dev_attr_vbios_build.attr, NULL }; @@ -1862,6 +1863,7 @@ int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) return 0; } +#endif /** * amdgpu_atombios_fini - free the driver info and callbacks for atombios @@ -1882,6 +1884,9 @@ void amdgpu_atombios_fini(struct amdgpu_device *adev) adev->mode_info.atom_context = NULL; kfree(adev->mode_info.atom_card_info); adev->mode_info.atom_card_info = NULL; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_vbios_version); +#endif } /** @@ -1898,6 +1903,9 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) { struct card_info *atom_card_info = kzalloc(sizeof(struct card_info), GFP_KERNEL); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif if (!atom_card_info) return -ENOMEM; @@ -1929,6 +1937,14 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) amdgpu_atombios_allocate_fb_scratch(adev); } +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_vbios_version); + if (ret) { + DRM_ERROR("Failed to create device file for VBIOS version\n"); + return ret; + } +#endif + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 867bc5c5ce67d..ae32b280273aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -215,6 +215,8 @@ int amdgpu_atombios_get_data_table(struct amdgpu_device *adev, void amdgpu_atombios_fini(struct amdgpu_device *adev); int amdgpu_atombios_init(struct amdgpu_device *adev); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index 636385c80f643..cd9aa5b45e943 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -296,249 +296,357 @@ static int convert_atom_mem_type_to_vram_type(struct amdgpu_device *adev, return vram_type; } -int -amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, +static int amdgpu_atomfirmware_get_uma_carveout_info_v2_3(struct amdgpu_device *adev, + union igp_info *igp_info, + struct amdgpu_uma_carveout_info *uma_info) +{ + struct uma_carveout_option *opts; + uint8_t nr_uma_options; + int i; + + nr_uma_options = igp_info->v23.UMACarveoutIndexMax; + + if (!nr_uma_options) + return -ENODEV; + + if (nr_uma_options > MAX_UMA_OPTION_ENTRIES) { + drm_dbg(adev_to_drm(adev), + "Number of UMA options exceeds max table size. Options will not be parsed"); + return -EINVAL; + } + + uma_info->num_entries = nr_uma_options; + uma_info->uma_option_index = igp_info->v23.UMACarveoutIndex; + + opts = igp_info->v23.UMASizeControlOption; + + for (i = 0; i < nr_uma_options; i++) { + if (!opts[i].memoryCarvedGb) + uma_info->entries[i].memory_carved_mb = 512; + else + uma_info->entries[i].memory_carved_mb = (uint32_t)opts[i].memoryCarvedGb << 10; + + uma_info->entries[i].flags = opts[i].uma_carveout_option_flags.all8; + strscpy(uma_info->entries[i].name, opts[i].optionName, MAX_UMA_OPTION_NAME); + } + + return 0; +} + +int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, + struct amdgpu_uma_carveout_info *uma_info) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + union igp_info *igp_info; + u16 data_offset, size; + u8 frev, crev; + int index; + + if (!(adev->flags & AMD_IS_APU)) + return -ENODEV; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + integratedsysteminfo); + + if (!amdgpu_atom_parse_data_header(mode_info->atom_context, + index, &size, + &frev, &crev, &data_offset)) { + return -EINVAL; + } + + igp_info = (union igp_info *) + (mode_info->atom_context->bios + data_offset); + + switch (frev) { + case 2: + switch (crev) { + case 3: + return amdgpu_atomfirmware_get_uma_carveout_info_v2_3(adev, igp_info, uma_info); + break; + default: + break; + } + break; + default: + break; + } + return -ENODEV; +} + +int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor) { struct amdgpu_mode_info *mode_info = &adev->mode_info; - int index, i = 0; + int index; u16 data_offset, size; union igp_info *igp_info; - union vram_info *vram_info; - union umc_info *umc_info; - union vram_module *vram_module; u8 frev, crev; u8 mem_type; - u8 mem_vendor; u32 mem_channel_number; u32 mem_channel_width; - u32 module_id; - if (adev->flags & AMD_IS_APU) - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, integratedsysteminfo); - else { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - case IP_VERSION(12, 0, 0): - case IP_VERSION(12, 0, 1): - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); + if (amdgpu_atom_parse_data_header(mode_info->atom_context, + index, &size, + &frev, &crev, &data_offset)) { + igp_info = (union igp_info *) + (mode_info->atom_context->bios + data_offset); + switch (frev) { + case 1: + switch (crev) { + case 11: + case 12: + mem_channel_number = igp_info->v11.umachannelnumber; + if (!mem_channel_number) + mem_channel_number = 1; + mem_type = igp_info->v11.memorytype; + if (mem_type == LpDdr5MemType) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + break; + default: + return -EINVAL; + } + break; + case 2: + switch (crev) { + case 1: + case 2: + mem_channel_number = igp_info->v21.umachannelnumber; + if (!mem_channel_number) + mem_channel_number = 1; + mem_type = igp_info->v21.memorytype; + if (mem_type == LpDdr5MemType) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + break; + case 3: + mem_channel_number = igp_info->v23.umachannelnumber; + if (!mem_channel_number) + mem_channel_number = 1; + mem_type = igp_info->v23.memorytype; + if (mem_type == LpDdr5MemType) + mem_channel_width = 32; + else + mem_channel_width = 64; + if (vram_width) + *vram_width = mem_channel_number * mem_channel_width; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + break; + default: + return -EINVAL; + } break; default: - index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info); + return -EINVAL; } + } else { + return -EINVAL; } + return 0; +} + +int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, + int *vram_vendor) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index; + u16 data_offset, size; + union umc_info *umc_info; + u8 frev, crev; + u8 mem_type; + u8 mem_vendor; + u32 mem_channel_number; + u32 mem_channel_width; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, umc_info); + if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { - if (adev->flags & AMD_IS_APU) { - igp_info = (union igp_info *) - (mode_info->atom_context->bios + data_offset); - switch (frev) { - case 1: - switch (crev) { - case 11: - case 12: - mem_channel_number = igp_info->v11.umachannelnumber; - if (!mem_channel_number) - mem_channel_number = 1; - mem_type = igp_info->v11.memorytype; - if (mem_type == LpDdr5MemType) - mem_channel_width = 32; - else - mem_channel_width = 64; - if (vram_width) - *vram_width = mem_channel_number * mem_channel_width; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - break; - default: - return -EINVAL; - } - break; - case 2: - switch (crev) { - case 1: - case 2: - mem_channel_number = igp_info->v21.umachannelnumber; - if (!mem_channel_number) - mem_channel_number = 1; - mem_type = igp_info->v21.memorytype; - if (mem_type == LpDdr5MemType) - mem_channel_width = 32; - else - mem_channel_width = 64; - if (vram_width) - *vram_width = mem_channel_number * mem_channel_width; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - break; - case 3: - mem_channel_number = igp_info->v23.umachannelnumber; - if (!mem_channel_number) - mem_channel_number = 1; - mem_type = igp_info->v23.memorytype; - if (mem_type == LpDdr5MemType) - mem_channel_width = 32; - else - mem_channel_width = 64; - if (vram_width) - *vram_width = mem_channel_number * mem_channel_width; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - break; - default: - return -EINVAL; - } + umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); + + if (frev == 4) { + switch (crev) { + case 0: + mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); + mem_type = le32_to_cpu(umc_info->v40.vram_type); + mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); + mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); break; default: return -EINVAL; } } else { - switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { - case IP_VERSION(12, 0, 0): - case IP_VERSION(12, 0, 1): - umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); - - if (frev == 4) { - switch (crev) { - case 0: - mem_channel_number = le32_to_cpu(umc_info->v40.channel_num); - mem_type = le32_to_cpu(umc_info->v40.vram_type); - mem_channel_width = le32_to_cpu(umc_info->v40.channel_width); - mem_vendor = RREG32(adev->bios_scratch_reg_offset + 4) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - break; - default: - return -EINVAL; - } - } else - return -EINVAL; + return -EINVAL; + } + } else { + return -EINVAL; + } + + return 0; +} + +int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, + int *vram_vendor) +{ + struct amdgpu_mode_info *mode_info = &adev->mode_info; + int index, i = 0; + u16 data_offset, size; + union vram_info *vram_info; + union vram_module *vram_module; + u8 frev, crev; + u8 mem_type; + u8 mem_vendor; + u32 mem_channel_number; + u32 mem_channel_width; + u32 module_id; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, vram_info); + + if (amdgpu_atom_parse_data_header(mode_info->atom_context, + index, &size, + &frev, &crev, &data_offset)) { + vram_info = (union vram_info *) + (mode_info->atom_context->bios + data_offset); + + module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; + if (frev == 3) { + switch (crev) { + /* v30 */ + case 0: + vram_module = (union vram_module *)vram_info->v30.vram_module; + mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + mem_type = vram_info->v30.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_info->v30.channel_num; + mem_channel_width = vram_info->v30.channel_width; + if (vram_width) + *vram_width = mem_channel_number * 16; break; default: - vram_info = (union vram_info *) - (mode_info->atom_context->bios + data_offset); - - module_id = (RREG32(adev->bios_scratch_reg_offset + 4) & 0x00ff0000) >> 16; - if (frev == 3) { - switch (crev) { - /* v30 */ - case 0: - vram_module = (union vram_module *)vram_info->v30.vram_module; - mem_vendor = (vram_module->v30.dram_vendor_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - mem_type = vram_info->v30.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_info->v30.channel_num; - mem_channel_width = vram_info->v30.channel_width; - if (vram_width) - *vram_width = mem_channel_number * 16; - break; - default: - return -EINVAL; - } - } else if (frev == 2) { - switch (crev) { - /* v23 */ - case 3: - if (module_id > vram_info->v23.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v23.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v9.vram_module_size); - i++; - } - mem_type = vram_module->v9.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v9.channel_num; - mem_channel_width = vram_module->v9.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - /* v24 */ - case 4: - if (module_id > vram_info->v24.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v24.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v10.vram_module_size); - i++; - } - mem_type = vram_module->v10.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v10.channel_num; - mem_channel_width = vram_module->v10.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - /* v25 */ - case 5: - if (module_id > vram_info->v25.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v25.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v11.vram_module_size); - i++; - } - mem_type = vram_module->v11.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v11.channel_num; - mem_channel_width = vram_module->v11.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - /* v26 */ - case 6: - if (module_id > vram_info->v26.vram_module_num) - module_id = 0; - vram_module = (union vram_module *)vram_info->v26.vram_module; - while (i < module_id) { - vram_module = (union vram_module *) - ((u8 *)vram_module + vram_module->v9.vram_module_size); - i++; - } - mem_type = vram_module->v9.memory_type; - if (vram_type) - *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); - mem_channel_number = vram_module->v9.channel_num; - mem_channel_width = vram_module->v9.channel_width; - if (vram_width) - *vram_width = mem_channel_number * (1 << mem_channel_width); - mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; - if (vram_vendor) - *vram_vendor = mem_vendor; - break; - default: - return -EINVAL; - } - } else { - /* invalid frev */ - return -EINVAL; + return -EINVAL; + } + } else if (frev == 2) { + switch (crev) { + /* v23 */ + case 3: + if (module_id > vram_info->v23.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v23.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v9.vram_module_size); + i++; + } + mem_type = vram_module->v9.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v9.channel_num; + mem_channel_width = vram_module->v9.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + /* v24 */ + case 4: + if (module_id > vram_info->v24.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v24.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v10.vram_module_size); + i++; } + mem_type = vram_module->v10.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v10.channel_num; + mem_channel_width = vram_module->v10.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v10.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + /* v25 */ + case 5: + if (module_id > vram_info->v25.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v25.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v11.vram_module_size); + i++; + } + mem_type = vram_module->v11.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v11.channel_num; + mem_channel_width = vram_module->v11.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v11.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + /* v26 */ + case 6: + if (module_id > vram_info->v26.vram_module_num) + module_id = 0; + vram_module = (union vram_module *)vram_info->v26.vram_module; + while (i < module_id) { + vram_module = (union vram_module *) + ((u8 *)vram_module + vram_module->v9.vram_module_size); + i++; + } + mem_type = vram_module->v9.memory_type; + if (vram_type) + *vram_type = convert_atom_mem_type_to_vram_type(adev, mem_type); + mem_channel_number = vram_module->v9.channel_num; + mem_channel_width = vram_module->v9.channel_width; + if (vram_width) + *vram_width = mem_channel_number * (1 << mem_channel_width); + mem_vendor = (vram_module->v9.vender_rev_id) & 0xF; + if (vram_vendor) + *vram_vendor = mem_vendor; + break; + default: + return -EINVAL; } + } else { + /* invalid frev */ + return -EINVAL; } + + } else { + return -EINVAL; } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h index 649b5530d8ae1..0760e45105133 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h @@ -30,8 +30,14 @@ uint32_t amdgpu_atomfirmware_query_firmware_capability(struct amdgpu_device *ade bool amdgpu_atomfirmware_gpu_virtualization_supported(struct amdgpu_device *adev); void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev); int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev); +int amdgpu_atomfirmware_get_integrated_system_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor); +int amdgpu_atomfirmware_get_umc_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor); int amdgpu_atomfirmware_get_vram_info(struct amdgpu_device *adev, int *vram_width, int *vram_type, int *vram_vendor); +int amdgpu_atomfirmware_get_uma_carveout_info(struct amdgpu_device *adev, + struct amdgpu_uma_carveout_info *uma_info); int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev); int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev); bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index 3893e6fc2f037..3353c78a258aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -44,7 +44,9 @@ struct amdgpu_atpx { static struct amdgpu_atpx_priv { bool atpx_detected; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool bridge_pm_usable; +#endif unsigned int quirks; /* handle for device - and atpx */ acpi_handle dhandle; @@ -221,11 +223,18 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) atpx->is_hybrid = false; } else { pr_notice("ATPX Hybrid Graphics\n"); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE /* * Disable legacy PM methods only when pcie port PM is usable, * otherwise the device might fail to power off or power on. */ atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable; +#else + /* + * This is a temporary hack for the kernel doesn't support D3. + */ + atpx->functions.power_cntl = true; +#endif atpx->is_hybrid = true; } } @@ -604,16 +613,20 @@ static bool amdgpu_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool d3_supported = false; struct pci_dev *parent_pdev; +#endif while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -622,8 +635,10 @@ static bool amdgpu_atpx_detect(void) has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -632,7 +647,9 @@ static bool amdgpu_atpx_detect(void) pr_info("vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE amdgpu_atpx_priv.bridge_pm_usable = d3_supported; +#endif amdgpu_atpx_init(); return true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c index 199693369c7ce..6f3c68cde75eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c @@ -35,11 +35,12 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, struct dma_fence *fence; int i, r; + mutex_lock(&adev->mman.default_entity.lock); stime = ktime_get(); for (i = 0; i < n; i++) { - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence, - false, false, 0); + r = amdgpu_copy_buffer(adev, &adev->mman.default_entity, + saddr, daddr, size, NULL, &fence, + false, 0); if (r) goto exit_do_move; r = dma_fence_wait(fence, false); @@ -49,6 +50,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size, } exit_do_move: + mutex_unlock(&adev->mman.default_entity.lock); etime = ktime_get(); *time_ms = ktime_ms_delta(etime, stime); @@ -66,7 +68,7 @@ static void amdgpu_benchmark_log_results(struct amdgpu_device *adev, throughput = div64_s64(throughput, time_ms); - dev_info(adev->dev, "amdgpu: %s %u bo moves of %u kB from" + dev_info(adev->dev, " %s %u bo moves of %u kB from" " %d to %d in %lld ms, throughput: %lld Mb/s or %lld MB/s\n", kind, n, size >> 10, sdomain, ddomain, time_ms, throughput * 8, throughput); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index 66fb37b643882..3270ea50bdc74 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -36,6 +36,7 @@ #define AMDGPU_BO_LIST_MAX_PRIORITY 32u #define AMDGPU_BO_LIST_NUM_BUCKETS (AMDGPU_BO_LIST_MAX_PRIORITY + 1) +#define AMDGPU_BO_LIST_MAX_ENTRIES (128 * 1024) static void amdgpu_bo_list_free_rcu(struct rcu_head *rcu) { @@ -60,11 +61,9 @@ static int amdgpu_bo_list_entry_cmp(const void *_a, const void *_b) { const struct amdgpu_bo_list_entry *a = _a, *b = _b; - if (a->priority > b->priority) - return 1; - if (a->priority < b->priority) - return -1; - return 0; + BUILD_BUG_ON(AMDGPU_BO_LIST_MAX_PRIORITY >= INT_MAX); + + return (int)a->priority - (int)b->priority; } int amdgpu_bo_list_create(struct amdgpu_device *adev, struct drm_file *filp, @@ -190,6 +189,9 @@ int amdgpu_bo_create_list_entry_array(struct drm_amdgpu_bo_list_in *in, const uint32_t bo_number = in->bo_number; struct drm_amdgpu_bo_list_entry *info; + if (bo_number > AMDGPU_BO_LIST_MAX_ENTRIES) + return -EINVAL; + /* copy the handle array from userspace to a kernel buffer */ if (likely(info_size == bo_info_size)) { info = vmemdup_array_user(uptr, bo_number, info_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 2b5e7c46a39d4..43862a8082110 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -24,6 +24,7 @@ #define __AMDGPU_BO_LIST_H__ #include +#include struct hmm_range; @@ -39,7 +40,13 @@ struct amdgpu_bo_list_entry { struct amdgpu_bo_va *bo_va; uint32_t priority; struct amdgpu_hmm_range *range; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; +#else + struct page **user_pages; + int user_invalidated; + struct ttm_validate_buffer tv; +#endif }; struct amdgpu_bo_list { @@ -54,8 +61,12 @@ struct amdgpu_bo_list { /* Protect access during command submission. */ struct mutex bo_list_mutex; - +#ifdef __counted_by struct amdgpu_bo_list_entry entries[] __counted_by(num_entries); +#else + struct amdgpu_bo_list_entry entries[]; +#endif + }; int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 004a6a9d6b9fa..09c8942c22d3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -349,7 +349,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, strscpy(fw_name, "amdgpu/vega20_smc.bin"); break; default: - DRM_ERROR("SMC firmware not supported\n"); + drm_err(adev_to_drm(adev), "SMC firmware not supported\n"); return -EINVAL; } @@ -357,7 +357,8 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, AMDGPU_UCODE_REQUIRED, "%s", fw_name); if (err) { - DRM_ERROR("Failed to load firmware \"%s\"", fw_name); + drm_err(adev_to_drm(adev), + "Failed to load firmware \"%s\"\n", fw_name); amdgpu_ucode_release(&adev->pm.fw); return err; } @@ -402,7 +403,7 @@ struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) kmalloc(sizeof(*cgs_device), GFP_KERNEL); if (!cgs_device) { - DRM_ERROR("Couldn't allocate CGS device structure\n"); + drm_err(adev_to_drm(adev), "Couldn't allocate CGS device structure\n"); return NULL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 9f96d568acf20..90d77ac3a209d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -109,7 +109,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -117,7 +121,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -126,7 +134,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) dig_connector = amdgpu_connector->con_priv; if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector->display_info.is_hdmi) { +#else + drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -150,7 +162,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; } +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif /* * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at @@ -176,7 +192,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { +#ifndef HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES + if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && +#else if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && +#endif (mode_clock * 5/4 <= max_tmds_clock)) bpc = 10; else @@ -219,10 +239,17 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif best_encoder = connector_funcs->best_encoder(connector); +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if ((encoder == best_encoder) && (status == connector_status_connected)) connected = true; else @@ -237,8 +264,15 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type == encoder_type) return encoder; } @@ -246,10 +280,10 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, return NULL; } -static struct edid * +static const struct drm_edid * amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) { - return drm_edid_duplicate(drm_edid_raw(adev->mode_info.bios_hardcoded_edid)); + return drm_edid_dup(adev->mode_info.bios_hardcoded_edid); } static void amdgpu_connector_get_edid(struct drm_connector *connector) @@ -268,8 +302,8 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != ENCODER_OBJECT_ID_NONE) && amdgpu_connector->ddc_bus->has_aux) { - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->aux.ddc); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->aux.ddc); } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; @@ -277,14 +311,14 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && amdgpu_connector->ddc_bus->has_aux) - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->aux.ddc); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->aux.ddc); else if (amdgpu_connector->ddc_bus) - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->adapter); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->adapter); } else if (amdgpu_connector->ddc_bus) { - amdgpu_connector->edid = drm_get_edid(connector, - &amdgpu_connector->ddc_bus->adapter); + amdgpu_connector->edid = drm_edid_read_ddc(connector, + &amdgpu_connector->ddc_bus->adapter); } if (!amdgpu_connector->edid) { @@ -292,30 +326,22 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) { amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); - drm_connector_update_edid_property(connector, amdgpu_connector->edid); + drm_edid_connector_update(connector, amdgpu_connector->edid); } } } -static void amdgpu_connector_free_edid(struct drm_connector *connector) -{ - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - - kfree(amdgpu_connector->edid); - amdgpu_connector->edid = NULL; -} - static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); int ret; if (amdgpu_connector->edid) { - drm_connector_update_edid_property(connector, amdgpu_connector->edid); - ret = drm_add_edid_modes(connector, amdgpu_connector->edid); + drm_edid_connector_update(connector, amdgpu_connector->edid); + ret = drm_edid_connector_add_modes(connector); return ret; } - drm_connector_update_edid_property(connector, NULL); + drm_edid_connector_update(connector, NULL); return 0; } @@ -323,9 +349,16 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -671,7 +704,11 @@ static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); @@ -754,7 +791,7 @@ static void amdgpu_connector_destroy(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); kfree(amdgpu_connector->con_priv); drm_connector_unregister(connector); drm_connector_cleanup(connector); @@ -834,7 +871,11 @@ static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) } static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -873,22 +914,23 @@ amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) dret = amdgpu_display_ddc_probe(amdgpu_connector, false); if (dret) { amdgpu_connector->detected_by_load = false; - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); amdgpu_connector_get_edid(connector); if (!amdgpu_connector->edid) { - DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", - connector->name); + drm_err(connector->dev, + "%s: probed a monitor but no|invalid EDID\n", + connector->name); ret = connector_status_connected; } else { amdgpu_connector->use_digital = - !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + drm_edid_is_digital(amdgpu_connector->edid); /* some oems have boards with separate digital and analog connectors * with a shared ddc line (often vga + hdmi) */ if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); ret = connector_status_disconnected; } else { ret = connector_status_connected; @@ -983,7 +1025,7 @@ static void amdgpu_connector_shared_ddc(enum drm_connector_status *status, /* hpd is our only option in this case */ if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); *status = connector_status_disconnected; } } @@ -1052,23 +1094,23 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) } if (dret) { amdgpu_connector->detected_by_load = false; - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); amdgpu_connector_get_edid(connector); if (!amdgpu_connector->edid) { - DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", + drm_err(adev_to_drm(adev), "%s: probed a monitor but no|invalid EDID\n", connector->name); ret = connector_status_connected; broken_edid = true; /* defer use_digital to later */ } else { amdgpu_connector->use_digital = - !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); + drm_edid_is_digital(amdgpu_connector->edid); /* some oems have boards with separate digital and analog connectors * with a shared ddc line (often vga + hdmi) */ if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); ret = connector_status_disconnected; } else { ret = connector_status_connected; @@ -1104,8 +1146,15 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) continue; @@ -1154,8 +1203,15 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (amdgpu_connector->use_digital == true) { if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) return encoder; @@ -1170,7 +1226,11 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) /* then check use digitial */ /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1213,7 +1273,11 @@ static int amdgpu_max_hdmi_pixel_clock(const struct amdgpu_device *adev) * Return: drm_mode_status indicating whether the mode is valid. */ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -1238,13 +1302,19 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector case CONNECTOR_OBJECT_ID_HDMI_TYPE_B: max_digital_pixel_clock_khz = max_dvi_single_link_pixel_clock * 2; break; + default: + return MODE_BAD; } /* When the display EDID claims that it's an HDMI display, * we use the HDMI encoder mode of the display HW, * so we should verify against the max HDMI clock here. */ - if (connector->display_info.is_hdmi) +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) + if (connector->display_info.is_hdmi) +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) +#endif max_digital_pixel_clock_khz = max_hdmi_pixel_clock; if (mode->clock > max_digital_pixel_clock_khz) @@ -1348,8 +1418,15 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); switch (amdgpu_encoder->encoder_id) { @@ -1368,9 +1445,16 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + int i; +#endif bool found = false; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) found = true; @@ -1416,7 +1500,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) goto out; } - amdgpu_connector_free_edid(connector); + drm_edid_free(amdgpu_connector->edid); if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { @@ -1493,7 +1577,11 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) } static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, - const struct drm_display_mode *mode) +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT + const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; @@ -1531,7 +1619,11 @@ static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { return amdgpu_atombios_dp_mode_valid_helper(connector, mode); } else { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; @@ -1667,7 +1759,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, if (router->ddc_valid || router->cd_valid) { amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); if (!amdgpu_connector->router_bus) - DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); } if (is_dp_bridge) { @@ -1681,7 +1774,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, has_aux = true; ddc = &amdgpu_connector->ddc_bus->adapter; } else { - DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); } } switch (connector_type) { @@ -1775,7 +1869,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, if (i2c_bus->valid) { amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); if (!amdgpu_connector->ddc_bus) - DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); else ddc = &amdgpu_connector->ddc_bus->adapter; } @@ -1800,7 +1895,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, if (i2c_bus->valid) { amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); if (!amdgpu_connector->ddc_bus) - DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); else ddc = &amdgpu_connector->ddc_bus->adapter; } @@ -1830,7 +1926,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, if (i2c_bus->valid) { amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); if (!amdgpu_connector->ddc_bus) - DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); else ddc = &amdgpu_connector->ddc_bus->adapter; } @@ -1886,7 +1983,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, if (i2c_bus->valid) { amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); if (!amdgpu_connector->ddc_bus) - DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); else ddc = &amdgpu_connector->ddc_bus->adapter; } @@ -1937,7 +2035,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, has_aux = true; ddc = &amdgpu_connector->ddc_bus->adapter; } else { - DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); } } drm_connector_init_with_ddc(dev, &amdgpu_connector->base, @@ -1985,7 +2084,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, has_aux = true; ddc = &amdgpu_connector->ddc_bus->adapter; } else { - DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "eDP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); } } drm_connector_init_with_ddc(dev, &amdgpu_connector->base, @@ -2008,7 +2108,8 @@ amdgpu_connector_add(struct amdgpu_device *adev, if (i2c_bus->valid) { amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); if (!amdgpu_connector->ddc_bus) - DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); + drm_err(adev_to_drm(adev), + "LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); else ddc = &amdgpu_connector->ddc_bus->adapter; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c index 425a3e5643608..c72c345334d01 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c @@ -23,6 +23,7 @@ */ #include #include "amdgpu.h" +#include "amdgpu_ras_mgr.h" static const guid_t MCE = CPER_NOTIFY_MCE; static const guid_t CMC = CPER_NOTIFY_CMC; @@ -559,7 +560,10 @@ int amdgpu_cper_init(struct amdgpu_device *adev) { int r; - if (!amdgpu_aca_is_enabled(adev) && !amdgpu_sriov_ras_cper_en(adev)) + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_ras_cper_en(adev)) + return 0; + else if (!amdgpu_sriov_vf(adev) && !amdgpu_uniras_enabled(adev) && + !amdgpu_aca_is_enabled(adev)) return 0; r = amdgpu_cper_ring_init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ecdfe6cb36ccd..4ba772eddc698 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -41,6 +41,8 @@ #include "amdgpu_gem.h" #include "amdgpu_ras.h" #include "amdgpu_hmm.h" +#include "amdgpu_display.h" +#include "amdgpu_hmm.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, @@ -84,13 +86,6 @@ static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p, if (r) return r; - /* - * Abort if there is no run queue associated with this entity. - * Possibly because of disabled HW IP. - */ - if (entity->rq == NULL) - return -EINVAL; - /* Check if we can add this IB to some existing job */ for (i = 0; i < p->gang_size; ++i) if (p->entities[i] == entity) @@ -263,12 +258,15 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, case AMDGPU_CHUNK_ID_DEPENDENCIES: case AMDGPU_CHUNK_ID_SYNCOBJ_IN: case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: break; - default: goto free_partial_kdata; } @@ -280,9 +278,14 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, } for (i = 0; i < p->gang_size; ++i) { +#ifdef HAVE_DRM_FILE_CLIENT_ID ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm, num_ibs[i], &p->jobs[i], p->filp->client_id); +#else + ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm, + num_ibs[i], &p->jobs[i], 0); +#endif if (ret) goto free_all_kdata; switch (p->adev->enforce_isolation[fpriv->xcp_id]) { @@ -452,7 +455,6 @@ static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p, } return 0; } - static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p, uint32_t handle, u64 point, u64 flags) @@ -536,7 +538,9 @@ static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p, drm_syncobj_find(p->filp, deps[i].handle); if (!p->post_deps[i].syncobj) return -EINVAL; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) p->post_deps[i].chain = NULL; +#endif p->post_deps[i].point = 0; p->num_post_deps++; } @@ -566,14 +570,14 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, for (i = 0; i < num_deps; ++i) { struct amdgpu_cs_post_dep *dep = &p->post_deps[i]; - +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) dep->chain = NULL; if (syncobj_deps[i].point) { dep->chain = dma_fence_chain_alloc(); if (!dep->chain) return -ENOMEM; } - +#endif dep->syncobj = drm_syncobj_find(p->filp, syncobj_deps[i].handle); if (!dep->syncobj) { @@ -610,7 +614,7 @@ static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) { unsigned int ce_preempt = 0, de_preempt = 0; - int i, r; + int i, r = 0; for (i = 0; i < p->nchunks; ++i) { struct amdgpu_cs_chunk *chunk; @@ -624,7 +628,9 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) return r; break; case AMDGPU_CHUNK_ID_DEPENDENCIES: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif r = amdgpu_cs_p2_dependencies(p, chunk); if (r) return r; @@ -639,6 +645,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk); if (r) @@ -649,6 +656,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: r = amdgpu_cs_p2_shadow(p, chunk); if (r) @@ -657,6 +665,11 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } + for (i = 0; i < p->gang_size; ++i) { + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->sync); + if (r) + return r; + } return 0; } @@ -804,7 +817,7 @@ static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) struct ttm_operation_ctx ctx = { .interruptible = true, .no_wait_gpu = false, - .resv = bo->tbo.base.resv + .resv = amdkcl_ttm_resvp(&bo->tbo), }; uint32_t domain; int r; @@ -861,6 +874,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo_list_entry *e; struct drm_gem_object *obj; unsigned long index; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + unsigned tries = 10; +#endif unsigned int i; int r; @@ -883,6 +899,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, mutex_lock(&p->bo_list->bo_list_mutex); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get userptr backing pages. If pages are updated after registered * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do * amdgpu_ttm_backend_bind() to flush and invalidate new pages @@ -892,8 +910,10 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo = e->bo; e->range = amdgpu_hmm_range_alloc(NULL); - if (unlikely(!e->range)) - return -ENOMEM; + if (unlikely(!e->range)) { + r = -ENOMEM; + goto out_free_user_pages; + } r = amdgpu_ttm_tt_get_user_pages(bo, e->range); if (r) @@ -934,29 +954,114 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct mm_struct *usermm; + usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); + if (usermm && usermm != current->mm) { + r = -EPERM; + goto out_free_user_pages; + } + if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && + e->user_invalidated) { + amdgpu_bo_placement_from_domain(e->bo, + AMDGPU_GEM_DOMAIN_CPU); + r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, + &ctx); + if (r) + goto out_free_user_pages; + amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, + e->range); + } + } +#else + while (1) { + struct list_head need_pages; + drm_exec_until_all_locked(&p->exec) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct mm_struct *usermm; + amdgpu_bo_list_for_each_entry(e, p->bo_list) { + /* One fence for TTM and one for each CS job */ + r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; - usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); - if (usermm && usermm != current->mm) { - r = -EPERM; - goto out_free_user_pages; + e->bo_va = amdgpu_vm_bo_find(vm, e->bo); + } + + if (p->uf_bo) { + r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + } } + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = e->bo; - if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && - e->user_invalidated) { - amdgpu_bo_placement_from_domain(e->bo, - AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, - &ctx); - if (r) - goto out_free_user_pages; + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { - amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, - e->range); + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + drm_exec_fini(&p->exec); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } } } +#endif amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, &p->bytes_moved_vis_threshold); @@ -993,11 +1098,24 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bo_list->oa_obj); return 0; + out_free_user_pages: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { amdgpu_hmm_range_free(e->range); e->range = NULL; } +#else +error_free_pages: + + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + if (!e->user_pages) + continue; + + release_pages(e->user_pages, e->tv.bo->ttm->num_pages); + kvfree(e->user_pages); + } +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return r; } @@ -1021,6 +1139,7 @@ static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p, struct amdgpu_job *job) { struct amdgpu_ring *ring = amdgpu_job_ring(job); + struct amdgpu_device *adev = ring->adev; unsigned int i; int r; @@ -1222,7 +1341,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) drm_exec_for_each_locked_object(&p->exec, index, obj) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); enum amdgpu_sync_mode sync_mode; sync_mode = amdgpu_bo_explicit_sync(bo) ? @@ -1268,6 +1387,7 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) int i; for (i = 0; i < p->num_post_deps; ++i) { +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) if (p->post_deps[i].chain && p->post_deps[i].point) { drm_syncobj_add_point(p->post_deps[i].syncobj, p->post_deps[i].chain, @@ -1277,6 +1397,10 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) drm_syncobj_replace_fence(p->post_deps[i].syncobj, p->fence); } +#else + drm_syncobj_replace_fence(p->post_deps[i].syncobj, + p->fence); +#endif } } @@ -1303,11 +1427,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, fence = &p->jobs[i]->base.s_fence->scheduled; dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&leader->base, fence); if (r) { dma_fence_put(fence); return r; } +#endif } if (p->gang_size > 1) { @@ -1315,6 +1441,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_job_set_gang_leader(p->jobs[i], leader); } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* No memory allocation is allowed while holding the notifier lock. * The lock is held until amdgpu_cs_submit is finished and fence is * added to BOs. @@ -1335,6 +1462,19 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, mutex_unlock(&p->adev->notifier_lock); return r; } +#else + /* No memory allocation is allowed while holding the mn lock */ + amdgpu_mn_lock(p->mn); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { + r = -ERESTARTSYS; + amdgpu_mn_unlock(p->mn); + return r; + } + } +#endif p->fence = dma_fence_get(&leader->base.s_fence->finished); drm_exec_for_each_locked_object(&p->exec, index, gobj) { @@ -1346,13 +1486,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (p->jobs[i] == leader) continue; - dma_resv_add_fence(gobj->resv, + dma_resv_add_fence(amdkcl_gem_resvp(gobj), &p->jobs[i]->base.s_fence->finished, DMA_RESV_USAGE_READ); } /* The gang leader as remembered as writer */ - dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE); + dma_resv_add_fence(amdkcl_gem_resvp(gobj), p->fence, DMA_RESV_USAGE_WRITE); } seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx], @@ -1378,7 +1518,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_unlock(&p->adev->notifier_lock); +#else + amdgpu_mn_unlock(p->mn); +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return 0; } @@ -1393,7 +1537,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) kfree(parser->post_deps[i].chain); +#endif } kfree(parser->post_deps); @@ -1747,6 +1893,13 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_amdgpu_fence *fences; int r; + /* + * fence_count must be non-zero; dma_fence_wait_any_timeout() + * does not accept an empty fence array. + */ + if (!wait->in.fence_count) + return -EINVAL; + /* Get the fences from userspace */ fences = memdup_array_user(u64_to_user_ptr(wait->in.fences), wait->in.fence_count, @@ -1796,7 +1949,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, *map = mapping; /* Double check that the BO is reserved by this CS */ - if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket) + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&(*bo)->tbo)) != &parser->exec.ticket) return -EINVAL; /* Make sure VRAM is allocated contigiously */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c index 02138aa557935..7b46bffb10ccb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c @@ -28,9 +28,13 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { - uint64_t addr = AMDGPU_VA_RESERVED_CSA_START(adev); - - addr = amdgpu_gmc_sign_extend(addr); + uint64_t addr; + if (adev->asic_type >= CHIP_NAVI10) { + addr = AMDGPU_VA_RESERVED_CSA_SIZE - AMDGPU_CSA_SIZE; + } else { + addr = AMDGPU_VA_RESERVED_CSA_START(adev); + addr = amdgpu_gmc_sign_extend(addr); + } return addr; } @@ -76,7 +80,8 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, r = drm_exec_lock_obj(&exec, &bo->tbo.base); drm_exec_retry_on_contention(&exec); if (unlikely(r)) { - DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r); + drm_err(adev_to_drm(adev), + "failed to reserve CSA,PD BOs: err=%d\n", r); goto error; } } @@ -92,7 +97,8 @@ int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, AMDGPU_PTE_EXECUTABLE); if (r) { - DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r); + drm_err(adev_to_drm(adev), + "failed to do bo_map on static CSA, err=%d\n", r); amdgpu_vm_bo_del(adev, *bo_va); goto error; } @@ -116,14 +122,16 @@ int amdgpu_unmap_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm, r = drm_exec_lock_obj(&exec, &bo->tbo.base); drm_exec_retry_on_contention(&exec); if (unlikely(r)) { - DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r); + drm_err(adev_to_drm(adev), + "failed to reserve CSA,PD BOs: err=%d\n", r); goto error; } } r = amdgpu_vm_bo_unmap(adev, bo_va, csa_addr); if (r) { - DRM_ERROR("failed to do bo_unmap on static CSA, err=%d\n", r); + drm_err(adev_to_drm(adev), + "failed to do bo_unmap on static CSA, err=%d\n", r); goto error; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index afedea02188dd..38c52df687d52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -216,6 +216,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, GFP_KERNEL); if (!entity) return -ENOMEM; + INIT_LIST_HEAD(&entity->sem_dep_list); + mutex_init(&entity->sem_lock); ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? ctx->init_priority : ctx->override_priority; @@ -232,13 +234,19 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, } else { struct amdgpu_fpriv *fpriv; - fpriv = container_of(ctx->ctx_mgr, struct amdgpu_fpriv, ctx_mgr); + /* TODO: Stop using fpriv here, we only need the xcp_id. */ + fpriv = container_of(ctx->mgr, struct amdgpu_fpriv, ctx_mgr); r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, &num_scheds, &scheds); if (r) goto error_free_entity; } + if (num_scheds == 0) { + r = -EINVAL; + goto error_free_entity; + } + /* disable load balance if the hw engine retains context among dependent jobs */ if (hw_ip == AMDGPU_HW_IP_VCN_ENC || hw_ip == AMDGPU_HW_IP_VCN_DEC || @@ -349,7 +357,6 @@ static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, else ctx->stable_pstate = current_stable_pstate; - ctx->ctx_mgr = &(fpriv->ctx_mgr); return 0; } @@ -438,18 +445,21 @@ int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, struct drm_sched_entity *ctx_entity; if (hw_ip >= AMDGPU_HW_IP_NUM) { - DRM_ERROR("unknown HW IP type: %d\n", hw_ip); + drm_err(adev_to_drm(ctx->mgr->adev), + "unknown HW IP type: %d\n", hw_ip); return -EINVAL; } /* Right now all IPs have only one instance - multiple rings. */ if (instance != 0) { - DRM_DEBUG("invalid ip instance: %d\n", instance); + drm_dbg(adev_to_drm(ctx->mgr->adev), + "invalid ip instance: %d\n", instance); return -EINVAL; } if (ring >= amdgpu_ctx_num_entities[hw_ip]) { - DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring); + drm_dbg(adev_to_drm(ctx->mgr->adev), + "invalid ring: %d %d\n", hw_ip, ring); return -EINVAL; } @@ -874,7 +884,8 @@ int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, r = dma_fence_wait(other, true); if (r < 0 && r != -ERESTARTSYS) - DRM_ERROR("Error (%ld) waiting for fence!\n", r); + drm_err(adev_to_drm(ctx->mgr->adev), + "AMDGPU: Error waiting for fence in ctx %p\n", ctx); dma_fence_put(other); return r; @@ -929,7 +940,7 @@ static void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) idr_for_each_entry(idp, ctx, id) { if (kref_read(&ctx->refcount) != 1) { - DRM_ERROR("ctx %p is still alive\n", ctx); + drm_err(adev_to_drm(mgr->adev), "ctx %p is still alive\n", ctx); continue; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index 090dfe86f75ba..e5eafa228388a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -39,25 +39,26 @@ struct amdgpu_ctx_entity { uint32_t hw_ip; uint64_t sequence; struct drm_sched_entity entity; + struct list_head sem_dep_list; + struct mutex sem_lock; struct dma_fence *fences[]; }; struct amdgpu_ctx { struct kref refcount; - struct amdgpu_ctx_mgr *mgr; + spinlock_t ring_lock; unsigned reset_counter; unsigned reset_counter_query; - uint64_t generation; - spinlock_t ring_lock; - struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM]; - bool preamble_presented; int32_t init_priority; int32_t override_priority; + uint32_t stable_pstate; atomic_t guilty; + bool preamble_presented; + uint64_t generation; unsigned long ras_counter_ce; unsigned long ras_counter_ue; - uint32_t stable_pstate; - struct amdgpu_ctx_mgr *ctx_mgr; + struct amdgpu_ctx_mgr *mgr; + struct amdgpu_ctx_entity *entities[AMDGPU_HW_IP_NUM][AMDGPU_MAX_ENTITY_NUM]; }; struct amdgpu_ctx_mgr { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 62d43b8cbe588..f21a57b7c74c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -39,6 +39,7 @@ #include "amdgpu_reset.h" #include "amdgpu_psp_ta.h" +#include "amdgpu_userq.h" #if defined(CONFIG_DEBUG_FS) @@ -616,6 +617,110 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user return r; } +/** + * amdgpu_debugfs_regs_pcie64_read - Read from a 64-bit PCIE register + * + * @f: open file handle + * @buf: User buffer to store read data in + * @size: Number of bytes to read + * @pos: Offset to seek to + */ +static ssize_t amdgpu_debugfs_regs_pcie64_read(struct file *f, char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x7 || *pos & 0x7) + return -EINVAL; + + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + r = amdgpu_virt_enable_access_debugfs(adev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + uint64_t value; + + value = RREG64_PCIE_EXT(*pos); + + r = put_user(value, (uint64_t *)buf); + if (r) + goto out; + + result += 8; + buf += 8; + *pos += 8; + size -= 8; + } + + r = result; +out: + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + amdgpu_virt_disable_access_debugfs(adev); + return r; +} + +/** + * amdgpu_debugfs_regs_pcie64_write - Write to a 64-bit PCIE register + * + * @f: open file handle + * @buf: User buffer to write data from + * @size: Number of bytes to write + * @pos: Offset to seek to + */ +static ssize_t amdgpu_debugfs_regs_pcie64_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = file_inode(f)->i_private; + ssize_t result = 0; + int r; + + if (size & 0x7 || *pos & 0x7) + return -EINVAL; + + r = pm_runtime_get_sync(adev_to_drm(adev)->dev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + r = amdgpu_virt_enable_access_debugfs(adev); + if (r < 0) { + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + return r; + } + + while (size) { + uint64_t value; + + r = get_user(value, (uint64_t *)buf); + if (r) + goto out; + + WREG64_PCIE_EXT(*pos, value); + + result += 8; + buf += 8; + *pos += 8; + size -= 8; + } + + r = result; +out: + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); + amdgpu_virt_disable_access_debugfs(adev); + return r; +} + /** * amdgpu_debugfs_regs_didt_read - Read from a DIDT register * @@ -638,7 +743,7 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf, if (size & 0x3 || *pos & 0x3) return -EINVAL; - if (!adev->didt_rreg) + if (!adev->reg.didt.rreg) return -EOPNOTSUPP; r = pm_runtime_get_sync(adev_to_drm(adev)->dev); @@ -696,7 +801,7 @@ static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user if (size & 0x3 || *pos & 0x3) return -EINVAL; - if (!adev->didt_wreg) + if (!adev->reg.didt.wreg) return -EOPNOTSUPP; r = pm_runtime_get_sync(adev_to_drm(adev)->dev); @@ -752,7 +857,7 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, ssize_t result = 0; int r; - if (!adev->smc_rreg) + if (!adev->reg.smc.rreg) return -EOPNOTSUPP; if (size & 0x3 || *pos & 0x3) @@ -810,7 +915,7 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * ssize_t result = 0; int r; - if (!adev->smc_wreg) + if (!adev->reg.smc.wreg) return -EOPNOTSUPP; if (size & 0x3 || *pos & 0x3) @@ -1524,6 +1629,12 @@ static const struct file_operations amdgpu_debugfs_regs_pcie_fops = { .write = amdgpu_debugfs_regs_pcie_write, .llseek = default_llseek }; +static const struct file_operations amdgpu_debugfs_regs_pcie64_fops = { + .owner = THIS_MODULE, + .read = amdgpu_debugfs_regs_pcie64_read, + .write = amdgpu_debugfs_regs_pcie64_write, + .llseek = default_llseek +}; static const struct file_operations amdgpu_debugfs_regs_smc_fops = { .owner = THIS_MODULE, .read = amdgpu_debugfs_regs_smc_read, @@ -1586,6 +1697,7 @@ static const struct file_operations *debugfs_regs[] = { &amdgpu_debugfs_gprwave_fops, &amdgpu_debugfs_regs_didt_fops, &amdgpu_debugfs_regs_pcie_fops, + &amdgpu_debugfs_regs_pcie64_fops, &amdgpu_debugfs_regs_smc_fops, &amdgpu_debugfs_gca_config_fops, &amdgpu_debugfs_sensors_fops, @@ -1603,6 +1715,7 @@ static const char * const debugfs_regs_names[] = { "amdgpu_gprwave", "amdgpu_regs_didt", "amdgpu_regs_pcie", + "amdgpu_regs_pcie64", "amdgpu_regs_smc", "amdgpu_gca_config", "amdgpu_sensors", @@ -1911,9 +2024,13 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) return -ENOMEM; /* Avoid accidently unparking the sched thread during GPU reset */ +#ifdef HAVE_DOWN_READ_KILLABLE r = down_read_killable(&adev->reset_domain->sem); if (r) goto pro_end; +#else + down_read(&adev->reset_domain->sem); +#endif /* stop the scheduler */ drm_sched_wqueue_stop(&ring->sched); @@ -1921,7 +2038,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) /* preempt the IB */ r = amdgpu_ring_preempt_ib(ring); if (r) { - DRM_WARN("failed to preempt ring %d\n", ring->idx); + drm_warn(adev_to_drm(adev), "failed to preempt ring %d\n", ring->idx); goto failure; } @@ -1929,7 +2046,7 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) if (atomic_read(&ring->fence_drv.last_seq) != ring->fence_drv.sync_seq) { - DRM_INFO("ring %d was preempted\n", ring->idx); + drm_info(adev_to_drm(adev), "ring %d was preempted\n", ring->idx); amdgpu_ib_preempt_mark_partial_job(ring); @@ -2016,14 +2133,16 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) ent = debugfs_create_file("amdgpu_preempt_ib", 0600, root, adev, &fops_ib_preempt); if (IS_ERR(ent)) { - DRM_ERROR("unable to create amdgpu_preempt_ib debugsfs file\n"); + drm_err(adev_to_drm(adev), + "unable to create amdgpu_preempt_ib debugsfs file\n"); return PTR_ERR(ent); } ent = debugfs_create_file("amdgpu_force_sclk", 0200, root, adev, &fops_sclk_set); if (IS_ERR(ent)) { - DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n"); + drm_err(adev_to_drm(adev), + "unable to create amdgpu_set_sclk debugsfs file\n"); return PTR_ERR(ent); } @@ -2036,7 +2155,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) r = amdgpu_debugfs_regs_init(adev); if (r) - DRM_ERROR("registering register debugfs failed (%d).\n", r); + drm_err(adev_to_drm(adev), "registering register debugfs failed (%d).\n", r); amdgpu_debugfs_firmware_init(adev); amdgpu_ta_if_debugfs_init(adev); @@ -2086,12 +2205,12 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) &amdgpu_evict_vram_fops); debugfs_create_file("amdgpu_evict_gtt", 0400, root, adev, &amdgpu_evict_gtt_fops); + debugfs_create_file("amdgpu_benchmark", 0200, root, adev, + &amdgpu_benchmark_fops); debugfs_create_file("amdgpu_test_ib", 0400, root, adev, &amdgpu_debugfs_test_ib_fops); debugfs_create_file("amdgpu_vm_info", 0444, root, adev, &amdgpu_debugfs_vm_info_fops); - debugfs_create_file("amdgpu_benchmark", 0200, root, adev, - &amdgpu_benchmark_fops); adev->debugfs_vbios_blob.data = adev->bios; adev->debugfs_vbios_blob.size = adev->bios_size; @@ -2154,10 +2273,61 @@ static const struct file_operations amdgpu_pt_info_fops = { .release = single_release, }; +static int amdgpu_mqd_info_read(struct seq_file *m, void *unused) +{ + struct amdgpu_usermode_queue *queue = m->private; + struct amdgpu_bo *bo; + int r; + + if (!queue || !queue->mqd.obj) + return -EINVAL; + + bo = amdgpu_bo_ref(queue->mqd.obj); + r = amdgpu_bo_reserve(bo, true); + if (r) { + amdgpu_bo_unref(&bo); + return -EINVAL; + } + + seq_printf(m, "queue_type: %d\n", queue->queue_type); + seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue->mqd.obj)); + + amdgpu_bo_unreserve(bo); + amdgpu_bo_unref(&bo); + + return 0; +} + +static int amdgpu_mqd_info_open(struct inode *inode, struct file *file) +{ + return single_open(file, amdgpu_mqd_info_read, inode->i_private); +} + +static const struct file_operations amdgpu_mqd_info_fops = { + .owner = THIS_MODULE, + .open = amdgpu_mqd_info_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +void amdgpu_debugfs_userq_init(struct drm_file *file, struct amdgpu_usermode_queue *queue, int qid) +{ +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT + char queue_name[32]; + + scnprintf(queue_name, sizeof(queue_name), "queue_%d", qid); + queue->debugfs_queue = debugfs_create_dir(queue_name, file->debugfs_client); + debugfs_create_file("mqd_info", 0444, queue->debugfs_queue, queue, &amdgpu_mqd_info_fops); +#endif +} + void amdgpu_debugfs_vm_init(struct drm_file *file) { +#ifdef STRUCT_DRM_FILE_DEBUGFS_CLIENT debugfs_create_file("vm_pagetable_info", 0444, file->debugfs_client, file, &amdgpu_pt_info_fops); +#endif } #else @@ -2172,4 +2342,9 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev) void amdgpu_debugfs_vm_init(struct drm_file *file) { } +void amdgpu_debugfs_userq_init(struct drm_file *file, + struct amdgpu_usermode_queue *queue, + int qid) +{ +} #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index e7b3c38e51864..e88b4a1e564c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,6 +25,7 @@ /* * Debugfs */ +struct amdgpu_usermode_queue; int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); @@ -34,4 +35,7 @@ void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); void amdgpu_debugfs_gem_init(struct amdgpu_device *adev); void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev); void amdgpu_debugfs_vm_init(struct drm_file *file); +void amdgpu_debugfs_userq_init(struct drm_file *file, + struct amdgpu_usermode_queue *queue, + int qid); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index 4e2fe6674db87..bbfda0be6d46e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -32,8 +32,16 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, bool vram_lost, struct amdgpu_job *job) { } +void amdgpu_coredump_init(struct amdgpu_device *adev) +{ +} +void amdgpu_coredump_fini(struct amdgpu_device *adev) +{ +} #else +#define AMDGPU_CORE_DUMP_SIZE_MAX (256 * 1024 * 1024) + const char *hw_ip_names[MAX_HWIP] = { [GC_HWIP] = "GC", [HDP_HWIP] = "HDP", @@ -187,20 +195,22 @@ static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev, drm_printf(p, "VPE feature version: %u, fw version: 0x%08x\n", adev->vpe.feature_version, adev->vpe.fw_version); - drm_printf(p, "\nVBIOS Information\n"); - drm_printf(p, "vbios name : %s\n", ctx->name); - drm_printf(p, "vbios pn : %s\n", ctx->vbios_pn); - drm_printf(p, "vbios version : %d\n", ctx->version); - drm_printf(p, "vbios ver_str : %s\n", ctx->vbios_ver_str); - drm_printf(p, "vbios date : %s\n", ctx->date); + if (adev->bios) { + drm_printf(p, "\nVBIOS Information\n"); + drm_printf(p, "vbios name : %s\n", ctx->name); + drm_printf(p, "vbios pn : %s\n", ctx->vbios_pn); + drm_printf(p, "vbios version : %d\n", ctx->version); + drm_printf(p, "vbios ver_str : %s\n", ctx->vbios_ver_str); + drm_printf(p, "vbios date : %s\n", ctx->date); + }else { + drm_printf(p, "\nVBIOS Information: NA\n"); + } } static ssize_t -amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, - void *data, size_t datalen) +amdgpu_devcoredump_format(char *buffer, size_t count, struct amdgpu_coredump_info *coredump) { struct drm_printer p; - struct amdgpu_coredump_info *coredump = data; struct drm_print_iterator iter; struct amdgpu_vm_fault_info *fault_info; struct amdgpu_ip_block *ip_block; @@ -208,7 +218,6 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, iter.data = buffer; iter.offset = 0; - iter.start = offset; iter.remain = count; p = drm_coredump_printer(&iter); @@ -261,6 +270,8 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, } } + amdgpu_discovery_dump(coredump->adev, &p); + /* IP firmware information */ drm_printf(&p, "\nIP Firmwares\n"); amdgpu_devcoredump_fw_info(coredump->adev, &p); @@ -320,9 +331,63 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, return count - iter.remain; } +static ssize_t +amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, + void *data, size_t datalen) +{ + struct amdgpu_coredump_info *coredump = data; + ssize_t byte_copied; + + if (!coredump) + return -ENODEV; + + if (!coredump->formatted) + return -ENODEV; + + if (offset >= coredump->formatted_size) + return 0; + + byte_copied = count < coredump->formatted_size - offset ? count : + coredump->formatted_size - offset; + memcpy(buffer, coredump->formatted + offset, byte_copied); + + return byte_copied; +} + static void amdgpu_devcoredump_free(void *data) { - kfree(data); + struct amdgpu_coredump_info *coredump = data; + + kvfree(coredump->formatted); + kvfree(data); +} + +static void amdgpu_devcoredump_deferred_work(struct work_struct *work) +{ + struct amdgpu_device *adev = container_of(work, typeof(*adev), coredump_work); + struct amdgpu_coredump_info *coredump = adev->coredump; + + /* Do a one-time preparation of the coredump output because + * repeatingly calling drm_coredump_printer is very slow. + */ + coredump->formatted_size = amdgpu_devcoredump_format( + NULL, AMDGPU_CORE_DUMP_SIZE_MAX, coredump); + coredump->formatted = kvzalloc(coredump->formatted_size, GFP_KERNEL); + if (!coredump->formatted) { + amdgpu_devcoredump_free(coredump); + goto end; + } + + amdgpu_devcoredump_format(coredump->formatted, coredump->formatted_size, coredump); + + /* If there's an existing coredump for this device, the free function will be + * called immediately so coredump might be invalid after the call to dev_coredumpm. + */ + dev_coredumpm(coredump->adev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT, + amdgpu_devcoredump_read, amdgpu_devcoredump_free); + +end: + adev->coredump = NULL; } void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, @@ -332,12 +397,13 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, struct amdgpu_coredump_info *coredump; struct drm_sched_job *s_job; - coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT); + /* No need to generate a new coredump if there's one in progress already. */ + if (work_pending(&adev->coredump_work)) + return; - if (!coredump) { - DRM_ERROR("%s: failed to allocate memory for coredump\n", __func__); + coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT); + if (!coredump) return; - } coredump->skip_vram_check = skip_vram_check; coredump->reset_vram_lost = vram_lost; @@ -361,11 +427,26 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, ktime_get_ts64(&coredump->reset_time); - dev_coredumpm(dev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT, - amdgpu_devcoredump_read, amdgpu_devcoredump_free); + /* Update the current coredump pointer (no lock needed, this function can only be called + * from a single thread) + */ + adev->coredump = coredump; + /* Kick off coredump formatting to a worker thread. */ + queue_work(system_unbound_wq, &adev->coredump_work); drm_info(dev, "AMDGPU device coredump file has been created\n"); drm_info(dev, "Check your /sys/class/drm/card%d/device/devcoredump/data\n", dev->primary->index); } + +void amdgpu_coredump_init(struct amdgpu_device *adev) +{ + INIT_WORK(&adev->coredump_work, amdgpu_devcoredump_deferred_work); +} + +void amdgpu_coredump_fini(struct amdgpu_device *adev) +{ + /* Finish deferred coredump formatting before HW/IP teardown. */ + flush_work(&adev->coredump_work); +} #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h index ef9772c6bcc9e..f8f2f4df129b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h @@ -35,12 +35,20 @@ struct amdgpu_coredump_info { struct amdgpu_device *adev; struct amdgpu_task_info reset_task_info; struct timespec64 reset_time; + bool skip_vram_check; bool reset_vram_lost; struct amdgpu_ring *ring; + /* Readable form of coredevdump, generate once to speed up + * reading it (see drm_coredump_printer's documentation). + */ + ssize_t formatted_size; + char *formatted; }; #endif void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, bool vram_lost, struct amdgpu_job *job); +void amdgpu_coredump_init(struct amdgpu_device *adev); +void amdgpu_coredump_fini(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d2c3885de711f..d5995665f535d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -31,11 +31,14 @@ #include #include #include +#include #include #include #include #include +#include #include +#include #include #include @@ -255,7 +258,11 @@ static void amdgpu_device_attr_sysfs_fini(struct amdgpu_device *adev) } static ssize_t amdgpu_sysfs_reg_state_get(struct file *f, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *attr, char *buf, +#else + struct bin_attribute *attr, char *buf, +#endif loff_t ppos, size_t count) { struct device *dev = kobj_to_dev(kobj); @@ -313,42 +320,6 @@ void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev) sysfs_remove_bin_file(&adev->dev->kobj, &bin_attr_reg_state); } -int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block) -{ - int r; - - if (ip_block->version->funcs->suspend) { - r = ip_block->version->funcs->suspend(ip_block); - if (r) { - dev_err(ip_block->adev->dev, - "suspend of IP block <%s> failed %d\n", - ip_block->version->funcs->name, r); - return r; - } - } - - ip_block->status.hw = false; - return 0; -} - -int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) -{ - int r; - - if (ip_block->version->funcs->resume) { - r = ip_block->version->funcs->resume(ip_block); - if (r) { - dev_err(ip_block->adev->dev, - "resume of IP block <%s> failed %d\n", - ip_block->version->funcs->name, r); - return r; - } - } - - ip_block->status.hw = true; - return 0; -} - /** * DOC: board_info * @@ -364,7 +335,7 @@ int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) * - "unknown" - Not known * */ - +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static ssize_t amdgpu_device_get_board_info(struct device *dev, struct device_attribute *attr, char *buf) @@ -416,6 +387,176 @@ static const struct attribute_group amdgpu_board_attrs_group = { .attrs = amdgpu_board_attrs, .is_visible = amdgpu_board_attrs_is_visible }; +#endif + +/** + * DOC: uma/carveout_options + * + * This is a read-only file that lists all available UMA allocation + * options and their corresponding indices. Example output:: + * + * $ cat uma/carveout_options + * 0: Minimum (512 MB) + * 1: (1 GB) + * 2: (2 GB) + * 3: (4 GB) + * 4: (6 GB) + * 5: (8 GB) + * 6: (12 GB) + * 7: Medium (16 GB) + * 8: (24 GB) + * 9: High (32 GB) + */ +static ssize_t carveout_options_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct amdgpu_uma_carveout_info *uma_info = &adev->uma_info; + uint32_t memory_carved; + ssize_t size = 0; + + if (!uma_info || !uma_info->num_entries) + return -ENODEV; + + for (int i = 0; i < uma_info->num_entries; i++) { + memory_carved = uma_info->entries[i].memory_carved_mb; + if (memory_carved >= SZ_1G/SZ_1M) { + size += sysfs_emit_at(buf, size, "%d: %s (%u GB)\n", + i, + uma_info->entries[i].name, + memory_carved >> 10); + } else { + size += sysfs_emit_at(buf, size, "%d: %s (%u MB)\n", + i, + uma_info->entries[i].name, + memory_carved); + } + } + + return size; +} +static DEVICE_ATTR_RO(carveout_options); + +/** + * DOC: uma/carveout + * + * This file is both readable and writable. When read, it shows the + * index of the current setting. Writing a valid index to this file + * allows users to change the UMA carveout size to the selected option + * on the next boot. + * + * The available options and their corresponding indices can be read + * from the uma/carveout_options file. + */ +static ssize_t carveout_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + + return sysfs_emit(buf, "%u\n", adev->uma_info.uma_option_index); +} + +static ssize_t carveout_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + struct amdgpu_uma_carveout_info *uma_info = &adev->uma_info; + struct amdgpu_uma_carveout_option *opt; + unsigned long val; + uint8_t flags; + int r; + + r = kstrtoul(buf, 10, &val); + if (r) + return r; + + if (val >= uma_info->num_entries) + return -EINVAL; + + val = array_index_nospec(val, uma_info->num_entries); + opt = &uma_info->entries[val]; + + if (!(opt->flags & AMDGPU_UMA_FLAG_AUTO) && + !(opt->flags & AMDGPU_UMA_FLAG_CUSTOM)) { + drm_err_once(ddev, "Option %lu not supported due to lack of Custom/Auto flag", val); + return -EINVAL; + } + + flags = opt->flags; + flags &= ~((flags & AMDGPU_UMA_FLAG_AUTO) >> 1); + + guard(mutex)(&uma_info->update_lock); + + r = amdgpu_acpi_set_uma_allocation_size(adev, val, flags); + if (r) + return r; + + uma_info->uma_option_index = val; + + return count; +} +static DEVICE_ATTR_RW(carveout); + +static struct attribute *amdgpu_uma_attrs[] = { + &dev_attr_carveout.attr, + &dev_attr_carveout_options.attr, + NULL +}; + +const struct attribute_group amdgpu_uma_attr_group = { + .name = "uma", + .attrs = amdgpu_uma_attrs +}; + +static void amdgpu_uma_sysfs_init(struct amdgpu_device *adev) +{ + int rc; + + if (!(adev->flags & AMD_IS_APU)) + return; + + if (!amdgpu_acpi_is_set_uma_allocation_size_supported()) + return; + + rc = amdgpu_atomfirmware_get_uma_carveout_info(adev, &adev->uma_info); + if (rc) { + drm_dbg(adev_to_drm(adev), + "Failed to parse UMA carveout info from VBIOS: %d\n", rc); + goto out_info; + } + + mutex_init(&adev->uma_info.update_lock); + + rc = devm_device_add_group(adev->dev, &amdgpu_uma_attr_group); + if (rc) { + drm_dbg(adev_to_drm(adev), "Failed to add UMA carveout sysfs interfaces %d\n", rc); + goto out_attr; + } + + return; + +out_attr: + mutex_destroy(&adev->uma_info.update_lock); +out_info: + return; +} + +static void amdgpu_uma_sysfs_fini(struct amdgpu_device *adev) +{ + struct amdgpu_uma_carveout_info *uma_info = &adev->uma_info; + + if (!amdgpu_acpi_is_set_uma_allocation_size_supported()) + return; + + mutex_destroy(&uma_info->update_lock); + uma_info->num_entries = 0; +} static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); @@ -684,739 +825,44 @@ void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, * register access helper functions. */ -/* Check if hw access should be skipped because of hotplug or device error */ -bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) -{ - if (adev->no_hw_access) - return true; - -#ifdef CONFIG_LOCKDEP - /* - * This is a bit complicated to understand, so worth a comment. What we assert - * here is that the GPU reset is not running on another thread in parallel. - * - * For this we trylock the read side of the reset semaphore, if that succeeds - * we know that the reset is not running in parallel. - * - * If the trylock fails we assert that we are either already holding the read - * side of the lock or are the reset thread itself and hold the write side of - * the lock. - */ - if (in_task()) { - if (down_read_trylock(&adev->reset_domain->sem)) - up_read(&adev->reset_domain->sem); - else - lockdep_assert_held(&adev->reset_domain->sem); - } -#endif - return false; -} - -/** - * amdgpu_device_rreg - read a memory mapped IO or indirect register - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @acc_flags: access flags which require special behavior - * - * Returns the 32 bit value from the offset specified. - */ -uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags) -{ - uint32_t ret; - - if (amdgpu_device_skip_hw_access(adev)) - return 0; - - if ((reg * 4) < adev->rmmio_size) { - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_kiq_rreg(adev, reg, 0); - up_read(&adev->reset_domain->sem); - } else { - ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - ret = adev->pcie_rreg(adev, reg * 4); - } - - trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); - - return ret; -} - -/* - * MMIO register read with bytes helper functions - * @offset:bytes offset from MMIO start - */ - -/** - * amdgpu_mm_rreg8 - read a memory mapped IO register - * - * @adev: amdgpu_device pointer - * @offset: byte aligned register offset - * - * Returns the 8 bit value from the offset specified. - */ -uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) -{ - if (amdgpu_device_skip_hw_access(adev)) - return 0; - - if (offset < adev->rmmio_size) - return (readb(adev->rmmio + offset)); - BUG(); -} - - -/** - * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @acc_flags: access flags which require special behavior - * @xcc_id: xcc accelerated compute core id - * - * Returns the 32 bit value from the offset specified. - */ -uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t acc_flags, - uint32_t xcc_id) -{ - uint32_t ret, rlcg_flag; - - if (amdgpu_device_skip_hw_access(adev)) - return 0; - - if ((reg * 4) < adev->rmmio_size) { - if (amdgpu_sriov_vf(adev) && - !amdgpu_sriov_runtime(adev) && - adev->gfx.rlc.rlcg_reg_access_supported && - amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, - GC_HWIP, false, - &rlcg_flag)) { - ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); - } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - ret = amdgpu_kiq_rreg(adev, reg, xcc_id); - up_read(&adev->reset_domain->sem); - } else { - ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - ret = adev->pcie_rreg(adev, reg * 4); - } - - return ret; -} - -/* - * MMIO register write with bytes helper functions - * @offset:bytes offset from MMIO start - * @value: the value want to be written to the register - */ - -/** - * amdgpu_mm_wreg8 - read a memory mapped IO register - * - * @adev: amdgpu_device pointer - * @offset: byte aligned register offset - * @value: 8 bit value to write - * - * Writes the value specified to the offset specified. - */ -void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) -{ - if (amdgpu_device_skip_hw_access(adev)) - return; - - if (offset < adev->rmmio_size) - writeb(value, adev->rmmio + offset); - else - BUG(); -} - -/** - * amdgpu_device_wreg - write to a memory mapped IO or indirect register - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @v: 32 bit value to write to the register - * @acc_flags: access flags which require special behavior - * - * Writes the value specified to the offset specified. - */ -void amdgpu_device_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags) -{ - if (amdgpu_device_skip_hw_access(adev)) - return; - - if ((reg * 4) < adev->rmmio_size) { - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - amdgpu_kiq_wreg(adev, reg, v, 0); - up_read(&adev->reset_domain->sem); - } else { - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - adev->pcie_wreg(adev, reg * 4, v); - } - - trace_amdgpu_device_wreg(adev->pdev->device, reg, v); -} - -/** - * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range - * - * @adev: amdgpu_device pointer - * @reg: mmio/rlc register - * @v: value to write - * @xcc_id: xcc accelerated compute core id - * - * this function is invoked only for the debugfs register access - */ -void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t xcc_id) -{ - if (amdgpu_device_skip_hw_access(adev)) - return; - - if (amdgpu_sriov_fullaccess(adev) && - adev->gfx.rlc.funcs && - adev->gfx.rlc.funcs->is_rlcg_access_range) { - if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) - return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); - } else if ((reg * 4) >= adev->rmmio_size) { - adev->pcie_wreg(adev, reg * 4, v); - } else { - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } -} - -/** - * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC - * - * @adev: amdgpu_device pointer - * @reg: dword aligned register offset - * @v: 32 bit value to write to the register - * @acc_flags: access flags which require special behavior - * @xcc_id: xcc accelerated compute core id - * - * Writes the value specified to the offset specified. - */ -void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t v, - uint32_t acc_flags, uint32_t xcc_id) -{ - uint32_t rlcg_flag; - - if (amdgpu_device_skip_hw_access(adev)) - return; - - if ((reg * 4) < adev->rmmio_size) { - if (amdgpu_sriov_vf(adev) && - !amdgpu_sriov_runtime(adev) && - adev->gfx.rlc.rlcg_reg_access_supported && - amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, - GC_HWIP, true, - &rlcg_flag)) { - amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); - } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { - amdgpu_kiq_wreg(adev, reg, v, xcc_id); - up_read(&adev->reset_domain->sem); - } else { - writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } - } else { - adev->pcie_wreg(adev, reg * 4, v); - } -} - -/** - * amdgpu_device_indirect_rreg - read an indirect register - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register address to read from - * - * Returns the value of indirect register @reg_addr - */ -u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, - u32 reg_addr) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - u32 r; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - r = readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, - u64 reg_addr) -{ - unsigned long flags, pcie_index, pcie_index_hi, pcie_data; - u32 r; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - - if (unlikely(!adev->nbio.funcs)) { - pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; - pcie_data = AMDGPU_PCIE_DATA_FALLBACK; - } else { - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - } - - if (reg_addr >> 32) { - if (unlikely(!adev->nbio.funcs)) - pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK; - else - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - } else { - pcie_index_hi = 0; - } - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - r = readl(pcie_data_offset); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -/** - * amdgpu_device_indirect_rreg64 - read a 64bits indirect register - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register address to read from - * - * Returns the value of indirect register @reg_addr - */ -u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, - u32 reg_addr) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - u64 r; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - /* read low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - r = readl(pcie_data_offset); - /* read high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - r |= ((u64)readl(pcie_data_offset) << 32); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, - u64 reg_addr) -{ - unsigned long flags, pcie_index, pcie_data; - unsigned long pcie_index_hi = 0; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - u64 r; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - /* read low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - r = readl(pcie_data_offset); - /* read high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - r |= ((u64)readl(pcie_data_offset) << 32); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - - return r; -} - -/** - * amdgpu_device_indirect_wreg - write an indirect register address - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register offset - * @reg_data: indirect register data - * - */ -void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, - u32 reg_addr, u32 reg_data) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - writel(reg_data, pcie_data_offset); - readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, - u64 reg_addr, u32 reg_data) -{ - unsigned long flags, pcie_index, pcie_index_hi, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - else - pcie_index_hi = 0; - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - writel(reg_data, pcie_data_offset); - readl(pcie_data_offset); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -/** - * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address - * - * @adev: amdgpu_device pointer - * @reg_addr: indirect register offset - * @reg_data: indirect register data - * - */ -void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, - u32 reg_addr, u64 reg_data) -{ - unsigned long flags, pcie_index, pcie_data; - void __iomem *pcie_index_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - - /* write low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); - readl(pcie_data_offset); - /* write high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - writel((u32)(reg_data >> 32), pcie_data_offset); - readl(pcie_data_offset); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, - u64 reg_addr, u64 reg_data) -{ - unsigned long flags, pcie_index, pcie_data; - unsigned long pcie_index_hi = 0; - void __iomem *pcie_index_offset; - void __iomem *pcie_index_hi_offset; - void __iomem *pcie_data_offset; - - pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); - pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); - if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) - pcie_index_hi = adev->nbio.funcs->get_pcie_index_hi_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; - pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; - if (pcie_index_hi != 0) - pcie_index_hi_offset = (void __iomem *)adev->rmmio + - pcie_index_hi * 4; - - /* write low 32 bits */ - writel(reg_addr, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); - readl(pcie_data_offset); - /* write high 32 bits */ - writel(reg_addr + 4, pcie_index_offset); - readl(pcie_index_offset); - if (pcie_index_hi != 0) { - writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - writel((u32)(reg_data >> 32), pcie_data_offset); - readl(pcie_data_offset); - - /* clear the high bits */ - if (pcie_index_hi != 0) { - writel(0, pcie_index_hi_offset); - readl(pcie_index_hi_offset); - } - - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - -/** - * amdgpu_device_get_rev_id - query device rev_id - * - * @adev: amdgpu_device pointer - * - * Return device rev_id - */ -u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) -{ - return adev->nbio.funcs->get_rev_id(adev); -} - -/** - * amdgpu_invalid_rreg - dummy reg read function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - * Returns the value in the register. - */ -static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg) -{ - dev_err(adev->dev, "Invalid callback to read register 0x%04X\n", reg); - BUG(); - return 0; -} - -static uint32_t amdgpu_invalid_rreg_ext(struct amdgpu_device *adev, uint64_t reg) -{ - dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); - BUG(); - return 0; -} - -/** - * amdgpu_invalid_wreg - dummy reg write function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * @v: value to write to the register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - */ -static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) -{ - dev_err(adev->dev, - "Invalid callback to write register 0x%04X with 0x%08X\n", reg, - v); - BUG(); -} - -static void amdgpu_invalid_wreg_ext(struct amdgpu_device *adev, uint64_t reg, uint32_t v) -{ - dev_err(adev->dev, - "Invalid callback to write register 0x%llX with 0x%08X\n", reg, - v); - BUG(); -} - -/** - * amdgpu_invalid_rreg64 - dummy 64 bit reg read function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - * Returns the value in the register. - */ -static uint64_t amdgpu_invalid_rreg64(struct amdgpu_device *adev, uint32_t reg) -{ - dev_err(adev->dev, "Invalid callback to read 64 bit register 0x%04X\n", - reg); - BUG(); - return 0; -} - -static uint64_t amdgpu_invalid_rreg64_ext(struct amdgpu_device *adev, uint64_t reg) -{ - dev_err(adev->dev, "Invalid callback to read register 0x%llX\n", reg); - BUG(); - return 0; -} - -/** - * amdgpu_invalid_wreg64 - dummy reg write function - * - * @adev: amdgpu_device pointer - * @reg: offset of register - * @v: value to write to the register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - */ -static void amdgpu_invalid_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) -{ - dev_err(adev->dev, - "Invalid callback to write 64 bit register 0x%04X with 0x%08llX\n", - reg, v); - BUG(); -} - -static void amdgpu_invalid_wreg64_ext(struct amdgpu_device *adev, uint64_t reg, uint64_t v) +/* Check if hw access should be skipped because of hotplug or device error */ +bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) { - dev_err(adev->dev, - "Invalid callback to write 64 bit register 0x%llX with 0x%08llX\n", - reg, v); - BUG(); -} + if (adev->no_hw_access) + return true; -/** - * amdgpu_block_invalid_rreg - dummy reg read function - * - * @adev: amdgpu_device pointer - * @block: offset of instance - * @reg: offset of register - * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). - * Returns the value in the register. - */ -static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev, - uint32_t block, uint32_t reg) -{ - dev_err(adev->dev, - "Invalid callback to read register 0x%04X in block 0x%04X\n", - reg, block); - BUG(); - return 0; +#ifdef CONFIG_LOCKDEP + /* + * This is a bit complicated to understand, so worth a comment. What we assert + * here is that the GPU reset is not running on another thread in parallel. + * + * For this we trylock the read side of the reset semaphore, if that succeeds + * we know that the reset is not running in parallel. + * + * If the trylock fails we assert that we are either already holding the read + * side of the lock or are the reset thread itself and hold the write side of + * the lock. + */ + if (in_task()) { + if (down_read_trylock(&adev->reset_domain->sem)) + up_read(&adev->reset_domain->sem); + else + lockdep_assert_held(&adev->reset_domain->sem); + } +#endif + return false; } /** - * amdgpu_block_invalid_wreg - dummy reg write function + * amdgpu_device_get_rev_id - query device rev_id * * @adev: amdgpu_device pointer - * @block: offset of instance - * @reg: offset of register - * @v: value to write to the register * - * Dummy register read function. Used for register blocks - * that certain asics don't have (all asics). + * Return device rev_id */ -static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, - uint32_t block, - uint32_t reg, uint32_t v) +u32 amdgpu_device_get_rev_id(struct amdgpu_device *adev) { - dev_err(adev->dev, - "Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n", - reg, block, v); - BUG(); + return adev->nbio.funcs->get_rev_id(adev); } static uint32_t amdgpu_device_get_vbios_flags(struct amdgpu_device *adev) @@ -1664,6 +1110,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) spin_unlock_irqrestore(&adev->wb.lock, flags); } +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR /** * amdgpu_device_resize_fb_bar - try to resize FB BAR * @@ -1739,15 +1186,33 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) /* Tear down doorbell as resizing will release BARs */ amdgpu_doorbell_fini(adev); +#ifdef HAVE_PCI_RESIZE_RESOURCE_ALIGN r = pci_resize_resource(adev->pdev, 0, rbar_size, (adev->asic_type >= CHIP_BONAIRE) ? 1 << 5 : 1 << 2); + + if (r == -ENOSPC) + dev_info(adev->dev, + "Not enough PCI address space for a large BAR."); + else if (r && r != -ENOTSUPP) + dev_err(adev->dev, "Problem resizing BAR0 (%d).", r); +#else + if (adev->asic_type >= CHIP_BONAIRE) + pci_release_resource(adev->pdev, 2); + + pci_release_resource(adev->pdev, 0); + + r = pci_resize_resource(adev->pdev, 0, rbar_size); + if (r == -ENOSPC) dev_info(adev->dev, "Not enough PCI address space for a large BAR."); else if (r && r != -ENOTSUPP) dev_err(adev->dev, "Problem resizing BAR0 (%d).", r); + pci_assign_unassigned_bus_resources(adev->pdev->bus); +#endif + /* When the doorbell or fb BAR isn't available we have no chance of * using the device. */ @@ -1759,6 +1224,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) return 0; } +#endif /* * GPU helpers function. @@ -1945,7 +1411,11 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) return false; if (amdgpu_device_aspm_support_quirk(adev)) return false; +#ifdef HAVE_PCIE_ASPM_ENABLED return pcie_aspm_enabled(adev->pdev); +#else + return false; +#endif } /* if we get transitioned to only one device, take VGA back */ @@ -1958,11 +1428,18 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) * Enable/disable vga decode (all asics). * Returns VGA resource flags. */ +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, bool state) +#else +static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) +#endif { +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); - +#else + struct amdgpu_device *adev = cookie; +#endif amdgpu_asic_set_vga_state(adev, state); if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | @@ -2134,422 +1611,140 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) /* valid range is between 4 and 9 inclusive */ if (amdgpu_vm_fragment_size != -1 && (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) { - dev_warn(adev->dev, "valid range is between 4 and 9\n"); - amdgpu_vm_fragment_size = -1; - } - - if (amdgpu_sched_hw_submission < 2) { - dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", - amdgpu_sched_hw_submission); - amdgpu_sched_hw_submission = 2; - } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { - dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", - amdgpu_sched_hw_submission); - amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); - } - - if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) { - dev_warn(adev->dev, "invalid option for reset method, reverting to default\n"); - amdgpu_reset_method = -1; - } - - amdgpu_device_check_smu_prv_buffer_size(adev); - - amdgpu_device_check_vm_size(adev); - - amdgpu_device_check_block_size(adev); - - adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); - - for (i = 0; i < MAX_XCP; i++) { - switch (amdgpu_enforce_isolation) { - case -1: - case 0: - default: - /* disable */ - adev->enforce_isolation[i] = AMDGPU_ENFORCE_ISOLATION_DISABLE; - break; - case 1: - /* enable */ - adev->enforce_isolation[i] = - AMDGPU_ENFORCE_ISOLATION_ENABLE; - break; - case 2: - /* enable legacy mode */ - adev->enforce_isolation[i] = - AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY; - break; - case 3: - /* enable only process isolation without submitting cleaner shader */ - adev->enforce_isolation[i] = - AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER; - break; - } - } - - return 0; -} - -/** - * amdgpu_switcheroo_set_state - set switcheroo state - * - * @pdev: pci dev pointer - * @state: vga_switcheroo state - * - * Callback for the switcheroo driver. Suspends or resumes - * the asics before or after it is powered up using ACPI methods. - */ -static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, - enum vga_switcheroo_state state) -{ - struct drm_device *dev = pci_get_drvdata(pdev); - int r; - - if (amdgpu_device_supports_px(drm_to_adev(dev)) && - state == VGA_SWITCHEROO_OFF) - return; - - if (state == VGA_SWITCHEROO_ON) { - pr_info("switched on\n"); - /* don't suspend or resume card normally */ - dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; - - pci_set_power_state(pdev, PCI_D0); - amdgpu_device_load_pci_state(pdev); - r = pci_enable_device(pdev); - if (r) - dev_warn(&pdev->dev, "pci_enable_device failed (%d)\n", - r); - amdgpu_device_resume(dev, true); - - dev->switch_power_state = DRM_SWITCH_POWER_ON; - } else { - dev_info(&pdev->dev, "switched off\n"); - dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; - amdgpu_device_prepare(dev); - amdgpu_device_suspend(dev, true); - amdgpu_device_cache_pci_state(pdev); - /* Shut down the device */ - pci_disable_device(pdev); - pci_set_power_state(pdev, PCI_D3cold); - dev->switch_power_state = DRM_SWITCH_POWER_OFF; - } -} - -/** - * amdgpu_switcheroo_can_switch - see if switcheroo state can change - * - * @pdev: pci dev pointer - * - * Callback for the switcheroo driver. Check of the switcheroo - * state can be changed. - * Returns true if the state can be changed, false if not. - */ -static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) -{ - struct drm_device *dev = pci_get_drvdata(pdev); - - /* - * FIXME: open_count is protected by drm_global_mutex but that would lead to - * locking inversion with the driver load path. And the access here is - * completely racy anyway. So don't bother with locking for now. - */ - return atomic_read(&dev->open_count) == 0; -} - -static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { - .set_gpu_state = amdgpu_switcheroo_set_state, - .reprobe = NULL, - .can_switch = amdgpu_switcheroo_can_switch, -}; - -/** - * amdgpu_device_ip_set_clockgating_state - set the CG state - * - * @dev: amdgpu_device pointer - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) - * @state: clockgating state (gate or ungate) - * - * Sets the requested clockgating state for all instances of - * the hardware IP specified. - * Returns the error code from the last instance. - */ -int amdgpu_device_ip_set_clockgating_state(void *dev, - enum amd_ip_block_type block_type, - enum amd_clockgating_state state) -{ - struct amdgpu_device *adev = dev; - int i, r = 0; - - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; - if (adev->ip_blocks[i].version->type != block_type) - continue; - if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) - continue; - r = adev->ip_blocks[i].version->funcs->set_clockgating_state( - &adev->ip_blocks[i], state); - if (r) - dev_err(adev->dev, - "set_clockgating_state of IP block <%s> failed %d\n", - adev->ip_blocks[i].version->funcs->name, r); - } - return r; -} - -/** - * amdgpu_device_ip_set_powergating_state - set the PG state - * - * @dev: amdgpu_device pointer - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) - * @state: powergating state (gate or ungate) - * - * Sets the requested powergating state for all instances of - * the hardware IP specified. - * Returns the error code from the last instance. - */ -int amdgpu_device_ip_set_powergating_state(void *dev, - enum amd_ip_block_type block_type, - enum amd_powergating_state state) -{ - struct amdgpu_device *adev = dev; - int i, r = 0; - - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; - if (adev->ip_blocks[i].version->type != block_type) - continue; - if (!adev->ip_blocks[i].version->funcs->set_powergating_state) - continue; - r = adev->ip_blocks[i].version->funcs->set_powergating_state( - &adev->ip_blocks[i], state); - if (r) - dev_err(adev->dev, - "set_powergating_state of IP block <%s> failed %d\n", - adev->ip_blocks[i].version->funcs->name, r); - } - return r; -} - -/** - * amdgpu_device_ip_get_clockgating_state - get the CG state - * - * @adev: amdgpu_device pointer - * @flags: clockgating feature flags - * - * Walks the list of IPs on the device and updates the clockgating - * flags for each IP. - * Updates @flags with the feature flags for each hardware IP where - * clockgating is enabled. - */ -void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, - u64 *flags) -{ - int i; - - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; - if (adev->ip_blocks[i].version->funcs->get_clockgating_state) - adev->ip_blocks[i].version->funcs->get_clockgating_state( - &adev->ip_blocks[i], flags); - } -} - -/** - * amdgpu_device_ip_wait_for_idle - wait for idle - * - * @adev: amdgpu_device pointer - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) - * - * Waits for the request hardware IP to be idle. - * Returns 0 for success or a negative error code on failure. - */ -int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type) -{ - int i, r; - - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; - if (adev->ip_blocks[i].version->type == block_type) { - if (adev->ip_blocks[i].version->funcs->wait_for_idle) { - r = adev->ip_blocks[i].version->funcs->wait_for_idle( - &adev->ip_blocks[i]); - if (r) - return r; - } - break; - } + dev_warn(adev->dev, "valid range is between 4 and 9\n"); + amdgpu_vm_fragment_size = -1; } - return 0; - -} -/** - * amdgpu_device_ip_is_hw - is the hardware IP enabled - * - * @adev: amdgpu_device pointer - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) - * - * Check if the hardware IP is enable or not. - * Returns true if it the IP is enable, false if not. - */ -bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, - enum amd_ip_block_type block_type) -{ - int i; + if (amdgpu_sched_hw_submission < 2) { + dev_warn(adev->dev, "sched hw submission jobs (%d) must be at least 2\n", + amdgpu_sched_hw_submission); + amdgpu_sched_hw_submission = 2; + } else if (!is_power_of_2(amdgpu_sched_hw_submission)) { + dev_warn(adev->dev, "sched hw submission jobs (%d) must be a power of 2\n", + amdgpu_sched_hw_submission); + amdgpu_sched_hw_submission = roundup_pow_of_two(amdgpu_sched_hw_submission); + } - for (i = 0; i < adev->num_ip_blocks; i++) { - if (adev->ip_blocks[i].version->type == block_type) - return adev->ip_blocks[i].status.hw; + if (amdgpu_reset_method < -1 || amdgpu_reset_method > 4) { + dev_warn(adev->dev, "invalid option for reset method, reverting to default\n"); + amdgpu_reset_method = -1; } - return false; -} -/** - * amdgpu_device_ip_is_valid - is the hardware IP valid - * - * @adev: amdgpu_device pointer - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) - * - * Check if the hardware IP is valid or not. - * Returns true if it the IP is valid, false if not. - */ -bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, - enum amd_ip_block_type block_type) -{ - int i; + amdgpu_device_check_smu_prv_buffer_size(adev); - for (i = 0; i < adev->num_ip_blocks; i++) { - if (adev->ip_blocks[i].version->type == block_type) - return adev->ip_blocks[i].status.valid; - } - return false; + amdgpu_device_check_vm_size(adev); -} + amdgpu_device_check_block_size(adev); -/** - * amdgpu_device_ip_get_ip_block - get a hw IP pointer - * - * @adev: amdgpu_device pointer - * @type: Type of hardware IP (SMU, GFX, UVD, etc.) - * - * Returns a pointer to the hardware IP block structure - * if it exists for the asic, otherwise NULL. - */ -struct amdgpu_ip_block * -amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, - enum amd_ip_block_type type) -{ - int i; + adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); + amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96); - for (i = 0; i < adev->num_ip_blocks; i++) - if (adev->ip_blocks[i].version->type == type) - return &adev->ip_blocks[i]; + for (i = 0; i < MAX_XCP; i++) { + switch (amdgpu_enforce_isolation) { + case -1: + case 0: + default: + /* disable */ + adev->enforce_isolation[i] = AMDGPU_ENFORCE_ISOLATION_DISABLE; + break; + case 1: + /* enable */ + adev->enforce_isolation[i] = + AMDGPU_ENFORCE_ISOLATION_ENABLE; + break; + case 2: + /* enable legacy mode */ + adev->enforce_isolation[i] = + AMDGPU_ENFORCE_ISOLATION_ENABLE_LEGACY; + break; + case 3: + /* enable only process isolation without submitting cleaner shader */ + adev->enforce_isolation[i] = + AMDGPU_ENFORCE_ISOLATION_NO_CLEANER_SHADER; + break; + } + } - return NULL; + return 0; } /** - * amdgpu_device_ip_block_version_cmp + * amdgpu_switcheroo_set_state - set switcheroo state * - * @adev: amdgpu_device pointer - * @type: enum amd_ip_block_type - * @major: major version - * @minor: minor version + * @pdev: pci dev pointer + * @state: vga_switcheroo state * - * return 0 if equal or greater - * return 1 if smaller or the ip_block doesn't exist + * Callback for the switcheroo driver. Suspends or resumes + * the asics before or after it is powered up using ACPI methods. */ -int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, - enum amd_ip_block_type type, - u32 major, u32 minor) +static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, + enum vga_switcheroo_state state) { - struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); + struct drm_device *dev = pci_get_drvdata(pdev); + int r; - if (ip_block && ((ip_block->version->major > major) || - ((ip_block->version->major == major) && - (ip_block->version->minor >= minor)))) - return 0; + if (amdgpu_device_supports_px(drm_to_adev(dev)) && + state == VGA_SWITCHEROO_OFF) + return; - return 1; -} - -static const char *ip_block_names[] = { - [AMD_IP_BLOCK_TYPE_COMMON] = "common", - [AMD_IP_BLOCK_TYPE_GMC] = "gmc", - [AMD_IP_BLOCK_TYPE_IH] = "ih", - [AMD_IP_BLOCK_TYPE_SMC] = "smu", - [AMD_IP_BLOCK_TYPE_PSP] = "psp", - [AMD_IP_BLOCK_TYPE_DCE] = "dce", - [AMD_IP_BLOCK_TYPE_GFX] = "gfx", - [AMD_IP_BLOCK_TYPE_SDMA] = "sdma", - [AMD_IP_BLOCK_TYPE_UVD] = "uvd", - [AMD_IP_BLOCK_TYPE_VCE] = "vce", - [AMD_IP_BLOCK_TYPE_ACP] = "acp", - [AMD_IP_BLOCK_TYPE_VCN] = "vcn", - [AMD_IP_BLOCK_TYPE_MES] = "mes", - [AMD_IP_BLOCK_TYPE_JPEG] = "jpeg", - [AMD_IP_BLOCK_TYPE_VPE] = "vpe", - [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", - [AMD_IP_BLOCK_TYPE_ISP] = "isp", - [AMD_IP_BLOCK_TYPE_RAS] = "ras", -}; + if (state == VGA_SWITCHEROO_ON) { + pr_info("switched on\n"); + /* don't suspend or resume card normally */ + dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; -static const char *ip_block_name(struct amdgpu_device *adev, enum amd_ip_block_type type) -{ - int idx = (int)type; + pci_set_power_state(pdev, PCI_D0); + amdgpu_device_load_pci_state(pdev); + r = pci_enable_device(pdev); + if (r) + dev_warn(&pdev->dev, "pci_enable_device failed (%d)\n", + r); + amdgpu_device_resume(dev, true); - return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : "unknown"; + dev->switch_power_state = DRM_SWITCH_POWER_ON; + } else { + dev_info(&pdev->dev, "switched off\n"); + dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; + amdgpu_device_prepare(dev); + amdgpu_device_suspend(dev, true); + amdgpu_device_cache_pci_state(pdev); + /* Shut down the device */ + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3cold); + dev->switch_power_state = DRM_SWITCH_POWER_OFF; + } } /** - * amdgpu_device_ip_block_add + * amdgpu_switcheroo_can_switch - see if switcheroo state can change * - * @adev: amdgpu_device pointer - * @ip_block_version: pointer to the IP to add + * @pdev: pci dev pointer * - * Adds the IP block driver information to the collection of IPs - * on the asic. + * Callback for the switcheroo driver. Check of the switcheroo + * state can be changed. + * Returns true if the state can be changed, false if not. */ -int amdgpu_device_ip_block_add(struct amdgpu_device *adev, - const struct amdgpu_ip_block_version *ip_block_version) +static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) { - if (!ip_block_version) - return -EINVAL; - - switch (ip_block_version->type) { - case AMD_IP_BLOCK_TYPE_VCN: - if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) - return 0; - break; - case AMD_IP_BLOCK_TYPE_JPEG: - if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) - return 0; - break; - default: - break; - } - - dev_info(adev->dev, "detected ip block number %d <%s_v%d_%d_%d> (%s)\n", - adev->num_ip_blocks, - ip_block_name(adev, ip_block_version->type), - ip_block_version->major, - ip_block_version->minor, - ip_block_version->rev, - ip_block_version->funcs->name); - - adev->ip_blocks[adev->num_ip_blocks].adev = adev; - - adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; + struct drm_device *dev = pci_get_drvdata(pdev); - return 0; + /* + * FIXME: open_count is protected by drm_global_mutex but that would lead to + * locking inversion with the driver load path. And the access here is + * completely racy anyway. So don't bother with locking for now. + */ +#ifdef HAVE_DRM_DEVICE_OPEN_COUNT_INT + return dev->open_count == 0; +#else + return atomic_read(&dev->open_count) == 0; +#endif } +static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { + .set_gpu_state = amdgpu_switcheroo_set_state, + .reprobe = NULL, + .can_switch = amdgpu_switcheroo_can_switch, +}; + /** * amdgpu_device_enable_virtual_display - enable virtual display feature * @@ -2843,8 +2038,10 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) break; default: r = amdgpu_discovery_set_ip_blocks(adev); - if (r) + if (r) { + adev->num_ip_blocks = 0; return r; + } break; } @@ -3309,19 +2506,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) if (r) goto init_failed; - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); /* Don't init kfd if whole hive need to be reset during init */ if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { - kgd2kfd_init_zone_device(adev); amdgpu_amdkfd_device_init(adev); } amdgpu_fru_get_product_info(adev); - if (!amdgpu_sriov_vf(adev) || amdgpu_sriov_ras_cper_en(adev)) - r = amdgpu_cper_init(adev); + r = amdgpu_cper_init(adev); init_failed: @@ -3401,6 +2595,8 @@ int amdgpu_device_set_cg_state(struct amdgpu_device *adev, i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; if (!adev->ip_blocks[i].status.late_initialized) continue; + if (!adev->ip_blocks[i].version) + continue; /* skip CG for GFX, SDMA on S0ix */ if (adev->in_s0ix && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || @@ -3440,6 +2636,8 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev, i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j - 1; if (!adev->ip_blocks[i].status.late_initialized) continue; + if (!adev->ip_blocks[i].version) + continue; /* skip PG for GFX, SDMA on S0ix */ if (adev->in_s0ix && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || @@ -3647,6 +2845,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) int i, r; for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].version) + continue; if (!adev->ip_blocks[i].version->funcs->early_fini) continue; @@ -3658,10 +2858,8 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) } } - amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); - amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); - amdgpu_amdkfd_suspend(adev, true); + amdgpu_amdkfd_teardown_processes(adev); amdgpu_userq_suspend(adev); /* Workaround for ASICs need to disable SMC first */ @@ -3726,6 +2924,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.sw) continue; + if (!adev->ip_blocks[i].version) + continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) { amdgpu_ucode_free_bo(adev); amdgpu_free_static_csa(&adev->virt.csa_obj); @@ -3752,6 +2952,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_blocks[i].status.late_initialized) continue; + if (!adev->ip_blocks[i].version) + continue; if (adev->ip_blocks[i].version->funcs->late_fini) adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]); adev->ip_blocks[i].status.late_initialized = false; @@ -4203,8 +3405,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev) r = amdgpu_device_ip_resume_phase2(adev); - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); if (r) return r; @@ -4264,17 +3465,6 @@ bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, case CHIP_VERDE: case CHIP_OLAND: return amdgpu_dc != 0 && IS_ENABLED(CONFIG_DRM_AMD_DC_SI); - case CHIP_KAVERI: - case CHIP_KABINI: - case CHIP_MULLINS: - /* - * We have systems in the wild with these ASICs that require - * TRAVIS and NUTMEG support which is not supported with DC. - * - * Fallback to the non-DC driver here by default so as not to - * cause regressions. - */ - return amdgpu_dc > 0; default: return amdgpu_dc != 0; #else @@ -4351,7 +3541,8 @@ static void amdgpu_device_xgmi_reset_func(struct work_struct *__work) static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) { - char *input = amdgpu_lockup_timeout; + char buf[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; + char *input = buf; char *timeout_setting = NULL; int index = 0; long timeout; @@ -4361,9 +3552,17 @@ static int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev) adev->gfx_timeout = adev->compute_timeout = adev->sdma_timeout = adev->video_timeout = msecs_to_jiffies(2000); - if (!strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) + if (!strnlen(amdgpu_lockup_timeout, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) return 0; + /* + * strsep() destructively modifies its input by replacing delimiters + * with '\0'. Use a stack copy so the global module parameter buffer + * remains intact for multi-GPU systems where this function is called + * once per device. + */ + strscpy(buf, amdgpu_lockup_timeout, sizeof(buf)); + while ((timeout_setting = strsep(&input, ",")) && strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENGTH)) { ret = kstrtol(timeout_setting, 0, &timeout); @@ -4462,11 +3661,12 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) { int r; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = amdgpu_atombios_sysfs_init(adev); if (r) drm_err(&adev->ddev, "registering atombios sysfs failed (%d).\n", r); - +#endif r = amdgpu_pm_sysfs_init(adev); if (r) dev_err(adev->dev, "registering pm sysfs failed (%d).\n", r); @@ -4482,14 +3682,17 @@ static int amdgpu_device_sys_interface_init(struct amdgpu_device *adev) if (r) dev_err(adev->dev, "Could not create amdgpu device attr\n"); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); if (r) dev_err(adev->dev, "Could not create amdgpu board attributes\n"); +#endif amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); amdgpu_xcp_sysfs_init(adev); + amdgpu_uma_sysfs_init(adev); return r; } @@ -4505,6 +3708,7 @@ static void amdgpu_device_sys_interface_fini(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); amdgpu_xcp_sysfs_fini(adev); + amdgpu_uma_sysfs_fini(adev); } /** @@ -4550,26 +3754,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); - adev->smc_rreg = &amdgpu_invalid_rreg; - adev->smc_wreg = &amdgpu_invalid_wreg; - adev->pcie_rreg = &amdgpu_invalid_rreg; - adev->pcie_wreg = &amdgpu_invalid_wreg; - adev->pcie_rreg_ext = &amdgpu_invalid_rreg_ext; - adev->pcie_wreg_ext = &amdgpu_invalid_wreg_ext; - adev->pciep_rreg = &amdgpu_invalid_rreg; - adev->pciep_wreg = &amdgpu_invalid_wreg; - adev->pcie_rreg64 = &amdgpu_invalid_rreg64; - adev->pcie_wreg64 = &amdgpu_invalid_wreg64; - adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; - adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; - adev->uvd_ctx_rreg = &amdgpu_invalid_rreg; - adev->uvd_ctx_wreg = &amdgpu_invalid_wreg; - adev->didt_rreg = &amdgpu_invalid_rreg; - adev->didt_wreg = &amdgpu_invalid_wreg; - adev->gc_cac_rreg = &amdgpu_invalid_rreg; - adev->gc_cac_wreg = &amdgpu_invalid_wreg; - adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; - adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; + amdgpu_reg_access_init(adev); dev_info( adev->dev, @@ -4592,7 +3777,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.vf_errors.lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_init(&adev->notifier_lock); +#endif mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); mutex_init(&adev->gfx.reset_sem_mutex); @@ -4614,18 +3801,16 @@ int amdgpu_device_init(struct amdgpu_device *adev, return r; spin_lock_init(&adev->mmio_idx_lock); - spin_lock_init(&adev->smc_idx_lock); - spin_lock_init(&adev->pcie_idx_lock); - spin_lock_init(&adev->uvd_ctx_idx_lock); - spin_lock_init(&adev->didt_idx_lock); - spin_lock_init(&adev->gc_cac_idx_lock); - spin_lock_init(&adev->se_cac_idx_lock); - spin_lock_init(&adev->audio_endpt_idx_lock); spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->virt.rlcg_reg_lock); spin_lock_init(&adev->wb.lock); +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->userq_xa, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->userq_idr); + spin_lock_init(&adev->userq_lock); +#endif INIT_LIST_HEAD(&adev->reset_list); @@ -4658,6 +3843,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); INIT_WORK(&adev->userq_reset_work, amdgpu_userq_reset_work); + amdgpu_coredump_init(adev); + adev->gfx.gfx_off_req_count = 1; adev->gfx.gfx_off_residency = 0; adev->gfx.gfx_off_entrycount = 0; @@ -4673,7 +3860,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, */ ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); +#ifdef RATELIMIT_MSG_ON_RELEASE ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); +#endif /* Registers mapping */ /* TODO: block userspace mapping of io register */ @@ -4755,9 +3944,21 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_gmc_noretry_set(adev); /* Need to get xgmi info early to decide the reset behavior*/ if (adev->gmc.xgmi.supported) { - r = adev->gfxhub.funcs->get_xgmi_info(adev); - if (r) - return r; + if (adev->gfxhub.funcs && + adev->gfxhub.funcs->get_xgmi_info) { + r = adev->gfxhub.funcs->get_xgmi_info(adev); + if (r) + return r; + } + } + + if (adev->gmc.xgmi.connected_to_cpu) { + if (adev->mmhub.funcs && + adev->mmhub.funcs->get_xgmi_info) { + r = adev->mmhub.funcs->get_xgmi_info(adev); + if (r) + return r; + } } /* enable PCIE atomic ops */ @@ -4769,9 +3970,10 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* APUs w/ gfx9 onwards doesn't reply on PCIe atomics, rather it is a * internal path natively support atomics, set have_atomics_support to true. */ - } else if ((adev->flags & AMD_IS_APU) && - (amdgpu_ip_version(adev, GC_HWIP, 0) > - IP_VERSION(9, 0, 0))) { + } else if ((adev->flags & AMD_IS_APU && + amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(9, 0, 0)) || + (adev->gmc.xgmi.connected_to_cpu && + amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0))) { adev->have_atomics_support = true; } else { adev->have_atomics_support = @@ -4806,9 +4008,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, dev_info(adev->dev, "Pending hive reset.\n"); amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_MINIMAL_XGMI); - } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && - !amdgpu_device_has_display_hardware(adev)) { - r = psp_gpu_reset(adev); } else { tmp = amdgpu_reset_method; /* It should do a default reset when loading or reloading the driver, @@ -4874,6 +4073,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* init the mode config */ drm_mode_config_init(adev_to_drm(adev)); + if (amdgpu_sriov_vf(adev)) { + adev->timeout_wq = alloc_ordered_workqueue("amdgpu_ring_timeout_wq", 0); + if (!adev->timeout_wq) + dev_warn(adev->dev, "alloc_ordered_workqueue failed\n"); + } + r = amdgpu_device_ip_init(adev); if (r) { dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); @@ -4930,8 +4135,15 @@ int amdgpu_device_init(struct amdgpu_device *adev, flush_delayed_work(&adev->delayed_init_work); } + /* Don't init kfd if whole hive need to be reset during init */ + if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { + kgd2kfd_init_zone_device(adev); + kfd_update_svm_support_properties(adev); + } + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) amdgpu_xgmi_reset_on_init(adev); + /* * Place those sysfs registering after `late_init`. As some of those * operations performed in `late_init` might affect the sysfs @@ -4953,7 +4165,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, * ignore it */ if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); +#else + vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); +#endif px = amdgpu_device_supports_px(adev); @@ -5029,7 +4245,7 @@ static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) */ void amdgpu_device_fini_hw(struct amdgpu_device *adev) { - dev_info(adev->dev, "amdgpu: finishing device.\n"); + dev_info(adev->dev, "finishing device.\n"); flush_delayed_work(&adev->delayed_init_work); if (adev->mman.initialized) @@ -5046,6 +4262,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_virt_fini_data_exchange(adev); } + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); + /* disable all interrupts */ amdgpu_irq_disable_all(adev); if (adev->mode_info.mode_config_initialized) { @@ -5068,9 +4287,10 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) * before ip_fini_early to prevent kfd locking refcount issues by calling * amdgpu_amdkfd_suspend() */ - if (drm_dev_is_unplugged(adev_to_drm(adev))) + if (pci_dev_is_disconnected(adev->pdev)) amdgpu_amdkfd_device_fini_sw(adev); + amdgpu_coredump_fini(adev); amdgpu_device_ip_fini_early(adev); amdgpu_irq_fini_hw(adev); @@ -5080,7 +4300,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_gart_dummy_page_fini(adev); - if (drm_dev_is_unplugged(adev_to_drm(adev))) + if (pci_dev_is_disconnected(adev->pdev)) amdgpu_device_unmap_mmio(adev); } @@ -5128,7 +4348,11 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) vga_switcheroo_fini_domain_pm_ops(adev->dev); if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_unregister(adev->pdev); +#else + vga_client_register(adev->pdev, NULL, NULL, NULL); +#endif if (drm_dev_enter(adev_to_drm(adev), &idx)) { @@ -5341,8 +4565,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients) return 0; unwind_evict: - if (adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(adev, true); + amdgpu_ttm_set_buffer_funcs_status(adev, true); amdgpu_fence_driver_hw_init(adev); unwind_userq: @@ -5877,6 +5100,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) /* enable mmio access after mode 1 reset completed */ adev->no_hw_access = false; + /* ensure no_hw_access is updated before we access hw */ + smp_mb(); + amdgpu_device_load_pci_state(adev->pdev); ret = amdgpu_psp_wait_for_bootloader(adev); if (ret) @@ -6073,8 +5299,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) if (r) goto out; - if (tmp_adev->mman.buffer_funcs_ring->sched.ready) - amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); + amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); r = amdgpu_device_ip_resume_phase3(tmp_adev); if (r) @@ -6319,6 +5544,8 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + amdgpu_reset_domain_clear_pending(adev->reset_domain); + #if defined(CONFIG_DEBUG_FS) if (!amdgpu_sriov_vf(adev)) cancel_work(&adev->reset_work); @@ -6452,7 +5679,7 @@ static void amdgpu_device_halt_activities(struct amdgpu_device *adev, if (!amdgpu_ring_sched_ready(ring)) continue; - drm_sched_stop(&ring->sched, job ? &job->base : NULL); + drm_sched_wqueue_stop(&ring->sched); if (need_emergency_restart) amdgpu_job_stop_all_jobs_on_sched(&ring->sched); @@ -6536,7 +5763,7 @@ static int amdgpu_device_sched_resume(struct list_head *device_list, if (!amdgpu_ring_sched_ready(ring)) continue; - drm_sched_start(&ring->sched, 0); + drm_sched_wqueue_start(&ring->sched); } if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled) @@ -6551,7 +5778,7 @@ static int amdgpu_device_sched_resume(struct list_head *device_list, !amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) dev_info( tmp_adev->dev, - "GPU reset(%d) failed with error %d \n", + "GPU reset(%d) failed with error %d\n", atomic_read( &tmp_adev->gpu_reset_counter), tmp_adev->asic_reset_res); @@ -6626,6 +5853,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, /* save the pasid here as the job may be freed before the end of the reset */ int pasid = job ? job->pasid : -EINVAL; + if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) + return 0; + /* * If it reaches here because of hang/timeout and a RAS error is * detected at the same time, let RAS recovery take care of it. @@ -6693,7 +5923,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, * * job->base holds a reference to parent fence */ - if (job && dma_fence_is_signaled(&job->hw_fence->base)) { + if (job && (dma_fence_get_status(&job->hw_fence->base) > 0)) { job_signaled = true; dev_info(adev->dev, "Guilty job already signaled, skipping HW reset"); goto skip_hw_reset; @@ -7024,21 +6254,30 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) * Return true if @peer_adev can access (DMA) @adev through the PCIe * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of * @peer_adev. + * + * @note: CONFIG_HSA_AMD_P2P indicates support for P2P DMA mappings. Query + * P2PDMA distance only if the kernel has all the prerequisites for P2P DMA + * support. Otherwise fall back to the less reliable legacy P2P support to + * avoid regressions. + * */ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) { + bool p2p_access = true; + bool p2p_addressable = false; + bool is_large_bar = adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + #ifdef CONFIG_HSA_AMD_P2P - bool p2p_access = + p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); if (!p2p_access) dev_info(adev->dev, "PCIe P2P access from peer device %s is not supported by the chipset\n", pci_name(peer_adev->pdev)); - - bool is_large_bar = adev->gmc.visible_vram_size && - adev->gmc.real_vram_size == adev->gmc.visible_vram_size; - bool p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev); + p2p_addressable = amdgpu_device_check_iommu_remap(peer_adev); +#endif if (!p2p_addressable) { uint64_t address_mask = peer_adev->dev->dma_mask ? @@ -7050,9 +6289,6 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, aper_limit & address_mask); } return pcie_p2p && is_large_bar && p2p_access && p2p_addressable; -#else - return false; -#endif } int amdgpu_device_baco_enter(struct amdgpu_device *adev) @@ -7202,6 +6438,15 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) dev_info(adev->dev, "PCI error: slot reset callback!!\n"); memset(&reset_context, 0, sizeof(reset_context)); + INIT_LIST_HEAD(&device_list); + hive = amdgpu_get_xgmi_hive(adev); + if (hive) { + mutex_lock(&hive->hive_lock); + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) + list_add_tail(&tmp_adev->reset_list, &device_list); + } else { + list_add_tail(&adev->reset_list, &device_list); + } if (adev->pcie_reset_ctx.swus) link_dev = adev->pcie_reset_ctx.swus; @@ -7242,19 +6487,13 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) reset_context.reset_req_dev = adev; set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); - INIT_LIST_HEAD(&device_list); - hive = amdgpu_get_xgmi_hive(adev); if (hive) { - mutex_lock(&hive->hive_lock); reset_context.hive = hive; - list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) tmp_adev->pcie_reset_ctx.in_link_reset = true; - list_add_tail(&tmp_adev->reset_list, &device_list); - } } else { set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); - list_add_tail(&adev->reset_list, &device_list); } r = amdgpu_device_asic_reset(adev, &device_list, &reset_context); @@ -7501,6 +6740,9 @@ void amdgpu_device_halt(struct amdgpu_device *adev) amdgpu_xcp_dev_unplug(adev); drm_dev_unplug(ddev); + amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); + amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); + amdgpu_irq_disable_all(adev); amdgpu_fence_driver_hw_fini(adev); @@ -7513,39 +6755,6 @@ void amdgpu_device_halt(struct amdgpu_device *adev) pci_wait_for_pending_transaction(pdev); } -u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, - u32 reg) -{ - unsigned long flags, address, data; - u32 r; - - address = adev->nbio.funcs->get_pcie_port_index_offset(adev); - data = adev->nbio.funcs->get_pcie_port_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - WREG32(address, reg * 4); - (void)RREG32(address); - r = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); - return r; -} - -void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, - u32 reg, u32 v) -{ - unsigned long flags, address, data; - - address = adev->nbio.funcs->get_pcie_port_index_offset(adev); - data = adev->nbio.funcs->get_pcie_port_data_offset(adev); - - spin_lock_irqsave(&adev->pcie_idx_lock, flags); - WREG32(address, reg * 4); - (void)RREG32(address); - WREG32(data, v); - (void)RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); -} - /** * amdgpu_device_get_gang - return a reference to the current gang * @adev: amdgpu_device pointer @@ -7728,36 +6937,6 @@ bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev) } } -uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, - uint32_t inst, uint32_t reg_addr, char reg_name[], - uint32_t expected_value, uint32_t mask) -{ - uint32_t ret = 0; - uint32_t old_ = 0; - uint32_t tmp_ = RREG32(reg_addr); - uint32_t loop = adev->usec_timeout; - - while ((tmp_ & (mask)) != (expected_value)) { - if (old_ != tmp_) { - loop = adev->usec_timeout; - old_ = tmp_; - } else - udelay(1); - tmp_ = RREG32(reg_addr); - loop--; - if (!loop) { - dev_warn( - adev->dev, - "Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn", - inst, reg_name, (uint32_t)expected_value, - (uint32_t)(tmp_ & (mask))); - ret = -ETIMEDOUT; - break; - } - } - return ret; -} - ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring) { ssize_t size = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index fa2a22dfa0487..c3c6c4d1c8f22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -71,6 +71,7 @@ #include "nv.h" #include "soc21.h" #include "soc24.h" +#include "soc_v1_0.h" #include "navi10_ih.h" #include "ih_v6_0.h" #include "ih_v6_1.h" @@ -78,12 +79,15 @@ #include "gfx_v10_0.h" #include "gfx_v11_0.h" #include "gfx_v12_0.h" +#include "gfx_v12_1.h" #include "sdma_v5_0.h" #include "sdma_v5_2.h" #include "sdma_v6_0.h" #include "sdma_v7_0.h" +#include "sdma_v7_1.h" #include "lsdma_v6_0.h" #include "lsdma_v7_0.h" +#include "lsdma_v7_1.h" #include "vcn_v2_0.h" #include "jpeg_v2_0.h" #include "vcn_v3_0.h" @@ -97,16 +101,23 @@ #include "amdgpu_vkms.h" #include "mes_v11_0.h" #include "mes_v12_0.h" +#include "mes_v12_1.h" #include "smuio_v11_0.h" #include "smuio_v11_0_6.h" #include "smuio_v13_0.h" #include "smuio_v13_0_3.h" #include "smuio_v13_0_6.h" #include "smuio_v14_0_2.h" +#include "smuio_v15_0_0.h" +#include "smuio_v15_0_8.h" #include "vcn_v5_0_0.h" #include "vcn_v5_0_1.h" +#include "vcn_v5_0_2.h" #include "jpeg_v5_0_0.h" #include "jpeg_v5_0_1.h" +#include "jpeg_v5_0_2.h" +#include "jpeg_v5_3_0.h" + #include "amdgpu_ras_mgr.h" #include "amdgpu_vpe.h" @@ -124,6 +135,7 @@ MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); +/* Note: These registers are consistent across all the SOCs */ #define mmIP_DISCOVERY_VERSION 0x16A00 #define mmRCC_CONFIG_MEMSIZE 0xde3 #define mmMP0_SMN_C2PMSG_33 0x16061 @@ -131,6 +143,10 @@ MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); #define mmMM_INDEX_HI 0x6 #define mmMM_DATA 0x1 +#define mmDRIVER_SCRATCH_0 0x94 +#define mmDRIVER_SCRATCH_1 0x95 +#define mmDRIVER_SCRATCH_2 0x96 + static const char *hw_id_names[HW_ID_MAX] = { [MP1_HWID] = "MP1", [MP2_HWID] = "MP2", @@ -209,6 +225,8 @@ static const char *hw_id_names[HW_ID_MAX] = { [XGBE_HWID] = "XGBE", [MP0_HWID] = "MP0", [VPE_HWID] = "VPE", + [ATU_HWID] = "ATU", + [AIGC_HWID] = "AIGC", }; static int hw_id_map[MAX_HWIP] = { @@ -240,41 +258,15 @@ static int hw_id_map[MAX_HWIP] = { [PCIE_HWIP] = PCIE_HWID, [VPE_HWIP] = VPE_HWID, [ISP_HWIP] = ISP_HWID, + [ATU_HWIP] = ATU_HWID, }; -static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) +static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, + bool *is_tmr_in_sysmem) { - u64 tmr_offset, tmr_size, pos; - void *discv_regn; - int ret; - - ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); - if (ret) - return ret; - - pos = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; - - /* This region is read-only and reserved from system use */ - discv_regn = memremap(pos, adev->discovery.size, MEMREMAP_WC); - if (discv_regn) { - memcpy(binary, discv_regn, adev->discovery.size); - memunmap(discv_regn); - return 0; - } - - return -ENOENT; -} - -#define IP_DISCOVERY_V2 2 -#define IP_DISCOVERY_V4 4 - -static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, - uint8_t *binary) -{ - bool sz_valid = true; - uint64_t vram_size; - int i, ret = 0; - u32 msg; + u64 vram_size, tmr_offset, tmr_size; + u32 msg, tmr_offset_lo, tmr_offset_hi; + int i, ret; if (!amdgpu_sriov_vf(adev)) { /* It can take up to two second for IFWI init to complete on some dGPUs, @@ -294,51 +286,102 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, } vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); - if (!vram_size || vram_size == U32_MAX) - sz_valid = false; + if (vram_size == U32_MAX) + return -ENXIO; + else if (!vram_size) + *is_tmr_in_sysmem = true; else - vram_size <<= 20; + *is_tmr_in_sysmem = false; - /* - * If in VRAM, discovery TMR is marked for reservation. If it is in system mem, - * then it is not required to be reserved. - */ - if (sz_valid) { - if (amdgpu_sriov_vf(adev) && adev->virt.is_dynamic_crit_regn_enabled) { - /* For SRIOV VFs with dynamic critical region enabled, - * we will get the IPD binary via below call. - * If dynamic critical is disabled, fall through to normal seq. - */ - if (amdgpu_virt_get_dynamic_data_info(adev, - AMD_SRIOV_MSG_IPD_TABLE_ID, binary, - &adev->discovery.size)) { - dev_err(adev->dev, - "failed to read discovery info from dynamic critical region."); - ret = -EINVAL; - goto exit; - } + /* init the default tmr size and offset */ + adev->discovery.size = DISCOVERY_TMR_SIZE; + if (vram_size) + adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; + + if (amdgpu_sriov_vf(adev)) { + if (adev->virt.is_dynamic_crit_regn_enabled) { + adev->discovery.offset = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; + adev->discovery.size = + adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; + if (!adev->discovery.offset || !adev->discovery.size) + return -EINVAL; } else { - uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; + goto out; + } + } else { + tmr_size = RREG32(mmDRIVER_SCRATCH_2); + if (tmr_size) { + /* It's preferred to transition to PSP mailbox reg interface + * for both bare-metal and passthrough if available */ + adev->discovery.size = (u32)tmr_size; + tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); + tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); + adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | + le32_to_cpu(tmr_offset_lo)); + } else if (!vram_size) { + /* fall back to apci approach to query tmr offset if vram_size is 0 */ + ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); + if (ret) + return ret; + adev->discovery.size = DISCOVERY_TMR_SIZE; + adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; + } + } +out: + adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); + if (!adev->discovery.bin) + return -ENOMEM; + adev->discovery.debugfs_blob.data = adev->discovery.bin; + adev->discovery.debugfs_blob.size = adev->discovery.size; + + return 0; +} + +static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) +{ + void *discv_regn; + + /* This region is read-only and reserved from system use */ + discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); + if (discv_regn) { + memcpy(binary, discv_regn, adev->discovery.size); + memunmap(discv_regn); + return 0; + } + + return -ENOENT; +} + +#define IP_DISCOVERY_V2 2 +#define IP_DISCOVERY_V4 4 - amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, - adev->discovery.size, false); +static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, + uint8_t *binary, + bool is_tmr_in_sysmem) +{ + int ret = 0; + + if (!is_tmr_in_sysmem) { + if (amdgpu_sriov_vf(adev) && + amdgpu_sriov_xgmi_connected_to_cpu(adev)) { + ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); + } else { + amdgpu_device_vram_access(adev, adev->discovery.offset, + (uint32_t *)binary, + adev->discovery.size, false); adev->discovery.reserve_tmr = true; } } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } - if (ret) - dev_err(adev->dev, - "failed to read discovery info from memory, vram size read: %llx", - vram_size); -exit: return ret; } static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, - uint8_t *binary, - const char *fw_name) + uint8_t *binary, + const char *fw_name) { const struct firmware *fw; int r; @@ -369,10 +412,21 @@ static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size return checksum; } -static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size, +static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, + uint8_t *data, uint32_t size, uint16_t expected) { - return !!(amdgpu_discovery_calculate_checksum(data, size) == expected); + uint16_t calculated; + + calculated = amdgpu_discovery_calculate_checksum(data, size); + + if (calculated != expected) { + dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", + calculated, expected, size); + return false; + } + + return true; } static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) @@ -409,14 +463,12 @@ static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) } static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, - struct binary_header *bhdr) + struct table_info *info) { uint8_t *discovery_bin = adev->discovery.bin; - struct table_info *info; uint16_t checksum; uint16_t offset; - info = &bhdr->table_list[NPS_INFO]; offset = le16_to_cpu(info->offset); checksum = le16_to_cpu(info->checksum); @@ -428,7 +480,7 @@ static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, return -EINVAL; } - if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, + if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, le32_to_cpu(nhdr->size_bytes), checksum)) { dev_dbg(adev->dev, "invalid nps info data table checksum\n"); @@ -469,23 +521,130 @@ static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) } } -static int amdgpu_discovery_init(struct amdgpu_device *adev) +static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, + struct table_info **info, + uint16_t table_id) +{ + struct binary_header *bhdr = + (struct binary_header *)adev->discovery.bin; + struct binary_header_v2 *bhdrv2; + + switch (bhdr->version_major) { + case 2: + bhdrv2 = (struct binary_header_v2 *)adev->discovery.bin; + *info = &bhdrv2->table_list[table_id]; + break; + case 1: + *info = &bhdr->table_list[table_id]; + break; + default: + dev_err(adev->dev, "Invalid ip discovery table version\n"); + return -EINVAL; + } + + return 0; +} + +static int amdgpu_discovery_table_check(struct amdgpu_device *adev, + uint8_t *discovery_bin, + uint16_t table_id) { + int r, act_val, exp_val, table_size; + uint16_t offset, checksum; struct table_info *info; + bool check_table = true; + char *table_name; + + r = amdgpu_discovery_get_table_info(adev, &info, table_id); + if (r) + return r; + offset = le16_to_cpu(info->offset); + checksum = le16_to_cpu(info->checksum); + + switch (table_id) { + case IP_DISCOVERY: { + struct ip_discovery_header *ihdr = + (struct ip_discovery_header *)(discovery_bin + offset); + act_val = le32_to_cpu(ihdr->signature); + exp_val = DISCOVERY_TABLE_SIGNATURE; + table_size = le16_to_cpu(ihdr->size); + table_name = "data table"; + break; + } + case GC: { + struct gpu_info_header *ghdr = + (struct gpu_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(ghdr->table_id); + exp_val = GC_TABLE_ID; + table_size = le16_to_cpu(ghdr->size); + table_name = "gc table"; + break; + } + case HARVEST_INFO: { + struct harvest_info_header *hhdr = + (struct harvest_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(hhdr->signature); + exp_val = HARVEST_TABLE_SIGNATURE; + table_size = sizeof(struct harvest_table); + table_name = "harvest table"; + break; + } + case VCN_INFO: { + struct vcn_info_header *vhdr = + (struct vcn_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(vhdr->table_id); + exp_val = VCN_INFO_TABLE_ID; + table_size = le32_to_cpu(vhdr->size_bytes); + table_name = "vcn table"; + break; + } + case MALL_INFO: { + struct mall_info_header *mhdr = + (struct mall_info_header *)(discovery_bin + offset); + act_val = le32_to_cpu(mhdr->table_id); + exp_val = MALL_INFO_TABLE_ID; + table_size = le32_to_cpu(mhdr->size_bytes); + table_name = "mall table"; + check_table = false; + break; + } + default: + dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); + check_table = false; + break; + } + + if (check_table && offset) { + if (act_val != exp_val) { + dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); + return -EINVAL; + } + + if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, + table_size, checksum)) { + dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); + return -EINVAL; + } + } + + return 0; +} + +static int amdgpu_discovery_init(struct amdgpu_device *adev) +{ struct binary_header *bhdr; uint8_t *discovery_bin; const char *fw_name; uint16_t offset; uint16_t size; uint16_t checksum; + uint16_t table_id; + bool is_tmr_in_sysmem; int r; - adev->discovery.bin = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL); - if (!adev->discovery.bin) - return -ENOMEM; - adev->discovery.size = DISCOVERY_TMR_SIZE; - adev->discovery.debugfs_blob.data = adev->discovery.bin; - adev->discovery.debugfs_blob.size = adev->discovery.size; + r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); + if (r) + return r; discovery_bin = adev->discovery.bin; /* Read from file if it is the preferred option */ @@ -498,7 +657,8 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) goto out; } else { drm_dbg(&adev->ddev, "use ip discovery information from memory"); - r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin); + r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, + is_tmr_in_sysmem); if (r) goto out; } @@ -518,125 +678,17 @@ static int amdgpu_discovery_init(struct amdgpu_device *adev) size = le16_to_cpu(bhdr->binary_size) - offset; checksum = le16_to_cpu(bhdr->binary_checksum); - if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, size, + if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, checksum)) { dev_err(adev->dev, "invalid ip discovery binary checksum\n"); r = -EINVAL; goto out; } - info = &bhdr->table_list[IP_DISCOVERY]; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct ip_discovery_header *ihdr = - (struct ip_discovery_header *)(discovery_bin + offset); - if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) { - dev_err(adev->dev, "invalid ip discovery data table signature\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, - le16_to_cpu(ihdr->size), - checksum)) { - dev_err(adev->dev, "invalid ip discovery data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - info = &bhdr->table_list[GC]; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct gpu_info_header *ghdr = - (struct gpu_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(ghdr->table_id) != GC_TABLE_ID) { - dev_err(adev->dev, "invalid ip discovery gc table id\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum(discovery_bin + offset, - le32_to_cpu(ghdr->size), - checksum)) { - dev_err(adev->dev, "invalid gc data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - info = &bhdr->table_list[HARVEST_INFO]; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct harvest_info_header *hhdr = - (struct harvest_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(hhdr->signature) != HARVEST_TABLE_SIGNATURE) { - dev_err(adev->dev, "invalid ip discovery harvest table signature\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum( - discovery_bin + offset, - sizeof(struct harvest_table), checksum)) { - dev_err(adev->dev, "invalid harvest data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - info = &bhdr->table_list[VCN_INFO]; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (offset) { - struct vcn_info_header *vhdr = - (struct vcn_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(vhdr->table_id) != VCN_INFO_TABLE_ID) { - dev_err(adev->dev, "invalid ip discovery vcn table id\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum( - discovery_bin + offset, - le32_to_cpu(vhdr->size_bytes), checksum)) { - dev_err(adev->dev, "invalid vcn data table checksum\n"); - r = -EINVAL; - goto out; - } - } - - info = &bhdr->table_list[MALL_INFO]; - offset = le16_to_cpu(info->offset); - checksum = le16_to_cpu(info->checksum); - - if (0 && offset) { - struct mall_info_header *mhdr = - (struct mall_info_header *)(discovery_bin + offset); - - if (le32_to_cpu(mhdr->table_id) != MALL_INFO_TABLE_ID) { - dev_err(adev->dev, "invalid ip discovery mall table id\n"); - r = -EINVAL; - goto out; - } - - if (!amdgpu_discovery_verify_checksum( - discovery_bin + offset, - le32_to_cpu(mhdr->size_bytes), checksum)) { - dev_err(adev->dev, "invalid mall data table checksum\n"); - r = -EINVAL; + for (table_id = 0; table_id <= MALL_INFO; table_id++) { + r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); + if (r) goto out; - } } return 0; @@ -748,14 +800,15 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, uint32_t *umc_harvest_count) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; struct harvest_table *harvest_info; u16 offset; int i; - uint32_t umc_harvest_config = 0; + u64 umc_harvest_config = 0; - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) + return; + offset = le16_to_cpu(info->offset); if (!offset) { dev_err(adev->dev, "invalid harvest table offset\n"); @@ -808,7 +861,7 @@ static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, } } - adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & + adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & ~umc_harvest_config; } @@ -823,7 +876,11 @@ struct ip_hw_instance { u8 harvest; int num_base_addresses; +#ifdef __counted_by u32 base_addr[] __counted_by(num_base_addresses); +#else + u32 base_addr[]; +#endif }; struct ip_hw_id { @@ -880,22 +937,19 @@ static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, ch static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) { - ssize_t res, at; + ssize_t at; int ii; - for (res = at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { + for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { /* Here we satisfy the condition that, at + size <= PAGE_SIZE. */ if (at + 12 > PAGE_SIZE) break; - res = sysfs_emit_at(buf, at, "0x%08X\n", + at += sysfs_emit_at(buf, at, "0x%08X\n", ip_hw_instance->base_addr[ii]); - if (res <= 0) - break; - at += res; } - return res < 0 ? res : at; + return at; } static struct ip_hw_instance_attr ip_hw_attr[] = { @@ -910,7 +964,9 @@ static struct ip_hw_instance_attr ip_hw_attr[] = { }; static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_hw_instance); +#endif #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) @@ -942,7 +998,11 @@ static void ip_hw_instance_release(struct kobject *kobj) static const struct kobj_type ip_hw_instance_ktype = { .release = ip_hw_instance_release, .sysfs_ops = &ip_hw_instance_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_hw_instance_groups, +#else + .default_attrs = ip_hw_instance_attrs, +#endif }; /* -------------------------------------------------- */ @@ -991,7 +1051,9 @@ static struct attribute *ip_die_entry_attrs[] = { &num_ips_attr.attr, NULL, }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ +#endif #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) @@ -1024,7 +1086,11 @@ static const struct sysfs_ops ip_die_entry_sysfs_ops = { static const struct kobj_type ip_die_entry_ktype = { .release = ip_die_entry_release, .sysfs_ops = &ip_die_entry_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_die_entry_groups, +#else + .default_attrs = ip_die_entry_attrs, +#endif }; static const struct kobj_type die_kobj_ktype = { @@ -1177,13 +1243,8 @@ static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, ip_hw_instance->num_instance); ip_hw_instance->num_base_addresses = ip->num_base_address; - for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { - if (reg_base_64) - ip_hw_instance->base_addr[kk] = - lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; - else - ip_hw_instance->base_addr[kk] = ip->base_address[kk]; - } + for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) + ip_hw_instance->base_addr[kk] = ip->base_address[kk]; kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; @@ -1206,7 +1267,7 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) { struct ip_discovery_top *ip_top = adev->discovery.ip_top; uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; struct ip_discovery_header *ihdr; struct die_header *dhdr; struct kset *die_kset = &ip_top->die_kset; @@ -1214,10 +1275,12 @@ static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev) size_t ip_offset; int ii, res; - bhdr = (struct binary_header *)discovery_bin; + res = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); + if (res) + return res; ihdr = (struct ip_discovery_header *)(discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + le16_to_cpu(info->offset)); num_dies = le16_to_cpu(ihdr->num_dies); DRM_DEBUG("number of dies: %d\n", num_dies); @@ -1348,6 +1411,9 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) struct list_head *el, *tmp; struct kset *die_kset; + if (!ip_top) + return; + die_kset = &ip_top->die_kset; spin_lock(&die_kset->list_lock); list_for_each_prev_safe(el, tmp, &die_kset->list) { @@ -1361,12 +1427,58 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) kobject_put(&ip_top->kobj); } +/* devcoredump support */ +void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) +{ + struct ip_discovery_top *ip_top = adev->discovery.ip_top; + struct ip_die_entry *ip_die_entry; + struct list_head *el_die, *el_hw_id, *el_hw_inst; + struct ip_hw_id *hw_id; + struct kset *die_kset; + struct ip_hw_instance *ip_inst; + int i = 0, j; + + if (!ip_top) + return; + + die_kset = &ip_top->die_kset; + + drm_printf(p, "\nHW IP Discovery\n"); + + spin_lock(&die_kset->list_lock); + list_for_each(el_die, &die_kset->list) { + drm_printf(p, "die %d\n", i++); + ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); + + list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { + hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); + drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); + + list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { + ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); + drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); + drm_printf(p, "\tmajor %d\n", ip_inst->major); + drm_printf(p, "\tminor %d\n", ip_inst->minor); + drm_printf(p, "\trevision %d\n", ip_inst->revision); + drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); + drm_printf(p, "\tnum_base_addresses %d\n", + ip_inst->num_base_addresses); + for (j = 0; j < ip_inst->num_base_addresses; j++) + drm_printf(p, "\tbase_addr[%d] 0x%08X\n", + j, ip_inst->base_addr[j]); + } + } + } + spin_unlock(&die_kset->list_lock); +} + + /* ================================================== */ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) { uint8_t num_base_address, subrev, variant; - struct binary_header *bhdr; + struct table_info *info; struct ip_discovery_header *ihdr; struct die_header *dhdr; uint8_t *discovery_bin; @@ -1391,10 +1503,12 @@ static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) adev->sdma.sdma_mask = 0; adev->vcn.inst_mask = 0; adev->jpeg.inst_mask = 0; - bhdr = (struct binary_header *)discovery_bin; + r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); + if (r) + return r; ihdr = (struct ip_discovery_header *)(discovery_bin + - le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); + le16_to_cpu(info->offset)); num_dies = le16_to_cpu(ihdr->num_dies); DRM_DEBUG("number of dies: %d\n", num_dies); @@ -1567,14 +1681,15 @@ static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; struct ip_discovery_header *ihdr; - struct binary_header *bhdr; + struct table_info *info; int vcn_harvest_count = 0; int umc_harvest_count = 0; - uint16_t offset, ihdr_ver; + uint16_t ihdr_ver; - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset); - ihdr = (struct ip_discovery_header *)(discovery_bin + offset); + if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) + return; + ihdr = (struct ip_discovery_header *)(discovery_bin + + le16_to_cpu(info->offset)); ihdr_ver = le16_to_cpu(ihdr->version); /* * Harvest table does not fit Navi1x and legacy GPUs, @@ -1622,7 +1737,7 @@ union gc_info { static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; union gc_info *gc_info; u16 offset; @@ -1631,8 +1746,9 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[GC].offset); + if (amdgpu_discovery_get_table_info(adev, &info, GC)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return 0; @@ -1731,7 +1847,7 @@ union mall_info { static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; union mall_info *mall_info; u32 u, mall_size_per_umc, m_s_present, half_use; u64 mall_size; @@ -1742,8 +1858,9 @@ static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return 0; @@ -1788,7 +1905,7 @@ union vcn_info { static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) { uint8_t *discovery_bin = adev->discovery.bin; - struct binary_header *bhdr; + struct table_info *info; union vcn_info *vcn_info; u16 offset; int v; @@ -1808,8 +1925,9 @@ static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return 0; @@ -1846,20 +1964,32 @@ static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, uint64_t vram_size, pos, offset; struct nps_info_header *nhdr; struct binary_header bhdr; + struct binary_header_v2 bhdrv2; uint16_t checksum; vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; pos = vram_size - DISCOVERY_TMR_OFFSET; amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); - offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); - checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); + switch (bhdr.version_major) { + case 2: + amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); + offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); + checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); + break; + case 1: + offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); + checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); + break; + default: + return -EINVAL; + } amdgpu_device_vram_access(adev, (pos + offset), nps_data, sizeof(*nps_data), false); nhdr = (struct nps_info_header *)(nps_data); - if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, + if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, le32_to_cpu(nhdr->size_bytes), checksum)) { dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); @@ -1871,12 +2001,11 @@ static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, - struct amdgpu_gmc_memrange **ranges, + struct amdgpu_gmc_memrange *ranges, int *range_cnt, bool refresh) { uint8_t *discovery_bin = adev->discovery.bin; - struct amdgpu_gmc_memrange *mem_ranges; - struct binary_header *bhdr; + struct table_info *info; union nps_info *nps_info; union nps_info nps_data; u16 offset; @@ -1897,14 +2026,15 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, return -EINVAL; } - bhdr = (struct binary_header *)discovery_bin; - offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); + if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) + return -EINVAL; + offset = le16_to_cpu(info->offset); if (!offset) return -ENOENT; /* If verification fails, return as if NPS table doesn't exist */ - if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) + if (amdgpu_discovery_verify_npsinfo(adev, info)) return -ENOENT; nps_info = (union nps_info *)(discovery_bin + offset); @@ -1912,22 +2042,22 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, switch (le16_to_cpu(nps_info->v1.header.version_major)) { case 1: - mem_ranges = kvcalloc(nps_info->v1.count, - sizeof(*mem_ranges), - GFP_KERNEL); - if (!mem_ranges) - return -ENOMEM; *nps_type = nps_info->v1.nps_type; + if (*range_cnt < nps_info->v1.count) { + dev_dbg(adev->dev, + "not enough space for nps ranges: %d < %d\n", + *range_cnt, nps_info->v1.count); + return -ENOSPC; + } *range_cnt = nps_info->v1.count; for (i = 0; i < *range_cnt; i++) { - mem_ranges[i].base_address = + ranges[i].base_address = nps_info->v1.instance_info[i].base_address; - mem_ranges[i].limit_address = + ranges[i].limit_address = nps_info->v1.instance_info[i].limit_address; - mem_ranges[i].nid_mask = -1; - mem_ranges[i].flags = 0; + ranges[i].nid_mask = -1; + ranges[i].flags = 0; } - *ranges = mem_ranges; break; default: dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", @@ -1980,12 +2110,16 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); break; + case IP_VERSION(12, 1, 0): + amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); + break; default: dev_err(adev->dev, "Failed to add common ip block(GC_HWIP:0x%x)\n", @@ -2036,10 +2170,12 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): + case IP_VERSION(12, 1, 0): amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); break; default: @@ -2081,9 +2217,11 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); break; case IP_VERSION(6, 1, 0): + case IP_VERSION(6, 1, 1): amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); break; case IP_VERSION(7, 0, 0): + case IP_VERSION(7, 1, 0): amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); break; default: @@ -2137,6 +2275,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(13, 0, 11): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): case IP_VERSION(14, 0, 0): case IP_VERSION(14, 0, 1): case IP_VERSION(14, 0, 4): @@ -2150,6 +2289,12 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(14, 0, 5): amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); break; + case IP_VERSION(15, 0, 0): + amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); + break; + case IP_VERSION(15, 0, 8): + amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); + break; default: dev_err(adev->dev, "Failed to add psp ip block(MP0_HWIP:0x%x)\n", @@ -2213,6 +2358,10 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(14, 0, 5): amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); break; + case IP_VERSION(15, 0, 0): + case IP_VERSION(15, 0, 8): + amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); + break; default: dev_err(adev->dev, "Failed to add smu ip block(MP1_HWIP:0x%x)\n", @@ -2264,6 +2413,7 @@ static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 1, 0): + case IP_VERSION(4, 2, 0): /* TODO: Fix IP version. DC code expects version 4.0.1 */ if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); @@ -2342,12 +2492,16 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); break; + case IP_VERSION(12, 1, 0): + amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); + break; default: dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", amdgpu_ip_version(adev, GC_HWIP, 0)); @@ -2398,12 +2552,16 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 1, 1): case IP_VERSION(6, 1, 2): case IP_VERSION(6, 1, 3): + case IP_VERSION(6, 1, 4): amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); break; case IP_VERSION(7, 0, 0): case IP_VERSION(7, 0, 1): amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); break; + case IP_VERSION(7, 1, 0): + amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); + break; default: dev_err(adev->dev, "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", @@ -2511,10 +2669,18 @@ static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); break; + case IP_VERSION(5, 3, 0): + amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); + amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); + break; case IP_VERSION(5, 0, 1): amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); break; + case IP_VERSION(5, 0, 2): + amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); + amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); + break; default: dev_err(adev->dev, "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", @@ -2537,6 +2703,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); adev->enable_mes = true; adev->enable_mes_kiq = true; @@ -2549,6 +2716,13 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) if (amdgpu_uni_mes) adev->enable_uni_mes = true; break; + case IP_VERSION(12, 1, 0): + amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); + adev->enable_mes = true; + adev->enable_mes_kiq = true; + if (amdgpu_uni_mes) + adev->enable_uni_mes = true; + break; default: break; } @@ -2563,6 +2737,9 @@ static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) case IP_VERSION(9, 5, 0): aqua_vanjaram_init_soc_config(adev); break; + case IP_VERSION(12, 1, 0): + soc_v1_0_init_soc_config(adev); + break; default: break; } @@ -2931,8 +3108,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 3): adev->family = AMDGPU_FAMILY_GC_11_5_0; break; + case IP_VERSION(11, 5, 4): + adev->family = AMDGPU_FAMILY_GC_11_5_4; + break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): + case IP_VERSION(12, 1, 0): adev->family = AMDGPU_FAMILY_GC_12_0_0; break; default: @@ -2955,6 +3136,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): adev->flags |= AMD_IS_APU; break; default: @@ -3025,6 +3207,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; break; case IP_VERSION(6, 3, 1): + case IP_VERSION(7, 11, 4): adev->nbio.funcs = &nbif_v6_3_1_funcs; adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; break; @@ -3059,6 +3242,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(6, 0, 0): case IP_VERSION(6, 0, 1): case IP_VERSION(6, 1, 0): + case IP_VERSION(6, 1, 1): adev->hdp.funcs = &hdp_v6_0_funcs; break; case IP_VERSION(7, 0, 0): @@ -3140,6 +3324,12 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(14, 0, 2): adev->smuio.funcs = &smuio_v14_0_2_funcs; break; + case IP_VERSION(15, 0, 0): + adev->smuio.funcs = &smuio_v15_0_0_funcs; + break; + case IP_VERSION(15, 0, 8): + adev->smuio.funcs = &smuio_v15_0_8_funcs; + break; default: break; } @@ -3155,6 +3345,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) case IP_VERSION(7, 0, 1): adev->lsdma.funcs = &lsdma_v7_0_funcs; break; + case IP_VERSION(7, 1, 0): + adev->lsdma.funcs = &lsdma_v7_1_funcs; + break; default: break; } @@ -3210,8 +3403,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) return r; if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && - !amdgpu_sriov_vf(adev)) || - (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) { + !amdgpu_sriov_vf(adev) && + amdgpu_dpm == 1) || + (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && + amdgpu_dpm == 1)) { r = amdgpu_discovery_set_smu_ip_blocks(adev); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index 4ce04486cc319..0ff1a7923eedf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -30,10 +30,12 @@ #define DISCOVERY_TMR_OFFSET (64 << 10) struct ip_discovery_top; +struct drm_printer; struct amdgpu_discovery_info { struct debugfs_blob_wrapper debugfs_blob; struct ip_discovery_top *ip_top; + uint64_t offset; uint32_t size; uint8_t *bin; bool reserve_tmr; @@ -44,7 +46,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev); int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, - struct amdgpu_gmc_memrange **ranges, + struct amdgpu_gmc_memrange *ranges, int *range_cnt, bool refresh); +void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p); + #endif /* __AMDGPU_DISCOVERY__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 52bc04452812e..8d084842a2a75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -217,13 +217,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; /* schedule unpin of the old buffer */ - obj = crtc->primary->fb->obj[0]; + obj = drm_gem_fb_get_obj(crtc->primary->fb, 0); /* take a reference to the old object */ work->old_abo = gem_to_amdgpu_bo(obj); amdgpu_bo_ref(work->old_abo); - obj = fb->obj[0]; + obj = drm_gem_fb_get_obj(fb, 0); new_abo = gem_to_amdgpu_bo(obj); /* pin the new buffer */ @@ -249,7 +249,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, goto unpin; } - r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, &work->shared_count, &work->shared); if (unlikely(r != 0)) { @@ -415,15 +415,15 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) int i = 0; drm_connector_list_iter_begin(dev, &iter); - DRM_INFO("AMDGPU Display Connectors\n"); + drm_info(dev, "AMDGPU Display Connectors\n"); drm_for_each_connector_iter(connector, &iter) { amdgpu_connector = to_amdgpu_connector(connector); - DRM_INFO("Connector %d:\n", i); - DRM_INFO(" %s\n", connector->name); + drm_info(dev, "Connector %d:\n", i); + drm_info(dev, " %s\n", connector->name); if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) - DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); + drm_info(dev, " %s\n", hpd_names[amdgpu_connector->hpd.hpd]); if (amdgpu_connector->ddc_bus) { - DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + drm_info(dev, " DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", amdgpu_connector->ddc_bus->rec.mask_clk_reg, amdgpu_connector->ddc_bus->rec.mask_data_reg, amdgpu_connector->ddc_bus->rec.a_clk_reg, @@ -433,11 +433,11 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) amdgpu_connector->ddc_bus->rec.y_clk_reg, amdgpu_connector->ddc_bus->rec.y_data_reg); if (amdgpu_connector->router.ddc_valid) - DRM_INFO(" DDC Router 0x%x/0x%x\n", + drm_info(dev, " DDC Router 0x%x/0x%x\n", amdgpu_connector->router.ddc_mux_control_pin, amdgpu_connector->router.ddc_mux_state); if (amdgpu_connector->router.cd_valid) - DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", + drm_info(dev, " Clock/Data Router 0x%x/0x%x\n", amdgpu_connector->router.cd_mux_control_pin, amdgpu_connector->router.cd_mux_state); } else { @@ -447,35 +447,35 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) connector->connector_type == DRM_MODE_CONNECTOR_DVIA || connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) - DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); + drm_info(dev, " DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); } - DRM_INFO(" Encoders:\n"); + drm_info(dev, " Encoders:\n"); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); devices = amdgpu_encoder->devices & amdgpu_connector->devices; if (devices) { if (devices & ATOM_DEVICE_CRT1_SUPPORT) - DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_CRT2_SUPPORT) - DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_LCD1_SUPPORT) - DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_DFP1_SUPPORT) - DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_DFP2_SUPPORT) - DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_DFP3_SUPPORT) - DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_DFP4_SUPPORT) - DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_DFP5_SUPPORT) - DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_DFP6_SUPPORT) - DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_TV1_SUPPORT) - DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); if (devices & ATOM_DEVICE_CV_SUPPORT) - DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + drm_info(dev, " CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); } } i++; @@ -578,6 +578,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, return domain; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static const struct drm_format_info dcc_formats[] = { { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, @@ -670,7 +671,7 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier) /* returning NULL will cause the default format structs to be used. */ return NULL; } - +#endif /* * Tries to extract the renderable DCC offset from the opaque metadata attached @@ -746,6 +747,7 @@ static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) { struct amdgpu_device *adev = drm_to_adev(afb->base.dev); @@ -939,6 +941,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) afb->base.flags |= DRM_MODE_FB_MODIFIERS; return 0; } +#endif /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) @@ -961,6 +964,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) } } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, unsigned int *width, unsigned int *height) { @@ -1043,17 +1047,16 @@ static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane (uint64_t)rfb->base.pitches[plane] / block_pitch * block_size * DIV_ROUND_UP(height, block_height); - if (rfb->base.obj[0]->size < size) { + if (drm_gem_fb_get_obj(&rfb->base, 0)->size < size) { drm_dbg_kms(rfb->base.dev, "BO size 0x%zx is less than 0x%llx required for plane %d\n", - rfb->base.obj[0]->size, size, plane); + drm_gem_fb_get_obj(&rfb->base, 0)->size, size, plane); return -EINVAL; } return 0; } - static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) { const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); @@ -1061,7 +1064,11 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) int ret; unsigned int i, block_width, block_height, block_size_log2; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (rfb->base.dev->mode_config.fb_modifiers_not_supported) +#else + if (!rfb->base.dev->mode_config.allow_fb_modifiers) +#endif return 0; for (i = 0; i < format_info->num_planes; ++i) { @@ -1157,6 +1164,7 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) return 0; } +#endif static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, uint64_t *tiling_flags, bool *tmz_surface, @@ -1172,7 +1180,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&((struct amdgpu_framebuffer *)amdgpu_fb)->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { @@ -1191,17 +1199,56 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return r; } +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS + drm_helper_mode_fill_fb_struct(dev, &rfb->base, NULL, mode_cmd); +#else + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif + + ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); + if (ret) + goto err; + + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (ret) + goto err; + + return 0; +err: + drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); + rfb->base.obj[0] = NULL; + return ret; +} + static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object *obj) { int ret; rfb->base.obj[0] = obj; + +#ifdef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS drm_helper_mode_fill_fb_struct(dev, &rfb->base, info, mode_cmd); +#else + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); +#endif + + +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, mode_cmd->modifier[0])) { @@ -1212,6 +1259,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, ret = -EINVAL; goto err; } +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1245,6 +1293,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, * This needs to happen before modifier conversion as that might change * the number of planes. */ +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 1; i < rfb->base.format->num_planes; ++i) { if (mode_cmd->handles[i] != mode_cmd->handles[0]) { drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", @@ -1253,13 +1302,19 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } } +#endif ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface, &rfb->gfx12_dcc); if (ret) return ret; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { +#else + if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) { +#endif drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); ret = check_tiling_flags_gfx6(rfb); @@ -1267,7 +1322,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (!dev->mode_config.fb_modifiers_not_supported && +#else + if (dev->mode_config.allow_fb_modifiers && +#endif !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ret = convert_tiling_flags_to_modifier_gfx12(rfb); @@ -1289,6 +1348,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, drm_gem_object_get(rfb->base.obj[0]); rfb->base.obj[i] = rfb->base.obj[0]; } +#endif return 0; } @@ -1296,7 +1356,9 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd) { struct amdgpu_framebuffer *amdgpu_fb; @@ -1319,25 +1381,38 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); if (drm_gem_is_imported(obj) && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-EINVAL); } amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); if (amdgpu_fb == NULL) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-ENOMEM); } ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO info, mode_cmd, obj); +#else + mode_cmd, obj); +#endif if (ret) { kfree(amdgpu_fb); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(ret); } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif + return &amdgpu_fb->base; } @@ -1534,7 +1609,11 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector && connector->display_info.is_hdmi && +#else + drm_detect_hdmi_monitor(drm_edid_raw(to_amdgpu_connector(connector)->edid)) && +#endif amdgpu_display_is_hdtv_mode(mode)))) { if (amdgpu_encoder->underscan_hborder != 0) amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; @@ -1732,27 +1811,12 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, stime, etime, mode); } -static bool -amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) -{ - struct drm_device *dev = adev_to_drm(adev); - struct drm_fb_helper *fb_helper = dev->fb_helper; - - if (!fb_helper || !fb_helper->buffer) - return false; - - if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj) - return false; - - return true; -} - int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); @@ -1775,7 +1839,6 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_framebuffer *fb = crtc->primary->fb; - struct amdgpu_bo *robj; if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); @@ -1790,8 +1853,9 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) if (!fb || !fb->obj[0]) continue; - robj = gem_to_amdgpu_bo(fb->obj[0]); - if (!amdgpu_display_robj_is_fb(adev, robj)) { + if (!drm_fb_helper_gem_is_fb(dev->fb_helper, fb->obj[0])) { + struct amdgpu_bo *robj = gem_to_amdgpu_bo(fb->obj[0]); + r = amdgpu_bo_reserve(robj, true); if (r == 0) { amdgpu_bo_unpin(robj); @@ -1847,6 +1911,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) return 0; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER /* panic_bo is set in amdgpu_dm_plane_get_scanout_buffer() and only used in amdgpu_dm_set_pixel() * they are called from the panic handler, and protected by the drm_panic spinlock. */ @@ -1931,3 +1996,4 @@ int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, return 0; } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h index 49a29bf47a379..dd4c421510685 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.h @@ -44,7 +44,9 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, struct drm_framebuffer * amdgpu_display_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, +#ifdef HAVE_DRM_FB_CREATE_FORMAT_INFO const struct drm_format_info *info, +#endif const struct drm_mode_fb_cmd2 *mode_cmd); const struct drm_format_info * amdgpu_lookup_format_info(u32 format, uint64_t modifier); @@ -52,8 +54,10 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier); int amdgpu_display_suspend_helper(struct amdgpu_device *adev); int amdgpu_display_resume_helper(struct amdgpu_device *adev); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER int amdgpu_display_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb); +#endif #define ABM_SYSFS_CONTROL -1 #define ABM_LEVEL_OFF 0 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index c1461317eb298..79828c6f694b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -37,12 +37,190 @@ #include "amdgpu_dma_buf.h" #include "amdgpu_xgmi.h" #include "amdgpu_vm.h" +#include "amdgpu_ttm.h" #include #include #include #include #include +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation + * @obj: GEM BO + * @vma: Virtual memory area + * + * Sets up a userspace mapping of the BO's memory in the given + * virtual memory area. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + unsigned asize = amdgpu_bo_size(bo); + int ret; + + if (!vma->vm_file) + return -ENODEV; + + if (adev == NULL) + return -ENODEV; + + /* Check for valid size. */ + if (asize < vma->vm_end - vma->vm_start) + return -EINVAL; + + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || + (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { + return -EPERM; + } + vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; + + /* prime mmap does not need to check access, so allow here */ + ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); + if (ret) + return ret; + + ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); + drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); + + return ret; +} +#endif + +#if defined(HAVE_DMA_BUF_OPS_LEGACY) +static int +__dma_resv_make_exclusive(struct dma_resv *obj) +{ + struct dma_fence **fences; + unsigned int count; + int r; + + if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ + return 0; + + r = dma_resv_get_fences(obj, DMA_RESV_USAGE_READ, &count, &fences); + if (r) + return r; + + if (count == 0) { + /* Now that was unexpected. */ + } else if (count == 1) { + dma_resv_add_fence(obj, fences[0], DMA_RESV_USAGE_WRITE); + dma_fence_put(fences[0]); + kfree(fences); + } else { + struct dma_fence_array *array; + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), 0, + false); + if (!array) + goto err_fences_put; + + dma_resv_add_fence(obj, &array->base, DMA_RESV_USAGE_WRITE); + dma_fence_put(&array->base); + } + + return 0; + +err_fences_put: + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; +} + +/** + * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * Makes sure that the shared DMA buffer can be accessed by the target device. + * For now, simply pins it to the GTT domain, where it should be accessible by + * all DMA devices. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + long r; + + r = drm_gem_map_attach(dma_buf, attach); + + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + goto error_detach; + + + if (attach->dev->driver != adev->dev->driver) { + /* + * We only create shared fences for internal use, but importers + * of the dmabuf rely on exclusive fences for implicitly + * tracking write hazards. As any of the current fences may + * correspond to a write, we need to convert all existing + * fences on the reservation object into a single exclusive + * fence. + */ + r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); + if (r) + goto error_unreserve; + } + + /* pin buffer into GTT */ + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + goto error_unreserve; + + +error_unreserve: + amdgpu_bo_unreserve(bo); + +error_detach: + if (r) + drm_gem_map_detach(dma_buf, attach); + return r; +} + +/** + * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * This is called when a shared DMA buffer no longer needs to be accessible by + * another device. For now, simply unpins the buffer from GTT. + */ +static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + goto error; + + amdgpu_bo_unpin(bo); + amdgpu_bo_unreserve(bo); + +error: + drm_gem_map_detach(dma_buf, attach); +} +#else static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops; /** @@ -95,9 +273,11 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) attach->peer2peer = false; +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) && pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; +#endif r = dma_resv_lock(bo->tbo.base.resv, NULL); if (r) @@ -110,6 +290,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, return 0; } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation * @@ -164,6 +345,7 @@ static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach) amdgpu_bo_unpin(bo); } +#endif /** * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation @@ -188,21 +370,29 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct sg_table *sgt; long r; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (!bo->tbo.pin_count) { /* move buffer into GTT or VRAM */ struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; domains |= AMDGPU_GEM_DOMAIN_VRAM; } +#endif amdgpu_bo_placement_from_domain(bo, domains); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) return ERR_PTR(r); } +#else + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + return ERR_PTR(r); +#endif switch (bo->tbo.resource->mem_type) { case TTM_PL_TT: @@ -218,17 +408,20 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, break; case TTM_PL_VRAM: - /* XGMI-accessible memory should never be DMA-mapped */ - if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible( - dma_buf_attach_adev(attach), bo))) - return ERR_PTR(-EINVAL); - r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0, bo->tbo.base.size, attach->dev, dir, &sgt); if (r) return ERR_PTR(r); break; + + case AMDGPU_PL_MMIO_REMAP: + r = amdgpu_ttm_mmio_remap_alloc_sgt(adev, bo->tbo.resource, + attach->dev, dir, &sgt); + if (r) + return ERR_PTR(r); + break; + default: return ERR_PTR(-EINVAL); } @@ -254,6 +447,15 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, struct sg_table *sgt, enum dma_data_direction dir) { + struct drm_gem_object *obj = attach->dmabuf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + if (bo->tbo.resource && + bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP) { + amdgpu_ttm_mmio_remap_free_sgt(attach->dev, dir, sgt); + return; + } + if (sg_page(sgt->sgl)) { dma_unmap_sgtable(attach->dev, sgt, dir, 0); sg_free_table(sgt); @@ -261,7 +463,12 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, } else { amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt); } + +#ifndef HAVE_STRUCT_DMA_BUF_OPS_PIN + amdgpu_bo_unpin(bo); +#endif } +#endif /** * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation @@ -304,6 +511,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, return ret; } +#ifdef HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) { struct drm_gem_object *obj = dma_buf->priv; @@ -333,18 +541,36 @@ static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map drm_gem_dmabuf_vunmap(dma_buf, map); amdgpu_bo_unpin(bo); } +#endif const struct dma_buf_ops amdgpu_dmabuf_ops = { +#if defined(HAVE_DMA_BUF_OPS_LEGACY) + .attach = amdgpu_dma_buf_map_attach, + .detach = amdgpu_dma_buf_map_detach, + .map_dma_buf = drm_gem_map_dma_buf, + .unmap_dma_buf = drm_gem_unmap_dma_buf, +#else +#ifdef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING + .dynamic_mapping = true, +#endif .attach = amdgpu_dma_buf_attach, +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, .unpin = amdgpu_dma_buf_unpin, +#endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, +#endif .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, +#ifdef HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG .vmap = amdgpu_dma_buf_vmap, .vunmap = amdgpu_dma_buf_vunmap, +#else + .vmap = drm_gem_dmabuf_vmap, + .vunmap = drm_gem_dmabuf_vunmap, +#endif }; /** @@ -357,7 +583,12 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { * Returns: * Shared DMA buffer representing the GEM BO from the given device. */ +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); @@ -379,13 +610,136 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, if (ret) return ERR_PTR(ret); +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI buf = drm_gem_prime_export(gobj, flags); - if (!IS_ERR(buf)) +#else + buf = drm_gem_prime_export(dev, gobj, flags); +#endif + + if (!IS_ERR(buf)) { +#ifdef AMDKCL_DMA_BUF_SHARE_ADDR_SPACE + buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; +#endif buf->ops = &amdgpu_dmabuf_ops; + } return buf; } +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +/** + * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation + * @obj: GEM BO + * + * Returns: + * The BO's reservation object. + */ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + return amdkcl_ttm_resvp(&bo->tbo); +} +#endif + +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table + * implementation + * @obj: GEM buffer object (BO) + * + * Returns: + * A scatter/gather table for the pinned pages of the BO's memory. + */ +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int npages = bo->tbo.ttm->num_pages; + + return drm_prime_pages_to_sg(obj->dev, bo->tbo.ttm->pages, npages); +} + +/** + * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table + * implementation + * @dev: DRM device + * @attach: DMA-buf attachment + * @sg: Scatter/gather table + * + * Imports shared DMA buffer memory exported by another device. + * + * Returns: + * A new GEM BO of the given DRM device, representing the memory + * described by the given DMA-buf attachment and scatter/gather table. + */ +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg) +{ + struct dma_resv *resv = attach->dmabuf->resv; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_bo *bo; + struct amdgpu_bo_param bp; + int ret; + + memset(&bp, 0, sizeof(bp)); + bp.size = attach->dmabuf->size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_CPU; + bp.flags = 0; + bp.type = ttm_bo_type_sg; + bp.resv = resv; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); + dma_resv_lock(resv, NULL); + ret = amdgpu_bo_create(adev, &bp, &bo); + if (ret) + goto error; + + bo->tbo.sg = sg; + bo->tbo.ttm->sg = sg; + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + dma_resv_unlock(resv); + return &bo->tbo.base; + +error: + dma_resv_unlock(resv); + return ERR_PTR(ret); +} + +/** + * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation + * @dev: DRM device + * @dma_buf: Shared DMA buffer + * + * The main work is done by the &drm_gem_prime_import helper, which in turn + * uses &amdgpu_gem_prime_import_sg_table. + * + * Returns: + * GEM BO representing the shared DMA buffer for the given device. + */ +struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, + struct dma_buf *dma_buf) +{ + struct drm_gem_object *obj; + + if (dma_buf->ops == &amdgpu_dmabuf_ops) { + obj = dma_buf->priv; + if (obj->dev == dev) { + /* + * Importing dmabuf exported from out own gem increases + * refcount on gem itself instead of f_count of dmabuf. + */ + drm_gem_object_get(obj); + return obj; + } + } + + return drm_gem_prime_import(dev, dma_buf); +} +#else /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -437,6 +791,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf) return ERR_PTR(ret); } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_move_notify - &attach.move_notify implementation * @@ -472,7 +827,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); if (ticket) { /* When we get an error here it means that somebody @@ -496,8 +851,15 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) r = dma_resv_reserve_fences(resv, 2); if (!r) r = amdgpu_vm_clear_freed(adev, vm, NULL); + + /* Don't pass 'ticket' to amdgpu_vm_handle_moved: we want the clear=true + * path to be used otherwise we might update the PT of another process + * while it's using the BO. + * With clear=true, amdgpu_vm_bo_update will sync to command submission + * from the same VM. + */ if (!r) - r = amdgpu_vm_handle_moved(adev, vm, ticket); + r = amdgpu_vm_handle_moved(adev, vm, NULL); if (r && r != -EBUSY) DRM_ERROR("Failed to invalidate VM page tables (%d))\n", @@ -508,10 +870,12 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, +#endif .move_notify = amdgpu_dma_buf_move_notify }; - +#endif /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -544,8 +908,12 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, if (IS_ERR(obj)) return obj; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN attach = dma_buf_dynamic_attach(dma_buf, dev->dev, &amdgpu_dma_buf_attach_ops, obj); +#else + attach = dma_buf_dynamic_attach(dma_buf, dev->dev, true); +#endif if (IS_ERR(attach)) { drm_gem_object_put(obj); return ERR_CAST(attach); @@ -555,6 +923,7 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, obj->import_attach = attach; return obj; } +#endif /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index 3e93b9b407a97..9db5f1d2a29c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -25,12 +25,35 @@ #include +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg); +#endif + +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags); struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); +#endif + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); +#endif + extern const struct dma_buf_ops amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h index 2675689ef70f7..ebd14c292978d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h @@ -348,6 +348,36 @@ enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF }; +enum AMDGPU_SOC_V1_0_DOORBELL_ASSIGNMENT { + /* KIQ/HIQ/DIQ */ + AMDGPU_SOC_V1_0_DOORBELL_KIQ_START = 0x000, + AMDGPU_SOC_V1_0_DOORBELL_HIQ = 0x001, + AMDGPU_SOC_V1_0_DOORBELL_DIQ = 0x002, + /* Compute: 0x03 ~ 0x20 */ + AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START = 0x003, + AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_END = 0x00A, + AMDGPU_SOC_V1_0_DOORBELL_MES_RING0 = 0x00B, + AMDGPU_SOC_V1_0_DOORBELL_MES_RING1 = 0x00C, + AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START = 0x00D, + AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END = 0x01F, + AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE = 0x020, + + /* SDMA: 0x100 ~ 0x19F */ + AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START = 0x100, + AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_END = 0x19F, + /* IH: 0x1A0 ~ 0x1AF */ + AMDGPU_SOC_V1_0_DOORBELL_IH = 0x1A0, + /* VCN: 0x1B0 ~ 0x1EF */ + AMDGPU_SOC_V1_0_DOORBELL_VCN_START = 0x1B0, + AMDGPU_SOC_V1_0_DOORBELL_VCN_END = 0x1EF, + + AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP = AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START, + AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP = AMDGPU_SOC_V1_0_DOORBELL_VCN_END, + + AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT = 0x1EF, + AMDGPU_SOC_V1_0_DOORBELL_INVALID = 0xFFFF +}; + u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c index 3040437d99c23..bc78585673215 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c @@ -129,7 +129,7 @@ uint32_t amdgpu_doorbell_index_on_bar(struct amdgpu_device *adev, { int db_bo_offset; - db_bo_offset = amdgpu_bo_gpu_offset_no_check(db_bo); + db_bo_offset = amdgpu_bo_gpu_offset(db_bo); /* doorbell index is 32 bit but doorbell's size can be 32 bit * or 64 bit, so *db_size(in byte)/4 for alignment. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 39387da8586b4..8b801b5ea18ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -176,6 +176,8 @@ int amdgpu_exp_hw_support; int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; +int amdgpu_no_evict; +int amdgpu_direct_gma_size; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -223,9 +225,7 @@ uint amdgpu_dc_visual_confirm; int amdgpu_async_gfx_ring = 1; int amdgpu_mcbp = -1; int amdgpu_discovery = -1; -int amdgpu_mes; int amdgpu_mes_log_enable = 0; -int amdgpu_mes_kiq; int amdgpu_uni_mes = 1; int amdgpu_noretry = -1; int amdgpu_force_asic_type = -1; @@ -500,6 +500,12 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); + /** * DOC: forcelongtraining (uint) * Force long memory training in resume. @@ -690,15 +696,6 @@ MODULE_PARM_DESC(discovery, "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); module_param_named(discovery, amdgpu_discovery, int, 0444); -/** - * DOC: mes (int) - * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. - * (0 = disabled (default), 1 = enabled) - */ -MODULE_PARM_DESC(mes, - "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); -module_param_named(mes, amdgpu_mes, int, 0444); - /** * DOC: mes_log_enable (int) * Enable Micro Engine Scheduler log. This is used to enable/disable MES internal log. @@ -708,15 +705,6 @@ MODULE_PARM_DESC(mes_log_enable, "Enable Micro Engine Scheduler log (0 = disabled (default), 1 = enabled)"); module_param_named(mes_log_enable, amdgpu_mes_log_enable, int, 0444); -/** - * DOC: mes_kiq (int) - * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. - * (0 = disabled (default), 1 = enabled) - */ -MODULE_PARM_DESC(mes_kiq, - "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); -module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); - /** * DOC: uni_mes (int) * Enable Unified Micro Engine Scheduler. This is a new engine pipe for unified scheduler. @@ -854,24 +842,38 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa int amdgpu_no_queue_eviction_on_vm_fault; MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); module_param_named_unsafe(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); + +/** + * DOC: priv_cp_queues (int) + * Enable privileged mode for CP queues. Default value: 0 (off) + */ +int priv_cp_queues; +module_param(priv_cp_queues, int, 0644); +MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); + +/** + * DOC: keep_idle_process_evicted (bool) + * Keep an evicted process evicted if it is idle. Default value: false (off) + */ +bool keep_idle_process_evicted; +module_param(keep_idle_process_evicted, bool, 0444); +MODULE_PARM_DESC(keep_idle_process_evicted, "Restore evicted process only if queues are active (N = off(default), Y = on)"); #endif /** * DOC: mtype_local (int) */ -int amdgpu_mtype_local; -MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)"); +int amdgpu_mtype_local = -1; +MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (default: ASIC dependent, 0 = MTYPE_RW, 1 = MTYPE_NC, 2 = MTYPE_CC)"); module_param_named_unsafe(mtype_local, amdgpu_mtype_local, int, 0444); /** * DOC: pcie_p2p (bool) * Enable PCIe P2P (requires large-BAR). Default value: true (on) */ -#ifdef CONFIG_HSA_AMD_P2P bool pcie_p2p = true; module_param(pcie_p2p, bool, 0444); MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); -#endif /** * DOC: dcfeaturemask (uint) @@ -2210,6 +2212,10 @@ static const struct pci_device_id pciidlist[] = { .class_mask = 0xffffff, .driver_data = CHIP_IP_DISCOVERY }, +#ifdef HAVE_DRM_AMDGPU_PCIID_H +#include +#endif + {0, 0, 0} }; @@ -2223,7 +2229,7 @@ static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { {0x67FF, 0xF7, CHIP_POLARIS10}, }; -static const struct drm_driver amdgpu_kms_driver; +static struct drm_driver amdgpu_kms_driver; static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) { @@ -2405,12 +2411,17 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, return -ENODEV; } + if (flags == 0) { + DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); + return -ENODEV; + } + if (amdgpu_virtual_display || amdgpu_device_asic_has_dc_support(pdev, flags & AMD_ASIC_MASK)) supports_atomic = true; if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { - DRM_INFO("This hardware requires experimental hardware support.\n" + dev_info(&pdev->dev, "This hardware requires experimental hardware support.\n" "See modparam exp_hw_support\n"); return -ENODEV; } @@ -2439,13 +2450,25 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); + /* Check and increase the vma range */ + kcl_drm_vma_offset_manager_adjust(ddev->vma_offset_manager); + if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; + kcl_pci_create_measure_file(pdev); + kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) +#ifndef AMDKCL_DEVM_DRM_DEV_ALLOC return ret; +#else + goto err_free; +#endif +#ifdef HAVE_DRM_DEVICE_PDEV + ddev->pdev = pdev; +#endif pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); @@ -2457,7 +2480,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, retry_init: ret = drm_dev_register(ddev, flags); if (ret == -EAGAIN && ++retry <= 3) { - DRM_INFO("retry init %d\n", retry); + drm_info(adev_to_drm(adev), "retry init %d\n", retry); /* Don't request EX mode too frequently which is attacking */ msleep(5000); goto retry_init; @@ -2479,6 +2502,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, */ if (adev->mode_info.mode_config_initialized && !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { +#ifdef HAVE_DRM_CLIENT_SETUP const struct drm_format_info *format; /* select 8 bpp console on low vram cards */ @@ -2486,8 +2510,13 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, format = drm_format_info(DRM_FORMAT_C8); else format = NULL; - drm_client_setup(adev_to_drm(adev), format); +#else + if (adev->gmc.real_vram_size <= (32*1024*1024)) + drm_fbdev_ttm_setup(adev_to_drm(adev), 8); + else + drm_fbdev_ttm_setup(adev_to_drm(adev), 32); +#endif } ret = amdgpu_debugfs_init(adev); @@ -2541,6 +2570,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, err_pci: pci_disable_device(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +err_free: + amdkcl_drm_dev_release(ddev); +#endif return ret; } @@ -2554,7 +2587,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) amdgpu_xcp_dev_unplug(adev); amdgpu_gmc_prepare_nps_mode_change(adev); drm_dev_unplug(dev); - if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); @@ -2567,9 +2599,23 @@ amdgpu_pci_remove(struct pci_dev *pdev) * Clear the Bus Master Enable bit and then wait on the PCIe Device * StatusTransactions Pending bit. */ + kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC + amdkcl_drm_dev_release(dev); +#endif +} + +#ifndef HAVE_DRM_DRM_MANAGED_H +static void amdgpu_driver_release(struct drm_device *ddev) +{ + struct amdgpu_device *adev = drm_to_adev(ddev); + + drm_dev_fini(ddev); + kfree(adev); } +#endif static void amdgpu_pci_shutdown(struct pci_dev *pdev) @@ -2636,6 +2682,7 @@ static int amdgpu_pmops_suspend(struct device *dev) else if (amdgpu_acpi_is_s3_active(adev)) adev->in_s3 = true; if (!adev->in_s0ix && !adev->in_s3) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE #if IS_ENABLED(CONFIG_SUSPEND) /* don't allow going deep first time followed by s2idle the next time */ if (adev->last_suspend_state != PM_SUSPEND_ON && @@ -2644,13 +2691,16 @@ static int amdgpu_pmops_suspend(struct device *dev) pm_suspend_target_state); return -EINVAL; } +#endif #endif return 0; } +#ifdef HAVE_PM_SUSPEND_TARGET_STATE #if IS_ENABLED(CONFIG_SUSPEND) /* cache the state last used for suspend */ adev->last_suspend_state = pm_suspend_target_state; +#endif #endif return amdgpu_device_suspend(drm_dev, true); @@ -2712,11 +2762,13 @@ static int amdgpu_pmops_thaw(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); +#if defined(HAVE_PM_HIBERNATION_MODE_IS_SUSPEND) || defined(HAVE_PM_HIBERNATE_IS_RECOVERING) /* do not resume device if it's normal hibernation */ if (console_suspend_enabled && !pm_hibernate_is_recovering() && !pm_hibernation_mode_is_suspend()) return 0; +#endif return amdgpu_device_resume(drm_dev, true); } @@ -2972,9 +3024,11 @@ static int amdgpu_drm_release(struct inode *inode, struct file *filp) int idx; if (fpriv && drm_dev_enter(dev, &idx)) { - fpriv->evf_mgr.fd_closing = true; - amdgpu_eviction_fence_destroy(&fpriv->evf_mgr); + amdgpu_evf_mgr_shutdown(&fpriv->evf_mgr); + amdgpu_userq_mgr_cancel_resume(&fpriv->userq_mgr); + amdgpu_evf_mgr_flush_suspend(&fpriv->evf_mgr); amdgpu_userq_mgr_fini(&fpriv->userq_mgr); + amdgpu_evf_mgr_fini(&fpriv->evf_mgr); drm_dev_exit(idx); } @@ -3033,7 +3087,7 @@ static const struct file_operations amdgpu_driver_kms_fops = { .flush = amdgpu_flush, .release = amdgpu_drm_release, .unlocked_ioctl = amdgpu_drm_ioctl, - .mmap = drm_gem_mmap, + .mmap = amdkcl_drm_gem_mmap, .poll = drm_poll, .read = drm_read, #ifdef CONFIG_COMPAT @@ -3042,7 +3096,9 @@ static const struct file_operations amdgpu_driver_kms_fops = { #ifdef CONFIG_PROC_FS .show_fdinfo = drm_show_fdinfo, #endif +#ifdef HAVE_FILE_OPERATION_FOP_FLAGS .fop_flags = FOP_UNSIGNED_OFFSET, +#endif }; int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) @@ -3082,31 +3138,87 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_SIGNAL, amdgpu_userq_signal_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_USERQ_WAIT, amdgpu_userq_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_LIST_HANDLES, amdgpu_gem_list_handles_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) }; -static const struct drm_driver amdgpu_kms_driver = { +static struct drm_driver amdgpu_kms_driver = { .driver_features = - DRIVER_ATOMIC | - DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_ATOMIC + | DRIVER_HAVE_IRQ +#ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED + | DRIVER_IRQ_SHARED +#endif /* HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ +#ifdef HAVE_DRM_DRV_DRIVER_PRIME + | DRIVER_PRIME +#endif /* HAVE_DRM_DRV_DRIVER_PRIME */ + | DRIVER_GEM + | DRIVER_RENDER | DRIVER_MODESET + | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, + .enable_vblank = kcl_amdgpu_enable_vblank_kms, + .disable_vblank = kcl_amdgpu_disable_vblank_kms, + .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, + .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, +#endif +#ifdef CONFIG_DRM_LEGACY + .irq_handler = amdgpu_irq_handler, +#endif .ioctls = amdgpu_ioctls_kms, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_free_object_unlocked = amdgpu_gem_object_free, + .gem_open_object = amdgpu_gem_object_open, + .gem_close_object = amdgpu_gem_object_close, +#endif .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, +#ifdef DRM_FBDEV_TTM_DRIVER_OPS DRM_FBDEV_TTM_DRIVER_OPS, +#endif .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_DRIVER_SHOW_FDINFO #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif +#endif + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_export = amdgpu_gem_prime_export, +#endif .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ + .gem_prime_res_obj = amdgpu_gem_prime_res_obj, +#endif +#if defined(HAVE_DMA_BUF_OPS_LEGACY) + .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, + .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, +#endif + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_vmap = amdgpu_gem_prime_vmap, + .gem_prime_vunmap = amdgpu_gem_prime_vunmap, +#endif + +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP + .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, +#ifdef HAVE_DRM_DRIVER_DATE + .date = DRIVER_DATE, +#endif .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, @@ -3114,22 +3226,35 @@ static const struct drm_driver amdgpu_kms_driver = { const struct drm_driver amdgpu_partition_driver = { .driver_features = - DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .ioctls = amdgpu_ioctls_kms, .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, +#ifdef DRM_FBDEV_TTM_DRIVER_OPS DRM_FBDEV_TTM_DRIVER_OPS, +#endif .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP + .gem_prime_mmap = drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, +#ifdef HAVE_DRM_DRIVER_DATE + .date = DRIVER_DATE, +#endif .major = KMS_DRIVER_MAJOR, .minor = KMS_DRIVER_MINOR, .patchlevel = KMS_DRIVER_PATCHLEVEL, @@ -3142,12 +3267,14 @@ static struct pci_error_handlers amdgpu_pci_err_handler = { .resume = amdgpu_pci_resume, }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static const struct attribute_group *amdgpu_sysfs_groups[] = { &amdgpu_vram_mgr_attr_group, &amdgpu_gtt_mgr_attr_group, &amdgpu_flash_attr_group, NULL, }; +#endif static struct pci_driver amdgpu_kms_pci_driver = { .name = DRIVER_NAME, @@ -3157,7 +3284,9 @@ static struct pci_driver amdgpu_kms_pci_driver = { .shutdown = amdgpu_pci_shutdown, .driver.pm = pm_ptr(&amdgpu_pm_ops), .err_handler = &amdgpu_pci_err_handler, +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS .dev_groups = amdgpu_sysfs_groups, +#endif }; static int __init amdgpu_init(void) @@ -3172,7 +3301,9 @@ static int __init amdgpu_init(void) if (r) goto error_fence; - DRM_INFO("amdgpu kernel modesetting enabled.\n"); + DRM_INFO("amdgpu version: %s\n", AMDGPU_VERSION); + DRM_INFO("OS DRM version: %d.%d.%d\n", DRM_VER, DRM_PATCH, DRM_SUB); + amdgpu_register_atpx_handler(); amdgpu_acpi_detect(); @@ -3203,7 +3334,9 @@ static void __exit amdgpu_exit(void) amdgpu_acpi_release(); amdgpu_sync_fini(); amdgpu_userq_fence_slab_fini(); +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE mmu_notifier_synchronize(); +#endif amdgpu_xcp_drv_release(); } @@ -3213,3 +3346,4 @@ module_exit(amdgpu_exit); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); +MODULE_VERSION(AMDGPU_VERSION); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h index 2d86cc6f7f4dd..664f98371451f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h @@ -40,6 +40,9 @@ #define DRIVER_NAME "amdgpu" #define DRIVER_DESC "AMD GPU" +#ifdef HAVE_DRM_DRIVER_DATE +#define DRIVER_DATE "20150101" +#endif extern const struct drm_driver amdgpu_partition_driver; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 3aaeed2d35620..173adcbb5eee0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -222,7 +222,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif if (pixel_clock > 340000) return true; else @@ -244,7 +248,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, return false; else { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid))) { +#endif if (pixel_clock > 340000) return true; else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c index 23d7d0b0d6252..790f21903386e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c @@ -25,9 +25,6 @@ #include #include "amdgpu.h" -#define work_to_evf_mgr(w, name) container_of(w, struct amdgpu_eviction_fence_mgr, name) -#define evf_mgr_to_fpriv(e) container_of(e, struct amdgpu_fpriv, evf_mgr) - static const char * amdgpu_eviction_fence_get_driver_name(struct dma_fence *fence) { @@ -43,127 +40,93 @@ amdgpu_eviction_fence_get_timeline_name(struct dma_fence *f) return ef->timeline_name; } -int -amdgpu_eviction_fence_replace_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct drm_exec *exec) +static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f) { - struct amdgpu_eviction_fence *old_ef, *new_ef; - struct drm_gem_object *obj; - unsigned long index; - int ret; - - if (evf_mgr->ev_fence && - !dma_fence_is_signaled(&evf_mgr->ev_fence->base)) - return 0; - /* - * Steps to replace eviction fence: - * * lock all objects in exec (caller) - * * create a new eviction fence - * * update new eviction fence in evf_mgr - * * attach the new eviction fence to BOs - * * release the old fence - * * unlock the objects (caller) - */ - new_ef = amdgpu_eviction_fence_create(evf_mgr); - if (!new_ef) { - DRM_ERROR("Failed to create new eviction fence\n"); - return -ENOMEM; - } - - /* Update the eviction fence now */ - spin_lock(&evf_mgr->ev_fence_lock); - old_ef = evf_mgr->ev_fence; - evf_mgr->ev_fence = new_ef; - spin_unlock(&evf_mgr->ev_fence_lock); + struct amdgpu_eviction_fence *ev_fence = to_ev_fence(f); - /* Attach the new fence */ - drm_exec_for_each_locked_object(exec, index, obj) { - struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - - if (!bo) - continue; - ret = amdgpu_eviction_fence_attach(evf_mgr, bo); - if (ret) { - DRM_ERROR("Failed to attch new eviction fence\n"); - goto free_err; - } - } - - /* Free old fence */ - if (old_ef) - dma_fence_put(&old_ef->base); - return 0; - -free_err: - kfree(new_ef); - return ret; + schedule_work(&ev_fence->evf_mgr->suspend_work); + return true; } +static const struct dma_fence_ops amdgpu_eviction_fence_ops = { + .get_driver_name = amdgpu_eviction_fence_get_driver_name, + .get_timeline_name = amdgpu_eviction_fence_get_timeline_name, + .enable_signaling = amdgpu_eviction_fence_enable_signaling, +}; + static void amdgpu_eviction_fence_suspend_worker(struct work_struct *work) { - struct amdgpu_eviction_fence_mgr *evf_mgr = work_to_evf_mgr(work, suspend_work.work); - struct amdgpu_fpriv *fpriv = evf_mgr_to_fpriv(evf_mgr); + struct amdgpu_eviction_fence_mgr *evf_mgr = + container_of(work, struct amdgpu_eviction_fence_mgr, + suspend_work); + struct amdgpu_fpriv *fpriv = + container_of(evf_mgr, struct amdgpu_fpriv, evf_mgr); struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; - struct amdgpu_eviction_fence *ev_fence; + struct dma_fence *ev_fence; + bool cookie; mutex_lock(&uq_mgr->userq_mutex); - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - if (ev_fence) - dma_fence_get(&ev_fence->base); - else - goto unlock; - spin_unlock(&evf_mgr->ev_fence_lock); - amdgpu_userq_evict(uq_mgr, ev_fence); + /* + * This is intentionally after taking the userq_mutex since we do + * allocate memory while holding this lock, but only after ensuring that + * the eviction fence is signaled. + */ + cookie = dma_fence_begin_signalling(); - mutex_unlock(&uq_mgr->userq_mutex); - dma_fence_put(&ev_fence->base); - return; + ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + amdgpu_userq_evict(uq_mgr); + + /* + * Signaling the eviction fence must be done while holding the + * userq_mutex. Otherwise we won't resume the queues before issuing the + * next fence. + */ + dma_fence_signal(ev_fence); + dma_fence_end_signalling(cookie); + dma_fence_put(ev_fence); + + if (!evf_mgr->shutdown) + schedule_delayed_work(&uq_mgr->resume_work, 0); -unlock: - spin_unlock(&evf_mgr->ev_fence_lock); mutex_unlock(&uq_mgr->userq_mutex); } -static bool amdgpu_eviction_fence_enable_signaling(struct dma_fence *f) +int amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo) { - struct amdgpu_eviction_fence_mgr *evf_mgr; - struct amdgpu_eviction_fence *ev_fence; - - if (!f) - return true; - - ev_fence = to_ev_fence(f); - evf_mgr = ev_fence->evf_mgr; + struct dma_fence *ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + struct ttm_operation_ctx ctx = { false, false }; + struct dma_resv *resv = bo->tbo.base.resv; + int ret; - schedule_delayed_work(&evf_mgr->suspend_work, 0); - return true; -} + if (!dma_fence_is_signaled(ev_fence)) { -static const struct dma_fence_ops amdgpu_eviction_fence_ops = { - .get_driver_name = amdgpu_eviction_fence_get_driver_name, - .get_timeline_name = amdgpu_eviction_fence_get_timeline_name, - .enable_signaling = amdgpu_eviction_fence_enable_signaling, -}; + amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (!ret) + dma_resv_add_fence(resv, ev_fence, + DMA_RESV_USAGE_BOOKKEEP); + } else { + ret = 0; + } -void amdgpu_eviction_fence_signal(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_eviction_fence *ev_fence) -{ - spin_lock(&evf_mgr->ev_fence_lock); - dma_fence_signal(&ev_fence->base); - spin_unlock(&evf_mgr->ev_fence_lock); + dma_fence_put(ev_fence); + return ret; } -struct amdgpu_eviction_fence * -amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr) +int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct drm_exec *exec) { struct amdgpu_eviction_fence *ev_fence; + struct drm_gem_object *obj; + unsigned long index; + /* Create and initialize a new eviction fence */ ev_fence = kzalloc(sizeof(*ev_fence), GFP_KERNEL); if (!ev_fence) - return NULL; + return -ENOMEM; ev_fence->evf_mgr = evf_mgr; get_task_comm(ev_fence->timeline_name, current); @@ -171,71 +134,55 @@ amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr) dma_fence_init64(&ev_fence->base, &amdgpu_eviction_fence_ops, &ev_fence->lock, evf_mgr->ev_fence_ctx, atomic_inc_return(&evf_mgr->ev_fence_seq)); - return ev_fence; -} - -void amdgpu_eviction_fence_destroy(struct amdgpu_eviction_fence_mgr *evf_mgr) -{ - struct amdgpu_eviction_fence *ev_fence; - - /* Wait for any pending work to execute */ - flush_delayed_work(&evf_mgr->suspend_work); - - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - spin_unlock(&evf_mgr->ev_fence_lock); - - if (!ev_fence) - return; - - dma_fence_wait(&ev_fence->base, false); - - /* Last unref of ev_fence */ - dma_fence_put(&ev_fence->base); -} -int amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo) -{ - struct amdgpu_eviction_fence *ev_fence; - struct dma_resv *resv = bo->tbo.base.resv; - int ret; + /* Remember it for newly added BOs */ + dma_fence_put(evf_mgr->ev_fence); + evf_mgr->ev_fence = &ev_fence->base; - if (!resv) - return 0; + /* And add it to all existing BOs */ + drm_exec_for_each_locked_object(exec, index, obj) { + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - ret = dma_resv_reserve_fences(resv, 1); - if (ret) { - DRM_DEBUG_DRIVER("Failed to resv fence space\n"); - return ret; + amdgpu_evf_mgr_attach_fence(evf_mgr, bo); } - - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - if (ev_fence) - dma_resv_add_fence(resv, &ev_fence->base, DMA_RESV_USAGE_BOOKKEEP); - spin_unlock(&evf_mgr->ev_fence_lock); - return 0; } -void amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo) +void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo) { struct dma_fence *stub = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, evf_mgr->ev_fence_ctx, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), evf_mgr->ev_fence_ctx, stub, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(stub); } -int amdgpu_eviction_fence_init(struct amdgpu_eviction_fence_mgr *evf_mgr) +void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr) { - /* This needs to be done one time per open */ atomic_set(&evf_mgr->ev_fence_seq, 0); evf_mgr->ev_fence_ctx = dma_fence_context_alloc(1); - spin_lock_init(&evf_mgr->ev_fence_lock); + evf_mgr->ev_fence = dma_fence_get_stub(); - INIT_DELAYED_WORK(&evf_mgr->suspend_work, amdgpu_eviction_fence_suspend_worker); - return 0; + INIT_WORK(&evf_mgr->suspend_work, amdgpu_eviction_fence_suspend_worker); +} + +void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + evf_mgr->shutdown = true; + /* Make sure that the shutdown is visible to the suspend work */ + flush_work(&evf_mgr->suspend_work); +} + +void amdgpu_evf_mgr_flush_suspend(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + dma_fence_wait(rcu_dereference_protected(evf_mgr->ev_fence, true), + false); + /* Make sure that we are done with the last suspend work */ + flush_work(&evf_mgr->suspend_work); +} + +void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + dma_fence_put(evf_mgr->ev_fence); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h index fcd867b7147dd..2a750add4e7b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h @@ -25,6 +25,8 @@ #ifndef AMDGPU_EV_FENCE_H_ #define AMDGPU_EV_FENCE_H_ +#include + struct amdgpu_eviction_fence { struct dma_fence base; spinlock_t lock; @@ -35,35 +37,36 @@ struct amdgpu_eviction_fence { struct amdgpu_eviction_fence_mgr { u64 ev_fence_ctx; atomic_t ev_fence_seq; - spinlock_t ev_fence_lock; - struct amdgpu_eviction_fence *ev_fence; - struct delayed_work suspend_work; - uint8_t fd_closing; -}; - -/* Eviction fence helper functions */ -struct amdgpu_eviction_fence * -amdgpu_eviction_fence_create(struct amdgpu_eviction_fence_mgr *evf_mgr); -void -amdgpu_eviction_fence_destroy(struct amdgpu_eviction_fence_mgr *evf_mgr); - -int -amdgpu_eviction_fence_attach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo); + /* + * Only updated while holding the VM resv lock. + * Only signaled while holding the userq mutex. + */ + struct dma_fence __rcu *ev_fence; + struct work_struct suspend_work; + bool shutdown; +}; -void -amdgpu_eviction_fence_detach(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_bo *bo); +static inline struct dma_fence * +amdgpu_evf_mgr_get_fence(struct amdgpu_eviction_fence_mgr *evf_mgr) +{ + struct dma_fence *ev_fence; -int -amdgpu_eviction_fence_init(struct amdgpu_eviction_fence_mgr *evf_mgr); + rcu_read_lock(); + ev_fence = dma_fence_get_rcu_safe(&evf_mgr->ev_fence); + rcu_read_unlock(); + return ev_fence; +} -void -amdgpu_eviction_fence_signal(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct amdgpu_eviction_fence *ev_fence); +int amdgpu_evf_mgr_attach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo); +int amdgpu_evf_mgr_rearm(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct drm_exec *exec); +void amdgpu_evf_mgr_detach_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, + struct amdgpu_bo *bo); +void amdgpu_evf_mgr_init(struct amdgpu_eviction_fence_mgr *evf_mgr); +void amdgpu_evf_mgr_shutdown(struct amdgpu_eviction_fence_mgr *evf_mgr); +void amdgpu_evf_mgr_flush_suspend(struct amdgpu_eviction_fence_mgr *evf_mgr); +void amdgpu_evf_mgr_fini(struct amdgpu_eviction_fence_mgr *evf_mgr); -int -amdgpu_eviction_fence_replace_fence(struct amdgpu_eviction_fence_mgr *evf_mgr, - struct drm_exec *exec); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c index b349bb3676d5f..e6bc424d5debd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c @@ -115,8 +115,13 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file) stats[TTM_PL_TT].drm.private) / 1024UL); for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { +#ifdef HAVE_KTIME_IS_UNION + if (!usage[hw_ip].tv64) + continue; +#else if (!usage[hw_ip]) continue; +#endif drm_printf(p, "drm-engine-%s:\t%lld ns\n", amdgpu_ip_name[hw_ip], ktime_to_ns(usage[hw_ip])); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index d78d9e7fb9d15..aefa0bcbf8d26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -89,16 +89,6 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring) return seq; } -static void amdgpu_fence_save_fence_wptr_start(struct amdgpu_fence *af) -{ - af->fence_wptr_start = af->ring->wptr; -} - -static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af) -{ - af->fence_wptr_end = af->ring->wptr; -} - /** * amdgpu_fence_emit - emit a fence on the requested ring * @@ -107,16 +97,14 @@ static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af) * @flags: flags to pass into the subordinate .emit_fence() call * * Emits a fence command on the requested ring (all asics). - * Returns 0 on success, -ENOMEM on failure. */ -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, - unsigned int flags) +void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, + unsigned int flags) { struct amdgpu_device *adev = ring->adev; struct dma_fence *fence; struct dma_fence __rcu **ptr; uint32_t seq; - int r; fence = &af->base; af->ring = ring; @@ -126,11 +114,9 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, &ring->fence_drv.lock, adev->fence_context + ring->idx, seq); - amdgpu_fence_save_fence_wptr_start(af); amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, seq, flags | AMDGPU_FENCE_FLAG_INT); - amdgpu_fence_save_fence_wptr_end(af); - amdgpu_fence_save_wptr(af); + pm_runtime_get_noresume(adev_to_drm(adev)->dev); ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; if (unlikely(rcu_dereference_protected(*ptr, 1))) { @@ -141,10 +127,13 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, rcu_read_unlock(); if (old) { - r = dma_fence_wait(old, false); + /* + * dma_fence_wait(old, false) is not interruptible. + * It will not return an error in this case. + * So we can safely ignore the return value. + */ + dma_fence_wait(old, false); dma_fence_put(old); - if (r) - return r; } } @@ -154,8 +143,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, * emitting the fence would mess up the hardware ring buffer. */ rcu_assign_pointer(*ptr, dma_fence_get(fence)); - - return 0; } /** @@ -241,7 +228,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) do { struct dma_fence *fence, **ptr; - struct amdgpu_fence *am_fence; ++last_seq; last_seq &= drv->num_fences_mask; @@ -254,12 +240,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) if (!fence) continue; - /* Save the wptr in the fence driver so we know what the last processed - * wptr was. This is required for re-emitting the ring state for - * queues that are reset but are not guilty and thus have no guilty fence. - */ - am_fence = container_of(fence, struct amdgpu_fence, base); - drv->signalled_wptr = am_fence->wptr; dma_fence_signal(fence); dma_fence_put(fence); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -458,7 +438,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, * @ring: ring to init the fence driver on * * Init the fence driver for the requested ring (all asics). - * Helper function for amdgpu_fence_driver_init(). + * Helper function for amdgpu_fence_driver_sw_init(). */ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) { @@ -686,7 +666,6 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error) */ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) { - amdgpu_fence_driver_set_error(ring, -ECANCELED); amdgpu_fence_write(ring, ring->fence_drv.sync_seq); amdgpu_fence_process(ring); } @@ -708,25 +687,29 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) */ /** - * amdgpu_fence_driver_guilty_force_completion - force signal of specified sequence + * amdgpu_ring_set_fence_errors_and_reemit - Set dma_fence errors and reemit * - * @af: fence of the ring to signal + * @ring: the ring to operate on + * @guilty_fence: fence of the ring to update * */ -void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af) +void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring, + struct amdgpu_fence *guilty_fence) { struct dma_fence *unprocessed; struct dma_fence __rcu **ptr; struct amdgpu_fence *fence; - struct amdgpu_ring *ring = af->ring; unsigned long flags; u32 seq, last_seq; - bool reemitted = false; + unsigned int i; + bool is_guilty_fence; + bool is_guilty_context; last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; - /* mark all fences from the guilty context with an error */ + ring->reemit = true; + amdgpu_ring_alloc(ring, ring->ring_backup_entries_to_copy); spin_lock_irqsave(&ring->fence_drv.lock, flags); do { last_seq++; @@ -738,39 +721,45 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af) if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) { fence = container_of(unprocessed, struct amdgpu_fence, base); + is_guilty_fence = fence == guilty_fence; + is_guilty_context = fence->context == guilty_fence->context; - if (fence->reemitted > 1) - reemitted = true; - else if (fence == af) + /* mark all fences from the guilty context with an error */ + if (is_guilty_fence) dma_fence_set_error(&fence->base, -ETIME); - else if (fence->context == af->context) + else if (is_guilty_context) dma_fence_set_error(&fence->base, -ECANCELED); + + /* reemit the packet stream and update wptrs */ + fence->ib_wptr = ring->wptr; + for (i = 0; i < fence->ib_dw_size; i++) { + /* Skip the IB(s) for the guilty context. */ + if (is_guilty_context && + i >= fence->skip_ib_dw_start_offset && + i < fence->skip_ib_dw_end_offset) + amdgpu_ring_write(ring, ring->funcs->nop); + else + amdgpu_ring_write(ring, + ring->ring_backup[fence->backup_idx + i]); + } } rcu_read_unlock(); } while (last_seq != seq); spin_unlock_irqrestore(&ring->fence_drv.lock, flags); - - if (reemitted) { - /* if we've already reemitted once then just cancel everything */ - amdgpu_fence_driver_force_completion(af->ring); - af->ring->ring_backup_entries_to_copy = 0; - } -} - -void amdgpu_fence_save_wptr(struct amdgpu_fence *af) -{ - af->wptr = af->ring->wptr; + amdgpu_ring_commit(ring); + ring->reemit = false; } static void amdgpu_ring_backup_unprocessed_command(struct amdgpu_ring *ring, - u64 start_wptr, u64 end_wptr) + struct amdgpu_fence *af) { - unsigned int first_idx = start_wptr & ring->buf_mask; - unsigned int last_idx = end_wptr & ring->buf_mask; + unsigned int first_idx = af->ib_wptr & ring->buf_mask; + unsigned int dw_size = af->ib_dw_size; unsigned int i; + af->backup_idx = ring->ring_backup_entries_to_copy; /* Backup the contents of the ring buffer. */ - for (i = first_idx; i != last_idx; ++i, i &= ring->buf_mask) + for (i = first_idx; dw_size > 0; ++i, i &= ring->buf_mask, --dw_size) ring->ring_backup[ring->ring_backup_entries_to_copy++] = ring->ring[i]; } @@ -780,12 +769,10 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, struct dma_fence *unprocessed; struct dma_fence __rcu **ptr; struct amdgpu_fence *fence; - u64 wptr; u32 seq, last_seq; last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; - wptr = ring->fence_drv.signalled_wptr; ring->ring_backup_entries_to_copy = 0; do { @@ -799,21 +786,7 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring, if (unprocessed && !dma_fence_is_signaled(unprocessed)) { fence = container_of(unprocessed, struct amdgpu_fence, base); - /* save everything if the ring is not guilty, otherwise - * just save the content from other contexts. - */ - if (!fence->reemitted && - (!guilty_fence || (fence->context != guilty_fence->context))) { - amdgpu_ring_backup_unprocessed_command(ring, wptr, - fence->wptr); - } else if (!fence->reemitted) { - /* always save the fence */ - amdgpu_ring_backup_unprocessed_command(ring, - fence->fence_wptr_start, - fence->fence_wptr_end); - } - wptr = fence->wptr; - fence->reemitted++; + amdgpu_ring_backup_unprocessed_command(ring, fence); } rcu_read_unlock(); } while (last_seq != seq); @@ -936,9 +909,9 @@ static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused) * * Manually trigger a gpu reset at the next fence wait. */ -static int gpu_recover_get(void *data, u64 *val) +static int amdgpu_debugfs_gpu_recover_show(struct seq_file *m, void *unused) { - struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); int r; @@ -951,7 +924,7 @@ static int gpu_recover_get(void *data, u64 *val) if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work)) flush_work(&adev->reset_work); - *val = atomic_read(&adev->reset_domain->reset_res); + // *val = atomic_read(&adev->reset_domain->reset_res); pm_runtime_put_autosuspend(dev->dev); @@ -959,8 +932,7 @@ static int gpu_recover_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); -DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, - "%lld\n"); +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gpu_recover); static void amdgpu_debugfs_reset_work(struct work_struct *work) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c index b0082aa7f3c61..c5178e2b794d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c @@ -106,6 +106,7 @@ static bool is_fru_eeprom_supported(struct amdgpu_device *adev, u32 *fru_addr) *fru_addr = FRU_EEPROM_MADDR_8; return true; case IP_VERSION(13, 0, 12): + case IP_VERSION(15, 0, 8): if (fru_addr) *fru_addr = FRU_EEPROM_MADDR_INV; return true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c index 328a1b9635481..988ec7d7b4874 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.c @@ -62,17 +62,17 @@ static ssize_t amdgpu_fw_attestation_debugfs_read(struct file *f, struct FW_ATT_RECORD fw_att_record = {0}; if (size < sizeof(struct FW_ATT_RECORD)) { - DRM_WARN("FW attestation input buffer not enough memory"); + drm_warn(adev_to_drm(adev), "FW attestation input buffer not enough memory"); return -EINVAL; } if ((*pos + sizeof(struct FW_ATT_DB_HEADER)) >= FW_ATTESTATION_MAX_SIZE) { - DRM_WARN("FW attestation out of bounds"); + drm_warn(adev_to_drm(adev), "FW attestation out of bounds"); return 0; } if (psp_get_fw_attestation_records_addr(&adev->psp, &records_addr)) { - DRM_WARN("Failed to get FW attestation record address"); + drm_warn(adev_to_drm(adev), "Failed to get FW attestation record address"); return -EINVAL; } @@ -86,11 +86,12 @@ static ssize_t amdgpu_fw_attestation_debugfs_read(struct file *f, false); if (fw_att_hdr.AttDbCookie != FW_ATTESTATION_DB_COOKIE) { - DRM_WARN("Invalid FW attestation cookie"); + drm_warn(adev_to_drm(adev), "Invalid FW attestation cookie"); return -EINVAL; } - DRM_INFO("FW attestation version = 0x%X", fw_att_hdr.AttDbVersion); + drm_info(adev_to_drm(adev), "FW attestation version = 0x%X", + fw_att_hdr.AttDbVersion); } amdgpu_device_vram_access(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c index 1485f47894401..4d884180cf61c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c @@ -403,6 +403,50 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, drm_dev_exit(idx); } +/** + * amdgpu_gart_map_gfx9_mqd - map mqd and ctrl_stack dma_addresses into GART entries + * + * @adev: amdgpu_device pointer + * @offset: offset into the GPU's gart aperture + * @pages: number of pages to bind + * @dma_addr: DMA addresses of pages + * @flags: page table entry flags + * + * Map the MQD and control stack addresses into GART entries with the correct + * memory types on gfxv9. The MQD occupies the first 4KB and is followed by + * the control stack. The MQD uses UC (uncached) memory, while the control stack + * uses NC (non-coherent) memory. + */ +void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset, + int pages, dma_addr_t *dma_addr, uint64_t flags) +{ + uint64_t page_base; + unsigned int i, j, t; + int idx; + uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); + void *dst; + + if (!adev->gart.ptr) + return; + + if (!drm_dev_enter(adev_to_drm(adev), &idx)) + return; + + t = offset / AMDGPU_GPU_PAGE_SIZE; + dst = adev->gart.ptr; + for (i = 0; i < pages; i++) { + page_base = dma_addr[i]; + for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) { + if ((i == 0) && (j == 0)) + amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); + else + amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, ctrl_flags); + page_base += AMDGPU_GPU_PAGE_SIZE; + } + } + drm_dev_exit(idx); +} + /** * amdgpu_gart_bind - bind pages into the gart page table * @@ -476,7 +520,7 @@ int amdgpu_gart_init(struct amdgpu_device *adev) /* Compute table size */ adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; - DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", + drm_info(adev_to_drm(adev), "GART: num cpu pages %u, num gpu pages %u\n", adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index d3118275ddae8..6ebd2da32ea60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -62,6 +62,8 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, int pages, dma_addr_t *dma_addr, uint64_t flags, void *dst); +void amdgpu_gart_map_gfx9_mqd(struct amdgpu_device *adev, uint64_t offset, + int pages, dma_addr_t *dma_addr, uint64_t flags); void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, int pages, dma_addr_t *dma_addr, uint64_t flags); void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 3e38c5db29871..6e3e192e8210e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -106,56 +107,26 @@ amdgpu_gem_update_timeline_node(struct drm_file *filp, *chain = dma_fence_chain_alloc(); if (!*chain) { drm_syncobj_put(*syncobj); + *syncobj = NULL; return -ENOMEM; } return 0; } -static void -amdgpu_gem_update_bo_mapping(struct drm_file *filp, - struct amdgpu_bo_va *bo_va, - uint32_t operation, - uint64_t point, - struct dma_fence *fence, - struct drm_syncobj *syncobj, - struct dma_fence_chain *chain) -{ - struct amdgpu_bo *bo = bo_va ? bo_va->base.bo : NULL; - struct amdgpu_fpriv *fpriv = filp->driver_priv; - struct amdgpu_vm *vm = &fpriv->vm; - struct dma_fence *last_update; - - if (!syncobj) - return; - - /* Find the last update fence */ - switch (operation) { - case AMDGPU_VA_OP_MAP: - case AMDGPU_VA_OP_REPLACE: - if (bo && (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)) - last_update = vm->last_update; - else - last_update = bo_va->last_pt_update; - break; - case AMDGPU_VA_OP_UNMAP: - case AMDGPU_VA_OP_CLEAR: - last_update = fence; - break; - default: - return; - } - - /* Add fence to timeline */ - if (!point) - drm_syncobj_replace_fence(syncobj, last_update); - else - drm_syncobj_add_point(syncobj, chain, last_update, point); -} +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#else +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) { - struct ttm_buffer_object *bo = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#endif + struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret; int idx; @@ -171,18 +142,18 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) goto unlock; } - ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT); + ret = ttm_bo_vm_fault_reserved(vmf, vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); drm_dev_exit(idx); } else { - ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); + ret = ttm_bo_vm_dummy_page(vmf, vma->vm_page_prot); } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; unlock: - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } @@ -194,8 +165,25 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { }; static void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#endif { struct amdgpu_bo *aobj = gem_to_amdgpu_bo(gobj); + struct amdgpu_device *adev; + + if (aobj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { + if (!amdgpu_bo_reserve(aobj, false)) { + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); + } + } + + adev = amdgpu_ttm_adev(aobj->tbo.bdev); + if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + atomic64_sub(amdgpu_bo_size(aobj), + &adev->direct_gma.vram_usage); + else if (aobj->tbo.resource && aobj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + atomic64_sub(amdgpu_bo_size(aobj), + &adev->direct_gma.gart_usage); amdgpu_hmm_unregister(aobj); ttm_bo_fini(&aobj->tbo); @@ -210,12 +198,30 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, struct amdgpu_bo *bo; struct amdgpu_bo_user *ubo; struct amdgpu_bo_param bp; + unsigned long max_size; int r; memset(&bp, 0, sizeof(bp)); *obj = NULL; flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; + if ((initial_domain & AMDGPU_GEM_DOMAIN_DGMA) || + (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { + flags |= AMDGPU_GEM_CREATE_NO_EVICT; + max_size = (unsigned long)amdgpu_direct_gma_size << 20; + + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + max_size -= atomic64_read(&adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + max_size -= atomic64_read(&adev->direct_gma.gart_usage); + + if (size > max_size) { + DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", + size >> 20, max_size >> 20); + return -ENOMEM; + } + } + bp.size = size; bp.byte_align = alignment; bp.type = type; @@ -233,6 +239,11 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, bo = &ubo->bo; *obj = &bo->tbo.base; + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + atomic64_add(size, &adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + atomic64_add(size, &adev->direct_gma.gart_usage); + return 0; } @@ -264,8 +275,13 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */ +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); @@ -273,6 +289,7 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; struct mm_struct *mm; + struct drm_exec exec; int r; mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); @@ -283,26 +300,31 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, !amdgpu_vm_is_bo_always_valid(vm, abo)) return -EPERM; - r = amdgpu_bo_reserve(abo, false); - if (r) - return r; + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); + drm_exec_until_all_locked(&exec) { + r = drm_exec_prepare_obj(&exec, &abo->tbo.base, 1); + drm_exec_retry_on_contention(&exec); + if (unlikely(r)) + goto out_unlock; + + r = amdgpu_vm_lock_pd(vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (unlikely(r)) + goto out_unlock; + } amdgpu_vm_bo_update_shared(abo); bo_va = amdgpu_vm_bo_find(vm, abo); - if (!bo_va) + if (!bo_va) { bo_va = amdgpu_vm_bo_add(adev, vm, abo); - else + r = amdgpu_evf_mgr_attach_fence(&fpriv->evf_mgr, abo); + if (r) + goto out_unlock; + } else { ++bo_va->ref_count; - - /* attach gfx eviction fence */ - r = amdgpu_eviction_fence_attach(&fpriv->evf_mgr, abo); - if (r) { - DRM_DEBUG_DRIVER("Failed to attach eviction fence to BO\n"); - amdgpu_bo_unreserve(abo); - return r; } - amdgpu_bo_unreserve(abo); + drm_exec_fini(&exec); /* Validate and add eviction fence to DMABuf imports with dynamic * attachment in compute VMs. Re-validation will be done by @@ -335,12 +357,20 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, } } mutex_unlock(&vm->process_info->lock); + return r; +out_unlock: + drm_exec_fini(&exec); return r; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -366,7 +396,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, } if (!amdgpu_vm_is_bo_always_valid(vm, bo)) - amdgpu_eviction_fence_detach(&fpriv->evf_mgr, bo); + amdgpu_evf_mgr_detach_fence(&fpriv->evf_mgr, bo); bo_va = amdgpu_vm_bo_find(vm, bo); if (!bo_va || --bo_va->ref_count) @@ -378,7 +408,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, goto out_unlock; r = amdgpu_vm_clear_freed(adev, vm, &fence); - if (unlikely(r < 0)) + if (unlikely(r < 0) && !drm_dev_is_unplugged(adev_to_drm(adev))) dev_err(adev->dev, "failed to clear page " "tables on GEM object close (%ld)\n", r); if (r || !fence) @@ -388,11 +418,12 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, dma_fence_put(fence); out_unlock: - if (r) + if (r && !drm_dev_is_unplugged(adev_to_drm(adev))) dev_err(adev->dev, "leaking bo va (%ld)\n", r); drm_exec_fini(&exec); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); @@ -413,17 +444,28 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#endif +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#elif defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) + .vmap = amdgpu_drm_gem_ttm_vmap, + .vunmap = amdgpu_drm_gem_ttm_vunmap, +#else + .vmap = amdgpu_gem_prime_vmap, + .vunmap = amdgpu_gem_prime_vunmap, +#endif .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; +#endif /* * GEM ioctls. @@ -458,9 +500,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, /* always clear VRAM */ flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; - if (args->in.domains & AMDGPU_GEM_DOMAIN_MMIO_REMAP) - return -EINVAL; - /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { @@ -479,7 +518,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, if (r) return r; - resv = vm->root.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); } initial_domain = (u32)(0xffffffff & args->in.domains); @@ -572,19 +611,27 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto release_object; if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED range = amdgpu_hmm_range_alloc(NULL); if (unlikely(!range)) return -ENOMEM; r = amdgpu_ttm_tt_get_user_pages(bo, range); +#else + r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages); +#endif if (r) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_hmm_range_free(range); +#endif goto release_object; } r = amdgpu_bo_reserve(bo, true); if (r) goto user_pages_done; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, range); +#endif amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); @@ -594,20 +641,91 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, } r = drm_gem_handle_create(filp, gobj, &handle); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (r) goto user_pages_done; args->handle = handle; +#else + /* drop reference from allocate - handle holds it now */ + drm_gem_object_put(gobj); + if (r) + return r; + + args->handle = handle; + return 0; +#endif user_pages_done: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) amdgpu_hmm_range_free(range); +#else + release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); +#endif + release_object: drm_gem_object_put(gobj); return r; } +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + struct drm_amdgpu_gem_dgma *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct drm_gem_object *gobj; + struct amdgpu_bo *abo; + dma_addr_t *dma_addr; + uint32_t handle; + int i, r = 0; + + switch (args->op) { + case AMDGPU_GEM_DGMA_IMPORT: + /* create a gem object to contain this object in */ + r = amdgpu_gem_object_create(adev, args->size, 0, + AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, + 0, NULL, &gobj, fpriv->xcp_id + 1); + if (r) + return r; + + abo = gem_to_amdgpu_bo(gobj); + dma_addr = kmalloc_array(PFN_UP(abo->tbo.resource->size), sizeof(dma_addr_t), GFP_KERNEL); + if (unlikely(dma_addr == NULL)) + goto release_object; + + for (i = 0; i < PFN_UP(abo->tbo.resource->size); i++) + dma_addr[i] = args->addr + i * PAGE_SIZE; + abo->dgma_import_base = args->addr; + abo->dgma_addr = (void *)dma_addr; + r = drm_gem_handle_create(filp, gobj, &handle); + args->handle = handle; + break; + case AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR: + gobj = drm_gem_object_lookup(filp, args->handle); + if (gobj == NULL) + return -ENOENT; + + abo = gem_to_amdgpu_bo(gobj); + if (abo->tbo.resource->mem_type != AMDGPU_PL_DGMA) { + r = -EINVAL; + goto release_object; + } + args->addr = amdgpu_bo_gpu_offset(abo) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM) + + adev->gmc.aper_base; + break; + default: + return -EINVAL; + } + +release_object: + drm_gem_object_put(gobj); + return r; +} + int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p) @@ -684,7 +802,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, return -ENOENT; robj = gem_to_amdgpu_bo(gobj); - ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(&robj->tbo), DMA_RESV_USAGE_READ, true, timeout); /* ret == 0 means not signaled, @@ -719,6 +837,15 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, if (unlikely(r != 0)) goto out; + /* Reject MMIO_REMAP BOs at IOCTL level: metadata/tiling does not apply. */ + if (robj->tbo.resource && + robj->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP) { + DRM_WARN("metadata ioctl on MMIO_REMAP BO (handle %d)\n", + args->handle); + r = -EINVAL; + goto unreserve; + } + if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); r = amdgpu_bo_get_metadata(robj, args->data.data, @@ -760,20 +887,31 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, */ static struct dma_fence * amdgpu_gem_va_update_vm(struct amdgpu_device *adev, - struct amdgpu_vm *vm, + struct amdgpu_fpriv *fpriv, struct amdgpu_bo_va *bo_va, uint32_t operation) { - struct dma_fence *fence = dma_fence_get_stub(); - int r; + struct dma_fence *fence; + struct amdgpu_vm *vm = &fpriv->vm; + int r = 0; + /* If the VM is not ready return only a stub. */ if (!amdgpu_vm_ready(vm)) - return fence; + return dma_fence_get_stub(); - r = amdgpu_vm_clear_freed(adev, vm, &fence); + + /* + * First clean up any freed mappings in the VM. + * + * amdgpu_vm_clear_freed() may replace @fence with a new fence if it + * schedules GPU work. If nothing needs clearing, @fence can remain as + * the original vm->last_update. + */ + r = amdgpu_vm_clear_freed(adev, vm, &vm->last_update); if (r) goto error; + /* For MAP/REPLACE we also need to update the BO mappings. */ if (operation == AMDGPU_VA_OP_MAP || operation == AMDGPU_VA_OP_REPLACE) { r = amdgpu_vm_bo_update(adev, bo_va, false); @@ -781,13 +919,56 @@ amdgpu_gem_va_update_vm(struct amdgpu_device *adev, goto error; } + /* Always update PDEs after we touched the mappings. */ r = amdgpu_vm_update_pdes(adev, vm, false); + if (r) + goto error; + + if (vm->is_compute_context) { + if (bo_va->last_pt_update) + r = dma_fence_wait(bo_va->last_pt_update, true); + if (!r && vm->last_update) + r = dma_fence_wait(vm->last_update, true); + if (!r) { + uint32_t xcc_mask = (!adev->xcp_mgr || + fpriv->xcp_id == ~0) ? 1 : + adev->xcp_mgr->xcp[fpriv->xcp_id] + .ip[AMDGPU_XCP_GFX].inst_mask; + + r = amdgpu_vm_flush_compute_tlb(adev, vm, + TLB_FLUSH_LEGACY, + xcc_mask); + } + } + + if ((operation == AMDGPU_VA_OP_MAP || + operation == AMDGPU_VA_OP_REPLACE) && + !amdgpu_vm_is_bo_always_valid(vm, bo_va->base.bo)) { + + /* + * For MAP/REPLACE of non per-VM BOs we need to sync to both the + * bo_va->last_pt_update and vm->last_update or otherwise we + * potentially miss the PDE updates. + */ + fence = dma_fence_unwrap_merge(vm->last_update, + bo_va->last_pt_update); + if (!fence) { + /* As fallback in OOM situations */ + dma_fence_wait(vm->last_update, false); + dma_fence_wait(bo_va->last_pt_update, false); + fence = dma_fence_get_stub(); + } + } else { + fence = dma_fence_get(vm->last_update); + } + + return fence; error: if (r && r != -ERESTARTSYS) DRM_ERROR("Couldn't update BO_VA (%d)\n", r); - return fence; + return dma_fence_get(vm->last_update); } int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, @@ -808,11 +989,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, struct amdgpu_bo_va *bo_va; struct drm_syncobj *timeline_syncobj = NULL; struct dma_fence_chain *timeline_chain = NULL; - struct dma_fence *fence; struct drm_exec exec; uint64_t vm_size; int r = 0; + /* Validate virtual address range against reserved regions. */ if (args->va_address < AMDGPU_VA_RESERVED_BOTTOM) { dev_dbg(dev->dev, "va_address 0x%llx is in reserved area 0x%llx\n", @@ -846,6 +1027,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } + /* Validate operation type. */ switch (args->operation) { case AMDGPU_VA_OP_MAP: case AMDGPU_VA_OP_UNMAP: @@ -858,6 +1040,10 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, return -EINVAL; } + if (args->flags & AMDGPU_VM_DELAY_UPDATE && + args->vm_timeline_syncobj_out) + return -EINVAL; + if ((args->operation != AMDGPU_VA_OP_CLEAR) && !(args->flags & AMDGPU_VM_PAGE_PRT)) { gobj = drm_gem_object_lookup(filp, args->handle); @@ -869,6 +1055,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, abo = NULL; } + /* Add input syncobj fences (if any) for synchronization. */ r = amdgpu_gem_add_input_fence(filp, args->input_fence_syncobj_handles, args->num_syncobj_handles); @@ -891,6 +1078,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, goto error; } + /* Resolve the BO-VA mapping for this VM/BO combination. */ if (abo) { bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); if (!bo_va) { @@ -903,6 +1091,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, bo_va = NULL; } + /* + * Prepare the timeline syncobj node if the user requested a VM + * timeline update. This only allocates/looks up the syncobj and + * chain node; the actual fence is attached later. + */ r = amdgpu_gem_update_timeline_node(filp, args->vm_timeline_syncobj_out, args->vm_timeline_point, @@ -934,22 +1127,40 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, default: break; } - if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) { - fence = amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, - args->operation); - if (timeline_syncobj) - amdgpu_gem_update_bo_mapping(filp, bo_va, - args->operation, - args->vm_timeline_point, - fence, timeline_syncobj, - timeline_chain); - else - dma_fence_put(fence); + /* + * Once the VA operation is done, update the VM and obtain the fence + * that represents the last relevant update for this mapping. This + * fence can then be exported to the user-visible VM timeline. + */ + if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && + (!adev->debug_vm || timeline_syncobj)) { + struct dma_fence *fence; + + fence = amdgpu_gem_va_update_vm(adev, fpriv, bo_va, + args->operation); + if (timeline_syncobj) { + if (!args->vm_timeline_point) { + /* Replace the existing fence when no point is given. */ + drm_syncobj_replace_fence(timeline_syncobj, + fence); + } else { + /* Attach the last-update fence at a specific point. */ + drm_syncobj_add_point(timeline_syncobj, + timeline_chain, + fence, + args->vm_timeline_point); + timeline_chain = NULL; + } + } + dma_fence_put(fence); } error: + dma_fence_chain_free(timeline_chain); + if (timeline_syncobj) + drm_syncobj_put(timeline_syncobj); drm_exec_fini(&exec); error_put_gobj: drm_gem_object_put(gobj); @@ -1225,6 +1436,7 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); + args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, @@ -1270,7 +1482,12 @@ static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) */ rcu_read_lock(); pid = rcu_dereference(file->pid); - task = pid_task(pid, PIDTYPE_TGID); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PID); +#endif seq_printf(m, "pid %8d command %s:\n", pid_nr(pid), task ? task->comm : ""); rcu_read_unlock(); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h index b558336bc4c6c..51dbaec84db28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.h @@ -33,7 +33,9 @@ #define AMDGPU_GEM_DOMAIN_MAX 0x3 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, tbo.base) +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK extern const struct drm_gem_object_funcs amdgpu_gem_object_funcs; +#endif unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); @@ -82,6 +84,7 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE | \ AMDGPU_GEM_CREATE_ENCRYPTED | \ AMDGPU_GEM_CREATE_GFX12_DCC | \ + AMDGPU_GEM_CREATE_GFX12_DCC | \ AMDGPU_GEM_CREATE_DISCARDABLE | \ AMDGPU_GEM_CREATE_COHERENT | \ AMDGPU_GEM_CREATE_UNCACHED | \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 8b118c53f3515..cab3196a87fb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -100,6 +100,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, /** * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter * + * @adev: amdgpu device pointer * @mask: array in which the per-shader array disable masks will be stored * @max_se: number of SEs * @max_sh: number of SHs @@ -107,7 +108,8 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, * The bitmask of CUs to be disabled in the shader array determined by se and * sh is stored in mask[se * max_sh + sh]. */ -void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh) +void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, + unsigned int max_se, unsigned int max_sh) { unsigned int se, sh, cu; const char *p; @@ -123,16 +125,16 @@ void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsign int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu); if (ret < 3) { - DRM_ERROR("amdgpu: could not parse disable_cu\n"); + drm_err(adev_to_drm(adev), "could not parse disable_cu\n"); return; } if (se < max_se && sh < max_sh && cu < 16) { - DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu); + drm_info(adev_to_drm(adev), "Disabling CU %u.%u.%u\n", se, sh, cu); mask[se * max_sh + sh] |= 1u << cu; } else { - DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n", - se, sh, cu); + drm_err(adev_to_drm(adev), "disable_cu %u.%u.%u is out of range\n", + se, sh, cu); } next = strchr(p, ','); @@ -150,7 +152,7 @@ static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev) static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) { if (amdgpu_compute_multipipe != -1) { - dev_info(adev->dev, "amdgpu: forcing compute pipe policy %d\n", + dev_info(adev->dev, " forcing compute pipe policy %d\n", amdgpu_compute_multipipe); return amdgpu_compute_multipipe == 1; } @@ -383,6 +385,8 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; struct amdgpu_ring *ring = &kiq->ring; u32 domain = AMDGPU_GEM_DOMAIN_GTT; + u32 gfx_mqd_size = max(adev->mqds[AMDGPU_HW_IP_GFX].mqd_size, mqd_size); + u32 compute_mqd_size = max(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size, mqd_size); #if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ @@ -422,17 +426,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, for (i = 0; i < adev->gfx.num_gfx_rings; i++) { ring = &adev->gfx.gfx_ring[i]; if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - domain, &ring->mqd_obj, + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(gfx_mqd_size), + PAGE_SIZE, domain, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); return r; } - ring->mqd_size = mqd_size; + ring->mqd_size = gfx_mqd_size; /* prepare MQD backup */ - adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL); + adev->gfx.me.mqd_backup[i] = kzalloc(gfx_mqd_size, GFP_KERNEL); if (!adev->gfx.me.mqd_backup[i]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; @@ -446,17 +450,17 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, j = i + xcc_id * adev->gfx.num_compute_rings; ring = &adev->gfx.compute_ring[j]; if (!ring->mqd_obj) { - r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, - domain, &ring->mqd_obj, + r = amdgpu_bo_create_kernel(adev, AMDGPU_MQD_SIZE_ALIGN(compute_mqd_size), + PAGE_SIZE, domain, &ring->mqd_obj, &ring->mqd_gpu_addr, &ring->mqd_ptr); if (r) { dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); return r; } - ring->mqd_size = mqd_size; + ring->mqd_size = compute_mqd_size; /* prepare MQD backup */ - adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL); + adev->gfx.mec.mqd_backup[j] = kzalloc(compute_mqd_size, GFP_KERNEL); if (!adev->gfx.mec.mqd_backup[j]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; @@ -499,6 +503,55 @@ void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id) &ring->mqd_ptr); } +void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, + uint32_t cu_mask_count, uint32_t *se_mask) +{ + struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; + struct amdgpu_gfx_config *gfx_info = &adev->gfx.config; + uint32_t cu_per_sh[8][4] = {0}; + int i, se, sh, cu, cu_bitmap_sh_mul; + int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; + bool wgp_mode_req = amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0); + int cu_inc = wgp_mode_req ? 2 : 1; + uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1; + int num_xcc, inc, inst = 0; + + if (xcc_inst < 0) + xcc_inst = 0; + + num_xcc = hweight16(adev->gfx.xcc_mask); + if (!num_xcc) + num_xcc = 1; + + inc = cu_inc * num_xcc; + + cu_bitmap_sh_mul = 2; + + for (se = 0; se < gfx_info->max_shader_engines; se++) + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) + cu_per_sh[se][sh] = hweight32( + cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * + cu_bitmap_sh_mul]); + + for (i = 0; i < gfx_info->max_shader_engines; i++) + se_mask[i] = 0; + + i = inst; + for (cu = 0; cu < 16; cu += cu_inc) { + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { + for (se = 0; se < gfx_info->max_shader_engines; se++) { + if (cu_per_sh[se][sh] > cu) { + if ((i / 32) < cu_mask_count && (cu_mask[i / 32] & (1 << (i % 32)))) + se_mask[se] |= en_mask << (cu + sh * 16); + i += inc; + if (i >= cu_mask_count * 32) + return; + } + } + } + } +} + int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) { struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; @@ -511,7 +564,7 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) j = i + xcc_id * adev->gfx.num_compute_rings; amdgpu_mes_unmap_legacy_queue(adev, &adev->gfx.compute_ring[j], - RESET_QUEUES, 0, 0); + RESET_QUEUES, 0, 0, xcc_id); } return 0; } @@ -562,7 +615,7 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id) j = i + xcc_id * adev->gfx.num_gfx_rings; amdgpu_mes_unmap_legacy_queue(adev, &adev->gfx.gfx_ring[j], - PREEMPT_QUEUES, 0, 0); + PREEMPT_QUEUES, 0, 0, xcc_id); } } return 0; @@ -644,7 +697,8 @@ static int amdgpu_gfx_mes_enable_kcq(struct amdgpu_device *adev, int xcc_id) for (i = 0; i < adev->gfx.num_compute_rings; i++) { j = i + xcc_id * adev->gfx.num_compute_rings; r = amdgpu_mes_map_legacy_queue(adev, - &adev->gfx.compute_ring[j]); + &adev->gfx.compute_ring[j], + xcc_id); if (r) { dev_err(adev->dev, "failed to map compute queue\n"); return r; @@ -733,7 +787,8 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id) for (i = 0; i < adev->gfx.num_gfx_rings; i++) { j = i + xcc_id * adev->gfx.num_gfx_rings; r = amdgpu_mes_map_legacy_queue(adev, - &adev->gfx.gfx_ring[j]); + &adev->gfx.gfx_ring[j], + xcc_id); if (r) { dev_err(adev->dev, "failed to map gfx queue\n"); return r; @@ -1067,7 +1122,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_ return 0; if (adev->mes.ring[0].sched.ready) - return amdgpu_mes_rreg(adev, reg); + return amdgpu_mes_rreg(adev, reg, xcc_id); BUG_ON(!ring->funcs->emit_rreg); @@ -1143,7 +1198,7 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3 return; if (adev->mes.ring[0].sched.ready) { - amdgpu_mes_wreg(adev, reg, v); + amdgpu_mes_wreg(adev, reg, v, xcc_id); return; } @@ -1195,6 +1250,40 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3 dev_err(adev->dev, "failed to write reg:%x\n", reg); } +void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *hdp_flush_mask, uint32_t *reg_mem_engine) +{ + + if (!ring || !hdp_flush_mask || !reg_mem_engine) { + DRM_INFO("%s:invalid params\n", __func__); + return; + } + + const struct nbio_hdp_flush_reg *nbio_hf_reg = ring->adev->nbio.hdp_flush_reg; + + switch (ring->funcs->type) { + case AMDGPU_RING_TYPE_GFX: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; + *reg_mem_engine = 1; /* pfp */ + break; + case AMDGPU_RING_TYPE_COMPUTE: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; + *reg_mem_engine = 0; + break; + case AMDGPU_RING_TYPE_MES: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp8; + *reg_mem_engine = 0; + break; + case AMDGPU_RING_TYPE_KIQ: + *hdp_flush_mask = nbio_hf_reg->ref_and_mask_cp9; + *reg_mem_engine = 0; + break; + default: + DRM_ERROR("%s:unsupported ring type %d\n", __func__, ring->funcs->type); + return; + } +} + int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev) { signed long r, cnt = 0; @@ -1260,7 +1349,8 @@ int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev) failed_unlock: spin_unlock_irqrestore(&kiq->ring_lock, flags); failed_kiq_hdp_flush: - dev_err(adev->dev, "failed to flush HDP via KIQ\n"); + if (!amdgpu_in_reset(adev)) + dev_err(adev->dev, "failed to flush HDP via KIQ\n"); return r < 0 ? r : -EIO; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index efd61a1ccc661..67b590daccb39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -164,6 +164,15 @@ struct amdgpu_kiq { void *mqd_backup; }; +struct spm_funcs { + void (*start)(struct amdgpu_device *adev, int xcc_id); + void (*stop)(struct amdgpu_device *adev, int xcc_id); + void (*set_rdptr)(struct amdgpu_device *adev, int xcc_id, u32 rptr); + void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, int xcc_id, u64 gpu_rptr, u32 size); + /* Packet sizes */ + int set_spm_config_size; +}; + /* * GFX configurations */ @@ -328,6 +337,8 @@ struct amdgpu_gfx_shadow_info { u32 shadow_alignment; u32 csa_size; u32 csa_alignment; + u32 eop_size; + u32 eop_alignment; }; struct amdgpu_gfx_funcs { @@ -356,6 +367,8 @@ struct amdgpu_gfx_funcs { int num_xccs_per_xcp); int (*ih_node_to_logical_xcc)(struct amdgpu_device *adev, int ih_node); int (*get_xccs_per_xcp)(struct amdgpu_device *adev); + void (*get_hdp_flush_mask)(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine); }; struct sq_work { @@ -414,6 +427,7 @@ struct amdgpu_gfx { struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_imu imu; + const struct spm_funcs *spmfuncs; bool rs64_enable; /* firmware format */ const struct firmware *me_fw; /* ME firmware */ uint32_t me_fw_version; @@ -457,8 +471,10 @@ struct amdgpu_gfx { struct amdgpu_irq_src priv_inst_irq; struct amdgpu_irq_src bad_op_irq; struct amdgpu_irq_src cp_ecc_error_irq; + struct amdgpu_irq_src spm_irq; struct amdgpu_irq_src sq_irq; struct amdgpu_irq_src rlc_gc_fed_irq; + struct amdgpu_irq_src rlc_poison_irq; struct sq_work sq_work; /* gfx status */ @@ -565,8 +581,8 @@ static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width) return (u32)((1ULL << bit_width) - 1); } -void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, - unsigned max_sh); +void amdgpu_gfx_parse_disable_cu(struct amdgpu_device *adev, unsigned int *mask, + unsigned int max_se, unsigned int max_sh); int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, int xcc_id); @@ -579,6 +595,8 @@ int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, unsigned mqd_size, int xcc_id); void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); +void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, + uint32_t cu_mask_count, uint32_t *se_mask); int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id); @@ -615,6 +633,8 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_id); void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint32_t xcc_id); +void amdgpu_gfx_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine); int amdgpu_kiq_hdp_flush(struct amdgpu_device *adev); int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev); void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, uint32_t ucode_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index d9c7ad297293b..a549819566fa7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -34,6 +34,7 @@ #include "amdgpu_ras.h" #include "amdgpu_reset.h" #include "amdgpu_xgmi.h" +#include "amdgpu_atomfirmware.h" #include #include @@ -529,6 +530,54 @@ void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, } while (fault->timestamp < tmp); } +int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry, + u64 addr, + u32 cam_index, + u32 node_id, + bool write_fault) +{ + int ret; + + if (adev->irq.retry_cam_enabled) { + /* Delegate it to a different ring if the hardware hasn't + * already done it. + */ + if (entry->ih == &adev->irq.ih) { + amdgpu_irq_delegate(adev, entry, 8); + return 1; + } + + ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, + addr, entry->timestamp, write_fault); + WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); + if (ret) + return 1; + } else { + /* Process it only if it's the first fault for this address */ + if (entry->ih != &adev->irq.ih_soft && + amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, + entry->timestamp)) + return 1; + + /* Delegate it to a different ring if the hardware hasn't + * already done it. + */ + if (entry->ih == &adev->irq.ih) { + amdgpu_irq_delegate(adev, entry, 8); + return 1; + } + + /* Try to handle the recoverable page faults by filling page + * tables + */ + if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, + addr, entry->timestamp, write_fault)) + return 1; + } + return 0; +} + int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev) { int r; @@ -694,8 +743,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, * translation. Avoid this by doing the invalidation from the SDMA * itself at least for GART. */ - mutex_lock(&adev->mman.gtt_window_lock); - r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr, + mutex_lock(&adev->mman.default_entity.lock); + r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base, AMDGPU_FENCE_OWNER_UNDEFINED, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB); @@ -707,7 +756,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; amdgpu_ring_pad_ib(ring, &job->ibs[0]); fence = amdgpu_job_submit(job); - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); dma_fence_wait(fence, false); dma_fence_put(fence); @@ -715,7 +764,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, return; error_alloc: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&adev->mman.default_entity.lock); dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r); } @@ -723,10 +772,12 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) { + u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : + adev->usec_timeout; struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring; struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; unsigned int ndw; - int r, cnt = 0; + int r; uint32_t seq; /* @@ -789,17 +840,7 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, amdgpu_ring_commit(ring); spin_unlock(&adev->gfx.kiq[inst].ring_lock); - - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); - - might_sleep(); - while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && - !amdgpu_reset_pending(adev->reset_domain)) { - msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); - r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); - } - - if (cnt > MAX_KIQ_REG_TRY) { + if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) { dev_err(adev->dev, "timeout waiting for kiq fence\n"); r = -ETIME; } else @@ -822,9 +863,9 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, unsigned long flags; uint32_t seq; - if (adev->mes.ring[0].sched.ready) { + if (adev->mes.ring[MES_PIPE_INST(xcc_inst, 0)].sched.ready) { amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1, - ref, mask); + ref, mask, xcc_inst); return; } @@ -912,6 +953,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): /* Don't enable it by default yet. */ if (amdgpu_tmz < 1) { @@ -956,6 +998,27 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) gmc->noretry = 1; else gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; + + /* keep this for kfd test fail */ + switch (adev->asic_type) { + case CHIP_VEGA10: + case CHIP_NAVI10: + case CHIP_NAVI14: + case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: + case CHIP_DIMGREY_CAVEFISH: + /* + * noretry = 0 will cause kfd page fault tests fail + * for some ASICs, so set default to 1 for these ASICs. + */ + if (amdgpu_noretry == -1) + gmc->noretry = 1; + else + gmc->noretry = amdgpu_noretry; + break; + default: + break; + } } void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, @@ -1019,6 +1082,16 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev) case CHIP_RENOIR: adev->mman.keep_stolen_vga_memory = true; break; + case CHIP_POLARIS10: + case CHIP_POLARIS11: + case CHIP_POLARIS12: + /* MacBookPros with switchable graphics put VRAM at 0 when + * the iGPU is enabled which results in cursor issues if + * the cursor ends up at 0. Reserve vram at 0 in that case. + */ + if (adev->gmc.vram_start == 0) + adev->mman.keep_stolen_vga_memory = true; + break; default: adev->mman.keep_stolen_vga_memory = false; break; @@ -1315,18 +1388,18 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges, uint8_t *exp_ranges) { - struct amdgpu_gmc_memrange *ranges; + struct amdgpu_gmc_memrange ranges[AMDGPU_MAX_MEM_RANGES]; int range_cnt, ret, i, j; uint32_t nps_type; bool refresh; if (!mem_ranges || !exp_ranges) return -EINVAL; - + range_cnt = AMDGPU_MAX_MEM_RANGES; refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS); - ret = amdgpu_discovery_get_nps_info(adev, &nps_type, &ranges, - &range_cnt, refresh); + ret = amdgpu_discovery_get_nps_info(adev, &nps_type, ranges, &range_cnt, + refresh); if (ret) return ret; @@ -1387,8 +1460,6 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, if (!*exp_ranges) *exp_ranges = range_cnt; err: - kfree(ranges); - return ret; } @@ -1691,3 +1762,31 @@ int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev) return 0; } + +int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor) +{ + int ret = 0; + + if (adev->flags & AMD_IS_APU) + return amdgpu_atomfirmware_get_integrated_system_info(adev, + vram_width, vram_type, vram_vendor); + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 0, 0): + case IP_VERSION(12, 0, 1): + return amdgpu_atomfirmware_get_umc_info(adev, + vram_width, vram_type, vram_vendor); + case IP_VERSION(9, 5, 0): + case IP_VERSION(9, 4, 4): + case IP_VERSION(9, 4, 3): + ret = amdgpu_atomfirmware_get_umc_info(adev, + vram_width, vram_type, vram_vendor); + if (vram_width && !ret) + *vram_width *= hweight32(adev->aid_mask); + return ret; + default: + return amdgpu_atomfirmware_get_vram_info(adev, + vram_width, vram_type, vram_vendor); + } + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 727342689d4ba..32e73e8ba778c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -32,9 +32,11 @@ #include "amdgpu_xgmi.h" #include "amdgpu_ras.h" -/* VA hole for 48bit addresses on Vega10 */ -#define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL -#define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL +/* VA hole for 48bit and 57bit addresses */ +#define AMDGPU_GMC_HOLE_START (adev->vm_manager.max_level == 4 ?\ + 0x0100000000000000ULL : 0x0000800000000000ULL) +#define AMDGPU_GMC_HOLE_END (adev->vm_manager.max_level == 4 ?\ + 0xff00000000000000ULL : 0xffff800000000000ULL) /* * Hardware is programmed as if the hole doesn't exists with start and end @@ -43,7 +45,8 @@ * This mask is used to remove the upper 16bits of the VA and so come up with * the linear addr value. */ -#define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL +#define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.max_level == 4 ?\ + 0x01ffffffffffffffULL : 0x0000ffffffffffffULL) /* * Ring size as power of two for the log of recent faults. @@ -91,6 +94,10 @@ enum amdgpu_memory_partition { #define AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE 0x20 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_EXE 0x10 +#define AMDGPU_GMC121_FAULT_SOURCE_DATA_READ 0x400000 +#define AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE 0x200000 +#define AMDGPU_GMC121_FAULT_SOURCE_DATA_EXE 0x100000 + /* * GMC page fault information */ @@ -353,6 +360,7 @@ struct amdgpu_gmc { u64 MC_VM_MX_L1_TLB_CNTL; u64 noretry_flags; + u64 init_pte_flags; bool flush_tlb_needs_extra_type_0; bool flush_tlb_needs_extra_type_2; @@ -394,13 +402,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) * * @addr: address to extend */ -static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) -{ - if (addr >= AMDGPU_GMC_HOLE_START) - addr |= AMDGPU_GMC_HOLE_END; - - return addr; -} +#define amdgpu_gmc_sign_extend(addr) ((addr) >= AMDGPU_GMC_HOLE_START ?\ + ((addr) | AMDGPU_GMC_HOLE_END) : (addr)) bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev); int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); @@ -426,6 +429,12 @@ bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint16_t pasid, uint64_t timestamp); void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, uint16_t pasid); +int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry, + u64 addr, + u32 cam_index, + u32 node_id, + bool write_fault); int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); @@ -473,4 +482,6 @@ amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges); +int amdgpu_gmc_get_vram_info(struct amdgpu_device *adev, + int *vram_width, int *vram_type, int *vram_vendor); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 895c1e4c6747b..34a103289f5de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -26,6 +26,8 @@ #include "amdgpu.h" +#define GART_ENTRY_WITHOUT_BO_COLOR 1 + static inline struct amdgpu_gtt_mgr * to_gtt_mgr(struct ttm_resource_manager *man) { @@ -76,6 +78,7 @@ static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO, static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO, amdgpu_mem_info_gtt_used_show, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_gtt_mgr_attributes[] = { &dev_attr_mem_info_gtt_total.attr, &dev_attr_mem_info_gtt_used.attr, @@ -85,6 +88,7 @@ static struct attribute *amdgpu_gtt_mgr_attributes[] = { const struct attribute_group amdgpu_gtt_mgr_attr_group = { .attrs = amdgpu_gtt_mgr_attributes }; +#endif /** * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space @@ -180,6 +184,49 @@ static void amdgpu_gtt_mgr_del(struct ttm_resource_manager *man, kfree(node); } +/** + * amdgpu_gtt_mgr_alloc_entries - alloc GART entries without GTT bo + * + * @mgr: The GTT manager object + * @mm_node: The drm mm node to return the new allocation node information + * @num_pages: The number of pages for the new allocation + * @mode: The new allocation mode + * + * Helper to dynamic alloc GART entries to map memory not accociated with + * GTT BO, for example VRAM BO physical memory, remote physical memory. + */ +int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr, + struct drm_mm_node *mm_node, + u64 num_pages, + enum drm_mm_insert_mode mode) +{ + struct amdgpu_device *adev = container_of(mgr, typeof(*adev), mman.gtt_mgr); + int r; + + spin_lock(&mgr->lock); + r = drm_mm_insert_node_in_range(&mgr->mm, mm_node, num_pages, + 0, GART_ENTRY_WITHOUT_BO_COLOR, 0, + adev->gmc.gart_size >> PAGE_SHIFT, + mode); + spin_unlock(&mgr->lock); + return r; +} + +/** + * amdgpu_gtt_mgr_free_entries - free GART entries not accocaited with GTT bo + * + * @mgr: The GTT manager object + * @mm_node: The drm mm node to free + */ +void amdgpu_gtt_mgr_free_entries(struct amdgpu_gtt_mgr *mgr, + struct drm_mm_node *mm_node) +{ + spin_lock(&mgr->lock); + if (drm_mm_node_allocated(mm_node)) + drm_mm_remove_node(mm_node); + spin_unlock(&mgr->lock); +} + /** * amdgpu_gtt_mgr_recover - re-init gart * @@ -196,6 +243,9 @@ void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr) adev = container_of(mgr, typeof(*adev), mman.gtt_mgr); spin_lock(&mgr->lock); drm_mm_for_each_node(mm_node, &mgr->mm) { + if (mm_node->color == GART_ENTRY_WITHOUT_BO_COLOR) + continue; + node = container_of(mm_node, typeof(*node), mm_nodes[0]); amdgpu_ttm_recover_gart(node->base.bo); } @@ -276,19 +326,31 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) { struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; struct ttm_resource_manager *man = &mgr->manager; - uint64_t start, size; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif man->use_tt = true; man->func = &amdgpu_gtt_mgr_func; ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size); - start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; - start += amdgpu_vce_required_gart_pages(adev); - size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; - drm_mm_init(&mgr->mm, start, size); + drm_mm_init(&mgr->mm, 0, adev->gmc.gart_size >> PAGE_SHIFT); spin_lock_init(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_total\n"); + return ret; + } + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_used); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_used\n"); + return ret; + } +#endif + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); ttm_resource_manager_set_used(man, true); return 0; @@ -317,7 +379,10 @@ void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev) spin_lock(&mgr->lock); drm_mm_takedown(&mgr->mm); spin_unlock(&mgr->lock); - +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total); + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 90d26d820bac0..7364124a2afec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -51,8 +51,648 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_hmm.h" -#define MAX_WALK_BYTE (2UL << 30) +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +/** + * struct amdgpu_mn + * + * @adev: amdgpu device pointer + * @mm: process address space + * @mn: MMU notifier structure + * @type: type of MMU notifier + * @work: destruction work item + * @node: hash table node to find structure by adev and mn + * @lock: rw semaphore protecting the notifier nodes + * @objects: interval tree containing amdgpu_mn_nodes + * @read_lock: mutex for recursive locking of @lock + * @recursion: depth of recursion + * + * Data for each amdgpu device and process address space. + */ +struct amdgpu_mn { + /* constant after initialisation */ + struct amdgpu_device *adev; + struct mm_struct *mm; + struct mmu_notifier mn; + enum amdgpu_mn_type type; + + /* protected by adev->mn_lock */ + struct hlist_node node; + + /* objects protected by lock */ + struct rw_semaphore lock; + struct rb_root_cached objects; + struct mutex read_lock; + atomic_t recursion; +#if !defined(HAVE_MMU_NOTIFIER_PUT) + struct rcu_head rcu; +#endif +}; + +/** + * struct amdgpu_mn_node + * + * @it: interval node defining start-last of the affected address range + * @bos: list of all BOs in the affected address range + * + * Manages all BOs which are affected of a certain range of address space. + */ +struct amdgpu_mn_node { + struct interval_tree_node it; + struct list_head bos; +}; + +#ifdef HAVE_MMU_NOTIFIER_PUT +static void amdgpu_mn_free(struct mmu_notifier *mn) +{ + kfree(container_of(mn, struct amdgpu_mn, mn)); +} +#else +static void amdgpu_mn_free(struct rcu_head *rcu) +{ + kfree(container_of(rcu, struct amdgpu_mn, rcu)); +} +#endif + +/** + * amdgpu_mn_destroy - destroy the MMU notifier + * + * @amn: our notifier + * + * Destroy the notifier + */ +static void amdgpu_mn_destroy(struct amdgpu_mn *amn) +{ + struct amdgpu_device *adev = amn->adev; + struct amdgpu_mn_node *node, *next_node; + struct amdgpu_bo *bo, *next_bo; + + mutex_lock(&adev->mn_lock); + down_write(&amn->lock); + hash_del(&amn->node); + rbtree_postorder_for_each_entry_safe(node, next_node, + &amn->objects.rb_root, it.rb) { + list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { + bo->mn = NULL; + list_del_init(&bo->mn_list); + } + kfree(node); + } + + amn->objects = RB_ROOT_CACHED; + + up_write(&amn->lock); + +#ifdef HAVE_MMU_NOTIFIER_PUT + mmu_notifier_put(&amn->mn); +#else + mmu_notifier_unregister_no_release(&amn->mn, amn->mm); + mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); +#endif + + mutex_unlock(&adev->mn_lock); +} + +/** + * amdgpu_mn_release - callback to notify about mm destruction + * + * @mn: our notifier + * @mm: the mm this callback is about + * + * Destroy our notifier. + */ +static void amdgpu_mn_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + amdgpu_mn_destroy(amn); +} + + +/** + * amdgpu_mn_lock - take the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_lock(struct amdgpu_mn *mn) +{ + if (mn) + down_write(&mn->lock); +} + +/** + * amdgpu_mn_unlock - drop the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_unlock(struct amdgpu_mn *mn) +{ + if (mn) + up_write(&mn->lock); +} + +#if !defined(HAVE_5ARGS_INVALIDATE_RANGE_START) && !defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) +{ + /* FIXME: Need figure out one way to detect + * if we are in oom reaper context. + */ + mutex_lock(&amn->read_lock); + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); +} +#else +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) +{ + /* Non blockable occurs only in oom reaper context. + * In this case, process is going to be killed anyway. + * Let oom reaper fail at this stage. + */ + if (!blockable) + return -EAGAIN; + + mutex_lock(&amn->read_lock); + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); + + return 0; +} +#endif + +/** + * amdgpu_mn_read_unlock - drop the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn) +{ + if (atomic_dec_return(&amn->recursion) == 0) + up_read_non_owner(&amn->lock); +} + +/** + * amdgpu_mn_invalidate_node - unmap all BOs of a node + * + * @node: the node with the BOs to unmap + * @start: start of address range affected + * @end: end of address range affected + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, + unsigned long start, + unsigned long end) +{ + struct amdgpu_bo *bo; + long r; + unsigned long userptr; + + list_for_each_entry(bo, &node->bos, mn_list) { + + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end, &userptr)) + continue; + + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), + true, false, MAX_SCHEDULE_TIMEOUT); + if (r <= 0) + DRM_ERROR("(%ld) failed to wait for user bo\n", r); + + amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm); + } +} + +#if defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @range: mmu notifier context + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + /* TODO we should be able to split locking for interval tree and + * amdgpu_mn_invalidate_node + */ + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + amdgpu_mn_invalidate_node(node, range->start, end); + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + unsigned long userptr; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + range->start, + end, &userptr)) + amdgpu_amdkfd_evict_userptr(mem, range->mm); + } + } + + return 0; +} + +#else + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + amdgpu_mn_invalidate_node(node, start, end); + } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif +} + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long userptr; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + start, end, &userptr)) + amdgpu_amdkfd_evict_userptr(mem, mm); + } + } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif +} + +#endif + +/** + * amdgpu_mn_invalidate_range_end - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Release the lock again to allow new command submissions. + */ +static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, +#ifdef HAVE_2ARGS_INVALIDATE_RANGE_START + const struct mmu_notifier_range *range) +#else + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + amdgpu_mn_read_unlock(amn); +} + +static const struct mmu_notifier_ops amdgpu_mn_ops[] = { + [AMDGPU_MN_TYPE_GFX] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, + [AMDGPU_MN_TYPE_HSA] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, +}; + +/* Low bits of any reasonable mm pointer will be unused due to struct + * alignment. Use these bits to make a unique key from the mm pointer + * and notifier type. + */ +#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type)) + +/** + * amdgpu_mn_get - create notifier context + * + * @adev: amdgpu device pointer + * @type: type of MMU notifier context + * + * Creates a notifier context for current->mm. + */ +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + struct mm_struct *mm = current->mm; + struct amdgpu_mn *amn; + unsigned long key = AMDGPU_MN_KEY(mm, type); + int r; + + mutex_lock(&adev->mn_lock); + if (down_write_killable(&mm->mmap_sem)) { + mutex_unlock(&adev->mn_lock); + return ERR_PTR(-EINTR); + } + + hash_for_each_possible(adev->mn_hash, amn, node, key) + if (AMDGPU_MN_KEY(amn->mm, amn->type) == key) + goto release_locks; + + amn = kzalloc(sizeof(*amn), GFP_KERNEL); + if (!amn) { + amn = ERR_PTR(-ENOMEM); + goto release_locks; + } + + amn->adev = adev; + amn->mm = mm; + init_rwsem(&amn->lock); + amn->type = type; + amn->mn.ops = &amdgpu_mn_ops[type]; + amn->objects = RB_ROOT_CACHED; + mutex_init(&amn->read_lock); + atomic_set(&amn->recursion, 0); + + r = __mmu_notifier_register(&amn->mn, mm); + if (r) + goto free_amn; + + hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type)); + +release_locks: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + + return amn; + +free_amn: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + kfree(amn); + + return ERR_PTR(r); +} + +/** + * amdgpu_hmm_register - register a BO for notifier updates + * + * @bo: amdgpu buffer object + * @addr: userptr addr we should monitor + * + * Registers an MMU notifier for the given BO at the specified address. + * Returns 0 on success, -ERRNO if anything goes wrong. + */ +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) +{ + unsigned long end = addr + amdgpu_bo_size(bo) - 1; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + enum amdgpu_mn_type type = + bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX; + struct amdgpu_mn *amn; + struct amdgpu_mn_node *node = NULL, *new_node; + struct list_head bos; + struct interval_tree_node *it; + + amn = amdgpu_mn_get(adev, type); + if (IS_ERR(amn)) + return PTR_ERR(amn); + + new_node = kmalloc(sizeof(*new_node), GFP_KERNEL); + if (!new_node) + return -ENOMEM; + + INIT_LIST_HEAD(&bos); + + down_write(&amn->lock); + + while ((it = interval_tree_iter_first(&amn->objects, addr, end))) { + kfree(node); + node = container_of(it, struct amdgpu_mn_node, it); + interval_tree_remove(&node->it, &amn->objects); + addr = min(it->start, addr); + end = max(it->last, end); + list_splice(&node->bos, &bos); + } + + if (!node) + node = new_node; + else + kfree(new_node); + + bo->mn = amn; + + node->it.start = addr; + node->it.last = end; + INIT_LIST_HEAD(&node->bos); + list_splice(&bos, &node->bos); + list_add(&bo->mn_list, &node->bos); + + interval_tree_insert(&node->it, &amn->objects); + + up_write(&amn->lock); + + return 0; +} + +/** + * amdgpu_hmm_unregister - unregister a BO for notifier updates + * + * @bo: amdgpu buffer object + * + * Remove any registration of MMU notifier updates from the buffer object. + */ +void amdgpu_hmm_unregister(struct amdgpu_bo *bo) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_mn *amn; + struct list_head *head; + + mutex_lock(&adev->mn_lock); + + amn = bo->mn; + if (amn == NULL) { + mutex_unlock(&adev->mn_lock); + return; + } + + down_write(&amn->lock); + + /* save the next list entry for later */ + head = bo->mn_list.next; + + bo->mn = NULL; + list_del_init(&bo->mn_list); + + if (list_empty(head)) { + struct amdgpu_mn_node *node; + + node = container_of(head, struct amdgpu_mn_node, bos); + interval_tree_remove(&node->it, &amn->objects); + kfree(node); + } + + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); +} + +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ + +#define MAX_WALK_BYTE (2UL << 30) /** * amdgpu_hmm_invalidate_gfx - callback to notify about mm change * @@ -78,7 +718,7 @@ static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni, mmu_interval_set_seq(mni, cur_seq); - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); mutex_unlock(&adev->notifier_lock); if (r <= 0) @@ -165,6 +805,21 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) bo->notifier.mm = NULL; } +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif + int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, @@ -183,10 +838,20 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, } hmm_range->notifier = notifier; +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + hmm_range->flags = hmm_range_flags; + hmm_range->values = hmm_range_values; + hmm_range->pfn_shift = PAGE_SHIFT; + hmm_range->default_flags = hmm_range_flags[HMM_PFN_VALID]; + if (!readonly) + hmm_range->default_flags |= hmm_range->flags[HMM_PFN_WRITE]; + hmm_range->pfns = (uint64_t *)pfns; +#else hmm_range->default_flags = HMM_PFN_REQ_FAULT; if (!readonly) hmm_range->default_flags |= HMM_PFN_REQ_WRITE; hmm_range->hmm_pfns = pfns; +#endif hmm_range->start = start; end = start + npages * PAGE_SIZE; hmm_range->dev_private_owner = owner; @@ -202,8 +867,16 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, retry: hmm_range->notifier_seq = mmu_interval_read_begin(notifier); r = hmm_range_fault(hmm_range); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if (unlikely(r <= 0)) { +#else if (unlikely(r)) { +#endif +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout)) +#else if (r == -EBUSY && !time_after(jiffies, timeout)) +#endif goto retry; goto out_free_pfns; } @@ -291,3 +964,4 @@ void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) amdgpu_bo_unref(&range->bo); kfree(range); } +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 140bc9cd57b42..8df46f967cd09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -24,6 +24,41 @@ #ifndef __AMDGPU_MN_H__ #define __AMDGPU_MN_H__ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#include +/* + * MMU Notifier + */ +struct amdgpu_mn; + +enum amdgpu_mn_type { + AMDGPU_MN_TYPE_GFX, + AMDGPU_MN_TYPE_HSA, +}; + +#if defined(CONFIG_MMU_NOTIFIER) +void amdgpu_mn_lock(struct amdgpu_mn *mn); +void amdgpu_mn_unlock(struct amdgpu_mn *mn); +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type); +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_hmm_unregister(struct amdgpu_bo *bo); +#else /* !CONFIG_MMU_NOTIFIER */ +static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} +static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} +static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + return NULL; +} +static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) +{ + return -ENODEV; +} +static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} +#endif /* CONFIG_MMU_NOTIFIER */ +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include #include #include @@ -31,6 +66,22 @@ #include #include +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +extern const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX]; +extern const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX]; + +static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) +{ + struct hmm_range hmm_range = { + .flags = hmm_range_flags, + .values = hmm_range_values, + .pfn_shift = PAGE_SHIFT, + }; + + return hmm_device_entry_to_page(&hmm_range, hmm_pfn); +} +#endif struct amdgpu_hmm_range { struct hmm_range hmm_range; struct amdgpu_bo *bo; @@ -69,5 +120,6 @@ static inline struct amdgpu_hmm_range *amdgpu_hmm_range_alloc(struct amdgpu_bo * static inline void amdgpu_hmm_range_free(struct amdgpu_hmm_range *range) {} #endif +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 44f230d67da24..3099379af0b29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -129,6 +129,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, struct amdgpu_ib *ib = &ibs[0]; struct dma_fence *tmp = NULL; struct amdgpu_fence *af; + struct amdgpu_fence *vm_af; bool need_ctx_switch; struct amdgpu_vm *vm; uint64_t fence_ctx; @@ -141,6 +142,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, unsigned int cond_exec; unsigned int i; int r = 0; + unsigned extra_nop = 0; if (num_ibs == 0) return -EINVAL; @@ -196,6 +198,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, alloc_size = ring->funcs->emit_frame_size + num_ibs * ring->funcs->emit_ib_size; + if (job && !job->vm_needs_flush && ring->funcs->type == AMDGPU_RING_TYPE_GFX) { + extra_nop = 128; + alloc_size += extra_nop; + } + r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); @@ -215,25 +222,29 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, dma_fence_put(tmp); } - if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) - ring->funcs->emit_mem_sync(ring); + if (job) { + amdgpu_ring_insert_nop(ring, extra_nop); /* prevent CE go too fast than DE */ + vm_af = job->hw_vm_fence; + /* VM sequence */ + vm_af->ib_wptr = ring->wptr; + amdgpu_vm_flush(ring, job, need_pipe_sync); + vm_af->ib_dw_size = + amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr); + } - if (ring->funcs->emit_wave_limit && - ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) - ring->funcs->emit_wave_limit(ring, true); + /* IB sequence */ + af->ib_wptr = ring->wptr; + amdgpu_ring_ib_begin(ring); if (ring->funcs->insert_start) ring->funcs->insert_start(ring); - if (job) { - r = amdgpu_vm_flush(ring, job, need_pipe_sync); - if (r) { - amdgpu_ring_undo(ring); - return r; - } - } + if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync) + ring->funcs->emit_mem_sync(ring); - amdgpu_ring_ib_begin(ring); + if (ring->funcs->emit_wave_limit && + ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) + ring->funcs->emit_wave_limit(ring, true); if (ring->funcs->emit_gfx_shadow && adev->gfx.cp_gfx_shadow) amdgpu_ring_emit_gfx_shadow(ring, shadow_va, csa_va, gds_va, @@ -243,6 +254,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, cond_exec = amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); + /* Skip the IB for guilty contexts */ + af->skip_ib_dw_start_offset = + amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); amdgpu_device_flush_hdp(adev, ring); if (need_ctx_switch) @@ -281,6 +295,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_emit_frame_cntl(ring, false, secure); amdgpu_device_invalidate_hdp(adev, ring); + /* Skip the IB for guilty contexts */ + af->skip_ib_dw_end_offset = + amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; @@ -297,14 +314,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); } - r = amdgpu_fence_emit(ring, af, fence_flags); - if (r) { - dev_err(adev->dev, "failed to emit fence (%d)\n", r); - if (job && job->vmid) - amdgpu_vmid_reset(adev, ring->vm_hub, job->vmid); - amdgpu_ring_undo(ring); - goto free_fence; - } + amdgpu_fence_emit(ring, af, fence_flags); *f = &af->base; /* get a ref for the job */ if (job) @@ -323,15 +333,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, ring->hw_prio == AMDGPU_GFX_PIPE_PRIO_HIGH) ring->funcs->emit_wave_limit(ring, false); - /* Save the wptr associated with this fence. - * This must be last for resets to work properly - * as we need to save the wptr associated with this - * fence so we know what rings contents to backup - * after we reset the queue. - */ - amdgpu_fence_save_wptr(af); - amdgpu_ring_ib_end(ring); + + af->ib_dw_size = amdgpu_ring_get_dw_distance(ring, af->ib_wptr, ring->wptr); + amdgpu_ring_commit(ring); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 9cab36322c165..684f40fce73ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -22,7 +22,7 @@ */ #include "amdgpu_ids.h" -#include +#include #include @@ -35,10 +35,13 @@ * PASIDs are global address space identifiers that can be shared * between the GPU, an IOMMU and the driver. VMs on different devices * may use the same PASID if they share the same address - * space. Therefore PASIDs are allocated using a global IDA. VMs are - * looked up from the PASID per amdgpu_device. + * space. Therefore PASIDs are allocated using IDR cyclic allocator + * (similar to kernel PID allocation) which naturally delays reuse. + * VMs are looked up from the PASID per amdgpu_device. */ -static DEFINE_IDA(amdgpu_pasid_ida); + +static DEFINE_XARRAY_FLAGS(amdgpu_pasid_xa, XA_FLAGS_LOCK_IRQ | XA_FLAGS_ALLOC1); +static u32 amdgpu_pasid_xa_next; /* Helper to free pasid from a fence callback */ struct amdgpu_pasid_cb { @@ -50,8 +53,8 @@ struct amdgpu_pasid_cb { * amdgpu_pasid_alloc - Allocate a PASID * @bits: Maximum width of the PASID in bits, must be at least 1 * - * Allocates a PASID of the given width while keeping smaller PASIDs - * available if possible. + * Uses kernel's IDR cyclic allocator (same as PID allocation). + * Allocates sequentially with automatic wrap-around. * * Returns a positive integer on success. Returns %-EINVAL if bits==0. * Returns %-ENOSPC if no PASID was available. Returns %-ENOMEM on @@ -59,29 +62,37 @@ struct amdgpu_pasid_cb { */ int amdgpu_pasid_alloc(unsigned int bits) { - int pasid = -EINVAL; + u32 pasid; + int r; - for (bits = min(bits, 31U); bits > 0; bits--) { - pasid = ida_alloc_range(&amdgpu_pasid_ida, 1U << (bits - 1), - (1U << bits) - 1, GFP_KERNEL); - if (pasid != -ENOSPC) - break; - } + if (bits == 0) + return -EINVAL; - if (pasid >= 0) - trace_amdgpu_pasid_allocated(pasid); + r = xa_alloc_cyclic_irq(&amdgpu_pasid_xa, &pasid, xa_mk_value(0), + XA_LIMIT(1, (1U << bits) - 1), + &amdgpu_pasid_xa_next, GFP_KERNEL); + if (r < 0) + return r; + trace_amdgpu_pasid_allocated(pasid); return pasid; } /** * amdgpu_pasid_free - Free a PASID * @pasid: PASID to free + * + * Called in IRQ context. */ void amdgpu_pasid_free(u32 pasid) { + unsigned long flags; + trace_amdgpu_pasid_freed(pasid); - ida_free(&amdgpu_pasid_ida, pasid); + + xa_lock_irqsave(&amdgpu_pasid_xa, flags); + __xa_erase(&amdgpu_pasid_xa, pasid); + xa_unlock_irqrestore(&amdgpu_pasid_xa, flags); } static void amdgpu_pasid_free_cb(struct dma_fence *fence, @@ -616,3 +627,13 @@ void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev) } } } + +/** + * amdgpu_pasid_mgr_cleanup - cleanup PASID manager + * + * Cleanup the IDR allocator. + */ +void amdgpu_pasid_mgr_cleanup(void) +{ + xa_destroy(&amdgpu_pasid_xa); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h index b3649cd3af569..a57919478d3bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h @@ -74,6 +74,7 @@ int amdgpu_pasid_alloc(unsigned int bits); void amdgpu_pasid_free(u32 pasid); void amdgpu_pasid_free_delayed(struct dma_resv *resv, u32 pasid); +void amdgpu_pasid_mgr_cleanup(void); bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, struct amdgpu_vmid *id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h index 484e936812e45..9c56be725ff3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h @@ -36,6 +36,10 @@ struct amdgpu_imu_funcs { int (*start_imu)(struct amdgpu_device *adev); void (*program_rlc_ram)(struct amdgpu_device *adev); int (*wait_for_reset_status)(struct amdgpu_device *adev); + int (*switch_compute_partition)(struct amdgpu_device *adev, + int num_xccs_per_xcp, + int compute_partition_mode); + void (*init_mcm_addr_lut)(struct amdgpu_device *adev); }; struct imu_rlc_ram_golden { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c index 99e1cf4fc955e..6aa54156bbc97 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.c @@ -94,3 +94,318 @@ void amdgpu_ip_map_init(struct amdgpu_device *adev) adev->ip_map.logical_to_dev_inst = amdgpu_logical_to_dev_inst; adev->ip_map.logical_to_dev_mask = amdgpu_logical_to_dev_mask; } + +int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block) +{ + int r; + + if (ip_block->version->funcs->suspend) { + r = ip_block->version->funcs->suspend(ip_block); + if (r) { + dev_err(ip_block->adev->dev, + "suspend of IP block <%s> failed %d\n", + ip_block->version->funcs->name, r); + return r; + } + } + + ip_block->status.hw = false; + return 0; +} + +int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block) +{ + int r; + + if (ip_block->version->funcs->resume) { + r = ip_block->version->funcs->resume(ip_block); + if (r) { + dev_err(ip_block->adev->dev, + "resume of IP block <%s> failed %d\n", + ip_block->version->funcs->name, r); + return r; + } + } + + ip_block->status.hw = true; + return 0; +} + +/** + * amdgpu_device_ip_get_ip_block - get a hw IP pointer + * + * @adev: amdgpu_device pointer + * @type: Type of hardware IP (SMU, GFX, UVD, etc.) + * + * Returns a pointer to the hardware IP block structure + * if it exists for the asic, otherwise NULL. + */ +struct amdgpu_ip_block * +amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, + enum amd_ip_block_type type) +{ + int i; + + for (i = 0; i < adev->num_ip_blocks; i++) + if (adev->ip_blocks[i].version->type == type) + return &adev->ip_blocks[i]; + + return NULL; +} + +/** + * amdgpu_device_ip_block_version_cmp + * + * @adev: amdgpu_device pointer + * @type: enum amd_ip_block_type + * @major: major version + * @minor: minor version + * + * return 0 if equal or greater + * return 1 if smaller or the ip_block doesn't exist + */ +int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, + enum amd_ip_block_type type, u32 major, + u32 minor) +{ + struct amdgpu_ip_block *ip_block = + amdgpu_device_ip_get_ip_block(adev, type); + + if (ip_block && ((ip_block->version->major > major) || + ((ip_block->version->major == major) && + (ip_block->version->minor >= minor)))) + return 0; + + return 1; +} + +static const char *const ip_block_names[] = { + [AMD_IP_BLOCK_TYPE_COMMON] = "common", + [AMD_IP_BLOCK_TYPE_GMC] = "gmc", + [AMD_IP_BLOCK_TYPE_IH] = "ih", + [AMD_IP_BLOCK_TYPE_SMC] = "smu", + [AMD_IP_BLOCK_TYPE_PSP] = "psp", + [AMD_IP_BLOCK_TYPE_DCE] = "dce", + [AMD_IP_BLOCK_TYPE_GFX] = "gfx", + [AMD_IP_BLOCK_TYPE_SDMA] = "sdma", + [AMD_IP_BLOCK_TYPE_UVD] = "uvd", + [AMD_IP_BLOCK_TYPE_VCE] = "vce", + [AMD_IP_BLOCK_TYPE_ACP] = "acp", + [AMD_IP_BLOCK_TYPE_VCN] = "vcn", + [AMD_IP_BLOCK_TYPE_MES] = "mes", + [AMD_IP_BLOCK_TYPE_JPEG] = "jpeg", + [AMD_IP_BLOCK_TYPE_VPE] = "vpe", + [AMD_IP_BLOCK_TYPE_UMSCH_MM] = "umsch_mm", + [AMD_IP_BLOCK_TYPE_ISP] = "isp", + [AMD_IP_BLOCK_TYPE_RAS] = "ras", +}; + +static const char *ip_block_name(struct amdgpu_device *adev, + enum amd_ip_block_type type) +{ + int idx = (int)type; + + return idx < ARRAY_SIZE(ip_block_names) ? ip_block_names[idx] : + "unknown"; +} + +/** + * amdgpu_device_ip_block_add + * + * @adev: amdgpu_device pointer + * @ip_block_version: pointer to the IP to add + * + * Adds the IP block driver information to the collection of IPs + * on the asic. + */ +int amdgpu_device_ip_block_add( + struct amdgpu_device *adev, + const struct amdgpu_ip_block_version *ip_block_version) +{ + if (!ip_block_version) + return -EINVAL; + + switch (ip_block_version->type) { + case AMD_IP_BLOCK_TYPE_VCN: + if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) + return 0; + break; + case AMD_IP_BLOCK_TYPE_JPEG: + if (adev->harvest_ip_mask & AMD_HARVEST_IP_JPEG_MASK) + return 0; + break; + default: + break; + } + + dev_info(adev->dev, "detected ip block number %d <%s_v%d_%d_%d> (%s)\n", + adev->num_ip_blocks, + ip_block_name(adev, ip_block_version->type), + ip_block_version->major, ip_block_version->minor, + ip_block_version->rev, ip_block_version->funcs->name); + + adev->ip_blocks[adev->num_ip_blocks].adev = adev; + + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; + + return 0; +} + +/** + * amdgpu_device_ip_set_clockgating_state - set the CG state + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * @state: clockgating state (gate or ungate) + * + * Sets the requested clockgating state for all instances of + * the hardware IP specified. + * Returns the error code from the last instance. + */ +int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state) +{ + int i, r = 0; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + if (adev->ip_blocks[i].version->type != block_type) + continue; + if (!adev->ip_blocks[i].version->funcs->set_clockgating_state) + continue; + r = adev->ip_blocks[i].version->funcs->set_clockgating_state( + &adev->ip_blocks[i], state); + if (r) + dev_err(adev->dev, + "set_clockgating_state of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + } + return r; +} + +/** + * amdgpu_device_ip_set_powergating_state - set the PG state + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * @state: powergating state (gate or ungate) + * + * Sets the requested powergating state for all instances of + * the hardware IP specified. + * Returns the error code from the last instance. + */ +int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_powergating_state state) +{ + int i, r = 0; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + if (adev->ip_blocks[i].version->type != block_type) + continue; + if (!adev->ip_blocks[i].version->funcs->set_powergating_state) + continue; + r = adev->ip_blocks[i].version->funcs->set_powergating_state( + &adev->ip_blocks[i], state); + if (r) + dev_err(adev->dev, + "set_powergating_state of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + } + return r; +} + +/** + * amdgpu_device_ip_get_clockgating_state - get the CG state + * + * @adev: amdgpu_device pointer + * @flags: clockgating feature flags + * + * Walks the list of IPs on the device and updates the clockgating + * flags for each IP. + * Updates @flags with the feature flags for each hardware IP where + * clockgating is enabled. + */ +void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, + u64 *flags) +{ + int i; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid) + continue; + if (adev->ip_blocks[i].version->funcs->get_clockgating_state) + adev->ip_blocks[i].version->funcs->get_clockgating_state( + &adev->ip_blocks[i], flags); + } +} + +/** + * amdgpu_device_ip_wait_for_idle - wait for idle + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * + * Waits for the request hardware IP to be idle. + * Returns 0 for success or a negative error code on failure. + */ +int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) +{ + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, block_type); + if (!ip_block || !ip_block->status.valid) + return 0; + + if (ip_block->version->funcs->wait_for_idle) + return ip_block->version->funcs->wait_for_idle(ip_block); + + return 0; +} + +/** + * amdgpu_device_ip_is_hw - is the hardware IP enabled + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * + * Check if the hardware IP is enable or not. + * Returns true if it the IP is enable, false if not. + */ +bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) +{ + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, block_type); + if (ip_block) + return ip_block->status.hw; + + return false; +} + +/** + * amdgpu_device_ip_is_valid - is the hardware IP valid + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * + * Check if the hardware IP is valid or not. + * Returns true if it the IP is valid, false if not. + */ +bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) +{ + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, block_type); + if (ip_block) + return ip_block->status.valid; + + return false; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h index 2490fd322aece..1d0df6d93957e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ip.h @@ -24,6 +24,131 @@ #ifndef __AMDGPU_IP_H__ #define __AMDGPU_IP_H__ +#include "amd_shared.h" + +struct amdgpu_device; + +/* Define the HW IP blocks will be used in driver , add more if necessary */ +enum amd_hw_ip_block_type { + GC_HWIP = 1, + HDP_HWIP, + SDMA0_HWIP, + SDMA1_HWIP, + SDMA2_HWIP, + SDMA3_HWIP, + SDMA4_HWIP, + SDMA5_HWIP, + SDMA6_HWIP, + SDMA7_HWIP, + LSDMA_HWIP, + MMHUB_HWIP, + ATHUB_HWIP, + NBIO_HWIP, + MP0_HWIP, + MP1_HWIP, + UVD_HWIP, + VCN_HWIP = UVD_HWIP, + JPEG_HWIP = VCN_HWIP, + VCN1_HWIP, + VCE_HWIP, + VPE_HWIP, + DF_HWIP, + DCE_HWIP, + OSSSYS_HWIP, + SMUIO_HWIP, + PWR_HWIP, + NBIF_HWIP, + THM_HWIP, + CLK_HWIP, + UMC_HWIP, + RSMU_HWIP, + XGMI_HWIP, + DCI_HWIP, + PCIE_HWIP, + ISP_HWIP, + ATU_HWIP, + AIGC_HWIP, + MAX_HWIP +}; + +#define HWIP_MAX_INSTANCE 48 + +#define HW_ID_MAX 300 +#define IP_VERSION_FULL(mj, mn, rv, var, srev) \ + (((mj) << 24) | ((mn) << 16) | ((rv) << 8) | ((var) << 4) | (srev)) +#define IP_VERSION(mj, mn, rv) IP_VERSION_FULL(mj, mn, rv, 0, 0) +#define IP_VERSION_MAJ(ver) ((ver) >> 24) +#define IP_VERSION_MIN(ver) (((ver) >> 16) & 0xFF) +#define IP_VERSION_REV(ver) (((ver) >> 8) & 0xFF) +#define IP_VERSION_VARIANT(ver) (((ver) >> 4) & 0xF) +#define IP_VERSION_SUBREV(ver) ((ver) & 0xF) +#define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) + +struct amdgpu_ip_map_info { + /* Map of logical to actual dev instances/mask */ + uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; + int8_t (*logical_to_dev_inst)(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int8_t inst); + uint32_t (*logical_to_dev_mask)(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + uint32_t mask); +}; + +#define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM + +struct amdgpu_ip_block_status { + bool valid; + bool sw; + bool hw; + bool late_initialized; + bool hang; +}; + +struct amdgpu_ip_block_version { + const enum amd_ip_block_type type; + const u32 major; + const u32 minor; + const u32 rev; + const struct amd_ip_funcs *funcs; +}; + +struct amdgpu_ip_block { + struct amdgpu_ip_block_status status; + const struct amdgpu_ip_block_version *version; + struct amdgpu_device *adev; +}; + void amdgpu_ip_map_init(struct amdgpu_device *adev); +int amdgpu_ip_block_suspend(struct amdgpu_ip_block *ip_block); +int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); + +struct amdgpu_ip_block * +amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, + enum amd_ip_block_type type); + +int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, + enum amd_ip_block_type type, u32 major, + u32 minor); + +int amdgpu_device_ip_block_add( + struct amdgpu_device *adev, + const struct amdgpu_ip_block_version *ip_block_version); + +int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_clockgating_state state); +int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, + enum amd_ip_block_type block_type, + enum amd_powergating_state state); +void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, + u64 *flags); +int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); +bool amdgpu_device_ip_is_hw(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); +bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); + #endif /* __AMDGPU_IP_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 8112ffc85995e..3bd40fd9c49a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -99,6 +99,41 @@ const char *soc15_ih_clientid_name[] = { "MP1" }; +const char *soc_v1_0_ih_clientid_name[] = { + "IH", + "Reserved", + "ATHUB", + "BIF", + "Reserved", + "Reserved", + "Reserved", + "RLC", + "Reserved", + "Reserved", + "GFX", + "IMU", + "Reserved", + "Reserved", + "VCN1 or UVD1", + "THM", + "VCN or UVD", + "Reserved", + "VMC", + "Reserved", + "GRBM_CP", + "GC_AID", + "ROM_SMUIO", + "DF", + "Reserved", + "PWR", + "LSDMA", + "GC_UTCL2", + "nHT", + "Reserved", + "MP0", + "MP1", +}; + const int node_id_to_phys_map[NODEID_MAX] = { [AID0_NODEID] = 0, [XCD0_NODEID] = 0, @@ -162,7 +197,10 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev) * Returns: * result of handling the IRQ, as defined by &irqreturn_t */ -static irqreturn_t amdgpu_irq_handler(int irq, void *arg) +#ifndef CONFIG_DRM_LEGACY +static +#endif +irqreturn_t amdgpu_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; struct amdgpu_device *adev = drm_to_adev(dev); @@ -316,7 +354,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev) adev->irq.irq = irq; adev_to_drm(adev)->max_vblank_count = 0x00ffffff; - dev_dbg(adev->dev, "amdgpu: irq initialized.\n"); + dev_dbg(adev->dev, "irq initialized.\n"); return 0; free_vectors: @@ -471,7 +509,6 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { generic_handle_domain_irq(adev->irq.domain, src_id); - } else if (!adev->irq.client[client_id].sources) { dev_dbg(adev->dev, "Unregistered interrupt client_id: %d src_id: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 9f0417456abda..3633019100867 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -26,6 +26,7 @@ #include #include "soc15_ih_clientid.h" +#include "soc_v1_0_ih_clientid.h" #include "amdgpu_ih.h" #define AMDGPU_MAX_IRQ_SRC_ID 0x100 @@ -121,6 +122,9 @@ enum interrupt_node_id_per_aid { extern const int node_id_to_phys_map[NODEID_MAX]; void amdgpu_irq_disable_all(struct amdgpu_device *adev); +#ifdef CONFIG_DRM_LEGACY +irqreturn_t amdgpu_irq_handler(int irq, void *arg); +#endif int amdgpu_irq_init(struct amdgpu_device *adev); void amdgpu_irq_fini_sw(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 7ccb724b2488d..55172c2dcc355 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -135,8 +135,12 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) ring->funcs->reset) { dev_err(adev->dev, "Starting %s ring reset\n", s_job->sched->name); + /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ + drm_sched_wqueue_stop(&ring->sched); r = amdgpu_ring_reset(ring, job->vmid, job->hw_fence); if (!r) { + /* Start the scheduler again */ + drm_sched_wqueue_start(&ring->sched); atomic_inc(&ring->adev->gpu_reset_counter); dev_err(adev->dev, "Ring %s reset succeeded\n", ring->sched.name); @@ -147,7 +151,8 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) dev_err(adev->dev, "Ring %s reset failed\n", ring->sched.name); } - dma_fence_set_error(&s_job->s_fence->finished, -ETIME); + if (dma_fence_get_status(&s_job->s_fence->finished) == 0) + dma_fence_set_error(&s_job->s_fence->finished, -ETIME); if (amdgpu_device_should_recover_gpu(ring->adev)) { struct amdgpu_reset_context reset_context; @@ -176,7 +181,8 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) exit: amdgpu_vm_put_task_info(ti); drm_dev_exit(idx); - return DRM_GPU_SCHED_STAT_RESET; + /* This is needed to add the job back to the pending list */ + return DRM_GPU_SCHED_STAT_NO_HANG; } int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h index 7abf069d17d42..56a88e14a0448 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h @@ -59,6 +59,10 @@ enum amdgpu_ib_pool_type; #define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB (18446744073709551604ULL) #define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP (18446744073709551603ULL) #define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST (18446744073709551602ULL) +#define AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST (18446744073709551601ULL) +#define AMDGPU_KERNEL_JOB_ID_SDMA_RING_TEST (18446744073709551600ULL) +#define AMDGPU_KERNEL_JOB_ID_VPE_RING_TEST (18446744073709551599ULL) +#define AMDGPU_KERNEL_JOB_ID_RUN_SHADER (18446744073709551598ULL) struct amdgpu_job { struct drm_sched_job base; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index 63ee6ba6a9316..56128f6930a4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -402,9 +402,15 @@ static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, amdgpu_debugfs_jpeg_sched_mask_get, amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, + amdgpu_debugfs_jpeg_sched_mask_get, + amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index f65edd80cabfa..4a0fda4a660dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -83,7 +83,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); - if (adev == NULL) + if (adev == NULL || !adev->num_ip_blocks) return; amdgpu_unregister_gpu_instance(adev); @@ -92,7 +92,7 @@ void amdgpu_driver_unload_kms(struct drm_device *dev) return; if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_UNLOAD)) - DRM_WARN("smart shift update failed\n"); + drm_warn(dev, "smart shift update failed\n"); amdgpu_acpi_fini(adev); amdgpu_device_fini_hw(adev); @@ -105,7 +105,7 @@ void amdgpu_register_gpu_instance(struct amdgpu_device *adev) mutex_lock(&mgpu_info.mutex); if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { - DRM_ERROR("Cannot register more gpu instance\n"); + drm_err(adev_to_drm(adev), "Cannot register more gpu instance\n"); mutex_unlock(&mgpu_info.mutex); return; } @@ -162,7 +162,7 @@ int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) dev_dbg(dev->dev, "Error during ACPI methods call\n"); if (amdgpu_acpi_smart_shift_update(adev, AMDGPU_SS_DRV_LOAD)) - DRM_WARN("smart shift update failed\n"); + drm_warn(dev, "smart shift update failed\n"); out: if (r) @@ -394,6 +394,42 @@ static int amdgpu_userq_metadata_info_gfx(struct amdgpu_device *adev, return ret; } +static int amdgpu_userq_metadata_info_compute(struct amdgpu_device *adev, + struct drm_amdgpu_info *info, + struct drm_amdgpu_info_uq_metadata_compute *meta) +{ + int ret = -EOPNOTSUPP; + + if (adev->gfx.funcs->get_gfx_shadow_info) { + struct amdgpu_gfx_shadow_info shadow = {}; + + adev->gfx.funcs->get_gfx_shadow_info(adev, &shadow, true); + meta->eop_size = shadow.eop_size; + meta->eop_alignment = shadow.eop_alignment; + ret = 0; + } + + return ret; +} + +static int amdgpu_userq_metadata_info_sdma(struct amdgpu_device *adev, + struct drm_amdgpu_info *info, + struct drm_amdgpu_info_uq_metadata_sdma *meta) +{ + int ret = -EOPNOTSUPP; + + if (adev->sdma.get_csa_info) { + struct amdgpu_sdma_csa_info csa = {}; + + adev->sdma.get_csa_info(adev, &csa); + meta->csa_size = csa.size; + meta->csa_alignment = csa.alignment; + ret = 0; + } + + return ret; +} + static int amdgpu_hw_ip_info(struct amdgpu_device *adev, struct drm_amdgpu_info *info, struct drm_amdgpu_info_hw_ip *result) @@ -635,6 +671,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; switch (info->query) { + case AMDGPU_INFO_VIRTUAL_RANGE: { + struct drm_amdgpu_virtual_range range_info; + + switch (info->virtual_range.aperture) { + case AMDGPU_SUA_APERTURE_PRIVATE: + range_info.start = adev->gmc.private_aperture_start; + range_info.end = adev->gmc.private_aperture_end; + break; + case AMDGPU_SUA_APERTURE_SHARED: + range_info.start = adev->gmc.shared_aperture_start; + range_info.end = adev->gmc.shared_aperture_end; + break; + default: + return -EINVAL; + } + return copy_to_user(out, &range_info, + min((size_t)size, sizeof(range_info))) ? -EFAULT : 0; + } case AMDGPU_INFO_ACCEL_WORKING: ui32 = adev->accel_working; return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; @@ -1132,6 +1186,21 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; } } + case AMDGPU_INFO_CAPABILITY: { + struct drm_amdgpu_capability cap; + + memset(&cap, 0, sizeof(cap)); + if (amdgpu_no_evict) + cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + + if (amdgpu_direct_gma_size) { + cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; + cap.direct_gma_size = amdgpu_direct_gma_size; + } + + return copy_to_user(out, &cap, + min((size_t)size, sizeof(cap))) ? -EFAULT : 0; + } case AMDGPU_INFO_SENSOR: { if (!adev->pm.dpm_enabled) return -ENOENT; @@ -1337,6 +1406,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } + case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1348,15 +1418,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); +#endif gpuvm_fault.addr = vm->fault_info.addr; gpuvm_fault.status = vm->fault_info.status; gpuvm_fault.vmhub = vm->fault_info.vmhub; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } + case AMDGPU_INFO_UQ_FW_AREAS: { struct drm_amdgpu_info_uq_metadata meta_info = {}; @@ -1366,6 +1445,22 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (ret) return ret; + ret = copy_to_user(out, &meta_info, + min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; + return 0; + case AMDGPU_HW_IP_COMPUTE: + ret = amdgpu_userq_metadata_info_compute(adev, info, &meta_info.compute); + if (ret) + return ret; + + ret = copy_to_user(out, &meta_info, + min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; + return 0; + case AMDGPU_HW_IP_DMA: + ret = amdgpu_userq_metadata_info_sdma(adev, info, &meta_info.sdma); + if (ret) + return ret; + ret = copy_to_user(out, &meta_info, min((size_t)size, sizeof(meta_info))) ? -EFAULT : 0; return 0; @@ -1393,6 +1488,7 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) { struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv; + struct drm_exec exec; int r, pasid; /* Ensure IB tests are run on ring */ @@ -1432,7 +1528,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) if (r) goto error_pasid; + drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); + drm_exec_until_all_locked(&exec) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &exec, 0); + drm_exec_retry_on_contention(&exec); + if (unlikely(r)) + goto error_vm; + } + fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); + drm_exec_fini(&exec); if (!fpriv->prt_va) { r = -ENOMEM; goto error_vm; @@ -1453,15 +1558,16 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) mutex_init(&fpriv->bo_list_lock); idr_init_base(&fpriv->bo_list_handles, 1); + spin_lock_init(&fpriv->sem_handles_lock); + idr_init(&fpriv->sem_handles); r = amdgpu_userq_mgr_init(&fpriv->userq_mgr, file_priv, adev); if (r) - DRM_WARN("Can't setup usermode queues, use legacy workload submission only\n"); - - r = amdgpu_eviction_fence_init(&fpriv->evf_mgr); - if (r) - goto error_vm; + drm_warn(adev_to_drm(adev), + "Failed to init usermode queue manager (%d), use legacy workload submission only\n", + r); + amdgpu_evf_mgr_init(&fpriv->evf_mgr); amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); file_priv->driver_priv = fpriv; @@ -1497,6 +1603,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_bo_list *list; + struct amdgpu_sem *sem; struct amdgpu_bo *pd; u32 pasid; int handle; @@ -1532,7 +1639,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, amdgpu_vm_fini(adev, &fpriv->vm); if (pasid) - amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); + amdgpu_pasid_free_delayed(amdkcl_ttm_resvp(&pd->tbo), pasid); amdgpu_bo_unref(&pd); idr_for_each_entry(&fpriv->bo_list_handles, list, handle) @@ -1541,19 +1648,26 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, idr_destroy(&fpriv->bo_list_handles); mutex_destroy(&fpriv->bo_list_lock); + idr_for_each_entry(&fpriv->sem_handles, sem, handle) + amdgpu_sem_destroy(fpriv, handle); + idr_destroy(&fpriv->sem_handles); + kfree(fpriv); file_priv->driver_priv = NULL; pm_runtime_put_autosuspend(dev->dev); } - void amdgpu_driver_release_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); amdgpu_device_fini_sw(adev); pci_set_drvdata(adev->pdev, NULL); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(dev); + kfree(adev); +#endif } /* @@ -1570,7 +1684,7 @@ void amdgpu_driver_release_kms(struct drm_device *dev) u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int vpos, hpos, stat; u32 count; @@ -1638,7 +1752,7 @@ u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); @@ -1655,7 +1769,7 @@ int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 9c182ce501af4..0d4c77c1b4b5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -88,25 +88,46 @@ static void amdgpu_mes_doorbell_free(struct amdgpu_device *adev) bitmap_free(adev->mes.doorbell_bitmap); } +static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe, + u32 num_hqd_per_pipe, + u32 num_reserved_hqd) +{ + if (num_pipe == 0) + return 0; + + u32 total_hqd_mask = (u32)((1ULL << num_hqd_per_pipe) - 1); + u32 reserved_hqd_mask = (u32)((1ULL << DIV_ROUND_UP(num_reserved_hqd, num_pipe)) - 1); + + return (total_hqd_mask & ~reserved_hqd_mask); +} + int amdgpu_mes_init(struct amdgpu_device *adev) { int i, r, num_pipes; + u32 total_vmid_mask, reserved_vmid_mask; + int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; + u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me, + adev->gfx.me.num_queue_per_pipe, + adev->gfx.disable_kq ? 0 : adev->gfx.num_gfx_rings); + u32 compute_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.mec.num_pipe_per_mec, + adev->gfx.mec.num_queue_per_pipe, + adev->gfx.disable_kq ? 0 : adev->gfx.num_compute_rings); adev->mes.adev = adev; - idr_init(&adev->mes.pasid_idr); - idr_init(&adev->mes.gang_id_idr); - idr_init(&adev->mes.queue_id_idr); ida_init(&adev->mes.doorbell_ida); spin_lock_init(&adev->mes.queue_id_lock); mutex_init(&adev->mes.mutex_hidden); - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) spin_lock_init(&adev->mes.ring_lock[i]); adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; + total_vmid_mask = (u32)((1UL << 16) - 1); + reserved_vmid_mask = (u32)((1UL << adev->vm_manager.first_kfd_vmid) - 1); + adev->mes.vmid_mask_mmhub = 0xFF00; - adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xFFFE : 0xFF00; + adev->mes.vmid_mask_gfxhub = total_vmid_mask & ~reserved_vmid_mask; num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; if (num_pipes > AMDGPU_MES_MAX_GFX_PIPES) @@ -116,22 +137,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev) for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) { if (i >= num_pipes) break; - if (amdgpu_ip_version(adev, GC_HWIP, 0) >= - IP_VERSION(12, 0, 0)) - /* - * GFX V12 has only one GFX pipe, but 8 queues in it. - * GFX pipe 0 queue 0 is being used by Kernel queue. - * Set GFX pipe 0 queue 1-7 for MES scheduling - * mask = 1111 1110b - */ - adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE; - else - /* - * GFX pipe 0 queue 0 is being used by Kernel queue. - * Set GFX pipe 0 queue 1 for MES scheduling - * mask = 10b - */ - adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2; + + adev->mes.gfx_hqd_mask[i] = gfx_hqd_mask; } num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; @@ -140,9 +147,16 @@ int amdgpu_mes_init(struct amdgpu_device *adev) num_pipes, AMDGPU_MES_MAX_COMPUTE_PIPES); for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) { - if (i >= num_pipes) + /* + * Currently, only MEC1 is used for both kernel and user compute queue. + * To enable other MEC, we need to redistribute queues per pipe and + * adjust queue resource shared with kfd that needs a separate patch. + * Skip other MEC for now to avoid potential issues. + */ + if (i >= adev->gfx.mec.num_pipe_per_mec) break; - adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC; + + adev->mes.compute_hqd_mask[i] = compute_hqd_mask; } num_pipes = adev->sdma.num_instances; @@ -156,7 +170,18 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.sdma_hqd_mask[i] = 0xfc; } - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { + dev_info(adev->dev, + "MES: vmid_mask_mmhub 0x%08x, vmid_mask_gfxhub 0x%08x\n", + adev->mes.vmid_mask_mmhub, + adev->mes.vmid_mask_gfxhub); + + dev_info(adev->dev, + "MES: gfx_hqd_mask 0x%08x, compute_hqd_mask 0x%08x, sdma_hqd_mask 0x%08x\n", + adev->mes.gfx_hqd_mask[0], + adev->mes.compute_hqd_mask[0], + adev->mes.sdma_hqd_mask[0]); + + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]); if (r) { dev_err(adev->dev, @@ -192,16 +217,18 @@ int amdgpu_mes_init(struct amdgpu_device *adev) goto error_doorbell; if (adev->mes.hung_queue_db_array_size) { - r = amdgpu_bo_create_kernel(adev, - adev->mes.hung_queue_db_array_size * sizeof(u32), - PAGE_SIZE, - AMDGPU_GEM_DOMAIN_GTT, - &adev->mes.hung_queue_db_array_gpu_obj, - &adev->mes.hung_queue_db_array_gpu_addr, - &adev->mes.hung_queue_db_array_cpu_addr); - if (r) { - dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); - goto error_doorbell; + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { + r = amdgpu_bo_create_kernel(adev, + adev->mes.hung_queue_db_array_size * sizeof(u32), + PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->mes.hung_queue_db_array_gpu_obj[i], + &adev->mes.hung_queue_db_array_gpu_addr[i], + &adev->mes.hung_queue_db_array_cpu_addr[i]); + if (r) { + dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r); + goto error_doorbell; + } } } @@ -210,17 +237,18 @@ int amdgpu_mes_init(struct amdgpu_device *adev) error_doorbell: amdgpu_mes_doorbell_free(adev); error: - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { if (adev->mes.sch_ctx_ptr[i]) amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); if (adev->mes.query_status_fence_ptr[i]) amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs[i]); + if (adev->mes.hung_queue_db_array_gpu_obj[i]) + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], + &adev->mes.hung_queue_db_array_gpu_addr[i], + &adev->mes.hung_queue_db_array_cpu_addr[i]); } - idr_destroy(&adev->mes.pasid_idr); - idr_destroy(&adev->mes.gang_id_idr); - idr_destroy(&adev->mes.queue_id_idr); ida_destroy(&adev->mes.doorbell_ida); mutex_destroy(&adev->mes.mutex_hidden); return r; @@ -229,16 +257,17 @@ int amdgpu_mes_init(struct amdgpu_device *adev) void amdgpu_mes_fini(struct amdgpu_device *adev) { int i; - - amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj, - &adev->mes.hung_queue_db_array_gpu_addr, - &adev->mes.hung_queue_db_array_cpu_addr); + int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, &adev->mes.event_log_gpu_addr, &adev->mes.event_log_cpu_addr); - for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) { + for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) { + amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i], + &adev->mes.hung_queue_db_array_gpu_addr[i], + &adev->mes.hung_queue_db_array_cpu_addr[i]); + if (adev->mes.sch_ctx_ptr[i]) amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); if (adev->mes.query_status_fence_ptr[i]) @@ -248,9 +277,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) amdgpu_mes_doorbell_free(adev); - idr_destroy(&adev->mes.pasid_idr); - idr_destroy(&adev->mes.gang_id_idr); - idr_destroy(&adev->mes.queue_id_idr); ida_destroy(&adev->mes.doorbell_ida); mutex_destroy(&adev->mes.mutex_hidden); } @@ -304,13 +330,14 @@ int amdgpu_mes_resume(struct amdgpu_device *adev) } int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, - struct amdgpu_ring *ring) + struct amdgpu_ring *ring, uint32_t xcc_id) { struct mes_map_legacy_queue_input queue_input; int r; memset(&queue_input, 0, sizeof(queue_input)); + queue_input.xcc_id = xcc_id; queue_input.queue_type = ring->funcs->type; queue_input.doorbell_offset = ring->doorbell_index; queue_input.pipe_id = ring->pipe; @@ -330,11 +357,12 @@ int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, enum amdgpu_unmap_queues_action action, - u64 gpu_addr, u64 seq) + u64 gpu_addr, u64 seq, uint32_t xcc_id) { struct mes_unmap_legacy_queue_input queue_input; int r; + queue_input.xcc_id = xcc_id; queue_input.action = action; queue_input.queue_type = ring->funcs->type; queue_input.doorbell_offset = ring->doorbell_index; @@ -355,13 +383,15 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid, - bool use_mmio) + bool use_mmio, + uint32_t xcc_id) { struct mes_reset_queue_input queue_input; int r; memset(&queue_input, 0, sizeof(queue_input)); + queue_input.xcc_id = xcc_id; queue_input.queue_type = ring->funcs->type; queue_input.doorbell_offset = ring->doorbell_index; queue_input.me_id = ring->me; @@ -393,11 +423,11 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, int queue_type, bool detect_only, unsigned int *hung_db_num, - u32 *hung_db_array) - + u32 *hung_db_array, + uint32_t xcc_id) { struct mes_detect_and_reset_queue_input input; - u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr; + u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id]; int r, i; if (!hung_db_num || !hung_db_array) @@ -409,7 +439,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, return -EINVAL; /* Clear the doorbell array before detection */ - memset(adev->mes.hung_queue_db_array_cpu_addr, AMDGPU_MES_INVALID_DB_OFFSET, + memset(adev->mes.hung_queue_db_array_cpu_addr[xcc_id], AMDGPU_MES_INVALID_DB_OFFSET, adev->mes.hung_queue_db_array_size * sizeof(u32)); input.queue_type = queue_type; input.detect_only = detect_only; @@ -436,7 +466,8 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, return r; } -uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) +uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t xcc_id) { struct mes_misc_op_input op_input; int r, val = 0; @@ -450,6 +481,7 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) } read_val_gpu_addr = adev->wb.gpu_addr + (addr_offset * 4); read_val_ptr = (uint32_t *)&adev->wb.wb[addr_offset]; + op_input.xcc_id = xcc_id; op_input.op = MES_MISC_OP_READ_REG; op_input.read_reg.reg_offset = reg; op_input.read_reg.buffer_addr = read_val_gpu_addr; @@ -473,12 +505,13 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) return val; } -int amdgpu_mes_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t val) +int amdgpu_mes_wreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t val, uint32_t xcc_id) { struct mes_misc_op_input op_input; int r; + op_input.xcc_id = xcc_id; op_input.op = MES_MISC_OP_WRITE_REG; op_input.write_reg.reg_offset = reg; op_input.write_reg.reg_value = val; @@ -501,11 +534,13 @@ int amdgpu_mes_wreg(struct amdgpu_device *adev, int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, uint32_t reg0, uint32_t reg1, - uint32_t ref, uint32_t mask) + uint32_t ref, uint32_t mask, + uint32_t xcc_id) { struct mes_misc_op_input op_input; int r; + op_input.xcc_id = xcc_id; op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT; op_input.wrm_reg.reg0 = reg0; op_input.wrm_reg.reg1 = reg1; @@ -530,14 +565,23 @@ int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, int amdgpu_mes_hdp_flush(struct amdgpu_device *adev) { - uint32_t hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask; + uint32_t hdp_flush_req_offset, hdp_flush_done_offset; + struct amdgpu_ring *mes_ring; + uint32_t ref_and_mask = 0, reg_mem_engine = 0; + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "mes hdp flush is not supported.\n"); + return -EINVAL; + } + + mes_ring = &adev->mes.ring[0]; hdp_flush_req_offset = adev->nbio.funcs->get_hdp_flush_req_offset(adev); hdp_flush_done_offset = adev->nbio.funcs->get_hdp_flush_done_offset(adev); - ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0; + + adev->gfx.funcs->get_hdp_flush_mask(mes_ring, &ref_and_mask, ®_mem_engine); return amdgpu_mes_reg_write_reg_wait(adev, hdp_flush_req_offset, hdp_flush_done_offset, - ref_and_mask, ref_and_mask); + ref_and_mask, ref_and_mask, 0); } int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, @@ -545,7 +589,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, uint32_t spi_gdbg_per_vmid_cntl, const uint32_t *tcp_watch_cntl, uint32_t flags, - bool trap_en) + bool trap_en, + uint32_t xcc_id) { struct mes_misc_op_input op_input = {0}; int r; @@ -556,6 +601,7 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, return -EINVAL; } + op_input.xcc_id = xcc_id; op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; op_input.set_shader_debugger.process_context_addr = process_context_addr; op_input.set_shader_debugger.flags.u32all = flags; @@ -584,7 +630,8 @@ int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, } int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, - uint64_t process_context_addr) + uint64_t process_context_addr, + uint32_t xcc_id) { struct mes_misc_op_input op_input = {0}; int r; @@ -595,6 +642,7 @@ int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, return -EINVAL; } + op_input.xcc_id = xcc_id; op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; op_input.set_shader_debugger.process_context_addr = process_context_addr; op_input.set_shader_debugger.flags.process_ctx_flush = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index e989225b354bb..f80e3aca9c78e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -58,19 +58,25 @@ enum amdgpu_mes_priority_level { struct amdgpu_mes_funcs; enum amdgpu_mes_pipe { - AMDGPU_MES_SCHED_PIPE = 0, - AMDGPU_MES_KIQ_PIPE, + AMDGPU_MES_PIPE_0 = 0, + AMDGPU_MES_PIPE_1, AMDGPU_MAX_MES_PIPES = 2, }; +#define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0 +#define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1 + +#define AMDGPU_MAX_MES_INST_PIPES \ + (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES) + +#define MES_PIPE_INST(xcc_id, pipe_id) \ + (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id) + struct amdgpu_mes { struct amdgpu_device *adev; struct mutex mutex_hidden; - struct idr pasid_idr; - struct idr gang_id_idr; - struct idr queue_id_idr; struct ida doorbell_ida; spinlock_t queue_id_lock; @@ -86,29 +92,29 @@ struct amdgpu_mes { uint64_t default_process_quantum; uint64_t default_gang_quantum; - struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; - spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES]; + spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES]; const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; /* mes ucode */ - struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; /* mes ucode data */ - struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES]; uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; /* eop gpu obj */ - struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; - uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; + struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; - void *mqd_backup[AMDGPU_MAX_MES_PIPES]; - struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; + void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES]; + struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES]; uint32_t vmid_mask_gfxhub; uint32_t vmid_mask_mmhub; @@ -116,18 +122,21 @@ struct amdgpu_mes { uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; - uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; - uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; - uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; - uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; - uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; + + uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES]; + uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES]; uint32_t saved_flags; /* initialize kiq pipe */ - int (*kiq_hw_init)(struct amdgpu_device *adev); - int (*kiq_hw_fini)(struct amdgpu_device *adev); + int (*kiq_hw_init)(struct amdgpu_device *adev, + uint32_t xcc_id); + int (*kiq_hw_fini)(struct amdgpu_device *adev, + uint32_t xcc_id); /* MES doorbells */ uint32_t db_start_dw_offset; @@ -150,9 +159,15 @@ struct amdgpu_mes { int hung_queue_db_array_size; int hung_queue_hqd_info_offset; - struct amdgpu_bo *hung_queue_db_array_gpu_obj; - uint64_t hung_queue_db_array_gpu_addr; - void *hung_queue_db_array_cpu_addr; + struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES]; + + /* cooperative dispatch */ + bool enable_coop_mode; + int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES]; + struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES]; + uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES]; }; struct amdgpu_mes_gang { @@ -208,6 +223,7 @@ struct amdgpu_mes_gang_properties { }; struct mes_add_queue_input { + uint32_t xcc_id; uint32_t process_id; uint64_t page_table_base_addr; uint64_t process_va_start; @@ -234,15 +250,19 @@ struct mes_add_queue_input { uint32_t is_aql_queue; uint32_t queue_size; uint32_t exclusively_scheduled; + uint32_t sh_mem_config_data; + uint32_t vm_cntx_cntl; }; struct mes_remove_queue_input { + uint32_t xcc_id; uint32_t doorbell_offset; uint64_t gang_context_addr; bool remove_queue_after_reset; }; struct mes_map_legacy_queue_input { + uint32_t xcc_id; uint32_t queue_type; uint32_t doorbell_offset; uint32_t pipe_id; @@ -252,6 +272,7 @@ struct mes_map_legacy_queue_input { }; struct mes_unmap_legacy_queue_input { + uint32_t xcc_id; enum amdgpu_unmap_queues_action action; uint32_t queue_type; uint32_t doorbell_offset; @@ -262,6 +283,7 @@ struct mes_unmap_legacy_queue_input { }; struct mes_suspend_gang_input { + uint32_t xcc_id; bool suspend_all_gangs; uint64_t gang_context_addr; uint64_t suspend_fence_addr; @@ -269,11 +291,13 @@ struct mes_suspend_gang_input { }; struct mes_resume_gang_input { + uint32_t xcc_id; bool resume_all_gangs; uint64_t gang_context_addr; }; struct mes_reset_queue_input { + uint32_t xcc_id; uint32_t queue_type; uint32_t doorbell_offset; bool use_mmio; @@ -309,7 +333,8 @@ enum mes_misc_opcode { }; struct mes_misc_op_input { - enum mes_misc_opcode op; + uint32_t xcc_id; + enum mes_misc_opcode op; union { struct { @@ -395,8 +420,10 @@ struct amdgpu_mes_funcs { struct mes_inv_tlbs_pasid_input *input); }; -#define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) -#define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) +#define amdgpu_mes_kiq_hw_init(adev, xcc_id) \ + (adev)->mes.kiq_hw_init((adev), (xcc_id)) +#define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \ + (adev)->mes.kiq_hw_fini((adev), (xcc_id)) int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); int amdgpu_mes_init(struct amdgpu_device *adev); @@ -406,38 +433,42 @@ int amdgpu_mes_suspend(struct amdgpu_device *adev); int amdgpu_mes_resume(struct amdgpu_device *adev); int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, - struct amdgpu_ring *ring); + struct amdgpu_ring *ring, uint32_t xcc_id); int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, enum amdgpu_unmap_queues_action action, - u64 gpu_addr, u64 seq); + u64 gpu_addr, u64 seq, uint32_t xcc_id); int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid, - bool use_mmio); + bool use_mmio, + uint32_t xcc_id); int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev); int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev, int queue_type, bool detect_only, unsigned int *hung_db_num, - u32 *hung_db_array); + u32 *hung_db_array, + uint32_t xcc_id); -uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); +uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t xcc_id); int amdgpu_mes_wreg(struct amdgpu_device *adev, - uint32_t reg, uint32_t val); + uint32_t reg, uint32_t val, uint32_t xcc_id); int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, uint32_t reg0, uint32_t reg1, - uint32_t ref, uint32_t mask); + uint32_t ref, uint32_t mask, uint32_t xcc_id); int amdgpu_mes_hdp_flush(struct amdgpu_device *adev); int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, uint64_t process_context_addr, uint32_t spi_gdbg_per_vmid_cntl, const uint32_t *tcp_watch_cntl, uint32_t flags, - bool trap_en); + bool trap_en, + uint32_t xcc_id); int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, - uint64_t process_context_addr); + uint64_t process_context_addr, uint32_t xcc_id); uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, enum amdgpu_mes_priority_level prio); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h index 1ca9d4ed8063a..6b8214650e5d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h @@ -63,14 +63,40 @@ struct amdgpu_mmhub_funcs { uint64_t page_table_base); void (*update_power_gating)(struct amdgpu_device *adev, bool enable); + int (*get_xgmi_info)(struct amdgpu_device *adev); +}; + +struct amdgpu_mmhub_client_ids { + const char * const (*names)[2]; + unsigned int size; }; struct amdgpu_mmhub { struct ras_common_if *ras_if; const struct amdgpu_mmhub_funcs *funcs; struct amdgpu_mmhub_ras *ras; + struct amdgpu_mmhub_client_ids client_ids; }; +static inline void +amdgpu_mmhub_init_client_info(struct amdgpu_mmhub *mmhub, + const char * const (*names)[2], + unsigned int size) +{ + mmhub->client_ids.names = names; + mmhub->client_ids.size = size; +} + +static inline const char * +amdgpu_mmhub_client_name(struct amdgpu_mmhub *mmhub, + u32 cid, bool is_write) +{ + if (cid < mmhub->client_ids.size) + return mmhub->client_ids.names[cid][is_write]; + + return NULL; +} + int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index dc8d2f52c7d61..c899c647cc7f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -368,15 +368,15 @@ struct amdgpu_mode_info { struct drm_property *plane_ctm_property; /** - * @shaper_lut_property: Plane property to set pre-blending shaper LUT - * that converts color content before 3D LUT. If - * plane_shaper_tf_property != Identity TF, AMD color module will + * @plane_shaper_lut_property: Plane property to set pre-blending + * shaper LUT that converts color content before 3D LUT. + * If plane_shaper_tf_property != Identity TF, AMD color module will * combine the user LUT values with pre-defined TF into the LUT * parameters to be programmed. */ struct drm_property *plane_shaper_lut_property; /** - * @shaper_lut_size_property: Plane property for the size of + * @plane_shaper_lut_size_property: Plane property for the size of * pre-blending shaper LUT as supported by the driver (read-only). */ struct drm_property *plane_shaper_lut_size_property; @@ -400,10 +400,10 @@ struct amdgpu_mode_info { */ struct drm_property *plane_lut3d_property; /** - * @plane_degamma_lut_size_property: Plane property to define the max - * size of 3D LUT as supported by the driver (read-only). The max size - * is the max size of one dimension and, therefore, the max number of - * entries for 3D LUT array is the 3D LUT size cubed; + * @plane_lut3d_size_property: Plane property to define the max size + * of 3D LUT as supported by the driver (read-only). The max size is + * the max size of one dimension and, therefore, the max number of + * entries for 3D LUT array is the 3D LUT size cubed. */ struct drm_property *plane_lut3d_size_property; /** @@ -624,7 +624,7 @@ struct amdgpu_connector { bool use_digital; /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ - struct edid *edid; + const struct drm_edid *edid; void *con_priv; bool dac_load_detect; bool detected_by_load; /* if the connection status was determined by load */ @@ -682,6 +682,11 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); + int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); void amdgpu_enc_destroy(struct drm_encoder *encoder); @@ -698,6 +703,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); + /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index e08f58de4b17f..6dfe08a5e64e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -61,6 +61,8 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + kfree(bo->dgma_addr); + amdgpu_bo_kunmap(bo); if (drm_gem_is_imported(&bo->tbo.base)) @@ -113,7 +115,23 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) struct ttm_placement *placement = &abo->placement; struct ttm_place *places = abo->placements; u64 flags = abo->flags; - u32 c = 0; + u32 c = 0, i; + + if ((domain & AMDGPU_GEM_DOMAIN_DGMA) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA; + places[c].flags = 0; + c++; + } + + if ((domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA_IMPORT; + places[c].flags = 0; + c++; + } if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; @@ -135,7 +153,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); - else + else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) places[c].flags |= TTM_PL_FLAG_TOPDOWN; if (abo->tbo.type == ttm_bo_type_kernel && @@ -153,14 +171,6 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) c++; } - if (domain & AMDGPU_GEM_DOMAIN_MMIO_REMAP) { - places[c].fpfn = 0; - places[c].lpfn = 0; - places[c].mem_type = AMDGPU_PL_MMIO_REMAP; - places[c].flags = 0; - c++; - } - if (domain & AMDGPU_GEM_DOMAIN_GTT) { places[c].fpfn = 0; places[c].lpfn = 0; @@ -220,6 +230,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); + for (i = 0; i < c; i++) + if (flags & AMDGPU_GEM_CREATE_TOP_DOWN) + places[i].flags |= TTM_PL_FLAG_TOPDOWN; placement->num_placement = c; placement->placement = places; } @@ -672,7 +685,9 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bo == NULL) return -ENOMEM; drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK bo->tbo.base.funcs = &amdgpu_gem_object_funcs; +#endif bo->vm_bo = NULL; bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : bp->domain; @@ -725,11 +740,11 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r = amdgpu_ttm_clear_buffer(bo, amdkcl_ttm_resvp(&bo->tbo), &fence); if (unlikely(r)) goto fail_unreserve; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); } @@ -743,11 +758,20 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + if (((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) || + bp->domain & (AMDGPU_GEM_DOMAIN_DGMA | AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(bo, bp->domain); + amdgpu_bo_unreserve(bo); + } + return 0; fail_unreserve: if (!bp->resv) - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); amdgpu_bo_unref(&bo); return r; } @@ -831,7 +855,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) return -EPERM; - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, false, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; @@ -972,8 +996,10 @@ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) */ domain = amdgpu_bo_get_preferred_domain(adev, domain); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_pin(bo->tbo.base.import_attach); +#endif /* force to pin into visible video ram */ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) @@ -1023,8 +1049,10 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (drm_gem_is_imported(&bo->tbo.base)) dma_buf_unpin(bo->tbo.base.import_attach); +#endif if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); @@ -1050,7 +1078,8 @@ static const char * const amdgpu_vram_names[] = { "DDR5", "LPDDR4", "LPDDR5", - "HBM3E" + "HBM3E", + "HBM4" }; /** @@ -1064,6 +1093,9 @@ static const char * const amdgpu_vram_names[] = { */ int amdgpu_bo_init(struct amdgpu_device *adev) { + /* set the default AGP aperture state */ + amdgpu_gmc_set_agp_default(adev, &adev->gmc); + /* On A+A platform, VRAM can be mapped as WB */ if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { /* reserve PAT memory space to WC for VRAM */ @@ -1080,10 +1112,10 @@ int amdgpu_bo_init(struct amdgpu_device *adev) adev->gmc.aper_size); } - DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", + drm_info(adev_to_drm(adev), "Detected VRAM RAM=%lluM, BAR=%lluM\n", adev->gmc.mc_vram_size >> 20, (unsigned long long)adev->gmc.aper_size >> 20); - DRM_INFO("RAM width %dbits %s\n", + drm_info(adev_to_drm(adev), "RAM width %dbits %s\n", adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); return amdgpu_ttm_init(adev); } @@ -1125,6 +1157,10 @@ int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_bo_user *ubo; + /* MMIO_REMAP is BAR I/O space; tiling should never be used here. */ + WARN_ON_ONCE(bo->tbo.resource && + bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP); + BUG_ON(bo->tbo.type == ttm_bo_type_kernel); if (adev->family <= AMDGPU_FAMILY_CZ && AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) @@ -1147,8 +1183,15 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) { struct amdgpu_bo_user *ubo; + /* + * MMIO_REMAP BOs are not real VRAM/GTT memory but a fixed BAR I/O window. + * They should never go through GEM tiling helpers. + */ + WARN_ON_ONCE(bo->tbo.resource && + bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP); + BUG_ON(bo->tbo.type == ttm_bo_type_kernel); - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); ubo = to_amdgpu_bo_user(bo); if (tiling_flags) @@ -1268,9 +1311,11 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, amdgpu_bo_kunmap(abo); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (abo->tbo.base.dma_buf && !drm_gem_is_imported(&abo->tbo.base) && old_mem && old_mem->mem_type != TTM_PL_SYSTEM) dma_buf_move_notify(abo->tbo.base.dma_buf); +#endif /* move_notify is called before move happens */ trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, @@ -1307,7 +1352,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) * So when this locking here fails something is wrong with the reference * counting. */ - if (WARN_ON_ONCE(!dma_resv_trylock(&bo->base._resv))) + if (WARN_ON_ONCE(!dma_resv_trylock(&amdkcl_ttm_resv(bo)))) return; amdgpu_amdkfd_remove_all_eviction_fences(abo); @@ -1317,21 +1362,21 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) goto out; - r = dma_resv_reserve_fences(&bo->base._resv, 1); + r = dma_resv_reserve_fences(&amdkcl_ttm_resv(bo), 1); if (r) goto out; - r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true, - AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); + r = amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &amdkcl_ttm_resv(bo), + &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE); if (WARN_ON(r)) goto out; amdgpu_vram_mgr_set_cleared(bo->resource); - dma_resv_add_fence(&bo->base._resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(&amdkcl_ttm_resv(bo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); out: - dma_resv_unlock(&bo->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(bo)); } /** @@ -1396,7 +1441,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared) { - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); int r; r = dma_resv_reserve_fences(resv, 1); @@ -1452,7 +1497,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, + return amdgpu_bo_sync_wait_resv(adev, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_NE_OWNER, owner, intr); } @@ -1469,11 +1514,12 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); - WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && + WARN_ON_ONCE(!dma_resv_is_locked(amdkcl_ttm_resvp(&bo->tbo)) && !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); + WARN_ON_ONCE(bo->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT); return amdgpu_bo_gpu_offset_no_check(bo); } @@ -1534,8 +1580,17 @@ u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) */ uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo) { - uint32_t domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK; + u32 domain; + /* + * MMIO_REMAP is internal now, so it no longer maps from a userspace + * domain bit. Keep fdinfo/mem-stats visibility by checking the actual + * TTM placement. + */ + if (bo->tbo.resource && bo->tbo.resource->mem_type == AMDGPU_PL_MMIO_REMAP) + return AMDGPU_PL_MMIO_REMAP; + + domain = bo->preferred_domains & AMDGPU_GEM_DOMAIN_MASK; if (!domain) return TTM_PL_SYSTEM; @@ -1554,8 +1609,6 @@ uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo) return AMDGPU_PL_OA; case AMDGPU_GEM_DOMAIN_DOORBELL: return AMDGPU_PL_DOORBELL; - case AMDGPU_GEM_DOMAIN_MMIO_REMAP: - return AMDGPU_PL_MMIO_REMAP; default: return TTM_PL_SYSTEM; } @@ -1610,7 +1663,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) unsigned int pin_count; u64 size; - if (dma_resv_trylock(bo->tbo.base.resv)) { + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { if (!bo->tbo.resource) { placement = "NONE"; } else { @@ -1621,6 +1674,12 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) else placement = "VRAM"; break; + case AMDGPU_PL_DGMA: + placement = "DGMA"; + break; + case AMDGPU_PL_DGMA_IMPORT: + placement = "DGMA_IMPORT"; + break; case TTM_PL_TT: placement = "GTT"; break; @@ -1648,7 +1707,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) break; } } - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } else { placement = "UNKNOWN"; } @@ -1677,9 +1736,9 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); /* Add the gem obj resv fence dump*/ - if (dma_resv_trylock(bo->tbo.base.resv)) { - dma_resv_describe(bo->tbo.base.resv, m); - dma_resv_unlock(bo->tbo.base.resv); + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { + dma_resv_describe(amdkcl_ttm_resvp(&bo->tbo), m); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } seq_puts(m, "\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 52c2d1731aabf..c72f4ac77c9f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -113,11 +113,24 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct amdgpu_mn *mn; +#endif + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; #endif +#else + struct list_head mn_list; +#endif + struct kgd_mem *kfd_bo; + /* DGMA imported buffer info */ + void *dgma_addr; + phys_addr_t dgma_import_base; + /* * For GPUs with spatial partitioning, xcp partition number, -1 means * any partition. For other ASICs without spatial partition, always 0 @@ -132,7 +145,6 @@ struct amdgpu_bo_user { u64 metadata_flags; void *metadata; u32 metadata_size; - }; struct amdgpu_bo_vm { @@ -168,8 +180,10 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) return AMDGPU_GEM_DOMAIN_OA; case AMDGPU_PL_DOORBELL: return AMDGPU_GEM_DOMAIN_DOORBELL; - case AMDGPU_PL_MMIO_REMAP: - return AMDGPU_GEM_DOMAIN_MMIO_REMAP; + case AMDGPU_PL_DGMA: + return AMDGPU_GEM_DOMAIN_DGMA; + case AMDGPU_PL_DGMA_IMPORT: + return AMDGPU_GEM_DOMAIN_DGMA_IMPORT; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c index 6e91ea1de5aaf..1017a30d3687d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -275,9 +275,13 @@ static void amdgpu_perf_read(struct perf_event *event) if ((!pe->adev->df.funcs) || (!pe->adev->df.funcs->pmc_get_count)) return; - +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG prev = local64_read(&hwc->prev_count); +#endif do { +#ifndef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG + prev = local64_read(&hwc->prev_count); +#endif switch (hwc->config_base) { case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF: case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI: @@ -288,8 +292,11 @@ static void amdgpu_perf_read(struct perf_event *event) count = 0; break; } +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG } while (!local64_try_cmpxchg(&hwc->prev_count, &prev, count)); - +#else + } while (local64_cmpxchg(&hwc->prev_count, prev, count) != prev); +#endif local64_add(count - prev, &event->count); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 0b10497d487c3..727ce2eac40fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -39,6 +39,8 @@ #include "psp_v13_0.h" #include "psp_v13_0_4.h" #include "psp_v14_0.h" +#include "psp_v15_0.h" +#include "psp_v15_0_8.h" #include "amdgpu_ras.h" #include "amdgpu_securedisplay.h" @@ -146,6 +148,7 @@ static int psp_init_sriov_microcode(struct psp_context *psp) break; case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): ret = psp_init_cap_microcode(psp, ucode_prefix); ret &= psp_init_ta_microcode(psp, ucode_prefix); break; @@ -217,6 +220,7 @@ static int psp_early_init(struct amdgpu_ip_block *ip_block) psp->autoload_supported = false; break; case IP_VERSION(13, 0, 12): + case IP_VERSION(13, 0, 15): psp_v13_0_set_psp_funcs(psp); psp->autoload_supported = false; adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev); @@ -259,6 +263,13 @@ static int psp_early_init(struct amdgpu_ip_block *ip_block) psp_v14_0_set_psp_funcs(psp); psp->boot_time_tmr = false; break; + case IP_VERSION(15, 0, 0): + psp_v15_0_0_set_psp_funcs(psp); + psp->boot_time_tmr = false; + break; + case IP_VERSION(15, 0, 8): + psp_v15_0_8_set_psp_funcs(psp); + break; default: return -EINVAL; } @@ -374,7 +385,8 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) return false; db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; @@ -726,7 +738,7 @@ psp_cmd_submit_buf(struct psp_context *psp, ras_intr = amdgpu_ras_intr_triggered(); if (ras_intr) break; - usleep_range(10, 100); + usleep_range(60, 100); amdgpu_device_invalidate_hdp(psp->adev, NULL); } @@ -893,18 +905,12 @@ static int psp_tmr_init(struct psp_context *psp) static bool psp_skip_tmr(struct psp_context *psp) { - switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { - case IP_VERSION(11, 0, 9): - case IP_VERSION(11, 0, 7): - case IP_VERSION(13, 0, 2): - case IP_VERSION(13, 0, 6): - case IP_VERSION(13, 0, 10): - case IP_VERSION(13, 0, 12): - case IP_VERSION(13, 0, 14): - return true; - default: - return false; - } + u32 ip_version = amdgpu_ip_version(psp->adev, MP0_HWIP, 0); + + if (amdgpu_sriov_vf(psp->adev)) + return (ip_version >= IP_VERSION(11, 0, 7)) ? true : false; + else + return (!psp->boot_time_tmr || !psp->autoload_supported) ? false : true; } static int psp_tmr_load(struct psp_context *psp) @@ -912,10 +918,7 @@ static int psp_tmr_load(struct psp_context *psp) int ret; struct psp_gfx_cmd_resp *cmd; - /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. - * Already set up by host driver. - */ - if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) + if (psp_skip_tmr(psp)) return 0; cmd = acquire_psp_cmd_buf(psp); @@ -947,10 +950,7 @@ static int psp_tmr_unload(struct psp_context *psp) int ret; struct psp_gfx_cmd_resp *cmd; - /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV, - * as TMR is not loaded at all - */ - if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) + if (psp_skip_tmr(psp)) return 0; cmd = acquire_psp_cmd_buf(psp); @@ -1995,6 +1995,7 @@ int psp_ras_initialize(struct psp_context *psp) ras_cmd->ras_in_message.init_flags.nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); ras_cmd->ras_in_message.init_flags.active_umc_mask = adev->umc.active_mask; + ras_cmd->ras_in_message.init_flags.vram_type = (uint8_t)adev->gmc.vram_type; ret = psp_ta_load(psp, &psp->ras_context.context); @@ -2620,18 +2621,16 @@ static int psp_hw_start(struct psp_context *psp) return ret; } - if (!psp->boot_time_tmr || !psp->autoload_supported) { - ret = psp_tmr_load(psp); - if (ret) { - dev_err(adev->dev, "PSP load tmr failed!\n"); - return ret; - } + ret = psp_tmr_load(psp); + if (ret) { + dev_err(adev->dev, "PSP load tmr failed!\n"); + return ret; } return 0; } -static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, +int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) { switch (ucode->ucode_id) { @@ -2719,6 +2718,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, case AMDGPU_UCODE_ID_RLC_DRAM: *type = GFX_FW_TYPE_RLC_DRAM_BOOT; break; + case AMDGPU_UCODE_ID_RLC_IRAM_1: + *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; + break; + case AMDGPU_UCODE_ID_RLC_DRAM_1: + *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; + break; case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; break; @@ -2887,6 +2892,8 @@ static void psp_print_fw_hdr(struct psp_context *psp, amdgpu_ucode_print_gfx_hdr(hdr); break; case AMDGPU_UCODE_ID_RLC_G: + case AMDGPU_UCODE_ID_RLC_DRAM_1: + case AMDGPU_UCODE_ID_RLC_IRAM_1: hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; amdgpu_ucode_print_rlc_hdr(hdr); break; @@ -2911,10 +2918,9 @@ static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp, cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; - ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); + ret = psp_get_fw_type(psp, ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); if (ret) - dev_err(psp->adev->dev, "Unknown firmware type\n"); - + dev_err(psp->adev->dev, "Unknown firmware type %d\n", ucode->ucode_id); return ret; } @@ -3077,7 +3083,11 @@ static int psp_load_non_psp_fw(struct psp_context *psp) amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 11) || amdgpu_ip_version(adev, MP0_HWIP, 0) == - IP_VERSION(11, 0, 12)) && + IP_VERSION(11, 0, 12) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == + IP_VERSION(15, 0, 0) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == + IP_VERSION(15, 0, 8)) && (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) @@ -3086,6 +3096,13 @@ static int psp_load_non_psp_fw(struct psp_context *psp) */ continue; + /* IMU ucode is part of IFWI and MP0 15.0.8 would load it */ + if (amdgpu_ip_version(adev, MP0_HWIP, 0) == + IP_VERSION(15, 0, 8) && + (ucode->ucode_id == AMDGPU_UCODE_ID_IMU_I || + ucode->ucode_id == AMDGPU_UCODE_ID_IMU_D)) + continue; + psp_print_fw_hdr(psp, ucode); ret = psp_execute_ip_fw_load(psp, ucode); @@ -4031,7 +4048,7 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) } int psp_config_sq_perfmon(struct psp_context *psp, - uint32_t xcp_id, bool core_override_enable, + uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) { int ret; @@ -4039,12 +4056,9 @@ int psp_config_sq_perfmon(struct psp_context *psp, if (amdgpu_sriov_vf(psp->adev)) return 0; - if (xcp_id > MAX_XCP) { - dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); - return -EINVAL; - } - - if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { + if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6) && + amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12) && + amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) { dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); return -EINVAL; @@ -4052,15 +4066,15 @@ int psp_config_sq_perfmon(struct psp_context *psp, struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; - cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); + cmd->cmd.config_sq_perfmon.gfx_xcc_mask = BIT_MASK(xcc_id); cmd->cmd.config_sq_perfmon.core_override = core_override_enable; cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); if (ret) - dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", - xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); + dev_warn(psp->adev->dev, "PSP failed to config sq: xcc%d core%d reg%d perfmon%d\n", + xcc_id, core_override_enable, reg_override_enable, perfmon_override_enable); release_psp_cmd_buf(psp); return ret; @@ -4191,8 +4205,13 @@ int is_psp_fw_valid(struct psp_bin_desc bin) } static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, +#else + struct bin_attribute *bin_attr, +#endif char *buffer, loff_t pos, size_t count) + { struct device *dev = kobj_to_dev(kobj); struct drm_device *ddev = dev_get_drvdata(dev); @@ -4227,7 +4246,11 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, } static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct device *dev = kobj_to_dev(kobj); @@ -4279,7 +4302,11 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, * Writing to this file will stage an IFWI for update. Reading from this file * will trigger the update process. */ +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW static const struct bin_attribute psp_vbflash_bin_attr = { +#else +static struct bin_attribute psp_vbflash_bin_attr = { +#endif .attr = {.name = "psp_vbflash", .mode = 0660}, .size = 0, .write = amdgpu_psp_vbflash_write, @@ -4310,10 +4337,17 @@ static ssize_t amdgpu_psp_vbflash_status(struct device *dev, } static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW static const struct bin_attribute *const bin_flash_attrs[] = { &psp_vbflash_bin_attr, NULL }; +#else +static struct bin_attribute *bin_flash_attrs[] = { + &psp_vbflash_bin_attr, + NULL +}; +#endif static struct attribute *flash_attrs[] = { &dev_attr_psp_vbflash_status.attr, @@ -4334,7 +4368,10 @@ static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribu } static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, - const struct bin_attribute *attr, +#ifdef HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE + const +#endif + struct bin_attribute *attr, int idx) { struct device *dev = kobj_to_dev(kobj); @@ -4531,3 +4568,19 @@ const struct amdgpu_ip_block_version psp_v14_0_ip_block = { .rev = 0, .funcs = &psp_ip_funcs, }; + +const struct amdgpu_ip_block_version psp_v15_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_PSP, + .major = 15, + .minor = 0, + .rev = 0, + .funcs = &psp_ip_funcs, +}; + +const struct amdgpu_ip_block_version psp_v15_0_8_ip_block = { + .type = AMD_IP_BLOCK_TYPE_PSP, + .major = 15, + .minor = 0, + .rev = 8, + .funcs = &psp_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 237b624aa51ca..c6e311077b58e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -172,6 +172,8 @@ struct psp_funcs { bool (*is_reload_needed)(struct psp_context *psp); int (*reg_program_no_ring)(struct psp_context *psp, uint32_t val, enum psp_reg_prog_id id); + int (*get_fw_type)(struct amdgpu_firmware_info *ucode, + enum psp_gfx_fw_type *type); }; struct ta_funcs { @@ -524,6 +526,10 @@ struct amdgpu_psp_funcs { ((psp)->funcs->reg_program_no_ring ? \ (psp)->funcs->reg_program_no_ring((psp), val, id) : -EINVAL) +#define psp_get_fw_type(psp, ucode, type) \ + ((psp)->funcs->get_fw_type ? \ + (psp)->funcs->get_fw_type(ucode, type):amdgpu_psp_get_fw_type(ucode, type)) + extern const struct amd_ip_funcs psp_ip_funcs; extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; @@ -534,6 +540,8 @@ extern const struct amdgpu_ip_block_version psp_v12_0_ip_block; extern const struct amdgpu_ip_block_version psp_v13_0_ip_block; extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block; extern const struct amdgpu_ip_block_version psp_v14_0_ip_block; +extern const struct amdgpu_ip_block_version psp_v15_0_ip_block; +extern const struct amdgpu_ip_block_version psp_v15_0_8_ip_block; int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t field_val, uint32_t mask, uint32_t flags); @@ -615,12 +623,14 @@ int is_psp_fw_valid(struct psp_bin_desc bin); int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); bool amdgpu_psp_get_ras_capability(struct psp_context *psp); -int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, +int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcc_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); int amdgpu_psp_reg_program_no_ring(struct psp_context *psp, uint32_t val, enum psp_reg_prog_id id); void amdgpu_psp_debugfs_init(struct amdgpu_device *adev); +int amdgpu_psp_get_fw_type(struct amdgpu_firmware_info *ucode, + enum psp_gfx_fw_type *type); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c index 6e8aad91bcd30..0d3c18f04ac36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c @@ -332,13 +332,13 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size if (!context || !context->initialized) { dev_err(adev->dev, "TA is not initialized\n"); ret = -EINVAL; - goto err_free_shared_buf; + goto free_shared_buf; } if (!psp->ta_funcs || !psp->ta_funcs->fn_ta_invoke) { dev_err(adev->dev, "Unsupported function to invoke TA\n"); ret = -EOPNOTSUPP; - goto err_free_shared_buf; + goto free_shared_buf; } context->session_id = ta_id; @@ -346,7 +346,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size mutex_lock(&psp->ras_context.mutex); ret = prep_ta_mem_context(&context->mem_context, shared_buf, shared_buf_len); if (ret) - goto err_free_shared_buf; + goto unlock; ret = psp_fn_ta_invoke(psp, cmd_id); if (ret || context->resp_status) { @@ -354,15 +354,17 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size ret, context->resp_status); if (!ret) { ret = -EINVAL; - goto err_free_shared_buf; + goto unlock; } } if (copy_to_user((char *)&buf[copy_pos], context->mem_context.shared_buf, shared_buf_len)) ret = -EFAULT; -err_free_shared_buf: +unlock: mutex_unlock(&psp->ras_context.mutex); + +free_shared_buf: kfree(shared_buf); return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 2a6cf7963dde2..da221b5414440 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -21,6 +21,7 @@ * * */ +#include "amdgpu_reg_access.h" #include #include #include @@ -42,6 +43,7 @@ #include "amdgpu_reset.h" #include "amdgpu_psp.h" #include "amdgpu_ras_mgr.h" +#include "amdgpu_virt_ras_cmd.h" #ifdef CONFIG_X86_MCE_AMD #include @@ -228,17 +230,33 @@ static int amdgpu_check_address_validity(struct amdgpu_device *adev, return 0; if (amdgpu_sriov_vf(adev)) { - if (amdgpu_virt_check_vf_critical_region(adev, address, &hit)) - return -EPERM; - return hit ? -EACCES : 0; + if (amdgpu_uniras_enabled(adev)) { + if (amdgpu_virt_ras_check_address_validity(adev, address, &hit)) + return -EPERM; + if (hit) + return -EACCES; + } else { + if (amdgpu_virt_check_vf_critical_region(adev, address, &hit)) + return -EPERM; + return hit ? -EACCES : 0; + } } if ((address >= adev->gmc.mc_vram_size) || (address >= RAS_UMC_INJECT_ADDR_LIMIT)) return -EFAULT; - count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, + if (amdgpu_uniras_enabled(adev)) { + if (amdgpu_sriov_vf(adev)) + count = amdgpu_virt_ras_convert_retired_address(adev, address, + page_pfns, ARRAY_SIZE(page_pfns)); + else + count = amdgpu_ras_mgr_lookup_bad_pages_in_a_row(adev, address, + page_pfns, ARRAY_SIZE(page_pfns)); + } else + count = amdgpu_umc_lookup_bad_pages_in_a_row(adev, address, page_pfns, ARRAY_SIZE(page_pfns)); + if (count <= 0) return -EPERM; @@ -1881,7 +1899,11 @@ static char *amdgpu_ras_badpage_flags_str(unsigned int flags) */ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, +#ifdef HAVE_BIN_ATTR_CONST_ARGS struct kobject *kobj, const struct bin_attribute *attr, +#else + struct kobject *kobj, struct bin_attribute *attr, +#endif char *buf, loff_t ppos, size_t count) { struct amdgpu_ras *con = @@ -1917,8 +1939,6 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, for (i = 0; i < bps_count; i++) { address = ((uint64_t)bps[i].bp) << AMDGPU_GPU_PAGE_SHIFT; - if (amdgpu_ras_check_critical_address(adev, address)) - continue; bps[i].size = AMDGPU_GPU_PAGE_SIZE; @@ -1931,6 +1951,10 @@ static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, else bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED; + if ((bps[i].flags != AMDGPU_RAS_RETIRE_PAGE_RESERVED) && + amdgpu_ras_check_critical_address(adev, address)) + bps[i].flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED; + s += scnprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n", bps[i].bp, @@ -2230,6 +2254,7 @@ static bool amdgpu_ras_aca_is_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): ret = true; break; default: @@ -2300,10 +2325,17 @@ static int amdgpu_ras_fs_init(struct amdgpu_device *adev) &con->event_state_attr.attr, NULL }; +#ifdef HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW const struct bin_attribute *bin_attrs[] = { NULL, NULL, }; +#else + struct bin_attribute *bin_attrs[] = { + NULL, + NULL, + }; +#endif int r; group.attrs = attrs; @@ -2777,6 +2809,10 @@ static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, if (!data->bps[i].ts) continue; + /* U64_MAX is used to mark the record as invalid */ + if (data->bps[i].retired_page == U64_MAX) + continue; + bps[r].bp = data->bps[i].retired_page; r++; if (r >= count) @@ -3076,18 +3112,20 @@ static int __amdgpu_ras_restore_bad_pages(struct amdgpu_device *adev, struct ras_err_handler_data *data = con->eh_data; for (j = 0; j < count; j++) { + if (!data->space_left && + amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { + return -ENOMEM; + } + if (amdgpu_ras_check_bad_page_unlock(con, bps[j].retired_page << AMDGPU_GPU_PAGE_SHIFT)) { + /* set to U64_MAX to mark it as invalid */ + data->bps[data->count].retired_page = U64_MAX; data->count++; data->space_left--; continue; } - if (!data->space_left && - amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { - return -ENOMEM; - } - amdgpu_ras_reserve_page(adev, bps[j].retired_page); memcpy(&data->bps[data->count], &(bps[j]), @@ -3105,9 +3143,11 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev, enum amdgpu_memory_partition nps) { int i = 0; + uint64_t chan_idx_v2; enum amdgpu_memory_partition save_nps; save_nps = (bps[0].retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + chan_idx_v2 = bps[0].retired_page & UMC_CHANNEL_IDX_V2; /*old asics just have pa in eeprom*/ if (IP_VERSION_MAJ(amdgpu_ip_version(adev, UMC_HWIP, 0)) < 12) { @@ -3119,7 +3159,7 @@ static int __amdgpu_ras_convert_rec_array_from_rom(struct amdgpu_device *adev, for (i = 0; i < adev->umc.retire_unit; i++) bps[i].retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); - if (save_nps) { + if (save_nps || chan_idx_v2) { if (save_nps == nps) { if (amdgpu_umc_pages_in_a_row(adev, err_data, bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT)) @@ -3163,10 +3203,12 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, enum amdgpu_memory_partition nps) { int i = 0; + uint64_t chan_idx_v2; enum amdgpu_memory_partition save_nps; if (!amdgpu_ras_smu_eeprom_supported(adev)) { save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK; + chan_idx_v2 = bps->retired_page & UMC_CHANNEL_IDX_V2; bps->retired_page &= ~(UMC_NPS_MASK << UMC_NPS_SHIFT); } else { /* if pmfw manages eeprom, save_nps is not stored on eeprom, @@ -3188,16 +3230,19 @@ static int __amdgpu_ras_convert_rec_from_rom(struct amdgpu_device *adev, err_data->err_addr[i].mcumc_id = bps->mcumc_id; } } else { - if (bps->address) { + if (save_nps || chan_idx_v2) { if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data)) return -EINVAL; } else { /* for specific old eeprom data, mca address is not stored, * calc it from pa */ - if (amdgpu_umc_pa2mca(adev, bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, - &(bps->address), AMDGPU_NPS1_PARTITION_MODE)) - return -EINVAL; + if (bps->address == 0) + if (amdgpu_umc_pa2mca(adev, + bps->retired_page << AMDGPU_GPU_PAGE_SHIFT, + &(bps->address), + AMDGPU_NPS1_PARTITION_MODE)) + return -EINVAL; if (amdgpu_ras_mca2pa(adev, bps, err_data)) return -EOPNOTSUPP; @@ -3249,8 +3294,6 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, /* deal with retire_unit records a time */ ret = __amdgpu_ras_convert_rec_array_from_rom(adev, &bps[i], &err_data, nps); - if (ret) - con->bad_page_num -= adev->umc.retire_unit; i += (adev->umc.retire_unit - 1); } else { break; @@ -3263,8 +3306,6 @@ int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, for (; i < pages; i++) { ret = __amdgpu_ras_convert_rec_from_rom(adev, &bps[i], &err_data, nps); - if (ret) - con->bad_page_num -= adev->umc.retire_unit; } con->eh_data->count_saved = con->eh_data->count; @@ -3897,6 +3938,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); #endif + return 0; free: @@ -3971,6 +4013,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): return true; default: return false; @@ -3984,6 +4027,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): case IP_VERSION(14, 0, 3): return true; default: @@ -4153,7 +4197,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) adev->aca.is_enabled = (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)); + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)); } /* bad page feature is not applicable to specific app platform */ @@ -4241,6 +4286,7 @@ static void amdgpu_ras_init_reserved_vram_size(struct amdgpu_device *adev) case IP_VERSION(13, 0, 2): case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 12): + case IP_VERSION(13, 0, 15): con->reserved_pages_in_bytes = AMDGPU_RAS_RESERVED_VRAM_SIZE_DEFAULT; break; case IP_VERSION(13, 0, 14): @@ -4343,7 +4389,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) * to handle fatal error */ r = amdgpu_nbio_ras_sw_init(adev); if (r) - return r; + goto release_con; if (adev->nbio.ras && adev->nbio.ras->init_ras_controller_interrupt) { @@ -4421,10 +4467,10 @@ static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, return 0; if (amdgpu_ras_query_error_status(adev, &info) != 0) - DRM_WARN("RAS init harvest failure"); + drm_warn(adev_to_drm(adev), "RAS init query failure"); if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) - DRM_WARN("RAS init harvest reset failure"); + drm_warn(adev_to_drm(adev), "RAS init harvest reset failure"); return 0; } @@ -4641,6 +4687,8 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); } + amdgpu_ras_check_bad_page_status(adev); + return 0; } @@ -4928,8 +4976,10 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ +#ifdef HAVE_SMCA_UMC_V2 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) +#endif return NOTIFY_DONE; /* @@ -5387,7 +5437,11 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void) return err_node; } +#ifdef HAVE_LIST_CMP_FUNC_IS_CONST_PARAM static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) +#else +static int ras_err_info_cmp(void *priv, struct list_head *a, struct list_head *b) +#endif { struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); @@ -5505,11 +5559,11 @@ static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev, * is changed. In such case, replace the aqua_vanjaram implementation * with more common helper */ reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + - aqua_vanjaram_encode_ext_smn_addressing(instance); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance); fw_status = amdgpu_device_indirect_rreg_ext(adev, reg_addr); reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) + - aqua_vanjaram_encode_ext_smn_addressing(instance); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance); boot_error = amdgpu_device_indirect_rreg_ext(adev, reg_addr); socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error); @@ -5575,7 +5629,7 @@ static bool amdgpu_ras_boot_error_detected(struct amdgpu_device *adev, int retry_loop; reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + - aqua_vanjaram_encode_ext_smn_addressing(instance); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, instance); for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) { reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 64dd7a81bff5f..cdf4909592d22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -508,6 +508,9 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) control->bad_channel_bitmap = 0; amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); con->update_channel_flag = false; + /* there is no record on eeprom now, clear the counter */ + if (con->eh_data) + con->eh_data->count_saved = 0; amdgpu_ras_debugfs_set_ret_size(control); @@ -1555,6 +1558,8 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + int dev_var = adev->pdev->device & 0xF; + uint32_t vram_type = adev->gmc.vram_type; int res; if (amdgpu_ras_smu_eeprom_supported(adev)) @@ -1594,6 +1599,12 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) return amdgpu_ras_eeprom_reset_table(control); } + if (!(adev->flags & AMD_IS_APU) && (dev_var == 0x5) && + (vram_type == AMDGPU_VRAM_TYPE_HBM3E) && + (hdr->version < RAS_TABLE_VER_V3)) { + return amdgpu_ras_eeprom_reset_table(control); + } + switch (hdr->version) { case RAS_TABLE_VER_V2_1: case RAS_TABLE_VER_V3: @@ -1701,10 +1712,12 @@ int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) } res = __verify_ras_table_checksum(control); - if (res) + if (res) { dev_err(adev->dev, "RAS table incorrect checksum or error:%d\n", res); + return -EINVAL; + } /* Warn if we are at 90% of the threshold or above */ @@ -1928,3 +1941,26 @@ int amdgpu_ras_smu_erase_ras_table(struct amdgpu_device *adev, result); return -EOPNOTSUPP; } + +void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev) +{ + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); + struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; + + if (!control || amdgpu_bad_page_threshold == 0) + return; + + if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { + if (amdgpu_dpm_send_rma_reason(adev)) + dev_warn(adev->dev, "Unable to send out-of-band RMA CPER"); + else + dev_dbg(adev->dev, "Sent out-of-band RMA CPER"); + + if (adev->cper.enabled && !amdgpu_uniras_enabled(adev)) { + if (amdgpu_cper_generate_bp_threshold_record(adev)) + dev_warn(adev->dev, "Unable to send in-band RMA CPER"); + else + dev_dbg(adev->dev, "Sent in-band RMA CPER"); + } + } +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h index 2e5d63957e714..a62114800a92a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h @@ -193,6 +193,8 @@ int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control); +void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev); + extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops; extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c new file mode 100644 index 0000000000000..540040c76058b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "amdgpu.h" +#include "amdgpu_reset.h" +#include "amdgpu_trace.h" +#include "amdgpu_virt.h" +#include "amdgpu_reg_access.h" + +#define AMDGPU_PCIE_INDEX_FALLBACK (0x38 >> 2) +#define AMDGPU_PCIE_INDEX_HI_FALLBACK (0x44 >> 2) +#define AMDGPU_PCIE_DATA_FALLBACK (0x3C >> 2) + +void amdgpu_reg_access_init(struct amdgpu_device *adev) +{ + spin_lock_init(&adev->reg.smc.lock); + adev->reg.smc.rreg = NULL; + adev->reg.smc.wreg = NULL; + + spin_lock_init(&adev->reg.uvd_ctx.lock); + adev->reg.uvd_ctx.rreg = NULL; + adev->reg.uvd_ctx.wreg = NULL; + + spin_lock_init(&adev->reg.didt.lock); + adev->reg.didt.rreg = NULL; + adev->reg.didt.wreg = NULL; + + spin_lock_init(&adev->reg.gc_cac.lock); + adev->reg.gc_cac.rreg = NULL; + adev->reg.gc_cac.wreg = NULL; + + spin_lock_init(&adev->reg.se_cac.lock); + adev->reg.se_cac.rreg = NULL; + adev->reg.se_cac.wreg = NULL; + + spin_lock_init(&adev->reg.audio_endpt.lock); + adev->reg.audio_endpt.rreg = NULL; + adev->reg.audio_endpt.wreg = NULL; + + spin_lock_init(&adev->reg.pcie.lock); + adev->reg.pcie.rreg = NULL; + adev->reg.pcie.wreg = NULL; + adev->reg.pcie.rreg_ext = NULL; + adev->reg.pcie.wreg_ext = NULL; + adev->reg.pcie.rreg64 = NULL; + adev->reg.pcie.wreg64 = NULL; + adev->reg.pcie.rreg64_ext = NULL; + adev->reg.pcie.wreg64_ext = NULL; + adev->reg.pcie.port_rreg = NULL; + adev->reg.pcie.port_wreg = NULL; +} + +uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.smc.rreg) { + dev_err_once(adev->dev, "SMC register read not supported\n"); + return 0; + } + return adev->reg.smc.rreg(adev, reg); +} + +void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.smc.wreg) { + dev_err_once(adev->dev, "SMC register write not supported\n"); + return; + } + adev->reg.smc.wreg(adev, reg, v); +} + +uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.uvd_ctx.rreg) { + dev_err_once(adev->dev, + "UVD_CTX register read not supported\n"); + return 0; + } + return adev->reg.uvd_ctx.rreg(adev, reg); +} + +void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v) +{ + if (!adev->reg.uvd_ctx.wreg) { + dev_err_once(adev->dev, + "UVD_CTX register write not supported\n"); + return; + } + adev->reg.uvd_ctx.wreg(adev, reg, v); +} + +uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.didt.rreg) { + dev_err_once(adev->dev, "DIDT register read not supported\n"); + return 0; + } + return adev->reg.didt.rreg(adev, reg); +} + +void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.didt.wreg) { + dev_err_once(adev->dev, "DIDT register write not supported\n"); + return; + } + adev->reg.didt.wreg(adev, reg, v); +} + +uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.gc_cac.rreg) { + dev_err_once(adev->dev, "GC_CAC register read not supported\n"); + return 0; + } + return adev->reg.gc_cac.rreg(adev, reg); +} + +void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v) +{ + if (!adev->reg.gc_cac.wreg) { + dev_err_once(adev->dev, + "GC_CAC register write not supported\n"); + return; + } + adev->reg.gc_cac.wreg(adev, reg, v); +} + +uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.se_cac.rreg) { + dev_err_once(adev->dev, "SE_CAC register read not supported\n"); + return 0; + } + return adev->reg.se_cac.rreg(adev, reg); +} + +void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v) +{ + if (!adev->reg.se_cac.wreg) { + dev_err_once(adev->dev, + "SE_CAC register write not supported\n"); + return; + } + adev->reg.se_cac.wreg(adev, reg, v); +} + +uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg) +{ + if (!adev->reg.audio_endpt.rreg) { + dev_err_once(adev->dev, + "AUDIO_ENDPT register read not supported\n"); + return 0; + } + return adev->reg.audio_endpt.rreg(adev, block, reg); +} + +void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg, uint32_t v) +{ + if (!adev->reg.audio_endpt.wreg) { + dev_err_once(adev->dev, + "AUDIO_ENDPT register write not supported\n"); + return; + } + adev->reg.audio_endpt.wreg(adev, block, reg, v); +} + +uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.pcie.rreg) { + dev_err_once(adev->dev, "PCIE register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg(adev, reg); +} + +void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.pcie.wreg) { + dev_err_once(adev->dev, "PCIE register write not supported\n"); + return; + } + adev->reg.pcie.wreg(adev, reg, v); +} + +uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg) +{ + if (!adev->reg.pcie.rreg_ext) { + dev_err_once(adev->dev, "PCIE EXT register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg_ext(adev, reg); +} + +void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, + uint32_t v) +{ + if (!adev->reg.pcie.wreg_ext) { + dev_err_once(adev->dev, "PCIE EXT register write not supported\n"); + return; + } + adev->reg.pcie.wreg_ext(adev, reg, v); +} + +uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.pcie.rreg64) { + dev_err_once(adev->dev, "PCIE 64-bit register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg64(adev, reg); +} + +void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v) +{ + if (!adev->reg.pcie.wreg64) { + dev_err_once(adev->dev, "PCIE 64-bit register write not supported\n"); + return; + } + adev->reg.pcie.wreg64(adev, reg, v); +} + +uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg) +{ + if (!adev->reg.pcie.rreg64_ext) { + dev_err_once(adev->dev, "PCIE EXT 64-bit register read not supported\n"); + return 0; + } + return adev->reg.pcie.rreg64_ext(adev, reg); +} + +void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, + uint64_t v) +{ + if (!adev->reg.pcie.wreg64_ext) { + dev_err_once(adev->dev, "PCIE EXT 64-bit register write not supported\n"); + return; + } + adev->reg.pcie.wreg64_ext(adev, reg, v); +} + +uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg) +{ + if (!adev->reg.pcie.port_rreg) { + dev_err_once(adev->dev, "PCIEP register read not supported\n"); + return 0; + } + return adev->reg.pcie.port_rreg(adev, reg); +} + +void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v) +{ + if (!adev->reg.pcie.port_wreg) { + dev_err_once(adev->dev, "PCIEP register write not supported\n"); + return; + } + adev->reg.pcie.port_wreg(adev, reg, v); +} + +static int amdgpu_reg_get_smn_base_version(struct amdgpu_device *adev) +{ + struct pci_dev *pdev = adev->pdev; + int id; + + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + + id = (pdev->device >> 4) & 0xFFFF; + if (id == 0x74A || id == 0x74B || id == 0x75A || id == 0x75B) + return 1; + + return -EOPNOTSUPP; +} + +uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst) +{ + if (!adev->reg.smn.get_smn_base) { + int version = amdgpu_reg_get_smn_base_version(adev); + switch (version) { + case 1: + return amdgpu_reg_smn_v1_0_get_base(adev, block, + die_inst); + default: + dev_err_once( + adev->dev, + "SMN base address query not supported for this device\n"); + return 0; + } + } + return adev->reg.smn.get_smn_base(adev, block, die_inst); +} + +uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst) +{ + uint64_t smn_base; + + if (die_inst == 0) + return 0; + + switch (block) { + case XGMI_HWIP: + case NBIO_HWIP: + case MP0_HWIP: + case UMC_HWIP: + case DF_HWIP: + smn_base = ((uint64_t)(die_inst & 0x3) << 32) | (1ULL << 34); + break; + default: + dev_warn_once( + adev->dev, + "SMN base address query not supported for this block %d\n", + block); + smn_base = 0; + break; + } + + return smn_base; +} + +/* + * register access helper functions. + */ + +/** + * amdgpu_device_rreg - read a memory mapped IO or indirect register + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @acc_flags: access flags which require special behavior + * + * Returns the 32 bit value from the offset specified. + */ +uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags) +{ + uint32_t ret; + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if ((reg * 4) < adev->rmmio_size) { + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_kiq_rreg(adev, reg, 0); + up_read(&adev->reset_domain->sem); + } else { + ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + ret = amdgpu_reg_pcie_rd32(adev, reg * 4); + } + + trace_amdgpu_device_rreg(adev->pdev->device, reg, ret); + + return ret; +} + +/* + * MMIO register read with bytes helper functions + * @offset:bytes offset from MMIO start + */ + +/** + * amdgpu_mm_rreg8 - read a memory mapped IO register + * + * @adev: amdgpu_device pointer + * @offset: byte aligned register offset + * + * Returns the 8 bit value from the offset specified. + */ +uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset) +{ + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if (offset < adev->rmmio_size) + return (readb(adev->rmmio + offset)); + BUG(); +} + +/** + * amdgpu_device_xcc_rreg - read a memory mapped IO or indirect register with specific XCC + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @acc_flags: access flags which require special behavior + * @xcc_id: xcc accelerated compute core id + * + * Returns the 32 bit value from the offset specified. + */ +uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags, uint32_t xcc_id) +{ + uint32_t ret, rlcg_flag; + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + if ((reg * 4) < adev->rmmio_size) { + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_runtime(adev) && + adev->gfx.rlc.rlcg_reg_access_supported && + amdgpu_virt_get_rlcg_reg_access_flag( + adev, acc_flags, GC_HWIP, false, &rlcg_flag)) { + ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, + GET_INST(GC, xcc_id)); + } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_kiq_rreg(adev, reg, xcc_id); + up_read(&adev->reset_domain->sem); + } else { + ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + ret = amdgpu_reg_pcie_rd32(adev, reg * 4); + } + + return ret; +} + +/* + * MMIO register write with bytes helper functions + * @offset:bytes offset from MMIO start + * @value: the value want to be written to the register + */ + +/** + * amdgpu_mm_wreg8 - read a memory mapped IO register + * + * @adev: amdgpu_device pointer + * @offset: byte aligned register offset + * @value: 8 bit value to write + * + * Writes the value specified to the offset specified. + */ +void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value) +{ + if (amdgpu_device_skip_hw_access(adev)) + return; + + if (offset < adev->rmmio_size) + writeb(value, adev->rmmio + offset); + else + BUG(); +} + +/** + * amdgpu_device_wreg - write to a memory mapped IO or indirect register + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @v: 32 bit value to write to the register + * @acc_flags: access flags which require special behavior + * + * Writes the value specified to the offset specified. + */ +void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + uint32_t acc_flags) +{ + if (amdgpu_device_skip_hw_access(adev)) + return; + + if ((reg * 4) < adev->rmmio_size) { + if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_kiq_wreg(adev, reg, v, 0); + up_read(&adev->reset_domain->sem); + } else { + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + amdgpu_reg_pcie_wr32(adev, reg * 4, v); + } + + trace_amdgpu_device_wreg(adev->pdev->device, reg, v); +} + +/** + * amdgpu_mm_wreg_mmio_rlc - write register either with direct/indirect mmio or with RLC path if in range + * + * @adev: amdgpu_device pointer + * @reg: mmio/rlc register + * @v: value to write + * @xcc_id: xcc accelerated compute core id + * + * this function is invoked only for the debugfs register access + */ +void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t xcc_id) +{ + if (amdgpu_device_skip_hw_access(adev)) + return; + + if (amdgpu_sriov_fullaccess(adev) && adev->gfx.rlc.funcs && + adev->gfx.rlc.funcs->is_rlcg_access_range) { + if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg)) + return amdgpu_sriov_wreg(adev, reg, v, 0, 0, xcc_id); + } else if ((reg * 4) >= adev->rmmio_size) { + amdgpu_reg_pcie_wr32(adev, reg * 4, v); + } else { + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } +} + +/** + * amdgpu_device_xcc_wreg - write to a memory mapped IO or indirect register with specific XCC + * + * @adev: amdgpu_device pointer + * @reg: dword aligned register offset + * @v: 32 bit value to write to the register + * @acc_flags: access flags which require special behavior + * @xcc_id: xcc accelerated compute core id + * + * Writes the value specified to the offset specified. + */ +void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t acc_flags, uint32_t xcc_id) +{ + uint32_t rlcg_flag; + + if (amdgpu_device_skip_hw_access(adev)) + return; + + if ((reg * 4) < adev->rmmio_size) { + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_runtime(adev) && + adev->gfx.rlc.rlcg_reg_access_supported && + amdgpu_virt_get_rlcg_reg_access_flag( + adev, acc_flags, GC_HWIP, true, &rlcg_flag)) { + amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, + GET_INST(GC, xcc_id)); + } else if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_kiq_wreg(adev, reg, v, xcc_id); + up_read(&adev->reset_domain->sem); + } else { + writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } + } else { + amdgpu_reg_pcie_wr32(adev, reg * 4, v); + } +} + +/** + * amdgpu_device_indirect_rreg - read an indirect register + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register address to read from + * + * Returns the value of indirect register @reg_addr + */ +u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + u32 r; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + r = readl(pcie_data_offset); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); + + return r; +} + +u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr) +{ + unsigned long flags, pcie_index, pcie_index_hi, pcie_data; + u32 r; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + + if (unlikely(!adev->nbio.funcs)) { + pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; + pcie_data = AMDGPU_PCIE_DATA_FALLBACK; + } else { + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + } + + if (reg_addr >> 32) { + if (unlikely(!adev->nbio.funcs)) + pcie_index_hi = AMDGPU_PCIE_INDEX_HI_FALLBACK; + else + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset( + adev); + } else { + pcie_index_hi = 0; + } + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + r = readl(pcie_data_offset); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); + + return r; +} + +/** + * amdgpu_device_indirect_rreg64 - read a 64bits indirect register + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register address to read from + * + * Returns the value of indirect register @reg_addr + */ +u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + u64 r; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + /* read low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + r = readl(pcie_data_offset); + /* read high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + r |= ((u64)readl(pcie_data_offset) << 32); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); + + return r; +} + +u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr) +{ + unsigned long flags, pcie_index, pcie_data; + unsigned long pcie_index_hi = 0; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + u64 r; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + /* read low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + r = readl(pcie_data_offset); + /* read high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + r |= ((u64)readl(pcie_data_offset) << 32); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); + + return r; +} + +/** + * amdgpu_device_indirect_wreg - write an indirect register address + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register offset + * @reg_data: indirect register data + * + */ +void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, + u32 reg_data) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + writel(reg_data, pcie_data_offset); + readl(pcie_data_offset); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); +} + +void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, + u32 reg_data) +{ + unsigned long flags, pcie_index, pcie_index_hi, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset(adev); + else + pcie_index_hi = 0; + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + writel(reg_data, pcie_data_offset); + readl(pcie_data_offset); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); +} + +/** + * amdgpu_device_indirect_wreg64 - write a 64bits indirect register address + * + * @adev: amdgpu_device pointer + * @reg_addr: indirect register offset + * @reg_data: indirect register data + * + */ +void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, + u64 reg_data) +{ + unsigned long flags, pcie_index, pcie_data; + void __iomem *pcie_index_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + + /* write low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); + readl(pcie_data_offset); + /* write high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + writel((u32)(reg_data >> 32), pcie_data_offset); + readl(pcie_data_offset); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); +} + +void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, + u64 reg_data) +{ + unsigned long flags, pcie_index, pcie_data; + unsigned long pcie_index_hi = 0; + void __iomem *pcie_index_offset; + void __iomem *pcie_index_hi_offset; + void __iomem *pcie_data_offset; + + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); + pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); + if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) + pcie_index_hi = + adev->nbio.funcs->get_pcie_index_hi_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; + pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; + if (pcie_index_hi != 0) + pcie_index_hi_offset = + (void __iomem *)adev->rmmio + pcie_index_hi * 4; + + /* write low 32 bits */ + writel(reg_addr, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + writel((u32)(reg_data & 0xffffffffULL), pcie_data_offset); + readl(pcie_data_offset); + /* write high 32 bits */ + writel(reg_addr + 4, pcie_index_offset); + readl(pcie_index_offset); + if (pcie_index_hi != 0) { + writel((reg_addr >> 32) & 0xff, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + writel((u32)(reg_data >> 32), pcie_data_offset); + readl(pcie_data_offset); + + /* clear the high bits */ + if (pcie_index_hi != 0) { + writel(0, pcie_index_hi_offset); + readl(pcie_index_hi_offset); + } + + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); +} + +u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) +{ + unsigned long flags, address, data; + u32 r; + + address = adev->nbio.funcs->get_pcie_port_index_offset(adev); + data = adev->nbio.funcs->get_pcie_port_data_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + WREG32(address, reg * 4); + (void)RREG32(address); + r = RREG32(data); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); + return r; +} + +void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) +{ + unsigned long flags, address, data; + + address = adev->nbio.funcs->get_pcie_port_index_offset(adev); + data = adev->nbio.funcs->get_pcie_port_data_offset(adev); + + spin_lock_irqsave(&adev->reg.pcie.lock, flags); + WREG32(address, reg * 4); + (void)RREG32(address); + WREG32(data, v); + (void)RREG32(data); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); +} + +uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, + uint32_t reg_addr, char reg_name[], + uint32_t expected_value, uint32_t mask) +{ + uint32_t ret = 0; + uint32_t old_ = 0; + uint32_t tmp_ = RREG32(reg_addr); + uint32_t loop = adev->usec_timeout; + + while ((tmp_ & (mask)) != (expected_value)) { + if (old_ != tmp_) { + loop = adev->usec_timeout; + old_ = tmp_; + } else + udelay(1); + tmp_ = RREG32(reg_addr); + loop--; + if (!loop) { + dev_warn( + adev->dev, + "Register(%d) [%s] failed to reach value 0x%08x != 0x%08xn", + inst, reg_name, (uint32_t)expected_value, + (uint32_t)(tmp_ & (mask))); + ret = -ETIMEDOUT; + break; + } + } + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h new file mode 100644 index 0000000000000..4d88e5cd19fc9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_REG_ACCESS_H__ +#define __AMDGPU_REG_ACCESS_H__ + +#include +#include + +#include "amdgpu_ip.h" + +struct amdgpu_device; + +typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t); +typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t); +typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); +typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t); +typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t); +typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t); +typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t); +typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t); + +typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t, + uint32_t); +typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t, + uint32_t); +typedef uint64_t (*amdgpu_reg_get_smn_base64_t)(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst); + +struct amdgpu_reg_ind { + spinlock_t lock; + amdgpu_rreg_t rreg; + amdgpu_wreg_t wreg; +}; + +struct amdgpu_reg_ind_blk { + spinlock_t lock; + amdgpu_block_rreg_t rreg; + amdgpu_block_wreg_t wreg; +}; + +struct amdgpu_reg_pcie_ind { + spinlock_t lock; + amdgpu_rreg_t rreg; + amdgpu_wreg_t wreg; + amdgpu_rreg_ext_t rreg_ext; + amdgpu_wreg_ext_t wreg_ext; + amdgpu_rreg64_t rreg64; + amdgpu_wreg64_t wreg64; + amdgpu_rreg64_ext_t rreg64_ext; + amdgpu_wreg64_ext_t wreg64_ext; + amdgpu_rreg_t port_rreg; + amdgpu_wreg_t port_wreg; +}; + +struct amdgpu_reg_smn_ext { + amdgpu_reg_get_smn_base64_t get_smn_base; +}; + +struct amdgpu_reg_access { + struct amdgpu_reg_ind smc; + struct amdgpu_reg_ind uvd_ctx; + struct amdgpu_reg_ind didt; + struct amdgpu_reg_ind gc_cac; + struct amdgpu_reg_ind se_cac; + struct amdgpu_reg_ind_blk audio_endpt; + struct amdgpu_reg_pcie_ind pcie; + struct amdgpu_reg_smn_ext smn; +}; + +void amdgpu_reg_access_init(struct amdgpu_device *adev); +uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v); +uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v); +uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg); +void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block, + uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); +uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg); +void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg, + uint32_t v); +uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v); +uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg); +void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg, + uint64_t v); +uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg); +void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg, + uint32_t v); +uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst); +uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev, + enum amd_hw_ip_block_type block, + int die_inst); + +uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags); +uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t acc_flags, uint32_t xcc_id); +void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, + uint32_t acc_flags); +void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t acc_flags, uint32_t xcc_id); +void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, + uint32_t v, uint32_t xcc_id); +void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, + uint8_t value); +uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); + +u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr); +u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr); +u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr); +u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr); +void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, + u32 reg_data); +void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, + u32 reg_data); +void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, + u64 reg_data); +void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, + u64 reg_data); + +u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg); +void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v); + +uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst, + uint32_t reg_addr, char reg_name[], + uint32_t expected_value, uint32_t mask); + +#endif /* __AMDGPU_REG_ACCESS_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 28c4ad62f50e2..4c50530e7c327 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -271,6 +271,14 @@ void amdgpu_reset_destroy_reset_domain(struct kref *ref) kvfree(reset_domain); } +static void amdgpu_reset_domain_cancel_all_work(struct work_struct *work) +{ + struct amdgpu_reset_domain *reset_domain = + container_of(work, struct amdgpu_reset_domain, clear); + + reset_domain->drain = false; +} + struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, char *wq_name) { @@ -293,6 +301,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d } + INIT_WORK(&reset_domain->clear, amdgpu_reset_domain_cancel_all_work); atomic_set(&reset_domain->in_gpu_reset, 0); atomic_set(&reset_domain->reset_res, 0); init_rwsem(&reset_domain->sem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 07b4d37f1db69..fbf5e95dbd16e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -99,6 +99,8 @@ struct amdgpu_reset_domain { struct rw_semaphore sem; atomic_t in_gpu_reset; atomic_t reset_res; + struct work_struct clear; + bool drain; }; int amdgpu_reset_init(struct amdgpu_device *adev); @@ -137,6 +139,20 @@ static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *doma return queue_work(domain->wq, work); } +static inline void amdgpu_reset_domain_clear_pending(struct amdgpu_reset_domain *domain) +{ + domain->drain = true; + /* queue one more work to the domain queue. Till this work is finished, + * domain is in drain mode. + */ + queue_work(domain->wq, &domain->clear); +} + +static inline bool amdgpu_reset_domain_in_drain_mode(struct amdgpu_reset_domain *domain) +{ + return domain->drain; +} + static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain) { lockdep_assert_held(&domain->sem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index c596b6df2e2d4..e47a155f4bb1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -76,8 +76,12 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type) * @ring: amdgpu_ring structure holding ring information * @ndw: number of dwords to allocate in the ring buffer * - * Allocate @ndw dwords in the ring buffer (all asics). - * Returns 0 on success, error on failure. + * Allocate @ndw dwords in the ring buffer. The number of dwords should be the + * sum of all commands written to the ring. + * + * Returns: + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the + * maximum dword allowed for one submission. */ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) { @@ -86,10 +90,13 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; /* Make sure we aren't trying to allocate more space - * than the maximum for one submission + * than the maximum for one submission. Skip for reemit + * since we may be reemitting several submissions. */ - if (WARN_ON_ONCE(ndw > ring->max_dw)) - return -ENOMEM; + if (!ring->reemit) { + if (WARN_ON_ONCE(ndw > ring->max_dw)) + return -ENOMEM; + } ring->count_dw = ndw; ring->wptr_old = ring->wptr; @@ -101,29 +108,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) } /** - * amdgpu_ring_alloc_reemit - allocate space on the ring buffer for reemit - * - * @ring: amdgpu_ring structure holding ring information - * @ndw: number of dwords to allocate in the ring buffer - * - * Allocate @ndw dwords in the ring buffer (all asics). - * doesn't check the max_dw limit as we may be reemitting - * several submissions. - */ -static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw) -{ - /* Align requested size with padding so unlock_commit can - * pad safely */ - ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; - - ring->count_dw = ndw; - ring->wptr_old = ring->wptr; - - if (ring->funcs->begin_use) - ring->funcs->begin_use(ring); -} - -/** amdgpu_ring_insert_nop - insert NOP packets + * amdgpu_ring_insert_nop - insert NOP packets * * @ring: amdgpu_ring structure holding ring information * @count: the number of NOP packets to insert @@ -186,7 +171,7 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) uint32_t count; if (ring->count_dw < 0) - DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); + drm_err(adev_to_drm(ring->adev), "writing more dwords to the ring than expected!\n"); /* We pad to match fetch size */ count = ring->funcs->align_mask + 1 - @@ -567,8 +552,9 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { struct amdgpu_ring *ring = file_inode(f)->i_private; - uint32_t value, result, early[3]; + u32 value, result, early[3] = { 0 }; uint64_t p; + u32 avail_dw, start_dw, read_dw; loff_t i; int r; @@ -580,10 +566,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, result = 0; - if (*pos < 12) { - if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) - mutex_lock(&ring->adev->cper.ring_lock); + if (ring->funcs->type == AMDGPU_RING_TYPE_CPER) + mutex_lock(&ring->adev->cper.ring_lock); + if (*pos < 12) { early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; early[2] = ring->wptr & ring->buf_mask; @@ -615,13 +601,24 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, *pos += 4; } } else { + early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask; + early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask; + p = early[0]; if (early[0] <= early[1]) - size = (early[1] - early[0]); + avail_dw = early[1] - early[0]; else - size = ring->ring_size - (early[0] - early[1]); + avail_dw = ring->buf_mask + 1 - (early[0] - early[1]); - while (size) { + start_dw = (*pos > 12) ? ((*pos - 12) >> 2) : 0; + if (start_dw >= avail_dw) + goto out; + + p = (p + start_dw) & ring->ptr_mask; + avail_dw -= start_dw; + read_dw = min_t(u32, avail_dw, size >> 2); + + while (read_dw) { if (p == early[1]) goto out; @@ -634,9 +631,10 @@ static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, buf += 4; result += 4; - size--; + read_dw--; p++; p &= ring->ptr_mask; + *pos += 4; } } @@ -706,7 +704,6 @@ static int amdgpu_debugfs_ring_error(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, amdgpu_debugfs_ring_error, "%lld\n"); - #endif void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, @@ -737,7 +734,6 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, sprintf(name, "amdgpu_error_%s", ring->name); debugfs_create_file(name, 0200, root, ring, &amdgpu_debugfs_error_fops); - #endif } @@ -863,8 +859,6 @@ bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring) void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence) { - /* Stop the scheduler to prevent anybody else from touching the ring buffer. */ - drm_sched_wqueue_stop(&ring->sched); /* back up the non-guilty commands */ amdgpu_ring_backup_unprocessed_commands(ring, guilty_fence); } @@ -872,7 +866,6 @@ void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring, int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, struct amdgpu_fence *guilty_fence) { - unsigned int i; int r; /* verify that the ring is functional */ @@ -880,18 +873,9 @@ int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring, if (r) return r; - /* signal the guilty fence and set an error on all fences from the context */ - if (guilty_fence) - amdgpu_fence_driver_guilty_force_completion(guilty_fence); - /* Re-emit the non-guilty commands */ - if (ring->ring_backup_entries_to_copy) { - amdgpu_ring_alloc_reemit(ring, ring->ring_backup_entries_to_copy); - for (i = 0; i < ring->ring_backup_entries_to_copy; i++) - amdgpu_ring_write(ring, ring->ring_backup[i]); - amdgpu_ring_commit(ring); - } - /* Start the scheduler again */ - drm_sched_wqueue_start(&ring->sched); + /* set an error on all fences from the context and reemit */ + amdgpu_ring_set_fence_errors_and_reemit(ring, guilty_fence); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 055437d4edf9f..ce5af137ee400 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level { #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) #define AMDGPU_FENCE_FLAG_INT (1 << 1) #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) + +/* Ensure the execution in case of preemption or reset */ #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) @@ -119,7 +121,6 @@ struct amdgpu_fence_driver { /* sync_seq is protected by ring emission lock */ uint32_t sync_seq; atomic_t last_seq; - u64 signalled_wptr; bool initialized; struct amdgpu_irq_src *irq_src; unsigned irq_type; @@ -144,23 +145,23 @@ struct amdgpu_fence { struct amdgpu_ring *ring; ktime_t start_timestamp; - /* wptr for the total submission for resets */ - u64 wptr; + /* location and size of the IB */ + u64 ib_wptr; + unsigned int ib_dw_size; + unsigned int skip_ib_dw_start_offset; + unsigned int skip_ib_dw_end_offset; /* fence context for resets */ u64 context; - /* has this fence been reemitted */ - unsigned int reemitted; - /* wptr for the fence for the submission */ - u64 fence_wptr_start; - u64 fence_wptr_end; + /* idx for ring backups */ + unsigned int backup_idx; }; extern const struct drm_sched_backend_ops amdgpu_sched_ops; void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error); void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); -void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af); -void amdgpu_fence_save_wptr(struct amdgpu_fence *af); +void amdgpu_ring_set_fence_errors_and_reemit(struct amdgpu_ring *ring, + struct amdgpu_fence *guilty_fence); int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, @@ -170,8 +171,8 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); -int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, - unsigned int flags); +void amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af, + unsigned int flags); int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, uint32_t timeout); bool amdgpu_fence_process(struct amdgpu_ring *ring); @@ -311,6 +312,7 @@ struct amdgpu_ring { /* backups for resets */ uint32_t *ring_backup; unsigned int ring_backup_entries_to_copy; + bool reemit; unsigned rptr_offs; u64 rptr_gpu_addr; u32 *rptr_cpu_addr; @@ -520,6 +522,17 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, ring->count_dw -= count_dw; } +static inline unsigned int amdgpu_ring_get_dw_distance(struct amdgpu_ring *ring, + u64 start_wptr, u64 end_wptr) +{ + unsigned int start = start_wptr & ring->buf_mask; + unsigned int end = end_wptr & ring->buf_mask; + + if (end < start) + end += ring->ring_size >> 2; + return end - start; +} + /** * amdgpu_ring_patch_cond_exec - patch dw count of conditional execute * @ring: amdgpu_ring structure @@ -530,18 +543,13 @@ static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, unsigned int offset) { - unsigned cur; - if (!ring->funcs->init_cond_exec) return; WARN_ON(offset > ring->buf_mask); WARN_ON(ring->ring[offset] != 0); - cur = (ring->wptr - 1) & ring->buf_mask; - if (cur < offset) - cur += ring->ring_size >> 2; - ring->ring[offset] = cur - offset; + ring->ring[offset] = amdgpu_ring_get_dw_distance(ring, offset, ring->wptr - 1); } int amdgpu_ring_test_helper(struct amdgpu_ring *ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c index 5aa830a02d80b..572a60e1b3cbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c @@ -515,6 +515,40 @@ static void amdgpu_gfx_rlc_init_microcode_v2_4(struct amdgpu_device *adev) } } +static void amdgpu_gfx_rlc_init_microcode_v2_5(struct amdgpu_device *adev) +{ + const struct rlc_firmware_header_v2_5 *rlc_hdr; + struct amdgpu_firmware_info *info; + + rlc_hdr = (const struct rlc_firmware_header_v2_5 *)adev->gfx.rlc_fw->data; + adev->gfx.rlc.rlc_1_iram_ucode_size_bytes = + le32_to_cpu(rlc_hdr->rlc_1_iram_ucode_size_bytes); + adev->gfx.rlc.rlc_1_iram_ucode = (u8 *)rlc_hdr + + le32_to_cpu(rlc_hdr->rlc_1_iram_ucode_offset_bytes); + adev->gfx.rlc.rlc_1_dram_ucode_size_bytes = + le32_to_cpu(rlc_hdr->rlc_1_dram_ucode_size_bytes); + adev->gfx.rlc.rlc_1_dram_ucode = (u8 *)rlc_hdr + + le32_to_cpu(rlc_hdr->rlc_1_dram_ucode_offset_bytes); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + if (adev->gfx.rlc.rlc_1_iram_ucode_size_bytes) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM_1]; + info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM_1; + info->fw = adev->gfx.rlc_fw; + adev->firmware.fw_size += + ALIGN(adev->gfx.rlc.rlc_1_iram_ucode_size_bytes, PAGE_SIZE); + } + + if (adev->gfx.rlc.rlc_1_dram_ucode_size_bytes) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM_1]; + info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM_1; + info->fw = adev->gfx.rlc_fw; + adev->firmware.fw_size += + ALIGN(adev->gfx.rlc.rlc_1_dram_ucode_size_bytes, PAGE_SIZE); + } + } +} + int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev, uint16_t version_major, uint16_t version_minor) @@ -545,6 +579,7 @@ int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev, amdgpu_gfx_rlc_init_microcode_v2_3(adev); if (version_minor == 4) amdgpu_gfx_rlc_init_microcode_v2_4(adev); - + if (version_minor == 5) + amdgpu_gfx_rlc_init_microcode_v2_5(adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h index 2ce310b319421..e535534237a1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h @@ -257,7 +257,8 @@ struct amdgpu_rlc_funcs { void (*stop)(struct amdgpu_device *adev); void (*reset)(struct amdgpu_device *adev); void (*start)(struct amdgpu_device *adev); - void (*update_spm_vmid)(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid); + void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid); bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg); }; @@ -269,6 +270,15 @@ struct amdgpu_rlcg_reg_access_ctrl { uint32_t grbm_cntl; uint32_t grbm_idx; uint32_t spare_int; + + uint32_t vfi_cmd; + uint32_t vfi_stat; + uint32_t vfi_addr; + uint32_t vfi_data; + uint32_t vfi_grbm_cntl; + uint32_t vfi_grbm_idx; + uint32_t vfi_grbm_cntl_data; + uint32_t vfi_grbm_idx_data; }; struct amdgpu_rlc { @@ -310,6 +320,8 @@ struct amdgpu_rlc { u32 save_restore_list_srm_size_bytes; u32 rlc_iram_ucode_size_bytes; u32 rlc_dram_ucode_size_bytes; + u32 rlc_1_iram_ucode_size_bytes; + u32 rlc_1_dram_ucode_size_bytes; u32 rlcp_ucode_size_bytes; u32 rlcv_ucode_size_bytes; u32 global_tap_delays_ucode_size_bytes; @@ -325,6 +337,8 @@ struct amdgpu_rlc { u8 *save_restore_list_srm; u8 *rlc_iram_ucode; u8 *rlc_dram_ucode; + u8 *rlc_1_iram_ucode; + u8 *rlc_1_dram_ucode; u8 *rlcp_ucode; u8 *rlcv_ucode; u8 *global_tap_delays_ucode; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 341beec595375..0eecfaa3a94c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -103,10 +103,8 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, return -EINVAL; } - if (!amdgpu_ctx_priority_is_valid(args->in.priority)) { - WARN(1, "Invalid context priority %d\n", args->in.priority); + if (!amdgpu_ctx_priority_is_valid(args->in.priority)) return -EINVAL; - } switch (args->in.op) { case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index 8b8a04138711c..321310ba2c08e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c @@ -558,6 +558,9 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device *adev, uint32_t instance_id, struct amdgpu_ring *gfx_ring = &sdma_instance->ring; struct amdgpu_ring *page_ring = &sdma_instance->page; + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + mutex_lock(&sdma_instance->engine_reset_mutex); if (!caller_handles_kernel_queues) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h index 34311f32be4c6..2bf365609775a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h @@ -50,6 +50,11 @@ enum amdgpu_sdma_irq { #define NUM_SDMA(x) hweight32(x) +struct amdgpu_sdma_csa_info { + u32 size; + u32 alignment; +}; + struct amdgpu_sdma_funcs { int (*stop_kernel_queue)(struct amdgpu_ring *ring); int (*start_kernel_queue)(struct amdgpu_ring *ring); @@ -65,7 +70,10 @@ struct amdgpu_sdma_instance { struct amdgpu_ring ring; struct amdgpu_ring page; bool burst_nop; - uint32_t aid_id; + union { + uint32_t aid_id; + uint32_t xcc_id; + }; struct amdgpu_bo *sdma_fw_obj; uint64_t sdma_fw_gpu_addr; @@ -123,7 +131,10 @@ struct amdgpu_sdma { int num_instances; uint32_t sdma_mask; - int num_inst_per_aid; + union { + int num_inst_per_aid; + int num_inst_per_xcc; + }; uint32_t srbm_soft_reset; bool has_page_queue; struct ras_common_if *ras_if; @@ -133,6 +144,8 @@ struct amdgpu_sdma { struct list_head reset_callback_list; bool no_user_submission; bool disable_uq; + void (*get_csa_info)(struct amdgpu_device *adev, + struct amdgpu_sdma_csa_info *csa_info); }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c new file mode 100644 index 0000000000000..8f42a77b4b6fb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -0,0 +1,478 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chunming Zhou + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_sem.h" + +#define to_amdgpu_ctx_entity(e) \ + container_of((e), struct amdgpu_ctx_entity, entity) + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem); + +static void amdgpu_sem_core_free(struct kref *kref) +{ + struct amdgpu_sem_core *core = container_of( + kref, struct amdgpu_sem_core, kref); + + dma_fence_put(core->fence); + mutex_destroy(&core->lock); + kfree(core); +} + +static void amdgpu_sem_free(struct kref *kref) +{ + struct amdgpu_sem *sem = container_of( + kref, struct amdgpu_sem, kref); + + kref_put(&sem->base->kref, amdgpu_sem_core_free); + kfree(sem); +} + +static inline void amdgpu_sem_get(struct amdgpu_sem *sem) +{ + if (sem) + kref_get(&sem->kref); +} + +void amdgpu_sem_put(struct amdgpu_sem *sem) +{ + if (sem) + kref_put(&sem->kref, amdgpu_sem_free); +} + +static int amdgpu_sem_release(struct inode *inode, struct file *file) +{ + struct amdgpu_sem_core *core = file->private_data; + + /* set the core->file to null if file got released */ + mutex_lock(&core->lock); + core->file = NULL; + mutex_unlock(&core->lock); + + kref_put(&core->kref, amdgpu_sem_core_free); + return 0; +} + +static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) +{ + return 0; +} + +static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + +static const struct file_operations amdgpu_sem_fops = { + .release = amdgpu_sem_release, + .poll = amdgpu_sem_poll, + .unlocked_ioctl = amdgpu_sem_file_ioctl, + .compat_ioctl = amdgpu_sem_file_ioctl, +}; + + +static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem; + + spin_lock(&fpriv->sem_handles_lock); + + /* Check if we currently have a reference on the object */ + sem = idr_find(&fpriv->sem_handles, handle); + amdgpu_sem_get(sem); + + spin_unlock(&fpriv->sem_handles_lock); + + return sem; +} + +static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void) +{ + struct amdgpu_sem_core *core; + + core = kzalloc(sizeof(*core), GFP_KERNEL); + if (!core) + return NULL; + + kref_init(&core->kref); + mutex_init(&core->lock); + return core; +} + +static struct amdgpu_sem *amdgpu_sem_alloc(void) +{ + struct amdgpu_sem *sem; + + sem = kzalloc(sizeof(*sem), GFP_KERNEL); + if (!sem) + return NULL; + + kref_init(&sem->kref); + INIT_LIST_HEAD(&sem->list); + + return sem; +} + +static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_alloc(); + core = amdgpu_sem_core_alloc(); + if (!sem || !core) { + kfree(sem); + kfree(core); + return -ENOMEM; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, INT_MAX, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handle = ret; + + return 0; +} + +static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv, + u32 handle, struct dma_fence *fence) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + mutex_lock(&core->lock); + dma_fence_put(core->fence); + core->fence = dma_fence_get(fence); + mutex_unlock(&core->lock); + + amdgpu_sem_put(sem); + return 0; +} + +static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct amdgpu_sem *sem; + int ret; + + sem = amdgpu_sem_lookup(fpriv, in->handle); + if (!sem) + return -EINVAL; + + ret = amdgpu_sem_entity_add(fpriv, in, sem); + amdgpu_sem_put(sem); + + return ret; +} + +static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, + int fd, u32 *handle) +{ + struct file *file = fget(fd); + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + if (unlikely(!handle || !fpriv || !file)) + return -EINVAL; + + if (unlikely(file->f_op != &amdgpu_sem_fops)) { + ret = -EINVAL; + goto err_file; + } + + core = file->private_data; + if (unlikely(!core)) { + ret = -EINVAL; + goto err_file; + } + + kref_get(&core->kref); + sem = amdgpu_sem_alloc(); + if (unlikely(!sem)) { + ret = -ENOMEM; + goto err_kref; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + ret = idr_alloc(&fpriv->sem_handles, sem, 1, INT_MAX, GFP_NOWAIT); + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + if (ret < 0) + goto err_sem; + + *handle = ret; + fput(file); + + return 0; + +err_sem: + amdgpu_sem_put(sem); +err_kref: + kref_put(&core->kref, amdgpu_sem_core_free); +err_file: + fput(file); + + return ret; +} + +static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, + u32 handle, int *fd) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int new_fd, ret; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (unlikely(!sem)) + return -EINVAL; + + core = sem->base; + if (unlikely(!core)) { + ret = -EINVAL; + goto err_put_sem; + } + + kref_get(&core->kref); + mutex_lock(&core->lock); + if (!core->file) { + core->file = anon_inode_getfile("sem_file", + &amdgpu_sem_fops, + core, 0); + if (IS_ERR(core->file)) { + mutex_unlock(&core->lock); + ret = PTR_ERR(core->file); + goto err_put_kref; + } + } else { + get_file(core->file); + } + mutex_unlock(&core->lock); + + new_fd = get_unused_fd_flags(O_CLOEXEC); + if (new_fd < 0) { + ret = new_fd; + goto err_put_file; + } + + fd_install(new_fd, core->file); + + *fd = new_fd; + + amdgpu_sem_put(sem); + + return 0; + +err_put_file: + fput(core->file); +err_put_kref: + kref_put(&core->kref, amdgpu_sem_core_free); +err_put_sem: + amdgpu_sem_put(sem); + + return ret; +} + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return; + + spin_lock(&fpriv->sem_handles_lock); + idr_remove(&fpriv->sem_handles, handle); + spin_unlock(&fpriv->sem_handles_lock); + + kref_put(&sem->kref, amdgpu_sem_free); + kref_put(&sem->kref, amdgpu_sem_free); +} + +static struct dma_fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct drm_sched_entity *entity; + struct amdgpu_ctx *ctx; + struct dma_fence *fence; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return NULL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) { + amdgpu_ctx_put(ctx); + return NULL; + } + /* get the last fence of this entity */ + fence = amdgpu_ctx_get_fence(ctx, entity, in->seq); + amdgpu_ctx_put(ctx); + + return fence; +} + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_sem_dep *dep; + struct drm_sched_entity *entity; + struct amdgpu_ctx_entity *centity; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return -EINVAL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) + goto err; + + dep = kzalloc(sizeof(*dep), GFP_KERNEL); + if (!dep) + goto err; + + INIT_LIST_HEAD(&dep->list); + dep->fence = dma_fence_get(sem->base->fence); + + centity = to_amdgpu_ctx_entity(entity); + mutex_lock(¢ity->sem_lock); + list_add(&dep->list, ¢ity->sem_dep_list); + mutex_unlock(¢ity->sem_lock); + +err: + amdgpu_ctx_put(ctx); + return r; +} + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync) +{ + struct amdgpu_sem_dep *dep, *tmp; + struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); + int r = 0; + + if (list_empty(¢ity->sem_dep_list)) + return 0; + + mutex_lock(¢ity->sem_lock); + list_for_each_entry_safe(dep, tmp, ¢ity->sem_dep_list, + list) { + r = amdgpu_sync_fence(sync, dep->fence, GFP_KERNEL); + if (r) + goto err; + dma_fence_put(dep->fence); + list_del_init(&dep->list); + kfree(dep); + } +err: + mutex_unlock(¢ity->sem_lock); + return r; +} + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_sem *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct dma_fence *fence; + int r = 0; + + switch (args->in.op) { + case AMDGPU_SEM_OP_CREATE_SEM: + r = amdgpu_sem_create(fpriv, &args->out.handle); + break; + case AMDGPU_SEM_OP_WAIT_SEM: + r = amdgpu_sem_wait(fpriv, &args->in); + break; + case AMDGPU_SEM_OP_SIGNAL_SEM: + fence = amdgpu_sem_get_fence(fpriv, &args->in); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + return r; + } + r = amdgpu_sem_signal(fpriv, args->in.handle, fence); + dma_fence_put(fence); + break; + case AMDGPU_SEM_OP_IMPORT_SEM: + r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle); + break; + case AMDGPU_SEM_OP_EXPORT_SEM: + r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd); + break; + case AMDGPU_SEM_OP_DESTROY_SEM: + amdgpu_sem_destroy(fpriv, args->in.handle); + break; + default: + r = -EINVAL; + break; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h new file mode 100644 index 0000000000000..dbbb9d4540233 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Chunming Zhou + * + */ + + +#ifndef _LINUX_AMDGPU_SEM_H +#define _LINUX_AMDGPU_SEM_H + +#include +#include +#include +#include +#include + +struct amdgpu_sem_core { + struct file *file; + struct kref kref; + struct dma_fence *fence; + struct mutex lock; +}; + +struct amdgpu_sem_dep { + struct dma_fence *fence; + struct list_head list; +}; + +struct amdgpu_sem { + struct amdgpu_sem_core *base; + struct kref kref; + struct list_head list; +}; + +void amdgpu_sem_put(struct amdgpu_sem *sem); + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync); + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle); + +#endif /* _LINUX_AMDGPU_SEM_H */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h index ec9d12f85f39f..124b13a68f3f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_smuio.h @@ -27,6 +27,7 @@ enum amdgpu_pkg_type { AMDGPU_PKG_TYPE_APU = 2, AMDGPU_PKG_TYPE_CEM = 3, AMDGPU_PKG_TYPE_OAM = 4, + AMDGPU_PKG_TYPE_BB = 5, AMDGPU_PKG_TYPE_UNKNOWN, }; @@ -44,6 +45,8 @@ struct amdgpu_smuio_funcs { u32 (*get_socket_id)(struct amdgpu_device *adev); enum amdgpu_pkg_type (*get_pkg_type)(struct amdgpu_device *adev); bool (*is_host_gpu_xgmi_supported)(struct amdgpu_device *adev); + bool (*is_connected_with_ethernet_switch)(struct amdgpu_device *adev); + bool (*is_custom_hbm_supported)(struct amdgpu_device *adev); u64 (*get_gpu_clock_counter)(struct amdgpu_device *adev); }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index d6ae9974c952e..04afbbfd7bb1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -29,8 +29,6 @@ * Christian König */ -#include - #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_amdkfd.h" @@ -446,11 +444,13 @@ int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job) } dma_fence_get(f); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&job->base, f); if (r) { dma_fence_put(f); return r; } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index d13e64a69e255..eb878eadf8461 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -176,10 +176,10 @@ TRACE_EVENT(amdgpu_cs_ioctl, ), TP_fast_assign( - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u", @@ -199,10 +199,10 @@ TRACE_EVENT(amdgpu_sched_run_job, ), TP_fast_assign( - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("timeline=%s, fence=%llu:%llu, ring_name=%s, num_ibs=%u", @@ -227,7 +227,7 @@ TRACE_EVENT(amdgpu_vm_grab_id, TP_fast_assign( __entry->pasid = vm->pasid; - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = job->vmid; __entry->vm_hub = ring->vm_hub, __entry->pd_addr = job->vm_pd_addr; @@ -421,7 +421,7 @@ TRACE_EVENT(amdgpu_vm_flush, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = vmid; __entry->vm_hub = ring->vm_hub; __entry->pd_addr = pd_addr; @@ -479,7 +479,7 @@ TRACE_EVENT(amdgpu_cleaner_shader, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->seqno = fence->seqno; ), TP_printk("ring=%s, seqno=%Lu", __get_str(ring), __entry->seqno) @@ -553,7 +553,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, sched_job->base.sched->name); __entry->fence = fence; __entry->ctx = fence->context; __entry->seqno = fence->seqno; @@ -583,5 +583,5 @@ TRACE_EVENT(amdgpu_reset_reg_dumps, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu +#define TRACE_INCLUDE_PATH . #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 2b931e855abd9..b07d091379e7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -32,6 +32,9 @@ #include #include +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#endif #include #include #include @@ -61,7 +64,11 @@ #include "amdgpu_res_cursor.h" #include "bif/bif_4_1_d.h" +#ifdef HAVE_MODULE_IMPORT_NS_NEED_A_STRING MODULE_IMPORT_NS("DMA_BUF"); +#else +MODULE_IMPORT_NS(DMA_BUF); +#endif #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) @@ -128,6 +135,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, return; case TTM_PL_VRAM: + case AMDGPU_PL_DGMA: if (!adev->mman.buffer_funcs_enabled) { /* Move to system memory */ amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -154,6 +162,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } break; case TTM_PL_TT: + case AMDGPU_PL_DGMA_IMPORT: case AMDGPU_PL_PREEMPT: default: amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -162,13 +171,49 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, *placement = abo->placement; } +static struct dma_fence * +amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_job *job, u32 num_dw) +{ + struct amdgpu_ring *ring; + + ring = adev->mman.buffer_funcs_ring; + amdgpu_ring_pad_ib(ring, &job->ibs[0]); + WARN_ON(job->ibs[0].length_dw > num_dw); + + lockdep_assert_held(&entity->lock); + + return amdgpu_job_submit(job); +} + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_verify_access - Verify access for a mmap call + * + * @bo: The buffer object to map + * @filp: The file pointer from the process performing the mmap + * + * This is called by ttm_bo_mmap() to verify whether a process + * has the right to mmap a BO to their process space. + */ +static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) +{ + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); + + if (amdgpu_ttm_tt_get_usermm(bo->ttm)) + return -EPERM; + return drm_vma_node_verify_access(&abo->tbo.base.vma_node, + filp->private_data); +} +#endif + /** * amdgpu_ttm_map_buffer - Map memory into the GART windows + * @entity: entity to run the window setup job * @bo: buffer object to map * @mem: memory object to map * @mm_cur: range to map * @window: which GART window to use - * @ring: DMA ring to use for the copy * @tmz: if we should setup a TMZ enabled mapping * @size: in number of bytes to map, out number of bytes mapped * @addr: resulting address inside the MC address space @@ -176,13 +221,14 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, * Setup one of the GART windows to access a specific piece of memory or return * the physical address for local memory. */ -static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, +static int amdgpu_ttm_map_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct ttm_buffer_object *bo, struct ttm_resource *mem, struct amdgpu_res_cursor *mm_cur, - unsigned int window, struct amdgpu_ring *ring, + unsigned int window, bool tmz, uint64_t *size, uint64_t *addr) { - struct amdgpu_device *adev = ring->adev; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); unsigned int offset, num_pages, num_dw, num_bytes; uint64_t src_addr, dst_addr; struct amdgpu_job *job; @@ -215,15 +261,13 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, *size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset); - *addr = adev->gmc.gart_start; - *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * - AMDGPU_GPU_PAGE_SIZE; + *addr = amdgpu_compute_gart_address(&adev->gmc, entity, window); *addr += offset; num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; - r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, + r = amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, &job, @@ -235,13 +279,10 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, src_addr += job->ibs[0].gpu_addr; dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); - dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; + dst_addr += (entity->gart_window_offs[window] >> AMDGPU_GPU_PAGE_SHIFT) * 8; amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); if (tmz) flags |= AMDGPU_PTE_TMZ; @@ -259,13 +300,14 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, amdgpu_gart_map_vram_range(adev, pa, 0, num_pages, flags, cpu_addr); } - dma_fence_put(amdgpu_job_submit(job)); + dma_fence_put(amdgpu_ttm_job_submit(adev, entity, job, num_dw)); return 0; } /** * amdgpu_ttm_copy_mem_to_mem - Helper function for copy * @adev: amdgpu device + * @entity: entity to run the jobs * @src: buffer/address where to read from * @dst: buffer/address where to write to * @size: number of bytes to copy @@ -280,13 +322,13 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, */ __attribute__((nonnull)) static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, const struct amdgpu_copy_mem *src, const struct amdgpu_copy_mem *dst, uint64_t size, bool tmz, struct dma_resv *resv, struct dma_fence **f) { - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct amdgpu_res_cursor src_mm, dst_mm; struct dma_fence *fence = NULL; int r = 0; @@ -302,7 +344,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, amdgpu_res_first(src->mem, src->offset, size, &src_mm); amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (src_mm.remaining) { uint64_t from, to, cur_size, tiling_flags; uint32_t num_type, data_format, max_com, write_compress_disable; @@ -312,13 +354,13 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20); /* Map src to window 0 and dst to window 1. */ - r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, - 0, ring, tmz, &cur_size, &from); + r = amdgpu_ttm_map_buffer(entity, src->bo, src->mem, &src_mm, + 0, tmz, &cur_size, &from); if (r) goto error; - r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, - 1, ring, tmz, &cur_size, &to); + r = amdgpu_ttm_map_buffer(entity, dst->bo, dst->mem, &dst_mm, + 1, tmz, &cur_size, &to); if (r) goto error; @@ -345,8 +387,8 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, write_compress_disable)); } - r = amdgpu_copy_buffer(ring, from, to, cur_size, resv, - &next, false, true, copy_flags); + r = amdgpu_copy_buffer(adev, entity, from, to, cur_size, resv, + &next, true, copy_flags); if (r) goto error; @@ -357,7 +399,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, amdgpu_res_next(&dst_mm, cur_size); } error: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); *f = fence; return r; } @@ -386,10 +428,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, src.offset = 0; dst.offset = 0; - r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, + r = amdgpu_ttm_copy_mem_to_mem(adev, + &adev->mman.move_entity, + &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), - bo->base.resv, &fence); + amdkcl_ttm_resvp(bo), &fence); if (r) goto error; @@ -398,8 +442,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { struct dma_fence *wipe_fence = NULL; - r = amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence, - false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); + r = amdgpu_fill_buffer(&adev->mman.move_entity, + abo, 0, NULL, &wipe_fence, + AMDGPU_KERNEL_JOB_ID_MOVE_BLIT); if (r) { goto error; } else if (wipe_fence) { @@ -499,6 +544,7 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, } abo = ttm_to_amdgpu_bo(bo); + adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -507,6 +553,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, ttm_bo_move_null(bo, new_mem); return 0; } + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + if (old_mem->mem_type == TTM_PL_SYSTEM && (new_mem->mem_type == TTM_PL_TT || new_mem->mem_type == AMDGPU_PL_PREEMPT)) { @@ -609,7 +659,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, case AMDGPU_PL_PREEMPT: break; case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; + case AMDGPU_PL_DGMA: + mem->bus.offset = (mem->start << PAGE_SHIFT) + + amdgpu_ttm_domain_start(adev, mem->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); if (adev->mman.aper_base_kaddr && mem->placement & TTM_PL_FLAG_CONTIGUOUS) @@ -631,6 +684,17 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, mem->bus.is_iomem = true; mem->bus.caching = ttm_uncached; break; + case AMDGPU_PL_DGMA_IMPORT: + { + struct amdgpu_bo *abo; + + abo = ttm_to_amdgpu_bo(mem->bo); + mem->bus.addr = abo->dgma_addr; + mem->bus.offset = abo->dgma_import_base; + mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; + break; + } default: return -EINVAL; } @@ -643,6 +707,10 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_res_cursor cursor; + if (bo->resource->mem_type == AMDGPU_PL_DGMA || + bo->resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + return (bo->resource->bus.offset >> PAGE_SHIFT) + page_offset; + amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor); @@ -670,6 +738,12 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) return adev->gmc.gart_start; case TTM_PL_VRAM: return adev->gmc.vram_start; + case AMDGPU_PL_DGMA: + if (adev->direct_gma.dgma_bo) + return amdgpu_bo_gpu_offset(adev->direct_gma.dgma_bo); + fallthrough; + case AMDGPU_PL_DGMA_IMPORT: + return 0; } return 0; @@ -678,6 +752,13 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) /* * TTM backend functions. */ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +struct amdgpu_ttm_gup_task_list { + struct list_head list; + struct task_struct *task; +}; +#endif + struct amdgpu_ttm_tt { struct ttm_tt ttm; struct drm_gem_object *gobj; @@ -686,12 +767,19 @@ struct amdgpu_ttm_tt { struct task_struct *usertask; uint32_t userflags; bool bound; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spinlock_t guptasklock; + struct list_head guptasks; + atomic_t mmu_invalidations; + uint32_t last_set_pages; +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ int32_t pool_id; }; #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) #ifdef CONFIG_DRM_AMDGPU_USERPTR +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update @@ -744,9 +832,89 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, return r; } +#else +/* + * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR + * pointer to memory + * + * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos(). + * This provides a wrapper around the get_user_pages() call to provide + * device accessible pages that back user memory. + */ +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +{ + struct ttm_tt *ttm = bo->tbo.ttm; + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct mm_struct *mm = gtt->usertask->mm; + unsigned int flags = 0; + unsigned pinned = 0; + int r; -#endif + if (!mm) /* Happens during process shutdown */ + return -ESRCH; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + flags |= FOLL_WRITE; + + down_read(&mm->mmap_sem); + + if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { + /* + * check that we only use anonymous memory to prevent problems + * with writeback + */ + unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; + struct vm_area_struct *vma; + + vma = find_vma(mm, gtt->userptr); + if (!vma || vma->vm_file || vma->vm_end < end) { + up_read(&mm->mmap_sem); + return -EPERM; + } + } + + /* loop enough times using contiguous pages of memory */ + do { + unsigned num_pages = ttm->num_pages - pinned; + uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; + struct page **p = pages + pinned; + struct amdgpu_ttm_gup_task_list guptask; + + guptask.task = current; + spin_lock(>t->guptasklock); + list_add(&guptask.list, >t->guptasks); + spin_unlock(>t->guptasklock); + + if (mm == current->mm) + r = get_user_pages(userptr, num_pages, flags, p); + else + r = kcl_get_user_pages_remote(gtt->usertask, + mm, userptr, num_pages, + flags, p, NULL, NULL); + + spin_lock(>t->guptasklock); + list_del(&guptask.list); + spin_unlock(>t->guptasklock); + + if (r < 0) + goto release_pages; + + pinned += r; + + } while (pinned < ttm->num_pages); + + up_read(&mm->mmap_sem); + return 0; +release_pages: + release_pages(pages, pinned); + up_read(&mm->mmap_sem); + return r; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif /* CONFIG_DRM_AMDGPU_USERPTR */ + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. * @@ -762,6 +930,52 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *r ttm->pages[i] = range ? hmm_pfn_to_page(range->hmm_range.hmm_pfns[i]) : NULL; } +#else +/** + * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. + * + * Called by amdgpu_cs_list_validate(). This creates the page list + * that backs user memory and will ultimately be mapped into the device + * address space. + */ +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + gtt->last_set_pages = atomic_read(>t->mmu_invalidations); + for (i = 0; i < ttm->num_pages; ++i) { + if (ttm->pages[i]) + put_page(ttm->pages[i]); + + ttm->pages[i] = pages ? pages[i] : NULL; + } +} + +/** + * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty + * + * Called while unpinning userptr pages + */ +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + for (i = 0; i < ttm->num_pages; ++i) { + struct page *page = ttm->pages[i]; + + if (!page) + continue; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + set_page_dirty(page); + + mark_page_accessed(page); + } +} +#endif + /* * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages * @@ -821,7 +1035,15 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, /* unmap the pages mapped to the device */ dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED sg_free_table(ttm->sg); +#else + /* mark the pages as dirty */ + amdgpu_ttm_tt_mark_user_pages(ttm); + + sg_free_table(ttm->sg); +#endif } /* @@ -839,25 +1061,15 @@ static void amdgpu_ttm_gart_bind_gfx9_mqd(struct amdgpu_device *adev, int num_xcc = max(1U, adev->gfx.num_xcc_per_xcp); uint64_t page_idx, pages_per_xcc; int i; - uint64_t ctrl_flags = AMDGPU_PTE_MTYPE_VG10(flags, AMDGPU_MTYPE_NC); pages_per_xcc = total_pages; do_div(pages_per_xcc, num_xcc); for (i = 0, page_idx = 0; i < num_xcc; i++, page_idx += pages_per_xcc) { - /* MQD page: use default flags */ - amdgpu_gart_bind(adev, + amdgpu_gart_map_gfx9_mqd(adev, gtt->offset + (page_idx << PAGE_SHIFT), - 1, >t->ttm.dma_address[page_idx], flags); - /* - * Ctrl pages - modify the memory type to NC (ctrl_flags) from - * the second page of the BO onward. - */ - amdgpu_gart_bind(adev, - gtt->offset + ((page_idx + 1) << PAGE_SHIFT), - pages_per_xcc - 1, - >t->ttm.dma_address[page_idx + 1], - ctrl_flags); + pages_per_xcc, >t->ttm.dma_address[page_idx], + flags); } } @@ -909,6 +1121,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, return r; } } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) if (!ttm->sg) { struct dma_buf_attachment *attach; struct sg_table *sgt; @@ -920,6 +1134,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, ttm->sg = sgt; } +#endif drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, ttm->num_pages); @@ -1032,11 +1247,14 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, if (gtt->userptr) { amdgpu_ttm_tt_unpin_userptr(bdev, ttm); } else if (ttm->sg && drm_gem_is_imported(gtt->gobj)) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) struct dma_buf_attachment *attach; attach = gtt->gobj->import_attach; dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); ttm->sg = NULL; +#endif } if (!gtt->bound) @@ -1062,6 +1280,86 @@ static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, kfree(gtt); } +/** + * amdgpu_ttm_mmio_remap_alloc_sgt - build an sg_table for MMIO_REMAP I/O aperture + * @adev: amdgpu device providing the remap BAR base (adev->rmmio_remap.bus_addr) + * @res: TTM resource of the BO to export; expected to live in AMDGPU_PL_MMIO_REMAP + * @dev: importing device to map for (typically @attach->dev in dma-buf paths) + * @dir: DMA data direction for the importer (passed to dma_map_resource()) + * @sgt: output; on success, set to a newly allocated sg_table describing the I/O span + * + * The HDP flush page (AMDGPU_PL_MMIO_REMAP) is a fixed hardware I/O window in a PCI + * BAR—there are no struct pages to back it. Importers still need a DMA address list, + * so we synthesize a minimal sg_table and populate it from dma_map_resource(), not + * from pages. Using the common amdgpu_res_cursor walker keeps the offset/size math + * consistent with other TTM/manager users. + * + * - @res is assumed to be a small, contiguous I/O region (typically a single 4 KiB + * page) in AMDGPU_PL_MMIO_REMAP. Callers should validate placement before calling. + * - The sg entry is created with sg_set_page(sg, NULL, …) to reflect I/O space. + * - The mapping uses DMA_ATTR_SKIP_CPU_SYNC because this is MMIO, not cacheable RAM. + * - Peer reachability / p2pdma policy checks must be done by the caller. + * + * Return: + * * 0 on success, with *@sgt set to a valid table that must be freed via + * amdgpu_ttm_mmio_remap_free_sgt(). + * * -ENOMEM if allocation of the sg_table fails. + * * -EIO if dma_map_resource() fails. + * + */ +int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev, + struct ttm_resource *res, + struct device *dev, + enum dma_data_direction dir, + struct sg_table **sgt) +{ + struct amdgpu_res_cursor cur; + dma_addr_t dma; + resource_size_t phys; + struct scatterlist *sg; + int r; + + /* Walk the resource once; MMIO_REMAP is expected to be contiguous+small. */ + amdgpu_res_first(res, 0, res->size, &cur); + + /* Translate byte offset in the remap window into a host physical BAR address. */ + phys = adev->rmmio_remap.bus_addr + cur.start; + + /* Build a single-entry sg_table mapped as I/O (no struct page backing). */ + *sgt = kzalloc(sizeof(**sgt), GFP_KERNEL); + if (!*sgt) + return -ENOMEM; + r = sg_alloc_table(*sgt, 1, GFP_KERNEL); + if (r) { + kfree(*sgt); + return r; + } + sg = (*sgt)->sgl; + sg_set_page(sg, NULL, cur.size, 0); /* WHY: I/O space → no pages */ + + dma = dma_map_resource(dev, phys, cur.size, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (dma_mapping_error(dev, dma)) { + sg_free_table(*sgt); + kfree(*sgt); + return -EIO; + } + sg_dma_address(sg) = dma; + sg_dma_len(sg) = cur.size; + return 0; +} + +void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev, + enum dma_data_direction dir, + struct sg_table *sgt) +{ + struct scatterlist *sg = sgt->sgl; + + dma_unmap_resource(dev, sg_dma_address(sg), sg_dma_len(sg), + dir, DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(sgt); +} + /** * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO * @@ -1237,6 +1535,13 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, gtt->usertask = current->group_leader; get_task_struct(gtt->usertask); +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spin_lock_init(>t->guptasklock); + INIT_LIST_HEAD(>t->guptasks); + atomic_set(>t->mmu_invalidations, 0); + gtt->last_set_pages = 0; +#endif + return 0; } @@ -1256,6 +1561,7 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) return gtt->usertask->mm; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an * address range for the current task. @@ -1295,6 +1601,77 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) return true; } +#else +/* + * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an + * address range for the current task. + * + */ +bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, + unsigned long end, unsigned long *userptr) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct amdgpu_ttm_gup_task_list *entry; + unsigned long size; + + if (gtt == NULL || !gtt->userptr) + return false; + + /* Return false if no part of the ttm_tt object lies within + * the range + */ + size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; + if (gtt->userptr > end || gtt->userptr + size <= start) + return false; + + /* Search the lists of tasks that hold this mapping and see + * if current is one of them. If it is return false. + */ + spin_lock(>t->guptasklock); + list_for_each_entry(entry, >t->guptasks, list) { + if (entry->task == current) { + spin_unlock(>t->guptasklock); + return false; + } + } + spin_unlock(>t->guptasklock); + + atomic_inc(>t->mmu_invalidations); + + if (userptr) + *userptr = gtt->userptr; + + return true; +} + +/** + * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated? + */ +bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, + int *last_invalidated) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + int prev_invalidated = *last_invalidated; + + *last_invalidated = atomic_read(>t->mmu_invalidations); + return prev_invalidated != *last_invalidated; +} + +/** + * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object + * been invalidated since the last time they've been set? + */ +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL || !gtt->userptr) + return false; + + return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ + /* * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? */ @@ -1354,6 +1731,9 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, { uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); + if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + flags |= AMDGPU_PTE_SYSTEM; + flags |= adev->gart.gart_pte_flags; flags |= AMDGPU_PTE_READABLE; @@ -1393,7 +1773,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * If true, then return false as any KFD process needs all its BOs to * be resident to run successfully */ - dma_resv_for_each_fence(&resv_cursor, bo->base.resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, f) { if (amdkfd_fence_check_mm(f, current->mm) && !(place->flags & TTM_PL_FLAG_CONTIGUOUS)) @@ -1478,7 +1858,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, memcpy(adev->mman.sdma_access_ptr, buf, len); num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); - r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, + r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, AMDGPU_IB_POOL_DELAYED, &job, @@ -1486,7 +1866,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, if (r) goto out; - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&adev->mman.default_entity.lock); amdgpu_res_first(abo->tbo.resource, offset, len, &src_mm); src_addr = amdgpu_ttm_domain_start(adev, bo->resource->mem_type) + src_mm.start; @@ -1497,11 +1877,8 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo, amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, PAGE_SIZE, 0); - amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - - fence = amdgpu_job_submit(job); - mutex_unlock(&adev->mman.gtt_window_lock); + fence = amdgpu_ttm_job_submit(adev, &adev->mman.default_entity, job, num_dw); + mutex_unlock(&adev->mman.default_entity.lock); if (!dma_fence_wait_timeout(fence, false, adev->sdma_timeout)) r = -ETIMEDOUT; @@ -1578,6 +1955,9 @@ static struct ttm_device_funcs amdgpu_bo_driver = { .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, .move = &amdgpu_bo_move, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .verify_access = &amdgpu_verify_access, +#endif .delete_mem_notify = &amdgpu_bo_delete_mem_notify, .release_notify = &amdgpu_bo_release_notify, .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, @@ -1744,7 +2124,13 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))) reserve_size = max(reserve_size, (uint32_t)280 << 20); - else if (!reserve_size) + else if (!adev->bios && + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { + if (hweight32(adev->aid_mask) == 1) + reserve_size = max(reserve_size, (uint32_t)128 << 20); + else + reserve_size = max(reserve_size, (uint32_t)144 << 20); + } else if (!reserve_size) reserve_size = DISCOVERY_TMR_OFFSET; if (mem_train_support) { @@ -1776,6 +2162,101 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } +static int amdgpu_direct_gma_init(struct amdgpu_device *adev) +{ + struct amdgpu_bo *abo; + struct amdgpu_bo_param bp; + unsigned long size; + int r; + + if (amdgpu_direct_gma_size > 0) { + struct iommu_domain *dom = iommu_get_domain_for_dev(adev->dev); + if (dom && dom->type != IOMMU_DOMAIN_IDENTITY) { + DRM_INFO("IOMMU is enabled and not in pass through mode, disable direct GMA\n"); + amdgpu_direct_gma_size = 0; + } + } + + if (amdgpu_direct_gma_size == 0) + return 0; + + size = (unsigned long)amdgpu_direct_gma_size << 20; + + memset(&bp, 0, sizeof(bp)); + bp.size = size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_TOP_DOWN; + bp.type = ttm_bo_type_kernel; + bp.resv = NULL; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); + + /* reserve in visible vram */ + r = amdgpu_bo_create(adev, &bp, &abo); + if (unlikely(r)) + goto error_out; + + r = amdgpu_bo_reserve(abo, false); + if (unlikely(r)) + goto error_free; + + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + amdgpu_bo_unreserve(abo); + if (unlikely(r)) + goto error_free; + + adev->direct_gma.dgma_bo = abo; + + /* reserve in gtt */ + atomic64_add(size, &adev->gart_pin_size); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA, + false, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_put_node; + + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, + false, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_release_mm; + + DRM_INFO("%dMB VRAM/GTT reserved for Direct GMA\n", amdgpu_direct_gma_size); + return 0; + +error_release_mm: + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + +error_put_node: + atomic64_sub(size, &adev->gart_pin_size); +error_free: + amdgpu_bo_unref(&abo); + +error_out: + amdgpu_direct_gma_size = 0; + memset(&adev->direct_gma, 0, sizeof(adev->direct_gma)); + DRM_ERROR("Fail to enable Direct GMA\n"); + return r; +} + +static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) +{ + int r; + + if (amdgpu_direct_gma_size == 0) + return; + + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT); + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + + r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); + if (r == 0) { + amdgpu_bo_unpin(adev->direct_gma.dgma_bo); + amdgpu_bo_unreserve(adev->direct_gma.dgma_bo); + } + amdgpu_bo_unref(&adev->direct_gma.dgma_bo); + atomic64_sub((u64)amdgpu_direct_gma_size << 20, &adev->gart_pin_size); +} + static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) { int i; @@ -1812,10 +2293,10 @@ static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) } /** - * amdgpu_ttm_mmio_remap_bo_init - Allocate the singleton 4K MMIO_REMAP BO + * amdgpu_ttm_alloc_mmio_remap_bo - Allocate the singleton MMIO_REMAP BO * @adev: amdgpu device * - * Allocates a one-page (4K) GEM BO in AMDGPU_GEM_DOMAIN_MMIO_REMAP when the + * Allocates a global BO with backing AMDGPU_PL_MMIO_REMAP when the * hardware exposes a remap base (adev->rmmio_remap.bus_addr) and the host * PAGE_SIZE is <= AMDGPU_GPU_PAGE_SIZE (4K). The BO is created as a regular * GEM object (amdgpu_bo_create). @@ -1824,46 +2305,143 @@ static void amdgpu_ttm_pools_fini(struct amdgpu_device *adev) * * 0 on success or intentional skip (feature not present/unsupported) * * negative errno on allocation failure */ -static int amdgpu_ttm_mmio_remap_bo_init(struct amdgpu_device *adev) +static int amdgpu_ttm_alloc_mmio_remap_bo(struct amdgpu_device *adev) { + struct ttm_operation_ctx ctx = { false, false }; + struct ttm_placement placement; + struct ttm_buffer_object *tbo; + struct ttm_place placements; struct amdgpu_bo_param bp; + struct ttm_resource *tmp; int r; /* Skip if HW doesn't expose remap, or if PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE (4K). */ if (!adev->rmmio_remap.bus_addr || PAGE_SIZE > AMDGPU_GPU_PAGE_SIZE) return 0; + /* + * Allocate a BO first and then move it to AMDGPU_PL_MMIO_REMAP. + * The initial TTM resource assigned by amdgpu_bo_create() is + * replaced below with a fixed MMIO_REMAP placement. + */ memset(&bp, 0, sizeof(bp)); - - /* Create exactly one GEM BO in the MMIO_REMAP domain. */ - bp.type = ttm_bo_type_device; /* userspace-mappable GEM */ - bp.size = AMDGPU_GPU_PAGE_SIZE; /* 4K */ + bp.type = ttm_bo_type_device; + bp.size = AMDGPU_GPU_PAGE_SIZE; bp.byte_align = AMDGPU_GPU_PAGE_SIZE; - bp.domain = AMDGPU_GEM_DOMAIN_MMIO_REMAP; + bp.domain = 0; bp.flags = 0; bp.resv = NULL; bp.bo_ptr_size = sizeof(struct amdgpu_bo); - r = amdgpu_bo_create(adev, &bp, &adev->rmmio_remap.bo); if (r) return r; + r = amdgpu_bo_reserve(adev->rmmio_remap.bo, true); + if (r) + goto err_unref; + + tbo = &adev->rmmio_remap.bo->tbo; + + /* + * MMIO_REMAP is a fixed I/O placement (AMDGPU_PL_MMIO_REMAP). + */ + placement.num_placement = 1; + placement.placement = &placements; + placements.fpfn = 0; + placements.lpfn = 0; + placements.mem_type = AMDGPU_PL_MMIO_REMAP; + placements.flags = 0; + /* Force the BO into the fixed MMIO_REMAP placement */ + r = ttm_bo_mem_space(tbo, &placement, &tmp, &ctx); + if (unlikely(r)) + goto err_unlock; + + ttm_resource_free(tbo, &tbo->resource); + ttm_bo_assign_mem(tbo, tmp); + ttm_bo_pin(tbo); + + amdgpu_bo_unreserve(adev->rmmio_remap.bo); return 0; + +err_unlock: + amdgpu_bo_unreserve(adev->rmmio_remap.bo); + +err_unref: + amdgpu_bo_unref(&adev->rmmio_remap.bo); + adev->rmmio_remap.bo = NULL; + return r; } /** - * amdgpu_ttm_mmio_remap_bo_fini - Free the singleton MMIO_REMAP BO + * amdgpu_ttm_free_mmio_remap_bo - Free the singleton MMIO_REMAP BO * @adev: amdgpu device * * Frees the kernel-owned MMIO_REMAP BO if it was allocated by * amdgpu_ttm_mmio_remap_bo_init(). */ -static void amdgpu_ttm_mmio_remap_bo_fini(struct amdgpu_device *adev) +static void amdgpu_ttm_free_mmio_remap_bo(struct amdgpu_device *adev) { + if (!adev->rmmio_remap.bo) + return; + + if (!amdgpu_bo_reserve(adev->rmmio_remap.bo, true)) { + ttm_bo_unpin(&adev->rmmio_remap.bo->tbo); + amdgpu_bo_unreserve(adev->rmmio_remap.bo); + } + + /* + * At this point we rely on normal DRM teardown ordering: + * no new user ioctls can access the global MMIO_REMAP BO + * once TTM teardown begins. + */ amdgpu_bo_unref(&adev->rmmio_remap.bo); adev->rmmio_remap.bo = NULL; } +static int amdgpu_ttm_buffer_entity_init(struct amdgpu_gtt_mgr *mgr, + struct amdgpu_ttm_buffer_entity *entity, + enum drm_sched_priority prio, + struct drm_gpu_scheduler **scheds, + int num_schedulers, + u32 num_gart_windows) +{ + int i, r, num_pages; + + r = drm_sched_entity_init(&entity->base, prio, scheds, num_schedulers, NULL); + if (r) + return r; + + mutex_init(&entity->lock); + + if (ARRAY_SIZE(entity->gart_window_offs) < num_gart_windows) + return -EINVAL; + if (num_gart_windows == 0) + return 0; + + num_pages = num_gart_windows * AMDGPU_GTT_MAX_TRANSFER_SIZE; + r = amdgpu_gtt_mgr_alloc_entries(mgr, &entity->gart_node, num_pages, + DRM_MM_INSERT_BEST); + if (r) { + drm_sched_entity_destroy(&entity->base); + return r; + } + + for (i = 0; i < num_gart_windows; i++) { + entity->gart_window_offs[i] = + amdgpu_gtt_node_to_byte_offset(&entity->gart_node) + + i * AMDGPU_GTT_MAX_TRANSFER_SIZE * PAGE_SIZE; + } + + return 0; +} + +static void amdgpu_ttm_buffer_entity_fini(struct amdgpu_gtt_mgr *mgr, + struct amdgpu_ttm_buffer_entity *entity) +{ + amdgpu_gtt_mgr_free_entries(mgr, &entity->gart_node); + drm_sched_entity_destroy(&entity->base); +} + /* * amdgpu_ttm_init - Init the memory management (ttm) as well as various * gtt/vram related fields. @@ -1878,8 +2456,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) uint64_t gtt_size; int r; - mutex_init(&adev->mman.gtt_window_lock); - dma_set_max_seg_size(adev->dev, UINT_MAX); /* No others user of address space so set it to 0 */ r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, @@ -1988,7 +2564,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_DEBUG_DRIVER("Skipped stolen memory reservation\n"); } - dev_info(adev->dev, "amdgpu: %uM of VRAM memory ready\n", + dev_info(adev->dev, " %uM of VRAM memory ready\n", (unsigned int)(adev->gmc.real_vram_size / (1024 * 1024))); /* Compute GTT size, either based on TTM limit @@ -2007,6 +2583,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) gtt_size = configured_size; } + /* reserve for DGMA import domain */ + gtt_size -= (uint64_t)amdgpu_direct_gma_size << 20; /* Initialize GTT memory pool */ r = amdgpu_gtt_mgr_init(adev, gtt_size); @@ -2014,9 +2592,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) dev_err(adev->dev, "Failed initializing GTT heap.\n"); return r; } - dev_info(adev->dev, "amdgpu: %uM of GTT memory ready.\n", + dev_info(adev->dev, " %uM of GTT memory ready.\n", (unsigned int)(gtt_size / (1024 * 1024))); + amdgpu_direct_gma_init(adev); if (adev->flags & AMD_IS_APU) { if (adev->gmc.real_vram_size < gtt_size) adev->apu_prefer_gtt = true; @@ -2043,8 +2622,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) return r; } - /* Allocate the singleton MMIO_REMAP BO (4K) if supported */ - r = amdgpu_ttm_mmio_remap_bo_init(adev); + /* Allocate the singleton MMIO_REMAP BO if supported */ + r = amdgpu_ttm_alloc_mmio_remap_bo(adev); if (r) return r; @@ -2077,7 +2656,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) AMDGPU_GEM_DOMAIN_GTT, &adev->mman.sdma_access_bo, NULL, &adev->mman.sdma_access_ptr)) - DRM_WARN("Debug VRAM access will use slowpath MM access\n"); + drm_warn(adev_to_drm(adev), + "Debug VRAM access will use slowpath MM access\n"); return 0; } @@ -2111,7 +2691,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) amdgpu_bo_free_kernel(&adev->mman.sdma_access_bo, NULL, &adev->mman.sdma_access_ptr); - amdgpu_ttm_mmio_remap_bo_fini(adev); + amdgpu_ttm_free_mmio_remap_bo(adev); amdgpu_ttm_fw_reserve_vram_fini(adev); amdgpu_ttm_drv_reserve_vram_fini(adev); @@ -2124,6 +2704,8 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + drain_workqueue(adev->mman.bdev.wq); + amdgpu_direct_gma_fini(adev); if (!adev->gmc.is_app_apu) amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); @@ -2137,7 +2719,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_MMIO_REMAP); ttm_device_fini(&adev->mman.bdev); adev->mman.initialized = false; - dev_info(adev->dev, "amdgpu: ttm finalized\n"); + dev_info(adev->dev, " ttm finalized\n"); } /** @@ -2163,30 +2745,49 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) struct amdgpu_ring *ring; struct drm_gpu_scheduler *sched; + if (!adev->mman.buffer_funcs_ring || !adev->mman.buffer_funcs_ring->sched.ready) { + dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use"); + return; + } + ring = adev->mman.buffer_funcs_ring; sched = &ring->sched; - r = drm_sched_entity_init(&adev->mman.high_pr, - DRM_SCHED_PRIORITY_KERNEL, &sched, - 1, NULL); - if (r) { + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.default_entity, + DRM_SCHED_PRIORITY_KERNEL, + &sched, 1, 0); + if (r < 0) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", - r); + "Failed setting up TTM entity (%d)\n", r); return; } - r = drm_sched_entity_init(&adev->mman.low_pr, - DRM_SCHED_PRIORITY_NORMAL, &sched, - 1, NULL); - if (r) { + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.clear_entity, + DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, 1); + if (r < 0) { dev_err(adev->dev, - "Failed setting up TTM BO move entity (%d)\n", - r); - goto error_free_entity; + "Failed setting up TTM BO clear entity (%d)\n", r); + goto error_free_default_entity; + } + + r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr, + &adev->mman.move_entity, + DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, 2); + if (r < 0) { + dev_err(adev->dev, + "Failed setting up TTM BO move entity (%d)\n", r); + goto error_free_clear_entity; } } else { - drm_sched_entity_destroy(&adev->mman.high_pr); - drm_sched_entity_destroy(&adev->mman.low_pr); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entity); + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.move_entity); /* Drop all the old fences since re-creating the scheduler entities * will allocate new contexts. */ @@ -2203,25 +2804,25 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) return; -error_free_entity: - drm_sched_entity_destroy(&adev->mman.high_pr); +error_free_clear_entity: + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.clear_entity); +error_free_default_entity: + amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr, + &adev->mman.default_entity); } static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, - bool direct_submit, + struct amdgpu_ttm_buffer_entity *entity, unsigned int num_dw, struct dma_resv *resv, bool vm_needs_flush, struct amdgpu_job **job, - bool delayed, u64 k_job_id) + u64 k_job_id) { - enum amdgpu_ib_pool_type pool = direct_submit ? - AMDGPU_IB_POOL_DIRECT : - AMDGPU_IB_POOL_DELAYED; + enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED; int r; - struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr : - &adev->mman.high_pr; - r = amdgpu_job_alloc_with_ib(adev, entity, + r = amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4, pool, job, k_job_id); if (r) @@ -2233,27 +2834,103 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, adev->gart.bo); (*job)->vm_needs_flush = true; } +#ifndef HAVE_STRUCT_XARRAY + return 0; +#else if (!resv) return 0; return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, DMA_RESV_USAGE_BOOKKEEP); +#endif } -int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vma->vm_private_data; +#else +static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vmf->vma->vm_private_data; +#endif + vm_fault_t ret; + + ret = ttm_bo_vm_reserve(bo, vmf); + if (ret) + return ret; + + ret = amdgpu_bo_fault_reserve_notify(bo); + if (ret) + goto unlock; + + ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) + return ret; + +unlock: + dma_resv_unlock(amdkcl_ttm_resvp(bo)); + return ret; +} + +static struct vm_operations_struct amdgpu_ttm_vm_ops = { + .fault = amdgpu_ttm_fault, + .open = ttm_bo_vm_open, + .close = ttm_bo_vm_close, + .access = ttm_bo_vm_access +}; + +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *file_priv = filp->private_data; + struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); + int r; + + r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); + if (unlikely(r != 0)) + return r; + + vma->vm_ops = &amdgpu_ttm_vm_ops; + return 0; +} + +/* This function should be called with mm lock held */ +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + if (vma->vm_ops == &amdgpu_ttm_vm_ops) + return true; + + return false; +} +#else +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma) +{ + pr_err_once("bo from address verification not supported\n"); + + return false; +} +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + +int amdgpu_copy_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, - struct dma_fence **fence, bool direct_submit, + struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags) { - struct amdgpu_device *adev = ring->adev; unsigned int num_loops, num_dw; + struct amdgpu_ring *ring; struct amdgpu_job *job; uint32_t max_bytes; unsigned int i; int r; - if (!direct_submit && !ring->sched.ready) { + ring = adev->mman.buffer_funcs_ring; + + if (!ring->sched.ready) { dev_err(adev->dev, "Trying to move memory with ring turned off.\n"); return -EINVAL; @@ -2262,11 +2939,11 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, max_bytes = adev->mman.buffer_funcs->copy_max_bytes; num_loops = DIV_ROUND_UP(byte_count, max_bytes); num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); - r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw, - resv, vm_needs_flush, &job, false, + r = amdgpu_ttm_prepare_job(adev, entity, num_dw, + resv, vm_needs_flush, &job, AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER); if (r) - return r; + goto error_free; for (i = 0; i < num_loops; i++) { uint32_t cur_size_in_bytes = min(byte_count, max_bytes); @@ -2278,16 +2955,9 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, byte_count -= cur_size_in_bytes; } - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - if (direct_submit) - r = amdgpu_job_submit_direct(job, ring, fence); - else - *fence = amdgpu_job_submit(job); - if (r) - goto error_free; + *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); - return r; + return 0; error_free: amdgpu_job_free(job); @@ -2295,14 +2965,15 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, return r; } -static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, +static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint32_t src_data, uint64_t dst_addr, uint32_t byte_count, struct dma_resv *resv, struct dma_fence **fence, - bool vm_needs_flush, bool delayed, + bool vm_needs_flush, u64 k_job_id) { - struct amdgpu_device *adev = ring->adev; unsigned int num_loops, num_dw; struct amdgpu_job *job; uint32_t max_bytes; @@ -2312,8 +2983,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, max_bytes = adev->mman.buffer_funcs->fill_max_bytes; num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes); num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8); - r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush, - &job, delayed, k_job_id); + r = amdgpu_ttm_prepare_job(adev, entity, num_dw, resv, + vm_needs_flush, &job, k_job_id); if (r) return r; @@ -2327,9 +2998,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data, byte_count -= cur_size; } - amdgpu_ring_pad_ib(ring, &job->ibs[0]); - WARN_ON(job->ibs[0].length_dw > num_dw); - *fence = amdgpu_job_submit(job); + *fence = amdgpu_ttm_job_submit(adev, entity, job, num_dw); return 0; } @@ -2349,7 +3018,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, struct dma_fence **fence) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_ttm_buffer_entity *entity; struct amdgpu_res_cursor cursor; u64 addr; int r = 0; @@ -2360,11 +3029,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, if (!fence) return -EINVAL; + entity = &adev->mman.clear_entity; *fence = dma_fence_get_stub(); amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (cursor.remaining) { struct dma_fence *next = NULL; u64 size; @@ -2377,13 +3047,13 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, /* Never clear more than 256MiB at once to avoid timeouts */ size = min(cursor.size, 256ULL << 20); - r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &cursor, - 1, ring, false, &size, &addr); + r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &cursor, + 0, false, &size, &addr); if (r) goto err; - r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv, - &next, true, true, + r = amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv, + &next, true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); if (r) goto err; @@ -2394,20 +3064,19 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, amdgpu_res_next(&cursor, size); } err: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); return r; } -int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **f, - bool delayed, - u64 k_job_id) +int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, + uint32_t src_data, + struct dma_resv *resv, + struct dma_fence **f, + u64 k_job_id) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; struct dma_fence *fence = NULL; struct amdgpu_res_cursor dst; int r; @@ -2420,7 +3089,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); - mutex_lock(&adev->mman.gtt_window_lock); + mutex_lock(&entity->lock); while (dst.remaining) { struct dma_fence *next; uint64_t cur_size, to; @@ -2428,13 +3097,14 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, /* Never fill more than 256MiB at once to avoid timeouts */ cur_size = min(dst.size, 256ULL << 20); - r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst, - 1, ring, false, &cur_size, &to); + r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &dst, + 0, false, &cur_size, &to); if (r) goto error; - r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv, - &next, true, delayed, k_job_id); + r = amdgpu_ttm_fill_mem(adev, entity, + src_data, to, cur_size, resv, + &next, true, k_job_id); if (r) goto error; @@ -2444,7 +3114,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, amdgpu_res_next(&dst, cur_size); } error: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); if (f) *f = dma_fence_get(fence); dma_fence_put(fence); @@ -2482,7 +3152,6 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) } #if defined(CONFIG_DEBUG_FS) - static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) { struct amdgpu_device *adev = m->private; @@ -2490,7 +3159,31 @@ static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) return ttm_pool_debugfs(&adev->mman.bdev.pool, m); } +static int amdgpu_mm_dgma_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_dgma_import_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA_IMPORT); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); /* * amdgpu_ttm_vram_read - Linear read access to VRAM @@ -2701,6 +3394,7 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) &amdgpu_ttm_iomem_fops); debugfs_create_file("ttm_page_pool", 0444, root, adev, &amdgpu_ttm_page_pool_fops); + ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), root, "amdgpu_vram_mm"); @@ -2717,5 +3411,11 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) AMDGPU_PL_OA), root, "amdgpu_oa_mm"); + if (amdgpu_direct_gma_size) { + debugfs_create_file("amdgpu_dgma_mm", 0444, root, adev, + &amdgpu_mm_dgma_table_fops); + debugfs_create_file("amdgpu_dgma_import_mm", 0444, root, adev, + &amdgpu_mm_dgma_import_table_fops); + } #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 577ee04ce0bf1..adaf520927478 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -29,6 +29,7 @@ #include #include "amdgpu_vram_mgr.h" #include "amdgpu_hmm.h" +#include "amdgpu_gmc.h" #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) @@ -36,10 +37,12 @@ #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5) +#define __AMDGPU_PL_LAST (TTM_PL_PRIV + 5) #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6) +#define AMDGPU_PL_DGMA (TTM_PL_PRIV + 7) +#define AMDGPU_PL_DGMA_IMPORT (TTM_PL_PRIV + 8) -#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 -#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 +#define AMDGPU_GTT_MAX_TRANSFER_SIZE 1024 extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; @@ -52,6 +55,20 @@ struct amdgpu_gtt_mgr { spinlock_t lock; }; +struct amdgpu_ttm_buffer_entity { + struct drm_sched_entity base; + struct mutex lock; + struct drm_mm_node gart_node; + u64 gart_window_offs[2]; +}; + +struct amdgpu_dgma_import_mgr { + struct ttm_resource_manager manager; + struct drm_mm mm; + spinlock_t lock; + atomic64_t available; +}; + struct amdgpu_mman { struct ttm_device bdev; struct ttm_pool *ttm_pools; @@ -63,14 +80,14 @@ struct amdgpu_mman { struct amdgpu_ring *buffer_funcs_ring; bool buffer_funcs_enabled; - struct mutex gtt_window_lock; - /* High priority scheduler entity for buffer moves */ - struct drm_sched_entity high_pr; - /* Low priority scheduler entity for VRAM clearing */ - struct drm_sched_entity low_pr; + /* @default_entity: for workarounds, has no gart windows */ + struct amdgpu_ttm_buffer_entity default_entity; + struct amdgpu_ttm_buffer_entity clear_entity; + struct amdgpu_ttm_buffer_entity move_entity; struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; + struct amdgpu_dgma_import_mgr dgma_import_mgr; struct ttm_resource_manager preempt_mgr; uint64_t stolen_vga_size; @@ -137,6 +154,12 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); +int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr, + struct drm_mm_node *mm_node, + u64 num_pages, + enum drm_mm_insert_mode mode); +void amdgpu_gtt_mgr_free_entries(struct amdgpu_gtt_mgr *mgr, + struct drm_mm_node *mm_node); uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); @@ -163,37 +186,81 @@ int amdgpu_ttm_init(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable); -int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, +bool amdgpu_vma_is_amdgpu_bo(struct vm_area_struct *vma); + +int amdgpu_copy_buffer(struct amdgpu_device *adev, + struct amdgpu_ttm_buffer_entity *entity, + uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, - struct dma_fence **fence, bool direct_submit, + struct dma_fence **fence, bool vm_needs_flush, uint32_t copy_flags); int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, struct dma_resv *resv, struct dma_fence **fence); -int amdgpu_fill_buffer(struct amdgpu_bo *bo, - uint32_t src_data, - struct dma_resv *resv, - struct dma_fence **fence, - bool delayed, - u64 k_job_id); +int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity, + struct amdgpu_bo *bo, + uint32_t src_data, + struct dma_resv *resv, + struct dma_fence **f, + u64 k_job_id); + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); +#endif int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range); #else +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages); +#endif +#else +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct amdgpu_hmm_range *range) { return -EPERM; } +#else +static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +{ + return -EPERM; +} #endif +#endif + +/** + * amdgpu_compute_gart_address() - Returns GART address of an entity's window + * @gmc: The &struct amdgpu_gmc instance to use + * @entity: The &struct amdgpu_ttm_buffer_entity owning the GART window + * @index: The window to use (must be 0 or 1) + */ +static inline u64 amdgpu_compute_gart_address(struct amdgpu_gmc *gmc, + struct amdgpu_ttm_buffer_entity *entity, + int index) +{ + return gmc->gart_start + entity->gart_window_offs[index]; +} + +/** + * amdgpu_gtt_node_to_byte_offset() - Returns a byte offset of a gtt node + */ +static inline u64 amdgpu_gtt_node_to_byte_offset(const struct drm_mm_node *gtt_node) +{ + return gtt_node->start * (u64)PAGE_SIZE; +} +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range); +#else +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages); +#endif int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, uint64_t *user_addr); int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, @@ -202,9 +269,14 @@ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, unsigned long end, unsigned long *userptr); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +#else bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, int *last_invalidated); -bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm); +#endif bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, @@ -213,4 +285,13 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); +int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev, + struct ttm_resource *res, + struct device *dev, + enum dma_data_direction dir, + struct sg_table **sgt); +void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev, + enum dma_data_direction dir, + struct sg_table *sgt); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c index e96f24e9ad571..6d9e96fabd581 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c @@ -166,6 +166,8 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2); const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 = container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3); + const struct rlc_firmware_header_v2_5 *rlc_hdr_v2_5 = + container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_5, v2_2); switch (version_minor) { case 0: @@ -287,6 +289,26 @@ void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes)); break; + case 5: + /* rlc_hdr v2_5 */ + DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_size_bytes)); + DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_offset_bytes)); + DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_size_bytes)); + DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_offset_bytes)); + /* rlc_hdr v2_5 */ + DRM_DEBUG("rlc_1_iram_ucode_size_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_size_bytes)); + DRM_DEBUG("rlc_1_iram_ucode_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_offset_bytes)); + DRM_DEBUG("rlc_1_dram_ucode_size_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_size_bytes)); + DRM_DEBUG("rlc_1_dram_ucode_offset_bytes: %u\n", + le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_offset_bytes)); + break; default: DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); break; @@ -631,6 +653,10 @@ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id) return "RLC_IRAM"; case AMDGPU_UCODE_ID_RLC_DRAM: return "RLC_DRAM"; + case AMDGPU_UCODE_ID_RLC_IRAM_1: + return "RLC_IRAM_1"; + case AMDGPU_UCODE_ID_RLC_DRAM_1: + return "RLC_DRAM_1"; case AMDGPU_UCODE_ID_RLC_G: return "RLC_G"; case AMDGPU_UCODE_ID_RLC_P: @@ -911,6 +937,14 @@ static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; ucode_addr = adev->gfx.rlc.rlc_dram_ucode; break; + case AMDGPU_UCODE_ID_RLC_IRAM_1: + ucode->ucode_size = adev->gfx.rlc.rlc_1_iram_ucode_size_bytes; + ucode_addr = adev->gfx.rlc.rlc_1_iram_ucode; + break; + case AMDGPU_UCODE_ID_RLC_DRAM_1: + ucode->ucode_size = adev->gfx.rlc.rlc_1_dram_ucode_size_bytes; + ucode_addr = adev->gfx.rlc.rlc_1_dram_ucode; + break; case AMDGPU_UCODE_ID_RLC_P: ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes; ucode_addr = adev->gfx.rlc.rlcp_ucode; @@ -1116,7 +1150,7 @@ int amdgpu_ucode_create_bo(struct amdgpu_device *adev) if ((adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) && (adev->firmware.load_type != AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)) { amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, - (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ? + (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, &adev->firmware.fw_buf, &adev->firmware.fw_buf_mc, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 6349aad6da35b..f316776fe950a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -300,6 +300,15 @@ struct rlc_firmware_header_v2_4 { uint32_t se3_tap_delays_ucode_offset_bytes; }; +/* version_major=2, version_minor=5 */ +struct rlc_firmware_header_v2_5 { + struct rlc_firmware_header_v2_2 v2_2; + uint32_t rlc_1_iram_ucode_size_bytes; + uint32_t rlc_1_iram_ucode_offset_bytes; + uint32_t rlc_1_dram_ucode_size_bytes; + uint32_t rlc_1_dram_ucode_offset_bytes; +}; + /* version_major=1, version_minor=0 */ struct sdma_firmware_header_v1_0 { struct common_firmware_header header; @@ -449,6 +458,7 @@ union amdgpu_firmware_header { struct rlc_firmware_header_v2_2 rlc_v2_2; struct rlc_firmware_header_v2_3 rlc_v2_3; struct rlc_firmware_header_v2_4 rlc_v2_4; + struct rlc_firmware_header_v2_5 rlc_v2_5; struct sdma_firmware_header_v1_0 sdma; struct sdma_firmware_header_v1_1 sdma_v1_1; struct sdma_firmware_header_v2_0 sdma_v2_0; @@ -512,6 +522,8 @@ enum AMDGPU_UCODE_ID { AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM, AMDGPU_UCODE_ID_RLC_IRAM, AMDGPU_UCODE_ID_RLC_DRAM, + AMDGPU_UCODE_ID_RLC_IRAM_1, + AMDGPU_UCODE_ID_RLC_DRAM_1, AMDGPU_UCODE_ID_RLC_P, AMDGPU_UCODE_ID_RLC_V, AMDGPU_UCODE_ID_RLC_G, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index 3f0b0e9af4f34..1be722ba6c9ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -398,6 +398,17 @@ int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, return 0; } +int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct ras_ih_info ih_info = {0}; + + ih_info.block = RAS_BLOCK_ID__UMC; + amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); + return 0; +} + int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, uint64_t err_addr, uint64_t retired_page, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h index 28dff750c47e3..8494a55ebf76c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h @@ -161,6 +161,9 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry); +int amdgpu_umc_uniras_process_ecc_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry); int amdgpu_umc_fill_error_record(struct ras_err_data *err_data, uint64_t err_addr, uint64_t retired_page, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c index 58b26c78b6425..611d67b7ff02f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c @@ -148,6 +148,69 @@ amdgpu_userq_detect_and_reset_queues(struct amdgpu_userq_mgr *uq_mgr) return r; } +static void amdgpu_userq_hang_detect_work(struct work_struct *work) +{ + struct amdgpu_usermode_queue *queue = container_of(work, + struct amdgpu_usermode_queue, + hang_detect_work.work); + struct dma_fence *fence; + struct amdgpu_userq_mgr *uq_mgr; + + if (!queue->userq_mgr) + return; + + uq_mgr = queue->userq_mgr; + fence = READ_ONCE(queue->hang_detect_fence); + /* Fence already signaled – no action needed */ + if (!fence || dma_fence_is_signaled(fence)) + return; + + mutex_lock(&uq_mgr->userq_mutex); + amdgpu_userq_detect_and_reset_queues(uq_mgr); + mutex_unlock(&uq_mgr->userq_mutex); +} + +/* + * Start hang detection for a user queue fence. A delayed work will be scheduled + * to check if the fence is still pending after the timeout period. +*/ +void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue) +{ + struct amdgpu_device *adev; + unsigned long timeout_ms; + + if (!queue || !queue->userq_mgr || !queue->userq_mgr->adev) + return; + + adev = queue->userq_mgr->adev; + /* Determine timeout based on queue type */ + switch (queue->queue_type) { + case AMDGPU_RING_TYPE_GFX: + timeout_ms = adev->gfx_timeout; + break; + case AMDGPU_RING_TYPE_COMPUTE: + timeout_ms = adev->compute_timeout; + break; + case AMDGPU_RING_TYPE_SDMA: + timeout_ms = adev->sdma_timeout; + break; + default: + timeout_ms = adev->gfx_timeout; + break; + } + + /* Store the fence to monitor and schedule hang detection */ + WRITE_ONCE(queue->hang_detect_fence, queue->last_fence); + schedule_delayed_work(&queue->hang_detect_work, + msecs_to_jiffies(timeout_ms)); +} + +static void amdgpu_userq_init_hang_detect_work(struct amdgpu_usermode_queue *queue) +{ + INIT_DELAYED_WORK(&queue->hang_detect_work, amdgpu_userq_hang_detect_work); + queue->hang_detect_fence = NULL; +} + static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, struct amdgpu_bo_va_mapping *va_map, u64 addr) { @@ -166,7 +229,8 @@ static int amdgpu_userq_buffer_va_list_add(struct amdgpu_usermode_queue *queue, return 0; } -int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, +int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, + struct amdgpu_usermode_queue *queue, u64 addr, u64 expected_size) { struct amdgpu_bo_va_mapping *va_map; @@ -271,10 +335,9 @@ static int amdgpu_userq_buffer_vas_list_cleanup(struct amdgpu_device *adev, return r; } -static int -amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int amdgpu_userq_preempt_helper(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; @@ -282,7 +345,7 @@ amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr, int r = 0; if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { - r = userq_funcs->preempt(uq_mgr, queue); + r = userq_funcs->preempt(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; found_hung_queue = true; @@ -297,17 +360,16 @@ amdgpu_userq_preempt_helper(struct amdgpu_userq_mgr *uq_mgr, return r; } -static int -amdgpu_userq_restore_helper(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int amdgpu_userq_restore_helper(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; int r = 0; if (queue->state == AMDGPU_USERQ_STATE_PREEMPTED) { - r = userq_funcs->restore(uq_mgr, queue); + r = userq_funcs->restore(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; } else { @@ -318,10 +380,9 @@ amdgpu_userq_restore_helper(struct amdgpu_userq_mgr *uq_mgr, return r; } -static int -amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int amdgpu_userq_unmap_helper(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; @@ -330,7 +391,7 @@ amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, if ((queue->state == AMDGPU_USERQ_STATE_MAPPED) || (queue->state == AMDGPU_USERQ_STATE_PREEMPTED)) { - r = userq_funcs->unmap(uq_mgr, queue); + r = userq_funcs->unmap(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; found_hung_queue = true; @@ -345,17 +406,16 @@ amdgpu_userq_unmap_helper(struct amdgpu_userq_mgr *uq_mgr, return r; } -static int -amdgpu_userq_map_helper(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int amdgpu_userq_map_helper(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *userq_funcs = adev->userq_funcs[queue->queue_type]; int r = 0; if (queue->state == AMDGPU_USERQ_STATE_UNMAPPED) { - r = userq_funcs->map(uq_mgr, queue); + r = userq_funcs->map(queue); if (r) { queue->state = AMDGPU_USERQ_STATE_HUNG; amdgpu_userq_detect_and_reset_queues(uq_mgr); @@ -367,10 +427,9 @@ amdgpu_userq_map_helper(struct amdgpu_userq_mgr *uq_mgr, return r; } -static int -amdgpu_userq_wait_for_last_fence(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int amdgpu_userq_wait_for_last_fence(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct dma_fence *f = queue->last_fence; int ret = 0; @@ -387,11 +446,9 @@ amdgpu_userq_wait_for_last_fence(struct amdgpu_userq_mgr *uq_mgr, return ret; } -static void -amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue, - int queue_id) +static void amdgpu_userq_cleanup(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; const struct amdgpu_userq_funcs *uq_funcs = adev->userq_funcs[queue->queue_type]; @@ -400,10 +457,9 @@ amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, /* Drop the userq reference. */ amdgpu_userq_buffer_vas_list_cleanup(adev, queue); - uq_funcs->mqd_destroy(uq_mgr, queue); + uq_funcs->mqd_destroy(queue); amdgpu_userq_fence_driver_free(queue); /* Use interrupt-safe locking since IRQ handlers may access these XArrays */ - xa_erase_irq(&uq_mgr->userq_mgr_xa, (unsigned long)queue_id); xa_erase_irq(&adev->userq_doorbell_xa, queue->doorbell_index); queue->userq_mgr = NULL; list_del(&queue->userq_va_list); @@ -412,27 +468,20 @@ amdgpu_userq_cleanup(struct amdgpu_userq_mgr *uq_mgr, up_read(&adev->reset_domain->sem); } -static struct amdgpu_usermode_queue * -amdgpu_userq_find(struct amdgpu_userq_mgr *uq_mgr, int qid) -{ - return xa_load(&uq_mgr->userq_mgr_xa, qid); -} - void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr) { - struct amdgpu_eviction_fence *ev_fence; + struct dma_fence *ev_fence; retry: /* Flush any pending resume work to create ev_fence */ flush_delayed_work(&uq_mgr->resume_work); mutex_lock(&uq_mgr->userq_mutex); - spin_lock(&evf_mgr->ev_fence_lock); - ev_fence = evf_mgr->ev_fence; - spin_unlock(&evf_mgr->ev_fence_lock); - if (!ev_fence || dma_fence_is_signaled(&ev_fence->base)) { + ev_fence = amdgpu_evf_mgr_get_fence(evf_mgr); + if (dma_fence_is_signaled(ev_fence)) { + dma_fence_put(ev_fence); mutex_unlock(&uq_mgr->userq_mutex); /* * Looks like there was no pending resume work, @@ -441,6 +490,7 @@ amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *uq_mgr, schedule_delayed_work(&uq_mgr->resume_work, 0); goto retry; } + dma_fence_put(ev_fence); } int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, @@ -550,6 +600,13 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, goto unpin_bo; } + /* Validate doorbell_offset is within the doorbell BO */ + if ((u64)db_info->doorbell_offset * db_size + db_size > + amdgpu_bo_size(db_obj->obj)) { + r = -EINVAL; + goto unpin_bo; + } + index = amdgpu_doorbell_index_on_bar(uq_mgr->adev, db_obj->obj, db_info->doorbell_offset, db_size); drm_dbg_driver(adev_to_drm(uq_mgr->adev), @@ -567,42 +624,46 @@ amdgpu_userq_get_doorbell_index(struct amdgpu_userq_mgr *uq_mgr, } static int -amdgpu_userq_destroy(struct drm_file *filp, int queue_id) +amdgpu_userq_destroy(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue) { - struct amdgpu_fpriv *fpriv = filp->driver_priv; - struct amdgpu_userq_mgr *uq_mgr = &fpriv->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; - struct amdgpu_usermode_queue *queue; int r = 0; cancel_delayed_work_sync(&uq_mgr->resume_work); + + /* Cancel any pending hang detection work and cleanup */ + cancel_delayed_work_sync(&queue->hang_detect_work); + mutex_lock(&uq_mgr->userq_mutex); + queue->hang_detect_fence = NULL; + amdgpu_userq_wait_for_last_fence(queue); - queue = amdgpu_userq_find(uq_mgr, queue_id); - if (!queue) { - drm_dbg_driver(adev_to_drm(uq_mgr->adev), "Invalid queue id to destroy\n"); - mutex_unlock(&uq_mgr->userq_mutex); - return -EINVAL; - } - amdgpu_userq_wait_for_last_fence(uq_mgr, queue); r = amdgpu_bo_reserve(queue->db_obj.obj, true); if (!r) { amdgpu_bo_unpin(queue->db_obj.obj); amdgpu_bo_unreserve(queue->db_obj.obj); } amdgpu_bo_unref(&queue->db_obj.obj); + + r = amdgpu_bo_reserve(queue->wptr_obj.obj, true); + if (!r) { + amdgpu_bo_unpin(queue->wptr_obj.obj); + amdgpu_bo_unreserve(queue->wptr_obj.obj); + } + amdgpu_bo_unref(&queue->wptr_obj.obj); + atomic_dec(&uq_mgr->userq_count[queue->queue_type]); #if defined(CONFIG_DEBUG_FS) debugfs_remove_recursive(queue->debugfs_queue); #endif amdgpu_userq_detect_and_reset_queues(uq_mgr); - r = amdgpu_userq_unmap_helper(uq_mgr, queue); + r = amdgpu_userq_unmap_helper(queue); /*TODO: It requires a reset for userq hw unmap error*/ if (unlikely(r != AMDGPU_USERQ_STATE_UNMAPPED)) { drm_warn(adev_to_drm(uq_mgr->adev), "trying to destroy a HW mapping userq\n"); queue->state = AMDGPU_USERQ_STATE_HUNG; } - amdgpu_userq_cleanup(uq_mgr, queue, queue_id); + amdgpu_userq_cleanup(queue); mutex_unlock(&uq_mgr->userq_mutex); pm_runtime_put_autosuspend(adev_to_drm(adev)->dev); @@ -610,6 +671,37 @@ amdgpu_userq_destroy(struct drm_file *filp, int queue_id) return r; } +static void amdgpu_userq_kref_destroy(struct kref *kref) +{ + int r; + struct amdgpu_usermode_queue *queue = + container_of(kref, struct amdgpu_usermode_queue, refcount); + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; + + r = amdgpu_userq_destroy(uq_mgr, queue); + if (r) + drm_file_err(uq_mgr->file, "Failed to destroy usermode queue %d\n", r); +} + +struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid) +{ + struct amdgpu_usermode_queue *queue; + + xa_lock(&uq_mgr->userq_xa); + queue = xa_load(&uq_mgr->userq_xa, qid); + if (queue) + kref_get(&queue->refcount); + xa_unlock(&uq_mgr->userq_xa); + + return queue; +} + +void amdgpu_userq_put(struct amdgpu_usermode_queue *queue) +{ + if (queue) + kref_put(&queue->refcount, amdgpu_userq_kref_destroy); +} + static int amdgpu_userq_priority_permit(struct drm_file *filp, int priority) { @@ -625,46 +717,6 @@ static int amdgpu_userq_priority_permit(struct drm_file *filp, return -EACCES; } -#if defined(CONFIG_DEBUG_FS) -static int amdgpu_mqd_info_read(struct seq_file *m, void *unused) -{ - struct amdgpu_usermode_queue *queue = m->private; - struct amdgpu_bo *bo; - int r; - - if (!queue || !queue->mqd.obj) - return -EINVAL; - - bo = amdgpu_bo_ref(queue->mqd.obj); - r = amdgpu_bo_reserve(bo, true); - if (r) { - amdgpu_bo_unref(&bo); - return -EINVAL; - } - - seq_printf(m, "queue_type: %d\n", queue->queue_type); - seq_printf(m, "mqd_gpu_address: 0x%llx\n", amdgpu_bo_gpu_offset(queue->mqd.obj)); - - amdgpu_bo_unreserve(bo); - amdgpu_bo_unref(&bo); - - return 0; -} - -static int amdgpu_mqd_info_open(struct inode *inode, struct file *file) -{ - return single_open(file, amdgpu_mqd_info_read, inode->i_private); -} - -static const struct file_operations amdgpu_mqd_info_fops = { - .owner = THIS_MODULE, - .open = amdgpu_mqd_info_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; -#endif - static int amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) { @@ -674,7 +726,6 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) const struct amdgpu_userq_funcs *uq_funcs; struct amdgpu_usermode_queue *queue; struct amdgpu_db_info db_info; - char *queue_name; bool skip_map_queue; u32 qid; uint64_t index; @@ -729,61 +780,41 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) db_info.db_obj = &queue->db_obj; db_info.doorbell_offset = args->in.doorbell_offset; + queue->userq_mgr = uq_mgr; /* Validate the userq virtual address.*/ - if (amdgpu_userq_input_va_validate(queue, args->in.queue_va, args->in.queue_size) || - amdgpu_userq_input_va_validate(queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || - amdgpu_userq_input_va_validate(queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { + if (amdgpu_userq_input_va_validate(adev, queue, args->in.queue_va, args->in.queue_size) || + amdgpu_userq_input_va_validate(adev, queue, args->in.rptr_va, AMDGPU_GPU_PAGE_SIZE) || + amdgpu_userq_input_va_validate(adev, queue, args->in.wptr_va, AMDGPU_GPU_PAGE_SIZE)) { r = -EINVAL; - kfree(queue); - goto unlock; + goto free_queue; } /* Convert relative doorbell offset into absolute doorbell index */ index = amdgpu_userq_get_doorbell_index(uq_mgr, &db_info, filp); if (index == (uint64_t)-EINVAL) { drm_file_err(uq_mgr->file, "Failed to get doorbell for queue\n"); - kfree(queue); r = -EINVAL; - goto unlock; + goto free_queue; } queue->doorbell_index = index; +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&queue->fence_drv_xa, XA_FLAGS_ALLOC); +#else + idr_init(&queue->fence_drv_idr); + spin_lock_init(&queue->fence_drv_lock); +#endif r = amdgpu_userq_fence_driver_alloc(adev, queue); if (r) { drm_file_err(uq_mgr->file, "Failed to alloc fence driver\n"); - goto unlock; + goto free_queue; } - r = uq_funcs->mqd_create(uq_mgr, &args->in, queue); + r = uq_funcs->mqd_create(queue, &args->in); if (r) { drm_file_err(uq_mgr->file, "Failed to create Queue\n"); - amdgpu_userq_fence_driver_free(queue); - kfree(queue); - goto unlock; - } - - /* Wait for mode-1 reset to complete */ - down_read(&adev->reset_domain->sem); - r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); - if (r) { - kfree(queue); - up_read(&adev->reset_domain->sem); - goto unlock; - } - - r = xa_alloc(&uq_mgr->userq_mgr_xa, &qid, queue, XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); - if (r) { - drm_file_err(uq_mgr->file, "Failed to allocate a queue id\n"); - amdgpu_userq_fence_driver_free(queue); - uq_funcs->mqd_destroy(uq_mgr, queue); - kfree(queue); - r = -ENOMEM; - up_read(&adev->reset_domain->sem); - goto unlock; + goto clean_fence_driver; } - up_read(&adev->reset_domain->sem); - queue->userq_mgr = uq_mgr; /* don't map the queue if scheduling is halted */ if (adev->userq_halt_for_enforce_isolation && @@ -793,33 +824,55 @@ amdgpu_userq_create(struct drm_file *filp, union drm_amdgpu_userq *args) else skip_map_queue = false; if (!skip_map_queue) { - r = amdgpu_userq_map_helper(uq_mgr, queue); + r = amdgpu_userq_map_helper(queue); if (r) { drm_file_err(uq_mgr->file, "Failed to map Queue\n"); - xa_erase(&uq_mgr->userq_mgr_xa, qid); - amdgpu_userq_fence_driver_free(queue); - uq_funcs->mqd_destroy(uq_mgr, queue); - kfree(queue); - goto unlock; + down_read(&adev->reset_domain->sem); + goto clean_mqd; } } - queue_name = kasprintf(GFP_KERNEL, "queue-%d", qid); - if (!queue_name) { + /* drop this refcount during queue destroy */ + kref_init(&queue->refcount); + + /* Wait for mode-1 reset to complete */ + down_read(&adev->reset_domain->sem); + + r = xa_alloc(&uq_mgr->userq_xa, &qid, queue, + XA_LIMIT(1, AMDGPU_MAX_USERQ_COUNT), GFP_KERNEL); + if (r) { + if (!skip_map_queue) + amdgpu_userq_unmap_helper(queue); + r = -ENOMEM; - goto unlock; + goto clean_mqd; } -#if defined(CONFIG_DEBUG_FS) - /* Queue dentry per client to hold MQD information */ - queue->debugfs_queue = debugfs_create_dir(queue_name, filp->debugfs_client); - debugfs_create_file("mqd_info", 0444, queue->debugfs_queue, queue, &amdgpu_mqd_info_fops); -#endif - kfree(queue_name); + r = xa_err(xa_store_irq(&adev->userq_doorbell_xa, index, queue, GFP_KERNEL)); + if (r) { + xa_erase(&uq_mgr->userq_xa, qid); + if (!skip_map_queue) + amdgpu_userq_unmap_helper(queue); + + goto clean_mqd; + } + up_read(&adev->reset_domain->sem); + + amdgpu_debugfs_userq_init(filp, queue, qid); + amdgpu_userq_init_hang_detect_work(queue); args->out.queue_id = qid; atomic_inc(&uq_mgr->userq_count[queue->queue_type]); + mutex_unlock(&uq_mgr->userq_mutex); + return 0; +clean_mqd: + uq_funcs->mqd_destroy(queue); + up_read(&adev->reset_domain->sem); +clean_fence_driver: + amdgpu_userq_fence_driver_free(queue); +free_queue: + kfree(queue); unlock: mutex_unlock(&uq_mgr->userq_mutex); @@ -860,6 +913,17 @@ static int amdgpu_userq_input_args_validate(struct drm_device *dev, drm_file_err(filp, "invalidate userq queue va or size\n"); return -EINVAL; } + + if (!is_power_of_2(args->in.queue_size)) { + drm_file_err(filp, "Queue size must be a power of 2\n"); + return -EINVAL; + } + + if (args->in.queue_size < AMDGPU_GPU_PAGE_SIZE) { + drm_file_err(filp, "Queue size smaller than AMDGPU_GPU_PAGE_SIZE\n"); + return -EINVAL; + } + if (!args->in.wptr_va || !args->in.rptr_va) { drm_file_err(filp, "invalidate userq queue rptr or wptr\n"); return -EINVAL; @@ -902,7 +966,9 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { union drm_amdgpu_userq *args = data; - int r; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_usermode_queue *queue; + int r = 0; if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; @@ -917,11 +983,16 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, drm_file_err(filp, "Failed to create usermode queue\n"); break; - case AMDGPU_USERQ_OP_FREE: - r = amdgpu_userq_destroy(filp, args->in.queue_id); - if (r) - drm_file_err(filp, "Failed to destroy usermode queue\n"); + case AMDGPU_USERQ_OP_FREE: { + xa_lock(&fpriv->userq_mgr.userq_xa); + queue = __xa_erase(&fpriv->userq_mgr.userq_xa, args->in.queue_id); + xa_unlock(&fpriv->userq_mgr.userq_xa); + if (!queue) + return -ENOENT; + + amdgpu_userq_put(queue); break; + } default: drm_dbg_driver(dev, "Invalid user queue op specified: %d\n", args->in.op); @@ -938,8 +1009,9 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) unsigned long queue_id; int ret = 0, r; + mutex_lock(&uq_mgr->userq_mutex); /* Resume all the queues for this process */ - xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { + xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { if (!amdgpu_userq_buffer_vas_mapped(queue)) { drm_file_err(uq_mgr->file, @@ -948,10 +1020,12 @@ amdgpu_userq_restore_all(struct amdgpu_userq_mgr *uq_mgr) continue; } - r = amdgpu_userq_restore_helper(uq_mgr, queue); + r = amdgpu_userq_restore_helper(queue); if (r) ret = r; + } + mutex_unlock(&uq_mgr->userq_mutex); if (ret) drm_file_err(uq_mgr->file, "Failed to map all the queues\n"); @@ -1010,21 +1084,28 @@ static int amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) { struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + struct amdgpu_device *adev = uq_mgr->adev; + struct amdgpu_vm *vm = &fpriv->vm; + struct amdgpu_bo_va *bo_va; + struct drm_exec exec; + int ret; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool invalidated = false, new_addition = false; struct ttm_operation_ctx ctx = { true, false }; - struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_hmm_range *range; - struct amdgpu_vm *vm = &fpriv->vm; unsigned long key, tmp_key; - struct amdgpu_bo_va *bo_va; struct amdgpu_bo *bo; - struct drm_exec exec; struct xarray xa; - int ret; xa_init(&xa); retry_lock: +#else + dev_warn_once(adev->dev, "HMM is not functional; falling back to legacy path. " + "Legacy path is untested and may be unstable. " + "Please enable HMM or refer to documentation for supported kernels.\n"); + WARN_ON_ONCE(1); +#endif drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); drm_exec_until_all_locked(&exec) { ret = amdgpu_vm_lock_pd(vm, &exec, 1); @@ -1051,6 +1132,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) goto unlock_all; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (invalidated) { xa_for_each(&xa, tmp_key, range) { bo = range->bo; @@ -1068,11 +1150,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) } invalidated = false; } +#endif ret = amdgpu_vm_handle_moved(adev, vm, NULL); if (ret) goto unlock_all; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED key = 0; /* Validate User Ptr BOs */ list_for_each_entry(bo_va, &vm->done, base.vm_status) { @@ -1118,6 +1202,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) new_addition = false; goto retry_lock; } +#endif ret = amdgpu_vm_update_pdes(adev, vm, false); if (ret) @@ -1132,12 +1217,13 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) dma_fence_wait(bo_va->last_pt_update, false); dma_fence_wait(vm->last_update, false); - ret = amdgpu_eviction_fence_replace_fence(&fpriv->evf_mgr, &exec); + ret = amdgpu_evf_mgr_rearm(&fpriv->evf_mgr, &exec); if (ret) drm_file_err(uq_mgr->file, "Failed to replace eviction fence\n"); unlock_all: drm_exec_fini(&exec); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED xa_for_each(&xa, tmp_key, range) { if (!range) continue; @@ -1145,6 +1231,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr) amdgpu_hmm_range_free(range); } xa_destroy(&xa); +#endif return ret; } @@ -1152,26 +1239,25 @@ static void amdgpu_userq_restore_worker(struct work_struct *work) { struct amdgpu_userq_mgr *uq_mgr = work_to_uq_mgr(work, resume_work.work); struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); + struct dma_fence *ev_fence; int ret; - flush_delayed_work(&fpriv->evf_mgr.suspend_work); - - mutex_lock(&uq_mgr->userq_mutex); + ev_fence = amdgpu_evf_mgr_get_fence(&fpriv->evf_mgr); + if (!dma_fence_is_signaled(ev_fence)) + goto put_fence; ret = amdgpu_userq_vm_validate(uq_mgr); if (ret) { drm_file_err(uq_mgr->file, "Failed to validate BOs to restore\n"); - goto unlock; + goto put_fence; } ret = amdgpu_userq_restore_all(uq_mgr); - if (ret) { + if (ret) drm_file_err(uq_mgr->file, "Failed to restore all queues\n"); - goto unlock; - } -unlock: - mutex_unlock(&uq_mgr->userq_mutex); +put_fence: + dma_fence_put(ev_fence); } static int @@ -1183,8 +1269,8 @@ amdgpu_userq_evict_all(struct amdgpu_userq_mgr *uq_mgr) amdgpu_userq_detect_and_reset_queues(uq_mgr); /* Try to unmap all the queues in this process ctx */ - xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { - r = amdgpu_userq_preempt_helper(uq_mgr, queue); + xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { + r = amdgpu_userq_preempt_helper(queue); if (r) ret = r; } @@ -1218,15 +1304,17 @@ amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) unsigned long queue_id; int ret; - xa_for_each(&uq_mgr->userq_mgr_xa, queue_id, queue) { + xa_for_each(&uq_mgr->userq_xa, queue_id, queue) { struct dma_fence *f = queue->last_fence; if (!f || dma_fence_is_signaled(f)) continue; + ret = dma_fence_wait_timeout(f, true, msecs_to_jiffies(100)); if (ret <= 0) { drm_file_err(uq_mgr->file, "Timed out waiting for fence=%llu:%llu\n", f->context, f->seqno); + return -ETIMEDOUT; } } @@ -1235,11 +1323,8 @@ amdgpu_userq_wait_for_signal(struct amdgpu_userq_mgr *uq_mgr) } void -amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_eviction_fence *ev_fence) +amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr) { - struct amdgpu_fpriv *fpriv = uq_mgr_to_fpriv(uq_mgr); - struct amdgpu_eviction_fence_mgr *evf_mgr = &fpriv->evf_mgr; struct amdgpu_device *adev = uq_mgr->adev; int ret; @@ -1252,23 +1337,13 @@ amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, if (ret) dev_err(adev->dev, "Failed to evict userqueue\n"); - /* Signal current eviction fence */ - amdgpu_eviction_fence_signal(evf_mgr, ev_fence); - - if (evf_mgr->fd_closing) { - cancel_delayed_work_sync(&uq_mgr->resume_work); - return; - } - - /* Schedule a resume work */ - schedule_delayed_work(&uq_mgr->resume_work, 0); } int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, struct amdgpu_device *adev) { mutex_init(&userq_mgr->userq_mutex); - xa_init_flags(&userq_mgr->userq_mgr_xa, XA_FLAGS_ALLOC); + xa_init_flags(&userq_mgr->userq_xa, XA_FLAGS_ALLOC); userq_mgr->adev = adev; userq_mgr->file = file_priv; @@ -1276,23 +1351,31 @@ int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *f return 0; } +void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr) +{ + cancel_delayed_work_sync(&userq_mgr->resume_work); +} + void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr) { struct amdgpu_usermode_queue *queue; - unsigned long queue_id; + unsigned long queue_id = 0; - cancel_delayed_work_sync(&userq_mgr->resume_work); + for (;;) { + xa_lock(&userq_mgr->userq_xa); + queue = xa_find(&userq_mgr->userq_xa, &queue_id, ULONG_MAX, + XA_PRESENT); + if (queue) + __xa_erase(&userq_mgr->userq_xa, queue_id); + xa_unlock(&userq_mgr->userq_xa); - mutex_lock(&userq_mgr->userq_mutex); - amdgpu_userq_detect_and_reset_queues(userq_mgr); - xa_for_each(&userq_mgr->userq_mgr_xa, queue_id, queue) { - amdgpu_userq_wait_for_last_fence(userq_mgr, queue); - amdgpu_userq_unmap_helper(userq_mgr, queue); - amdgpu_userq_cleanup(userq_mgr, queue, queue_id); + if (!queue) + break; + + amdgpu_userq_put(queue); } - xa_destroy(&userq_mgr->userq_mgr_xa); - mutex_unlock(&userq_mgr->userq_mutex); + xa_destroy(&userq_mgr->userq_xa); mutex_destroy(&userq_mgr->userq_mutex); } @@ -1313,9 +1396,9 @@ int amdgpu_userq_suspend(struct amdgpu_device *adev) guard(mutex)(&uqm->userq_mutex); amdgpu_userq_detect_and_reset_queues(uqm); if (adev->in_s0ix) - r = amdgpu_userq_preempt_helper(uqm, queue); + r = amdgpu_userq_preempt_helper(queue); else - r = amdgpu_userq_unmap_helper(uqm, queue); + r = amdgpu_userq_unmap_helper(queue); if (r) return r; } @@ -1337,9 +1420,9 @@ int amdgpu_userq_resume(struct amdgpu_device *adev) uqm = queue->userq_mgr; guard(mutex)(&uqm->userq_mutex); if (adev->in_s0ix) - r = amdgpu_userq_restore_helper(uqm, queue); + r = amdgpu_userq_restore_helper(queue); else - r = amdgpu_userq_map_helper(uqm, queue); + r = amdgpu_userq_map_helper(queue); if (r) return r; } @@ -1371,7 +1454,7 @@ int amdgpu_userq_stop_sched_for_enforce_isolation(struct amdgpu_device *adev, (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { amdgpu_userq_detect_and_reset_queues(uqm); - r = amdgpu_userq_preempt_helper(uqm, queue); + r = amdgpu_userq_preempt_helper(queue); if (r) ret = r; } @@ -1403,9 +1486,9 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, if (((queue->queue_type == AMDGPU_HW_IP_GFX) || (queue->queue_type == AMDGPU_HW_IP_COMPUTE)) && (queue->xcp_id == idx)) { - r = amdgpu_userq_restore_helper(uqm, queue); - if (r) - ret = r; + r = amdgpu_userq_restore_helper(queue); + if (r) + ret = r; } mutex_unlock(&uqm->userq_mutex); } @@ -1455,9 +1538,9 @@ void amdgpu_userq_pre_reset(struct amdgpu_device *adev) uqm = queue->userq_mgr; cancel_delayed_work_sync(&uqm->resume_work); if (queue->state == AMDGPU_USERQ_STATE_MAPPED) { - amdgpu_userq_wait_for_last_fence(uqm, queue); + amdgpu_userq_wait_for_last_fence(queue); userq_funcs = adev->userq_funcs[queue->queue_type]; - userq_funcs->unmap(uqm, queue); + userq_funcs->unmap(queue); /* just mark all queues as hung at this point. * if unmap succeeds, we could map again * in amdgpu_userq_post_reset() if vram is not lost @@ -1474,18 +1557,16 @@ int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost) * at this point, we should be able to map it again * and continue if vram is not lost. */ - struct amdgpu_userq_mgr *uqm; struct amdgpu_usermode_queue *queue; const struct amdgpu_userq_funcs *userq_funcs; unsigned long queue_id; int r = 0; xa_for_each(&adev->userq_doorbell_xa, queue_id, queue) { - uqm = queue->userq_mgr; if (queue->state == AMDGPU_USERQ_STATE_HUNG && !vram_lost) { userq_funcs = adev->userq_funcs[queue->queue_type]; /* Re-map queue */ - r = userq_funcs->map(uqm, queue); + r = userq_funcs->map(queue); if (r) { dev_err(adev->dev, "Failed to remap queue %ld\n", queue_id); continue; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h index b48b3bc293fca..a379f70da8273 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h @@ -66,30 +66,34 @@ struct amdgpu_usermode_queue { struct amdgpu_userq_obj db_obj; struct amdgpu_userq_obj fw_obj; struct amdgpu_userq_obj wptr_obj; +#ifdef HAVE_STRUCT_XARRAY struct xarray fence_drv_xa; +#else + struct idr fence_drv_idr; + spinlock_t fence_drv_lock; +#endif struct amdgpu_userq_fence_driver *fence_drv; struct dma_fence *last_fence; u32 xcp_id; int priority; struct dentry *debugfs_queue; + struct delayed_work hang_detect_work; + struct dma_fence *hang_detect_fence; + struct kref refcount; struct list_head userq_va_list; }; struct amdgpu_userq_funcs { - int (*mqd_create)(struct amdgpu_userq_mgr *uq_mgr, - struct drm_amdgpu_userq_in *args, - struct amdgpu_usermode_queue *queue); - void (*mqd_destroy)(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *uq); - int (*unmap)(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue); - int (*map)(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue); - int (*preempt)(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue); - int (*restore)(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue); + int (*mqd_create)(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args); + int (*mqd_update)(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args); + void (*mqd_destroy)(struct amdgpu_usermode_queue *uq); + int (*unmap)(struct amdgpu_usermode_queue *queue); + int (*map)(struct amdgpu_usermode_queue *queue); + int (*preempt)(struct amdgpu_usermode_queue *queue); + int (*restore)(struct amdgpu_usermode_queue *queue); int (*detect_and_reset)(struct amdgpu_device *adev, int queue_type); }; @@ -97,11 +101,11 @@ struct amdgpu_userq_funcs { /* Usermode queues for gfx */ struct amdgpu_userq_mgr { /** - * @userq_mgr_xa: Per-process user queue map (queue ID → queue) + * @userq_xa: Per-process user queue map (queue ID → queue) * Key: queue_id (unique ID within the process's userq manager) * Value: struct amdgpu_usermode_queue */ - struct xarray userq_mgr_xa; + struct xarray userq_xa; struct mutex userq_mutex; struct amdgpu_device *adev; struct delayed_work resume_work; @@ -116,11 +120,15 @@ struct amdgpu_db_info { struct amdgpu_userq_obj *db_obj; }; +struct amdgpu_usermode_queue *amdgpu_userq_get(struct amdgpu_userq_mgr *uq_mgr, u32 qid); +void amdgpu_userq_put(struct amdgpu_usermode_queue *queue); + int amdgpu_userq_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct drm_file *file_priv, struct amdgpu_device *adev); +void amdgpu_userq_mgr_cancel_resume(struct amdgpu_userq_mgr *userq_mgr); void amdgpu_userq_mgr_fini(struct amdgpu_userq_mgr *userq_mgr); int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, @@ -130,8 +138,7 @@ int amdgpu_userq_create_object(struct amdgpu_userq_mgr *uq_mgr, void amdgpu_userq_destroy_object(struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_userq_obj *userq_obj); -void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_eviction_fence *ev_fence); +void amdgpu_userq_evict(struct amdgpu_userq_mgr *uq_mgr); void amdgpu_userq_ensure_ev_fence(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_eviction_fence_mgr *evf_mgr); @@ -153,8 +160,10 @@ int amdgpu_userq_start_sched_for_enforce_isolation(struct amdgpu_device *adev, void amdgpu_userq_reset_work(struct work_struct *work); void amdgpu_userq_pre_reset(struct amdgpu_device *adev); int amdgpu_userq_post_reset(struct amdgpu_device *adev, bool vram_lost); +void amdgpu_userq_start_hang_detect_work(struct amdgpu_usermode_queue *queue); -int amdgpu_userq_input_va_validate(struct amdgpu_usermode_queue *queue, +int amdgpu_userq_input_va_validate(struct amdgpu_device *adev, + struct amdgpu_usermode_queue *queue, u64 addr, u64 expected_size); int amdgpu_userq_gem_va_unmap_validate(struct amdgpu_device *adev, struct amdgpu_bo_va_mapping *mapping, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c index 85e9edc1cb6ff..cead6acb90759 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c @@ -35,6 +35,8 @@ static const struct dma_fence_ops amdgpu_userq_fence_ops; static struct kmem_cache *amdgpu_userq_fence_slab; +#define AMDGPU_USERQ_MAX_HANDLES (1U << 16) + int amdgpu_userq_fence_slab_init(void) { amdgpu_userq_fence_slab = kmem_cache_create("amdgpu_userq_fence", @@ -102,10 +104,17 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, fence_drv->context = dma_fence_context_alloc(1); get_task_comm(fence_drv->timeline_name, current); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->userq_xa, flags); r = xa_err(__xa_store(&adev->userq_xa, userq->doorbell_index, fence_drv, GFP_KERNEL)); xa_unlock_irqrestore(&adev->userq_xa, flags); +#else + spin_lock_irqsave(&adev->userq_lock, flags); + r = idr_alloc(&adev->userq_idr, fence_drv, userq->doorbell_index, + userq->doorbell_index + 1, GFP_KERNEL); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif if (r) goto free_seq64; @@ -121,11 +130,16 @@ int amdgpu_userq_fence_driver_alloc(struct amdgpu_device *adev, return r; } +#ifdef HAVE_STRUCT_XARRAY static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) +#else +static void amdgpu_userq_walk_and_drop_fence_drv(struct idr *idr, spinlock_t *idr_lock) +#endif { struct amdgpu_userq_fence_driver *fence_drv; unsigned long index; +#ifdef HAVE_STRUCT_XARRAY if (xa_empty(xa)) return; @@ -136,6 +150,18 @@ static void amdgpu_userq_walk_and_drop_fence_drv(struct xarray *xa) } xa_unlock(xa); +#else + if (idr_is_empty(idr)) + return; + + spin_lock(idr_lock); + idr_for_each_entry(idr, fence_drv, index) { + idr_remove(idr, index); + amdgpu_userq_fence_driver_put(fence_drv); + } + + spin_unlock(idr_lock); +#endif } void @@ -143,8 +169,16 @@ amdgpu_userq_fence_driver_free(struct amdgpu_usermode_queue *userq) { dma_fence_put(userq->last_fence); +#ifdef HAVE_STRUCT_XARRAY amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_xa); xa_destroy(&userq->fence_drv_xa); +#else + unsigned long flags; + amdgpu_userq_walk_and_drop_fence_drv(&userq->fence_drv_idr, &userq->fence_drv_lock); + spin_lock_irqsave(&userq->fence_drv_lock, flags); + idr_destroy(&userq->fence_drv_idr); + spin_unlock_irqrestore(&userq->fence_drv_lock, flags); +#endif /* Drop the fence_drv reference held by user queue */ amdgpu_userq_fence_driver_put(userq->fence_drv); } @@ -188,7 +222,12 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref) struct amdgpu_userq_fence_driver *xa_fence_drv; struct amdgpu_device *adev = fence_drv->adev; struct amdgpu_userq_fence *fence, *tmp; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; + struct spinlock *idr_lock = &adev->userq_lock; +#endif unsigned long index, flags; struct dma_fence *f; @@ -206,11 +245,19 @@ void amdgpu_userq_fence_driver_destroy(struct kref *ref) } spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); xa_for_each(xa, index, xa_fence_drv) if (xa_fence_drv == fence_drv) __xa_erase(xa, index); xa_unlock_irqrestore(xa, flags); +#else + spin_lock_irqsave(idr_lock, flags); + idr_for_each_entry(idr, xa_fence_drv, index) + if (xa_fence_drv == fence_drv) + idr_remove(idr, index); + spin_unlock_irqrestore(idr_lock, flags); +#endif /* Free seq64 memory */ amdgpu_seq64_free(adev, fence_drv->va); @@ -256,13 +303,22 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, amdgpu_userq_fence_driver_get(fence_drv); dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY if (!xa_empty(&userq->fence_drv_xa)) { +#else + if (!idr_is_empty(&userq->fence_drv_idr)) { +#endif struct amdgpu_userq_fence_driver *stored_fence_drv; unsigned long index, count = 0; int i = 0; +#ifdef HAVE_STRUCT_XARRAY xa_lock(&userq->fence_drv_xa); xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) +#else + spin_lock(&userq->fence_drv_lock); + idr_for_each_entry(&userq->fence_drv_idr, stored_fence_drv, index) +#endif count++; userq_fence->fence_drv_array = @@ -271,15 +327,25 @@ static int amdgpu_userq_fence_create(struct amdgpu_usermode_queue *userq, GFP_ATOMIC); if (userq_fence->fence_drv_array) { +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&userq->fence_drv_xa, index, stored_fence_drv) { userq_fence->fence_drv_array[i] = stored_fence_drv; __xa_erase(&userq->fence_drv_xa, index); +#else + idr_for_each_entry(&userq->fence_drv_idr, stored_fence_drv, index) { + userq_fence->fence_drv_array[i] = stored_fence_drv; + idr_remove(&userq->fence_drv_idr, index); +#endif i++; } } userq_fence->fence_drv_array_count = i; +#ifdef HAVE_STRUCT_XARRAY xa_unlock(&userq->fence_drv_xa); +#else + spin_unlock(&userq->fence_drv_lock); +#endif } else { userq_fence->fence_drv_array = NULL; userq_fence->fence_drv_array_count = 0; @@ -334,7 +400,6 @@ static void amdgpu_userq_fence_free(struct rcu_head *rcu) /* Release the fence driver reference */ amdgpu_userq_fence_driver_put(fence_drv); - kvfree(userq_fence->fence_drv_array); kmem_cache_free(amdgpu_userq_fence_slab, userq_fence); } @@ -354,6 +419,7 @@ static const struct dma_fence_ops amdgpu_userq_fence_ops = { /** * amdgpu_userq_fence_read_wptr - Read the userq wptr value * + * @adev: amdgpu_device pointer * @queue: user mode queue structure pointer * @wptr: write pointer value * @@ -363,7 +429,8 @@ static const struct dma_fence_ops amdgpu_userq_fence_ops = { * * Returns wptr value on success, error on failure. */ -static int amdgpu_userq_fence_read_wptr(struct amdgpu_usermode_queue *queue, +static int amdgpu_userq_fence_read_wptr(struct amdgpu_device *adev, + struct amdgpu_usermode_queue *queue, u64 *wptr) { struct amdgpu_bo_va_mapping *mapping; @@ -457,28 +524,32 @@ amdgpu_userq_fence_driver_force_completion(struct amdgpu_usermode_queue *userq) int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { + struct amdgpu_device *adev = drm_to_adev(dev); + struct drm_amdgpu_userq_signal *args = data; + const unsigned int num_write_bo_handles = args->num_bo_write_handles; + const unsigned int num_read_bo_handles = args->num_bo_read_handles; struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; - struct drm_amdgpu_userq_signal *args = data; - struct drm_gem_object **gobj_write = NULL; - struct drm_gem_object **gobj_read = NULL; - struct amdgpu_usermode_queue *queue; + struct drm_gem_object **gobj_write, **gobj_read; + u32 *syncobj_handles, num_syncobj_handles; struct amdgpu_userq_fence *userq_fence; + struct amdgpu_usermode_queue *queue = NULL; struct drm_syncobj **syncobj = NULL; - u32 *bo_handles_write, num_write_bo_handles; - u32 *syncobj_handles, num_syncobj_handles; - u32 *bo_handles_read, num_read_bo_handles; - int r, i, entry, rentry, wentry; struct dma_fence *fence; struct drm_exec exec; + int r, i, entry; u64 wptr; if (!amdgpu_userq_enabled(dev)) return -ENOTSUPP; + if (args->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + args->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) + return -EINVAL; + num_syncobj_handles = args->num_syncobj_handles; - syncobj_handles = memdup_user(u64_to_user_ptr(args->syncobj_handles), - size_mul(sizeof(u32), num_syncobj_handles)); + syncobj_handles = memdup_array_user(u64_to_user_ptr(args->syncobj_handles), + num_syncobj_handles, sizeof(u32)); if (IS_ERR(syncobj_handles)) return PTR_ERR(syncobj_handles); @@ -497,60 +568,28 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } } - num_read_bo_handles = args->num_bo_read_handles; - bo_handles_read = memdup_user(u64_to_user_ptr(args->bo_read_handles), - sizeof(u32) * num_read_bo_handles); - if (IS_ERR(bo_handles_read)) { - r = PTR_ERR(bo_handles_read); + r = drm_gem_objects_lookup(filp, + u64_to_user_ptr(args->bo_read_handles), + num_read_bo_handles, + &gobj_read); + if (r) goto free_syncobj; - } - - /* Array of pointers to the GEM read objects */ - gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL); - if (!gobj_read) { - r = -ENOMEM; - goto free_bo_handles_read; - } - for (rentry = 0; rentry < num_read_bo_handles; rentry++) { - gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]); - if (!gobj_read[rentry]) { - r = -ENOENT; - goto put_gobj_read; - } - } - - num_write_bo_handles = args->num_bo_write_handles; - bo_handles_write = memdup_user(u64_to_user_ptr(args->bo_write_handles), - sizeof(u32) * num_write_bo_handles); - if (IS_ERR(bo_handles_write)) { - r = PTR_ERR(bo_handles_write); + r = drm_gem_objects_lookup(filp, + u64_to_user_ptr(args->bo_write_handles), + num_write_bo_handles, + &gobj_write); + if (r) goto put_gobj_read; - } - - /* Array of pointers to the GEM write objects */ - gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL); - if (!gobj_write) { - r = -ENOMEM; - goto free_bo_handles_write; - } - - for (wentry = 0; wentry < num_write_bo_handles; wentry++) { - gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]); - if (!gobj_write[wentry]) { - r = -ENOENT; - goto put_gobj_write; - } - } /* Retrieve the user queue */ - queue = xa_load(&userq_mgr->userq_mgr_xa, args->queue_id); + queue = amdgpu_userq_get(userq_mgr, args->queue_id); if (!queue) { r = -ENOENT; goto put_gobj_write; } - r = amdgpu_userq_fence_read_wptr(queue, &wptr); + r = amdgpu_userq_fence_read_wptr(adev, queue, &wptr); if (r) goto put_gobj_write; @@ -571,6 +610,7 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, dma_fence_put(queue->last_fence); queue->last_fence = dma_fence_get(fence); + amdgpu_userq_start_hang_detect_work(queue); mutex_unlock(&userq_mgr->userq_mutex); drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, @@ -594,18 +634,18 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, } for (i = 0; i < num_read_bo_handles; i++) { - if (!gobj_read || !gobj_read[i]->resv) + if (!gobj_read || !amdkcl_gem_resvp(gobj_read[i])) continue; - dma_resv_add_fence(gobj_read[i]->resv, fence, + dma_resv_add_fence(amdkcl_gem_resvp(gobj_read[i]), fence, DMA_RESV_USAGE_READ); } for (i = 0; i < num_write_bo_handles; i++) { - if (!gobj_write || !gobj_write[i]->resv) + if (!gobj_write || !amdkcl_gem_resvp(gobj_write[i])) continue; - dma_resv_add_fence(gobj_write[i]->resv, fence, + dma_resv_add_fence(amdkcl_gem_resvp(gobj_write[i]), fence, DMA_RESV_USAGE_WRITE); } @@ -619,17 +659,13 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, exec_fini: drm_exec_fini(&exec); put_gobj_write: - while (wentry-- > 0) - drm_gem_object_put(gobj_write[wentry]); - kfree(gobj_write); -free_bo_handles_write: - kfree(bo_handles_write); + for (i = 0; i < num_write_bo_handles; i++) + drm_gem_object_put(gobj_write[i]); + kvfree(gobj_write); put_gobj_read: - while (rentry-- > 0) - drm_gem_object_put(gobj_read[rentry]); - kfree(gobj_read); -free_bo_handles_read: - kfree(bo_handles_read); + for (i = 0; i < num_read_bo_handles; i++) + drm_gem_object_put(gobj_read[i]); + kvfree(gobj_read); free_syncobj: while (entry-- > 0) if (syncobj[entry]) @@ -638,382 +674,419 @@ int amdgpu_userq_signal_ioctl(struct drm_device *dev, void *data, free_syncobj_handles: kfree(syncobj_handles); + if (queue) + amdgpu_userq_put(queue); + return r; } -int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, - struct drm_file *filp) +/* Count the number of expected fences so userspace can alloc a buffer */ +static int +amdgpu_userq_wait_count_fences(struct drm_file *filp, + struct drm_amdgpu_userq_wait *wait_info, + u32 *syncobj_handles, u32 *timeline_points, + u32 *timeline_handles, + struct drm_gem_object **gobj_write, + struct drm_gem_object **gobj_read) { - u32 *syncobj_handles, *timeline_points, *timeline_handles, *bo_handles_read, *bo_handles_write; - u32 num_syncobj, num_read_bo_handles, num_write_bo_handles; - struct drm_amdgpu_userq_fence_info *fence_info = NULL; - struct drm_amdgpu_userq_wait *wait_info = data; - struct amdgpu_fpriv *fpriv = filp->driver_priv; - struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; - struct amdgpu_usermode_queue *waitq; - struct drm_gem_object **gobj_write; - struct drm_gem_object **gobj_read; - struct dma_fence **fences = NULL; - u16 num_points, num_fences = 0; - int r, i, rentry, wentry, cnt; + int num_read_bo_handles, num_write_bo_handles; + struct dma_fence_unwrap iter; + struct dma_fence *fence, *f; + unsigned int num_fences = 0; struct drm_exec exec; + int i, r; + + /* + * This needs to be outside of the lock provided by drm_exec for + * DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT to work correctly. + */ + + /* Count timeline fences */ + for (i = 0; i < wait_info->num_syncobj_timeline_handles; i++) { + r = drm_syncobj_find_fence(filp, timeline_handles[i], + timeline_points[i], + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + return r; + + dma_fence_unwrap_for_each(f, &iter, fence) + num_fences++; - if (!amdgpu_userq_enabled(dev)) - return -ENOTSUPP; + dma_fence_put(fence); + } - num_read_bo_handles = wait_info->num_bo_read_handles; - bo_handles_read = memdup_user(u64_to_user_ptr(wait_info->bo_read_handles), - size_mul(sizeof(u32), num_read_bo_handles)); - if (IS_ERR(bo_handles_read)) - return PTR_ERR(bo_handles_read); + /* Count boolean fences */ + for (i = 0; i < wait_info->num_syncobj_handles; i++) { + r = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + return r; - num_write_bo_handles = wait_info->num_bo_write_handles; - bo_handles_write = memdup_user(u64_to_user_ptr(wait_info->bo_write_handles), - size_mul(sizeof(u32), num_write_bo_handles)); - if (IS_ERR(bo_handles_write)) { - r = PTR_ERR(bo_handles_write); - goto free_bo_handles_read; + num_fences++; + dma_fence_put(fence); } - num_syncobj = wait_info->num_syncobj_handles; - syncobj_handles = memdup_user(u64_to_user_ptr(wait_info->syncobj_handles), - size_mul(sizeof(u32), num_syncobj)); - if (IS_ERR(syncobj_handles)) { - r = PTR_ERR(syncobj_handles); - goto free_bo_handles_write; - } + /* Lock all the GEM objects */ + /* TODO: It is actually not necessary to lock them */ + num_read_bo_handles = wait_info->num_bo_read_handles; + num_write_bo_handles = wait_info->num_bo_write_handles; + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, + num_read_bo_handles + num_write_bo_handles); - num_points = wait_info->num_syncobj_timeline_handles; - timeline_handles = memdup_user(u64_to_user_ptr(wait_info->syncobj_timeline_handles), - sizeof(u32) * num_points); - if (IS_ERR(timeline_handles)) { - r = PTR_ERR(timeline_handles); - goto free_syncobj_handles; - } + drm_exec_until_all_locked(&exec) { + r = drm_exec_prepare_array(&exec, gobj_read, + num_read_bo_handles, 1); + drm_exec_retry_on_contention(&exec); + if (r) + goto error_unlock; - timeline_points = memdup_user(u64_to_user_ptr(wait_info->syncobj_timeline_points), - sizeof(u32) * num_points); - if (IS_ERR(timeline_points)) { - r = PTR_ERR(timeline_points); - goto free_timeline_handles; + r = drm_exec_prepare_array(&exec, gobj_write, + num_write_bo_handles, 1); + drm_exec_retry_on_contention(&exec); + if (r) + goto error_unlock; } - gobj_read = kmalloc_array(num_read_bo_handles, sizeof(*gobj_read), GFP_KERNEL); - if (!gobj_read) { - r = -ENOMEM; - goto free_timeline_points; - } + /* Count read fences */ + for (i = 0; i < num_read_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; - for (rentry = 0; rentry < num_read_bo_handles; rentry++) { - gobj_read[rentry] = drm_gem_object_lookup(filp, bo_handles_read[rentry]); - if (!gobj_read[rentry]) { - r = -ENOENT; - goto put_gobj_read; - } + dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + DMA_RESV_USAGE_READ, fence) + num_fences++; } - gobj_write = kmalloc_array(num_write_bo_handles, sizeof(*gobj_write), GFP_KERNEL); - if (!gobj_write) { - r = -ENOMEM; - goto put_gobj_read; - } + /* Count write fences */ + for (i = 0; i < num_write_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; - for (wentry = 0; wentry < num_write_bo_handles; wentry++) { - gobj_write[wentry] = drm_gem_object_lookup(filp, bo_handles_write[wentry]); - if (!gobj_write[wentry]) { - r = -ENOENT; - goto put_gobj_write; - } + dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + DMA_RESV_USAGE_WRITE, fence) + num_fences++; } - drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, - (num_read_bo_handles + num_write_bo_handles)); + wait_info->num_fences = min(num_fences, USHRT_MAX); + r = 0; - /* Lock all BOs with retry handling */ - drm_exec_until_all_locked(&exec) { - r = drm_exec_prepare_array(&exec, gobj_read, num_read_bo_handles, 1); - drm_exec_retry_on_contention(&exec); - if (r) { - drm_exec_fini(&exec); - goto put_gobj_write; - } +error_unlock: + /* Unlock all the GEM objects */ + drm_exec_fini(&exec); + return r; +} - r = drm_exec_prepare_array(&exec, gobj_write, num_write_bo_handles, 1); - drm_exec_retry_on_contention(&exec); - if (r) { - drm_exec_fini(&exec); - goto put_gobj_write; - } +static int +amdgpu_userq_wait_add_fence(struct drm_amdgpu_userq_wait *wait_info, + struct dma_fence **fences, unsigned int *num_fences, + struct dma_fence *fence) +{ + /* As fallback shouldn't userspace allocate enough space */ + if (*num_fences >= wait_info->num_fences) + return dma_fence_wait(fence, true); + + fences[(*num_fences)++] = dma_fence_get(fence); + return 0; +} + +static int +amdgpu_userq_wait_return_fence_info(struct drm_file *filp, + struct drm_amdgpu_userq_wait *wait_info, + u32 *syncobj_handles, u32 *timeline_points, + u32 *timeline_handles, + struct drm_gem_object **gobj_write, + struct drm_gem_object **gobj_read) +{ + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_userq_mgr *userq_mgr = &fpriv->userq_mgr; + struct drm_amdgpu_userq_fence_info *fence_info; + int num_read_bo_handles, num_write_bo_handles; + struct amdgpu_usermode_queue *waitq; + struct dma_fence **fences, *fence, *f; + struct dma_fence_unwrap iter; + int num_points, num_syncobj; + unsigned int num_fences = 0; + struct drm_exec exec; + int i, cnt, r; + + fence_info = kmalloc_array(wait_info->num_fences, sizeof(*fence_info), + GFP_KERNEL); + if (!fence_info) + return -ENOMEM; + + fences = kmalloc_array(wait_info->num_fences, sizeof(*fences), + GFP_KERNEL); + if (!fences) { + r = -ENOMEM; + goto free_fence_info; } - if (!wait_info->num_fences) { - if (num_points) { - struct dma_fence_unwrap iter; - struct dma_fence *fence; - struct dma_fence *f; - - for (i = 0; i < num_points; i++) { - r = drm_syncobj_find_fence(filp, timeline_handles[i], - timeline_points[i], - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto exec_fini; - - dma_fence_unwrap_for_each(f, &iter, fence) - num_fences++; + /* Retrieve timeline fences */ + num_points = wait_info->num_syncobj_timeline_handles; + for (i = 0; i < num_points; i++) { + r = drm_syncobj_find_fence(filp, timeline_handles[i], + timeline_points[i], + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + goto free_fences; + dma_fence_unwrap_for_each(f, &iter, fence) { + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, f); + if (r) { dma_fence_put(fence); + goto free_fences; } } - /* Count syncobj's fence */ - for (i = 0; i < num_syncobj; i++) { - struct dma_fence *fence; - - r = drm_syncobj_find_fence(filp, syncobj_handles[i], - 0, - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto exec_fini; - - num_fences++; - dma_fence_put(fence); - } + dma_fence_put(fence); + } - /* Count GEM objects fence */ - for (i = 0; i < num_read_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; + /* Retrieve boolean fences */ + num_syncobj = wait_info->num_syncobj_handles; + for (i = 0; i < num_syncobj; i++) { + struct dma_fence *fence; - dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, - DMA_RESV_USAGE_READ, fence) - num_fences++; - } + r = drm_syncobj_find_fence(filp, syncobj_handles[i], 0, + DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, + &fence); + if (r) + goto free_fences; - for (i = 0; i < num_write_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, fence); + dma_fence_put(fence); + if (r) + goto free_fences; - dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, - DMA_RESV_USAGE_WRITE, fence) - num_fences++; - } + } - /* - * Passing num_fences = 0 means that userspace doesn't want to - * retrieve userq_fence_info. If num_fences = 0 we skip filling - * userq_fence_info and return the actual number of fences on - * args->num_fences. - */ - wait_info->num_fences = num_fences; - } else { - /* Array of fence info */ - fence_info = kmalloc_array(wait_info->num_fences, sizeof(*fence_info), GFP_KERNEL); - if (!fence_info) { - r = -ENOMEM; - goto exec_fini; - } + /* Lock all the GEM objects */ + num_read_bo_handles = wait_info->num_bo_read_handles; + num_write_bo_handles = wait_info->num_bo_write_handles; + drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, + num_read_bo_handles + num_write_bo_handles); - /* Array of fences */ - fences = kmalloc_array(wait_info->num_fences, sizeof(*fences), GFP_KERNEL); - if (!fences) { - r = -ENOMEM; - goto free_fence_info; - } + drm_exec_until_all_locked(&exec) { + r = drm_exec_prepare_array(&exec, gobj_read, + num_read_bo_handles, 1); + drm_exec_retry_on_contention(&exec); + if (r) + goto error_unlock; - /* Retrieve GEM read objects fence */ - for (i = 0; i < num_read_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; + r = drm_exec_prepare_array(&exec, gobj_write, + num_write_bo_handles, 1); + drm_exec_retry_on_contention(&exec); + if (r) + goto error_unlock; + } - dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, - DMA_RESV_USAGE_READ, fence) { - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { - r = -EINVAL; - goto free_fences; - } + /* Retrieve GEM read objects fence */ + for (i = 0; i < num_read_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; - fences[num_fences++] = fence; - dma_fence_get(fence); - } + dma_resv_for_each_fence(&resv_cursor, gobj_read[i]->resv, + DMA_RESV_USAGE_READ, fence) { + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, fence); + if (r) + goto error_unlock; } + } - /* Retrieve GEM write objects fence */ - for (i = 0; i < num_write_bo_handles; i++) { - struct dma_resv_iter resv_cursor; - struct dma_fence *fence; - - dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, - DMA_RESV_USAGE_WRITE, fence) { - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { - r = -EINVAL; - goto free_fences; - } + /* Retrieve GEM write objects fence */ + for (i = 0; i < num_write_bo_handles; i++) { + struct dma_resv_iter resv_cursor; + struct dma_fence *fence; - fences[num_fences++] = fence; - dma_fence_get(fence); - } + dma_resv_for_each_fence(&resv_cursor, gobj_write[i]->resv, + DMA_RESV_USAGE_WRITE, fence) { + r = amdgpu_userq_wait_add_fence(wait_info, fences, + &num_fences, fence); + if (r) + goto error_unlock; } + } - if (num_points) { - struct dma_fence_unwrap iter; - struct dma_fence *fence; - struct dma_fence *f; - - for (i = 0; i < num_points; i++) { - r = drm_syncobj_find_fence(filp, timeline_handles[i], - timeline_points[i], - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto free_fences; - - dma_fence_unwrap_for_each(f, &iter, fence) { - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { - r = -EINVAL; - goto free_fences; - } - - dma_fence_get(f); - fences[num_fences++] = f; - } + drm_exec_fini(&exec); - dma_fence_put(fence); - } - } + /* + * Keep only the latest fences to reduce the number of values + * given back to userspace. + */ + num_fences = dma_fence_dedup_array(fences, num_fences); - /* Retrieve syncobj's fence */ - for (i = 0; i < num_syncobj; i++) { - struct dma_fence *fence; + waitq = amdgpu_userq_get(userq_mgr, wait_info->waitq_id); + if (!waitq) { + r = -EINVAL; + goto free_fences; + } - r = drm_syncobj_find_fence(filp, syncobj_handles[i], - 0, - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &fence); - if (r) - goto free_fences; + for (i = 0, cnt = 0; i < num_fences; i++) { + struct amdgpu_userq_fence_driver *fence_drv; + struct amdgpu_userq_fence *userq_fence; + u32 index; - if (WARN_ON_ONCE(num_fences >= wait_info->num_fences)) { - r = -EINVAL; - goto free_fences; - } + userq_fence = to_amdgpu_userq_fence(fences[i]); + if (!userq_fence) { + /* + * Just waiting on other driver fences should + * be good for now + */ + r = dma_fence_wait(fences[i], true); + if (r) + goto put_waitq; - fences[num_fences++] = fence; + continue; } + fence_drv = userq_fence->fence_drv; /* - * Keep only the latest fences to reduce the number of values - * given back to userspace. + * We need to make sure the user queue release their reference + * to the fence drivers at some point before queue destruction. + * Otherwise, we would gather those references until we don't + * have any more space left and crash. */ - num_fences = dma_fence_dedup_array(fences, num_fences); +#ifdef HAVE_STRUCT_XARRAY + r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, + xa_limit_32b, GFP_KERNEL); + if (r) +#else + spin_lock(&waitq->fence_drv_lock); + r = idr_alloc(&waitq->fence_drv_idr, fence_drv, 0, 0, GFP_KERNEL); + index = r; + spin_unlock(&waitq->fence_drv_lock); + if (r < 0) +#endif + goto put_waitq; + + amdgpu_userq_fence_driver_get(fence_drv); + + /* Store drm syncobj's gpu va address and value */ + fence_info[cnt].va = fence_drv->va; + fence_info[cnt].value = fences[i]->seqno; + + /* Increment the actual userq fence count */ + cnt++; + } + wait_info->num_fences = cnt; - waitq = xa_load(&userq_mgr->userq_mgr_xa, wait_info->waitq_id); - if (!waitq) { - r = -EINVAL; - goto free_fences; - } + /* Copy userq fence info to user space */ + if (copy_to_user(u64_to_user_ptr(wait_info->out_fences), + fence_info, cnt * sizeof(*fence_info))) + r = -EFAULT; + else + r = 0; - for (i = 0, cnt = 0; i < num_fences; i++) { - struct amdgpu_userq_fence_driver *fence_drv; - struct amdgpu_userq_fence *userq_fence; - u32 index; - - userq_fence = to_amdgpu_userq_fence(fences[i]); - if (!userq_fence) { - /* - * Just waiting on other driver fences should - * be good for now - */ - r = dma_fence_wait(fences[i], true); - if (r) { - dma_fence_put(fences[i]); - goto free_fences; - } - - dma_fence_put(fences[i]); - continue; - } +put_waitq: + amdgpu_userq_put(waitq); - fence_drv = userq_fence->fence_drv; - /* - * We need to make sure the user queue release their reference - * to the fence drivers at some point before queue destruction. - * Otherwise, we would gather those references until we don't - * have any more space left and crash. - */ - r = xa_alloc(&waitq->fence_drv_xa, &index, fence_drv, - xa_limit_32b, GFP_KERNEL); - if (r) - goto free_fences; +free_fences: + while (num_fences--) + dma_fence_put(fences[num_fences]); + kfree(fences); - amdgpu_userq_fence_driver_get(fence_drv); +free_fence_info: + kfree(fence_info); + return r; - /* Store drm syncobj's gpu va address and value */ - fence_info[cnt].va = fence_drv->va; - fence_info[cnt].value = fences[i]->seqno; +error_unlock: + drm_exec_fini(&exec); + goto free_fences; +} - dma_fence_put(fences[i]); - /* Increment the actual userq fence count */ - cnt++; - } +int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + int num_points, num_syncobj, num_read_bo_handles, num_write_bo_handles; + u32 *syncobj_handles, *timeline_points, *timeline_handles; + struct drm_amdgpu_userq_wait *wait_info = data; + struct drm_gem_object **gobj_write; + struct drm_gem_object **gobj_read; + void __user *ptr; + int r; - wait_info->num_fences = cnt; - /* Copy userq fence info to user space */ - if (copy_to_user(u64_to_user_ptr(wait_info->out_fences), - fence_info, wait_info->num_fences * sizeof(*fence_info))) { - r = -EFAULT; - goto free_fences; - } + if (!amdgpu_userq_enabled(dev)) + return -ENOTSUPP; + + if (wait_info->num_bo_write_handles > AMDGPU_USERQ_MAX_HANDLES || + wait_info->num_bo_read_handles > AMDGPU_USERQ_MAX_HANDLES) + return -EINVAL; + + num_syncobj = wait_info->num_syncobj_handles; + ptr = u64_to_user_ptr(wait_info->syncobj_handles); + syncobj_handles = memdup_array_user(ptr, num_syncobj, sizeof(u32)); + if (IS_ERR(syncobj_handles)) + return PTR_ERR(syncobj_handles); - kfree(fences); - kfree(fence_info); + num_points = wait_info->num_syncobj_timeline_handles; + ptr = u64_to_user_ptr(wait_info->syncobj_timeline_handles); + timeline_handles = memdup_array_user(ptr, num_points, sizeof(u32)); + if (IS_ERR(timeline_handles)) { + r = PTR_ERR(timeline_handles); + goto free_syncobj_handles; } - drm_exec_fini(&exec); - for (i = 0; i < num_read_bo_handles; i++) - drm_gem_object_put(gobj_read[i]); - kfree(gobj_read); + ptr = u64_to_user_ptr(wait_info->syncobj_timeline_points); + timeline_points = memdup_array_user(ptr, num_points, sizeof(u32)); + if (IS_ERR(timeline_points)) { + r = PTR_ERR(timeline_points); + goto free_timeline_handles; + } - for (i = 0; i < num_write_bo_handles; i++) - drm_gem_object_put(gobj_write[i]); - kfree(gobj_write); + num_read_bo_handles = wait_info->num_bo_read_handles; + ptr = u64_to_user_ptr(wait_info->bo_read_handles); + r = drm_gem_objects_lookup(filp, ptr, num_read_bo_handles, &gobj_read); + if (r) + goto free_timeline_points; - kfree(timeline_points); - kfree(timeline_handles); - kfree(syncobj_handles); - kfree(bo_handles_write); - kfree(bo_handles_read); + num_write_bo_handles = wait_info->num_bo_write_handles; + ptr = u64_to_user_ptr(wait_info->bo_write_handles); + r = drm_gem_objects_lookup(filp, ptr, num_write_bo_handles, + &gobj_write); + if (r) + goto put_gobj_read; - return 0; + /* + * Passing num_fences = 0 means that userspace doesn't want to + * retrieve userq_fence_info. If num_fences = 0 we skip filling + * userq_fence_info and return the actual number of fences on + * args->num_fences. + */ + if (!wait_info->num_fences) { + r = amdgpu_userq_wait_count_fences(filp, wait_info, + syncobj_handles, + timeline_points, + timeline_handles, + gobj_write, + gobj_read); + } else { + r = amdgpu_userq_wait_return_fence_info(filp, wait_info, + syncobj_handles, + timeline_points, + timeline_handles, + gobj_write, + gobj_read); + } + + while (num_write_bo_handles--) + drm_gem_object_put(gobj_write[num_write_bo_handles]); + kvfree(gobj_write); -free_fences: - while (num_fences-- > 0) - dma_fence_put(fences[num_fences]); - kfree(fences); -free_fence_info: - kfree(fence_info); -exec_fini: - drm_exec_fini(&exec); -put_gobj_write: - while (wentry-- > 0) - drm_gem_object_put(gobj_write[wentry]); - kfree(gobj_write); put_gobj_read: - while (rentry-- > 0) - drm_gem_object_put(gobj_read[rentry]); - kfree(gobj_read); + while (num_read_bo_handles--) + drm_gem_object_put(gobj_read[num_read_bo_handles]); + kvfree(gobj_read); + free_timeline_points: kfree(timeline_points); free_timeline_handles: kfree(timeline_handles); free_syncobj_handles: kfree(syncobj_handles); -free_bo_handles_write: - kfree(bo_handles_write); -free_bo_handles_read: - kfree(bo_handles_read); - return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 5c38f0d30c87a..9b8378c996aac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -279,7 +279,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; - DRM_INFO("Found UVD firmware Version: %u.%u Family ID: %u\n", + drm_info(adev_to_drm(adev), "Found UVD firmware Version: %u.%u Family ID: %u\n", version_major, version_minor, family_id); /* @@ -306,7 +306,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; - DRM_INFO("Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", + drm_info(adev_to_drm(adev), "Found UVD firmware ENC: %u.%u DEC: .%u Family ID: %u\n", enc_major, enc_minor, dec_minor, family_id); adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; @@ -467,7 +467,8 @@ int amdgpu_uvd_prepare_suspend(struct amdgpu_device *adev) int amdgpu_uvd_suspend(struct amdgpu_device *adev) { if (amdgpu_ras_intr_triggered()) - DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); + drm_warn(adev_to_drm(adev), + "UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); return 0; } @@ -1170,11 +1171,13 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (r) goto err_free; } else { +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_resv_dependencies(&job->base, - bo->tbo.base.resv, + amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; +#endif f = amdgpu_job_submit(job); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index a7d8f1ce6ac2d..eb4a15db2ef20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -450,24 +450,6 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) } } -/** - * amdgpu_vce_required_gart_pages() - gets number of GART pages required by VCE - * - * @adev: amdgpu_device pointer - * - * Returns how many GART pages we need before GTT for the VCE IP block. - * For VCE1, see vce_v1_0_ensure_vcpu_bo_32bit_addr for details. - * For VCE2+, this is not needed so return zero. - */ -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev) -{ - /* VCE IP block not added yet, so can't use amdgpu_ip_version */ - if (adev->family == AMDGPU_FAMILY_SI) - return 512; - - return 0; -} - /** * amdgpu_vce_get_create_msg - generate a VCE create msg * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index 1c3464ce50378..778c714c8385d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -52,6 +52,7 @@ struct amdgpu_vce { uint32_t srbm_soft_reset; unsigned num_rings; uint32_t keyselect; + struct drm_mm_node gart_node; }; int amdgpu_vce_early_init(struct amdgpu_device *adev); @@ -61,7 +62,6 @@ int amdgpu_vce_entity_init(struct amdgpu_device *adev, struct amdgpu_ring *ring) int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); -u32 amdgpu_vce_required_gart_pages(struct amdgpu_device *adev); int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job, struct amdgpu_ib *ib); int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 5e0786ea911b3..03d95dca93d75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -63,6 +63,8 @@ #define FIRMWARE_VCN4_0_6_1 "amdgpu/vcn_4_0_6_1.bin" #define FIRMWARE_VCN5_0_0 "amdgpu/vcn_5_0_0.bin" #define FIRMWARE_VCN5_0_1 "amdgpu/vcn_5_0_1.bin" +#define FIRMWARE_VCN5_0_2 "amdgpu/vcn_5_0_2.bin" +#define FIRMWARE_VCN5_3_0 "amdgpu/vcn_5_3_0.bin" MODULE_FIRMWARE(FIRMWARE_RAVEN); MODULE_FIRMWARE(FIRMWARE_PICASSO); @@ -90,6 +92,8 @@ MODULE_FIRMWARE(FIRMWARE_VCN4_0_6); MODULE_FIRMWARE(FIRMWARE_VCN4_0_6_1); MODULE_FIRMWARE(FIRMWARE_VCN5_0_0); MODULE_FIRMWARE(FIRMWARE_VCN5_0_1); +MODULE_FIRMWARE(FIRMWARE_VCN5_0_2); +MODULE_FIRMWARE(FIRMWARE_VCN5_3_0); static void amdgpu_vcn_idle_work_handler(struct work_struct *work); static void amdgpu_vcn_reg_dump_fini(struct amdgpu_device *adev); @@ -1093,7 +1097,8 @@ int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout) long r; if ((amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(4, 0, 3)) && - (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1))) { + (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 1)) && + (amdgpu_ip_version(adev, UVD_HWIP, 0) != IP_VERSION(5, 0, 2))) { r = amdgpu_vcn_enc_ring_test_ib(ring, timeout); if (r) goto error; @@ -1130,7 +1135,8 @@ void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev, int i) return; if ((amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(4, 0, 3) || - amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1)) + amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 1) || + amdgpu_ip_version(adev, UVD_HWIP, 0) == IP_VERSION(5, 0, 2)) && (i > 0)) return; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 47a6ce4fdc744..c8e4c6e356aab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -37,6 +37,7 @@ #include "vi.h" #include "soc15.h" #include "nv.h" +#include "amdgpu_virt_ras_cmd.h" #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ do { \ @@ -604,10 +605,10 @@ static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) #ifdef MODULE if (THIS_MODULE->version != NULL) - strcpy(vf2pf_info->driver_version, THIS_MODULE->version); + strscpy(vf2pf_info->driver_version, THIS_MODULE->version); else #endif - strcpy(vf2pf_info->driver_version, "N/A"); + strscpy(vf2pf_info->driver_version, "N/A"); vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all vf2pf_info->driver_cert = 0; @@ -949,11 +950,6 @@ int amdgpu_virt_init_critical_region(struct amdgpu_device *adev) if (adev->virt.req_init_data_ver != GPU_CRIT_REGION_V2) return 0; - if (init_hdr_offset < 0) { - dev_err(adev->dev, "Invalid init header offset\n"); - return -EINVAL; - } - vram_size = RREG32(mmRCC_CONFIG_MEMSIZE); if (!vram_size || vram_size == U32_MAX) return -EINVAL; @@ -1261,6 +1257,7 @@ bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_i || ucode_id == AMDGPU_UCODE_ID_SDMA5 || ucode_id == AMDGPU_UCODE_ID_SDMA6 || ucode_id == AMDGPU_UCODE_ID_SDMA7 + || ucode_id == AMDGPU_UCODE_ID_SDMA_RS64 || ucode_id == AMDGPU_UCODE_ID_RLC_G || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL || ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM @@ -1337,6 +1334,133 @@ bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, return ret; } +static u32 amdgpu_virt_rlcg_vfi_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) +{ + uint32_t timeout = 100; + uint32_t i; + + struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; + void *vfi_cmd; + void *vfi_stat; + void *vfi_addr; + void *vfi_data; + void *vfi_grbm_cntl; + void *vfi_grbm_idx; + uint32_t cmd; + uint32_t stat; + uint32_t addr = offset; + uint32_t data; + uint32_t grbm_cntl_data; + uint32_t grbm_idx_data; + + unsigned long flags; + bool is_err = true; + + if (!adev->gfx.rlc.rlcg_reg_access_supported) { + dev_err(adev->dev, "VFi interface is not available\n"); + return 0; + } + + if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { + dev_err(adev->dev, "VFi invalid XCC, xcc_id=0x%x\n", xcc_id); + return 0; + } + + if (amdgpu_device_skip_hw_access(adev)) + return 0; + + reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; + vfi_cmd = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_cmd; + vfi_stat = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_stat; + vfi_addr = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_addr; + vfi_data = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_data; + vfi_grbm_cntl = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_cntl; + vfi_grbm_idx = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->vfi_grbm_idx; + grbm_cntl_data = reg_access_ctrl->vfi_grbm_cntl_data; + grbm_idx_data = reg_access_ctrl->vfi_grbm_idx_data; + + if (flag == AMDGPU_RLCG_GC_WRITE) { + data = v; + cmd = AMDGPU_RLCG_VFI_CMD__WR; + + // the GRBM_GFX_CNTL and GRBM_GFX_INDEX are protected by mutex outside this call + if (addr == reg_access_ctrl->grbm_cntl) { + reg_access_ctrl->vfi_grbm_cntl_data = data; + return 0; + } else if (addr == reg_access_ctrl->grbm_idx) { + reg_access_ctrl->vfi_grbm_idx_data = data; + return 0; + } + + } else if (flag == AMDGPU_RLCG_GC_READ) { + data = 0; + cmd = AMDGPU_RLCG_VFI_CMD__RD; + + // the GRBM_GFX_CNTL and GRBM_GFX_INDEX are protected by mutex outside this call + if (addr == reg_access_ctrl->grbm_cntl) + return grbm_cntl_data; + else if (addr == reg_access_ctrl->grbm_idx) + return grbm_idx_data; + + } else { + dev_err(adev->dev, "VFi invalid access, flag=0x%x\n", flag); + return 0; + } + + spin_lock_irqsave(&adev->virt.rlcg_reg_lock, flags); + + writel(addr, vfi_addr); + writel(data, vfi_data); + writel(grbm_cntl_data, vfi_grbm_cntl); + writel(grbm_idx_data, vfi_grbm_idx); + + writel(AMDGPU_RLCG_VFI_STAT__BUSY, vfi_stat); + writel(cmd, vfi_cmd); + + for (i = 0; i < timeout; i++) { + stat = readl(vfi_stat); + if (stat != AMDGPU_RLCG_VFI_STAT__BUSY) + break; + udelay(10); + } + + switch (stat) { + case AMDGPU_RLCG_VFI_STAT__DONE: + is_err = false; + if (cmd == AMDGPU_RLCG_VFI_CMD__RD) + data = readl(vfi_data); + break; + case AMDGPU_RLCG_VFI_STAT__BUSY: + dev_err(adev->dev, "VFi access timeout\n"); + break; + case AMDGPU_RLCG_VFI_STAT__INV_CMD: + dev_err(adev->dev, "VFi invalid command\n"); + break; + case AMDGPU_RLCG_VFI_STAT__INV_ADDR: + dev_err(adev->dev, "VFi invalid address\n"); + break; + case AMDGPU_RLCG_VFI_STAT__ERR: + dev_err(adev->dev, "VFi unknown error\n"); + break; + default: + dev_err(adev->dev, "VFi unknown status code\n"); + break; + } + + spin_unlock_irqrestore(&adev->virt.rlcg_reg_lock, flags); + + if (is_err) + dev_err(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd=0x%x\n", + grbm_cntl_data, grbm_idx_data, + addr, addr * 4, data, cmd); + else + dev_dbg(adev->dev, "VFi: [grbm_cntl=0x%x grbm_idx=0x%x] addr=0x%x (byte addr 0x%x), data=0x%x, cmd=0x%x\n", + grbm_cntl_data, grbm_idx_data, + addr, addr * 4, data, cmd); + + return data; +} + u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) { struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; @@ -1350,6 +1474,9 @@ u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 f void *spare_int; unsigned long flags; + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) + return amdgpu_virt_rlcg_vfi_reg_rw(adev, offset, v, flag, xcc_id); + if (!adev->gfx.rlc.rlcg_reg_access_supported) { dev_err(adev->dev, "indirect registers access through rlcg is not available\n"); @@ -1533,6 +1660,9 @@ bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev) if (adev->virt.ras_en_caps.bits.poison_propogation_mode) con->poison_supported = true; /* Poison is handled by host */ + if (adev->virt.ras_en_caps.bits.uniras_supported) + amdgpu_virt_ras_set_remote_uniras(adev, true); + return true; } @@ -1845,3 +1975,28 @@ int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, b return r; } + +static int req_remote_ras_cmd(struct amdgpu_device *adev, + u32 param1, u32 param2, u32 param3) +{ + struct amdgpu_virt *virt = &adev->virt; + + if (virt->ops && virt->ops->req_remote_ras_cmd) + return virt->ops->req_remote_ras_cmd(adev, param1, param2, param3); + return -ENOENT; +} + +int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev, + uint64_t buf, uint32_t buf_len) +{ + uint64_t gpa = buf; + int ret = -EIO; + + if (down_read_trylock(&adev->reset_domain->sem)) { + ret = req_remote_ras_cmd(adev, + lower_32_bits(gpa), upper_32_bits(gpa), buf_len); + up_read(&adev->reset_domain->sem); + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index 01d5bca2dee16..9da0c6e9b8695 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -47,6 +47,15 @@ #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF #define AMDGPU_RLCG_SCRATCH1_ERROR_MASK 0xF000000 +#define AMDGPU_RLCG_VFI_CMD__WR 0x0 +#define AMDGPU_RLCG_VFI_CMD__RD 0x1 + +#define AMDGPU_RLCG_VFI_STAT__BUSY 0x0 +#define AMDGPU_RLCG_VFI_STAT__DONE 0x1 +#define AMDGPU_RLCG_VFI_STAT__INV_CMD 0x2 +#define AMDGPU_RLCG_VFI_STAT__INV_ADDR 0x3 +#define AMDGPU_RLCG_VFI_STAT__ERR 0xFF + /* all asic after AI use this offset */ #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 /* tonga/fiji use this offset */ @@ -105,6 +114,8 @@ struct amdgpu_virt_ops { int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr); int (*req_bad_pages)(struct amdgpu_device *adev); int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr); + int (*req_remote_ras_cmd)(struct amdgpu_device *adev, + u32 param1, u32 param2, u32 param3); }; /* @@ -151,6 +162,7 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), AMDGIM_FEATURE_RAS_CPER = (1 << 11), AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12), + AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -401,6 +413,9 @@ struct amdgpu_video_codec_info; #define amdgpu_sriov_xgmi_ta_ext_peer_link_en(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK) +#define amdgpu_sriov_xgmi_connected_to_cpu(adev) \ +((adev)->virt.gim_feature & AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU) + static inline bool is_virtual_machine(void) { #if defined(CONFIG_X86) @@ -483,4 +498,6 @@ bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev, enum amdgpu_ras_block block); void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev); int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit); +int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev, + uint64_t buf, uint32_t buf_len); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 79bad9cbe2abd..5cb7848d3a7a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -53,7 +53,9 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer, output->period_ns); if (ret_overrun != 1) - DRM_WARN("%s: vblank timer overrun\n", __func__); + drm_warn(amdgpu_crtc->base.dev, + "%s: vblank timer overrun count: %llu\n", + __func__, ret_overrun); ret = drm_crtc_handle_vblank(crtc); /* Don't queue timer again when vblank is disabled. */ @@ -99,10 +101,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, } *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - - if (WARN_ON(*vblank_time == vblank->time)) + if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; - /* * To prevent races we roll the hrtimer forward before we do any * interrupt processing - this is how real hw works (the interrupt is @@ -110,8 +110,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, * the vblank core expects. Therefore we need to always correct the * timestampe by one frame. */ - *vblank_time -= output->period_ns; + *vblank_time = ktime_sub(*vblank_time, output->period_ns); return true; } @@ -122,25 +122,39 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .enable_vblank = amdgpu_vkms_enable_vblank, .disable_vblank = amdgpu_vkms_disable_vblank, .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, +#endif }; static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { drm_crtc_vblank_on(crtc); } static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { drm_crtc_vblank_off(crtc); } static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { unsigned long flags; if (crtc->state->event) { @@ -157,6 +171,7 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } + static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { .atomic_flush = amdgpu_vkms_crtc_atomic_flush, .atomic_enable = amdgpu_vkms_crtc_atomic_enable, @@ -187,8 +202,13 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, amdgpu_crtc->connector = NULL; amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE; +#ifdef HAVE_HRTIMER_SETUP hrtimer_setup(&amdgpu_crtc->vblank_timer, &amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC, HRTIMER_MODE_REL); +#else + hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate; +#endif return ret; } @@ -260,16 +280,26 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { }; static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *old_state) +#else + struct drm_plane_state *old_state) +#endif { return; } static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state) +{ + struct drm_atomic_state *state = new_plane_state->state; +#endif struct drm_crtc_state *crtc_state; int ret; @@ -278,6 +308,7 @@ static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); + if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); @@ -326,7 +357,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); goto error_unlock; @@ -486,6 +517,105 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + return 0; +} + +static void amdgpu_vkms_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) +{ + return; +} + +static int amdgpu_vkms_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + *vbl = 0; + *position = 0; + + return -EINVAL; +} + +static bool amdgpu_vkms_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return true; +} + +static void amdgpu_vkms_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return; +} + +static u32 amdgpu_vkms_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return 0; +} + +static void amdgpu_vkms_bandwidth_update(struct amdgpu_device *adev) +{ + return; +} + +static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { + .bandwidth_update = &amdgpu_vkms_bandwidth_update, + .vblank_get_counter = &amdgpu_vkms_vblank_get_counter, + .backlight_set_level = NULL, + .backlight_get_level = NULL, + .hpd_sense = &amdgpu_vkms_hpd_sense, + .hpd_set_polarity = &amdgpu_vkms_hpd_set_polarity, + .hpd_get_gpio_reg = &amdgpu_vkms_hpd_get_gpio_reg, + .page_flip = &amdgpu_vkms_page_flip, + .page_flip_get_scanoutpos = &amdgpu_vkms_crtc_get_scanoutpos, + .add_encoder = NULL, + .add_connector = NULL, +}; + +static int amdgpu_vkms_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + if (type > AMDGPU_CRTC_IRQ_VBLANK6) + return -EINVAL; + + if (type >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[type]) { + DRM_DEBUG("invalid crtc %d\n", type); + return -EINVAL; + } + + adev->mode_info.crtcs[type]->vsync_timer_enabled = state; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + amdgpu_vkms_enable_vblank(&adev->mode_info.crtcs[type]->base); + else + amdgpu_vkms_disable_vblank(&adev->mode_info.crtcs[type]->base); + + return 0; +} + +static const struct amdgpu_irq_src_funcs amdgpu_vkms_crtc_irq_funcs = { + .set = amdgpu_vkms_set_crtc_irq_state, + .process = NULL, +}; + +static int amdgpu_vkms_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + adev->crtc_irq.num_types = adev->mode_info.num_crtc; + adev->crtc_irq.funcs = &amdgpu_vkms_crtc_irq_funcs; + + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + adev->mode_info.num_hpd = 1; + adev->mode_info.num_dig = 1; + return 0; +} +#endif + const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, .atomic_check = drm_atomic_helper_check, @@ -512,7 +642,9 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) @@ -638,6 +770,9 @@ static int amdgpu_vkms_set_powergating_state(struct amdgpu_ip_block *ip_block, static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { .name = "amdgpu_vkms", +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .early_init = amdgpu_vkms_early_init, +#endif .sw_init = amdgpu_vkms_sw_init, .sw_fini = amdgpu_vkms_sw_fini, .hw_init = amdgpu_vkms_hw_init, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index a67285118c37b..c1d074c326000 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -138,6 +138,20 @@ static void amdgpu_vm_assert_locked(struct amdgpu_vm *vm) dma_resv_assert_held(vm->root.bo->tbo.base.resv); } +/** + * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid + * + * @vm: VM to test against. + * @bo: BO to be tested. + * + * Returns true if the BO shares the dma_resv object with the root PD and is + * always guaranteed to be valid inside the VM. + */ +bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) +{ + return bo && amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo); +} + /** * amdgpu_vm_bo_evicted - vm_bo is evicted * @@ -427,7 +441,7 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, if (!amdgpu_vm_is_bo_always_valid(vm, bo)) return; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move); if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) @@ -636,7 +650,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, spin_unlock(&vm->status_lock); bo = bo_base->bo; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); r = validate(param, bo); if (r) @@ -764,12 +778,9 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, * @need_pipe_sync: is pipe sync needed * * Emit a VM flush when it is necessary. - * - * Returns: - * 0 on success, errno otherwise. */ -int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, - bool need_pipe_sync) +void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, + bool need_pipe_sync) { struct amdgpu_device *adev = ring->adev; struct amdgpu_isolation *isolation = &adev->isolation[ring->xcp_id]; @@ -783,8 +794,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool cleaner_shader_needed = false; bool pasid_mapping_needed = false; struct dma_fence *fence = NULL; - unsigned int patch; - int r; + unsigned int patch = 0; if (amdgpu_vmid_had_gpu_reset(adev, id)) { gds_switch_needed = true; @@ -812,9 +822,20 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync && !cleaner_shader_needed) - return 0; + return; amdgpu_ring_ib_begin(ring); + + /* There is no matching insert_end for this on purpose for the vm flush. + * The IB portion of the submission has both. Having multiple + * insert_start sequences is ok, but you can only have one insert_end + * per submission based on the way VCN FW works. For JPEG + * you can as many insert_start and insert_end sequences as you like as + * long as the rest of the packets come between start and end sequences. + */ + if (ring->funcs->insert_start) + ring->funcs->insert_start(ring); + if (ring->funcs->init_cond_exec) patch = amdgpu_ring_init_cond_exec(ring, ring->cond_exe_gpu_addr); @@ -834,7 +855,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid); if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid); + adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid); if (ring->funcs->emit_gds_switch && gds_switch_needed) { @@ -845,9 +866,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, } if (vm_flush_needed || pasid_mapping_needed || cleaner_shader_needed) { - r = amdgpu_fence_emit(ring, job->hw_vm_fence, 0); - if (r) - return r; + amdgpu_fence_emit(ring, job->hw_vm_fence, 0); fence = &job->hw_vm_fence->base; /* get a ref for the job */ dma_fence_get(fence); @@ -892,7 +911,6 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, } amdgpu_ring_ib_end(ring); - return 0; } /** @@ -1069,11 +1087,14 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, } /* Prepare a TLB flush fence to be attached to PTs */ - if (!params->unlocked) { + /* The check for need_tlb_fence should be dropped once we + * sort out the issues with KIQ/MES TLB invalidation timeouts. + */ + if (!params->unlocked && vm->need_tlb_fence) { amdgpu_vm_tlb_fence_create(params->adev, vm, fence); /* Makes sure no PD/PT is freed before the flush */ - dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), *fence, DMA_RESV_USAGE_BOOKKEEP); } } @@ -1170,45 +1191,59 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t tmp, num_entries, addr; num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; - if (pages_addr) { - bool contiguous = true; - if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { - uint64_t pfn = cursor.start >> PAGE_SHIFT; - uint64_t count; + if (res && (res->mem_type == AMDGPU_PL_DGMA_IMPORT || + res->mem_type == AMDGPU_PL_DGMA)) { + uint64_t pfn = offset >> PAGE_SHIFT; + + if (res->mem_type == AMDGPU_PL_DGMA_IMPORT) { + addr = 0; + } else { + addr = pfn << PAGE_SHIFT; + addr += vram_base + + cursor.start + amdgpu_ttm_domain_start(adev, res->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); + params.pages_addr = NULL; + } + } else { + if (pages_addr) { + bool contiguous = true; + + if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { + uint64_t pfn = cursor.start >> PAGE_SHIFT; + uint64_t count; - contiguous = pages_addr[pfn + 1] == - pages_addr[pfn] + PAGE_SIZE; + contiguous = pages_addr[pfn + 1] == + pages_addr[pfn] + PAGE_SIZE; - tmp = num_entries / - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - for (count = 2; count < tmp; ++count) { - uint64_t idx = pfn + count; + tmp = num_entries / + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + for (count = 2; count < tmp; ++count) { + uint64_t idx = pfn + count; if (contiguous != (pages_addr[idx] == - pages_addr[idx - 1] + PAGE_SIZE)) + pages_addr[idx - 1] + PAGE_SIZE)) break; - } - if (!contiguous) + } + if (!contiguous) count--; - num_entries = count * - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - } + num_entries = count * + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + } - if (!contiguous) { - addr = cursor.start; - params.pages_addr = pages_addr; + if (!contiguous) { + addr = cursor.start; + params.pages_addr = pages_addr; + } else { + addr = pages_addr[cursor.start >> PAGE_SHIFT]; + params.pages_addr = NULL; + } + } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { + addr = vram_base + cursor.start; } else { - addr = pages_addr[cursor.start >> PAGE_SHIFT]; - params.pages_addr = NULL; + addr = 0; } - - } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { - addr = vram_base + cursor.start; - } else { - addr = 0; } - tmp = start + num_entries; r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags); if (r) @@ -1271,6 +1306,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t flags; bool uncached; int r; + struct amdgpu_device *bo_adev = adev; amdgpu_sync_create(&sync); if (clear) { @@ -1279,12 +1315,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, /* Implicitly sync to command submissions in the same VM before * unmapping. */ - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; if (bo) { - r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv); + r = amdgpu_sync_kfd(&sync, amdkcl_ttm_resvp(&bo->tbo)); if (r) goto error_free; } @@ -1309,17 +1345,17 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; + else if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ - r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_EXPLICIT, vm); if (r) goto error_free; } if (bo) { - struct amdgpu_device *bo_adev; - flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); if (amdgpu_bo_encrypted(bo)) @@ -1362,6 +1398,18 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, amdgpu_gmc_get_vm_pte(adev, vm, bo, mapping->flags, &update_flags); + if (adev != bo_adev && + !(update_flags & AMDGPU_PTE_SYSTEM) && + !mapping->bo_va->is_xgmi) { + if (amdgpu_device_is_peer_accessible(bo_adev, adev)) { + update_flags |= AMDGPU_PTE_SYSTEM; + vram_base = bo_adev->gmc.aper_base; + } else { + DRM_DEBUG_DRIVER("Failed to map the VRAM for peer device access.\n"); + return -EINVAL; + } + } + trace_amdgpu_vm_bo_update(mapping); r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, @@ -1516,7 +1564,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, */ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); struct dma_resv_iter cursor; struct dma_fence *fence; @@ -1557,7 +1605,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, * unmapping. */ amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; @@ -1629,7 +1677,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - resv = bo_va->base.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); spin_unlock(&vm->status_lock); /* Try to reserve the BO to avoid clearing its ptes */ @@ -1735,6 +1783,8 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, { struct amdgpu_bo_va *bo_va; + amdgpu_vm_assert_locked(vm); + bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL); if (bo_va == NULL) { return NULL; @@ -1749,7 +1799,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, if (!bo) return bo_va; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) { bo_va->is_xgmi = true; /* Power up XGMI if it can be potentially used */ @@ -2160,7 +2210,7 @@ void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) struct amdgpu_bo *bo; bo = mapping->bo_va->base.bo; - if (dma_resv_locking_ctx(bo->tbo.base.resv) != + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) continue; } @@ -2187,10 +2237,10 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_vm_bo_base **base; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); if (bo) { - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_vm_is_bo_always_valid(vm, bo)) ttm_bo_set_bulk_move(&bo->tbo, NULL); @@ -2247,7 +2297,7 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo) return true; /* Don't evict VM page tables while they are busy */ - if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP)) + if (!dma_resv_test_signaled(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP)) return false; /* Try to block ongoing updates */ @@ -2398,6 +2448,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, } adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; + adev->vm_manager.max_level = max_level; tmp = roundup_pow_of_two(adev->vm_manager.max_pfn); if (amdgpu_vm_block_size != -1) @@ -2405,6 +2456,9 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1; adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp); switch (adev->vm_manager.num_level) { + case 4: + adev->vm_manager.root_level = AMDGPU_VM_PDB3; + break; case 3: adev->vm_manager.root_level = AMDGPU_VM_PDB2; break; @@ -2468,9 +2522,15 @@ amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid) struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); vm = xa_load(&adev->vm_manager.pasids, pasid); xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return vm; } @@ -2599,6 +2659,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ttm_lru_bulk_move_init(&vm->lru_bulk_move); vm->is_compute_context = false; + vm->need_tlb_fence = amdgpu_userq_enabled(&adev->ddev); vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_GFX); @@ -2636,7 +2697,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, } amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); - r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root_bo->tbo), 1); if (r) goto error_free_root; @@ -2736,6 +2797,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) dma_fence_put(vm->last_update); vm->last_update = dma_fence_get_stub(); vm->is_compute_context = true; + vm->need_tlb_fence = true; unreserve_bo: amdgpu_bo_unreserve(vm->root.bo); @@ -2874,7 +2936,12 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) adev->vm_manager.vm_update_mode = 0; #endif +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->vm_manager.pasid_idr); + spin_lock_init(&adev->vm_manager.pasid_lock); +#endif } /** @@ -2886,10 +2953,16 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) */ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) { +#ifdef HAVE_STRUCT_XARRAY WARN_ON(!xa_empty(&adev->vm_manager.pasids)); xa_destroy(&adev->vm_manager.pasids); +#else + WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); + idr_destroy(&adev->vm_manager.pasid_idr); +#endif amdgpu_vmid_mgr_fini(adev); + amdgpu_pasid_mgr_cleanup(); } /** @@ -2952,37 +3025,55 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, struct amdgpu_vm *vm; int r; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm) { root = amdgpu_bo_ref(vm->root.bo); is_compute_context = vm->is_compute_context; } else { root = NULL; } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!root) return false; - addr /= AMDGPU_GPU_PAGE_SIZE; - if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, - node_id, addr, ts, write_fault)) { + node_id, addr >> PAGE_SHIFT, ts, write_fault)) { amdgpu_bo_unref(&root); return true; } + addr /= AMDGPU_GPU_PAGE_SIZE; + r = amdgpu_bo_reserve(root, true); if (r) goto error_unref; /* Double check that the VM still exists */ +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm && vm->root.bo != root) vm = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!vm) goto error_unlock; @@ -3006,7 +3097,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, value = 0; } - r = dma_resv_reserve_fences(root->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root->tbo), 1); if (r) { pr_debug("failed %d to reserve fence slot\n", r); goto error_unlock; @@ -3138,6 +3229,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ + void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3147,9 +3239,14 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); - vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif + /* Don't update the fault cache if status is 0. In the multiple * fault case, subsequent faults will return a 0 status which is * useless for userspace and replaces the useful fault status, so @@ -3182,21 +3279,11 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, WARN_ONCE(1, "Invalid vmhub %u\n", vmhub); } } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); -} - -/** - * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid - * - * @vm: VM to test against. - * @bo: BO to be tested. - * - * Returns true if the BO shares the dma_resv object with the root PD and is - * always guaranteed to be valid inside the VM. - */ -bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) -{ - return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv; +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif } void amdgpu_vm_print_task_info(struct amdgpu_device *adev, @@ -3207,3 +3294,20 @@ void amdgpu_vm_print_task_info(struct amdgpu_device *adev, task_info->process_name, task_info->tgid, task_info->task.comm, task_info->task.pid); } + +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev, + const struct amdgpu_vm_pte_funcs *vm_pte_funcs) +{ + struct drm_gpu_scheduler *sched; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) { + if (adev->sdma.has_page_queue) + sched = &adev->sdma.instance[i].page.sched; + else + sched = &adev->sdma.instance[i].ring.sched; + adev->vm_manager.vm_pte_scheds[i] = sched; + } + adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; + adev->vm_manager.vm_pte_funcs = vm_pte_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 15d757c016cbb..33c680c483c76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -129,6 +129,7 @@ struct amdgpu_bo_vm; AMDGPU_PTE_MTYPE_GFX12_SHIFT(mtype)) #define AMDGPU_PTE_DCC (1ULL << 58) +#define AMDGPU_PTE_BUS_ATOMICS (1ULL << 59) #define AMDGPU_PTE_IS_PTE (1ULL << 63) /* PDE Block Fragment Size for gfx v12 */ @@ -185,9 +186,10 @@ struct amdgpu_bo_vm; #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) /* VMPT level enumerate, and the hiberachy is: - * PDB2->PDB1->PDB0->PTB + * PDB3->PDB2->PDB1->PDB0->PTB */ enum amdgpu_vm_level { + AMDGPU_VM_PDB3, AMDGPU_VM_PDB2, AMDGPU_VM_PDB1, AMDGPU_VM_PDB0, @@ -439,6 +441,8 @@ struct amdgpu_vm { struct ttm_lru_bulk_move lru_bulk_move; /* Flag to indicate if VM is used for compute */ bool is_compute_context; + /* Flag to indicate if VM needs a TLB fence (KFD or KGD) */ + bool need_tlb_fence; /* Memory partition number, -1 means any partition */ int8_t mem_id; @@ -454,6 +458,7 @@ struct amdgpu_vm_manager { bool concurrent_flush; uint64_t max_pfn; + uint32_t max_level; uint32_t num_level; uint32_t block_size; uint32_t fragment_size; @@ -479,7 +484,12 @@ struct amdgpu_vm_manager { /* PASID to VM mapping, will be used in interrupt context to * look up VM of a page fault */ +#ifdef HAVE_STRUCT_XARRAY struct xarray pasids; +#else + struct idr pasid_idr; + spinlock_t pasid_lock; +#endif /* Global registration of recent page fault information */ struct amdgpu_vm_fault_info fault_info; }; @@ -510,7 +520,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket, int (*callback)(void *p, struct amdgpu_bo *bo), void *param); -int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); +void amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); int amdgpu_vm_update_pdes(struct amdgpu_device *adev, struct amdgpu_vm *vm, bool immediate); int amdgpu_vm_clear_freed(struct amdgpu_device *adev, @@ -676,6 +686,7 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, uint64_t addr, uint32_t status, unsigned int vmhub); + void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 22e2e5b473415..e784f6311178a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -77,7 +77,7 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, uint64_t value; long r; - r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&vmbo->bo.tbo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index f794fb1cc06e6..105b46b4dc9ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -51,6 +51,7 @@ static unsigned int amdgpu_vm_pt_level_shift(struct amdgpu_device *adev, unsigned int level) { switch (level) { + case AMDGPU_VM_PDB3: case AMDGPU_VM_PDB2: case AMDGPU_VM_PDB1: case AMDGPU_VM_PDB0: @@ -366,6 +367,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo *ancestor = &vmbo->bo; unsigned int entries; struct amdgpu_bo *bo = &vmbo->bo; + uint64_t value = 0, flags = 0; uint64_t addr; int r, idx; @@ -403,7 +405,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, addr = 0; - uint64_t value = 0, flags = 0; if (adev->asic_type >= CHIP_VEGA10) { if (level != AMDGPU_VM_PTB) { /* Handle leaf PDEs as PTEs */ @@ -412,7 +413,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, &value, &flags); } else { /* Workaround for fault priority problem on GMC9 */ - flags = AMDGPU_PTE_EXECUTABLE; + flags = AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags; } } @@ -473,7 +474,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, bp.xcp_id_plus1 = xcp_id + 1; if (vm->root.bo) - bp.resv = vm->root.bo->tbo.base.resv; + bp.resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); return amdgpu_bo_create_vm(adev, &bp, vmbo); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 36805dcfa1598..4a694075c2dc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -128,7 +128,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, swap(p->vm->last_unlocked, tmp); dma_fence_put(tmp); } else { - dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, + dma_resv_add_fence(amdkcl_ttm_resvp(&p->vm->root.bo->tbo), f, DMA_RESV_USAGE_BOOKKEEP); } @@ -229,15 +229,17 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, int r; /* Wait for PD/PT moves to be completed */ - dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); + dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); + #ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&p->job->base, fence); if (r) { dma_fence_put(fence); dma_resv_iter_end(&cursor); return r; } +#endif } dma_resv_iter_end(&cursor); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index aa78c2ee9e21c..fd881388d6125 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -790,7 +790,7 @@ static int vpe_ring_test_ring(struct amdgpu_ring *ring) ret = amdgpu_ring_alloc(ring, 4); if (ret) { - dev_err(adev->dev, "amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, ret); + dev_err(adev->dev, "dma failed to lock ring %d (%d).\n", ring->idx, ret); goto out; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 9d934c07fa6b8..3487bc738ba46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -214,7 +214,11 @@ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO, static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO, amdgpu_mem_info_vram_vendor, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vram_mgr_attributes[] = { +#else +static const struct attribute *amdgpu_vram_mgr_attributes[] = { +#endif &dev_attr_mem_info_vram_total.attr, &dev_attr_mem_info_vis_vram_total.attr, &dev_attr_mem_info_vram_used.attr, @@ -223,6 +227,7 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = { NULL }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int i) { @@ -244,6 +249,7 @@ const struct attribute_group amdgpu_vram_mgr_attr_group = { .attrs = amdgpu_vram_mgr_attributes, .is_visible = amdgpu_vram_attrs_is_visible }; +#endif /** * amdgpu_vram_mgr_vis_size - Calculate visible block size @@ -715,12 +721,15 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, unsigned long size = min(cursor.size, AMDGPU_MAX_SG_SEGMENT_SIZE); dma_addr_t addr; - addr = dma_map_resource(dev, phys, size, dir, - DMA_ATTR_SKIP_CPU_SYNC); - r = dma_mapping_error(dev, addr); - if (r) - goto error_unmap; - + if (dev) { + addr = dma_map_resource(dev, phys, size, dir, + DMA_ATTR_SKIP_CPU_SYNC); + r = dma_mapping_error(dev, addr); + if (r) + goto error_unmap; + } else { + addr = phys; + } sg_set_page(sg, NULL, size, 0); sg_dma_address(sg) = addr; sg_dma_len(sg) = size; @@ -734,10 +743,10 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, for_each_sgtable_sg((*sgt), sg, i) { if (!sg->length) continue; - - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); } sg_free_table(*sgt); @@ -762,10 +771,12 @@ void amdgpu_vram_mgr_free_sgt(struct device *dev, struct scatterlist *sg; int i; - for_each_sgtable_sg(sgt, sg, i) - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) { + for_each_sgtable_sg(sgt, sg, i) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); + } sg_free_table(sgt); kfree(sgt); } @@ -916,10 +927,15 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; struct ttm_resource_manager *man = &mgr->manager; int err; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif +#ifdef HAVE_DRMM_CGROUP_REGISTER_REGION man->cg = drmm_cgroup_register_region(adev_to_drm(adev), "vram", adev->gmc.real_vram_size); if (IS_ERR(man->cg)) return PTR_ERR(man->cg); +#endif ttm_resource_manager_init(man, &adev->mman.bdev, adev->gmc.real_vram_size); @@ -928,6 +944,12 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) INIT_LIST_HEAD(&mgr->reserved_pages); INIT_LIST_HEAD(&mgr->allocated_vres_list); mgr->default_page_size = PAGE_SIZE; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + /* Add the two VRAM-related sysfs files */ + ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); + if (ret) + DRM_ERROR("Failed to register sysfs\n"); +#endif man->func = &amdgpu_vram_mgr_func; err = drm_buddy_init(&mgr->mm, man->size, PAGE_SIZE); @@ -972,6 +994,9 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) drm_buddy_fini(&mgr->mm); mutex_unlock(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + sysfs_remove_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 1083db8cea2eb..663aa67803f7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -540,6 +540,7 @@ static void amdgpu_set_xcp_id(struct amdgpu_device *adev, case AMDGPU_HW_IP_GFX: case AMDGPU_RING_TYPE_COMPUTE: case AMDGPU_RING_TYPE_KIQ: + case AMDGPU_RING_TYPE_MES: ip_blk = AMDGPU_XCP_GFX; break; case AMDGPU_RING_TYPE_SDMA: @@ -743,7 +744,9 @@ static const char *nps_desc[] = { [AMDGPU_NPS8_PARTITION_MODE] = "NPS8", }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); +#endif #define to_xcp_attr(x) \ container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr) @@ -770,7 +773,11 @@ static const struct sysfs_ops xcp_cfg_res_sysfs_ops = { static const struct kobj_type xcp_cfg_res_sysfs_ktype = { .sysfs_ops = &xcp_cfg_res_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = xcp_cfg_res_sysfs_groups, +#else + .default_attrs = xcp_cfg_res_sysfs_attrs, +#endif }; const char *xcp_res_names[] = { @@ -871,7 +878,11 @@ static ssize_t xcp_config_store(struct kobject *kobj, } static struct kobj_attribute xcp_cfg_sysfs_mode = +#ifdef __ATTR_RW_MODE __ATTR_RW_MODE(xcp_config, 0644); +#else + __ATTR(xcp_config, 0644, xcp_config_show, xcp_config_store); +#endif static void xcp_cfg_sysfs_release(struct kobject *kobj) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 1928d9e224fca..8058e8f35d414 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -41,6 +41,9 @@ #define AMDGPU_XCP_OPS_KFD (1 << 0) +#define XCP_INST_MASK(num_inst, xcp_id) \ + (num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0) + struct amdgpu_fpriv; enum AMDGPU_XCP_IP_BLOCK { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index aad530c46a9f4..9a4e8715742a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -42,8 +42,6 @@ #define XGMI_STATE_DISABLE 0xD1 #define XGMI_STATE_LS0 0x81 -#define XGMI_LINK_ACTIVE 1 -#define XGMI_LINK_INACTIVE 0 static DEFINE_MUTEX(xgmi_mutex); @@ -340,7 +338,7 @@ static u32 xgmi_v6_4_get_link_status(struct amdgpu_device *adev, int global_link if (!(adev->aid_mask & BIT(i))) return U32_MAX; - addr += adev->asic_funcs->encode_ext_smn_addressing(i); + addr += amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i); return RREG32_PCIE_EXT(addr); } @@ -349,6 +347,9 @@ int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num) { u32 xgmi_state_reg_val; + if (amdgpu_sriov_vf(adev)) + return AMDGPU_XGMI_LINK_NA; + if (adev->gmc.xgmi.num_physical_nodes <= 1) return -EINVAL; @@ -365,9 +366,9 @@ int amdgpu_get_xgmi_link_status(struct amdgpu_device *adev, int global_link_num) return -ENOLINK; if ((xgmi_state_reg_val & 0xFF) == XGMI_STATE_LS0) - return XGMI_LINK_ACTIVE; + return AMDGPU_XGMI_LINK_ACTIVE; - return XGMI_LINK_INACTIVE; + return AMDGPU_XGMI_LINK_INACTIVE; } /** @@ -406,7 +407,9 @@ static struct attribute *amdgpu_xgmi_hive_attrs[] = { &amdgpu_xgmi_hive_id, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); +#endif static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, struct attribute *attr, char *buf) @@ -439,7 +442,11 @@ static const struct sysfs_ops amdgpu_xgmi_hive_ops = { static const struct kobj_type amdgpu_xgmi_hive_type = { .release = amdgpu_xgmi_hive_release, .sysfs_ops = &amdgpu_xgmi_hive_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = amdgpu_xgmi_hive_groups, +#else + .default_attrs = amdgpu_xgmi_hive_attrs, +#endif }; static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, @@ -471,12 +478,12 @@ static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; - int i; + int i, offset = 0; for (i = 0; i < top->num_nodes; i++) - sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops); + offset += sysfs_emit_at(buf, offset, "%02x ", top->nodes[i].num_hops); - return sysfs_emit(buf, "%s\n", buf); + return offset + sysfs_emit_at(buf, offset, "\n"); } static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, @@ -486,12 +493,12 @@ static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; - int i; + int i, offset = 0; for (i = 0; i < top->num_nodes; i++) - sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links); + offset += sysfs_emit_at(buf, offset, "%02x ", top->nodes[i].num_links); - return sysfs_emit(buf, "%s\n", buf); + return offset + sysfs_emit_at(buf, offset, "\n"); } static ssize_t amdgpu_xgmi_show_connected_port_num(struct device *dev, @@ -1176,7 +1183,7 @@ static int xgmi_v6_4_0_aca_bank_parser(struct aca_handle *handle, struct aca_ban switch (type) { case ACA_SMU_TYPE_UE: - if (ext_error_code != 0 && ext_error_code != 9) + if (ext_error_code != 0 && ext_error_code != 1 && ext_error_code != 9) count = 0ULL; bank->aca_err_type = ACA_ERROR_TYPE_UE; @@ -1292,7 +1299,10 @@ static void amdgpu_xgmi_legacy_reset_ras_error_count(struct amdgpu_device *adev) static void __xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst, u64 mca_base) { - WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); + uint64_t smn_base = + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst); + + WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL); } static void xgmi_v6_4_0_reset_error_count(struct amdgpu_device *adev, int xgmi_inst) @@ -1502,6 +1512,7 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a u64 mca_base, struct ras_err_data *err_data) { int xgmi_inst = mcm_info->die_id; + uint64_t smn_base; u64 status = 0; status = RREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS); @@ -1518,8 +1529,8 @@ static void __xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, struct a default: break; } - - WREG64_MCA(xgmi_inst, mca_base, ACA_REG_IDX_STATUS, 0ULL); + smn_base = amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, xgmi_inst); + WREG64_MCA(smn_base, mca_base, ACA_REG_IDX_STATUS, 0ULL); } static void xgmi_v6_4_0_query_error_count(struct amdgpu_device *adev, int xgmi_inst, struct ras_err_data *err_data) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 3cdb1e0eca377..847cfd1fd0046 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -161,7 +161,8 @@ union amd_sriov_msg_feature_flags { uint32_t ras_telemetry : 1; uint32_t ras_cper : 1; uint32_t xgmi_ta_ext_peer_link : 1; - uint32_t reserved : 19; + uint32_t xgmi_connected_to_cpu : 1; + uint32_t reserved : 18; } flags; uint32_t all; }; @@ -201,7 +202,8 @@ union amd_sriov_ras_caps { uint64_t block_mpio : 1; uint64_t block_mmsch : 1; uint64_t poison_propogation_mode : 1; - uint64_t reserved : 43; + uint64_t uniras_supported : 1; + uint64_t reserved : 42; } bits; uint64_t all; }; @@ -469,14 +471,23 @@ struct amd_sriov_ras_chk_criti { uint32_t hit; }; +union amd_sriov_ras_host_push { + struct amd_sriov_ras_telemetry_error_count error_count; + struct amd_sriov_ras_cper_dump cper_dump; + struct amd_sriov_ras_chk_criti chk_criti; +}; + +#define AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE 4096 +#define AMD_SRIOV_UNIRAS_CMD_MAX_SIZE (4096 * 13) +struct amd_sriov_uniras_shared_mem { + uint8_t blocks_ecc_buf[AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE]; + uint8_t cmd_buf[AMD_SRIOV_UNIRAS_CMD_MAX_SIZE]; +}; + struct amdsriov_ras_telemetry { struct amd_sriov_ras_telemetry_header header; - - union { - struct amd_sriov_ras_telemetry_error_count error_count; - struct amd_sriov_ras_cper_dump cper_dump; - struct amd_sriov_ras_chk_criti chk_criti; - } body; + union amd_sriov_ras_host_push body; + struct amd_sriov_uniras_shared_mem uniras_shared_mem; }; /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ @@ -509,6 +520,10 @@ _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0, _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX, "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX"); +_Static_assert( + sizeof(struct amdsriov_ras_telemetry) <= AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1 << 10, +"amdsriov_ras_telemetry must be " stringification(AMD_SRIOV_MSG_RAS_TELEMETRY_SIZE_KB_V1) " KB"); + #undef _stringification #undef stringification #endif diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index f9e2edf5260bc..72ea37dbfea8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -31,9 +31,6 @@ #include "sdma_v4_4_2.h" #include "amdgpu_ip.h" -#define XCP_INST_MASK(num_inst, xcp_id) \ - (num_inst ? GENMASK(num_inst - 1, 0) << (xcp_id * num_inst) : 0) - void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) { int i; @@ -61,25 +58,6 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev) adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1; } -/* Fixed pattern for smn addressing on different AIDs: - * bit[34]: indicate cross AID access - * bit[33:32]: indicate target AID id - * AID id range is 0 ~ 3 as maximum AID number is 4. - */ -u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id) -{ - u64 ext_offset; - - /* local routing and bit[34:32] will be zeros */ - if (ext_id == 0) - return 0; - - /* Initiated from host, accessing to all non-zero aids are cross traffic */ - ext_offset = ((u64)(ext_id & 0x3) << 32) | (1ULL << 34); - - return ext_offset; -} - static enum amdgpu_gfx_partition __aqua_vanjaram_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) { @@ -593,7 +571,7 @@ static void aqua_read_smn_ext(struct amdgpu_device *adev, uint64_t smn_addr, int i) { regdata->addr = - smn_addr + adev->asic_funcs->encode_ext_smn_addressing(i); + smn_addr + amdgpu_reg_get_smn_base64(adev, XGMI_HWIP, i); regdata->value = RREG32_PCIE_EXT(regdata->addr); } diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index 7a063e44d4298..cc5b6ea7f6d8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -1462,8 +1462,6 @@ static void atom_get_vbios_pn(struct atom_context *ctx) ctx->vbios_pn[count] = 0; } - - pr_info("ATOM BIOS: %s\n", ctx->vbios_pn); } static void atom_get_vbios_version(struct atom_context *ctx) @@ -1520,6 +1518,30 @@ static void atom_get_vbios_build(struct atom_context *ctx) strscpy(ctx->build_num, str, len); } +static inline void atom_print_vbios_info(struct atom_context *ctx) +{ + char vbios_info[256]; + int off = 0; + + if (ctx->vbios_pn[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%s", ctx->vbios_pn); + if (ctx->build_num[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%sbuild: %s", off ? ", " : "", + ctx->build_num); + if (ctx->vbios_ver_str[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%sver: %s", off ? ", " : "", + ctx->vbios_ver_str); + if (ctx->date[0]) + off += scnprintf(vbios_info + off, sizeof(vbios_info) - off, + "%s%.10s", off ? ", " : "", + ctx->date); + if (off) + drm_info(ctx->card->dev, "ATOM BIOS: %s\n", vbios_info); +} + struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) { int base; @@ -1582,6 +1604,8 @@ struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) atom_get_vbios_version(ctx); atom_get_vbios_build(ctx); + atom_print_vbios_info(ctx); + return ctx; } diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 492813ab1b541..b81674da7ed76 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -189,7 +189,10 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) { amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; + +#ifdef HAVE_DRM_DP_AUX_DRM_DEV amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; +#endif drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = true; @@ -613,7 +616,11 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; voltage = 0xff; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) < 0) { @@ -678,7 +685,11 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; channel_eq = false; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_channel_eq_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) < 0) { diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index a51f3414b65dd..d966cf0d5b283 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -186,10 +186,12 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) goto register_acpi_backlight; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(dev, "Skipping amdgpu atom DIG backlight registration\n"); goto register_acpi_backlight; } +#endif pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL); if (!pdata) { @@ -218,7 +220,7 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode bd->props.power = BACKLIGHT_POWER_ON; backlight_update_status(bd); - DRM_INFO("amdgpu atom DIG backlight initialized\n"); + drm_info(adev_to_drm(adev), "ATOM DIG backlight initialized\n"); return; @@ -228,7 +230,11 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode register_acpi_backlight: /* Try registering an ACPI video backlight device instead. */ +#ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#else + return; +#endif } void @@ -256,7 +262,7 @@ amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *amdgpu_encoder) backlight_device_unregister(bd); kfree(pdata); - DRM_INFO("amdgpu atom LVDS backlight unloaded\n"); + drm_info(adev_to_drm(adev), "ATOM LVDS backlight unloaded\n"); } } @@ -466,7 +472,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_connector->use_digital && (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid)) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else if (amdgpu_connector->use_digital) @@ -485,7 +495,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid)) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else @@ -503,7 +517,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) } else if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(drm_edid_raw(amdgpu_connector->edid)) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else @@ -1724,7 +1742,7 @@ amdgpu_atombios_encoder_dac_detect(struct drm_encoder *encoder, uint32_t bios_0_scratch; if (!amdgpu_atombios_encoder_dac_load_detect(encoder, connector)) { - DRM_DEBUG_KMS("detect returned false \n"); + DRM_DEBUG_KMS("detect returned false\n"); return connector_status_unknown; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 9cd63b4177bf2..29954c7d61b06 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -154,11 +154,11 @@ static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(mmPCIE_INDEX, reg); (void)RREG32(mmPCIE_INDEX); r = RREG32(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -166,12 +166,12 @@ static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(mmPCIE_INDEX, reg); (void)RREG32(mmPCIE_INDEX); WREG32(mmPCIE_DATA, v); (void)RREG32(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) @@ -179,10 +179,10 @@ static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); r = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -190,10 +190,10 @@ static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); WREG32(mmSMC_IND_DATA_0, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) @@ -201,10 +201,10 @@ static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); r = RREG32(mmUVD_CTX_DATA); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -212,10 +212,10 @@ static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32(mmUVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) @@ -223,10 +223,10 @@ static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); r = RREG32(mmDIDT_IND_DATA); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -234,10 +234,10 @@ static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); WREG32(mmDIDT_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static const u32 bonaire_golden_spm_registers[] = @@ -1027,7 +1027,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, dw_ptr = (u32 *)bios; length_dw = ALIGN(length_bytes, 4) / 4; /* take the smc lock since we are using the smc index */ - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); /* set rom index to 0 */ WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); WREG32(mmSMC_IND_DATA_0, 0); @@ -1035,7 +1035,7 @@ static bool cik_read_bios_from_rom(struct amdgpu_device *adev, WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); for (i = 0; i < length_dw; i++) dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return true; } @@ -1552,16 +1552,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { if (current_data_rate == 2) { - DRM_INFO("PCIE gen 3 link speeds already enabled\n"); + drm_info(adev_to_drm(adev), "PCIE gen 3 link speeds already enabled\n"); return; } - DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); + drm_info(adev_to_drm(adev), "enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { if (current_data_rate == 1) { - DRM_INFO("PCIE gen 2 link speeds already enabled\n"); + drm_info(adev_to_drm(adev), "PCIE gen 2 link speeds already enabled\n"); return; } - DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); + drm_info(adev_to_drm(adev), "enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); } if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) @@ -1957,10 +1957,6 @@ static uint64_t cik_get_pcie_replay_count(struct amdgpu_device *adev) return (nak_r + nak_g); } -static void cik_pre_asic_init(struct amdgpu_device *adev) -{ -} - static const struct amdgpu_asic_funcs cik_asic_funcs = { .read_disabled_bios = &cik_read_disabled_bios, @@ -1981,7 +1977,6 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .need_reset_on_init = &cik_need_reset_on_init, .get_pcie_replay_count = &cik_get_pcie_replay_count, .supports_baco = &cik_asic_supports_baco, - .pre_asic_init = &cik_pre_asic_init, .query_video_codecs = &cik_query_video_codecs, }; @@ -1989,14 +1984,14 @@ static int cik_common_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->smc_rreg = &cik_smc_rreg; - adev->smc_wreg = &cik_smc_wreg; - adev->pcie_rreg = &cik_pcie_rreg; - adev->pcie_wreg = &cik_pcie_wreg; - adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; - adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; - adev->didt_rreg = &cik_didt_rreg; - adev->didt_wreg = &cik_didt_wreg; + adev->reg.smc.rreg = cik_smc_rreg; + adev->reg.smc.wreg = cik_smc_wreg; + adev->reg.pcie.rreg = &cik_pcie_rreg; + adev->reg.pcie.wreg = &cik_pcie_wreg; + adev->reg.uvd_ctx.rreg = &cik_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &cik_uvd_ctx_wreg; + adev->reg.didt.rreg = &cik_didt_rreg; + adev->reg.didt.wreg = &cik_didt_wreg; adev->asic_funcs = &cik_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 9e8715b4739da..22780c09177d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -53,7 +53,6 @@ static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); -static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block); u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); @@ -919,6 +918,14 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev, } } +static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = cik_sdma_vm_copy_pte, + + .write_pte = cik_sdma_vm_write_pte, + .set_pte_pde = cik_sdma_vm_set_pte_pde, +}; + static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -933,7 +940,7 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); cik_sdma_set_buffer_funcs(adev); - cik_sdma_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs); return 0; } @@ -1337,26 +1344,6 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = cik_sdma_vm_copy_pte, - - .write_pte = cik_sdma_vm_write_pte, - .set_pte_pde = cik_sdma_vm_set_pte_pde, -}; - -static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version cik_sdma_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 72ca6538b2e49..e3437219efedb 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -175,10 +175,10 @@ static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, unsigned long flags; u32 r; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); return r; } @@ -188,10 +188,10 @@ static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, { unsigned long flags; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); } static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) @@ -1298,7 +1298,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder return; } - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); + sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); if (sad_count < 0) { DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); sad_count = 0; @@ -1368,7 +1368,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); + sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); if (sad_count < 0) DRM_ERROR("Couldn't read SADs: %d\n", sad_count); if (sad_count <= 0) @@ -1700,7 +1700,13 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, dce_v10_0_audio_write_sad_regs(encoder); dce_v10_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; @@ -1838,7 +1844,7 @@ static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_device *dev = crtc->dev; @@ -1855,32 +1861,27 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, bool bypass_lut = false; /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } - if (atomic) - target_fb = fb; - else - target_fb = crtc->primary->fb; + target_fb = crtc->primary->fb; /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) return r; - if (!atomic) { - abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r != 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(abo); + return -EINVAL; } fb_location = amdgpu_bo_gpu_offset(abo); @@ -2068,8 +2069,8 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, /* set pageflip to happen anywhere in vblank interval */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); - if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + if (fb && fb != crtc->primary->fb) { + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2483,10 +2484,12 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2555,7 +2558,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); @@ -2611,7 +2614,7 @@ static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); dce_v10_0_cursor_reset(crtc); @@ -2659,14 +2662,7 @@ static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); + return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y); } static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { @@ -2674,13 +2670,15 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { .mode_fixup = dce_v10_0_crtc_mode_fixup, .mode_set = dce_v10_0_crtc_mode_set, .mode_set_base = dce_v10_0_crtc_set_base, - .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, .prepare = dce_v10_0_crtc_prepare, .commit = dce_v10_0_crtc_commit, .disable = dce_v10_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v10_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2706,6 +2704,7 @@ static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_fu .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v10_0_panic_flush, }; +#endif static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2754,7 +2753,9 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs); +#endif return 0; } @@ -2763,8 +2764,8 @@ static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; + adev->reg.audio_endpt.rreg = &dce_v10_0_audio_endpt_rreg; + adev->reg.audio_endpt.wreg = &dce_v10_0_audio_endpt_wreg; dce_v10_0_set_display_funcs(adev); @@ -2818,7 +2819,9 @@ static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index acc887a58518d..89155beadcd11 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -138,10 +138,10 @@ static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, unsigned long flags; u32 r; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); return r; } @@ -151,11 +151,11 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, { unsigned long flags; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); } static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) @@ -1265,7 +1265,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); + sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); if (sad_count < 0) { DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); sad_count = 0; @@ -1346,7 +1346,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); + sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); if (sad_count < 0) DRM_ERROR("Couldn't read SADs: %d\n", sad_count); if (sad_count <= 0) @@ -1527,7 +1527,13 @@ static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, ssize_t err; u32 tmp; +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; @@ -1876,7 +1882,7 @@ static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_device *dev = crtc->dev; @@ -1892,32 +1898,27 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, bool bypass_lut = false; /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } - if (atomic) - target_fb = fb; - else - target_fb = crtc->primary->fb; + target_fb = crtc->primary->fb; /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) return r; - if (!atomic) { - abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r != 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(abo); + return -EINVAL; } fb_location = amdgpu_bo_gpu_offset(abo); @@ -2083,8 +2084,8 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, /* set pageflip to happen anywhere in vblank interval */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); - if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + if (fb && fb != crtc->primary->fb) { + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2455,10 +2456,12 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2523,7 +2526,7 @@ static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); @@ -2578,7 +2581,7 @@ static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); dce_v6_0_cursor_reset(crtc); @@ -2626,14 +2629,7 @@ static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); + return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y); } static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { @@ -2641,13 +2637,15 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { .mode_fixup = dce_v6_0_crtc_mode_fixup, .mode_set = dce_v6_0_crtc_mode_set, .mode_set_base = dce_v6_0_crtc_set_base, - .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, .prepare = dce_v6_0_crtc_prepare, .commit = dce_v6_0_crtc_commit, .disable = dce_v6_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v6_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2673,6 +2671,7 @@ static const struct drm_plane_helper_funcs dce_v6_0_drm_primary_plane_helper_fun .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v6_0_panic_flush, }; +#endif static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2701,7 +2700,9 @@ static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); +#endif return 0; } @@ -2710,8 +2711,8 @@ static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; + adev->reg.audio_endpt.rreg = &dce_v6_0_audio_endpt_rreg; + adev->reg.audio_endpt.wreg = &dce_v6_0_audio_endpt_wreg; dce_v6_0_set_display_funcs(adev); @@ -2767,7 +2768,9 @@ static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev_to_drm(adev)->mode_config.max_height = 16384; adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 2ccd6aad8dd65..3ed41cec58e56 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -126,10 +126,10 @@ static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, unsigned long flags; u32 r; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); return r; } @@ -139,10 +139,10 @@ static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, { unsigned long flags; - spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.audio_endpt.lock, flags); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); - spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.audio_endpt.lock, flags); } static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) @@ -1271,7 +1271,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb); + sad_count = drm_edid_to_speaker_allocation(drm_edid_raw(amdgpu_connector->edid), &sadb); if (sad_count < 0) { DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); sad_count = 0; @@ -1339,7 +1339,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) return; } - sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads); + sad_count = drm_edid_to_sad(drm_edid_raw(amdgpu_connector->edid), &sads); if (sad_count < 0) DRM_ERROR("Couldn't read SADs: %d\n", sad_count); if (sad_count <= 0) @@ -1652,7 +1652,13 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, dce_v8_0_audio_write_sad_regs(encoder); dce_v8_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; @@ -1785,7 +1791,7 @@ static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, struct drm_framebuffer *fb, - int x, int y, int atomic) + int x, int y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_device *dev = crtc->dev; @@ -1802,32 +1808,27 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, bool bypass_lut = false; /* no fb bound */ - if (!atomic && !crtc->primary->fb) { + if (!crtc->primary->fb) { DRM_DEBUG_KMS("No FB bound\n"); return 0; } - if (atomic) - target_fb = fb; - else - target_fb = crtc->primary->fb; + target_fb = crtc->primary->fb; /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) return r; - if (!atomic) { - abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; - r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r != 0)) { - amdgpu_bo_unreserve(abo); - return -EINVAL; - } + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(abo); + return -EINVAL; } fb_location = amdgpu_bo_gpu_offset(abo); @@ -1995,8 +1996,8 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, /* set pageflip to happen anywhere in vblank interval */ WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); - if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + if (fb && fb != crtc->primary->fb) { + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2402,10 +2403,12 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2474,7 +2477,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); @@ -2537,7 +2540,7 @@ static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); - dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); + dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); dce_v8_0_cursor_reset(crtc); @@ -2585,14 +2588,7 @@ static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { - return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, enum mode_set_atomic state) -{ - return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); + return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y); } static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { @@ -2600,13 +2596,15 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { .mode_fixup = dce_v8_0_crtc_mode_fixup, .mode_set = dce_v8_0_crtc_mode_set, .mode_set_base = dce_v8_0_crtc_set_base, - .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic, .prepare = dce_v8_0_crtc_prepare, .commit = dce_v8_0_crtc_commit, .disable = dce_v8_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void dce_v8_0_panic_flush(struct drm_plane *plane) { struct drm_framebuffer *fb; @@ -2631,6 +2629,7 @@ static const struct drm_plane_helper_funcs dce_v8_0_drm_primary_plane_helper_fun .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = dce_v8_0_panic_flush, }; +#endif static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) { @@ -2659,7 +2658,9 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->encoder = NULL; amdgpu_crtc->connector = NULL; drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v8_0_drm_primary_plane_helper_funcs); +#endif return 0; } @@ -2668,8 +2669,8 @@ static int dce_v8_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; - adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; + adev->reg.audio_endpt.rreg = &dce_v8_0_audio_endpt_rreg; + adev->reg.audio_endpt.wreg = &dce_v8_0_audio_endpt_wreg; dce_v8_0_set_display_funcs(adev); @@ -2736,7 +2737,9 @@ static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block) else adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c index 621aeca538803..7e7e6c389895a 100644 --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c @@ -51,7 +51,7 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); WREG32(data, ficaa_val); @@ -61,7 +61,7 @@ static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); ficadh_val = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val); } @@ -74,7 +74,7 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); WREG32(data, ficaa_val); @@ -84,7 +84,7 @@ static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); WREG32(data, ficadh_val); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /* @@ -102,12 +102,12 @@ static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, lo_addr); *lo_val = RREG32(data); WREG32(address, hi_addr); *hi_val = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /* @@ -124,12 +124,12 @@ static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, lo_addr); WREG32(data, lo_val); WREG32(address, hi_addr); WREG32(data, hi_val); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } /* same as perfmon_wreg but return status on write value check */ @@ -143,7 +143,7 @@ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, address = adev->nbio.funcs->get_pcie_index_offset(adev); data = adev->nbio.funcs->get_pcie_data_offset(adev); - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(address, lo_addr); WREG32(data, lo_val); WREG32(address, hi_addr); @@ -153,7 +153,7 @@ static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, lo_val_rb = RREG32(data); WREG32(address, hi_addr); hi_val_rb = RREG32(data); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); if (!(lo_val == lo_val_rb && hi_val == hi_val_rb)) return -EBUSY; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index fc65fb36e115a..66d22ec27ac98 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4041,8 +4041,8 @@ static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) WREG32(scratch, 0xCAFEDEAD); r = amdgpu_ring_alloc(ring, 3); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", - ring->idx, r); + drm_err(adev_to_drm(adev), "cp failed to lock ring %d (%d).\n", + ring->idx, r); return r; } @@ -4090,7 +4090,7 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err1; } @@ -4170,7 +4170,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) } if (!adev->gfx.cp_fw_write_wait) - DRM_WARN_ONCE("CP firmware version too old, please update!"); + drm_warn_once(adev_to_drm(adev), "CP firmware version too old, please update!"); } static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) @@ -4575,6 +4575,7 @@ static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) @@ -4871,6 +4872,13 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_EOP_INTERRUPT, @@ -6378,7 +6386,7 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) ring = &adev->gfx.gfx_ring[0]; r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -6428,7 +6436,7 @@ static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) ring = &adev->gfx.gfx_ring[1]; r = amdgpu_ring_alloc(ring, 2); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -6751,7 +6759,7 @@ static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, /* set up default queue priority level * 0x0 = low priority, 0x1 = high priority */ - if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) + if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) priority = 1; tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); @@ -7536,6 +7544,7 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* WA added for Vangogh asic fixing the SMU suspend failure * It needs to set power gating again during gfxoff control @@ -7787,6 +7796,94 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v10_0_spm_start(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); + + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v10_0_spm_stop(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, + 0, mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0x1); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v10_0_spm_funcs = { + .start = &gfx_v10_0_spm_start, + .stop = &gfx_v10_0_spm_stop, + .set_rdptr = &gfx_v10_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v10_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v10_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v10_0_spm_funcs; +} + static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -7818,6 +7915,7 @@ static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v10_0_set_spm_funcs(adev); gfx_v10_0_set_kiq_pm4_funcs(adev); gfx_v10_0_set_ring_funcs(adev); gfx_v10_0_set_irq_funcs(adev); @@ -7840,6 +7938,10 @@ static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -8318,7 +8420,8 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev, } } -static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) +static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) { amdgpu_gfx_off_ctrl(adev, false); @@ -8613,25 +8716,13 @@ static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), @@ -8720,7 +8811,11 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | PACKET3_RELEASE_MEM_GCR_GL2_WB | - PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ + PACKET3_RELEASE_MEM_GCR_GL2_INV | + PACKET3_RELEASE_MEM_GCR_GL2_US | + PACKET3_RELEASE_MEM_GCR_GL1_INV | + PACKET3_RELEASE_MEM_GCR_GLV_INV | + PACKET3_RELEASE_MEM_GCR_GLM_INV | PACKET3_RELEASE_MEM_GCR_GLM_WB | PACKET3_RELEASE_MEM_CACHE_POLICY(3) | PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | @@ -9395,7 +9490,7 @@ static int gfx_v10_0_bad_op_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - DRM_ERROR("Illegal opcode in command stream \n"); + DRM_ERROR("Illegal opcode in command stream\n"); gfx_v10_0_handle_priv_fault(adev, entry); return 0; } @@ -9807,6 +9902,32 @@ static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring) amdgpu_gfx_enforce_isolation_ring_end_use(ring); } +static int gfx_v10_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v10_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); + return 0; +} + static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { .name = "gfx_v10_0", .early_init = gfx_v10_0_early_init, @@ -9993,6 +10114,11 @@ static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { .process = gfx_v10_0_kiq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v10_0_spm_irq_funcs = { + .set = gfx_v10_0_spm_set_interrupt_state, + .process = gfx_v10_0_spm_irq, +}; + static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; @@ -10001,6 +10127,9 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v10_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; @@ -10124,7 +10253,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, if (!adev || !cu_info) return -EINVAL; - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index e642236ea2c51..0f686c7473f3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -120,6 +120,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_3_pfp.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_3_me.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_3_mec.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_3_rlc.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_pfp.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_me.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_rlc.bin"); static const struct amdgpu_hwip_reg_entry gc_reg_list_11_0[] = { SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), @@ -416,7 +420,8 @@ static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); + amdgpu_mes_unmap_legacy_queue(adev, ring, action, + gpu_addr, seq, 0); return; } @@ -566,8 +571,8 @@ static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring) WREG32(scratch, 0xCAFEDEAD); r = amdgpu_ring_alloc(ring, 5); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", - ring->idx, r); + drm_err(adev_to_drm(adev), "cp failed to lock ring %d (%d).\n", + ring->idx, r); return r; } @@ -623,7 +628,7 @@ static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err1; } @@ -917,7 +922,7 @@ static int gfx_v11_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -1052,10 +1057,14 @@ static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v11_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, struct amdgpu_gfx_shadow_info *shadow_info) { + /* for gfx */ shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; shadow_info->csa_size = MQD_FWWORKAREA_SIZE; shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; + /* for compute */ + shadow_info->eop_size = GFX11_MEC_HPD_SIZE; + shadow_info->eop_alignment = 256; } static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev, @@ -1080,6 +1089,7 @@ static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = { .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q, .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk, .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) @@ -1107,6 +1117,7 @@ static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): adev->gfx.config.max_hw_contexts = 8; adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; @@ -1589,6 +1600,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): adev->gfx.me.num_me = 1; adev->gfx.me.num_pipe_per_me = 1; adev->gfx.me.num_queue_per_pipe = 2; @@ -3046,7 +3058,8 @@ static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0) || amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 1) || amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 2) || - amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3)) + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 3) || + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 4)) bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1); else @@ -3617,7 +3630,7 @@ static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) ring = &adev->gfx.gfx_ring[0]; r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev)); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(&adev->ddev, "cp failed to lock ring (%d).\n", r); return r; } @@ -3662,7 +3675,7 @@ static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev) ring = &adev->gfx.gfx_ring[1]; r = amdgpu_ring_alloc(ring, 2); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -4075,7 +4088,7 @@ static void gfx_v11_0_gfx_mqd_set_priority(struct amdgpu_device *adev, /* set up default queue priority level * 0x0 = low priority, 0x1 = high priority */ - if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) + if (prop->hqd_queue_priority == AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM) priority = 1; tmp = regCP_GFX_HQD_QUEUE_PRIORITY_DEFAULT; @@ -4225,6 +4238,37 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) return gfx_v11_0_cp_gfx_start(adev); } +static void gfx_v11_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, + struct v11_compute_mqd *mqd, + struct amdgpu_mqd_prop *prop) +{ + uint32_t se_mask[8] = {0}; + uint32_t wa_mask; + bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); + + if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) + return; + + if (has_wa_flag) { + wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? + 0xffff : 0xffffffff; + mqd->compute_static_thread_mgmt_se0 = wa_mask; + mqd->compute_static_thread_mgmt_se1 = wa_mask; + mqd->compute_static_thread_mgmt_se2 = wa_mask; + mqd->compute_static_thread_mgmt_se3 = wa_mask; + return; + } + + amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, + prop->cu_mask_count, se_mask); + + mqd->compute_static_thread_mgmt_se0 = se_mask[0]; + mqd->compute_static_thread_mgmt_se1 = se_mask[1]; + mqd->compute_static_thread_mgmt_se2 = se_mask[2]; + mqd->compute_static_thread_mgmt_se3 = se_mask[3]; +} + static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) { @@ -4359,6 +4403,8 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, /* set UQ fenceaddress */ mqd->fence_address_lo = lower_32_bits(prop->fence_address); mqd->fence_address_hi = upper_32_bits(prop->fence_address); + /* set CU mask */ + gfx_v11_0_compute_mqd_set_cu_mask(adev, mqd, prop); return 0; } @@ -4593,7 +4639,7 @@ static int gfx_v11_0_cp_resume(struct amdgpu_device *adev) } if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) - r = amdgpu_mes_kiq_hw_init(adev); + r = amdgpu_mes_kiq_hw_init(adev, 0); else r = gfx_v11_0_kiq_resume(adev); if (r) @@ -4783,7 +4829,7 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) adev->gfx.is_poweron = true; if(get_gb_addr_config(adev)) - DRM_WARN("Invalid gb_addr_config !\n"); + drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && adev->gfx.rs64_enable) @@ -4901,7 +4947,7 @@ static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) if (amdgpu_gfx_disable_kcq(adev, 0)) DRM_ERROR("KCQ disable failed\n"); - amdgpu_mes_kiq_hw_fini(adev); + amdgpu_mes_kiq_hw_fini(adev, 0); } if (amdgpu_sriov_vf(adev)) @@ -5568,7 +5614,8 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev, return 0; } -static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) +static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid) { u32 reg, pre_data, data; @@ -5633,6 +5680,7 @@ static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1); break; default: @@ -5671,6 +5719,7 @@ static int gfx_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): if (!enable) amdgpu_gfx_off_ctrl(adev, false); @@ -5705,6 +5754,7 @@ static int gfx_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): gfx_v11_0_update_gfx_clock_gating(adev, state == AMD_CG_STATE_GATE); break; @@ -5831,25 +5881,13 @@ static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), @@ -6451,14 +6489,24 @@ static int gfx_v11_0_eop_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; - struct xarray *xa = &adev->userq_xa; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY + struct xarray *xa = &adev->userq_xa; xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + struct idr *idr = &adev->userq_idr; + + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -6664,7 +6712,7 @@ static int gfx_v11_0_bad_op_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - DRM_ERROR("Illegal opcode in command stream \n"); + DRM_ERROR("Illegal opcode in command stream\n"); gfx_v11_0_handle_priv_fault(adev, entry); return 0; } @@ -6828,7 +6876,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); if (r) { dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); @@ -6844,7 +6892,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = amdgpu_mes_map_legacy_queue(adev, ring); + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); if (r) { dev_err(adev->dev, "failed to remap kgq\n"); return r; @@ -6993,7 +7041,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); if (r) { dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); r = gfx_v11_0_reset_compute_pipe(ring); @@ -7006,7 +7054,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, dev_err(adev->dev, "fail to init kcq\n"); return r; } - r = amdgpu_mes_map_legacy_queue(adev, ring); + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); if (r) { dev_err(adev->dev, "failed to remap kcq\n"); return r; @@ -7480,7 +7528,7 @@ static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, if (!adev || !cu_info) return -EINVAL; - amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 4aab89a9ab401..dc4b5162163f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -355,7 +355,8 @@ static void gfx_v12_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { - amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); + amdgpu_mes_unmap_legacy_queue(adev, ring, action, + gpu_addr, seq, 0); return; } @@ -458,8 +459,8 @@ static int gfx_v12_0_ring_test_ring(struct amdgpu_ring *ring) WREG32(scratch, 0xCAFEDEAD); r = amdgpu_ring_alloc(ring, 5); if (r) { - dev_err(adev->dev, - "amdgpu: cp failed to lock ring %d (%d).\n", + drm_err(adev_to_drm(adev), + "cp failed to lock ring %d (%d).\n", ring->idx, r); return r; } @@ -516,7 +517,7 @@ static int gfx_v12_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err1; } @@ -760,7 +761,7 @@ static int gfx_v12_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -908,10 +909,14 @@ static void gfx_v12_0_select_me_pipe_q(struct amdgpu_device *adev, static void gfx_v12_0_get_gfx_shadow_info_nocheck(struct amdgpu_device *adev, struct amdgpu_gfx_shadow_info *shadow_info) { + /* for gfx */ shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE; shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT; shadow_info->csa_size = MQD_FWWORKAREA_SIZE; shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT; + /* for compute */ + shadow_info->eop_size = GFX12_MEC_HPD_SIZE; + shadow_info->eop_alignment = 256; } static int gfx_v12_0_get_gfx_shadow_info(struct amdgpu_device *adev, @@ -936,6 +941,7 @@ static const struct amdgpu_gfx_funcs gfx_v12_0_gfx_funcs = { .select_me_pipe_q = &gfx_v12_0_select_me_pipe_q, .update_perfmon_mgcg = &gfx_v12_0_update_perf_clk, .get_gfx_shadow_info = &gfx_v12_0_get_gfx_shadow_info, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v12_0_gpu_early_init(struct amdgpu_device *adev) @@ -3103,6 +3109,37 @@ static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) return gfx_v12_0_cp_gfx_start(adev); } +static void gfx_v12_0_compute_mqd_set_cu_mask(struct amdgpu_device *adev, + struct v12_compute_mqd *mqd, + struct amdgpu_mqd_prop *prop) +{ + uint32_t se_mask[8] = {0}; + uint32_t wa_mask; + bool has_wa_flag = prop->cu_flags & (AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE | + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE); + + if (!has_wa_flag && (!prop->cu_mask || !prop->cu_mask_count)) + return; + + if (has_wa_flag) { + wa_mask = (prop->cu_flags & AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE) ? + 0xffff : 0xffffffff; + mqd->compute_static_thread_mgmt_se0 = wa_mask; + mqd->compute_static_thread_mgmt_se1 = wa_mask; + mqd->compute_static_thread_mgmt_se2 = wa_mask; + mqd->compute_static_thread_mgmt_se3 = wa_mask; + return; + } + + amdgpu_gfx_mqd_symmetrically_map_cu_mask(adev, prop->cu_mask, + prop->cu_mask_count, se_mask); + + mqd->compute_static_thread_mgmt_se0 = se_mask[0]; + mqd->compute_static_thread_mgmt_se1 = se_mask[1]; + mqd->compute_static_thread_mgmt_se2 = se_mask[2]; + mqd->compute_static_thread_mgmt_se3 = se_mask[3]; +} + static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, struct amdgpu_mqd_prop *prop) { @@ -3236,6 +3273,8 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, /* set UQ fenceaddress */ mqd->fence_address_lo = lower_32_bits(prop->fence_address); mqd->fence_address_hi = upper_32_bits(prop->fence_address); + /* set CU mask */ + gfx_v12_0_compute_mqd_set_cu_mask(adev, mqd, prop); return 0; } @@ -3469,7 +3508,7 @@ static int gfx_v12_0_cp_resume(struct amdgpu_device *adev) } if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) - r = amdgpu_mes_kiq_hw_init(adev); + r = amdgpu_mes_kiq_hw_init(adev, 0); else r = gfx_v12_0_kiq_resume(adev); if (r) @@ -3650,7 +3689,7 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) adev->gfx.is_poweron = true; if (get_gb_addr_config(adev)) - DRM_WARN("Invalid gb_addr_config !\n"); + drm_warn(adev_to_drm(adev), "Invalid gb_addr_config !\n"); if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) gfx_v12_0_config_gfx_rs64(adev); @@ -3758,7 +3797,7 @@ static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) if (amdgpu_gfx_disable_kcq(adev, 0)) DRM_ERROR("KCQ disable failed\n"); - amdgpu_mes_kiq_hw_fini(adev); + amdgpu_mes_kiq_hw_fini(adev, 0); } if (amdgpu_sriov_vf(adev)) { @@ -3955,6 +3994,7 @@ static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev, } static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev, + int xcc_id, struct amdgpu_ring *ring, unsigned vmid) { @@ -4386,25 +4426,13 @@ static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v12_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), @@ -4827,14 +4855,24 @@ static int gfx_v12_0_eop_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; - struct xarray *xa = &adev->userq_xa; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY + struct xarray *xa = &adev->userq_xa; xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + struct idr *idr = &adev->userq_idr; + + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } else { me_id = (entry->ring_id & 0x0c) >> 2; pipe_id = (entry->ring_id & 0x03) >> 0; @@ -5040,7 +5078,7 @@ static int gfx_v12_0_bad_op_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - DRM_ERROR("Illegal opcode in command stream \n"); + DRM_ERROR("Illegal opcode in command stream\n"); gfx_v12_0_handle_priv_fault(adev, entry); return 0; } @@ -5302,7 +5340,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, use_mmio, 0); if (r) { dev_warn(adev->dev, "reset via MES failed and try pipe reset %d\n", r); r = gfx_v12_reset_gfx_pipe(ring); @@ -5317,7 +5355,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, return r; } - r = amdgpu_mes_map_legacy_queue(adev, ring); + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); if (r) { dev_err(adev->dev, "failed to remap kgq\n"); return r; @@ -5419,7 +5457,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, true, 0); if (r) { dev_warn(adev->dev, "fail(%d) to reset kcq and try pipe reset\n", r); r = gfx_v12_0_reset_compute_pipe(ring); @@ -5432,7 +5470,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, dev_err(adev->dev, "failed to init kcq\n"); return r; } - r = amdgpu_mes_map_legacy_queue(adev, ring); + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); if (r) { dev_err(adev->dev, "failed to remap kcq\n"); return r; @@ -5724,7 +5762,7 @@ static int gfx_v12_0_get_cu_info(struct amdgpu_device *adev, if (!adev || !cu_info) return -EINVAL; - amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2); + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 8, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c new file mode 100644 index 0000000000000..db49582a211f7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c @@ -0,0 +1,4125 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_gfx.h" +#include "amdgpu_psp.h" +#include "amdgpu_smu.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_userq_fence.h" +#include "imu_v12_1.h" +#include "soc_v1_0.h" +#include "gfx_v12_1_pkt.h" + +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "soc24_enum.h" +#include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" + +#include "soc15.h" +#include "clearstate_gfx12.h" +#include "v12_structs.h" +#include "gfx_v12_1.h" +#include "mes_v12_1.h" +#include "amdgpu_ras_mgr.h" + +#define GFX12_MEC_HPD_SIZE 2048 +#define NUM_SIMD_PER_CU_GFX12_1 4 + +#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L + +#define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000000 +#define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 +#define regCP_MQD_CONTROL_DEFAULT 0x00000100 +#define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 +#define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 +#define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0ae06301 +#define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 + +MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin"); + +#define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 +#define DEFAULT_SH_MEM_CONFIG \ + ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ + (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ + (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) + +static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id); +static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev); +static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev); +static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev); +static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev); +static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev); +static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, + struct amdgpu_cu_info *cu_info); +static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev); +static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 instance, int xcc_id); +static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val); +static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); +static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, + uint16_t pasid, uint32_t flush_type, + bool all_hub, uint8_t dst_sel); +static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); +static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); +static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, + bool enable); +static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, + bool enable, int xcc_id); +static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev); + +static void gfx_v12_1_kiq_set_resources(struct amdgpu_ring *kiq_ring, + uint64_t queue_mask) +{ + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); + amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | + PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ + amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ + amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ + amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ + amdgpu_ring_write(kiq_ring, 0); /* oac mask */ + amdgpu_ring_write(kiq_ring, 0); +} + +static void gfx_v12_1_kiq_map_queues(struct amdgpu_ring *kiq_ring, + struct amdgpu_ring *ring) +{ + uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); + uint64_t wptr_addr = ring->wptr_gpu_addr; + uint32_t me = 0, eng_sel = 0; + + switch (ring->funcs->type) { + case AMDGPU_RING_TYPE_COMPUTE: + me = 1; + eng_sel = 0; + break; + case AMDGPU_RING_TYPE_MES: + me = 2; + eng_sel = 5; + break; + default: + WARN_ON(1); + } + + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); + /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ + PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ + PACKET3_MAP_QUEUES_QUEUE(ring->queue) | + PACKET3_MAP_QUEUES_PIPE(ring->pipe) | + PACKET3_MAP_QUEUES_ME((me)) | + PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ + PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | + PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ + amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); + amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); + amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); +} + +static void gfx_v12_1_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, + struct amdgpu_ring *ring, + enum amdgpu_unmap_queues_action action, + u64 gpu_addr, u64 seq) +{ + struct amdgpu_device *adev = kiq_ring->adev; + uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; + + if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { + amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, + seq, kiq_ring->xcc_id); + return; + } + + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + PACKET3_UNMAP_QUEUES_ACTION(action) | + PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | + PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | + PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); + amdgpu_ring_write(kiq_ring, + PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); + + if (action == PREEMPT_QUEUES_NO_UNMAP) { + amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); + amdgpu_ring_write(kiq_ring, seq); + } else { + amdgpu_ring_write(kiq_ring, 0); + amdgpu_ring_write(kiq_ring, 0); + amdgpu_ring_write(kiq_ring, 0); + } +} + +static void gfx_v12_1_kiq_query_status(struct amdgpu_ring *kiq_ring, + struct amdgpu_ring *ring, + u64 addr, u64 seq) +{ + uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; + + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); + amdgpu_ring_write(kiq_ring, + PACKET3_QUERY_STATUS_CONTEXT_ID(0) | + PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | + PACKET3_QUERY_STATUS_COMMAND(2)); + amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ + PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | + PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); + amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); + amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); + amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); + amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); +} + +static void gfx_v12_1_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, + uint16_t pasid, + uint32_t flush_type, + bool all_hub) +{ + gfx_v12_1_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); +} + +static const struct kiq_pm4_funcs gfx_v12_1_kiq_pm4_funcs = { + .kiq_set_resources = gfx_v12_1_kiq_set_resources, + .kiq_map_queues = gfx_v12_1_kiq_map_queues, + .kiq_unmap_queues = gfx_v12_1_kiq_unmap_queues, + .kiq_query_status = gfx_v12_1_kiq_query_status, + .kiq_invalidate_tlbs = gfx_v12_1_kiq_invalidate_tlbs, + .set_resources_size = 8, + .map_queues_size = 7, + .unmap_queues_size = 6, + .query_status_size = 7, + .invalidate_tlbs_size = 2, +}; + +static void gfx_v12_1_set_kiq_pm4_funcs(struct amdgpu_device *adev) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i =0; i < num_xcc; i++) + adev->gfx.kiq[i].pmf = &gfx_v12_1_kiq_pm4_funcs; +} + +static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, + int mem_space, int opt, uint32_t addr0, + uint32_t addr1, uint32_t ref, + uint32_t mask, uint32_t inv) +{ + if (mem_space == 0) { + addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0); + addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1); + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, + /* memory (1) or register (0) */ + (WAIT_REG_MEM_MEM_SPACE(mem_space) | + WAIT_REG_MEM_OPERATION(opt) | /* wait */ + WAIT_REG_MEM_FUNCTION(3))); /* equal */ + + if (mem_space) + BUG_ON(addr0 & 0x3); /* Dword align */ + amdgpu_ring_write(ring, addr0); + amdgpu_ring_write(ring, addr1); + amdgpu_ring_write(ring, ref); + amdgpu_ring_write(ring, mask); + amdgpu_ring_write(ring, inv); /* poll interval */ +} + +static int gfx_v12_1_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t scratch_reg0_offset, xcc_offset; + uint32_t tmp = 0; + unsigned i; + int r; + + /* Use register offset which is local to XCC in the packet */ + xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); + scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); + WREG32(scratch_reg0_offset, 0xCAFEDEAD); + tmp = RREG32(scratch_reg0_offset); + + r = amdgpu_ring_alloc(ring, 5); + if (r) { + dev_err(adev->dev, + "amdgpu: cp failed to lock ring %d (%d).\n", + ring->idx, r); + return r; + } + + if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { + gfx_v12_1_ring_emit_wreg(ring, xcc_offset, 0xDEADBEEF); + } else { + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); + amdgpu_ring_write(ring, xcc_offset - + PACKET3_SET_UCONFIG_REG_START); + amdgpu_ring_write(ring, 0xDEADBEEF); + } + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32(scratch_reg0_offset); + if (tmp == 0xDEADBEEF) + break; + if (amdgpu_emu_mode == 1) + msleep(1); + else + udelay(1); + } + + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; + return r; +} + +static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + struct dma_fence *f = NULL; + unsigned index; + uint64_t gpu_addr; + volatile uint32_t *cpu_ptr; + long r; + + /* MES KIQ fw hasn't indirect buffer support for now */ + if (adev->enable_mes_kiq && + ring->funcs->type == AMDGPU_RING_TYPE_KIQ) + return 0; + + memset(&ib, 0, sizeof(ib)); + + r = amdgpu_device_wb_get(adev, &index); + if (r) + return r; + + gpu_addr = adev->wb.gpu_addr + (index * 4); + adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); + cpu_ptr = &adev->wb.wb[index]; + + r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib); + if (r) { + dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); + goto err1; + } + + ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); + ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + ib.ptr[2] = lower_32_bits(gpu_addr); + ib.ptr[3] = upper_32_bits(gpu_addr); + ib.ptr[4] = 0xDEADBEEF; + ib.length_dw = 5; + + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + if (r) + goto err2; + + r = dma_fence_wait_timeout(f, false, timeout); + if (r == 0) { + r = -ETIMEDOUT; + goto err2; + } else if (r < 0) { + goto err2; + } + + if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) + r = 0; + else + r = -EINVAL; +err2: + amdgpu_ib_free(&ib, NULL); + dma_fence_put(f); +err1: + amdgpu_device_wb_free(adev, index); + return r; +} + +static void gfx_v12_1_free_microcode(struct amdgpu_device *adev) +{ + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + + kfree(adev->gfx.rlc.register_list_format); +} + +static int gfx_v12_1_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) +{ + const struct psp_firmware_header_v1_0 *toc_hdr; + int err = 0; + + err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_toc.bin", ucode_prefix); + if (err) + goto out; + + toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; + adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); + adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); + adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); + adev->psp.toc.start_addr = (uint8_t *)toc_hdr + + le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); + return 0; +out: + amdgpu_ucode_release(&adev->psp.toc_fw); + return err; +} + +static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) +{ + char ucode_prefix[15]; + int err; + const struct rlc_firmware_header_v2_0 *rlc_hdr; + uint16_t version_major; + uint16_t version_minor; + + DRM_DEBUG("\n"); + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + + if (!amdgpu_sriov_vf(adev)) { + err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_rlc.bin", ucode_prefix); + if (err) + goto out; + rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + version_major = le16_to_cpu(rlc_hdr->header.header_version_major); + version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); + err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); + if (err) + goto out; + } + + err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, + AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_mec.bin", ucode_prefix); + if (err) + goto out; + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); + amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) + err = gfx_v12_1_init_toc_microcode(adev, ucode_prefix); + + /* only one MEC for gfx 12 */ + adev->gfx.mec2_fw = NULL; + + if (adev->gfx.imu.funcs) { + if (adev->gfx.imu.funcs->init_microcode) { + err = adev->gfx.imu.funcs->init_microcode(adev); + if (err) + dev_err(adev->dev, "Failed to load imu firmware!\n"); + } + } + +out: + if (err) { + amdgpu_ucode_release(&adev->gfx.rlc_fw); + amdgpu_ucode_release(&adev->gfx.mec_fw); + } + + return err; +} + +static u32 gfx_v12_1_get_csb_size(struct amdgpu_device *adev) +{ + u32 count = 0; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + count += 1; + + for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { + if (sect->id == SECT_CONTEXT) { + for (ext = sect->section; ext->extent != NULL; ++ext) + count += 2 + ext->reg_count; + } else + return 0; + } + + return count; +} + +static void gfx_v12_1_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) +{ + u32 count = 0, clustercount = 0, i; + const struct cs_section_def *sect = NULL; + const struct cs_extent_def *ext = NULL; + + if (adev->gfx.rlc.cs_data == NULL) + return; + if (buffer == NULL) + return; + + count += 1; + + for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { + if (sect->id == SECT_CONTEXT) { + for (ext = sect->section; ext->extent != NULL; ++ext) { + clustercount++; + buffer[count++] = ext->reg_count; + buffer[count++] = ext->reg_index; + + for (i = 0; i < ext->reg_count; i++) + buffer[count++] = cpu_to_le32(ext->extent[i]); + } + } else + return; + } + + buffer[0] = clustercount; +} + +static void gfx_v12_1_rlc_fini(struct amdgpu_device *adev) +{ + /* clear state block */ + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + + /* jump table block */ + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); +} + +static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) +{ + int xcc_id, num_xcc; + struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; + + reg_access_ctrl->grbm_cntl = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); + reg_access_ctrl->grbm_idx = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); + + reg_access_ctrl->vfi_cmd = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD); + reg_access_ctrl->vfi_stat = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT); + reg_access_ctrl->vfi_addr = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR); + reg_access_ctrl->vfi_data = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA); + reg_access_ctrl->vfi_grbm_cntl = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL); + reg_access_ctrl->vfi_grbm_idx = + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX); + reg_access_ctrl->vfi_grbm_cntl_data = 0; + reg_access_ctrl->vfi_grbm_idx_data = 0; + } + adev->gfx.rlc.rlcg_reg_access_supported = true; +} + +static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) +{ + const struct cs_section_def *cs_data; + int r, i, num_xcc; + + adev->gfx.rlc.cs_data = gfx12_cs_data; + + cs_data = adev->gfx.rlc.cs_data; + + if (cs_data) { + /* init clear state block */ + r = amdgpu_gfx_rlc_init_csb(adev); + if (r) + return r; + } + + /* init spm vmid with 0xf */ + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + if (adev->gfx.rlc.funcs->update_spm_vmid) + adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); + } + + return 0; +} + +static void gfx_v12_1_mec_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); + amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); +} + +static int gfx_v12_1_mec_init(struct amdgpu_device *adev) +{ + int r, i, num_xcc; + u32 *hpd; + size_t mec_hpd_size; + + bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, + AMDGPU_MAX_COMPUTE_QUEUES); + + /* take ownership of the relevant compute queues */ + amdgpu_gfx_compute_queue_acquire(adev); + mec_hpd_size = adev->gfx.num_compute_rings * + GFX12_MEC_HPD_SIZE * num_xcc; + + if (mec_hpd_size) { + r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.mec.hpd_eop_obj, + &adev->gfx.mec.hpd_eop_gpu_addr, + (void **)&hpd); + if (r) { + dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); + gfx_v12_1_mec_fini(adev); + return r; + } + + memset(hpd, 0, mec_hpd_size); + + amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); + amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); + } + + return 0; +} + +static uint32_t wave_read_ind(struct amdgpu_device *adev, + uint32_t xcc_id, uint32_t wave, + uint32_t address) +{ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (address << SQ_IND_INDEX__INDEX__SHIFT)); + return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); +} + +static void wave_read_regs(struct amdgpu_device *adev, + uint32_t xcc_id, uint32_t wave, + uint32_t thread, uint32_t regno, + uint32_t num, uint32_t *out) +{ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, + (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | + (regno << SQ_IND_INDEX__INDEX__SHIFT) | + (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | + (SQ_IND_INDEX__AUTO_INCR_MASK)); + while (num--) + *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); +} + +static void gfx_v12_1_read_wave_data(struct amdgpu_device *adev, + uint32_t xcc_id, + uint32_t simd, uint32_t wave, + uint32_t *dst, int *no_fields) +{ + /* in gfx12 the SIMD_ID is specified as part of the INSTANCE + * field when performing a select_se_sh so it should be + * zero here */ + WARN_ON(simd != 0); + + /* type 4 wave data */ + dst[(*no_fields)++] = 4; + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); + dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); +} + +static void gfx_v12_1_read_wave_sgprs(struct amdgpu_device *adev, + uint32_t xcc_id, uint32_t simd, + uint32_t wave, uint32_t start, + uint32_t size, uint32_t *dst) +{ + WARN_ON(simd != 0); + + wave_read_regs(adev, xcc_id, wave, 0, + start + SQIND_WAVE_SGPRS_OFFSET, + size, dst); +} + +static void gfx_v12_1_read_wave_vgprs(struct amdgpu_device *adev, + uint32_t xcc_id, uint32_t simd, + uint32_t wave, uint32_t thread, + uint32_t start, uint32_t size, + uint32_t *dst) +{ + wave_read_regs(adev, xcc_id, wave, thread, + start + SQIND_WAVE_VGPRS_OFFSET, + size, dst); +} + +static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) +{ + soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); +} + +static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) +{ + /* Fill this in when the interface is ready */ + return 1; +} + +static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) +{ + int logic_xcc; + int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4; + + for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { + if (xcc == GET_INST(GC, logic_xcc)) + return logic_xcc; + } + + dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); + return -EINVAL; +} + +static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { + .get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter, + .select_se_sh = &gfx_v12_1_xcc_select_se_sh, + .read_wave_data = &gfx_v12_1_read_wave_data, + .read_wave_sgprs = &gfx_v12_1_read_wave_sgprs, + .read_wave_vgprs = &gfx_v12_1_read_wave_vgprs, + .select_me_pipe_q = &gfx_v12_1_select_me_pipe_q, + .update_perfmon_mgcg = &gfx_v12_1_update_perf_clk, + .get_xccs_per_xcp = &gfx_v12_1_get_xccs_per_xcp, + .ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst, +}; + +static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 1, 0): + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + break; + default: + BUG(); + break; + } + + return 0; +} + +static int gfx_v12_1_compute_ring_init(struct amdgpu_device *adev, int ring_id, + int xcc_id, int mec, int pipe, int queue) +{ + int r; + unsigned irq_type; + struct amdgpu_ring *ring; + unsigned int hw_prio; + uint32_t xcc_doorbell_start; + + ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + + ring_id]; + + /* mec0 is me1 */ + ring->xcc_id = xcc_id; + ring->me = mec + 1; + ring->pipe = pipe; + ring->queue = queue; + + ring->ring_obj = NULL; + ring->use_doorbell = true; + xcc_doorbell_start = adev->doorbell_index.mec_ring0 + + xcc_id * adev->doorbell_index.xcc_doorbell_range; + ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; + ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + + (ring_id + xcc_id * adev->gfx.num_compute_rings) * + GFX12_MEC_HPD_SIZE; + ring->vm_hub = AMDGPU_GFXHUB(xcc_id); + sprintf(ring->name, "comp_%d.%d.%d.%d", + ring->xcc_id, ring->me, ring->pipe, ring->queue); + + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) + + ring->pipe; + hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? + AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; + /* type-2 packets are deprecated on MEC, use type-3 instead */ + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, + hw_prio, NULL); + if (r) + return r; + + return 0; +} + +static struct { + SOC24_FIRMWARE_ID id; + unsigned int offset; + unsigned int size; + unsigned int size_x16; + unsigned int num_inst; +} rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; + +#define RLC_TOC_OFFSET_DWUNIT 8 +#define RLC_SIZE_MULTIPLE 1024 +#define RLC_TOC_UMF_SIZE_inM 23ULL +#define RLC_TOC_FORMAT_API 165ULL + +#define RLC_NUM_INS_CODE0 1 +#define RLC_NUM_INS_CODE1 8 +#define RLC_NUM_INS_CODE2 2 +#define RLC_NUM_INS_CODE3 16 + +static void gfx_v12_1_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) +{ + RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; + + while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { + rlc_autoload_info[ucode->id].id = ucode->id; + rlc_autoload_info[ucode->id].offset = + ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; + rlc_autoload_info[ucode->id].size = + ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : + ucode->size * 4; + switch (ucode->vfflr_image_code) { + case 0: + rlc_autoload_info[ucode->id].num_inst = + RLC_NUM_INS_CODE0; + break; + case 1: + rlc_autoload_info[ucode->id].num_inst = + RLC_NUM_INS_CODE1; + break; + case 2: + rlc_autoload_info[ucode->id].num_inst = + RLC_NUM_INS_CODE2; + break; + case 3: + rlc_autoload_info[ucode->id].num_inst = + RLC_NUM_INS_CODE3; + break; + default: + dev_err(adev->dev, + "Invalid Instance number detected\n"); + break; + } + ucode++; + } +} + +static uint32_t gfx_v12_1_calc_toc_total_size(struct amdgpu_device *adev) +{ + uint32_t total_size = 0; + SOC24_FIRMWARE_ID id; + + gfx_v12_1_parse_rlc_toc(adev, adev->psp.toc.start_addr); + + for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) + total_size += rlc_autoload_info[id].size; + + /* In case the offset in rlc toc ucode is aligned */ + if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) + total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + + rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; + if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) + total_size = RLC_TOC_UMF_SIZE_inM << 20; + + return total_size; +} + +static int gfx_v12_1_rlc_autoload_buffer_init(struct amdgpu_device *adev) +{ + int r; + uint32_t total_size; + + total_size = gfx_v12_1_calc_toc_total_size(adev); + + r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.rlc.rlc_autoload_bo, + &adev->gfx.rlc.rlc_autoload_gpu_addr, + (void **)&adev->gfx.rlc.rlc_autoload_ptr); + + if (r) { + dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); + return r; + } + + return 0; +} + +static void gfx_v12_1_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, + SOC24_FIRMWARE_ID id, + const void *fw_data, + uint32_t fw_size) +{ + uint32_t toc_offset; + uint32_t toc_fw_size, toc_fw_inst_size; + char *ptr = adev->gfx.rlc.rlc_autoload_ptr; + int i, num_inst; + + if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) + return; + + toc_offset = rlc_autoload_info[id].offset; + toc_fw_size = rlc_autoload_info[id].size; + num_inst = rlc_autoload_info[id].num_inst; + toc_fw_inst_size = toc_fw_size / num_inst; + + if (fw_size == 0) + fw_size = toc_fw_inst_size; + + if (fw_size > toc_fw_inst_size) + fw_size = toc_fw_inst_size; + + for (i = 0; i < num_inst; i++) { + if ((num_inst == RLC_NUM_INS_CODE0) || + ((1 << (i / 2)) & adev->gfx.xcc_mask)) { + memcpy(ptr + toc_offset + i * toc_fw_inst_size, fw_data, fw_size); + + if (fw_size < toc_fw_inst_size) + memset(ptr + toc_offset + fw_size + i * toc_fw_inst_size, + 0, toc_fw_inst_size - fw_size); + } + } +} + +static void +gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) +{ + void *data; + uint32_t size; + uint32_t *toc_ptr; + + data = adev->psp.toc.start_addr; + size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; + + toc_ptr = (uint32_t *)data + size / 4 - 2; + *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; + + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, + data, size); +} + +static void +gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) +{ + const __le32 *fw_data; + uint32_t fw_size; + const struct gfx_firmware_header_v2_0 *cpv2_hdr; + const struct rlc_firmware_header_v2_0 *rlc_hdr; + const struct rlc_firmware_header_v2_1 *rlcv21_hdr; + const struct rlc_firmware_header_v2_2 *rlcv22_hdr; + uint16_t version_major, version_minor; + + /* mec ucode */ + cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) + adev->gfx.mec_fw->data; + /* instruction */ + fw_data = (const __le32 *) (adev->gfx.mec_fw->data + + le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); + fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, + fw_data, fw_size); + /* data */ + fw_data = (const __le32 *) (adev->gfx.mec_fw->data + + le32_to_cpu(cpv2_hdr->data_offset_bytes)); + fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, + fw_data, fw_size); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, + fw_data, fw_size); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, + fw_data, fw_size); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, + fw_data, fw_size); + + /* rlc ucode */ + rlc_hdr = (const struct rlc_firmware_header_v2_0 *) + adev->gfx.rlc_fw->data; + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, + fw_data, fw_size); + + version_major = le16_to_cpu(rlc_hdr->header.header_version_major); + version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); + if (version_major == 2) { + if (version_minor >= 1) { + rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); + fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, + fw_data, fw_size); + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); + fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, + fw_data, fw_size); + } + if (version_minor >= 2) { + rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); + fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, + fw_data, fw_size); + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); + fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, + fw_data, fw_size); + } + } +} + +static void +gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) +{ + const __le32 *fw_data; + uint32_t fw_size; + const struct sdma_firmware_header_v3_0 *sdma_hdr; + + if (adev->sdma.instance[0].fw) { + sdma_hdr = (const struct sdma_firmware_header_v3_0 *) + adev->sdma.instance[0].fw->data; + fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + + le32_to_cpu(sdma_hdr->ucode_offset_bytes)); + fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); + + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, + fw_data, fw_size); + } +} + +static void +gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) +{ + const __le32 *fw_data; + unsigned fw_size; + const struct mes_firmware_header_v1_0 *mes_hdr; + int pipe, ucode_id, data_id; + + for (pipe = 0; pipe < 2; pipe++) { + if (pipe == 0) { + ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; + data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; + } else { + ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; + data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; + } + + mes_hdr = (const struct mes_firmware_header_v1_0 *) + adev->mes.fw[pipe]->data; + + fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + + le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); + fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); + + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); + + fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + + le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); + fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); + + gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); + } +} + +static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) +{ + uint32_t rlc_g_offset, rlc_g_size; + uint64_t gpu_addr; + uint32_t data; + int i, num_xcc; + + /* RLC autoload sequence 2: copy ucode */ + gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev); + gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(adev); + gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(adev); + gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(adev); + + rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; + rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; + gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + WREG32_SOC15(GC, GET_INST(GC, i), + regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, + upper_32_bits(gpu_addr)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, + lower_32_bits(gpu_addr)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGFX_IMU_RLC_BOOTLOADER_SIZE, + rlc_g_size); + } + + if (adev->gfx.imu.funcs) { + /* RLC autoload sequence 3: load IMU fw */ + if (adev->gfx.imu.funcs->load_microcode) + adev->gfx.imu.funcs->load_microcode(adev); + } + + /* unhalt rlc to start autoload */ + for (i = 0; i < num_xcc; i++) { + data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE); + data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); + data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data); + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); + } + + return 0; +} + +static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) +{ + int i, j, k, r, ring_id = 0; + unsigned num_compute_rings; + int xcc_id, num_xcc; + struct amdgpu_device *adev = ip_block->adev; + + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 1, 0): + adev->gfx.mec.num_mec = 1; + adev->gfx.mec.num_pipe_per_mec = 4; + adev->gfx.mec.num_queue_per_pipe = 8; + break; + default: + adev->gfx.mec.num_mec = 2; + adev->gfx.mec.num_pipe_per_mec = 2; + adev->gfx.mec.num_queue_per_pipe = 4; + break; + } + + if (adev->gfx.num_compute_rings) { + /* recalculate compute rings to use based on hardware configuration */ + num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * + adev->gfx.mec.num_queue_per_pipe) / 2; + adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, + num_compute_rings); + } + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + /* EOP Event */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, + GFX_12_1_0__SRCID__CP_EOP_INTERRUPT, + &adev->gfx.eop_irq); + if (r) + return r; + + /* Privileged reg */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, + GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT, + &adev->gfx.priv_reg_irq); + if (r) + return r; + + /* Privileged inst */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, + GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT, + &adev->gfx.priv_inst_irq); + if (r) + return r; + + /* RLC POISON Error */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_RLC, + GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT, + &adev->gfx.rlc_poison_irq); + if (r) + return r; + + adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; + + r = gfx_v12_1_rlc_init(adev); + if (r) { + dev_err(adev->dev, "Failed to init rlc BOs!\n"); + return r; + } + + r = gfx_v12_1_mec_init(adev); + if (r) { + dev_err(adev->dev, "Failed to init MEC BOs!\n"); + return r; + } + + /* set up the compute queues - allocate horizontally across pipes */ + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + ring_id = 0; + for (i = 0; i < adev->gfx.mec.num_mec; ++i) { + for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { + for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { + if (!amdgpu_gfx_is_mec_queue_enabled(adev, + xcc_id, i, k, j)) + continue; + + r = gfx_v12_1_compute_ring_init(adev, ring_id, + xcc_id, i, k, j); + if (r) + return r; + + ring_id++; + } + } + } + + if (!adev->enable_mes_kiq) { + r = amdgpu_gfx_kiq_init(adev, GFX12_MEC_HPD_SIZE, xcc_id); + if (r) { + dev_err(adev->dev, "Failed to init KIQ BOs!\n"); + return r; + } + + r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); + if (r) + return r; + } + + r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_1_compute_mqd), xcc_id); + if (r) + return r; + } + + /* allocate visible FB for rlc auto-loading fw */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { + r = gfx_v12_1_rlc_autoload_buffer_init(adev); + if (r) + return r; + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + r = gfx_v12_1_init_cp_compute_microcode_bo(adev); + if (r) + return r; + } + + r = gfx_v12_1_gpu_early_init(adev); + if (r) + return r; + + r = amdgpu_gfx_sysfs_init(adev); + if (r) + return r; + + return 0; +} + +static void gfx_v12_1_rlc_autoload_buffer_fini(struct amdgpu_device *adev) +{ + amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, + &adev->gfx.rlc.rlc_autoload_gpu_addr, + (void **)&adev->gfx.rlc.rlc_autoload_ptr); +} + +static int gfx_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) +{ + int i, num_xcc; + struct amdgpu_device *adev = ip_block->adev; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) + amdgpu_ring_fini(&adev->gfx.compute_ring[i]); + + for (i = 0; i < num_xcc; i++) { + amdgpu_gfx_mqd_sw_fini(adev, i); + + if (!adev->enable_mes_kiq) { + amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); + amdgpu_gfx_kiq_fini(adev, i); + } + } + + gfx_v12_1_rlc_fini(adev); + gfx_v12_1_mec_fini(adev); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) + gfx_v12_1_rlc_autoload_buffer_fini(adev); + + gfx_v12_1_free_microcode(adev); + amdgpu_gfx_sysfs_fini(adev); + + return 0; +} + +static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 instance, int xcc_id) +{ + u32 data; + + if (instance == 0xffffffff) + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, + INSTANCE_BROADCAST_WRITES, 1); + else + data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, + instance); + + if (se_num == 0xffffffff) + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, + 1); + else + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); + + if (sh_num == 0xffffffff) + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, + 1); + else + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); + + WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); +} + +static u32 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device *adev, + int xcc_id) +{ + u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; + + gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE); + gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, + CC_GC_SA_UNIT_DISABLE, + SA_DISABLE); + gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE); + gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, + GC_USER_SA_UNIT_DISABLE, + SA_DISABLE); + sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * + adev->gfx.config.max_shader_engines); + + return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); +} + +static u32 gfx_v12_1_get_rb_active_bitmap(struct amdgpu_device *adev, + int xcc_id) +{ + u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; + u32 rb_mask; + + gc_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regCC_RB_BACKEND_DISABLE); + gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, + CC_RB_BACKEND_DISABLE, + BACKEND_DISABLE); + gc_user_disabled_rb_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regGC_USER_RB_BACKEND_DISABLE); + gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, + GC_USER_RB_BACKEND_DISABLE, + BACKEND_DISABLE); + rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * + adev->gfx.config.max_shader_engines); + + return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); +} + +static void gfx_v12_1_setup_rb(struct amdgpu_device *adev) +{ + u32 rb_bitmap_width_per_sa; + u32 max_sa; + u32 active_sa_bitmap; + u32 global_active_rb_bitmap; + u32 active_rb_bitmap = 0; + u32 i; + int xcc_id; + + for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { + /* query sa bitmap from SA_UNIT_DISABLE registers */ + active_sa_bitmap = gfx_v12_1_get_sa_active_bitmap(adev, xcc_id); + /* query rb bitmap from RB_BACKEND_DISABLE registers */ + global_active_rb_bitmap = gfx_v12_1_get_rb_active_bitmap(adev, xcc_id); + + /* generate active rb bitmap according to active sa bitmap */ + max_sa = adev->gfx.config.max_shader_engines * + adev->gfx.config.max_sh_per_se; + rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / + adev->gfx.config.max_sh_per_se; + for (i = 0; i < max_sa; i++) { + if (active_sa_bitmap & (1 << i)) + active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); + } + + active_rb_bitmap |= global_active_rb_bitmap; + } + + adev->gfx.config.backend_enable_mask = active_rb_bitmap; + adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); +} + +static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, + int xcc_id) +{ + int i; + uint32_t sh_mem_bases; + uint32_t data; + + /* + * Configure apertures: + * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) + * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) + */ + sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, + (adev->gmc.private_aperture_start >> 58)); + sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, + (adev->gmc.shared_aperture_start >> 48)); + + mutex_lock(&adev->srbm_mutex); + for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { + soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); + /* CP and shaders */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); + + /* Enable trap for each kfd vmid. */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); + + /* Disable VGPR deallocation instruction for each KFD vmid. */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG); + data = REG_SET_FIELD(data, SQ_DEBUG, DISABLE_VGPR_DEALLOC, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data); + } + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); +} + +static void gfx_v12_1_tcp_harvest(struct amdgpu_device *adev) +{ + /* TODO: harvest feature to be added later. */ +} + +static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev) +{ +} + +static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, + int xcc_id) +{ + u32 tmp; + int i; + + /* XXX SH_MEM regs */ + /* where to put LDS, scratch, GPUVM in FSA64 space */ + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { + soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); + /* CP and shaders */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); + if (i != 0) { + tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, + (adev->gmc.private_aperture_start >> 58)); + tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, + (adev->gmc.shared_aperture_start >> 48)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); + } + } + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + + mutex_unlock(&adev->srbm_mutex); + + gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); +} + +static void gfx_v12_1_constants_init(struct amdgpu_device *adev) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + gfx_v12_1_setup_rb(adev); + gfx_v12_1_get_cu_info(adev, &adev->gfx.cu_info); + gfx_v12_1_get_tcc_info(adev); + adev->gfx.config.pa_sc_tile_steering_override = 0; + + for (i = 0; i < num_xcc; i++) + gfx_v12_1_xcc_constants_init(adev, i); +} + +static void gfx_v12_1_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + u32 tmp; + + if (amdgpu_sriov_vf(adev)) + return; + + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); + + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, + enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, + enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, + enable ? 1 : 0); + tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, + enable ? 1 : 0); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); +} + +static int gfx_v12_1_xcc_init_csb(struct amdgpu_device *adev, + int xcc_id) +{ + adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI, + adev->gfx.rlc.clear_state_gpu_addr >> 32); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO, + adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); + + return 0; +} + +static void gfx_v12_1_xcc_rlc_stop(struct amdgpu_device *adev, + int xcc_id) +{ + u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL); + + tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp); +} + +static void gfx_v12_1_rlc_stop(struct amdgpu_device *adev) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + gfx_v12_1_xcc_rlc_stop(adev, i); +} + +static void gfx_v12_1_xcc_rlc_reset(struct amdgpu_device *adev, + int xcc_id) +{ + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), + GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); + udelay(50); + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), + GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); + udelay(50); +} + +static void gfx_v12_1_rlc_reset(struct amdgpu_device *adev) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + gfx_v12_1_xcc_rlc_reset(adev, i); +} + +static void gfx_v12_1_xcc_rlc_smu_handshake_cntl(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint32_t rlc_pg_cntl; + + rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL); + + if (!enable) { + /* RLC_PG_CNTL[23] = 0 (default) + * RLC will wait for handshake acks with SMU + * GFXOFF will be enabled + * RLC_PG_CNTL[23] = 1 + * RLC will not issue any message to SMU + * hence no handshake between SMU & RLC + * GFXOFF will be disabled + */ + rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; + } else + rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl); +} + +static void gfx_v12_1_xcc_rlc_start(struct amdgpu_device *adev, + int xcc_id) +{ + /* TODO: enable rlc & smu handshake until smu + * and gfxoff feature works as expected */ + if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) + gfx_v12_1_xcc_rlc_smu_handshake_cntl(adev, false, xcc_id); + + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1); + udelay(50); +} + +static void gfx_v12_1_rlc_start(struct amdgpu_device *adev) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + gfx_v12_1_xcc_rlc_start(adev, i); + } +} + +static void gfx_v12_1_xcc_rlc_enable_srm(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t tmp; + + /* enable Save Restore Machine */ + tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL)); + tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; + tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; + WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp); +} + +static void gfx_v12_1_xcc_load_rlcg_microcode(struct amdgpu_device *adev, + int xcc_id) +{ + const struct rlc_firmware_header_v2_0 *hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, + RLCG_UCODE_LOADING_START_ADDRESS); + + for (i = 0; i < fw_size; i++) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_GPM_UCODE_DATA, + le32_to_cpup(fw_data++)); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_GPM_UCODE_ADDR, + adev->gfx.rlc_fw_version); +} + +static void gfx_v12_1_xcc_load_rlc_iram_dram_microcode(struct amdgpu_device *adev, + int xcc_id) +{ + const struct rlc_firmware_header_v2_2 *hdr; + const __le32 *fw_data; + unsigned i, fw_size; + u32 tmp; + + hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); + fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0); + + for (i = 0; i < fw_size; i++) { + if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) + msleep(1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_LX6_IRAM_DATA, + le32_to_cpup(fw_data++)); + } + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); + + fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + + le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); + fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_LX6_DRAM_ADDR, 0); + for (i = 0; i < fw_size; i++) { + if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) + msleep(1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_LX6_DRAM_DATA, + le32_to_cpup(fw_data++)); + } + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); + + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL); + tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); + tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp); +} + +static int gfx_v12_1_xcc_rlc_load_microcode(struct amdgpu_device *adev, + int xcc_id) +{ + const struct rlc_firmware_header_v2_0 *hdr; + uint16_t version_major; + uint16_t version_minor; + + if (!adev->gfx.rlc_fw) + return -EINVAL; + + hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; + amdgpu_ucode_print_rlc_hdr(&hdr->header); + + version_major = le16_to_cpu(hdr->header.header_version_major); + version_minor = le16_to_cpu(hdr->header.header_version_minor); + + if (version_major == 2) { + gfx_v12_1_xcc_load_rlcg_microcode(adev, xcc_id); + if (amdgpu_dpm == 1) { + if (version_minor >= 2) + gfx_v12_1_xcc_load_rlc_iram_dram_microcode(adev, xcc_id); + } + + return 0; + } + + return -EINVAL; +} + +static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev, + int xcc_id) +{ + int r; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + gfx_v12_1_xcc_init_csb(adev, xcc_id); + + if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ + gfx_v12_1_xcc_rlc_enable_srm(adev, xcc_id); + } else { + if (amdgpu_sriov_vf(adev)) { + gfx_v12_1_xcc_init_csb(adev, xcc_id); + return 0; + } + + gfx_v12_1_xcc_rlc_stop(adev, xcc_id); + + /* disable CG */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); + + /* disable PG */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + /* legacy rlc firmware loading */ + r = gfx_v12_1_xcc_rlc_load_microcode(adev, xcc_id); + if (r) + return r; + } + + gfx_v12_1_xcc_init_csb(adev, xcc_id); + + gfx_v12_1_xcc_rlc_start(adev, xcc_id); + } + + return 0; +} + +static int gfx_v12_1_rlc_resume(struct amdgpu_device *adev) +{ + int r, i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + r = gfx_v12_1_xcc_rlc_resume(adev, i); + if (r) + return r; + } + + return 0; +} + +static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev, + int xcc_id) +{ + const struct gfx_firmware_header_v2_0 *mec_hdr; + uint32_t pipe_id, tmp; + + mec_hdr = (const struct gfx_firmware_header_v2_0 *) + adev->gfx.mec_fw->data; + + /* config mec program start addr */ + for (pipe_id = 0; pipe_id < 4; pipe_id++) { + soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, + mec_hdr->ucode_start_addr_lo >> 2 | + mec_hdr->ucode_start_addr_hi << 30); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, + mec_hdr->ucode_start_addr_hi >> 2); + } + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + + /* reset mec pipe */ + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); + + /* clear mec pipe reset */ + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); + tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); +} + +static void gfx_v12_1_config_gfx_rs64(struct amdgpu_device *adev) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + for (i = 0; i < num_xcc; i++) + gfx_v12_1_xcc_config_gfx_rs64(adev, i); +} + +static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev, + int xcc_id) +{ + const struct gfx_firmware_header_v2_0 *cp_hdr; + unsigned pipe_id; + + cp_hdr = (const struct gfx_firmware_header_v2_0 *) + adev->gfx.mec_fw->data; + mutex_lock(&adev->srbm_mutex); + for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { + soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, + cp_hdr->ucode_start_addr_lo >> 2 | + cp_hdr->ucode_start_addr_hi << 30); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, + cp_hdr->ucode_start_addr_hi >> 2); + } + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); +} + +static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t cp_status; + uint32_t bootload_status; + int i; + + for (i = 0; i < adev->usec_timeout; i++) { + cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT); + bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_RLCS_BOOTLOAD_STATUS); + + if ((cp_status == 0) && + (REG_GET_FIELD(bootload_status, + RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { + break; + } + udelay(1); + if (amdgpu_emu_mode) + msleep(10); + } + + if (i >= adev->usec_timeout) { + dev_err(adev->dev, + "rlc autoload: xcc%d gc ucode autoload timeout\n", xcc_id); + return -ETIMEDOUT; + } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { + gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); + } + + return 0; +} + +static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) +{ + int xcc_id; + + for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) + gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id); + + return 0; +} + +static void gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + u32 data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, + enable ? 0 : 1); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, + enable ? 0 : 1); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, + enable ? 0 : 1); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, + enable ? 0 : 1); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, + enable ? 0 : 1); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, + enable ? 1 : 0); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, + enable ? 1 : 0); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, + enable ? 1 : 0); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, + enable ? 1 : 0); + data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, + enable ? 0 : 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); + + adev->gfx.kiq[xcc_id].ring.sched.ready = enable; + + udelay(50); +} + +static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev) +{ + const struct gfx_firmware_header_v2_0 *mec_hdr; + const __le32 *fw_ucode, *fw_data; + u32 fw_ucode_size, fw_data_size; + u32 *fw_ucode_ptr, *fw_data_ptr; + int i, r, xcc_id; + + if (!adev->gfx.mec_fw) + return -EINVAL; + + mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; + amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); + + fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + + le32_to_cpu(mec_hdr->ucode_offset_bytes)); + fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); + + fw_data = (const __le32 *) (adev->gfx.mec_fw->data + + le32_to_cpu(mec_hdr->data_offset_bytes)); + fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); + + if (adev->gfx.mec.mec_fw_obj == NULL) { + r = amdgpu_bo_create_reserved(adev, fw_ucode_size, + 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.mec.mec_fw_obj, + &adev->gfx.mec.mec_fw_gpu_addr, + (void **)&fw_ucode_ptr); + if (r) { + dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); + gfx_v12_1_mec_fini(adev); + return r; + } + + memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); + + amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); + amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); + } + + if (adev->gfx.mec.mec_fw_data_obj == NULL) { + r = amdgpu_bo_create_reserved(adev, + ALIGN(fw_data_size, 64 * 1024) * + adev->gfx.mec.num_pipe_per_mec * NUM_XCC(adev->gfx.xcc_mask), + 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, + &adev->gfx.mec.mec_fw_data_obj, + &adev->gfx.mec.mec_fw_data_gpu_addr, + (void **)&fw_data_ptr); + if (r) { + dev_err(adev->dev, "(%d) failed to create mec fw data bo\n", r); + gfx_v12_1_mec_fini(adev); + return r; + } + + for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * + ALIGN(fw_data_size, 64 * 1024) / 4; + memcpy(fw_data_ptr + offset, fw_data, fw_data_size); + } + } + + amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); + amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); + } + + return 0; +} + +static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *adev, + int xcc_id) +{ + const struct gfx_firmware_header_v2_0 *mec_hdr; + u32 fw_data_size; + u32 tmp, i, usec_timeout = 50000; /* Wait for 50 ms */ + + if (!adev->gfx.mec_fw) + return -EINVAL; + + mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; + fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); + + gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); + + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); + + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); + tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); + + mutex_lock(&adev->srbm_mutex); + for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { + soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, + lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + + (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * + ALIGN(fw_data_size, 64 * 1024))); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, + upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + + (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * + ALIGN(fw_data_size, 64 * 1024))); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, + lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, + upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); + } + mutex_unlock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + + /* Trigger an invalidation of the L1 instruction caches */ + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); + tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); + + /* Wait for invalidation complete */ + for (i = 0; i < usec_timeout; i++) { + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); + if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, + INVALIDATE_DCACHE_COMPLETE)) + break; + udelay(1); + } + + if (i >= usec_timeout) { + dev_err(adev->dev, "failed to invalidate data cache\n"); + return -EINVAL; + } + + /* Trigger an invalidation of the L1 instruction caches */ + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); + tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); + + /* Wait for invalidation complete */ + for (i = 0; i < usec_timeout; i++) { + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); + if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, + INVALIDATE_CACHE_COMPLETE)) + break; + udelay(1); + } + + if (i >= usec_timeout) { + dev_err(adev->dev, "failed to invalidate instruction cache\n"); + return -EINVAL; + } + + gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); + + return 0; +} + +static void gfx_v12_1_xcc_kiq_setting(struct amdgpu_ring *ring, + int xcc_id) +{ + uint32_t tmp; + struct amdgpu_device *adev = ring->adev; + + /* tell RLC which is KIQ queue */ + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); + tmp &= 0xffffff00; + tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); + tmp |= 0x80; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); +} + +static void gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device *adev, + int xcc_id) +{ + /* disable gfx engine doorbell range */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0); + + /* set compute engine doorbell range */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER, + ((adev->doorbell_index.kiq + + xcc_id * adev->doorbell_index.xcc_doorbell_range) * + 2) << 2); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER, + ((adev->doorbell_index.userqueue_end + + xcc_id * adev->doorbell_index.xcc_doorbell_range) * + 2) << 2); +} + +static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, + struct amdgpu_mqd_prop *prop) +{ + struct v12_1_compute_mqd *mqd = m; + uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; + uint32_t tmp; + + mqd->header = 0xC0310800; + mqd->compute_pipelinestat_enable = 0x00000001; + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; + mqd->compute_misc_reserved = 0x00000007; + + eop_base_addr = prop->eop_gpu_addr >> 8; + mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; + mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = regCP_HQD_EOP_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, + (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); + + mqd->cp_hqd_eop_control = tmp; + + /* enable doorbell? */ + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; + + if (prop->use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, prop->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_HIT, 0); + } else { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 0); + } + + mqd->cp_hqd_pq_doorbell_control = tmp; + + /* disable the queue if it's active */ + mqd->cp_hqd_dequeue_request = 0; + mqd->cp_hqd_pq_rptr = 0; + mqd->cp_hqd_pq_wptr_lo = 0; + mqd->cp_hqd_pq_wptr_hi = 0; + + /* set the pointer to the MQD */ + mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); + + /* set MQD vmid to 0 */ + tmp = regCP_MQD_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); + mqd->cp_mqd_control = tmp; + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; + mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + tmp = regCP_HQD_PQ_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, + (order_base_2(prop->queue_size / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, + (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + mqd->cp_hqd_pq_control = tmp; + + /* set the wb address whether it's enabled or not */ + wb_gpu_addr = prop->rptr_gpu_addr; + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = prop->wptr_gpu_addr; + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + + tmp = 0; + /* enable the doorbell if requested */ + if (prop->use_doorbell) { + tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, prop->doorbell_index); + + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_HIT, 0); + } + + mqd->cp_hqd_pq_doorbell_control = tmp; + + /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; + + /* set the vmid for the queue */ + mqd->cp_hqd_vmid = 0; + + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63); + mqd->cp_hqd_persistent_state = tmp; + + /* set MIN_IB_AVAIL_SIZE */ + tmp = regCP_HQD_IB_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1); + mqd->cp_hqd_ib_control = tmp; + + /* set static priority for a compute queue/ring */ + mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; + mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; + + mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : + AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); + + mqd->cp_hqd_active = prop->hqd_active; + + return 0; +} + +static int gfx_v12_1_xcc_kiq_init_register(struct amdgpu_ring *ring, + int xcc_id) +{ + struct amdgpu_device *adev = ring->adev; + struct v12_1_compute_mqd *mqd = ring->mqd_ptr; + int j; + + /* inactivate the queue */ + if (amdgpu_sriov_vf(adev)) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); + + /* disable wptr polling */ + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); + + /* write the EOP addr */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, + mqd->cp_hqd_eop_base_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, + mqd->cp_hqd_eop_base_addr_hi); + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, + mqd->cp_hqd_eop_control); + + /* enable doorbell? */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, + mqd->cp_hqd_pq_doorbell_control); + + /* disable the queue if it's active */ + if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); + for (j = 0; j < adev->usec_timeout; j++) { + if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, + mqd->cp_hqd_dequeue_request); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, + mqd->cp_hqd_pq_rptr); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, + mqd->cp_hqd_pq_wptr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, + mqd->cp_hqd_pq_wptr_hi); + } + + /* set the pointer to the MQD */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, + mqd->cp_mqd_base_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, + mqd->cp_mqd_base_addr_hi); + + /* set MQD vmid to 0 */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, + mqd->cp_mqd_control); + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, + mqd->cp_hqd_pq_base_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, + mqd->cp_hqd_pq_base_hi); + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, + mqd->cp_hqd_pq_control); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, + mqd->cp_hqd_pq_rptr_report_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, + mqd->cp_hqd_pq_rptr_report_addr_hi); + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, + mqd->cp_hqd_pq_wptr_poll_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, + mqd->cp_hqd_pq_wptr_poll_addr_hi); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, + mqd->cp_hqd_pq_doorbell_control); + + /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, + mqd->cp_hqd_pq_wptr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, + mqd->cp_hqd_pq_wptr_hi); + + /* set the vmid for the queue */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, + mqd->cp_hqd_persistent_state); + + /* activate the queue */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, + mqd->cp_hqd_active); + + if (ring->use_doorbell) + WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); + + return 0; +} + +static int gfx_v12_1_xcc_kiq_init_queue(struct amdgpu_ring *ring, + int xcc_id) +{ + struct amdgpu_device *adev = ring->adev; + struct v12_1_compute_mqd *mqd = ring->mqd_ptr; + + gfx_v12_1_xcc_kiq_setting(ring, xcc_id); + + if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ + /* reset MQD to a clean status */ + if (adev->gfx.kiq[xcc_id].mqd_backup) + memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(*mqd)); + + /* reset ring buffer */ + ring->wptr = 0; + amdgpu_ring_clear_ring(ring); + + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); + gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + } else { + memset((void *)mqd, 0, sizeof(*mqd)); + if (amdgpu_sriov_vf(adev) && adev->in_suspend) + amdgpu_ring_clear_ring(ring); + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); + amdgpu_ring_init_mqd(ring); + gfx_v12_1_xcc_kiq_init_register(ring, xcc_id); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + if (adev->gfx.kiq[xcc_id].mqd_backup) + memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(*mqd)); + } + + return 0; +} + +static int gfx_v12_1_xcc_kcq_init_queue(struct amdgpu_ring *ring, + int xcc_id) +{ + struct amdgpu_device *adev = ring->adev; + struct v12_1_compute_mqd *mqd = ring->mqd_ptr; + int mqd_idx = ring - &adev->gfx.compute_ring[0]; + + if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + memset((void *)mqd, 0, sizeof(*mqd)); + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); + amdgpu_ring_init_mqd(ring); + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); + } else { + /* restore MQD to a clean status */ + if (adev->gfx.mec.mqd_backup[mqd_idx]) + memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); + /* reset ring buffer */ + ring->wptr = 0; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + amdgpu_ring_clear_ring(ring); + } + + return 0; +} + +static int gfx_v12_1_xcc_kiq_resume(struct amdgpu_device *adev, + int xcc_id) +{ + struct amdgpu_ring *ring; + int r; + + ring = &adev->gfx.kiq[xcc_id].ring; + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + return r; + + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (unlikely(r != 0)) { + amdgpu_bo_unreserve(ring->mqd_obj); + return r; + } + + gfx_v12_1_xcc_kiq_init_queue(ring, xcc_id); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + amdgpu_bo_unreserve(ring->mqd_obj); + ring->sched.ready = true; + return 0; +} + +static int gfx_v12_1_xcc_kcq_resume(struct amdgpu_device *adev, + int xcc_id) +{ + struct amdgpu_ring *ring = NULL; + int r = 0, i; + + if (!amdgpu_async_gfx_ring) + gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) + goto done; + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v12_1_xcc_kcq_init_queue(ring, xcc_id); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) + goto done; + } + + r = amdgpu_gfx_enable_kcq(adev, xcc_id); +done: + return r; +} + +static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask) +{ + int r, i, xcc_id; + struct amdgpu_ring *ring; + + for_each_inst(xcc_id, xcc_mask) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + /* legacy firmware loading */ + r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_id); + if (r) + return r; + } + + /* GFX CGCG and LS is set by default */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) + gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); + + gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); + + gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); + + if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) + r = amdgpu_mes_kiq_hw_init(adev, xcc_id); + else + r = gfx_v12_1_xcc_kiq_resume(adev, xcc_id); + if (r) + return r; + + r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); + if (r) + return r; + + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + } + } + + return 0; +} + +static int gfx_v12_1_cp_resume(struct amdgpu_device *adev) +{ + int num_xcc, num_xcp, num_xcc_per_xcp; + uint16_t xcc_mask; + int r = 0; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + if (amdgpu_sriov_vf(adev)) { + enum amdgpu_gfx_partition mode; + + mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, + AMDGPU_XCP_FL_NONE); + if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) + return -EINVAL; + if (adev->gfx.funcs && + adev->gfx.funcs->get_xccs_per_xcp) { + num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); + adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; + num_xcp = num_xcc / num_xcc_per_xcp; + } else { + return -EINVAL; + } + r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); + + } else { + if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, + AMDGPU_XCP_FL_NONE) == + AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) + r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, + amdgpu_user_partt_mode); + } + + if (r) + return r; + + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); + + return gfx_v12_1_xcc_cp_resume(adev, xcc_mask); +} + +static int gfx_v12_1_gfxhub_enable(struct amdgpu_device *adev) +{ + int r, i; + bool value; + + r = adev->gfxhub.funcs->gart_enable(adev); + if (r) + return r; + + value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? + false : true; + + adev->gfxhub.funcs->set_fault_enable_default(adev, value); + /* TODO investigate why TLB flush is needed, + * are we missing a flush somewhere else? */ + for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { + if (AMDGPU_IS_GFXHUB(i)) + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(i), 0); + } + + return 0; +} + +static int get_gb_addr_config(struct amdgpu_device *adev) +{ + u32 gb_addr_config; + + gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG_READ); + if (gb_addr_config == 0) + return -EINVAL; + + adev->gfx.config.gb_addr_config_fields.num_pkrs = + 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG_READ, NUM_PKRS); + + adev->gfx.config.gb_addr_config = gb_addr_config; + + adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << + REG_GET_FIELD(adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG_READ, NUM_PIPES); + + adev->gfx.config.max_tile_pipes = + adev->gfx.config.gb_addr_config_fields.num_pipes; + + adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << + REG_GET_FIELD(adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG_READ, MAX_COMPRESSED_FRAGS); + adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << + REG_GET_FIELD(adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG_READ, NUM_RB_PER_SE); + adev->gfx.config.gb_addr_config_fields.num_se = 1 << + REG_GET_FIELD(adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG_READ, NUM_SHADER_ENGINES); + adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + + REG_GET_FIELD(adev->gfx.config.gb_addr_config, + GB_ADDR_CONFIG_READ, PIPE_INTERLEAVE_SIZE)); + + return 0; +} + +static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); + data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG); + data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); +} + +static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + + /* Set the TCP UTCL0 register to enable atomics */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1); + data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); +} + +static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev, + int xcc_id) +{ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf); +} + +static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3); + data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); +} + +static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); + data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); +} + +static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { + gfx_v12_1_xcc_disable_burst(adev, i); + gfx_v12_1_xcc_enable_atomics(adev, i); + gfx_v12_1_xcc_disable_early_write_ack(adev, i); + gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); + } +} + +static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) +{ + int r, i, num_xcc; + struct amdgpu_device *adev = ip_block->adev; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { + /* rlc autoload firmware */ + r = gfx_v12_1_rlc_backdoor_autoload_enable(adev); + if (r) + return r; + } else { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + if (adev->gfx.imu.funcs) { + if (adev->gfx.imu.funcs->load_microcode) + adev->gfx.imu.funcs->load_microcode(adev); + } + + for (i = 0; i < num_xcc; i++) { + /* disable gpa mode in backdoor loading */ + gfx_v12_1_xcc_disable_gpa_mode(adev, i); + } + } + } + + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || + (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { + r = gfx_v12_1_wait_for_rlc_autoload_complete(adev); + if (r) { + dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); + return r; + } + } + + adev->gfx.is_poweron = true; + + if (get_gb_addr_config(adev)) + DRM_WARN("Invalid gb_addr_config !\n"); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) + gfx_v12_1_config_gfx_rs64(adev); + + r = gfx_v12_1_gfxhub_enable(adev); + if (r) + return r; + + gfx_v12_1_init_golden_registers(adev); + + gfx_v12_1_constants_init(adev); + + if (adev->nbio.funcs->gc_doorbell_init) + adev->nbio.funcs->gc_doorbell_init(adev); + + r = gfx_v12_1_rlc_resume(adev); + if (r) + return r; + + /* + * init golden registers and rlc resume may override some registers, + * reconfig them here + */ + gfx_v12_1_tcp_harvest(adev); + + r = gfx_v12_1_cp_resume(adev); + if (r) + return r; + + return r; +} + +static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t tmp; + + if (!adev->no_hw_access) { + if (amdgpu_gfx_disable_kcq(adev, xcc_id)) + DRM_ERROR("KCQ disable failed\n"); + + amdgpu_mes_kiq_hw_fini(adev, xcc_id); + } + + if (amdgpu_sriov_vf(adev)) { + /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); + tmp &= 0xffffff00; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); + } + gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); + gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); +} + +static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, + bool enable) +{ + unsigned int irq_type; + int m, p, r; + + if (adev->gfx.disable_kq) { + for (m = 0; m < adev->gfx.mec.num_mec; ++m) { + for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { + irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + + (m * adev->gfx.mec.num_pipe_per_mec) + + p; + if (enable) + r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, + irq_type); + else + r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, + irq_type); + if (r) + return r; + } + } + } + + return 0; +} + +static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, num_xcc; + + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + gfx_v12_1_set_userq_eop_interrupts(adev, false); + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + gfx_v12_1_xcc_fini(adev, i); + } + + adev->gfxhub.funcs->gart_disable(adev); + + adev->gfx.is_poweron = false; + + return 0; +} + +static int gfx_v12_1_suspend(struct amdgpu_ip_block *ip_block) +{ + return gfx_v12_1_hw_fini(ip_block); +} + +static int gfx_v12_1_resume(struct amdgpu_ip_block *ip_block) +{ + return gfx_v12_1_hw_init(ip_block); +} + +static bool gfx_v12_1_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), + regGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) + return false; + } + return true; +} + +static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + unsigned i; + struct amdgpu_device *adev = ip_block->adev; + + for (i = 0; i < adev->usec_timeout; i++) { + if (gfx_v12_1_is_idle(ip_block)) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) +{ + uint64_t clock = 0; + + if (adev->smuio.funcs && + adev->smuio.funcs->get_gpu_clock_counter) + clock = adev->smuio.funcs->get_gpu_clock_counter(adev); + else + dev_warn(adev->dev, "query gpu clock counter is not supported\n"); + + return clock; +} + +static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + + switch (amdgpu_user_queue) { + case -1: + default: + adev->gfx.disable_kq = true; + adev->gfx.disable_uq = true; + break; + case 0: + adev->gfx.disable_kq = false; + adev->gfx.disable_uq = true; + break; + } + + adev->gfx.funcs = &gfx_v12_1_gfx_funcs; + + if (adev->gfx.disable_kq) + adev->gfx.num_compute_rings = 0; + else + adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), + AMDGPU_MAX_COMPUTE_RINGS); + + gfx_v12_1_set_kiq_pm4_funcs(adev); + gfx_v12_1_set_ring_funcs(adev); + gfx_v12_1_set_irq_funcs(adev); + gfx_v12_1_set_rlc_funcs(adev); + gfx_v12_1_set_mqd_funcs(adev); + gfx_v12_1_set_imu_funcs(adev); + + gfx_v12_1_init_rlcg_reg_access_ctrl(adev); + + return gfx_v12_1_init_microcode(adev); +} + +static int gfx_v12_1_late_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); + if (r) + return r; + + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); + if (r) + return r; + + r = gfx_v12_1_set_userq_eop_interrupts(adev, true); + if (r) + return r; + + return 0; +} + +static bool gfx_v12_1_is_rlc_enabled(struct amdgpu_device *adev) +{ + uint32_t rlc_cntl; + + /* if RLC is not enabled, do nothing */ + rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); + return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; +} + +static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + unsigned i; + + data = RLC_SAFE_MODE__CMD_MASK; + data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); + + /* wait for RLC_SAFE_MODE */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) + break; + udelay(1); + } +} + +static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, + int xcc_id) +{ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); +} + +static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, + bool enable) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + gfx_v12_1_xcc_update_perf_clk(adev, enable, i); +} + +static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, + int xcc_id, + struct amdgpu_ring *ring, + unsigned vmid) +{ + u32 reg, data; + + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); + if (amdgpu_sriov_is_pp_one_vf(adev)) + data = RREG32_NO_KIQ(reg); + else + data = RREG32(reg); + + data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; + data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; + + if (amdgpu_sriov_is_pp_one_vf(adev)) + WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); + else + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); + + if (ring + && amdgpu_sriov_is_pp_one_vf(adev) + && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) + || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { + uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); + amdgpu_ring_emit_wreg(ring, reg, data); + } +} + +static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = { + .is_rlc_enabled = gfx_v12_1_is_rlc_enabled, + .set_safe_mode = gfx_v12_1_xcc_set_safe_mode, + .unset_safe_mode = gfx_v12_1_xcc_unset_safe_mode, + .init = gfx_v12_1_rlc_init, + .get_csb_size = gfx_v12_1_get_csb_size, + .get_csb_buffer = gfx_v12_1_get_csb_buffer, + .resume = gfx_v12_1_rlc_resume, + .stop = gfx_v12_1_rlc_stop, + .reset = gfx_v12_1_rlc_reset, + .start = gfx_v12_1_rlc_start, + .update_spm_vmid = gfx_v12_1_update_spm_vmid, +}; + +#if 0 +static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) +{ + /* TODO */ +} + +static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) +{ + /* TODO */ +} +#endif + +static int gfx_v12_1_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + bool enable = (state == AMD_PG_STATE_GATE); + + if (amdgpu_sriov_vf(adev)) + return 0; + + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 1, 0): + amdgpu_gfx_off_ctrl(adev, enable); + break; + default: + break; + } + + return 0; +} + +static void gfx_v12_1_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint32_t def, data; + + if (!(adev->cg_flags & + (AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS))) + return; + + if (enable) { + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_CGTT_MGCG_OVERRIDE); + + /* unset CGCG override */ + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || + adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; + + /* update CGCG override bits */ + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_CGTT_MGCG_OVERRIDE, data); + + /* enable cgcg FSM(0x0000363F) */ + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); + + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { + data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; + data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | + RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; + } + + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { + data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; + data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | + RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + } + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regRLC_CGCG_CGLS_CTRL, data); + + /* set IDLE_POLL_COUNT(0x00900100) */ + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); + + data &= ~CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK; + data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; + data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | + (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL); + data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); + data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); + data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); + data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data); + } else { + /* Program RLC_CGCG_CGLS_CTRL */ + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); + + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) + data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; + + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) + data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); + } +} + +static void gfx_v12_1_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint32_t data, def; + if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) + return; + + /* It is disabled by HW by default */ + if (enable) { + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { + /* 1 - RLC_CGTT_MGCG_OVERRIDE */ + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); + + data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); + } + } else { + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) { + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); + + data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); + } + } +} + +static void gfx_v12_1_xcc_update_repeater_fgcg(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint32_t def, data; + + if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) + return; + + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); + + if (enable) + data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); + else + data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | + RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); +} + +static void gfx_v12_1_xcc_update_sram_fgcg(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint32_t def, data; + + if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) + return; + + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); + + if (enable) + data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; + else + data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); +} + +static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint32_t def, data; + + if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) + return; + + def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); + + if (enable) + data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; + else + data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; + + if (def != data) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); +} + +static int gfx_v12_1_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); + + gfx_v12_1_xcc_update_coarse_grain_clock_gating(adev, enable, xcc_id); + + gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, enable, xcc_id); + + gfx_v12_1_xcc_update_repeater_fgcg(adev, enable, xcc_id); + + gfx_v12_1_xcc_update_sram_fgcg(adev, enable, xcc_id); + + gfx_v12_1_xcc_update_perf_clk(adev, enable, xcc_id); + + if (adev->cg_flags & + (AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS)) + gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, enable, xcc_id); + + amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); + + return 0; +} + +static int gfx_v12_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, num_xcc; + + if (amdgpu_sriov_vf(adev)) + return 0; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + switch (adev->ip_versions[GC_HWIP][0]) { + case IP_VERSION(12, 1, 0): + for (i = 0; i < num_xcc; i++) + gfx_v12_1_xcc_update_gfx_clock_gating(adev, + state == AMD_CG_STATE_GATE, i); + break; + default: + break; + } + + return 0; +} + +static void gfx_v12_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) +{ + struct amdgpu_device *adev = ip_block->adev; + int data; + + /* AMD_CG_SUPPORT_GFX_MGCG */ + data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE); + if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) + *flags |= AMD_CG_SUPPORT_GFX_MGCG; + + /* AMD_CG_SUPPORT_REPEATER_FGCG */ + if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) + *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; + + /* AMD_CG_SUPPORT_GFX_FGCG */ + if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) + *flags |= AMD_CG_SUPPORT_GFX_FGCG; + + /* AMD_CG_SUPPORT_GFX_PERF_CLK */ + if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) + *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; + + /* AMD_CG_SUPPORT_GFX_CGCG */ + data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL); + if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_CGCG; + + /* AMD_CG_SUPPORT_GFX_CGLS */ + if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) + *flags |= AMD_CG_SUPPORT_GFX_CGLS; +} + +static u64 gfx_v12_1_ring_get_rptr_compute(struct amdgpu_ring *ring) +{ + /* gfx12 hardware is 32bit rptr */ + return *(uint32_t *)ring->rptr_cpu_addr; +} + +static u64 gfx_v12_1_ring_get_wptr_compute(struct amdgpu_ring *ring) +{ + u64 wptr; + + /* XXX check if swapping is necessary on BE */ + if (ring->use_doorbell) + wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); + else + BUG(); + return wptr; +} + +static void gfx_v12_1_ring_set_wptr_compute(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + /* XXX check if swapping is necessary on BE */ + if (ring->use_doorbell) { + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, + ring->wptr); + WDOORBELL64(ring->doorbell_index, ring->wptr); + } else { + BUG(); /* only DOORBELL method supported on gfx12 now */ + } +} + +static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, + struct amdgpu_job *job, + struct amdgpu_ib *ib, + uint32_t flags) +{ + unsigned vmid = AMDGPU_JOB_GET_VMID(job); + u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); + + /* Currently, there is a high possibility to get wave ID mismatch + * between ME and GDS, leading to a hw deadlock, because ME generates + * different wave IDs than the GDS expects. This situation happens + * randomly when at least 5 compute pipes use GDS ordered append. + * The wave IDs generated by ME are also wrong after suspend/resume. + * Those are probably bugs somewhere else in the kernel driver. + * + * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and + * GDS to 0 for this ring (me/pipe). + */ + if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { + amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); + amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); + } + + amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); + BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ + amdgpu_ring_write(ring, +#ifdef __BIG_ENDIAN + (2 << 0) | +#endif + lower_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, control); +} + +static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) +{ + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + + /* RELEASE_MEM - flush caches, send int */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ(1) | + PACKET3_RELEASE_MEM_GCR_GLV_WB | + PACKET3_RELEASE_MEM_GCR_GL2_WB | + PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(2) | + PACKET3_RELEASE_MEM_TEMPORAL(3) | + PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | + PACKET3_RELEASE_MEM_EVENT_INDEX(5))); + amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | + PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); + + /* + * the address should be Qword aligned if 64bit write, Dword + * aligned if only send 32bit data low (discard data high) + */ + if (write64bit) + BUG_ON(addr & 0x7); + else + BUG_ON(addr & 0x3); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + amdgpu_ring_write(ring, 0); +} + +static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +{ + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; + + gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr), + upper_32_bits(addr), seq, 0xffffffff, 4); +} + +static void gfx_v12_1_ring_invalidate_tlbs(struct amdgpu_ring *ring, + uint16_t pasid, uint32_t flush_type, + bool all_hub, uint8_t dst_sel) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); + amdgpu_ring_write(ring, + PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | + PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | + PACKET3_INVALIDATE_TLBS_PASID(pasid) | + PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); +} + +static void gfx_v12_1_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) +{ + amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); + + /* compute doesn't have PFP */ + if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { + /* sync PFP to ME, otherwise we might get invalid PFP reads */ + amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); + amdgpu_ring_write(ring, 0x0); + } +} + +static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned int flags) +{ + struct amdgpu_device *adev = ring->adev; + + /* we only allocate 32bit for each seq wb address */ + BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + /* write fence seq to the "addr" */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + if (flags & AMDGPU_FENCE_FLAG_INT) { + /* set register to trigger INT */ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); + amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ + } +} + +static void gfx_v12_1_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, + uint32_t reg_val_offs) +{ + struct amdgpu_device *adev = ring->adev; + + reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); + amdgpu_ring_write(ring, 0 | /* src: register*/ + (5 << 8) | /* dst: memory */ + (1 << 20)); /* write confirm */ + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + + reg_val_offs * 4)); + amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + + reg_val_offs * 4)); +} + +static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, + uint32_t reg, + uint32_t val) +{ + uint32_t cmd = 0; + + reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + switch (ring->funcs->type) { + case AMDGPU_RING_TYPE_KIQ: + cmd = (1 << 16); /* no inc addr */ + break; + default: + cmd = WR_CONFIRM; + break; + } + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, cmd); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v12_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val, uint32_t mask) +{ + gfx_v12_1_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); +} + +static void gfx_v12_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, + uint32_t reg0, uint32_t reg1, + uint32_t ref, uint32_t mask) +{ + gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, + ref, mask, 0x20); +} + +static void gfx_v12_1_xcc_set_compute_eop_interrupt_state(struct amdgpu_device *adev, + int me, int pipe, + enum amdgpu_interrupt_state state, + int xcc_id) +{ + u32 mec_int_cntl, mec_int_cntl_reg; + + /* + * amdgpu controls only the first MEC. That's why this function only + * handles the setting of interrupts for this specific MEC. All other + * pipes' interrupts are set by amdkfd. + */ + + if (me == 1) { + switch (pipe) { + case 0: + mec_int_cntl_reg = SOC15_REG_OFFSET( + GC, GET_INST(GC, xcc_id), + regCP_ME1_PIPE0_INT_CNTL); + break; + case 1: + mec_int_cntl_reg = SOC15_REG_OFFSET( + GC, GET_INST(GC, xcc_id), + regCP_ME1_PIPE1_INT_CNTL); + break; + case 2: + mec_int_cntl_reg = SOC15_REG_OFFSET( + GC, GET_INST(GC, xcc_id), + regCP_ME1_PIPE2_INT_CNTL); + break; + case 3: + mec_int_cntl_reg = SOC15_REG_OFFSET( + GC, GET_INST(GC, xcc_id), + regCP_ME1_PIPE3_INT_CNTL); + break; + default: + DRM_DEBUG("invalid pipe %d\n", pipe); + return; + } + } else { + DRM_DEBUG("invalid me %d\n", me); + return; + } + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + TIME_STAMP_INT_ENABLE, 0); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + GENERIC0_INT_ENABLE, 0); + WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); + break; + case AMDGPU_IRQ_STATE_ENABLE: + mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + TIME_STAMP_INT_ENABLE, 1); + mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, + GENERIC0_INT_ENABLE, 1); + WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); + break; + default: + break; + } +} + +static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned type, + enum amdgpu_interrupt_state state) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + switch (type) { + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: + gfx_v12_1_xcc_set_compute_eop_interrupt_state( + adev, 1, 0, state, i); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: + gfx_v12_1_xcc_set_compute_eop_interrupt_state( + adev, 1, 1, state, i); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: + gfx_v12_1_xcc_set_compute_eop_interrupt_state( + adev, 1, 2, state, i); + break; + case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: + gfx_v12_1_xcc_set_compute_eop_interrupt_state( + adev, 1, 3, state, i); + break; + default: + break; + } + } + + return 0; +} + +static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u32 doorbell_offset = entry->src_data[0]; + u8 me_id, pipe_id, queue_id; + struct amdgpu_ring *ring; + int i, xcc_id; + + DRM_DEBUG("IH: CP EOP\n"); + + if (adev->enable_mes && doorbell_offset) { + struct amdgpu_userq_fence_driver *fence_drv = NULL; + struct xarray *xa = &adev->userq_xa; + unsigned long flags; + + xa_lock_irqsave(xa, flags); + fence_drv = xa_load(xa, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + xa_unlock_irqrestore(xa, flags); + } else { + me_id = (entry->ring_id & 0x0c) >> 2; + pipe_id = (entry->ring_id & 0x03) >> 0; + queue_id = (entry->ring_id & 0x70) >> 4; + xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); + + if (xcc_id == -EINVAL) + return -EINVAL; + + switch (me_id) { + case 1: + case 2: + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring + [i + + xcc_id * adev->gfx.num_compute_rings]; + /* Per-queue interrupt is supported for MEC starting from VI. + * The interrupt can only be enabled/disabled per pipe instead + * of per queue. + */ + if ((ring->me == me_id) && + (ring->pipe == pipe_id) && + (ring->queue == queue_id)) + amdgpu_fence_process(ring); + } + break; + default: + dev_dbg(adev->dev, "Unexpected me %d in eop_irq\n", me_id); + break; + } + } + + return 0; +} + +static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + case AMDGPU_IRQ_STATE_ENABLE: + for (i = 0; i < num_xcc; i++) + WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, + PRIV_REG_INT_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); + break; + default: + break; + } + + return 0; +} + +static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + case AMDGPU_IRQ_STATE_ENABLE: + for (i = 0; i < num_xcc; i++) + WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, + PRIV_INSTR_INT_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); + break; + default: + break; + } + + return 0; +} + +static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, + struct amdgpu_iv_entry *entry) +{ + u8 me_id, pipe_id, queue_id; + struct amdgpu_ring *ring; + int i, xcc_id; + + me_id = (entry->ring_id & 0x0c) >> 2; + pipe_id = (entry->ring_id & 0x03) >> 0; + queue_id = (entry->ring_id & 0x70) >> 4; + xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); + + if (xcc_id == -EINVAL) + return; + + if (!adev->gfx.disable_kq) { + switch (me_id) { + case 1: + case 2: + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring + [i + + xcc_id * adev->gfx.num_compute_rings]; + if (ring->me == me_id && ring->pipe == pipe_id && + ring->queue == queue_id) + drm_sched_fault(&ring->sched); + } + break; + default: + dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); + break; + } + } +} + +static int gfx_v12_1_priv_reg_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal register access in command stream\n"); + gfx_v12_1_handle_priv_fault(adev, entry); + return 0; +} + +static int gfx_v12_1_priv_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_ERROR("Illegal instruction in command stream\n"); + gfx_v12_1_handle_priv_fault(adev, entry); + return 0; +} + +static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t rlc_fed_status = 0; + uint32_t ras_blk = RAS_BLOCK_ID__GFX; + struct ras_ih_info ih_info = {0}; + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + rlc_fed_status |= RREG32(SOC15_REG_OFFSET(GC, + GET_INST(GC, i), regRLC_RLCS_FED_STATUS)); + + if (!rlc_fed_status) + return 0; + + if (REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA0_FED_ERR) || + REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA1_FED_ERR)) + ras_blk = RAS_BLOCK_ID__SDMA; + + dev_warn(adev->dev, "RLC %d FED IRQ\n", ras_blk); + + ih_info.block = ras_blk; + ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); + return 0; +} + +static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) +{ + const unsigned int gcr_cntl = + PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1) | + PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(2); + + /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ + amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); + amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ + amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ + amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ +} + +static const struct amd_ip_funcs gfx_v12_1_ip_funcs = { + .name = "gfx_v12_1", + .early_init = gfx_v12_1_early_init, + .late_init = gfx_v12_1_late_init, + .sw_init = gfx_v12_1_sw_init, + .sw_fini = gfx_v12_1_sw_fini, + .hw_init = gfx_v12_1_hw_init, + .hw_fini = gfx_v12_1_hw_fini, + .suspend = gfx_v12_1_suspend, + .resume = gfx_v12_1_resume, + .is_idle = gfx_v12_1_is_idle, + .wait_for_idle = gfx_v12_1_wait_for_idle, + .set_clockgating_state = gfx_v12_1_set_clockgating_state, + .set_powergating_state = gfx_v12_1_set_powergating_state, + .get_clockgating_state = gfx_v12_1_get_clockgating_state, +}; + +static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, + .get_rptr = gfx_v12_1_ring_get_rptr_compute, + .get_wptr = gfx_v12_1_ring_get_wptr_compute, + .set_wptr = gfx_v12_1_ring_set_wptr_compute, + .emit_frame_size = + 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + + 2 + /* gfx_v12_1_ring_emit_vm_flush */ + 8 + 8 + 8 + /* gfx_v12_1_ring_emit_fence x3 for user fence, vm fence */ + 8, /* gfx_v12_1_emit_mem_sync */ + .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ + .emit_ib = gfx_v12_1_ring_emit_ib_compute, + .emit_fence = gfx_v12_1_ring_emit_fence, + .emit_pipeline_sync = gfx_v12_1_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v12_1_ring_emit_vm_flush, + .test_ring = gfx_v12_1_ring_test_ring, + .test_ib = gfx_v12_1_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, + .emit_wreg = gfx_v12_1_ring_emit_wreg, + .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, + .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, + .emit_mem_sync = gfx_v12_1_emit_mem_sync, +}; + +static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_kiq = { + .type = AMDGPU_RING_TYPE_KIQ, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, + .get_rptr = gfx_v12_1_ring_get_rptr_compute, + .get_wptr = gfx_v12_1_ring_get_wptr_compute, + .set_wptr = gfx_v12_1_ring_set_wptr_compute, + .emit_frame_size = + 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + + 2 + /* gfx_v12_1_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v12_1_ring_emit_fence_kiq x3 for user fence, vm fence */ + .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ + .emit_ib = gfx_v12_1_ring_emit_ib_compute, + .emit_fence = gfx_v12_1_ring_emit_fence_kiq, + .test_ring = gfx_v12_1_ring_test_ring, + .test_ib = gfx_v12_1_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .pad_ib = amdgpu_ring_generic_pad_ib, + .emit_rreg = gfx_v12_1_ring_emit_rreg, + .emit_wreg = gfx_v12_1_ring_emit_wreg, + .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, + .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, +}; + +static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev) +{ + int i, j, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + adev->gfx.kiq[i].ring.funcs = &gfx_v12_1_ring_funcs_kiq; + + for (j = 0; j < adev->gfx.num_compute_rings; j++) + adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs = + &gfx_v12_1_ring_funcs_compute; + } +} + +static const struct amdgpu_irq_src_funcs gfx_v12_1_eop_irq_funcs = { + .set = gfx_v12_1_set_eop_interrupt_state, + .process = gfx_v12_1_eop_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_reg_irq_funcs = { + .set = gfx_v12_1_set_priv_reg_fault_state, + .process = gfx_v12_1_priv_reg_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_inst_irq_funcs = { + .set = gfx_v12_1_set_priv_inst_fault_state, + .process = gfx_v12_1_priv_inst_irq, +}; + +static const struct amdgpu_irq_src_funcs gfx_v12_1_rlc_poison_irq_funcs = { + .process = gfx_v12_1_rlc_poison_irq, +}; + +static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; + adev->gfx.eop_irq.funcs = &gfx_v12_1_eop_irq_funcs; + + adev->gfx.priv_reg_irq.num_types = 1; + adev->gfx.priv_reg_irq.funcs = &gfx_v12_1_priv_reg_irq_funcs; + + adev->gfx.priv_inst_irq.num_types = 1; + adev->gfx.priv_inst_irq.funcs = &gfx_v12_1_priv_inst_irq_funcs; + + adev->gfx.rlc_poison_irq.num_types = 1; + adev->gfx.rlc_poison_irq.funcs = &gfx_v12_1_rlc_poison_irq_funcs; +} + +static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev) +{ + if (adev->flags & AMD_IS_APU) + adev->gfx.imu.mode = MISSION_MODE; + else + adev->gfx.imu.mode = DEBUG_MODE; + if (!amdgpu_sriov_vf(adev)) + adev->gfx.imu.funcs = &gfx_v12_1_imu_funcs; +} + +static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev) +{ + adev->gfx.rlc.funcs = &gfx_v12_1_rlc_funcs; +} + +static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev) +{ + /* set compute eng mqd */ + adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = + sizeof(struct v12_1_compute_mqd); + adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = + gfx_v12_1_compute_mqd_init; +} + +static void gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device *adev, + u32 bitmap, int xcc_id) +{ + u32 data; + + if (!bitmap) + return; + + data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; + data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); +} + +static u32 gfx_v12_1_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev, + int xcc_id) +{ + u32 data, mask; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); + data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); + + data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; + data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; + + mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); + + return (~data) & mask; +} + +static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, + struct amdgpu_cu_info *cu_info) +{ + int i, j, k, counter, xcc_id, active_cu_number = 0; + u32 mask, bitmap; + unsigned int disable_masks[2 * 2]; + + if (!adev || !cu_info) + return -EINVAL; + + if (adev->gfx.config.max_shader_engines > 2 || + adev->gfx.config.max_sh_per_se > 2) { + dev_err(adev->dev, + "Max SE (%d) and Max SA per SE (%d) is greater than expected\n", + adev->gfx.config.max_shader_engines, + adev->gfx.config.max_sh_per_se); + return -EINVAL; + } + + amdgpu_gfx_parse_disable_cu(adev, disable_masks, + adev->gfx.config.max_shader_engines, + adev->gfx.config.max_sh_per_se); + + mutex_lock(&adev->grbm_idx_mutex); + for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + bitmap = i * adev->gfx.config.max_sh_per_se + j; + if (!((gfx_v12_1_get_sa_active_bitmap(adev, xcc_id) >> bitmap) & 1)) + continue; + mask = 1; + counter = 0; + gfx_v12_1_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); + gfx_v12_1_set_user_cu_inactive_bitmap_per_sh( + adev, + disable_masks[i * adev->gfx.config.max_sh_per_se + j], + xcc_id); + bitmap = gfx_v12_1_get_cu_active_bitmap_per_sh(adev, xcc_id); + + cu_info->bitmap[xcc_id][i][j] = bitmap; + + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { + if (bitmap & mask) + counter++; + + mask <<= 1; + } + active_cu_number += counter; + } + } + gfx_v12_1_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); + } + mutex_unlock(&adev->grbm_idx_mutex); + + cu_info->number = active_cu_number; + cu_info->simd_per_cu = NUM_SIMD_PER_CU_GFX12_1; + cu_info->lds_size = 320; + + return 0; +} + +const struct amdgpu_ip_block_version gfx_v12_1_ip_block = { + .type = AMD_IP_BLOCK_TYPE_GFX, + .major = 12, + .minor = 1, + .rev = 0, + .funcs = &gfx_v12_1_ip_funcs, +}; + +static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + uint32_t tmp_mask; + int i, r; + + /* TODO : Initialize golden regs */ + /* gfx_v12_1_init_golden_registers(adev); */ + + tmp_mask = inst_mask; + for_each_inst(i, tmp_mask) + gfx_v12_1_xcc_constants_init(adev, i); + + if (!amdgpu_sriov_vf(adev)) { + tmp_mask = inst_mask; + for_each_inst(i, tmp_mask) { + r = gfx_v12_1_xcc_rlc_resume(adev, i); + if (r) + return r; + } + } + + r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); + + return r; +} + +static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; + + for_each_inst(i, inst_mask) + gfx_v12_1_xcc_fini(adev, i); + + return 0; +} + +struct amdgpu_xcp_ip_funcs gfx_v12_1_xcp_funcs = { + .suspend = &gfx_v12_1_xcp_suspend, + .resume = &gfx_v12_1_xcp_resume +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.h new file mode 100644 index 0000000000000..684d93a1e2f8e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.h @@ -0,0 +1,31 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFX_V12_1_H__ +#define __GFX_V12_1_H__ + +extern const struct amdgpu_ip_block_version gfx_v12_1_ip_block; + +extern struct amdgpu_xcp_ip_funcs gfx_v12_1_xcp_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h new file mode 100644 index 0000000000000..21a07530c64d5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h @@ -0,0 +1,454 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef GFX_V12_1_PKT_H +#define GFX_V12_1_PKT_H + +/** + * PM4 definitions + */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + ((reg) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 +#define PACKET3_CLEAR_STATE 0x12 +#define PACKET3_INDEX_BUFFER_SIZE 0x13 +#define PACKET3_DISPATCH_DIRECT 0x15 +#define PACKET3_DISPATCH_INDIRECT 0x16 +#define PACKET3_ATOMIC_MEM 0x1E +#define PACKET3_OCCLUSION_QUERY 0x1F +#define PACKET3_SET_PREDICATION 0x20 +#define PACKET3_REG_RMW 0x21 +#define PACKET3_COND_EXEC 0x22 +#define PACKET3_PRED_EXEC 0x23 +#define PACKET3_DRAW_INDIRECT 0x24 +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 +#define PACKET3_INDEX_BASE 0x26 +#define PACKET3_DRAW_INDEX_2 0x27 +#define PACKET3_CONTEXT_CONTROL 0x28 +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C +#define PACKET3_DRAW_INDEX_AUTO 0x2D +#define PACKET3_NUM_INSTANCES 0x2F +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 +#define PACKET3_WRITE_DATA 0x37 +#define WRITE_DATA_DST_SEL(x) (((x) & 0xf) << 8) + /* 0 - register + * 1 - reserved + * 2 - tc_l2 + * 3 - reserved + * 4 - reserved + * 5 - memory (same as tc_l2) + * 6 - memory_mapped_adc_persistent_state + */ +#define WRITE_DATA_SCOPE(x) (((x) & 0x3) << 12) +#define WRITE_DATA_MODE(x) (((x) & 0x3) << 14) + /* 0 - local xcd + * 1 - remote/local aid + * 2 - remote xcd + * 3 - remote mid + */ +#define WRITE_DATA_ADDR_INCR (1 << 16) +#define WRITE_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) +#define WR_CONFIRM (1 << 20) +#define WRITE_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) +#define WRITE_DATA_TEMPORAL(x) (((x) & 0x3) << 25) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu + */ +#define WRITE_DATA_COOP_DISABLE (1 << 27) +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PACKET3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_FUNCTION(x) (((x) & 0x7) << 0) + /* 0 - always + * 1 - < + * 2 - <= + * 3 - == + * 4 - != + * 5 - >= + * 6 - > + */ +#define WAIT_REG_MEM_MEM_SPACE(x) (((x) & 0x3) << 4) + /* 0 - reg + * 1 - mem + */ +#define WAIT_REG_MEM_OPERATION(x) (((x) & 0x3) << 6) + /* 0 - wait_reg_mem + * 1 - wr_wait_wr_reg + */ +#define WAIT_REG_MEM_MODE(x) (((x) & 0x3) << 10) + /* 0 - local xcd + * 1 - remote/local aid + * 2 - remote xcd + * 3 - remote mid + */ +#define WAIT_REG_MEM_MID_DIE_ID(x) (((x) & 0x3) << 12) +#define WAIT_REG_MEM_XCD_DIE_ID(x) (((x) & 0xf) << 14) +#define WAIT_REG_MEM_MES_INTR_PIPE(x) (((x) & 0x3) << 22) +#define WAIT_REG_MEM_MES_ACTION(x) (((x) & 0x1) << 24) +#define WAIT_REG_MEM_TEMPORAL(x) (((x) & 0x3) << 25) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu + */ +#define PACKET3_INDIRECT_BUFFER 0x3F +#define INDIRECT_BUFFER_VALID (1 << 23) +#define INDIRECT_BUFFER_TEMPORAL(x) (x) << 28) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu + */ +#define PACKET3_COND_INDIRECT_BUFFER 0x3F +#define PACKET3_COPY_DATA 0x40 +#define COPY_DATA_SRC_SEL(x) (((x) & 0xf) << 0) +#define COPY_DATA_DST_SEL(x) (((x) & 0xf) << 8) +#define COPY_DATA_SRC_SCOPE(x) (((x) & 0x3) << 4) +#define COPY_DATA_DST_SCOPE(x) (((x) & 0x3) << 27) +#define COPY_DATA_MODE(x) (((x) & 0x3) << 6) + /* 0 - local xcd + * 1 - remote/local aid + * 2 - remote xcd + * 3 - remote mid + */ +#define COPY_DATA_SRC_TEMPORAL(x) (((x) & 0x3) << 13) +#define COPY_DATA_DST_TEMPORAL(x) (((x) & 0x3) << 25) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu + */ +#define COPY_DATA_COUNT_SEL (1 << 16) +#define COPY_DATA_SRC_DST_REMOTE_MODE(x) (((x)) & 0x1 << 16) + /* 0 - src remote + * 1 - dst remote + */ +#define COPY_DATA_MID_DIE_ID(x) (((x) & 0x3) << 18) +#define COPY_DATA_XCD_DIE_ID(x) (((x) & 0xf) << 21) +#define COPY_DATA_PQ_EXE_STATUS (1 << 27) +#define PACKET3_PFP_SYNC_ME 0x42 +#define PACKET3_COND_WRITE 0x45 +#define PACKET3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) +#define EVENT_INDEX(x) ((x) << 8) + /* 0 - any non-TS event + * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* + * 2 - SAMPLE_PIPELINESTAT + * 3 - SAMPLE_STREAMOUTSTAT* + * 4 - *S_PARTIAL_FLUSH + */ +#define PACKET3_RELEASE_MEM 0x49 +#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) +#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) +#define PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(x) ((x) << 12) +#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) +#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) +#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE(x) ((x) << 17) +#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) +#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) +#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) +#define PACKET3_RELEASE_MEM_GCR_SEQ(x) ((x) << 22) +#define PACKET3_RELEASE_MEM_GCR_GLV_WB (1 << 24) +#define PACKET3_RELEASE_MEM_TEMPORAL(x) ((x) << 25) + /* 0 - temporal__release_mem__rt + * 1 - temporal__release_mem__nt + * 2 - temporal__release_mem__ht + * 3 - temporal__release_mem__lu + */ +#define PACKET3_RELEASE_MEM_PQ_EXE_STATUS (1 << 28) +#define PACKET3_RELEASE_MEM_GCR_GLK_INV (1 << 30) + +#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) + /* 0 - memory controller + * 1 - TC/L2 + * 2 - register + */ +#define PACKET3_RELEASE_MEM_MES_INTR_PIPE(x) ((x) << 20) +#define PACKET3_RELEASE_MEM_MES_ACTION_ID(x) ((x) << 22) +#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) + /* 0 - none + * 1 - interrupt only (DATA_SEL = 0) + * 2 - interrupt when data write is confirmed + */ +#define PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x) (1 << 28) +#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) + /* 0 - discard + * 1 - send low 32bit data + * 2 - send 64bit data + * 3 - send 64bit GPU counter value + * 4 - send 64bit sys counter value + */ + +#define PACKET3_PREAMBLE_CNTL 0x4A +# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) +# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) +#define PACKET3_DMA_DATA 0x50 +/* 1. header + * 2. CONTROL + * 3. SRC_ADDR_LO or DATA [31:0] + * 4. SRC_ADDR_HI [31:0] + * 5. DST_ADDR_LO [31:0] + * 6. DST_ADDR_HI [7:0] + * 7. COMMAND [31:26] | BYTE_COUNT [25:0] + */ +/* CONTROL */ +# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SRC_TEMPORAL(x) ((x) << 13) + /* 0 - rt + * 1 - nt + * 2 - ht + * 3 - lu + */ +# define PACKET3_DMA_DATA_SRC_SCOPE(x) ((x) << 15) +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_DST_TEMPORAL(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +# define PACKET3_DMA_DATA_DST_SCOPE(x) ((x) << 27) +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +/* COMMAND */ +# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) +# define PACKET3_DMA_DATA_CMD_DIS_WC (1 << 30) +#define PACKET3_CONTEXT_REG_RMW 0x51 +#define PACKET3_ACQUIRE_MEM 0x58 +/* 1. HEADER + * 2. COHER_CNTL [30:0] + * 2.1 ENGINE_SEL [31:31] + * 2. COHER_SIZE [31:0] + * 3. COHER_SIZE_HI [7:0] + * 4. COHER_BASE_LO [31:0] + * 5. COHER_BASE_HI [23:0] + * 7. POLL_INTERVAL [15:0] + * 8. GCR_CNTL [18:0] + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) + /* + * 0:NOP + * 1:ALL + * 2:RANGE + * 3:FIRST_LAST + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) + /* + * 0:ALL + * 1:reserved + * 2:RANGE + * 3:FIRST_LAST + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(x) ((x) << 4) + /* + * 0:Device scope + * 1:System scope + * 2:Force INV/WB all + * 3:Reserved + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_WB(x) ((x) << 6) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) + /* + * 0:ALL + * 1:VOL + * 2:RANGE + * 3:FIRST_LAST + */ +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) +#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) + /* + * 0: PARALLEL + * 1: FORWARD + * 2: REVERSE + */ +#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) +#define PACKET3_GEN_PDEPTE 0x5B +#define PACKET3_PRIME_UTCL2 0x5D +#define PACKET3_LOAD_UCONFIG_REG 0x5E +#define PACKET3_LOAD_SH_REG 0x5F +#define PACKET3_LOAD_CONFIG_REG 0x60 +#define PACKET3_LOAD_CONTEXT_REG 0x61 +#define PACKET3_LOAD_COMPUTE_STATE 0x62 +#define PACKET3_LOAD_SH_REG_INDEX 0x63 +#define PACKET3_SET_CONFIG_REG 0x68 +#define PACKET3_SET_CONFIG_REG_START 0x00002000 +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 +#define PACKET3_SET_CONTEXT_REG 0x69 +#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 +#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 +#define PACKET3_SET_SH_REG 0x76 +#define PACKET3_SET_SH_REG_START 0x00002c00 +#define PACKET3_SET_SH_REG_END 0x00003000 +#define PACKET3_SET_SH_REG_OFFSET 0x77 +#define PACKET3_SET_QUEUE_REG 0x78 +#define PACKET3_SET_UCONFIG_REG 0x79 +#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 +#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 +#define PACKET3_SET_UCONFIG_REG_INDEX 0x7A +#define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C +#define PACKET3_DISPATCH_DRAW 0x8D +#define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 +#define PACKET3_WAIT_REG_MEM64 0x93 +#define PACKET3_HDP_FLUSH 0x95 +#define PACKET3_INVALIDATE_TLBS 0x98 +#define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) +#define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) +#define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) +#define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29) + +#define PACKET3_DMA_DATA_FILL_MULTI 0x9A +#define PACKET3_SET_SH_REG_INDEX 0x9B +#define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F +#define PACKET3_SET_RESOURCES 0xA0 +/* 1. header + * 2. CONTROL + * 3. QUEUE_MASK_LO [31:0] + * 4. QUEUE_MASK_HI [31:0] + * 5. GWS_MASK_LO [31:0] + * 6. GWS_MASK_HI [31:0] + * 7. OAC_MASK [15:0] + * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] + */ +# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) +# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) +# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) +#define PACKET3_MAP_QUEUES 0xA2 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. MQD_ADDR_LO [31:0] + * 5. MQD_ADDR_HI [31:0] + * 6. WPTR_ADDR_LO [31:0] + * 7. WPTR_ADDR_HI [31:0] + */ +/* CONTROL */ +# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) +# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) +# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) +# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) +# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) +# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) +# define PACKET3_MAP_QUEUES_QUEUE_GROUP(x) ((x) << 24) +# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) +# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) +/* CONTROL2 */ +# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) +#define PACKET3_UNMAP_QUEUES 0xA3 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. CONTROL3 + * 5. CONTROL4 + * 6. CONTROL5 + */ +/* CONTROL */ +# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) + /* 0 - PREEMPT_QUEUES + * 1 - RESET_QUEUES + * 2 - DISABLE_PROCESS_QUEUES + * 3 - PREEMPT_QUEUES_NO_UNMAP + */ +# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) +# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) +# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) +/* CONTROL2a */ +# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) +/* CONTROL2b */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) +/* CONTROL3a */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) +/* CONTROL3b */ +# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) +/* CONTROL4 */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) +/* CONTROL5 */ +# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) +#define PACKET3_QUERY_STATUS 0xA4 +/* 1. header + * 2. CONTROL + * 3. CONTROL2 + * 4. ADDR_LO [31:0] + * 5. ADDR_HI [31:0] + * 6. DATA_LO [31:0] + * 7. DATA_HI [31:0] + */ +/* CONTROL */ +# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) +# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) +# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) +/* CONTROL2a */ +# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) +/* CONTROL2b */ +# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) +# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 28) + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 80565392313f1..73223d97a87f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2010,7 +2010,7 @@ static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) r = amdgpu_ring_alloc(ring, 7 + 4); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); @@ -2031,7 +2031,7 @@ static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev) r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -3002,7 +3002,7 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev, u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) { - DRM_INFO("Not implemented\n"); + drm_info(adev_to_drm(adev), "Not implemented\n"); } static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { @@ -3555,7 +3555,7 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) memset(cu_info, 0, sizeof(*cu_info)); - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 2b7aba22ecc19..2b691452775bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2068,23 +2068,15 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask; - int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; + int usepfp; + struct amdgpu_device *adev = ring->adev; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; - break; - case 2: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; - break; - default: - return; - } - } else { - ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, &usepfp); amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ WAIT_REG_MEM_FUNCTION(3) | /* == */ @@ -2473,7 +2465,7 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev) r = amdgpu_ring_alloc(ring, gfx_v7_0_get_csb_size(adev) + 8); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -3245,7 +3237,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -3471,7 +3463,8 @@ static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) +static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid) { u32 data; @@ -4074,12 +4067,49 @@ static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev, cik_srbm_select(adev, me, pipe, q, vm); } +/** + * gfx_v7_0_get_hdp_flush_mask - get the reference and mask for HDP flush + * + * @ring: amdgpu_ring structure holding ring information + * @ref_and_mask: pointer to store the reference and mask + * @reg_mem_engine: pointer to store the register memory engine + * + * Calculates the reference and mask for HDP flush based on the ring type and me. + */ +static void gfx_v7_0_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine) +{ + if (!ring || !ref_and_mask || !reg_mem_engine) { + DRM_INFO("%s:invalid params\n", __func__); + return; + } + + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE || + ring->funcs->type == AMDGPU_RING_TYPE_KIQ) { + switch (ring->me) { + case 1: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; + break; + case 2: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; + break; + default: + return; + } + *reg_mem_engine = 0; + } else { + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + *reg_mem_engine = 1; + } +} + static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, .select_se_sh = &gfx_v7_0_select_se_sh, .read_wave_data = &gfx_v7_0_read_wave_data, .read_wave_sgprs = &gfx_v7_0_read_wave_sgprs, - .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q + .select_me_pipe_q = &gfx_v7_0_select_me_pipe_q, + .get_hdp_flush_mask = &gfx_v7_0_get_hdp_flush_mask, }; static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { @@ -5033,7 +5063,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) memset(cu_info, 0, sizeof(*cu_info)); - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 1c87375e1dd58..99c68d4db3777 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1048,7 +1048,7 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) if (adev->gfx.ce_feature_version >= 46 && adev->gfx.pfp_feature_version >= 46) { adev->virt.chained_ib_support = true; - DRM_INFO("Chained IB support enabled!\n"); + drm_info(adev_to_drm(adev), "Chained IB support enabled!\n"); } else adev->virt.chained_ib_support = false; @@ -1274,7 +1274,7 @@ static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) /* init spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); return 0; } @@ -1509,7 +1509,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) r = amdgpu_ib_get(adev, NULL, total_size, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%d).\n", r); return r; } @@ -1604,14 +1604,14 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) /* shedule the ib on the ring */ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); if (r) { - DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); + drm_err(adev_to_drm(adev), "ib submit failed (%d).\n", r); goto fail; } /* wait for the GPU to finish processing the IB */ r = dma_fence_wait(f, false); if (r) { - DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + drm_err(adev_to_drm(adev), "fence wait failed (%d).\n", r); goto fail; } @@ -1910,6 +1910,12 @@ static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, + VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR, &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); if (r) @@ -3820,7 +3826,7 @@ static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); mutex_unlock(&adev->grbm_idx_mutex); - DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", i, j); return; } @@ -4143,7 +4149,7 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -4854,6 +4860,7 @@ static int gfx_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* disable KCQ to avoid CPC touch memory not valid anymore */ gfx_v8_0_kcq_disable(adev); @@ -5211,15 +5218,142 @@ static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id start + SQIND_WAVE_SGPRS_OFFSET, size, dst); } +/** + * gfx_v8_0_get_hdp_flush_mask - get the reference and mask for HDP flush + * + * @ring: amdgpu_ring structure holding ring information + * @ref_and_mask: pointer to store the reference and mask + * @reg_mem_engine: pointer to store the register memory engine + * + * Calculates the reference and mask for HDP flush based on the ring type and me. + */ +static void gfx_v8_0_get_hdp_flush_mask(struct amdgpu_ring *ring, + uint32_t *ref_and_mask, uint32_t *reg_mem_engine) +{ + if (!ring || !ref_and_mask || !reg_mem_engine) { + DRM_INFO("%s:invalid params\n", __func__); + return; + } + + if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) || + (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) { + switch (ring->me) { + case 1: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; + break; + case 2: + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; + break; + default: + return; + } + *reg_mem_engine = 0; + } else { + *ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; + *reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ + } +} static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter, .select_se_sh = &gfx_v8_0_select_se_sh, .read_wave_data = &gfx_v8_0_read_wave_data, .read_wave_sgprs = &gfx_v8_0_read_wave_sgprs, - .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q + .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q, + .get_hdp_flush_mask = &gfx_v8_0_get_hdp_flush_mask, +}; + +static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, + bool wc, uint32_t reg, uint32_t val) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | + WRITE_DATA_DST_SEL(0) | + (wc ? WR_CONFIRM : 0)); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v8_0_spm_start(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmGRBM_GFX_INDEX, data); + + + data = RREG32(mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, STRM_PERFMON_STATE_START_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_INT_CNTL, 1); +} + +static void gfx_v8_0_spm_stop(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + PERFMON_STATE, CP_PERFMON_STATE_STOP_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); +} + +static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); +} + +static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_HI, upper_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_SIZE, size); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_SEGMENT_THRESHOLD, 0x1); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, 0); +} + +static const struct spm_funcs gfx_v8_0_spm_funcs = { + .start = &gfx_v8_0_spm_start, + .stop = &gfx_v8_0_spm_stop, + .set_rdptr = &gfx_v8_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v8_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, }; +static void gfx_v8_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v8_0_spm_funcs; +} + static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -5229,6 +5363,7 @@ static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); adev->gfx.funcs = &gfx_v8_0_gfx_funcs; + gfx_v8_0_set_spm_funcs(adev); gfx_v8_0_set_ring_funcs(adev); gfx_v8_0_set_irq_funcs(adev); gfx_v8_0_set_gds_init(adev); @@ -5269,6 +5404,10 @@ static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) return r; } + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + return 0; } @@ -5541,7 +5680,8 @@ static void gfx_v8_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id) } } -static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned vmid) +static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned vmid) { u32 data; @@ -5999,25 +6139,14 @@ static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask, reg_mem_engine; + struct amdgpu_device *adev = ring->adev; - if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) || - (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)) { - switch (ring->me) { - case 1: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; - break; - case 2: - ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; - reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ WAIT_REG_MEM_FUNCTION(3) | /* == */ @@ -6643,7 +6772,7 @@ static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data, switch (enc) { case 0: - DRM_INFO("SQ general purpose intr detected:" + drm_info(adev_to_drm(adev), "SQ general purpose intr detected:" "se_id %d, immed_overflow %d, host_reg_overflow %d," "host_cmd_overflow %d, cmd_timestamp %d," "reg_timestamp %d, thread_trace_buff_full %d," @@ -6685,7 +6814,7 @@ static void gfx_v8_0_parse_sq_irq(struct amdgpu_device *adev, unsigned ih_data, else sprintf(type, "EDC/ECC error"); - DRM_INFO( + drm_info(adev_to_drm(adev), "SQ %s detected: " "se_id %d, sh_id %d, cu_id %d, simd_id %d, wave_id %d, vm_id %d " "trap %s, sq_ed_info.source %s.\n", @@ -6760,6 +6889,31 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ } +static int gfx_v8_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v8_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); + return 0; +} /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f @@ -6817,7 +6971,6 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) gfx_v8_0_emit_wave_limit_cs(ring, i, enable); } - } static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { @@ -6985,11 +7138,19 @@ static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = { .process = gfx_v8_0_sq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v8_0_spm_irq_funcs = { + .set = gfx_v8_0_spm_set_interrupt_state, + .process = gfx_v8_0_spm_irq, +}; + static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v8_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; @@ -7058,7 +7219,7 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) else ao_cu_num = adev->gfx.config.max_cu_per_sh; - amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); + amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4, 2); mutex_lock(&adev->grbm_idx_mutex); for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 0148d7ff34d99..186bc33f5ffff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1301,7 +1301,8 @@ static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) (adev->gfx.mec_feature_version < 46) || (adev->gfx.pfp_fw_version < 0x000000b7) || (adev->gfx.pfp_feature_version < 46))) - DRM_WARN_ONCE("CP firmware version too old, please update!"); + drm_warn_once(adev_to_drm(adev), + "CP firmware version too old, please update!"); switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 0, 1): @@ -2004,6 +2005,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; const struct amdgpu_ras_block_hw_ops gfx_v9_0_ras_ops = { @@ -2039,7 +2041,7 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; - DRM_INFO("fix gfx.config for vega12\n"); + drm_info(adev_to_drm(adev), "fix gfx.config for vega12\n"); break; case IP_VERSION(9, 4, 0): adev->gfx.ras = &gfx_v9_0_ras; @@ -2273,6 +2275,13 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -2353,7 +2362,7 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) { ring = &adev->gfx.sw_gfx_ring[i]; ring->ring_obj = NULL; - sprintf(ring->name, amdgpu_sw_ring_name(i)); + strscpy(ring->name, amdgpu_sw_ring_name(i), sizeof(ring->name)); ring->use_doorbell = true; ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; ring->is_sw_ring = true; @@ -2409,8 +2418,10 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) amdgpu_get_soft_full_reset_mask(&adev->gfx.gfx_ring[0]); adev->gfx.compute_supported_reset = amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); - if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_gpu_ring_reset) + if (!amdgpu_sriov_vf(adev) && !adev->debug_disable_gpu_ring_reset) { adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + adev->gfx.gfx_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + } r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, 0); if (r) { @@ -2727,7 +2738,7 @@ static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); mutex_unlock(&adev->grbm_idx_mutex); - DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", i, j); return; } @@ -3150,7 +3161,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) /* RLC_GPM_GENERAL_6 : RLC Ucode version */ rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); if(rlc_ucode_ver == 0x108) { - DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", + drm_info(adev_to_drm(adev), "Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", rlc_ucode_ver, adev->gfx.rlc_fw_version); /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, * default is 0x9C4 to create a 100us interval */ @@ -3333,12 +3344,12 @@ static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) */ if (adev->flags & AMD_IS_APU && adev->in_s3 && !pm_resume_via_firmware()) { - DRM_INFO("Will skip the CSB packet resubmit\n"); + drm_info(adev_to_drm(adev), "Will skip the CSB packet resubmit\n"); return 0; } r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); if (r) { - DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); + drm_err(adev_to_drm(adev), "cp failed to lock ring (%d).\n", r); return r; } @@ -4052,6 +4063,7 @@ static int gfx_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -4581,7 +4593,7 @@ static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) r = amdgpu_ring_alloc(ring, 7); if (r) { - DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", + drm_err(adev_to_drm(adev), "GDS workarounds failed to lock ring %s (%d).\n", ring->name, r); return r; } @@ -4670,7 +4682,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) r = amdgpu_ib_get(adev, NULL, total_size, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%d).\n", r); return r; } @@ -4771,14 +4783,14 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) /* shedule the ib on the ring */ r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); if (r) { - DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); + drm_err(adev_to_drm(adev), "ib schedule failed (%d).\n", r); goto fail; } /* wait for the GPU to finish processing the IB */ r = dma_fence_wait(f, false); if (r) { - DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); + drm_err(adev_to_drm(adev), "fence wait failed (%d).\n", r); goto fail; } @@ -4789,6 +4801,95 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) return r; } +static void gfx_v9_0_spm_start(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v9_0_spm_stop(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); +} + +static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0x1); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_0_spm_funcs = { + .start = &gfx_v9_0_spm_start, + .stop = &gfx_v9_0_spm_stop, + .set_rdptr = &gfx_v9_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_0_spm_funcs; +} + static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -4803,6 +4904,7 @@ static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) adev->gfx.xcc_mask = 1; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_0_set_spm_funcs(adev); gfx_v9_0_set_kiq_pm4_funcs(adev); gfx_v9_0_set_ring_funcs(adev); gfx_v9_0_set_irq_funcs(adev); @@ -4858,6 +4960,10 @@ static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -5171,7 +5277,8 @@ static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); } -static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned int vmid) +static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) { amdgpu_gfx_off_ctrl(adev, false); @@ -5379,25 +5486,13 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), @@ -5581,15 +5676,42 @@ static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, 0); } -static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +static void gfx_v9_0_ring_emit_event_write(struct amdgpu_ring *ring, + uint32_t event_type, + uint32_t event_index) { - int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); - uint32_t seq = ring->fence_drv.sync_seq; - uint64_t addr = ring->fence_drv.gpu_addr; + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); + amdgpu_ring_write(ring, EVENT_TYPE(event_type) | + EVENT_INDEX(event_index)); +} + +static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) +{ + const unsigned int cp_coher_cntl = + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | + PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); + + /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ + amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); + amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ + amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ + amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ + amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ + amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ +} - gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, - lower_32_bits(addr), upper_32_bits(addr), - seq, 0xffffffff, 4); +static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +{ + if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { + gfx_v9_0_ring_emit_event_write(ring, VS_PARTIAL_FLUSH, 4); + gfx_v9_0_ring_emit_event_write(ring, PS_PARTIAL_FLUSH, 4); + } + gfx_v9_0_ring_emit_event_write(ring, CS_PARTIAL_FLUSH, 4); + gfx_v9_0_emit_mem_sync(ring); } static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, @@ -5744,7 +5866,7 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring) if (i >= adev->usec_timeout) { r = -EINVAL; - DRM_WARN("ring %d timeout to preempt ib\n", ring->idx); + drm_warn(adev_to_drm(adev), "ring %d timeout to preempt ib\n", ring->idx); } /*reset the CP_VMID_PREEMPT after trailing fence*/ @@ -7080,23 +7202,30 @@ static void gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, gfx_v9_0_query_utc_edc_status(adev, err_data); } -static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) +static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) { - const unsigned int cp_coher_cntl = - PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | - PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | - PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | - PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | - PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} - /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ - amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); - amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ - amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ - amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ - amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ - amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ - amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ +static int gfx_v9_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev, 0); + return 0; } static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, @@ -7173,6 +7302,91 @@ static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) amdgpu_ring_insert_nop(ring, num_nop - 1); } +static void gfx_v9_0_ring_emit_wreg_me(struct amdgpu_ring *ring, + uint32_t reg, + uint32_t val) +{ + uint32_t cmd = 0; + + switch (ring->funcs->type) { + case AMDGPU_RING_TYPE_KIQ: + cmd = (1 << 16); /* no inc addr */ + break; + default: + cmd = WR_CONFIRM; + break; + } + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, cmd); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static int gfx_v9_0_reset_kgq(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + u32 tmp; + int r; + + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, 5)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + /* send the reset - 5 */ + tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); + gfx_v9_0_ring_emit_wreg(kiq_ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); + amdgpu_ring_commit(kiq_ring); + r = amdgpu_ring_test_ring(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); + if (r) + return r; + + if (amdgpu_ring_alloc(ring, 8 + 7 + 5 + 2 + 8 + 7)) + return -ENOMEM; + /* emit the fence to finish the reset - 8 */ + ring->trail_seq++; + gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, + ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC); + /* wait for the fence - 7 */ + gfx_v9_0_wait_reg_mem(ring, 0, 1, 0, + lower_32_bits(ring->trail_fence_gpu_addr), + upper_32_bits(ring->trail_fence_gpu_addr), + ring->trail_seq, 0xffffffff, 4); + /* clear mmCP_VMID_RESET - 5 */ + gfx_v9_0_ring_emit_wreg_me(ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0); + /* event write ENABLE_LEGACY_PIPELINE - 2 */ + gfx_v9_0_ring_emit_event_write(ring, ENABLE_LEGACY_PIPELINE, 0); + /* emit a regular fence - 8 */ + ring->trail_seq++; + gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, + ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC); + /* wait for the fence - 7 */ + gfx_v9_0_wait_reg_mem(ring, 1, 1, 0, + lower_32_bits(ring->trail_fence_gpu_addr), + upper_32_bits(ring->trail_fence_gpu_addr), + ring->trail_seq, 0xffffffff, 4); + amdgpu_ring_commit(ring); + /* wait for the commands to complete */ + r = amdgpu_ring_test_ring(ring); + if (r) + return r; + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) @@ -7413,7 +7627,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .set_wptr = gfx_v9_0_ring_set_wptr_gfx, .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5 + /* COND_EXEC */ - 7 + /* PIPELINE_SYNC */ + 13 + /* PIPELINE_SYNC */ SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* VM_FLUSH */ @@ -7451,9 +7665,9 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .emit_wreg = gfx_v9_0_ring_emit_wreg, .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v9_0_ring_soft_recovery, .emit_mem_sync = gfx_v9_0_emit_mem_sync, .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, + .reset = gfx_v9_0_reset_kgq, .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, }; @@ -7469,7 +7683,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { .set_wptr = amdgpu_sw_ring_set_wptr_gfx, .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5 + /* COND_EXEC */ - 7 + /* PIPELINE_SYNC */ + 13 + /* PIPELINE_SYNC */ SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 2 + /* VM_FLUSH */ @@ -7530,7 +7744,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 20 + /* gfx_v9_0_ring_emit_gds_switch */ 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 5 + /* hdp invalidate */ - 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + 9 + /* gfx_v9_0_ring_emit_pipeline_sync */ SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ @@ -7552,7 +7766,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { .emit_wreg = gfx_v9_0_ring_emit_wreg, .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, - .soft_recovery = gfx_v9_0_ring_soft_recovery, .emit_mem_sync = gfx_v9_0_emit_mem_sync, .emit_wave_limit = gfx_v9_0_emit_wave_limit, .reset = gfx_v9_0_reset_kcq, @@ -7573,7 +7786,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 20 + /* gfx_v9_0_ring_emit_gds_switch */ 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 5 + /* hdp invalidate */ - 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ @@ -7632,12 +7844,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { .process = amdgpu_gfx_cp_ecc_error_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_0_spm_irq_funcs = { + .set = gfx_v9_0_spm_set_interrupt_state, + .process = gfx_v9_0_spm_irq, +}; static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; @@ -7772,7 +7991,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, adev->gfx.config.max_sh_per_se > 16) return -EINVAL; - amdgpu_gfx_parse_disable_cu(disable_masks, + amdgpu_gfx_parse_disable_cu(adev, disable_masks, adev->gfx.config.max_shader_engines, adev->gfx.config.max_sh_per_se); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index 8058ea91ecafd..fdaa7e72a62cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -772,7 +772,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, for (i = first_vmid; i < last_vmid; i++) { data = 0; soc15_grbm_select(adev, 0, 0, 0, i, 0); - data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index cbb74ffc47925..7e6a01f457d75 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -169,6 +169,8 @@ static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); +static void gfx_v9_4_3_update_spm_vmid_internal(struct amdgpu_device *adev, + int xcc_id, unsigned int vmid); static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); @@ -848,6 +850,7 @@ static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, + .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, }; static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, @@ -1065,6 +1068,13 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) num_xcc = NUM_XCC(adev->gfx.xcc_mask); + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -1453,10 +1463,14 @@ static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) { - /* init spm vmid with 0xf */ - if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); + int i, num_xcc; + if (amdgpu_sriov_vf(adev)) + return 0; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) + adev->gfx.rlc.funcs->update_spm_vmid(adev, i, NULL, 0xf); return 0; } @@ -1481,7 +1495,7 @@ static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 0xffffffff, 0xffffffff, xcc_id); mutex_unlock(&adev->grbm_idx_mutex); - DRM_INFO("Timeout wait for RLC serdes %u,%u\n", + drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", i, j); return; } @@ -1582,7 +1596,7 @@ static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); if (rlc_ucode_ver == 0x108) { dev_info(adev->dev, - "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", + "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", rlc_ucode_ver, adev->gfx.rlc_fw_version); /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, * default is 0x9C4 to create a 100us interval */ @@ -1631,14 +1645,15 @@ static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) { int r; + gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { - gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); /* legacy rlc firmware loading */ r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); if (r) return r; - gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); } + gfx_v9_4_3_update_spm_vmid_internal(adev, xcc_id, 0xf); + gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); /* disable CG */ @@ -1666,28 +1681,38 @@ static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned vmid) +static void gfx_v9_4_3_update_spm_vmid_internal(struct amdgpu_device *adev, + int xcc_id, unsigned int vmid) { u32 reg, pre_data, data; - reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); + reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) pre_data = RREG32_NO_KIQ(reg); else - pre_data = RREG32(reg); + pre_data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; if (pre_data != data) { if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { - WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); } else - WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); } } +static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, + struct amdgpu_ring *ring, unsigned int vmid) +{ + amdgpu_gfx_off_ctrl(adev, false); + + gfx_v9_4_3_update_spm_vmid_internal(adev, xcc_id, vmid); + + amdgpu_gfx_off_ctrl(adev, true); +} + static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, @@ -2375,6 +2400,7 @@ static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) int i, num_xcc; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -2509,12 +2535,112 @@ static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v9_4_3_spm_start(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), 0); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_INT_CNTL), 1); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); + data |= RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); +} + +static void gfx_v9_4_3_spm_stop(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); + data &= (~RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), 0); +} + +static void gfx_v9_4_3_spm_set_rdptr(struct amdgpu_device *adev, int xcc_id, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_4_3_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + int xcc_id, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + regRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + regRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), + regRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), + regRLC_SPM_SEGMENT_THRESHOLD), 0x1); + + gfx_v9_4_3_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_4_3_spm_funcs = { + .start = &gfx_v9_4_3_spm_start, + .stop = &gfx_v9_4_3_spm_stop, + .set_rdptr = &gfx_v9_4_3_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_4_3_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_4_3_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_4_3_spm_funcs; +} + static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_4_3_set_spm_funcs(adev); gfx_v9_4_3_set_kiq_pm4_funcs(adev); gfx_v9_4_3_set_ring_funcs(adev); gfx_v9_4_3_set_irq_funcs(adev); @@ -2536,6 +2662,10 @@ static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -2818,25 +2948,13 @@ static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; u32 ref_and_mask, reg_mem_engine; - const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; - if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { - switch (ring->me) { - case 1: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; - break; - case 2: - ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; - break; - default: - return; - } - reg_mem_engine = 0; - } else { - ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; - reg_mem_engine = 1; /* pfp */ + if (!adev->gfx.funcs->get_hdp_flush_mask) { + dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); + return; } + adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, adev->nbio.funcs->get_hdp_flush_req_offset(adev), adev->nbio.funcs->get_hdp_flush_done_offset(adev), @@ -3406,6 +3524,41 @@ static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } +static int gfx_v9_4_3_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + int i, num_xcc; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, GET_INST(GC, i), regRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + } + return 0; +} + +static int gfx_v9_4_3_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int xcc_id; + + xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); + + amdgpu_amdkfd_rlc_spm_interrupt(adev, xcc_id); + return 0; +} + static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { @@ -4833,11 +4986,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { .process = gfx_v9_4_3_priv_inst_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_4_3_spm_irq_funcs = { + .set = gfx_v9_4_3_spm_set_interrupt_state, + .process = gfx_v9_4_3_spm_irq, +}; + static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_4_3_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; @@ -4914,7 +5075,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, adev->gfx.config.max_sh_per_se > 16) return -EINVAL; - amdgpu_gfx_parse_disable_cu(disable_masks, + amdgpu_gfx_parse_disable_cu(adev, disable_masks, adev->gfx.config.max_shader_engines, adev->gfx.config.max_sh_per_se); diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c new file mode 100644 index 0000000000000..3544eb42dca60 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c @@ -0,0 +1,866 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "amdgpu_xcp.h" +#include "gfxhub_v12_1.h" + +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "soc_v1_0_enum.h" + +#include "soc15_common.h" + +#define regGCVM_L2_CNTL3_DEFAULT 0x80120007 +#define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 +#define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 +#define regGRBM_GFX_INDEX_DEFAULT 0xe0000000 + + +static u64 gfxhub_v12_1_get_fb_location(struct amdgpu_device *adev) +{ + u64 base; + + base = RREG32_SOC15(GC, GET_INST(GC, 0), + regGCMC_VM_FB_LOCATION_BASE_LO32); + base &= GCMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK; + base <<= 24; + + base |= ((u64)(GCMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK & + RREG32_SOC15(GC, GET_INST(GC, 0), + regGCMC_VM_FB_LOCATION_BASE_HI32)) << 56); + return base; +} + +static u64 gfxhub_v12_1_get_mc_fb_offset(struct amdgpu_device *adev) +{ + return (u64)(RREG32_SOC15(GC, GET_INST(GC, 0), + regGCMC_VM_FB_OFFSET) << 24); +} + +static void gfxhub_v12_1_xcc_setup_vm_pt_regs(struct amdgpu_device *adev, + uint32_t vmid, + uint64_t page_table_base, + uint32_t xcc_mask) +{ + struct amdgpu_vmhub *hub; + int i; + + for_each_inst(i, xcc_mask) { + hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; + WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + hub->ctx_addr_distance * vmid, + lower_32_bits(page_table_base)); + + WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + hub->ctx_addr_distance * vmid, + upper_32_bits(page_table_base)); + } +} + +static void gfxhub_v12_1_setup_vm_pt_regs(struct amdgpu_device *adev, + uint32_t vmid, + uint64_t page_table_base) +{ + uint32_t xcc_mask; + + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); + gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, + xcc_mask); +} + +static void gfxhub_v12_1_xcc_init_gart_aperture_regs(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + uint64_t pt_base; + int i; + + if (adev->gmc.pdb0_bo) + pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); + else + pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + + gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); + + /* If use GART for FB translation, vmid0 page table covers both + * vram and system memory (gart) + */ + for_each_inst(i, xcc_mask) { + if (adev->gmc.pdb0_bo) { + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.fb_start >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.fb_start >> 44)); + + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } else { + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } + } +} + +static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + uint64_t value; + uint32_t tmp; + int i; + + /*TODO: revisit whether the SRIOV guest access to theseregisters + * is blocked by security policy or not */ + if (amdgpu_sriov_vf(adev)) + return; + + for_each_inst(i, xcc_mask) { + if (adev->gmc.pdb0_bo) { + /* Disable agp and system aperture + * when vmid0 page table is enabled */ + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_TOP_LO32, 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_TOP_HI32, 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_BASE_LO32, + 0xFFFFFFFF); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_BASE_HI32, 1); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_AGP_TOP_LO32, 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_AGP_TOP_HI32, 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BOT_LO32, + 0xFFFFFFFF); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BOT_HI32, 1); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + 0xFFFFFFFF); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + 0x7F); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); + } else { + /* Program the AGP BAR */ + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BASE_LO32, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BASE_HI32, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BOT_LO32, + lower_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_BOT_HI32, + upper_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_TOP_LO32, + lower_32_bits(adev->gmc.agp_end >> 24)); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_AGP_TOP_HI32, + upper_32_bits(adev->gmc.agp_end >> 24)); + + /* Program the system aperture low logical page number. */ + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + lower_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + upper_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, + lower_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, + upper_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + } + + /* Set default page address. */ + value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page_addr >> 12)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page_addr >> 44)); + + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL2); + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, + ENABLE_RETRY_FAULT_INTERRUPT, 0x1); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); + } +} + +static void gfxhub_v12_1_xcc_init_tlb_regs(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + uint32_t tmp; + int i; + + for_each_inst(i, xcc_mask) { + /* Setup TLB control */ + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_MX_L1_TLB_CNTL); + + tmp = REG_SET_FIELD(tmp, + GCMC_VM_MX_L1_TLB_CNTL, + ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, + GCMC_VM_MX_L1_TLB_CNTL, + SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, + GCMC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, + GCMC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + tmp = REG_SET_FIELD(tmp, + GCMC_VM_MX_L1_TLB_CNTL, + ECO_BITS, 0); + tmp = REG_SET_FIELD(tmp, + GCMC_VM_MX_L1_TLB_CNTL, + MTYPE, MTYPE_UC); + + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCMC_VM_MX_L1_TLB_CNTL, tmp); + } +} + +static void gfxhub_v12_1_xcc_init_cache_regs(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + uint32_t tmp; + int i; + + for_each_inst(i, xcc_mask) { + /* Setup L2 cache */ + tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + ENABLE_L2_CACHE, 1); + /*TODO: set ENABLE_L2_FRAGMENT_PROCESSING to 1? */ + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + ENABLE_L2_FRAGMENT_PROCESSING, 0); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + PDE_FAULT_CLASSIFICATION, 0); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + CONTEXT1_IDENTITY_ACCESS_MODE, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, + IDENTITY_MODE_FRAGMENT_SIZE, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCVM_L2_CNTL, tmp); + + tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL2); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, + INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, + INVALIDATE_L2_CACHE, 1); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), + regGCVM_L2_CNTL2, tmp); + + tmp = regGCVM_L2_CNTL3_DEFAULT; + if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + } else { + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + } + WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL3, tmp); + + tmp = regGCVM_L2_CNTL4_DEFAULT; + if (adev->gmc.xgmi.connected_to_cpu) { + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } + + WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL4, tmp); + + tmp = regGCVM_L2_CNTL5_DEFAULT; + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, + L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL5, tmp); + } +} + +static void gfxhub_v12_1_xcc_enable_system_domain(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + uint32_t tmp; + int i; + + for_each_inst(i, xcc_mask) { + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, + ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, + PAGE_TABLE_DEPTH, + adev->gmc.vmid0_page_table_depth); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, + PAGE_TABLE_BLOCK_SIZE, + adev->gmc.vmid0_page_table_block_size); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_CNTL, tmp); + } +} + +static void gfxhub_v12_1_xcc_disable_identity_aperture(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + int i; + + for_each_inst(i, xcc_mask) { + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0XFFFFFFFF); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, + 0x00001FFF); + + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, + 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, + 0); + + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, + 0); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, + 0); + } +} + +static void gfxhub_v12_1_xcc_setup_vmid_config(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + struct amdgpu_vmhub *hub; + unsigned int num_level, block_size; + uint32_t tmp; + int i, j; + + num_level = adev->vm_manager.num_level; + block_size = adev->vm_manager.block_size; + block_size -= 9; + + for_each_inst(j, xcc_mask) { + hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; + for (i = 0; i <= 14; i++) { + tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_CONTEXT1_CNTL, + i * hub->ctx_distance); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + PAGE_TABLE_DEPTH, num_level); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + PAGE_TABLE_BLOCK_SIZE, block_size); + /* Send no-retry XNACK on fault to suppress VM fault storm */ + tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + 1); + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regGCVM_CONTEXT1_CNTL, + i * hub->ctx_distance, tmp); + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, + i * hub->ctx_addr_distance, + lower_32_bits(adev->vm_manager.max_pfn - 1)); + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, + i * hub->ctx_addr_distance, + upper_32_bits(adev->vm_manager.max_pfn - 1)); + } + + hub->vm_cntx_cntl = tmp; + } +} + +static void gfxhub_v12_1_xcc_program_invalidation(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + struct amdgpu_vmhub *hub; + unsigned int i, j; + + for_each_inst(j, xcc_mask) { + hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; + + for (i = 0 ; i < 18; ++i) { + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + i * hub->eng_addr_distance, 0xFFFFFFFF); + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + i * hub->eng_addr_distance, 0x3FFF); + } + } +} + +static int gfxhub_v12_1_xcc_gart_enable(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + uint32_t i; + + if (amdgpu_sriov_vf(adev)) { + /* GCMC_VM_FB_LOCATION_BASE/TOP are VF copy registers + * VBIO post does not program them at boot up phase + * Need driver to program them from guest side */ + for_each_inst(i, xcc_mask) { + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_BASE_LO32, + lower_32_bits(adev->gmc.vram_start >> 24)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_BASE_HI32, + upper_32_bits(adev->gmc.vram_start >> 24)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_TOP_LO32, + lower_32_bits(adev->gmc.vram_end >> 24)); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCMC_VM_FB_LOCATION_TOP_HI32, + upper_32_bits(adev->gmc.vram_end >> 24)); + } + } + /* GART Enable. */ + gfxhub_v12_1_xcc_init_gart_aperture_regs(adev, xcc_mask); + gfxhub_v12_1_xcc_init_system_aperture_regs(adev, xcc_mask); + gfxhub_v12_1_xcc_init_tlb_regs(adev, xcc_mask); + if (!amdgpu_sriov_vf(adev)) + gfxhub_v12_1_xcc_init_cache_regs(adev, xcc_mask); + + gfxhub_v12_1_xcc_enable_system_domain(adev, xcc_mask); + if (!amdgpu_sriov_vf(adev)) + gfxhub_v12_1_xcc_disable_identity_aperture(adev, xcc_mask); + gfxhub_v12_1_xcc_setup_vmid_config(adev, xcc_mask); + gfxhub_v12_1_xcc_program_invalidation(adev, xcc_mask); + + return 0; +} + +static int gfxhub_v12_1_gart_enable(struct amdgpu_device *adev) +{ + uint32_t xcc_mask; + + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); + return gfxhub_v12_1_xcc_gart_enable(adev, xcc_mask); +} + +static void gfxhub_v12_1_xcc_gart_disable(struct amdgpu_device *adev, + uint32_t xcc_mask) +{ + struct amdgpu_vmhub *hub; + u32 tmp; + u32 i, j; + + for_each_inst(j, xcc_mask) { + hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; + /* Disable all tables */ + for (i = 0; i < 16; i++) + WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), + regGCVM_CONTEXT0_CNTL, + i * hub->ctx_distance, 0); + + /* Setup TLB control */ + tmp = RREG32_SOC15(GC, GET_INST(GC, j), + regGCMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, + ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 0); + WREG32_SOC15_RLC(GC, GET_INST(GC, j), + regGCMC_VM_MX_L1_TLB_CNTL, tmp); + + /* Setup L2 cache */ + if (!amdgpu_sriov_vf(adev)) { + tmp = RREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL, tmp); + WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL3, 0); + } + } +} + +static void gfxhub_v12_1_gart_disable(struct amdgpu_device *adev) +{ + uint32_t xcc_mask; + + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); + gfxhub_v12_1_xcc_gart_disable(adev, xcc_mask); +} + +static void gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev, + bool value, uint32_t xcc_mask) +{ + u32 tmp; + int i; + + for_each_inst(i, xcc_mask) { + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL_LO32); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE3_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, + value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + CLIENT_ID_NO_RETRY_FAULT_INTERRUPT, value ? 0xFFFF:0); + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT, value); + if (!value) + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_LO32, + CRASH_ON_NO_RETRY_FAULT, 1); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL_LO32, tmp); + + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL_HI32); + if (!value) + tmp = REG_SET_FIELD(tmp, + GCVM_L2_PROTECTION_FAULT_CNTL_HI32, + CRASH_ON_RETRY_FAULT, 1); + WREG32_SOC15(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL_HI32, tmp); + } +} + +/** + * gfxhub_v12_1_set_fault_enable_default - update GART/VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +static void gfxhub_v12_1_set_fault_enable_default(struct amdgpu_device *adev, + bool value) +{ + uint32_t xcc_mask; + + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); + gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, xcc_mask); +} + +static uint32_t gfxhub_v12_1_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + /* invalidate using legacy mode on vmid*/ + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + FLUSH_TYPE, flush_type); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + INVALIDATE_L2_PDE3, 1); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +static const char *gfxhub_v12_1_client_ids[] = { + "CB", + "DB", + "GE1", + "GE2", + "CPF", + "CPC", + "CPG", + "RLC", + "TCP", + "SQC (inst)", + "SQC (data)", + "SQG/PC/SC", + "Reserved", + "SDMA0", + "SDMA1", + "GCR", + "Reserved", + "Reserved", + "WGS", + "DSM", + "PA" +}; + +/*TODO: l2 protection fault status is increased to 64bits. + * some critical fields like FED are moved to STATUS_HI32 */ +static void gfxhub_v12_1_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + u32 cid = REG_GET_FIELD(status, + GCVM_L2_PROTECTION_FAULT_STATUS_LO32, + CID); + + dev_err(adev->dev, + "GCVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", + status); + dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", + cid >= ARRAY_SIZE(gfxhub_v12_1_client_ids) ? + "unknown" : gfxhub_v12_1_client_ids[cid], cid); + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", + REG_GET_FIELD(status, + GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", + REG_GET_FIELD(status, + GCVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", + REG_GET_FIELD(status, + GCVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", + REG_GET_FIELD(status, + GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); + dev_err(adev->dev, "\t RW: 0x%lx\n", + REG_GET_FIELD(status, + GCVM_L2_PROTECTION_FAULT_STATUS_LO32, RW)); +} + +static const struct amdgpu_vmhub_funcs gfxhub_v12_1_vmhub_funcs = { + .print_l2_protection_fault_status = gfxhub_v12_1_print_l2_protection_fault_status, + .get_invalidate_req = gfxhub_v12_1_get_invalidate_req, +}; + +static void gfxhub_v12_1_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) +{ + struct amdgpu_vmhub *hub; + int i; + + for_each_inst(i, xcc_mask) { + hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); + hub->ctx0_ptb_addr_hi32 = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); + hub->vm_inv_eng0_sem = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_INVALIDATE_ENG0_SEM); + hub->vm_inv_eng0_req = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_INVALIDATE_ENG0_REQ); + hub->vm_inv_eng0_ack = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_INVALIDATE_ENG0_ACK); + hub->vm_context0_cntl = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_CONTEXT0_CNTL); + /* TODO: add a new member to accomandate additional fault status/cntl reg */ + hub->vm_l2_pro_fault_status = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_STATUS_LO32); + hub->vm_l2_pro_fault_cntl = + SOC15_REG_OFFSET(GC, GET_INST(GC, i), + regGCVM_L2_PROTECTION_FAULT_CNTL_LO32); + hub->ctx_distance = + regGCVM_CONTEXT1_CNTL - + regGCVM_CONTEXT0_CNTL; + hub->ctx_addr_distance = + regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - + regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; + hub->eng_distance = + regGCVM_INVALIDATE_ENG1_REQ - + regGCVM_INVALIDATE_ENG0_REQ; + hub->eng_addr_distance = + regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - + regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + + hub->vm_cntx_cntl_vm_fault = + GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; + + hub->vmhub_funcs = &gfxhub_v12_1_vmhub_funcs; + } +} + +static void gfxhub_v12_1_init(struct amdgpu_device *adev) +{ + uint32_t xcc_mask; + + xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); + gfxhub_v12_1_xcc_init(adev, xcc_mask); +} + +const struct amdgpu_gfxhub_funcs gfxhub_v12_1_funcs = { + .get_fb_location = gfxhub_v12_1_get_fb_location, + .get_mc_fb_offset = gfxhub_v12_1_get_mc_fb_offset, + .setup_vm_pt_regs = gfxhub_v12_1_setup_vm_pt_regs, + .gart_enable = gfxhub_v12_1_gart_enable, + .gart_disable = gfxhub_v12_1_gart_disable, + .set_fault_enable_default = gfxhub_v12_1_set_fault_enable_default, + .init = gfxhub_v12_1_init, +}; + +static int gfxhub_v12_1_xcp_resume(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool value; + + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) + value = false; + else + value = true; + + gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, inst_mask); + + if (!amdgpu_sriov_vf(adev)) + return gfxhub_v12_1_xcc_gart_enable(adev, inst_mask); + + return 0; +} + +static int gfxhub_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!amdgpu_sriov_vf(adev)) + gfxhub_v12_1_xcc_gart_disable(adev, inst_mask); + + return 0; +} + +struct amdgpu_xcp_ip_funcs gfxhub_v12_1_xcp_funcs = { + .suspend = &gfxhub_v12_1_xcp_suspend, + .resume = &gfxhub_v12_1_xcp_resume +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.h b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.h new file mode 100644 index 0000000000000..b3f8f0aa00243 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.h @@ -0,0 +1,31 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GFXHUB_V12_1_H__ +#define __GFXHUB_V12_1_H__ + +extern const struct amdgpu_gfxhub_funcs gfxhub_v12_1_funcs; + +extern struct amdgpu_xcp_ip_funcs gfxhub_v12_1_xcp_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c index deb95fab02dfe..aceb8447feacc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c @@ -649,7 +649,7 @@ static void gfxhub_v2_1_halt(struct amdgpu_device *adev) } if (!time) - DRM_WARN("failed to wait for GRBM(EA) idle\n"); + drm_warn(adev_to_drm(adev), "failed to wait for GRBM(EA) idle\n"); } const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index ce6e04242c522..feda8209f1fc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -115,27 +115,10 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, addr |= ((u64)entry->src_data[1] & 0xf) << 44; if (retry_fault) { + int ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, 0, 0, + write_fault); /* Returning 1 here also prevents sending the IV to the KFD */ - - /* Process it onyl if it's the first fault for this address */ - if (entry->ih != &adev->irq.ih_soft && - amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, - entry->timestamp)) - return 1; - - /* Delegate it to a different ring if the hardware hasn't - * already done it. - */ - if (entry->ih == &adev->irq.ih) { - amdgpu_irq_delegate(adev, entry, 8); - return 1; - } - - /* Try to handle the recoverable page faults by filling page - * tables - */ - if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, - entry->timestamp, write_fault)) + if (ret == 1) return 1; } @@ -152,7 +135,6 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); } @@ -674,7 +656,6 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) @@ -784,7 +765,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ } else { - r = amdgpu_atomfirmware_get_vram_info(adev, + r = amdgpu_gmc_get_vram_info(adev, &vram_width, &vram_type, &vram_vendor); adev->gmc.vram_width = vram_width; @@ -867,7 +848,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); if (r) { - dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); + drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); return r; } @@ -974,7 +955,7 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) if (!adev->in_s0ix) gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); - DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index ba59ee8e398a8..0f6e2b00c5735 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -114,27 +114,10 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, addr |= ((u64)entry->src_data[1] & 0xf) << 44; if (retry_fault) { + int ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, 0, 0, + write_fault); /* Returning 1 here also prevents sending the IV to the KFD */ - - /* Process it only if it's the first fault for this address */ - if (entry->ih != &adev->irq.ih_soft && - amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, - entry->timestamp)) - return 1; - - /* Delegate it to a different ring if the hardware hasn't - * already done it. - */ - if (entry->ih == &adev->irq.ih) { - amdgpu_irq_delegate(adev, entry, 8); - return 1; - } - - /* Try to handle the recoverable page faults by filling page - * tables - */ - if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, - entry->timestamp, write_fault)) + if (ret == 1) return 1; } @@ -149,7 +132,6 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); } @@ -601,6 +583,7 @@ static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) case IP_VERSION(3, 3, 0): case IP_VERSION(3, 3, 1): case IP_VERSION(3, 3, 2): + case IP_VERSION(3, 4, 0): adev->mmhub.funcs = &mmhub_v3_3_funcs; break; default: @@ -619,6 +602,7 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs; break; default: @@ -671,7 +655,6 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); if (!amdgpu_sriov_vf(adev) && @@ -766,7 +749,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) spin_lock_init(&adev->gmc.invalidate_lock); - r = amdgpu_atomfirmware_get_vram_info(adev, + r = amdgpu_gmc_get_vram_info(adev, &vram_width, &vram_type, &vram_vendor); adev->gmc.vram_width = vram_width; @@ -795,6 +778,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); /* @@ -838,7 +822,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); if (r) { - dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); + drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); return r; } @@ -939,7 +923,7 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) adev->mmhub.funcs->set_fault_enable_default(adev, value); gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); - DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 7a9d6894e3216..6e184ea069ef2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -28,6 +28,7 @@ #include "amdgpu.h" #include "amdgpu_atomfirmware.h" #include "gmc_v12_0.h" +#include "gmc_v12_1.h" #include "athub/athub_4_1_0_sh_mask.h" #include "athub/athub_4_1_0_offset.h" #include "oss/osssys_7_0_0_offset.h" @@ -38,7 +39,9 @@ #include "soc15_common.h" #include "nbif_v6_3_1.h" #include "gfxhub_v12_0.h" +#include "gfxhub_v12_1.h" #include "mmhub_v4_1_0.h" +#include "mmhub_v4_2_0.h" #include "athub_v4_1_0.h" #include "umc_v8_14.h" @@ -107,27 +110,10 @@ static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; if (retry_fault) { + int ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, 0, 0, + write_fault); /* Returning 1 here also prevents sending the IV to the KFD */ - - /* Process it only if it's the first fault for this address */ - if (entry->ih != &adev->irq.ih_soft && - amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, - entry->timestamp)) - return 1; - - /* Delegate it to a different ring if the hardware hasn't - * already done it. - */ - if (entry->ih == &adev->irq.ih) { - amdgpu_irq_delegate(adev, entry, 8); - return 1; - } - - /* Try to handle the recoverable page faults by filling page - * tables - */ - if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, - entry->timestamp, write_fault)) + if (ret == 1) return 1; } @@ -623,6 +609,9 @@ static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) case IP_VERSION(4, 1, 0): adev->mmhub.funcs = &mmhub_v4_1_0_funcs; break; + case IP_VERSION(4, 2, 0): + adev->mmhub.funcs = &mmhub_v4_2_0_funcs; + break; default: break; } @@ -635,6 +624,9 @@ static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) case IP_VERSION(12, 0, 1): adev->gfxhub.funcs = &gfxhub_v12_0_funcs; break; + case IP_VERSION(12, 1, 0): + adev->gfxhub.funcs = &gfxhub_v12_1_funcs; + break; default: break; } @@ -644,18 +636,39 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; + if (adev->smuio.funcs && + adev->smuio.funcs->is_host_gpu_xgmi_supported) + adev->gmc.xgmi.connected_to_cpu = + adev->smuio.funcs->is_host_gpu_xgmi_supported(adev); + + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 1, 0): + gmc_v12_1_set_gmc_funcs(adev); + gmc_v12_1_set_irq_funcs(adev); + adev->gmc.init_pte_flags = AMDGPU_PTE_IS_PTE; + break; + default: + gmc_v12_0_set_gmc_funcs(adev); + gmc_v12_0_set_irq_funcs(adev); + break; + } gmc_v12_0_set_gfxhub_funcs(adev); gmc_v12_0_set_mmhub_funcs(adev); - gmc_v12_0_set_gmc_funcs(adev); - gmc_v12_0_set_irq_funcs(adev); gmc_v12_0_set_umc_funcs(adev); adev->gmc.shared_aperture_start = 0x2000000000000000ULL; adev->gmc.shared_aperture_end = adev->gmc.shared_aperture_start + (4ULL << 30) - 1; + adev->gmc.private_aperture_start = 0x1000000000000000ULL; - adev->gmc.private_aperture_end = - adev->gmc.private_aperture_start + (4ULL << 30) - 1; + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) + adev->gmc.private_aperture_end = + adev->gmc.private_aperture_start + (1ULL << 57) - 1; + else + adev->gmc.private_aperture_end = + adev->gmc.private_aperture_start + (4ULL << 30) - 1; + + adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; return 0; } @@ -683,17 +696,23 @@ static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); - amdgpu_gmc_vram_location(adev, &adev->gmc, base); - amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); - if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) - amdgpu_gmc_agp_location(adev, mc); - + if (amdgpu_gmc_is_pdb0_enabled(adev)) { + amdgpu_gmc_sysvm_location(adev, mc); + } else { + amdgpu_gmc_set_agp_default(adev, mc); + amdgpu_gmc_vram_location(adev, &adev->gmc, base); + amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); + if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) + amdgpu_gmc_agp_location(adev, mc); + } /* base offset of vram pages */ if (amdgpu_sriov_vf(adev)) adev->vm_manager.vram_base_offset = 0; else adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); + + adev->vm_manager.vram_base_offset += + adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; } /** @@ -709,12 +728,17 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) { int r; - /* size in MB on si */ - adev->gmc.mc_vram_size = - adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; + if (adev->gmc.xgmi.connected_to_cpu) + adev->gmc.mc_vram_size = + adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes; + else + adev->gmc.mc_vram_size = + adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; + adev->gmc.real_vram_size = adev->gmc.mc_vram_size; - if (!(adev->flags & AMD_IS_APU)) { + if (!(adev->flags & AMD_IS_APU) && + !adev->gmc.xgmi.connected_to_cpu) { r = amdgpu_device_resize_fb_bar(adev); if (r) return r; @@ -724,8 +748,12 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev) adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); #ifdef CONFIG_X86_64 - if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { - adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); + if (((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) || + (adev->gmc.xgmi.connected_to_cpu)) { + adev->gmc.aper_base = + adev->mmhub.funcs->get_mc_fb_offset(adev) + + adev->gmc.xgmi.physical_node_id * + adev->gmc.xgmi.node_segment_size; adev->gmc.aper_size = adev->gmc.real_vram_size; } #endif @@ -754,6 +782,14 @@ static int gmc_v12_0_gart_init(struct amdgpu_device *adev) return 0; } + if (amdgpu_gmc_is_pdb0_enabled(adev)) { + adev->gmc.vmid0_page_table_depth = 1; + adev->gmc.vmid0_page_table_block_size = 12; + } else { + adev->gmc.vmid0_page_table_depth = 0; + adev->gmc.vmid0_page_table_block_size = 0; + } + /* Initialize common gart structure */ r = amdgpu_gart_init(adev); if (r) @@ -764,13 +800,21 @@ static int gmc_v12_0_gart_init(struct amdgpu_device *adev) AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_IS_PTE; - return amdgpu_gart_table_vram_alloc(adev); + r = amdgpu_gart_table_vram_alloc(adev); + if (r) + return r; + + if (amdgpu_gmc_is_pdb0_enabled(adev)) + r = amdgpu_gmc_pdb0_alloc(adev); + + return r; } static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, vram_width = 0, vram_type = 0, vram_vendor = 0; struct amdgpu_device *adev = ip_block->adev; + int i; adev->mmhub.funcs->init(adev); @@ -778,12 +822,15 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) spin_lock_init(&adev->gmc.invalidate_lock); - r = amdgpu_atomfirmware_get_vram_info(adev, - &vram_width, &vram_type, &vram_vendor); - adev->gmc.vram_width = vram_width; - - adev->gmc.vram_type = vram_type; - adev->gmc.vram_vendor = vram_vendor; + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { + gmc_v12_1_init_vram_info(adev); + } else { + r = amdgpu_gmc_get_vram_info(adev, + &vram_width, &vram_type, &vram_vendor); + adev->gmc.vram_width = vram_width; + adev->gmc.vram_type = vram_type; + adev->gmc.vram_vendor = vram_vendor; + } switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 0, 0): @@ -797,6 +844,18 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) */ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); break; + case IP_VERSION(12, 1, 0): + bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0), + NUM_XCC(adev->gfx.xcc_mask)); + for (i = 0; i < hweight32(adev->aid_mask); i++) + set_bit(AMDGPU_MMHUB0(i), adev->vmhubs_mask); + /* + * To fulfill 5-level page support, + * vm size is 128PetaByte (57bit), maximum size, + * block size 512 (9bit) + */ + amdgpu_vm_adjust_size(adev, 128 * 1024 * 1024, 9, 4, 57); + break; default: break; } @@ -809,16 +868,40 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, - UTCL2_1_0__SRCID__FAULT, - &adev->gmc.vm_fault); + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_UTCL2, + UTCL2_1_0__SRCID__FAULT, + &adev->gmc.vm_fault); + if (r) + return r; + /* Add GCVM UTCL2 Retry fault */ + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_UTCL2, + UTCL2_1_0__SRCID__RETRY, + &adev->gmc.vm_fault); + if (r) + return r; + + /* Add MMVM UTCL2 Retry fault */ + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, + VMC_1_0__SRCID__VM_RETRY, + &adev->gmc.vm_fault); + } else { + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, + UTCL2_1_0__SRCID__FAULT, + &adev->gmc.vm_fault); + } if (r) return r; if (!amdgpu_sriov_vf(adev)) { /* interrupt sent to DF. */ - r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 0, 0)) + r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, + &adev->gmc.ecc_irq); + else + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_DF, 0, &adev->gmc.ecc_irq); + if (r) return r; } @@ -827,11 +910,11 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) * Set the internal MC address mask This is the max address of the GPU's * internal address space. */ - adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ + adev->gmc.mc_mask = AMDGPU_GMC_HOLE_MASK; r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); if (r) { - printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); + drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); return r; } @@ -843,6 +926,14 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) amdgpu_gmc_get_vbios_allocations(adev); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) { + r = amdgpu_gmc_init_mem_ranges(adev); + if (r) + return r; + } +#endif + /* Memory manager */ r = amdgpu_bo_init(adev); if (r) @@ -858,7 +949,11 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) * amdgpu graphics/compute will use VMIDs 1-7 * amdkfd will use VMIDs 8-15 */ - adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; + adev->vm_manager.first_kfd_vmid = + amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) ? + 3 : 8; + adev->vm_manager.first_kfd_vmid = + adev->gfx.disable_kq ? 1 : (adev->vm_manager.first_kfd_vmid); amdgpu_vm_manager_init(adev); @@ -888,6 +983,7 @@ static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_vm_manager_fini(adev); gmc_v12_0_gart_fini(adev); amdgpu_gem_force_release(adev); + amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); amdgpu_bo_fini(adev); return 0; @@ -907,6 +1003,9 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) int r; bool value; + if (adev->gmc.xgmi.connected_to_cpu) + amdgpu_gmc_init_pdb0(adev); + if (adev->gart.bo == NULL) { dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); return -EINVAL; @@ -924,10 +1023,11 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; adev->mmhub.funcs->set_fault_enable_default(adev, value); - gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); + adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); - dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned)(adev->gmc.gart_size >> 20), + (adev->gmc.pdb0_bo) ? (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo) : (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); return 0; @@ -1026,7 +1126,10 @@ static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, if (r) return r; - return athub_v4_1_0_set_clockgating(adev, state); + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) + return athub_v4_1_0_set_clockgating(adev, state); + else + return 0; } static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) @@ -1035,7 +1138,8 @@ static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u6 adev->mmhub.funcs->get_clockgating(adev, flags); - athub_v4_1_0_get_clockgating(adev, flags); + if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) + athub_v4_1_0_get_clockgating(adev, flags); } static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c new file mode 100644 index 0000000000000..7ea7b9c30bca9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c @@ -0,0 +1,646 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "gmc_v12_1.h" +#include "soc15_common.h" +#include "soc_v1_0_enum.h" +#include "oss/osssys_7_1_0_offset.h" +#include "oss/osssys_7_1_0_sh_mask.h" +#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" + +static int gmc_v12_1_vm_fault_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + struct amdgpu_vmhub *hub; + u32 tmp, reg, i, j; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { + hub = &adev->vmhub[j]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + + /* This works because this interrupt is only + * enabled at init/resume and disabled in + * fini/suspend, so the overall state doesn't + * change over the course of suspend/resume. + */ + if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) + continue; + + if (j >= AMDGPU_MMHUB0(0)) + tmp = RREG32_SOC15_IP(MMHUB, reg); + else + tmp = RREG32_XCC(reg, j); + + tmp &= ~hub->vm_cntx_cntl_vm_fault; + + if (j >= AMDGPU_MMHUB0(0)) + WREG32_SOC15_IP(MMHUB, reg, tmp); + else + WREG32_XCC(reg, tmp, j); + } + } + break; + case AMDGPU_IRQ_STATE_ENABLE: + for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { + hub = &adev->vmhub[j]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + + /* This works because this interrupt is only + * enabled at init/resume and disabled in + * fini/suspend, so the overall state doesn't + * change over the course of suspend/resume. + */ + if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) + continue; + + if (j >= AMDGPU_MMHUB0(0)) + tmp = RREG32_SOC15_IP(MMHUB, reg); + else + tmp = RREG32_XCC(reg, j); + + tmp |= hub->vm_cntx_cntl_vm_fault; + + if (j >= AMDGPU_MMHUB0(0)) + WREG32_SOC15_IP(MMHUB, reg, tmp); + else + WREG32_XCC(reg, tmp, j); + } + } + break; + default: + break; + } + + return 0; +} + +static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct amdgpu_task_info *task_info; + bool retry_fault = false, write_fault = false; + unsigned int vmhub, node_id; + struct amdgpu_vmhub *hub; + uint32_t cam_index = 0; + const char *hub_name; + int ret, xcc_id = 0; + uint32_t status = 0; + u64 addr; + + node_id = entry->node_id; + + addr = (u64)entry->src_data[0] << 12; + addr |= ((u64)entry->src_data[1] & 0x1fff) << 44; + + if (entry->src_id == UTCL2_1_0__SRCID__RETRY) { + retry_fault = true; + write_fault = !!(entry->src_data[1] & AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE); + } + + if (entry->client_id == SOC_V1_0_IH_CLIENTID_VMC) { + hub_name = "mmhub0"; + vmhub = AMDGPU_MMHUB0(node_id / 4); + } else { + hub_name = "gfxhub0"; + if (adev->gfx.funcs->ih_node_to_logical_xcc) { + xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, + node_id); + if (xcc_id < 0) + xcc_id = 0; + } + vmhub = xcc_id; + } + + hub = &adev->vmhub[vmhub]; + + if (retry_fault) { + if (adev->irq.retry_cam_enabled) { + /* Delegate it to a different ring if the hardware hasn't + * already done it. + */ + if (entry->ih == &adev->irq.ih) { + amdgpu_irq_delegate(adev, entry, 8); + return 1; + } + + cam_index = entry->src_data[3] & 0x3ff; + + ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, + addr, entry->timestamp, write_fault); + WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); + if (ret) + return 1; + } else { + /* Process it onyl if it's the first fault for this address */ + if (entry->ih != &adev->irq.ih_soft && + amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, + entry->timestamp)) + return 1; + + /* Delegate it to a different ring if the hardware hasn't + * already done it. + */ + if (entry->ih == &adev->irq.ih) { + amdgpu_irq_delegate(adev, entry, 8); + return 1; + } + + /* Try to handle the recoverable page faults by filling page + * tables + */ + if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, + addr, entry->timestamp, write_fault)) + return 1; + } + } + + if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) + return 1; + + if (!printk_ratelimit()) + return 0; + + dev_err(adev->dev, + "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, + retry_fault ? "retry" : "no-retry", + entry->src_id, entry->ring_id, entry->vmid, entry->pasid); + + task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); + if (task_info) { + amdgpu_vm_print_task_info(adev, task_info); + amdgpu_vm_put_task_info(task_info); + } + + dev_err(adev->dev, " in page starting at address 0x%016llx from IH client %d (%s)\n", + addr, entry->client_id, soc_v1_0_ih_clientid_name[entry->client_id]); + + if (amdgpu_sriov_vf(adev)) + return 0; + + /* + * Issue a dummy read to wait for the status register to + * be updated to avoid reading an incorrect value due to + * the new fast GRBM interface. + */ + if (entry->vmid_src == AMDGPU_GFXHUB(0)) + RREG32(hub->vm_l2_pro_fault_status); + + status = RREG32(hub->vm_l2_pro_fault_status); + + /* Only print L2 fault status if the status register could be read and + * contains useful information + */ + if (!status) + return 0; + + WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); + + amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); + + hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); + + return 0; +} + +static bool gmc_v12_1_get_vmid_pasid_mapping_info(struct amdgpu_device *adev, + uint8_t vmid, uint8_t inst, + uint16_t *p_pasid) +{ + uint16_t index; + + if (inst/4) + index = 0xA + inst%4; + else + index = 0x2 + inst%4; + + WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), index); + + *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; + + return !!(*p_pasid); +} + +/* + * GART + * VMID 0 is the physical GPU addresses as used by the kernel. + * VMIDs 1-15 are used for userspace clients and are handled + * by the amdgpu vm/hsa code. + */ + +static void gmc_v12_1_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, + unsigned int vmhub, uint32_t flush_type) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; + u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); + u32 tmp; + /* Use register 17 for GART */ + const unsigned eng = 17; + unsigned int i; + unsigned char hub_ip = 0; + + hub_ip = (AMDGPU_IS_GFXHUB(vmhub)) ? + GC_HWIP : MMHUB_HWIP; + + spin_lock(&adev->gmc.invalidate_lock); + + WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); + + /* Wait for ACK with a delay.*/ + for (i = 0; i < adev->usec_timeout; i++) { + tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + + hub->eng_distance * eng, hub_ip); + tmp &= 1 << vmid; + if (tmp) + break; + + udelay(1); + } + + /* Issue additional private vm invalidation to MMHUB */ + if (!AMDGPU_IS_GFXHUB(vmhub) && + (hub->vm_l2_bank_select_reserved_cid2) && + !amdgpu_sriov_vf(adev)) { + inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); + /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ + inv_req |= (1 << 25); + /* Issue private invalidation */ + WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); + /* Read back to ensure invalidation is done*/ + RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); + } + + spin_unlock(&adev->gmc.invalidate_lock); + + if (i < adev->usec_timeout) + return; + + dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); +} + +/** + * gmc_v12_1_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * @vmhub: which hub to flush + * @flush_type: the flush type + * + * Flush the TLB for the requested page table. + */ +static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, + uint32_t vmhub, uint32_t flush_type) +{ + u32 inst; + + if (AMDGPU_IS_GFXHUB(vmhub) && + !adev->gfx.is_poweron) + return; + + if (vmhub >= AMDGPU_MMHUB0(0)) + inst = 0; + else + inst = vmhub; + + /* This is necessary for SRIOV as well as for GFXOFF to function + * properly under bare metal + */ + if (((adev->gfx.kiq[inst].ring.sched.ready || + adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) && + (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)))) { + struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; + const unsigned eng = 17; + u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); + u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; + u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; + + amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, + 1 << vmid, inst); + return; + } + + gmc_v12_1_flush_vm_hub(adev, vmid, vmhub, 0); + return; +} + +/** + * gmc_v12_1_flush_gpu_tlb_pasid - tlb flush via pasid + * + * @adev: amdgpu_device pointer + * @pasid: pasid to be flush + * @flush_type: the flush type + * @all_hub: flush all hubs + * @inst: is used to select which instance of KIQ to use for the invalidation + * + * Flush the TLB for the requested pasid. + */ +static void gmc_v12_1_flush_gpu_tlb_pasid(struct amdgpu_device *adev, + uint16_t pasid, uint32_t flush_type, + bool all_hub, uint32_t inst) +{ + uint16_t queried; + int vmid, i; + + if (adev->enable_uni_mes && adev->mes.ring[0].sched.ready && + (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x6f) { + struct mes_inv_tlbs_pasid_input input = {0}; + input.xcc_id = inst; + input.pasid = pasid; + input.flush_type = flush_type; + + /* MES will invalidate hubs for the device(including slave xcc) from master, ignore request from slave */ + if (!amdgpu_gfx_is_master_xcc(adev, inst)) + return; + + input.hub_id = AMDGPU_GFXHUB(0); + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + + if (all_hub) { + /* invalidate mm_hub */ + if (test_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask)) { + input.hub_id = AMDGPU_MMHUB0(0); + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + } + if (test_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask)) { + input.hub_id = AMDGPU_MMHUB1(0); + adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); + } + } + return; + } + + for (vmid = 1; vmid < 16; vmid++) { + bool valid; + + valid = gmc_v12_1_get_vmid_pasid_mapping_info(adev, vmid, inst, + &queried); + if (!valid || queried != pasid) + continue; + + if (all_hub) { + for_each_set_bit(i, adev->vmhubs_mask, + AMDGPU_MAX_VMHUBS) + gmc_v12_1_flush_gpu_tlb(adev, vmid, i, + flush_type); + } else { + gmc_v12_1_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(inst), + flush_type); + } + } +} + +static uint64_t gmc_v12_1_emit_flush_gpu_tlb(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) +{ + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; + uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); + unsigned eng = ring->vm_inv_eng; + + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + + (hub->ctx_addr_distance * vmid), + lower_32_bits(pd_addr)); + + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + + (hub->ctx_addr_distance * vmid), + upper_32_bits(pd_addr)); + + amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + + hub->eng_distance * eng, + hub->vm_inv_eng0_ack + + hub->eng_distance * eng, + req, 1 << vmid); + + return pd_addr; +} + +static void gmc_v12_1_emit_pasid_mapping(struct amdgpu_ring *ring, + unsigned vmid, unsigned pasid) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t reg; + + if (ring->vm_hub == AMDGPU_GFXHUB(0)) + reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; + else + reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; + + amdgpu_ring_emit_wreg(ring, reg, pasid); +} + +/* + * PTE format: + * 63 P + * 62:59 reserved + * 58 D + * 57 G + * 56 T + * 55:54 M + * 53:52 SW + * 51:48 reserved for future + * 47:12 4k physical page base address + * 11:7 fragment + * 6 write + * 5 read + * 4 exe + * 3 Z + * 2 snooped + * 1 system + * 0 valid + * + * PDE format: + * 63 P + * 62:58 block fragment size + * 57 reserved + * 56 A + * 55:54 M + * 53:52 reserved + * 51:48 reserved for future + * 47:6 physical base address of PD or PTE + * 5:3 reserved + * 2 C + * 1 system + * 0 valid + */ + +static void gmc_v12_1_get_vm_pde(struct amdgpu_device *adev, int level, + uint64_t *addr, uint64_t *flags) +{ + if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) + *addr = adev->vm_manager.vram_base_offset + *addr - + adev->gmc.vram_start; + BUG_ON(*addr & 0xFFFF00000000003FULL); + + *flags |= AMDGPU_PTE_SNOOPED; + + if (!adev->gmc.translate_further) + return; + + if (level == AMDGPU_VM_PDB1) { + /* Set the block fragment size */ + if (!(*flags & AMDGPU_PDE_PTE_GFX12)) + *flags |= AMDGPU_PDE_BFS_GFX12(0x9); + + } else if (level == AMDGPU_VM_PDB0) { + if (*flags & AMDGPU_PDE_PTE_GFX12) + *flags &= ~AMDGPU_PDE_PTE_GFX12; + } +} + +static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, + struct amdgpu_bo *bo, + uint64_t *flags) +{ + struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); + bool is_vram = bo->tbo.resource && + bo->tbo.resource->mem_type == TTM_PL_VRAM; + bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | + AMDGPU_GEM_CREATE_EXT_COHERENT); + bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; + uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); + bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; + unsigned int mtype, mtype_local, mtype_remote; + bool snoop = false; + bool is_local = false; + bool is_aid_a1; + + switch (gc_ip_version) { + case IP_VERSION(12, 1, 0): + is_aid_a1 = (adev->rev_id & 0x10); + + mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC; + mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC; + if (amdgpu_mtype_local == 0) { + DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); + mtype_local = MTYPE_RW; + } else if (amdgpu_mtype_local == 1) { + DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); + mtype_local = MTYPE_NC; + } else if (amdgpu_mtype_local == 2) { + DRM_INFO_ONCE("MTYPE_CC not supported, using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC"); + } else { + DRM_INFO_ONCE("Using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC"); + } + + is_local = (is_vram && adev == bo_adev); + snoop = true; + if (uncached) { + mtype = MTYPE_UC; + } else if (ext_coherent) { + mtype = is_local ? mtype_local : MTYPE_UC; + } else { + mtype = is_local ? mtype_local : mtype_remote; + } + break; + default: + if (uncached || coherent) + mtype = MTYPE_UC; + else + mtype = MTYPE_NC; + } + + if (mtype != MTYPE_NC) + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, mtype); + + if (is_local || adev->have_atomics_support) + *flags |= AMDGPU_PTE_BUS_ATOMICS; + + *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; +} + +static void gmc_v12_1_get_vm_pte(struct amdgpu_device *adev, + struct amdgpu_vm *vm, + struct amdgpu_bo *bo, + uint32_t vm_flags, + uint64_t *flags) +{ + if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) + *flags |= AMDGPU_PTE_EXECUTABLE; + else + *flags &= ~AMDGPU_PTE_EXECUTABLE; + + switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { + case AMDGPU_VM_MTYPE_DEFAULT: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_NC: + default: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); + break; + case AMDGPU_VM_MTYPE_RW: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_RW); + break; + case AMDGPU_VM_MTYPE_UC: + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); + break; + } + + if ((*flags & AMDGPU_PTE_VALID) && bo) + gmc_v12_1_get_coherence_flags(adev, bo, flags); +} + +static const struct amdgpu_gmc_funcs gmc_v12_1_gmc_funcs = { + .flush_gpu_tlb = gmc_v12_1_flush_gpu_tlb, + .flush_gpu_tlb_pasid = gmc_v12_1_flush_gpu_tlb_pasid, + .emit_flush_gpu_tlb = gmc_v12_1_emit_flush_gpu_tlb, + .emit_pasid_mapping = gmc_v12_1_emit_pasid_mapping, + .get_vm_pde = gmc_v12_1_get_vm_pde, + .get_vm_pte = gmc_v12_1_get_vm_pte, + .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition, + .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, +}; + +void gmc_v12_1_set_gmc_funcs(struct amdgpu_device *adev) +{ + adev->gmc.gmc_funcs = &gmc_v12_1_gmc_funcs; +} + +static const struct amdgpu_irq_src_funcs gmc_v12_1_irq_funcs = { + .set = gmc_v12_1_vm_fault_interrupt_state, + .process = gmc_v12_1_process_interrupt, +}; + +static const struct amdgpu_irq_src_funcs gmc_v12_1_ecc_funcs = { + .process = amdgpu_umc_uniras_process_ecc_irq, +}; + +void gmc_v12_1_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->gmc.vm_fault.num_types = 1; + adev->gmc.vm_fault.funcs = &gmc_v12_1_irq_funcs; + + adev->gmc.ecc_irq.num_types = 1; + adev->gmc.ecc_irq.funcs = &gmc_v12_1_ecc_funcs; +} + +void gmc_v12_1_init_vram_info(struct amdgpu_device *adev) +{ + /* TODO: query vram_info from ip discovery binary */ + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM4; + adev->gmc.vram_width = 384 * 64; +} diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.h b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.h new file mode 100644 index 0000000000000..2f08f4b8cd99e --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.h @@ -0,0 +1,30 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __GMC_V12_1_H__ +#define __GMC_V12_1_H__ + +void gmc_v12_1_set_gmc_funcs(struct amdgpu_device *adev); +void gmc_v12_1_set_irq_funcs(struct amdgpu_device *adev); +void gmc_v12_1_init_vram_info(struct amdgpu_device *adev); +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index a8ec95f42926b..b4d597772f0b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -211,7 +211,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); } @@ -555,7 +554,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) gmc_v6_0_set_fault_enable_default(adev, true); gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0); - dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), (unsigned long long)table_addr); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index fbd0bf147f50c..18c9839f4a500 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -242,7 +242,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } @@ -705,7 +704,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) } gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); - DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), (unsigned long long)table_addr); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 6551b60f25847..98baad2cfbc50 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -417,7 +417,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } @@ -555,12 +554,17 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) break; } adev->gmc.vram_width = numchan * chansize; + /* FIXME: The above calculation is outdated. + * For HBM provide a temporary fix + */ + if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) + adev->gmc.vram_width = AMDGPU_VRAM_TYPE_HBM_WIDTH; } /* size in MB on si */ tmp = RREG32(mmCONFIG_MEMSIZE); /* some boards may have garbage in the upper 16 bits */ if (tmp & 0xffff0000) { - DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); + drm_info(adev_to_drm(adev), "Probably bad vram size: 0x%08x\n", tmp); if (tmp & 0xffff) tmp &= 0xffff; } @@ -939,7 +943,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) gmc_v8_0_set_fault_enable_default(adev, true); gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); - DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned int)(adev->gmc.gart_size >> 20), (unsigned long long)table_addr); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index f1ee3921d970c..b38769162de8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -583,44 +583,13 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, hub = &adev->vmhub[vmhub]; if (retry_fault) { - if (adev->irq.retry_cam_enabled) { - /* Delegate it to a different ring if the hardware hasn't - * already done it. - */ - if (entry->ih == &adev->irq.ih) { - amdgpu_irq_delegate(adev, entry, 8); - return 1; - } - - cam_index = entry->src_data[2] & 0x3ff; - - ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, - addr, entry->timestamp, write_fault); - WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); - if (ret) - return 1; - } else { - /* Process it onyl if it's the first fault for this address */ - if (entry->ih != &adev->irq.ih_soft && - amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, - entry->timestamp)) - return 1; - - /* Delegate it to a different ring if the hardware hasn't - * already done it. - */ - if (entry->ih == &adev->irq.ih) { - amdgpu_irq_delegate(adev, entry, 8); - return 1; - } + cam_index = entry->src_data[2] & 0x3ff; - /* Try to handle the recoverable page faults by filling page - * tables - */ - if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, - addr, entry->timestamp, write_fault)) - return 1; - } + ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, cam_index, node_id, + write_fault); + /* Returning 1 here also prevents sending the IV to the KFD */ + if (ret == 1) + return 1; } if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) @@ -691,35 +660,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, gfxhub_client_ids[cid], cid); } else { - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(9, 0, 0): - mmhub_cid = mmhub_client_ids_vega10[cid][rw]; - break; - case IP_VERSION(9, 3, 0): - mmhub_cid = mmhub_client_ids_vega12[cid][rw]; - break; - case IP_VERSION(9, 4, 0): - mmhub_cid = mmhub_client_ids_vega20[cid][rw]; - break; - case IP_VERSION(9, 4, 1): - mmhub_cid = mmhub_client_ids_arcturus[cid][rw]; - break; - case IP_VERSION(9, 1, 0): - case IP_VERSION(9, 2, 0): - mmhub_cid = mmhub_client_ids_raven[cid][rw]; - break; - case IP_VERSION(1, 5, 0): - case IP_VERSION(2, 4, 0): - mmhub_cid = mmhub_client_ids_renoir[cid][rw]; - break; - case IP_VERSION(1, 8, 0): - case IP_VERSION(9, 4, 2): - mmhub_cid = mmhub_client_ids_aldebaran[cid][rw]; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); } @@ -1119,7 +1060,7 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, bool snoop = false; bool is_local; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); switch (gc_ip_version) { case IP_VERSION(9, 4, 1): @@ -1168,13 +1109,13 @@ static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev, */ mtype_local = MTYPE_RW; if (amdgpu_mtype_local == 1) { - DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); + drm_info_once(adev_to_drm(adev), "Using MTYPE_NC for local memory\n"); mtype_local = MTYPE_NC; } else if (amdgpu_mtype_local == 2) { - DRM_INFO_ONCE("Using MTYPE_CC for local memory\n"); + drm_info_once(adev_to_drm(adev), "Using MTYPE_CC for local memory\n"); mtype_local = MTYPE_CC; } else { - DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); + drm_info_once(adev_to_drm(adev), "Using MTYPE_RW for local memory\n"); } is_local = (!is_vram && (adev->flags & AMD_IS_APU) && num_possible_nodes() <= 1) || @@ -1459,6 +1400,52 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) } } +static void gmc_v9_0_init_mmhub_client_info(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { + case IP_VERSION(9, 0, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vega10, + ARRAY_SIZE(mmhub_client_ids_vega10)); + break; + case IP_VERSION(9, 3, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vega12, + ARRAY_SIZE(mmhub_client_ids_vega12)); + break; + case IP_VERSION(9, 4, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vega20, + ARRAY_SIZE(mmhub_client_ids_vega20)); + break; + case IP_VERSION(9, 4, 1): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_arcturus, + ARRAY_SIZE(mmhub_client_ids_arcturus)); + break; + case IP_VERSION(9, 1, 0): + case IP_VERSION(9, 2, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_raven, + ARRAY_SIZE(mmhub_client_ids_raven)); + break; + case IP_VERSION(1, 5, 0): + case IP_VERSION(2, 4, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_renoir, + ARRAY_SIZE(mmhub_client_ids_renoir)); + break; + case IP_VERSION(1, 8, 0): + case IP_VERSION(9, 4, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_aldebaran, + ARRAY_SIZE(mmhub_client_ids_aldebaran)); + break; + default: + break; + } +} + static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) { switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { @@ -1476,6 +1463,8 @@ static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev) adev->mmhub.funcs = &mmhub_v1_0_funcs; break; } + + gmc_v9_0_init_mmhub_client_info(adev); } static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev) @@ -1667,8 +1656,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, { u64 base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); - /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; if (amdgpu_gmc_is_pdb0_enabled(adev)) { @@ -1834,24 +1821,37 @@ static void gmc_v9_0_save_registers(struct amdgpu_device *adev) adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); } -static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) +static void gmc_v9_0_init_vram_info(struct amdgpu_device *adev) { static const u32 regBIF_BIOS_SCRATCH_4 = 0x50; + int dev_var = adev->pdev->device & 0xF; u32 vram_info; - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; - adev->gmc.vram_width = 128 * 64; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && - adev->rev_id == 0x3) - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; - - if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { - vram_info = RREG32(regBIF_BIOS_SCRATCH_4); - adev->gmc.vram_vendor = vram_info & 0xF; + if (adev->gmc.is_app_apu) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; + adev->gmc.vram_width = 128 * 64; + } else if (adev->flags & AMD_IS_APU) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; + adev->gmc.vram_width = 64 * 64; + } else if (amdgpu_is_multi_aid(adev)) { + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; + adev->gmc.vram_width = 128 * 64; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) && + adev->rev_id == 0x3) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && + (dev_var == 0x5)) + adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E; + + if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) { + vram_info = RREG32(regBIF_BIOS_SCRATCH_4); + adev->gmc.vram_vendor = vram_info & 0xF; + } } } @@ -1867,19 +1867,11 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) spin_lock_init(&adev->gmc.invalidate_lock); - if (amdgpu_is_multi_aid(adev)) { - gmc_v9_4_3_init_vram_info(adev); - } else if (!adev->bios) { - if (adev->flags & AMD_IS_APU) { - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; - adev->gmc.vram_width = 64 * 64; - } else { - adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; - adev->gmc.vram_width = 128 * 64; - } + if (!adev->bios) { + gmc_v9_0_init_vram_info(adev); } else { - r = amdgpu_atomfirmware_get_vram_info(adev, - &vram_width, &vram_type, &vram_vendor); + r = amdgpu_gmc_get_vram_info(adev, + &vram_width, &vram_type, &vram_vendor); if (amdgpu_sriov_vf(adev)) /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN, * and DF related registers is not readable, seems hardcord is the @@ -1907,6 +1899,7 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) adev->gmc.vram_type = vram_type; adev->gmc.vram_vendor = vram_vendor; } + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 1, 0): case IP_VERSION(9, 2, 2): @@ -2006,7 +1999,7 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) 44; r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits)); if (r) { - dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); + drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); return r; } adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits); @@ -2162,12 +2155,12 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) if (r) return r; - DRM_INFO("PCIE GART of %uM enabled.\n", + drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled.\n", (unsigned int)(adev->gmc.gart_size >> 20)); if (adev->gmc.pdb0_bo) - DRM_INFO("PDB0 located at 0x%016llX\n", + drm_info(adev_to_drm(adev), "PDB0 located at 0x%016llX\n", (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); - DRM_INFO("PTB located at 0x%016llX\n", + drm_info(adev_to_drm(adev), "PTB located at 0x%016llX\n", (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index e6c0d86d34865..239b3c8b1237b 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -36,6 +36,9 @@ #define HDP_MEM_POWER_CTRL__RC_MEM_POWER_LS_EN_MASK 0x00020000L #define mmHDP_MEM_POWER_CTRL_BASE_IDX 0 +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK 0x00000010L +#define HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE__SHIFT 0x4 + static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { @@ -136,6 +139,9 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, static void hdp_v4_0_init_registers(struct amdgpu_device *adev) { + uint32_t aid_mask = adev->aid_mask; + u32 tmp, i; + switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { case IP_VERSION(4, 2, 1): WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); @@ -152,6 +158,17 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 0)) WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2); + else if (amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 2) && + !adev->gmc.is_app_apu) { + for_each_inst(i, aid_mask) { + tmp = RREG32_SOC15(HDP, GET_INST(HDP, i), mmHDP_MMHUB_CNTL); + if (tmp & HDP_MMHUB_CNTL__HDP_MMHUB_RO_OVERRIDE_MASK ) { + tmp = REG_SET_FIELD(tmp, HDP_MMHUB_CNTL, HDP_MMHUB_RO_OVERRIDE, 0); + WREG32_SOC15(HDP, GET_INST(HDP, i), mmHDP_MMHUB_CNTL, tmp); + } + } + + } WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index b32ea4129c616..1fbe904f4223b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -279,6 +279,23 @@ static int ih_v7_0_enable_ring(struct amdgpu_device *adev, return 0; } +static uint32_t ih_v7_0_setup_retry_doorbell(u32 doorbell_index) +{ + u32 val = 0; + + val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index); + val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1); + + return val; +} + +#define regIH_RING1_CLIENT_CFG_INDEX_V7_1 0x122 +#define regIH_RING1_CLIENT_CFG_INDEX_V7_1_BASE_IDX 0 +#define regIH_RING1_CLIENT_CFG_DATA_V7_1 0x123 +#define regIH_RING1_CLIENT_CFG_DATA_V7_1_BASE_IDX 0 +#define regIH_CHICKEN_V7_1 0x129 +#define regIH_CHICKEN_V7_1_BASE_IDX 0 + /** * ih_v7_0_irq_init - init and enable the interrupt ring * @@ -297,6 +314,7 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) u32 tmp; int ret; int i; + u32 reg_addr; /* disable irqs */ ret = ih_v7_0_toggle_interrupts(adev, false); @@ -308,10 +326,15 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) || (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) { if (ih[0]->use_bus_addr) { - ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_CHICKEN_V7_1); + else + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_CHICKEN); + ih_chicken = RREG32(reg_addr); + /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); - WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken); + WREG32(reg_addr, ih_chicken); } } @@ -348,21 +371,45 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) /* Redirect the interrupts to IH RB1 for dGPU */ if (adev->irq.ih1.ring_size) { - tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX_V7_1); + else + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX); + tmp = RREG32(reg_addr); + /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0); - WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp); + WREG32(reg_addr, tmp); - tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA_V7_1); + else + reg_addr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA); + tmp = RREG32(reg_addr); + /* The reg fields definitions are identical in ih v7_0 and ih v7_1 */ tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa); tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0); tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID_MATCH_ENABLE, 0x1); - - WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp); + WREG32(reg_addr, tmp); } pci_set_master(adev->pdev); + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) { + /* Allocate the doorbell for IH Retry CAM */ + adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 2) << 1; + WREG32_SOC15(OSSSYS, 0, regIH_DOORBELL_RETRY_CAM, + ih_v7_0_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index)); + + /* Enable IH Retry CAM */ + tmp = RREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL); + tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, ENABLE, 1); + tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, CAM_SIZE, 0xF); + WREG32_SOC15(OSSSYS, 0, regIH_RETRY_INT_CAM_CNTL, tmp); + + adev->irq.retry_cam_enabled = true; + } + /* enable interrupts */ ret = ih_v7_0_toggle_interrupts(adev, true); if (ret) @@ -542,6 +589,7 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) int r; struct amdgpu_device *adev = ip_block->adev; bool use_bus_addr; + unsigned int sw_ring_size; r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0, &adev->irq.self_irq); @@ -573,7 +621,9 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) /* initialize ih control register offset */ ih_v7_0_init_register_offset(adev); - r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true); + sw_ring_size = (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(7, 1, 0)) ? + IH_SW_RING_SIZE : PAGE_SIZE; + r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, sw_ring_size, true); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index cc626036ed9c3..46d25d55ebbeb 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -41,6 +41,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_1_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_2_imu.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_3_imu.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_imu.bin"); static int imu_v11_0_init_microcode(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c new file mode 100644 index 0000000000000..539785a51f69f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c @@ -0,0 +1,166 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "amdgpu_imu.h" +#include "amdgpu_dpm.h" + +#include "imu_v12_1.h" + +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "mmhub/mmhub_4_2_0_offset.h" + +MODULE_FIRMWARE("amdgpu/gc_12_1_0_imu.bin"); + +#define TRANSFER_RAM_MASK 0x001c0000 + +static int imu_v12_1_init_microcode(struct amdgpu_device *adev) +{ + char ucode_prefix[15]; + int err; + const struct imu_firmware_header_v1_0 *imu_hdr; + struct amdgpu_firmware_info *info = NULL; + + DRM_DEBUG("\n"); + + amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); + err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s_imu.bin", ucode_prefix); + if (err) + goto out; + + imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; + adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I]; + info->ucode_id = AMDGPU_UCODE_ID_IMU_I; + info->fw = adev->gfx.imu_fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes), PAGE_SIZE); + info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_D]; + info->ucode_id = AMDGPU_UCODE_ID_IMU_D; + info->fw = adev->gfx.imu_fw; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes), PAGE_SIZE); + } + +out: + if (err) { + dev_err(adev->dev, + "gfx12: Failed to load firmware \"%s_imu.bin\"\n", + ucode_prefix); + amdgpu_ucode_release(&adev->gfx.imu_fw); + } + + return err; +} + +static void imu_v12_1_xcc_load_microcode(struct amdgpu_device *adev, + int xcc_id) +{ + const struct imu_firmware_header_v1_0 *hdr; + const __le32 *fw_data; + unsigned i, fw_size; + + hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; + fw_data = (const __le32 *)(adev->gfx.imu_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + fw_size = le32_to_cpu(hdr->imu_iram_ucode_size_bytes) / 4; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGFX_IMU_I_RAM_ADDR, 0); + + for (i = 0; i < fw_size; i++) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regGFX_IMU_I_RAM_DATA, + le32_to_cpup(fw_data++)); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regGFX_IMU_I_RAM_ADDR, + adev->gfx.imu_fw_version); + + fw_data = (const __le32 *)(adev->gfx.imu_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + + le32_to_cpu(hdr->imu_iram_ucode_size_bytes)); + fw_size = le32_to_cpu(hdr->imu_dram_ucode_size_bytes) / 4; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGFX_IMU_D_RAM_ADDR, 0); + + for (i = 0; i < fw_size; i++) + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regGFX_IMU_D_RAM_DATA, + le32_to_cpup(fw_data++)); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regGFX_IMU_D_RAM_ADDR, + adev->gfx.imu_fw_version); +} + +static int imu_v12_1_load_microcode(struct amdgpu_device *adev) +{ + int i, num_xcc; + + if (!adev->gfx.imu_fw) + return -EINVAL; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + for (i = 0; i < num_xcc; i++) { + imu_v12_1_xcc_load_microcode(adev, i); + } + + return 0; +} + +static int imu_v12_1_switch_compute_partition(struct amdgpu_device *adev, + int num_xccs_per_xcp, + int compute_partition_mode) +{ + int ret; + + if (adev->psp.funcs) { + /*TODO: revisit asp interface once it's avaialble */ + ret = psp_spatial_partition(&adev->psp, + NUM_XCC(adev->gfx.xcc_mask) / + num_xccs_per_xcp); + if (ret) + return ret; + } + + adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; + + return 0; +} + +static void imu_v12_1_init_mcm_addr_lut(struct amdgpu_device *adev) +{ + /* todo: fill in when interface is ready */ +} + +const struct amdgpu_imu_funcs gfx_v12_1_imu_funcs = { + .init_microcode = imu_v12_1_init_microcode, + .load_microcode = imu_v12_1_load_microcode, + .switch_compute_partition = imu_v12_1_switch_compute_partition, + .init_mcm_addr_lut = imu_v12_1_init_mcm_addr_lut, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.h b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.h new file mode 100644 index 0000000000000..4a7c12bf7b0fb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.h @@ -0,0 +1,30 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __IMU_V12_1_H__ +#define __IMU_V12_1_H__ + +extern const struct amdgpu_imu_funcs gfx_v12_1_imu_funcs; + +#endif + diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c index 0002bcc6c4ec0..b0931932e3194 100644 --- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c +++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c @@ -129,7 +129,7 @@ static int isp_genpd_add_device(struct device *dev, void *data) if (!pdev) return -EINVAL; - if (!dev->type->name) { + if (!dev->type || !dev->type->name) { drm_dbg(&adev->ddev, "Invalid device type to add\n"); goto exit; } @@ -165,7 +165,7 @@ static int isp_genpd_remove_device(struct device *dev, void *data) if (!pdev) return -EINVAL; - if (!dev->type->name) { + if (!dev->type || !dev->type->name) { drm_dbg(&adev->ddev, "Invalid device type to remove\n"); goto exit; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 27c76bd424cfb..9fe8d10ab2705 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -240,7 +240,7 @@ static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev) UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); if (r) { - DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); + drm_err(adev_to_drm(adev), "failed to disable JPEG power gating\n"); return r; } } @@ -271,7 +271,7 @@ static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev) UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); if (r) { - DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); + drm_err(adev_to_drm(adev), "failed to enable JPEG power gating\n"); return r; } } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index d1a011c40ba23..98f5e0622bc58 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -298,7 +298,7 @@ static int jpeg_v3_0_disable_static_power_gating(struct amdgpu_device *adev) UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); if (r) { - DRM_ERROR("amdgpu: JPEG disable power gating failed\n"); + drm_err(adev_to_drm(adev), "failed to disable JPEG power gating\n"); return r; } } @@ -333,7 +333,7 @@ static int jpeg_v3_0_enable_static_power_gating(struct amdgpu_device *adev) UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); if (r) { - DRM_ERROR("amdgpu: JPEG enable power gating failed\n"); + drm_err(adev_to_drm(adev), "failed to enable JPEG power gating\n"); return r; } } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 33db2c1ae6cca..0bd83820dd20c 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -335,7 +335,7 @@ static int jpeg_v4_0_disable_static_power_gating(struct amdgpu_device *adev) UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); if (r) { - DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG disable power gating failed\n"); + drm_err(adev_to_drm(adev), "failed to disable JPEG power gating\n"); return r; } } @@ -370,7 +370,7 @@ static int jpeg_v4_0_enable_static_power_gating(struct amdgpu_device *adev) UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK); if (r) { - DRM_DEV_ERROR(adev->dev, "amdgpu: JPEG enable power gating failed\n"); + drm_err(adev_to_drm(adev), "failed to enable JPEG power gating\n"); return r; } } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index aae7328973d18..4b4aa95536242 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -1145,13 +1145,18 @@ static int jpeg_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) { - if (amdgpu_sriov_vf(ring->adev)) - return -EOPNOTSUPP; + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + int r; + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); amdgpu_ring_reset_helper_begin(ring, timedout_fence); jpeg_v4_0_3_core_stall_reset(ring); jpeg_v4_0_3_start_jrbc(ring); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + mutex_unlock(&vinst->engine_reset_mutex); + return r; } static const struct amd_ip_funcs jpeg_v4_0_3_ip_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c index ab0bf880d3d8a..edecbfe66c79a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c @@ -844,10 +844,19 @@ static int jpeg_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) { + struct amdgpu_device *adev = ring->adev; + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + int r; + + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); + amdgpu_ring_reset_helper_begin(ring, timedout_fence); jpeg_v5_0_1_core_stall_reset(ring); jpeg_v5_0_1_init_jrbc(ring); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + mutex_unlock(&vinst->engine_reset_mutex); + return r; } static const struct amd_ip_funcs jpeg_v5_0_1_ip_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c new file mode 100644 index 0000000000000..285c459379c4a --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.c @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu.h" +#include "amdgpu_jpeg.h" +#include "amdgpu_pm.h" +#include "soc15.h" +#include "soc15d.h" +#include "jpeg_v4_0_3.h" +#include "jpeg_v5_0_2.h" +#include "mmsch_v5_0.h" + +#include "vcn/vcn_5_0_0_offset.h" +#include "vcn/vcn_5_0_0_sh_mask.h" +#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" + +static void jpeg_v5_0_2_set_dec_ring_funcs(struct amdgpu_device *adev); +static void jpeg_v5_0_2_set_irq_funcs(struct amdgpu_device *adev); +static int jpeg_v5_0_2_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state); +static void jpeg_v5_0_2_dec_ring_set_wptr(struct amdgpu_ring *ring); + +static int amdgpu_ih_srcid_jpeg[] = { + VCN_5_0__SRCID__JPEG_DECODE, + VCN_5_0__SRCID__JPEG1_DECODE, + VCN_5_0__SRCID__JPEG2_DECODE, + VCN_5_0__SRCID__JPEG3_DECODE, + VCN_5_0__SRCID__JPEG4_DECODE, + VCN_5_0__SRCID__JPEG5_DECODE, + VCN_5_0__SRCID__JPEG6_DECODE, + VCN_5_0__SRCID__JPEG7_DECODE, + VCN_5_0__SRCID__JPEG8_DECODE, + VCN_5_0__SRCID__JPEG9_DECODE, +}; + +static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0_2[] = { + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC1_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC2_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC3_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC4_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC5_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC6_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC7_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC8_UVD_JRBC_STATUS), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_RPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_RB_WPTR), + SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC9_UVD_JRBC_STATUS), +}; + +static int jpeg_v5_0_2_core_reg_offset(u32 pipe) +{ + if (pipe <= AMDGPU_MAX_JPEG_RINGS_4_0_3) + return ((0x40 * pipe) - 0xc80); + else + return ((0x40 * pipe) - 0x440); +} + +/** + * jpeg_v5_0_2_early_init - set function pointers + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Set ring and irq function pointers + */ +static int jpeg_v5_0_2_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) + return -ENOENT; + + adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; + jpeg_v5_0_2_set_dec_ring_funcs(adev); + jpeg_v5_0_2_set_irq_funcs(adev); + + return 0; +} + +/** + * jpeg_v5_0_2_sw_init - sw init for JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Load firmware and sw initialization + */ +static int jpeg_v5_0_2_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, j, r, jpeg_inst; + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + /* JPEG TRAP */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, + amdgpu_ih_srcid_jpeg[j], &adev->jpeg.inst->irq); + if (r) + return r; + } + + r = amdgpu_jpeg_sw_init(adev); + if (r) + return r; + + r = amdgpu_jpeg_resume(adev); + if (r) + return r; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + jpeg_inst = GET_INST(JPEG, i); + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + ring->use_doorbell = false; + ring->vm_hub = AMDGPU_MMHUB0(adev->jpeg.inst[i].aid_id); + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 1 + j + 11 * jpeg_inst; + sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j); + r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, + AMDGPU_RING_PRIO_DEFAULT, NULL); + if (r) + return r; + + adev->jpeg.internal.jpeg_pitch[j] = + regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET; + adev->jpeg.inst[i].external.jpeg_pitch[j] = + SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0, + (j ? jpeg_v5_0_2_core_reg_offset(j) : 0)); + } + } + + r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_2, ARRAY_SIZE(jpeg_reg_list_5_0_2)); + if (r) + return r; + + adev->jpeg.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); + adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + r = amdgpu_jpeg_sysfs_reset_mask_init(adev); + + return r; +} + +/** + * jpeg_v5_0_2_sw_fini - sw fini for JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * JPEG suspend and free up sw allocation + */ +static int jpeg_v5_0_2_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_jpeg_suspend(adev); + if (r) + return r; + + amdgpu_jpeg_sysfs_reset_mask_fini(adev); + + r = amdgpu_jpeg_sw_fini(adev); + + return r; +} + +/** + * jpeg_v5_0_2_hw_init - start and test JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + */ +static int jpeg_v5_0_2_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, j, r, jpeg_inst, tmp; + + if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) + adev->jpeg.caps |= AMDGPU_JPEG_CAPS(RRMT_ENABLED); + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + jpeg_inst = GET_INST(JPEG, i); + ring = adev->jpeg.inst[i].ring_dec; + + /* Remove JPEG Tile antihang mechanism */ + tmp = RREG32_SOC15(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS); + tmp &= (~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); + WREG32_SOC15(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS, tmp); + + if (ring->use_doorbell) + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 11 * jpeg_inst, + adev->jpeg.inst[i].aid_id); + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + if (ring->use_doorbell) + WREG32_SOC15_OFFSET(VCN, GET_INST(VCN, i), regVCN_JPEG_DB_CTRL, + ring->pipe, + ring->doorbell_index << + VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + } + } + + return 0; +} + +/** + * jpeg_v5_0_2_hw_fini - stop the hardware block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Stop the JPEG block, mark ring as not ready any more + */ +static int jpeg_v5_0_2_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret = 0; + + cancel_delayed_work_sync(&adev->jpeg.idle_work); + + if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) + ret = jpeg_v5_0_2_set_powergating_state(ip_block, AMD_PG_STATE_GATE); + + return ret; +} + +/** + * jpeg_v5_0_2_suspend - suspend JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * HW fini and suspend JPEG block + */ +static int jpeg_v5_0_2_suspend(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = jpeg_v5_0_2_hw_fini(ip_block); + if (r) + return r; + + r = amdgpu_jpeg_suspend(adev); + + return r; +} + +/** + * jpeg_v5_0_2_resume - resume JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Resume firmware and hw init JPEG block + */ +static int jpeg_v5_0_2_resume(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_jpeg_resume(adev); + if (r) + return r; + + r = jpeg_v5_0_2_hw_init(ip_block); + + return r; +} + +static void jpeg_v5_0_2_init_inst(struct amdgpu_device *adev, int i) +{ + int jpeg_inst = GET_INST(JPEG, i); + + /* disable anti hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, + ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); + + /* keep the JPEG in static PG mode */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0, + ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK); + + /* MJPEG global tiling registers */ + WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + + /* enable JMI channel */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0, + ~UVD_JMI_CNTL__SOFT_RESET_MASK); +} + +static void jpeg_v5_0_2_deinit_inst(struct amdgpu_device *adev, int i) +{ + int jpeg_inst = GET_INST(JPEG, i); + /* reset JMI */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), + UVD_JMI_CNTL__SOFT_RESET_MASK, + ~UVD_JMI_CNTL__SOFT_RESET_MASK); + + /* enable anti hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), + UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, + ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); +} + +static void jpeg_v5_0_2_init_jrbc(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 reg, data, mask; + int jpeg_inst = GET_INST(JPEG, ring->me); + int reg_offset = ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0; + + /* enable System Interrupt for JRBC */ + reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN); + if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) { + data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe; + mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe); + WREG32_P(reg, data, mask); + } else { + data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12); + mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12)); + WREG32_P(reg, data, mask); + } + + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_LMI_JRBC_RB_VMID, + reg_offset, 0); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_CNTL, + reg_offset, + (0x00000001L | 0x00000002L)); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, + reg_offset, lower_32_bits(ring->gpu_addr)); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, + reg_offset, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_RPTR, + reg_offset, 0); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_WPTR, + reg_offset, 0); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_CNTL, + reg_offset, 0x00000002L); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JRBC_RB_SIZE, + reg_offset, ring->ring_size / 4); + ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR, + reg_offset); +} + +/** + * jpeg_v5_0_2_start - start JPEG block + * + * @adev: amdgpu_device pointer + * + * Setup and start the JPEG block + */ +static int jpeg_v5_0_2_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring; + int i, j; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + jpeg_v5_0_2_init_inst(adev, i); + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + jpeg_v5_0_2_init_jrbc(ring); + } + } + + return 0; +} + +/** + * jpeg_v5_0_2_stop - stop JPEG block + * + * @adev: amdgpu_device pointer + * + * stop the JPEG block + */ +static int jpeg_v5_0_2_stop(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) + jpeg_v5_0_2_deinit_inst(adev, i); + + return 0; +} + +/** + * jpeg_v5_0_2_dec_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t jpeg_v5_0_2_dec_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_RPTR, + ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0); +} + +/** + * jpeg_v5_0_2_dec_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t jpeg_v5_0_2_dec_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) + return adev->wb.wb[ring->wptr_offs]; + + return RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), regUVD_JRBC_RB_WPTR, + ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0); +} + +/** + * jpeg_v5_0_2_dec_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void jpeg_v5_0_2_dec_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); + } else { + WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), + regUVD_JRBC_RB_WPTR, + (ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0), + lower_32_bits(ring->wptr)); + } +} + +static bool jpeg_v5_0_2_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + bool ret = false; + int i, j; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + int reg_offset = (j ? jpeg_v5_0_2_core_reg_offset(j) : 0); + + ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), + regUVD_JRBC_STATUS, reg_offset) & + UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == + UVD_JRBC_STATUS__RB_JOB_DONE_MASK); + } + } + + return ret; +} + +static int jpeg_v5_0_2_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret = 0; + int i, j; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + int reg_offset = (j ? jpeg_v5_0_2_core_reg_offset(j) : 0); + + ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), + regUVD_JRBC_STATUS, reg_offset, + UVD_JRBC_STATUS__RB_JOB_DONE_MASK, + UVD_JRBC_STATUS__RB_JOB_DONE_MASK); + } + } + return ret; +} + +static int jpeg_v5_0_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + bool enable = state == AMD_CG_STATE_GATE; + + int i; + + if (!enable) + return 0; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + if (!jpeg_v5_0_2_is_idle(ip_block)) + return -EBUSY; + } + + return 0; +} + +static int jpeg_v5_0_2_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret; + + if (state == adev->jpeg.cur_state) + return 0; + + if (state == AMD_PG_STATE_GATE) + ret = jpeg_v5_0_2_stop(adev); + else + ret = jpeg_v5_0_2_start(adev); + + if (!ret) + adev->jpeg.cur_state = state; + + return ret; +} + +static int jpeg_v5_0_2_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + return 0; +} + +static int jpeg_v5_0_2_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + u32 i, inst; + + i = node_id_to_phys_map[entry->node_id]; + DRM_DEV_DEBUG(adev->dev, "IH: JPEG TRAP\n"); + + for (inst = 0; inst < adev->jpeg.num_jpeg_inst; ++inst) + if (adev->jpeg.inst[inst].aid_id == i) + break; + + if (inst >= adev->jpeg.num_jpeg_inst) { + dev_WARN_ONCE(adev->dev, 1, + "Interrupt received for unknown JPEG instance %d", + entry->node_id); + return 0; + } + + switch (entry->src_id) { + case VCN_5_0__SRCID__JPEG_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[0]); + break; + case VCN_5_0__SRCID__JPEG1_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[1]); + break; + case VCN_5_0__SRCID__JPEG2_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[2]); + break; + case VCN_5_0__SRCID__JPEG3_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[3]); + break; + case VCN_5_0__SRCID__JPEG4_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[4]); + break; + case VCN_5_0__SRCID__JPEG5_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[5]); + break; + case VCN_5_0__SRCID__JPEG6_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[6]); + break; + case VCN_5_0__SRCID__JPEG7_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[7]); + break; + case VCN_5_0__SRCID__JPEG8_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[8]); + break; + case VCN_5_0__SRCID__JPEG9_DECODE: + amdgpu_fence_process(&adev->jpeg.inst[inst].ring_dec[9]); + break; + default: + DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static void jpeg_v5_0_2_core_stall_reset(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + int jpeg_inst = GET_INST(JPEG, ring->me); + int reg_offset = ring->pipe ? jpeg_v5_0_2_core_reg_offset(ring->pipe) : 0; + + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_STALL, + reg_offset, 0x1F); + SOC15_WAIT_ON_RREG_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS, + reg_offset, 0x1F, 0x1F); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_JPEG_LMI_DROP, + reg_offset, 0x1F); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 1 << ring->pipe); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_UVD_JMI_CLIENT_STALL, + reg_offset, 0x00); + WREG32_SOC15_OFFSET(JPEG, jpeg_inst, + regUVD_JMI0_JPEG_LMI_DROP, + reg_offset, 0x00); + WREG32_SOC15(JPEG, jpeg_inst, regJPEG_CORE_RST_CTRL, 0x00); +} + +static int jpeg_v5_0_2_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + jpeg_v5_0_2_core_stall_reset(ring); + jpeg_v5_0_2_init_jrbc(ring); + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + +static const struct amd_ip_funcs jpeg_v5_0_2_ip_funcs = { + .name = "jpeg_v5_0_2", + .early_init = jpeg_v5_0_2_early_init, + .late_init = NULL, + .sw_init = jpeg_v5_0_2_sw_init, + .sw_fini = jpeg_v5_0_2_sw_fini, + .hw_init = jpeg_v5_0_2_hw_init, + .hw_fini = jpeg_v5_0_2_hw_fini, + .suspend = jpeg_v5_0_2_suspend, + .resume = jpeg_v5_0_2_resume, + .is_idle = jpeg_v5_0_2_is_idle, + .wait_for_idle = jpeg_v5_0_2_wait_for_idle, + .check_soft_reset = NULL, + .pre_soft_reset = NULL, + .soft_reset = NULL, + .post_soft_reset = NULL, + .set_clockgating_state = jpeg_v5_0_2_set_clockgating_state, + .set_powergating_state = jpeg_v5_0_2_set_powergating_state, + .dump_ip_state = amdgpu_jpeg_dump_ip_state, + .print_ip_state = amdgpu_jpeg_print_ip_state, +}; + +static const struct amdgpu_ring_funcs jpeg_v5_0_2_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_JPEG, + .align_mask = 0xf, + .get_rptr = jpeg_v5_0_2_dec_ring_get_rptr, + .get_wptr = jpeg_v5_0_2_dec_ring_get_wptr, + .set_wptr = jpeg_v5_0_2_dec_ring_set_wptr, + .emit_frame_size = + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + + 8 + /* jpeg_v5_0_2_dec_ring_emit_vm_flush */ + 22 + 22 + /* jpeg_v5_0_2_dec_ring_emit_fence x2 vm fence */ + 8 + 16, + .emit_ib_size = 22, /* jpeg_v5_0_2_dec_ring_emit_ib */ + .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, + .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, + .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, + .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, + .test_ring = amdgpu_jpeg_dec_ring_test_ring, + .test_ib = amdgpu_jpeg_dec_ring_test_ib, + .insert_nop = jpeg_v4_0_3_dec_ring_nop, + .insert_start = jpeg_v4_0_3_dec_ring_insert_start, + .insert_end = jpeg_v4_0_3_dec_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_jpeg_ring_begin_use, + .end_use = amdgpu_jpeg_ring_end_use, + .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, + .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, + .reset = jpeg_v5_0_2_ring_reset, +}; + +static void jpeg_v5_0_2_set_dec_ring_funcs(struct amdgpu_device *adev) +{ + int i, j, jpeg_inst; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + adev->jpeg.inst[i].ring_dec[j].funcs = &jpeg_v5_0_2_dec_ring_vm_funcs; + adev->jpeg.inst[i].ring_dec[j].me = i; + adev->jpeg.inst[i].ring_dec[j].pipe = j; + } + jpeg_inst = GET_INST(JPEG, i); + adev->jpeg.inst[i].aid_id = + jpeg_inst / adev->jpeg.num_inst_per_aid; + } +} + +static const struct amdgpu_irq_src_funcs jpeg_v5_0_2_irq_funcs = { + .set = jpeg_v5_0_2_set_interrupt_state, + .process = jpeg_v5_0_2_process_interrupt, +}; + +static void jpeg_v5_0_2_set_irq_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) + adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; + + adev->jpeg.inst->irq.funcs = &jpeg_v5_0_2_irq_funcs; +} + +const struct amdgpu_ip_block_version jpeg_v5_0_2_ip_block = { + .type = AMD_IP_BLOCK_TYPE_JPEG, + .major = 5, + .minor = 0, + .rev = 2, + .funcs = &jpeg_v5_0_2_ip_funcs, +}; + +#if 0 +static int jpeg_v5_0_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank, + enum aca_smu_type type, void *data) +{ + struct aca_bank_info info; + u64 misc0; + int ret; + + ret = aca_bank_info_decode(bank, &info); + if (ret) + return ret; + + misc0 = bank->regs[ACA_REG_IDX_MISC0]; + switch (type) { + case ACA_SMU_TYPE_UE: + bank->aca_err_type = ACA_ERROR_TYPE_UE; + ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE, + 1ULL); + break; + case ACA_SMU_TYPE_CE: + bank->aca_err_type = ACA_ERROR_TYPE_CE; + ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, + ACA_REG__MISC0__ERRCNT(misc0)); + break; + default: + return -EINVAL; + } + + return ret; +} + +/* reference to smu driver if header file */ +static int jpeg_v5_0_2_err_codes[] = { + 16, 17, 18, 19, 20, 21, 22, 23, /* JPEG[0-9][S|D] */ + 24, 25, 26, 27, 28, 29, 30, 31, + 48, 49, 50, 51, +}; + +static bool jpeg_v5_0_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, + enum aca_smu_type type, void *data) +{ + u32 instlo; + + instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); + instlo &= GENMASK(31, 1); + + if (instlo != mmSMNAID_AID0_MCA_SMU) + return false; + + if (aca_bank_check_error_codes(handle->adev, bank, + jpeg_v5_0_2_err_codes, + ARRAY_SIZE(jpeg_v5_0_2_err_codes))) + return false; + + return true; +} + +static const struct aca_bank_ops jpeg_v5_0_2_aca_bank_ops = { + .aca_bank_parser = jpeg_v5_0_2_aca_bank_parser, + .aca_bank_is_valid = jpeg_v5_0_2_aca_bank_is_valid, +}; + +static const struct aca_info jpeg_v5_0_2_aca_info = { + .hwip = ACA_HWIP_TYPE_SMU, + .mask = ACA_ERROR_UE_MASK, + .bank_ops = &jpeg_v5_0_2_aca_bank_ops, +}; +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h new file mode 100644 index 0000000000000..c201a2c42a0dc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h @@ -0,0 +1,111 @@ +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __JPEG_V5_0_2_H__ +#define __JPEG_V5_0_2_H__ + +extern const struct amdgpu_ip_block_version jpeg_v5_0_2_ip_block; + +#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094 +#define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe + +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640 +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649 +#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x0000 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC1_UVD_JRBC_STATUS 0x0009 +#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x000a +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0040 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0049 +#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x004a +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0080 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0089 +#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x008a +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_RB_WPTR 0x00c0 +#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_STATUS 0x00c9 +#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC4_UVD_JRBC_RB_RPTR 0x00ca +#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_RB_WPTR 0x0100 +#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_STATUS 0x0109 +#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC5_UVD_JRBC_RB_RPTR 0x010a +#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_RB_WPTR 0x0140 +#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_STATUS 0x0149 +#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC6_UVD_JRBC_RB_RPTR 0x014a +#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_RB_WPTR 0x0180 +#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_STATUS 0x0189 +#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC7_UVD_JRBC_RB_RPTR 0x018a +#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_RB_WPTR 0x01c0 +#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_STATUS 0x01c9 +#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX 0 +#define regUVD_JRBC8_UVD_JRBC_RB_RPTR 0x01ca +#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX 0 +#define regUVD_JRBC9_UVD_JRBC_RB_WPTR 0x0440 +#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC9_UVD_JRBC_STATUS 0x0449 +#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC9_UVD_JRBC_RB_RPTR 0x044a +#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JMI0_JPEG_LMI_DROP 0x0663 +#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX 1 +#define regUVD_JMI0_UVD_JMI_CLIENT_STALL 0x067a +#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX 1 +#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS 0x067b +#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 1 +#define regJPEG_CORE_RST_CTRL 0x072e +#define regJPEG_CORE_RST_CTRL_BASE_IDX 1 + +#define regVCN_RRMT_CNTL 0x0940 +#define regVCN_RRMT_CNTL_BASE_IDX 1 + +enum amdgpu_jpeg_v5_0_2_sub_block { + AMDGPU_JPEG_V5_0_2_JPEG0 = 0, + AMDGPU_JPEG_V5_0_2_JPEG1, + + AMDGPU_JPEG_V5_0_2_MAX_SUB_BLOCK, +}; + +#endif /* __JPEG_V5_0_2_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c new file mode 100644 index 0000000000000..1821dced936fb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.c @@ -0,0 +1,714 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu.h" +#include "amdgpu_jpeg.h" +#include "amdgpu_pm.h" +#include "soc15.h" +#include "soc15d.h" +#include "jpeg_v2_0.h" +#include "jpeg_v4_0_3.h" + +#include "vcn/vcn_5_3_0_offset.h" +#include "vcn/vcn_5_3_0_sh_mask.h" +#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" +#include "jpeg_v5_3_0.h" + +static void jpeg_v5_3_0_set_dec_ring_funcs(struct amdgpu_device *adev); +static void jpeg_v5_3_0_set_irq_funcs(struct amdgpu_device *adev); +static int jpeg_v5_3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state); + + +/** + * jpeg_v5_3_0_early_init - set function pointers + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Set ring and irq function pointers + */ +static int jpeg_v5_3_0_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + adev->jpeg.num_jpeg_inst = 1; + adev->jpeg.num_jpeg_rings = 1; + + jpeg_v5_3_0_set_dec_ring_funcs(adev); + jpeg_v5_3_0_set_irq_funcs(adev); + + return 0; +} + +/** + * jpeg_v5_3_0_sw_init - sw init for JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Load firmware and sw initialization + */ +static int jpeg_v5_3_0_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int r; + + /* JPEG TRAP */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, + VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); + if (r) + return r; + + r = amdgpu_jpeg_sw_init(adev); + if (r) + return r; + + r = amdgpu_jpeg_resume(adev); + if (r) + return r; + + ring = adev->jpeg.inst->ring_dec; + ring->use_doorbell = true; + ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1; + ring->vm_hub = AMDGPU_MMHUB0(0); + + sprintf(ring->name, "jpeg_dec"); + r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, + AMDGPU_RING_PRIO_DEFAULT, NULL); + if (r) + return r; + + adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET; + adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); + + /* TODO: Add queue reset mask when FW fully supports it */ + adev->jpeg.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]); + if (!amdgpu_sriov_vf(adev)) + adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + r = amdgpu_jpeg_sysfs_reset_mask_init(adev); + if (r) + return r; + return 0; +} + +/** + * jpeg_v5_3_0_sw_fini - sw fini for JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * JPEG suspend and free up sw allocation + */ +static int jpeg_v5_3_0_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_jpeg_suspend(adev); + if (r) + return r; + + amdgpu_jpeg_sysfs_reset_mask_fini(adev); + r = amdgpu_jpeg_sw_fini(adev); + + return r; +} + +/** + * jpeg_v5_3_0_hw_init - start and test JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + */ +static int jpeg_v5_3_0_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; + int r; + + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0); + + /* Skip ring test because pause DPG is not implemented. */ + if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) + return 0; + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + + return 0; +} + +/** + * jpeg_v5_3_0_hw_fini - stop the hardware block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Stop the JPEG block, mark ring as not ready any more + */ +static int jpeg_v5_3_0_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + cancel_delayed_work_sync(&adev->jpeg.idle_work); + + if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && + RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS)) + jpeg_v5_3_0_set_powergating_state(ip_block, AMD_PG_STATE_GATE); + + return 0; +} + +/** + * jpeg_v5_3_0_suspend - suspend JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * HW fini and suspend JPEG block + */ +static int jpeg_v5_3_0_suspend(struct amdgpu_ip_block *ip_block) +{ + int r; + + r = jpeg_v5_3_0_hw_fini(ip_block); + if (r) + return r; + + r = amdgpu_jpeg_suspend(ip_block->adev); + + return r; +} + +/** + * jpeg_v5_3_0_resume - resume JPEG block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Resume firmware and hw init JPEG block + */ +static int jpeg_v5_3_0_resume(struct amdgpu_ip_block *ip_block) +{ + int r; + + r = amdgpu_jpeg_resume(ip_block->adev); + if (r) + return r; + + r = jpeg_v5_3_0_hw_init(ip_block); + + return r; +} + +static void jpeg_v5_3_0_disable_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data = 0; + + WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); + + data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); + data &= ~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK + | JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK); + WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); +} + +static void jpeg_v5_3_0_enable_clock_gating(struct amdgpu_device *adev) +{ + uint32_t data = 0; + + data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL); + + data |= 1 << JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT; + WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data); + + data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE); + data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK + |JPEG_CGC_GATE__JPEG_ENC_MASK + |JPEG_CGC_GATE__JMCIF_MASK + |JPEG_CGC_GATE__JRBBM_MASK); + WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data); +} + +static int jpeg_v5_3_0_disable_power_gating(struct amdgpu_device *adev) +{ + uint32_t data = 0; + + data = 1 << UVD_IPX_DLDO_CONFIG_ONO1__ONO1_PWR_CONFIG__SHIFT; + WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG_ONO1, data); + SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, + UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); + + /* disable anti hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0, + ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); + + return 0; +} + +static int jpeg_v5_3_0_enable_power_gating(struct amdgpu_device *adev) +{ + /* enable anti hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), + UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK, + ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK); + + if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) { + WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG_ONO1), + 2 << UVD_IPX_DLDO_CONFIG_ONO1__ONO1_PWR_CONFIG__SHIFT); + SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, + 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT, + UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK); + } + + return 0; +} + +static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev, + int inst_idx, uint8_t indirect) +{ + uint32_t data = 0; + + // JPEG disable CGC + if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG) + data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + else + data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; + + data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; + data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; + + if (indirect) { + ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); + + // Turn on All JPEG clocks + data = 0; + ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); + } else { + WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); + + // Turn on All JPEG clocks + data = 0; + WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); + } +} + +/** + * jpeg_v5_3_0_start_dpg_mode - Jpeg start with dpg mode + * + * @adev: amdgpu_device pointer + * @inst_idx: instance number index + * @indirect: indirectly write sram + * + * Start JPEG block with dpg mode + */ +static int jpeg_v5_3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) +{ + struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; + uint32_t reg_data = 0; + + jpeg_v5_3_0_enable_power_gating(adev); + + // enable dynamic power gating mode + reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); + reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK; + WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); + + if (indirect) + adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = + (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; + + jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); + + /* MJPEG global tiling registers */ + if (indirect) + ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, indirect); + else + WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config, 1); + + /* enable System Interrupt for JRBC */ + if (indirect) + ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN, + JPEG_SYS_INT_EN__DJRBC0_MASK, indirect); + else + WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN, + JPEG_SYS_INT_EN__DJRBC0_MASK, 1); + + if (indirect) { + /* add nop to workaround PSP size check */ + ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect); + + amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); + } + + WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, + ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + + WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); + WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); + WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_RPTR, 0); + WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 0); + WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_CNTL, 0x00000002L); + WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_SIZE, ring->ring_size / 4); + ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC0_UVD_JRBC_RB_WPTR); + + return 0; +} + +/** + * jpeg_v5_3_0_stop_dpg_mode - Jpeg stop with dpg mode + * + * @adev: amdgpu_device pointer + * @inst_idx: instance number index + * + * Stop JPEG block with dpg mode + */ +static void jpeg_v5_3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) +{ + uint32_t reg_data = 0; + + reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS); + reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK; + WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data); +} + +/** + * jpeg_v5_3_0_start - start JPEG block + * + * @adev: amdgpu_device pointer + * + * Setup and start the JPEG block + */ +static int jpeg_v5_3_0_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; + int r; + + if (adev->pm.dpm_enabled) + amdgpu_dpm_enable_jpeg(adev, true); + + if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { + r = jpeg_v5_3_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram); + return r; + } + + /* disable power gating */ + r = jpeg_v5_3_0_disable_power_gating(adev); + if (r) + return r; + + /* JPEG disable CGC */ + jpeg_v5_3_0_disable_clock_gating(adev); + + /* MJPEG global tiling registers */ + WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + + /* enable JMI channel */ + WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0, + ~UVD_JMI_CNTL__SOFT_RESET_MASK); + + /* enable System Interrupt for JRBC */ + WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN), + JPEG_SYS_INT_EN__DJRBC0_MASK, + ~JPEG_SYS_INT_EN__DJRBC0_MASK); + + WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, + ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + + WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0); + WREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); + WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, + lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, + upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR, 0); + WREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR, 0); + WREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_CNTL, 0x00000002L); + WREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_SIZE, ring->ring_size / 4); + ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR); + + return 0; +} + +/** + * jpeg_v5_3_0_stop - stop JPEG block + * + * @adev: amdgpu_device pointer + * + * stop the JPEG block + */ +static int jpeg_v5_3_0_stop(struct amdgpu_device *adev) +{ + int r; + + if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) { + jpeg_v5_3_0_stop_dpg_mode(adev, 0); + } else { + + /* reset JMI */ + WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), + UVD_JMI_CNTL__SOFT_RESET_MASK, + ~UVD_JMI_CNTL__SOFT_RESET_MASK); + + jpeg_v5_3_0_enable_clock_gating(adev); + + /* enable power gating */ + r = jpeg_v5_3_0_enable_power_gating(adev); + if (r) + return r; + } + + if (adev->pm.dpm_enabled) + amdgpu_dpm_enable_jpeg(adev, false); + + return 0; +} + +/** + * jpeg_v5_3_0_dec_ring_get_rptr - get read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware read pointer + */ +static uint64_t jpeg_v5_3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + return RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_RPTR); +} + +/** + * jpeg_v5_3_0_dec_ring_get_wptr - get write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware write pointer + */ +static uint64_t jpeg_v5_3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) + return *ring->wptr_cpu_addr; + else + return RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR); +} + +/** + * jpeg_v5_3_0_dec_ring_set_wptr - set write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the write pointer to the hardware + */ +static void jpeg_v5_3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); + } else { + WREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); + } +} + +static bool jpeg_v5_3_0_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret = 1; + + ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS) & + UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK) == + UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK)); + + return ret; +} + +static int jpeg_v5_3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC0_UVD_JRBC_STATUS, + UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK, + UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK); +} + +static int jpeg_v5_3_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + bool enable = (state == AMD_CG_STATE_GATE) ? true : false; + + if (enable) { + if (!jpeg_v5_3_0_is_idle(ip_block)) + return -EBUSY; + jpeg_v5_3_0_enable_clock_gating(adev); + } else { + jpeg_v5_3_0_disable_clock_gating(adev); + } + + return 0; +} + +static int jpeg_v5_3_0_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + int ret; + + if (state == adev->jpeg.cur_state) + return 0; + + if (state == AMD_PG_STATE_GATE) + ret = jpeg_v5_3_0_stop(adev); + else + ret = jpeg_v5_3_0_start(adev); + + if (!ret) + adev->jpeg.cur_state = state; + + return ret; +} + +static int jpeg_v5_3_0_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + return 0; +} + +static int jpeg_v5_3_0_process_interrupt(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + DRM_DEBUG("IH: JPEG TRAP\n"); + + switch (entry->src_id) { + case VCN_5_0__SRCID__JPEG_DECODE: + amdgpu_fence_process(adev->jpeg.inst->ring_dec); + break; + default: + DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static int jpeg_v5_3_0_ring_reset(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + int r; + + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + r = jpeg_v5_3_0_stop(ring->adev); + if (r) + return r; + r = jpeg_v5_3_0_start(ring->adev); + if (r) + return r; + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + +static const struct amd_ip_funcs jpeg_v5_3_0_ip_funcs = { + .name = "jpeg_v5_3_0", + .early_init = jpeg_v5_3_0_early_init, + .sw_init = jpeg_v5_3_0_sw_init, + .sw_fini = jpeg_v5_3_0_sw_fini, + .hw_init = jpeg_v5_3_0_hw_init, + .hw_fini = jpeg_v5_3_0_hw_fini, + .suspend = jpeg_v5_3_0_suspend, + .resume = jpeg_v5_3_0_resume, + .is_idle = jpeg_v5_3_0_is_idle, + .wait_for_idle = jpeg_v5_3_0_wait_for_idle, + .set_clockgating_state = jpeg_v5_3_0_set_clockgating_state, + .set_powergating_state = jpeg_v5_3_0_set_powergating_state, +}; + +static const struct amdgpu_ring_funcs jpeg_v5_3_0_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_JPEG, + .align_mask = 0xf, + .get_rptr = jpeg_v5_3_0_dec_ring_get_rptr, + .get_wptr = jpeg_v5_3_0_dec_ring_get_wptr, + .set_wptr = jpeg_v5_3_0_dec_ring_set_wptr, + .parse_cs = amdgpu_jpeg_dec_parse_cs, + .emit_frame_size = + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + + 8 + /* jpeg_v5_3_0_dec_ring_emit_vm_flush */ + 22 + 22 + /* jpeg_v5_3_0_dec_ring_emit_fence x2 vm fence */ + 8 + 16, + .emit_ib_size = 22, /* jpeg_v5_3_0_dec_ring_emit_ib */ + .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, + .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, + .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, + .test_ring = amdgpu_jpeg_dec_ring_test_ring, + .test_ib = amdgpu_jpeg_dec_ring_test_ib, + .insert_nop = jpeg_v4_0_3_dec_ring_nop, + .insert_start = jpeg_v4_0_3_dec_ring_insert_start, + .insert_end = jpeg_v4_0_3_dec_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_jpeg_ring_begin_use, + .end_use = amdgpu_jpeg_ring_end_use, + .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg, + .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, + .reset = jpeg_v5_3_0_ring_reset, +}; + +static void jpeg_v5_3_0_set_dec_ring_funcs(struct amdgpu_device *adev) +{ + adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_3_0_dec_ring_vm_funcs; +} + +static const struct amdgpu_irq_src_funcs jpeg_v5_3_0_irq_funcs = { + .set = jpeg_v5_3_0_set_interrupt_state, + .process = jpeg_v5_3_0_process_interrupt, +}; + +static void jpeg_v5_3_0_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->jpeg.inst->irq.num_types = 1; + adev->jpeg.inst->irq.funcs = &jpeg_v5_3_0_irq_funcs; +} + +const struct amdgpu_ip_block_version jpeg_v5_3_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_JPEG, + .major = 5, + .minor = 3, + .rev = 0, + .funcs = &jpeg_v5_3_0_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h new file mode 100644 index 0000000000000..c1e7537d0f183 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_3_0.h @@ -0,0 +1,35 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __JPEG_V5_3_0_H__ +#define __JPEG_V5_3_0_H__ + +#define vcnipJPEG_CGC_GATE 0x4160 +#define vcnipJPEG_CGC_CTRL 0x4161 +#define vcnipJPEG_SYS_INT_EN 0x4141 +#define vcnipUVD_NO_OP 0x0029 +#define vcnipJPEG_DEC_GFX10_ADDR_CONFIG 0x404A + +extern const struct amdgpu_ip_block_version jpeg_v5_3_0_ip_block; + +#endif /* __JPEG_V5_0_0_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c new file mode 100644 index 0000000000000..d93a0e65ce7de --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.c @@ -0,0 +1,99 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "lsdma_v7_1.h" +#include "amdgpu_lsdma.h" + +#include "lsdma/lsdma_7_1_0_offset.h" +#include "lsdma/lsdma_7_1_0_sh_mask.h" + +static int lsdma_v7_1_wait_pio_status(struct amdgpu_device *adev) +{ + return amdgpu_lsdma_wait_for(adev, SOC15_REG_OFFSET(LSDMA, 0, regLSDMA_PIO_STATUS), + LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK, + LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK); +} + +static int lsdma_v7_1_copy_mem(struct amdgpu_device *adev, + uint64_t src_addr, + uint64_t dst_addr, + uint64_t size) +{ + int ret; + uint32_t tmp; + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr)); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); + + tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, COUNT, size); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, RAW_WAIT, 0); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); + + ret = lsdma_v7_1_wait_pio_status(adev); + if (ret) + dev_err(adev->dev, "LSDMA PIO failed to copy memory!\n"); + + return ret; +} + +static int lsdma_v7_1_fill_mem(struct amdgpu_device *adev, + uint64_t dst_addr, + uint32_t data, + uint64_t size) +{ + int ret; + uint32_t tmp; + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); + + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); + + tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, COUNT, size); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, RAW_WAIT, 0); + tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1); + WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); + + ret = lsdma_v7_1_wait_pio_status(adev); + if (ret) + dev_err(adev->dev, "LSDMA PIO failed to fill memory!\n"); + + return ret; +} + +const struct amdgpu_lsdma_funcs lsdma_v7_1_funcs = { + .copy_mem = lsdma_v7_1_copy_mem, + .fill_mem = lsdma_v7_1_fill_mem, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h new file mode 100644 index 0000000000000..3d1ab605849a0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/lsdma_v7_1.h @@ -0,0 +1,31 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __LSDMA_V7_1_H__ +#define __LSDMA_V7_1_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_lsdma_funcs lsdma_v7_1_funcs; + +#endif /* __LSDMA_V7_1_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c index 64cae89357b65..527cf2f14691d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c @@ -59,7 +59,8 @@ mes_userq_map_gtt_bo_to_gart(struct amdgpu_bo *bo) } static int -mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, +mes_userq_create_wptr_mapping(struct amdgpu_device *adev, + struct amdgpu_userq_mgr *uq_mgr, struct amdgpu_usermode_queue *queue, uint64_t wptr) { @@ -93,8 +94,28 @@ mes_userq_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, return ret; } - queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj); + ret = amdgpu_bo_reserve(wptr_obj->obj, true); + if (ret) { + DRM_ERROR("Failed to reserve wptr bo\n"); + return ret; + } + + /* TODO use eviction fence instead of pinning. */ + ret = amdgpu_bo_pin(wptr_obj->obj, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + drm_file_err(uq_mgr->file, "[Usermode queues] Failed to pin wptr bo\n"); + goto unresv_bo; + } + + queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset(wptr_obj->obj); + amdgpu_bo_unreserve(wptr_obj->obj); + return 0; + +unresv_bo: + amdgpu_bo_unreserve(wptr_obj->obj); + return ret; + } static int convert_to_mes_priority(int priority) @@ -112,9 +133,9 @@ static int convert_to_mes_priority(int priority) } } -static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_map(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_userq_obj *ctx = &queue->fw_obj; struct amdgpu_mqd_prop *userq_props = queue->userq_prop; @@ -157,9 +178,9 @@ static int mes_userq_map(struct amdgpu_userq_mgr *uq_mgr, return 0; } -static int mes_userq_unmap(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct mes_remove_queue_input queue_input; struct amdgpu_userq_obj *ctx = &queue->fw_obj; @@ -223,7 +244,7 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, amdgpu_mes_lock(&adev->mes); r = amdgpu_mes_detect_and_reset_hung_queues(adev, queue_type, false, - &hung_db_num, db_array); + &hung_db_num, db_array, 0); amdgpu_mes_unlock(&adev->mes); if (r) { dev_err(adev->dev, "Failed to detect and reset queues, err (%d)\n", r); @@ -251,10 +272,10 @@ static int mes_userq_detect_and_reset(struct amdgpu_device *adev, return r; } -static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, - struct drm_amdgpu_userq_in *args_in, - struct amdgpu_usermode_queue *queue) +static int mes_userq_mqd_create(struct amdgpu_usermode_queue *queue, + struct drm_amdgpu_userq_in *args_in) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct amdgpu_mqd *mqd_hw_default = &adev->mqds[queue->queue_type]; struct drm_amdgpu_userq_in *mqd_user = args_in; @@ -268,7 +289,8 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, return -ENOMEM; } - r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, mqd_hw_default->mqd_size); + r = amdgpu_userq_create_object(uq_mgr, &queue->mqd, + AMDGPU_MQD_SIZE_ALIGN(mqd_hw_default->mqd_size)); if (r) { DRM_ERROR("Failed to create MQD object for userqueue\n"); goto free_props; @@ -300,10 +322,12 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, goto free_mqd; } - r = amdgpu_userq_input_va_validate(queue, compute_mqd->eop_va, + r = amdgpu_userq_input_va_validate(adev, queue, compute_mqd->eop_va, 2048); - if (r) + if (r) { + kfree(compute_mqd); goto free_mqd; + } userq_props->eop_gpu_addr = compute_mqd->eop_va; userq_props->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_NORMAL; @@ -341,14 +365,18 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, userq_props->tmz_queue = mqd_user->flags & AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE; - r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->shadow_va, + r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->shadow_va, shadow_info.shadow_size); - if (r) + if (r) { + kfree(mqd_gfx_v11); goto free_mqd; - r = amdgpu_userq_input_va_validate(queue, mqd_gfx_v11->csa_va, + } + r = amdgpu_userq_input_va_validate(adev, queue, mqd_gfx_v11->csa_va, shadow_info.csa_size); - if (r) + if (r) { + kfree(mqd_gfx_v11); goto free_mqd; + } kfree(mqd_gfx_v11); } else if (queue->queue_type == AMDGPU_HW_IP_DMA) { @@ -366,10 +394,12 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, r = -ENOMEM; goto free_mqd; } - r = amdgpu_userq_input_va_validate(queue, mqd_sdma_v11->csa_va, + r = amdgpu_userq_input_va_validate(adev, queue, mqd_sdma_v11->csa_va, 32); - if (r) + if (r) { + kfree(mqd_sdma_v11); goto free_mqd; + } userq_props->csa_addr = mqd_sdma_v11->csa_va; kfree(mqd_sdma_v11); @@ -391,7 +421,7 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, } /* FW expects WPTR BOs to be mapped into GART */ - r = mes_userq_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr); + r = mes_userq_create_wptr_mapping(adev, uq_mgr, queue, userq_props->wptr_gpu_addr); if (r) { DRM_ERROR("Failed to create WPTR mapping\n"); goto free_ctx; @@ -411,18 +441,18 @@ static int mes_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, return r; } -static void -mes_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static void mes_userq_mqd_destroy(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; + amdgpu_userq_destroy_object(uq_mgr, &queue->fw_obj); kfree(queue->userq_prop); amdgpu_userq_destroy_object(uq_mgr, &queue->mqd); } -static int mes_userq_preempt(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_preempt(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct mes_suspend_gang_input queue_input; struct amdgpu_userq_obj *ctx = &queue->fw_obj; @@ -466,9 +496,9 @@ static int mes_userq_preempt(struct amdgpu_userq_mgr *uq_mgr, return r; } -static int mes_userq_restore(struct amdgpu_userq_mgr *uq_mgr, - struct amdgpu_usermode_queue *queue) +static int mes_userq_restore(struct amdgpu_usermode_queue *queue) { + struct amdgpu_userq_mgr *uq_mgr = queue->userq_mgr; struct amdgpu_device *adev = uq_mgr->adev; struct mes_resume_gang_input queue_input; struct amdgpu_userq_obj *ctx = &queue->fw_obj; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index ceddc953785fe..a926a330700e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -56,11 +56,13 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes_2.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_3_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes_2.bin"); +MODULE_FIRMWARE("amdgpu/gc_11_5_4_mes1.bin"); static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); -static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); -static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); +static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); +static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); #define MES_EOP_SIZE 2048 #define GFX_MES_DRAM_SIZE 0x80000 @@ -660,7 +662,7 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes, break; default: - DRM_ERROR("unsupported misc op (%d) \n", input->op); + drm_err(adev_to_drm(mes->adev), "unsupported misc op (%d)\n", input->op); return -EINVAL; } @@ -718,11 +720,6 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; mes_set_hw_res_pkt.oversubscription_timer = 50; - if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x7f) - mes_set_hw_res_pkt.enable_lr_compute_wa = 1; - else - dev_info_once(mes->adev->dev, - "MES FW version must be >= 0x7f to enable LR compute workaround.\n"); if (amdgpu_mes_log_enable) { mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; @@ -811,7 +808,7 @@ static int mes_v11_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, mes_reset_queue_pkt.queue_type = convert_to_mes_queue_type(input->queue_type); mes_reset_queue_pkt.doorbell_offset_addr = - mes->hung_queue_db_array_gpu_addr; + mes->hung_queue_db_array_gpu_addr[0]; if (input->detect_only) mes_reset_queue_pkt.hang_detect_only = 1; @@ -1570,7 +1567,7 @@ static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); } -static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) +static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) { int r = 0; struct amdgpu_ip_block *ip_block; @@ -1625,7 +1622,7 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) return r; } -static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) +static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) { if (adev->mes.ring[0].sched.ready) { mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 744e95d3984ad..023c7345ea548 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -42,8 +42,8 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); -static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); -static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); +static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); +static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); #define MES_EOP_SIZE 2048 @@ -699,7 +699,7 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, break; default: - DRM_ERROR("unsupported misc op (%d) \n", input->op); + DRM_ERROR("unsupported misc op (%d)\n", input->op); return -EINVAL; } @@ -731,6 +731,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) int i; struct amdgpu_device *adev = mes->adev; union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; + uint32_t mes_rev = (pipe == AMDGPU_MES_SCHED_PIPE) ? + (mes->sched_version & AMDGPU_MES_VERSION_MASK) : + (mes->kiq_version & AMDGPU_MES_VERSION_MASK); memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); @@ -779,18 +782,13 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.enable_reg_active_poll = 1; mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; - if ((mes->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x82) - mes_set_hw_res_pkt.enable_lr_compute_wa = 1; - else - dev_info_once(adev->dev, - "MES FW version must be >= 0x82 to enable LR compute workaround.\n"); /* * Keep oversubscribe timer for sdma . When we have unmapped doorbell * handling support, other queue will not use the oversubscribe timer. * handling mode - 0: disabled; 1: basic version; 2: basic+ version */ - mes_set_hw_res_pkt.oversubscription_timer = 50; + mes_set_hw_res_pkt.oversubscription_timer = mes_rev < 0x8b ? 0 : 50; mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; if (amdgpu_mes_log_enable) { @@ -939,7 +937,7 @@ static int mes_v12_0_detect_and_reset_hung_queues(struct amdgpu_mes *mes, mes_reset_queue_pkt.queue_type = convert_to_mes_queue_type(input->queue_type); mes_reset_queue_pkt.doorbell_offset_addr = - mes->hung_queue_db_array_gpu_addr; + mes->hung_queue_db_array_gpu_addr[0]; if (input->detect_only) mes_reset_queue_pkt.hang_detect_only = 1; @@ -1489,7 +1487,7 @@ static int mes_v12_0_queue_init(struct amdgpu_device *adev, if (pipe == AMDGPU_MES_SCHED_PIPE) { if (adev->enable_uni_mes) - r = amdgpu_mes_map_legacy_queue(adev, ring); + r = amdgpu_mes_map_legacy_queue(adev, ring, 0); else r = mes_v12_0_kiq_enable_queue(adev); if (r) @@ -1739,7 +1737,7 @@ static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); } -static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) +static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) { int r = 0; struct amdgpu_ip_block *ip_block; @@ -1801,13 +1799,13 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) return r; } -static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) +static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) { if (adev->mes.ring[0].sched.ready) { if (adev->enable_uni_mes) amdgpu_mes_unmap_legacy_queue(adev, &adev->mes.ring[AMDGPU_MES_SCHED_PIPE], - RESET_QUEUES, 0, 0); + RESET_QUEUES, 0, 0, 0); else mes_v12_0_kiq_dequeue_sched(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c new file mode 100644 index 0000000000000..0e90895447691 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -0,0 +1,2282 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include "amdgpu.h" +#include "soc15_common.h" +#include "soc_v1_0.h" +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "gc/gc_11_0_0_default.h" +#include "v12_structs.h" +#include "mes_v12_api_def.h" +#include "gfx_v12_1_pkt.h" +#include "sdma_v7_1_0_pkt_open.h" + +MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_1_0_mes1.bin"); +MODULE_FIRMWARE("amdgpu/gc_12_1_0_uni_mes.bin"); + +static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block); +static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id); +static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block); +static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id); +static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id); +static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id); + +#define MES_EOP_SIZE 2048 + +#define regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT 0x100000 +#define XCC_MID_MASK 0x41000000 + +static void mes_v12_1_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring->use_doorbell) { + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, + ring->wptr); + WDOORBELL64(ring->doorbell_index, ring->wptr); + } else { + BUG(); + } +} + +static u64 mes_v12_1_ring_get_rptr(struct amdgpu_ring *ring) +{ + return *ring->rptr_cpu_addr; +} + +static u64 mes_v12_1_ring_get_wptr(struct amdgpu_ring *ring) +{ + u64 wptr; + + if (ring->use_doorbell) + wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); + else + BUG(); + return wptr; +} + +static const struct amdgpu_ring_funcs mes_v12_1_ring_funcs = { + .type = AMDGPU_RING_TYPE_MES, + .align_mask = 1, + .nop = 0, + .support_64bit_ptrs = true, + .get_rptr = mes_v12_1_ring_get_rptr, + .get_wptr = mes_v12_1_ring_get_wptr, + .set_wptr = mes_v12_1_ring_set_wptr, + .insert_nop = amdgpu_ring_insert_nop, +}; + +static const char *mes_v12_1_opcodes[] = { + "SET_HW_RSRC", + "SET_SCHEDULING_CONFIG", + "ADD_QUEUE", + "REMOVE_QUEUE", + "PERFORM_YIELD", + "SET_GANG_PRIORITY_LEVEL", + "SUSPEND", + "RESUME", + "RESET", + "SET_LOG_BUFFER", + "CHANGE_GANG_PRORITY", + "QUERY_SCHEDULER_STATUS", + "unused", + "SET_DEBUG_VMID", + "MISC", + "UPDATE_ROOT_PAGE_TABLE", + "AMD_LOG", + "SET_SE_MODE", + "SET_GANG_SUBMIT", + "SET_HW_RSRC_1", + "INVALIDATE_TLBS", +}; + +static const char *mes_v12_1_misc_opcodes[] = { + "WRITE_REG", + "INV_GART", + "QUERY_STATUS", + "READ_REG", + "WAIT_REG_MEM", + "SET_SHADER_DEBUGGER", + "NOTIFY_WORK_ON_UNMAPPED_QUEUE", + "NOTIFY_TO_UNMAP_PROCESSES", +}; + +static const char *mes_v12_1_get_op_string(union MESAPI__MISC *x_pkt) +{ + const char *op_str = NULL; + + if (x_pkt->header.opcode < ARRAY_SIZE(mes_v12_1_opcodes)) + op_str = mes_v12_1_opcodes[x_pkt->header.opcode]; + + return op_str; +} + +static const char *mes_v12_1_get_misc_op_string(union MESAPI__MISC *x_pkt) +{ + const char *op_str = NULL; + + if ((x_pkt->header.opcode == MES_SCH_API_MISC) && + (x_pkt->opcode < ARRAY_SIZE(mes_v12_1_misc_opcodes))) + op_str = mes_v12_1_misc_opcodes[x_pkt->opcode]; + + return op_str; +} + +static int mes_v12_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, + int xcc_id, int pipe, void *pkt, + int size, int api_status_off) +{ + union MESAPI__QUERY_MES_STATUS mes_status_pkt; + signed long timeout = 2100000; /* 2100 ms */ + struct amdgpu_device *adev = mes->adev; + struct amdgpu_ring *ring = &mes->ring[MES_PIPE_INST(xcc_id, pipe)]; + spinlock_t *ring_lock = &mes->ring_lock[MES_PIPE_INST(xcc_id, pipe)]; + struct MES_API_STATUS *api_status; + union MESAPI__MISC *x_pkt = pkt; + const char *op_str, *misc_op_str; + unsigned long flags; + u64 status_gpu_addr; + u32 seq, status_offset; + u64 *status_ptr; + signed long r; + int ret; + + if (x_pkt->header.opcode >= MES_SCH_API_MAX) + return -EINVAL; + + if (amdgpu_emu_mode) { + timeout *= 1000; + } else if (amdgpu_sriov_vf(adev)) { + /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ + timeout = 15 * 600 * 1000; + } + + ret = amdgpu_device_wb_get(adev, &status_offset); + if (ret) + return ret; + + status_gpu_addr = adev->wb.gpu_addr + (status_offset * 4); + status_ptr = (u64 *)&adev->wb.wb[status_offset]; + *status_ptr = 0; + + spin_lock_irqsave(ring_lock, flags); + r = amdgpu_ring_alloc(ring, (size + sizeof(mes_status_pkt)) / 4); + if (r) + goto error_unlock_free; + + seq = ++ring->fence_drv.sync_seq; + r = amdgpu_fence_wait_polling(ring, + seq - ring->fence_drv.num_fences_mask, + timeout); + if (r < 1) + goto error_undo; + + api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); + api_status->api_completion_fence_addr = status_gpu_addr; + api_status->api_completion_fence_value = 1; + + amdgpu_ring_write_multiple(ring, pkt, size / 4); + + memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); + mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; + mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + mes_status_pkt.api_status.api_completion_fence_addr = + ring->fence_drv.gpu_addr; + mes_status_pkt.api_status.api_completion_fence_value = seq; + + amdgpu_ring_write_multiple(ring, &mes_status_pkt, + sizeof(mes_status_pkt) / 4); + + amdgpu_ring_commit(ring); + spin_unlock_irqrestore(ring_lock, flags); + + op_str = mes_v12_1_get_op_string(x_pkt); + misc_op_str = mes_v12_1_get_misc_op_string(x_pkt); + + if (misc_op_str) + dev_dbg(adev->dev, "MES(%d, %d) msg=%s (%s) was emitted\n", + xcc_id, pipe, op_str, misc_op_str); + else if (op_str) + dev_dbg(adev->dev, "MES(%d, %d) msg=%s was emitted\n", + xcc_id, pipe, op_str); + else + dev_dbg(adev->dev, "MES(%d, %d) msg=%d was emitted\n", + xcc_id, pipe, x_pkt->header.opcode); + + r = amdgpu_fence_wait_polling(ring, seq, timeout); + if (r < 1 || !*status_ptr) { + if (misc_op_str) + dev_err(adev->dev, + "MES(%d, %d) failed to respond to msg=%s (%s)\n", + xcc_id, pipe, op_str, misc_op_str); + else if (op_str) + dev_err(adev->dev, + "MES(%d, %d) failed to respond to msg=%s\n", + xcc_id, pipe, op_str); + else + dev_err(adev->dev, + "MES(%d, %d) failed to respond to msg=%d\n", + xcc_id, pipe, x_pkt->header.opcode); + + while (halt_if_hws_hang) + schedule(); + + r = -ETIMEDOUT; + goto error_wb_free; + } + + amdgpu_device_wb_free(adev, status_offset); + return 0; + +error_undo: + dev_err(adev->dev, "MES(%d, %d) ring buffer is full.\n", xcc_id, pipe); + amdgpu_ring_undo(ring); + +error_unlock_free: + spin_unlock_irqrestore(ring_lock, flags); + +error_wb_free: + amdgpu_device_wb_free(adev, status_offset); + return r; +} + +static int convert_to_mes_queue_type(int queue_type) +{ + if (queue_type == AMDGPU_RING_TYPE_GFX) + return MES_QUEUE_TYPE_GFX; + else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) + return MES_QUEUE_TYPE_COMPUTE; + else if (queue_type == AMDGPU_RING_TYPE_SDMA) + return MES_QUEUE_TYPE_SDMA; + else if (queue_type == AMDGPU_RING_TYPE_MES) + return MES_QUEUE_TYPE_SCHQ; + else + BUG(); + return -1; +} + +static int mes_v12_1_add_hw_queue(struct amdgpu_mes *mes, + struct mes_add_queue_input *input) +{ + union MESAPI__ADD_QUEUE mes_add_queue_pkt; + int xcc_id = input->xcc_id; + int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); + + if (mes->enable_coop_mode) + xcc_id = mes->master_xcc_ids[inst]; + + memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); + + mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; + mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_add_queue_pkt.process_id = input->process_id; + mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; + mes_add_queue_pkt.process_va_start = input->process_va_start; + mes_add_queue_pkt.process_va_end = input->process_va_end; + mes_add_queue_pkt.process_quantum = input->process_quantum; + mes_add_queue_pkt.process_context_addr = input->process_context_addr; + mes_add_queue_pkt.gang_quantum = input->gang_quantum; + mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; + mes_add_queue_pkt.inprocess_gang_priority = + input->inprocess_gang_priority; + mes_add_queue_pkt.gang_global_priority_level = + input->gang_global_priority_level; + mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; + mes_add_queue_pkt.mqd_addr = input->mqd_addr; + + mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; + + mes_add_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + mes_add_queue_pkt.paging = input->paging; + mes_add_queue_pkt.vm_context_cntl = input->vm_cntx_cntl; + mes_add_queue_pkt.gws_base = input->gws_base; + mes_add_queue_pkt.gws_size = input->gws_size; + mes_add_queue_pkt.trap_handler_addr = input->tba_addr; + mes_add_queue_pkt.tma_addr = input->tma_addr; + mes_add_queue_pkt.trap_en = input->trap_en; + mes_add_queue_pkt.skip_process_ctx_clear = input->skip_process_ctx_clear; + mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; + + /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ + mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; + mes_add_queue_pkt.gds_size = input->queue_size; + + /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ + mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; + mes_add_queue_pkt.gds_size = input->queue_size; + + mes_add_queue_pkt.full_sh_mem_config_data = input->sh_mem_config_data; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), + offsetof(union MESAPI__ADD_QUEUE, api_status)); +} + +static int mes_v12_1_remove_hw_queue(struct amdgpu_mes *mes, + struct mes_remove_queue_input *input) +{ + union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; + int xcc_id = input->xcc_id; + int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); + + if (mes->enable_coop_mode) + xcc_id = mes->master_xcc_ids[inst]; + + memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); + + mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; + mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; + mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + xcc_id, AMDGPU_MES_SCHED_PIPE, + &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), + offsetof(union MESAPI__REMOVE_QUEUE, api_status)); +} + +static int mes_v12_1_reset_hw_queue(struct amdgpu_mes *mes, + struct mes_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + int pipe; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; + /* mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; */ + /*mes_reset_queue_pkt.reset_queue_only = 1;*/ + + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, pipe, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__REMOVE_QUEUE, api_status)); +} + +static int mes_v12_1_map_legacy_queue(struct amdgpu_mes *mes, + struct mes_map_legacy_queue_input *input) +{ + union MESAPI__ADD_QUEUE mes_add_queue_pkt; + int pipe; + + memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); + + mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; + mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_add_queue_pkt.pipe_id = input->pipe_id; + mes_add_queue_pkt.queue_id = input->queue_id; + mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; + mes_add_queue_pkt.mqd_addr = input->mqd_addr; + mes_add_queue_pkt.wptr_addr = input->wptr_addr; + mes_add_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + mes_add_queue_pkt.map_legacy_kq = 1; + + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, pipe, + &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), + offsetof(union MESAPI__ADD_QUEUE, api_status)); +} + +static int mes_v12_1_unmap_legacy_queue(struct amdgpu_mes *mes, + struct mes_unmap_legacy_queue_input *input) +{ + union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; + int pipe; + + memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); + + mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; + mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; + mes_remove_queue_pkt.gang_context_addr = 0; + + mes_remove_queue_pkt.pipe_id = input->pipe_id; + mes_remove_queue_pkt.queue_id = input->queue_id; + + if (input->action == PREEMPT_QUEUES_NO_UNMAP) { + mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; + mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; + mes_remove_queue_pkt.tf_data = + lower_32_bits(input->trail_fence_data); + } else { + mes_remove_queue_pkt.unmap_legacy_queue = 1; + mes_remove_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + } + + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, pipe, + &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), + offsetof(union MESAPI__REMOVE_QUEUE, api_status)); +} + +static int mes_v12_1_suspend_gang(struct amdgpu_mes *mes, + struct mes_suspend_gang_input *input) +{ + return 0; +} + +static int mes_v12_1_resume_gang(struct amdgpu_mes *mes, + struct mes_resume_gang_input *input) +{ + return 0; +} + +static int mes_v12_1_query_sched_status(struct amdgpu_mes *mes, + int pipe, int xcc_id) +{ + union MESAPI__QUERY_MES_STATUS mes_status_pkt; + + memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); + + mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; + mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, + &mes_status_pkt, sizeof(mes_status_pkt), + offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); +} +static uint32_t mes_v12_1_get_xcc_from_reg(uint32_t reg_offset) +{ + return ((reg_offset >> 16) & 0x7); +} + +static void mes_v12_1_get_rrmt(uint32_t reg, uint32_t xcc_id, + struct RRMT_OPTION *rrmt_opt, + uint32_t *out_reg) +{ + uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) { + rrmt_opt->xcd_die_id = mes_v12_1_get_xcc_from_reg(reg); + rrmt_opt->mode = (xcc_id == rrmt_opt->xcd_die_id) ? + MES_RRMT_MODE_LOCAL_XCD : MES_RRMT_MODE_REMOTE_XCD; + } else { + rrmt_opt->mode = MES_RRMT_MODE_REMOTE_MID; + if (soc_v1_0_mid1_reg_range(reg)) + rrmt_opt->mid_die_id = 1; + } + + *out_reg = soc_v1_0_normalize_reg_offset(reg); +} + +static int mes_v12_1_misc_op(struct amdgpu_mes *mes, + struct mes_misc_op_input *input) +{ + struct amdgpu_device *adev = mes->adev; + union MESAPI__MISC misc_pkt; + int pipe; + + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + + memset(&misc_pkt, 0, sizeof(misc_pkt)); + + misc_pkt.header.type = MES_API_TYPE_SCHEDULER; + misc_pkt.header.opcode = MES_SCH_API_MISC; + misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + switch (input->op) { + case MES_MISC_OP_READ_REG: + misc_pkt.opcode = MESAPI_MISC__READ_REG; + misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; + mes_v12_1_get_rrmt(input->read_reg.reg_offset, + GET_INST(GC, input->xcc_id), + &misc_pkt.read_reg.rrmt_opt, + &misc_pkt.read_reg.reg_offset); + break; + case MES_MISC_OP_WRITE_REG: + misc_pkt.opcode = MESAPI_MISC__WRITE_REG; + misc_pkt.write_reg.reg_value = input->write_reg.reg_value; + mes_v12_1_get_rrmt(input->write_reg.reg_offset, + GET_INST(GC, input->xcc_id), + &misc_pkt.write_reg.rrmt_opt, + &misc_pkt.write_reg.reg_offset); + break; + case MES_MISC_OP_WRM_REG_WAIT: + misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; + misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; + misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; + misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; + misc_pkt.wait_reg_mem.reg_offset2 = 0; + mes_v12_1_get_rrmt(input->wrm_reg.reg0, + GET_INST(GC, input->xcc_id), + &misc_pkt.wait_reg_mem.rrmt_opt1, + &misc_pkt.wait_reg_mem.reg_offset1); + break; + case MES_MISC_OP_WRM_REG_WR_WAIT: + misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; + misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; + misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; + misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; + mes_v12_1_get_rrmt(input->wrm_reg.reg0, + GET_INST(GC, input->xcc_id), + &misc_pkt.wait_reg_mem.rrmt_opt1, + &misc_pkt.wait_reg_mem.reg_offset1); + mes_v12_1_get_rrmt(input->wrm_reg.reg1, + GET_INST(GC, input->xcc_id), + &misc_pkt.wait_reg_mem.rrmt_opt2, + &misc_pkt.wait_reg_mem.reg_offset2); + break; + case MES_MISC_OP_SET_SHADER_DEBUGGER: + pipe = AMDGPU_MES_SCHED_PIPE; + misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; + misc_pkt.set_shader_debugger.process_context_addr = + input->set_shader_debugger.process_context_addr; + misc_pkt.set_shader_debugger.flags.u32all = + input->set_shader_debugger.flags.u32all; + misc_pkt.set_shader_debugger.spi_gdbg_per_vmid_cntl = + input->set_shader_debugger.spi_gdbg_per_vmid_cntl; + memcpy(misc_pkt.set_shader_debugger.tcp_watch_cntl, + input->set_shader_debugger.tcp_watch_cntl, + sizeof(misc_pkt.set_shader_debugger.tcp_watch_cntl)); + misc_pkt.set_shader_debugger.trap_en = input->set_shader_debugger.trap_en; + break; + case MES_MISC_OP_CHANGE_CONFIG: + misc_pkt.opcode = MESAPI_MISC__CHANGE_CONFIG; + misc_pkt.change_config.opcode = + MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS; + misc_pkt.change_config.option.bits.limit_single_process = + input->change_config.option.limit_single_process; + break; + default: + DRM_ERROR("unsupported misc op (%d) \n", input->op); + return -EINVAL; + } + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, pipe, + &misc_pkt, sizeof(misc_pkt), + offsetof(union MESAPI__MISC, api_status)); +} + +static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes, + int pipe, int xcc_id) +{ + union MESAPI_SET_HW_RESOURCES_1 mes_set_hw_res_1_pkt; + int master_xcc_id, inst = MES_PIPE_INST(xcc_id, pipe); + + memset(&mes_set_hw_res_1_pkt, 0, sizeof(mes_set_hw_res_1_pkt)); + + mes_set_hw_res_1_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_set_hw_res_1_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC_1; + mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100; + + if (mes->enable_coop_mode && pipe == AMDGPU_MES_SCHED_PIPE) { + master_xcc_id = mes->master_xcc_ids[inst]; + mes_set_hw_res_1_pkt.mes_coop_mode = 1; + mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr = + mes->shared_cmd_buf_gpu_addr[master_xcc_id]; + } + + return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, + &mes_set_hw_res_1_pkt, sizeof(mes_set_hw_res_1_pkt), + offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status)); +} + +static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt) +{ + /* + * GFX V12 has only one GFX pipe, but 8 queues in it. + * GFX pipe 0 queue 0 is being used by Kernel queue. + * Set GFX pipe 0 queue 1-7 for MES scheduling + * mask = 1111 1110b + */ + pkt->gfx_hqd_mask[0] = 0xFE; +} + +static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes, + int pipe, int xcc_id) +{ + int i; + struct amdgpu_device *adev = mes->adev; + union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; + + memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); + + mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; + mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + if (pipe == AMDGPU_MES_SCHED_PIPE) { + mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; + mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; + mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; + mes_set_hw_res_pkt.paging_vmid = 0; + + for (i = 0; i < MAX_COMPUTE_PIPES; i++) + mes_set_hw_res_pkt.compute_hqd_mask[i] = + mes->compute_hqd_mask[i]; + + mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt); + + for (i = 0; i < MAX_SDMA_PIPES; i++) + mes_set_hw_res_pkt.sdma_hqd_mask[i] = + mes->sdma_hqd_mask[i]; + + for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) + mes_set_hw_res_pkt.aggregated_doorbells[i] = + mes->aggregated_doorbells[i]; + } + + mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = + mes->sch_ctx_gpu_addr[pipe]; + mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = + mes->query_status_fence_gpu_addr[pipe]; + + for (i = 0; i < 5; i++) { + mes_set_hw_res_pkt.gc_base[i] = + adev->reg_offset[GC_HWIP][0][i]; + mes_set_hw_res_pkt.mmhub_base[i] = + adev->reg_offset[MMHUB_HWIP][0][i]; + mes_set_hw_res_pkt.osssys_base[i] = + adev->reg_offset[OSSSYS_HWIP][0][i]; + } + + mes_set_hw_res_pkt.disable_reset = 1; + mes_set_hw_res_pkt.disable_mes_log = 1; + mes_set_hw_res_pkt.use_different_vmid_compute = 1; + mes_set_hw_res_pkt.enable_reg_active_poll = 1; + mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; + + /* + * Keep oversubscribe timer for sdma . When we have unmapped doorbell + * handling support, other queue will not use the oversubscribe timer. + * handling mode - 0: disabled; 1: basic version; 2: basic+ version + */ + mes_set_hw_res_pkt.oversubscription_timer = 50; + mes_set_hw_res_pkt.unmapped_doorbell_handling = 1; + + if (amdgpu_mes_log_enable) { + mes_set_hw_res_pkt.enable_mes_event_int_logging = 1; + mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = + mes->event_log_gpu_addr + MES_PIPE_INST(xcc_id, pipe) * AMDGPU_MES_LOG_BUFFER_SIZE; + } + + if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE) + mes_set_hw_res_pkt.limit_single_process = 1; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe, + &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), + offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); +} + +static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes, + int xcc_id) +{ + struct amdgpu_device *adev = mes->adev; + uint32_t data; + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1); + data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | + CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | + CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); + data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << + CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; + data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL1, data); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2); + data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | + CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | + CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); + data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << + CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; + data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL2, data); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3); + data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | + CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | + CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); + data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << + CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; + data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL3, data); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4); + data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | + CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | + CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); + data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << + CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; + data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL4, data); + + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5); + data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | + CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | + CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); + data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << + CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; + data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_DOORBELL_CONTROL5, data); + + data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_GFX_CONTROL, data); +} + + +static void mes_v12_1_enable_unmapped_doorbell_handling( + struct amdgpu_mes *mes, bool enable, int xcc_id) +{ + struct amdgpu_device *adev = mes->adev; + uint32_t data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL); + + /* + * The default PROC_LSB settng is 0xc which means doorbell + * addr[16:12] gives the doorbell page number. For kfd, each + * process will use 2 pages of doorbell, we need to change the + * setting to 0xd + */ + data &= ~CP_UNMAPPED_DOORBELL__PROC_LSB_MASK; + data |= 0xd << CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT; + + data |= (enable ? 1 : 0) << CP_UNMAPPED_DOORBELL__ENABLE__SHIFT; + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_UNMAPPED_DOORBELL, data); +} + +#if 0 +static int mes_v12_1_reset_legacy_queue(struct amdgpu_mes *mes, + struct mes_reset_legacy_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + int pipe; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.queue_type = + convert_to_mes_queue_type(input->queue_type); + + if (mes_reset_queue_pkt.queue_type == MES_QUEUE_TYPE_GFX) { + mes_reset_queue_pkt.reset_legacy_gfx = 1; + mes_reset_queue_pkt.pipe_id_lp = input->pipe_id; + mes_reset_queue_pkt.queue_id_lp = input->queue_id; + mes_reset_queue_pkt.mqd_mc_addr_lp = input->mqd_addr; + mes_reset_queue_pkt.doorbell_offset_lp = input->doorbell_offset; + mes_reset_queue_pkt.wptr_addr_lp = input->wptr_addr; + mes_reset_queue_pkt.vmid_id_lp = input->vmid; + } else { + mes_reset_queue_pkt.reset_queue_only = 1; + mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; + } + + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + + return mes_v12_1_submit_pkt_and_poll_completion(mes, + input->xcc_id, pipe, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__RESET, api_status)); +} +#endif + +static int mes_v12_inv_tlb_convert_hub_id(uint8_t id) +{ + /* + * MES doesn't support invalidate gc_hub on slave xcc individually + * master xcc will invalidate all gc_hub for the partition + */ + if (AMDGPU_IS_GFXHUB(id)) + return 0; + else if (AMDGPU_IS_MMHUB0(id)) + return 1; + else if (AMDGPU_IS_MMHUB1(id)) + return 2; + return -EINVAL; + +} + +static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes, + struct mes_inv_tlbs_pasid_input *input) +{ + union MESAPI__INV_TLBS mes_inv_tlbs; + int xcc_id = input->xcc_id; + int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); + int ret; + + if (mes->enable_coop_mode) + xcc_id = mes->master_xcc_ids[inst]; + + memset(&mes_inv_tlbs, 0, sizeof(mes_inv_tlbs)); + + mes_inv_tlbs.header.type = MES_API_TYPE_SCHEDULER; + mes_inv_tlbs.header.opcode = MES_SCH_API_INV_TLBS; + mes_inv_tlbs.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_inv_tlbs.invalidate_tlbs.inv_sel = 0; + mes_inv_tlbs.invalidate_tlbs.flush_type = input->flush_type; + mes_inv_tlbs.invalidate_tlbs.inv_sel_id = input->pasid; + + /*convert amdgpu_mes_hub_id to mes expected hub_id */ + ret = mes_v12_inv_tlb_convert_hub_id(input->hub_id); + if (ret < 0) + return -EINVAL; + mes_inv_tlbs.invalidate_tlbs.hub_id = ret; + return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE, + &mes_inv_tlbs, sizeof(mes_inv_tlbs), + offsetof(union MESAPI__INV_TLBS, api_status)); + +} + +static const struct amdgpu_mes_funcs mes_v12_1_funcs = { + .add_hw_queue = mes_v12_1_add_hw_queue, + .remove_hw_queue = mes_v12_1_remove_hw_queue, + .map_legacy_queue = mes_v12_1_map_legacy_queue, + .unmap_legacy_queue = mes_v12_1_unmap_legacy_queue, + .suspend_gang = mes_v12_1_suspend_gang, + .resume_gang = mes_v12_1_resume_gang, + .misc_op = mes_v12_1_misc_op, + .reset_hw_queue = mes_v12_1_reset_hw_queue, + .invalidate_tlbs_pasid = mes_v12_1_inv_tlbs_pasid, +}; + +static int mes_v12_1_allocate_ucode_buffer(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + int r, inst = MES_PIPE_INST(xcc_id, pipe); + const struct mes_firmware_header_v1_0 *mes_hdr; + const __le32 *fw_data; + unsigned fw_size; + + mes_hdr = (const struct mes_firmware_header_v1_0 *) + adev->mes.fw[pipe]->data; + + fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + + le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); + fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); + + r = amdgpu_bo_create_reserved(adev, fw_size, + PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->mes.ucode_fw_obj[inst], + &adev->mes.ucode_fw_gpu_addr[inst], + (void **)&adev->mes.ucode_fw_ptr[inst]); + if (r) { + dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); + return r; + } + + memcpy(adev->mes.ucode_fw_ptr[inst], fw_data, fw_size); + + amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[inst]); + amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[inst]); + + return 0; +} + +static int mes_v12_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + int r, inst = MES_PIPE_INST(xcc_id, pipe); + const struct mes_firmware_header_v1_0 *mes_hdr; + const __le32 *fw_data; + unsigned fw_size; + + mes_hdr = (const struct mes_firmware_header_v1_0 *) + adev->mes.fw[pipe]->data; + + fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + + le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); + fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); + + r = amdgpu_bo_create_reserved(adev, fw_size, + 64 * 1024, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->mes.data_fw_obj[inst], + &adev->mes.data_fw_gpu_addr[inst], + (void **)&adev->mes.data_fw_ptr[inst]); + if (r) { + dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); + return r; + } + + memcpy(adev->mes.data_fw_ptr[inst], fw_data, fw_size); + + amdgpu_bo_kunmap(adev->mes.data_fw_obj[inst]); + amdgpu_bo_unreserve(adev->mes.data_fw_obj[inst]); + + return 0; +} + +static void mes_v12_1_free_ucode_buffers(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + int inst = MES_PIPE_INST(xcc_id, pipe); + + amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[inst], + &adev->mes.data_fw_gpu_addr[inst], + (void **)&adev->mes.data_fw_ptr[inst]); + + amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[inst], + &adev->mes.ucode_fw_gpu_addr[inst], + (void **)&adev->mes.ucode_fw_ptr[inst]); +} + +static void mes_v12_1_enable(struct amdgpu_device *adev, + bool enable, int xcc_id) +{ + uint64_t ucode_addr; + uint32_t pipe, data = 0; + + if (enable) { + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); + + mutex_lock(&adev->srbm_mutex); + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, + GET_INST(GC, xcc_id)); + + ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regCP_MES_PRGRM_CNTR_START, + lower_32_bits(ucode_addr)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regCP_MES_PRGRM_CNTR_START_HI, + upper_32_bits(ucode_addr)); + } + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + /* unhalt MES and activate pipe0 */ + data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); + + if (amdgpu_emu_mode) + msleep(500); + else if (adev->enable_uni_mes) + udelay(500); + else + udelay(50); + } else { + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); + data = REG_SET_FIELD(data, CP_MES_CNTL, + MES_INVALIDATE_ICACHE, 1); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 1); + data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_CNTL, data); + } +} + +static void mes_v12_1_set_ucode_start_addr(struct amdgpu_device *adev, + int xcc_id) +{ + uint64_t ucode_addr; + int pipe; + + mes_v12_1_enable(adev, false, xcc_id); + + mutex_lock(&adev->srbm_mutex); + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + /* me=3, queue=0 */ + soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); + + /* set ucode start address */ + ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START, + lower_32_bits(ucode_addr)); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_PRGRM_CNTR_START_HI, + upper_32_bits(ucode_addr)); + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + } + mutex_unlock(&adev->srbm_mutex); +} + +/* This function is for backdoor MES firmware */ +static int mes_v12_1_load_microcode(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + bool prime_icache, int xcc_id) +{ + int r, inst = MES_PIPE_INST(xcc_id, pipe); + uint32_t data; + + mes_v12_1_enable(adev, false, xcc_id); + + if (!adev->mes.fw[pipe]) + return -EINVAL; + + r = mes_v12_1_allocate_ucode_buffer(adev, pipe, xcc_id); + if (r) + return r; + + r = mes_v12_1_allocate_ucode_data_buffer(adev, pipe, xcc_id); + if (r) { + mes_v12_1_free_ucode_buffers(adev, pipe, xcc_id); + return r; + } + + mutex_lock(&adev->srbm_mutex); + /* me=3, pipe=0, queue=0 */ + soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_CNTL, 0); + + /* set ucode fimrware address */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_LO, + lower_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_BASE_HI, + upper_32_bits(adev->mes.ucode_fw_gpu_addr[inst])); + + /* set ucode instruction cache boundary to 2M-1 */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MIBOUND_LO, 0x1FFFFF); + + /* set ucode data firmware address */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_LO, + lower_32_bits(adev->mes.data_fw_gpu_addr[inst])); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBASE_HI, + upper_32_bits(adev->mes.data_fw_gpu_addr[inst])); + + /* Set data cache boundary CP_MES_MDBOUND_LO */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_MDBOUND_LO, 0x7FFFF); + + if (prime_icache) { + /* invalidate ICACHE */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); + data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); + data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); + + /* prime the ICACHE. */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL); + data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_IC_OP_CNTL, data); + } + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + return 0; +} + +static int mes_v12_1_allocate_eop_buf(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + int r, inst = MES_PIPE_INST(xcc_id, pipe); + u32 *eop; + + r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, + &adev->mes.eop_gpu_obj[inst], + &adev->mes.eop_gpu_addr[inst], + (void **)&eop); + if (r) { + dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); + return r; + } + + memset(eop, 0, + adev->mes.eop_gpu_obj[inst]->tbo.base.size); + + amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[inst]); + amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[inst]); + + return 0; +} + +static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + int r, inst = MES_PIPE_INST(xcc_id, pipe); + + if (pipe == AMDGPU_MES_KIQ_PIPE) + return 0; + + r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->mes.shared_cmd_buf_obj[inst], + &adev->mes.shared_cmd_buf_gpu_addr[inst], + NULL); + if (r) { + dev_err(adev->dev, + "(%d) failed to create shared cmd buf bo\n", r); + return r; + } + + return 0; +} + +static int mes_v12_1_mqd_init(struct amdgpu_ring *ring) +{ + struct v12_1_mes_mqd *mqd = ring->mqd_ptr; + uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; + uint32_t tmp; + + mqd->header = 0xC0310800; + mqd->compute_pipelinestat_enable = 0x00000001; + mqd->compute_static_thread_mgmt_se0 = 0xffffffff; + mqd->compute_static_thread_mgmt_se1 = 0xffffffff; + mqd->compute_static_thread_mgmt_se2 = 0xffffffff; + mqd->compute_static_thread_mgmt_se3 = 0xffffffff; + mqd->compute_misc_reserved = 0x00000007; + + eop_base_addr = ring->eop_gpu_addr >> 8; + + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = regCP_HQD_EOP_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, + (order_base_2(MES_EOP_SIZE / 4) - 1)); + + mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); + mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); + mqd->cp_hqd_eop_control = tmp; + + /* disable the queue if it's active */ + ring->wptr = 0; + mqd->cp_hqd_pq_rptr = 0; + mqd->cp_hqd_pq_wptr_lo = 0; + mqd->cp_hqd_pq_wptr_hi = 0; + + /* set the pointer to the MQD */ + mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; + mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); + + /* set MQD vmid to 0 */ + tmp = regCP_MQD_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); + mqd->cp_mqd_control = tmp; + + /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ + hqd_gpu_addr = ring->gpu_addr >> 8; + mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); + mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); + + /* set the wb address whether it's enabled or not */ + wb_gpu_addr = ring->rptr_gpu_addr; + mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; + mqd->cp_hqd_pq_rptr_report_addr_hi = + upper_32_bits(wb_gpu_addr) & 0xffff; + + /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ + wb_gpu_addr = ring->wptr_gpu_addr; + mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; + mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; + + /* set up the HQD, this is similar to CP_RB0_CNTL */ + tmp = regCP_HQD_PQ_CONTROL_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, + (order_base_2(ring->ring_size / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, + ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); + mqd->cp_hqd_pq_control = tmp; + + /* enable doorbell */ + tmp = 0; + if (ring->use_doorbell) { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_OFFSET, ring->doorbell_index); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_SOURCE, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_HIT, 0); + } else { + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 0); + } + mqd->cp_hqd_pq_doorbell_control = tmp; + + mqd->cp_hqd_vmid = 0; + /* activate the queue */ + mqd->cp_hqd_active = 1; + + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, + PRELOAD_SIZE, 0x63); + mqd->cp_hqd_persistent_state = tmp; + + mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_MES_12_1_DEFAULT; + mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; + mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; + + /* + * Set CP_HQD_GFX_CONTROL.DB_UPDATED_MSG_EN[15] to enable unmapped + * doorbell handling. This is a reserved CP internal register can + * not be accesss by others + */ + mqd->cp_hqd_gfx_control = BIT(15); + + return 0; +} + +static void mes_v12_1_queue_init_register(struct amdgpu_ring *ring, + int xcc_id) +{ + struct v12_1_mes_mqd *mqd = ring->mqd_ptr; + struct amdgpu_device *adev = ring->adev; + uint32_t data = 0; + + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 3, ring->pipe, 0, 0, GET_INST(GC, xcc_id)); + + /* set CP_HQD_VMID.VMID = 0. */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID); + data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, data); + + /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); + data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); + + /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); + + /* set CP_MQD_CONTROL.VMID=0 */ + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); + data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 0); + + /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); + + /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, + mqd->cp_hqd_pq_rptr_report_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, + mqd->cp_hqd_pq_rptr_report_addr_hi); + + /* set CP_HQD_PQ_CONTROL */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); + + /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, + mqd->cp_hqd_pq_wptr_poll_addr_lo); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, + mqd->cp_hqd_pq_wptr_poll_addr_hi); + + /* set CP_HQD_PQ_DOORBELL_CONTROL */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, + mqd->cp_hqd_pq_doorbell_control); + + /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); + + /* set CP_HQD_ACTIVE.ACTIVE=1 */ + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, mqd->cp_hqd_active); + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); +} + +static int mes_v12_1_kiq_enable_queue(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[xcc_id].ring; + int r, inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); + + if (!kiq->pmf || !kiq->pmf->kiq_map_queues) + return -EINVAL; + + r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); + if (r) { + DRM_ERROR("Failed to lock KIQ (%d).\n", r); + return r; + } + + kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[inst]); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) { + DRM_ERROR("kfq enable failed\n"); + kiq_ring->sched.ready = false; + } + return r; +} + +static int mes_v12_1_queue_init(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + struct amdgpu_ring *ring; + int r; + + if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) + ring = &adev->gfx.kiq[xcc_id].ring; + else + ring = &adev->mes.ring[MES_PIPE_INST(xcc_id, pipe)]; + + if ((adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) && + (amdgpu_in_reset(adev) || adev->in_suspend)) { + *(ring->wptr_cpu_addr) = 0; + *(ring->rptr_cpu_addr) = 0; + amdgpu_ring_clear_ring(ring); + } + + r = mes_v12_1_mqd_init(ring); + if (r) + return r; + + if (pipe == AMDGPU_MES_SCHED_PIPE) { + if (adev->enable_uni_mes) + r = amdgpu_mes_map_legacy_queue(adev, ring, xcc_id); + else + r = mes_v12_1_kiq_enable_queue(adev, xcc_id); + if (r) + return r; + } else { + mes_v12_1_queue_init_register(ring, xcc_id); + } + + /* get MES scheduler/KIQ versions */ + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id)); + + if (pipe == AMDGPU_MES_SCHED_PIPE) + adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); + else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) + adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO); + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + return 0; +} + +static int mes_v12_1_ring_init(struct amdgpu_device *adev, + int xcc_id, int pipe) +{ + struct amdgpu_ring *ring; + int inst = MES_PIPE_INST(xcc_id, pipe); + + ring = &adev->mes.ring[inst]; + + ring->funcs = &mes_v12_1_ring_funcs; + + ring->me = 3; + ring->pipe = pipe; + ring->queue = 0; + ring->xcc_id = xcc_id; + ring->vm_hub = AMDGPU_GFXHUB(xcc_id); + + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; + ring->no_scheduler = true; + snprintf(ring->name, sizeof(ring->name), "mes_%hhu.%hhu.%hhu.%hhu", + (unsigned char)xcc_id, (unsigned char)ring->me, + (unsigned char)ring->pipe, (unsigned char)ring->queue); + + if (pipe == AMDGPU_MES_SCHED_PIPE) + ring->doorbell_index = + (adev->doorbell_index.mes_ring0 + + xcc_id * adev->doorbell_index.xcc_doorbell_range) + << 1; + else + ring->doorbell_index = + (adev->doorbell_index.mes_ring1 + + xcc_id * adev->doorbell_index.xcc_doorbell_range) + << 1; + + return amdgpu_ring_init(adev, ring, 1024, NULL, 0, + AMDGPU_RING_PRIO_DEFAULT, NULL); +} + +static int mes_v12_1_kiq_ring_init(struct amdgpu_device *adev, int xcc_id) +{ + struct amdgpu_ring *ring; + int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); + + spin_lock_init(&adev->gfx.kiq[xcc_id].ring_lock); + + ring = &adev->gfx.kiq[xcc_id].ring; + + ring->me = 3; + ring->pipe = 1; + ring->queue = 0; + ring->xcc_id = xcc_id; + ring->vm_hub = AMDGPU_GFXHUB(xcc_id); + + ring->adev = NULL; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->eop_gpu_addr = adev->mes.eop_gpu_addr[inst]; + ring->no_scheduler = true; + ring->doorbell_index = + (adev->doorbell_index.mes_ring1 + + xcc_id * adev->doorbell_index.xcc_doorbell_range) + << 1; + + snprintf(ring->name, sizeof(ring->name), "mes_kiq_%hhu.%hhu.%hhu.%hhu", + (unsigned char)xcc_id, (unsigned char)ring->me, + (unsigned char)ring->pipe, (unsigned char)ring->queue); + + return amdgpu_ring_init(adev, ring, 1024, NULL, 0, + AMDGPU_RING_PRIO_DEFAULT, NULL); +} + +static int mes_v12_1_mqd_sw_init(struct amdgpu_device *adev, + enum amdgpu_mes_pipe pipe, + int xcc_id) +{ + int r, mqd_size = sizeof(struct v12_1_mes_mqd); + struct amdgpu_ring *ring; + int inst = MES_PIPE_INST(xcc_id, pipe); + + if (!adev->enable_uni_mes && pipe == AMDGPU_MES_KIQ_PIPE) + ring = &adev->gfx.kiq[xcc_id].ring; + else + ring = &adev->mes.ring[inst]; + + if (ring->mqd_obj) + return 0; + + r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, + &ring->mqd_gpu_addr, &ring->mqd_ptr); + if (r) { + dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); + return r; + } + + memset(ring->mqd_ptr, 0, mqd_size); + + /* prepare MQD backup */ + adev->mes.mqd_backup[inst] = kmalloc(mqd_size, GFP_KERNEL); + if (!adev->mes.mqd_backup[inst]) + dev_warn(adev->dev, + "no memory to create MQD backup for ring %s\n", + ring->name); + + return 0; +} + +static int mes_v12_1_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + adev->mes.funcs = &mes_v12_1_funcs; + adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; + adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; + adev->mes.enable_legacy_queue_map = true; + + adev->mes.event_log_size = + adev->enable_uni_mes ? (AMDGPU_MAX_MES_PIPES * AMDGPU_MES_LOG_BUFFER_SIZE * num_xcc) : AMDGPU_MES_LOG_BUFFER_SIZE; + + r = amdgpu_mes_init(adev); + if (r) + return r; + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + r = mes_v12_1_allocate_eop_buf(adev, pipe, xcc_id); + if (r) + return r; + + r = mes_v12_1_mqd_sw_init(adev, pipe, xcc_id); + if (r) + return r; + + if (!adev->enable_uni_mes && pipe == + AMDGPU_MES_KIQ_PIPE) + r = mes_v12_1_kiq_ring_init(adev, xcc_id); + else + r = mes_v12_1_ring_init(adev, xcc_id, pipe); + if (r) + return r; + + if (adev->enable_uni_mes && num_xcc > 1) { + r = mes_v12_1_allocate_shared_cmd_buf(adev, + pipe, xcc_id); + if (r) + return r; + } + } + } + + return 0; +} + +static int mes_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int pipe, inst, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + inst = MES_PIPE_INST(xcc_id, pipe); + + amdgpu_bo_free_kernel(&adev->mes.shared_cmd_buf_obj[inst], + &adev->mes.shared_cmd_buf_gpu_addr[inst], + NULL); + + kfree(adev->mes.mqd_backup[inst]); + + amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[inst], + &adev->mes.eop_gpu_addr[inst], + NULL); + + if (adev->enable_uni_mes || pipe == AMDGPU_MES_SCHED_PIPE) { + amdgpu_bo_free_kernel(&adev->mes.ring[inst].mqd_obj, + &adev->mes.ring[inst].mqd_gpu_addr, + &adev->mes.ring[inst].mqd_ptr); + amdgpu_ring_fini(&adev->mes.ring[inst]); + } + } + } + + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) + amdgpu_ucode_release(&adev->mes.fw[pipe]); + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + if (!adev->enable_uni_mes) { + amdgpu_bo_free_kernel(&adev->gfx.kiq[xcc_id].ring.mqd_obj, + &adev->gfx.kiq[xcc_id].ring.mqd_gpu_addr, + &adev->gfx.kiq[xcc_id].ring.mqd_ptr); + amdgpu_ring_fini(&adev->gfx.kiq[xcc_id].ring); + } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + mes_v12_1_free_ucode_buffers(adev, + AMDGPU_MES_KIQ_PIPE, xcc_id); + mes_v12_1_free_ucode_buffers(adev, + AMDGPU_MES_SCHED_PIPE, xcc_id); + } + } + + amdgpu_mes_fini(adev); + return 0; +} + +static void mes_v12_1_kiq_dequeue_sched(struct amdgpu_device *adev, + int xcc_id) +{ + uint32_t data; + int i; + + mutex_lock(&adev->srbm_mutex); + soc_v1_0_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0, + GET_INST(GC, xcc_id)); + + /* disable the queue if it's active */ + if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + } + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); + data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_EN, 0); + data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, + DOORBELL_HIT, 1); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, data); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); + + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); + + soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + + adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = false; +} + +static void mes_v12_1_kiq_setting(struct amdgpu_ring *ring, int xcc_id) +{ + uint32_t tmp; + struct amdgpu_device *adev = ring->adev; + + /* tell RLC which is KIQ queue */ + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); + tmp &= 0xffffff00; + tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); + tmp |= 0x80; + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); +} + +static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id) +{ + int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_KIQ_PIPE); + int r = 0; + struct amdgpu_ip_block *ip_block; + + if (adev->enable_uni_mes) + mes_v12_1_kiq_setting(&adev->mes.ring[inst], xcc_id); + else + mes_v12_1_kiq_setting(&adev->gfx.kiq[xcc_id].ring, xcc_id); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + + r = mes_v12_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, + false, xcc_id); + if (r) { + DRM_ERROR("failed to load MES fw, r=%d\n", r); + return r; + } + + r = mes_v12_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, + true, xcc_id); + if (r) { + DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); + return r; + } + + mes_v12_1_set_ucode_start_addr(adev, xcc_id); + + } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) + mes_v12_1_set_ucode_start_addr(adev, xcc_id); + + mes_v12_1_enable(adev, true, xcc_id); + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); + if (unlikely(!ip_block)) { + dev_err(adev->dev, "Failed to get MES handle\n"); + return -EINVAL; + } + + r = mes_v12_1_queue_init(adev, AMDGPU_MES_KIQ_PIPE, xcc_id); + if (r) + goto failure; + + if (adev->enable_uni_mes) { + r = mes_v12_1_set_hw_resources(&adev->mes, + AMDGPU_MES_KIQ_PIPE, xcc_id); + if (r) + goto failure; + + mes_v12_1_set_hw_resources_1(&adev->mes, + AMDGPU_MES_KIQ_PIPE, xcc_id); + } + + if (adev->mes.enable_legacy_queue_map) { + r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); + if (r) + goto failure; + } + + return r; + +failure: + mes_v12_1_hw_fini(ip_block); + return r; +} + +static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id) +{ + int inst = MES_PIPE_INST(xcc_id, AMDGPU_MES_SCHED_PIPE); + + if (adev->mes.ring[inst].sched.ready) { + if (adev->enable_uni_mes) + amdgpu_mes_unmap_legacy_queue(adev, + &adev->mes.ring[inst], + RESET_QUEUES, 0, 0, xcc_id); + else + mes_v12_1_kiq_dequeue_sched(adev, xcc_id); + + adev->mes.ring[inst].sched.ready = false; + } + + mes_v12_1_enable(adev, false, xcc_id); + + return 0; +} + +static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id) +{ + u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); + int r = 0; + + if (num_xcc == 1) + return r; + + if (adev->gfx.funcs && + adev->gfx.funcs->get_xccs_per_xcp) + num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); + else + return -EINVAL; + + switch (adev->xcp_mgr->mode) { + case AMDGPU_SPX_PARTITION_MODE: + adev->mes.enable_coop_mode = 1; + adev->mes.master_xcc_ids[xcc_id] = 0; + break; + case AMDGPU_DPX_PARTITION_MODE: + adev->mes.enable_coop_mode = 1; + adev->mes.master_xcc_ids[xcc_id] = + (xcc_id/num_xcc_per_xcp) * (num_xcc / 2); + break; + case AMDGPU_QPX_PARTITION_MODE: + adev->mes.enable_coop_mode = 1; + adev->mes.master_xcc_ids[xcc_id] = + (xcc_id/num_xcc_per_xcp) * (num_xcc / 4); + break; + case AMDGPU_CPX_PARTITION_MODE: + adev->mes.enable_coop_mode = 0; + break; + default: + r = -EINVAL; + break; + } + return r; +} + +static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) +{ + int r; + struct amdgpu_device *adev = ip_block->adev; + + if (adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready) + goto out; + + if (!adev->enable_mes_kiq) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + r = mes_v12_1_load_microcode(adev, + AMDGPU_MES_SCHED_PIPE, true, xcc_id); + if (r) { + DRM_ERROR("failed to MES fw, r=%d\n", r); + return r; + } + + mes_v12_1_set_ucode_start_addr(adev, xcc_id); + + } else if (adev->firmware.load_type == + AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { + + mes_v12_1_set_ucode_start_addr(adev, xcc_id); + } + + mes_v12_1_enable(adev, true, xcc_id); + } + + /* Enable the MES to handle doorbell ring on unmapped queue */ + mes_v12_1_enable_unmapped_doorbell_handling(&adev->mes, true, xcc_id); + + r = mes_v12_1_queue_init(adev, AMDGPU_MES_SCHED_PIPE, xcc_id); + if (r) + goto failure; + + r = mes_v12_1_set_hw_resources(&adev->mes, + AMDGPU_MES_SCHED_PIPE, xcc_id); + if (r) + goto failure; + + if (adev->enable_uni_mes) { + r = mes_v12_1_setup_coop_mode(adev, xcc_id); + if (r) + goto failure; + mes_v12_1_set_hw_resources_1(&adev->mes, + AMDGPU_MES_SCHED_PIPE, xcc_id); + } + mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); + + r = mes_v12_1_query_sched_status(&adev->mes, + AMDGPU_MES_SCHED_PIPE, xcc_id); + if (r) { + DRM_ERROR("MES is busy\n"); + goto failure; + } + +out: + /* + * Disable KIQ ring usage from the driver once MES is enabled. + * MES uses KIQ ring exclusively so driver cannot access KIQ ring + * with MES enabled. + */ + adev->gfx.kiq[xcc_id].ring.sched.ready = false; + adev->mes.ring[MES_PIPE_INST(xcc_id, 0)].sched.ready = true; + + return 0; + +failure: + mes_v12_1_hw_fini(ip_block); + return r; +} + +static int mes_v12_1_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); + if (r) + return r; + } + + return 0; +} + +static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) +{ + return 0; +} + +static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block) +{ + int r; + + r = amdgpu_mes_suspend(ip_block->adev); + if (r) + return r; + + return mes_v12_1_hw_fini(ip_block); +} + +static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block) +{ + int r; + + r = mes_v12_1_hw_init(ip_block); + if (r) + return r; + + return amdgpu_mes_resume(ip_block->adev); +} + +static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int pipe, r; + + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + r = amdgpu_mes_init_microcode(adev, pipe); + if (r) + return r; + } + + return 0; +} + +static int mes_v12_1_late_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + /* TODO: remove it if issue fixed. */ + if (adev->mes.enable_coop_mode) + return 0; + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + /* for COOP mode, only test master xcc. */ + if (adev->mes.enable_coop_mode && + adev->mes.master_xcc_ids[xcc_id] != xcc_id) + continue; + + mes_v12_1_self_test(adev, xcc_id); + } + + return 0; +} + +static const struct amd_ip_funcs mes_v12_1_ip_funcs = { + .name = "mes_v12_1", + .early_init = mes_v12_1_early_init, + .late_init = mes_v12_1_late_init, + .sw_init = mes_v12_1_sw_init, + .sw_fini = mes_v12_1_sw_fini, + .hw_init = mes_v12_1_hw_init, + .hw_fini = mes_v12_1_hw_fini, + .suspend = mes_v12_1_suspend, + .resume = mes_v12_1_resume, +}; + +const struct amdgpu_ip_block_version mes_v12_1_ip_block = { + .type = AMD_IP_BLOCK_TYPE_MES, + .major = 12, + .minor = 1, + .rev = 0, + .funcs = &mes_v12_1_ip_funcs, +}; + +static int mes_v12_1_alloc_test_buf(struct amdgpu_device *adev, + struct amdgpu_bo **bo, uint64_t *addr, + void **ptr, int size) +{ + amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, + bo, addr, ptr); + if (!*bo) { + dev_err(adev->dev, "failed to allocate test buffer bo\n"); + return -ENOMEM; + } + memset(*ptr, 0, size); + return 0; +} + +static int mes_v12_1_map_test_bo(struct amdgpu_device *adev, + struct amdgpu_bo *bo, struct amdgpu_vm *vm, + struct amdgpu_bo_va **bo_va, u64 va, int size) +{ + struct amdgpu_sync sync; + int r; + + r = amdgpu_map_static_csa(adev, vm, bo, bo_va, va, size); + if (r) + return r; + + amdgpu_sync_create(&sync); + + r = amdgpu_vm_bo_update(adev, *bo_va, false); + if (r) { + dev_err(adev->dev, "failed to do vm_bo_update on meta data\n"); + goto error; + } + amdgpu_sync_fence(&sync, (*bo_va)->last_pt_update, GFP_KERNEL); + + r = amdgpu_vm_update_pdes(adev, vm, false); + if (r) { + dev_err(adev->dev, "failed to update pdes on meta data\n"); + goto error; + } + amdgpu_sync_fence(&sync, vm->last_update, GFP_KERNEL); + amdgpu_sync_wait(&sync, false); + +error: + amdgpu_sync_free(&sync); + return 0; +} + +static int mes_v12_1_test_ring(struct amdgpu_device *adev, int xcc_id, + u32 *queue_ptr, u64 fence_gpu_addr, + void *fence_cpu_ptr, void *wptr_cpu_addr, + u64 doorbell_idx, int queue_type) +{ + volatile uint32_t *cpu_ptr = fence_cpu_ptr; + int num_xcc = NUM_XCC(adev->gfx.xcc_mask); + int sdma_ring_align = 0x10, compute_ring_align = 0x100; + uint32_t tmp, xcc_offset; + int r = 0, i, wptr = 0; + + if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { + if (!adev->mes.enable_coop_mode) { + WREG32_SOC15(GC, GET_INST(GC, xcc_id), + regSCRATCH_REG0, 0xCAFEDEAD); + } else { + for (i = 0; i < num_xcc; i++) { + if (adev->mes.master_xcc_ids[i] == xcc_id) + WREG32_SOC15(GC, GET_INST(GC, i), + regSCRATCH_REG0, 0xCAFEDEAD); + } + } + + xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); + queue_ptr[wptr++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); + queue_ptr[wptr++] = xcc_offset - PACKET3_SET_UCONFIG_REG_START; + queue_ptr[wptr++] = 0xDEADBEEF; + + for (i = wptr; i < compute_ring_align; i++) + queue_ptr[wptr++] = PACKET3(PACKET3_NOP, 0x3FFF); + + } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { + *cpu_ptr = 0xCAFEDEAD; + + queue_ptr[wptr++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + queue_ptr[wptr++] = lower_32_bits(fence_gpu_addr); + queue_ptr[wptr++] = upper_32_bits(fence_gpu_addr); + queue_ptr[wptr++] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); + queue_ptr[wptr++] = 0xDEADBEEF; + + for (i = wptr; i < sdma_ring_align; i++) + queue_ptr[wptr++] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + + wptr <<= 2; + } + + atomic64_set((atomic64_t *)wptr_cpu_addr, wptr); + WDOORBELL64(doorbell_idx, wptr); + + for (i = 0; i < adev->usec_timeout; i++) { + if (queue_type == AMDGPU_RING_TYPE_SDMA) { + tmp = le32_to_cpu(*cpu_ptr); + } else { + if (!adev->mes.enable_coop_mode) { + tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), + regSCRATCH_REG0); + } else { + for (i = 0; i < num_xcc; i++) { + if (xcc_id != adev->mes.master_xcc_ids[i]) + continue; + + tmp = RREG32_SOC15(GC, GET_INST(GC, i), + regSCRATCH_REG0); + if (tmp != 0xDEADBEEF) + break; + } + } + } + + if (tmp == 0xDEADBEEF) + break; + + if (amdgpu_emu_mode == 1) + msleep(1); + else + udelay(1); + } + + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "xcc%d: mes self test (%s) failed\n", xcc_id, + queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); + + while (halt_if_hws_hang) + schedule(); + + r = -ETIMEDOUT; + } else { + dev_info(adev->dev, "xcc%d: mes self test (%s) pass\n", xcc_id, + queue_type == AMDGPU_RING_TYPE_SDMA ? "sdma" : "compute"); + } + + return r; +} + +#define USER_CTX_SIZE (PAGE_SIZE * 2) +#define USER_CTX_VA AMDGPU_VA_RESERVED_BOTTOM +#define RING_OFFSET(addr) ((addr)) +#define EOP_OFFSET(addr) ((addr) + PAGE_SIZE) +#define WPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64)) +#define RPTR_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 2) +#define FENCE_OFFSET(addr) ((addr) + USER_CTX_SIZE - sizeof(u64) * 3) + +static int mes_v12_1_test_queue(struct amdgpu_device *adev, int xcc_id, + int pasid, struct amdgpu_vm *vm, u64 meta_gpu_addr, + u64 queue_gpu_addr, void *ctx_ptr, int queue_type) +{ + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + struct amdgpu_mqd *mqd_mgr = &adev->mqds[queue_type]; + struct amdgpu_mqd_prop mqd_prop = {0}; + struct mes_add_queue_input add_queue = {0}; + struct mes_remove_queue_input remove_queue = {0}; + struct amdgpu_bo *mqd_bo = NULL; + int num_xcc = NUM_XCC(adev->gfx.xcc_mask); + int i, r, off, mqd_size, mqd_count = 1; + void *mqd_ptr = NULL; + u64 mqd_gpu_addr, doorbell_idx; + + /* extra one page size padding for mes fw */ + mqd_size = mqd_mgr->mqd_size + PAGE_SIZE; + + if (queue_type == AMDGPU_RING_TYPE_SDMA) { + doorbell_idx = adev->mes.db_start_dw_offset + \ + adev->doorbell_index.sdma_engine[0]; + } else { + doorbell_idx = adev->mes.db_start_dw_offset + \ + adev->doorbell_index.userqueue_start; + } + + if (adev->mes.enable_coop_mode && + queue_type == AMDGPU_RING_TYPE_COMPUTE) { + for (i = 0, mqd_count = 0; i < num_xcc; i++) { + if (adev->mes.master_xcc_ids[i] == xcc_id) + mqd_count++; + } + mqd_size *= mqd_count; + } + + r = mes_v12_1_alloc_test_buf(adev, &mqd_bo, &mqd_gpu_addr, + &mqd_ptr, mqd_size * mqd_count); + if (r < 0) + return r; + + mqd_prop.mqd_gpu_addr = mqd_gpu_addr; + mqd_prop.hqd_base_gpu_addr = RING_OFFSET(USER_CTX_VA); + mqd_prop.eop_gpu_addr = EOP_OFFSET(USER_CTX_VA); + mqd_prop.wptr_gpu_addr = WPTR_OFFSET(USER_CTX_VA); + mqd_prop.rptr_gpu_addr = RPTR_OFFSET(USER_CTX_VA); + mqd_prop.doorbell_index = doorbell_idx; + mqd_prop.queue_size = PAGE_SIZE; + mqd_prop.mqd_stride_size = mqd_size; + mqd_prop.use_doorbell = true; + mqd_prop.hqd_active = false; + + mqd_mgr->init_mqd(adev, mqd_ptr, &mqd_prop); + if (mqd_count > 1) { + for (i = 1; i < mqd_count; i++) { + off = mqd_size * i; + mqd_prop.mqd_gpu_addr = mqd_gpu_addr + off; + mqd_mgr->init_mqd(adev, (char *)mqd_ptr + off, + &mqd_prop); + } + } + + add_queue.xcc_id = xcc_id; + add_queue.process_id = pasid; + add_queue.page_table_base_addr = adev->vm_manager.vram_base_offset + + amdgpu_bo_gpu_offset(vm->root.bo) - adev->gmc.vram_start; + add_queue.process_va_start = 0; + add_queue.process_va_end = adev->vm_manager.max_pfn - 1; + add_queue.process_context_addr = meta_gpu_addr; + add_queue.gang_context_addr = meta_gpu_addr + AMDGPU_MES_PROC_CTX_SIZE; + add_queue.doorbell_offset = doorbell_idx; + add_queue.mqd_addr = mqd_gpu_addr; + add_queue.wptr_addr = mqd_prop.wptr_gpu_addr; + add_queue.wptr_mc_addr = WPTR_OFFSET(queue_gpu_addr); + add_queue.queue_type = queue_type; + add_queue.vm_cntx_cntl = hub->vm_cntx_cntl; + + r = mes_v12_1_add_hw_queue(&adev->mes, &add_queue); + if (r) + goto error; + + mes_v12_1_test_ring(adev, xcc_id, (u32 *)RING_OFFSET((char *)ctx_ptr), + FENCE_OFFSET(USER_CTX_VA), + FENCE_OFFSET((char *)ctx_ptr), + WPTR_OFFSET((char *)ctx_ptr), + doorbell_idx, queue_type); + + remove_queue.xcc_id = xcc_id; + remove_queue.doorbell_offset = doorbell_idx; + remove_queue.gang_context_addr = add_queue.gang_context_addr; + r = mes_v12_1_remove_hw_queue(&adev->mes, &remove_queue); + +error: + amdgpu_bo_free_kernel(&mqd_bo, &mqd_gpu_addr, &mqd_ptr); + return r; +} + +static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id) +{ + int queue_types[] = { AMDGPU_RING_TYPE_COMPUTE, + /* AMDGPU_RING_TYPE_SDMA */ }; + struct amdgpu_bo_va *bo_va = NULL; + struct amdgpu_vm *vm = NULL; + struct amdgpu_bo *meta_bo = NULL, *ctx_bo = NULL; + void *meta_ptr = NULL, *ctx_ptr = NULL; + u64 meta_gpu_addr, ctx_gpu_addr; + int size, i, r, pasid; + + pasid = amdgpu_pasid_alloc(16); + if (pasid < 0) + pasid = 0; + + size = AMDGPU_MES_PROC_CTX_SIZE + AMDGPU_MES_GANG_CTX_SIZE; + r = mes_v12_1_alloc_test_buf(adev, &meta_bo, &meta_gpu_addr, + &meta_ptr, size); + if (r < 0) + goto err2; + + r = mes_v12_1_alloc_test_buf(adev, &ctx_bo, &ctx_gpu_addr, + &ctx_ptr, USER_CTX_SIZE); + if (r < 0) + goto err2; + + vm = kzalloc(sizeof(*vm), GFP_KERNEL); + if (!vm) { + r = -ENOMEM; + goto err2; + } + + r = amdgpu_vm_init(adev, vm, -1, pasid); + if (r) + goto err1; + + r = mes_v12_1_map_test_bo(adev, ctx_bo, vm, &bo_va, + USER_CTX_VA, USER_CTX_SIZE); + if (r) + goto err0; + + for (i = 0; i < ARRAY_SIZE(queue_types); i++) { + memset(ctx_ptr, 0, USER_CTX_SIZE); + + r = mes_v12_1_test_queue(adev, xcc_id, pasid, vm, meta_gpu_addr, + ctx_gpu_addr, ctx_ptr, queue_types[i]); + if (r) + break; + } + + amdgpu_unmap_static_csa(adev, vm, ctx_bo, bo_va, USER_CTX_VA); +err0: + amdgpu_vm_fini(adev, vm); +err1: + kfree(vm); +err2: + amdgpu_bo_free_kernel(&meta_bo, &meta_gpu_addr, &meta_ptr); + amdgpu_bo_free_kernel(&ctx_bo, &ctx_gpu_addr, &ctx_ptr); + amdgpu_pasid_free(pasid); + return r; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.h b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.h new file mode 100644 index 0000000000000..cfc048f652b07 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.h @@ -0,0 +1,29 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __MES_V12_1_H__ +#define __MES_V12_1_H__ + +extern const struct amdgpu_ip_block_version mes_v12_1_ip_block; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c index a0cc8e218ca1e..42a09a277ec3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c @@ -141,7 +141,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -151,22 +151,7 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(2, 0, 0): - case IP_VERSION(2, 0, 2): - mmhub_cid = mmhub_client_ids_navi1x[cid][rw]; - break; - case IP_VERSION(2, 1, 0): - case IP_VERSION(2, 1, 1): - mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw]; - break; - case IP_VERSION(2, 1, 2): - mmhub_cid = mmhub_client_ids_beige_goby[cid][rw]; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -518,6 +503,31 @@ static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = { .get_invalidate_req = mmhub_v2_0_get_invalidate_req, }; +static void mmhub_v2_0_init_client_info(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { + case IP_VERSION(2, 0, 0): + case IP_VERSION(2, 0, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_navi1x, + ARRAY_SIZE(mmhub_client_ids_navi1x)); + break; + case IP_VERSION(2, 1, 0): + case IP_VERSION(2, 1, 1): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_sienna_cichlid, + ARRAY_SIZE(mmhub_client_ids_sienna_cichlid)); + break; + case IP_VERSION(2, 1, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_beige_goby, + ARRAY_SIZE(mmhub_client_ids_beige_goby)); + break; + default: + break; + } +} + static void mmhub_v2_0_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; @@ -558,6 +568,8 @@ static void mmhub_v2_0_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs; + + mmhub_v2_0_init_client_info(adev); } static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c index 5eb8122e27469..31c479d76c421 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c @@ -80,7 +80,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -90,16 +90,7 @@ mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(2, 3, 0): - case IP_VERSION(2, 4, 0): - case IP_VERSION(2, 4, 1): - mmhub_cid = mmhub_client_ids_vangogh[cid][rw]; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -486,6 +477,10 @@ static void mmhub_v2_3_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_vangogh, + ARRAY_SIZE(mmhub_client_ids_vangogh)); } static void diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c index 7d5242df58a51..3d82cfa0f1b51 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c @@ -97,7 +97,7 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -107,15 +107,7 @@ mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(3, 0, 0): - case IP_VERSION(3, 0, 1): - mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw]; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -520,6 +512,10 @@ static void mmhub_v3_0_init(struct amdgpu_device *adev) SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE); hub->vmhub_funcs = &mmhub_v3_0_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_0_0, + ARRAY_SIZE(mmhub_client_ids_v3_0_0)); } static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c index 910337dc28d10..a1b0b7b39a42a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c @@ -104,7 +104,7 @@ mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -114,16 +114,7 @@ mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(3, 0, 1): - mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw]; - break; - default: - mmhub_cid = NULL; - break; - } - + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -503,6 +494,10 @@ static void mmhub_v3_0_1_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_0_1, + ARRAY_SIZE(mmhub_client_ids_v3_0_1)); } static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c index f0f182f033b98..34e8dbd47c0f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c @@ -97,7 +97,7 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -107,8 +107,7 @@ mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - - mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw]; + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -509,6 +508,10 @@ static void mmhub_v3_0_2_init(struct amdgpu_device *adev) SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2); hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_0_2, + ARRAY_SIZE(mmhub_client_ids_v3_0_2)); } static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c index f6fc9778bc305..cfce7e1297d4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c @@ -163,6 +163,35 @@ static const char *mmhub_client_ids_v3_3_1[][2] = { [32+30][1] = "VCN1", }; +static const char *mmhub_client_ids_v3_4[][2] = { + [0][0] = "VMC", + [4][0] = "DCEDMC", + [5][0] = "MPXSP", + [6][0] = "MPASP", + [7][0] = "MP1", + [8][0] = "MPM", + [23][0] = "HDP", + [24][0] = "LSDMA", + [25][0] = "JPEG", + [26][0] = "VPE", + [27][0] = "VSCH", + [28][0] = "VCNU", + [30][0] = "VCNRD", + [3][1] = "DCEDWB", + [4][1] = "DCEDMC", + [5][1] = "MPXSP", + [6][1] = "MPASAP", + [7][1] = "MP1", + [8][1] = "MPM", + [21][1] = "OSSSYS", + [23][1] = "HDP", + [24][1] = "LSDMA", + [25][1] = "JPEG", + [26][1] = "VPE", + [27][1] = "VSCH", + [29][1] = "VCNWR", +}; + static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, uint32_t flush_type) { @@ -188,7 +217,7 @@ mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS, CID); @@ -198,24 +227,10 @@ mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", status); - - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(3, 3, 0): - case IP_VERSION(3, 3, 2): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? - mmhub_client_ids_v3_3[cid][rw] : - cid == 0x140 ? "UMSCH" : NULL; - break; - case IP_VERSION(3, 3, 1): - mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3_1) ? - mmhub_client_ids_v3_3_1[cid][rw] : - cid == 0x140 ? "UMSCH" : NULL; - break; - default: - mmhub_cid = NULL; - break; - } - + if (cid == 0x140) + mmhub_cid = "UMSCH"; + else + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -606,6 +621,30 @@ static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { .get_invalidate_req = mmhub_v3_3_get_invalidate_req, }; +static void mmhub_v3_3_init_client_info(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { + case IP_VERSION(3, 3, 0): + case IP_VERSION(3, 3, 2): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_3, + ARRAY_SIZE(mmhub_client_ids_v3_3)); + break; + case IP_VERSION(3, 3, 1): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_3_1, + ARRAY_SIZE(mmhub_client_ids_v3_3_1)); + break; + case IP_VERSION(3, 4, 0): + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v3_4, + ARRAY_SIZE(mmhub_client_ids_v3_4)); + break; + default: + break; + } +} + static void mmhub_v3_3_init(struct amdgpu_device *adev) { struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; @@ -646,6 +685,8 @@ static void mmhub_v3_3_init(struct amdgpu_device *adev) MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; + + mmhub_v3_3_init_client_info(adev); } static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c index 951998454b257..bef75c4c48d3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c @@ -90,7 +90,7 @@ mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, uint32_t status) { uint32_t cid, rw; - const char *mmhub_cid = NULL; + const char *mmhub_cid; cid = REG_GET_FIELD(status, MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); @@ -100,14 +100,7 @@ mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, dev_err(adev->dev, "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", status); - switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { - case IP_VERSION(4, 1, 0): - mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw]; - break; - default: - mmhub_cid = NULL; - break; - } + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", mmhub_cid ? mmhub_cid : "unknown", cid); dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", @@ -514,6 +507,10 @@ static void mmhub_v4_1_0_init(struct amdgpu_device *adev) SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE); hub->vmhub_funcs = &mmhub_v4_1_0_vmhub_funcs; + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v4_1_0, + ARRAY_SIZE(mmhub_client_ids_v4_1_0)); } static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c new file mode 100644 index 0000000000000..29f7ed4668587 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c @@ -0,0 +1,957 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "amdgpu.h" +#include "mmhub_v4_2_0.h" + +#include "mmhub/mmhub_4_2_0_offset.h" +#include "mmhub/mmhub_4_2_0_sh_mask.h" + +#include "soc15_common.h" +#include "soc24_enum.h" + +#define regMMVM_L2_CNTL3_DEFAULT 0x80100007 +#define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 +#define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 + +static const char *mmhub_client_ids_v4_2_0[][2] = { + [0][0] = "VMC", + [4][0] = "DCEDMC", + [5][0] = "DCEVGA", + [6][0] = "MP0", + [7][0] = "MP1", + [8][0] = "MPIO", + [16][0] = "HDP", + [17][0] = "LSDMA", + [18][0] = "JPEG", + [19][0] = "VCNU0", + [21][0] = "VSCH", + [22][0] = "VCNU1", + [23][0] = "VCN1", + [32+20][0] = "VCN0", + [2][1] = "DBGUNBIO", + [3][1] = "DCEDWB", + [4][1] = "DCEDMC", + [5][1] = "DCEVGA", + [6][1] = "MP0", + [7][1] = "MP1", + [8][1] = "MPIO", + [10][1] = "DBGU0", + [11][1] = "DBGU1", + [12][1] = "DBGU2", + [13][1] = "DBGU3", + [14][1] = "XDP", + [15][1] = "OSSSYS", + [16][1] = "HDP", + [17][1] = "LSDMA", + [18][1] = "JPEG", + [19][1] = "VCNU0", + [20][1] = "VCN0", + [21][1] = "VSCH", + [22][1] = "VCNU1", + [23][1] = "VCN1", +}; + +static int mmhub_v4_2_0_get_xgmi_info(struct amdgpu_device *adev) +{ + u32 max_num_physical_nodes; + u32 max_physical_node_id; + u32 xgmi_lfb_cntl; + u32 max_region; + u64 seg_size; + + /* limit this callback to A + A configuration only */ + if (!adev->gmc.xgmi.connected_to_cpu) + return 0; + + xgmi_lfb_cntl = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), + regMMMC_VM_XGMI_LFB_CNTL); + seg_size = REG_GET_FIELD( + RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMMMC_VM_XGMI_LFB_SIZE), + MMMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; + max_region = + REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); + + max_num_physical_nodes = 4; + max_physical_node_id = 3; + + adev->gmc.xgmi.num_physical_nodes = max_region + 1; + + if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) + return -EINVAL; + + adev->gmc.xgmi.physical_node_id = + REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); + + if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) + return -EINVAL; + + adev->gmc.xgmi.node_segment_size = seg_size; + + return 0; +} + +static u64 mmhub_v4_2_0_get_fb_location(struct amdgpu_device *adev) +{ + u64 base; + + base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), + regMMMC_VM_FB_LOCATION_BASE_LO32); + base &= MMMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK; + base <<= 24; + + base |= ((u64)(MMMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK & + RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), + regMMMC_VM_FB_LOCATION_BASE_HI32)) << 56); + + return base; +} + +static u64 mmhub_v4_2_0_get_mc_fb_offset(struct amdgpu_device *adev) +{ + return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), + regMMMC_VM_FB_OFFSET) << 24; +} + +static void mmhub_v4_2_0_mid_setup_vm_pt_regs(struct amdgpu_device *adev, + uint32_t vmid, + uint64_t page_table_base, + uint32_t mid_mask) +{ + struct amdgpu_vmhub *hub; + int i; + + for_each_inst(i, mid_mask) { + hub = &adev->vmhub[AMDGPU_MMHUB0(i)]; + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, + hub->ctx_addr_distance * vmid, + lower_32_bits(page_table_base)); + + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, + hub->ctx_addr_distance * vmid, + upper_32_bits(page_table_base)); + } +} + +static void mmhub_v4_2_0_setup_vm_pt_regs(struct amdgpu_device *adev, + uint32_t vmid, + uint64_t page_table_base) +{ + uint32_t mid_mask; + + mid_mask = adev->aid_mask; + mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, vmid, + page_table_base, + mid_mask); +} + +static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + uint64_t pt_base; + int i; + + if (adev->gmc.pdb0_bo) + pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); + else + pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); + + mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, 0, pt_base, mid_mask); + + for_each_inst(i, mid_mask) { + if (adev->gmc.pdb0_bo) { + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.fb_start >> 12)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.fb_start >> 44)); + + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } else { + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, + (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, + (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, + (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, + (u32)(adev->gmc.gart_end >> 44)); + } + } +} + +static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + uint64_t value; + uint32_t tmp; + int i; + + /* + * the new L1 policy will block SRIOV guest from writing + * these regs, and they will be programed at host. + * so skip programing these regs. + */ + if (amdgpu_sriov_vf(adev)) + return; + + for_each_inst(i, mid_mask) { + if (adev->gmc.pdb0_bo) { + /* Disable agp and system aperture + * when vmid0 page table is enabled */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_TOP_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_TOP_HI32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_BASE_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_FB_LOCATION_BASE_HI32, 1); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_HI32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_HI32, 1); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + 0x7F); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); + } else { + /* Program the AGP BAR */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BASE_LO32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BASE_HI32, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_LO32, + lower_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_BOT_HI32, + upper_32_bits(adev->gmc.agp_start >> 24)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_LO32, + lower_32_bits(adev->gmc.agp_end >> 24)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_AGP_TOP_HI32, + upper_32_bits(adev->gmc.agp_end >> 24)); + + /* Program the system aperture low logical page number. */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, + lower_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, + upper_32_bits(min(adev->gmc.fb_start, + adev->gmc.agp_start) >> 18)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, + lower_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, + upper_32_bits(max(adev->gmc.fb_end, + adev->gmc.agp_end) >> 18)); + } + + /* Set default page address. */ + value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, + (u32)(value >> 44)); + + /* Program "protection fault". */ + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, + (u32)(adev->dummy_page_addr >> 12)); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, + (u32)((u64)adev->dummy_page_addr >> 44)); + + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_CNTL2); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, + ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, + ENABLE_RETRY_FAULT_INTERRUPT, 0x1); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); + } +} + +static void mmhub_v4_2_0_mid_init_tlb_regs(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + uint32_t tmp; + int i; + + for_each_inst(i, mid_mask) { + /* Setup TLB control */ + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_MX_L1_TLB_CNTL); + + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 1); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + MTYPE, MTYPE_UC); /* UC, uncached */ + + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMMC_VM_MX_L1_TLB_CNTL, tmp); + } +} + +static void mmhub_v4_2_0_mid_init_cache_regs(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + uint32_t tmp; + int i; + + /* These registers are not accessible to VF-SRIOV. + * The PF will program them instead. + */ + if (amdgpu_sriov_vf(adev)) + return; + + for_each_inst(i, mid_mask) { + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, + ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); + /* XXX for emulation, Refer to closed source code.*/ + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, + L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, + PDE_FAULT_CLASSIFICATION, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, + CONTEXT1_IDENTITY_ACCESS_MODE, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, + IDENTITY_MODE_FRAGMENT_SIZE, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL, tmp); + + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, + INVALIDATE_ALL_L1_TLBS, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, + INVALIDATE_L2_CACHE, 1); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2, tmp); + + tmp = regMMVM_L2_CNTL3_DEFAULT; + if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); + } else { + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); + } + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL3, tmp); + + tmp = regMMVM_L2_CNTL4_DEFAULT; + /* For AMD APP APUs setup WC memory */ + if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) { + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 1); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 1); + } else { + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, + VMC_TAP_PDE_REQUEST_PHYSICAL, 0); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, + VMC_TAP_PTE_REQUEST_PHYSICAL, 0); + } + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL4, tmp); + + tmp = regMMVM_L2_CNTL5_DEFAULT; + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, + L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL5, tmp); + } +} + +static void mmhub_v4_2_0_mid_enable_system_domain(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + uint32_t tmp; + int i; + + for_each_inst(i, mid_mask) { + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, + ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, + PAGE_TABLE_DEPTH, adev->gmc.vmid0_page_table_depth); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, + PAGE_TABLE_BLOCK_SIZE, + adev->gmc.vmid0_page_table_block_size); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_CNTL, tmp); + } +} + +static void mmhub_v4_2_0_mid_disable_identity_aperture(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + int i; + + /* These registers are not accessible to VF-SRIOV. + * The PF will program them instead. + */ + if (amdgpu_sriov_vf(adev)) + return; + + for_each_inst(i, mid_mask) { + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, + 0xFFFFFFFF); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, + 0x00001FFF); + + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, + 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, + 0); + + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, + 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, + 0); + } +} + +static void mmhub_v4_2_0_mid_setup_vmid_config(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + struct amdgpu_vmhub *hub; + uint32_t tmp; + int i, j; + + for_each_inst(j, mid_mask) { + hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; + for (i = 0; i <= 14; i++) { + tmp = RREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), + regMMVM_CONTEXT1_CNTL, + i * hub->ctx_distance); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, + adev->vm_manager.num_level); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, + 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + PAGE_TABLE_BLOCK_SIZE, + adev->vm_manager.block_size - 9); + /* Send no-retry XNACK on fault to suppress VM fault storm. */ + tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, + RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, + !amdgpu_noretry); + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_CNTL, + i * hub->ctx_distance, tmp); + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, + i * hub->ctx_addr_distance, 0); + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, + i * hub->ctx_addr_distance, + lower_32_bits(adev->vm_manager.max_pfn - 1)); + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, + i * hub->ctx_addr_distance, + upper_32_bits(adev->vm_manager.max_pfn - 1)); + } + } + + hub->vm_cntx_cntl = tmp; +} + +static void mmhub_v4_2_0_mid_program_invalidation(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + struct amdgpu_vmhub *hub; + unsigned int i, j; + + for_each_inst(j, mid_mask) { + hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; + + for (i = 0; i < 18; ++i) { + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), + regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, + i * hub->eng_addr_distance, 0xffffffff); + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), + regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, + i * hub->eng_addr_distance, 0x3fff); + } + } +} + +static int mmhub_v4_2_0_mid_gart_enable(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + /* GART Enable. */ + mmhub_v4_2_0_mid_init_gart_aperture_regs(adev, mid_mask); + mmhub_v4_2_0_mid_init_system_aperture_regs(adev, mid_mask); + mmhub_v4_2_0_mid_init_tlb_regs(adev, mid_mask); + mmhub_v4_2_0_mid_init_cache_regs(adev, mid_mask); + + mmhub_v4_2_0_mid_enable_system_domain(adev, mid_mask); + mmhub_v4_2_0_mid_disable_identity_aperture(adev, mid_mask); + mmhub_v4_2_0_mid_setup_vmid_config(adev, mid_mask); + mmhub_v4_2_0_mid_program_invalidation(adev, mid_mask); + + return 0; +} +static int mmhub_v4_2_0_gart_enable(struct amdgpu_device *adev) +{ + uint32_t mid_mask; + + mid_mask = adev->aid_mask; + return mmhub_v4_2_0_mid_gart_enable(adev, mid_mask); +} + +static void mmhub_v4_2_0_mid_gart_disable(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + struct amdgpu_vmhub *hub; + u32 tmp; + u32 i, j; + + for_each_inst(j, mid_mask) { + hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; + /* Disable all tables */ + for (i = 0; i < 16; i++) + WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), + regMMVM_CONTEXT0_CNTL, + i * hub->ctx_distance, 0); + + /* Setup TLB control */ + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), + regMMMC_VM_MX_L1_TLB_CNTL); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + ENABLE_L1_TLB, 0); + tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, + ENABLE_ADVANCED_DRIVER_MODEL, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), + regMMMC_VM_MX_L1_TLB_CNTL, tmp); + + /* Setup L2 cache */ + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL); + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL, tmp); + WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL3, 0); + } +} + +static void mmhub_v4_2_0_gart_disable(struct amdgpu_device *adev) +{ + uint32_t mid_mask; + + mid_mask = adev->aid_mask; + mmhub_v4_2_0_mid_gart_disable(adev, mid_mask); +} + +static void +mmhub_v4_2_0_mid_set_fault_enable_default(struct amdgpu_device *adev, + bool value, uint32_t mid_mask) +{ + u32 tmp; + int i; + + /* These registers are not accessible to VF-SRIOV. + * The PF will program them instead. + */ + if (amdgpu_sriov_vf(adev)) + return; + + for_each_inst(i, mid_mask) { + tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_CNTL_LO32); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, + value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + if (!value) { + tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, + CRASH_ON_NO_RETRY_FAULT, 1); + } + WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_CNTL_LO32, tmp); + } +} + + +/** + * mmhub_v4_2_0_set_fault_enable_default - update GART/VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +static void +mmhub_v4_2_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value) +{ + uint32_t mid_mask; + + mid_mask = adev->aid_mask; + mmhub_v4_2_0_mid_set_fault_enable_default(adev, value, mid_mask); +} + +static uint32_t mmhub_v4_2_0_get_invalidate_req(unsigned int vmid, + uint32_t flush_type) +{ + u32 req = 0; + + /* invalidate using legacy mode on vmid*/ + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, + PER_VMID_INVALIDATE_REQ, 1 << vmid); + /* Only use legacy inv on mmhub side */ + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE3, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); + req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, + CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); + + return req; +} + +/*TODO: l2 protection fault status is increased to 64bits. + * some critical fields like FED are moved to STATUS_HI32 */ +static void +mmhub_v4_2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, + uint32_t status) +{ + uint32_t cid, rw; + const char *mmhub_cid; + + cid = REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); + rw = REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW); + + dev_err(adev->dev, + "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", + status); + mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); + dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", + mmhub_cid ? mmhub_cid : "unknown", cid); + dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); + dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); + dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); + dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", + REG_GET_FIELD(status, + MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); + dev_err(adev->dev, "\t RW: 0x%x\n", rw); +} + + +static const struct amdgpu_vmhub_funcs mmhub_v4_2_0_vmhub_funcs = { + .print_l2_protection_fault_status = mmhub_v4_2_0_print_l2_protection_fault_status, + .get_invalidate_req = mmhub_v4_2_0_get_invalidate_req, +}; + +static void mmhub_v4_2_0_mid_init(struct amdgpu_device *adev, + uint32_t mid_mask) +{ + struct amdgpu_vmhub *hub; + int i; + + for_each_inst(i, mid_mask) { + hub = &adev->vmhub[AMDGPU_MMHUB0(i)]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); + hub->ctx0_ptb_addr_hi32 = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); + hub->vm_inv_eng0_sem = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_INVALIDATE_ENG0_SEM); + hub->vm_inv_eng0_req = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_INVALIDATE_ENG0_REQ); + hub->vm_inv_eng0_ack = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_INVALIDATE_ENG0_ACK); + hub->vm_context0_cntl = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_CONTEXT0_CNTL); + /* TODO: add a new member to accomandate additional fault status/cntl reg */ + hub->vm_l2_pro_fault_status = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_STATUS_LO32); + hub->vm_l2_pro_fault_cntl = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), + regMMVM_L2_PROTECTION_FAULT_CNTL_LO32); + + hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; + hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - + regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; + hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - + regMMVM_INVALIDATE_ENG0_REQ; + hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - + regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; + + hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; + + hub->vm_l2_bank_select_reserved_cid2 = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_BANK_SELECT_RESERVED_CID2); + + hub->vm_contexts_disable = + SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXTS_DISABLE); + + hub->vmhub_funcs = &mmhub_v4_2_0_vmhub_funcs; + } +} + +static void mmhub_v4_2_0_init(struct amdgpu_device *adev) +{ + uint32_t mid_mask; + + mid_mask = adev->aid_mask; + mmhub_v4_2_0_mid_init(adev, mid_mask); + + amdgpu_mmhub_init_client_info(&adev->mmhub, + mmhub_client_ids_v4_2_0, + ARRAY_SIZE(mmhub_client_ids_v4_2_0)); +} + +static void +mmhub_v4_2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + uint32_t def1, data1, def2 = 0, data2 = 0; + def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG); + def1 = data1 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2); + def2 = data2 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2); + + if (enable) { + data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; + data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); + + data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); + } else { + data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; + data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | + DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); + + data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | + DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); + } + + if (def != data) + WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data); + if (def1 != data1) + WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2, data1); + + if (def2 != data2) + WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2, data2); +} + +static void +mmhub_v4_2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, + bool enable) +{ + uint32_t def, data; + + def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG); + + if (enable) + data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; + else + data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; + + if (def != data) + WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data); +} + +static int mmhub_v4_2_0_set_clockgating(struct amdgpu_device *adev, + enum amd_clockgating_state state) +{ + if (amdgpu_sriov_vf(adev)) + return 0; + + if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) + mmhub_v4_2_0_update_medium_grain_clock_gating(adev, + state == AMD_CG_STATE_GATE); + + if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) + mmhub_v4_2_0_update_medium_grain_light_sleep(adev, + state == AMD_CG_STATE_GATE); + + return 0; +} + +static void mmhub_v4_2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) +{ + int data; + + if (amdgpu_sriov_vf(adev)) + *flags = 0; + + data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG); + + /* AMD_CG_SUPPORT_MC_MGCG */ + if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_MC_MGCG; + + /* AMD_CG_SUPPORT_MC_LS */ + if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) + *flags |= AMD_CG_SUPPORT_MC_LS; +} + +const struct amdgpu_mmhub_funcs mmhub_v4_2_0_funcs = { + .init = mmhub_v4_2_0_init, + .get_fb_location = mmhub_v4_2_0_get_fb_location, + .get_mc_fb_offset = mmhub_v4_2_0_get_mc_fb_offset, + .setup_vm_pt_regs = mmhub_v4_2_0_setup_vm_pt_regs, + .gart_enable = mmhub_v4_2_0_gart_enable, + .gart_disable = mmhub_v4_2_0_gart_disable, + .set_fault_enable_default = mmhub_v4_2_0_set_fault_enable_default, + .set_clockgating = mmhub_v4_2_0_set_clockgating, + .get_clockgating = mmhub_v4_2_0_get_clockgating, + .get_xgmi_info = mmhub_v4_2_0_get_xgmi_info, +}; + +static int mmhub_v4_2_0_xcp_resume(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + bool value; + + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) + value = false; + else + value = true; + + mmhub_v4_2_0_mid_set_fault_enable_default(adev, value, inst_mask); + + if (!amdgpu_sriov_vf(adev)) + return mmhub_v4_2_0_mid_gart_enable(adev, inst_mask); + + return 0; +} + +static int mmhub_v4_2_0_xcp_suspend(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (!amdgpu_sriov_vf(adev)) + mmhub_v4_2_0_mid_gart_disable(adev, inst_mask); + + return 0; +} + +struct amdgpu_xcp_ip_funcs mmhub_v4_2_0_xcp_funcs = { + .suspend = &mmhub_v4_2_0_xcp_suspend, + .resume = &mmhub_v4_2_0_xcp_resume +}; diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.h b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.h new file mode 100644 index 0000000000000..4ea6de7ac7ae7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.h @@ -0,0 +1,28 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __MMHUB_V4_2_0_H__ +#define __MMHUB_V4_2_0_H__ + +extern const struct amdgpu_mmhub_funcs mmhub_v4_2_0_funcs; + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index e7cd07383d56e..f2e456390b27e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -96,7 +96,9 @@ static int xgpu_nv_poll_ack(struct amdgpu_device *adev) timeout -= 5; } while (timeout > 1); - dev_err(adev->dev, "Doesn't get TRN_MSG_ACK from pf in %d msec \n", NV_MAILBOX_POLL_ACK_TIMEDOUT); + dev_err(adev->dev, + "Doesn't get TRN_MSG_ACK from pf in %d msec\n", + NV_MAILBOX_POLL_ACK_TIMEDOUT); return -ETIME; } @@ -209,6 +211,9 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, case IDH_REQ_RAS_CHK_CRITI: event = IDH_REQ_RAS_CHK_CRITI_READY; break; + case IDH_REQ_RAS_REMOTE_CMD: + event = IDH_REQ_RAS_REMOTE_CMD_READY; + break; default: break; } @@ -585,6 +590,13 @@ static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr adev, IDH_REQ_RAS_CHK_CRITI, addr_hi, addr_lo, 0); } +static int xgpu_nv_req_remote_ras_cmd(struct amdgpu_device *adev, + u32 param1, u32 param2, u32 param3) +{ + return xgpu_nv_send_access_requests_with_param( + adev, IDH_REQ_RAS_REMOTE_CMD, param1, param2, param3); +} + const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_full_gpu = xgpu_nv_request_full_gpu_access, .rel_full_gpu = xgpu_nv_release_full_gpu_access, @@ -598,5 +610,6 @@ const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_ras_err_count = xgpu_nv_req_ras_err_count, .req_ras_cper_dump = xgpu_nv_req_ras_cper_dump, .req_bad_pages = xgpu_nv_req_ras_bad_pages, - .req_ras_chk_criti = xgpu_nv_check_vf_critical_region + .req_ras_chk_criti = xgpu_nv_check_vf_critical_region, + .req_remote_ras_cmd = xgpu_nv_req_remote_ras_cmd, }; diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h index c1083e5e41e02..dc57a4f697eec 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h @@ -43,7 +43,8 @@ enum idh_request { IDH_REQ_RAS_ERROR_COUNT = 203, IDH_REQ_RAS_CPER_DUMP = 204, IDH_REQ_RAS_BAD_PAGES = 205, - IDH_REQ_RAS_CHK_CRITI = 206 + IDH_REQ_RAS_CHK_CRITI = 206, + IDH_REQ_RAS_REMOTE_CMD = 207, }; enum idh_event { @@ -64,6 +65,7 @@ enum idh_event { IDH_RAS_BAD_PAGES_NOTIFICATION = 16, IDH_UNRECOV_ERR_NOTIFICATION = 17, IDH_REQ_RAS_CHK_CRITI_READY = 18, + IDH_REQ_RAS_REMOTE_CMD_READY = 19, IDH_TEXT_MESSAGE = 255, }; diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c index 9b4025c39e440..db14a1a326d20 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c @@ -30,6 +30,31 @@ #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" #include +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6 +#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3 + static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) { WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, @@ -98,7 +123,11 @@ static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, S2A_DOORBELL_PORT2_RANGE_SIZE, 0); - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); + } else { + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); + } } } @@ -140,16 +169,28 @@ static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, S2A_DOORBELL_PORT4_RANGE_SIZE, 0); - if (instance) - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); - else - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { + if (instance) + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); + else + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); + } else { + if (instance) + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); + else + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); + } } static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) { - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); + } else { + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); + } } static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, @@ -214,7 +255,11 @@ static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, S2A_DOORBELL_PORT1_RANGE_SIZE, 0); - WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, ih_doorbell_range); + } else { + WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); + } } static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) @@ -269,12 +314,20 @@ static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) { - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); + } + else { + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); + } } static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) { - return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); + if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); + else + return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); } const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = { diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c index bed5ef4d87889..05cbd65420d2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c @@ -279,6 +279,7 @@ static void nbio_v7_11_init_registers(struct amdgpu_device *adev) case IP_VERSION(7, 11, 1): case IP_VERSION(7, 11, 2): case IP_VERSION(7, 11, 3): + case IP_VERSION(7, 11, 4): data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4) & ~BIT(23); WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF5_STRAP4, data); break; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 50e77d9b30afa..7ce1a1b956065 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -283,10 +283,10 @@ static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); r = RREG32(data); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -297,10 +297,10 @@ static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 nv_get_config_memsize(struct amdgpu_device *adev) @@ -593,10 +593,6 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev) adev->doorbell_index.sdma_doorbell_range = 20; } -static void nv_pre_asic_init(struct amdgpu_device *adev) -{ -} - static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, bool enter) { @@ -630,7 +626,6 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = { .need_reset_on_init = &nv_need_reset_on_init, .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, .supports_baco = &amdgpu_dpm_is_baco_supported, - .pre_asic_init = &nv_pre_asic_init, .update_umd_stable_pstate = &nv_update_umd_stable_pstate, .query_video_codecs = &nv_query_video_codecs, }; @@ -640,21 +635,15 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - - /* TODO: will add them during VCN v2 implementation */ - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; - - adev->didt_rreg = &nv_didt_rreg; - adev->didt_wreg = &nv_didt_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; + + adev->reg.didt.rreg = &nv_didt_rreg; + adev->reg.didt.wreg = &nv_didt_wreg; adev->asic_funcs = &nv_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 73f87131a7e9f..c52ba7c94bf4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -299,6 +299,8 @@ enum psp_gfx_fw_type { GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */ GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */ GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */ + GFX_FW_TYPE_RLX6_UCODE_CORE1 = 98, /* RLCV_IRAM MI */ + GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1 = 99, /* RLCV DRAM BOOT MI */ GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */ GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */ GFX_FW_TYPE_VPE = 102, @@ -359,7 +361,7 @@ struct psp_gfx_cmd_sriov_spatial_part { /*Structure for sq performance monitoring/profiling enable/disable*/ struct psp_gfx_cmd_config_sq_perfmon { - uint32_t gfx_xcp_mask; + uint32_t gfx_xcc_mask; uint8_t core_override; uint8_t reg_override; uint8_t perfmon_override; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c index 3584b8c18fd99..8a6431487ed04 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c @@ -140,7 +140,7 @@ static int psp_v10_0_ring_destroy(struct psp_context *psp, static int psp_v10_0_mode1_reset(struct psp_context *psp) { - DRM_INFO("psp mode 1 reset not supported now! \n"); + drm_info(adev_to_drm(psp->adev), "psp mode 1 reset not supported now!\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c index a9be7a5050268..9aa988982304b 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c @@ -412,7 +412,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp) MBOX_TOS_READY_MASK, 0); if (ret) { - DRM_INFO("psp is not working correctly before mode1 reset!\n"); + drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c index 4c6450d62299a..c3cae29eeca1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c @@ -225,7 +225,7 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp) MBOX_TOS_READY_MASK, 0); if (ret) { - DRM_INFO("psp is not working correctly before mode1 reset!\n"); + drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); return -EINVAL; } @@ -240,11 +240,11 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp) 0); if (ret) { - DRM_INFO("psp mode 1 reset failed!\n"); + drm_info(adev_to_drm(adev), "psp mode 1 reset failed!\n"); return -EINVAL; } - DRM_INFO("psp mode1 reset succeed \n"); + drm_info(adev_to_drm(adev), "psp mode1 reset succeed\n"); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index af4a7d7c4abd8..a0c84f81c0c9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -57,6 +57,8 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_15_sos.bin"); +MODULE_FIRMWARE("amdgpu/psp_13_0_15_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); @@ -121,6 +123,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp) case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 12): case IP_VERSION(13, 0, 14): + case IP_VERSION(13, 0, 15): err = psp_init_sos_microcode(psp, ucode_prefix); if (err) return err; @@ -156,13 +159,14 @@ static void psp_v13_0_bootloader_print_status(struct psp_context *psp, if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) { at = 0; for_each_inst(i, adev->aid_mask) { bl_status_reg = (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92) << 2) + - adev->asic_funcs->encode_ext_smn_addressing(i); + amdgpu_reg_get_smn_base64(adev, MP0_HWIP, i); at += snprintf(bl_status_msg + at, PSP13_BL_STATUS_SIZE - at, " status(%02i): 0x%08x", i, @@ -202,7 +206,8 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) retry_cnt = ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))) ? PSP_VMBX_POLLING_LIMIT : 10; /* Wait for bootloader to signify that it is ready having bit 31 of @@ -232,7 +237,8 @@ static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) { ret = psp_v13_0_wait_for_vmbx_ready(psp); if (ret) amdgpu_ras_query_boot_status(adev, 4); @@ -872,7 +878,8 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp) if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || - amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || + amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) && (!(adev->flags & AMD_IS_APU))) { reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c new file mode 100644 index 0000000000000..73a709773e85b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c @@ -0,0 +1,206 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_psp.h" +#include "amdgpu_ucode.h" +#include "soc15_common.h" +#include "psp_v15_0.h" + +#include "mp/mp_15_0_0_offset.h" +#include "mp/mp_15_0_0_sh_mask.h" + +MODULE_FIRMWARE("amdgpu/psp_15_0_0_toc.bin"); + +static int psp_v15_0_0_init_microcode(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + char ucode_prefix[30]; + int err = 0; + + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); + + err = psp_init_toc_microcode(psp, ucode_prefix); + if (err) + return err; + + err = psp_init_ta_microcode(psp, ucode_prefix); + if (err) + return err; + + return 0; +} + +static int psp_v15_0_0_ring_stop(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + /* Write the ring destroy command*/ + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + /* Wait for response flag (bit 31) */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), + 0x80000000, 0x80000000, false); + } else { + /* Write the ring destroy command*/ + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, + GFX_CTRL_CMD_ID_DESTROY_RINGS); + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + /* Wait for response flag (bit 31) */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), + 0x80000000, 0x80000000, false); + } + + return ret; +} + +static int psp_v15_0_0_ring_create(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + unsigned int psp_ring_reg = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + ret = psp_v15_0_0_ring_stop(psp, ring_type); + if (ret) { + DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); + return ret; + } + + /* Write low address of the ring to C2PMSG_102 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); + /* Write high address of the ring to C2PMSG_103 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); + + /* Write the ring initialization command to C2PMSG_101 */ + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_INIT_GPCOM_RING); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_101 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), + 0x80000000, 0x8000FFFF, false); + + } else { + /* Wait for sOS ready for ring creation */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), + 0x80000000, 0x80000000, false); + if (ret) { + DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); + return ret; + } + + /* Write low address of the ring to C2PMSG_69 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg); + /* Write high address of the ring to C2PMSG_70 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg); + /* Write size of ring to C2PMSG_71 */ + psp_ring_reg = ring->ring_size; + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg); + /* Write the ring initialization command to C2PMSG_64 */ + psp_ring_reg = ring_type; + psp_ring_reg = psp_ring_reg << 16; + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_64 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64), + 0x80000000, 0x8000FFFF, false); + } + + return ret; +} + +static int psp_v15_0_0_ring_destroy(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + ret = psp_v15_0_0_ring_stop(psp, ring_type); + if (ret) + DRM_ERROR("Fail to stop psp ring\n"); + + amdgpu_bo_free_kernel(&adev->firmware.rbuf, + &ring->ring_mem_mc_addr, + (void **)&ring->ring_mem); + + return ret; +} + +static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp) +{ + uint32_t data; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) + data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); + else + data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67); + + return data; +} + +static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_CONSUME_CMD); + } else + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value); +} + +static const struct psp_funcs psp_v15_0_0_funcs = { + .init_microcode = psp_v15_0_0_init_microcode, + .ring_create = psp_v15_0_0_ring_create, + .ring_stop = psp_v15_0_0_ring_stop, + .ring_destroy = psp_v15_0_0_ring_destroy, + .ring_get_wptr = psp_v15_0_0_ring_get_wptr, + .ring_set_wptr = psp_v15_0_0_ring_set_wptr, +}; + +void psp_v15_0_0_set_psp_funcs(struct psp_context *psp) +{ + psp->funcs = &psp_v15_0_0_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h new file mode 100644 index 0000000000000..ebd612103526f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.h @@ -0,0 +1,30 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __PSP_V15_0_0_H__ +#define __PSP_V15_0_0_H__ + +#include "amdgpu_psp.h" + +void psp_v15_0_0_set_psp_funcs(struct psp_context *psp); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c new file mode 100644 index 0000000000000..b2d7cbd894c03 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c @@ -0,0 +1,363 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include +#include +#include "amdgpu.h" +#include "amdgpu_psp.h" +#include "amdgpu_ucode.h" +#include "soc15_common.h" +#include "psp_v15_0_8.h" + +#include "mp/mp_15_0_8_offset.h" +#include "mp/mp_15_0_8_sh_mask.h" + +MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin"); + +static int psp_v15_0_8_init_microcode(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + char ucode_prefix[30]; + int err = 0; + + amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); + + err = psp_init_toc_microcode(psp, ucode_prefix); + if (err) + return err; + + return 0; +} + +static int psp_v15_0_8_ring_stop(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + /* Write the ring destroy command*/ + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + /* Wait for response flag (bit 31) */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), + 0x80000000, 0x80000000, false); + } else { + /* Write the ring destroy command*/ + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, + GFX_CTRL_CMD_ID_DESTROY_RINGS); + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + /* Wait for response flag (bit 31) */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), + 0x80000000, 0x80000000, false); + } + + return ret; +} + +static int psp_v15_0_8_ring_create(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + unsigned int psp_ring_reg = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + ret = psp_v15_0_8_ring_stop(psp, ring_type); + if (ret) { + DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); + return ret; + } + + /* Write low address of the ring to C2PMSG_102 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); + /* Write high address of the ring to C2PMSG_103 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); + + /* Write the ring initialization command to C2PMSG_101 */ + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_INIT_GPCOM_RING); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_101 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), + 0x80000000, 0x8000FFFF, false); + + } else { + /* Wait for sOS ready for ring creation */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), + 0x80000000, 0x80000000, false); + if (ret) { + DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); + return ret; + } + + /* Write low address of the ring to C2PMSG_69 */ + psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); + /* Write high address of the ring to C2PMSG_70 */ + psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); + /* Write size of ring to C2PMSG_71 */ + psp_ring_reg = ring->ring_size; + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); + /* Write the ring initialization command to C2PMSG_64 */ + psp_ring_reg = ring_type; + psp_ring_reg = psp_ring_reg << 16; + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); + + /* there might be handshake issue with hardware which needs delay */ + mdelay(20); + + /* Wait for response flag (bit 31) in C2PMSG_64 */ + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), + 0x80000000, 0x8000FFFF, false); + } + + return ret; +} + +static int psp_v15_0_8_ring_destroy(struct psp_context *psp, + enum psp_ring_type ring_type) +{ + int ret = 0; + struct psp_ring *ring = &psp->km_ring; + struct amdgpu_device *adev = psp->adev; + + ret = psp_v15_0_8_ring_stop(psp, ring_type); + if (ret) + DRM_ERROR("Fail to stop psp ring\n"); + + amdgpu_bo_free_kernel(&adev->firmware.rbuf, + &ring->ring_mem_mc_addr, + (void **)&ring->ring_mem); + + return ret; +} + +static uint32_t psp_v15_0_8_ring_get_wptr(struct psp_context *psp) +{ + uint32_t data; + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) + data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); + else + data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); + + return data; +} + +static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value) +{ + struct amdgpu_device *adev = psp->adev; + + if (amdgpu_sriov_vf(adev)) { + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, + GFX_CTRL_CMD_ID_CONSUME_CMD); + } else + WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); +} + +static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + u32 reg_data; + + /* query ras cap should be done from host side */ + if (amdgpu_sriov_vf(adev)) + return false; + + if (!con) + return false; + + reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127); + adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); + con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; + + return true; +} + +static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode, + enum psp_gfx_fw_type *type) +{ + switch (ucode->ucode_id) { + case AMDGPU_UCODE_ID_CAP: + *type = GFX_FW_TYPE_CAP; + break; + case AMDGPU_UCODE_ID_SDMA0: + *type = GFX_FW_TYPE_SDMA0; + break; + case AMDGPU_UCODE_ID_SDMA1: + *type = GFX_FW_TYPE_SDMA1; + break; + case AMDGPU_UCODE_ID_SDMA2: + *type = GFX_FW_TYPE_SDMA2; + break; + case AMDGPU_UCODE_ID_SDMA3: + *type = GFX_FW_TYPE_SDMA3; + break; + case AMDGPU_UCODE_ID_SDMA4: + *type = GFX_FW_TYPE_SDMA4; + break; + case AMDGPU_UCODE_ID_SDMA5: + *type = GFX_FW_TYPE_SDMA5; + break; + case AMDGPU_UCODE_ID_SDMA6: + *type = GFX_FW_TYPE_SDMA6; + break; + case AMDGPU_UCODE_ID_SDMA7: + *type = GFX_FW_TYPE_SDMA7; + break; + case AMDGPU_UCODE_ID_CP_MES: + *type = GFX_FW_TYPE_RS64_MES; + break; + case AMDGPU_UCODE_ID_CP_MES_DATA: + *type = GFX_FW_TYPE_RS64_MES_STACK; + break; + case AMDGPU_UCODE_ID_CP_MES1: + *type = GFX_FW_TYPE_RS64_KIQ; + break; + case AMDGPU_UCODE_ID_CP_MES1_DATA: + *type = GFX_FW_TYPE_RS64_KIQ_STACK; + break; + case AMDGPU_UCODE_ID_RLC_P: + *type = GFX_FW_TYPE_RLC_P; + break; + case AMDGPU_UCODE_ID_RLC_V: + *type = GFX_FW_TYPE_RLC_V; + break; + case AMDGPU_UCODE_ID_RLC_G: + *type = GFX_FW_TYPE_RLC_G; + break; + case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: + *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; + break; + case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: + *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; + break; + case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: + *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; + break; + case AMDGPU_UCODE_ID_RLC_IRAM: + *type = GFX_FW_TYPE_RLC_IRAM; + break; + case AMDGPU_UCODE_ID_RLC_DRAM: + *type = GFX_FW_TYPE_RLC_DRAM_BOOT; + break; + case AMDGPU_UCODE_ID_RLC_IRAM_1: + *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; + break; + case AMDGPU_UCODE_ID_RLC_DRAM_1: + *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; + break; + case AMDGPU_UCODE_ID_SMC: + *type = GFX_FW_TYPE_SMU; + break; + case AMDGPU_UCODE_ID_PPTABLE: + *type = GFX_FW_TYPE_PPTABLE; + break; + case AMDGPU_UCODE_ID_VCN: + *type = GFX_FW_TYPE_VCN; + break; + case AMDGPU_UCODE_ID_VCN1: + *type = GFX_FW_TYPE_VCN1; + break; + case AMDGPU_UCODE_ID_VCN0_RAM: + *type = GFX_FW_TYPE_VCN0_RAM; + break; + case AMDGPU_UCODE_ID_VCN1_RAM: + *type = GFX_FW_TYPE_VCN1_RAM; + break; + case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: + case AMDGPU_UCODE_ID_SDMA_RS64: + *type = GFX_FW_TYPE_SDMA0; + break; + case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: + *type = GFX_FW_TYPE_SDMA_UCODE_TH1; + break; + case AMDGPU_UCODE_ID_IMU_I: + *type = GFX_FW_TYPE_IMU_I; + break; + case AMDGPU_UCODE_ID_IMU_D: + *type = GFX_FW_TYPE_IMU_D; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC: + *type = GFX_FW_TYPE_RS64_MEC; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; + break; + case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: + *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; + break; + case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: + *type = GFX_FW_TYPE_UMSCH_UCODE; + break; + case AMDGPU_UCODE_ID_UMSCH_MM_DATA: + *type = GFX_FW_TYPE_UMSCH_DATA; + break; + case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: + *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; + break; + case AMDGPU_UCODE_ID_P2S_TABLE: + *type = GFX_FW_TYPE_P2S_TABLE; + break; + case AMDGPU_UCODE_ID_MAXIMUM: + default: + return -EINVAL; + } + + return 0; +} + +static const struct psp_funcs psp_v15_0_8_funcs = { + .init_microcode = psp_v15_0_8_init_microcode, + .ring_create = psp_v15_0_8_ring_create, + .ring_stop = psp_v15_0_8_ring_stop, + .ring_destroy = psp_v15_0_8_ring_destroy, + .ring_get_wptr = psp_v15_0_8_ring_get_wptr, + .ring_set_wptr = psp_v15_0_8_ring_set_wptr, + .get_fw_type = psp_v15_0_8_get_fw_type, + .get_ras_capability = psp_v15_0_8_get_ras_capability, +}; + +void psp_v15_0_8_set_psp_funcs(struct psp_context *psp) +{ + psp->funcs = &psp_v15_0_8_funcs; +} diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.h b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.h new file mode 100644 index 0000000000000..6bb1bb517007b --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.h @@ -0,0 +1,30 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __PSP_V15_0_8_H__ +#define __PSP_V15_0_8_H__ + +#include "amdgpu_psp.h" + +void psp_v15_0_8_set_psp_funcs(struct psp_context *psp); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c index 833830bc3e2e3..f5030efc6c804 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c @@ -315,7 +315,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp) ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0); if (ret) { - DRM_INFO("psp is not working correctly before mode1 reset!\n"); + drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); return -EINVAL; } @@ -329,11 +329,11 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp) ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0); if (ret) { - DRM_INFO("psp mode 1 reset failed!\n"); + drm_info(adev_to_drm(adev), "psp mode 1 reset failed!\n"); return -EINVAL; } - DRM_INFO("psp mode1 reset succeed \n"); + drm_info(adev_to_drm(adev), "psp mode1 reset succeed\n"); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 92ce580647cdc..0090ace49024f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -51,7 +51,6 @@ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); @@ -809,6 +808,14 @@ static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } +static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v2_4_vm_copy_pte, + + .write_pte = sdma_v2_4_vm_write_pte, + .set_pte_pde = sdma_v2_4_vm_set_pte_pde, +}; + static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -822,7 +829,7 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) sdma_v2_4_set_ring_funcs(adev); sdma_v2_4_set_buffer_funcs(adev); - sdma_v2_4_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs); sdma_v2_4_set_irq_funcs(adev); return 0; @@ -1232,26 +1239,6 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v2_4_vm_copy_pte, - - .write_pte = sdma_v2_4_vm_write_pte, - .set_pte_pde = sdma_v2_4_vm_set_pte_pde, -}; - -static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v2_4_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 2, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 1c076bd1cf73e..2526d393162ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -51,7 +51,6 @@ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); @@ -1082,6 +1081,14 @@ static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } +static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v3_0_vm_copy_pte, + + .write_pte = sdma_v3_0_vm_write_pte, + .set_pte_pde = sdma_v3_0_vm_set_pte_pde, +}; + static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1102,7 +1109,7 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v3_0_set_ring_funcs(adev); sdma_v3_0_set_buffer_funcs(adev); - sdma_v3_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs); sdma_v3_0_set_irq_funcs(adev); return 0; @@ -1674,26 +1681,6 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v3_0_vm_copy_pte, - - .write_pte = sdma_v3_0_vm_write_pte, - .set_pte_pde = sdma_v3_0_vm_set_pte_pde, -}; - -static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v3_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index f38004e6064e5..64fef615642cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -129,7 +129,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_0[] = { static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_0_set_ras_funcs(struct amdgpu_device *adev); @@ -1068,6 +1067,7 @@ static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) /* Set ring buffer size in dwords */ uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); + barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); @@ -1751,6 +1751,14 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) } } +static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v4_0_vm_copy_pte, + + .write_pte = sdma_v4_0_vm_write_pte, + .set_pte_pde = sdma_v4_0_vm_set_pte_pde, +}; + static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1769,7 +1777,7 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v4_0_set_ring_funcs(adev); sdma_v4_0_set_buffer_funcs(adev); - sdma_v4_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs); sdma_v4_0_set_irq_funcs(adev); sdma_v4_0_set_ras_funcs(adev); @@ -2170,7 +2178,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, instance = sdma_v4_0_irq_id_to_seq(entry->client_id); if (instance < 0 || instance >= adev->sdma.num_instances) { - dev_err(adev->dev, "sdma instance invalid %d\n", instance); + dev_err_ratelimited(adev->dev, "sdma instance invalid %d\n", instance); return -EINVAL; } @@ -2597,48 +2605,37 @@ static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 22, .copy_num_dw = 7, .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 22, + .fill_num_dw = 5, + .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, +}; + +static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = { + .copy_max_bytes = 1 << 30, + .copy_num_dw = 7, + .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, + + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, }; static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) { - adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; + if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0)) + adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs; + else + adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; if (adev->sdma.has_page_queue) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page; else adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v4_0_vm_copy_pte, - - .write_pte = sdma_v4_0_vm_write_pte, - .set_pte_pde = sdma_v4_0_vm_set_pte_pde, -}; - -static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - struct drm_gpu_scheduler *sched; - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - if (adev->sdma.has_page_queue) - sched = &adev->sdma.instance[i].page.sched; - else - sched = &adev->sdma.instance[i].ring.sched; - adev->vm_manager.vm_pte_scheds[i] = sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - static void sdma_v4_0_get_ras_error_count(uint32_t value, uint32_t instance, uint32_t *sec_count) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index a1443990d5c60..78bdfed0a7fd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -104,7 +104,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_4_4_2[] = { static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev); static void sdma_v4_4_2_update_reset_mask(struct amdgpu_device *adev); @@ -1347,6 +1346,14 @@ static const struct amdgpu_sdma_funcs sdma_v4_4_2_sdma_funcs = { .soft_reset_kernel_queue = &sdma_v4_4_2_soft_reset_engine, }; +static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v4_4_2_vm_copy_pte, + + .write_pte = sdma_v4_4_2_vm_write_pte, + .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, +}; + static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1362,7 +1369,7 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) sdma_v4_4_2_set_ring_funcs(adev); sdma_v4_4_2_set_buffer_funcs(adev); - sdma_v4_4_2_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs); sdma_v4_4_2_set_irq_funcs(adev); sdma_v4_4_2_set_ras_funcs(adev); return 0; @@ -2298,11 +2305,11 @@ static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 7, .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer, }; @@ -2316,30 +2323,6 @@ static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v4_4_2_vm_copy_pte, - - .write_pte = sdma_v4_4_2_vm_write_pte, - .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde, -}; - -static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - struct drm_gpu_scheduler *sched; - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - if (adev->sdma.has_page_queue) - sched = &adev->sdma.instance[i].page.sched; - else - sched = &adev->sdma.instance[i].ring.sched; - adev->vm_manager.vm_pte_scheds[i] = sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - /** * sdma_v4_4_2_update_reset_mask - update reset mask for SDMA * @adev: Pointer to the AMDGPU device structure diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 8ddc4df06a1fd..52f4e9e099cbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -110,7 +110,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_0[] = { static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v5_0_stop_queue(struct amdgpu_ring *ring); static int sdma_v5_0_restore_queue(struct amdgpu_ring *ring); @@ -1031,7 +1030,7 @@ static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 20); if (r) { - DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); amdgpu_device_wb_free(adev, index); return r; } @@ -1096,7 +1095,7 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err0; } @@ -1117,11 +1116,11 @@ static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { - DRM_ERROR("amdgpu: IB test timed out\n"); + drm_err(adev_to_drm(adev), "IB test timed out\n"); r = -ETIMEDOUT; goto err1; } else if (r < 0) { - DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r); goto err1; } @@ -1357,6 +1356,13 @@ static const struct amdgpu_sdma_funcs sdma_v5_0_sdma_funcs = { .soft_reset_kernel_queue = &sdma_v5_0_soft_reset_engine, }; +static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v5_0_vm_copy_pte, + .write_pte = sdma_v5_0_vm_write_pte, + .set_pte_pde = sdma_v5_0_vm_set_pte_pde, +}; + static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1368,7 +1374,7 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v5_0_set_ring_funcs(adev); sdma_v5_0_set_buffer_funcs(adev); - sdma_v5_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs); sdma_v5_0_set_irq_funcs(adev); sdma_v5_0_set_mqd_funcs(adev); @@ -1424,18 +1430,9 @@ static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { - case IP_VERSION(5, 0, 0): - case IP_VERSION(5, 0, 2): - case IP_VERSION(5, 0, 5): - if ((adev->sdma.instance[0].fw_version >= 35) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - default: - break; - } + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; /* Allocate memory for SDMA IP Dump buffer */ ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); @@ -1704,24 +1701,12 @@ static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t mes_queue_id = entry->src_data[0]; - DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } switch (entry->client_id) { case SOC15_IH_CLIENTID_SDMA0: @@ -2073,27 +2058,6 @@ static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) } } -static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v5_0_vm_copy_pte, - .write_pte = sdma_v5_0_vm_write_pte, - .set_pte_pde = sdma_v5_0_vm_set_pte_pde, -}; - -static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - if (adev->vm_manager.vm_pte_funcs == NULL) { - adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; - } -} - const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 5, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 51101b0aa2fab..b4fb90cc8f7d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -111,7 +111,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_5_2[] = { static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v5_2_stop_queue(struct amdgpu_ring *ring); static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring); @@ -931,7 +930,7 @@ static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 20); if (r) { - DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); amdgpu_device_wb_free(adev, index); return r; } @@ -995,7 +994,7 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err0; } @@ -1016,11 +1015,11 @@ static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { - DRM_ERROR("amdgpu: IB test timed out\n"); + drm_err(adev_to_drm(adev), "IB test timed out\n"); r = -ETIMEDOUT; goto err1; } else if (r < 0) { - DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r); goto err1; } @@ -1248,6 +1247,13 @@ static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } +static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v5_2_vm_copy_pte, + .write_pte = sdma_v5_2_vm_write_pte, + .set_pte_pde = sdma_v5_2_vm_set_pte_pde, +}; + static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1259,7 +1265,7 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) sdma_v5_2_set_ring_funcs(adev); sdma_v5_2_set_buffer_funcs(adev); - sdma_v5_2_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs); sdma_v5_2_set_irq_funcs(adev); sdma_v5_2_set_mqd_funcs(adev); @@ -1325,8 +1331,8 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) ring->use_doorbell = true; ring->me = i; - DRM_INFO("use_doorbell being set to: [%s]\n", - ring->use_doorbell?"true":"false"); + drm_info(adev_to_drm(adev), "use_doorbell being set to: [%s]\n", + ring->use_doorbell?"true":"false"); ring->doorbell_index = (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset @@ -1342,25 +1348,9 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { - case IP_VERSION(5, 2, 0): - case IP_VERSION(5, 2, 2): - case IP_VERSION(5, 2, 3): - case IP_VERSION(5, 2, 4): - if ((adev->sdma.instance[0].fw_version >= 76) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - case IP_VERSION(5, 2, 5): - if ((adev->sdma.instance[0].fw_version >= 34) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - default: - break; - } + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; /* Allocate memory for SDMA IP Dump buffer */ ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); @@ -1617,24 +1607,12 @@ static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - uint32_t mes_queue_id = entry->src_data[0]; - DRM_DEBUG("IH: SDMA trap\n"); - if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { - struct amdgpu_mes_queue *queue; - - mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; - - spin_lock(&adev->mes.queue_id_lock); - queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); - if (queue) { - DRM_DEBUG("process smda queue id = %d\n", mes_queue_id); - amdgpu_fence_process(queue->ring); - } - spin_unlock(&adev->mes.queue_id_lock); + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) return 0; - } switch (entry->client_id) { case SOC15_IH_CLIENTID_SDMA0: @@ -2067,11 +2045,11 @@ static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 7, .emit_copy_buffer = sdma_v5_2_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, /* HW supports 1 << 30, but PAL uses 1 << 22 */ .fill_num_dw = 5, .emit_fill_buffer = sdma_v5_2_emit_fill_buffer, }; @@ -2084,27 +2062,6 @@ static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev) } } -static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v5_2_vm_copy_pte, - .write_pte = sdma_v5_2_vm_write_pte, - .set_pte_pde = sdma_v5_2_vm_set_pte_pde, -}; - -static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - if (adev->vm_manager.vm_pte_funcs == NULL) { - adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; - } -} - const struct amdgpu_ip_block_version sdma_v5_2_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 5, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 2170400449872..377f9fb7aa438 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -54,6 +54,7 @@ MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin"); MODULE_FIRMWARE("amdgpu/sdma_6_1_3.bin"); +MODULE_FIRMWARE("amdgpu/sdma_6_1_4.bin"); #define SDMA1_REG_OFFSET 0x600 #define SDMA0_HYP_DEC_REG_START 0x5880 @@ -119,7 +120,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = { static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v6_0_start(struct amdgpu_device *adev); @@ -937,7 +937,7 @@ static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { - DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); amdgpu_device_wb_free(adev, index); return r; } @@ -1001,7 +1001,7 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err0; } @@ -1022,11 +1022,11 @@ static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { - DRM_ERROR("amdgpu: IB test timed out\n"); + drm_err(adev_to_drm(adev), "IB test timed out\n"); r = -ETIMEDOUT; goto err1; } else if (r < 0) { - DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r); goto err1; } @@ -1268,6 +1268,24 @@ static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) } } +/* all sizes are in bytes */ +#define SDMA6_CSA_SIZE 32 +#define SDMA6_CSA_ALIGNMENT 4 + +static void sdma_v6_0_get_csa_info(struct amdgpu_device *adev, + struct amdgpu_sdma_csa_info *csa_info) +{ + csa_info->size = SDMA6_CSA_SIZE; + csa_info->alignment = SDMA6_CSA_ALIGNMENT; +} + +static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { + .copy_pte_num_dw = 7, + .copy_pte = sdma_v6_0_vm_copy_pte, + .write_pte = sdma_v6_0_vm_write_pte, + .set_pte_pde = sdma_v6_0_vm_set_pte_pde, +}; + static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1296,10 +1314,11 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v6_0_set_ring_funcs(adev); sdma_v6_0_set_buffer_funcs(adev); - sdma_v6_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs); sdma_v6_0_set_irq_funcs(adev); sdma_v6_0_set_mqd_funcs(adev); sdma_v6_0_set_ras_funcs(adev); + adev->sdma.get_csa_info = &sdma_v6_0_get_csa_info; return 0; } @@ -1351,18 +1370,9 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev->sdma.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); - switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { - case IP_VERSION(6, 0, 0): - case IP_VERSION(6, 0, 2): - case IP_VERSION(6, 0, 3): - if ((adev->sdma.instance[0].fw_version >= 21) && - !amdgpu_sriov_vf(adev) && - !adev->debug_disable_gpu_ring_reset) - adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; - break; - default: - break; - } + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; if (amdgpu_sdma_ras_sw_init(adev)) { dev_err(adev->dev, "Failed to initialize sdma ras block!\n"); @@ -1586,7 +1596,7 @@ static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); + r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); if (r) return r; @@ -1653,16 +1663,30 @@ static int sdma_v6_0_process_fence_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; + struct spinlock_t *idr_lock = &adev->userq_lock; +#endif unsigned long flags; doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); +#else + spin_lock_irqsave(idr_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); +#endif if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(xa, flags); +#else + spin_unlock_irqrestore(idr_lock, flags); +#endif } return 0; @@ -1874,11 +1898,11 @@ static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 7, .emit_copy_buffer = sdma_v6_0_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v6_0_emit_fill_buffer, }; @@ -1889,25 +1913,6 @@ static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, - .copy_pte = sdma_v6_0_vm_copy_pte, - .write_pte = sdma_v6_0_vm_write_pte, - .set_pte_pde = sdma_v6_0_vm_set_pte_pde, -}; - -static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v6_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 6, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 2b81344dcd668..60e8453638896 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -119,7 +119,6 @@ static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { static void sdma_v7_0_set_ring_funcs(struct amdgpu_device *adev); static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev); -static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev); static void sdma_v7_0_set_irq_funcs(struct amdgpu_device *adev); static int sdma_v7_0_start(struct amdgpu_device *adev); @@ -816,7 +815,7 @@ static int sdma_v7_0_reset_queue(struct amdgpu_ring *ring, amdgpu_ring_reset_helper_begin(ring, timedout_fence); - r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); + r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); if (r) return r; @@ -954,7 +953,7 @@ static int sdma_v7_0_ring_test_ring(struct amdgpu_ring *ring) r = amdgpu_ring_alloc(ring, 5); if (r) { - DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + drm_err(adev_to_drm(adev), "dma failed to lock ring %d (%d).\n", ring->idx, r); amdgpu_device_wb_free(adev, index); return r; } @@ -1018,7 +1017,7 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); if (r) { - DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + drm_err(adev_to_drm(adev), "failed to get ib (%ld).\n", r); goto err0; } @@ -1039,11 +1038,11 @@ static int sdma_v7_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) r = dma_fence_wait_timeout(f, false, timeout); if (r == 0) { - DRM_ERROR("amdgpu: IB test timed out\n"); + drm_err(adev_to_drm(adev), "IB test timed out\n"); r = -ETIMEDOUT; goto err1; } else if (r < 0) { - DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + drm_err(adev_to_drm(adev), "fence wait failed (%ld).\n", r); goto err1; } @@ -1253,6 +1252,24 @@ static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } +/* all sizes are in bytes */ +#define SDMA7_CSA_SIZE 32 +#define SDMA7_CSA_ALIGNMENT 4 + +static void sdma_v7_0_get_csa_info(struct amdgpu_device *adev, + struct amdgpu_sdma_csa_info *csa_info) +{ + csa_info->size = SDMA7_CSA_SIZE; + csa_info->alignment = SDMA7_CSA_ALIGNMENT; +} + +static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { + .copy_pte_num_dw = 8, + .copy_pte = sdma_v7_0_vm_copy_pte, + .write_pte = sdma_v7_0_vm_write_pte, + .set_pte_pde = sdma_v7_0_vm_set_pte_pde, +}; + static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -1283,9 +1300,10 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) sdma_v7_0_set_ring_funcs(adev); sdma_v7_0_set_buffer_funcs(adev); - sdma_v7_0_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs); sdma_v7_0_set_irq_funcs(adev); sdma_v7_0_set_mqd_funcs(adev); + adev->sdma.get_csa_info = &sdma_v7_0_get_csa_info; return 0; } @@ -1492,7 +1510,7 @@ static int sdma_v7_0_ring_preempt_ib(struct amdgpu_ring *ring) ring->trail_seq += 1; r = amdgpu_ring_alloc(ring, 10); if (r) { - DRM_ERROR("ring %d failed to be allocated \n", ring->idx); + DRM_ERROR("ring %d failed to be allocated\n", ring->idx); return r; } sdma_v7_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, @@ -1577,16 +1595,28 @@ static int sdma_v7_0_process_fence_irq(struct amdgpu_device *adev, if (adev->enable_mes && doorbell_offset) { struct amdgpu_userq_fence_driver *fence_drv = NULL; +#ifdef HAVE_STRUCT_XARRAY struct xarray *xa = &adev->userq_xa; +#else + struct idr *idr = &adev->userq_idr; +#endif unsigned long flags; doorbell_offset >>= SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(xa, flags); fence_drv = xa_load(xa, doorbell_offset); if (fence_drv) amdgpu_userq_fence_driver_process(fence_drv); xa_unlock_irqrestore(xa, flags); +#else + spin_lock_irqsave(&adev->userq_lock, flags); + fence_drv = idr_find(idr, doorbell_offset); + if (fence_drv) + amdgpu_userq_fence_driver_process(fence_drv); + spin_unlock_irqrestore(&adev->userq_lock, flags); +#endif } return 0; @@ -1817,10 +1847,10 @@ static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, } static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = { - .copy_max_bytes = 0x400000, + .copy_max_bytes = 1 << 30, .copy_num_dw = 8, .emit_copy_buffer = sdma_v7_0_emit_copy_buffer, - .fill_max_bytes = 0x400000, + .fill_max_bytes = 1 << 30, .fill_num_dw = 5, .emit_fill_buffer = sdma_v7_0_emit_fill_buffer, }; @@ -1831,25 +1861,6 @@ static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { - .copy_pte_num_dw = 8, - .copy_pte = sdma_v7_0_vm_copy_pte, - .write_pte = sdma_v7_0_vm_write_pte, - .set_pte_pde = sdma_v7_0_vm_set_pte_pde, -}; - -static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version sdma_v7_0_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, .major = 7, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c new file mode 100644 index 0000000000000..f20e0fc3fc743 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c @@ -0,0 +1,1802 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include + +#include "amdgpu.h" +#include "amdgpu_ucode.h" +#include "amdgpu_trace.h" + +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" + +#include "soc15_common.h" +#include "soc15.h" +#include "sdma_v7_1_0_pkt_open.h" +#include "nbio_v4_3.h" +#include "sdma_common.h" +#include "sdma_v7_1.h" +#include "v12_structs.h" +#include "mes_userqueue.h" +#include "soc_v1_0.h" + +MODULE_FIRMWARE("amdgpu/sdma_7_1_0.bin"); + +#define SDMA1_REG_OFFSET 0x600 +#define SDMA0_SDMA_IDX_0_END 0x450 +#define SDMA1_HYP_DEC_REG_OFFSET 0x30 + +static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_1[] = { + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS1_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS2_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS3_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS4_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS5_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_STATUS6_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UCODE_REV), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_RB_RPTR_FETCH_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_RB_RPTR_FETCH), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UTCL1_RD_STATUS), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UTCL1_WR_STATUS), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UTCL1_RD_XNACK0), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UTCL1_RD_XNACK1), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UTCL1_WR_XNACK0), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_UTCL1_WR_XNACK1), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_RB_CNTL), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_RB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_RB_WPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_IB_OFFSET), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_IB_BASE_LO), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_IB_BASE_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_IB_CNTL), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_IB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_IB_SUB_REMAIN), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE0_DUMMY_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE_STATUS0), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_RB_CNTL), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_RB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_RB_RPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_RB_WPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_RB_WPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_IB_OFFSET), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_IB_BASE_LO), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_IB_BASE_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_IB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_IB_SUB_REMAIN), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE1_DUMMY_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_RB_CNTL), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_RB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_RB_RPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_RB_WPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_RB_WPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_IB_OFFSET), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_IB_BASE_LO), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_IB_BASE_HI), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_IB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_IB_SUB_REMAIN), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_QUEUE2_DUMMY_REG), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_INT_STATUS), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_VM_CNTL), + SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), + SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_SDMA_CHICKEN_BITS), +}; + +static void sdma_v7_1_set_ring_funcs(struct amdgpu_device *adev); +static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev); +static void sdma_v7_1_set_irq_funcs(struct amdgpu_device *adev); +static int sdma_v7_1_inst_start(struct amdgpu_device *adev, + uint32_t inst_mask); + +static u32 sdma_v7_1_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) +{ + u32 base; + u32 dev_inst = GET_INST(SDMA0, instance); + int xcc_id = adev->sdma.instance[instance].xcc_id; + int xcc_inst = dev_inst % adev->sdma.num_inst_per_xcc; + + if (internal_offset >= SDMA0_SDMA_IDX_0_END) { + base = adev->reg_offset[GC_HWIP][xcc_id][1]; + if (xcc_inst != 0) + internal_offset += SDMA1_HYP_DEC_REG_OFFSET * xcc_inst; + } else { + base = adev->reg_offset[GC_HWIP][xcc_id][0]; + if (xcc_inst != 0) + internal_offset += SDMA1_REG_OFFSET * xcc_inst; + } + + return base + internal_offset; +} + +static unsigned sdma_v7_1_ring_init_cond_exec(struct amdgpu_ring *ring, + uint64_t addr) +{ + unsigned ret; + + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE)); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, 1); + /* this is the offset we need patch later */ + ret = ring->wptr & ring->buf_mask; + /* insert dummy here and patch it later */ + amdgpu_ring_write(ring, 0); + + return ret; +} + +/** + * sdma_v7_1_ring_get_rptr - get the current read pointer + * + * @ring: amdgpu ring pointer + * + * Get the current rptr from the hardware. + */ +static uint64_t sdma_v7_1_ring_get_rptr(struct amdgpu_ring *ring) +{ + u64 *rptr; + + /* XXX check if swapping is necessary on BE */ + rptr = (u64 *)ring->rptr_cpu_addr; + + DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); + return ((*rptr) >> 2); +} + +/** + * sdma_v7_1_ring_get_wptr - get the current write pointer + * + * @ring: amdgpu ring pointer + * + * Get the current wptr from the hardware. + */ +static uint64_t sdma_v7_1_ring_get_wptr(struct amdgpu_ring *ring) +{ + u64 wptr = 0; + + if (ring->use_doorbell) { + /* XXX check if swapping is necessary on BE */ + wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); + DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); + } + + return wptr >> 2; +} + +/** + * sdma_v7_1_ring_set_wptr - commit the write pointer + * + * @ring: amdgpu ring pointer + * + * Write the wptr back to the hardware. + */ +static void sdma_v7_1_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + DRM_DEBUG("Setting write pointer\n"); + + if (ring->use_doorbell) { + DRM_DEBUG("Using doorbell -- " + "wptr_offs == 0x%08x " + "lower_32_bits(ring->wptr) << 2 == 0x%08x " + "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", + ring->wptr_offs, + lower_32_bits(ring->wptr << 2), + upper_32_bits(ring->wptr << 2)); + /* XXX check if swapping is necessary on BE */ + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, + ring->wptr << 2); + DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", + ring->doorbell_index, ring->wptr << 2); + WDOORBELL64(ring->doorbell_index, ring->wptr << 2); + } else { + DRM_DEBUG("Not using doorbell -- " + "regSDMA%i_GFX_RB_WPTR == 0x%08x " + "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", + ring->me, + lower_32_bits(ring->wptr << 2), + ring->me, + upper_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, + ring->me, + regSDMA0_SDMA_QUEUE0_RB_WPTR), + lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, + ring->me, + regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), + upper_32_bits(ring->wptr << 2)); + } +} + +static void sdma_v7_1_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) +{ + struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); + int i; + + for (i = 0; i < count; i++) + if (sdma && sdma->burst_nop && (i == 0)) + amdgpu_ring_write(ring, ring->funcs->nop | + SDMA_PKT_NOP_HEADER_COUNT(count - 1)); + else + amdgpu_ring_write(ring, ring->funcs->nop); +} + +/** + * sdma_v7_1_ring_emit_ib - Schedule an IB on the DMA engine + * + * @ring: amdgpu ring pointer + * @job: job to retrieve vmid from + * @ib: IB object to schedule + * @flags: unused + * + * Schedule an IB in the DMA ring. + */ +static void sdma_v7_1_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_job *job, + struct amdgpu_ib *ib, + uint32_t flags) +{ + unsigned vmid = AMDGPU_JOB_GET_VMID(job); + uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); + + /* An IB packet must end on a 8 DW boundary--the next dword + * must be on a 8-dword boundary. Our IB packet below is 6 + * dwords long, thus add x number of NOPs, such that, in + * modular arithmetic, + * wptr + 6 + x = 8k, k >= 0, which in C is, + * (wptr + 6 + x) % 8 = 0. + * The expression below, is a solution of x. + */ + sdma_v7_1_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); + + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) | + SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); + /* base must be 32 byte aligned */ + amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); + amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); + amdgpu_ring_write(ring, ib->length_dw); + amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); + amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); +} + +/** + * sdma_v7_1_ring_emit_mem_sync - flush the IB by graphics cache rinse + * + * @ring: amdgpu ring pointer + * + * flush the IB by graphics cache rinse. + */ +static void sdma_v7_1_ring_emit_mem_sync(struct amdgpu_ring *ring) +{ + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | + SDMA_GCR_GLI_INV(1); + + /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_56_32(0)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_0(gcr_cntl) | + SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_15_7(0)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_16(0)); + amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD5_LIMIT_VA_56_48(0) | + SDMA_PKT_GCR_REQ_PAYLOAD5_VMID(0)); +} + + +/** + * sdma_v7_1_ring_emit_fence - emit a fence on the DMA ring + * + * @ring: amdgpu ring pointer + * @addr: address + * @seq: fence seq number + * @flags: fence flags + * + * Add a DMA fence packet to the ring to write + * the fence seq number and DMA trap packet to generate + * an interrupt if needed. + */ +static void sdma_v7_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + unsigned flags) +{ + bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; + /* write the fence */ + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | + SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ + /* zero in first two bits */ + BUG_ON(addr & 0x3); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, lower_32_bits(seq)); + + /* optionally write high bits as well */ + if (write64bit) { + addr += 4; + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) | + SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); + /* zero in first two bits */ + BUG_ON(addr & 0x3); + amdgpu_ring_write(ring, lower_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(addr)); + amdgpu_ring_write(ring, upper_32_bits(seq)); + } + + if (flags & AMDGPU_FENCE_FLAG_INT) { + /* generate an interrupt */ + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP)); + amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); + } +} + +/** + * sdma_v7_1_inst_gfx_stop - stop the gfx async dma engines + * + * @adev: amdgpu_device pointer + * @inst_mask: mask of dma engine instances to be disabled + * + * Stop the gfx async dma ring buffers. + */ +static void sdma_v7_1_inst_gfx_stop(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + u32 rb_cntl, ib_cntl; + int i; + + for_each_inst(i, inst_mask) { + rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_SDMA_QUEUE0_IB_CNTL, IB_ENABLE, 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL), ib_cntl); + } +} + +/** + * sdma_v7_1_inst_rlc_stop - stop the compute async dma engines + * + * @adev: amdgpu_device pointer + * @inst_mask: mask of dma engine instances to be disabled + * + * Stop the compute async dma queues. + */ +static void sdma_v7_1_inst_rlc_stop(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + /* XXX todo */ +} + +/** + * sdma_v7_1_inst_ctx_switch_enable - stop the async dma engines context switch + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs context switch. + * @inst_mask: mask of dma engine instances to be enabled + * + * Halt or unhalt the async dma engines context switch. + */ +static void sdma_v7_1_inst_ctx_switch_enable(struct amdgpu_device *adev, + bool enable, uint32_t inst_mask) +{ + int i; + + for_each_inst(i, inst_mask) { + WREG32_SOC15_IP(GC, + sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_TIMEOUT), 0x80); + } +} + +/** + * sdma_v7_1_inst_enable - stop the async dma engines + * + * @adev: amdgpu_device pointer + * @enable: enable/disable the DMA MEs. + * @inst_mask: mask of dma engine instances to be enabled + * + * Halt or unhalt the async dma engines. + */ +static void sdma_v7_1_inst_enable(struct amdgpu_device *adev, + bool enable, uint32_t inst_mask) +{ + u32 mcu_cntl; + int i; + + if (!enable) { + sdma_v7_1_inst_gfx_stop(adev, inst_mask); + sdma_v7_1_inst_rlc_stop(adev, inst_mask); + } + + if (amdgpu_sriov_vf(adev)) + return; + + for_each_inst(i, inst_mask) { + mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL)); + mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_SDMA_MCU_CNTL, HALT, enable ? 0 : 1); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), mcu_cntl); + } +} + +/** + * sdma_v7_1_gfx_resume_instance - start/restart a certain sdma engine + * + * @adev: amdgpu_device pointer + * @i: instance + * @restore: used to restore wptr when restart + * + * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. + * Return 0 for success. + */ +static int sdma_v7_1_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) +{ + struct amdgpu_ring *ring; + u32 rb_cntl, ib_cntl; + u32 rb_bufsz; + u32 doorbell; + u32 doorbell_offset; + u32 temp; + u64 wptr_gpu_addr; + int r; + + ring = &adev->sdma.instance[i].ring; + + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); +#ifdef __BIG_ENDIAN + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); +#endif + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_PRIV, 1); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + if (restore) { + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } else { + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR), 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_HI), 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), 0); + } + /* setup the wptr shadow polling */ + wptr_gpu_addr = ring->wptr_gpu_addr; + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + if (amdgpu_sriov_vf(adev)) + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1); + else + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, MCU_WPTR_POLL_ENABLE, 1); + + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_BASE), ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); + + if (!restore) + ring->wptr = 0; + + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE), 1); + + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + } + + doorbell = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET)); + + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 0); + } + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET), doorbell_offset); + + if (i == 0) + adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index, + adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); + + if (amdgpu_sriov_vf(adev)) + sdma_v7_1_ring_set_wptr(ring); + + /* set minor_ptr_update to 0 after wptr programed */ + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE), 0); + + /* Set up sdma hang watchdog */ + temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_WATCHDOG_CNTL)); + /* 100ms per unit */ + temp = REG_SET_FIELD(temp, SDMA0_SDMA_WATCHDOG_CNTL, QUEUE_HANG_COUNT, + max(adev->usec_timeout/100000, 1)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_WATCHDOG_CNTL), temp); + + /* Set up RESP_MODE to non-copy addresses */ + temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_SDMA_UTCL1_CNTL, RESP_MODE, 3); + temp = REG_SET_FIELD(temp, SDMA0_SDMA_UTCL1_CNTL, REDO_DELAY, 9); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_CNTL), temp); + + /* program default cache read and write policy */ + temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_PAGE)); + /* clean read policy and write policy bits */ + temp &= 0xFF0FFF; + temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | + (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_UTCL1_PAGE), temp); + + if (!amdgpu_sriov_vf(adev)) { + /* unhalt engine */ + temp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_SDMA_MCU_CNTL, HALT, 0); + temp = REG_SET_FIELD(temp, SDMA0_SDMA_MCU_CNTL, RESET, 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), temp); + } + + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl); + + ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_SDMA_QUEUE0_IB_CNTL, IB_ENABLE, 1); +#ifdef __BIG_ENDIAN + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_SDMA_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); +#endif + /* enable DMA IBs */ + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_IB_CNTL), ib_cntl); + ring->sched.ready = true; + + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v7_1_inst_ctx_switch_enable(adev, true, i); + sdma_v7_1_inst_enable(adev, true, i); + } + + r = amdgpu_ring_test_helper(ring); + if (r) + ring->sched.ready = false; + + return r; +} + +/** + * sdma_v7_1_inst_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * @inst_mask: mask of dma engine instances to be enabled + * + * Set up the gfx DMA ring buffers and enable them. + * Returns 0 for success, error for failure. + */ +static int sdma_v7_1_inst_gfx_resume(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + int i, r; + + for_each_inst(i, inst_mask) { + r = sdma_v7_1_gfx_resume_instance(adev, i, false); + if (r) + return r; + } + + return 0; + +} + +/** + * sdma_v7_1_inst_rlc_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * @inst_mask: mask of dma engine instances to be enabled + * + * Set up the compute DMA queues and enable them. + * Returns 0 for success, error for failure. + */ +static int sdma_v7_1_inst_rlc_resume(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + return 0; +} + +static void sdma_v7_1_inst_free_ucode_buffer(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + int i; + + for_each_inst(i, inst_mask) { + amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj, + &adev->sdma.instance[i].sdma_fw_gpu_addr, + (void **)&adev->sdma.instance[i].sdma_fw_ptr); + } +} + +/** + * sdma_v7_1_inst_load_microcode - load the sDMA ME ucode + * + * @adev: amdgpu_device pointer + * @inst_mask: mask of dma engine instances to be enabled + * + * Loads the sDMA0/1 ucode. + * Returns 0 for success, -EINVAL if the ucode is not available. + */ +static int sdma_v7_1_inst_load_microcode(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + const struct sdma_firmware_header_v3_0 *hdr; + const __le32 *fw_data; + u32 fw_size; + uint32_t tmp, sdma_status, ic_op_cntl; + int i, r, j; + + /* halt the MEs */ + sdma_v7_1_inst_enable(adev, false, inst_mask); + + if (!adev->sdma.instance[0].fw) + return -EINVAL; + + hdr = (const struct sdma_firmware_header_v3_0 *) + adev->sdma.instance[0].fw->data; + amdgpu_ucode_print_sdma_hdr(&hdr->header); + + fw_data = (const __le32 *)(adev->sdma.instance[0].fw->data + + le32_to_cpu(hdr->ucode_offset_bytes)); + fw_size = le32_to_cpu(hdr->ucode_size_bytes); + + for_each_inst(i, inst_mask) { + r = amdgpu_bo_create_reserved(adev, fw_size, + PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->sdma.instance[i].sdma_fw_obj, + &adev->sdma.instance[i].sdma_fw_gpu_addr, + (void **)&adev->sdma.instance[i].sdma_fw_ptr); + if (r) { + dev_err(adev->dev, "(%d) failed to create sdma ucode bo\n", r); + return r; + } + + memcpy(adev->sdma.instance[i].sdma_fw_ptr, fw_data, fw_size); + + amdgpu_bo_kunmap(adev->sdma.instance[i].sdma_fw_obj); + amdgpu_bo_unreserve(adev->sdma.instance[i].sdma_fw_obj); + + tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_CNTL)); + tmp = REG_SET_FIELD(tmp, SDMA0_SDMA_IC_CNTL, GPA, 0); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_CNTL), tmp); + + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_BASE_LO), + lower_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_BASE_HI), + upper_32_bits(adev->sdma.instance[i].sdma_fw_gpu_addr)); + + tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL)); + tmp = REG_SET_FIELD(tmp, SDMA0_SDMA_IC_OP_CNTL, PRIME_ICACHE, 1); + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL), tmp); + + /* Wait for sdma ucode init complete */ + for (j = 0; j < adev->usec_timeout; j++) { + ic_op_cntl = RREG32_SOC15_IP(GC, + sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_IC_OP_CNTL)); + sdma_status = RREG32_SOC15_IP(GC, + sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_STATUS_REG)); + if ((REG_GET_FIELD(ic_op_cntl, SDMA0_SDMA_IC_OP_CNTL, ICACHE_PRIMED) == 1) && + (REG_GET_FIELD(sdma_status, SDMA0_SDMA_STATUS_REG, UCODE_INIT_DONE) == 1)) + break; + udelay(1); + } + + if (j >= adev->usec_timeout) { + dev_err(adev->dev, "failed to init sdma ucode\n"); + return -EINVAL; + } + } + + return 0; +} + +static int sdma_v7_1_soft_reset(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + uint32_t inst_mask; + u32 tmp; + int i; + + inst_mask = GENMASK(NUM_XCC(adev->sdma.sdma_mask) - 1, 0); + sdma_v7_1_inst_gfx_stop(adev, inst_mask); + + for_each_inst(i, inst_mask) { + //tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FREEZE)); + //tmp |= SDMA0_SDMA_FREEZE__FREEZE_MASK; + //WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FREEZE), tmp); + tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL)); + tmp |= SDMA0_SDMA_MCU_CNTL__HALT_MASK; + tmp |= SDMA0_SDMA_MCU_CNTL__RESET_MASK; + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), tmp); + + WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_PREEMPT), 0); + + udelay(100); + + tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i; + WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + + udelay(100); + + WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0); + tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET); + + udelay(100); + } + + return sdma_v7_1_inst_start(adev, inst_mask); +} + +static bool sdma_v7_1_check_soft_reset(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, r; + long tmo = msecs_to_jiffies(1000); + + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + r = amdgpu_ring_test_ib(ring, tmo); + if (r) + return true; + } + + return false; +} + +static int sdma_v7_1_reset_queue(struct amdgpu_ring *ring, + unsigned int vmid, + struct amdgpu_fence *timedout_fence) +{ + struct amdgpu_device *adev = ring->adev; + int r; + + if (ring->me >= adev->sdma.num_instances) { + dev_err(adev->dev, "sdma instance not found\n"); + return -EINVAL; + } + + amdgpu_ring_reset_helper_begin(ring, timedout_fence); + + r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true, 0); + if (r) + return r; + + r = sdma_v7_1_gfx_resume_instance(adev, ring->me, true); + if (r) + return r; + + return amdgpu_ring_reset_helper_end(ring, timedout_fence); +} + +/** + * sdma_v7_1_inst_start - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * @inst_mask: mask of dma engine instances to be enabled + * + * Set up the DMA engines and enable them. + * Returns 0 for success, error for failure. + */ +static int sdma_v7_1_inst_start(struct amdgpu_device *adev, + uint32_t inst_mask) +{ + int r = 0; + + if (amdgpu_sriov_vf(adev)) { + sdma_v7_1_inst_ctx_switch_enable(adev, false, inst_mask); + sdma_v7_1_inst_enable(adev, false, inst_mask); + + /* set RB registers */ + r = sdma_v7_1_inst_gfx_resume(adev, inst_mask); + return r; + } + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { + r = sdma_v7_1_inst_load_microcode(adev, inst_mask); + if (r) { + sdma_v7_1_inst_free_ucode_buffer(adev, inst_mask); + return r; + } + + if (amdgpu_emu_mode == 1) + msleep(1000); + } + + /* unhalt the MEs */ + sdma_v7_1_inst_enable(adev, true, inst_mask); + /* enable sdma ring preemption */ + sdma_v7_1_inst_ctx_switch_enable(adev, true, inst_mask); + + /* start the gfx rings and rlc compute queues */ + r = sdma_v7_1_inst_gfx_resume(adev, inst_mask); + if (r) + return r; + r = sdma_v7_1_inst_rlc_resume(adev, inst_mask); + + return r; +} + +static int sdma_v7_1_mqd_init(struct amdgpu_device *adev, void *mqd, + struct amdgpu_mqd_prop *prop) +{ + struct v12_sdma_mqd *m = mqd; + uint64_t wb_gpu_addr; + + m->sdmax_rlcx_rb_cntl = + order_base_2(prop->queue_size / 4) << SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | + 1 << SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | + 4 << SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | + 1 << SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; + + m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8); + m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8); + + wb_gpu_addr = prop->wptr_gpu_addr; + m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr); + m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr); + + wb_gpu_addr = prop->rptr_gpu_addr; + m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr); + m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr); + + m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, 0, + regSDMA0_SDMA_QUEUE0_IB_CNTL)); + + m->sdmax_rlcx_doorbell_offset = + prop->doorbell_index << SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; + + m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 1); + + m->sdmax_rlcx_doorbell_log = 0; + m->sdmax_rlcx_rb_aql_cntl = 0x4000; //regSDMA0_SDMA_QUEUE0_RB_AQL_CNTL_DEFAULT; + m->sdmax_rlcx_dummy_reg = 0xf; //regSDMA0_SDMA_QUEUE0_DUMMY_REG_DEFAULT; + + m->sdmax_rlcx_csa_addr_lo = lower_32_bits(prop->csa_addr); + m->sdmax_rlcx_csa_addr_hi = upper_32_bits(prop->csa_addr); + + return 0; +} + +static void sdma_v7_1_set_mqd_funcs(struct amdgpu_device *adev) +{ + adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v12_sdma_mqd); + adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v7_1_mqd_init; +} + +/** + * sdma_v7_1_ring_test_ring - simple async dma engine test + * + * @ring: amdgpu_ring structure holding ring information + * + * Test the DMA engine by writing using it to write an + * value to memory. + * Returns 0 for success, error for failure. + */ +static int sdma_v7_1_ring_test_ring(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + unsigned i; + unsigned index; + int r; + u32 tmp; + u64 gpu_addr; + + tmp = 0xCAFEDEAD; + + r = amdgpu_device_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ring_alloc(ring, 5); + if (r) { + DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); + amdgpu_device_wb_free(adev, index); + return r; + } + + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); + amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); + amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); + amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); + amdgpu_ring_write(ring, 0xDEADBEEF); + amdgpu_ring_commit(ring); + + for (i = 0; i < adev->usec_timeout; i++) { + tmp = le32_to_cpu(adev->wb.wb[index]); + if (tmp == 0xDEADBEEF) + break; + if (amdgpu_emu_mode == 1) + msleep(1); + else + udelay(1); + } + + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; + + amdgpu_device_wb_free(adev, index); + + return r; +} + +/** + * sdma_v7_1_ring_test_ib - test an IB on the DMA engine + * + * @ring: amdgpu_ring structure holding ring information + * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT + * + * Test a simple IB in the DMA ring. + * Returns 0 on success, error on failure. + */ +static int sdma_v7_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_ib ib; + struct dma_fence *f = NULL; + unsigned index; + long r; + u32 tmp = 0; + u64 gpu_addr; + + tmp = 0xCAFEDEAD; + memset(&ib, 0, sizeof(ib)); + + r = amdgpu_device_wb_get(adev, &index); + if (r) { + dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); + return r; + } + + gpu_addr = adev->wb.gpu_addr + (index * 4); + adev->wb.wb[index] = cpu_to_le32(tmp); + + r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib); + if (r) { + DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); + goto err0; + } + + ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + ib.ptr[1] = lower_32_bits(gpu_addr); + ib.ptr[2] = upper_32_bits(gpu_addr); + ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); + ib.ptr[4] = 0xDEADBEEF; + ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); + ib.length_dw = 8; + + r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); + if (r) + goto err1; + + r = dma_fence_wait_timeout(f, false, timeout); + if (r == 0) { + DRM_ERROR("amdgpu: IB test timed out\n"); + r = -ETIMEDOUT; + goto err1; + } else if (r < 0) { + DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); + goto err1; + } + + tmp = le32_to_cpu(adev->wb.wb[index]); + + if (tmp == 0xDEADBEEF) + r = 0; + else + r = -EINVAL; + +err1: + amdgpu_ib_free(&ib, NULL); + dma_fence_put(f); +err0: + amdgpu_device_wb_free(adev, index); + return r; +} + + +/** + * sdma_v7_1_vm_copy_pte - update PTEs by copying them from the GART + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @src: src addr to copy from + * @count: number of page entries to update + * + * Update PTEs by copying them from the GART using sDMA. + */ +static void sdma_v7_1_vm_copy_pte(struct amdgpu_ib *ib, + uint64_t pe, uint64_t src, + unsigned count) +{ + unsigned bytes = count * 8; + + ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + + ib->ptr[ib->length_dw++] = bytes - 1; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src); + ib->ptr[ib->length_dw++] = upper_32_bits(src); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + +} + +/** + * sdma_v7_1_vm_write_pte - update PTEs by writing them manually + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @value: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * + * Update PTEs by writing them manually using sDMA. + */ +static void sdma_v7_1_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, + uint64_t value, unsigned count, + uint32_t incr) +{ + unsigned ndw = count * 2; + + ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); + ib->ptr[ib->length_dw++] = lower_32_bits(pe); + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = ndw - 1; + for (; ndw > 0; ndw -= 2) { + ib->ptr[ib->length_dw++] = lower_32_bits(value); + ib->ptr[ib->length_dw++] = upper_32_bits(value); + value += incr; + } +} + +/** + * sdma_v7_1_vm_set_pte_pde - update the page tables using sDMA + * + * @ib: indirect buffer to fill with commands + * @pe: addr of the page entry + * @addr: dst addr to write into pe + * @count: number of page entries to update + * @incr: increase next addr by incr bytes + * @flags: access flags + * + * Update the page tables using sDMA. + */ +static void sdma_v7_1_vm_set_pte_pde(struct amdgpu_ib *ib, + uint64_t pe, + uint64_t addr, unsigned count, + uint32_t incr, uint64_t flags) +{ + /* for physically contiguous pages (vram) */ + u32 header = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE); + + /* TODO: + * When VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is enabled, change below MTYPE + * to RW for AID A1 and UC for AID A0. NC needs additional GCR flush and need not + * be supported. Also, honour amdgpu_mtype_local override. RW would additionally + * require setting SCOPE bits in the header. + * + * header |= (SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x2:RW) | + * SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1) | + * SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(0x3:SYS_SCOPE)); + */ + + /* VM_L2_CNTL5.WALKER_FETCH_PDE_MTYPE_ENABLE is 0 which defaults to UC. So, + * use MTYPE_UC (0x3). For ref. MTYPE_RW=0x2 MTYPE_NC=0x0 + */ + header |= SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(0x3) | SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(0x1); + + ib->ptr[ib->length_dw++] = header; + ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ + ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ + ib->ptr[ib->length_dw++] = upper_32_bits(flags); + ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ + ib->ptr[ib->length_dw++] = upper_32_bits(addr); + ib->ptr[ib->length_dw++] = incr; /* increment size */ + ib->ptr[ib->length_dw++] = 0; + ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ +} + +/** + * sdma_v7_1_ring_pad_ib - pad the IB + * + * @ring: amdgpu ring pointer + * @ib: indirect buffer to fill with padding + * + * Pad the IB with NOPs to a boundary multiple of 8. + */ +static void sdma_v7_1_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) +{ + struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); + u32 pad_count; + int i; + + pad_count = (-ib->length_dw) & 0x7; + for (i = 0; i < pad_count; i++) + if (sdma && sdma->burst_nop && (i == 0)) + ib->ptr[ib->length_dw++] = + SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) | + SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); + else + ib->ptr[ib->length_dw++] = + SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP); +} + +/** + * sdma_v7_1_ring_emit_pipeline_sync - sync the pipeline + * + * @ring: amdgpu_ring pointer + * + * Make sure all previous operations are completed (CIK). + */ +static void sdma_v7_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) +{ + uint32_t seq = ring->fence_drv.sync_seq; + uint64_t addr = ring->fence_drv.gpu_addr; + + /* wait for idle */ + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ + SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); + amdgpu_ring_write(ring, addr & 0xfffffffc); + amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); + amdgpu_ring_write(ring, seq); /* reference */ + amdgpu_ring_write(ring, 0xffffffff); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ +} + +/** + * sdma_v7_1_ring_emit_vm_flush - vm flush using sDMA + * + * @ring: amdgpu_ring pointer + * @vmid: vmid number to use + * @pd_addr: address + * + * Update the page table base and flush the VM TLB + * using sDMA. + */ +static void sdma_v7_1_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) +{ + amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); +} + +static void sdma_v7_1_ring_emit_wreg(struct amdgpu_ring *ring, + uint32_t reg, uint32_t val) +{ + /* SRBM WRITE command will not support on sdma v7. + * Use Register WRITE command instead, which OPCODE is same as SRBM WRITE + */ + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE)); + amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2); + amdgpu_ring_write(ring, val); +} + +static void sdma_v7_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val, uint32_t mask) +{ + amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ + amdgpu_ring_write(ring, soc_v1_0_normalize_xcc_reg_offset(reg) << 2); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); /* reference */ + amdgpu_ring_write(ring, mask); /* mask */ + amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); +} + +static void sdma_v7_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, + uint32_t reg0, uint32_t reg1, + uint32_t ref, uint32_t mask) +{ + amdgpu_ring_emit_wreg(ring, reg0, ref); + /* wait for a cycle to reset vm_inv_eng*_ack */ + amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); + amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); +} + +static const struct amdgpu_vm_pte_funcs sdma_v7_1_vm_pte_funcs = { + .copy_pte_num_dw = 8, + .copy_pte = sdma_v7_1_vm_copy_pte, + .write_pte = sdma_v7_1_vm_write_pte, + .set_pte_pde = sdma_v7_1_vm_set_pte_pde, +}; + +static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r; + + r = amdgpu_sdma_init_microcode(adev, 0, true); + if (r) { + DRM_ERROR("Failed to init sdma firmware!\n"); + return r; + } + + sdma_v7_1_set_ring_funcs(adev); + sdma_v7_1_set_buffer_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs); + sdma_v7_1_set_irq_funcs(adev); + sdma_v7_1_set_mqd_funcs(adev); + + return 0; +} + +static int sdma_v7_1_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_ring *ring; + int r, i; + struct amdgpu_device *adev = ip_block->adev; + uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_1); + uint32_t *ptr; + u32 xcc_id; + + /* SDMA trap event */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GFX, + GFX_12_1_0__SRCID__SDMA_TRAP, + &adev->sdma.trap_irq); + if (r) + return r; + + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->me = i; + + for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) { + if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id)) + break; + } + + DRM_DEBUG("SDMA%d.%d use_doorbell being set to: [%s]\n", + xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc, + ring->use_doorbell?"true":"false"); + + ring->doorbell_index = + (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset + + ring->vm_hub = AMDGPU_GFXHUB(xcc_id); + sprintf(ring->name, "sdma%d.%d", xcc_id, + GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc); + r = amdgpu_ring_init(adev, ring, 1024, + &adev->sdma.trap_irq, + AMDGPU_SDMA_IRQ_INSTANCE0 + i, + AMDGPU_RING_PRIO_DEFAULT, NULL); + if (r) + return r; + } + + adev->sdma.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring); + if (!amdgpu_sriov_vf(adev) && + !adev->debug_disable_gpu_ring_reset) + adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; + + r = amdgpu_sdma_sysfs_reset_mask_init(adev); + if (r) + return r; + /* Allocate memory for SDMA IP Dump buffer */ + ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (ptr) + adev->sdma.ip_dump = ptr; + else + DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n"); + +#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ + adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs; +#endif + + return r; +} + +static int sdma_v7_1_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ring_fini(&adev->sdma.instance[i].ring); + + amdgpu_sdma_sysfs_reset_mask_fini(adev); + amdgpu_sdma_destroy_inst_ctx(adev, true); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) + sdma_v7_1_inst_free_ucode_buffer(adev, adev->sdma.sdma_mask); + + kfree(adev->sdma.ip_dump); + + return 0; +} + +static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + uint32_t inst_mask; + + inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); + + return sdma_v7_1_inst_start(adev, inst_mask); +} + +static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + if (amdgpu_sriov_vf(adev)) + return 0; + + sdma_v7_1_inst_ctx_switch_enable(adev, false, adev->sdma.sdma_mask); + sdma_v7_1_inst_enable(adev, false, adev->sdma.sdma_mask); + + return 0; +} + +static int sdma_v7_1_suspend(struct amdgpu_ip_block *ip_block) +{ + return sdma_v7_1_hw_fini(ip_block); +} + +static int sdma_v7_1_resume(struct amdgpu_ip_block *ip_block) +{ + return sdma_v7_1_hw_init(ip_block); +} + +static bool sdma_v7_1_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + u32 i; + + for (i = 0; i < adev->sdma.num_instances; i++) { + u32 tmp = RREG32(sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_STATUS_REG)); + + if (!(tmp & SDMA0_SDMA_STATUS_REG__IDLE_MASK)) + return false; + } + + return true; +} + +static int sdma_v7_1_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + unsigned i, j; + u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; + struct amdgpu_device *adev = ip_block->adev; + + for (i = 0; i < adev->usec_timeout; i++) { + for (j = 0; j < adev->sdma.num_instances; j++) { + sdma[j] = RREG32(sdma_v7_1_get_reg_offset(adev, + j, regSDMA0_SDMA_STATUS_REG)); + if (!(sdma[j] & SDMA0_SDMA_STATUS_REG__IDLE_MASK)) + break; + } + if (j == adev->sdma.num_instances) + return 0; + udelay(1); + } + return -ETIMEDOUT; +} + +static int sdma_v7_1_ring_preempt_ib(struct amdgpu_ring *ring) +{ + int i, r = 0; + struct amdgpu_device *adev = ring->adev; + u32 index = 0; + u64 sdma_gfx_preempt; + + amdgpu_sdma_get_index_from_ring(ring, &index); + sdma_gfx_preempt = + sdma_v7_1_get_reg_offset(adev, index, regSDMA0_SDMA_QUEUE0_PREEMPT); + + /* assert preemption condition */ + amdgpu_ring_set_preempt_cond_exec(ring, false); + + /* emit the trailing fence */ + ring->trail_seq += 1; + r = amdgpu_ring_alloc(ring, 10); + if (r) { + DRM_ERROR("ring %d failed to be allocated \n", ring->idx); + return r; + } + sdma_v7_1_ring_emit_fence(ring, ring->trail_fence_gpu_addr, + ring->trail_seq, 0); + amdgpu_ring_commit(ring); + + /* assert IB preemption */ + WREG32(sdma_gfx_preempt, 1); + + /* poll the trailing fence */ + for (i = 0; i < adev->usec_timeout; i++) { + if (ring->trail_seq == + le32_to_cpu(*(ring->trail_fence_cpu_addr))) + break; + udelay(1); + } + + if (i >= adev->usec_timeout) { + r = -EINVAL; + DRM_ERROR("ring %d failed to be preempted\n", ring->idx); + } + + /* deassert IB preemption */ + WREG32(sdma_gfx_preempt, 0); + + /* deassert the preemption condition */ + amdgpu_ring_set_preempt_cond_exec(ring, true); + return r; +} + +static int sdma_v7_1_set_trap_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + u32 sdma_cntl; + + u32 reg_offset = sdma_v7_1_get_reg_offset(adev, type, regSDMA0_SDMA_CNTL); + + sdma_cntl = RREG32(reg_offset); + sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_SDMA_CNTL, TRAP_ENABLE, + state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); + WREG32(reg_offset, sdma_cntl); + + return 0; +} + +static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + int inst, instances, queue, xcc_id = 0; + + DRM_DEBUG("IH: SDMA trap\n"); + + if (drm_WARN_ON_ONCE(&adev->ddev, + adev->enable_mes && + (entry->src_data[0] & AMDGPU_FENCE_MES_QUEUE_FLAG))) + return 0; + + queue = entry->ring_id & 0xf; + if (adev->gfx.funcs && adev->gfx.funcs->ih_node_to_logical_xcc) + xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, entry->node_id); + else + dev_warn(adev->dev, "IH: SDMA may get wrong xcc id as gfx function not available\n"); + inst = ((entry->ring_id & 0xf0) >> 4) + + GET_INST(GC, xcc_id) * adev->sdma.num_inst_per_xcc; + for (instances = 0; instances < adev->sdma.num_instances; instances++) { + if (inst == GET_INST(SDMA0, instances)) + break; + } + if (instances > adev->sdma.num_instances - 1) { + DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n"); + return -EINVAL; + } + + switch (entry->client_id) { + case SOC_V1_0_IH_CLIENTID_GFX: + switch (queue) { + case 0: + amdgpu_fence_process(&adev->sdma.instance[instances].ring); + break; + default: + break; + } + break; + } + return 0; +} + +static int sdma_v7_1_process_illegal_inst_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + return 0; +} + +static int sdma_v7_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + return 0; +} + +static int sdma_v7_1_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + return 0; +} + +static void sdma_v7_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, + u64 *flags) +{ +} + +static void sdma_v7_1_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, j; + uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_1); + uint32_t instance_offset; + + if (!adev->sdma.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances); + for (i = 0; i < adev->sdma.num_instances; i++) { + instance_offset = i * reg_count; + drm_printf(p, "\nInstance:%d\n", i); + + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_7_1[j].reg_name, + adev->sdma.ip_dump[instance_offset + j]); + } +} + +static void sdma_v7_1_dump_ip_state(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, j; + uint32_t instance_offset; + uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_1); + + if (!adev->sdma.ip_dump) + return; + + amdgpu_gfx_off_ctrl(adev, false); + for (i = 0; i < adev->sdma.num_instances; i++) { + instance_offset = i * reg_count; + for (j = 0; j < reg_count; j++) + adev->sdma.ip_dump[instance_offset + j] = + RREG32(sdma_v7_1_get_reg_offset(adev, i, + sdma_reg_list_7_1[j].reg_offset)); + } + amdgpu_gfx_off_ctrl(adev, true); +} + +const struct amd_ip_funcs sdma_v7_1_ip_funcs = { + .name = "sdma_v7_1", + .early_init = sdma_v7_1_early_init, + .late_init = NULL, + .sw_init = sdma_v7_1_sw_init, + .sw_fini = sdma_v7_1_sw_fini, + .hw_init = sdma_v7_1_hw_init, + .hw_fini = sdma_v7_1_hw_fini, + .suspend = sdma_v7_1_suspend, + .resume = sdma_v7_1_resume, + .is_idle = sdma_v7_1_is_idle, + .wait_for_idle = sdma_v7_1_wait_for_idle, + .soft_reset = sdma_v7_1_soft_reset, + .check_soft_reset = sdma_v7_1_check_soft_reset, + .set_clockgating_state = sdma_v7_1_set_clockgating_state, + .set_powergating_state = sdma_v7_1_set_powergating_state, + .get_clockgating_state = sdma_v7_1_get_clockgating_state, + .dump_ip_state = sdma_v7_1_dump_ip_state, + .print_ip_state = sdma_v7_1_print_ip_state, +}; + +static const struct amdgpu_ring_funcs sdma_v7_1_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, + .secure_submission_supported = true, + .get_rptr = sdma_v7_1_ring_get_rptr, + .get_wptr = sdma_v7_1_ring_get_wptr, + .set_wptr = sdma_v7_1_ring_set_wptr, + .emit_frame_size = + 5 + /* sdma_v7_1_ring_init_cond_exec */ + 6 + /* sdma_v7_1_ring_emit_pipeline_sync */ + /* sdma_v7_1_ring_emit_vm_flush */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + + 10 + 10 + 10, /* sdma_v7_1_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 5 + 7 + 6, /* sdma_v7_1_ring_emit_ib */ + .emit_ib = sdma_v7_1_ring_emit_ib, + .emit_mem_sync = sdma_v7_1_ring_emit_mem_sync, + .emit_fence = sdma_v7_1_ring_emit_fence, + .emit_pipeline_sync = sdma_v7_1_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v7_1_ring_emit_vm_flush, + .test_ring = sdma_v7_1_ring_test_ring, + .test_ib = sdma_v7_1_ring_test_ib, + .insert_nop = sdma_v7_1_ring_insert_nop, + .pad_ib = sdma_v7_1_ring_pad_ib, + .emit_wreg = sdma_v7_1_ring_emit_wreg, + .emit_reg_wait = sdma_v7_1_ring_emit_reg_wait, + .emit_reg_write_reg_wait = sdma_v7_1_ring_emit_reg_write_reg_wait, + .init_cond_exec = sdma_v7_1_ring_init_cond_exec, + .preempt_ib = sdma_v7_1_ring_preempt_ib, + .reset = sdma_v7_1_reset_queue, +}; + +static void sdma_v7_1_set_ring_funcs(struct amdgpu_device *adev) +{ + int i, dev_inst; + + for (i = 0; i < adev->sdma.num_instances; i++) { + adev->sdma.instance[i].ring.funcs = &sdma_v7_1_ring_funcs; + adev->sdma.instance[i].ring.me = i; + + dev_inst = GET_INST(SDMA0, i); + /* XCC to which SDMA belongs depends on physical instance */ + adev->sdma.instance[i].xcc_id = + dev_inst / adev->sdma.num_inst_per_xcc; + } +} + +static const struct amdgpu_irq_src_funcs sdma_v7_1_trap_irq_funcs = { + .set = sdma_v7_1_set_trap_irq_state, + .process = sdma_v7_1_process_trap_irq, +}; + +static const struct amdgpu_irq_src_funcs sdma_v7_1_illegal_inst_irq_funcs = { + .process = sdma_v7_1_process_illegal_inst_irq, +}; + +static void sdma_v7_1_set_irq_funcs(struct amdgpu_device *adev) +{ + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + + adev->sdma.num_instances; + adev->sdma.trap_irq.funcs = &sdma_v7_1_trap_irq_funcs; + adev->sdma.illegal_inst_irq.funcs = &sdma_v7_1_illegal_inst_irq_funcs; +} + +/** + * sdma_v7_1_emit_copy_buffer - copy buffer using the sDMA engine + * + * @ib: indirect buffer to fill with commands + * @src_offset: src GPU address + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * @copy_flags: copy flags for the buffers + * + * Copy GPU buffers using the DMA engine. + * Used by the amdgpu ttm implementation to move pages if + * registered as the asic copy callback. + */ +static void sdma_v7_1_emit_copy_buffer(struct amdgpu_ib *ib, + uint64_t src_offset, + uint64_t dst_offset, + uint32_t byte_count, + uint32_t copy_flags) +{ + ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | + SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0); + + ib->ptr[ib->length_dw++] = byte_count - 1; + ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ + ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); +} + +/** + * sdma_v7_1_emit_fill_buffer - fill buffer using the sDMA engine + * + * @ib: indirect buffer to fill + * @src_data: value to write to buffer + * @dst_offset: dst GPU address + * @byte_count: number of bytes to xfer + * + * Fill GPU buffers using the DMA engine. + */ +static void sdma_v7_1_emit_fill_buffer(struct amdgpu_ib *ib, + uint32_t src_data, + uint64_t dst_offset, + uint32_t byte_count) +{ + ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL); + ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); + ib->ptr[ib->length_dw++] = src_data; + ib->ptr[ib->length_dw++] = byte_count - 1; +} + +static const struct amdgpu_buffer_funcs sdma_v7_1_buffer_funcs = { + .copy_max_bytes = 1 << 30, + .copy_num_dw = 8, + .emit_copy_buffer = sdma_v7_1_emit_copy_buffer, + .fill_max_bytes = 1 << 30, + .fill_num_dw = 5, + .emit_fill_buffer = sdma_v7_1_emit_fill_buffer, +}; + +static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev) +{ + adev->mman.buffer_funcs = &sdma_v7_1_buffer_funcs; + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; +} + +const struct amdgpu_ip_block_version sdma_v7_1_ip_block = { + .type = AMD_IP_BLOCK_TYPE_SDMA, + .major = 7, + .minor = 1, + .rev = 0, + .funcs = &sdma_v7_1_ip_funcs, +}; + +static int sdma_v7_1_xcp_resume(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int r; + + r = sdma_v7_1_inst_start(adev, inst_mask); + + return r; +} + +static int sdma_v7_1_xcp_suspend(void *handle, uint32_t inst_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + sdma_v7_1_inst_ctx_switch_enable(adev, false, inst_mask); + sdma_v7_1_inst_enable(adev, false, inst_mask); + + return 0; +} + +struct amdgpu_xcp_ip_funcs sdma_v7_1_xcp_funcs = { + .suspend = &sdma_v7_1_xcp_suspend, + .resume = &sdma_v7_1_xcp_resume +}; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.h b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.h new file mode 100644 index 0000000000000..1a07ef09a103f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.h @@ -0,0 +1,31 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __SDMA_V7_1_H__ +#define __SDMA_V7_1_H__ + +extern const struct amd_ip_funcs sdma_v7_1_ip_funcs; +extern const struct amdgpu_ip_block_version sdma_v7_1_ip_block; +extern struct amdgpu_xcp_ip_funcs sdma_v7_1_xcp_funcs; + +#endif /* __SDMA_V7_1_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1_0_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1_0_pkt_open.h new file mode 100644 index 0000000000000..b051e4f920884 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1_0_pkt_open.h @@ -0,0 +1,5673 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SDMA_V7_1_0_PKT_OPEN_H_ +#define __SDMA_V7_1_0_PKT_OPEN_H_ + +#define SDMA_OP_NOP 0 +#define SDMA_OP_COPY 1 +#define SDMA_OP_WRITE 2 +#define SDMA_OP_INDIRECT 4 +#define SDMA_OP_FENCE 5 +#define SDMA_OP_TRAP 6 +#define SDMA_OP_SEM 7 +#define SDMA_OP_POLL_REGMEM 8 +#define SDMA_OP_COND_EXE 9 +#define SDMA_OP_ATOMIC 10 +#define SDMA_OP_CONST_FILL 11 +#define SDMA_OP_PTEPDE 12 +#define SDMA_OP_TIMESTAMP 13 +#define SDMA_OP_SRBM_WRITE 14 +#define SDMA_OP_PRE_EXE 15 +#define SDMA_OP_GPUVM_INV 16 +#define SDMA_OP_GCR_REQ 17 +#define SDMA_OP_DUMMY_TRAP 32 +#define SDMA_SUBOP_TIMESTAMP_SET 0 +#define SDMA_SUBOP_TIMESTAMP_GET 1 +#define SDMA_SUBOP_TIMESTAMP_GET_GLOBAL 2 +#define SDMA_SUBOP_COPY_LINEAR 0 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND 4 +#define SDMA_SUBOP_COPY_TILED 1 +#define SDMA_SUBOP_COPY_TILED_SUB_WIND 5 +#define SDMA_SUBOP_COPY_T2T_SUB_WIND 6 +#define SDMA_SUBOP_COPY_SOA 3 +#define SDMA_SUBOP_COPY_DIRTY_PAGE 7 +#define SDMA_SUBOP_COPY_LINEAR_PHY 8 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_LARGE 36 +#define SDMA_SUBOP_COPY_LINEAR_BC 16 +#define SDMA_SUBOP_COPY_TILED_BC 17 +#define SDMA_SUBOP_COPY_LINEAR_SUB_WIND_BC 20 +#define SDMA_SUBOP_COPY_TILED_SUB_WIND_BC 21 +#define SDMA_SUBOP_COPY_T2T_SUB_WIND_BC 22 +#define SDMA_SUBOP_WRITE_LINEAR 0 +#define SDMA_SUBOP_WRITE_TILED 1 +#define SDMA_SUBOP_WRITE_TILED_BC 17 +#define SDMA_SUBOP_PTEPDE_GEN 0 +#define SDMA_SUBOP_PTEPDE_COPY 1 +#define SDMA_SUBOP_PTEPDE_RMW 2 +#define SDMA_SUBOP_PTEPDE_COPY_BACKWARDS 3 +#define SDMA_SUBOP_MEM_INCR 1 +#define SDMA_SUBOP_DATA_FILL_MULTI 1 +#define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 +#define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 +#define SDMA_SUBOP_POLL_MEM_VERIFY 3 +#define SDMA_SUBOP_VM_INVALIDATION 4 +#define HEADER_AGENT_DISPATCH 4 +#define HEADER_BARRIER 5 +#define SDMA_OP_AQL_COPY 0 +#define SDMA_OP_AQL_BARRIER_OR 0 + +#define SDMA_GCR_RANGE_IS_PA (1 << 18) +#define SDMA_GCR_SEQ(x) (((x) & 0x3) << 16) +#define SDMA_GCR_GL2_WB (1 << 15) +#define SDMA_GCR_GL2_INV (1 << 14) +#define SDMA_GCR_GL2_DISCARD (1 << 13) +#define SDMA_GCR_GL2_RANGE(x) (((x) & 0x3) << 11) +#define SDMA_GCR_GL2_US (1 << 10) +#define SDMA_GCR_GL1_INV (1 << 9) +#define SDMA_GCR_GLV_INV (1 << 8) +#define SDMA_GCR_GLK_INV (1 << 7) +#define SDMA_GCR_GLK_WB (1 << 6) +#define SDMA_GCR_GLM_INV (1 << 5) +#define SDMA_GCR_GLM_WB (1 << 4) +#define SDMA_GCR_GL1_RANGE(x) (((x) & 0x3) << 2) +#define SDMA_GCR_GLI_INV(x) (((x) & 0x3) << 0) + +#define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f) +#define SDMA_DCC_NUM_TYPE(x) (((x) & 0x7) << 9) +#define SDMA_DCC_READ_CM(x) (((x) & 0x3) << 16) +#define SDMA_DCC_WRITE_CM(x) (((x) & 0x3) << 18) +#define SDMA_DCC_MAX_COM(x) (((x) & 0x3) << 24) +#define SDMA_DCC_MAX_UCOM(x) (((x) & 0x1) << 26) + +/* +** Definitions for SDMA_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_LINEAR_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_HEADER_tmz_shift) + +/*define for npd field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_npd_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_npd_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_npd_shift 28 +#define SDMA_PKT_COPY_LINEAR_HEADER_NPD(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_npd_mask) << SDMA_PKT_COPY_LINEAR_HEADER_npd_shift) + +/*define for backwards field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift 25 +#define SDMA_PKT_COPY_LINEAR_HEADER_BACKWARDS(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_backwards_mask) << SDMA_PKT_COPY_LINEAR_HEADER_backwards_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_LINEAR_COUNT_count_mask 0x3FFFFFFF +#define SDMA_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_cache_policy field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_cache_policy field*/ +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 2 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 +#define SDMA_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_BC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_BC_HEADER_sub_op_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_offset 1 +#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift 0 +#define SDMA_PKT_COPY_LINEAR_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_COUNT_count_mask) << SDMA_PKT_COPY_LINEAR_BC_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_sw_shift) + +/*define for dst_ha field*/ +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_offset 2 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift 19 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_dst_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_offset 2 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift 27 +#define SDMA_PKT_COPY_LINEAR_BC_PARAMETER_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_mask) << SDMA_PKT_COPY_LINEAR_BC_PARAMETER_src_ha_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_BC_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_DIRTY_PAGE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_cpv_shift) + +/*define for all field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_offset 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift 31 +#define SDMA_PKT_COPY_DIRTY_PAGE_HEADER_ALL(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_mask) << SDMA_PKT_COPY_DIRTY_PAGE_HEADER_all_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_offset 1 +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_mask) << SDMA_PKT_COPY_DIRTY_PAGE_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_mtype field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask 0x00000007 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift 3 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_mtype_shift) + +/*define for dst_l2_policy field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift 6 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_l2_policy_shift) + +/*define for dst_llc field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift 8 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_llc_shift) + +/*define for src_mtype field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask 0x00000007 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift 11 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_mtype_shift) + +/*define for src_l2_policy field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift 14 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_l2_policy_shift) + +/*define for src_llc field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift 16 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_llc_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift 17 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sw_shift) + +/*define for dst_gcc field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift 19 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gcc_shift) + +/*define for dst_sys field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift 20 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_sys_shift) + +/*define for dst_snoop field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift 22 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_snoop_shift) + +/*define for dst_gpa field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift 23 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_dst_gpa_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sw_shift) + +/*define for src_sys field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift 28 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_sys_shift) + +/*define for src_snoop field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift 30 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_snoop_shift) + +/*define for src_gpa field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_offset 2 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift 31 +#define SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_DIRTY_PAGE_PARAMETER_src_gpa_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_DIRTY_PAGE_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_PHYSICAL_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_HEADER_cpv_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_count_shift) + +/*define for addr_pair_num field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_offset 1 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask 0x000000FF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift 24 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_ADDR_PAIR_NUM(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_COUNT_addr_pair_num_shift) + +/*define for PARAMETER word*/ +/*define for dst_mtype field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask 0x00000007 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift 3 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_mtype_shift) + +/*define for dst_l2_policy field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift 6 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_l2_policy_shift) + +/*define for dst_llc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift 8 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_llc_shift) + +/*define for src_mtype field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask 0x00000007 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift 11 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_MTYPE(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_mtype_shift) + +/*define for src_l2_policy field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift 14 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_L2_POLICY(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_l2_policy_shift) + +/*define for src_llc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift 16 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_LLC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_llc_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift 17 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_gcc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift 19 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gcc_shift) + +/*define for dst_sys field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift 20 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_sys_shift) + +/*define for dst_log field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift 21 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_LOG(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_log_shift) + +/*define for dst_snoop field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift 22 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_snoop_shift) + +/*define for dst_gpa field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift 23 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_DST_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_dst_gpa_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_gcc field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift 27 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GCC(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gcc_shift) + +/*define for src_sys field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift 28 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SYS(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_sys_shift) + +/*define for src_snoop field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift 30 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_SNOOP(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_snoop_shift) + +/*define for src_gpa field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_offset 2 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask 0x00000001 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift 31 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_SRC_GPA(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_PARAMETER_src_gpa_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 5 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 6 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_PHYSICAL_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_BROADCAST_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_cpv_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_HEADER_broadcast_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_offset 1 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask 0x3FFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_sw_shift) + +/*define for dst2_cache_policy field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift 10 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst2_cache_policy_shift) + +/*define for dst1_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift 16 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_sw_shift) + +/*define for dst1_cache_policy field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift 18 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_DST1_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_dst1_cache_policy_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_cache_policy field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_offset 2 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift 26 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_PARAMETER_src_cache_policy_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 3 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 4 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST1_ADDR_LO word*/ +/*define for dst1_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_offset 5 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_DST1_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_LO_dst1_addr_31_0_shift) + +/*define for DST1_ADDR_HI word*/ +/*define for dst1_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_offset 6 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_DST1_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST1_ADDR_HI_dst1_addr_63_32_shift) + +/*define for DST2_ADDR_LO word*/ +/*define for dst2_addr_31_0 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_offset 7 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_DST2_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_LO_dst2_addr_31_0_shift) + +/*define for DST2_ADDR_HI word*/ +/*define for dst2_addr_63_32 field*/ +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_offset 8 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift 0 +#define SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_DST2_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_mask) << SDMA_PKT_COPY_BROADCAST_LINEAR_DST2_ADDR_HI_dst2_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_cpv_shift) + +/*define for elementsize field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift 29 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_HEADER_elementsize_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask 0x00001FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_z_shift) + +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_4_src_pitch_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_5_src_slice_pitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_8 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_8_dst_y_shift) + +/*define for DW_9 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask 0x00001FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_z_shift) + +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_9_dst_pitch_shift) + +/*define for DW_10 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_10_dst_slice_pitch_shift) + +/*define for DW_11 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_11_rect_y_shift) + +/*define for DW_12 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask 0x00001FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_sw_shift) + +/*define for dst_cache_policy field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_dst_cache_policy_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_sw_shift) + +/*define for src_cache_policy field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift 26 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_DW_12_src_cache_policy_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_HEADER_cpv_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_3_src_x_shift) + +/*define for DW_4 word*/ +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_4_src_y_shift) + +/*define for DW_5 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_5_src_z_shift) + +/*define for DW_6 word*/ +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_6_src_pitch_shift) + +/*define for DW_7 word*/ +/*define for src_slice_pitch_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_SRC_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_7_src_slice_pitch_31_0_shift) + +/*define for DW_8 word*/ +/*define for src_slice_pitch_47_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask 0x0000FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_SRC_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_8_src_slice_pitch_47_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_11 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_11_dst_x_shift) + +/*define for DW_12 word*/ +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_12_dst_y_shift) + +/*define for DW_13 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_offset 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_13_dst_z_shift) + +/*define for DW_14 word*/ +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_offset 14 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_14_dst_pitch_shift) + +/*define for DW_15 word*/ +/*define for dst_slice_pitch_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_offset 15 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_DST_SLICE_PITCH_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_15_dst_slice_pitch_31_0_shift) + +/*define for DW_16 word*/ +/*define for dst_slice_pitch_47_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_offset 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask 0x0000FFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SLICE_PITCH_47_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_slice_pitch_47_32_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_offset 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_sw_shift) + +/*define for dst_policy field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_offset 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_DST_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_dst_policy_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_offset 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_sw_shift) + +/*define for src_policy field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_offset 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift 26 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_SRC_POLICY(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_16_src_policy_shift) + +/*define for DW_17 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_offset 17 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_17_rect_x_shift) + +/*define for DW_18 word*/ +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_offset 18 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_18_rect_y_shift) + +/*define for DW_19 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_offset 19 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_LARGE_DW_19_rect_z_shift) + + +/* +** Definitions for SDMA_PKT_COPY_LINEAR_SUBWIN_BC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_sub_op_shift) + +/*define for elementsize field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_offset 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask 0x00000007 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift 29 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_ELEMENTSIZE(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_HEADER_elementsize_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_z_shift) + +/*define for src_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_offset 4 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_SRC_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_4_src_pitch_shift) + +/*define for DW_5 word*/ +/*define for src_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_offset 5 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_SRC_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_5_src_slice_pitch_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_offset 6 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_offset 7 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_8 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_offset 8 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_DST_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_8_dst_y_shift) + +/*define for DW_9 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_z_shift) + +/*define for dst_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_offset 9 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift 13 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_DST_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_9_dst_pitch_shift) + +/*define for DW_10 word*/ +/*define for dst_slice_pitch field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_offset 10 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_DST_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_10_dst_slice_pitch_shift) + +/*define for DW_11 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_X(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_offset 11 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_RECT_Y(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_11_rect_y_shift) + +/*define for DW_12 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift 0 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_RECT_Z(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift 16 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_sw_shift) + +/*define for dst_ha field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift 19 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_DST_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_dst_ha_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift 24 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_SW(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_sw_shift) + +/*define for src_ha field*/ +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_offset 12 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask 0x00000001 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift 27 +#define SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_SRC_HA(x) (((x) & SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_mask) << SDMA_PKT_COPY_LINEAR_SUBWIN_BC_DW_12_src_ha_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_op_mask) << SDMA_PKT_COPY_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_encrypt_mask) << SDMA_PKT_COPY_TILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_TILED_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_TILED_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_HEADER_cpv_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_DW_3_width_offset 3 +#define SDMA_PKT_COPY_TILED_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_3_width_shift 0 +#define SDMA_PKT_COPY_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_3_width_mask) << SDMA_PKT_COPY_TILED_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_DW_4_height_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_4_height_shift 0 +#define SDMA_PKT_COPY_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_height_mask) << SDMA_PKT_COPY_TILED_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_DW_4_depth_offset 4 +#define SDMA_PKT_COPY_TILED_DW_4_depth_mask 0x00001FFF +#define SDMA_PKT_COPY_TILED_DW_4_depth_shift 16 +#define SDMA_PKT_COPY_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_DW_5_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_DW_5_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_TILED_DW_5_dimension_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_5_dimension_shift 9 +#define SDMA_PKT_COPY_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_dimension_mask) << SDMA_PKT_COPY_TILED_DW_5_dimension_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_TILED_DW_5_mip_max_offset 5 +#define SDMA_PKT_COPY_TILED_DW_5_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_DW_5_mip_max_shift 16 +#define SDMA_PKT_COPY_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_DW_5_mip_max_mask) << SDMA_PKT_COPY_TILED_DW_5_mip_max_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_TILED_DW_6_x_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_x_shift 0 +#define SDMA_PKT_COPY_TILED_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_x_mask) << SDMA_PKT_COPY_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_TILED_DW_6_y_offset 6 +#define SDMA_PKT_COPY_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_DW_6_y_shift 16 +#define SDMA_PKT_COPY_TILED_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_DW_6_y_mask) << SDMA_PKT_COPY_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_TILED_DW_7_z_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_z_mask 0x00001FFF +#define SDMA_PKT_COPY_TILED_DW_7_z_shift 0 +#define SDMA_PKT_COPY_TILED_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_z_mask) << SDMA_PKT_COPY_TILED_DW_7_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_sw_shift) + +/*define for linear_cache_policy field*/ +#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift 18 +#define SDMA_PKT_COPY_TILED_DW_7_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_linear_cache_policy_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_sw_shift) + +/*define for tile_cache_policy field*/ +#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_offset 7 +#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift 26 +#define SDMA_PKT_COPY_TILED_DW_7_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_DW_7_tile_cache_policy_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_TILED_COUNT_count_offset 12 +#define SDMA_PKT_COPY_TILED_COUNT_count_mask 0x3FFFFFFF +#define SDMA_PKT_COPY_TILED_COUNT_count_shift 0 +#define SDMA_PKT_COPY_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_COUNT_count_mask) << SDMA_PKT_COPY_TILED_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_BC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_BC_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_BC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_BC_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_BC_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_3_width_offset 3 +#define SDMA_PKT_COPY_TILED_BC_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_BC_DW_3_width_shift 0 +#define SDMA_PKT_COPY_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_3_width_mask) << SDMA_PKT_COPY_TILED_BC_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_4_height_offset 4 +#define SDMA_PKT_COPY_TILED_BC_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_BC_DW_4_height_shift 0 +#define SDMA_PKT_COPY_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_height_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_offset 4 +#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift 16 +#define SDMA_PKT_COPY_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_4_depth_mask) << SDMA_PKT_COPY_TILED_BC_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift 3 +#define SDMA_PKT_COPY_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift 8 +#define SDMA_PKT_COPY_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift 15 +#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift 18 +#define SDMA_PKT_COPY_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift 21 +#define SDMA_PKT_COPY_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift 24 +#define SDMA_PKT_COPY_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_offset 5 +#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift 26 +#define SDMA_PKT_COPY_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_COPY_TILED_BC_DW_5_pipe_config_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_6_x_offset 6 +#define SDMA_PKT_COPY_TILED_BC_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_BC_DW_6_x_shift 0 +#define SDMA_PKT_COPY_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_x_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_6_y_offset 6 +#define SDMA_PKT_COPY_TILED_BC_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_BC_DW_6_y_shift 16 +#define SDMA_PKT_COPY_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_6_y_mask) << SDMA_PKT_COPY_TILED_BC_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_7_z_offset 7 +#define SDMA_PKT_COPY_TILED_BC_DW_7_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_BC_DW_7_z_shift 0 +#define SDMA_PKT_COPY_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_z_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_offset 7 +#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_BC_DW_7_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_offset 7 +#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_BC_DW_7_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_mask) << SDMA_PKT_COPY_TILED_BC_DW_7_tile_sw_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 8 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 9 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_BC_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_TILED_BC_COUNT_count_offset 12 +#define SDMA_PKT_COPY_TILED_BC_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_COPY_TILED_BC_COUNT_count_shift 2 +#define SDMA_PKT_COPY_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_TILED_BC_COUNT_count_mask) << SDMA_PKT_COPY_TILED_BC_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_L2T_BROADCAST packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift 19 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_cpv_shift) + +/*define for videocopy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_VIDEOCOPY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_videocopy_shift) + +/*define for broadcast field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_offset 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask 0x00000001 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift 27 +#define SDMA_PKT_COPY_L2T_BROADCAST_HEADER_BROADCAST(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_mask) << SDMA_PKT_COPY_L2T_BROADCAST_HEADER_broadcast_shift) + +/*define for TILED_ADDR_LO_0 word*/ +/*define for tiled_addr0_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_offset 1 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_TILED_ADDR0_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_0_tiled_addr0_31_0_shift) + +/*define for TILED_ADDR_HI_0 word*/ +/*define for tiled_addr0_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_offset 2 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_TILED_ADDR0_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_0_tiled_addr0_63_32_shift) + +/*define for TILED_ADDR_LO_1 word*/ +/*define for tiled_addr1_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_offset 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_TILED_ADDR1_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_LO_1_tiled_addr1_31_0_shift) + +/*define for TILED_ADDR_HI_1 word*/ +/*define for tiled_addr1_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_offset 4 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_TILED_ADDR1_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_TILED_ADDR_HI_1_tiled_addr1_63_32_shift) + +/*define for DW_5 word*/ +/*define for width field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_offset 5 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_5_WIDTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_5_width_shift) + +/*define for DW_6 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_HEIGHT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_offset 6 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask 0x00001FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_6_DEPTH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_6_depth_shift) + +/*define for DW_7 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_DIMENSION(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_dimension_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_offset 7 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_7_MIP_MAX(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_7_mip_max_shift) + +/*define for DW_8 word*/ +/*define for x field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_X(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_x_shift) + +/*define for y field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_offset 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask 0x00003FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_8_Y(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_8_y_shift) + +/*define for DW_9 word*/ +/*define for z field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_offset 9 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask 0x00001FFF +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_9_Z(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_9_z_shift) + +/*define for DW_10 word*/ +/*define for dst2_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift 8 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_sw_shift) + +/*define for dst2_cache_policy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_DST2_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_dst2_cache_policy_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift 16 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_sw_shift) + +/*define for linear_cache_policy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift 18 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_linear_cache_policy_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift 24 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_SW(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_sw_shift) + +/*define for tile_cache_policy field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_offset 10 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift 26 +#define SDMA_PKT_COPY_L2T_BROADCAST_DW_10_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_mask) << SDMA_PKT_COPY_L2T_BROADCAST_DW_10_tile_cache_policy_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_offset 11 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_offset 12 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for LINEAR_PITCH word*/ +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_offset 13 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask 0x0007FFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_PITCH_linear_pitch_shift) + +/*define for LINEAR_SLICE_PITCH word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_offset 14 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_mask) << SDMA_PKT_COPY_L2T_BROADCAST_LINEAR_SLICE_PITCH_linear_slice_pitch_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_offset 15 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask 0x3FFFFFFF +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift 0 +#define SDMA_PKT_COPY_L2T_BROADCAST_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_mask) << SDMA_PKT_COPY_L2T_BROADCAST_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_COPY_T2T packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_op_shift 0 +#define SDMA_PKT_COPY_T2T_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_op_mask) << SDMA_PKT_COPY_T2T_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_T2T_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_T2T_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_T2T_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_tmz_mask) << SDMA_PKT_COPY_T2T_HEADER_tmz_shift) + +/*define for dcc field*/ +#define SDMA_PKT_COPY_T2T_HEADER_dcc_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_dcc_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_HEADER_dcc_shift 19 +#define SDMA_PKT_COPY_T2T_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_T2T_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_HEADER_cpv_shift 28 +#define SDMA_PKT_COPY_T2T_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_cpv_mask) << SDMA_PKT_COPY_T2T_HEADER_cpv_shift) + +/*define for dcc_dir field*/ +#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_offset 0 +#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift 31 +#define SDMA_PKT_COPY_T2T_HEADER_DCC_DIR(x) (((x) & SDMA_PKT_COPY_T2T_HEADER_dcc_dir_mask) << SDMA_PKT_COPY_T2T_HEADER_dcc_dir_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_T2T_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_T2T_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_z_mask 0x00001FFF +#define SDMA_PKT_COPY_T2T_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_DW_4_src_z_shift) + +/*define for src_width field*/ +#define SDMA_PKT_COPY_T2T_DW_4_src_width_offset 4 +#define SDMA_PKT_COPY_T2T_DW_4_src_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_4_src_width_shift 16 +#define SDMA_PKT_COPY_T2T_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_DW_4_src_width_shift) + +/*define for DW_5 word*/ +/*define for src_height field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_height_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_5_src_height_shift 0 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_DW_5_src_height_shift) + +/*define for src_depth field*/ +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_offset 5 +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_mask 0x00001FFF +#define SDMA_PKT_COPY_T2T_DW_5_src_depth_shift 16 +#define SDMA_PKT_COPY_T2T_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_DW_5_src_depth_shift) + +/*define for DW_6 word*/ +/*define for src_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_DW_6_src_element_size_shift) + +/*define for src_swizzle_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_6_src_swizzle_mode_shift) + +/*define for src_dimension field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift 9 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_dimension_mask) << SDMA_PKT_COPY_T2T_DW_6_src_dimension_shift) + +/*define for src_mip_max field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift 16 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_max_shift) + +/*define for src_mip_id field*/ +#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_offset 6 +#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift 20 +#define SDMA_PKT_COPY_T2T_DW_6_SRC_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_6_src_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_6_src_mip_id_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_offset 7 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_offset 8 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_offset 9 +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_9_dst_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_DW_9_dst_y_shift) + +/*define for DW_10 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_mask 0x00001FFF +#define SDMA_PKT_COPY_T2T_DW_10_dst_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_z_shift) + +/*define for dst_width field*/ +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_offset 10 +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_10_dst_width_shift 16 +#define SDMA_PKT_COPY_T2T_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_DW_10_dst_width_shift) + +/*define for DW_11 word*/ +/*define for dst_height field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_11_dst_height_shift 0 +#define SDMA_PKT_COPY_T2T_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_height_shift) + +/*define for dst_depth field*/ +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_offset 11 +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask 0x00001FFF +#define SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift 16 +#define SDMA_PKT_COPY_T2T_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_DW_11_dst_depth_shift) + +/*define for DW_12 word*/ +/*define for dst_element_size field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_element_size_shift) + +/*define for dst_swizzle_mode field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_T2T_DW_12_DST_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_swizzle_mode_shift) + +/*define for dst_dimension field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift 9 +#define SDMA_PKT_COPY_T2T_DW_12_DST_DIMENSION(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_dimension_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_dimension_shift) + +/*define for dst_mip_max field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift 16 +#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_MAX(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_max_shift) + +/*define for dst_mip_id field*/ +#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_offset 12 +#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift 20 +#define SDMA_PKT_COPY_T2T_DW_12_DST_MIP_ID(x) (((x) & SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_mask) << SDMA_PKT_COPY_T2T_DW_12_dst_mip_id_shift) + +/*define for DW_13 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_x_shift 0 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_offset 13 +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_DW_13_rect_y_shift 16 +#define SDMA_PKT_COPY_T2T_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_DW_13_rect_y_shift) + +/*define for DW_14 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_mask 0x00001FFF +#define SDMA_PKT_COPY_T2T_DW_14_rect_z_shift 0 +#define SDMA_PKT_COPY_T2T_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_DW_14_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift 16 +#define SDMA_PKT_COPY_T2T_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_sw_shift) + +/*define for dst_cache_policy field*/ +#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift 18 +#define SDMA_PKT_COPY_T2T_DW_14_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_dst_cache_policy_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_DW_14_src_sw_shift 24 +#define SDMA_PKT_COPY_T2T_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_DW_14_src_sw_shift) + +/*define for src_cache_policy field*/ +#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_offset 14 +#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift 26 +#define SDMA_PKT_COPY_T2T_DW_14_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_mask) << SDMA_PKT_COPY_T2T_DW_14_src_cache_policy_shift) + +/*define for META_ADDR_LO word*/ +/*define for meta_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_offset 15 +#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_T2T_META_ADDR_LO_meta_addr_31_0_shift) + +/*define for META_ADDR_HI word*/ +/*define for meta_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_offset 16 +#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_T2T_META_ADDR_HI_meta_addr_63_32_shift) + +/*define for META_CONFIG word*/ +/*define for data_format field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask 0x0000007F +#define SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift 0 +#define SDMA_PKT_COPY_T2T_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_data_format_shift) + +/*define for color_transform_disable field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift 7 +#define SDMA_PKT_COPY_T2T_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_color_transform_disable_shift) + +/*define for alpha_is_on_msb field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift 8 +#define SDMA_PKT_COPY_T2T_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_alpha_is_on_msb_shift) + +/*define for number_type field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift 9 +#define SDMA_PKT_COPY_T2T_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_number_type_shift) + +/*define for surface_type field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift 12 +#define SDMA_PKT_COPY_T2T_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_surface_type_shift) + +/*define for meta_llc field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift 14 +#define SDMA_PKT_COPY_T2T_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_llc_shift) + +/*define for max_comp_block_size field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift 24 +#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_comp_block_size_shift) + +/*define for max_uncomp_block_size field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift 26 +#define SDMA_PKT_COPY_T2T_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_max_uncomp_block_size_shift) + +/*define for write_compress_enable field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift 28 +#define SDMA_PKT_COPY_T2T_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_write_compress_enable_shift) + +/*define for meta_tmz field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift 29 +#define SDMA_PKT_COPY_T2T_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_meta_tmz_shift) + +/*define for pipe_aligned field*/ +#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_offset 17 +#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask 0x00000001 +#define SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift 31 +#define SDMA_PKT_COPY_T2T_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_T2T_META_CONFIG_pipe_aligned_shift) + + +/* +** Definitions for SDMA_PKT_COPY_T2T_BC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_T2T_BC_HEADER_op_offset 0 +#define SDMA_PKT_COPY_T2T_BC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_BC_HEADER_op_shift 0 +#define SDMA_PKT_COPY_T2T_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_T2T_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_T2T_BC_HEADER_sub_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for src_x field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_offset 3 +#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_x_shift) + +/*define for src_y field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_offset 3 +#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_3_SRC_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_3_src_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_3_src_y_shift) + +/*define for DW_4 word*/ +/*define for src_z field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_offset 4 +#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_z_shift) + +/*define for src_width field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_offset 4 +#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_4_SRC_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_4_src_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_4_src_width_shift) + +/*define for DW_5 word*/ +/*define for src_height field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_offset 5 +#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_height_shift) + +/*define for src_depth field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_offset 5 +#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_5_SRC_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_5_src_depth_shift) + +/*define for DW_6 word*/ +/*define for src_element_size field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_element_size_shift) + +/*define for src_array_mode field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift 3 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_array_mode_shift) + +/*define for src_mit_mode field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift 8 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mit_mode_shift) + +/*define for src_tilesplit_size field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_tilesplit_size_shift) + +/*define for src_bank_w field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift 15 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_w_shift) + +/*define for src_bank_h field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift 18 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_bank_h_shift) + +/*define for src_num_bank field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift 21 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_num_bank_shift) + +/*define for src_mat_aspt field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift 24 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_mat_aspt_shift) + +/*define for src_pipe_config field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_offset 6 +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift 26 +#define SDMA_PKT_COPY_T2T_BC_DW_6_SRC_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_6_src_pipe_config_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_offset 7 +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_offset 8 +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_COPY_T2T_BC_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for dst_x field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_offset 9 +#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_x_shift) + +/*define for dst_y field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_offset 9 +#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_9_DST_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_9_dst_y_shift) + +/*define for DW_10 word*/ +/*define for dst_z field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_offset 10 +#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_z_shift) + +/*define for dst_width field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_offset 10 +#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_10_DST_WIDTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_mask) << SDMA_PKT_COPY_T2T_BC_DW_10_dst_width_shift) + +/*define for DW_11 word*/ +/*define for dst_height field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_offset 11 +#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_HEIGHT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_height_shift) + +/*define for dst_depth field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_offset 11 +#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask 0x00000FFF +#define SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_11_DST_DEPTH(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_mask) << SDMA_PKT_COPY_T2T_BC_DW_11_dst_depth_shift) + +/*define for DW_12 word*/ +/*define for dst_element_size field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_element_size_shift) + +/*define for dst_array_mode field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift 3 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_array_mode_shift) + +/*define for dst_mit_mode field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift 8 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MIT_MODE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mit_mode_shift) + +/*define for dst_tilesplit_size field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_tilesplit_size_shift) + +/*define for dst_bank_w field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift 15 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_W(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_w_shift) + +/*define for dst_bank_h field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift 18 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_BANK_H(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_bank_h_shift) + +/*define for dst_num_bank field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift 21 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_NUM_BANK(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_num_bank_shift) + +/*define for dst_mat_aspt field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift 24 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_mat_aspt_shift) + +/*define for dst_pipe_config field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_offset 12 +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift 26 +#define SDMA_PKT_COPY_T2T_BC_DW_12_DST_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_mask) << SDMA_PKT_COPY_T2T_BC_DW_12_dst_pipe_config_shift) + +/*define for DW_13 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_offset 13 +#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_X(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_offset 13 +#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_13_RECT_Y(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_mask) << SDMA_PKT_COPY_T2T_BC_DW_13_rect_y_shift) + +/*define for DW_14 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_offset 14 +#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift 0 +#define SDMA_PKT_COPY_T2T_BC_DW_14_RECT_Z(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_rect_z_shift) + +/*define for dst_sw field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_offset 14 +#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift 16 +#define SDMA_PKT_COPY_T2T_BC_DW_14_DST_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_dst_sw_shift) + +/*define for src_sw field*/ +#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_offset 14 +#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask 0x00000003 +#define SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift 24 +#define SDMA_PKT_COPY_T2T_BC_DW_14_SRC_SW(x) (((x) & SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_mask) << SDMA_PKT_COPY_T2T_BC_DW_14_src_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_SUBWIN packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_tmz_shift) + +/*define for dcc field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift 19 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DCC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_dcc_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift 28 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_cpv_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for tiled_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_x_shift) + +/*define for tiled_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_3_tiled_y_shift) + +/*define for DW_4 word*/ +/*define for tiled_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask 0x00001FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_tiled_z_shift) + +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_4_width_shift) + +/*define for DW_5 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask 0x00001FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_5_depth_shift) + +/*define for DW_6 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_SWIZZLE_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_DIMENSION(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_dimension_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_MAX(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_max_shift) + +/*define for mip_id field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift 20 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_6_MIP_ID(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_6_mip_id_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for linear_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_x_shift) + +/*define for linear_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_9_linear_y_shift) + +/*define for DW_10 word*/ +/*define for linear_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask 0x00001FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_z_shift) + +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_10_linear_pitch_shift) + +/*define for DW_11 word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_11_linear_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_12_rect_y_shift) + +/*define for DW_13 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask 0x00001FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_rect_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_sw_shift) + +/*define for linear_cache_policy field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_linear_cache_policy_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_sw_shift) + +/*define for tile_cache_policy field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift 26 +#define SDMA_PKT_COPY_TILED_SUBWIN_DW_13_TILE_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_mask) << SDMA_PKT_COPY_TILED_SUBWIN_DW_13_tile_cache_policy_shift) + +/*define for META_ADDR_LO word*/ +/*define for meta_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_offset 14 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_META_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_LO_meta_addr_31_0_shift) + +/*define for META_ADDR_HI word*/ +/*define for meta_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_offset 15 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_META_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_ADDR_HI_meta_addr_63_32_shift) + +/*define for META_CONFIG word*/ +/*define for data_format field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask 0x0000007F +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_DATA_FORMAT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_data_format_shift) + +/*define for color_transform_disable field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_COLOR_TRANSFORM_DISABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_color_transform_disable_shift) + +/*define for alpha_is_on_msb field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_ALPHA_IS_ON_MSB(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_alpha_is_on_msb_shift) + +/*define for number_type field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_NUMBER_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_number_type_shift) + +/*define for surface_type field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_SURFACE_TYPE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_surface_type_shift) + +/*define for meta_llc field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift 14 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_LLC(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_llc_shift) + +/*define for max_comp_block_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_COMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_comp_block_size_shift) + +/*define for max_uncomp_block_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift 26 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_MAX_UNCOMP_BLOCK_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_max_uncomp_block_size_shift) + +/*define for write_compress_enable field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift 28 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_WRITE_COMPRESS_ENABLE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_write_compress_enable_shift) + +/*define for meta_tmz field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift 29 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_META_TMZ(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_meta_tmz_shift) + +/*define for pipe_aligned field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_offset 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_PIPE_ALIGNED(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_mask) << SDMA_PKT_COPY_TILED_SUBWIN_META_CONFIG_pipe_aligned_shift) + + +/* +** Definitions for SDMA_PKT_COPY_TILED_SUBWIN_BC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_sub_op_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_HEADER_detile_shift) + +/*define for TILED_ADDR_LO word*/ +/*define for tiled_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_offset 1 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_TILED_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_LO_tiled_addr_31_0_shift) + +/*define for TILED_ADDR_HI word*/ +/*define for tiled_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_offset 2 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_TILED_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_TILED_ADDR_HI_tiled_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for tiled_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_x_shift) + +/*define for tiled_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_offset 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_TILED_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_3_tiled_y_shift) + +/*define for DW_4 word*/ +/*define for tiled_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_TILED_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_tiled_z_shift) + +/*define for width field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_offset 4 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_WIDTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_4_width_shift) + +/*define for DW_5 word*/ +/*define for height field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_HEIGHT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_offset 5 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_DEPTH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_5_depth_shift) + +/*define for DW_6 word*/ +/*define for element_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ELEMENT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask 0x0000000F +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift 3 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_ARRAY_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MIT_MODE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift 15 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_W(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift 18 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_BANK_H(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift 21 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_NUM_BANK(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_MAT_ASPT(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_offset 6 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask 0x0000001F +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift 26 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_PIPE_CONFIG(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_6_pipe_config_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_offset 7 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_offset 8 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_LINEAR_ADDR_HI_linear_addr_63_32_shift) + +/*define for DW_9 word*/ +/*define for linear_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_x_shift) + +/*define for linear_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_offset 9 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_LINEAR_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_9_linear_y_shift) + +/*define for DW_10 word*/ +/*define for linear_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_z_shift) + +/*define for linear_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_offset 10 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_LINEAR_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_10_linear_pitch_shift) + +/*define for DW_11 word*/ +/*define for linear_slice_pitch field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_offset 11 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask 0x0FFFFFFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_LINEAR_SLICE_PITCH(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_11_linear_slice_pitch_shift) + +/*define for DW_12 word*/ +/*define for rect_x field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_X(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_x_shift) + +/*define for rect_y field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_offset 12 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask 0x00003FFF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_RECT_Y(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_12_rect_y_shift) + +/*define for DW_13 word*/ +/*define for rect_z field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask 0x000007FF +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift 0 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_RECT_Z(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_rect_z_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift 16 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_linear_sw_shift) + +/*define for tile_sw field*/ +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_offset 13 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask 0x00000003 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift 24 +#define SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_TILE_SW(x) (((x) & SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_mask) << SDMA_PKT_COPY_TILED_SUBWIN_BC_DW_13_tile_sw_shift) + + +/* +** Definitions for SDMA_PKT_COPY_STRUCT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_op_shift 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift 8 +#define SDMA_PKT_COPY_STRUCT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_sub_op_mask) << SDMA_PKT_COPY_STRUCT_HEADER_sub_op_shift) + +/*define for tmz field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift 18 +#define SDMA_PKT_COPY_STRUCT_HEADER_TMZ(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_tmz_mask) << SDMA_PKT_COPY_STRUCT_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift 28 +#define SDMA_PKT_COPY_STRUCT_HEADER_CPV(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_cpv_mask) << SDMA_PKT_COPY_STRUCT_HEADER_cpv_shift) + +/*define for detile field*/ +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_offset 0 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_mask 0x00000001 +#define SDMA_PKT_COPY_STRUCT_HEADER_detile_shift 31 +#define SDMA_PKT_COPY_STRUCT_HEADER_DETILE(x) (((x) & SDMA_PKT_COPY_STRUCT_HEADER_detile_mask) << SDMA_PKT_COPY_STRUCT_HEADER_detile_shift) + +/*define for SB_ADDR_LO word*/ +/*define for sb_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_offset 1 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_SB_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_LO_sb_addr_31_0_shift) + +/*define for SB_ADDR_HI word*/ +/*define for sb_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_offset 2 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_SB_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_SB_ADDR_HI_sb_addr_63_32_shift) + +/*define for START_INDEX word*/ +/*define for start_index field*/ +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_offset 3 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift 0 +#define SDMA_PKT_COPY_STRUCT_START_INDEX_START_INDEX(x) (((x) & SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_mask) << SDMA_PKT_COPY_STRUCT_START_INDEX_start_index_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_COPY_STRUCT_COUNT_count_offset 4 +#define SDMA_PKT_COPY_STRUCT_COUNT_count_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_COUNT_count_shift 0 +#define SDMA_PKT_COPY_STRUCT_COUNT_COUNT(x) (((x) & SDMA_PKT_COPY_STRUCT_COUNT_count_mask) << SDMA_PKT_COPY_STRUCT_COUNT_count_shift) + +/*define for DW_5 word*/ +/*define for stride field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_mask 0x000007FF +#define SDMA_PKT_COPY_STRUCT_DW_5_stride_shift 0 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRIDE(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_stride_mask) << SDMA_PKT_COPY_STRUCT_DW_5_stride_shift) + +/*define for linear_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift 16 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_sw_shift) + +/*define for linear_cache_policy field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift 18 +#define SDMA_PKT_COPY_STRUCT_DW_5_LINEAR_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_linear_cache_policy_shift) + +/*define for struct_sw field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask 0x00000003 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift 24 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_SW(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_sw_shift) + +/*define for struct_cache_policy field*/ +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_offset 5 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask 0x00000007 +#define SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift 26 +#define SDMA_PKT_COPY_STRUCT_DW_5_STRUCT_CACHE_POLICY(x) (((x) & SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_mask) << SDMA_PKT_COPY_STRUCT_DW_5_struct_cache_policy_shift) + +/*define for LINEAR_ADDR_LO word*/ +/*define for linear_addr_31_0 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_offset 6 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_LINEAR_ADDR_31_0(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_LO_linear_addr_31_0_shift) + +/*define for LINEAR_ADDR_HI word*/ +/*define for linear_addr_63_32 field*/ +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_offset 7 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift 0 +#define SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_LINEAR_ADDR_63_32(x) (((x) & SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_mask) << SDMA_PKT_COPY_STRUCT_LINEAR_ADDR_HI_linear_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_UNTILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_UNTILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_WRITE_UNTILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift 18 +#define SDMA_PKT_WRITE_UNTILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_offset 0 +#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift 28 +#define SDMA_PKT_WRITE_UNTILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_UNTILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_UNTILED_HEADER_cpv_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_UNTILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_UNTILED_DW_3_count_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_count_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_count_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift 24 +#define SDMA_PKT_WRITE_UNTILED_DW_3_SW(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_sw_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_sw_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_offset 3 +#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask 0x00000007 +#define SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift 26 +#define SDMA_PKT_WRITE_UNTILED_DW_3_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_mask) << SDMA_PKT_WRITE_UNTILED_DW_3_cache_policy_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_offset 4 +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_UNTILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_UNTILED_DATA0_data0_mask) << SDMA_PKT_WRITE_UNTILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_TILED packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_TILED_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_TILED_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_HEADER_sub_op_shift) + +/*define for encrypt field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift 16 +#define SDMA_PKT_WRITE_TILED_HEADER_ENCRYPT(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_encrypt_mask) << SDMA_PKT_WRITE_TILED_HEADER_encrypt_shift) + +/*define for tmz field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_tmz_shift 18 +#define SDMA_PKT_WRITE_TILED_HEADER_TMZ(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_tmz_mask) << SDMA_PKT_WRITE_TILED_HEADER_tmz_shift) + +/*define for cpv field*/ +#define SDMA_PKT_WRITE_TILED_HEADER_cpv_offset 0 +#define SDMA_PKT_WRITE_TILED_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_WRITE_TILED_HEADER_cpv_shift 28 +#define SDMA_PKT_WRITE_TILED_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_TILED_HEADER_cpv_mask) << SDMA_PKT_WRITE_TILED_HEADER_cpv_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_TILED_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_WRITE_TILED_DW_3_width_offset 3 +#define SDMA_PKT_WRITE_TILED_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_3_width_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_height_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_4_height_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_WRITE_TILED_DW_4_depth_offset 4 +#define SDMA_PKT_WRITE_TILED_DW_4_depth_mask 0x00001FFF +#define SDMA_PKT_WRITE_TILED_DW_4_depth_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_5_element_size_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_DW_5_element_size_shift) + +/*define for swizzle_mode field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask 0x0000001F +#define SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift 3 +#define SDMA_PKT_WRITE_TILED_DW_5_SWIZZLE_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_mask) << SDMA_PKT_WRITE_TILED_DW_5_swizzle_mode_shift) + +/*define for dimension field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_5_dimension_shift 9 +#define SDMA_PKT_WRITE_TILED_DW_5_DIMENSION(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_dimension_mask) << SDMA_PKT_WRITE_TILED_DW_5_dimension_shift) + +/*define for mip_max field*/ +#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_offset 5 +#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask 0x0000000F +#define SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_5_MIP_MAX(x) (((x) & SDMA_PKT_WRITE_TILED_DW_5_mip_max_mask) << SDMA_PKT_WRITE_TILED_DW_5_mip_max_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_x_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_x_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_WRITE_TILED_DW_6_y_offset 6 +#define SDMA_PKT_WRITE_TILED_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_DW_6_y_shift 16 +#define SDMA_PKT_WRITE_TILED_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_z_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_z_mask 0x00001FFF +#define SDMA_PKT_WRITE_TILED_DW_7_z_shift 0 +#define SDMA_PKT_WRITE_TILED_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_DW_7_z_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_sw_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_DW_7_sw_shift 24 +#define SDMA_PKT_WRITE_TILED_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_DW_7_sw_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_offset 7 +#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift 26 +#define SDMA_PKT_WRITE_TILED_DW_7_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_TILED_DW_7_cache_policy_mask) << SDMA_PKT_WRITE_TILED_DW_7_cache_policy_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_TILED_COUNT_count_offset 8 +#define SDMA_PKT_WRITE_TILED_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_TILED_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_TILED_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_COUNT_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_TILED_DATA0_data0_offset 9 +#define SDMA_PKT_WRITE_TILED_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_TILED_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_TILED_BC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_TILED_BC_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_mask) << SDMA_PKT_WRITE_TILED_BC_HEADER_sub_op_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_TILED_BC_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DW_3 word*/ +/*define for width field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_offset 3 +#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DW_3_WIDTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_3_width_mask) << SDMA_PKT_WRITE_TILED_BC_DW_3_width_shift) + +/*define for DW_4 word*/ +/*define for height field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_offset 4 +#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DW_4_HEIGHT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_height_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_height_shift) + +/*define for depth field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_offset 4 +#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift 16 +#define SDMA_PKT_WRITE_TILED_BC_DW_4_DEPTH(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_4_depth_mask) << SDMA_PKT_WRITE_TILED_BC_DW_4_depth_shift) + +/*define for DW_5 word*/ +/*define for element_size field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_ELEMENT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_element_size_shift) + +/*define for array_mode field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask 0x0000000F +#define SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift 3 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_ARRAY_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_array_mode_shift) + +/*define for mit_mode field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift 8 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_MIT_MODE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mit_mode_shift) + +/*define for tilesplit_size field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask 0x00000007 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift 11 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_TILESPLIT_SIZE(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_tilesplit_size_shift) + +/*define for bank_w field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift 15 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_W(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_w_shift) + +/*define for bank_h field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift 18 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_BANK_H(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_bank_h_shift) + +/*define for num_bank field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift 21 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_NUM_BANK(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_num_bank_shift) + +/*define for mat_aspt field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift 24 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_MAT_ASPT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_mat_aspt_shift) + +/*define for pipe_config field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_offset 5 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask 0x0000001F +#define SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift 26 +#define SDMA_PKT_WRITE_TILED_BC_DW_5_PIPE_CONFIG(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_mask) << SDMA_PKT_WRITE_TILED_BC_DW_5_pipe_config_shift) + +/*define for DW_6 word*/ +/*define for x field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_offset 6 +#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DW_6_X(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_x_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_x_shift) + +/*define for y field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_offset 6 +#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask 0x00003FFF +#define SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift 16 +#define SDMA_PKT_WRITE_TILED_BC_DW_6_Y(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_6_y_mask) << SDMA_PKT_WRITE_TILED_BC_DW_6_y_shift) + +/*define for DW_7 word*/ +/*define for z field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_offset 7 +#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask 0x000007FF +#define SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DW_7_Z(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_z_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_z_shift) + +/*define for sw field*/ +#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_offset 7 +#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask 0x00000003 +#define SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift 24 +#define SDMA_PKT_WRITE_TILED_BC_DW_7_SW(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DW_7_sw_mask) << SDMA_PKT_WRITE_TILED_BC_DW_7_sw_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_offset 8 +#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask 0x000FFFFF +#define SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift 2 +#define SDMA_PKT_WRITE_TILED_BC_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_TILED_BC_COUNT_count_mask) << SDMA_PKT_WRITE_TILED_BC_COUNT_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_offset 9 +#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift 0 +#define SDMA_PKT_WRITE_TILED_BC_DATA0_DATA0(x) (((x) & SDMA_PKT_WRITE_TILED_BC_DATA0_data0_mask) << SDMA_PKT_WRITE_TILED_BC_DATA0_data0_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_COPY packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_COPY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_sub_op_shift) + +/*define for mtype field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_mtype_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_mtype_mask 0x00000003 +#define SDMA_PKT_PTEPDE_COPY_HEADER_mtype_shift 16 +#define SDMA_PKT_PTEPDE_COPY_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_mtype_shift) + +/*define for snoop field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_snoop_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_snoop_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_HEADER_snoop_shift 22 +#define SDMA_PKT_PTEPDE_COPY_HEADER_SNOOP(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_snoop_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_snoop_shift) + +/*define for scope field*/ +#define SDMA_PKT_PTEPDE_COPY_HEADER_scope_offset 0 +#define SDMA_PKT_PTEPDE_COPY_HEADER_scope_mask 0x00000003 +#define SDMA_PKT_PTEPDE_COPY_HEADER_scope_shift 24 +#define SDMA_PKT_PTEPDE_COPY_HEADER_SCOPE(x) (((x) & SDMA_PKT_PTEPDE_COPY_HEADER_scope_mask) << SDMA_PKT_PTEPDE_COPY_HEADER_scope_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_offset 5 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_offset 6 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_PTEPDE_COPY_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_mask) << SDMA_PKT_PTEPDE_COPY_MASK_DW1_mask_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_offset 7 +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_PTEPDE_COPY_COUNT_count_shift 0 +#define SDMA_PKT_PTEPDE_COPY_COUNT_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_count_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_count_shift) + +/*define for dst_cache_policy field*/ +#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_offset 7 +#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask 0x00000007 +#define SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift 22 +#define SDMA_PKT_PTEPDE_COPY_COUNT_DST_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_dst_cache_policy_shift) + +/*define for src_cache_policy field*/ +#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_offset 7 +#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask 0x00000007 +#define SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift 29 +#define SDMA_PKT_PTEPDE_COPY_COUNT_SRC_CACHE_POLICY(x) (((x) & SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_mask) << SDMA_PKT_PTEPDE_COPY_COUNT_src_cache_policy_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_COPY_BACKWARDS packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_sub_op_shift) + +/*define for pte_size field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask 0x00000003 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift 28 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTE_SIZE(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_pte_size_shift) + +/*define for direction field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift 30 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_DIRECTION(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_direction_shift) + +/*define for ptepde_op field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_offset 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask 0x00000001 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift 31 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_PTEPDE_OP(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_HEADER_ptepde_op_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_BIT_FOR_DW word*/ +/*define for mask_first_xfer field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_offset 5 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_FIRST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_first_xfer_shift) + +/*define for mask_last_xfer field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_offset 5 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask 0x000000FF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift 8 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_MASK_LAST_XFER(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_MASK_BIT_FOR_DW_mask_last_xfer_shift) + +/*define for COUNT_IN_32B_XFER word*/ +/*define for count field*/ +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_offset 6 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask 0x0001FFFF +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift 0 +#define SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_COUNT(x) (((x) & SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_mask) << SDMA_PKT_PTEPDE_COPY_BACKWARDS_COUNT_IN_32B_XFER_count_shift) + + +/* +** Definitions for SDMA_PKT_PTEPDE_RMW packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_RMW_HEADER_op_shift 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift 8 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sub_op_shift) + +/*define for mtype field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask 0x00000007 +#define SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift 16 +#define SDMA_PKT_PTEPDE_RMW_HEADER_MTYPE(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_mtype_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_mtype_shift) + +/*define for gcc field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift 19 +#define SDMA_PKT_PTEPDE_RMW_HEADER_GCC(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gcc_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gcc_shift) + +/*define for sys field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift 20 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SYS(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_sys_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_sys_shift) + +/*define for snp field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift 22 +#define SDMA_PKT_PTEPDE_RMW_HEADER_SNP(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_snp_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_snp_shift) + +/*define for gpa field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift 23 +#define SDMA_PKT_PTEPDE_RMW_HEADER_GPA(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_gpa_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_gpa_shift) + +/*define for l2_policy field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask 0x00000003 +#define SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift 24 +#define SDMA_PKT_PTEPDE_RMW_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_l2_policy_shift) + +/*define for llc_policy field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift 26 +#define SDMA_PKT_PTEPDE_RMW_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_llc_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_offset 0 +#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift 28 +#define SDMA_PKT_PTEPDE_RMW_HEADER_CPV(x) (((x) & SDMA_PKT_PTEPDE_RMW_HEADER_cpv_mask) << SDMA_PKT_PTEPDE_RMW_HEADER_cpv_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_mask) << SDMA_PKT_PTEPDE_RMW_ADDR_HI_addr_63_32_shift) + +/*define for MASK_LO word*/ +/*define for mask_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_offset 3 +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_MASK_LO_MASK_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_mask) << SDMA_PKT_PTEPDE_RMW_MASK_LO_mask_31_0_shift) + +/*define for MASK_HI word*/ +/*define for mask_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_offset 4 +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_MASK_HI_MASK_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_mask) << SDMA_PKT_PTEPDE_RMW_MASK_HI_mask_63_32_shift) + +/*define for VALUE_LO word*/ +/*define for value_31_0 field*/ +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_offset 5 +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift 0 +#define SDMA_PKT_PTEPDE_RMW_VALUE_LO_VALUE_31_0(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_LO_value_31_0_shift) + +/*define for VALUE_HI word*/ +/*define for value_63_32 field*/ +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_offset 6 +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift 0 +#define SDMA_PKT_PTEPDE_RMW_VALUE_HI_VALUE_63_32(x) (((x) & SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_mask) << SDMA_PKT_PTEPDE_RMW_VALUE_HI_value_63_32_shift) + +/*define for COUNT word*/ +/*define for num_of_pte field*/ +#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_offset 7 +#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask 0xFFFFFFFF +#define SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift 0 +#define SDMA_PKT_PTEPDE_RMW_COUNT_NUM_OF_PTE(x) (((x) & SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_mask) << SDMA_PKT_PTEPDE_RMW_COUNT_num_of_pte_shift) + + +/* +** Definitions for SDMA_PKT_REGISTER_RMW packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_REGISTER_RMW_HEADER_op_offset 0 +#define SDMA_PKT_REGISTER_RMW_HEADER_op_mask 0x000000FF +#define SDMA_PKT_REGISTER_RMW_HEADER_op_shift 0 +#define SDMA_PKT_REGISTER_RMW_HEADER_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_offset 0 +#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift 8 +#define SDMA_PKT_REGISTER_RMW_HEADER_SUB_OP(x) (((x) & SDMA_PKT_REGISTER_RMW_HEADER_sub_op_mask) << SDMA_PKT_REGISTER_RMW_HEADER_sub_op_shift) + +/*define for ADDR word*/ +/*define for addr field*/ +#define SDMA_PKT_REGISTER_RMW_ADDR_addr_offset 1 +#define SDMA_PKT_REGISTER_RMW_ADDR_addr_mask 0x000FFFFF +#define SDMA_PKT_REGISTER_RMW_ADDR_addr_shift 0 +#define SDMA_PKT_REGISTER_RMW_ADDR_ADDR(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_addr_mask) << SDMA_PKT_REGISTER_RMW_ADDR_addr_shift) + +/*define for aperture_id field*/ +#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_offset 1 +#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask 0x00000FFF +#define SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift 20 +#define SDMA_PKT_REGISTER_RMW_ADDR_APERTURE_ID(x) (((x) & SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_mask) << SDMA_PKT_REGISTER_RMW_ADDR_aperture_id_shift) + +/*define for MASK word*/ +/*define for mask field*/ +#define SDMA_PKT_REGISTER_RMW_MASK_mask_offset 2 +#define SDMA_PKT_REGISTER_RMW_MASK_mask_mask 0xFFFFFFFF +#define SDMA_PKT_REGISTER_RMW_MASK_mask_shift 0 +#define SDMA_PKT_REGISTER_RMW_MASK_MASK(x) (((x) & SDMA_PKT_REGISTER_RMW_MASK_mask_mask) << SDMA_PKT_REGISTER_RMW_MASK_mask_shift) + +/*define for VALUE word*/ +/*define for value field*/ +#define SDMA_PKT_REGISTER_RMW_VALUE_value_offset 3 +#define SDMA_PKT_REGISTER_RMW_VALUE_value_mask 0xFFFFFFFF +#define SDMA_PKT_REGISTER_RMW_VALUE_value_shift 0 +#define SDMA_PKT_REGISTER_RMW_VALUE_VALUE(x) (((x) & SDMA_PKT_REGISTER_RMW_VALUE_value_mask) << SDMA_PKT_REGISTER_RMW_VALUE_value_shift) + +/*define for MISC word*/ +/*define for stride field*/ +#define SDMA_PKT_REGISTER_RMW_MISC_stride_offset 4 +#define SDMA_PKT_REGISTER_RMW_MISC_stride_mask 0x000FFFFF +#define SDMA_PKT_REGISTER_RMW_MISC_stride_shift 0 +#define SDMA_PKT_REGISTER_RMW_MISC_STRIDE(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_stride_mask) << SDMA_PKT_REGISTER_RMW_MISC_stride_shift) + +/*define for num_of_reg field*/ +#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_offset 4 +#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask 0x00000FFF +#define SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift 20 +#define SDMA_PKT_REGISTER_RMW_MISC_NUM_OF_REG(x) (((x) & SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_mask) << SDMA_PKT_REGISTER_RMW_MISC_num_of_reg_shift) + + +/* +** Definitions for SDMA_PKT_WRITE_INCR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_op_shift 0 +#define SDMA_PKT_WRITE_INCR_HEADER_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift 8 +#define SDMA_PKT_WRITE_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_sub_op_mask) << SDMA_PKT_WRITE_INCR_HEADER_sub_op_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift 24 +#define SDMA_PKT_WRITE_INCR_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cache_policy_mask) << SDMA_PKT_WRITE_INCR_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_WRITE_INCR_HEADER_cpv_offset 0 +#define SDMA_PKT_WRITE_INCR_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_WRITE_INCR_HEADER_cpv_shift 28 +#define SDMA_PKT_WRITE_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_WRITE_INCR_HEADER_cpv_mask) << SDMA_PKT_WRITE_INCR_HEADER_cpv_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_WRITE_INCR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_WRITE_INCR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for MASK_DW0 word*/ +/*define for mask_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_offset 3 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW0_MASK_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_mask) << SDMA_PKT_WRITE_INCR_MASK_DW0_mask_dw0_shift) + +/*define for MASK_DW1 word*/ +/*define for mask_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_offset 4 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_MASK_DW1_MASK_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_mask) << SDMA_PKT_WRITE_INCR_MASK_DW1_mask_dw1_shift) + +/*define for INIT_DW0 word*/ +/*define for init_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_offset 5 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW0_INIT_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_mask) << SDMA_PKT_WRITE_INCR_INIT_DW0_init_dw0_shift) + +/*define for INIT_DW1 word*/ +/*define for init_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_offset 6 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INIT_DW1_INIT_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_mask) << SDMA_PKT_WRITE_INCR_INIT_DW1_init_dw1_shift) + +/*define for INCR_DW0 word*/ +/*define for incr_dw0 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_offset 7 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW0_INCR_DW0(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_mask) << SDMA_PKT_WRITE_INCR_INCR_DW0_incr_dw0_shift) + +/*define for INCR_DW1 word*/ +/*define for incr_dw1 field*/ +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_offset 8 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask 0xFFFFFFFF +#define SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift 0 +#define SDMA_PKT_WRITE_INCR_INCR_DW1_INCR_DW1(x) (((x) & SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_mask) << SDMA_PKT_WRITE_INCR_INCR_DW1_incr_dw1_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_WRITE_INCR_COUNT_count_offset 9 +#define SDMA_PKT_WRITE_INCR_COUNT_count_mask 0x0007FFFF +#define SDMA_PKT_WRITE_INCR_COUNT_count_shift 0 +#define SDMA_PKT_WRITE_INCR_COUNT_COUNT(x) (((x) & SDMA_PKT_WRITE_INCR_COUNT_count_mask) << SDMA_PKT_WRITE_INCR_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_INDIRECT packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_INDIRECT_HEADER_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_op_shift 0 +#define SDMA_PKT_INDIRECT_HEADER_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_op_mask) << SDMA_PKT_INDIRECT_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_INDIRECT_HEADER_sub_op_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_INDIRECT_HEADER_sub_op_shift 8 +#define SDMA_PKT_INDIRECT_HEADER_SUB_OP(x) (((x) & SDMA_PKT_INDIRECT_HEADER_sub_op_mask) << SDMA_PKT_INDIRECT_HEADER_sub_op_shift) + +/*define for vmid field*/ +#define SDMA_PKT_INDIRECT_HEADER_vmid_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_vmid_mask 0x0000000F +#define SDMA_PKT_INDIRECT_HEADER_vmid_shift 16 +#define SDMA_PKT_INDIRECT_HEADER_VMID(x) (((x) & SDMA_PKT_INDIRECT_HEADER_vmid_mask) << SDMA_PKT_INDIRECT_HEADER_vmid_shift) + +/*define for priv field*/ +#define SDMA_PKT_INDIRECT_HEADER_priv_offset 0 +#define SDMA_PKT_INDIRECT_HEADER_priv_mask 0x00000001 +#define SDMA_PKT_INDIRECT_HEADER_priv_shift 31 +#define SDMA_PKT_INDIRECT_HEADER_PRIV(x) (((x) & SDMA_PKT_INDIRECT_HEADER_priv_mask) << SDMA_PKT_INDIRECT_HEADER_priv_shift) + +/*define for BASE_LO word*/ +/*define for ib_base_31_0 field*/ +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_offset 1 +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift 0 +#define SDMA_PKT_INDIRECT_BASE_LO_IB_BASE_31_0(x) (((x) & SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_mask) << SDMA_PKT_INDIRECT_BASE_LO_ib_base_31_0_shift) + +/*define for BASE_HI word*/ +/*define for ib_base_63_32 field*/ +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_offset 2 +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift 0 +#define SDMA_PKT_INDIRECT_BASE_HI_IB_BASE_63_32(x) (((x) & SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_mask) << SDMA_PKT_INDIRECT_BASE_HI_ib_base_63_32_shift) + +/*define for IB_SIZE word*/ +/*define for ib_size field*/ +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_offset 3 +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask 0x000FFFFF +#define SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift 0 +#define SDMA_PKT_INDIRECT_IB_SIZE_IB_SIZE(x) (((x) & SDMA_PKT_INDIRECT_IB_SIZE_ib_size_mask) << SDMA_PKT_INDIRECT_IB_SIZE_ib_size_shift) + +/*define for CSA_ADDR_LO word*/ +/*define for csa_addr_31_0 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_offset 4 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_LO_CSA_ADDR_31_0(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_LO_csa_addr_31_0_shift) + +/*define for CSA_ADDR_HI word*/ +/*define for csa_addr_63_32 field*/ +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_offset 5 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift 0 +#define SDMA_PKT_INDIRECT_CSA_ADDR_HI_CSA_ADDR_63_32(x) (((x) & SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_mask) << SDMA_PKT_INDIRECT_CSA_ADDR_HI_csa_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_SEMAPHORE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_op_shift 0 +#define SDMA_PKT_SEMAPHORE_HEADER_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SEMAPHORE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_sub_op_mask) << SDMA_PKT_SEMAPHORE_HEADER_sub_op_shift) + +/*define for write_one field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_write_one_shift 29 +#define SDMA_PKT_SEMAPHORE_HEADER_WRITE_ONE(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_write_one_mask) << SDMA_PKT_SEMAPHORE_HEADER_write_one_shift) + +/*define for signal field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_signal_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_signal_shift 30 +#define SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_signal_mask) << SDMA_PKT_SEMAPHORE_HEADER_signal_shift) + +/*define for mailbox field*/ +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_offset 0 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask 0x00000001 +#define SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift 31 +#define SDMA_PKT_SEMAPHORE_HEADER_MAILBOX(x) (((x) & SDMA_PKT_SEMAPHORE_HEADER_mailbox_mask) << SDMA_PKT_SEMAPHORE_HEADER_mailbox_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_SEMAPHORE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_SEMAPHORE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_SEMAPHORE_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_MEM_INCR packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_MEM_INCR_HEADER_op_offset 0 +#define SDMA_PKT_MEM_INCR_HEADER_op_mask 0x000000FF +#define SDMA_PKT_MEM_INCR_HEADER_op_shift 0 +#define SDMA_PKT_MEM_INCR_HEADER_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_op_mask) << SDMA_PKT_MEM_INCR_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_MEM_INCR_HEADER_sub_op_offset 0 +#define SDMA_PKT_MEM_INCR_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_MEM_INCR_HEADER_sub_op_shift 8 +#define SDMA_PKT_MEM_INCR_HEADER_SUB_OP(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_sub_op_mask) << SDMA_PKT_MEM_INCR_HEADER_sub_op_shift) + +/*define for l2_policy field*/ +#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_offset 0 +#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask 0x00000003 +#define SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift 24 +#define SDMA_PKT_MEM_INCR_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_l2_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_l2_policy_shift) + +/*define for llc_policy field*/ +#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_offset 0 +#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask 0x00000001 +#define SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift 26 +#define SDMA_PKT_MEM_INCR_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_llc_policy_mask) << SDMA_PKT_MEM_INCR_HEADER_llc_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_MEM_INCR_HEADER_cpv_offset 0 +#define SDMA_PKT_MEM_INCR_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_MEM_INCR_HEADER_cpv_shift 28 +#define SDMA_PKT_MEM_INCR_HEADER_CPV(x) (((x) & SDMA_PKT_MEM_INCR_HEADER_cpv_mask) << SDMA_PKT_MEM_INCR_HEADER_cpv_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_MEM_INCR_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_mask) << SDMA_PKT_MEM_INCR_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_MEM_INCR_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_mask) << SDMA_PKT_MEM_INCR_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_VM_INVALIDATION packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF +#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8 +#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) + +/*define for gfx_eng_id field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask 0x0000001F +#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift 16 +#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) + +/*define for mm_eng_id field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask 0x0000001F +#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift 24 +#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) + +/*define for INVALIDATEREQ word*/ +/*define for invalidatereq field*/ +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1 +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0 +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) + +/*define for ADDRESSRANGELO word*/ +/*define for addressrangelo field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) + +/*define for ADDRESSRANGEHI word*/ +/*define for invalidateack field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) + +/*define for addressrangehi field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) + +/*define for reserved field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) + + +/* +** Definitions for SDMA_PKT_FENCE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_FENCE_HEADER_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_op_shift 0 +#define SDMA_PKT_FENCE_HEADER_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_op_mask) << SDMA_PKT_FENCE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_FENCE_HEADER_sub_op_offset 0 +#define SDMA_PKT_FENCE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_FENCE_HEADER_sub_op_shift 8 +#define SDMA_PKT_FENCE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_FENCE_HEADER_sub_op_mask) << SDMA_PKT_FENCE_HEADER_sub_op_shift) + +/*define for mtype field*/ +#define SDMA_PKT_FENCE_HEADER_mtype_offset 0 +#define SDMA_PKT_FENCE_HEADER_mtype_mask 0x00000007 +#define SDMA_PKT_FENCE_HEADER_mtype_shift 16 +#define SDMA_PKT_FENCE_HEADER_MTYPE(x) (((x) & SDMA_PKT_FENCE_HEADER_mtype_mask) << SDMA_PKT_FENCE_HEADER_mtype_shift) + +/*define for gcc field*/ +#define SDMA_PKT_FENCE_HEADER_gcc_offset 0 +#define SDMA_PKT_FENCE_HEADER_gcc_mask 0x00000001 +#define SDMA_PKT_FENCE_HEADER_gcc_shift 19 +#define SDMA_PKT_FENCE_HEADER_GCC(x) (((x) & SDMA_PKT_FENCE_HEADER_gcc_mask) << SDMA_PKT_FENCE_HEADER_gcc_shift) + +/*define for sys field*/ +#define SDMA_PKT_FENCE_HEADER_sys_offset 0 +#define SDMA_PKT_FENCE_HEADER_sys_mask 0x00000001 +#define SDMA_PKT_FENCE_HEADER_sys_shift 20 +#define SDMA_PKT_FENCE_HEADER_SYS(x) (((x) & SDMA_PKT_FENCE_HEADER_sys_mask) << SDMA_PKT_FENCE_HEADER_sys_shift) + +/*define for snp field*/ +#define SDMA_PKT_FENCE_HEADER_snp_offset 0 +#define SDMA_PKT_FENCE_HEADER_snp_mask 0x00000001 +#define SDMA_PKT_FENCE_HEADER_snp_shift 22 +#define SDMA_PKT_FENCE_HEADER_SNP(x) (((x) & SDMA_PKT_FENCE_HEADER_snp_mask) << SDMA_PKT_FENCE_HEADER_snp_shift) + +/*define for gpa field*/ +#define SDMA_PKT_FENCE_HEADER_gpa_offset 0 +#define SDMA_PKT_FENCE_HEADER_gpa_mask 0x00000001 +#define SDMA_PKT_FENCE_HEADER_gpa_shift 23 +#define SDMA_PKT_FENCE_HEADER_GPA(x) (((x) & SDMA_PKT_FENCE_HEADER_gpa_mask) << SDMA_PKT_FENCE_HEADER_gpa_shift) + +/*define for l2_policy field*/ +#define SDMA_PKT_FENCE_HEADER_l2_policy_offset 0 +#define SDMA_PKT_FENCE_HEADER_l2_policy_mask 0x00000003 +#define SDMA_PKT_FENCE_HEADER_l2_policy_shift 24 +#define SDMA_PKT_FENCE_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_l2_policy_mask) << SDMA_PKT_FENCE_HEADER_l2_policy_shift) + +/*define for llc_policy field*/ +#define SDMA_PKT_FENCE_HEADER_llc_policy_offset 0 +#define SDMA_PKT_FENCE_HEADER_llc_policy_mask 0x00000001 +#define SDMA_PKT_FENCE_HEADER_llc_policy_shift 26 +#define SDMA_PKT_FENCE_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_FENCE_HEADER_llc_policy_mask) << SDMA_PKT_FENCE_HEADER_llc_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_FENCE_HEADER_cpv_offset 0 +#define SDMA_PKT_FENCE_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_FENCE_HEADER_cpv_shift 28 +#define SDMA_PKT_FENCE_HEADER_CPV(x) (((x) & SDMA_PKT_FENCE_HEADER_cpv_mask) << SDMA_PKT_FENCE_HEADER_cpv_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_FENCE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_FENCE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_FENCE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_FENCE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_FENCE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_FENCE_ADDR_HI_addr_63_32_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_FENCE_DATA_data_offset 3 +#define SDMA_PKT_FENCE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_FENCE_DATA_data_shift 0 +#define SDMA_PKT_FENCE_DATA_DATA(x) (((x) & SDMA_PKT_FENCE_DATA_data_mask) << SDMA_PKT_FENCE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_SRBM_WRITE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_op_shift 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift 8 +#define SDMA_PKT_SRBM_WRITE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_sub_op_mask) << SDMA_PKT_SRBM_WRITE_HEADER_sub_op_shift) + +/*define for byte_en field*/ +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_offset 0 +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask 0x0000000F +#define SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift 28 +#define SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(x) (((x) & SDMA_PKT_SRBM_WRITE_HEADER_byte_en_mask) << SDMA_PKT_SRBM_WRITE_HEADER_byte_en_shift) + +/*define for ADDR word*/ +/*define for addr field*/ +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_offset 1 +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_mask 0x0003FFFF +#define SDMA_PKT_SRBM_WRITE_ADDR_addr_shift 0 +#define SDMA_PKT_SRBM_WRITE_ADDR_ADDR(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_addr_mask) << SDMA_PKT_SRBM_WRITE_ADDR_addr_shift) + +/*define for apertureid field*/ +#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_offset 1 +#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask 0x00000FFF +#define SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift 20 +#define SDMA_PKT_SRBM_WRITE_ADDR_APERTUREID(x) (((x) & SDMA_PKT_SRBM_WRITE_ADDR_apertureid_mask) << SDMA_PKT_SRBM_WRITE_ADDR_apertureid_shift) + +/*define for DATA word*/ +/*define for data field*/ +#define SDMA_PKT_SRBM_WRITE_DATA_data_offset 2 +#define SDMA_PKT_SRBM_WRITE_DATA_data_mask 0xFFFFFFFF +#define SDMA_PKT_SRBM_WRITE_DATA_data_shift 0 +#define SDMA_PKT_SRBM_WRITE_DATA_DATA(x) (((x) & SDMA_PKT_SRBM_WRITE_DATA_data_mask) << SDMA_PKT_SRBM_WRITE_DATA_data_shift) + + +/* +** Definitions for SDMA_PKT_PRE_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_op_shift 0 +#define SDMA_PKT_PRE_EXE_HEADER_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_op_mask) << SDMA_PKT_PRE_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_PRE_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_sub_op_mask) << SDMA_PKT_PRE_EXE_HEADER_sub_op_shift) + +/*define for dev_sel field*/ +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_offset 0 +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask 0x000000FF +#define SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift 16 +#define SDMA_PKT_PRE_EXE_HEADER_DEV_SEL(x) (((x) & SDMA_PKT_PRE_EXE_HEADER_dev_sel_mask) << SDMA_PKT_PRE_EXE_HEADER_dev_sel_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_offset 1 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_PRE_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_PRE_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_COND_EXE packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_COND_EXE_HEADER_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_op_shift 0 +#define SDMA_PKT_COND_EXE_HEADER_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_op_mask) << SDMA_PKT_COND_EXE_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_COND_EXE_HEADER_sub_op_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_COND_EXE_HEADER_sub_op_shift 8 +#define SDMA_PKT_COND_EXE_HEADER_SUB_OP(x) (((x) & SDMA_PKT_COND_EXE_HEADER_sub_op_mask) << SDMA_PKT_COND_EXE_HEADER_sub_op_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_COND_EXE_HEADER_cache_policy_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_COND_EXE_HEADER_cache_policy_shift 24 +#define SDMA_PKT_COND_EXE_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cache_policy_mask) << SDMA_PKT_COND_EXE_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_COND_EXE_HEADER_cpv_offset 0 +#define SDMA_PKT_COND_EXE_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_COND_EXE_HEADER_cpv_shift 28 +#define SDMA_PKT_COND_EXE_HEADER_CPV(x) (((x) & SDMA_PKT_COND_EXE_HEADER_cpv_mask) << SDMA_PKT_COND_EXE_HEADER_cpv_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_mask) << SDMA_PKT_COND_EXE_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_COND_EXE_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_mask) << SDMA_PKT_COND_EXE_ADDR_HI_addr_63_32_shift) + +/*define for REFERENCE word*/ +/*define for reference field*/ +#define SDMA_PKT_COND_EXE_REFERENCE_reference_offset 3 +#define SDMA_PKT_COND_EXE_REFERENCE_reference_mask 0xFFFFFFFF +#define SDMA_PKT_COND_EXE_REFERENCE_reference_shift 0 +#define SDMA_PKT_COND_EXE_REFERENCE_REFERENCE(x) (((x) & SDMA_PKT_COND_EXE_REFERENCE_reference_mask) << SDMA_PKT_COND_EXE_REFERENCE_reference_shift) + +/*define for EXEC_COUNT word*/ +/*define for exec_count field*/ +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_offset 4 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask 0x00003FFF +#define SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift 0 +#define SDMA_PKT_COND_EXE_EXEC_COUNT_EXEC_COUNT(x) (((x) & SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_mask) << SDMA_PKT_COND_EXE_EXEC_COUNT_exec_count_shift) + + +/* +** Definitions for SDMA_PKT_CONSTANT_FILL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_op_shift 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift 8 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sub_op_shift) + +/*define for sw field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift 16 +#define SDMA_PKT_CONSTANT_FILL_HEADER_SW(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_sw_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_sw_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift 24 +#define SDMA_PKT_CONSTANT_FILL_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift 28 +#define SDMA_PKT_CONSTANT_FILL_HEADER_CPV(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_cpv_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_cpv_shift) + +/*define for fillsize field*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask 0x00000003 +#define SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift 30 +#define SDMA_PKT_CONSTANT_FILL_HEADER_FILLSIZE(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_fillsize_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_offset 1 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_offset 2 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_CONSTANT_FILL_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for DATA word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_offset 3 +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift 0 +#define SDMA_PKT_CONSTANT_FILL_DATA_SRC_DATA_31_0(x) (((x) & SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_mask) << SDMA_PKT_CONSTANT_FILL_DATA_src_data_31_0_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_offset 4 +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_mask 0x3FFFFFFF +#define SDMA_PKT_CONSTANT_FILL_COUNT_count_shift 0 +#define SDMA_PKT_CONSTANT_FILL_COUNT_COUNT(x) (((x) & SDMA_PKT_CONSTANT_FILL_COUNT_count_mask) << SDMA_PKT_CONSTANT_FILL_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_DATA_FILL_MULTI packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask 0x000000FF +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift 8 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_sub_op_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift 24 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift 28 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_CPV(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_cpv_shift) + +/*define for memlog_clr field*/ +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_offset 0 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask 0x00000001 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift 31 +#define SDMA_PKT_DATA_FILL_MULTI_HEADER_MEMLOG_CLR(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_mask) << SDMA_PKT_DATA_FILL_MULTI_HEADER_memlog_clr_shift) + +/*define for BYTE_STRIDE word*/ +/*define for byte_stride field*/ +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_offset 1 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_BYTE_STRIDE(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_STRIDE_byte_stride_shift) + +/*define for DMA_COUNT word*/ +/*define for dma_count field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_offset 2 +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_DMA_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_mask) << SDMA_PKT_DATA_FILL_MULTI_DMA_COUNT_dma_count_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_offset 3 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_offset 4 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_PKT_DATA_FILL_MULTI_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for BYTE_COUNT word*/ +/*define for count field*/ +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_offset 5 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask 0x03FFFFFF +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift 0 +#define SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_COUNT(x) (((x) & SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_mask) << SDMA_PKT_DATA_FILL_MULTI_BYTE_COUNT_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REGMEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REGMEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REGMEM_HEADER_sub_op_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift 20 +#define SDMA_PKT_POLL_REGMEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift 24 +#define SDMA_PKT_POLL_REGMEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REGMEM_HEADER_cpv_shift) + +/*define for hdp_flush field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift 26 +#define SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_mask) << SDMA_PKT_POLL_REGMEM_HEADER_hdp_flush_shift) + +/*define for func field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_func_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_mask 0x00000007 +#define SDMA_PKT_POLL_REGMEM_HEADER_func_shift 28 +#define SDMA_PKT_POLL_REGMEM_HEADER_FUNC(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_func_mask) << SDMA_PKT_POLL_REGMEM_HEADER_func_shift) + +/*define for mem_poll field*/ +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_offset 0 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask 0x00000001 +#define SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift 31 +#define SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(x) (((x) & SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_mask) << SDMA_PKT_POLL_REGMEM_HEADER_mem_poll_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REGMEM_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REGMEM_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REGMEM_ADDR_HI_addr_63_32_shift) + +/*define for VALUE word*/ +/*define for value field*/ +#define SDMA_PKT_POLL_REGMEM_VALUE_value_offset 3 +#define SDMA_PKT_POLL_REGMEM_VALUE_value_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_VALUE_value_shift 0 +#define SDMA_PKT_POLL_REGMEM_VALUE_VALUE(x) (((x) & SDMA_PKT_POLL_REGMEM_VALUE_value_mask) << SDMA_PKT_POLL_REGMEM_VALUE_value_shift) + +/*define for MASK word*/ +/*define for mask field*/ +#define SDMA_PKT_POLL_REGMEM_MASK_mask_offset 4 +#define SDMA_PKT_POLL_REGMEM_MASK_mask_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REGMEM_MASK_mask_shift 0 +#define SDMA_PKT_POLL_REGMEM_MASK_MASK(x) (((x) & SDMA_PKT_POLL_REGMEM_MASK_mask_mask) << SDMA_PKT_POLL_REGMEM_MASK_mask_shift) + +/*define for DW5 word*/ +/*define for interval field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_interval_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_interval_mask 0x0000FFFF +#define SDMA_PKT_POLL_REGMEM_DW5_interval_shift 0 +#define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDMA_PKT_POLL_REGMEM_DW5_interval_shift) + +/*define for retry_count field*/ +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_offset 5 +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask 0x00000FFF +#define SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift 16 +#define SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_retry_count_mask) << SDMA_PKT_POLL_REGMEM_DW5_retry_count_shift) + + +/* +** Definitions for SDMA_PKT_POLL_REG_WRITE_MEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_sub_op_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift 24 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_offset 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift 28 +#define SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_HEADER_cpv_shift) + +/*define for SRC_ADDR word*/ +/*define for addr_31_2 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_offset 1 +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask 0x3FFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift 2 +#define SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_ADDR_31_2(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_SRC_ADDR_addr_31_2_shift) + +/*define for DST_ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 2 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 3 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_REG_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_POLL_DBIT_WRITE_MEM packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_sub_op_shift) + +/*define for ea field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask 0x00000003 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift 16 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_EA(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_ea_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift 24 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_offset 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift 28 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_HEADER_cpv_shift) + +/*define for DST_ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_LO_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_DST_ADDR_HI_addr_63_32_shift) + +/*define for START_PAGE word*/ +/*define for addr_31_4 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_offset 3 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask 0x0FFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift 4 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_ADDR_31_4(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_START_PAGE_addr_31_4_shift) + +/*define for PAGE_NUM word*/ +/*define for page_num_31_0 field*/ +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_offset 4 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift 0 +#define SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_PAGE_NUM_31_0(x) (((x) & SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_mask) << SDMA_PKT_POLL_DBIT_WRITE_MEM_PAGE_NUM_page_num_31_0_shift) + + +/* +** Definitions for SDMA_PKT_POLL_MEM_VERIFY packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask 0x000000FF +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift 8 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_SUB_OP(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_sub_op_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift 24 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift 28 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_CPV(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_cpv_shift) + +/*define for mode field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_offset 0 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask 0x00000001 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift 31 +#define SDMA_PKT_POLL_MEM_VERIFY_HEADER_MODE(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_mask) << SDMA_PKT_POLL_MEM_VERIFY_HEADER_mode_shift) + +/*define for PATTERN word*/ +/*define for pattern field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_offset 1 +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_PATTERN_PATTERN(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_mask) << SDMA_PKT_POLL_MEM_VERIFY_PATTERN_pattern_shift) + +/*define for CMP0_ADDR_START_LO word*/ +/*define for cmp0_start_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_offset 2 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_CMP0_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_LO_cmp0_start_31_0_shift) + +/*define for CMP0_ADDR_START_HI word*/ +/*define for cmp0_start_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_offset 3 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_CMP0_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_START_HI_cmp0_start_63_32_shift) + +/*define for CMP0_ADDR_END_LO word*/ +/*define for cmp0_end_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_offset 4 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_CMP0_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_LO_cmp0_end_31_0_shift) + +/*define for CMP0_ADDR_END_HI word*/ +/*define for cmp0_end_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_offset 5 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_CMP0_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP0_ADDR_END_HI_cmp0_end_63_32_shift) + +/*define for CMP1_ADDR_START_LO word*/ +/*define for cmp1_start_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_offset 6 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_CMP1_START_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_LO_cmp1_start_31_0_shift) + +/*define for CMP1_ADDR_START_HI word*/ +/*define for cmp1_start_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_offset 7 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_CMP1_START_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_START_HI_cmp1_start_63_32_shift) + +/*define for CMP1_ADDR_END_LO word*/ +/*define for cmp1_end_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_offset 8 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_CMP1_END_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_LO_cmp1_end_31_0_shift) + +/*define for CMP1_ADDR_END_HI word*/ +/*define for cmp1_end_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_offset 9 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_CMP1_END_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_CMP1_ADDR_END_HI_cmp1_end_63_32_shift) + +/*define for REC_ADDR_LO word*/ +/*define for rec_31_0 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_offset 10 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_REC_31_0(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_LO_rec_31_0_shift) + +/*define for REC_ADDR_HI word*/ +/*define for rec_63_32 field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_offset 11 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_REC_63_32(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_mask) << SDMA_PKT_POLL_MEM_VERIFY_REC_ADDR_HI_rec_63_32_shift) + +/*define for RESERVED word*/ +/*define for reserved field*/ +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_offset 12 +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask 0xFFFFFFFF +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift 0 +#define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) + + +/* +** Definitions for SDMA_PKT_ATOMIC packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_ATOMIC_HEADER_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_op_mask 0x000000FF +#define SDMA_PKT_ATOMIC_HEADER_op_shift 0 +#define SDMA_PKT_ATOMIC_HEADER_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_op_mask) << SDMA_PKT_ATOMIC_HEADER_op_shift) + +/*define for loop field*/ +#define SDMA_PKT_ATOMIC_HEADER_loop_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_loop_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_loop_shift 16 +#define SDMA_PKT_ATOMIC_HEADER_LOOP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_loop_mask) << SDMA_PKT_ATOMIC_HEADER_loop_shift) + +/*define for tmz field*/ +#define SDMA_PKT_ATOMIC_HEADER_tmz_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_tmz_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_tmz_shift 18 +#define SDMA_PKT_ATOMIC_HEADER_TMZ(x) (((x) & SDMA_PKT_ATOMIC_HEADER_tmz_mask) << SDMA_PKT_ATOMIC_HEADER_tmz_shift) + +/*define for cache_policy field*/ +#define SDMA_PKT_ATOMIC_HEADER_cache_policy_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_cache_policy_mask 0x00000007 +#define SDMA_PKT_ATOMIC_HEADER_cache_policy_shift 20 +#define SDMA_PKT_ATOMIC_HEADER_CACHE_POLICY(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cache_policy_mask) << SDMA_PKT_ATOMIC_HEADER_cache_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_ATOMIC_HEADER_cpv_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_ATOMIC_HEADER_cpv_shift 24 +#define SDMA_PKT_ATOMIC_HEADER_CPV(x) (((x) & SDMA_PKT_ATOMIC_HEADER_cpv_mask) << SDMA_PKT_ATOMIC_HEADER_cpv_shift) + +/*define for atomic_op field*/ +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_offset 0 +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_mask 0x0000007F +#define SDMA_PKT_ATOMIC_HEADER_atomic_op_shift 25 +#define SDMA_PKT_ATOMIC_HEADER_ATOMIC_OP(x) (((x) & SDMA_PKT_ATOMIC_HEADER_atomic_op_mask) << SDMA_PKT_ATOMIC_HEADER_atomic_op_shift) + +/*define for ADDR_LO word*/ +/*define for addr_31_0 field*/ +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_offset 1 +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_LO_ADDR_31_0(x) (((x) & SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_mask) << SDMA_PKT_ATOMIC_ADDR_LO_addr_31_0_shift) + +/*define for ADDR_HI word*/ +/*define for addr_63_32 field*/ +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_offset 2 +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift 0 +#define SDMA_PKT_ATOMIC_ADDR_HI_ADDR_63_32(x) (((x) & SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_mask) << SDMA_PKT_ATOMIC_ADDR_HI_addr_63_32_shift) + +/*define for SRC_DATA_LO word*/ +/*define for src_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_offset 3 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_LO_SRC_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_mask) << SDMA_PKT_ATOMIC_SRC_DATA_LO_src_data_31_0_shift) + +/*define for SRC_DATA_HI word*/ +/*define for src_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_offset 4 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_SRC_DATA_HI_SRC_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_mask) << SDMA_PKT_ATOMIC_SRC_DATA_HI_src_data_63_32_shift) + +/*define for CMP_DATA_LO word*/ +/*define for cmp_data_31_0 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_offset 5 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_LO_CMP_DATA_31_0(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_mask) << SDMA_PKT_ATOMIC_CMP_DATA_LO_cmp_data_31_0_shift) + +/*define for CMP_DATA_HI word*/ +/*define for cmp_data_63_32 field*/ +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_offset 6 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift 0 +#define SDMA_PKT_ATOMIC_CMP_DATA_HI_CMP_DATA_63_32(x) (((x) & SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_mask) << SDMA_PKT_ATOMIC_CMP_DATA_HI_cmp_data_63_32_shift) + +/*define for LOOP_INTERVAL word*/ +/*define for loop_interval field*/ +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_offset 7 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask 0x00001FFF +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift 0 +#define SDMA_PKT_ATOMIC_LOOP_INTERVAL_LOOP_INTERVAL(x) (((x) & SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_mask) << SDMA_PKT_ATOMIC_LOOP_INTERVAL_loop_interval_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_SET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_SET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_SET_HEADER_sub_op_shift) + +/*define for INIT_DATA_LO word*/ +/*define for init_data_31_0 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_offset 1 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_INIT_DATA_31_0(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_LO_init_data_31_0_shift) + +/*define for INIT_DATA_HI word*/ +/*define for init_data_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_INIT_DATA_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_mask) << SDMA_PKT_TIMESTAMP_SET_INIT_DATA_HI_init_data_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_sub_op_shift) + +/*define for l2_policy field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask 0x00000003 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift 24 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_l2_policy_shift) + +/*define for llc_policy field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask 0x00000001 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift 26 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_llc_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift 28 +#define SDMA_PKT_TIMESTAMP_GET_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_HEADER_cpv_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TIMESTAMP_GET_GLOBAL packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift 8 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_sub_op_shift) + +/*define for l2_policy field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask 0x00000003 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift 24 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_L2_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_l2_policy_shift) + +/*define for llc_policy field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask 0x00000001 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift 26 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_LLC_POLICY(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_llc_policy_shift) + +/*define for cpv field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_offset 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask 0x00000001 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift 28 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_CPV(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_HEADER_cpv_shift) + +/*define for WRITE_ADDR_LO word*/ +/*define for write_addr_31_3 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_offset 1 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask 0x1FFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift 3 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_WRITE_ADDR_31_3(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_LO_write_addr_31_3_shift) + +/*define for WRITE_ADDR_HI word*/ +/*define for write_addr_63_32 field*/ +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_offset 2 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask 0xFFFFFFFF +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift 0 +#define SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_WRITE_ADDR_63_32(x) (((x) & SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_mask) << SDMA_PKT_TIMESTAMP_GET_GLOBAL_WRITE_ADDR_HI_write_addr_63_32_shift) + + +/* +** Definitions for SDMA_PKT_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_op_mask) << SDMA_PKT_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_TRAP_HEADER_sub_op_mask) << SDMA_PKT_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_DUMMY_TRAP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_offset 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_DUMMY_TRAP_HEADER_op_shift 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_offset 0 +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift 8 +#define SDMA_PKT_DUMMY_TRAP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_mask) << SDMA_PKT_DUMMY_TRAP_HEADER_sub_op_shift) + +/*define for INT_CONTEXT word*/ +/*define for int_context field*/ +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_offset 1 +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask 0x0FFFFFFF +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift 0 +#define SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_INT_CONTEXT(x) (((x) & SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_mask) << SDMA_PKT_DUMMY_TRAP_INT_CONTEXT_int_context_shift) + + +/* +** Definitions for SDMA_PKT_GPUVM_INV packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_GPUVM_INV_HEADER_op_offset 0 +#define SDMA_PKT_GPUVM_INV_HEADER_op_mask 0x000000FF +#define SDMA_PKT_GPUVM_INV_HEADER_op_shift 0 +#define SDMA_PKT_GPUVM_INV_HEADER_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_offset 0 +#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift 8 +#define SDMA_PKT_GPUVM_INV_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GPUVM_INV_HEADER_sub_op_mask) << SDMA_PKT_GPUVM_INV_HEADER_sub_op_shift) + +/*define for PAYLOAD1 word*/ +/*define for per_vmid_inv_req field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask 0x0000FFFF +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift 0 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_PER_VMID_INV_REQ(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_per_vmid_inv_req_shift) + +/*define for flush_type field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask 0x00000007 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift 16 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FLUSH_TYPE(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_flush_type_shift) + +/*define for l2_ptes field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift 19 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_ptes_shift) + +/*define for l2_pde0 field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift 20 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE0(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde0_shift) + +/*define for l2_pde1 field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift 21 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE1(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde1_shift) + +/*define for l2_pde2 field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift 22 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L2_PDE2(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l2_pde2_shift) + +/*define for l1_ptes field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift 23 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_L1_PTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_l1_ptes_shift) + +/*define for clr_protection_fault_status_addr field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift 24 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_CLR_PROTECTION_FAULT_STATUS_ADDR(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_clr_protection_fault_status_addr_shift) + +/*define for log_request field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift 25 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_LOG_REQUEST(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_log_request_shift) + +/*define for four_kilobytes field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_offset 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift 26 +#define SDMA_PKT_GPUVM_INV_PAYLOAD1_FOUR_KILOBYTES(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD1_four_kilobytes_shift) + +/*define for PAYLOAD2 word*/ +/*define for s field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_offset 2 +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask 0x00000001 +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift 0 +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_S(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_s_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_s_shift) + +/*define for page_va_42_12 field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_offset 2 +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask 0x7FFFFFFF +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift 1 +#define SDMA_PKT_GPUVM_INV_PAYLOAD2_PAGE_VA_42_12(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD2_page_va_42_12_shift) + +/*define for PAYLOAD3 word*/ +/*define for page_va_47_43 field*/ +#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_offset 3 +#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask 0x0000003F +#define SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift 0 +#define SDMA_PKT_GPUVM_INV_PAYLOAD3_PAGE_VA_47_43(x) (((x) & SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_mask) << SDMA_PKT_GPUVM_INV_PAYLOAD3_page_va_47_43_shift) + + +/* +** Definitions for SDMA_PKT_GCR_REQ packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_GCR_REQ_HEADER_op_offset 0 +#define SDMA_PKT_GCR_REQ_HEADER_op_mask 0x000000FF +#define SDMA_PKT_GCR_REQ_HEADER_op_shift 0 +#define SDMA_PKT_GCR_REQ_HEADER_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_op_mask) << SDMA_PKT_GCR_REQ_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_GCR_REQ_HEADER_sub_op_offset 0 +#define SDMA_PKT_GCR_REQ_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_GCR_REQ_HEADER_sub_op_shift 8 +#define SDMA_PKT_GCR_REQ_HEADER_SUB_OP(x) (((x) & SDMA_PKT_GCR_REQ_HEADER_sub_op_mask) << SDMA_PKT_GCR_REQ_HEADER_sub_op_shift) + +/*define for PAYLOAD1 word*/ +/*define for base_va_31_7 field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_offset 1 +#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask 0x01FFFFFF +#define SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift 7 +#define SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD1_base_va_31_7_shift) + +/*define for PAYLOAD2 word*/ +/*define for base_va_56_32 field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_56_32_offset 2 +#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_56_32_mask 0x00FFFFFF +#define SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_56_32_shift 0 +#define SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_56_32(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_56_32_mask) << SDMA_PKT_GCR_REQ_PAYLOAD2_base_va_56_32_shift) + +/*define for PAYLOAD3 word*/ +/*define for gcr_control_18_0 field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_0_offset 3 +#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_0_mask 0x0007FFFF +#define SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_0_shift 0 +#define SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_0(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_0_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_gcr_control_18_0_shift) + +/*define for limit_va_15_7 field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_15_7_offset 3 +#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_15_7_mask 0x000001FF +#define SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_15_7_shift 23 +#define SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_15_7(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_15_7_mask) << SDMA_PKT_GCR_REQ_PAYLOAD3_limit_va_15_7_shift) + +/*define for PAYLOAD4 word*/ +/*define for limit_va_47_16 field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_16_offset 4 +#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_16_mask 0xFFFFFFFF +#define SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_16_shift 0 +#define SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_16(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_16_mask) << SDMA_PKT_GCR_REQ_PAYLOAD4_limit_va_47_16_shift) + +/*define for PAYLOAD5 word*/ +/*define for limit_va_56_48 field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD5_limit_va_56_48_offset 5 +#define SDMA_PKT_GCR_REQ_PAYLOAD5_limit_va_56_48_mask 0x000001FF +#define SDMA_PKT_GCR_REQ_PAYLOAD5_limit_va_56_48_shift 0 +#define SDMA_PKT_GCR_REQ_PAYLOAD5_LIMIT_VA_56_48(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD5_limit_va_56_48_mask) << SDMA_PKT_GCR_REQ_PAYLOAD5_limit_va_56_48_shift) + +/*define for vmid field*/ +#define SDMA_PKT_GCR_REQ_PAYLOAD5_vmid_offset 5 +#define SDMA_PKT_GCR_REQ_PAYLOAD5_vmid_mask 0x0000000F +#define SDMA_PKT_GCR_REQ_PAYLOAD5_vmid_shift 26 +#define SDMA_PKT_GCR_REQ_PAYLOAD5_VMID(x) (((x) & SDMA_PKT_GCR_REQ_PAYLOAD5_vmid_mask) << SDMA_PKT_GCR_REQ_PAYLOAD5_vmid_shift) + + +/* +** Definitions for SDMA_PKT_NOP packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_NOP_HEADER_op_offset 0 +#define SDMA_PKT_NOP_HEADER_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_op_shift 0 +#define SDMA_PKT_NOP_HEADER_OP(x) (((x) & SDMA_PKT_NOP_HEADER_op_mask) << SDMA_PKT_NOP_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_NOP_HEADER_sub_op_offset 0 +#define SDMA_PKT_NOP_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_NOP_HEADER_sub_op_shift 8 +#define SDMA_PKT_NOP_HEADER_SUB_OP(x) (((x) & SDMA_PKT_NOP_HEADER_sub_op_mask) << SDMA_PKT_NOP_HEADER_sub_op_shift) + +/*define for count field*/ +#define SDMA_PKT_NOP_HEADER_count_offset 0 +#define SDMA_PKT_NOP_HEADER_count_mask 0x00003FFF +#define SDMA_PKT_NOP_HEADER_count_shift 16 +#define SDMA_PKT_NOP_HEADER_COUNT(x) (((x) & SDMA_PKT_NOP_HEADER_count_mask) << SDMA_PKT_NOP_HEADER_count_shift) + +/*define for DATA0 word*/ +/*define for data0 field*/ +#define SDMA_PKT_NOP_DATA0_data0_offset 1 +#define SDMA_PKT_NOP_DATA0_data0_mask 0xFFFFFFFF +#define SDMA_PKT_NOP_DATA0_data0_shift 0 +#define SDMA_PKT_NOP_DATA0_DATA0(x) (((x) & SDMA_PKT_NOP_DATA0_data0_mask) << SDMA_PKT_NOP_DATA0_data0_shift) + + +/* +** Definitions for SDMA_AQL_PKT_HEADER packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_format_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_HEADER_HEADER_format_shift 0 +#define SDMA_AQL_PKT_HEADER_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_format_mask) << SDMA_AQL_PKT_HEADER_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_HEADER_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_HEADER_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_barrier_mask) << SDMA_AQL_PKT_HEADER_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_HEADER_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_HEADER_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_HEADER_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_HEADER_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_HEADER_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_reserved_mask) << SDMA_AQL_PKT_HEADER_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_op_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_HEADER_HEADER_op_shift 16 +#define SDMA_AQL_PKT_HEADER_HEADER_OP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_op_mask) << SDMA_AQL_PKT_HEADER_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_HEADER_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_HEADER_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_subop_mask) << SDMA_AQL_PKT_HEADER_HEADER_subop_shift) + +/*define for cpv field*/ +#define SDMA_AQL_PKT_HEADER_HEADER_cpv_offset 0 +#define SDMA_AQL_PKT_HEADER_HEADER_cpv_mask 0x00000001 +#define SDMA_AQL_PKT_HEADER_HEADER_cpv_shift 28 +#define SDMA_AQL_PKT_HEADER_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_HEADER_HEADER_cpv_mask) << SDMA_AQL_PKT_HEADER_HEADER_cpv_shift) + + +/* +** Definitions for SDMA_AQL_PKT_COPY_LINEAR packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift 16 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_subop_shift) + +/*define for cpv field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_offset 0 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask 0x00000001 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift 28 +#define SDMA_AQL_PKT_COPY_LINEAR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_mask) << SDMA_AQL_PKT_COPY_LINEAR_HEADER_cpv_shift) + +/*define for RESERVED_DW1 word*/ +/*define for reserved_dw1 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_offset 1 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW1_reserved_dw1_shift) + +/*define for RETURN_ADDR_LO word*/ +/*define for return_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_offset 2 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_RETURN_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_LO_return_addr_31_0_shift) + +/*define for RETURN_ADDR_HI word*/ +/*define for return_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_offset 3 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_RETURN_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_RETURN_ADDR_HI_return_addr_63_32_shift) + +/*define for COUNT word*/ +/*define for count field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_offset 4 +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask 0x003FFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COUNT_COUNT(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_mask) << SDMA_AQL_PKT_COPY_LINEAR_COUNT_count_shift) + +/*define for PARAMETER word*/ +/*define for dst_sw field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift 16 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_sw_shift) + +/*define for dst_cache_policy field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift 18 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_DST_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_dst_cache_policy_shift) + +/*define for src_sw field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask 0x00000003 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift 24 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_SW(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_sw_shift) + +/*define for src_cache_policy field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_offset 5 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask 0x00000007 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift 26 +#define SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_SRC_CACHE_POLICY(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_mask) << SDMA_AQL_PKT_COPY_LINEAR_PARAMETER_src_cache_policy_shift) + +/*define for SRC_ADDR_LO word*/ +/*define for src_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_offset 6 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_SRC_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_LO_src_addr_31_0_shift) + +/*define for SRC_ADDR_HI word*/ +/*define for src_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_offset 7 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_SRC_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_SRC_ADDR_HI_src_addr_63_32_shift) + +/*define for DST_ADDR_LO word*/ +/*define for dst_addr_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_offset 8 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_DST_ADDR_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_LO_dst_addr_31_0_shift) + +/*define for DST_ADDR_HI word*/ +/*define for dst_addr_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_offset 9 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_DST_ADDR_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_DST_ADDR_HI_dst_addr_63_32_shift) + +/*define for RESERVED_DW10 word*/ +/*define for reserved_dw10 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_offset 10 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_RESERVED_DW10(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW10_reserved_dw10_shift) + +/*define for RESERVED_DW11 word*/ +/*define for reserved_dw11 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_offset 11 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_RESERVED_DW11(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW11_reserved_dw11_shift) + +/*define for RESERVED_DW12 word*/ +/*define for reserved_dw12 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_offset 12 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_RESERVED_DW12(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW12_reserved_dw12_shift) + +/*define for RESERVED_DW13 word*/ +/*define for reserved_dw13 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_offset 13 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_COPY_LINEAR_RESERVED_DW13_reserved_dw13_shift) + +/*define for COMPLETION_SIGNAL_LO word*/ +/*define for completion_signal_31_0 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) + +/*define for COMPLETION_SIGNAL_HI word*/ +/*define for completion_signal_63_32 field*/ +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 +#define SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_COPY_LINEAR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) + + +/* +** Definitions for SDMA_AQL_PKT_BARRIER_OR packet +*/ + +/*define for HEADER word*/ +/*define for format field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask 0x000000FF +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_FORMAT(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_format_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_format_shift) + +/*define for barrier field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask 0x00000001 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift 8 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_BARRIER(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_barrier_shift) + +/*define for acquire_fence_scope field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift 9 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_ACQUIRE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_acquire_fence_scope_shift) + +/*define for release_fence_scope field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask 0x00000003 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift 11 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RELEASE_FENCE_SCOPE(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_release_fence_scope_shift) + +/*define for reserved field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift 13 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_RESERVED(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_reserved_shift) + +/*define for op field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask 0x0000000F +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift 16 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_OP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_op_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_op_shift) + +/*define for subop field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift 20 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_SUBOP(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_subop_shift) + +/*define for cpv field*/ +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_offset 0 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask 0x00000001 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift 28 +#define SDMA_AQL_PKT_BARRIER_OR_HEADER_CPV(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_mask) << SDMA_AQL_PKT_BARRIER_OR_HEADER_cpv_shift) + +/*define for RESERVED_DW1 word*/ +/*define for reserved_dw1 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_offset 1 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_RESERVED_DW1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW1_reserved_dw1_shift) + +/*define for DEPENDENT_ADDR_0_LO word*/ +/*define for dependent_addr_0_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_offset 2 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_DEPENDENT_ADDR_0_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_LO_dependent_addr_0_31_0_shift) + +/*define for DEPENDENT_ADDR_0_HI word*/ +/*define for dependent_addr_0_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_offset 3 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_DEPENDENT_ADDR_0_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_0_HI_dependent_addr_0_63_32_shift) + +/*define for DEPENDENT_ADDR_1_LO word*/ +/*define for dependent_addr_1_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_offset 4 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_DEPENDENT_ADDR_1_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_LO_dependent_addr_1_31_0_shift) + +/*define for DEPENDENT_ADDR_1_HI word*/ +/*define for dependent_addr_1_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_offset 5 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_DEPENDENT_ADDR_1_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_1_HI_dependent_addr_1_63_32_shift) + +/*define for DEPENDENT_ADDR_2_LO word*/ +/*define for dependent_addr_2_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_offset 6 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_DEPENDENT_ADDR_2_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_LO_dependent_addr_2_31_0_shift) + +/*define for DEPENDENT_ADDR_2_HI word*/ +/*define for dependent_addr_2_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_offset 7 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_DEPENDENT_ADDR_2_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_2_HI_dependent_addr_2_63_32_shift) + +/*define for DEPENDENT_ADDR_3_LO word*/ +/*define for dependent_addr_3_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_offset 8 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_DEPENDENT_ADDR_3_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_LO_dependent_addr_3_31_0_shift) + +/*define for DEPENDENT_ADDR_3_HI word*/ +/*define for dependent_addr_3_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_offset 9 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_DEPENDENT_ADDR_3_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_3_HI_dependent_addr_3_63_32_shift) + +/*define for DEPENDENT_ADDR_4_LO word*/ +/*define for dependent_addr_4_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_offset 10 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_DEPENDENT_ADDR_4_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_LO_dependent_addr_4_31_0_shift) + +/*define for DEPENDENT_ADDR_4_HI word*/ +/*define for dependent_addr_4_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_offset 11 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_DEPENDENT_ADDR_4_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_DEPENDENT_ADDR_4_HI_dependent_addr_4_63_32_shift) + +/*define for CACHE_POLICY word*/ +/*define for cache_policy0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy0_shift) + +/*define for cache_policy1 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift 5 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY1(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy1_shift) + +/*define for cache_policy2 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift 10 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY2(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy2_shift) + +/*define for cache_policy3 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift 15 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY3(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy3_shift) + +/*define for cache_policy4 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_offset 12 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask 0x00000007 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift 20 +#define SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_CACHE_POLICY4(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_mask) << SDMA_AQL_PKT_BARRIER_OR_CACHE_POLICY_cache_policy4_shift) + +/*define for RESERVED_DW13 word*/ +/*define for reserved_dw13 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_offset 13 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_RESERVED_DW13(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_mask) << SDMA_AQL_PKT_BARRIER_OR_RESERVED_DW13_reserved_dw13_shift) + +/*define for COMPLETION_SIGNAL_LO word*/ +/*define for completion_signal_31_0 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_offset 14 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_COMPLETION_SIGNAL_31_0(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_LO_completion_signal_31_0_shift) + +/*define for COMPLETION_SIGNAL_HI word*/ +/*define for completion_signal_63_32 field*/ +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_offset 15 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask 0xFFFFFFFF +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0 +#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift) + + +#endif /* __SDMA_V7_1_0_PKT_OPEN_H_ */ diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index f7288372ee613..c26cb3e8bff6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1027,11 +1027,11 @@ static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(AMDGPU_PCIE_INDEX, reg); (void)RREG32(AMDGPU_PCIE_INDEX); r = RREG32(AMDGPU_PCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -1039,12 +1039,12 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(AMDGPU_PCIE_INDEX, reg); (void)RREG32(AMDGPU_PCIE_INDEX); WREG32(AMDGPU_PCIE_DATA, v); (void)RREG32(AMDGPU_PCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) @@ -1052,11 +1052,11 @@ static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); (void)RREG32(PCIE_PORT_INDEX); r = RREG32(PCIE_PORT_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -1064,12 +1064,12 @@ static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); (void)RREG32(PCIE_PORT_INDEX); WREG32(PCIE_PORT_DATA, (v)); (void)RREG32(PCIE_PORT_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) @@ -1077,10 +1077,10 @@ static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); r = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -1088,10 +1088,10 @@ static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, (reg)); WREG32(mmSMC_IND_DATA_0, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) @@ -1099,10 +1099,10 @@ static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); r = RREG32(mmUVD_CTX_DATA); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -1110,10 +1110,10 @@ static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32(mmUVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { @@ -2003,10 +2003,6 @@ static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) return 0; } -static void si_pre_asic_init(struct amdgpu_device *adev) -{ -} - static const struct amdgpu_asic_funcs si_asic_funcs = { .read_disabled_bios = &si_read_disabled_bios, @@ -2028,7 +2024,6 @@ static const struct amdgpu_asic_funcs si_asic_funcs = .need_reset_on_init = &si_need_reset_on_init, .get_pcie_replay_count = &si_get_pcie_replay_count, .supports_baco = &si_asic_supports_baco, - .pre_asic_init = &si_pre_asic_init, .query_video_codecs = &si_query_video_codecs, }; @@ -2042,16 +2037,14 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - adev->smc_rreg = &si_smc_rreg; - adev->smc_wreg = &si_smc_wreg; - adev->pcie_rreg = &si_pcie_rreg; - adev->pcie_wreg = &si_pcie_wreg; - adev->pciep_rreg = &si_pciep_rreg; - adev->pciep_wreg = &si_pciep_wreg; - adev->uvd_ctx_rreg = si_uvd_ctx_rreg; - adev->uvd_ctx_wreg = si_uvd_ctx_wreg; - adev->didt_rreg = NULL; - adev->didt_wreg = NULL; + adev->reg.smc.rreg = si_smc_rreg; + adev->reg.smc.wreg = si_smc_wreg; + adev->reg.pcie.rreg = &si_pcie_rreg; + adev->reg.pcie.wreg = &si_pcie_wreg; + adev->reg.pcie.port_rreg = &si_pciep_rreg; + adev->reg.pcie.port_wreg = &si_pciep_wreg; + adev->reg.uvd_ctx.rreg = &si_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &si_uvd_ctx_wreg; adev->asic_funcs = &si_asic_funcs; @@ -2260,16 +2253,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { if (current_data_rate == 2) { - DRM_INFO("PCIE gen 3 link speeds already enabled\n"); + drm_info(adev_to_drm(adev), "PCIE gen 3 link speeds already enabled\n"); return; } - DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); + drm_info(adev_to_drm(adev), "enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { if (current_data_rate == 1) { - DRM_INFO("PCIE gen 2 link speeds already enabled\n"); + drm_info(adev_to_drm(adev), "PCIE gen 2 link speeds already enabled\n"); return; } - DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); + drm_info(adev_to_drm(adev), "enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); } if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) @@ -2387,10 +2380,10 @@ static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); r = RREG32(EVERGREEN_PIF_PHY0_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -2398,10 +2391,10 @@ static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) @@ -2409,10 +2402,10 @@ static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); r = RREG32(EVERGREEN_PIF_PHY1_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -2420,10 +2413,10 @@ static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static void si_program_aspm(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 7f18e4875287c..3e58feb2d5e4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -37,7 +37,6 @@ const u32 sdma_offsets[SDMA_MAX_INSTANCE] = static void si_dma_set_ring_funcs(struct amdgpu_device *adev); static void si_dma_set_buffer_funcs(struct amdgpu_device *adev); -static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev); static void si_dma_set_irq_funcs(struct amdgpu_device *adev); /** @@ -473,6 +472,14 @@ static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } +static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { + .copy_pte_num_dw = 5, + .copy_pte = si_dma_vm_copy_pte, + + .write_pte = si_dma_vm_write_pte, + .set_pte_pde = si_dma_vm_set_pte_pde, +}; + static int si_dma_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -481,7 +488,7 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block) si_dma_set_ring_funcs(adev); si_dma_set_buffer_funcs(adev); - si_dma_set_vm_pte_funcs(adev); + amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs); si_dma_set_irq_funcs(adev); return 0; @@ -584,7 +591,7 @@ static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block) static int si_dma_soft_reset(struct amdgpu_ip_block *ip_block) { - DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n"); + drm_info(adev_to_drm(ip_block->adev), "si_dma_soft_reset --- not implemented !!!!!!!\n"); return 0; } @@ -830,26 +837,6 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev) adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } -static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { - .copy_pte_num_dw = 5, - .copy_pte = si_dma_vm_copy_pte, - - .write_pte = si_dma_vm_write_pte, - .set_pte_pde = si_dma_vm_set_pte_pde, -}; - -static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev) -{ - unsigned i; - - adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; - for (i = 0; i < adev->sdma.num_instances; i++) { - adev->vm_manager.vm_pte_scheds[i] = - &adev->sdma.instance[i].ring.sched; - } - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; -} - const struct amdgpu_ip_block_version si_dma_ip_block = { .type = AMD_IP_BLOCK_TYPE_SDMA, diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c index 68aef47254a90..c86acee05d0b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c @@ -196,7 +196,9 @@ static uint32_t smu_v11_0_i2c_poll_tx_status(struct i2c_adapter *control) if (REG_GET_FIELD(reg, CKSVII2C_IC_INTR_STAT, R_TX_ABRT) == 1) { reg_c_tx_abrt_source = RREG32_SOC15(SMUIO, 0, mmCKSVII2C_IC_TX_ABRT_SOURCE); - DRM_INFO("TX was terminated, IC_TX_ABRT_SOURCE val is:%x", reg_c_tx_abrt_source); + drm_info(adev_to_drm(adev), + "TX was terminated, IC_TX_ABRT_SOURCE val is:%x", + reg_c_tx_abrt_source); /* Check for stop due to NACK */ if (REG_GET_FIELD(reg_c_tx_abrt_source, @@ -769,7 +771,7 @@ bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control) uint8_t data[6] = {0xf, 0, 0xde, 0xad, 0xbe, 0xef}; - DRM_INFO("Begin"); + drm_info(adev_to_drm(adev), "Begin"); if (!smu_v11_0_i2c_bus_lock(control)) { DRM_ERROR("Failed to lock the bus!."); @@ -788,7 +790,7 @@ bool smu_v11_0_i2c_test_bus(struct i2c_adapter *control) smu_v11_0_i2c_bus_unlock(control); - DRM_INFO("End"); + drm_info(adev_to_drm(adev), "End"); return true; } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c new file mode 100644 index 0000000000000..eccc76650d82f --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.c @@ -0,0 +1,50 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "smuio_v15_0_0.h" +#include "smuio/smuio_15_0_0_offset.h" +#include "smuio/smuio_15_0_0_sh_mask.h" +#include + +static u64 smuio_v15_0_0_get_gpu_clock_counter(struct amdgpu_device *adev) +{ + u64 clock; + u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; + + preempt_disable(); + clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); + clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + /* the clock counter may be udpated during polling the counters */ + clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); + if (clock_counter_hi_pre != clock_counter_hi_after) + clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + preempt_enable(); + + clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); + + return clock; +} + +const struct amdgpu_smuio_funcs smuio_v15_0_0_funcs = { + .get_gpu_clock_counter = smuio_v15_0_0_get_gpu_clock_counter, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.h b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.h new file mode 100644 index 0000000000000..85e0f08283d93 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_0.h @@ -0,0 +1,30 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMUIO_V15_0_0_H__ +#define __SMUIO_V15_0_0_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_smuio_funcs smuio_v15_0_0_funcs; + +#endif /* __SMUIO_V15_0_0_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c new file mode 100644 index 0000000000000..ef29424c26cce --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.c @@ -0,0 +1,213 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "smuio_v15_0_8.h" +#include "smuio/smuio_15_0_8_offset.h" +#include "smuio/smuio_15_0_8_sh_mask.h" + +#define SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK 0x00000001L +#define SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK 0x00000008L +#define SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK 0x00000001L + +static u32 smuio_v15_0_8_get_rom_index_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(SMUIO, 0, regROM_INDEX); +} + +static u32 smuio_v15_0_8_get_rom_data_offset(struct amdgpu_device *adev) +{ + return SOC15_REG_OFFSET(SMUIO, 0, regROM_DATA); +} + +static void smuio_v15_0_8_update_rom_clock_gating(struct amdgpu_device *adev, bool enable) +{ + return; +} + +static u64 smuio_v15_0_8_get_gpu_clock_counter(struct amdgpu_device *adev) +{ + u64 clock; + u64 clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after; + + preempt_disable(); + clock_counter_hi_pre = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); + clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + /* the clock counter may be udpated during polling the counters */ + clock_counter_hi_after = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER); + if (clock_counter_hi_pre != clock_counter_hi_after) + clock_counter_lo = (u64)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER); + preempt_enable(); + + clock = clock_counter_lo | (clock_counter_hi_after << 32ULL); + + return clock; +} + +static void smuio_v15_0_8_get_clock_gating_state(struct amdgpu_device *adev, u64 *flags) +{ + u32 data; + + /* CGTT_ROM_CLK_CTRL0 is not available for APU */ + if (adev->flags & AMD_IS_APU) + return; + + data = RREG32_SOC15(SMUIO, 0, regCGTT_ROM_CLK_CTRL0); + if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK)) + *flags |= AMD_CG_SUPPORT_ROM_MGCG; +} + +/** + * smuio_v15_0_8_get_die_id - query die id from FCH. + * + * @adev: amdgpu device pointer + * + * Returns die id + */ +static u32 smuio_v15_0_8_get_die_id(struct amdgpu_device *adev) +{ + u32 data, die_id; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + die_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, DIE_ID); + + return die_id; +} + +/** + * smuio_v15_0_8_get_socket_id - query socket id from FCH + * + * @adev: amdgpu device pointer + * + * Returns socket id + */ +static u32 smuio_v15_0_8_get_socket_id(struct amdgpu_device *adev) +{ + u32 data, socket_id; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + socket_id = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, SOCKET_ID); + + return socket_id; +} + +/** + * smuio_v15_0_8_is_host_gpu_xgmi_supported - detect xgmi interface between cpu and gpu/s. + * + * @adev: amdgpu device pointer + * + * Returns true on success or false otherwise. + */ +static bool smuio_v15_0_8_is_host_gpu_xgmi_supported(struct amdgpu_device *adev) +{ + u32 data; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); + /* data[4:0] + * bit 0 == 0 host-gpu interface is PCIE + * bit 0 == 1 host-gpu interface is Alternate Protocal + * for AMD, this is XGMI + */ + data &= SMUIO_MCM_CONFIG__HOST_GPU_XGMI_MASK; + + return data ? true : false; +} + +#if 0 +/* + * smuio_v15_0_8_is_connected_with_ethernet_switch - detect systems connected with ethernet switch + * + * @adev: amdgpu device pointer + * + * Returns true on success or false otherwise. + */ +static bool smuio_v15_0_8_is_connected_with_ethernet_switch(struct amdgpu_device *adev) +{ + u32 data; + + if (!(adev->flags & AMD_IS_APU)) + return false; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, TOPOLOGY_ID); + /* data[4:0] + * bit 3 == 0 systems connected with ethernet switch + */ + data &= SMUIO_MCM_CONFIG__ETHERNET_SWITCH_MASK; + + return data ? false : true; +} +#endif + +static enum amdgpu_pkg_type smuio_v15_0_8_get_pkg_type(struct amdgpu_device *adev) +{ + enum amdgpu_pkg_type pkg_type; + u32 data; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE); + + /* data [3:0] + bit 2 and bit 3 identifies the pkg type */ + switch (data & 0xC) { + case 0x0: + pkg_type = AMDGPU_PKG_TYPE_BB; + break; + case 0x8: + pkg_type = AMDGPU_PKG_TYPE_CEM; + break; + default: + pkg_type = AMDGPU_PKG_TYPE_UNKNOWN; + break; + } + + return pkg_type; +} + +#if 0 +static bool smuio_v15_0_8_is_custom_hbm_supported(struct amdgpu_device *adev) +{ + u32 data; + + data = RREG32_SOC15(SMUIO, 0, regSMUIO_MCM_CONFIG); + data = REG_GET_FIELD(data, SMUIO_MCM_CONFIG, PKG_TYPE); + + /* data [3:0] + * bit 0 identifies custom HBM module */ + data &= SMUIO_MCM_CONFIG__CUSTOM_HBM_MASK; + + return data ? true : false; +} +#endif + +const struct amdgpu_smuio_funcs smuio_v15_0_8_funcs = { + .get_rom_index_offset = smuio_v15_0_8_get_rom_index_offset, + .get_rom_data_offset = smuio_v15_0_8_get_rom_data_offset, + .get_gpu_clock_counter = smuio_v15_0_8_get_gpu_clock_counter, + .get_die_id = smuio_v15_0_8_get_die_id, + .get_socket_id = smuio_v15_0_8_get_socket_id, + .is_host_gpu_xgmi_supported = smuio_v15_0_8_is_host_gpu_xgmi_supported, + .update_rom_clock_gating = smuio_v15_0_8_update_rom_clock_gating, + .get_clock_gating_state = smuio_v15_0_8_get_clock_gating_state, + .get_pkg_type = smuio_v15_0_8_get_pkg_type, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.h b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.h new file mode 100644 index 0000000000000..508547fcce035 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v15_0_8.h @@ -0,0 +1,30 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMUIO_V15_0_8_H__ +#define __SMUIO_V15_0_8_H__ + +#include "soc15_common.h" + +extern const struct amdgpu_smuio_funcs smuio_v15_0_8_funcs; + +#endif /* __SMUIO_V15_0_8_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 42f5d9c0e3af8..b456e4541d9ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -245,10 +245,10 @@ static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(address, ((reg) & 0x1ff)); r = RREG32(data); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -259,10 +259,10 @@ static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX); data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA); - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(address, ((reg) & 0x1ff)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) @@ -273,10 +273,10 @@ static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); r = RREG32(data); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -287,10 +287,10 @@ static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) @@ -298,10 +298,10 @@ static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); return r; } @@ -309,10 +309,10 @@ static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); } static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) @@ -320,10 +320,10 @@ static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->se_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.se_cac.lock, flags); WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA); - spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); return r; } @@ -331,10 +331,10 @@ static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->se_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.se_cac.lock, flags); WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg)); WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.se_cac.lock, flags); } static u32 soc15_get_config_memsize(struct amdgpu_device *adev) @@ -951,9 +951,7 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = .need_reset_on_init = &soc15_need_reset_on_init, .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, .supports_baco = &soc15_supports_baco, - .pre_asic_init = &soc15_pre_asic_init, .query_video_codecs = &soc15_query_video_codecs, - .encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing, .get_reg_state = &aqua_vanjaram_get_reg_state, }; @@ -962,24 +960,22 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; - adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; - adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; - adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; - adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; - adev->didt_rreg = &soc15_didt_rreg; - adev->didt_wreg = &soc15_didt_wreg; - adev->gc_cac_rreg = &soc15_gc_cac_rreg; - adev->gc_cac_wreg = &soc15_gc_cac_wreg; - adev->se_cac_rreg = &soc15_se_cac_rreg; - adev->se_cac_wreg = &soc15_se_cac_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; + adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; + adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; + adev->reg.uvd_ctx.rreg = &soc15_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; + adev->reg.didt.rreg = &soc15_didt_rreg; + adev->reg.didt.wreg = &soc15_didt_wreg; + adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; + adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; + adev->reg.se_cac.rreg = &soc15_se_cac_rreg; + adev->reg.se_cac.wreg = &soc15_se_cac_wreg; adev->rev_id = amdgpu_device_get_rev_id(adev); adev->external_rev_id = 0xFF; @@ -1201,6 +1197,7 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(9, 4, 4): case IP_VERSION(9, 5, 0): adev->asic_funcs = &aqua_vanjaram_asic_funcs; + adev->reg.smn.get_smn_base = &amdgpu_reg_smn_v1_0_get_base; adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_SDMA_MGCG | @@ -1479,7 +1476,8 @@ static void soc15_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && - (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14)) && + (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 15))) { /* AMD_CG_SUPPORT_DRM_MGCG */ data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0)); if (!(data & 0x01000000)) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h index c8ac11a9cdef6..46a6477b677ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h @@ -118,7 +118,6 @@ int vega10_reg_base_init(struct amdgpu_device *adev); int vega20_reg_base_init(struct amdgpu_device *adev); int arct_reg_base_init(struct amdgpu_device *adev); int aldebaran_reg_base_init(struct amdgpu_device *adev); -u64 aqua_vanjaram_encode_ext_smn_addressing(int ext_id); int aqua_vanjaram_init_soc_config(struct amdgpu_device *adev); ssize_t aqua_vanjaram_get_reg_state(struct amdgpu_device *adev, enum amdgpu_reg_state reg_state, void *buf, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h index 242b24f73c174..a7b5a95ebebbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h @@ -195,19 +195,22 @@ __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP, inst) /* inst equals to ext for some IPs */ -#define RREG32_SOC15_EXT(ip, inst, reg, ext) \ - RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ - + adev->asic_funcs->encode_ext_smn_addressing(ext)) \ - -#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ - WREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * 4 \ - + adev->asic_funcs->encode_ext_smn_addressing(ext), \ - value) \ - -#define RREG64_MCA(ext, mca_base, idx) \ - RREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8)) - -#define WREG64_MCA(ext, mca_base, idx, val) \ - WREG64_PCIE_EXT(adev->asic_funcs->encode_ext_smn_addressing(ext) + mca_base + (idx * 8), val) +#define RREG32_SOC15_EXT(ip, inst, reg, ext) \ + RREG32_PCIE_EXT((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + \ + reg) * 4 + \ + amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst)) + +#define WREG32_SOC15_EXT(ip, inst, reg, ext, value) \ + WREG32_PCIE_EXT( \ + (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) * \ + 4 + \ + amdgpu_reg_get_smn_base64(adev, ip##_HWIP, inst), \ + value) + +#define RREG64_MCA(smn_base, mca_base, idx) \ + RREG64_PCIE_EXT(smn_base + mca_base + (idx * 8)) + +#define WREG64_MCA(smn_base, mca_base, idx, val) \ + WREG64_PCIE_EXT(smn_base + mca_base + (idx * 8), val) #endif diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 25536d89635d3..fbd1d97f33add 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -141,6 +141,31 @@ static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = { .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1, }; +static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_encode_array_vcn0[] = { + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, +}; + +static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_encode_vcn0 = { + .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_encode_array_vcn0), + .codec_array = vcn_5_3_0_video_codecs_encode_array_vcn0, +}; + +static const struct amdgpu_video_codec_info vcn_5_3_0_video_codecs_decode_array_vcn0[] = { + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, +}; + +static const struct amdgpu_video_codecs vcn_5_3_0_video_codecs_decode_vcn0 = { + .codec_count = ARRAY_SIZE(vcn_5_3_0_video_codecs_decode_array_vcn0), + .codec_array = vcn_5_3_0_video_codecs_decode_array_vcn0, +}; + + static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, const struct amdgpu_video_codecs **codecs) { @@ -185,6 +210,12 @@ static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, else *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; return 0; + case IP_VERSION(5, 3, 0): + if (encode) + *codecs = &vcn_5_3_0_video_codecs_encode_vcn0; + else + *codecs = &vcn_5_3_0_video_codecs_decode_vcn0; + return 0; default: return -EINVAL; } @@ -198,10 +229,10 @@ static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); r = RREG32(data); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -212,10 +243,10 @@ static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(address, (reg)); WREG32(data, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 soc21_get_config_memsize(struct amdgpu_device *adev) @@ -391,6 +422,7 @@ soc21_asic_reset_method(struct amdgpu_device *adev) case IP_VERSION(14, 0, 1): case IP_VERSION(14, 0, 4): case IP_VERSION(14, 0, 5): + case IP_VERSION(15, 0, 0): return AMD_RESET_METHOD_MODE2; default: if (amdgpu_dpm_is_baco_supported(adev)) @@ -519,10 +551,6 @@ static void soc21_init_doorbell_index(struct amdgpu_device *adev) adev->doorbell_index.sdma_doorbell_range = 20; } -static void soc21_pre_asic_init(struct amdgpu_device *adev) -{ -} - static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, bool enter) { @@ -552,7 +580,6 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs = { .need_reset_on_init = &soc21_need_reset_on_init, .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, .supports_baco = &amdgpu_dpm_is_baco_supported, - .pre_asic_init = &soc21_pre_asic_init, .query_video_codecs = &soc21_query_video_codecs, .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, }; @@ -562,21 +589,15 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - - /* TODO: will add them during VCN v2 implementation */ - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; - - adev->didt_rreg = &soc21_didt_rreg; - adev->didt_wreg = &soc21_didt_wreg; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; + + adev->reg.didt.rreg = &soc21_didt_rreg; + adev->reg.didt.wreg = &soc21_didt_wreg; adev->asic_funcs = &soc21_asic_funcs; @@ -810,6 +831,34 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) AMD_PG_SUPPORT_GFX_PG; adev->external_rev_id = adev->rev_id + 0x50; break; + case IP_VERSION(11, 5, 4): + adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | + AMD_CG_SUPPORT_JPEG_MGCG | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | + AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_FGCG | + AMD_CG_SUPPORT_REPEATER_FGCG | + AMD_CG_SUPPORT_GFX_PERF_CLK | + AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_MC_MGCG | + AMD_CG_SUPPORT_MC_LS | + AMD_CG_SUPPORT_HDP_LS | + AMD_CG_SUPPORT_HDP_DS | + AMD_CG_SUPPORT_HDP_SD | + AMD_CG_SUPPORT_ATHUB_MGCG | + AMD_CG_SUPPORT_ATHUB_LS | + AMD_CG_SUPPORT_IH_CG | + AMD_CG_SUPPORT_BIF_MGCG | + AMD_CG_SUPPORT_BIF_LS; + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG | + AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_JPEG_DPG | + AMD_PG_SUPPORT_JPEG | + AMD_PG_SUPPORT_GFX_PG; + adev->external_rev_id = adev->rev_id + 0x1; + break; default: /* FIXME: not supported yet */ return -EINVAL; @@ -971,6 +1020,7 @@ static int soc21_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, case IP_VERSION(7, 11, 1): case IP_VERSION(7, 11, 2): case IP_VERSION(7, 11, 3): + case IP_VERSION(7, 11, 4): adev->nbio.funcs->update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE); adev->nbio.funcs->update_medium_grain_light_sleep(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 972b449ab89fa..d1adf19a51c45 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -327,10 +327,6 @@ static void soc24_init_doorbell_index(struct amdgpu_device *adev) adev->doorbell_index.sdma_doorbell_range = 20; } -static void soc24_pre_asic_init(struct amdgpu_device *adev) -{ -} - static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev, bool enter) { @@ -357,7 +353,6 @@ static const struct amdgpu_asic_funcs soc24_asic_funcs = { .need_reset_on_init = &soc24_need_reset_on_init, .get_pcie_replay_count = &soc24_get_pcie_replay_count, .supports_baco = &amdgpu_dpm_is_baco_supported, - .pre_asic_init = &soc24_pre_asic_init, .query_video_codecs = &soc24_query_video_codecs, .update_umd_stable_pstate = &soc24_update_umd_stable_pstate, }; @@ -367,18 +362,12 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); - adev->smc_rreg = NULL; - adev->smc_wreg = NULL; - adev->pcie_rreg = &amdgpu_device_indirect_rreg; - adev->pcie_wreg = &amdgpu_device_indirect_wreg; - adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; - adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; - adev->pciep_rreg = amdgpu_device_pcie_port_rreg; - adev->pciep_wreg = amdgpu_device_pcie_port_wreg; - adev->uvd_ctx_rreg = NULL; - adev->uvd_ctx_wreg = NULL; - adev->didt_rreg = NULL; - adev->didt_wreg = NULL; + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; adev->asic_funcs = &soc24_asic_funcs; @@ -489,7 +478,7 @@ static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block) if (adev->nbio.funcs->remap_hdp_registers) adev->nbio.funcs->remap_hdp_registers(adev); - if (adev->df.funcs->hw_init) + if (adev->df.funcs && adev->df.funcs->hw_init) adev->df.funcs->hw_init(adev); /* enable the doorbell aperture */ diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c new file mode 100644 index 0000000000000..709b1669b07bc --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c @@ -0,0 +1,939 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#include "amdgpu.h" +#include "soc15.h" +#include "soc15_common.h" +#include "soc_v1_0.h" +#include "amdgpu_ip.h" +#include "amdgpu_imu.h" +#include "gfxhub_v12_1.h" +#include "sdma_v7_1.h" +#include "gfx_v12_1.h" + +#include "gc/gc_12_1_0_offset.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "mp/mp_15_0_8_offset.h" + +#define XCC_REG_RANGE_0_LOW 0x1260 /* XCC gfxdec0 lower Bound */ +#define XCC_REG_RANGE_0_HIGH 0x3C00 /* XCC gfxdec0 upper Bound */ +#define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ +#define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ +#define NORMALIZE_XCC_REG_OFFSET(offset) \ + (offset & 0xFFFF) + +#define MID1_REG_RANGE_0_LOW 0x40000 +#define MID1_REG_RANGE_0_HIGH 0x80000 +#define NORMALIZE_MID_REG_OFFSET(offset) \ + (offset & 0x3FFFF) + +static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_encode_vcn0 = { + .codec_count = 0, + .codec_array = NULL, +}; + +static const struct amdgpu_video_codec_info vcn_5_0_2_video_codecs_decode_array_vcn0[] = { + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, + {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, +}; + +static const struct amdgpu_video_codecs vcn_5_0_2_video_codecs_decode_vcn0 = { + .codec_count = ARRAY_SIZE(vcn_5_0_2_video_codecs_decode_array_vcn0), + .codec_array = vcn_5_0_2_video_codecs_decode_array_vcn0, +}; + +static int soc_v1_0_query_video_codecs(struct amdgpu_device *adev, bool encode, + const struct amdgpu_video_codecs **codecs) +{ + switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { + case IP_VERSION(5, 0, 2): + if (encode) + *codecs = &vcn_5_0_2_video_codecs_encode_vcn0; + else + *codecs = &vcn_5_0_2_video_codecs_decode_vcn0; + return 0; + default: + return -EINVAL; + } +} + +/* Initialized doorbells for amdgpu including multimedia + * KFD can use all the rest in 2M doorbell bar */ +static void soc_v1_0_doorbell_index_init(struct amdgpu_device *adev) +{ + int i; + + adev->doorbell_index.kiq = AMDGPU_SOC_V1_0_DOORBELL_KIQ_START; + + adev->doorbell_index.mec_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START; + adev->doorbell_index.mes_ring0 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING0; + adev->doorbell_index.mes_ring1 = AMDGPU_SOC_V1_0_DOORBELL_MES_RING1; + + adev->doorbell_index.userqueue_start = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START; + adev->doorbell_index.userqueue_end = AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END; + adev->doorbell_index.xcc_doorbell_range = AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE; + + adev->doorbell_index.sdma_doorbell_range = 14; + for (i = 0; i < adev->sdma.num_instances; i++) + adev->doorbell_index.sdma_engine[i] = + AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START + + i * (adev->doorbell_index.sdma_doorbell_range >> 1); + + adev->doorbell_index.ih = AMDGPU_SOC_V1_0_DOORBELL_IH; + adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_SOC_V1_0_DOORBELL_VCN_START; + + adev->doorbell_index.first_non_cp = AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP; + adev->doorbell_index.last_non_cp = AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP; + + adev->doorbell_index.max_assignment = AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT << 1; +} + +/* Fixed pattern for upper 32bits smn addressing. + * bit[47:40]: Socket ID + * bit[39:34]: Die ID + * bit[32]: local or remote die in same socket + * The ext_id is comprised of socket_id and die_id. + * ext_id = (socket_id << 6) | (die_id) +*/ +u64 soc_v1_0_encode_ext_smn_addressing(int ext_id) +{ + u64 ext_offset; + int socket_id, die_id; + + /* local die routing for MID0 on local socket */ + if (ext_id == 0) + return 0; + + die_id = ext_id & 0x3; + socket_id = (ext_id >> 6) & 0xff; + + /* Initiated from host, accessing to non-MID0 is cross-die traffic */ + if (socket_id == 0) + ext_offset = ((u64)die_id << 34) | (1ULL << 32); + else if (socket_id != 0 && die_id != 0) + ext_offset = ((u64)socket_id << 40) | ((u64)die_id << 34) | + (3ULL << 32); + else + ext_offset = ((u64)socket_id << 40) | (1ULL << 33); + + return ext_offset; +} + +static u32 soc_v1_0_get_config_memsize(struct amdgpu_device *adev) +{ + return adev->nbio.funcs->get_memsize(adev); +} + +static u32 soc_v1_0_get_xclk(struct amdgpu_device *adev) +{ + return adev->clock.spll.reference_freq; +} + +void soc_v1_0_grbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, + u32 queue, u32 vmid, + int xcc_id) +{ + u32 grbm_gfx_cntl = 0; + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); + grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); + + WREG32_SOC15_RLC_SHADOW(GC, xcc_id, regGRBM_GFX_CNTL, grbm_gfx_cntl); +} + +static struct soc15_allowed_register_entry soc_v1_0_allowed_read_registers[] = { + { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS) }, + { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2) }, + { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS3) }, + { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0) }, + { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1) }, + { SOC15_REG_ENTRY(GC, 0, regCP_STAT) }, + { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1) }, + { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2) }, + { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3) }, + { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT) }, + { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1) }, + { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS) }, + { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT) }, + { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1) }, + { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS) }, + { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG_1) }, +}; + +static uint32_t soc_v1_0_read_indexed_register(struct amdgpu_device *adev, + u32 se_num, + u32 sh_num, + u32 reg_offset) +{ + uint32_t val; + + mutex_lock(&adev->grbm_idx_mutex); + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); + + val = RREG32(reg_offset); + + if (se_num != 0xffffffff || sh_num != 0xffffffff) + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); + mutex_unlock(&adev->grbm_idx_mutex); + return val; +} + +static uint32_t soc_v1_0_get_register_value(struct amdgpu_device *adev, + bool indexed, u32 se_num, + u32 sh_num, u32 reg_offset) +{ + if (indexed) { + return soc_v1_0_read_indexed_register(adev, se_num, sh_num, reg_offset); + } else { + if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG_1) && + adev->gfx.config.gb_addr_config) + return adev->gfx.config.gb_addr_config; + return RREG32(reg_offset); + } +} + +static int soc_v1_0_read_register(struct amdgpu_device *adev, + u32 se_num, u32 sh_num, + u32 reg_offset, u32 *value) +{ + uint32_t i; + struct soc15_allowed_register_entry *en; + + *value = 0; + for (i = 0; i < ARRAY_SIZE(soc_v1_0_allowed_read_registers); i++) { + en = &soc_v1_0_allowed_read_registers[i]; + if (!adev->reg_offset[en->hwip][en->inst]) + continue; + else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] + + en->reg_offset)) + continue; + + *value = soc_v1_0_get_register_value(adev, + soc_v1_0_allowed_read_registers[i].grbm_indexed, + se_num, sh_num, reg_offset); + return 0; + } + return -EINVAL; +} + +static bool soc_v1_0_need_full_reset(struct amdgpu_device *adev) +{ + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 1, 0): + default: + return true; + } +} + +static bool soc_v1_0_need_reset_on_init(struct amdgpu_device *adev) +{ + + return false; +} + +static enum amd_reset_method +soc_v1_0_asic_reset_method(struct amdgpu_device *adev) +{ + if ((adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) || + (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 8))) { + if (amdgpu_reset_method != -1) + dev_warn_once(adev->dev, "Reset override isn't supported, using Mode2 instead.\n"); + + return AMD_RESET_METHOD_MODE2; + } + + return amdgpu_reset_method; +} + +static int soc_v1_0_asic_reset(struct amdgpu_device *adev) +{ + switch (soc_v1_0_asic_reset_method(adev)) { + case AMD_RESET_METHOD_MODE2: + dev_info(adev->dev, "MODE2 reset\n"); + return amdgpu_dpm_mode2_reset(adev); + default: + dev_info(adev->dev, "Invalid reset method Not supported\n"); + return -EOPNOTSUPP; + } + + return 0; +} + +static const struct amdgpu_asic_funcs soc_v1_0_asic_funcs = { + .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, + .read_register = &soc_v1_0_read_register, + .get_config_memsize = &soc_v1_0_get_config_memsize, + .get_xclk = &soc_v1_0_get_xclk, + .need_full_reset = &soc_v1_0_need_full_reset, + .init_doorbell_index = &soc_v1_0_doorbell_index_init, + .need_reset_on_init = &soc_v1_0_need_reset_on_init, + .encode_ext_smn_addressing = &soc_v1_0_encode_ext_smn_addressing, + .reset = soc_v1_0_asic_reset, + .reset_method = &soc_v1_0_asic_reset_method, + .query_video_codecs = &soc_v1_0_query_video_codecs, +}; + +static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; + adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; + adev->reg.pcie.rreg_ext = &amdgpu_device_indirect_rreg_ext; + adev->reg.pcie.wreg_ext = &amdgpu_device_indirect_wreg_ext; + adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; + adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; + adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; + adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; + adev->reg.pcie.rreg64_ext = &amdgpu_device_indirect_rreg64_ext; + adev->reg.pcie.wreg64_ext = &amdgpu_device_indirect_wreg64_ext; + + adev->asic_funcs = &soc_v1_0_asic_funcs; + + adev->rev_id = amdgpu_device_get_rev_id(adev); + adev->external_rev_id = 0xff; + + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(12, 1, 0): + adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS; + adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; + adev->external_rev_id = adev->rev_id + 0x50; + break; + default: + /* FIXME: not supported yet */ + return -EINVAL; + } + + return 0; +} + +static int soc_v1_0_common_late_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + /* Enable selfring doorbell aperture late because doorbell BAR + * aperture will change if resize BAR successfully in gmc sw_init. + */ + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); + + return 0; +} + +static int soc_v1_0_common_sw_init(struct amdgpu_ip_block *ip_block) +{ + return 0; +} + +static int soc_v1_0_common_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + /* enable the doorbell aperture */ + adev->nbio.funcs->enable_doorbell_aperture(adev, true); + + return 0; +} + +static int soc_v1_0_common_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + + adev->nbio.funcs->enable_doorbell_aperture(adev, false); + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); + + return 0; +} + +static int soc_v1_0_common_suspend(struct amdgpu_ip_block *ip_block) +{ + return soc_v1_0_common_hw_fini(ip_block); +} + +static int soc_v1_0_common_resume(struct amdgpu_ip_block *ip_block) +{ + return soc_v1_0_common_hw_init(ip_block); +} + +static bool soc_v1_0_common_is_idle(struct amdgpu_ip_block *ip_block) +{ + return true; +} + +static int soc_v1_0_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + return 0; +} + +static int soc_v1_0_common_set_powergating_state(struct amdgpu_ip_block *ip_block, + enum amd_powergating_state state) +{ + return 0; +} + +static void soc_v1_0_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, + u64 *flags) +{ + return; +} + +static const struct amd_ip_funcs soc_v1_0_common_ip_funcs = { + .name = "soc_v1_0_common", + .early_init = soc_v1_0_common_early_init, + .late_init = soc_v1_0_common_late_init, + .sw_init = soc_v1_0_common_sw_init, + .hw_init = soc_v1_0_common_hw_init, + .hw_fini = soc_v1_0_common_hw_fini, + .suspend = soc_v1_0_common_suspend, + .resume = soc_v1_0_common_resume, + .is_idle = soc_v1_0_common_is_idle, + .set_clockgating_state = soc_v1_0_common_set_clockgating_state, + .set_powergating_state = soc_v1_0_common_set_powergating_state, + .get_clockgating_state = soc_v1_0_common_get_clockgating_state, +}; + +const struct amdgpu_ip_block_version soc_v1_0_common_ip_block = { + .type = AMD_IP_BLOCK_TYPE_COMMON, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &soc_v1_0_common_ip_funcs, +}; + +static enum amdgpu_gfx_partition __soc_v1_0_calc_xcp_mode(struct amdgpu_xcp_mgr *xcp_mgr) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + int num_xcc, num_xcc_per_xcp = 0, mode = 0; + + num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); + if (adev->gfx.funcs && + adev->gfx.funcs->get_xccs_per_xcp) + num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); + if ((num_xcc_per_xcp) && (num_xcc % num_xcc_per_xcp == 0)) + mode = num_xcc / num_xcc_per_xcp; + + if (num_xcc_per_xcp == 1) + return AMDGPU_CPX_PARTITION_MODE; + + switch (mode) { + case 1: + return AMDGPU_SPX_PARTITION_MODE; + case 2: + return AMDGPU_DPX_PARTITION_MODE; + case 3: + return AMDGPU_TPX_PARTITION_MODE; + case 4: + return AMDGPU_QPX_PARTITION_MODE; + default: + return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; + } + + return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; +} + +static int soc_v1_0_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) +{ + enum amdgpu_gfx_partition derv_mode, mode; + struct amdgpu_device *adev = xcp_mgr->adev; + + mode = AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; + derv_mode = __soc_v1_0_calc_xcp_mode(xcp_mgr); + + if (amdgpu_sriov_vf(adev) || !adev->psp.funcs) + return derv_mode; + + if (adev->nbio.funcs && + adev->nbio.funcs->get_compute_partition_mode) { + mode = adev->nbio.funcs->get_compute_partition_mode(adev); + if (mode != derv_mode) + dev_warn(adev->dev, + "Mismatch in compute partition mode - reported : %d derived : %d", + mode, derv_mode); + } + + return mode; +} + +static int __soc_v1_0_get_xcc_per_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int mode) +{ + int num_xcc, num_xcc_per_xcp = 0; + + num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); + + switch (mode) { + case AMDGPU_SPX_PARTITION_MODE: + num_xcc_per_xcp = num_xcc; + break; + case AMDGPU_DPX_PARTITION_MODE: + num_xcc_per_xcp = num_xcc / 2; + break; + case AMDGPU_TPX_PARTITION_MODE: + num_xcc_per_xcp = num_xcc / 3; + break; + case AMDGPU_QPX_PARTITION_MODE: + num_xcc_per_xcp = num_xcc / 4; + break; + case AMDGPU_CPX_PARTITION_MODE: + num_xcc_per_xcp = 1; + break; + } + + return num_xcc_per_xcp; +} + +static int __soc_v1_0_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, + enum AMDGPU_XCP_IP_BLOCK ip_id, + struct amdgpu_xcp_ip *ip) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + int num_sdma, num_vcn, num_shared_vcn, num_xcp; + int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; + + num_sdma = adev->sdma.num_instances; + num_vcn = adev->vcn.num_vcn_inst; + num_shared_vcn = 1; + + num_xcc_xcp = adev->gfx.num_xcc_per_xcp; + num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; + + switch (xcp_mgr->mode) { + case AMDGPU_SPX_PARTITION_MODE: + case AMDGPU_DPX_PARTITION_MODE: + case AMDGPU_TPX_PARTITION_MODE: + case AMDGPU_QPX_PARTITION_MODE: + case AMDGPU_CPX_PARTITION_MODE: + num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); + num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); + break; + default: + return -EINVAL; + } + + if (num_vcn && num_xcp > num_vcn) + num_shared_vcn = num_xcp / num_vcn; + + switch (ip_id) { + case AMDGPU_XCP_GFXHUB: + ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); + ip->ip_funcs = &gfxhub_v12_1_xcp_funcs; + break; + case AMDGPU_XCP_GFX: + ip->inst_mask = XCP_INST_MASK(num_xcc_xcp, xcp_id); + ip->ip_funcs = &gfx_v12_1_xcp_funcs; + break; + case AMDGPU_XCP_SDMA: + ip->inst_mask = XCP_INST_MASK(num_sdma_xcp, xcp_id); + ip->ip_funcs = &sdma_v7_1_xcp_funcs; + break; + case AMDGPU_XCP_VCN: + ip->inst_mask = + XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); + /* TODO : Assign IP funcs */ + break; + default: + return -EINVAL; + } + + ip->ip_id = ip_id; + + return 0; +} + +static int soc_v1_0_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, + int mode, + struct amdgpu_xcp_cfg *xcp_cfg) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + int max_res[AMDGPU_XCP_RES_MAX] = {}; + bool res_lt_xcp; + int num_xcp, i; + u16 nps_modes; + + if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) + return -EINVAL; + + max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); + max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; + max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; + max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; + + switch (mode) { + case AMDGPU_SPX_PARTITION_MODE: + num_xcp = 1; + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); + break; + case AMDGPU_DPX_PARTITION_MODE: + num_xcp = 2; + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE); + break; + case AMDGPU_TPX_PARTITION_MODE: + num_xcp = 3; + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | + BIT(AMDGPU_NPS4_PARTITION_MODE); + break; + case AMDGPU_QPX_PARTITION_MODE: + num_xcp = 4; + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | + BIT(AMDGPU_NPS4_PARTITION_MODE); + break; + case AMDGPU_CPX_PARTITION_MODE: + num_xcp = NUM_XCC(adev->gfx.xcc_mask); + nps_modes = BIT(AMDGPU_NPS1_PARTITION_MODE) | + BIT(AMDGPU_NPS4_PARTITION_MODE); + break; + default: + return -EINVAL; + } + + xcp_cfg->compatible_nps_modes = + (adev->gmc.supported_nps_modes & nps_modes); + xcp_cfg->num_res = ARRAY_SIZE(max_res); + + for (i = 0; i < xcp_cfg->num_res; i++) { + res_lt_xcp = max_res[i] < num_xcp; + xcp_cfg->xcp_res[i].id = i; + xcp_cfg->xcp_res[i].num_inst = + res_lt_xcp ? 1 : max_res[i] / num_xcp; + xcp_cfg->xcp_res[i].num_inst = + i == AMDGPU_XCP_RES_JPEG ? + xcp_cfg->xcp_res[i].num_inst * + adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; + xcp_cfg->xcp_res[i].num_shared = + res_lt_xcp ? num_xcp / max_res[i] : 1; + } + + return 0; +} + +static enum amdgpu_gfx_partition __soc_v1_0_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + int num_xcc; + + num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask); + + if (adev->gmc.num_mem_partitions == 1) + return AMDGPU_SPX_PARTITION_MODE; + + if (adev->gmc.num_mem_partitions == num_xcc) + return AMDGPU_CPX_PARTITION_MODE; + + if (adev->gmc.num_mem_partitions == 2) + return AMDGPU_DPX_PARTITION_MODE; + + return AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE; +} + +static bool __soc_v1_0_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, + enum amdgpu_gfx_partition mode) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + int num_xcc, num_xccs_per_xcp; + + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + switch (mode) { + case AMDGPU_SPX_PARTITION_MODE: + return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; + case AMDGPU_DPX_PARTITION_MODE: + return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; + case AMDGPU_TPX_PARTITION_MODE: + return (adev->gmc.num_mem_partitions == 1 || + adev->gmc.num_mem_partitions == 3) && + ((num_xcc % 3) == 0); + case AMDGPU_QPX_PARTITION_MODE: + num_xccs_per_xcp = num_xcc / 4; + return (adev->gmc.num_mem_partitions == 1 || + adev->gmc.num_mem_partitions == 4) && + (num_xccs_per_xcp >= 2); + case AMDGPU_CPX_PARTITION_MODE: + /* (num_xcc > 1) because 1 XCC is considered SPX, not CPX. + * (num_xcc % adev->gmc.num_mem_partitions) == 0 because + * num_compute_partitions can't be less than num_mem_partitions + */ + return ((num_xcc > 1) && + (num_xcc % adev->gmc.num_mem_partitions) == 0); + default: + return false; + } + + return false; +} + +static void __soc_v1_0_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) +{ + int mode; + + xcp_mgr->avail_xcp_modes = 0; + + for_each_inst(mode, xcp_mgr->supp_xcp_modes) { + if (__soc_v1_0_is_valid_mode(xcp_mgr, mode)) + xcp_mgr->avail_xcp_modes |= BIT(mode); + } +} + +static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, + int mode, int *num_xcps) +{ + int num_xcc_per_xcp, num_xcc, ret; + struct amdgpu_device *adev; + u32 flags = 0; + + adev = xcp_mgr->adev; + num_xcc = NUM_XCC(adev->gfx.xcc_mask); + + if (mode == AMDGPU_AUTO_COMPUTE_PARTITION_MODE) { + mode = __soc_v1_0_get_auto_mode(xcp_mgr); + if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) { + dev_err(adev->dev, + "Invalid config, no compatible compute partition mode found, available memory partitions: %d", + adev->gmc.num_mem_partitions); + return -EINVAL; + } + } else if (!__soc_v1_0_is_valid_mode(xcp_mgr, mode)) { + dev_err(adev->dev, + "Invalid compute partition mode requested, requested: %s, available memory partitions: %d", + amdgpu_gfx_compute_mode_desc(mode), adev->gmc.num_mem_partitions); + return -EINVAL; + } + + if (adev->kfd.init_complete && !amdgpu_in_reset(adev)) + flags |= AMDGPU_XCP_OPS_KFD; + + if (flags & AMDGPU_XCP_OPS_KFD) { + ret = amdgpu_amdkfd_check_and_lock_kfd(adev); + if (ret) + goto out; + } + + ret = amdgpu_xcp_pre_partition_switch(xcp_mgr, flags); + if (ret) + goto unlock; + + num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode); + if (adev->gfx.imu.funcs && + adev->gfx.imu.funcs->switch_compute_partition) { + ret = adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode); + if (ret) + goto out; + } + if (adev->gfx.imu.funcs && + adev->gfx.imu.funcs->init_mcm_addr_lut && + amdgpu_emu_mode) + adev->gfx.imu.funcs->init_mcm_addr_lut(adev); + + /* Init info about new xcps */ + *num_xcps = num_xcc / num_xcc_per_xcp; + amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); + + ret = amdgpu_xcp_post_partition_switch(xcp_mgr, flags); + if (!ret) + __soc_v1_0_update_available_partition_mode(xcp_mgr); +unlock: + if (flags & AMDGPU_XCP_OPS_KFD) + amdgpu_amdkfd_unlock_kfd(adev); +out: + return ret; +} + +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV +static int __soc_v1_0_get_xcp_mem_id(struct amdgpu_device *adev, + int xcc_id, uint8_t *mem_id) +{ + /* memory/spatial modes validation check is already done */ + *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp; + *mem_id /= adev->xcp_mgr->num_xcp_per_mem_partition; + + return 0; +} + +static int soc_v1_0_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, + struct amdgpu_xcp *xcp, uint8_t *mem_id) +{ + struct amdgpu_numa_info numa_info; + struct amdgpu_device *adev; + uint32_t xcc_mask; + int r, i, xcc_id; + + adev = xcp_mgr->adev; + /* TODO: BIOS is not returning the right info now + * Check on this later + */ + /* + if (adev->gmc.gmc_funcs->query_mem_partition_mode) + mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); + */ + if (adev->gmc.num_mem_partitions == 1) { + /* Only one range */ + *mem_id = 0; + return 0; + } + + r = amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &xcc_mask); + if (r || !xcc_mask) + return -EINVAL; + + xcc_id = ffs(xcc_mask) - 1; + if (!adev->gmc.is_app_apu) + return __soc_v1_0_get_xcp_mem_id(adev, xcc_id, mem_id); + + r = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info); + + if (r) + return r; + + r = -EINVAL; + for (i = 0; i < adev->gmc.num_mem_partitions; ++i) { + if (adev->gmc.mem_partitions[i].numa.node == numa_info.nid) { + *mem_id = i; + r = 0; + break; + } + } + + return r; +} +#endif + +static int soc_v1_0_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, + enum AMDGPU_XCP_IP_BLOCK ip_id, + struct amdgpu_xcp_ip *ip) +{ + if (!ip) + return -EINVAL; + + return __soc_v1_0_get_xcp_ip_info(xcp_mgr, xcp_id, ip_id, ip); +} + +struct amdgpu_xcp_mgr_funcs soc_v1_0_xcp_funcs = { + .switch_partition_mode = &soc_v1_0_switch_partition_mode, + .query_partition_mode = &soc_v1_0_query_partition_mode, + .get_ip_details = &soc_v1_0_get_xcp_ip_details, + .get_xcp_res_info = &soc_v1_0_get_xcp_res_info, +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV + .get_xcp_mem_id = &soc_v1_0_get_xcp_mem_id, +#endif +}; + +static int soc_v1_0_xcp_mgr_init(struct amdgpu_device *adev) +{ + int ret; + + if (amdgpu_sriov_vf(adev)) + soc_v1_0_xcp_funcs.switch_partition_mode = NULL; + + ret = amdgpu_xcp_mgr_init(adev, AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE, + 1, &soc_v1_0_xcp_funcs); + if (ret) + return ret; + + amdgpu_xcp_update_supported_modes(adev->xcp_mgr); + /* TODO: Default memory node affinity init */ + + return ret; +} + +int soc_v1_0_init_soc_config(struct amdgpu_device *adev) +{ + int ret, i; + int xcc_inst_per_aid = 4; + uint16_t xcc_mask, sdma_mask = 0; + + xcc_mask = adev->gfx.xcc_mask; + adev->aid_mask = 0; + for (i = 0; xcc_mask; xcc_mask >>= xcc_inst_per_aid, i++) { + if (xcc_mask & ((1U << xcc_inst_per_aid) - 1)) + adev->aid_mask |= (1 << i); + } + + adev->sdma.num_inst_per_xcc = 2; + for_each_inst(i, adev->gfx.xcc_mask) + sdma_mask |= + GENMASK(adev->sdma.num_inst_per_xcc - 1, 0) << + (i * adev->sdma.num_inst_per_xcc); + adev->sdma.sdma_mask = sdma_mask; + adev->sdma.num_instances = NUM_XCC(adev->sdma.sdma_mask); + + ret = soc_v1_0_xcp_mgr_init(adev); + if (ret) + return ret; + + amdgpu_ip_map_init(adev); + + return 0; +} + +bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg) +{ + if (((reg >= XCC_REG_RANGE_0_LOW) && (reg < XCC_REG_RANGE_0_HIGH)) || + ((reg >= XCC_REG_RANGE_1_LOW) && (reg < XCC_REG_RANGE_1_HIGH))) + return true; + else + return false; +} + +uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg) +{ + uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); + + /* If it is an XCC reg, normalize the reg to keep + * lower 16 bits in local xcc */ + + if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) + return normalized_reg; + else + return reg; +} + +bool soc_v1_0_mid1_reg_range(uint32_t reg) +{ + uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) + return false; + + if ((reg >= MID1_REG_RANGE_0_LOW) && (reg < MID1_REG_RANGE_0_HIGH)) + return true; + else + return false; +} + +uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg) +{ + uint32_t normalized_reg = soc_v1_0_normalize_xcc_reg_offset(reg); + + if (soc_v1_0_normalize_xcc_reg_range(normalized_reg)) + return soc_v1_0_normalize_xcc_reg_offset(reg); + + /* check if the reg offset is inside MID1. */ + if (soc_v1_0_mid1_reg_range(reg)) + return NORMALIZE_MID_REG_OFFSET(reg); + + return reg; +} + diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h new file mode 100644 index 0000000000000..16c220fcc4e92 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.h @@ -0,0 +1,39 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SOC_V1_0_H__ +#define __SOC_V1_0_H__ + +extern const struct amdgpu_ip_block_version soc_v1_0_common_ip_block; + +void soc_v1_0_grbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, + u32 queue, u32 vmid, + int xcc_id); +int soc_v1_0_init_soc_config(struct amdgpu_device *adev); +bool soc_v1_0_normalize_xcc_reg_range(uint32_t reg); +bool soc_v1_0_mid1_reg_range(uint32_t reg); +uint32_t soc_v1_0_normalize_xcc_reg_offset(uint32_t reg); +uint32_t soc_v1_0_normalize_reg_offset(uint32_t reg); +u64 soc_v1_0_encode_ext_smn_addressing(int ext_id); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h index 8a3f326474e54..f6178da910d35 100644 --- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h +++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h @@ -155,6 +155,7 @@ struct ta_ras_init_flags { uint8_t channel_dis_num; uint8_t nps_mode; uint32_t active_umc_mask; + uint8_t vram_type; }; struct ta_ras_mca_addr { diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c index 0f5b1719fda56..6cf674dfc8c40 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v12_0.c @@ -183,50 +183,97 @@ static void umc_v12_0_get_retire_flip_bits(struct amdgpu_device *adev) if (adev->gmc.gmc_funcs->query_mem_partition_mode) nps = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); - /* default setting */ - flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; - flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; - flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; - flip_bits->flip_row_bit = 13; - flip_bits->bit_num = 4; - flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; - - if (nps == AMDGPU_NPS2_PARTITION_MODE) { + if (adev->gmc.num_umc == 16) { + /* default setting */ + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_C2_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C3_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_C4_BIT; + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R13_BIT; + flip_bits->flip_row_bit = 13; + flip_bits->bit_num = 4; + flip_bits->r13_in_pa = UMC_V12_0_PA_R13_BIT; + + if (nps == AMDGPU_NPS2_PARTITION_MODE) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; + } else if (nps == AMDGPU_NPS4_PARTITION_MODE) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; + } + + switch (vram_type) { + case AMDGPU_VRAM_TYPE_HBM: + /* other nps modes are taken as nps1 */ + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; + else if (nps == AMDGPU_NPS4_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + + break; + case AMDGPU_VRAM_TYPE_HBM3E: + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; + flip_bits->flip_row_bit = 12; + + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + else if (nps == AMDGPU_NPS4_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + + break; + default: + dev_warn(adev->dev, + "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); + break; + } + } else if (adev->gmc.num_umc == 8) { + /* default setting */ flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH5_BIT; flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_C2_BIT; flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B1_BIT; + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; + flip_bits->flip_row_bit = 12; + flip_bits->bit_num = 4; flip_bits->r13_in_pa = UMC_V12_0_PA_R12_BIT; - } else if (nps == AMDGPU_NPS4_PARTITION_MODE) { - flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; - flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; - flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; - flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; - } - switch (vram_type) { - case AMDGPU_VRAM_TYPE_HBM: - /* other nps modes are taken as nps1 */ - if (nps == AMDGPU_NPS2_PARTITION_MODE) + if (nps == AMDGPU_NPS2_PARTITION_MODE) { + flip_bits->flip_bits_in_pa[0] = UMC_V12_0_PA_CH4_BIT; + flip_bits->flip_bits_in_pa[1] = UMC_V12_0_PA_CH5_BIT; + flip_bits->flip_bits_in_pa[2] = UMC_V12_0_PA_B0_BIT; + flip_bits->r13_in_pa = UMC_V12_0_PA_R11_BIT; + } + + switch (vram_type) { + case AMDGPU_VRAM_TYPE_HBM: flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; - else if (nps == AMDGPU_NPS4_PARTITION_MODE) - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; - break; - case AMDGPU_VRAM_TYPE_HBM3E: - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R12_BIT; - flip_bits->flip_row_bit = 12; + /* other nps modes are taken as nps1 */ + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; - if (nps == AMDGPU_NPS2_PARTITION_MODE) + break; + case AMDGPU_VRAM_TYPE_HBM3E: flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R11_BIT; - else if (nps == AMDGPU_NPS4_PARTITION_MODE) - flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + flip_bits->flip_row_bit = 12; - break; - default: + if (nps == AMDGPU_NPS2_PARTITION_MODE) + flip_bits->flip_bits_in_pa[3] = UMC_V12_0_PA_R10_BIT; + + break; + default: + dev_warn(adev->dev, + "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); + break; + } + } else { dev_warn(adev->dev, - "Unknown HBM type, set RAS retire flip bits to the value in NPS1 mode.\n"); - break; + "Unsupported UMC number(%d), failed to set RAS flip bits.\n", + adev->gmc.num_umc); + + return; } adev->umc.retire_unit = 0x1 << flip_bits->bit_num; diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c index f17d297b594bc..f2dfacb952b8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c @@ -267,7 +267,8 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, if ((adev->asic_type == CHIP_ARCTURUS) && amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) - DRM_WARN("Fail to disable DF-Cstate.\n"); + drm_warn(adev_to_drm(adev), + "Fail to disable DF-Cstate.\n"); LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { umc_reg_offset = get_umc_6_reg_offset(adev, @@ -284,7 +285,7 @@ static void umc_v6_1_query_ras_error_count(struct amdgpu_device *adev, if ((adev->asic_type == CHIP_ARCTURUS) && amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) - DRM_WARN("Fail to enable DF-Cstate\n"); + drm_warn(adev_to_drm(adev), "Fail to enable DF-Cstate\n"); if (rsmu_umc_index_state) umc_v6_1_enable_umc_index_mode(adev); @@ -366,7 +367,7 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, if ((adev->asic_type == CHIP_ARCTURUS) && amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) - DRM_WARN("Fail to disable DF-Cstate.\n"); + drm_warn(adev_to_drm(adev), "Fail to disable DF-Cstate.\n"); LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { umc_reg_offset = get_umc_6_reg_offset(adev, @@ -382,7 +383,7 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, if ((adev->asic_type == CHIP_ARCTURUS) && amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) - DRM_WARN("Fail to enable DF-Cstate\n"); + drm_warn(adev_to_drm(adev), "Fail to enable DF-Cstate\n"); if (rsmu_umc_index_state) umc_v6_1_enable_umc_index_mode(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 2e79a3afc7748..fea576a7f397f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -660,7 +660,7 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) r = uvd_v3_1_fw_validate(adev); if (r) { - DRM_ERROR("amdgpu: UVD Firmware validate fail (%d).\n", r); + drm_err(adev_to_drm(adev), "UVD Firmware validate fail (%d).\n", r); return r; } @@ -668,13 +668,13 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) r = amdgpu_ring_test_helper(ring); if (r) { - DRM_ERROR("amdgpu: UVD ring test fail (%d).\n", r); + drm_err(adev_to_drm(adev), "UVD ring test failed (%d).\n", r); goto done; } r = amdgpu_ring_alloc(ring, 10); if (r) { - DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); goto done; } @@ -701,7 +701,7 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) done: if (!r) - DRM_INFO("UVD initialized successfully.\n"); + drm_info(adev_to_drm(adev), "UVD initialized successfully.\n"); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 4b96fd5837720..73ce3d211ed64 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -167,7 +167,7 @@ static int uvd_v4_2_hw_init(struct amdgpu_ip_block *ip_block) r = amdgpu_ring_alloc(ring, 10); if (r) { - DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); goto done; } @@ -194,7 +194,7 @@ static int uvd_v4_2_hw_init(struct amdgpu_ip_block *ip_block) done: if (!r) - DRM_INFO("UVD initialized successfully.\n"); + drm_info(adev_to_drm(adev), "UVD initialized successfully.\n"); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 71409ad8b7ed1..454f109cbb2e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -164,7 +164,7 @@ static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block) r = amdgpu_ring_alloc(ring, 10); if (r) { - DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); goto done; } @@ -191,7 +191,7 @@ static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block) done: if (!r) - DRM_INFO("UVD initialized successfully.\n"); + drm_info(adev_to_drm(adev), "UVD initialized successfully.\n"); return r; @@ -846,7 +846,7 @@ static void uvd_v5_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 if (RREG32_SMC(ixCURRENT_PG_STATUS) & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { - DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); + drm_info(adev_to_drm(adev), "Cannot get clockgating state when UVD is powergated.\n"); goto out; } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index ceb94bbb03a48..ecd7ead7a60b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -408,7 +408,7 @@ static int uvd_v6_0_sw_init(struct amdgpu_ip_block *ip_block) adev->uvd.inst->irq.num_types = 1; adev->uvd.num_enc_rings = 0; - DRM_INFO("UVD ENC is disabled\n"); + drm_info(adev_to_drm(adev), "UVD ENC is disabled\n"); } ring = &adev->uvd.inst->ring; @@ -478,7 +478,7 @@ static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block) r = amdgpu_ring_alloc(ring, 10); if (r) { - DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); + drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); goto done; } @@ -515,9 +515,9 @@ static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block) done: if (!r) { if (uvd_v6_0_enc_support(adev)) - DRM_INFO("UVD and UVD ENC initialized successfully.\n"); + drm_info(adev_to_drm(adev), "UVD and UVD ENC initialized successfully.\n"); else - DRM_INFO("UVD initialized successfully.\n"); + drm_info(adev_to_drm(adev), "UVD initialized successfully.\n"); } return r; @@ -1513,7 +1513,7 @@ static void uvd_v6_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 data = RREG32_SMC(ixCURRENT_PG_STATUS); if (data & CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { - DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); + drm_info(adev_to_drm(adev), "Cannot get clockgating state when UVD is powergated.\n"); goto out; } @@ -1633,10 +1633,10 @@ static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) { if (adev->asic_type >= CHIP_POLARIS10) { adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_vm_funcs; - DRM_INFO("UVD is enabled in VM mode\n"); + drm_info(adev_to_drm(adev), "UVD is enabled in VM mode\n"); } else { adev->uvd.inst->ring.funcs = &uvd_v6_0_ring_phys_funcs; - DRM_INFO("UVD is enabled in physical mode\n"); + drm_info(adev_to_drm(adev), "UVD is enabled in physical mode\n"); } } @@ -1647,7 +1647,7 @@ static void uvd_v6_0_set_enc_ring_funcs(struct amdgpu_device *adev) for (i = 0; i < adev->uvd.num_enc_rings; ++i) adev->uvd.inst->ring_enc[i].funcs = &uvd_v6_0_enc_ring_vm_funcs; - DRM_INFO("UVD ENC is enabled in VM mode\n"); + drm_info(adev_to_drm(adev), "UVD ENC is enabled in VM mode\n"); } static const struct amdgpu_irq_src_funcs uvd_v6_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 1f8866f3f63c7..df2c83348315d 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -438,7 +438,7 @@ static int uvd_v7_0_sw_init(struct amdgpu_ip_block *ip_block) adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); } - DRM_INFO("PSP loading UVD firmware\n"); + drm_info(adev_to_drm(adev), "PSP loading UVD firmware\n"); } for (j = 0; j < adev->uvd.num_uvd_inst; j++) { @@ -542,7 +542,7 @@ static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block) r = amdgpu_ring_alloc(ring, 10); if (r) { - DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); + drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r); goto done; } @@ -582,7 +582,7 @@ static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block) } done: if (!r) - DRM_INFO("UVD and UVD ENC initialized successfully.\n"); + drm_info(adev_to_drm(adev), "UVD and UVD ENC initialized successfully.\n"); return r; } @@ -1606,7 +1606,7 @@ static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) continue; adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; adev->uvd.inst[i].ring.me = i; - DRM_INFO("UVD(%d) is enabled in VM mode\n", i); + drm_info(adev_to_drm(adev), "UVD(%d) is enabled in VM mode\n", i); } } @@ -1622,7 +1622,7 @@ static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) adev->uvd.inst[j].ring_enc[i].me = j; } - DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); + drm_info(adev_to_drm(adev), "UVD(%d) ENC is enabled in VM mode\n", j); } } diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c index 9ae4246185560..5b7b46d242c6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c @@ -47,11 +47,6 @@ #define VCE_V1_0_DATA_SIZE (7808 * (AMDGPU_MAX_VCE_HANDLES + 1)) #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02 -#define VCE_V1_0_GART_PAGE_START \ - (AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS) -#define VCE_V1_0_GART_ADDR_START \ - (VCE_V1_0_GART_PAGE_START * AMDGPU_GPU_PAGE_SIZE) - static void vce_v1_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v1_0_set_irq_funcs(struct amdgpu_device *adev); @@ -535,27 +530,29 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block) */ static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev) { - u64 gpu_addr = amdgpu_bo_gpu_offset(adev->vce.vcpu_bo); u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo); u64 max_vcpu_bo_addr = 0xffffffff - bo_size; u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE; u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo); u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID; + u64 vce_gart_start_offs; + int r; - /* - * Check if the VCPU BO already has a 32-bit address. - * Eg. if MC is configured to put VRAM in the low address range. - */ - if (gpu_addr <= max_vcpu_bo_addr) - return 0; + r = amdgpu_gtt_mgr_alloc_entries(&adev->mman.gtt_mgr, + &adev->vce.gart_node, num_pages, + DRM_MM_INSERT_LOW); + if (r) + return r; + + vce_gart_start_offs = amdgpu_gtt_node_to_byte_offset(&adev->vce.gart_node); /* Check if we can map the VCPU BO in GART to a 32-bit address. */ - if (adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START > max_vcpu_bo_addr) + if (adev->gmc.gart_start + vce_gart_start_offs > max_vcpu_bo_addr) return -EINVAL; - amdgpu_gart_map_vram_range(adev, pa, VCE_V1_0_GART_PAGE_START, + amdgpu_gart_map_vram_range(adev, pa, adev->vce.gart_node.start, num_pages, flags, adev->gart.ptr); - adev->vce.gpu_addr = adev->gmc.gart_start + VCE_V1_0_GART_ADDR_START; + adev->vce.gpu_addr = adev->gmc.gart_start + vce_gart_start_offs; if (adev->vce.gpu_addr > max_vcpu_bo_addr) return -EINVAL; @@ -610,7 +607,11 @@ static int vce_v1_0_sw_fini(struct amdgpu_ip_block *ip_block) if (r) return r; - return amdgpu_vce_sw_fini(adev); + r = amdgpu_vce_sw_fini(adev); + + amdgpu_gtt_mgr_free_entries(&adev->mman.gtt_mgr, &adev->vce.gart_node); + + return r; } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 8ea8a6193492f..db149eda62044 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -280,7 +280,7 @@ static int vce_v2_0_stop(struct amdgpu_device *adev) if (vce_v2_0_lmi_clean(adev)) { - DRM_INFO("VCE is not idle \n"); + drm_info(adev_to_drm(adev), "VCE is not idle\n"); return 0; } @@ -289,7 +289,7 @@ static int vce_v2_0_stop(struct amdgpu_device *adev) return -EINVAL; if (vce_v2_0_wait_for_idle(ip_block)) { - DRM_INFO("VCE is busy, Can't set clock gating"); + drm_info(adev_to_drm(adev), "VCE is busy, Can't set clock gating"); return 0; } @@ -481,7 +481,7 @@ static int vce_v2_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } - DRM_INFO("VCE initialized successfully.\n"); + drm_info(adev_to_drm(adev), "VCE initialized successfully.\n"); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 719e9643c43d4..03d79e464f04f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -485,7 +485,7 @@ static int vce_v3_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } - DRM_INFO("VCE initialized successfully.\n"); + drm_info(adev_to_drm(adev), "VCE initialized successfully.\n"); return 0; } @@ -846,7 +846,7 @@ static void vce_v3_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 data = RREG32_SMC(ixCURRENT_PG_STATUS); if (data & CURRENT_PG_STATUS__VCE_PG_STATUS_MASK) { - DRM_INFO("Cannot get clockgating state when VCE is powergated.\n"); + drm_info(adev_to_drm(adev), "Cannot get clockgating state when VCE is powergated.\n"); goto out; } @@ -978,13 +978,13 @@ static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs; adev->vce.ring[i].me = i; } - DRM_INFO("VCE enabled in VM mode\n"); + drm_info(adev_to_drm(adev), "VCE enabled in VM mode\n"); } else { for (i = 0; i < adev->vce.num_rings; i++) { adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs; adev->vce.ring[i].me = i; } - DRM_INFO("VCE enabled in physical mode\n"); + drm_info(adev_to_drm(adev), "VCE enabled in physical mode\n"); } } diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 2d64002bed61f..ee445d8abe474 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -460,7 +460,7 @@ static int vce_v4_0_sw_init(struct amdgpu_ip_block *ip_block) adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw; adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); - DRM_INFO("PSP loading VCE firmware\n"); + drm_info(adev_to_drm(adev), "PSP loading VCE firmware\n"); } else { r = amdgpu_vce_resume(adev); if (r) @@ -536,7 +536,7 @@ static int vce_v4_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } - DRM_INFO("VCE initialized successfully.\n"); + drm_info(adev_to_drm(adev), "VCE initialized successfully.\n"); return 0; } @@ -864,7 +864,7 @@ static void vce_v4_0_set_ring_funcs(struct amdgpu_device *adev) adev->vce.ring[i].funcs = &vce_v4_0_ring_vm_funcs; adev->vce.ring[i].me = i; } - DRM_INFO("VCE enabled in VM mode\n"); + drm_info(adev_to_drm(adev), "VCE enabled in VM mode\n"); } static const struct amdgpu_irq_src_funcs vce_v4_0_irq_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index a316797875a8f..e9d790914761c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -2053,6 +2053,7 @@ static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser, { struct ttm_operation_ctx ctx = { false, false }; struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; + struct amdgpu_device *adev = parser->adev; struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va_mapping *mapping; struct amdgpu_bo *bo; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 8897dcc9c1a0a..e35fae9cdaf66 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -1964,7 +1964,8 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) struct mmsch_v2_0_cmd_end end = { {0} }; struct mmsch_v2_0_init_header *header; uint32_t *init_table = adev->virt.mm_table.cpu_addr; - uint8_t i = 0; + + /* This path only programs VCN instance 0. */ header = (struct mmsch_v2_0_init_header *)init_table; direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; @@ -1983,93 +1984,93 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.inst[0].fw->size + 4); MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), + SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0xFFFFFFFF, 0x00000004); /* mc resume*/ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi); offset = 0; } else { MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), lower_32_bits(adev->vcn.inst->gpu_addr)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), upper_32_bits(adev->vcn.inst->gpu_addr)); offset = size; } MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), + SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), + SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(adev->vcn.inst->gpu_addr + offset)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(adev->vcn.inst->gpu_addr + offset)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), + SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), + SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), + SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), + SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); for (r = 0; r < adev->vcn.inst[0].num_enc_rings; ++r) { ring = &adev->vcn.inst->ring_enc[r]; ring->wptr = 0; MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), + SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), lower_32_bits(ring->gpu_addr)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), + SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), + SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_SIZE), ring->ring_size / 4); } ring = &adev->vcn.inst->ring_dec; ring->wptr = 0; MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), lower_32_bits(ring->gpu_addr)); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, + SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), upper_32_bits(ring->gpu_addr)); /* force RBC into idle state */ @@ -2080,7 +2081,7 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); MMSCH_V2_0_INSERT_DIRECT_WT( - SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); + SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), tmp); /* add end packet */ tmp = sizeof(struct mmsch_v2_0_cmd_end); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index cebee453871c1..006a154511971 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -521,7 +521,9 @@ static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) RREG32_SOC15(VCN, i, mmUVD_STATUS))) vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); - if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) + /* VF doesn't enable interrupt operations for RAS */ + if (!amdgpu_sriov_vf(adev) && + amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN)) amdgpu_irq_put(adev, &vinst->ras_poison_irq, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index d9cf8f0feeb3e..02d5c5af65f23 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1907,6 +1907,7 @@ static int vcn_v3_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, uint64_t addr) { struct ttm_operation_ctx ctx = { false, false }; + struct amdgpu_device *adev = p->adev; struct amdgpu_bo_va_mapping *map; uint32_t *msg, num_buffers; struct amdgpu_bo *bo; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 3ae666522d570..d17219be50f39 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1824,6 +1824,7 @@ static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, uint64_t addr) { struct ttm_operation_ctx ctx = { false, false }; + struct amdgpu_device *adev = p->adev; struct amdgpu_bo_va_mapping *map; uint32_t *msg, num_buffers; struct amdgpu_bo *bo; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index cb7123ec1a5d1..ff3013b97abd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -134,6 +134,21 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) return 0; } +static bool vcn_v4_0_3_is_psp_fw_reset_supported(struct amdgpu_device *adev) +{ + uint32_t fw_ver = adev->psp.sos.fw_version; + uint32_t pgm = (fw_ver >> 8) & 0xFF; + + /* + * FWDEV-159155: PSP SOS FW must be >= 0x0036015f for program 0x01 + * before enabling VCN per-queue reset. + */ + if (pgm == 1) + return fw_ver >= 0x0036015f; + + return true; +} + static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -141,7 +156,9 @@ static int vcn_v4_0_3_late_init(struct amdgpu_ip_block *ip_block) adev->vcn.supported_reset = amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); - if (amdgpu_dpm_reset_vcn_is_supported(adev) && !amdgpu_sriov_vf(adev)) + if (amdgpu_dpm_reset_vcn_is_supported(adev) && + vcn_v4_0_3_is_psp_fw_reset_supported(adev) && + !amdgpu_sriov_vf(adev)) adev->vcn.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; return 0; @@ -847,6 +864,7 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, int inst_idx = vinst->inst; struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; struct amdgpu_ring *ring; int vcn_inst, ret; uint32_t tmp; @@ -951,6 +969,9 @@ static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_vcn_inst *vinst, ring = &adev->vcn.inst[inst_idx].ring_enc[0]; + /* Pause dpg */ + vcn_v4_0_3_pause_dpg_mode(vinst, &state); + /* program the RB_BASE for ring buffer */ WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); @@ -1360,9 +1381,13 @@ static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) int inst_idx = vinst->inst; uint32_t tmp; int vcn_inst; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; vcn_inst = GET_INST(VCN, inst_idx); + /* Unpause dpg */ + vcn_v4_0_3_pause_dpg_mode(vinst, &state); + /* Wait for power status to be 1 */ SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); @@ -1486,6 +1511,39 @@ static int vcn_v4_0_3_stop(struct amdgpu_vcn_inst *vinst) static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, struct dpg_pause_state *new_state) { + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + uint32_t reg_data = 0; + int ret_code; + + /* pause/unpause if state is changed */ + if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { + DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d", + adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); + reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { + ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + + if (!ret_code) { + /* pause DPG */ + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); + + /* wait for ACK */ + SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + } + } else { + /* unpause dpg, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); + } + adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; + } return 0; } @@ -1596,6 +1654,60 @@ static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring) } } +static int vcn_v4_0_3_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + uint32_t wait_seq = 0; + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + + drm_sched_wqueue_stop(&ring->sched); + /* Get the last emitted fence sequence */ + wait_seq = atomic_read(&ring->fence_drv.last_seq); + if (wait_seq) + continue; + + /* if Jobs are still pending after timeout, + * We'll handle them in the bottom helper + */ + amdgpu_fence_wait_polling(ring, wait_seq, adev->video_timeout); + } + + return 0; +} + +static int vcn_v4_0_3_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + int i, r = 0; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + /* Force completion of any remaining jobs */ + amdgpu_fence_driver_force_completion(ring); + + if (ring->use_doorbell) + WREG32_SOC15_OFFSET( + VCN, GET_INST(VCN, inst), + regVCN_JPEG_DB_CTRL, + (ring->pipe ? (ring->pipe - 0x15) : 0), + ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + + drm_sched_wqueue_start(&ring->sched); + + DRM_DEV_DEBUG(adev->dev, "JPEG ring %d (inst %d) restored and sched restarted\n", + i, inst); + } + return 0; +} + static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) @@ -1604,7 +1716,19 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, int vcn_inst; struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + bool pg_state = false; + + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); + mutex_lock(&adev->jpeg.jpeg_pg_lock); + /* Ensure JPEG is powered on during reset if currently gated */ + if (adev->jpeg.cur_state == AMD_PG_STATE_GATE) { + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_UNGATE); + pg_state = true; + } + vcn_v4_0_3_reset_jpeg_pre_helper(adev, ring->me); amdgpu_ring_reset_helper_begin(ring, timedout_fence); vcn_inst = GET_INST(VCN, ring->me); @@ -1612,7 +1736,12 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, if (r) { DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); - return r; + /* Restore JPEG power gating state if it was originally gated */ + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; } /* This flag is not set for VF, assumed to be disabled always */ @@ -1621,7 +1750,25 @@ static int vcn_v4_0_3_ring_reset(struct amdgpu_ring *ring, vcn_v4_0_3_hw_init_inst(vinst); vcn_v4_0_3_start_dpg_mode(vinst, adev->vcn.inst[ring->me].indirect_sram); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + if (r) { + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; + } + + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + r = vcn_v4_0_3_reset_jpeg_post_helper(adev, ring->me); + +unlock: + mutex_unlock(&vinst->engine_reset_mutex); + + return r; } static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 0202df5db1e12..6109124f852e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -174,6 +174,10 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); fw_shared->sq.is_enabled = 1; + fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG); + fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ? + AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU; + if (amdgpu_vcnfw_log) amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 8bd457dea4cff..c28c6aff17aaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1301,6 +1301,59 @@ static void vcn_v5_0_1_unified_ring_set_wptr(struct amdgpu_ring *ring) } } +static int vcn_v5_0_1_reset_jpeg_pre_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + uint32_t wait_seq = 0; + int i; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + + drm_sched_wqueue_stop(&ring->sched); + wait_seq = atomic_read(&ring->fence_drv.last_seq); + if (wait_seq) + continue; + + /* if Jobs are still pending after timeout, + * We'll handle them in the bottom helper + */ + amdgpu_fence_wait_polling(ring, wait_seq, adev->video_timeout); + } + + return 0; +} + +static int vcn_v5_0_1_reset_jpeg_post_helper(struct amdgpu_device *adev, int inst) +{ + struct amdgpu_ring *ring; + int i, r = 0; + + for (i = 0; i < adev->jpeg.num_jpeg_rings; ++i) { + ring = &adev->jpeg.inst[inst].ring_dec[i]; + /* Force completion of any remaining jobs */ + amdgpu_fence_driver_force_completion(ring); + + if (ring->use_doorbell) + WREG32_SOC15_OFFSET( + VCN, GET_INST(VCN, inst), + regVCN_JPEG_DB_CTRL, + (ring->pipe ? (ring->pipe - 0x15) : 0), + ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT | + VCN_JPEG_DB_CTRL__EN_MASK); + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + + drm_sched_wqueue_start(&ring->sched); + + DRM_DEV_DEBUG(adev->dev, "JPEG ring %d (inst %d) restored and sched restarted\n", + i, inst); + } + return 0; +} + static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, unsigned int vmid, struct amdgpu_fence *timedout_fence) @@ -1309,6 +1362,18 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, int vcn_inst; struct amdgpu_device *adev = ring->adev; struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[ring->me]; + bool pg_state = false; + + /* take the vcn reset mutex here because resetting VCN will reset jpeg as well */ + mutex_lock(&vinst->engine_reset_mutex); + vcn_v5_0_1_reset_jpeg_pre_helper(adev, ring->me); + mutex_lock(&adev->jpeg.jpeg_pg_lock); + /* Ensure JPEG is powered on during reset if currently gated */ + if (adev->jpeg.cur_state == AMD_PG_STATE_GATE) { + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_UNGATE); + pg_state = true; + } amdgpu_ring_reset_helper_begin(ring, timedout_fence); @@ -1317,13 +1382,37 @@ static int vcn_v5_0_1_ring_reset(struct amdgpu_ring *ring, if (r) { DRM_DEV_ERROR(adev->dev, "VCN reset fail : %d\n", r); - return r; + /* Restore JPEG power gating state if it was originally gated */ + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; } vcn_v5_0_1_hw_init_inst(adev, ring->me); vcn_v5_0_1_start_dpg_mode(vinst, vinst->indirect_sram); - return amdgpu_ring_reset_helper_end(ring, timedout_fence); + r = amdgpu_ring_reset_helper_end(ring, timedout_fence); + if (r) { + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + goto unlock; + } + + if (pg_state) + amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_JPEG, + AMD_PG_STATE_GATE); + mutex_unlock(&adev->jpeg.jpeg_pg_lock); + + r = vcn_v5_0_1_reset_jpeg_post_helper(adev, ring->me); + +unlock: + mutex_unlock(&vinst->engine_reset_mutex); + + return r; } static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c new file mode 100644 index 0000000000000..c3d3cc0230580 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.c @@ -0,0 +1,1219 @@ +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "amdgpu_vcn.h" +#include "amdgpu_pm.h" +#include "soc15.h" +#include "soc15d.h" +#include "soc15_hw_ip.h" +#include "vcn_v2_0.h" +#include "vcn_v4_0_3.h" + +#include "vcn/vcn_5_0_0_offset.h" +#include "vcn/vcn_5_0_0_sh_mask.h" +#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h" +#include "vcn_v5_0_0.h" +#include "vcn_v5_0_1.h" +#include "vcn_v5_0_2.h" + +#include + +static void vcn_v5_0_2_set_unified_ring_funcs(struct amdgpu_device *adev); +static void vcn_v5_0_2_set_irq_funcs(struct amdgpu_device *adev); +static int vcn_v5_0_2_set_pg_state(struct amdgpu_vcn_inst *vinst, + enum amd_powergating_state state); +static void vcn_v5_0_2_unified_ring_set_wptr(struct amdgpu_ring *ring); + +/** + * vcn_v5_0_2_early_init - set function pointers and load microcode + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Set ring and irq function pointers + * Load microcode from filesystem + */ +static int vcn_v5_0_2_early_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, r; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) + /* re-use enc ring as unified ring */ + adev->vcn.inst[i].num_enc_rings = 1; + + vcn_v5_0_2_set_unified_ring_funcs(adev); + vcn_v5_0_2_set_irq_funcs(adev); + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + adev->vcn.inst[i].set_pg_state = vcn_v5_0_2_set_pg_state; + + r = amdgpu_vcn_early_init(adev, i); + if (r) + return r; + } + + return 0; +} + +static void vcn_v5_0_2_fw_shared_init(struct amdgpu_device *adev, int inst_idx) +{ + struct amdgpu_vcn5_fw_shared *fw_shared; + + fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + + if (fw_shared->sq.is_enabled) + return; + fw_shared->present_flag_0 = + cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE); + fw_shared->sq.is_enabled = 1; + + if (amdgpu_vcnfw_log) + amdgpu_vcn_fwlog_init(&adev->vcn.inst[inst_idx]); +} + +/** + * vcn_v5_0_2_sw_init - sw init for VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Load firmware and sw initialization + */ +static int vcn_v5_0_2_sw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, r, vcn_inst; + + /* VCN UNIFIED TRAP */ + r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_VCN, + VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst->irq); + if (r) + return r; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + vcn_inst = GET_INST(VCN, i); + + r = amdgpu_vcn_sw_init(adev, i); + if (r) + return r; + + amdgpu_vcn_setup_ucode(adev, i); + + r = amdgpu_vcn_resume(adev, i); + if (r) + return r; + + ring = &adev->vcn.inst[i].ring_enc[0]; + ring->use_doorbell = true; + + ring->doorbell_index = + (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 32 * vcn_inst; + + ring->vm_hub = AMDGPU_MMHUB0(adev->vcn.inst[i].aid_id); + sprintf(ring->name, "vcn_unified_%d", adev->vcn.inst[i].aid_id); + + r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, + AMDGPU_RING_PRIO_DEFAULT, &adev->vcn.inst[i].sched_score); + if (r) + return r; + + vcn_v5_0_2_fw_shared_init(adev, i); + } + + /* TODO: Add queue reset mask when FW fully supports it */ + adev->vcn.supported_reset = + amdgpu_get_soft_full_reset_mask(&adev->vcn.inst[0].ring_enc[0]); + + return amdgpu_vcn_sysfs_reset_mask_init(adev); +} + +/** + * vcn_v5_0_2_sw_fini - sw fini for VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * VCN suspend and free up sw allocation + */ +static int vcn_v5_0_2_sw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, r, idx; + + if (drm_dev_enter(adev_to_drm(adev), &idx)) { + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + struct amdgpu_vcn5_fw_shared *fw_shared; + + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->present_flag_0 = 0; + fw_shared->sq.is_enabled = 0; + } + + drm_dev_exit(idx); + } + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + r = amdgpu_vcn_suspend(adev, i); + if (r) + return r; + } + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) + amdgpu_vcn_sw_fini(adev, i); + + amdgpu_vcn_sysfs_reset_mask_fini(adev); + + kfree(adev->vcn.ip_dump); //TODO check + + return 0; +} + +/** + * vcn_v5_0_2_hw_init - start and test VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Initialize the hardware, boot up the VCPU and do some testing + */ +static int vcn_v5_0_2_hw_init(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_ring *ring; + int i, r, vcn_inst; + uint32_t tmp; + + if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x200) + adev->vcn.caps |= AMDGPU_VCN_CAPS(RRMT_ENABLED); + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + vcn_inst = GET_INST(VCN, i); + ring = &adev->vcn.inst[i].ring_enc[0]; + + /* Remove Video Tiles antihang mechanism */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); + tmp &= (~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); + + if (ring->use_doorbell) + adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, + ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + + 11 * vcn_inst), + adev->vcn.inst[i].aid_id); + + /* Re-init fw_shared, if required */ + vcn_v5_0_2_fw_shared_init(adev, i); + + r = amdgpu_ring_test_helper(ring); + if (r) + return r; + } + + return 0; +} + +/** + * vcn_v5_0_2_hw_fini - stop the hardware block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Stop the VCN block, mark ring as not ready any more + */ +static int vcn_v5_0_2_hw_fini(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; + + cancel_delayed_work_sync(&adev->vcn.inst[i].idle_work); + if (vinst->cur_state != AMD_PG_STATE_GATE) + vinst->set_pg_state(vinst, AMD_PG_STATE_GATE); + } + + return 0; +} + +/** + * vcn_v5_0_2_suspend - suspend VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * HW fini and suspend VCN block + */ +static int vcn_v5_0_2_suspend(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r, i; + + r = vcn_v5_0_2_hw_fini(ip_block); + if (r) + return r; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + r = amdgpu_vcn_suspend(ip_block->adev, i); + if (r) + return r; + } + + return r; +} + +/** + * vcn_v5_0_2_resume - resume VCN block + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Resume firmware and hw init VCN block + */ +static int vcn_v5_0_2_resume(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int r, i; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; + + if (amdgpu_in_reset(adev)) + vinst->cur_state = AMD_PG_STATE_GATE; + + r = amdgpu_vcn_resume(ip_block->adev, i); + if (r) + return r; + } + + r = vcn_v5_0_2_hw_init(ip_block); + + return r; +} + +/** + * vcn_v5_0_2_mc_resume - memory controller programming + * + * @vinst: VCN instance + * + * Let the VCN memory controller know it's offsets + */ +static void vcn_v5_0_2_mc_resume(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int inst = vinst->inst; + uint32_t offset, size, vcn_inst; + const struct common_firmware_header *hdr; + + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst].fw->data; + size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + + vcn_inst = GET_INST(VCN, inst); + /* cache window 0: fw */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, 0); + offset = 0; + } else { + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].gpu_addr)); + offset = size; + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET0, + AMDGPU_UVD_FIRMWARE_OFFSET >> 3); + } + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE0, size); + + /* cache window 1: stack */ + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); + + /* cache window 2: context */ + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET2, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); + + /* non-cache window */ + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, + lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, + upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_OFFSET0, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_NONCACHE_SIZE0, + AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared))); +} + +/** + * vcn_v5_0_2_mc_resume_dpg_mode - memory controller programming for dpg mode + * + * @vinst: VCN instance + * @indirect: indirectly write sram + * + * Let the VCN memory controller know it's offsets with dpg mode + */ +static void vcn_v5_0_2_mc_resume_dpg_mode(struct amdgpu_vcn_inst *vinst, + bool indirect) +{ + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + uint32_t offset, size; + const struct common_firmware_header *hdr; + + hdr = (const struct common_firmware_header *)adev->vcn.inst[inst_idx].fw->data; + size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); + + /* cache window 0: fw */ + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + if (!indirect) { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + + inst_idx].tmr_mc_addr_lo), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + + inst_idx].tmr_mc_addr_hi), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); + } else { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); + } + offset = 0; + } else { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); + offset = size; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET0), + AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); + } + + if (!indirect) + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect); + else + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); + + /* cache window 1: stack */ + if (!indirect) { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); + } else { + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); + } + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); + + /* cache window 2: context */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + + AMDGPU_VCN_STACK_SIZE), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + + AMDGPU_VCN_STACK_SIZE), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); + + /* non-cache window */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), + lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), + upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_NONCACHE_SIZE0), + AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn5_fw_shared)), 0, indirect); + + /* VCN global tiling registers */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); +} + +/** + * vcn_v5_0_2_disable_clock_gating - disable VCN clock gating + * + * @vinst: VCN instance + * + * Disable clock gating for VCN block + */ +static void vcn_v5_0_2_disable_clock_gating(struct amdgpu_vcn_inst *vinst) +{ +} + +/** + * vcn_v5_0_2_enable_clock_gating - enable VCN clock gating + * + * @vinst: VCN instance + * + * Enable clock gating for VCN block + */ +static void vcn_v5_0_2_enable_clock_gating(struct amdgpu_vcn_inst *vinst) +{ +} + +/** + * vcn_v5_0_2_pause_dpg_mode - VCN pause with dpg mode + * + * @vinst: VCN instance + * @new_state: pause state + * + * Pause dpg mode for VCN block + */ +static int vcn_v5_0_2_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, + struct dpg_pause_state *new_state) +{ + struct amdgpu_device *adev = vinst->adev; + uint32_t reg_data = 0; + int vcn_inst; + + vcn_inst = GET_INST(VCN, vinst->inst); + + /* pause/unpause if state is changed */ + if (vinst->pause_state.fw_based != new_state->fw_based) { + DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d %s\n", + vinst->pause_state.fw_based, new_state->fw_based, + new_state->fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE"); + reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) & + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { + /* pause DPG */ + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); + + /* wait for ACK */ + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); + } else { + /* unpause DPG, no need to wait */ + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); + } + vinst->pause_state.fw_based = new_state->fw_based; + } + + return 0; +} + +/** + * vcn_v5_0_2_start_dpg_mode - VCN start with dpg mode + * + * @vinst: VCN instance + * @indirect: indirectly write sram + * + * Start VCN block with dpg mode + */ +static int vcn_v5_0_2_start_dpg_mode(struct amdgpu_vcn_inst *vinst, + bool indirect) +{ + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + struct amdgpu_vcn5_fw_shared *fw_shared = + adev->vcn.inst[inst_idx].fw_shared.cpu_addr; + struct amdgpu_ring *ring; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; + int vcn_inst, ret; + uint32_t tmp; + + vcn_inst = GET_INST(VCN, inst_idx); + + /* disable register anti-hang mechanism */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 1, + ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + + /* enable dynamic power gating mode */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS); + tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_POWER_STATUS, tmp); + + if (indirect) { + adev->vcn.inst[inst_idx].dpg_sram_curr_addr = + (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; + /* Use dummy register 0xDEADBEEF passing AID selection to PSP FW */ + WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, + adev->vcn.inst[inst_idx].aid_id, 0, true); + } + + /* enable VCPU clock */ + tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); + tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); + + /* disable master interrupt */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_MASTINT_EN), 0, 0, indirect); + + /* setup regUVD_LMI_CTRL */ + tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__REQ_MODE_MASK | + UVD_LMI_CTRL__CRC_RESET_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | + 0x00100000L); + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_CTRL), tmp, 0, indirect); + + vcn_v5_0_2_mc_resume_dpg_mode(vinst, indirect); + + tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); + tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); + + /* enable LMI MC and UMC channels */ + tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT; + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_LMI_CTRL2), tmp, 0, indirect); + + /* enable master interrupt */ + WREG32_SOC24_DPG_MODE(inst_idx, SOC24_DPG_MODE_OFFSET( + VCN, 0, regUVD_MASTINT_EN), + UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); + + if (indirect) { + ret = amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); + if (ret) { + dev_err(adev->dev, "vcn sram load failed %d\n", ret); + return ret; + } + } + + /* resetting ring, fw should not check RB ring */ + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; + + /* Pause dpg */ + vcn_v5_0_2_pause_dpg_mode(vinst, &state); + + ring = &adev->vcn.inst[inst_idx].ring_enc[0]; + + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, lower_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / sizeof(uint32_t)); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); + + ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + /* resetting done, fw can check RB ring */ + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); + + WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + /* Read DB_CTRL to flush the write DB_CTRL command. */ + RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); + + return 0; +} + +/** + * vcn_v5_0_2_start - VCN start + * + * @vinst: VCN instance + * + * Start VCN block + */ +static int vcn_v5_0_2_start(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int i = vinst->inst; + struct amdgpu_vcn5_fw_shared *fw_shared; + struct amdgpu_ring *ring; + uint32_t tmp; + int j, k, r, vcn_inst; + + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) + return vcn_v5_0_2_start_dpg_mode(vinst, adev->vcn.inst[i].indirect_sram); + + vcn_inst = GET_INST(VCN, i); + + /* set VCN status busy */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS) | UVD_STATUS__UVD_BUSY; + WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, tmp); + + /* enable VCPU clock */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); + + /* disable master interrupt */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), 0, + ~UVD_MASTINT_EN__VCPU_EN_MASK); + + /* enable LMI MC and UMC channels */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_LMI_CTRL2), 0, + ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); + + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); + tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; + tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); + + /* setup regUVD_LMI_CTRL */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL); + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL, tmp | + UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | + UVD_LMI_CTRL__MASK_MC_URGENT_MASK | + UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | + UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); + + vcn_v5_0_2_mc_resume(vinst); + + /* VCN global tiling registers */ + WREG32_SOC15(VCN, vcn_inst, regUVD_GFX10_ADDR_CONFIG, + adev->gfx.config.gb_addr_config); + + /* unblock VCPU register access */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), 0, + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); + + /* release VCPU reset to boot */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + + for (j = 0; j < 10; ++j) { + uint32_t status; + + for (k = 0; k < 100; ++k) { + status = RREG32_SOC15(VCN, vcn_inst, regUVD_STATUS); + if (status & 2) + break; + mdelay(1000); + if (amdgpu_emu_mode == 1) + msleep(520); + } + + if (amdgpu_emu_mode == 1) { + r = -1; + if (status & 2) { + r = 0; + break; + } + } else { + r = 0; + if (status & 2) + break; + + dev_err(adev->dev, + "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i); + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__BLK_RST_MASK, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + mdelay(10); + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + + mdelay(10); + r = -1; + } + } + + if (r) { + dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i); + return r; + } + + /* enable master interrupt */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_MASTINT_EN), + UVD_MASTINT_EN__VCPU_EN_MASK, + ~UVD_MASTINT_EN__VCPU_EN_MASK); + + /* clear the busy bit of VCN_STATUS */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_STATUS), 0, + ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); + + ring = &adev->vcn.inst[i].ring_enc[0]; + + WREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL, + ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT | + VCN_RB1_DB_CTRL__EN_MASK); + + /* Read DB_CTRL to flush the write DB_CTRL command. */ + RREG32_SOC15(VCN, vcn_inst, regVCN_RB1_DB_CTRL); + + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_LO, ring->gpu_addr); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_SIZE, ring->ring_size / 4); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK); + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET; + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR, 0); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, 0); + + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_RPTR); + WREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR, tmp); + ring->wptr = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); + + tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); + tmp |= VCN_RB_ENABLE__RB1_EN_MASK; + WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); + fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF); + + return 0; +} + +/** + * vcn_v5_0_2_stop_dpg_mode - VCN stop with dpg mode + * + * @vinst: VCN instance + * + * Stop VCN block with dpg mode + */ +static void vcn_v5_0_2_stop_dpg_mode(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int inst_idx = vinst->inst; + uint32_t tmp; + int vcn_inst; + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; + + vcn_inst = GET_INST(VCN, inst_idx); + + /* Unpause dpg */ + vcn_v5_0_2_pause_dpg_mode(vinst, &state); + + /* Wait for power status to be 1 */ + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); + + /* wait for read ptr to be equal to write ptr */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_RB_WPTR); + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); + + /* disable dynamic power gating mode */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_POWER_STATUS), 0, + ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); +} + +/** + * vcn_v5_0_2_stop - VCN stop + * + * @vinst: VCN instance + * + * Stop VCN block + */ +static int vcn_v5_0_2_stop(struct amdgpu_vcn_inst *vinst) +{ + struct amdgpu_device *adev = vinst->adev; + int i = vinst->inst; + struct amdgpu_vcn5_fw_shared *fw_shared; + uint32_t tmp; + int r = 0, vcn_inst; + + vcn_inst = GET_INST(VCN, i); + + fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr; + fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF; + + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { + vcn_v5_0_2_stop_dpg_mode(vinst); + return 0; + } + + /* wait for vcn idle */ + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); + if (r) + return r; + + tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | + UVD_LMI_STATUS__READ_CLEAN_MASK | + UVD_LMI_STATUS__WRITE_CLEAN_MASK | + UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); + if (r) + return r; + + /* disable LMI UMC channel */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2); + tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_CTRL2, tmp); + tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | + UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; + r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); + if (r) + return r; + + /* block VCPU register access */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_RB_ARB_CTRL), + UVD_RB_ARB_CTRL__VCPU_DIS_MASK, + ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); + + /* reset VCPU */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), + UVD_VCPU_CNTL__BLK_RST_MASK, + ~UVD_VCPU_CNTL__BLK_RST_MASK); + + /* disable VCPU clock */ + WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, + ~(UVD_VCPU_CNTL__CLK_EN_MASK)); + + /* apply soft reset */ + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); + tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); + tmp = RREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET); + tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; + WREG32_SOC15(VCN, vcn_inst, regUVD_SOFT_RESET, tmp); + + /* clear status */ + WREG32_SOC15(VCN, vcn_inst, regUVD_STATUS, 0); + + return 0; +} + +/** + * vcn_v5_0_2_unified_ring_get_rptr - get unified read pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware unified read pointer + */ +static uint64_t vcn_v5_0_2_unified_ring_get_rptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); +} + +/** + * vcn_v5_0_2_unified_ring_get_wptr - get unified write pointer + * + * @ring: amdgpu_ring pointer + * + * Returns the current hardware unified write pointer + */ +static uint64_t vcn_v5_0_2_unified_ring_get_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + if (ring->use_doorbell) + return *ring->wptr_cpu_addr; + else + return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR); +} + +/** + * vcn_v5_0_2_unified_ring_set_wptr - set enc write pointer + * + * @ring: amdgpu_ring pointer + * + * Commits the enc write pointer to the hardware + */ +static void vcn_v5_0_2_unified_ring_set_wptr(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + + if (ring != &adev->vcn.inst[ring->me].ring_enc[0]) + DRM_ERROR("wrong ring id is identified in %s", __func__); + + if (ring->use_doorbell) { + *ring->wptr_cpu_addr = lower_32_bits(ring->wptr); + WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); + } else { + WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, + lower_32_bits(ring->wptr)); + } +} + +static const struct amdgpu_ring_funcs vcn_v5_0_2_unified_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_ENC, + .align_mask = 0x3f, + .nop = VCN_ENC_CMD_NO_OP, + .get_rptr = vcn_v5_0_2_unified_ring_get_rptr, + .get_wptr = vcn_v5_0_2_unified_ring_get_wptr, + .set_wptr = vcn_v5_0_2_unified_ring_set_wptr, + .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + + 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ + 5 + + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ + 1, /* vcn_v2_0_enc_ring_insert_end */ + .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ + .emit_ib = vcn_v2_0_enc_ring_emit_ib, + .emit_fence = vcn_v2_0_enc_ring_emit_fence, + .emit_vm_flush = vcn_v4_0_3_enc_ring_emit_vm_flush, + .emit_hdp_flush = vcn_v4_0_3_ring_emit_hdp_flush, + .test_ring = amdgpu_vcn_enc_ring_test_ring, + .test_ib = amdgpu_vcn_unified_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, + .insert_end = vcn_v2_0_enc_ring_insert_end, + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_vcn_ring_begin_use, + .end_use = amdgpu_vcn_ring_end_use, + .emit_wreg = vcn_v4_0_3_enc_ring_emit_wreg, + .emit_reg_wait = vcn_v4_0_3_enc_ring_emit_reg_wait, + .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, +}; + +/** + * vcn_v5_0_2_set_unified_ring_funcs - set unified ring functions + * + * @adev: amdgpu_device pointer + * + * Set unified ring functions + */ +static void vcn_v5_0_2_set_unified_ring_funcs(struct amdgpu_device *adev) +{ + int i, vcn_inst; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v5_0_2_unified_ring_vm_funcs; + adev->vcn.inst[i].ring_enc[0].me = i; + vcn_inst = GET_INST(VCN, i); + adev->vcn.inst[i].aid_id = vcn_inst / adev->vcn.num_inst_per_aid; + } +} + +/** + * vcn_v5_0_2_is_idle - check VCN block is idle + * + * @ip_block: Pointer to the amdgpu_ip_block structure + * + * Check whether VCN block is idle + */ +static bool vcn_v5_0_2_is_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, ret = 1; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) + ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); + + return ret; +} + +/** + * vcn_v5_0_2_wait_for_idle - wait for VCN block idle + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * + * Wait for VCN block idle + */ +static int vcn_v5_0_2_wait_for_idle(struct amdgpu_ip_block *ip_block) +{ + struct amdgpu_device *adev = ip_block->adev; + int i, ret = 0; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, + UVD_STATUS__IDLE); + if (ret) + return ret; + } + + return ret; +} + +/** + * vcn_v5_0_2_set_clockgating_state - set VCN block clockgating state + * + * @ip_block: Pointer to the amdgpu_ip_block for this hw instance. + * @state: clock gating state + * + * Set VCN block clockgating state + */ +static int vcn_v5_0_2_set_clockgating_state(struct amdgpu_ip_block *ip_block, + enum amd_clockgating_state state) +{ + struct amdgpu_device *adev = ip_block->adev; + bool enable = state == AMD_CG_STATE_GATE; + int i; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + struct amdgpu_vcn_inst *vinst = &adev->vcn.inst[i]; + + if (enable) { + if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) + return -EBUSY; + vcn_v5_0_2_enable_clock_gating(vinst); + } else { + vcn_v5_0_2_disable_clock_gating(vinst); + } + } + + return 0; +} + +static int vcn_v5_0_2_set_pg_state(struct amdgpu_vcn_inst *vinst, + enum amd_powergating_state state) +{ + int ret = 0; + + if (state == vinst->cur_state) + return 0; + + if (state == AMD_PG_STATE_GATE) + ret = vcn_v5_0_2_stop(vinst); + else + ret = vcn_v5_0_2_start(vinst); + + if (!ret) + vinst->cur_state = state; + + return ret; +} + +/** + * vcn_v5_0_2_process_interrupt - process VCN block interrupt + * + * @adev: amdgpu_device pointer + * @source: interrupt sources + * @entry: interrupt entry from clients and sources + * + * Process VCN block interrupt + */ +static int vcn_v5_0_2_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + uint32_t i, inst; + + i = node_id_to_phys_map[entry->node_id]; + + DRM_DEV_DEBUG(adev->dev, "IH: VCN TRAP\n"); + + for (inst = 0; inst < adev->vcn.num_vcn_inst; ++inst) + if (adev->vcn.inst[inst].aid_id == i) + break; + + if (inst >= adev->vcn.num_vcn_inst) { + dev_WARN_ONCE(adev->dev, 1, + "Interrupt received for unknown VCN instance %d", + entry->node_id); + return 0; + } + + switch (entry->src_id) { + case VCN_5_0__SRCID__UVD_ENC_GENERAL_PURPOSE: + amdgpu_fence_process(&adev->vcn.inst[inst].ring_enc[0]); + break; + default: + DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n", + entry->src_id, entry->src_data[0]); + break; + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs vcn_v5_0_2_irq_funcs = { + .process = vcn_v5_0_2_process_interrupt, +}; + +/** + * vcn_v5_0_2_set_irq_funcs - set VCN block interrupt irq functions + * + * @adev: amdgpu_device pointer + * + * Set VCN block interrupt irq functions + */ +static void vcn_v5_0_2_set_irq_funcs(struct amdgpu_device *adev) +{ + int i; + + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) + adev->vcn.inst->irq.num_types++; + adev->vcn.inst->irq.funcs = &vcn_v5_0_2_irq_funcs; +} + +static const struct amd_ip_funcs vcn_v5_0_2_ip_funcs = { + .name = "vcn_v5_0_2", + .early_init = vcn_v5_0_2_early_init, + .late_init = NULL, + .sw_init = vcn_v5_0_2_sw_init, + .sw_fini = vcn_v5_0_2_sw_fini, + .hw_init = vcn_v5_0_2_hw_init, + .hw_fini = vcn_v5_0_2_hw_fini, + .suspend = vcn_v5_0_2_suspend, + .resume = vcn_v5_0_2_resume, + .is_idle = vcn_v5_0_2_is_idle, + .wait_for_idle = vcn_v5_0_2_wait_for_idle, + .check_soft_reset = NULL, + .pre_soft_reset = NULL, + .soft_reset = NULL, + .post_soft_reset = NULL, + .set_clockgating_state = vcn_v5_0_2_set_clockgating_state, + .set_powergating_state = vcn_set_powergating_state, +}; + +const struct amdgpu_ip_block_version vcn_v5_0_2_ip_block = { + .type = AMD_IP_BLOCK_TYPE_VCN, + .major = 5, + .minor = 0, + .rev = 2, + .funcs = &vcn_v5_0_2_ip_funcs, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h new file mode 100644 index 0000000000000..461bdda91eb60 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_2.h @@ -0,0 +1,29 @@ +/* + * Copyright 2025-2026 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __VCN_v5_0_2_H__ +#define __VCN_v5_0_2_H__ + +extern const struct amdgpu_ip_block_version vcn_v5_0_2_ip_block; + +#endif /* __VCN_v5_0_2_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index a611a73451250..a256320b92f33 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -299,11 +299,11 @@ static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32_NO_KIQ(mmPCIE_INDEX, reg); (void)RREG32_NO_KIQ(mmPCIE_INDEX); r = RREG32_NO_KIQ(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); return r; } @@ -311,12 +311,12 @@ static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->pcie_idx_lock, flags); + spin_lock_irqsave(&adev->reg.pcie.lock, flags); WREG32_NO_KIQ(mmPCIE_INDEX, reg); (void)RREG32_NO_KIQ(mmPCIE_INDEX); WREG32_NO_KIQ(mmPCIE_DATA, v); (void)RREG32_NO_KIQ(mmPCIE_DATA); - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); } static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) @@ -324,10 +324,10 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -335,10 +335,10 @@ static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); WREG32_NO_KIQ(mmSMC_IND_DATA_11, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } /* smu_8_0_d.h */ @@ -350,10 +350,10 @@ static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmMP0PUB_IND_INDEX, (reg)); r = RREG32(mmMP0PUB_IND_DATA); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return r; } @@ -361,10 +361,10 @@ static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmMP0PUB_IND_INDEX, (reg)); WREG32(mmMP0PUB_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); } static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) @@ -372,10 +372,10 @@ static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); r = RREG32(mmUVD_CTX_DATA); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); return r; } @@ -383,10 +383,10 @@ static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); + spin_lock_irqsave(&adev->reg.uvd_ctx.lock, flags); WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); WREG32(mmUVD_CTX_DATA, (v)); - spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.uvd_ctx.lock, flags); } static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) @@ -394,10 +394,10 @@ static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); r = RREG32(mmDIDT_IND_DATA); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); return r; } @@ -405,10 +405,10 @@ static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->didt_idx_lock, flags); + spin_lock_irqsave(&adev->reg.didt.lock, flags); WREG32(mmDIDT_IND_INDEX, (reg)); WREG32(mmDIDT_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->didt_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.didt.lock, flags); } static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) @@ -416,10 +416,10 @@ static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) unsigned long flags; u32 r; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32(mmGC_CAC_IND_INDEX, (reg)); r = RREG32(mmGC_CAC_IND_DATA); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); return r; } @@ -427,10 +427,10 @@ static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) { unsigned long flags; - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); WREG32(mmGC_CAC_IND_INDEX, (reg)); WREG32(mmGC_CAC_IND_DATA, (v)); - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); } @@ -649,7 +649,7 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, dw_ptr = (u32 *)bios; length_dw = ALIGN(length_bytes, 4) / 4; /* take the smc lock since we are using the smc index */ - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); /* set rom index to 0 */ WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX); WREG32(mmSMC_IND_DATA_11, 0); @@ -657,7 +657,7 @@ static bool vi_read_bios_from_rom(struct amdgpu_device *adev, WREG32(mmSMC_IND_INDEX_11, ixROM_DATA); for (i = 0; i < length_dw; i++) dw_ptr[i] = RREG32(mmSMC_IND_DATA_11); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return true; } @@ -1424,10 +1424,6 @@ static bool vi_need_reset_on_init(struct amdgpu_device *adev) return false; } -static void vi_pre_asic_init(struct amdgpu_device *adev) -{ -} - static const struct amdgpu_asic_funcs vi_asic_funcs = { .read_disabled_bios = &vi_read_disabled_bios, @@ -1447,7 +1443,6 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = .need_reset_on_init = &vi_need_reset_on_init, .get_pcie_replay_count = &vi_get_pcie_replay_count, .supports_baco = &vi_asic_supports_baco, - .pre_asic_init = &vi_pre_asic_init, .query_video_codecs = &vi_query_video_codecs, }; @@ -1459,20 +1454,20 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; if (adev->flags & AMD_IS_APU) { - adev->smc_rreg = &cz_smc_rreg; - adev->smc_wreg = &cz_smc_wreg; + adev->reg.smc.rreg = cz_smc_rreg; + adev->reg.smc.wreg = cz_smc_wreg; } else { - adev->smc_rreg = &vi_smc_rreg; - adev->smc_wreg = &vi_smc_wreg; + adev->reg.smc.rreg = vi_smc_rreg; + adev->reg.smc.wreg = vi_smc_wreg; } - adev->pcie_rreg = &vi_pcie_rreg; - adev->pcie_wreg = &vi_pcie_wreg; - adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg; - adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg; - adev->didt_rreg = &vi_didt_rreg; - adev->didt_wreg = &vi_didt_wreg; - adev->gc_cac_rreg = &vi_gc_cac_rreg; - adev->gc_cac_wreg = &vi_gc_cac_wreg; + adev->reg.pcie.rreg = &vi_pcie_rreg; + adev->reg.pcie.wreg = &vi_pcie_wreg; + adev->reg.uvd_ctx.rreg = &vi_uvd_ctx_rreg; + adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; + adev->reg.didt.rreg = &vi_didt_rreg; + adev->reg.didt.wreg = &vi_didt_wreg; + adev->reg.gc_cac.rreg = &vi_gc_cac_rreg; + adev->reg.gc_cac.wreg = &vi_gc_cac_wreg; adev->asic_funcs = &vi_asic_funcs; diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile new file mode 100644 index 0000000000000..9af8d03f72b00 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: MIT +amdkcl-y += main.o kcl_common.o + +amdkcl-y += kcl_kernel_params.o +amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o + +amdkcl-y += kcl_ioctl.o \ + kcl_io.o kcl_security.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ + kcl_fence.o kcl_drm_cache.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ + kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ + kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ + kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_dp_helper.o kcl_drm_prime.o \ + kcl_drm_vblank.o kcl_drm_dp_mst_topology.o kcl_drm_syncobj.o kcl_drm_client_event.o \ + kcl_scatterlist.o kcl_kfifo.o kcl_cec_adap.o kcl_drm_hdcp.o kcl_drm_drv.o \ + kcl_dma_fence_array.o kcl_dma_fence_unwrap.o kcl_drm_probe_helper.o kcl_i2c_core_base.o \ + kcl_mempool.o + +amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o +amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_file.o +amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o +amdkcl-$(CONFIG_AMD_WBRF) += kcl_wbrf.o +CFLAGS_kcl_fence.o := -I$(src) + +ccflags-y += \ + -include $(src)/../dkms/config/config.h \ + -include $(src)/kcl_common.h + +ccflags-y += -DHAVE_CONFIG_H + +obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files new file mode 100644 index 0000000000000..64e285805c292 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -0,0 +1 @@ +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_exec.c drm_buddy.c" diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c new file mode 100644 index 0000000000000..554bebabd4adb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/****************************************************************************** + * + * Module Name: tbxface - ACPI table-oriented external interfaces + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#include +#include + +#ifndef HAVE_ACPI_PUT_TABLE +amdkcl_dummy_symbol(acpi_put_table, void, return, + struct acpi_table_header *table) +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c new file mode 100644 index 0000000000000..2b0c29936bc96 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -0,0 +1,75 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_BITMAP_FUNCS + +#include +#include +#include + +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags) +{ + return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), + flags); +} +EXPORT_SYMBOL(kcl_bitmap_alloc); + +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags) +{ + return kcl_bitmap_alloc(nbits, flags | __GFP_ZERO); +} +EXPORT_SYMBOL(kcl_bitmap_zalloc); + +void kcl_bitmap_free(const unsigned long *bitmap) +{ + kfree(bitmap); +} +EXPORT_SYMBOL(kcl_bitmap_free); +#endif /* HAVE_BITMAP_FUNCS */ + +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +/** + * kcl_bitmap_to_arr32 - copy the contents of bitmap to a u32 array of bits + * @buf: array of u32 (in host byte order), the dest bitmap + * @bitmap: array of unsigned longs, the source bitmap + * @nbits: number of bits in @bitmap + */ +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, unsigned int nbits) +{ + unsigned int i, halfwords; + + halfwords = DIV_ROUND_UP(nbits, 32); + for (i = 0; i < halfwords; i++) { + buf[i] = (u32) (bitmap[i/2] & UINT_MAX); + if (++i < halfwords) + buf[i] = (u32) (bitmap[i/2] >> 32); + } + + /* Clear tail bits in last element of array beyond nbits. */ + if (nbits % BITS_PER_LONG) + buf[halfwords - 1] &= (u32) (UINT_MAX >> ((-nbits) & 31)); +} +EXPORT_SYMBOL(kcl_bitmap_to_arr32); +#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c b/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c new file mode 100644 index 0000000000000..3a94597bac3a2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cec_adap.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * cec-adap.c - HDMI Consumer Electronics Control framework - CEC adapter + * + * Copyright 2016 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ +#include +#include +#include +#include + +#if !defined(HAVE_CEC_CONNECTOR_INFO) +void _kcl_cec_fill_conn_info_from_drm(struct cec_connector_info *conn_info, + const struct drm_connector *connector) +{ + memset(conn_info, 0, sizeof(*conn_info)); + conn_info->type = CEC_CONNECTOR_TYPE_DRM; + conn_info->drm.card_no = connector->dev->primary->index; + conn_info->drm.connector_id = connector->base.id; +} +EXPORT_SYMBOL_GPL(_kcl_cec_fill_conn_info_from_drm); + +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c new file mode 100644 index 0000000000000..3d11e965887ea --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include + +static unsigned long _kcl_kallsyms_lookup_name(const char *name) +{ + unsigned long addr = 0; +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = name; + r = register_kprobe(&kp); + if (!r) { + addr = (unsigned long)kp.addr; + unregister_kprobe(&kp); + } +#else + addr = kallsyms_lookup_name(name); +#endif + + return addr; +} + +void *amdkcl_fp_setup(const char *symbol, void *dummy) +{ + unsigned long addr; + void *fp = dummy; + + addr = _kcl_kallsyms_lookup_name(symbol); + if (addr == 0) { + if (fp) + pr_warn("Warning: fail to get symbol %s, replace it with kcl stub\n", symbol); + else { + pr_err("Error: fail to get symbol %s, abort...\n", symbol); + BUG(); + } + } else { + fp = (void *)addr; + } + + return fp; +} + diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h new file mode 100644 index 0000000000000..9c9eca94212b9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_COMMON_H +#define AMDKCL_COMMON_H + +#include +#include + +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "amdkcl: " fmt + +void *amdkcl_fp_setup(const char *symbol, void *dummy); + +/* + * create dummy func + */ +#define amdkcl_dummy_symbol(name, ret_type, ret, ...) \ +ret_type name(__VA_ARGS__) \ +{ \ + pr_warn_once("%s is not supported\n", #name); \ + ret ;\ +} \ +EXPORT_SYMBOL(name); + +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c new file mode 100644 index 0000000000000..f740a9626cd10 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#ifndef for_each_cpu_wrap +/* copied from lib/cpumask.c */ +/** + * cpumask_next_wrap - helper to implement for_each_cpu_wrap + * @n: the cpu prior to the place to search + * @mask: the cpumask pointer + * @start: the start point of the iteration + * @wrap: assume @n crossing @start terminates the iteration + * + * Returns >= nr_cpu_ids on completion + * + * Note: the @wrap argument is required for the start condition when + * we cannot assume @start is set in @mask. + */ +int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, int start, bool wrap) +{ + int next; + +again: + next = cpumask_next(n, mask); + + if (wrap && n < start && next >= start) { + return nr_cpumask_bits; + + } else if (next >= nr_cpumask_bits) { + wrap = true; + n = -1; + goto again; + } + + return next; +} +EXPORT_SYMBOL(_kcl_cpumask_next_wrap); +#endif + diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c new file mode 100644 index 0000000000000..919f869e81857 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * inode.c - part of debugfs, a tiny little debug file system + * + * Copyright (C) 2004,2019 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * Copyright (C) 2019 Linux Foundation + * + * debugfs is for people to use instead of /proc or /sys. + * See ./Documentation/core-api/kernel-api.rst for more details. + */ + +#include +#include +#include + +#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_XSIGNED +/* Copied from fs/libfs.c */ +struct simple_attr { + int (*get)(void *, u64 *); + int (*set)(void *, u64); + char get_buf[24]; /* enough to store a u64 and "\n\0" */ + char set_buf[24]; + void *data; + const char *fmt; /* format for read operation */ + struct mutex mutex; /* protects access to these buffers */ +}; + +static ssize_t simple_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct simple_attr *attr; + unsigned long long val; + size_t size; + ssize_t ret; + + attr = file->private_data; + if (!attr->set) + return -EACCES; + + ret = mutex_lock_interruptible(&attr->mutex); + if (ret) + return ret; + + ret = -EFAULT; + size = min(sizeof(attr->set_buf) - 1, len); + if (copy_from_user(attr->set_buf, buf, size)) + goto out; + + attr->set_buf[size] = '\0'; + if (is_signed) + ret = kstrtoll(attr->set_buf, 0, &val); + else + ret = kstrtoull(attr->set_buf, 0, &val); + if (ret) + goto out; + ret = attr->set(attr->data, val); + if (ret == 0) + ret = len; /* on success, claim we got the whole input */ +out: + mutex_unlock(&attr->mutex); + return ret; +} + +ssize_t simple_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return simple_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(simple_attr_write_signed); + +/* Copied from fs/debugfs/file.c */ +#define F_DENTRY(filp) ((filp)->f_path.dentry) +static ssize_t debugfs_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct dentry *dentry = F_DENTRY(file); + ssize_t ret; + + ret = debugfs_file_get(dentry); + if (unlikely(ret)) + return ret; + if (is_signed) + ret = simple_attr_write_signed(file, buf, len, ppos); + else + ret = simple_attr_write(file, buf, len, ppos); + debugfs_file_put(dentry); + return ret; +} + +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return debugfs_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(debugfs_attr_write_signed); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c new file mode 100644 index 0000000000000..1fb1830aa5039 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * device_cgroup.c - device cgroup subsystem + * + * Copyright 2007 IBM Corp + */ +#include +#include + +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) +/* + * __devcgroup_check_permission is introduced in v3.6-6796-gad676077a2ae + * as: + * static int __devcgroup_check_permission(struct dev_cgroup *dev_cgroup, + * short type, u32 major, u32 minor, + * short access) + * + * prototype change in v3.7-rc2-147-g8c9506d16925 to: + * static int __devcgroup_check_permission(short type, u32 major, u32 minor, + * short access) + * + * the current amdkcl don't support kernel earilier than v3.7-rc2-147-g8c9506d16925 + */ +int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); +EXPORT_SYMBOL(__kcl_devcgroup_check_permission); +#endif +void amdkcl_dev_cgroup_init(void) +{ +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) + __kcl_devcgroup_check_permission = amdkcl_fp_setup("__devcgroup_check_permission", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c new file mode 100644 index 0000000000000..f2a2cdcbf3165 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -0,0 +1,934 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * DOC: Reservation Object Overview + * + * The reservation object provides a mechanism to manage a container of + * dma_fence object associated with a resource. A reservation object + * can have any number of fences attaches to it. Each fence carries an usage + * parameter determining how the operation represented by the fence is using the + * resource. The RCU mechanism is used to protect read access to fences from + * locked write-side updates. + * + * See struct dma_resv for more details. + */ + +extern struct ww_class reservation_ww_class; + +/** + * dma_resv_list_alloc - allocate fence list + * @shared_max: number of fences we need space for + * + * Allocate a new dma_resv_list and make sure to correctly initialize + * shared_max. + */ +static struct dma_resv_list *dma_resv_list_alloc(unsigned int shared_max) +{ + struct dma_resv_list *list; + + list = kmalloc(struct_size(list, shared, shared_max), GFP_KERNEL); + if (!list) + return NULL; + + list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) / + sizeof(*list->shared); + + return list; +} + +/** + * dma_resv_list_free - free fence list + * @list: list to free + * + * Free a dma_resv_list and make sure to drop all references. + */ +static void dma_resv_list_free(struct dma_resv_list *list) +{ + unsigned int i; + + if (!list) + return; + + for (i = 0; i < list->shared_count; ++i) + dma_fence_put(rcu_dereference_protected(list->shared[i], true)); + + kfree_rcu(list, rcu); +} + +/** + * dma_resv_init - initialize a reservation object + * @obj: the reservation object + */ +void dma_resv_init(struct dma_resv *obj) +{ + ww_mutex_init(&obj->lock, &reservation_ww_class); + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + + RCU_INIT_POINTER(obj->fence, NULL); + RCU_INIT_POINTER(obj->fence_excl, NULL); +} +EXPORT_SYMBOL(dma_resv_init); + +/** + * dma_resv_fini - destroys a reservation object + * @obj: the reservation object + */ +void dma_resv_fini(struct dma_resv *obj) +{ + struct dma_resv_list *fobj; + struct dma_fence *excl; + + /* + * This object should be dead and all references must have + * been released to it, so no need to be protected with rcu. + */ + excl = rcu_dereference_protected(obj->fence_excl, 1); + if (excl) + dma_fence_put(excl); + + fobj = rcu_dereference_protected(obj->fence, 1); + dma_resv_list_free(fobj); + ww_mutex_destroy(&obj->lock); +} +EXPORT_SYMBOL(dma_resv_fini); + +/** + * dma_resv_reserve_fences - Reserve space to add shared fences to + * a dma_resv. + * @obj: reservation object + * @num_fences: number of fences we want to add + * + * Should be called before dma_resv_add_shared_fence(). Must + * be called with @obj locked through dma_resv_lock(). + * + * Note that the preallocated slots need to be re-reserved if @obj is unlocked + * at any time before calling dma_resv_add_shared_fence(). This is validated + * when CONFIG_DEBUG_MUTEXES is enabled. + * + * RETURNS + * Zero for success, or -errno + */ +int dma_resv_reserve_fences(struct dma_resv *obj, unsigned int num_fences) +{ + struct dma_resv_list *old, *new; + unsigned int i, j, k, max; + + dma_resv_assert_held(obj); + + old = dma_resv_shared_list(obj); + if (old && old->shared_max) { + if ((old->shared_count + num_fences) <= old->shared_max) + return 0; + max = max(old->shared_count + num_fences, old->shared_max * 2); + } else { + max = max(4ul, roundup_pow_of_two(num_fences)); + } + + new = dma_resv_list_alloc(max); + if (!new) + return -ENOMEM; + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = max; i < (old ? old->shared_count : 0); ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + if (dma_fence_is_signaled(fence)) + RCU_INIT_POINTER(new->shared[--k], fence); + else + RCU_INIT_POINTER(new->shared[j++], fence); + } + new->shared_count = j; + + /* + * We are not changing the effective set of fences here so can + * merely update the pointer to the new array; both existing + * readers and new readers will see exactly the same set of + * active (unsignaled) shared fences. Individual fences and the + * old array are protected by RCU and so will not vanish under + * the gaze of the rcu_read_lock() readers. + */ + rcu_assign_pointer(obj->fence, new); + + if (!old) + return 0; + + /* Drop the references to the signaled fences */ + for (i = k; i < max; ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(new->shared[i], + dma_resv_held(obj)); + dma_fence_put(fence); + } + kfree_rcu(old, rcu); + + return 0; +} +EXPORT_SYMBOL(dma_resv_reserve_fences); + +#ifdef CONFIG_DEBUG_MUTEXES +/** + * dma_resv_reset_max_fences - reset shared fences for debugging + * @obj: the dma_resv object to reset + * + * Reset the number of pre-reserved shared slots to test that drivers do + * correct slot allocation using dma_resv_reserve_fences(). See also + * &dma_resv_list.shared_max. + */ +void dma_resv_reset_max_fences(struct dma_resv *obj) +{ + struct dma_resv_list *fences = dma_resv_shared_list(obj); + + dma_resv_assert_held(obj); + + /* Test shared fence slot reservation */ + if (fences) + fences->shared_max = fences->shared_count; +} +EXPORT_SYMBOL(dma_resv_reset_max_fences); +#endif + +/** + * dma_resv_add_shared_fence - Add a fence to a shared slot + * @obj: the reservation object + * @fence: the shared fence to add + * + * Add a fence to a shared slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +static void dma_resv_add_shared_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_resv_list *fobj; + struct dma_fence *old; + unsigned int i, count; + + dma_fence_get(fence); + + dma_resv_assert_held(obj); + + /* Drivers should not add containers here, instead add each fence + * individually. + */ + WARN_ON(dma_fence_is_container(fence)); + + fobj = dma_resv_shared_list(obj); + count = fobj->shared_count; + + write_seqcount_begin(&obj->seq); + + for (i = 0; i < count; ++i) { + + old = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + if (old->context == fence->context || + dma_fence_is_signaled(old)) + goto replace; + } + + BUG_ON(fobj->shared_count >= fobj->shared_max); + old = NULL; + count++; + +replace: + RCU_INIT_POINTER(fobj->shared[i], fence); + /* pointer update must be visible before we extend the shared_count */ + smp_store_mb(fobj->shared_count, count); + + write_seqcount_end(&obj->seq); + dma_fence_put(old); +} + +/** + * dma_resv_replace_fences - replace fences in the dma_resv obj + * @obj: the reservation object + * @context: the context of the fences to replace + * @replacement: the new fence to use instead + * @usage: how the new fence is used, see enum dma_resv_usage + * + * Replace fences with a specified context with a new fence. Only valid if the + * operation represented by the original fence has no longer access to the + * resources represented by the dma_resv object when the new fence completes. + * + * And example for using this is replacing a preemption fence with a page table + * update fence which makes the resource inaccessible. + */ +void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, + struct dma_fence *replacement, + enum dma_resv_usage usage) +{ + struct dma_resv_list *list; + struct dma_fence *old; + unsigned int i; + + /* Only readers supported for now */ + WARN_ON(usage != DMA_RESV_USAGE_READ && usage != DMA_RESV_USAGE_BOOKKEEP); + + dma_resv_assert_held(obj); + + write_seqcount_begin(&obj->seq); + + old = dma_resv_excl_fence(obj); + if (old && old->context == context) { + RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); + dma_fence_put(old); + } + + list = dma_resv_shared_list(obj); + for (i = 0; list && i < list->shared_count; ++i) { + old = rcu_dereference_protected(list->shared[i], + dma_resv_held(obj)); + if (old->context != context) + continue; + + rcu_assign_pointer(list->shared[i], dma_fence_get(replacement)); + dma_fence_put(old); + } + + write_seqcount_end(&obj->seq); +} +EXPORT_SYMBOL(dma_resv_replace_fences); + +/** + * dma_resv_add_fence - Add a fence to the dma_resv obj + * @obj: the reservation object + * @fence: the fence to add + * @usage: how the fence is used, see enum dma_resv_usage + * + * Add a fence to a slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, + enum dma_resv_usage usage) +{ + struct dma_fence_chain *chain; + + if (usage >= DMA_RESV_USAGE_READ) { + dma_resv_add_shared_fence(obj, fence); + return; + } + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) { + /* We are out of memory, block as last resort */ + dma_fence_wait(fence, false); + return; + } + dma_fence_chain_init(chain, dma_resv_excl_fence(obj), dma_fence_get(fence), 1); + + /* Store the usage in the user bit to retrieve it later on */ + chain->base.flags |= usage << DMA_FENCE_FLAG_USER_BITS; + + /* Install the exclusive fence manually */ + write_seqcount_begin(&obj->seq); + RCU_INIT_POINTER(obj->fence_excl, &chain->base); + write_seqcount_end(&obj->seq); +} +EXPORT_SYMBOL(dma_resv_add_fence); + +/* Restart the iterator by initializing all the necessary fields, but not the + * relation to the dma_resv object. */ +static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) +{ + cursor->seq = read_seqcount_begin(&cursor->obj->seq); + cursor->index = -1; + cursor->shared_count = 0; + cursor->excl_fence = NULL; + cursor->kernel_iter = NULL; + if (cursor->usage >= DMA_RESV_USAGE_READ) { + cursor->fences = dma_resv_shared_list(cursor->obj); + if (cursor->fences) + cursor->shared_count = cursor->fences->shared_count; + } else { + cursor->fences = NULL; + } + cursor->is_restarted = true; +} + +/* Walk to the next not signaled fence and grab a reference to it */ +static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) +{ + struct dma_resv *obj = cursor->obj; + struct dma_fence_chain *chain; + struct dma_fence *f; + enum dma_resv_usage usage; + + do { + /* Drop the reference from the previous round */ + dma_fence_put(cursor->fence); + + if (cursor->index == -1) { + if (cursor->usage >= DMA_RESV_USAGE_WRITE) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + } else { + cursor->fence = NULL; + /* Only return KERNEL fences */ + if (!cursor->excl_fence) { + cursor->excl_fence = dma_resv_excl_fence(obj); + if (!cursor->excl_fence) + break; + + cursor->excl_fence = dma_fence_get(cursor->excl_fence); + cursor->kernel_iter = dma_fence_get(cursor->excl_fence); + } + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && !dma_fence_is_signaled(chain->fence)) + cursor->fence = chain->fence; + + cursor->kernel_iter = dma_fence_chain_walk(f); + + if (cursor->fence) + break; + } + + if (!cursor->fence) { + dma_fence_put(cursor->excl_fence); + cursor->excl_fence = NULL; + break; + } + } + } else if (!cursor->fences || + cursor->index >= cursor->shared_count) { + cursor->fence = NULL; + break; + + } else { + struct dma_resv_list *fences = cursor->fences; + unsigned int idx = cursor->index++; + + cursor->fence = rcu_dereference(fences->shared[idx]); + } + cursor->fence = dma_fence_get_rcu(cursor->fence); + if (!cursor->fence || !dma_fence_is_signaled(cursor->fence)) + break; + } while (true); +} + +/** + * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_first() whenver possible. + * + * Returns the first fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) +{ + bool restart = false; + + rcu_read_lock(); + do { + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + } + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + restart = true; + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_first_unlocked); + +/** + * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_next() whenver possible. + * + * Returns the next fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) +{ + bool restart; + + rcu_read_lock(); + cursor->is_restarted = false; + restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); + do { + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + + dma_resv_iter_restart_unlocked(cursor); + } + dma_resv_iter_walk_unlocked(cursor); + restart = true; + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_next_unlocked); + +/** + * dma_resv_iter_first - first fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Return the first fence in the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) +{ + struct dma_fence *fence, *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; + + dma_resv_assert_held(cursor->obj); + + cursor->index = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) + cursor->fences = dma_resv_shared_list(cursor->obj); + else + cursor->fences = NULL; + + cursor->kernel_iter = NULL; + fence = dma_resv_excl_fence(cursor->obj); + if (!fence) + fence = dma_resv_iter_next(cursor); + else if (cursor->usage == DMA_RESV_USAGE_KERNEL) { + cursor->kernel_iter = dma_fence_get(fence); + fence = NULL; + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL) + fence = chain->fence; + + if (fence) + break; + } + } + + cursor->is_restarted = true; + + return fence; +} +EXPORT_SYMBOL_GPL(dma_resv_iter_first); + +/** + * dma_resv_iter_next - next fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Return the next fences from the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) +{ + unsigned int idx; + struct dma_fence *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; + + dma_resv_assert_held(cursor->obj); + + cursor->is_restarted = false; + + if (cursor->usage == DMA_RESV_USAGE_KERNEL && cursor->kernel_iter != NULL) { + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && chain->fence) + return chain->fence; + } + } + + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) + return NULL; + + idx = cursor->index++; + return rcu_dereference_protected(cursor->fences->shared[idx], + dma_resv_held(cursor->obj)); +} +EXPORT_SYMBOL_GPL(dma_resv_iter_next); + +/** + * dma_resv_copy_fences - Copy all fences from src to dst. + * @dst: the destination reservation object + * @src: the source reservation object + * + * Copy all fences from src to dst. dst-lock must be held. + */ +int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + struct dma_resv_iter cursor; + struct dma_resv_list *list; + struct dma_fence *f, *excl; + + dma_resv_assert_held(dst); + + list = NULL; + excl = NULL; + + dma_resv_iter_begin(&cursor, src, DMA_RESV_USAGE_READ); + dma_resv_for_each_fence_unlocked(&cursor, f) { + + if (dma_resv_iter_is_restarted(&cursor)) { + dma_resv_list_free(list); + dma_fence_put(excl); + + if (cursor.shared_count) { + list = dma_resv_list_alloc(cursor.shared_count); + if (!list) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + + list->shared_count = 0; + + } else { + list = NULL; + } + excl = NULL; + } + + dma_fence_get(f); + if (dma_resv_iter_is_exclusive(&cursor)) + excl = f; + else + RCU_INIT_POINTER(list->shared[list->shared_count++], f); + } + dma_resv_iter_end(&cursor); + + write_seqcount_begin(&dst->seq); + excl = rcu_replace_pointer(dst->fence_excl, excl, dma_resv_held(dst)); + list = rcu_replace_pointer(dst->fence, list, dma_resv_held(dst)); + write_seqcount_end(&dst->seq); + + dma_resv_list_free(list); + dma_fence_put(excl); + + return 0; +} +EXPORT_SYMBOL(dma_resv_copy_fences); + +/** + * dma_resv_get_fences - Get an object's shared and exclusive + * fences without update side lock held + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @num_fences: the number of fences returned + * @fences: the array of fence ptrs returned (array is krealloc'd to the + * required size, and must be freed by caller) + * + * Retrieve all fences from the reservation object. + * Returns either zero or -ENOMEM. + */ +int dma_resv_get_fences(struct dma_resv *obj, enum dma_resv_usage usage, + unsigned int *num_fences, struct dma_fence ***fences) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + *num_fences = 0; + *fences = NULL; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + if (dma_resv_iter_is_restarted(&cursor)) { + unsigned int count; + + while (*num_fences) + dma_fence_put((*fences)[--(*num_fences)]); + + count = cursor.shared_count + 1; + + /* Eventually re-allocate the array */ + *fences = krealloc_array(*fences, count, + sizeof(void *), + GFP_KERNEL); + if (count && !*fences) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + } + + (*fences)[(*num_fences)++] = dma_fence_get(fence); + } + dma_resv_iter_end(&cursor); + + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_fences); + +/** + * dma_resv_get_singleton - Get a single fence for all the fences + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @fence: the resulting fence + * + * Get a single fence representing all the fences inside the resv object. + * Returns either 0 for success or -ENOMEM. + * + * Warning: This can't be used like this when adding the fence back to the resv + * object since that can lead to stack corruption when finalizing the + * dma_fence_array. + * + * Returns 0 on success and negative error values on failure. + */ +int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, + struct dma_fence **fence) +{ + struct dma_fence_array *array; + struct dma_fence **fences; + unsigned count; + int r; + + r = dma_resv_get_fences(obj, usage, &count, &fences); + if (r) + return r; + + if (count == 0) { + *fence = NULL; + return 0; + } + + if (count == 1) { + *fence = fences[0]; + kfree(fences); + return 0; + } + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), + 1, false); + if (!array) { + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; + } + + *fence = &array->base; + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_singleton); + +/** + * dma_resv_wait_timeout - Wait on reservation's objects + * shared and/or exclusive fences. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @intr: if true, do interruptible wait + * @timeout: timeout value in jiffies or zero to return immediately + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already + * RETURNS + * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or + * greater than zer on success. + */ +long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage, + bool intr, unsigned long timeout) +{ + long ret = timeout ? timeout : 1; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + ret = dma_fence_wait_timeout(fence, intr, ret); + if (ret <= 0) { + dma_resv_iter_end(&cursor); + return ret; + } + } + dma_resv_iter_end(&cursor); + + return ret; +} +EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); + +/** + * dma_resv_test_signaled - Test if a reservation object's fences have been + * signaled. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already. + * + * RETURNS + * + * True if all fences signaled, else false. + */ +bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + dma_resv_iter_end(&cursor); + return false; + } + dma_resv_iter_end(&cursor); + return true; +} +EXPORT_SYMBOL_GPL(dma_resv_test_signaled); + +/** + * dma_resv_describe - Dump description of the resv object into seq_file + * @obj: the reservation object + * @seq: the seq_file to dump the description into + * + * Dump a textual description of the fences inside an dma_resv object into the + * seq_file. + */ +void dma_resv_describe(struct dma_resv *obj, struct seq_file *seq) +{ + static const char *usage[] = { "write", "read" }; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_for_each_fence(&cursor, obj, DMA_RESV_USAGE_READ, fence) { + seq_printf(seq, "\t%s fence:", + usage[dma_resv_iter_usage(&cursor)]); + dma_fence_describe(fence, seq); + } +} +EXPORT_SYMBOL_GPL(dma_resv_describe); + +#if IS_ENABLED(CONFIG_LOCKDEP) +static int __init dma_resv_lockdep(void) +{ + struct mm_struct *mm = mm_alloc(); + struct ww_acquire_ctx ctx; + struct dma_resv obj; + struct address_space mapping; + int ret; + + if (!mm) + return -ENOMEM; + + dma_resv_init(&obj); + address_space_init_once(&mapping); + + mmap_read_lock(mm); + ww_acquire_init(&ctx, &reservation_ww_class); + ret = dma_resv_lock(&obj, &ctx); + if (ret == -EDEADLK) + dma_resv_lock_slow(&obj, &ctx); + fs_reclaim_acquire(GFP_KERNEL); + /* for unmap_mapping_range on trylocked buffer objects in shrinkers */ + i_mmap_lock_write(&mapping); + i_mmap_unlock_write(&mapping); +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#else + __dma_fence_might_wait(); +#endif + fs_reclaim_release(GFP_KERNEL); + ww_mutex_unlock(&obj.lock); + ww_acquire_fini(&ctx); + mmap_read_unlock(mm); + + mmput(mm); + + return 0; +} +subsys_initcall(dma_resv_lockdep); +#endif + + + + +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c new file mode 100644 index 0000000000000..f4b4040005a68 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_array.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * dma-fence-array: aggregate fences to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + */ + +#ifndef HAVE_DMA_FENCE_ARRAY_FIRST +#include + +struct dma_fence *kcl_dma_fence_array_first(struct dma_fence *head) +{ + struct dma_fence_array *array; + + if (!head) + return NULL; + + array = to_dma_fence_array(head); + if (!array) + return head; + + if (!array->num_fences) + return NULL; + + return array->fences[0]; +} +EXPORT_SYMBOL(kcl_dma_fence_array_first); + +struct dma_fence *kcl_dma_fence_array_next(struct dma_fence *head, + unsigned int index) +{ + struct dma_fence_array *array = to_dma_fence_array(head); + + if (!array || index >= array->num_fences) + return NULL; + + return array->fences[index]; +} +EXPORT_SYMBOL(kcl_dma_fence_array_next); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c new file mode 100644 index 0000000000000..aef948cfe4ad2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) + +#include +#include + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); + +/** + * dma_fence_chain_get_prev - use RCU to get a reference to the previous fence + * @chain: chain node to get the previous node from + * + * Use dma_fence_get_rcu_safe to get a reference to the previous fence of the + * chain node. + */ +static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain) +{ + struct dma_fence *prev; + + rcu_read_lock(); + prev = dma_fence_get_rcu_safe(&chain->prev); + rcu_read_unlock(); + return prev; +} + +/** + * dma_fence_chain_walk - chain walking function + * @fence: current chain node + * + * Walk the chain to the next node. Returns the next fence or NULL if we are at + * the end of the chain. Garbage collects chain nodes which are already + * signaled. + */ +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) +{ + struct dma_fence_chain *chain, *prev_chain; + struct dma_fence *prev, *replacement, *tmp; + + chain = to_dma_fence_chain(fence); + if (!chain) { + dma_fence_put(fence); + return NULL; + } + + while ((prev = dma_fence_chain_get_prev(chain))) { + + prev_chain = to_dma_fence_chain(prev); + if (prev_chain) { + if (!dma_fence_is_signaled(prev_chain->fence)) + break; + + replacement = dma_fence_chain_get_prev(prev_chain); + } else { + if (!dma_fence_is_signaled(prev)) + break; + + replacement = NULL; + } + + tmp = cmpxchg((struct dma_fence __force **)&chain->prev, + prev, replacement); + if (tmp == prev) + dma_fence_put(tmp); + else + dma_fence_put(replacement); + dma_fence_put(prev); + } + + dma_fence_put(fence); + return prev; +} +EXPORT_SYMBOL(dma_fence_chain_walk); + +/** + * dma_fence_chain_find_seqno - find fence chain node by seqno + * @pfence: pointer to the chain node where to start + * @seqno: the sequence number to search for + * + * Advance the fence pointer to the chain node which will signal this sequence + * number. If no sequence number is provided then this is a no-op. + * + * Returns EINVAL if the fence is not a chain node or the sequence number has + * not yet advanced far enough. + */ +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) +{ + struct dma_fence_chain *chain; + + if (!seqno) + return 0; + + chain = to_dma_fence_chain(*pfence); + if (!chain || chain->base.seqno < seqno) + return -EINVAL; + + dma_fence_chain_for_each(*pfence, &chain->base) { + if ((*pfence)->context != chain->base.context || + to_dma_fence_chain(*pfence)->prev_seqno < seqno) + break; + } + dma_fence_put(&chain->base); + + return 0; +} +EXPORT_SYMBOL(dma_fence_chain_find_seqno); + +static const char *dma_fence_chain_get_driver_name(struct dma_fence *fence) +{ + return "dma_fence_chain"; +} + +static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) +{ + return "unbound"; +} + +static void dma_fence_chain_irq_work(struct irq_work *work) +{ + struct dma_fence_chain *chain; + + chain = container_of(work, typeof(*chain), work); + + /* Try to rearm the callback */ + if (!dma_fence_chain_enable_signaling(&chain->base)) + /* Ok, we are done. No more unsignaled fences left */ + dma_fence_signal(&chain->base); + dma_fence_put(&chain->base); +} + +static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) +{ + struct dma_fence_chain *chain; + + chain = container_of(cb, typeof(*chain), cb); + init_irq_work(&chain->work, dma_fence_chain_irq_work); + irq_work_queue(&chain->work); + dma_fence_put(f); +} + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_chain *head = to_dma_fence_chain(fence); + + dma_fence_get(&head->base); + dma_fence_chain_for_each(fence, &head->base) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + dma_fence_get(f); + if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { + dma_fence_put(fence); + return true; + } + dma_fence_put(f); + } + dma_fence_put(&head->base); + return false; +} + +static bool dma_fence_chain_signaled(struct dma_fence *fence) +{ + dma_fence_chain_for_each(fence, fence) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + if (!dma_fence_is_signaled(f)) { + dma_fence_put(fence); + return false; + } + } + + return true; +} + +static void dma_fence_chain_release(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *prev; + + /* Manually unlink the chain as much as possible to avoid recursion + * and potential stack overflow. + */ + while ((prev = rcu_dereference_protected(chain->prev, true))) { + struct dma_fence_chain *prev_chain; + + if (kref_read(&prev->refcount) > 1) + break; + + prev_chain = to_dma_fence_chain(prev); + if (!prev_chain) + break; + + /* No need for atomic operations since we hold the last + * reference to prev_chain. + */ + chain->prev = prev_chain->prev; + RCU_INIT_POINTER(prev_chain->prev, NULL); + dma_fence_put(prev); + } + dma_fence_put(prev); + + dma_fence_put(chain->fence); + dma_fence_free(fence); +} + +const struct dma_fence_ops dma_fence_chain_ops = { +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO + .use_64bit_seqno = true, +#endif + .get_driver_name = dma_fence_chain_get_driver_name, + .get_timeline_name = dma_fence_chain_get_timeline_name, + .enable_signaling = dma_fence_chain_enable_signaling, + .signaled = dma_fence_chain_signaled, + .release = dma_fence_chain_release, +}; +EXPORT_SYMBOL(dma_fence_chain_ops); + +/** + * dma_fence_chain_init - initialize a fence chain + * @chain: the chain node to initialize + * @prev: the previous fence + * @fence: the current fence + * @seqno: the sequence number to use for the fence chain + * + * Initialize a new chain node and either start a new chain or add the node to + * the existing chain of the previous fence. + */ +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno) +{ + struct dma_fence_chain *prev_chain = to_dma_fence_chain(prev); + uint64_t context; + + spin_lock_init(&chain->lock); + rcu_assign_pointer(chain->prev, prev); + chain->fence = fence; + chain->prev_seqno = 0; + + /* Try to reuse the context of the previous chain node. */ +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { +#else + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno)) { +#endif + context = prev->context; + chain->prev_seqno = prev->seqno; + } else { + context = dma_fence_context_alloc(1); + /* Make sure that we always have a valid sequence number. */ + if (prev_chain) + seqno = max(prev->seqno, seqno); + } + + dma_fence_init(&chain->base, &dma_fence_chain_ops, + &chain->lock, context, seqno); +} +EXPORT_SYMBOL(dma_fence_chain_init); +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c new file mode 100644 index 0000000000000..242a5bcc44171 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_unwrap.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2007 Jens Axboe + * + * Scatterlist handling helpers. + */ +#include +#include +#include +#include +#include + +#ifndef HAVE_DMA_FENCE_DEDUP_ARRAY +static int fence_cmp(const void *_a, const void *_b) +{ + struct dma_fence *a = *(struct dma_fence **)_a; + struct dma_fence *b = *(struct dma_fence **)_b; + + if (a->context < b->context) + return -1; + else if (a->context > b->context) + return 1; + + if (dma_fence_is_later(b, a)) + return 1; + else if (dma_fence_is_later(a, b)) + return -1; + + return 0; +} + +/** + * dma_fence_dedup_array - Sort and deduplicate an array of dma_fence pointers + * @fences: Array of dma_fence pointers to be deduplicated + * @num_fences: Number of entries in the @fences array + * + * Sorts the input array by context, then removes duplicate + * fences with the same context, keeping only the most recent one. + * + * The array is modified in-place and unreferenced duplicate fences are released + * via dma_fence_put(). The function returns the new number of fences after + * deduplication. + * + * Return: Number of unique fences remaining in the array. + */ +int kcl_dma_fence_dedup_array(struct dma_fence **fences, int num_fences) +{ + int i, j; + + sort(fences, num_fences, sizeof(*fences), fence_cmp, NULL); + + /* + * Only keep the most recent fence for each context. + */ + j = 0; + for (i = 1; i < num_fences; i++) { + if (fences[i]->context == fences[j]->context) + dma_fence_put(fences[i]); + else + fences[++j] = fences[i]; + } + + return ++j; +} +EXPORT_SYMBOL_GPL(kcl_dma_fence_dedup_array); + +#endif + +#ifndef HAVE_DMA_FENCE_UNWRAP_MERGE +/* Implementation for the dma_fence_unwrap_merge() macro, don't use directly */ +struct dma_fence *kcl__dma_fence_unwrap_merge(unsigned int num_fences, + struct dma_fence **fences, + struct dma_fence_unwrap *iter) +{ + struct dma_fence *tmp, *unsignaled = NULL, **array; + struct dma_fence_array *result; + ktime_t timestamp; + int i, count; + + count = 0; + timestamp = ns_to_ktime(0); + for (i = 0; i < num_fences; ++i) { + dma_fence_unwrap_for_each(tmp, &iter[i], fences[i]) { + if (!dma_fence_is_signaled(tmp)) { + dma_fence_put(unsignaled); + unsignaled = dma_fence_get(tmp); + ++count; + } else { + ktime_t t = dma_fence_timestamp(tmp); + + if (ktime_after(t, timestamp)) + timestamp = t; + } + } + } + + /* + * If we couldn't find a pending fence just return a private signaled + * fence with the timestamp of the last signaled one. + * + * Or if there was a single unsignaled fence left we can return it + * directly and early since that is a major path on many workloads. + */ + if (count == 0) + return dma_fence_get_stub(); + else if (count == 1) + return unsignaled; + + dma_fence_put(unsignaled); + + array = kmalloc_array(count, sizeof(*array), GFP_KERNEL); + if (!array) + return NULL; + + count = 0; + for (i = 0; i < num_fences; ++i) { + dma_fence_unwrap_for_each(tmp, &iter[i], fences[i]) { + if (!dma_fence_is_signaled(tmp)) { + array[count++] = dma_fence_get(tmp); + } else { + ktime_t t = dma_fence_timestamp(tmp); + + if (ktime_after(t, timestamp)) + timestamp = t; + } + } + } + + if (count == 0 || count == 1) + goto return_fastpath; + + count = dma_fence_dedup_array(array, count); + + if (count > 1) { + result = dma_fence_array_create(count, array, + dma_fence_context_alloc(1), + 1, false); + if (!result) { + for (i = 0; i < count; i++) + dma_fence_put(array[i]); + tmp = NULL; + goto return_tmp; + } + return &result->base; + } + +return_fastpath: + if (count == 0) + tmp = dma_fence_get_stub(); + else + tmp = array[0]; + +return_tmp: + kfree(array); + return tmp; +} +EXPORT_SYMBOL_GPL(kcl__dma_fence_unwrap_merge); + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c new file mode 100644 index 0000000000000..a5c85881e336b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: MIT + +#if !defined(HAVE_DRM_DRM_APERTURE_H) && !defined(HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES) + +#include +#include + +#include +#include +#include "kcl_fbmem.h" + +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + int ret = 0; + + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ +#if IS_REACHABLE(CONFIG_FB) + ret = _kcl_remove_conflicting_pci_framebuffers(pdev, name); +#endif +#ifdef HAVE_VGA_REMOVE_VGACON + if (ret == 0) + ret = vga_remove_vgacon(pdev); +#endif + return ret; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); +#endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c new file mode 100644 index 0000000000000..0851d46f3a17e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#include +#include +#include + +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c */ +void +__drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + if (crtc_state) + crtc_state->crtc = crtc; + + crtc->state = crtc_state; +} +EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); +#endif + +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +/* + * This implementation is duplicated from v5.9-rc5-1595-ge1ad957d45f7 + * "Extract drm_atomic_helper_calc_timestamping_constants()" + * + */ +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) +{ + struct drm_crtc_state *new_crtc_state; + struct drm_crtc *crtc; + +#if !defined(for_each_new_crtc_in_state) + struct drm_device *dev = state->dev; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + new_crtc_state = crtc->state; +#else + int i; + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif + if (new_crtc_state->enable) + drm_calc_timestamping_constants(crtc, + &new_crtc_state->adjusted_mode); + } +} +EXPORT_SYMBOL(drm_atomic_helper_calc_timestamping_constants); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c new file mode 100644 index 0000000000000..85894bf3907c6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c @@ -0,0 +1,66 @@ +/* + * \file drm_memory.c + * Memory management wrappers for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +#include +#include + +/* Copied from drivers/gpu/drm/drm_memory.c */ +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits) +{ + struct resource *tmp; + resource_size_t max_iomem = 0; + + /* + * Xen paravirtual hosts require swiotlb regardless of requested dma + * transfer size. + * + * NOTE: Really, what it requires is use of the dma_alloc_coherent + * allocator used in ttm_dma_populate() instead of + * ttm_populate_and_map_pages(), which bounce buffers so much in + * Xen it leads to swiotlb buffer exhaustion. + */ + if (xen_pv_domain()) + return true; + + for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { + max_iomem = max(max_iomem, tmp->end); + } + + return max_iomem > ((u64)1 << dma_bits); +} +EXPORT_SYMBOL(drm_need_swiotlb); +#endif /* HAVE_DRM_NEED_SWIOTLB */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c new file mode 100644 index 0000000000000..23326cab0ea77 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_client_event.c @@ -0,0 +1,15 @@ +#include + +#ifndef HAVE_DRM_CLIENT_DEV_RESUME +void _kcl_drm_client_dev_resume(struct drm_device *dev) +{ + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, true); +} +EXPORT_SYMBOL(_kcl_drm_client_dev_resume); + +void _kcl_drm_client_dev_suspend(struct drm_device *dev) +{ + drm_fb_helper_set_suspend_unlocked(dev->fb_helper, false); +} +EXPORT_SYMBOL(_kcl_drm_client_dev_suspend); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c new file mode 100644 index 0000000000000..7616f113d4afb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#include + +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return drm_connector_init(dev, connector, funcs, connector_type); +} +EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); +#endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +amdkcl_dummy_symbol(drm_connector_attach_dp_subconnector_property, void, return, + struct drm_connector *connector) +amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, + struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]) +#endif + +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state) +{ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + struct drm_property_blob *old_blob = old_state->hdr_output_metadata; + struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + + if (!old_blob || !new_blob) + return old_blob == new_blob; + + if (old_blob->length != new_blob->length) + return false; + + return !memcmp(old_blob->data, new_blob->data, old_blob->length); +#else + return false; +#endif +} +EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); +#endif + +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.hdr_output_metadata_property; + + drm_object_attach_property(&connector->base, prop, 0); +#endif + + return 0; +} +EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); +#endif + +#if !defined(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK) +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return drm_connector_init_panel_orientation_property(connector, width, height); +} +EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); +#endif + +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +struct drm_property *prop = NULL; +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector) +{ + if(prop) + drm_object_attach_property(&connector->base, prop, DRM_MODE_COLORIMETRY_DEFAULT); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_connector_attach_colorspace_property); +#endif + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +/* copy from drivers/gpu/drm/drm_connector.c (v6.1-5788-gac3470b13f0d) */ +static const char * const colorspace_names[] = { + /* For Default case, driver will set the colorspace */ + [DRM_MODE_COLORIMETRY_DEFAULT] = "Default", + /* Standard Definition Colorimetry based on CEA 861 */ + [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = "SMPTE_170M_YCC", + [DRM_MODE_COLORIMETRY_BT709_YCC] = "BT709_YCC", + /* Standard Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_601] = "XVYCC_601", + /* High Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_709] = "XVYCC_709", + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */ + [DRM_MODE_COLORIMETRY_SYCC_601] = "SYCC_601", + /* Colorimetry based on IEC 61966-2-5 [33] */ + [DRM_MODE_COLORIMETRY_OPYCC_601] = "opYCC_601", + /* Colorimetry based on IEC 61966-2-5 */ + [DRM_MODE_COLORIMETRY_OPRGB] = "opRGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_CYCC] = "BT2020_CYCC", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_RGB] = "BT2020_RGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_YCC] = "BT2020_YCC", + /* Added as part of Additional Colorimetry Extension in 861.G */ + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65] = "DCI-P3_RGB_D65", + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER] = "DCI-P3_RGB_Theater", + [DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED] = "RGB_WIDE_FIXED", + /* Colorimetry based on scRGB (IEC 61966-2-2) */ + [DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT] = "RGB_WIDE_FLOAT", + [DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC", +}; + +static const u32 hdmi_colorspaces = + BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER); + +static const u32 dp_colorspaces = + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED) | + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT601_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); + +static int _kcl_drm_mode_create_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + struct drm_device *dev = connector->dev; + u32 colorspaces = supported_colorspaces | BIT(DRM_MODE_COLORIMETRY_DEFAULT); + struct drm_prop_enum_list enum_list[DRM_MODE_COLORIMETRY_COUNT]; + int i, len; + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (connector->colorspace_property) +#else + if (prop) +#endif + return 0; + + + if (!supported_colorspaces) { + drm_err(dev, "No supported colorspaces provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + if ((supported_colorspaces & -BIT(DRM_MODE_COLORIMETRY_COUNT)) != 0) { + drm_err(dev, "Unknown colorspace provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + len = 0; + for (i = 0; i < DRM_MODE_COLORIMETRY_COUNT; i++) { + if ((colorspaces & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = colorspace_names[i]; + len++; + } +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + connector->colorspace_property = +#else + prop = +#endif + drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace", + enum_list, + len); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (!connector->colorspace_property) +#else + if (!prop) +#endif + return -ENOMEM; + + return 0; +} +#endif /* KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & hdmi_colorspaces; + else + colorspaces = hdmi_colorspaces; + + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); +#endif + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & dp_colorspaces; + else + colorspaces = dp_colorspaces; + + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c new file mode 100644 index 0000000000000..c4e079c49d8ab --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2008 Red Hat Inc. + * + * DRM core CRTC related functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Keith Packard + * Eric Anholt + * Dave Airlie + * Jesse Barnes + */ +#include + +#ifndef HAVE_DRM_HELPER_FORCE_DISABLE_ALL +int _kcl_drm_helper_force_disable_all(struct drm_device *dev) +{ + struct drm_crtc *crtc; + int ret = 0; + + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + struct drm_mode_set set = { + .crtc = crtc, + }; + + ret = drm_mode_set_config_internal(&set); + if (ret) + goto out; + } +out: + drm_modeset_unlock_all(dev); + return ret; +} +EXPORT_SYMBOL(_kcl_drm_helper_force_disable_all); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c new file mode 100644 index 0000000000000..c27581210a3d6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c @@ -0,0 +1,118 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include +#include + +#ifndef HAVE_DRM_DP_READ_DPCD_CAPS +static int _kcl_drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + /* + * Prior to DP1.3 the bit represented by + * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. + * If it is set DP_DPCD_REV at 0000h could be at a value less than + * the true capability of the panel. The only way to check is to + * then compare 0000h and 2200h. + */ + if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) + return 0; + + ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, + sizeof(dpcd_ext)); + if (ret < 0) + return ret; + if (ret != sizeof(dpcd_ext)) + return -EIO; + + if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { + drm_dbg_kms( + drm_dev, + "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", + aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); + return 0; + } + + if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) + return 0; + + drm_dbg_kms(drm_dev, "%s: Base DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); + + return 0; +} + +/** + * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if + * available + * @aux: DisplayPort AUX channel + * @dpcd: Buffer to store the resulting DPCD in + * + * Attempts to read the base DPCD caps for @aux. Additionally, this function + * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if + * present. + * + * Returns: %0 if the DPCD was read successfully, negative error code + * otherwise. + */ +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + + ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); + if (ret < 0) + return ret; + if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) + return -EIO; + + ret = _kcl_drm_dp_read_extended_dpcd_caps(aux, dpcd); + if (ret < 0) + return ret; + + drm_dbg_kms(drm_dev, "%s: DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + return ret; +} +EXPORT_SYMBOL(_kcl_drm_dp_read_dpcd_caps); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c new file mode 100644 index 0000000000000..8b3f68cacab77 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_mst_topology.c @@ -0,0 +1,71 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include + +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE +static void _kcl_drm_dp_mst_queue_probe_work(struct drm_dp_mst_topology_mgr *mgr) +{ + queue_work(system_long_wq, &mgr->work); +} + +static void +_kcl_drm_dp_mst_topology_mgr_invalidate_mstb(struct drm_dp_mst_branch *mstb) +{ + struct drm_dp_mst_port *port; + + /* The link address will need to be re-sent on resume */ + mstb->link_address_sent = false; + + list_for_each_entry(port, &mstb->ports, next) + if (port->mstb) + _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(port->mstb); +} + +/** + * drm_dp_mst_topology_queue_probe - Queue a topology probe + * @mgr: manager to probe + * + * Queue a work to probe the MST topology. Driver's should call this only to + * sync the topology's HW->SW state after the MST link's parameters have + * changed in a way the state could've become out-of-sync. This is the case + * for instance when the link rate between the source and first downstream + * branch device has switched between UHBR and non-UHBR rates. Except of those + * cases - for instance when a sink gets plugged/unplugged to a port - the SW + * state will get updated automatically via MST UP message notifications. + */ +void _kcl_drm_dp_mst_topology_queue_probe(struct drm_dp_mst_topology_mgr *mgr) +{ + mutex_lock(&mgr->lock); + + if (drm_WARN_ON(mgr->dev, !mgr->mst_state || !mgr->mst_primary)) + goto out_unlock; + + _kcl_drm_dp_mst_topology_mgr_invalidate_mstb(mgr->mst_primary); + _kcl_drm_dp_mst_queue_probe_work(mgr); + +out_unlock: + mutex_unlock(&mgr->lock); +} +EXPORT_SYMBOL(_kcl_drm_dp_mst_topology_queue_probe); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c new file mode 100644 index 0000000000000..9f3cf9fbfb434 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -0,0 +1,108 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_DRM_DEV_WEDGED_EVENT +/* + * Available recovery methods for wedged device. To be sent along with device + * wedged uevent. + */ +static const char *drm_get_wedge_recovery(unsigned int opt) +{ + switch (BIT(opt)) { + case DRM_WEDGE_RECOVERY_NONE: + return "none"; + case DRM_WEDGE_RECOVERY_REBIND: + return "rebind"; + case DRM_WEDGE_RECOVERY_BUS_RESET: + return "bus-reset"; + default: + return NULL; + } +} + +#define WEDGE_STR_LEN 32 +#define PID_STR_LEN 15 +#define COMM_STR_LEN (TASK_COMM_LEN + 5) + +/** + * drm_dev_wedged_event - generate a device wedged uevent + * @dev: DRM device + * @method: method(s) to be used for recovery + * + * This generates a device wedged uevent for the DRM device specified by @dev. + * Recovery @method\(s) of choice will be sent in the uevent environment as + * ``WEDGED=[,..,]`` in order of less to more side-effects. + * If caller is unsure about recovery or @method is unknown (0), + * ``WEDGED=unknown`` will be sent instead. + * + * Refer to "Device Wedging" chapter in Documentation/gpu/drm-uapi.rst for more + * details. + * + * Returns: 0 on success, negative error code otherwise. + */ +int kcl_drm_dev_wedged_event(struct drm_device *dev, unsigned long method, + struct drm_wedge_task_info *info) +{ + char event_string[WEDGE_STR_LEN], pid_string[PID_STR_LEN], comm_string[COMM_STR_LEN]; + char *envp[] = { event_string, NULL, NULL, NULL }; + const char *recovery = NULL; + unsigned int len, opt; + + len = scnprintf(event_string, sizeof(event_string), "%s", "WEDGED="); + + for_each_set_bit(opt, &method, BITS_PER_TYPE(method)) { + recovery = drm_get_wedge_recovery(opt); + if (drm_WARN_ONCE(dev, !recovery, "invalid recovery method %u\n", opt)) + break; + + len += scnprintf(event_string + len, sizeof(event_string), "%s,", recovery); + } + if (recovery) + /* Get rid of trailing comma */ + event_string[len - 1] = '\0'; + else + /* Caller is unsure about recovery, do the best we can at this point. */ + snprintf(event_string, sizeof(event_string), "%s", "WEDGED=unknown"); + + drm_info(dev, "device wedged, %s\n", method == DRM_WEDGE_RECOVERY_NONE ? + "but recovered through reset" : "needs recovery"); + + if (info && (info->comm[0] != '\0') && (info->pid >= 0)) { + snprintf(pid_string, sizeof(pid_string), "PID=%u", info->pid); + snprintf(comm_string, sizeof(comm_string), "TASK=%s", info->comm); + envp[1] = pid_string; + envp[2] = comm_string; + } + + return kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); +} +EXPORT_SYMBOL(kcl_drm_dev_wedged_event); + +#endif /* HAVE_DRM_DEV_WEDGED_EVENT */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c new file mode 100644 index 0000000000000..8c799582dbbd7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -0,0 +1,332 @@ +/** + * drm_dsc_pps_payload_pack() - Populates the DSC PPS + * + * @pps_payload: + * Bitwise struct for DSC Picture Parameter Set. This is defined + * by &struct drm_dsc_picture_parameter_set + * @dsc_cfg: + * DSC Configuration data filled by driver as defined by + * &struct drm_dsc_config + * + * DSC source device sends a picture parameter set (PPS) containing the + * information required by the sink to decode the compressed frame. Driver + * populates the DSC PPS struct using the DSC configuration parameters in + * the order expected by the DSC Display Sink device. For the DSC, the sink + * device expects the PPS payload in big endian format for fields + * that span more than 1 byte. + */ + +#include +#include +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, + const struct drm_dsc_config *dsc_cfg) +{ + int i; + + /* Protect against someone accidentally changing struct size */ + BUILD_BUG_ON(sizeof(*pps_payload) != + DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); + + memset(pps_payload, 0, sizeof(*pps_payload)); + + /* PPS 0 */ + pps_payload->dsc_version = + dsc_cfg->dsc_version_minor | + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; + + /* PPS 1, 2 is 0 */ + + /* PPS 3 */ + pps_payload->pps_3 = + dsc_cfg->line_buf_depth | + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; + + /* PPS 4 */ + pps_payload->pps_4 = + ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT) | + dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 + dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | +#endif + dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | + dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; + + /* PPS 5 */ + pps_payload->bits_per_pixel_low = + (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); + + /* + * The DSC panel expects the PPS packet to have big endian format + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert + * to big endian format. If format is little endian, it will swap + * bytes to convert to Big endian else keep it unchanged. + */ + + /* PPS 6, 7 */ + pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); + + /* PPS 8, 9 */ + pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); + + /* PPS 10, 11 */ + pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); + + /* PPS 12, 13 */ + pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); + + /* PPS 14, 15 */ + pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); + + /* PPS 16 */ + pps_payload->initial_xmit_delay_high = + ((dsc_cfg->initial_xmit_delay & + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 17 */ + pps_payload->initial_xmit_delay_low = + (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); + + /* PPS 18, 19 */ + pps_payload->initial_dec_delay = + cpu_to_be16(dsc_cfg->initial_dec_delay); + + /* PPS 20 is 0 */ + + /* PPS 21 */ + pps_payload->initial_scale_value = + dsc_cfg->initial_scale_value; + + /* PPS 22, 23 */ + pps_payload->scale_increment_interval = + cpu_to_be16(dsc_cfg->scale_increment_interval); + + /* PPS 24 */ + pps_payload->scale_decrement_interval_high = + ((dsc_cfg->scale_decrement_interval & + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 25 */ + pps_payload->scale_decrement_interval_low = + (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); + + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ + + /* PPS 27 */ + pps_payload->first_line_bpg_offset = + dsc_cfg->first_line_bpg_offset; + + /* PPS 28, 29 */ + pps_payload->nfl_bpg_offset = + cpu_to_be16(dsc_cfg->nfl_bpg_offset); + + /* PPS 30, 31 */ + pps_payload->slice_bpg_offset = + cpu_to_be16(dsc_cfg->slice_bpg_offset); + + /* PPS 32, 33 */ + pps_payload->initial_offset = + cpu_to_be16(dsc_cfg->initial_offset); + + /* PPS 34, 35 */ + pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); + + /* PPS 36 */ + pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; + + /* PPS 37 */ + pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; + + /* PPS 38, 39 */ + pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size); + + /* PPS 40 */ + pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + + /* PPS 41 */ + pps_payload->rc_quant_incr_limit0 = + dsc_cfg->rc_quant_incr_limit0; + + /* PPS 42 */ + pps_payload->rc_quant_incr_limit1 = + dsc_cfg->rc_quant_incr_limit1; + + /* PPS 43 */ + pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | + DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; + + /* PPS 44 - 57 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) + pps_payload->rc_buf_thresh[i] = + dsc_cfg->rc_buf_thresh[i]; + + /* PPS 58 - 87 */ + /* + * For DSC sink programming the RC Range parameter fields + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] + */ + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + pps_payload->rc_range_parameters[i] = + cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << + DSC_PPS_RC_RANGE_MINQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_max_qp << + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_bpg_offset)); + } + + /* PPS 88 */ + pps_payload->native_422_420 = dsc_cfg->native_422 | + dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; + + /* PPS 89 */ + pps_payload->second_line_bpg_offset = + dsc_cfg->second_line_bpg_offset; + + /* PPS 90, 91 */ + pps_payload->nsl_bpg_offset = + cpu_to_be16(dsc_cfg->nsl_bpg_offset); + + /* PPS 92, 93 */ + pps_payload->second_line_offset_adj = + cpu_to_be16(dsc_cfg->second_line_offset_adj); + + /* PPS 94 - 127 are O */ +} +EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +#endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ + +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } else { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else if (vdsc_cfg->native_422) + num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 3 * (4 * vdsc_cfg->bits_per_component) - 2; + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -ERANGE; + } + + final_scale = (vdsc_cfg->rc_model_size * 8) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset) * + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c new file mode 100644 index 0000000000000..5db1c1e936f38 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include +#include +#include + +#ifndef HAVE_DRM_EDID_MALLOC +static const struct drm_edid *__kcl_drm_edid_alloc(const void *edid, size_t size) +{ + struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); + if (drm_edid) { + drm_edid->edid = edid; + drm_edid->size = size; + } + + return drm_edid; +} + +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size) +{ + const struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + edid = kmemdup(edid, size, GFP_KERNEL); + if (!edid) + return NULL; + + drm_edid = __kcl_drm_edid_alloc(edid, size); + if (!drm_edid) + kfree(edid); + + return drm_edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_alloc); + +void _kcl_drm_edid_free(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return; + + kfree(drm_edid->edid); + kfree(drm_edid); +} +EXPORT_SYMBOL(_kcl_drm_edid_free); + +const struct drm_edid *kcl_drm_edid_dup(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return NULL; + return _kcl_drm_edid_alloc(drm_edid->edid, drm_edid->size); +} +EXPORT_SYMBOL(kcl_drm_edid_dup); + +const struct drm_edid *kcl_drm_edid_read_ddc(struct drm_connector *connector, + struct i2c_adapter *adapter) +{ + struct edid *edid; + + if (connector->force == DRM_FORCE_OFF) + return NULL; + + if (connector->force == DRM_FORCE_ON && !connector->override_edid) + edid = drm_get_edid(connector, adapter); + else + edid = drm_get_edid(connector, adapter); + + if (!edid) + return NULL; + + return __kcl_drm_edid_alloc(edid, (edid->extensions + 1) * EDID_LENGTH); +} +EXPORT_SYMBOL(kcl_drm_edid_read_ddc); + +#endif + +#ifndef HAVE_DRM_EDID_RAW +static int edid_extension_block_count(const struct edid *edid) +{ + return edid->extensions; +} + +static int edid_block_count(const struct edid *edid) +{ + return edid_extension_block_count(edid) + 1; +} + +static int edid_size_by_blocks(int num_blocks) +{ + return num_blocks * EDID_LENGTH; +} + +static int edid_size(const struct edid *edid) +{ + return edid_size_by_blocks(edid_block_count(edid)); +} + +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid) +{ + if (!drm_edid || !drm_edid->size) + return NULL; + + /* + * Do not return pointers where relying on EDID extension count would + * lead to buffer overflow. + */ + if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) + return NULL; + + return drm_edid->edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_raw); +#endif + +#ifndef HAVE_DRM_EDID_CONNECTOR_UPDATE +int kcl_drm_edid_connector_update(struct drm_connector *connector, + const struct drm_edid *drm_edid) +{ + const struct edid *edid = _kcl_drm_edid_raw(drm_edid); + return drm_connector_update_edid_property(connector, edid); +} +EXPORT_SYMBOL(kcl_drm_edid_connector_update); +#endif + +#ifndef HAVE_DRM_EDID_CONNECTOR_ADD_MODES +int kcl_drm_edid_connector_add_modes(struct drm_connector *connector) +{ + struct edid *edid = NULL; + + if (connector->edid_blob_ptr) + edid = (struct edid *)connector->edid_blob_ptr->data; + + if (edid) + return drm_add_edid_modes(connector, edid); + + return 0; +} +EXPORT_SYMBOL(kcl_drm_edid_connector_add_modes); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c new file mode 100644 index 0000000000000..4dfc0efcc5e30 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct drm_framebuffer *fb = fb_helper->fb; + + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); + drm_fb_helper_fill_var(info, fb_helper, + sizes->fb_width, sizes->fb_height); + + info->par = fb_helper; + snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb", + fb_helper->dev->driver->name); + +} +EXPORT_SYMBOL(drm_fb_helper_fill_info); +#endif + +#ifndef HAVE_DRM_FB_HELPER_GEM_IS_FB +bool kcl_drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj) +{ + const struct drm_gem_object *gem = NULL; + + if (!fb_helper || !obj) + return false; + if (fb_helper->buffer && fb_helper->buffer->gem) + gem = fb_helper->buffer->gem; + else if (fb_helper->fb) + gem = drm_gem_fb_get_obj(fb_helper->fb, 0); + + return gem == obj; +} +EXPORT_SYMBOL_GPL(kcl_drm_fb_helper_gem_is_fb); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c new file mode 100644 index 0000000000000..21686ff9a5950 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +/* Copied from v5.3-rc1-380-gbb5a45d40d50 drivers/gpu/drm/drm_hdcp.c */ +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + struct drm_device *dev = connector->dev; + struct drm_connector_state *state = connector->state; + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + if (state->content_protection == val) + return; + + state->content_protection = val; +} +EXPORT_SYMBOL(_kcl_drm_hdcp_update_content_protection); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c new file mode 100644 index 0000000000000..a7963c347e685 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -0,0 +1,46 @@ +/* + * Copyright © 1997-2003 by The XFree86 Project, Inc. + * Copyright © 2007 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2005-2006 Luc Verhaegen + * Copyright (c) 2001, Andy Ritger aritger@nvidia.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ +#include +#include +#include + +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) +{ + struct list_head head = dst->head; + + memset(dst, 0, sizeof(*dst)); + *dst = *src; + dst->head = head; +} +EXPORT_SYMBOL(drm_mode_init); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c new file mode 100644 index 0000000000000..36ca9dec40c2b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * driver/drm/drm_prime.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int (*_kcl_drm_gem_prime_handle_to_fd)(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +EXPORT_SYMBOL(_kcl_drm_gem_prime_handle_to_fd); + +int (*_kcl_drm_gem_prime_fd_to_handle)(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +EXPORT_SYMBOL(_kcl_drm_gem_prime_fd_to_handle); +#endif + +void amdkcl_prime_init(void) +{ +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + _kcl_drm_gem_prime_handle_to_fd = amdkcl_fp_setup("drm_gem_prime_handle_to_fd", NULL); + _kcl_drm_gem_prime_fd_to_handle = amdkcl_fp_setup("drm_gem_prime_fd_to_handle", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c new file mode 100644 index 0000000000000..68e4abe6470c6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#include +#include +#include + +#if !defined(HAVE_DRM_ERR_MACRO) +void kcl_drm_err(const char *format, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(kcl_drm_err); + +#endif + +#ifndef HAVE_DRM_PRINT_BITS +/* Copied from v5.3-rc1-684-g141f6357f45c drivers/gpu/drm/drm_print.c */ +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + bool first = true; + unsigned int i; + + if (WARN_ON_ONCE(nbits > BITS_PER_TYPE(value))) + nbits = BITS_PER_TYPE(value); + + for_each_set_bit(i, &value, nbits) { + if (WARN_ON_ONCE(!bits[i])) + continue; + drm_printf(p, "%s%s", first ? "" : ",", + bits[i]); + first = false; + } + if (first) + drm_printf(p, "(none)"); +} +EXPORT_SYMBOL(drm_print_bits); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c new file mode 100644 index 0000000000000..9af3a1dd37f26 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_probe_helper.c @@ -0,0 +1,27 @@ +#include + +#ifndef HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED +/** + * drm_crtc_helper_mode_valid_fixed - Validates a display mode + * @crtc: the crtc + * @mode: the mode to validate + * @fixed_mode: the display hardware's mode + * + * Returns: + * MODE_OK on success, or another mode-status code otherwise. + */ +enum drm_mode_status kcl_drm_crtc_helper_mode_valid_fixed(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + const struct drm_display_mode *fixed_mode) +{ + if (mode->hdisplay != fixed_mode->hdisplay && mode->vdisplay != fixed_mode->vdisplay) + return MODE_ONE_SIZE; + else if (mode->hdisplay != fixed_mode->hdisplay) + return MODE_ONE_WIDTH; + else if (mode->vdisplay != fixed_mode->vdisplay) + return MODE_ONE_HEIGHT; + + return MODE_OK; +} +EXPORT_SYMBOL(kcl_drm_crtc_helper_mode_valid_fixed); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c new file mode 100644 index 0000000000000..7a44428ce88e2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_simple_kms_helper.c and modified for KCL */ +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +static const struct drm_encoder_funcs drm_simple_encoder_funcs_cleanup = { + .destroy = drm_encoder_cleanup, +}; + +int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return drm_encoder_init(dev, encoder, + &drm_simple_encoder_funcs_cleanup, + encoder_type, NULL); +} +EXPORT_SYMBOL(_kcl_drm_simple_encoder_init); + +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c new file mode 100644 index 0000000000000..c0dcc45d0666f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2011 Red Hat Inc. + * Copyright 2023 Intel Corporation. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* Algorithm: + * + * We store the last allocated bo in "hole", we always try to allocate + * after the last allocated bo. Principle is that in a linear GPU ring + * progression was is after last is the oldest bo we allocated and thus + * the first one that should no longer be in use by the GPU. + * + * If it's not the case we skip over the bo after last to the closest + * done bo if such one exist. If none exist and we are not asked to + * block we report failure to allocate. + * + * If we are asked to block we wait on all the oldest fence of all + * rings. We just wait for any of those fence to complete. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); + +/** + * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate + * @align: alignment for each suballocated chunk + * + * Prepares the suballocation manager for suballocations. + */ +void kcl_drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + unsigned int i; + + BUILD_BUG_ON(!is_power_of_2(DRM_SUBALLOC_MAX_QUEUES)); + + if (!align) + align = 1; + + /* alignment must be a power of 2 */ + if (WARN_ON_ONCE(align & (align - 1))) + align = roundup_pow_of_two(align); + + init_waitqueue_head(&sa_manager->wq); + sa_manager->size = size; + sa_manager->align = align; + sa_manager->hole = &sa_manager->olist; + INIT_LIST_HEAD(&sa_manager->olist); + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + INIT_LIST_HEAD(&sa_manager->flist[i]); +} +EXPORT_SYMBOL(kcl_drm_suballoc_manager_init); + +/** + * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * + * Cleans up the suballocation manager after use. All fences added + * with drm_suballoc_free() must be signaled, or we cannot clean up + * the entire manager. + */ +void kcl_drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (!sa_manager->size) + return; + + if (!list_empty(&sa_manager->olist)) { + sa_manager->hole = &sa_manager->olist; + kcl_drm_suballoc_try_free(sa_manager); + if (!list_empty(&sa_manager->olist)) + DRM_ERROR("sa_manager is not empty, clearing anyway\n"); + } + list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { + kcl_drm_suballoc_remove_locked(sa); + } + + sa_manager->size = 0; +} +EXPORT_SYMBOL(kcl_drm_suballoc_manager_fini); + +static void kcl_drm_suballoc_remove_locked(struct drm_suballoc *sa) +{ + struct drm_suballoc_manager *sa_manager = sa->manager; + + if (sa_manager->hole == &sa->olist) + sa_manager->hole = sa->olist.prev; + + list_del_init(&sa->olist); + list_del_init(&sa->flist); + dma_fence_put(sa->fence); + kfree(sa); +} + +static void kcl_drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (sa_manager->hole->next == &sa_manager->olist) + return; + + sa = list_entry(sa_manager->hole->next, struct drm_suballoc, olist); + list_for_each_entry_safe_from(sa, tmp, &sa_manager->olist, olist) { + if (!sa->fence || !dma_fence_is_signaled(sa->fence)) + return; + + kcl_drm_suballoc_remove_locked(sa); + } +} + +static size_t kcl_drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole != &sa_manager->olist) + return list_entry(hole, struct drm_suballoc, olist)->eoffset; + + return 0; +} + +static size_t kcl_drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole->next != &sa_manager->olist) + return list_entry(hole->next, struct drm_suballoc, olist)->soffset; + return sa_manager->size; +} + +static bool kcl_drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, + struct drm_suballoc *sa, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + if ((eoffset - soffset) >= (size + wasted)) { + soffset += wasted; + + sa->manager = sa_manager; + sa->soffset = soffset; + sa->eoffset = soffset + size; + list_add(&sa->olist, sa_manager->hole); + INIT_LIST_HEAD(&sa->flist); + sa_manager->hole = &sa->olist; + return true; + } + return false; +} + +static bool kcl___drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + unsigned int i; + + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (!list_empty(&sa_manager->flist[i])) + return true; + + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + eoffset = kcl_drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + return ((eoffset - soffset) >= (size + wasted)); +} + +/** + * drm_suballoc_event() - Check if we can stop waiting + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to allocate + * @align: alignment we need to match + * + * Return: true if either there is a fence we can wait for or + * enough free memory to satisfy the allocation directly. + * false otherwise. + */ +static bool kcl_drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + bool ret; + + spin_lock(&sa_manager->wq.lock); + ret = kcl___drm_suballoc_event(sa_manager, size, align); + spin_unlock(&sa_manager->wq.lock); + return ret; +} + +static bool kcl_drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, + struct dma_fence **fences, + unsigned int *tries) +{ + struct drm_suballoc *best_bo = NULL; + unsigned int i, best_idx; + size_t soffset, best, tmp; + + /* if hole points to the end of the buffer */ + if (sa_manager->hole->next == &sa_manager->olist) { + /* try again with its beginning */ + sa_manager->hole = &sa_manager->olist; + return true; + } + + soffset = kcl_drm_suballoc_hole_soffset(sa_manager); + /* to handle wrap around we add sa_manager->size */ + best = sa_manager->size * 2; + /* go over all fence list and try to find the closest sa + * of the current last + */ + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) { + struct drm_suballoc *sa; + + fences[i] = NULL; + + if (list_empty(&sa_manager->flist[i])) + continue; + + sa = list_first_entry(&sa_manager->flist[i], + struct drm_suballoc, flist); + + if (!dma_fence_is_signaled(sa->fence)) { + fences[i] = sa->fence; + continue; + } + + /* limit the number of tries each freelist gets */ + if (tries[i] > 2) + continue; + + tmp = sa->soffset; + if (tmp < soffset) { + /* wrap around, pretend it's after */ + tmp += sa_manager->size; + } + tmp -= soffset; + if (tmp < best) { + /* this sa bo is the closest one */ + best = tmp; + best_idx = i; + best_bo = sa; + } + } + + if (best_bo) { + ++tries[best_idx]; + sa_manager->hole = best_bo->olist.prev; + + /* + * We know that this one is signaled, + * so it's safe to remove it. + */ + kcl_drm_suballoc_remove_locked(best_bo); + return true; + } + return false; +} + +/** + * drm_suballoc_new() - Make a suballocation. + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate. + * @gfp: gfp flags used for memory allocation. Typically GFP_KERNEL but + * the argument is provided for suballocations from reclaim context or + * where the caller wants to avoid pipelining rather than wait for + * reclaim. + * @intr: Whether to perform waits interruptible. This should typically + * always be true, unless the caller needs to propagate a + * non-interruptible context from above layers. + * @align: Alignment. Must not exceed the default manager alignment. + * If @align is zero, then the manager alignment is used. + * + * Try to make a suballocation of size @size, which will be rounded + * up to the alignment specified in specified in drm_suballoc_manager_init(). + * + * Return: a new suballocated bo, or an ERR_PTR. + */ +struct drm_suballoc * +kcl_drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align) +{ + struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int tries[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int count; + int i, r; + struct drm_suballoc *sa; + + if (WARN_ON_ONCE(align > sa_manager->align)) + return ERR_PTR(-EINVAL); + if (WARN_ON_ONCE(size > sa_manager->size || !size)) + return ERR_PTR(-EINVAL); + + if (!align) + align = sa_manager->align; + + sa = kmalloc(sizeof(*sa), gfp); + if (!sa) + return ERR_PTR(-ENOMEM); + sa->manager = sa_manager; + sa->fence = NULL; + INIT_LIST_HEAD(&sa->olist); + INIT_LIST_HEAD(&sa->flist); + + spin_lock(&sa_manager->wq.lock); + do { + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + tries[i] = 0; + + do { + kcl_drm_suballoc_try_free(sa_manager); + + if (kcl_drm_suballoc_try_alloc(sa_manager, sa, + size, align)) { + spin_unlock(&sa_manager->wq.lock); + return sa; + } + + /* see if we can skip over some allocations */ + } while (kcl_drm_suballoc_next_hole(sa_manager, fences, tries)); + + for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (fences[i]) + fences[count++] = dma_fence_get(fences[i]); + + if (count) { + long t; + + spin_unlock(&sa_manager->wq.lock); + t = dma_fence_wait_any_timeout(fences, count, intr, + MAX_SCHEDULE_TIMEOUT, + NULL); + for (i = 0; i < count; ++i) + dma_fence_put(fences[i]); + + r = (t > 0) ? 0 : t; + spin_lock(&sa_manager->wq.lock); + } else if (intr) { + /* if we have nothing to wait for block */ + r = wait_event_interruptible_locked + (sa_manager->wq, + kcl___drm_suballoc_event(sa_manager, size, align)); + } else { + spin_unlock(&sa_manager->wq.lock); + wait_event(sa_manager->wq, + kcl_drm_suballoc_event(sa_manager, size, align)); + r = 0; + spin_lock(&sa_manager->wq.lock); + } + } while (!r); + + spin_unlock(&sa_manager->wq.lock); + kfree(sa); + return ERR_PTR(r); +} +EXPORT_SYMBOL(kcl_drm_suballoc_new); + +/** + * drm_suballoc_free - Free a suballocation + * @suballoc: pointer to the suballocation + * @fence: fence that signals when suballocation is idle + * + * Free the suballocation. The suballocation can be re-used after @fence signals. + */ +void kcl_drm_suballoc_free(struct drm_suballoc *suballoc, + struct dma_fence *fence) +{ + struct drm_suballoc_manager *sa_manager; + + if (!suballoc) + return; + + sa_manager = suballoc->manager; + + spin_lock(&sa_manager->wq.lock); + if (fence && !dma_fence_is_signaled(fence)) { + u32 idx; + + suballoc->fence = dma_fence_get(fence); + idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); + list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); + } else { + kcl_drm_suballoc_remove_locked(suballoc); + } + wake_up_all_locked(&sa_manager->wq); + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(kcl_drm_suballoc_free); + +#ifdef CONFIG_DEBUG_FS +void kcl_drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ + struct drm_suballoc *i; + + spin_lock(&sa_manager->wq.lock); + list_for_each_entry(i, &sa_manager->olist, olist) { + unsigned long long soffset = i->soffset; + unsigned long long eoffset = i->eoffset; + + if (&i->olist == sa_manager->hole) + drm_puts(p, ">"); + else + drm_puts(p, " "); + + drm_printf(p, "[0x%010llx 0x%010llx] size %8lld", + suballoc_base + soffset, suballoc_base + eoffset, + eoffset - soffset); + + if (i->fence) + drm_printf(p, " protected by 0x%016llx on context %llu", + (unsigned long long)i->fence->seqno, + (unsigned long long)i->fence->context); + + drm_puts(p, "\n"); + } + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(kcl_drm_suballoc_dump_debug_info); +#endif +MODULE_AUTHOR("Multiple"); +MODULE_DESCRIPTION("Range suballocator helper"); +MODULE_LICENSE("Dual MIT/GPL"); +#endif /*HAVE_DRM_SUBALLOC_MANAGER_INIT*/ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c new file mode 100644 index 0000000000000..20393f00b0a47 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_syncobj.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include +#include + +#ifndef HAVE_DRM_SYNCOBJ_ADD_POINT +struct syncobj_wait_entry { + struct list_head node; + struct task_struct *task; + struct dma_fence *fence; + struct dma_fence_cb fence_cb; + u64 point; +}; + +static void _kcl_syncobj_wait_syncobj_func(struct drm_syncobj *syncobj, + struct syncobj_wait_entry *wait) +{ + struct dma_fence *fence; + + /* This happens inside the syncobj lock */ + fence = rcu_dereference_protected(syncobj->fence, + lockdep_is_held(&syncobj->lock)); + dma_fence_get(fence); + if (!fence || dma_fence_chain_find_seqno(&fence, wait->point)) { + dma_fence_put(fence); + return; + } else if (!fence) { + wait->fence = dma_fence_get_stub(); + } else { + wait->fence = fence; + } + + wake_up_process(wait->task); + list_del_init(&wait->node); +} + +void _kcl_drm_syncobj_add_point(struct drm_syncobj *syncobj, + struct dma_fence_chain *chain, + struct dma_fence *fence, + uint64_t point) +{ + struct syncobj_wait_entry *wait_cur, *wait_tmp; + struct dma_fence *prev; + + dma_fence_get(fence); + + spin_lock(&syncobj->lock); + + prev = drm_syncobj_fence_get(syncobj); + /* You are adding an unorder point to timeline, which could cause payload returned from query_ioctl is 0! */ + if (prev && prev->seqno >= point) + DRM_DEBUG("You are adding an unorder point to timeline!\n"); + dma_fence_chain_init(chain, prev, fence, point); + rcu_assign_pointer(syncobj->fence, &chain->base); + + list_for_each_entry_safe(wait_cur, wait_tmp, &syncobj->cb_list, node) + _kcl_syncobj_wait_syncobj_func(syncobj, wait_cur); + + spin_unlock(&syncobj->lock); + + /* Walk the chain once to trigger garbage collection */ + dma_fence_chain_for_each(fence, prev); + dma_fence_put(prev); +} +EXPORT_SYMBOL(_kcl_drm_syncobj_add_point); +#endif + diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c new file mode 100644 index 0000000000000..f8d4ab7de31e3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c @@ -0,0 +1,43 @@ +/* + * drm_irq.c IRQ and vblank support + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/*copy from drivers/gpu/drm/drm_vblank.c */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +static struct drm_vblank_crtc * +drm_vblank_crtc(struct drm_device *dev, unsigned int pipe) +{ + return &dev->vblank[pipe]; +} + +struct drm_vblank_crtc * +drm_crtc_vblank_crtc(struct drm_crtc *crtc) +{ + return drm_vblank_crtc(crtc->dev, drm_crtc_index(crtc)); +} +EXPORT_SYMBOL(drm_crtc_vblank_crtc); +#endif + diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h new file mode 100644 index 0000000000000..5275dfcb6b6ca --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AMDKCL_KCL_FBMEM_H_ +#define _AMDKCL_KCL_FBMEM_H_ + +#include +#include + +static inline +int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP + return remove_conflicting_pci_framebuffers(pdev, name); +#else + /** + * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures + * handle bar 0 directly. + * as remove_conflicting_pci_framebuffers() for bar 2/5 fails on rhel7.9 + int bar, err; + + for (bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + err = remove_conflicting_pci_framebuffers(pdev, bar, name); + if (err) + return err; + } + */ + pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif +} +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c new file mode 100644 index 0000000000000..1214d429aaf28 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#define CREATE_TRACE_POINTS +#include "kcl_fence_trace.h" + +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +/** + * dma_fence_describe - Dump fence describtion into seq_file + * @fence: the 6fence to describe + * @seq: the seq_file to put the textual description into + * + * Dump a textual description of the fence and it's state into the seq_file. + */ +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq) +{ + seq_printf(seq, "%s %s seq %llu %ssignalled\n", + fence->ops->get_driver_name(fence), + fence->ops->get_timeline_name(fence), fence->seqno, + dma_fence_is_signaled(fence) ? "" : "un"); +} +EXPORT_SYMBOL(dma_fence_describe); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h new file mode 100644 index 0000000000000..5a74e165c087f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copied from include/trace/events/dma_fence.h */ +#if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_KCL_FENCE_H + +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM kcl_fence +#define TRACE_INCLUDE_FILE kcl_fence_trace + +struct dma_fence; + +DECLARE_EVENT_CLASS(kcl_fence, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence), + + TP_STRUCT__entry( + __string(driver, fence->ops->get_driver_name(fence)) + __string(timeline, fence->ops->get_timeline_name(fence)) + __field(unsigned int, context) + __field(unsigned int, seqno) + ), + + TP_fast_assign( + __amdkcl_assign_str(driver, fence->ops->get_driver_name(fence)); + __amdkcl_assign_str(timeline, fence->ops->get_timeline_name(fence)); + __entry->context = fence->context; + __entry->seqno = fence->seqno; + ), + + TP_printk("driver=%s timeline=%s context=%u seqno=%u", + __get_str(driver), __get_str(timeline), __entry->context, + __entry->seqno) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_init, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_enable_signal, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_start, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_end, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +#endif /* _TRACE_KCL_FENCE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c new file mode 100644 index 0000000000000..d021e8955bc40 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c @@ -0,0 +1,98 @@ +/* + * linux/fs/read_write.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include +#include +#include +#include + +#ifndef HAVE_VFS_IOCB_ITER_READ +int kcl_security_file_permission(struct file *file, int mask); + +static inline bool kcl_unsigned_offsets(struct file *file) +{ + return file->f_mode & FMODE_UNSIGNED_OFFSET; +} + +int kcl_rw_verify_area(int read_write, struct file *file, const loff_t *ppos, size_t count) +{ + if (unlikely((ssize_t) count < 0)) + return -EINVAL; + + if (ppos) { + loff_t pos = *ppos; + + if (unlikely(pos < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + if (count >= -pos) /* both values are in 0..LLONG_MAX */ + return -EOVERFLOW; + } else if (unlikely((loff_t) (pos + count) < 0)) { + if (!kcl_unsigned_offsets(file)) + return -EINVAL; + } + } + + return kcl_security_file_permission(file, + read_write == READ ? MAY_READ : MAY_WRITE); +} + +ssize_t kcl_vfs_iocb_iter_read(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->read_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_READ)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_READ)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + goto out; + ret = kcl_rw_verify_area(READ, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_read_iter(file, iocb, iter); +out: + if (ret >= 0) + fsnotify_access(file); + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_read); + +ssize_t kcl_vfs_iocb_iter_write(struct file *file, struct kiocb *iocb, + struct iov_iter *iter) +{ + size_t tot_len; + ssize_t ret = 0; + + if (!file->f_op->write_iter) + return -EINVAL; + if (!(file->f_mode & FMODE_WRITE)) + return -EBADF; + if (!(file->f_mode & FMODE_CAN_WRITE)) + return -EINVAL; + + tot_len = iov_iter_count(iter); + if (!tot_len) + return 0; + ret = kcl_rw_verify_area(WRITE, file, &iocb->ki_pos, tot_len); + if (ret < 0) + return ret; + + ret = call_write_iter(file, iocb, iter); + if (ret > 0) + fsnotify_modify(file); + + return ret; +} +EXPORT_SYMBOL(kcl_vfs_iocb_iter_write); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c b/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c new file mode 100644 index 0000000000000..5f6690633f9ef --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_i2c_core_base.c @@ -0,0 +1,30 @@ +/* + * i2c-core-base.c - a device driver for the i2c bus interface + * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2013-2019 Wolfram Sang + * + * With some changes from Kyösti Mälkki and + * Frodo Looijaard + */ + +#include +#include + +#ifndef HAVE_DEVM_I2C_ADD_ADAPTER +static void kcl_devm_i2c_del_adapter(void *adapter) +{ + i2c_del_adapter(adapter); +} + +int kcl_devm_i2c_add_adapter(struct device *dev, struct i2c_adapter *adapter) +{ + int ret; + + ret = i2c_add_adapter(adapter); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, kcl_devm_i2c_del_adapter, adapter); +} +EXPORT_SYMBOL_GPL(kcl_devm_i2c_add_adapter); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_io.c b/drivers/gpu/drm/amd/amdkcl/kcl_io.c new file mode 100644 index 0000000000000..c1f2307557352 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_io.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Page Attribute Table (PAT) support: handle memory caching attributes in page tables. + * + * Authors: Venkatesh Pallipadi + * Suresh B Siddha + * + * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen. + * + * Basic principles: + * + * PAT is a CPU feature supported by all modern x86 CPUs, to allow the firmware and + * the kernel to set one of a handful of 'caching type' attributes for physical + * memory ranges: uncached, write-combining, write-through, write-protected, + * and the most commonly used and default attribute: write-back caching. + * + * PAT support supercedes and augments MTRR support in a compatible fashion: MTRR is + * a hardware interface to enumerate a limited number of physical memory ranges + * and set their caching attributes explicitly, programmed into the CPU via MSRs. + * Even modern CPUs have MTRRs enabled - but these are typically not touched + * by the kernel or by user-space (such as the X server), we rely on PAT for any + * additional cache attribute logic. + * + * PAT doesn't work via explicit memory ranges, but uses page table entries to add + * cache attribute information to the mapped memory range: there's 3 bits used, + * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT), with the 8 possible values mapped by the + * CPU to actual cache attributes via an MSR loaded into the CPU (MSR_IA32_CR_PAT). + * + * ( There's a metric ton of finer details, such as compatibility with CPU quirks + * that only support 4 types of PAT entries, and interaction with MTRRs, see + * below for details. ) + */ +#include +#include + +/* Copied from arch/x86/mm/pat.c and modified for KCL */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) && \ + defined(CONFIG_X86) +#include + +static int (*_kcl_io_reserve_memtype)(resource_size_t start, resource_size_t end, + enum page_cache_mode *type); +static void (*_kcl_io_free_memtype)(resource_size_t start, resource_size_t end); + +int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size) +{ +#ifdef _PAGE_CACHE_WC + unsigned long type = _PAGE_CACHE_WC; +#else + enum page_cache_mode type = _PAGE_CACHE_MODE_WC; +#endif + + return _kcl_io_reserve_memtype(start, start + size, &type); +} +EXPORT_SYMBOL(_kcl_arch_io_reserve_memtype_wc); + +void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size) +{ + _kcl_io_free_memtype(start, start + size); +} +EXPORT_SYMBOL(_kcl_arch_io_free_memtype_wc); + +void amdkcl_io_init(void) +{ + _kcl_io_reserve_memtype = amdkcl_fp_setup("io_reserve_memtype", NULL); + _kcl_io_free_memtype = amdkcl_fp_setup("io_free_memtype", NULL); +} +#else +void amdkcl_io_init(void) +{ + +} +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c new file mode 100644 index 0000000000000..aef47eda7f4ab --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/ioctl.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b fs/ioctl.c */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +/** + * compat_ptr_ioctl - generic implementation of .compat_ioctl file operation + * + * This is not normally called as a function, but instead set in struct + * file_operations as + * + * .compat_ioctl = compat_ptr_ioctl, + * + * On most architectures, the compat_ptr_ioctl() just passes all arguments + * to the corresponding ->ioctl handler. The exception is arch/s390, where + * compat_ptr() clears the top bit of a 32-bit pointer value, so user space + * pointers to the second 2GB alias the first 2GB, as is the case for + * native 32-bit s390 user space. + * + * The compat_ptr_ioctl() function must therefore be used only with ioctl + * functions that either ignore the argument or pass a pointer to a + * compatible data type. + * + * If any ioctl command handled by fops->unlocked_ioctl passes a plain + * integer instead of a pointer, or any of the passed data types + * is incompatible between 32-bit and 64-bit architectures, a proper + * handler is required instead of compat_ptr_ioctl. + */ +long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + if (!file->f_op->unlocked_ioctl) + return -ENOIOCTLCMD; + + return file->f_op->unlocked_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +EXPORT_SYMBOL(_kcl_compat_ptr_ioctl); +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c new file mode 100644 index 0000000000000..e53a60dbb71f0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar + * Copyright (C) 2005-2006, Thomas Gleixner, Russell King + * + * This file contains the interrupt descriptor management code. Detailed + * information is available in Documentation/core-api/genericirq.rst + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/** + * generic_handle_irq - Invoke the handler for a particular irq + * @irq: The irq number to handle + * + * Returns: 0 on success, or -EINVAL if conversion has failed + * + * This function must be called from an IRQ context with irq regs + * initialized. + */ +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq) +{ + int irq; + irq = irq_find_mapping(domain, hwirq); + + return generic_handle_irq(irq); +} +EXPORT_SYMBOL_GPL(kcl_generic_handle_domain_irq); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c new file mode 100644 index 0000000000000..10fe1c5d9d9c4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Helpers for initial module or kernel cmdline parsing + Copyright (C) 2001 Rusty Russell. + +*/ +#include + +// Copied from kernel/params.c +#define STANDARD_PARAM_DEF(name, type, format, strtolfn) \ + int param_set_##name(const char *val, const struct kernel_param *kp) \ + { \ + return strtolfn(val, 0, (type *)kp->arg); \ + } \ + int param_get_##name(char *buffer, const struct kernel_param *kp) \ + { \ + return scnprintf(buffer, PAGE_SIZE, format "\n", \ + *((type *)kp->arg)); \ + } \ + const struct kernel_param_ops param_ops_##name = { \ + .set = param_set_##name, \ + .get = param_get_##name, \ + }; \ + EXPORT_SYMBOL(param_set_##name); \ + EXPORT_SYMBOL(param_get_##name); \ + EXPORT_SYMBOL(param_ops_##name) + +#ifdef _kcl_param_check_hexint +STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); +#endif + +#ifdef _kcl_param_check_ullong +STANDARD_PARAM_DEF(ullong, unsigned long long, "%llu", kstrtoull); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c new file mode 100644 index 0000000000000..86e0115437fbc --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kfifo.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#ifndef HAVE_KFIFO_OUT_LINEAR +#define __KFIFO_PEEK(data, out, mask) \ + ((data)[(out) & (mask)]) +/* + * __kfifo_peek_n internal helper function for determinate the length of + * the next record in the fifo + */ +static unsigned int __kfifo_peek_n(struct __kfifo *fifo, size_t recsize) +{ + unsigned int l; + unsigned int mask = fifo->mask; + unsigned char *data = fifo->data; + + l = __KFIFO_PEEK(data, fifo->out, mask); + + if (--recsize) + l |= __KFIFO_PEEK(data, fifo->out + 1, mask) << 8; + + return l; +} + +unsigned int __kfifo_out_linear(struct __kfifo *fifo, + unsigned int *tail, unsigned int n) +{ + unsigned int size = fifo->mask + 1; + unsigned int off = fifo->out & fifo->mask; + + if (tail) + *tail = off; + + return min3(n, fifo->in - fifo->out, size - off); +} +EXPORT_SYMBOL(__kfifo_out_linear); + +unsigned int __kfifo_out_linear_r(struct __kfifo *fifo, + unsigned int *tail, unsigned int n, size_t recsize) +{ + if (fifo->in == fifo->out) + return 0; + + if (tail) + *tail = fifo->out + recsize; + + return min(n, __kfifo_peek_n(fifo, recsize)); +} +EXPORT_SYMBOL(__kfifo_out_linear_r); + +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c new file mode 100644 index 0000000000000..e2cd6191d7171 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * (c) 2005-2016 Advanced Micro Devices, Inc. + * + * Written by Jacob Shin - AMD, Inc. + * Maintained by: Borislav Petkov + * + * All MC4_MISCi registers are shared between cores on a node. + */ +#ifdef CONFIG_X86_MCE_AMD +#include + +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) && !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +#if defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types smca_get_bank_type(unsigned int bank) +{ + struct smca_bank *b; + + if (bank >= MAX_NR_BANKS) + return N_SMCA_BANK_TYPES; + + b = &smca_banks[bank]; + if (!b->hwid) + return N_SMCA_BANK_TYPES; + + return b->hwid->bank_type; +} +#else +int smca_get_bank_type(unsigned int bank) +{ + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; +} +#endif +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif + +#endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c new file mode 100644 index 0000000000000..788b0224d6e59 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/************************************************************************** + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include + +/* Copied from mm/util.c and modified for KCL */ +#ifdef HAVE_NO_KVREALLOC +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) +{ + void *newp; + if (oldsize >= newsize) + return (void *)p; + newp = kvmalloc(newsize, flags); + if (!newp) + return NULL; + memcpy(newp, p, oldsize); + kvfree(p); + return newp; +} +EXPORT_SYMBOL(kvrealloc); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c b/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c new file mode 100644 index 0000000000000..aaa84255aff5d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mempool.c @@ -0,0 +1,40 @@ +#include +#include + +#ifndef HAVE_MEMPOOL_ALLOC_PREALLOCATED +/* + * Backport of mempool_alloc_preallocated from commit 37dcc69ad17a0 + * (mempool: introduce mempool_use_prealloc_only). + */ +static void *remove_element(mempool_t *pool) +{ + void *element = pool->elements[--pool->curr_nr]; + + BUG_ON(pool->curr_nr < 0); + return element; +} + +void *kcl_mempool_alloc_preallocated(mempool_t *pool) +{ + void *element; + unsigned long flags; + + spin_lock_irqsave(&pool->lock, flags); + if (likely(pool->curr_nr)) { + element = remove_element(pool); + spin_unlock_irqrestore(&pool->lock, flags); + /* paired with rmb in mempool_free(), read comment there */ + smp_wmb(); + /* + * Update the allocation stack trace as this is more useful + * for debugging. + */ + kmemleak_update_trace(element); + return element; + } + spin_unlock_irqrestore(&pool->lock, flags); + + return NULL; +} +EXPORT_SYMBOL_GPL(kcl_mempool_alloc_preallocated); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c new file mode 100644 index 0000000000000..a6d38823dc68c --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/kernel/fork.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +#ifndef HAVE_MMPUT_ASYNC +void (*_kcl_mmput_async)(struct mm_struct *mm); +EXPORT_SYMBOL(_kcl_mmput_async); + +void __kcl_mmput_async(struct mm_struct *mm) +{ + pr_warn_once("This kernel version not support API: mmput_async !\n"); +} +#endif + +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT_3ARG +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +/* copied from v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c and modified for kcl usage */ +void _kcl_zone_device_page_init(struct page *page, struct dev_pagemap *pgmap, unsigned int order) +{ +/* v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount */ +#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) + get_page(page); +#endif + lock_page(page); +} +#else +void _kcl_zone_device_page_init(struct page *page, struct dev_pagemap *pgmap, unsigned int order) +{ + VM_WARN_ON_ONCE(order > MAX_ORDER_NR_PAGES); + + WARN_ONCE(order, "legacy kernel without zone_device_page_init pgmap and order arg\n"); + zone_device_page_init(page); +} +#endif +EXPORT_SYMBOL_GPL(_kcl_zone_device_page_init); +#endif /* HAVE_ZONE_DEVICE_PAGE_INIT_3ARG */ + +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB +extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +#endif +#endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ + +void amdkcl_mm_init(void) +{ +#ifndef HAVE_MMPUT_ASYNC + _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); +#endif + +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB + _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); +#endif +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c new file mode 100644 index 0000000000000..3de9dfff5d0df --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c @@ -0,0 +1,44 @@ +#include +#include +#include + +#if !defined(HAVE_KMALLOC_SIZE_ROUNDUP) +#ifdef CONFIG_SLOB +/* copy from mm/slob.c */ +size_t kmalloc_size_roundup(size_t size) +{ + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + + return ALIGN(size, ARCH_KMALLOC_MINALIGN); +} + +EXPORT_SYMBOL(kmalloc_size_roundup); +#else +/* copy from mm/slab_common.c and modified for KCL usage. */ +struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +size_t kmalloc_size_roundup(size_t size) +{ + struct kmem_cache *c; + + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + /* Above the smaller buckets, size is a multiple of page size. */ + if (size > KMALLOC_MAX_CACHE_SIZE) + return PAGE_SIZE << get_order(size); + + /* The flags don't matter since size_index is common to all. */ + c = _kcl_kmalloc_slab(size, GFP_KERNEL); + return c ? kmem_cache_size(c) : 0; +} +EXPORT_SYMBOL(kmalloc_size_roundup); +#endif +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mn.c b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c new file mode 100644 index 0000000000000..20a0c2c5a9280 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include + +/* Copied from v3.16-6588-gb972216e27d1 mm/mmu_notifier.c */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +/* + * Modifications [2017-03-14] (c) [2017] + */ + +/* + * This function allows mmu_notifier::release callback to delay a call to + * a function that will free appropriate resources. The function must be + * quick and must not block. + */ +void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)) +{ + /* changed from call_srcu to call_rcu */ + call_rcu(rcu, func); +} +EXPORT_SYMBOL_GPL(mmu_notifier_call_srcu); + +void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + spin_lock(&mm->mmu_notifier_mm->lock); + /* + * Can not use list_del_rcu() since __mmu_notifier_release + * can delete it before we hold the lock. + */ + hlist_del_init_rcu(&mn->hlist); + spin_unlock(&mm->mmu_notifier_mm->lock); + + BUG_ON(atomic_read(&mm->mm_count) <= 0); + mmdrop(mm); +} +EXPORT_SYMBOL_GPL(mmu_notifier_unregister_no_release); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_numa.c b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c new file mode 100644 index 0000000000000..92605529089d1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +#ifndef HAVE_PXM_TO_NODE +int (*_kcl_pxm_to_node)(int pxm); +EXPORT_SYMBOL(_kcl_pxm_to_node); + +/* Copied from include/acpi/acpi_numa.h */ +static int __kcl_pxm_to_node_stub(int pxm) +{ + return 0; +} +#endif + +void amdkcl_numa_init(void) +{ +#ifndef HAVE_PXM_TO_NODE + _kcl_pxm_to_node = amdkcl_fp_setup("pxm_to_node", __kcl_pxm_to_node_stub); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c new file mode 100644 index 0000000000000..4b6735959d945 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/mm/page_alloc.c + * + * Manages the free list, the system allocates free pages here. + * Note that kmalloc() lives in slab.c + * + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * Swap reorganised 29.12.95, Stephen Tweedie + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 + * Reshaped it to be a zoned allocator, Ingo Molnar, Red Hat, 1999 + * Discontiguous memory support, Kanoj Sarcar, SGI, Nov 1999 + * Zone balancing, Kanoj Sarcar, SGI, Jan 2000 + * Per cpu hot/cold page lists, bulk allocation, Martin J. Bligh, Sept 2002 + * (lots of bits borrowed from Ingo Molnar & Andrew Morton) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include + +#include +#include +#include +//#include "internal.h" +//#include "shuffle.h" +//#include "page_reporting.h" + +/* Copied from mm/page_allo.c */ +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +static struct lockdep_map __fs_reclaim_map = + STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); + +static bool __need_reclaim(gfp_t gfp_mask) +{ + /* no reclaim without waiting on it */ + if (!(gfp_mask & __GFP_DIRECT_RECLAIM)) + return false; + + /* this guy won't enter reclaim */ + if (current->flags & PF_MEMALLOC) + return false; + + if (gfp_mask & __GFP_NOLOCKDEP) + return false; + + return true; +} + +void __fs_reclaim_acquire(void) +{ + lock_map_acquire(&__fs_reclaim_map); +} + +void __fs_reclaim_release(void) +{ + lock_map_release(&__fs_reclaim_map); +} + +void _kcl_fs_reclaim_acquire(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_acquire(); + +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#endif + + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_acquire); + +void _kcl_fs_reclaim_release(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_release(); + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_release); +#endif +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c new file mode 100644 index 0000000000000..742ba33ab1884 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Bus Services, see include/linux/pci.h for further explanation. + * + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang + * + * Copyright 1997 -- 2000 Martin Mares + * For codes copied from drivers/pci/pci.c + * + * (C) Copyright 2002-2004 Greg Kroah-Hartman + * (C) Copyright 2002-2004 IBM Corp. + * (C) Copyright 2003 Matthew Wilcox + * (C) Copyright 2003 Hewlett-Packard + * (C) Copyright 2004 Jon Smirl + * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes + * For codes copied from drivers/pci/pci-sysfs.c + */ + +#include +#include +#include + +enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); + +enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_width_cap); + +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ + u32 cap; + u16 ctl; + int ret; + + if (!pci_is_pcie(dev)) + return; + + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (ret) + return; + + if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) + return; + + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); + if (ret) + return; + + if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_EXT_TAG); + } +} +EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); +#endif + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev) +{ + struct acpi_device *adev; + + if (acpi_disabled) + return false; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return false; + + return adev->power.flags.power_resources && + acpi_has_method(adev->handle, "_PR3"); +} +EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ + +#ifdef AMDKCL_CREATE_MEASURE_FILE +/* Copied from drivers/pci/pci-sysfs.c */ +static ssize_t max_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%s\n", PCIE_SPEED2STR(kcl_pcie_get_speed_cap(pdev))); +} +static DEVICE_ATTR_RO(max_link_speed); + +static ssize_t max_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%u\n", kcl_pcie_get_width_cap(pdev)); +} +static DEVICE_ATTR_RO(max_link_width); + +static ssize_t current_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + const char *speed; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_16_0GB: + speed = "16 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_8_0GB: + speed = "8 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_5_0GB: + speed = "5 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_2_5GB: + speed = "2.5 GT/s"; + break; + default: + speed = "Unknown speed"; + } + + return sprintf(buf, "%s\n", speed); +} +static DEVICE_ATTR_RO(current_link_speed); + +static ssize_t current_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + return sprintf(buf, "%u\n", + (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT); +} +static DEVICE_ATTR_RO(current_link_width); + +static struct attribute *pcie_dev_attrs[] = { + &dev_attr_current_link_speed.attr, + &dev_attr_current_link_width.attr, + &dev_attr_max_link_width.attr, + &dev_attr_max_link_speed.attr, + NULL, +}; + +int _kcl_pci_create_measure_file(struct pci_dev *pdev) +{ + int ret = 0; + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_speed sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_speed sysfs files: %d\n", ret); + return ret; + } + + return ret; +} +EXPORT_SYMBOL(_kcl_pci_create_measure_file); + +void _kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_current_link_speed); + device_remove_file(&pdev->dev, &dev_attr_current_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_speed); +} +EXPORT_SYMBOL(_kcl_pci_remove_measure_file); +#endif /* AMDKCL_CREATE_MEASURE_FILE */ + +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static int _kcl_pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; + if (bar_idx == bar) + return pos; + } + + return -ENOENT; +} + +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos = _kcl_pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap &= PCI_REBAR_CAP_SIZES; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x7000) + cap = 0x3f000; + + return cap >> 4; +} +EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); +#endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ +#endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ + +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_GET_BASE_CLASS +static inline const struct pci_device_id * +pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) +{ + if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && + (id->device == PCI_ANY_ID || id->device == dev->device) && + (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && + (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && + !((id->class ^ dev->class) & id->class_mask)) + return id; + return NULL; +} + +static int match_pci_dev_by_id(struct device *dev, const void *data) +{ + struct pci_dev *pdev = to_pci_dev(dev); + const struct pci_device_id *id = data; + + if (pci_match_one_device(id, pdev)) + return 1; + return 0; +} + +static struct pci_dev *pci_get_dev_by_id(const struct pci_device_id *id, + struct pci_dev *from) +{ + struct device *dev; + struct device *dev_start = NULL; + struct pci_dev *pdev = NULL; + + if (from) + dev_start = &from->dev; + dev = bus_find_device(&pci_bus_type, dev_start, (void *)id, + match_pci_dev_by_id); + if (dev) + pdev = to_pci_dev(dev); + pci_dev_put(from); + return pdev; +} + +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from) +{ + struct pci_device_id id = { + .vendor = PCI_ANY_ID, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .class_mask = 0xFF0000, + .class = class << 16, + }; + + return pci_get_dev_by_id(&id, from); +} +EXPORT_SYMBOL(pci_get_base_class); +#endif /*HAVE_PCI_GET_BASE_CLASS*/ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c new file mode 100644 index 0000000000000..bfa5ed0e16feb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_scatterlist.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2007 Jens Axboe + * + * Scatterlist handling helpers. + */ +#include + +#ifndef HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT +int _kcl_sg_alloc_table_from_pages_segment(struct sg_table *sgt, struct page **pages, + unsigned int n_pages, unsigned int offset, + unsigned long size, unsigned int max_segment, + gfp_t gfp_mask) +{ +#ifdef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS + return PTR_ERR_OR_ZERO(__sg_alloc_table_from_pages(sgt, pages, n_pages, + offset, size, max_segment, + NULL, 0, gfp_mask)); +#else + return __sg_alloc_table_from_pages(sgt, pages, n_pages, offset, size, + max_segment, gfp_mask); +#endif +} +EXPORT_SYMBOL(_kcl_sg_alloc_table_from_pages_segment); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_security.c b/drivers/gpu/drm/amd/amdkcl/kcl_security.c new file mode 100644 index 0000000000000..6ba63cf49ef7a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_security.c @@ -0,0 +1,24 @@ +#include +#ifdef CONFIG_SECURITY +#include +#endif +#include "kcl_common.h" + +#ifndef HAVE_VFS_IOCB_ITER_READ +struct file; // Forward declaration + +int (*kcl_security_file_permission)(struct file *file, int mask); + +int _kcl_security_file_permission(struct file *file, int mask) +{ + pr_warn_once("This kernel version not support API: security_file_permission !\n"); + return 0; +} +#endif + +void amdkcl_security_init(void) +{ +#ifndef HAVE_VFS_IOCB_ITER_READ + kcl_security_file_permission = amdkcl_fp_setup("security_file_permission", _kcl_security_file_permission); +#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c new file mode 100644 index 0000000000000..c7f1086ebabd3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * kernel/power/main.c - PM subsystem core functionality. + * + * Copyright (c) 2003 Patrick Mochel + * Copyright (c) 2003 Open Source Development Lab + */ +#include +#include + +#ifndef HAVE_KSYS_SYNC_HELPER +/* Copied from kernel/power/main.c */ +#ifdef CONFIG_PM_SLEEP +long (*_kcl_ksys_sync)(void); + +void _kcl_ksys_sync_helper(void) +{ + pr_info("Syncing filesystems ... "); + _kcl_ksys_sync(); + pr_cont("done.\n"); +} +EXPORT_SYMBOL(_kcl_ksys_sync_helper); + +static bool _kcl_sys_sync_stub(void) +{ + pr_warn_once("kernel symbol [k]sys_sync not found!\n"); + return false; +} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ + +void amdkcl_suspend_init(void) +{ +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP + _kcl_ksys_sync = amdkcl_fp_setup("ksys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + _kcl_ksys_sync = amdkcl_fp_setup("sys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + pr_err_once("Error: fail to get symbol [k]sys_sync!\n"); + BUG(); +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c new file mode 100644 index 0000000000000..0b23918cc8486 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fs/sysfs/file.c - sysfs regular (text) file implementation + * + * Copyright (c) 2001-3 Patrick Mochel + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include +#include + +/* Copied from fs/sysfs/file.c */ +#ifndef HAVE_SYSFS_EMIT +int sysfs_emit(char *buf, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf), + "invalid sysfs_emit: buf:%p\n", buf)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf, PAGE_SIZE, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit); + +/** + * sysfs_emit_at - scnprintf equivalent, aware of PAGE_SIZE buffer. + * @buf: start of PAGE_SIZE buffer. + * @at: offset in @buf to start write in bytes + * @at must be >= 0 && < PAGE_SIZE + * @fmt: format + * @...: optional arguments to @fmt + * + * + * Returns number of characters written starting at &@buf[@at]. + */ +int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf) || at < 0 || at >= PAGE_SIZE, + "invalid sysfs_emit_at: buf:%p at:%d\n", buf, at)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf + at, PAGE_SIZE - at, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit_at); + +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_time.c b/drivers/gpu/drm/amd/amdkcl/kcl_time.c new file mode 100644 index 0000000000000..a6394747da818 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_time.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file contains the interface functions for the various time related + * system calls: time, stime, gettimeofday, settimeofday, adjtime + * + * Modification history: + * + * 1993-09-02 Philip Gladstone + * Created file with time related functions from sched/core.c and adjtimex() + * 1993-10-08 Torsten Duwe + * adjtime interface update and CMOS clock write code + * 1995-08-13 Torsten Duwe + * kernel PLL updated to 1994-12-13 specs (rfc-1589) + * 1999-01-16 Ulrich Windl + * Introduced error checking for many cases in adjtimex(). + * Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + * Allow time_constant larger than MAXTC(6) for NTP v4 (MAXTC == 10) + * (Even though the technical memorandum forbids it) + * 2004-07-14 Christoph Lameter + * Added getnstimeofday to allow the posix timer functions to return + * with nanosecond accuracy + */ +#include +#include + +#ifndef HAVE_JIFFIES64_TO_MSECS +/* Copied from kernel/time/time.c */ +u64 jiffies64_to_msecs(const u64 j) +{ +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (MSEC_PER_SEC / HZ) * j; +#else + return div_u64(j * HZ_TO_MSEC_NUM, HZ_TO_MSEC_DEN); +#endif +} +EXPORT_SYMBOL(jiffies64_to_msecs); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c new file mode 100644 index 0000000000000..7175409637df9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Swap reorganised 29.12.95, Stephen Tweedie. + * kswapd added: 7.1.96 sct + * Removed kswapd_ctl limits, and swap out as many pages as needed + * to bring the system back to freepages.high: 2.4.97, Rik van Riel. + * Zone aware kswapd started 02/00, Kanoj Sarcar (kanoj@sgi.com). + * Multiqueue VM started 5.8.00, Rik van Riel. + */ +#include +#include + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +static DECLARE_RWSEM(shrinker_rwsem); + +/** + * synchronize_shrinkers - Wait for all running shrinkers to complete. + * + * This is equivalent to calling unregister_shrink() and register_shrinker(), + * but atomically and with less overhead. This is useful to guarantee that all + * shrinker invocations have seen an update, before freeing memory, similar to + * rcu. + */ +void synchronize_shrinkers(void) +{ + down_write(&shrinker_rwsem); + up_write(&shrinker_rwsem); +} +EXPORT_SYMBOL(synchronize_shrinkers); +#endif diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c new file mode 100644 index 0000000000000..3299b4e78c7a7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c @@ -0,0 +1,319 @@ +//SPDX-License-Identifier: GPL-2.0 +/* + * Wifi Frequency Band Manage Interface + * Copyright (C) 2023 Advanced Micro Devices + */ + +#include +#include + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +/* + * Functions bit vector for WBRF method + * + * Bit 0: WBRF supported. + * Bit 1: Function 1 (Add / Remove frequency) is supported. + * Bit 2: Function 2 (Get frequency list) is supported. + */ +#define WBRF_ENABLED 0x0 +#define WBRF_RECORD 0x1 +#define WBRF_RETRIEVE 0x2 + +#define WBRF_REVISION 0x1 + +/* + * The data structure used for WBRF_RETRIEVE is not naturally aligned. + * And unfortunately the design has been settled down. + */ +struct amd_wbrf_ranges_out { + u32 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +} __packed; + +static const guid_t wifi_acpi_dsm_guid = + GUID_INIT(0x7b7656cf, 0xdc3d, 0x4c1c, + 0x83, 0xe9, 0x66, 0xe7, 0x21, 0xde, 0x30, 0x70); + +/* + * Used to notify consumer (amdgpu driver currently) about + * the wifi frequency is change. + */ +static BLOCKING_NOTIFIER_HEAD(wbrf_chain_head); + +static int wbrf_record(struct acpi_device *adev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + union acpi_object argv4; + union acpi_object *tmp; + union acpi_object *obj; + u32 num_of_ranges = 0; + u32 num_of_elements; + u32 arg_idx = 0; + int ret; + u32 i; + + if (!in) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (in->band_list[i].start && in->band_list[i].end) + num_of_ranges++; + } + + /* + * The num_of_ranges value in the "in" object supplied by + * the caller is required to be equal to the number of + * entries in the band_list array in there. + */ + if (num_of_ranges != in->num_of_ranges) + return -EINVAL; + + /* + * Every input frequency band comes with two end points(start/end) + * and each is accounted as an element. Meanwhile the range count + * and action type are accounted as an element each. + * So, the total element count = 2 * num_of_ranges + 1 + 1. + */ + num_of_elements = 2 * num_of_ranges + 2; + + tmp = kcalloc(num_of_elements, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + argv4.package.type = ACPI_TYPE_PACKAGE; + argv4.package.count = num_of_elements; + argv4.package.elements = tmp; + + /* save the number of ranges*/ + tmp[0].integer.type = ACPI_TYPE_INTEGER; + tmp[0].integer.value = num_of_ranges; + + /* save the action(WBRF_RECORD_ADD/REMOVE/RETRIEVE) */ + tmp[1].integer.type = ACPI_TYPE_INTEGER; + tmp[1].integer.value = action; + + arg_idx = 2; + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (!in->band_list[i].start || !in->band_list[i].end) + continue; + + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].start; + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].end; + } + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RECORD, &argv4); + + if (!obj) + return -EINVAL; + + if (obj->type != ACPI_TYPE_INTEGER) { + ret = -EINVAL; + goto out; + } + + ret = obj->integer.value; + if (ret) + ret = -EINVAL; + +out: + ACPI_FREE(obj); + kfree(tmp); + + return ret; +} + +/** + * acpi_amd_wbrf_add_remove - add or remove the frequency band the device is using + * + * @dev: device pointer + * @action: remove or add the frequency band into bios + * @in: input structure containing the frequency band the device is using + * + * Broadcast to other consumers the frequency band the device starts + * to use. Underneath the surface the information is cached into an + * internal buffer first. Then a notification is sent to all those + * registered consumers. So then they can retrieve that buffer to + * know the latest active frequency bands. Consumers that haven't + * yet been registered can retrieve the information from the cache + * when they register. + * + * Return: + * 0 for success add/remove wifi frequency band. + * Returns a negative error code for failure. + */ +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + struct acpi_device *adev; + int ret; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + ret = wbrf_record(adev, action, in); + if (ret) + return ret; + + blocking_notifier_call_chain(&wbrf_chain_head, WBRF_CHANGED, NULL); + + return 0; +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_add_remove); + +/** + * acpi_amd_wbrf_supported_producer - determine if the WBRF can be enabled + * for the device as a producer + * + * @dev: device pointer + * + * Check if the platform equipped with necessary implementations to + * support WBRF for the device as a producer. + * + * Return: + * true if WBRF is supported, otherwise returns false + */ +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RECORD)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_producer); + +/** + * acpi_amd_wbrf_supported_consumer - determine if the WBRF can be enabled + * for the device as a consumer + * + * @dev: device pointer + * + * Determine if the platform equipped with necessary implementations to + * support WBRF for the device as a consumer. + * + * Return: + * true if WBRF is supported, otherwise returns false. + */ +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RETRIEVE)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_consumer); + +/** + * amd_wbrf_retrieve_freq_band - retrieve current active frequency bands + * + * @dev: device pointer + * @out: output structure containing all the active frequency bands + * + * Retrieve the current active frequency bands which were broadcasted + * by other producers. The consumer who calls this API should take + * proper actions if any of the frequency band may cause RFI with its + * own frequency band used. + * + * Return: + * 0 for getting wifi freq band successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + struct amd_wbrf_ranges_out acpi_out = {0}; + struct acpi_device *adev; + union acpi_object *obj; + union acpi_object param; + int ret = 0; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + param.type = ACPI_TYPE_STRING; + param.string.length = 0; + param.string.pointer = NULL; + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RETRIEVE, ¶m); + if (!obj) + return -EINVAL; + + /* + * The return buffer is with variable length and the format below: + * number_of_entries(1 DWORD): Number of entries + * start_freq of 1st entry(1 QWORD): Start frequency of the 1st entry + * end_freq of 1st entry(1 QWORD): End frequency of the 1st entry + * ... + * ... + * start_freq of the last entry(1 QWORD) + * end_freq of the last entry(1 QWORD) + * + * Thus the buffer length is determined by the number of entries. + * - For zero entry scenario, the buffer length will be 4 bytes. + * - For one entry scenario, the buffer length will be 20 bytes. + */ + if (obj->buffer.length > sizeof(acpi_out) || obj->buffer.length < 4) { + dev_err(dev, "Wrong sized WBRT information"); + ret = -EINVAL; + goto out; + } + memcpy(&acpi_out, obj->buffer.pointer, obj->buffer.length); + + out->num_of_ranges = acpi_out.num_of_ranges; + memcpy(out->band_list, acpi_out.band_list, sizeof(acpi_out.band_list)); + +out: + ACPI_FREE(obj); + return ret; +} +EXPORT_SYMBOL_GPL(amd_wbrf_retrieve_freq_band); + +/** + * amd_wbrf_register_notifier - register for notifications of frequency + * band update + * + * @nb: driver notifier block + * + * The consumer should register itself via this API so that it can get + * notified on the frequency band updates from other producers. + * + * Return: + * 0 for registering a consumer driver successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_register_notifier); + +/** + * amd_wbrf_unregister_notifier - unregister for notifications of + * frequency band update + * + * @nb: driver notifier block + * + * The consumer should call this API when it is longer interested with + * the frequency band updates from other producers. Usually, this should + * be performed during driver cleanup. + * + * Return: + * 0 for unregistering a consumer driver. + * Returns a negative error code for failure. + */ +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_unregister_notifier); +#endif /*HAVE_LINUX_ACPI_AMD_WBRF_H*/ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c new file mode 100644 index 0000000000000..7c9b248df0e27 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -0,0 +1,46 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_CANCEL_WORK +static bool (*_kcl_cancel_work)(struct work_struct *work, bool is_dwork); + +bool _kcl_cancel_work_stub(struct work_struct *work, bool is_dwork) +{ + pr_warn_once("cancel_work function is not supported\n"); + return false; +} + +bool kcl_cancel_work(struct work_struct *work) +{ + return _kcl_cancel_work(work, false); +} +EXPORT_SYMBOL(kcl_cancel_work); +#endif + +void amdkcl_workqueue_init(void) +{ +#ifndef HAVE_CANCEL_WORK + _kcl_cancel_work = amdkcl_fp_setup("__cancel_work", _kcl_cancel_work_stub); +#endif /* HAVE_CANCEL_WORK */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c new file mode 100644 index 0000000000000..ad8aad6122de6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include + +extern void amdkcl_dev_cgroup_init(void); +extern void amdkcl_io_init(void); +extern void amdkcl_mm_init(void); +extern void amdkcl_suspend_init(void); +extern void amdkcl_numa_init(void); +extern void amdkcl_workqueue_init(void); +extern void amdkcl_prime_init(void); +extern void amdkcl_security_init(void); + +int __init amdkcl_init(void) +{ + amdkcl_dev_cgroup_init(); + amdkcl_io_init(); + amdkcl_mm_init(); + amdkcl_suspend_init(); + amdkcl_numa_init(); + amdkcl_workqueue_init(); + amdkcl_prime_init(); + amdkcl_security_init(); + + return 0; +} +module_init(amdkcl_init); + +void __exit amdkcl_exit(void) +{ +} + +module_exit(amdkcl_exit); + +MODULE_AUTHOR("AMD linux driver team"); +MODULE_DESCRIPTION("Module for OS kernel compatible layer"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 0ce08113c9f0b..d8e20df442622 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -38,6 +38,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_mqd_manager_v10.o \ $(AMDKFD_PATH)/kfd_mqd_manager_v11.o \ $(AMDKFD_PATH)/kfd_mqd_manager_v12.o \ + $(AMDKFD_PATH)/kfd_mqd_manager_v12_1.o \ $(AMDKFD_PATH)/kfd_kernel_queue.o \ $(AMDKFD_PATH)/kfd_packet_manager.o \ $(AMDKFD_PATH)/kfd_packet_manager_vi.o \ @@ -50,15 +51,23 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_device_queue_manager_v10.o \ $(AMDKFD_PATH)/kfd_device_queue_manager_v11.o \ $(AMDKFD_PATH)/kfd_device_queue_manager_v12.o \ + $(AMDKFD_PATH)/kfd_device_queue_manager_v12_1.o \ $(AMDKFD_PATH)/kfd_interrupt.o \ $(AMDKFD_PATH)/kfd_events.o \ $(AMDKFD_PATH)/cik_event_interrupt.o \ $(AMDKFD_PATH)/kfd_int_process_v9.o \ $(AMDKFD_PATH)/kfd_int_process_v10.o \ $(AMDKFD_PATH)/kfd_int_process_v11.o \ + $(AMDKFD_PATH)/kfd_int_process_v12_1.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ - $(AMDKFD_PATH)/kfd_debug.o + $(AMDKFD_PATH)/kfd_peerdirect.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_trace.o \ + $(AMDKFD_PATH)/kfd_spm.o \ + $(AMDKFD_PATH)/kfd_debug.o \ + $(AMDKFD_PATH)/kfd_pc_sampling.o \ + $(AMDKFD_PATH)/kfd_ais.o ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c index 73acbe0b7c212..b799c70f5742a 100644 --- a/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c +++ b/drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c @@ -97,11 +97,11 @@ static void cik_event_interrupt_wq(struct kfd_node *dev, return; if (ihre->source_id == CIK_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id, 28); + kfd_signal_event_interrupt(pasid, context_id, 28, true); else if (ihre->source_id == CIK_INTSRC_SDMA_TRAP) - kfd_signal_event_interrupt(pasid, context_id, 28); + kfd_signal_event_interrupt(pasid, context_id, 28, true); else if (ihre->source_id == CIK_INTSRC_SQ_INTERRUPT_MSG) - kfd_signal_event_interrupt(pasid, context_id & 0xff, 8); + kfd_signal_event_interrupt(pasid, context_id & 0xff, 8, true); else if (ihre->source_id == CIK_INTSRC_CP_BAD_OPCODE) kfd_signal_hw_exception_event(pasid); else if (ihre->source_id == CIK_INTSRC_GFX_PAGE_INV_FAULT || diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index f98c735b2905f..1831f1fecebdc 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,27 +274,32 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820259, + 0xbf820001, 0xbf82026f, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850066, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -303,13 +308,19 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x03800000, + 0x87777977, 0xbf0d986d, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1303,27 +1314,32 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202d5, + 0xbf820001, 0xbf8202eb, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850066, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1332,13 +1348,19 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x03800000, + 0x87777977, 0xbf0d986d, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1784,27 +1806,32 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202e0, + 0xbf820001, 0xbf8202f6, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, + 0xbf0c8a7b, 0xbf850004, + 0xbf0c986d, 0xbf850002, + 0x896dff6d, 0x01ff0000, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850066, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850047, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1813,13 +1840,19 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x03800000, + 0x87777977, 0xbf0d986d, + 0xbf840006, 0xbf0d9877, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0x896dff6d, + 0x01ff0000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef71898, 0xbef71899, + 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -3154,40 +3187,64 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202dc, + 0xbf820001, 0xbf82030c, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, - 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0x866eff7b, 0x04000400, + 0xbf06ff6e, 0x04000400, + 0xbf840003, 0xbefb189a, + 0xba7f0683, 0x00000000, + 0xbf0c8a7b, 0xbf850007, + 0xbf0c986d, 0xbf850005, + 0xbefb1896, 0xba7f0583, + 0x00000000, 0x896dff6d, + 0x01ff0000, 0x866eff78, + 0x00002000, 0xbf84000a, + 0xbf0d986d, 0xbf850023, + 0xbf0d9a7b, 0xbf850021, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, + 0xbf85006f, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, + 0x866eff7b, 0x03800900, + 0xbf850017, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, + 0x866e6f6e, 0xbf85000c, + 0xbf0d986d, 0xbf850003, 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf850007, 0xbf0d986d, + 0xbf850006, 0xbf0d9a7b, + 0xbf850004, 0x866eff7b, + 0x00000400, 0xbf850052, + 0xbeed1a9d, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031cfd, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8e739773, 0x8979ff79, + 0x03800000, 0x87797379, + 0xbf0d986d, 0xbf840008, + 0xbf0d9879, 0xbf840002, + 0xbeed1a9d, 0xbf820004, + 0x896dff6d, 0x01ff0000, + 0xba7f0583, 0x00000000, + 0xb8f3f803, 0xbf0d9a73, + 0xbf840006, 0xbf0d9979, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0xba7f0683, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef91898, 0xbef91899, + 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -3644,18 +3701,22 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { }; static const uint32_t cwsr_trap_gfx12_hex[] = { - 0xbfa00001, 0xbfa002b2, + 0xbfa00001, 0xbfa0024a, 0xb0804009, 0xb8eef81a, 0xbf880000, 0xb980081a, 0x00000000, 0xb8f8f804, 0x9177ff77, 0x0c000000, 0x846e9a6e, 0x8c776e77, 0x9178ff78, 0x00008c00, - 0xb8fbf811, 0x8b6eff78, - 0x00004000, 0xbfa10008, - 0x8b6eff7b, 0x00000080, + 0xb8fbf811, 0xbf0c877b, + 0xbfa20002, 0x916dff6d, + 0xf0000000, 0xbf0c857b, + 0xbfa20003, 0xbefb1087, + 0xb98001d1, 0x00000000, + 0x8b6eff78, 0x00004000, + 0xbfa10007, 0xbf0d877b, 0xbfa20018, 0x8b6ea07b, - 0xbfa2004a, 0xbf830010, + 0xbfa20053, 0xbf830010, 0xb8fbf811, 0xbfa0fffb, 0x8b6eff7b, 0x00000bd0, 0xbfa20010, 0xb8eef812, @@ -3666,55 +3727,58 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xf0000000, 0xbfa20005, 0x8b6fff6f, 0x00000200, 0xbfa20002, 0x8b6ea07b, - 0xbfa20034, 0xbefa4d82, - 0xbf8a0000, 0x84fa887a, - 0xbf0d8f7b, 0xbfa10002, - 0x8c7bff7b, 0xffff0000, - 0x8b6eff77, 0x0c000000, - 0x916dff6d, 0x0c000000, - 0x8c6d6e6d, 0xf4601bbd, - 0xf8000010, 0xbf8a0000, - 0x846e976e, 0x9177ff77, - 0x00800000, 0x8c776e77, - 0xf4603bbd, 0xf8000000, - 0xbf8a0000, 0xf4603ebd, - 0xf8000008, 0xbf8a0000, - 0x8bee6e6e, 0xbfa10001, - 0xbe80486e, 0x8b6eff6d, - 0xf0000000, 0xbfa20009, - 0xb8eef811, 0x8b6eff6e, - 0x00000080, 0xbfa20007, - 0x8c78ff78, 0x00004000, - 0x80ec886c, 0x82ed806d, - 0xbfa00002, 0x806c846c, - 0x826d806d, 0x8b6dff6d, - 0x0000ffff, 0x8bfe7e7e, - 0x8bea6a6a, 0x85788978, - 0x936eff77, 0x0002001a, - 0xb96ef81a, 0xb9783244, - 0xbe804a6c, 0xb8faf802, - 0xbf0d987a, 0xbfa10001, - 0xbfb00000, 0x8b6dff6d, - 0x0000ffff, 0xbefa0080, - 0xb97a0151, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbefe4d84, 0xbf8a0000, - 0x8b7aff7f, 0x04000000, - 0x847a857a, 0x8c6d7a6d, - 0xbefa007e, 0x8b7bff7f, - 0x0000ffff, 0xbefe00c1, - 0xbeff00c1, 0xee0a407a, - 0x000c0000, 0x00000000, - 0x7e000280, 0xbefe007a, - 0xbeff007b, 0xb8fb0742, - 0x847b997b, 0xb8fa3b05, - 0x807a817a, 0xbf0d997b, - 0xbfa20002, 0x847a897a, - 0xbfa00001, 0x847a8a7a, - 0xb8fb1e06, 0x847b8a7b, - 0x807a7b7a, 0x8b7bff7f, + 0xbfa2003d, 0xbeef007b, + 0xbefa4d82, 0xbf8a0000, + 0x84fa887a, 0xbf0d8f7b, + 0xbfa10002, 0x8c7bff7b, + 0xffff0000, 0x8b6eff77, + 0x0c000000, 0x916dff6d, + 0x0c000000, 0x8c6d6e6d, + 0xf4601bbd, 0xf8000010, + 0xbf8a0000, 0x846e976e, + 0x9177ff77, 0x01800000, + 0x8c776e77, 0xbf0d876f, + 0xbfa10006, 0xbf0d8e78, + 0xbfa20002, 0xbf0d9877, + 0xbfa20002, 0xb98001d1, + 0x00000000, 0xf4603bbd, + 0xf8000000, 0xbf8a0000, + 0xf4603ebd, 0xf8000008, + 0xbf8a0000, 0x8bee6e6e, + 0xbfa10001, 0xbe80486e, + 0x8b6eff6d, 0xf0000000, + 0xbfa20009, 0xb8eef811, + 0x8b6eff6e, 0x00000080, + 0xbfa20007, 0x8c78ff78, + 0x00004000, 0x80ec886c, + 0x82ed806d, 0xbfa00002, + 0x806c846c, 0x826d806d, + 0x8b6dff6d, 0x0000ffff, + 0x8bfe7e7e, 0x8bea6a6a, + 0x85788978, 0x936eff77, + 0x0002001a, 0xb96ef81a, + 0xb9783244, 0xbe804a6c, + 0xb8faf802, 0xbf0d987a, + 0xbfa10001, 0xbfb00000, + 0x8b6dff6d, 0x0000ffff, + 0xbefa0080, 0xb97a0151, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbefe4d84, + 0xbf8a0000, 0x8b7aff7f, + 0x04000000, 0x847a857a, + 0x8c6d7a6d, 0xbefa007e, + 0x8b7bff7f, 0x0000ffff, + 0xbefe00c1, 0xbeff00c1, + 0xee0a407a, 0x000c0000, + 0x00000000, 0x7e000280, + 0xbefe007a, 0xbeff007b, + 0xb8fb0742, 0x847b997b, + 0xb8fa3b05, 0x807a817a, + 0xbf0d997b, 0xbfa20002, + 0x847a897a, 0xbfa00001, + 0x847a8a7a, 0x8b7bff7f, 0x0000ffff, 0x807aff7a, - 0x00000200, 0x807a7e7a, + 0x00000240, 0x807a7e7a, 0x827b807b, 0xd7610000, 0x00010870, 0xd7610000, 0x00010a71, 0xd7610000, @@ -3726,226 +3790,175 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0x00011677, 0xd7610000, 0x00011a79, 0xd7610000, 0x00011c7e, 0xd7610000, - 0x00011e7f, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xbefe00ff, + 0x00011e7f, 0xbefe00ff, 0x00003fff, 0xbeff0080, 0xee0a407a, 0x000c0000, - 0x00004000, 0xd760007a, + 0x00000000, 0xd760007a, 0x00011d00, 0xd760007b, 0x00011f00, 0xbefe007a, 0xbeff007b, 0xbef4007e, 0x8b75ff7f, 0x0000ffff, - 0x8c75ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x10807fac, 0xbef1007d, - 0xbef00080, 0xb8f30742, + 0xbef1007d, 0xb8f30742, 0x84739973, 0xbefe00c1, 0x857d9973, 0x8b7d817d, 0xbf06817d, 0xbfa20002, 0xbeff0080, 0xbfa00002, - 0xbeff00c1, 0xbfa0000c, - 0xbef600ff, 0x01000000, - 0xc4068070, 0x008ce801, - 0x00008000, 0xc4068070, - 0x008ce802, 0x00010000, - 0xc4068070, 0x008ce803, - 0x00018000, 0xbfa0000b, - 0xbef600ff, 0x01000000, - 0xc4068070, 0x008ce801, - 0x00010000, 0xc4068070, - 0x008ce802, 0x00020000, - 0xc4068070, 0x008ce803, + 0xbeff00c1, 0xbfa0000a, + 0xee0a4074, 0x008c0000, + 0x00008000, 0xee0a4074, + 0x010c0000, 0x00010000, + 0xee0a4074, 0x018c0000, + 0x00018000, 0xbfa00009, + 0xee0a4074, 0x008c0000, + 0x00010000, 0xee0a4074, + 0x010c0000, 0x00020000, + 0xee0a4074, 0x018c0000, 0x00030000, 0xb8f03b05, 0x80708170, 0xbf0d9973, 0xbfa20002, 0x84708970, 0xbfa00001, 0x84708a70, - 0xb8fa1e06, 0x847a8a7a, - 0x80707a70, 0x8070ff70, - 0x00000200, 0xbef600ff, - 0x01000000, 0x7e000280, - 0x7e020280, 0x7e040280, - 0xbe804ec2, 0xbf94fffe, - 0xb8faf804, 0x8b7a847a, - 0x91788478, 0x8c787a78, - 0x917aff6d, 0x80000000, - 0xd7610002, 0x00010071, - 0xd7610002, 0x0001026c, - 0xd7610002, 0x0001047a, - 0xd7610002, 0x0001066e, - 0xd7610002, 0x0001086f, - 0xd7610002, 0x00010a78, - 0xd7610002, 0x00010e7b, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, - 0xd8500000, 0x00000000, + 0x8070ff70, 0x00000200, + 0x7e000280, 0x7e020280, + 0x7e040280, 0xbefd0080, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xbe804ec2, + 0xbf94fffe, 0xb8faf804, + 0x8b7a847a, 0x91788478, + 0x8c787a78, 0xd7610002, + 0x0000fa6c, 0x807d817d, + 0x8b7aff6d, 0x0000ffff, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xd7610002, + 0x0000fa6e, 0x807d817d, + 0xd7610002, 0x0000fa6f, + 0x807d817d, 0xd7610002, + 0x0000fa78, 0x807d817d, 0xb8faf811, 0xd7610002, - 0x00010c7a, 0xb8faf801, - 0xd7610002, 0x0001107a, - 0xb8faf814, 0xd7610002, - 0x0001127a, 0xb8faf815, - 0xd7610002, 0x0001147a, - 0xb8faf812, 0xd7610002, - 0x0001167a, 0xb8faf813, - 0xd7610002, 0x0001187a, + 0x0000fa7a, 0x807d817d, + 0xbefa0080, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xb8f1f801, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f814, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f815, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f812, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8f1f813, 0xd7610002, + 0x0000fa71, 0x807d817d, 0xb8faf802, 0xd7610002, - 0x00011a7a, 0xbefa50c1, - 0xbfc70000, 0xd7610002, - 0x00011c7a, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xbefe00ff, + 0x0000fa7a, 0x807d817d, + 0xbefa50c1, 0xbfc70000, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xbefe00ff, 0x0000ffff, 0xbeff0080, - 0xc4068070, 0x008ce802, + 0x80767074, 0x82778075, + 0xee0a4076, 0x010c0000, 0x00000000, 0xbefe00c1, 0xb8f03b05, 0x80708170, 0xbf0d9973, 0xbfa20002, 0x84708970, 0xbfa00001, - 0x84708a70, 0xb8fa1e06, - 0x847a8a7a, 0x80707a70, - 0xbef600ff, 0x01000000, - 0xbef90080, 0xbefd0080, - 0xbf800000, 0xbe804100, - 0xbe824102, 0xbe844104, - 0xbe864106, 0xbe884108, - 0xbe8a410a, 0xbe8c410c, - 0xbe8e410e, 0xbf068079, - 0xbfa10032, 0xd7610002, - 0x00010000, 0xd7610002, - 0x00010201, 0xd7610002, - 0x00010402, 0xd7610002, - 0x00010603, 0xd7610002, - 0x00010804, 0xd7610002, - 0x00010a05, 0xd7610002, - 0x00010c06, 0xd7610002, - 0x00010e07, 0xd7610002, - 0x00011008, 0xd7610002, - 0x00011209, 0xd7610002, - 0x0001140a, 0xd7610002, - 0x0001160b, 0xd7610002, - 0x0001180c, 0xd7610002, - 0x00011a0d, 0xd7610002, - 0x00011c0e, 0xd7610002, - 0x00011e0f, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0x80799079, - 0xbfa00038, 0xd7610002, - 0x00012000, 0xd7610002, - 0x00012201, 0xd7610002, - 0x00012402, 0xd7610002, - 0x00012603, 0xd7610002, - 0x00012804, 0xd7610002, - 0x00012a05, 0xd7610002, - 0x00012c06, 0xd7610002, - 0x00012e07, 0xd7610002, - 0x00013008, 0xd7610002, - 0x00013209, 0xd7610002, - 0x0001340a, 0xd7610002, - 0x0001360b, 0xd7610002, - 0x0001380c, 0xd7610002, - 0x00013a0d, 0xd7610002, - 0x00013c0e, 0xd7610002, - 0x00013e0f, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0x80799079, - 0xc4068070, 0x008ce802, + 0x84708a70, 0xbef90080, + 0xbefd0080, 0xbf800000, + 0xbe804100, 0xbe824102, + 0xbe844104, 0xbe864106, + 0xbe884108, 0xbe8a410a, + 0xbe8c410c, 0xbe8e410e, + 0xd7610002, 0x0000f200, + 0x80798179, 0xd7610002, + 0x0000f201, 0x80798179, + 0xd7610002, 0x0000f202, + 0x80798179, 0xd7610002, + 0x0000f203, 0x80798179, + 0xd7610002, 0x0000f204, + 0x80798179, 0xd7610002, + 0x0000f205, 0x80798179, + 0xd7610002, 0x0000f206, + 0x80798179, 0xd7610002, + 0x0000f207, 0x80798179, + 0xd7610002, 0x0000f208, + 0x80798179, 0xd7610002, + 0x0000f209, 0x80798179, + 0xd7610002, 0x0000f20a, + 0x80798179, 0xd7610002, + 0x0000f20b, 0x80798179, + 0xd7610002, 0x0000f20c, + 0x80798179, 0xd7610002, + 0x0000f20d, 0x80798179, + 0xd7610002, 0x0000f20e, + 0x80798179, 0xd7610002, + 0x0000f20f, 0x80798179, + 0xbf06a079, 0xbfa10009, + 0x80767074, 0x82778075, + 0xee0a4076, 0x010c0000, 0x00000000, 0x8070ff70, 0x00000080, 0xbef90080, 0x7e040280, 0x807d907d, 0xbf0aff7d, 0x00000060, - 0xbfa2ff88, 0xbe804100, + 0xbfa2ffb9, 0xbe804100, 0xbe824102, 0xbe844104, 0xbe864106, 0xbe884108, 0xbe8a410a, 0xd7610002, - 0x00010000, 0xd7610002, - 0x00010201, 0xd7610002, - 0x00010402, 0xd7610002, - 0x00010603, 0xd7610002, - 0x00010804, 0xd7610002, - 0x00010a05, 0xd7610002, - 0x00010c06, 0xd7610002, - 0x00010e07, 0xd7610002, - 0x00011008, 0xd7610002, - 0x00011209, 0xd7610002, - 0x0001140a, 0xd7610002, - 0x0001160b, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xd8500000, - 0x00000000, 0xc4068070, - 0x008ce802, 0x00000000, + 0x0000f200, 0x80798179, + 0xd7610002, 0x0000f201, + 0x80798179, 0xd7610002, + 0x0000f202, 0x80798179, + 0xd7610002, 0x0000f203, + 0x80798179, 0xd7610002, + 0x0000f204, 0x80798179, + 0xd7610002, 0x0000f205, + 0x80798179, 0xd7610002, + 0x0000f206, 0x80798179, + 0xd7610002, 0x0000f207, + 0x80798179, 0xd7610002, + 0x0000f208, 0x80798179, + 0xd7610002, 0x0000f209, + 0x80798179, 0xd7610002, + 0x0000f20a, 0x80798179, + 0xd7610002, 0x0000f20b, + 0x80798179, 0x80767074, + 0x82778075, 0xee0a4076, + 0x010c0000, 0x00000000, 0xbefe00c1, 0x857d9973, 0x8b7d817d, 0xbf06817d, 0xbfa20002, 0xbeff0080, 0xbfa00001, 0xbeff00c1, 0xb8fb4306, 0x8b7bc17b, - 0xbfa10044, 0x8b7aff6d, - 0x80000000, 0xbfa10041, - 0x847b897b, 0xbef6007b, - 0xb8f03b05, 0x80708170, - 0xbf0d9973, 0xbfa20002, - 0x84708970, 0xbfa00001, - 0x84708a70, 0xb8fa1e06, - 0x847a8a7a, 0x80707a70, + 0xbfa10042, 0x8b7aff6d, + 0x80000000, 0xbfa1003f, + 0x847b897b, 0xb8f03b05, + 0x80708170, 0xbf0d9973, + 0xbfa20002, 0x84708970, + 0xbfa00001, 0x84708a70, 0x8070ff70, 0x00000200, 0x8070ff70, 0x00000080, - 0xbef600ff, 0x01000000, 0xd71f0000, 0x000100c1, 0xd7200000, 0x000200c1, 0x16000084, 0x857d9973, 0x8b7d817d, 0xbf06817d, - 0xbefd0080, 0xbfa20013, + 0xbefd0080, 0xbfa20015, 0xbe8300ff, 0x00000080, 0xbf800000, 0xbf800000, 0xbf800000, 0xd8d80000, 0x01000000, 0xbf8a0000, - 0xc4068070, 0x008ce801, + 0x80767074, 0x82778075, + 0xee0a4076, 0x008c0000, 0x00000000, 0x807d037d, 0x80700370, 0xd5250000, 0x0001ff00, 0x00000080, - 0xbf0a7b7d, 0xbfa2fff3, - 0xbfa00012, 0xbe8300ff, + 0xbf0a7b7d, 0xbfa2fff1, + 0xbfa00014, 0xbe8300ff, 0x00000100, 0xbf800000, 0xbf800000, 0xbf800000, 0xd8d80000, 0x01000000, - 0xbf8a0000, 0xc4068070, - 0x008ce801, 0x00000000, + 0xbf8a0000, 0x80767074, + 0x82778075, 0xee0a4076, + 0x008c0000, 0x00000000, 0x807d037d, 0x80700370, 0xd5250000, 0x0001ff00, 0x00000100, 0xbf0a7b7d, - 0xbfa2fff3, 0xbefe00c1, + 0xbfa2fff1, 0xbefe00c1, 0x857d9973, 0x8b7d817d, 0xbf06817d, 0xbfa20004, 0xbef000ff, 0x00000200, @@ -3955,78 +3968,72 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0x807b817b, 0x847b827b, 0x857d9973, 0x8b7d817d, 0xbf06817d, 0xbfa2001b, - 0xbef600ff, 0x01000000, 0xbefd0084, 0xbf0a7b7d, - 0xbfa10040, 0x7e008700, + 0xbfa10032, 0x7e008700, 0x7e028701, 0x7e048702, - 0x7e068703, 0xc4068070, - 0x008ce800, 0x00000000, - 0xc4068070, 0x008ce801, - 0x00008000, 0xc4068070, - 0x008ce802, 0x00010000, - 0xc4068070, 0x008ce803, + 0x7e068703, 0x80767074, + 0x82778075, 0xee0a4076, + 0x000c0000, 0x00000000, + 0xee0a4076, 0x008c0000, + 0x00008000, 0xee0a4076, + 0x010c0000, 0x00010000, + 0xee0a4076, 0x018c0000, 0x00018000, 0x807d847d, 0x8070ff70, 0x00000200, - 0xbf0a7b7d, 0xbfa2ffeb, - 0xbfa0002a, 0xbef600ff, - 0x01000000, 0xbefd0084, - 0xbf0a7b7d, 0xbfa10015, + 0xbf0a7b7d, 0xbfa2ffe9, + 0xbfa0001a, 0xbefd0084, + 0xbf0a7b7d, 0xbfa10017, 0x7e008700, 0x7e028701, 0x7e048702, 0x7e068703, - 0xc4068070, 0x008ce800, - 0x00000000, 0xc4068070, - 0x008ce801, 0x00010000, - 0xc4068070, 0x008ce802, - 0x00020000, 0xc4068070, - 0x008ce803, 0x00030000, + 0x80767074, 0x82778075, + 0xee0a4076, 0x000c0000, + 0x00000000, 0xee0a4076, + 0x008c0000, 0x00010000, + 0xee0a4076, 0x010c0000, + 0x00020000, 0xee0a4076, + 0x018c0000, 0x00030000, 0x807d847d, 0x8070ff70, 0x00000400, 0xbf0a7b7d, - 0xbfa2ffeb, 0xb8fb1e06, - 0x8b7bc17b, 0xbfa1000d, - 0x847b837b, 0x807b7d7b, - 0xbefe00c1, 0xbeff0080, - 0x7e008700, 0xc4068070, - 0x008ce800, 0x00000000, - 0x807d817d, 0x8070ff70, - 0x00000080, 0xbf0a7b7d, - 0xbfa2fff7, 0xbfa00171, + 0xbfa2ffe9, 0xbfa0014c, 0xbef4007e, 0x8b75ff7f, - 0x0000ffff, 0x8c75ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x10807fac, - 0xbef1007f, 0xb8f20742, - 0x84729972, 0x8b6eff7f, - 0x04000000, 0xbfa1003b, - 0xbefe00c1, 0x857d9972, - 0x8b7d817d, 0xbf06817d, - 0xbfa20002, 0xbeff0080, - 0xbfa00001, 0xbeff00c1, - 0xb8ef4306, 0x8b6fc16f, - 0xbfa10030, 0x846f896f, - 0xbef6006f, 0xb8f83b05, + 0x0000ffff, 0xbef1007f, + 0xb8f20742, 0x84729972, + 0x8b6eff7f, 0x04000000, + 0xbfa10044, 0xbefe00c1, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8ef4306, + 0x8b6fc16f, 0xbfa10039, + 0x846f896f, 0xb8f83b05, 0x80788178, 0xbf0d9972, 0xbfa20002, 0x84788978, 0xbfa00001, 0x84788a78, - 0xb8ee1e06, 0x846e8a6e, - 0x80786e78, 0x8078ff78, - 0x00000200, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0x857d9972, - 0x8b7d817d, 0xbf06817d, - 0xbefd0080, 0xbfa2000d, - 0xc4050078, 0x0080e800, - 0x00000000, 0xbf8a0000, - 0xdac00000, 0x00000000, - 0x807dff7d, 0x00000080, + 0x8078ff78, 0x00000200, 0x8078ff78, 0x00000080, - 0xbf0a6f7d, 0xbfa2fff4, - 0xbfa0000c, 0xc4050078, - 0x0080e800, 0x00000000, - 0xbf8a0000, 0xdac00000, - 0x00000000, 0x807dff7d, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbefd0080, + 0xd71f0001, 0x000100c1, + 0xd7200001, 0x000202c1, + 0x30020282, 0xbfa20012, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xbf8a0000, + 0xd8340000, 0x00000001, + 0xd5250001, 0x0001ff01, + 0x00000080, 0x807dff7d, + 0x00000080, 0x8078ff78, + 0x00000080, 0xbf0a6f7d, + 0xbfa2ffef, 0xbfa00011, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xbf8a0000, + 0xd8340000, 0x00000001, + 0xd5250001, 0x0001ff01, + 0x00000100, 0x807dff7d, 0x00000100, 0x8078ff78, 0x00000100, 0xbf0a6f7d, - 0xbfa2fff4, 0xbef80080, + 0xbfa2ffef, 0xbef80080, 0xbefe00c1, 0x857d9972, 0x8b7d817d, 0xbf06817d, 0xbfa20002, 0xbeff0080, @@ -4034,121 +4041,103 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0xb8ef3b05, 0x806f816f, 0x846f826f, 0x857d9972, 0x8b7d817d, 0xbf06817d, - 0xbfa2002c, 0xbef600ff, - 0x01000000, 0xbeee0078, + 0xbfa2002c, 0xbeee0078, 0x8078ff78, 0x00000200, - 0xbefd0084, 0xbf0a6f7d, - 0xbfa10061, 0xc4050078, - 0x008ce800, 0x00000000, - 0xc4050078, 0x008ce801, - 0x00008000, 0xc4050078, - 0x008ce802, 0x00010000, - 0xc4050078, 0x008ce803, + 0xbefd0084, 0x80767874, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xee0a0076, 0x000c0001, + 0x00008000, 0xee0a0076, + 0x000c0002, 0x00010000, + 0xee0a0076, 0x000c0003, 0x00018000, 0xbf8a0000, 0x7e008500, 0x7e028501, 0x7e048502, 0x7e068503, 0x807d847d, 0x8078ff78, 0x00000200, 0xbf0a6f7d, - 0xbfa2ffea, 0xc405006e, - 0x008ce800, 0x00000000, - 0xc405006e, 0x008ce801, - 0x00008000, 0xc405006e, - 0x008ce802, 0x00010000, - 0xc405006e, 0x008ce803, + 0xbfa2ffe8, 0x80766e74, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xee0a0076, 0x000c0001, + 0x00008000, 0xee0a0076, + 0x000c0002, 0x00010000, + 0xee0a0076, 0x000c0003, 0x00018000, 0xbf8a0000, - 0xbfa0003d, 0xbef600ff, - 0x01000000, 0xbeee0078, + 0xbfa0002d, 0xbeee0078, 0x8078ff78, 0x00000400, 0xbefd0084, 0xbf0a6f7d, - 0xbfa10016, 0xc4050078, - 0x008ce800, 0x00000000, - 0xc4050078, 0x008ce801, - 0x00010000, 0xc4050078, - 0x008ce802, 0x00020000, - 0xc4050078, 0x008ce803, + 0xbfa10018, 0x80767874, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xee0a0076, 0x000c0001, + 0x00010000, 0xee0a0076, + 0x000c0002, 0x00020000, + 0xee0a0076, 0x000c0003, 0x00030000, 0xbf8a0000, 0x7e008500, 0x7e028501, 0x7e048502, 0x7e068503, 0x807d847d, 0x8078ff78, 0x00000400, 0xbf0a6f7d, - 0xbfa2ffea, 0xb8ef1e06, - 0x8b6fc16f, 0xbfa1000f, - 0x846f836f, 0x806f7d6f, - 0xbefe00c1, 0xbeff0080, - 0xc4050078, 0x008ce800, - 0x00000000, 0xbf8a0000, - 0x7e008500, 0x807d817d, - 0x8078ff78, 0x00000080, - 0xbf0a6f7d, 0xbfa2fff6, - 0xbeff00c1, 0xc405006e, - 0x008ce800, 0x00000000, - 0xc405006e, 0x008ce801, - 0x00010000, 0xc405006e, - 0x008ce802, 0x00020000, - 0xc405006e, 0x008ce803, + 0xbfa2ffe8, 0x80766e74, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xee0a0076, 0x000c0001, + 0x00010000, 0xee0a0076, + 0x000c0002, 0x00020000, + 0xee0a0076, 0x000c0003, 0x00030000, 0xbf8a0000, 0xb8f83b05, 0x80788178, 0xbf0d9972, 0xbfa20002, 0x84788978, 0xbfa00001, - 0x84788a78, 0xb8ee1e06, - 0x846e8a6e, 0x80786e78, - 0x8078ff78, 0x00000200, - 0x80f8ff78, 0x00000050, - 0xbef600ff, 0x01000000, - 0xbefd00ff, 0x0000006c, - 0x80f89078, 0xf462403a, - 0xf0000000, 0xbf8a0000, + 0x84788a78, 0x8078ff78, + 0x00000200, 0x80f8ff78, + 0x00000060, 0x80767874, + 0x82778075, 0xbefd00ff, + 0x0000006c, 0xf460403b, + 0xf8000000, 0xbf8a0000, 0x80fd847d, 0xbf800000, 0xbe804300, 0xbe824302, - 0x80f8a078, 0xf462603a, - 0xf0000000, 0xbf8a0000, - 0x80fd887d, 0xbf800000, - 0xbe804300, 0xbe824302, - 0xbe844304, 0xbe864306, - 0x80f8c078, 0xf462803a, - 0xf0000000, 0xbf8a0000, + 0x80f6a076, 0x82f78077, + 0xf460603b, 0xf8000000, + 0xbf8a0000, 0x80fd887d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0xbe844304, + 0xbe864306, 0x80f6c076, + 0x82f78077, 0xf460803b, + 0xf8000000, 0xbf8a0000, 0x80fd907d, 0xbf800000, 0xbe804300, 0xbe824302, 0xbe844304, 0xbe864306, 0xbe884308, 0xbe8a430a, 0xbe8c430c, 0xbe8e430e, - 0xbf06807d, 0xbfa1fff0, + 0xbf06807d, 0xbfa1ffef, 0xb980f801, 0x00000000, 0xb8f83b05, 0x80788178, 0xbf0d9972, 0xbfa20002, 0x84788978, 0xbfa00001, - 0x84788a78, 0xb8ee1e06, - 0x846e8a6e, 0x80786e78, - 0x8078ff78, 0x00000200, - 0xbef600ff, 0x01000000, - 0xbeff0071, 0xf4621bfa, - 0xf0000000, 0x80788478, - 0xf4621b3a, 0xf0000000, - 0x80788478, 0xf4621b7a, - 0xf0000000, 0x80788478, - 0xf4621c3a, 0xf0000000, - 0x80788478, 0xf4621c7a, - 0xf0000000, 0x80788478, - 0xf4621eba, 0xf0000000, - 0x80788478, 0xf4621efa, - 0xf0000000, 0x80788478, - 0xf4621e7a, 0xf0000000, - 0x80788478, 0xf4621cfa, - 0xf0000000, 0x80788478, - 0xf4621bba, 0xf0000000, - 0x80788478, 0xbf8a0000, - 0xb96ef814, 0xf4621bba, - 0xf0000000, 0x80788478, + 0x84788a78, 0x8078ff78, + 0x00000200, 0x80767874, + 0x82778075, 0xbeff0071, + 0xf4601bfb, 0xf8000000, + 0xf4601b3b, 0xf8000004, + 0xf4601b7b, 0xf8000008, + 0xf4601c3b, 0xf800000c, + 0xf4601c7b, 0xf8000010, + 0xf4601ebb, 0xf8000014, + 0xf4601efb, 0xf8000018, + 0xf4601e7b, 0xf800001c, + 0xf4601cfb, 0xf8000020, + 0xf4601bbb, 0xf8000024, + 0xbf8a0000, 0xb96ef814, + 0xf4601bbb, 0xf8000028, 0xbf8a0000, 0xb96ef815, - 0xf4621bba, 0xf0000000, - 0x80788478, 0xbf8a0000, - 0xb96ef812, 0xf4621bba, - 0xf0000000, 0x80788478, + 0xf4601bbb, 0xf800002c, + 0xbf8a0000, 0xb96ef812, + 0xf4601bbb, 0xf8000030, 0xbf8a0000, 0xb96ef813, 0x8b6eff7f, 0x04000000, - 0xbfa1000d, 0x80788478, - 0xf4621bba, 0xf0000000, - 0x80788478, 0xbf8a0000, + 0xbfa1000b, 0xf4601bbb, + 0xf8000038, 0xbf8a0000, 0xbf0d806e, 0xbfa10006, 0x856e906e, 0x8b6e6e6e, 0xbfa10003, 0xbe804ec1, @@ -4161,61 +4150,82 @@ static const uint32_t cwsr_trap_gfx12_hex[] = { 0x806e816e, 0xbf0d9972, 0xbfa20002, 0x846e896e, 0xbfa00001, 0x846e8a6e, - 0xb8ef1e06, 0x846f8a6f, - 0x806e6f6e, 0x806eff6e, - 0x00000200, 0x806e746e, - 0x826f8075, 0x8b6fff6f, - 0x0000ffff, 0xf4605c37, - 0xf8000050, 0xf4605d37, - 0xf8000060, 0xf4601e77, - 0xf8000074, 0xbf8a0000, - 0x8b6dff6d, 0x0000ffff, - 0x8bfe7e7e, 0x8bea6a6a, - 0x936eff77, 0x0002001a, - 0xb96ef81a, 0xb97af804, + 0x806eff6e, 0x00000240, + 0x806e746e, 0x826f8075, + 0xf4605c37, 0xf8000010, + 0xf4605d37, 0xf8000020, + 0xf4601e77, 0xf8000034, + 0xbf8a0000, 0x8b6dff6d, + 0x0000ffff, 0x8bfe7e7e, + 0x8bea6a6a, 0x936eff77, + 0x0002001a, 0xb96ef81a, + 0xb97af804, 0xbe804ec2, + 0xbf94fffe, 0xbe804a6c, 0xbe804ec2, 0xbf94fffe, - 0xbe804a6c, 0xbe804ec2, - 0xbf94fffe, 0xbfb10000, + 0xbfb10000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, 0xbf9f0000, - 0xbf9f0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { - 0xbf820001, 0xbf8202ca, + 0xbf820001, 0xbf8202fa, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, - 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0x866eff7b, 0x04000400, + 0xbf06ff6e, 0x04000400, + 0xbf840003, 0xbefb189a, + 0xba7f0683, 0x00000000, + 0xbf0c8a7b, 0xbf850007, + 0xbf0c986d, 0xbf850005, + 0xbefb1896, 0xba7f0583, + 0x00000000, 0x896dff6d, + 0x01ff0000, 0x866eff78, + 0x00002000, 0xbf84000a, + 0xbf0d986d, 0xbf850023, + 0xbf0d9a7b, 0xbf850021, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, + 0xbf85006f, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, + 0x866eff7b, 0x03800900, + 0xbf850017, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, + 0x866e6f6e, 0xbf85000c, + 0xbf0d986d, 0xbf850003, 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf850007, 0xbf0d986d, + 0xbf850006, 0xbf0d9a7b, + 0xbf850004, 0x866eff7b, + 0x00000400, 0xbf850052, + 0xbeed1a9d, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031cfd, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8e739773, 0x8979ff79, + 0x03800000, 0x87797379, + 0xbf0d986d, 0xbf840008, + 0xbf0d9879, 0xbf840002, + 0xbeed1a9d, 0xbf820004, + 0x896dff6d, 0x01ff0000, + 0xba7f0583, 0x00000000, + 0xb8f3f803, 0xbf0d9a73, + 0xbf840006, 0xbf0d9979, + 0xbf840002, 0xbeed1a9d, + 0xbf820002, 0xba7f0683, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840013, + 0xbef91898, 0xbef91899, + 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -4664,3 +4674,694 @@ static const uint32_t cwsr_trap_gfx9_5_0_hex[] = { 0xbf8a0000, 0xbe801f6c, 0xbf9b0000, 0x00000000, }; + +static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { + 0xbfa00001, 0xbfa003cb, + 0xb0804009, 0xb8f8f804, + 0x9178ff78, 0x00008c00, + 0xb8fbf811, 0xbf0c857b, + 0xbfa20003, 0xbefb1087, + 0xb98001d1, 0x00000000, + 0x8b6eff78, 0x00004000, + 0xbfa10007, 0xbf0d877b, + 0xbfa20018, 0x8b6ea07b, + 0xbfa200e3, 0xbf830010, + 0xb8fbf811, 0xbfa0fffb, + 0x8b6eff7b, 0x00000bd0, + 0xbfa20010, 0xb8eef812, + 0x8b6f8f7b, 0xbfa10002, + 0x8c6eff6e, 0x00000080, + 0xb8eff813, 0x8b6e6e6f, + 0xbfa20008, 0x8b6eff6d, + 0xf0000000, 0xbfa20005, + 0x8b6fff6f, 0x00000200, + 0xbfa20002, 0x8b6ea07b, + 0xbfa200cd, 0x9177ff77, + 0x007fc000, 0xb8fa04a1, + 0x847a967a, 0x8c777a77, + 0xb8fa0421, 0x847a957a, + 0x8c777a77, 0xb8fa3021, + 0x847a8e7a, 0x8c777a77, + 0xb980f821, 0x00000000, + 0xbeef007b, 0xbefa4d82, + 0xbf8a0000, 0x84fa887a, + 0xbf0d987b, 0xbfa10002, + 0x8c7bff7b, 0xfe000000, + 0xf4601bbd, 0xf8000010, + 0xbf8a0000, 0x846e976e, + 0x9177ff77, 0x01800000, + 0x8c776e77, 0xbf0d876f, + 0xbfa10006, 0xbf0d8e78, + 0xbfa20002, 0xbf0d9877, + 0xbfa20002, 0xb98001d1, + 0x00000000, 0xf4603bbd, + 0xf8000000, 0xbf8a0000, + 0xf4603ebd, 0xf8000008, + 0xbf8a0000, 0x8bee6e6e, + 0xbfa10001, 0xbe80486e, + 0x8b6eff6d, 0xf0000000, + 0xbfa20009, 0xb8eef811, + 0x8b6eff6e, 0x00000080, + 0xbfa20007, 0x8c78ff78, + 0x00004000, 0x80ec886c, + 0x82ed806d, 0xbfa00002, + 0x806c846c, 0x826d806d, + 0x8b6dff6d, 0x01ffffff, + 0xb8fbf811, 0xbf0d847b, + 0xbfa20081, 0xf4003eb6, + 0xf8000000, 0xbfc70000, + 0xf4003bb6, 0xf8000008, + 0x8b76ff7a, 0x80000000, + 0xbfa20027, 0x9376ff7a, + 0x00060019, 0x81f9a376, + 0xbf0b8179, 0xbfa2006e, + 0x81f9ac76, 0xbf0b8179, + 0xbfa20068, 0x81f9b776, + 0xbf0b8179, 0xbfa20065, + 0x8b76ff7a, 0x000001ff, + 0xbf06ff76, 0x000000fe, + 0xbfa20063, 0xbf06ff76, + 0x000000ff, 0xbfa2005d, + 0xbf06ff76, 0x000000fa, + 0xbfa2005a, 0x81f9ff76, + 0x000000e9, 0xbf0b8179, + 0xbfa20056, 0x8b76ff7b, + 0xffff0000, 0xbf06ff76, + 0xbf860000, 0xbfa1005a, + 0x9376ff7b, 0x0002000e, + 0x8b79ff7b, 0x00003f00, + 0x85798679, 0x8c767976, + 0xb9763b01, 0xbfa00052, + 0x8b76ff7a, 0xfc000000, + 0xbf06ff76, 0xd4000000, + 0xbfa20019, 0xbf06ff76, + 0xc8000000, 0xbfa2002d, + 0x8b76ff7a, 0xff000000, + 0xbf06ff76, 0xcf000000, + 0xbfa2003f, 0x8b79ff7a, + 0xffff0000, 0xbf06ff79, + 0xcc330000, 0xbfa2003d, + 0xbf06ff79, 0xcc880000, + 0xbfa2003a, 0xbf06ff79, + 0xcc350000, 0xbfa2003a, + 0xbf06ff79, 0xcc3a0000, + 0xbfa20037, 0xbf06ff76, + 0xcc000000, 0xbfa10034, + 0x8b76ff7b, 0x000001ff, + 0xbf06ff76, 0x000000ff, + 0xbfa20029, 0xbf06ff76, + 0x000000fa, 0xbfa20026, + 0x81f6ff76, 0x000000e9, + 0xbf0b8176, 0xbfa20022, + 0x8b76ff7b, 0x0003fe00, + 0xbf06ff76, 0x0001fe00, + 0xbfa2001d, 0x8b76ff7b, + 0x07fc0000, 0xbf06ff76, + 0x03fc0000, 0xbfa20018, + 0xbfa00014, 0x9376ff7a, + 0x00040016, 0x81f68176, + 0xbf0b8176, 0xbfa20012, + 0x9376ff7a, 0x00050011, + 0x81f68176, 0xbf0b8176, + 0xbfa2000d, 0x8b76ff7a, + 0x000001ff, 0xbf06ff76, + 0x000000ff, 0xbfa20008, + 0x8b76ff7b, 0x000001ff, + 0xbf06ff76, 0x000000ff, + 0xbfa20003, 0xbfc70000, + 0xbefb006e, 0xbfa0ffa7, + 0xbfc70000, 0xbefb006f, + 0xbfa0ffa4, 0x80ec886c, + 0x82ed806d, 0xbfa0fff7, + 0xbfc70000, 0x857a9677, + 0xb97a04a1, 0x857a9577, + 0xb97a0421, 0x857a8e77, + 0xb97a3021, 0x8bfe7e7e, + 0x8bea6a6a, 0x85788978, + 0xb9783244, 0xbe804a6c, + 0xb8faf802, 0xbf0d987a, + 0xbfa10001, 0xbfb00000, + 0x8b6dff6d, 0x01ffffff, + 0xbefa0080, 0xb97a0151, + 0x9177ff77, 0x007fc000, + 0xb8fa04a1, 0x847a967a, + 0x8c777a77, 0xb8fa0421, + 0x847a957a, 0x8c777a77, + 0xb8fa3021, 0x847a8e7a, + 0x8c777a77, 0xb980f821, + 0x00000000, 0xbf0d847b, + 0xbfa20081, 0xf4003eb6, + 0xf8000000, 0xbfc70000, + 0xf4003bb6, 0xf8000008, + 0x8b76ff7a, 0x80000000, + 0xbfa20027, 0x9376ff7a, + 0x00060019, 0x81f9a376, + 0xbf0b8179, 0xbfa2006e, + 0x81f9ac76, 0xbf0b8179, + 0xbfa20068, 0x81f9b776, + 0xbf0b8179, 0xbfa20065, + 0x8b76ff7a, 0x000001ff, + 0xbf06ff76, 0x000000fe, + 0xbfa20063, 0xbf06ff76, + 0x000000ff, 0xbfa2005d, + 0xbf06ff76, 0x000000fa, + 0xbfa2005a, 0x81f9ff76, + 0x000000e9, 0xbf0b8179, + 0xbfa20056, 0x8b76ff7b, + 0xffff0000, 0xbf06ff76, + 0xbf860000, 0xbfa1005a, + 0x9376ff7b, 0x0002000e, + 0x8b79ff7b, 0x00003f00, + 0x85798679, 0x8c767976, + 0xb9763b01, 0xbfa00052, + 0x8b76ff7a, 0xfc000000, + 0xbf06ff76, 0xd4000000, + 0xbfa20019, 0xbf06ff76, + 0xc8000000, 0xbfa2002d, + 0x8b76ff7a, 0xff000000, + 0xbf06ff76, 0xcf000000, + 0xbfa2003f, 0x8b79ff7a, + 0xffff0000, 0xbf06ff79, + 0xcc330000, 0xbfa2003d, + 0xbf06ff79, 0xcc880000, + 0xbfa2003a, 0xbf06ff79, + 0xcc350000, 0xbfa2003a, + 0xbf06ff79, 0xcc3a0000, + 0xbfa20037, 0xbf06ff76, + 0xcc000000, 0xbfa10034, + 0x8b76ff7b, 0x000001ff, + 0xbf06ff76, 0x000000ff, + 0xbfa20029, 0xbf06ff76, + 0x000000fa, 0xbfa20026, + 0x81f6ff76, 0x000000e9, + 0xbf0b8176, 0xbfa20022, + 0x8b76ff7b, 0x0003fe00, + 0xbf06ff76, 0x0001fe00, + 0xbfa2001d, 0x8b76ff7b, + 0x07fc0000, 0xbf06ff76, + 0x03fc0000, 0xbfa20018, + 0xbfa00014, 0x9376ff7a, + 0x00040016, 0x81f68176, + 0xbf0b8176, 0xbfa20012, + 0x9376ff7a, 0x00050011, + 0x81f68176, 0xbf0b8176, + 0xbfa2000d, 0x8b76ff7a, + 0x000001ff, 0xbf06ff76, + 0x000000ff, 0xbfa20008, + 0x8b76ff7b, 0x000001ff, + 0xbf06ff76, 0x000000ff, + 0xbfa20003, 0xbfc70000, + 0xbefb006e, 0xbfa0ffa7, + 0xbfc70000, 0xbefb006f, + 0xbfa0ffa4, 0x80ec886c, + 0x82ed806d, 0xbfa0fff7, + 0xbfc70000, 0xbeee007e, + 0xbeef007f, 0xbefe0180, + 0xbefe4d84, 0xbf8a0000, + 0x8b7aff7f, 0x04000000, + 0x847a857a, 0x8c6d7a6d, + 0xb8eff822, 0xb980f822, + 0x00000000, 0xb8fa2b01, + 0x847a997a, 0x8c6d7a6d, + 0xbefa0080, 0xb97a2b01, + 0xbefa007e, 0x8b7bff7f, + 0x01ffffff, 0xbefe00c1, + 0xbeff00c1, 0xee0a407a, + 0x000c0000, 0x00000000, + 0x7e000280, 0xbefe007a, + 0xbeff007b, 0xb8fb0742, + 0x847b997b, 0xb8fa3b05, + 0x807a817a, 0xbf0d997b, + 0xbfa20002, 0x847a897a, + 0xbfa00001, 0x847a8a7a, + 0x8b7bff7f, 0x01ffffff, + 0x807aff7a, 0x000001c0, + 0x807a7e7a, 0x827b807b, + 0xd7610000, 0x00010870, + 0xd7610000, 0x00010a71, + 0xd7610000, 0x00010c72, + 0xd7610000, 0x00010e73, + 0xd7610000, 0x00011074, + 0xd7610000, 0x00011275, + 0xd7610000, 0x00011476, + 0xd7610000, 0x00011677, + 0xd7610000, 0x00011a79, + 0xd7610000, 0x00011c7e, + 0xd7610000, 0x00011e7f, + 0xbefe00ff, 0x00003fff, + 0xbeff0080, 0xee0a407a, + 0x000c0000, 0x00000000, + 0xd760007a, 0x00011d00, + 0xd760007b, 0x00011f00, + 0xbefe007a, 0xbeff007b, + 0xbef4007e, 0x8b75ff7f, + 0x01ffffff, 0xbef1007d, + 0xb8f30742, 0x84739973, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20002, 0xbeff0080, + 0xbfa00002, 0xbeff00c1, + 0xbfa0000a, 0xee0a4074, + 0x008c0000, 0x00008000, + 0xee0a4074, 0x010c0000, + 0x00010000, 0xee0a4074, + 0x018c0000, 0x00018000, + 0xbfa00009, 0xee0a4074, + 0x008c0000, 0x00010000, + 0xee0a4074, 0x010c0000, + 0x00020000, 0xee0a4074, + 0x018c0000, 0x00030000, + 0xb8f03b05, 0x80708170, + 0xbf0d9973, 0xbfa20002, + 0x84708970, 0xbfa00001, + 0x84708a70, 0x8070ff70, + 0x00000200, 0x7e000280, + 0x7e020280, 0x7e040280, + 0xbefd0080, 0xd7610002, + 0x0000fa71, 0x807d817d, + 0xb8faf802, 0xbf0c8b7a, + 0xbfa20003, 0xbe804fc2, + 0xbf94fffe, 0xbfa10001, + 0xbe804ec4, 0xbf94fffc, + 0xbefa4c88, 0xbfc70000, + 0xbf0c807a, 0xbfa20006, + 0x9371ff7a, 0x00070004, + 0x937aff7a, 0x00070010, + 0xbf06717a, 0xbfa2fff6, + 0xb8faf804, 0x8b7aff7a, + 0x0001000c, 0x9178ff78, + 0x0001000c, 0x8c787a78, + 0xd7610002, 0x0000fa6c, + 0x807d817d, 0x8b7aff6d, + 0x01ffffff, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xd7610002, 0x0000fa6e, + 0x807d817d, 0xbefa0080, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xd7610002, + 0x0000fa78, 0x807d817d, + 0xb8faf811, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xd7610002, 0x0000fa6f, + 0x807d817d, 0xb8f1f801, + 0x937aff6d, 0x00060019, + 0x847a8c7a, 0x8c717a71, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f814, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f815, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f812, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8f1f813, + 0xd7610002, 0x0000fa71, + 0x807d817d, 0xb8faf802, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xbefa50c1, + 0xbfc70000, 0xd7610002, + 0x0000fa7a, 0x807d817d, + 0xbefa4c88, 0xbfc70000, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xb8faf81a, + 0xd7610002, 0x0000fa7a, + 0x807d817d, 0xbefe00c1, + 0xbeff0080, 0x80767074, + 0x82778075, 0xee0a4076, + 0x010c0000, 0x00000000, + 0xbefe00c1, 0x7e040280, + 0xbefa5081, 0xbfc70000, + 0xd7610002, 0x0001007a, + 0xbefa5082, 0xbfc70000, + 0xd7610002, 0x0001027a, + 0xbefa5083, 0xbfc70000, + 0xd7610002, 0x0001047a, + 0xbefa5084, 0xbfc70000, + 0xd7610002, 0x0001067a, + 0xbefa5085, 0xbfc70000, + 0xd7610002, 0x0001087a, + 0xbefa5086, 0xbfc70000, + 0xd7610002, 0x00010a7a, + 0xbefa5087, 0xbfc70000, + 0xd7610002, 0x00010c7a, + 0xbefa5088, 0xbfc70000, + 0xd7610002, 0x00010e7a, + 0xbefa5089, 0xbfc70000, + 0xd7610002, 0x0001107a, + 0xbefa508a, 0xbfc70000, + 0xd7610002, 0x0001127a, + 0xbefa508b, 0xbfc70000, + 0xd7610002, 0x0001147a, + 0xbefa508c, 0xbfc70000, + 0xd7610002, 0x0001167a, + 0xbefa508d, 0xbfc70000, + 0xd7610002, 0x0001187a, + 0xbefa508e, 0xbfc70000, + 0xd7610002, 0x00011a7a, + 0xbefa508f, 0xbfc70000, + 0xd7610002, 0x00011c7a, + 0xbefa5090, 0xbfc70000, + 0xd7610002, 0x00011e7a, + 0xee0a4076, 0x010c0000, + 0x00008000, 0xb8f03b05, + 0x80708170, 0xbf0d9973, + 0xbfa20002, 0x84708970, + 0xbfa00001, 0x84708a70, + 0xbef90080, 0xbefd0080, + 0xbf800000, 0xbe804100, + 0xbe824102, 0xbe844104, + 0xbe864106, 0xbe884108, + 0xbe8a410a, 0xbe8c410c, + 0xbe8e410e, 0xd7610002, + 0x0000f200, 0x80798179, + 0xd7610002, 0x0000f201, + 0x80798179, 0xd7610002, + 0x0000f202, 0x80798179, + 0xd7610002, 0x0000f203, + 0x80798179, 0xd7610002, + 0x0000f204, 0x80798179, + 0xd7610002, 0x0000f205, + 0x80798179, 0xd7610002, + 0x0000f206, 0x80798179, + 0xd7610002, 0x0000f207, + 0x80798179, 0xd7610002, + 0x0000f208, 0x80798179, + 0xd7610002, 0x0000f209, + 0x80798179, 0xd7610002, + 0x0000f20a, 0x80798179, + 0xd7610002, 0x0000f20b, + 0x80798179, 0xd7610002, + 0x0000f20c, 0x80798179, + 0xd7610002, 0x0000f20d, + 0x80798179, 0xd7610002, + 0x0000f20e, 0x80798179, + 0xd7610002, 0x0000f20f, + 0x80798179, 0xbf06a079, + 0xbfa10009, 0x80767074, + 0x82778075, 0xee0a4076, + 0x010c0000, 0x00000000, + 0x8070ff70, 0x00000080, + 0xbef90080, 0x7e040280, + 0x807d907d, 0xbf0aff7d, + 0x00000060, 0xbfa2ffb9, + 0xbe804100, 0xbe824102, + 0xbe844104, 0xbe864106, + 0xbe884108, 0xbe8a410a, + 0xd7610002, 0x0000f200, + 0x80798179, 0xd7610002, + 0x0000f201, 0x80798179, + 0xd7610002, 0x0000f202, + 0x80798179, 0xd7610002, + 0x0000f203, 0x80798179, + 0xd7610002, 0x0000f204, + 0x80798179, 0xd7610002, + 0x0000f205, 0x80798179, + 0xd7610002, 0x0000f206, + 0x80798179, 0xd7610002, + 0x0000f207, 0x80798179, + 0xd7610002, 0x0000f208, + 0x80798179, 0xd7610002, + 0x0000f209, 0x80798179, + 0xd7610002, 0x0000f20a, + 0x80798179, 0xd7610002, + 0x0000f20b, 0x80798179, + 0xbefe00ff, 0x0000ffff, + 0x80767074, 0x82778075, + 0xee0a4076, 0x010c0000, + 0x00000000, 0xbefe00c1, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8fb4306, + 0x8b7bc17b, 0xbfa10042, + 0x8b7aff6d, 0x80000000, + 0xbfa1003f, 0x847b8a7b, + 0xb8f03b05, 0x80708170, + 0xbf0d9973, 0xbfa20002, + 0x84708970, 0xbfa00001, + 0x84708a70, 0x8070ff70, + 0x00000200, 0x8070ff70, + 0x00000200, 0xd71f0000, + 0x000100c1, 0xd7200000, + 0x000200c1, 0x16000084, + 0x857d9973, 0x8b7d817d, + 0xbf06817d, 0xbefd0080, + 0xbfa20015, 0xbe8300ff, + 0x00000080, 0xbf800000, + 0xbf800000, 0xbf800000, + 0xd8d80000, 0x01000000, + 0xbf8a0000, 0x80767074, + 0x82778075, 0xee0a4076, + 0x008c0000, 0x00000000, + 0x807d037d, 0x80700370, + 0xd5250000, 0x0001ff00, + 0x00000080, 0xbf0a7b7d, + 0xbfa2fff1, 0xbfa00014, + 0xbe8300ff, 0x00000100, + 0xbf800000, 0xbf800000, + 0xbf800000, 0xd8d80000, + 0x01000000, 0xbf8a0000, + 0x80767074, 0x82778075, + 0xee0a4076, 0x008c0000, + 0x00000000, 0x807d037d, + 0x80700370, 0xd5250000, + 0x0001ff00, 0x00000100, + 0xbf0a7b7d, 0xbfa2fff1, + 0xbefe00c1, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa20004, 0xbef000ff, + 0x00000200, 0xbeff0080, + 0xbfa00003, 0xbef000ff, + 0x00000400, 0xbeff00c1, + 0xb8fb3b05, 0x807b817b, + 0x847b827b, 0x857d9973, + 0x8b7d817d, 0xbf06817d, + 0xbfa2001b, 0xbefd0084, + 0xbf0a7b7d, 0xbfa10032, + 0x7e008700, 0x7e028701, + 0x7e048702, 0x7e068703, + 0x80767074, 0x82778075, + 0xee0a4076, 0x000c0000, + 0x00000000, 0xee0a4076, + 0x008c0000, 0x00008000, + 0xee0a4076, 0x010c0000, + 0x00010000, 0xee0a4076, + 0x018c0000, 0x00018000, + 0x807d847d, 0x8070ff70, + 0x00000200, 0xbf0a7b7d, + 0xbfa2ffe9, 0xbfa0001a, + 0xbefd0084, 0xbf0a7b7d, + 0xbfa10017, 0x7e008700, + 0x7e028701, 0x7e048702, + 0x7e068703, 0x80767074, + 0x82778075, 0xee0a4076, + 0x000c0000, 0x00000000, + 0xee0a4076, 0x008c0000, + 0x00010000, 0xee0a4076, + 0x010c0000, 0x00020000, + 0xee0a4076, 0x018c0000, + 0x00030000, 0x807d847d, + 0x8070ff70, 0x00000400, + 0xbf0a7b7d, 0xbfa2ffe9, + 0xbfa00184, 0xbef4007e, + 0x8b75ff7f, 0x01ffffff, + 0xbef1007f, 0xb8f20742, + 0x84729972, 0x8b6eff7f, + 0x04000000, 0xbfa10044, + 0xbefe00c1, 0x857d9972, + 0x8b7d817d, 0xbf06817d, + 0xbfa20002, 0xbeff0080, + 0xbfa00001, 0xbeff00c1, + 0xb8ef4306, 0x8b6fc16f, + 0xbfa10039, 0x846f8a6f, + 0xb8f83b05, 0x80788178, + 0xbf0d9972, 0xbfa20002, + 0x84788978, 0xbfa00001, + 0x84788a78, 0x8078ff78, + 0x00000200, 0x8078ff78, + 0x00000200, 0x857d9972, + 0x8b7d817d, 0xbf06817d, + 0xbefd0080, 0xd71f0001, + 0x000100c1, 0xd7200001, + 0x000202c1, 0x30020282, + 0xbfa20012, 0x80767874, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xbf8a0000, 0xd8340000, + 0x00000001, 0xd5250001, + 0x0001ff01, 0x00000080, + 0x807dff7d, 0x00000080, + 0x8078ff78, 0x00000080, + 0xbf0a6f7d, 0xbfa2ffef, + 0xbfa00011, 0x80767874, + 0x82778075, 0xee0a0076, + 0x000c0000, 0x00000000, + 0xbf8a0000, 0xd8340000, + 0x00000001, 0xd5250001, + 0x0001ff01, 0x00000100, + 0x807dff7d, 0x00000100, + 0x8078ff78, 0x00000100, + 0xbf0a6f7d, 0xbfa2ffef, + 0xbef80080, 0xbefe00c1, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa20002, + 0xbeff0080, 0xbfa00001, + 0xbeff00c1, 0xb8ef3b05, + 0x806f816f, 0x846f826f, + 0x857d9972, 0x8b7d817d, + 0xbf06817d, 0xbfa2002c, + 0xbeee0078, 0x8078ff78, + 0x00000200, 0xbefd0084, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00008000, + 0xee0a0076, 0x000c0002, + 0x00010000, 0xee0a0076, + 0x000c0003, 0x00018000, + 0xbf8a0000, 0x7e008500, + 0x7e028501, 0x7e048502, + 0x7e068503, 0x807d847d, + 0x8078ff78, 0x00000200, + 0xbf0a6f7d, 0xbfa2ffe8, + 0x80766e74, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00008000, + 0xee0a0076, 0x000c0002, + 0x00010000, 0xee0a0076, + 0x000c0003, 0x00018000, + 0xbf8a0000, 0xbfa0002d, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefd0084, + 0xbf0a6f7d, 0xbfa10018, + 0x80767874, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00010000, + 0xee0a0076, 0x000c0002, + 0x00020000, 0xee0a0076, + 0x000c0003, 0x00030000, + 0xbf8a0000, 0x7e008500, + 0x7e028501, 0x7e048502, + 0x7e068503, 0x807d847d, + 0x8078ff78, 0x00000400, + 0xbf0a6f7d, 0xbfa2ffe8, + 0x80766e74, 0x82778075, + 0xee0a0076, 0x000c0000, + 0x00000000, 0xee0a0076, + 0x000c0001, 0x00010000, + 0xee0a0076, 0x000c0002, + 0x00020000, 0xee0a0076, + 0x000c0003, 0x00030000, + 0xbf8a0000, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0x8078ff78, 0x00000200, + 0x80f8ff78, 0x00000060, + 0x80767874, 0x82778075, + 0xbefd00ff, 0x0000006c, + 0xf460403b, 0xf8000000, + 0xbf8a0000, 0x80fd847d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0x80f6a076, + 0x82f78077, 0xf460603b, + 0xf8000000, 0xbf8a0000, + 0x80fd887d, 0xbf800000, + 0xbe804300, 0xbe824302, + 0xbe844304, 0xbe864306, + 0x80f6c076, 0x82f78077, + 0xf460803b, 0xf8000000, + 0xbf8a0000, 0x80fd907d, + 0xbf800000, 0xbe804300, + 0xbe824302, 0xbe844304, + 0xbe864306, 0xbe884308, + 0xbe8a430a, 0xbe8c430c, + 0xbe8e430e, 0xbf06807d, + 0xbfa1ffef, 0xb980f801, + 0x00000000, 0xb8f83b05, + 0x80788178, 0xbf0d9972, + 0xbfa20002, 0x84788978, + 0xbfa00001, 0x84788a78, + 0x8078ff78, 0x00000200, + 0x80767874, 0x82778075, + 0xbeff0071, 0xf4601bfb, + 0xf8000000, 0xf4601b3b, + 0xf8000004, 0xf4601b7b, + 0xf8000008, 0xf4601c3b, + 0xf800000c, 0xf4601c7b, + 0xf8000010, 0xf4601ebb, + 0xf8000014, 0xf4601efb, + 0xf8000018, 0xf4601e7b, + 0xf800001c, 0xf4601cfb, + 0xf8000020, 0xf4601bbb, + 0xf8000024, 0xbf8a0000, + 0xb96ef814, 0xf4601bbb, + 0xf8000028, 0xbf8a0000, + 0xb96ef815, 0xf4601bbb, + 0xf800002c, 0xbf8a0000, + 0xb96ef812, 0xf4601bbb, + 0xf8000030, 0xbf8a0000, + 0xb96ef813, 0x8b6eff7f, + 0x04000000, 0xbfa10022, + 0xf4601bbb, 0xf8000038, + 0xbf8a0000, 0xbf0d806e, + 0xbfa1001d, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804ec1, 0x816ec16e, + 0xbfa0fffb, 0xbef800ff, + 0x00000080, 0xbefd0081, + 0xf4601bbb, 0xf0000000, + 0xbfc70000, 0x80788478, + 0x937eff6e, 0x00070004, + 0x847e907e, 0x8c7d7e7d, + 0xbe80517d, 0x917dff7d, + 0x007f0000, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804e7d, 0x816ec16e, + 0xbfa0fffb, 0x807d817d, + 0xbf08907d, 0xbfa1ffec, + 0xf4601bbb, 0xf800003c, + 0xbfc70000, 0xbf0d806e, + 0xbfa1000c, 0xbf0d9a7f, + 0xbfa10002, 0xbf068180, + 0xbe804fc4, 0xbf94fffc, + 0xbfa10006, 0x856e906e, + 0x8b6e6e6e, 0xbfa10003, + 0xbe804ec3, 0x816ec16e, + 0xbfa0fffb, 0xf4601bbb, + 0xf8000040, 0xbfc70000, + 0xb96ef81a, 0xbefd006f, + 0xbefe0070, 0xbeff0071, + 0xb979f822, 0xb97b2011, + 0x857b867b, 0xb97b0191, + 0x857b827b, 0xb97bba11, + 0xb973f801, 0xb8ee3b05, + 0x806e816e, 0xbf0d9972, + 0xbfa20002, 0x846e896e, + 0xbfa00001, 0x846e8a6e, + 0x806eff6e, 0x000001c0, + 0x806e746e, 0x826f8075, + 0xf4605c37, 0xf8000010, + 0xf4605d37, 0xf8000020, + 0xf4601e77, 0xf8000034, + 0xbf8a0000, 0x856e9677, + 0xb96e04a1, 0x856e9577, + 0xb96e0421, 0x856e8e77, + 0xb96e3021, 0x8b6dff6d, + 0x01ffffff, 0x8bfe7e7e, + 0x8bea6a6a, 0xb97af804, + 0xb8eef802, 0xbf0c8b6e, + 0xbfa20003, 0xbe804fc2, + 0xbf94fffe, 0xbfa10001, + 0xbe804ec4, 0xbf94fffc, + 0x857a897a, 0xb97a0244, + 0xbe804a6c, 0xb8eef802, + 0xbf0c8b6e, 0xbfa20003, + 0xbe804fc2, 0xbf94fffe, + 0xbfa10001, 0xbe804ec4, + 0xbf94fffc, 0xbfb10000, + 0xbf9f0000, 0xbf9f0000, + 0xbf9f0000, 0xbf9f0000, + 0xbf9f0000, 0x00000000, +}; diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm index 07999b4649ded..0fe0a6b0af37e 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm @@ -28,11 +28,31 @@ */ #define CHIP_GFX12 37 +#define CHIP_GC_12_0_3 38 + +#define HAVE_XNACK (ASIC_FAMILY == CHIP_GC_12_0_3) +#define HAVE_57BIT_ADDRESS (ASIC_FAMILY == CHIP_GC_12_0_3) +#define HAVE_BANKED_VGPRS (ASIC_FAMILY == CHIP_GC_12_0_3) +#define NUM_NAMED_BARRIERS (ASIC_FAMILY == CHIP_GC_12_0_3 ? 0x10 : 0) +#define HAVE_CLUSTER_BARRIER (ASIC_FAMILY == CHIP_GC_12_0_3) +#define CLUSTER_BARRIER_SERIALIZE_WORKAROUND (ASIC_FAMILY == CHIP_GC_12_0_3) +#define RELAXED_SCHEDULING_IN_TRAP (ASIC_FAMILY == CHIP_GFX12) +#define HAVE_INSTRUCTION_FIXUP (ASIC_FAMILY == CHIP_GC_12_0_3) #define SINGLE_STEP_MISSED_WORKAROUND 1 //workaround for lost TRAP_AFTER_INST exception when SAVECTX raised #define HAVE_VALU_SGPR_HAZARD (ASIC_FAMILY == CHIP_GFX12) +#define HAVE_HT_TRAP_ID_WA (ASIC_FAMILY == CHIP_GFX12) +#define WAVE32_ONLY (ASIC_FAMILY == CHIP_GC_12_0_3) +#define SAVE_TTMPS_IN_SGPR_BLOCK (ASIC_FAMILY >= CHIP_GC_12_0_3) + +#if HAVE_XNACK && !WAVE32_ONLY +# error +#endif -var SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK = 0x4 +#define ADDRESS_HI32_NUM_BITS ((HAVE_57BIT_ADDRESS ? 57 : 48) - 32) +#define ADDRESS_HI32_MASK ((1 << ADDRESS_HI32_NUM_BITS) - 1) + +var SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK = 0x4 | (NUM_NAMED_BARRIERS ? 0x8 : 0) | (HAVE_CLUSTER_BARRIER ? 0x10000 : 0) var SQ_WAVE_STATE_PRIV_SCC_SHIFT = 9 var SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK = 0xC00 var SQ_WAVE_STATE_PRIV_HALT_MASK = 0x4000 @@ -41,6 +61,8 @@ var SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT = 15 var SQ_WAVE_STATUS_WAVE64_SHIFT = 29 var SQ_WAVE_STATUS_WAVE64_SIZE = 1 var SQ_WAVE_STATUS_NO_VGPRS_SHIFT = 24 +var SQ_WAVE_STATUS_HALT_SHIFT = 14 +var SQ_WAVE_STATUS_IN_WG_SHIFT = 11 var SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK = SQ_WAVE_STATE_PRIV_SYS_PRIO_MASK|SQ_WAVE_STATE_PRIV_POISON_ERR_MASK var S_SAVE_PC_HI_TRAP_ID_MASK = 0xF0000000 @@ -48,11 +70,15 @@ var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SHIFT = 12 var SQ_WAVE_LDS_ALLOC_LDS_SIZE_SIZE = 9 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SIZE = 8 var SQ_WAVE_GPR_ALLOC_VGPR_SIZE_SHIFT = 12 -var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT = 24 -var SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE = 4 + +#if ASIC_FAMILY < CHIP_GC_12_0_3 var SQ_WAVE_LDS_ALLOC_GRANULARITY = 9 +#else +var SQ_WAVE_LDS_ALLOC_GRANULARITY = 10 +#endif var SQ_WAVE_EXCP_FLAG_PRIV_ADDR_WATCH_MASK = 0xF +var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT = 4 var SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_MASK = 0x10 var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT = 5 var SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_MASK = 0x20 @@ -83,13 +109,50 @@ var SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT = 0 var SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE = 2 var BARRIER_STATE_SIGNAL_OFFSET = 16 +var BARRIER_STATE_SIGNAL_SIZE = 7 +var BARRIER_STATE_MEMBER_OFFSET = 4 +var BARRIER_STATE_MEMBER_SIZE = 7 var BARRIER_STATE_VALID_OFFSET = 0 +#if RELAXED_SCHEDULING_IN_TRAP +var TTMP11_SCHED_MODE_SHIFT = 26 +var TTMP11_SCHED_MODE_SIZE = 2 +var TTMP11_SCHED_MODE_MASK = 0xC000000 +#endif + +var NAMED_BARRIERS_SR_OFFSET_FROM_HWREG = 0x80 +var S_BARRIER_INIT_MEMBERCNT_MASK = 0x7F0000 +var S_BARRIER_INIT_MEMBERCNT_SHIFT = 0x10 + +var SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT = 18 +var SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE = 1 +var SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT = 16 +var SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE = 1 +var SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT = 0 +var SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE = 7 + +#if HAVE_BANKED_VGPRS +var SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT = 12 +var SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE = 6 +#endif + var TTMP11_SCHED_MODE_SHIFT = 26 var TTMP11_SCHED_MODE_SIZE = 2 var TTMP11_SCHED_MODE_MASK = 0xC000000 var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23 var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000 +var TTMP11_FIRST_REPLAY_SHIFT = 22 +var TTMP11_FIRST_REPLAY_MASK = 0x400000 +var TTMP11_REPLAY_W64H_SHIFT = 21 +var TTMP11_REPLAY_W64H_MASK = 0x200000 +var TTMP11_FXPTR_SHIFT = 14 +var TTMP11_FXPTR_MASK = 0x1FC000 + +var TTMP11_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP11_HOST_TRAP_ENABLED_MASK = (1 << TTMP11_HOST_TRAP_ENABLED_SHIFT) + +var TTMP11_FEATURES_ENABLED_FLAGS_SHIFT = TTMP11_DEBUG_TRAP_ENABLED_SHIFT +var TTMP11_FEATURES_ENABLED_FLAGS_MASK = TTMP11_DEBUG_TRAP_ENABLED_MASK | TTMP11_HOST_TRAP_ENABLED_MASK // SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] // when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE @@ -101,6 +164,11 @@ var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 var S_SAVE_PC_HI_FIRST_WAVE_MASK = 0x80000000 var S_SAVE_PC_HI_FIRST_WAVE_SHIFT = 31 +#if HAVE_BANKED_VGPRS +var S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT = 25 +var S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SIZE = 6 +#endif + var s_sgpr_save_num = 108 var s_save_spi_init_lo = exec_lo @@ -111,12 +179,12 @@ var s_save_exec_lo = ttmp2 var s_save_exec_hi = ttmp3 var s_save_state_priv = ttmp12 var s_save_excp_flag_priv = ttmp15 -var s_save_xnack_mask = s_save_excp_flag_priv +var s_save_xnack_mask = s_save_exec_hi var s_wave_size = ttmp7 -var s_save_buf_rsrc0 = ttmp8 -var s_save_buf_rsrc1 = ttmp9 -var s_save_buf_rsrc2 = ttmp10 -var s_save_buf_rsrc3 = ttmp11 +var s_save_base_addr_lo = ttmp8 +var s_save_base_addr_hi = ttmp9 +var s_save_addr_lo = ttmp10 +var s_save_addr_hi = ttmp11 var s_save_mem_offset = ttmp4 var s_save_alloc_size = s_save_excp_flag_priv var s_save_tmp = ttmp14 @@ -124,9 +192,6 @@ var s_save_m0 = ttmp5 var s_save_ttmps_lo = s_save_tmp var s_save_ttmps_hi = s_save_excp_flag_priv -var S_RESTORE_BUF_RSRC_WORD1_STRIDE = S_SAVE_BUF_RSRC_WORD1_STRIDE -var S_RESTORE_BUF_RSRC_WORD3_MISC = S_SAVE_BUF_RSRC_WORD3_MISC - var S_RESTORE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 var S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT = 26 var S_WAVE_SIZE = 25 @@ -147,15 +212,21 @@ var s_restore_exec_hi = ttmp5 var s_restore_state_priv = ttmp14 var s_restore_excp_flag_priv = ttmp15 var s_restore_xnack_mask = ttmp13 -var s_restore_buf_rsrc0 = ttmp8 -var s_restore_buf_rsrc1 = ttmp9 -var s_restore_buf_rsrc2 = ttmp10 -var s_restore_buf_rsrc3 = ttmp11 +var s_restore_base_addr_lo = ttmp8 +var s_restore_base_addr_hi = ttmp9 +var s_restore_addr_lo = ttmp10 +var s_restore_addr_hi = ttmp11 var s_restore_size = ttmp6 var s_restore_ttmps_lo = s_restore_tmp var s_restore_ttmps_hi = s_restore_alloc_size var s_restore_spi_init_hi_save = s_restore_exec_hi +#if SAVE_TTMPS_IN_SGPR_BLOCK +var TTMP_SR_OFFSET_FROM_HWREG = -0x40 +#else +var TTMP_SR_OFFSET_FROM_HWREG = 0x40 +#endif + shader main asic(DEFAULT) type(CS) @@ -167,18 +238,22 @@ L_JUMP_TO_RESTORE: s_branch L_RESTORE L_SKIP_RESTORE: +#if RELAXED_SCHEDULING_IN_TRAP // Assume most relaxed scheduling mode is set. Save and revert to normal mode. s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_SCHED_MODE) s_wait_alu 0 s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, \ SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT, SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE), 0 +#endif s_getreg_b32 s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV) //save STATUS since we will change SCC +#if RELAXED_SCHEDULING_IN_TRAP // Save SCHED_MODE[1:0] into ttmp11[27:26]. s_andn2_b32 ttmp11, ttmp11, TTMP11_SCHED_MODE_MASK s_lshl_b32 ttmp2, ttmp2, TTMP11_SCHED_MODE_SHIFT s_or_b32 ttmp11, ttmp11, ttmp2 +#endif // Clear SPI_PRIO: do not save with elevated priority. // Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd. @@ -186,12 +261,52 @@ L_SKIP_RESTORE: s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) +#if HAVE_HT_TRAP_ID_WA + // If we have both TRAP_ID (ttmp1[31:28]) != 0, and + // EXCP_FLAG_PRIV.HOST_TRAP == 1, we cannot reliably know if we entered + // the trap handler for an s_trap or a host trap. + // + // In both cases, if we see HOST_TRAP == 1, we can clear the TRAP_ID + // bits: + // - If this was a host trap, all good, those bits should have been 0 + // anyway, so they can be cleared. + // - If this was an s_trap, ttmp[0:1] still points to the s_trap + // instruction, and it will be the first to be executed after s_rfe. + // We do not change the behavior of the program, by not handling the + // trap just yet, assume this was just a host trap and deal with the + // s_trap on next entry. + s_bitcmp0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_cbranch_scc1 L_NOT_HOST_TRAP_WA + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK + +L_NOT_HOST_TRAP_WA: + // From now on in the trap handler, if we see TTMP1.TRAP_ID != 0, then it has + // to be because of a s_trap. If the second level trap handler sees + // both TRAP_ID != 0 and EXCP_FLAG_PRIV.HOST_TRAP == 1, it is because + // a HOST_TRAP was received while we were in the trap handler, future host + // trap can't influence ttmp1. So both the s_trap and host_trap can be handled + // in one go. +#endif + + // Ignore Host Trap if SAVECTX is also present. + // Usually s_trap has a higher priority than context_save, HAVE_HT_TRAP_ID_WA + // will reverse these priority's order when s_trap, host_trap and context save + // are raised at the same time. We will end-up ignoring the s_trap (because of + // the ambiguity with the host trap), ignoring the host trap (to be sure high + // frequency sampling cannot prevent CWSR) and directly doing the context save. + // The s_trap will be re-executed after context save/restore. + s_bitcmp0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT + s_bitset0_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT, 1), 0 + +L_NO_SAVE_AND_HT: s_and_b32 ttmp2, s_save_state_priv, SQ_WAVE_STATE_PRIV_HALT_MASK s_cbranch_scc0 L_NOT_HALTED L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_MASK + s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_SAVE: @@ -245,18 +360,23 @@ L_CHECK_TRAP_ID: s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: +#if HAVE_XNACK + save_and_clear_xnack_state_priv(ttmp14) +#endif + // Read second-level TBA/TMA from first-level TMA and jump if available. // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) // ttmp12 holds SQ_WAVE_STATUS + s_mov_b32 ttmp3, s_save_excp_flag_priv s_sendmsg_rtn_b64 [ttmp14, ttmp15], sendmsg(MSG_RTN_GET_TMA) s_wait_idle s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 - s_bitcmp1_b32 ttmp15, 0xF + s_bitcmp1_b32 ttmp15, (ADDRESS_HI32_NUM_BITS - 1) s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA - s_or_b32 ttmp15, ttmp15, 0xFFFF0000 + s_or_b32 ttmp15, ttmp15, ~ADDRESS_HI32_MASK L_NO_SIGN_EXTEND_TMA: -#if ASIC_FAMILY == CHIP_GFX12 +#if RELAXED_SCHEDULING_IN_TRAP // Move SCHED_MODE[1:0] from ttmp11 to unused bits in ttmp1[27:26] (return PC_HI). // The second-level trap will restore from ttmp1 for backwards compatibility. s_and_b32 ttmp2, ttmp11, TTMP11_SCHED_MODE_MASK @@ -264,12 +384,32 @@ L_NO_SIGN_EXTEND_TMA: s_or_b32 ttmp1, ttmp1, ttmp2 #endif - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag + s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // trap enabled flag s_wait_idle - s_lshl_b32 ttmp2, ttmp2, TTMP11_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 ttmp11, ttmp11, TTMP11_DEBUG_TRAP_ENABLED_MASK + s_lshl_b32 ttmp2, ttmp2, TTMP11_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 ttmp11, ttmp11, TTMP11_FEATURES_ENABLED_FLAGS_MASK s_or_b32 ttmp11, ttmp11, ttmp2 + // If not a host trap, then driver cannot mask this + s_bitcmp1_b32 ttmp3, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT + s_cbranch_scc0 L_NO_EXCEPTION_MASKING + + s_bitcmp1_b32 s_save_state_priv, SQ_WAVE_STATUS_HALT_SHIFT + s_cbranch_scc1 L_MASK_HOST_TRAP + + // Handle masking host traps if requested by the driver. + s_bitcmp1_b32 ttmp11, TTMP11_HOST_TRAP_ENABLED_SHIFT + + // We got here because of either a non-maskable exception or a maskable + // one (HT). The driver said the maskable HT should not be masked, so + // we can directly carry on to the 2nd level trap handler. + s_cbranch_scc1 L_NO_EXCEPTION_MASKING + +L_MASK_HOST_TRAP: + // The driver asked to mask the HT, be sure to do so. + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT, 1), 0x0 + +L_NO_EXCEPTION_MASKING: s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 scope:SCOPE_SYS // second-level TBA s_wait_idle s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 scope:SCOPE_SYS // second-level TMA @@ -303,18 +443,29 @@ L_TRAP_CASE: s_addc_u32 ttmp1, ttmp1, 0x0 L_EXIT_TRAP: - s_and_b32 ttmp1, ttmp1, 0xFFFF + s_and_b32 ttmp1, ttmp1, ADDRESS_HI32_MASK + +#if HAVE_INSTRUCTION_FIXUP + s_getreg_b32 s_save_excp_flag_priv, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) + fixup_instruction() +#endif + +#if HAVE_XNACK + restore_xnack_state_priv(s_save_tmp) +#endif // Restore SQ_WAVE_STATUS. s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 - // STATE_PRIV.BARRIER_COMPLETE may have changed since we read it. + // STATE_PRIV.*BARRIER_COMPLETE may have changed since we read it. // Only restore fields which the trap handler changes. s_lshr_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT +#if RELAXED_SCHEDULING_IN_TRAP // Assume relaxed scheduling mode after this point. restore_sched_mode(ttmp2) +#endif s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \ SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT - SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_state_priv @@ -329,11 +480,18 @@ L_SAVE: s_cbranch_scc0 L_HAVE_VGPRS s_endpgm L_HAVE_VGPRS: - - s_and_b32 s_save_pc_hi, s_save_pc_hi, 0x0000ffff //pc[47:32] + s_and_b32 s_save_pc_hi, s_save_pc_hi, ADDRESS_HI32_MASK s_mov_b32 s_save_tmp, 0 s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, SQ_WAVE_EXCP_FLAG_PRIV_SAVE_CONTEXT_SHIFT, 1), s_save_tmp //clear saveCtx bit +#if HAVE_XNACK + save_and_clear_xnack_state_priv(s_save_tmp) +#endif + +#if HAVE_INSTRUCTION_FIXUP + fixup_instruction() +#endif + /* inform SPI the readiness and wait for SPI's go signal */ s_mov_b32 s_save_exec_lo, exec_lo //save EXEC and use EXEC for the go signal from SPI s_mov_b32 s_save_exec_hi, exec_hi @@ -347,11 +505,25 @@ L_HAVE_VGPRS: s_lshl_b32 s_save_tmp, s_save_tmp, (S_SAVE_PC_HI_FIRST_WAVE_SHIFT - S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT) s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp +#if HAVE_XNACK + s_getreg_b32 s_save_xnack_mask, hwreg(HW_REG_WAVE_XNACK_MASK) + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_XNACK_MASK), 0 +#endif + +#if HAVE_BANKED_VGPRS + // Save and clear shader's DST/SRC0/SRC1 VGPR bank selection so we can use v[0-255]. + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE) + s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT + s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp + s_mov_b32 s_save_tmp, 0 + s_setreg_b32 hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE), s_save_tmp +#endif + // Trap temporaries must be saved via VGPR but all VGPRs are in use. // There is no ttmp space to hold the resource constant for VGPR save. // Save v0 by itself since it requires only two SGPRs. s_mov_b32 s_save_ttmps_lo, exec_lo - s_and_b32 s_save_ttmps_hi, exec_hi, 0xFFFF + s_and_b32 s_save_ttmps_hi, exec_hi, ADDRESS_HI32_MASK s_mov_b32 exec_lo, 0xFFFFFFFF s_mov_b32 exec_hi, 0xFFFFFFFF global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] scope:SCOPE_SYS @@ -360,13 +532,13 @@ L_HAVE_VGPRS: s_mov_b32 exec_hi, s_save_ttmps_hi // Save trap temporaries 4-11, 13 initialized by SPI debug dispatch logic - // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 + // ttmp SR memory offset: + // - gfx12: size(VGPR)+size(SGPR)+0x40 + // - gfx12.5: size(VGPR)+size(SGPR)-0x40 get_wave_size2(s_save_ttmps_hi) get_vgpr_size_bytes(s_save_ttmps_lo, s_save_ttmps_hi) - get_svgpr_size_bytes(s_save_ttmps_hi) - s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_ttmps_hi - s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, 0xFFFF - s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, get_sgpr_size_bytes() + s_and_b32 s_save_ttmps_hi, s_save_spi_init_hi, ADDRESS_HI32_MASK + s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, (get_sgpr_size_bytes() + TTMP_SR_OFFSET_FROM_HWREG) s_add_u32 s_save_ttmps_lo, s_save_ttmps_lo, s_save_spi_init_lo s_addc_u32 s_save_ttmps_hi, s_save_ttmps_hi, 0x0 @@ -381,27 +553,19 @@ L_HAVE_VGPRS: v_writelane_b32 v0, ttmp13, 0xD v_writelane_b32 v0, exec_lo, 0xE v_writelane_b32 v0, exec_hi, 0xF - valu_sgpr_hazard() s_mov_b32 exec_lo, 0x3FFF s_mov_b32 exec_hi, 0x0 - global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] offset:0x40 scope:SCOPE_SYS + global_store_dword_addtid v0, [s_save_ttmps_lo, s_save_ttmps_hi] scope:SCOPE_SYS v_readlane_b32 ttmp14, v0, 0xE v_readlane_b32 ttmp15, v0, 0xF s_mov_b32 exec_lo, ttmp14 s_mov_b32 exec_hi, ttmp15 - /* setup Resource Contants */ - s_mov_b32 s_save_buf_rsrc0, s_save_spi_init_lo //base_addr_lo - s_and_b32 s_save_buf_rsrc1, s_save_spi_init_hi, 0x0000FFFF //base_addr_hi - s_or_b32 s_save_buf_rsrc1, s_save_buf_rsrc1, S_SAVE_BUF_RSRC_WORD1_STRIDE - s_mov_b32 s_save_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) although not neccessarily inited - s_mov_b32 s_save_buf_rsrc3, S_SAVE_BUF_RSRC_WORD3_MISC - + s_mov_b32 s_save_base_addr_lo, s_save_spi_init_lo + s_and_b32 s_save_base_addr_hi, s_save_spi_init_hi, ADDRESS_HI32_MASK s_mov_b32 s_save_m0, m0 - /* global mem offset */ - s_mov_b32 s_save_mem_offset, 0x0 get_wave_size2(s_wave_size) /* save first 4 VGPRs, needed for SGPR save */ @@ -416,102 +580,136 @@ L_ENABLE_SAVE_4VGPR_EXEC_HI: s_mov_b32 exec_hi, 0xFFFFFFFF s_branch L_SAVE_4VGPR_WAVE64 L_SAVE_4VGPR_WAVE32: - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - // VGPR Allocated in 4-GPR granularity - - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3 + global_store_addtid_b32 v1, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:128 + global_store_addtid_b32 v2, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:128*2 + global_store_addtid_b32 v3, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:128*3 s_branch L_SAVE_HWREG L_SAVE_4VGPR_WAVE64: - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - // VGPR Allocated in 4-GPR granularity - - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3 + global_store_addtid_b32 v1, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:256 + global_store_addtid_b32 v2, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:256*2 + global_store_addtid_b32 v3, [s_save_base_addr_lo, s_save_base_addr_hi] scope:SCOPE_SYS offset:256*3 /* save HW registers */ L_SAVE_HWREG: - // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) + // HWREG SR memory offset : size(VGPR)+size(SGPR) get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) - get_svgpr_size_bytes(s_save_tmp) - s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - v_mov_b32 v0, 0x0 //Offset[31:0] from buffer resource v_mov_b32 v1, 0x0 //Offset[63:32] from buffer resource v_mov_b32 v2, 0x0 //Set of SGPRs for TCP store + s_mov_b32 m0, 0x0 //Next lane of v2 to write to + + write_hwreg_to_v2(s_save_m0) // Ensure no further changes to barrier or LDS state. - // STATE_PRIV.BARRIER_COMPLETE may change up to this point. - s_barrier_signal -2 - s_barrier_wait -2 + // STATE_PRIV.*BARRIER_COMPLETE may change up to this point. + wait_trap_barriers(s_save_tmp, s_save_m0, 1) - // Re-read final state of BARRIER_COMPLETE field for save. + // Re-read final state of *BARRIER_COMPLETE fields for save. s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATE_PRIV) - s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK - s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_BARRIER_COMPLETE_MASK + s_and_b32 s_save_tmp, s_save_tmp, SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK + s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALL_BARRIER_COMPLETE_MASK s_or_b32 s_save_state_priv, s_save_state_priv, s_save_tmp - s_andn2_b32 s_save_tmp, s_save_pc_hi, S_SAVE_PC_HI_FIRST_WAVE_MASK - v_writelane_b32 v2, s_save_m0, 0x0 - v_writelane_b32 v2, s_save_pc_lo, 0x1 - v_writelane_b32 v2, s_save_tmp, 0x2 - v_writelane_b32 v2, s_save_exec_lo, 0x3 - v_writelane_b32 v2, s_save_exec_hi, 0x4 - v_writelane_b32 v2, s_save_state_priv, 0x5 - v_writelane_b32 v2, s_save_xnack_mask, 0x7 - valu_sgpr_hazard() + write_hwreg_to_v2(s_save_pc_lo) + s_and_b32 s_save_tmp, s_save_pc_hi, ADDRESS_HI32_MASK + write_hwreg_to_v2(s_save_tmp) + write_hwreg_to_v2(s_save_exec_lo) +#if WAVE32_ONLY + s_mov_b32 s_save_tmp, 0 + write_hwreg_to_v2(s_save_tmp) +#else + write_hwreg_to_v2(s_save_exec_hi) +#endif + write_hwreg_to_v2(s_save_state_priv) s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV) - v_writelane_b32 v2, s_save_tmp, 0x6 + write_hwreg_to_v2(s_save_tmp) + +#if HAVE_XNACK + write_hwreg_to_v2(s_save_xnack_mask) +#else + s_mov_b32 s_save_tmp, 0 + write_hwreg_to_v2(s_save_tmp) +#endif - s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_MODE) - v_writelane_b32 v2, s_save_tmp, 0x8 + s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_MODE) - s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) - v_writelane_b32 v2, s_save_tmp, 0x9 +#if HAVE_BANKED_VGPRS + s_bfe_u32 s_save_tmp, s_save_pc_hi, (S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT | (S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SIZE << 0x10)) + s_lshl_b32 s_save_tmp, s_save_tmp, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT + s_or_b32 s_save_m0, s_save_m0, s_save_tmp +#endif + + write_hwreg_to_v2(s_save_m0) + + s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_SCRATCH_BASE_LO) + write_hwreg_to_v2(s_save_m0) - s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) - v_writelane_b32 v2, s_save_tmp, 0xA + s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_SCRATCH_BASE_HI) + write_hwreg_to_v2(s_save_m0) - s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) - v_writelane_b32 v2, s_save_tmp, 0xB + s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_EXCP_FLAG_USER) + write_hwreg_to_v2(s_save_m0) - s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_TRAP_CTRL) - v_writelane_b32 v2, s_save_tmp, 0xC + s_getreg_b32 s_save_m0, hwreg(HW_REG_WAVE_TRAP_CTRL) + write_hwreg_to_v2(s_save_m0) s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_STATUS) - v_writelane_b32 v2, s_save_tmp, 0xD + write_hwreg_to_v2(s_save_tmp) s_get_barrier_state s_save_tmp, -1 s_wait_kmcnt (0) - v_writelane_b32 v2, s_save_tmp, 0xE - valu_sgpr_hazard() + write_hwreg_to_v2(s_save_tmp) +#if HAVE_CLUSTER_BARRIER + s_sendmsg_rtn_b32 s_save_tmp, sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) + s_wait_kmcnt 0 + write_hwreg_to_v2(s_save_tmp) +#endif + +#if ASIC_FAMILY >= CHIP_GC_12_0_3 + s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_SCHED_MODE) + write_hwreg_to_v2(s_save_tmp) +#endif + +#if ! SAVE_TTMPS_IN_SGPR_BLOCK // Write HWREGs with 16 VGPR lanes. TTMPs occupy space after this. s_mov_b32 exec_lo, 0xFFFF +#else + // All 128 bytes are available for HWREGs. + s_mov_b32 exec_lo, 0xFFFFFFFF +#endif s_mov_b32 exec_hi, 0x0 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS // Write SGPRs with 32 VGPR lanes. This works in wave32 and wave64 mode. s_mov_b32 exec_lo, 0xFFFFFFFF +#if NUM_NAMED_BARRIERS + v_mov_b32 v2, 0 + + for var bar_idx = 0; bar_idx < NUM_NAMED_BARRIERS; bar_idx ++ + s_get_barrier_state s_save_tmp, (bar_idx + 1) + s_wait_kmcnt 0 + v_writelane_b32 v2, s_save_tmp, bar_idx + end + + global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:NAMED_BARRIERS_SR_OFFSET_FROM_HWREG +#endif + /* save SGPRs */ // Save SGPR before LDS save, then the s0 to s4 can be used during LDS save... - // SGPR SR memory offset : size(VGPR)+size(SVGPR) + // SGPR SR memory offset : size(VGPR) get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) - get_svgpr_size_bytes(s_save_tmp) - s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes s_mov_b32 ttmp13, 0x0 //next VGPR lane to copy SGPR into @@ -528,14 +726,14 @@ L_SAVE_SGPR_LOOP: s_movrels_b64 s12, s12 //s12 = s[12+m0], s13 = s[13+m0] s_movrels_b64 s14, s14 //s14 = s[14+m0], s15 = s[15+m0] - s_cmp_eq_u32 ttmp13, 0x0 - s_cbranch_scc0 L_WRITE_V2_SECOND_HALF - write_16sgpr_to_v2(s0, 0x0) - s_branch L_SAVE_SGPR_SKIP_TCP_STORE -L_WRITE_V2_SECOND_HALF: - write_16sgpr_to_v2(s0, 0x10) + write_16sgpr_to_v2(s0) + + s_cmp_eq_u32 ttmp13, 0x20 //have 32 VGPR lanes filled? + s_cbranch_scc0 L_SAVE_SGPR_SKIP_TCP_STORE - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS s_add_u32 s_save_mem_offset, s_save_mem_offset, 0x80 s_mov_b32 ttmp13, 0x0 v_mov_b32 v2, 0x0 @@ -554,7 +752,14 @@ L_SAVE_SGPR_SKIP_TCP_STORE: s_movrels_b64 s10, s10 //s10 = s[10+m0], s11 = s[11+m0] write_12sgpr_to_v2(s0) - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS +#if SAVE_TTMPS_IN_SGPR_BLOCK + // Last 16 dwords of the SGPR block already contain the TTMPS. Make + // sure to not override them. + s_mov_b32 exec_lo, 0xFFFF +#endif + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS /* save LDS */ @@ -580,18 +785,13 @@ L_SAVE_LDS_NORMAL: // first wave do LDS save; s_lshl_b32 s_save_alloc_size, s_save_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY - s_mov_b32 s_save_buf_rsrc2, s_save_alloc_size //NUM_RECORDS in bytes - // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) + // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) // get_vgpr_size_bytes(s_save_mem_offset, s_wave_size) - get_svgpr_size_bytes(s_save_tmp) - s_add_u32 s_save_mem_offset, s_save_mem_offset, s_save_tmp s_add_u32 s_save_mem_offset, s_save_mem_offset, get_sgpr_size_bytes() s_add_u32 s_save_mem_offset, s_save_mem_offset, get_hwreg_size_bytes() - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - //load 0~63*4(byte address) to vgpr v0 v_mbcnt_lo_u32_b32 v0, -1, 0 v_mbcnt_hi_u32_b32 v0, -1, v0 @@ -611,7 +811,9 @@ L_SAVE_LDS_W32: L_SAVE_LDS_LOOP_W32: ds_read_b32 v1, v0 s_wait_idle - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS s_add_u32 m0, m0, s3 //every buffer_store_lds does 128 bytes s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 @@ -629,7 +831,9 @@ L_SAVE_LDS_W64: L_SAVE_LDS_LOOP_W64: ds_read_b32 v1, v0 s_wait_idle - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS s_add_u32 m0, m0, s3 //every buffer_store_lds does 256 bytes s_add_u32 s_save_mem_offset, s_save_mem_offset, s3 @@ -662,8 +866,6 @@ L_SAVE_VGPR_NORMAL: s_cmp_eq_u32 m0, 1 s_cbranch_scc1 L_SAVE_VGPR_WAVE64 - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - // VGPR Allocated in 4-GPR granularity // VGPR store using dw burst @@ -677,10 +879,12 @@ L_SAVE_VGPR_W32_LOOP: v_movrels_b32 v2, v2 //v2 = v[2+m0] v_movrels_b32 v3, v3 //v3 = v[3+m0] - buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:128*3 + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v0, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS + global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:128 + global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:128*2 + global_store_addtid_b32 v3, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:128*3 s_add_u32 m0, m0, 4 //next vgpr index s_add_u32 s_save_mem_offset, s_save_mem_offset, 128*4 //every buffer_store_dword does 128 bytes @@ -690,12 +894,10 @@ L_SAVE_VGPR_W32_LOOP: s_branch L_SAVE_VGPR_END L_SAVE_VGPR_WAVE64: - s_mov_b32 s_save_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - // VGPR store using dw burst s_mov_b32 m0, 0x4 //VGPR initial index value =4 s_cmp_lt_u32 m0, s_save_alloc_size - s_cbranch_scc0 L_SAVE_SHARED_VGPR + s_cbranch_scc0 L_SAVE_VGPR_END L_SAVE_VGPR_W64_LOOP: v_movrels_b32 v0, v0 //v0 = v[0+m0] @@ -703,45 +905,24 @@ L_SAVE_VGPR_W64_LOOP: v_movrels_b32 v2, v2 //v2 = v[2+m0] v_movrels_b32 v3, v3 //v3 = v[3+m0] - buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS - buffer_store_dword v1, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256 - buffer_store_dword v2, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*2 - buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS offset:256*3 + s_add_u32 s_save_addr_lo, s_save_base_addr_lo, s_save_mem_offset + s_addc_u32 s_save_addr_hi, s_save_base_addr_hi, 0x0 + global_store_addtid_b32 v0, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS + global_store_addtid_b32 v1, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:256 + global_store_addtid_b32 v2, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:256*2 + global_store_addtid_b32 v3, [s_save_addr_lo, s_save_addr_hi] scope:SCOPE_SYS offset:256*3 s_add_u32 m0, m0, 4 //next vgpr index s_add_u32 s_save_mem_offset, s_save_mem_offset, 256*4 //every buffer_store_dword does 256 bytes s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 s_cbranch_scc1 L_SAVE_VGPR_W64_LOOP //VGPR save is complete? -L_SAVE_SHARED_VGPR: - s_getreg_b32 s_save_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) - s_and_b32 s_save_alloc_size, s_save_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? - s_cbranch_scc0 L_SAVE_VGPR_END //no shared_vgpr used? jump to L_SAVE_LDS - s_lshl_b32 s_save_alloc_size, s_save_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) - //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. - //save shared_vgpr will start from the index of m0 - s_add_u32 s_save_alloc_size, s_save_alloc_size, m0 - s_mov_b32 exec_lo, 0xFFFFFFFF - s_mov_b32 exec_hi, 0x00000000 - -L_SAVE_SHARED_VGPR_WAVE64_LOOP: - v_movrels_b32 v0, v0 //v0 = v[0+m0] - buffer_store_dword v0, v0, s_save_buf_rsrc0, s_save_mem_offset scope:SCOPE_SYS - s_add_u32 m0, m0, 1 //next vgpr index - s_add_u32 s_save_mem_offset, s_save_mem_offset, 128 - s_cmp_lt_u32 m0, s_save_alloc_size //scc = (m0 < s_save_alloc_size) ? 1 : 0 - s_cbranch_scc1 L_SAVE_SHARED_VGPR_WAVE64_LOOP //SHARED_VGPR save is complete? - L_SAVE_VGPR_END: s_branch L_END_PGM L_RESTORE: - /* Setup Resource Contants */ - s_mov_b32 s_restore_buf_rsrc0, s_restore_spi_init_lo //base_addr_lo - s_and_b32 s_restore_buf_rsrc1, s_restore_spi_init_hi, 0x0000FFFF //base_addr_hi - s_or_b32 s_restore_buf_rsrc1, s_restore_buf_rsrc1, S_RESTORE_BUF_RSRC_WORD1_STRIDE - s_mov_b32 s_restore_buf_rsrc2, 0 //NUM_RECORDS initial value = 0 (in bytes) - s_mov_b32 s_restore_buf_rsrc3, S_RESTORE_BUF_RSRC_WORD3_MISC + s_mov_b32 s_restore_base_addr_lo, s_restore_spi_init_lo + s_and_b32 s_restore_base_addr_hi, s_restore_spi_init_hi, ADDRESS_HI32_MASK // Save s_restore_spi_init_hi for later use. s_mov_b32 s_restore_spi_init_hi_save, s_restore_spi_init_hi @@ -768,28 +949,31 @@ L_RESTORE_LDS_NORMAL: s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //lds_size is zero? s_cbranch_scc0 L_RESTORE_VGPR //no lds used? jump to L_RESTORE_VGPR s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, SQ_WAVE_LDS_ALLOC_GRANULARITY - s_mov_b32 s_restore_buf_rsrc2, s_restore_alloc_size //NUM_RECORDS in bytes - // LDS at offset: size(VGPR)+size(SVGPR)+SIZE(SGPR)+SIZE(HWREG) + // LDS at offset: size(VGPR)+SIZE(SGPR)+SIZE(HWREG) // get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) - get_svgpr_size_bytes(s_restore_tmp) - s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_hwreg_size_bytes() - s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - s_lshr_b32 m0, s_restore_size, S_WAVE_SIZE s_and_b32 m0, m0, 1 s_cmp_eq_u32 m0, 1 s_mov_b32 m0, 0x0 + + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v1, -1, v1 + v_lshlrev_b32 v1, 2, v1 // 0, 4, 8, ... 124 (W32) or 252 (W64) + s_cbranch_scc1 L_RESTORE_LDS_LOOP_W64 L_RESTORE_LDS_LOOP_W32: - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 + global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS s_wait_idle - ds_store_addtid_b32 v0 + ds_store_b32 v1, v0 + v_add_nc_u32 v1, v1, 128 s_add_u32 m0, m0, 128 // 128 DW s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 //mem offset increased by 128DW s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 @@ -797,9 +981,12 @@ L_RESTORE_LDS_LOOP_W32: s_branch L_RESTORE_VGPR L_RESTORE_LDS_LOOP_W64: - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 + global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS s_wait_idle - ds_store_addtid_b32 v0 + ds_store_b32 v1, v0 + v_add_nc_u32 v1, v1, 256 s_add_u32 m0, m0, 256 // 256 DW s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256 //mem offset increased by 256DW s_cmp_lt_u32 m0, s_restore_alloc_size //scc=(m0 < s_restore_alloc_size) ? 1 : 0 @@ -828,20 +1015,18 @@ L_RESTORE_VGPR_NORMAL: s_cmp_eq_u32 m0, 1 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64 - s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - // VGPR load using dw burst s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v1, v0 will be the last s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128*4 s_mov_b32 m0, 4 //VGPR initial index value = 4 - s_cmp_lt_u32 m0, s_restore_alloc_size - s_cbranch_scc0 L_RESTORE_SGPR L_RESTORE_VGPR_WAVE32_LOOP: - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:128*3 + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 + global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS + global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128 + global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*2 + global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*3 s_wait_idle v_movreld_b32 v0, v0 //v[0+m0] = v0 v_movreld_b32 v1, v1 @@ -853,29 +1038,31 @@ L_RESTORE_VGPR_WAVE32_LOOP: s_cbranch_scc1 L_RESTORE_VGPR_WAVE32_LOOP //VGPR restore (except v0) is complete? /* VGPR restore on v0 */ - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:128*3 + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset_save + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 + global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS + global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128 + global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*2 + global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:128*3 s_wait_idle s_branch L_RESTORE_SGPR L_RESTORE_VGPR_WAVE64: - s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes - // VGPR load using dw burst s_mov_b32 s_restore_mem_offset_save, s_restore_mem_offset // restore start with v4, v0 will be the last s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 256*4 s_mov_b32 m0, 4 //VGPR initial index value = 4 s_cmp_lt_u32 m0, s_restore_alloc_size - s_cbranch_scc0 L_RESTORE_SHARED_VGPR + s_cbranch_scc0 L_RESTORE_V0 L_RESTORE_VGPR_WAVE64_LOOP: - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS offset:256*3 + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 + global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS + global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256 + global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*2 + global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*3 s_wait_idle v_movreld_b32 v0, v0 //v[0+m0] = v0 v_movreld_b32 v1, v1 @@ -886,50 +1073,29 @@ L_RESTORE_VGPR_WAVE64_LOOP: s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 s_cbranch_scc1 L_RESTORE_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? -L_RESTORE_SHARED_VGPR: - s_getreg_b32 s_restore_alloc_size, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) //shared_vgpr_size - s_and_b32 s_restore_alloc_size, s_restore_alloc_size, 0xFFFFFFFF //shared_vgpr_size is zero? - s_cbranch_scc0 L_RESTORE_V0 //no shared_vgpr used? - s_lshl_b32 s_restore_alloc_size, s_restore_alloc_size, 3 //Number of SHARED_VGPRs = shared_vgpr_size * 8 (non-zero value) - //m0 now has the value of normal vgpr count, just add the m0 with shared_vgpr count to get the total count. - //restore shared_vgpr will start from the index of m0 - s_add_u32 s_restore_alloc_size, s_restore_alloc_size, m0 - s_mov_b32 exec_lo, 0xFFFFFFFF - s_mov_b32 exec_hi, 0x00000000 -L_RESTORE_SHARED_VGPR_WAVE64_LOOP: - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset scope:SCOPE_SYS - s_wait_idle - v_movreld_b32 v0, v0 //v[0+m0] = v0 - s_add_u32 m0, m0, 1 //next vgpr index - s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 128 - s_cmp_lt_u32 m0, s_restore_alloc_size //scc = (m0 < s_restore_alloc_size) ? 1 : 0 - s_cbranch_scc1 L_RESTORE_SHARED_VGPR_WAVE64_LOOP //VGPR restore (except v0) is complete? - - s_mov_b32 exec_hi, 0xFFFFFFFF //restore back exec_hi before restoring V0!! - /* VGPR restore on v0 */ L_RESTORE_V0: - buffer_load_dword v0, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS - buffer_load_dword v1, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256 - buffer_load_dword v2, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256*2 - buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save scope:SCOPE_SYS offset:256*3 + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset_save + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 + global_load_addtid_b32 v0, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS + global_load_addtid_b32 v1, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256 + global_load_addtid_b32 v2, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*2 + global_load_addtid_b32 v3, [s_restore_addr_lo, s_restore_addr_hi] scope:SCOPE_SYS offset:256*3 s_wait_idle /* restore SGPRs */ //will be 2+8+16*6 - // SGPR SR memory offset : size(VGPR)+size(SVGPR) + // SGPR SR memory offset : size(VGPR) L_RESTORE_SGPR: get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) - get_svgpr_size_bytes(s_restore_tmp) - s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() - s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 20*4 //s108~s127 is not saved - - s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + s_sub_u32 s_restore_mem_offset, s_restore_mem_offset, 24*4 // s[104:107] + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 s_mov_b32 m0, s_sgpr_save_num - read_4sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) + s_load_b128 s0, [s_restore_addr_lo, s_restore_addr_hi], 0x0 scope:SCOPE_SYS s_wait_idle s_sub_u32 m0, m0, 4 // Restore from S[0] to S[104] @@ -938,7 +1104,9 @@ L_RESTORE_SGPR: s_movreld_b64 s0, s0 //s[0+m0] = s0 s_movreld_b64 s2, s2 - read_8sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) + s_sub_co_u32 s_restore_addr_lo, s_restore_addr_lo, 8*4 // s[96:103] + s_sub_co_ci_u32 s_restore_addr_hi, s_restore_addr_hi, 0 + s_load_b256 s0, [s_restore_addr_lo, s_restore_addr_hi], 0x0 scope:SCOPE_SYS s_wait_idle s_sub_u32 m0, m0, 8 // Restore from S[0] to S[96] @@ -950,7 +1118,9 @@ L_RESTORE_SGPR: s_movreld_b64 s6, s6 L_RESTORE_SGPR_LOOP: - read_16sgpr_from_mem(s0, s_restore_buf_rsrc0, s_restore_mem_offset) + s_sub_co_u32 s_restore_addr_lo, s_restore_addr_lo, 16*4 // s[0,16,32,48,64,80] + s_sub_co_ci_u32 s_restore_addr_hi, s_restore_addr_hi, 0 + s_load_b512 s0, [s_restore_addr_lo, s_restore_addr_hi], 0x0 scope:SCOPE_SYS s_wait_idle s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0] @@ -974,76 +1144,123 @@ L_RESTORE_SGPR: /* restore HW registers */ L_RESTORE_HWREG: - // HWREG SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR) + // HWREG SR memory offset : size(VGPR)+size(SGPR) get_vgpr_size_bytes(s_restore_mem_offset, s_restore_size) - get_svgpr_size_bytes(s_restore_tmp) - s_add_u32 s_restore_mem_offset, s_restore_mem_offset, s_restore_tmp s_add_u32 s_restore_mem_offset, s_restore_mem_offset, get_sgpr_size_bytes() - - s_mov_b32 s_restore_buf_rsrc2, 0x1000000 //NUM_RECORDS in bytes + s_add_u32 s_restore_addr_lo, s_restore_base_addr_lo, s_restore_mem_offset + s_addc_u32 s_restore_addr_hi, s_restore_base_addr_hi, 0x0 // Restore s_restore_spi_init_hi before the saved value gets clobbered. s_mov_b32 s_restore_spi_init_hi, s_restore_spi_init_hi_save - read_hwreg_from_mem(s_restore_m0, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_pc_lo, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_pc_hi, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_exec_lo, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_exec_hi, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_state_priv, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_excp_flag_priv, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_xnack_mask, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_mode, s_restore_buf_rsrc0, s_restore_mem_offset) - read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) + s_load_b32 s_restore_m0, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS + s_load_b32 s_restore_pc_lo, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x4 + s_load_b32 s_restore_pc_hi, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x8 + s_load_b32 s_restore_exec_lo, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0xC + s_load_b32 s_restore_exec_hi, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x10 + s_load_b32 s_restore_state_priv, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x14 + s_load_b32 s_restore_excp_flag_priv, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x18 + s_load_b32 s_restore_xnack_mask, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x1C + s_load_b32 s_restore_mode, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x20 + s_load_b32 s_restore_flat_scratch, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x24 s_wait_idle s_setreg_b32 hwreg(HW_REG_WAVE_SCRATCH_BASE_LO), s_restore_flat_scratch - read_hwreg_from_mem(s_restore_flat_scratch, s_restore_buf_rsrc0, s_restore_mem_offset) + s_load_b32 s_restore_flat_scratch, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x28 s_wait_idle s_setreg_b32 hwreg(HW_REG_WAVE_SCRATCH_BASE_HI), s_restore_flat_scratch - read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset) + s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x2C s_wait_idle s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_USER), s_restore_tmp - read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset) + s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x30 s_wait_idle s_setreg_b32 hwreg(HW_REG_WAVE_TRAP_CTRL), s_restore_tmp - // Only the first wave needs to restore the workgroup barrier. + // Only the first wave needs to restore group barriers. s_and_b32 s_restore_tmp, s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_MASK - s_cbranch_scc0 L_SKIP_BARRIER_RESTORE + s_cbranch_scc0 L_SKIP_GROUP_BARRIER_RESTORE // Skip over WAVE_STATUS, since there is no state to restore from it - s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 4 - read_hwreg_from_mem(s_restore_tmp, s_restore_buf_rsrc0, s_restore_mem_offset) + s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x38 s_wait_idle + // Skip group barriers if wave is not part of a group. s_bitcmp1_b32 s_restore_tmp, BARRIER_STATE_VALID_OFFSET - s_cbranch_scc0 L_SKIP_BARRIER_RESTORE + s_cbranch_scc0 L_SKIP_GROUP_BARRIER_RESTORE - // extract the saved signal count from s_restore_tmp - s_lshr_b32 s_restore_tmp, s_restore_tmp, BARRIER_STATE_SIGNAL_OFFSET + // Restore workgroup barrier signal count. + restore_barrier_signal_count(-1) - // We need to call s_barrier_signal repeatedly to restore the signal - // count of the work group barrier. The member count is already - // initialized with the number of waves in the work group. -L_BARRIER_RESTORE_LOOP: - s_and_b32 s_restore_tmp, s_restore_tmp, s_restore_tmp - s_cbranch_scc0 L_SKIP_BARRIER_RESTORE - s_barrier_signal -1 - s_add_i32 s_restore_tmp, s_restore_tmp, -1 - s_branch L_BARRIER_RESTORE_LOOP +#if NUM_NAMED_BARRIERS + s_mov_b32 s_restore_mem_offset, NAMED_BARRIERS_SR_OFFSET_FROM_HWREG + s_mov_b32 m0, 1 -L_SKIP_BARRIER_RESTORE: +L_RESTORE_NAMED_BARRIER_LOOP: + s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], s_restore_mem_offset scope:SCOPE_SYS + s_wait_kmcnt 0 + s_add_u32 s_restore_mem_offset, s_restore_mem_offset, 0x4 + + // Restore named barrier member count. + s_bfe_u32 exec_lo, s_restore_tmp, (BARRIER_STATE_MEMBER_OFFSET | (BARRIER_STATE_MEMBER_SIZE << 16)) + s_lshl_b32 exec_lo, exec_lo, S_BARRIER_INIT_MEMBERCNT_SHIFT + s_or_b32 m0, m0, exec_lo + s_barrier_init m0 + s_andn2_b32 m0, m0, S_BARRIER_INIT_MEMBERCNT_MASK + + // Restore named barrier signal count. + restore_barrier_signal_count(m0) + + s_add_u32 m0, m0, 1 + s_cmp_gt_u32 m0, NUM_NAMED_BARRIERS + s_cbranch_scc0 L_RESTORE_NAMED_BARRIER_LOOP +#endif + +L_SKIP_GROUP_BARRIER_RESTORE: +#if HAVE_CLUSTER_BARRIER + s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x3C + s_wait_kmcnt 0 + + // Skip cluster barrier restore if wave is not part of a cluster. + s_bitcmp1_b32 s_restore_tmp, BARRIER_STATE_VALID_OFFSET + s_cbranch_scc0 L_SKIP_CLUSTER_BARRIER_RESTORE + + // Only the first wave in the group signals the trap cluster barrier. + s_bitcmp1_b32 s_restore_spi_init_hi, S_RESTORE_SPI_INIT_FIRST_WAVE_SHIFT + s_cbranch_scc0 L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL + + // Clear SCC: s_barrier_signal_isfirst -4 writes SCC=>1 but not SCC=>0. + s_cmp_eq_u32 0, 1 + s_barrier_signal_isfirst -4 +L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL: + s_barrier_wait -4 + + // Only the first wave in the cluster restores the barrier. + s_cbranch_scc0 L_SKIP_CLUSTER_BARRIER_RESTORE + + // Restore cluster barrier signal count. + restore_barrier_signal_count(-3) +L_SKIP_CLUSTER_BARRIER_RESTORE: +#endif + +#if ASIC_FAMILY >= CHIP_GC_12_0_3 + s_load_b32 s_restore_tmp, [s_restore_addr_lo, s_restore_addr_hi], null scope:SCOPE_SYS offset:0x40 + s_wait_kmcnt 0 + s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE), s_restore_tmp +#endif s_mov_b32 m0, s_restore_m0 s_mov_b32 exec_lo, s_restore_exec_lo s_mov_b32 exec_hi, s_restore_exec_hi +#if HAVE_XNACK + s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_MASK), s_restore_xnack_mask +#endif + // EXCP_FLAG_PRIV.SAVE_CONTEXT and HOST_TRAP may have changed. // Only restore the other fields to avoid clobbering them. s_setreg_b32 hwreg(HW_REG_WAVE_EXCP_FLAG_PRIV, 0, SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_1_SIZE), s_restore_excp_flag_priv @@ -1055,78 +1272,74 @@ L_SKIP_BARRIER_RESTORE: s_setreg_b32 hwreg(HW_REG_WAVE_MODE), s_restore_mode // Restore trap temporaries 4-11, 13 initialized by SPI debug dispatch logic - // ttmp SR memory offset : size(VGPR)+size(SVGPR)+size(SGPR)+0x40 + // ttmp SR memory offset : + // - gfx12: size(VGPR)+size(SGPR)+0x40 + // - gfx12.5: size(VGPR)+size(SGPR)-0x40 get_vgpr_size_bytes(s_restore_ttmps_lo, s_restore_size) - get_svgpr_size_bytes(s_restore_ttmps_hi) - s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_ttmps_hi - s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, get_sgpr_size_bytes() - s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_buf_rsrc0 - s_addc_u32 s_restore_ttmps_hi, s_restore_buf_rsrc1, 0x0 - s_and_b32 s_restore_ttmps_hi, s_restore_ttmps_hi, 0xFFFF - s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x50 scope:SCOPE_SYS - s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x60 scope:SCOPE_SYS - s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x74 scope:SCOPE_SYS + s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, (get_sgpr_size_bytes() + TTMP_SR_OFFSET_FROM_HWREG) + s_add_u32 s_restore_ttmps_lo, s_restore_ttmps_lo, s_restore_base_addr_lo + s_addc_u32 s_restore_ttmps_hi, s_restore_base_addr_hi, 0x0 + s_load_dwordx4 [ttmp4, ttmp5, ttmp6, ttmp7], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x10 scope:SCOPE_SYS + s_load_dwordx4 [ttmp8, ttmp9, ttmp10, ttmp11], [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x20 scope:SCOPE_SYS + s_load_dword ttmp13, [s_restore_ttmps_lo, s_restore_ttmps_hi], 0x34 scope:SCOPE_SYS s_wait_idle - s_and_b32 s_restore_pc_hi, s_restore_pc_hi, 0x0000ffff //pc[47:32] //Do it here in order not to affect STATUS +#if HAVE_XNACK + restore_xnack_state_priv(s_restore_tmp) +#endif + + s_and_b32 s_restore_pc_hi, s_restore_pc_hi, ADDRESS_HI32_MASK //Do it here in order not to affect STATUS s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32 s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32 +#if RELAXED_SCHEDULING_IN_TRAP // Assume relaxed scheduling mode after this point. restore_sched_mode(s_restore_tmp) +#endif s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV), s_restore_state_priv // SCC is included, which is changed by previous salu - // Make barrier and LDS state visible to all waves in the group. - // STATE_PRIV.BARRIER_COMPLETE may change after this point. - s_barrier_signal -2 - s_barrier_wait -2 + // Make barrier and LDS state visible to all waves in the group/cluster. + // STATE_PRIV.*BARRIER_COMPLETE may change after this point. + wait_trap_barriers(s_restore_tmp, 0, 0) + +#if HAVE_CLUSTER_BARRIER + // SCC is changed by wait_trap_barriers, restore it separately. + s_lshr_b32 s_restore_state_priv, s_restore_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT + s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, 1), s_restore_state_priv +#endif s_rfe_b64 s_restore_pc_lo //Return to the main shader program and resume execution L_END_PGM: - // Make sure that no wave of the workgroup can exit the trap handler - // before the workgroup barrier state is saved. - s_barrier_signal -2 - s_barrier_wait -2 + // Make sure that no wave of the group/cluster can exit the trap handler + // before the group/cluster barrier state is saved. + wait_trap_barriers(s_restore_tmp, 0, 0) + s_endpgm_saved end -function write_16sgpr_to_v2(s, lane_offset) +function write_hwreg_to_v2(s) + // Copy into VGPR for later TCP store. + v_writelane_b32 v2, s, m0 + s_add_u32 m0, m0, 0x1 +end + + +function write_16sgpr_to_v2(s) // Copy into VGPR for later TCP store. for var sgpr_idx = 0; sgpr_idx < 16; sgpr_idx ++ - v_writelane_b32 v2, s[sgpr_idx], sgpr_idx + lane_offset + v_writelane_b32 v2, s[sgpr_idx], ttmp13 + s_add_u32 ttmp13, ttmp13, 0x1 end - valu_sgpr_hazard() - s_add_u32 ttmp13, ttmp13, 0x10 end function write_12sgpr_to_v2(s) // Copy into VGPR for later TCP store. for var sgpr_idx = 0; sgpr_idx < 12; sgpr_idx ++ - v_writelane_b32 v2, s[sgpr_idx], sgpr_idx + v_writelane_b32 v2, s[sgpr_idx], ttmp13 + s_add_u32 ttmp13, ttmp13, 0x1 end - valu_sgpr_hazard() -end - -function read_hwreg_from_mem(s, s_rsrc, s_mem_offset) - s_buffer_load_dword s, s_rsrc, s_mem_offset scope:SCOPE_SYS - s_add_u32 s_mem_offset, s_mem_offset, 4 -end - -function read_16sgpr_from_mem(s, s_rsrc, s_mem_offset) - s_sub_u32 s_mem_offset, s_mem_offset, 4*16 - s_buffer_load_dwordx16 s, s_rsrc, s_mem_offset scope:SCOPE_SYS -end - -function read_8sgpr_from_mem(s, s_rsrc, s_mem_offset) - s_sub_u32 s_mem_offset, s_mem_offset, 4*8 - s_buffer_load_dwordx8 s, s_rsrc, s_mem_offset scope:SCOPE_SYS -end - -function read_4sgpr_from_mem(s, s_rsrc, s_mem_offset) - s_sub_u32 s_mem_offset, s_mem_offset, 4*4 - s_buffer_load_dwordx4 s, s_rsrc, s_mem_offset scope:SCOPE_SYS end function get_vgpr_size_bytes(s_vgpr_size_byte, s_size) @@ -1141,17 +1354,16 @@ L_ENABLE_SHIFT_W64: L_SHIFT_DONE: end -function get_svgpr_size_bytes(s_svgpr_size_byte) - s_getreg_b32 s_svgpr_size_byte, hwreg(HW_REG_WAVE_LDS_ALLOC,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SHIFT,SQ_WAVE_LDS_ALLOC_VGPR_SHARED_SIZE_SIZE) - s_lshl_b32 s_svgpr_size_byte, s_svgpr_size_byte, (3+7) -end - function get_sgpr_size_bytes return 512 end function get_hwreg_size_bytes +#if ASIC_FAMILY >= CHIP_GC_12_0_3 + return 512 +#else return 128 +#endif end function get_wave_size2(s_reg) @@ -1159,15 +1371,258 @@ function get_wave_size2(s_reg) s_lshl_b32 s_reg, s_reg, S_WAVE_SIZE end -function valu_sgpr_hazard -#if HAVE_VALU_SGPR_HAZARD - for var rep = 0; rep < 8; rep ++ - ds_nop - end +#if HAVE_XNACK +function save_and_clear_xnack_state_priv(s_tmp) + // Preserve and clear XNACK state before issuing further translations. + // Save XNACK_STATE_PRIV.{FIRST_REPLAY, REPLAY_W64H, FXPTR} into ttmp11[22:14]. + s_andn2_b32 ttmp11, ttmp11, (TTMP11_FIRST_REPLAY_MASK | TTMP11_REPLAY_W64H_MASK | TTMP11_FXPTR_MASK) + + s_getreg_b32 s_tmp, hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE) + s_lshl_b32 s_tmp, s_tmp, TTMP11_FIRST_REPLAY_SHIFT + s_or_b32 ttmp11, ttmp11, s_tmp + + s_getreg_b32 s_tmp, hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE) + s_lshl_b32 s_tmp, s_tmp, TTMP11_REPLAY_W64H_SHIFT + s_or_b32 ttmp11, ttmp11, s_tmp + + s_getreg_b32 s_tmp, hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE) + s_lshl_b32 s_tmp, s_tmp, TTMP11_FXPTR_SHIFT + s_or_b32 ttmp11, ttmp11, s_tmp + + s_setreg_imm32_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV), 0 +end + +function restore_xnack_state_priv(s_tmp) + s_lshr_b32 s_tmp, ttmp11, TTMP11_FIRST_REPLAY_SHIFT + s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FIRST_REPLAY_SIZE), s_tmp + + s_lshr_b32 s_tmp, ttmp11, TTMP11_REPLAY_W64H_SHIFT + s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_REPLAY_W64H_SIZE), s_tmp + + s_lshr_b32 s_tmp, ttmp11, TTMP11_FXPTR_SHIFT + s_setreg_b32 hwreg(HW_REG_WAVE_XNACK_STATE_PRIV, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SHIFT, SQ_WAVE_XNACK_STATE_PRIV_FXPTR_SIZE), s_tmp +end +#endif + +function wait_trap_barriers(s_tmp1, s_tmp2, serialize_wa) +#if HAVE_CLUSTER_BARRIER + // If not in a WG then wave cannot use s_barrier_signal_isfirst. + s_getreg_b32 s_tmp1, hwreg(HW_REG_WAVE_STATUS) + s_bitcmp0_b32 s_tmp1, SQ_WAVE_STATUS_IN_WG_SHIFT + s_cbranch_scc1 L_TRAP_CLUSTER_BARRIER_SIGNAL + + s_barrier_signal_isfirst -2 + s_barrier_wait -2 + + // Only the first wave in the group signals the trap cluster barrier. + s_cbranch_scc0 L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL + +L_TRAP_CLUSTER_BARRIER_SIGNAL: + s_barrier_signal -4 + +L_SKIP_TRAP_CLUSTER_BARRIER_SIGNAL: + s_barrier_wait -4 + +#if CLUSTER_BARRIER_SERIALIZE_WORKAROUND +if serialize_wa + // Trap cluster barrier may complete with a user cluster barrier in-flight. + // This is indicated if user cluster member count and signal count are equal. +L_WAIT_USER_CLUSTER_BARRIER_COMPLETE: + s_sendmsg_rtn_b32 s_tmp1, sendmsg(MSG_RTN_GET_CLUSTER_BARRIER_STATE) + s_wait_kmcnt 0 + s_bitcmp0_b32 s_tmp1, BARRIER_STATE_VALID_OFFSET + s_cbranch_scc1 L_NOT_IN_CLUSTER + + s_bfe_u32 s_tmp2, s_tmp1, (BARRIER_STATE_MEMBER_OFFSET | (BARRIER_STATE_MEMBER_SIZE << 0x10)) + s_bfe_u32 s_tmp1, s_tmp1, (BARRIER_STATE_SIGNAL_OFFSET | (BARRIER_STATE_SIGNAL_SIZE << 0x10)) + s_cmp_eq_u32 s_tmp1, s_tmp2 + s_cbranch_scc1 L_WAIT_USER_CLUSTER_BARRIER_COMPLETE +end +L_NOT_IN_CLUSTER: +#endif + +#else + s_barrier_signal -2 + s_barrier_wait -2 #endif end +#if RELAXED_SCHEDULING_IN_TRAP function restore_sched_mode(s_tmp) s_bfe_u32 s_tmp, ttmp11, (TTMP11_SCHED_MODE_SHIFT | (TTMP11_SCHED_MODE_SIZE << 0x10)) s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE), s_tmp end +#endif + +function restore_barrier_signal_count(barrier_id) + // extract the saved signal count from s_restore_tmp + s_lshr_b32 s_restore_tmp, s_restore_tmp, BARRIER_STATE_SIGNAL_OFFSET + + // We need to call s_barrier_signal repeatedly to restore the signal count + // of the group/cluster barrier. The member count is already initialized. +L_BARRIER_RESTORE_LOOP: + s_and_b32 s_restore_tmp, s_restore_tmp, s_restore_tmp + s_cbranch_scc0 L_BARRIER_RESTORE_DONE + s_barrier_signal barrier_id + s_add_i32 s_restore_tmp, s_restore_tmp, -1 + s_branch L_BARRIER_RESTORE_LOOP + +L_BARRIER_RESTORE_DONE: +end + +#if HAVE_INSTRUCTION_FIXUP +function fixup_instruction + // PC read may fault if memory violation has been asserted. + // In this case no further progress is expected so fixup is not needed. + s_bitcmp1_b32 s_save_excp_flag_priv, SQ_WAVE_EXCP_FLAG_PRIV_MEM_VIOL_SHIFT + s_cbranch_scc1 L_FIXUP_DONE + + // ttmp[0:1]: {7b'0} PC[56:0] + // ttmp2, 3, 10, 13, 14, 15: free + s_load_b64 [ttmp14, ttmp15], [ttmp0, ttmp1], 0 scope:SCOPE_CU // Load the 2 instruction DW we are returning to + s_wait_kmcnt 0 + s_load_b64 [ttmp2, ttmp3], [ttmp0, ttmp1], 8 scope:SCOPE_CU // Load the next 2 instruction DW, just in case + s_and_b32 ttmp10, ttmp14, 0x80000000 // Check bit 31 in the first DWORD + // SCC set if ttmp10 is != 0, i.e. if bit 31 == 1 + s_cbranch_scc1 L_FIXUP_NOT_VOP12C // If bit 31 is 1, we are not VOP1, VOP2, or VOP3C + // Fall through here means bit 31 == 0, meaning we are VOP1, VOP2, or VOPC + // Size of instruction depends on Opcode or SRC0_9 + // Check for VOP2 opcode + s_bfe_u32 ttmp10, ttmp14, (25 | (6 << 0x10)) // Check bits 30:25 for VOP2 Opcode + // VOP2 V_FMAMK_F64 of V_FMAAK_F64 has implied 64-bit literature, 3 DW + s_sub_co_i32 ttmp13, ttmp10, 0x23 // V_FMAMK_F64 is 0x23, V_FMAAK_F64 is 0x24 + s_cmp_le_u32 ttmp13, 0x1 // 0==0x23, 1==0x24 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst + // VOP2 V_FMAMK_F32, V_FMAAK_F32, V_FMAMK_F16, V_FMAAK_F16, 2 DW + s_sub_co_i32 ttmp13, ttmp10, 0x2c // V_FMAMK_F32 is 0x2c, V_FMAAK_F32 is 0x2d + s_cmp_le_u32 ttmp13, 0x1 // 0==0x2c, 1==0x2d + s_cbranch_scc1 L_FIXUP_TWO_DWORD // If either, this is 2 DWORD inst + s_sub_co_i32 ttmp13, ttmp10, 0x37 // V_FMAMK_F16 is 0x37, V_FMAAK_F16 is 0x38 + s_cmp_le_u32 ttmp13, 0x1 // 0==0x37, 1==0x38 + s_cbranch_scc1 L_FIXUP_TWO_DWORD // If either, this is 2 DWORD inst + // Check SRC0_9 for VOP1, VOP2, and VOPC + s_and_b32 ttmp10, ttmp14, 0x1ff // Check bits 8:0 for SRC0_9 + // Literal constant 64 is 3 DWORDs + s_cmp_eq_u32 ttmp10, 0xfe // 0xfe == 254 == Literal constant64 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + // Literal constant 32, DPP16, DPP8, and DPP8FI are 2 DWORDs + s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 + s_cbranch_scc1 L_FIXUP_TWO_DWORD // 2 DWORD inst + s_cmp_eq_u32 ttmp10, 0xfa // 0xfa == 250 = DPP16 + s_cbranch_scc1 L_FIXUP_TWO_DWORD // 2 DWORD inst + s_sub_co_i32 ttmp13, ttmp10, 0xe9 // DPP8 is 0xe9, DPP8FI is 0xea + s_cmp_le_u32 ttmp13, 0x1 // 0==0xe9, 1==0xea + s_cbranch_scc1 L_FIXUP_TWO_DWORD // If either, this is 2 DWORD inst + // Instruction is 1 DWORD otherwise + +L_FIXUP_ONE_DWORD: + // Check if TTMP15 contains the value for S_SET_VGPR_MSB instruction + s_and_b32 ttmp10, ttmp15, 0xffff0000 // Check encoding in upper 16 bits + s_cmp_eq_u32 ttmp10, 0xbf860000 // Check if SOPP (9b'10_1111111) and S_SET_VGPR_MSB (7b'0000110) + s_cbranch_scc0 L_FIXUP_DONE // No problem, no fixup needed + // VALU op followed by a S_SET_VGPR_MSB. Need to pull SIMM[15:8] to fix up MODE.*_VGPR_MSB + s_bfe_u32 ttmp10, ttmp15, (14 | (2 << 0x10)) // Shift SIMM[15:14] over to 1:0, Dst + s_and_b32 ttmp13, ttmp15, 0x3f00 // Mask to get SIMM[13:8] only + s_lshr_b32 ttmp13, ttmp13, 6 // Shift SIMM[13:8] into 7:2, Src2, Src1, Src0 + s_or_b32 ttmp10, ttmp10, ttmp13 // Src2, Src1, Src0, Dst --> format in MODE register + s_setreg_b32 hwreg(HW_REG_WAVE_MODE, 12, 8), ttmp10 // Write value into MODE[19:12] + s_branch L_FIXUP_DONE + +L_FIXUP_NOT_VOP12C: + // ttmp[0:1]: {7b'0} PC[56:0] + // ttmp2: PC+2 value (not waitcnt'ed yet) + // ttmp3: PC+3 value (not waitcnt'ed yet) + // ttmp10, ttmp13: free + // ttmp14: PC+O value + // ttmp15: PC+1 value + // Not VOP1, VOP2, or VOPC. + // Check if we are VOP3 or VOP3SD + s_and_b32 ttmp10, ttmp14, 0xfc000000 // Bits 31:26 + s_cmp_eq_u32 ttmp10, 0xd4000000 // If 31:26 = 0x35, this is VOP3 or VOP3SD + s_cbranch_scc1 L_FIXUP_CHECK_VOP3 // If VOP3 or VOP3SD, need to check SRC2_9, SRC1_9, SRC0_9 + // Not VOP1, VOP2, VOPC, VOP3, or VOP3SD. + // Check for VOPD + s_cmp_eq_u32 ttmp10, 0xc8000000 // If 31:26 = 0x32, this is VOPD + s_cbranch_scc1 L_FIXUP_CHECK_VOPD // If VOPD, need to check OpX, OpY, SRCX0 and SRCY0 + // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD. + // Check if we are VOPD3 + s_and_b32 ttmp10, ttmp14, 0xff000000 // Bits 31:24 + s_cmp_eq_u32 ttmp10, 0xcf000000 // If 31:24 = 0xcf, this is VOPD3 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // If VOPD3, 3 DWORD inst + // Not VOP1, VOP2, VOPC, VOP3, VOP3SD, VOPD, or VOPD3. + // Check if we are in the middle of VOP3PX. + s_and_b32 ttmp13, ttmp14, 0xffff0000 // Bits 31:16 + s_cmp_eq_u32 ttmp13, 0xcc330000 // If 31:16 = 0xcc33, this is 8 bytes past VOP3PX + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE + s_cmp_eq_u32 ttmp13, 0xcc880000 // If 31:16 = 0xcc88, this is 8 bytes past VOP3PX + s_cbranch_scc1 L_FIXUP_VOP3PX_MIDDLE + // Might be in VOP3P, but we must ensure we are not VOP3PX2 + s_cmp_eq_u32 ttmp13, 0xcc350000 // If 31:16 = 0xcc35, this is VOP3PX2 + s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed + s_cmp_eq_u32 ttmp13, 0xcc3a0000 // If 31:16 = 0xcc3a, this is VOP3PX2 + s_cbranch_scc1 L_FIXUP_DONE // If VOP3PX2, no fixup needed + // Check if we are VOP3P + s_cmp_eq_u32 ttmp10, 0xcc000000 // If 31:24 = 0xcc, this is VOP3P + s_cbranch_scc0 L_FIXUP_DONE // Not in VOP3P, so instruction is not VOP1, VOP2, + // VOPC, VOP3, VOP3SD, VOP3P, VOPD, or VOPD3 + // No fixup needed. + // Fall-through if we are in VOP3P to check SRC2_9, SRC1_9, and SRC0_9 +L_FIXUP_CHECK_VOP3: + // Start with Src0, which is in bits 8:0 of second instruction DW, ttmp15 + s_and_b32 ttmp10, ttmp15, 0x1ff // Mask out unused bits + // Src0_9 == Literal constant 32, DPP16, DPP8, and DPP8FI means 3 DWORDs + s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + s_cmp_eq_u32 ttmp10, 0xfa // 0xfa == 250 = DPP16 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + s_sub_co_i32 ttmp10, ttmp10, 0xe9 // DPP8 is 0xe9, DPP8FI is 0xea + s_cmp_le_u32 ttmp10, 0x1 // 0==0xe9, 1==0xea + s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst + s_and_b32 ttmp10, ttmp15, 0x3fe00 // Next is Src1, which is in 17:9 + s_cmp_eq_u32 ttmp10, 0x1fe00 // 0xff == 255 = Literal constant32 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + s_and_b32 ttmp10, ttmp15, 0x7fc0000 // Next is Src2, which is in 26:18 + s_cmp_eq_u32 ttmp10, 0x3fc0000 // 0xff == 255 = Literal constant32 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + s_branch L_FIXUP_TWO_DWORD // No special encodings, VOP3* is 2 Dword + +L_FIXUP_CHECK_VOPD: + // OpX being V_DUAL_FMA*K_F32 means 3 DWORDs + s_bfe_u32 ttmp10, ttmp14, (22 | (4 << 0x10)) // OPX is bits 25:22 + s_sub_co_i32 ttmp10, ttmp10, 0x1 // V_DUAL_FMAAK_F32 is 0x1, V_DUAL_FMAMK_F32 is 0x2 + s_cmp_le_u32 ttmp10, 0x1 // 0==0x1, 1==0x2 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst + // OpY being V_DUAL_FMA*K_F32 means 3 DWORDs + s_bfe_u32 ttmp10, ttmp14, (17 | (5 << 0x10)) // OPX is bits 21:17 + s_sub_co_i32 ttmp10, ttmp10, 0x1 // V_DUAL_FMAAK_F32 is 0x1, V_DUAL_FMAMK_F32 is 0x2 + s_cmp_le_u32 ttmp10, 0x1 // 0==0x1, 1==0x2 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // If either, this is 3 DWORD inst + // SRCX0 == Literal constant 32 means 3 DWORDs + s_and_b32 ttmp10, ttmp14, 0x1ff // SRCX0 is in bits 8:0 of 1st DWORD + s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + // SRCY0 == Literal constant 32 means 3 DWORDs + s_and_b32 ttmp10, ttmp15, 0x1ff // SRCY0 is in bits 8:0 of 2nd DWORD + s_cmp_eq_u32 ttmp10, 0xff // 0xff == 255 = Literal constant32 + s_cbranch_scc1 L_FIXUP_THREE_DWORD // 3 DWORD inst + // If otherwise, no special encodings. Default VOPD is 2 Dword + // Fall-thru if true, because this is a 2 DWORD inst +L_FIXUP_TWO_DWORD: + s_wait_kmcnt 0 // Wait for PC+2 and PC+3 to arrive in ttmp2 and ttmp3 + s_mov_b32 ttmp15, ttmp2 // Move possible S_SET_VGPR_MSB into ttmp15 + s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB + +L_FIXUP_THREE_DWORD: + s_wait_kmcnt 0 // Wait for PC+2 and PC+3 to arrive in ttmp2 and ttmp3 + s_mov_b32 ttmp15, ttmp3 // Move possible S_SET_VGPR_MSB into ttmp15 + s_branch L_FIXUP_ONE_DWORD // Go to common logic that checks if it is S_SET_VGPR_MSB + +L_FIXUP_VOP3PX_MIDDLE: + s_sub_co_u32 ttmp0, ttmp0, 8 // Rewind PC 8 bytes to beginning of instruction + s_sub_co_ci_u32 ttmp1, ttmp1, 0 + s_branch L_FIXUP_TWO_DWORD // 2 DWORD inst (2nd half of a 4 DWORD inst) + +L_FIXUP_DONE: + s_wait_kmcnt 0 // Ensure load of ttmp2 and ttmp3 is done +end +#endif diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 6869e07a2fff2..dd2d93f6824ee 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -100,6 +100,7 @@ var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 +var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT = 22 var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 @@ -112,6 +113,8 @@ var SQ_WAVE_TRAPSTS_POST_SAVECTX_SIZE = 21 var SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK = 0x800 var SQ_WAVE_TRAPSTS_EXCP_HI_MASK = 0x7000 var SQ_WAVE_TRAPSTS_XNACK_ERROR_MASK = 0x10000000 +var SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK = 0x4000000 +var SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT = 26 var SQ_WAVE_MODE_EXCP_EN_SHIFT = 12 var SQ_WAVE_MODE_EXCP_EN_ADDR_WATCH_SHIFT = 19 @@ -125,12 +128,23 @@ var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI deb var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 +var TTMP_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP_HOST_TRAP_ENABLED_MASK = 0x1000000 +var TTMP_FEATURES_ENABLED_FLAGS_SHIFT = TTMP_DEBUG_TRAP_ENABLED_SHIFT +var TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT = 25 +var TTMP_STOCHASTIC_TRAP_ENABLED_MASK = 0x2000000 +var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK | TTMP_STOCHASTIC_TRAP_ENABLED_MASK /* Save */ var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 var S_SAVE_PC_HI_HT_MASK = 0x01000000 +var S_SAVE_PC_HI_HT_SHIFT = 24 +var S_SAVE_PC_HI_NEED_2ND_LVL_TH = 29 // Only used by the 1st level trap handler to remember if + // we saw a trap type that the driver could not mask, or + // a maskable trap that should not be masked. This is + // indicates that we must go to the 2nd level trap handler. var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 @@ -156,9 +170,15 @@ var s_save_m0 = ttmp5 var s_save_ttmps_lo = s_save_tmp //no conflict var s_save_ttmps_hi = s_save_trapsts //no conflict #if ASIC_FAMILY >= CHIP_GC_9_4_3 -var s_save_ib_sts = ttmp13 +var s_save_ib_sts = ttmp13 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request + // so bits 22:0 are available for stashing next variable's backup. +var s_tma_flags = ttmp7 // free #else -var s_save_ib_sts = ttmp11 +var s_save_ib_sts = ttmp11 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request, bit 6 is no-scratch, bits 5-0 are wave-in-wg + // so bits 22:7 are available for stashing next variable's backup +var s_tma_flags = ttmp13 // free #endif /* Restore */ @@ -222,13 +242,39 @@ L_SKIP_RESTORE: s_getreg_b32 s_save_trapsts, hwreg(HW_REG_TRAPSTS) +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // Ignore PERF_SNAPSHOT if SAVECTX is also present + s_and_b32 ttmp2, s_save_trapsts, (SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK) + s_cmp_eq_u32 ttmp2, (SQ_WAVE_TRAPSTS_SAVECTX_MASK | SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_MASK) + s_cbranch_scc0 L_NO_SAVE_AND_PERF_SNAP + s_bitset0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT, 1), 0 +L_NO_SAVE_AND_PERF_SNAP: +#endif + + // Ignore Host Trap if SAVECTX is also present + s_bitcmp0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT + s_bitcmp0_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_NO_SAVE_AND_HT +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_bitset0_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0 +#endif + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_HT_MASK | S_SAVE_PC_HI_TRAP_ID_MASK) +L_NO_SAVE_AND_HT: + s_and_b32 ttmp2, s_save_status, SQ_WAVE_STATUS_HALT_MASK s_cbranch_scc0 L_NOT_HALTED L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK - s_cbranch_scc1 L_FETCH_2ND_TRAP + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_bitcmp1_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#endif L_CHECK_SAVE: s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save @@ -246,12 +292,11 @@ L_NOT_HALTED: // Any concurrent SAVECTX will be handled upon re-entry once halted. // Check non-maskable exceptions. memory_violation, illegal_instruction - // and debugger (host trap, wave start/end, trap after instruction) - // exceptions always cause the wave to enter the trap handler. + // and debugger (wave start/end, trap after instruction) exceptions always + // cause the wave to enter the trap handler. s_and_b32 ttmp2, s_save_trapsts, \ SQ_WAVE_TRAPSTS_MEM_VIOL_MASK | \ SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK | \ - SQ_WAVE_TRAPSTS_HOST_TRAP_MASK | \ SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK | \ SQ_WAVE_TRAPSTS_WAVE_END_MASK | \ SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK @@ -274,9 +319,15 @@ L_NOT_ADDR_WATCH: s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_TRAP_ID: - // Check trap_id != 0 + // Check trap_id != 0. If this is a host trap (ttmp1.HT == 1), trap_id is + // non 0, but we defer that part of the check until later as this exception + // is driver maskable. We need to make sure that all non-driver-maskable + // exceptions are accounted for before checking for driver-maskable ones. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_SKIP_CHECK_TRAP_ID s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP +L_SKIP_CHECK_TRAP_ID: if SINGLE_STEP_MISSED_WORKAROUND // Prioritize single step exception over context save. @@ -286,16 +337,28 @@ if SINGLE_STEP_MISSED_WORKAROUND s_cbranch_scc1 L_FETCH_2ND_TRAP end + // Check TTMP1 bits 24 (HT) == 1 + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE + +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // Check for perf snapshot + s_bitcmp1_b32 s_save_trapsts, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE +#endif + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH +L_FETCH_2ND_TRAP_DRIVER_MASKABLE: // Preserve and clear scalar XNACK state before issuing scalar reads. save_and_clear_ib_sts(ttmp14) // Read second-level TBA/TMA from first-level TMA and jump if available. - // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) - // ttmp12 holds SQ_WAVE_STATUS + // ttmp[2:5] and s_tma_flags can be used (others hold SPI-initialized debug + // data) ttmp12 holds SQ_WAVE_STATUS s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 @@ -304,18 +367,65 @@ L_FETCH_2ND_TRAP: s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag - s_waitcnt lgkmcnt(0) - s_lshl_b32 ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp2 - + s_load_dword s_tma_flags, [ttmp14, ttmp15], 0x10 glc:1 //Load the debug enables and host trap enabled flags s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA - s_waitcnt lgkmcnt(0) s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) + // Put debug enable bit, stochastic trap bit, and host trap bit into SAVE_IB_STS register, bits + // 23-25, respectively + s_lshl_b32 s_tma_flags, s_tma_flags, TTMP_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_FEATURES_ENABLED_FLAGS_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, s_tma_flags + + // If not a host trap, then driver cannot mask this. Go to the 2nd-level + // trap handler now. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc0 L_CHECK_STOC + + // If driver said host traps are OK, go to the 2nd-level handler now. + s_bitcmp1_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_cbranch_scc0 L_MASKED_HT + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_branch L_CHECK_STOC + +L_MASKED_HT: + // The driver said host traps are masked, zero out host trap and trapID. + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0x0 +#endif + +L_CHECK_STOC: +#if ASIC_FAMILY >= CHIP_GC_9_4_3 + // If TRAPSTS says we did not have a stochastic sampling trap, then driver cannot mask this + s_getreg_b32 ttmp7, hwreg(HW_REG_TRAPSTS) + s_bitcmp1_b32 ttmp7, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT + s_cbranch_scc0 L_CHECK_REMAINING_EXCP + // If stochastic sampling trap was requested, should it be masked by the driver? + s_bitcmp1_b32 s_save_ib_sts, TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT + // If driver said stochastic traps are OK, allow the 2nd-level handler to take host trap + s_cbranch_scc0 L_MASKED_STOC + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_branch L_CHECK_REMAINING_EXCP + +L_MASKED_STOC: + // Otherwise, zero out TRAPSTS.stochastic_perf_snapshot bit, so possible 2nd level does not handle it + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_PERF_SNAPSHOT_SHIFT, 1), 0x0 +#endif + +L_CHECK_REMAINING_EXCP: + // Check if we found any reason to go to the 2nd level trap handler. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH // zero this out + s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler + +L_GOTO_2ND_TRAP: + // Reset bits used temporarily by 1st level trap handler so they do not + // leak to the 2nd level trap handler. + s_bitset0_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_ib_sts, TTMP_STOCHASTIC_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NEED_2ND_LVL_TH s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ais.c b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c new file mode 100644 index 0000000000000..7eea81b7d54ad --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ais.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include +#include +#include +#include +#include +#include +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +/* + * get_pci_dev_from_file - Get the PCI device that is hosting the file. + * For e.g., the NVME PCI device that is hosting the file. + * + * @file: The file pointer from which to derive the PCI device. + * Returns: Pointer to the PCI device if found, NULL otherwise. + */ +static struct pci_dev *get_pci_dev_from_file(struct file *file) +{ + struct device *dev; + struct pci_dev *pdev = NULL; + + if (!file->f_path.mnt || !file->f_path.mnt->mnt_sb || + !file->f_path.mnt->mnt_sb->s_bdev) { + pr_err("Invalid file path or mount point\n"); + return NULL; + } +#ifdef HAVE_BLOCK_DEVICE_BD_DEVICE + dev = file->f_path.mnt->mnt_sb->s_bdev->bd_device.parent; +#else + dev = disk_to_dev(file->f_path.mnt->mnt_sb->s_bdev->bd_disk)->parent; +#endif + if (!dev) { + pr_debug("No parent device found for the file\n"); + return NULL; + } + + /* Traverse up the device hierarchy to find a PCI device */ + while (dev && !dev_is_pci(dev)) + dev = dev->parent; + + if (dev && dev_is_pci(dev)) + pdev = to_pci_dev(dev); + + + return pdev; +} + +static struct bio_vec *amdgpu_init_bvec(struct sg_table *sgt, uint64_t size, + unsigned int *nr_segs) +{ + struct scatterlist *sg; + struct bio_vec *bvec; + uint64_t sg_len; + int64_t sg_offset = 0; + struct page *page; + unsigned int i, k = 0; + + bvec = kvcalloc(sgt->nents, sizeof(*bvec), GFP_KERNEL); + if (!bvec) + return NULL; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + page = pfn_to_page(PHYS_PFN(sg_dma_address(sg))); + if (!page || !is_pci_p2pdma_page(page)) { + /* If the page is not PCI P2P, we cannot use it */ + pr_err("Invalid PCI P2P page!\n"); + kvfree(bvec); + return NULL; + } + sg_offset = sg_dma_address(sg) - __pfn_to_phys(page_to_pfn(page)); + if (sg_offset < 0 || sg_offset >= sg->length) { + pr_err("Invalid sg_offset: %lld\n", sg_offset); + kvfree(bvec); + return NULL; + } + + sg_len = min(sg->length, size); + pr_debug("sg[%d] offset:%llx, size:%llx\n", i, sg_offset, sg_len); + + bvec[k].bv_page = page; + bvec[k].bv_len = sg_len; + bvec[k].bv_offset = sg_offset; + k++; + + size -= sg_len; + if ((int64_t)size <= 0) + break; + } + + *nr_segs = k; + return bvec; +} + +/* Each VRAM page uses sizeof(struct page) on system memory */ +#define AIS_P2P_PAGE_STRUCT_SIZE(size) ((size)/PAGE_SIZE * sizeof(struct page)) + +int kfd_ais_init(struct amdgpu_device *adev) +{ +#ifdef CONFIG_PCI_P2PDMA + int ret; + struct page *p2p_page = NULL; + unsigned long pci_start_pfn = PHYS_PFN(pci_resource_start(adev->pdev, 0)); + unsigned long size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); + bool is_large_bar = adev->gmc.visible_vram_size && + adev->gmc.real_vram_size == adev->gmc.visible_vram_size; + + if (amdgpu_sriov_vf(adev)) { + dev_dbg(adev->dev, "AIS: not supported on SRIOV\n"); + return 0; + } + + /* AIS support limited to large BAR dGPUs */ + if (adev->flags & AMD_IS_APU || adev->gmc.xgmi.connected_to_cpu || !is_large_bar) { + dev_dbg(adev->dev, "AIS: only supported for large BAR dGPU\n"); + return 0; + } + + p2p_page = pfn_valid(pci_start_pfn) ? pfn_to_page(pci_start_pfn) : NULL; + if (p2p_page && is_pci_p2pdma_page(p2p_page)) { + adev->kfd.dev->ais_initialized = true; + dev_dbg(adev->dev, "AIS: PCI P2PDMA resource already exists\n"); + return 0; + } + + ret = pci_p2pdma_add_resource(adev->pdev, 0 /*bar*/, 0 /*whole VRAM*/, + 0 /*offset*/); + if (ret) { + dev_dbg(adev->dev, "AIS: Failed to add PCI P2PDMA resource for VRAM %d\n", ret); + return 0; + } + dev_dbg(adev->dev, "AIS: reserve %ldMB system memory for VRAM (P2P) pages struct\n", + AIS_P2P_PAGE_STRUCT_SIZE(size) >> 20); + + amdgpu_amdkfd_reserve_system_mem(AIS_P2P_PAGE_STRUCT_SIZE(size)); + dev_info(adev->dev, "AIS: registered %ldMB device memory\n", size >> 20); + + adev->kfd.dev->ais_initialized = true; +#else + dev_dbg(adev->dev, "AIS: not supported. Check CONFIG_PCI_P2PDMA\n"); +#endif + return 0; +} + +void kfd_ais_deinit(struct amdgpu_device *adev) +{ + adev->kfd.dev->ais_initialized = false; +} + +#ifdef HAVE_STRUCT_XARRAY +static int kfd_ais_init_attr(struct attribute *attr, struct pci_dev *pdev, bool is_read) +{ + char *filename = kzalloc(MAX_SYSFS_FILENAME_LEN, GFP_KERNEL); + char *suffix; + + if (!filename) + return -ENOMEM; + + if (is_read) + suffix = "PCI_in"; + else + suffix = "PCI_out"; + + snprintf(filename, MAX_SYSFS_FILENAME_LEN, + "%04x:%02x:%02x.%d:%s", pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), suffix); + + attr->name = filename; + attr->mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(attr); + + return 0; +} + +static int kfd_ais_update_counters(uint64_t size_copied, struct pci_dev *pdev, + struct kfd_process_device *pdd, bool is_read) +{ + struct ais_counter_entry *counter; + int ret = 0; + + xa_lock(&pdd->ais_counters_xa); + counter = (struct ais_counter_entry *)xa_load(&pdd->ais_counters_xa, pdev->devfn); + if (counter) { + if (is_read) + counter->bytes_read += size_copied; + else + counter->bytes_written += size_copied; + + goto out; + } + + counter = kzalloc(sizeof(struct ais_counter_entry), GFP_KERNEL); + if (!counter) { + ret = -ENOMEM; + goto out; + } + + counter->pci_devfn = pdev->devfn; + if (is_read) + counter->bytes_read = size_copied; + else + counter->bytes_written = size_copied; + + ret = __xa_insert(&pdd->ais_counters_xa, pdev->devfn, counter, GFP_KERNEL); + if (ret) { + /* xa_insert failing means the entry is not empty, which shouldn't be possible */ + kvfree(counter); + goto out; + } + + ret = kfd_ais_init_attr(&counter->attr_bytes_read, pdev, true); + if (ret) + goto out; + ret = sysfs_create_file(pdd->kobj_ais, &counter->attr_bytes_read); + if (ret) + goto out; + + ret = kfd_ais_init_attr(&counter->attr_bytes_written, pdev, false); + if (ret) + goto out; + ret = sysfs_create_file(pdd->kobj_ais, &counter->attr_bytes_written); + +out: + xa_unlock(&pdd->ais_counters_xa); + return 0; +} +#endif /* HAVE_STRUCT_XARRAY */ + +int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, + struct kfd_ais_in_args *in, struct kfd_process_device *pdd, + uint64_t *size_copied) +{ + struct file *filep; + struct pci_dev *pdev; + struct sg_table *sgt; + int nr_segs = 0, retry = 3; + struct iov_iter iter; + struct kiocb kiocb; + struct bio_vec *bvec; + loff_t cur_pos; + int ret = 0; + bool is_read = (in->op == KFD_IOC_AIS_READ); + + /* For now support only page-aligned offsets and sizes. It could be + * improved to fs block size in the future + */ + if (!PAGE_ALIGNED(in->file_offset) || !PAGE_ALIGNED(in->size)) + return -EINVAL; + + filep = fget((unsigned int)in->fd); + if (!filep) + return -EBADF; + + pdev = get_pci_dev_from_file(filep); + if (!pdev) { + ret = -ENODEV; + goto out; + } + + if (pci_p2pdma_distance(pdev, adev->dev, false) < 0) { + dev_info(adev->dev, "DMA-BUF p2p not accessible!\n"); + ret = -ENODEV; + goto out; + } + + if (WARN_ON(bo->preferred_domains != AMDGPU_GEM_DOMAIN_VRAM)) { + ret = -EINVAL; + goto out; + } + /* Use NULL instead of peer pdev. This is deliberate so that + * sg_dma_address is set to physical address instead of dma mapped + * address. This helps in getting struct p2p_page that bvec needs. + * This should work irrespective of iommu + */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table(adev, bo, 0, in->handle_offset, + in->size, NULL, DMA_BIDIRECTIONAL, &sgt); + if (ret) { + dev_err(adev->dev, "AIS: failed to get SG table\n"); + goto out; + } + + bvec = amdgpu_init_bvec(sgt, in->size, &nr_segs); + if (!bvec) { + ret = -ENOMEM; + goto put_sg; + } + + iov_iter_bvec(&iter, is_read ? ITER_DEST : ITER_SOURCE, bvec, nr_segs, in->size); + init_sync_kiocb(&kiocb, filep); + kiocb.ki_pos = cur_pos = in->file_offset; + if (filep->f_flags & O_DIRECT) + kiocb.ki_flags |= IOCB_DIRECT; + + *size_copied = 0; + while (kiocb.ki_pos < in->file_offset + in->size) { + if (is_read) + ret = vfs_iocb_iter_read(filep, &kiocb, &iter); + else + ret = vfs_iocb_iter_write(filep, &kiocb, &iter); + if (ret < 0) { + dev_err(adev->dev, "AIS: vfs transfer failed %d\n", ret); + break; + } + if (ret == 0 && is_read) { + break; /* EOF */ + } + if (cur_pos == kiocb.ki_pos) { + /* No progress made, retry */ + if (retry-- > 0) { + dev_warn(adev->dev, "AIS: vfs transfer stalled, retrying...\n"); + continue; + } + dev_err(adev->dev, "AIS: vfs transfer stalled, giving up\n"); + ret = -EIO; + break; + } + cur_pos = kiocb.ki_pos; + *size_copied += ret; + } + + + if (ret > 0 || (ret == 0 && is_read)) { + dev_dbg(adev->dev, "AIS: vfs transfer %llu bytes\n", *size_copied); +#ifdef HAVE_STRUCT_XARRAY + ret = kfd_ais_update_counters(*size_copied, pdev, pdd, is_read); +#endif + } + + kvfree(bvec); +put_sg: + amdgpu_amdkfd_gpuvm_put_sg_table(bo, NULL, DMA_BIDIRECTIONAL, sgt); +out: + fput(filep); + return ret < 0 ? ret : 0; + +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 22925df6a791b..7ae654d7800c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -21,6 +21,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include @@ -39,6 +40,10 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_ipc.h" +#include "kfd_trace.h" +#include "kfd_pc_sampling.h" + #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -62,7 +67,7 @@ static const struct file_operations kfd_fops = { static int kfd_char_dev_major = -1; struct device *kfd_device; -static const struct class kfd_class = { +static struct class kfd_class = { .name = kfd_dev_name, }; @@ -164,8 +169,13 @@ static int kfd_release(struct inode *inode, struct file *filep) { struct kfd_process *process = filep->private_data; - if (process) - kfd_unref_process(process); + if (!process) + return 0; + + if (process->context_id != KFD_CONTEXT_ID_PRIMARY) + kfd_process_notifier_release_internal(process); + + kfd_unref_process(process); return 0; } @@ -200,7 +210,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; @@ -216,27 +226,32 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, pr_debug("Size lower. clamped to KFD_MIN_QUEUE_RING_SIZE"); } - if (!access_ok((const void __user *) args->read_pointer_address, + if ((args->metadata_ring_size != 0) && !is_power_of_2(args->metadata_ring_size)) { + pr_err("Metadata ring size must be a power of 2 or 0\n"); + return -EINVAL; + } + + if (!kcl_access_ok((const void __user *) args->read_pointer_address, sizeof(uint32_t))) { pr_err("Can't access read pointer\n"); return -EFAULT; } - if (!access_ok((const void __user *) args->write_pointer_address, + if (!kcl_access_ok((const void __user *) args->write_pointer_address, sizeof(uint32_t))) { pr_err("Can't access write pointer\n"); return -EFAULT; } if (args->eop_buffer_address && - !access_ok((const void __user *) args->eop_buffer_address, + !kcl_access_ok((const void __user *) args->eop_buffer_address, sizeof(uint32_t))) { pr_debug("Can't access eop buffer"); return -EFAULT; } if (args->ctx_save_restore_address && - !access_ok((const void __user *) args->ctx_save_restore_address, + !kcl_access_ok((const void __user *) args->ctx_save_restore_address, sizeof(uint32_t))) { pr_debug("Can't access ctx save restore buffer"); return -EFAULT; @@ -250,6 +265,9 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, q_properties->priority = args->queue_priority; q_properties->queue_address = args->ring_base_address; q_properties->queue_size = args->ring_size; + if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL) + q_properties->metadata_queue_size = args->metadata_ring_size; + q_properties->read_ptr = (void __user *)args->read_pointer_address; q_properties->write_ptr = (void __user *)args->write_pointer_address; q_properties->eop_ring_buffer_address = args->eop_buffer_address; @@ -454,7 +472,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; @@ -1053,10 +1071,19 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + struct vm_area_struct *vma; + uint64_t cpuva = 0; + unsigned int mem_type = 0; if (args->size == 0) return -EINVAL; + if (p->context_id != KFD_CONTEXT_ID_PRIMARY && (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR)) { + pr_debug("USERPTR is not supported on non-primary kfd_process\n"); + + return -EOPNOTSUPP; + } + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) /* Flush pending deferred work to avoid racing with deferred actions * from previous memory map changes (e.g. munmap). @@ -1116,7 +1143,38 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, goto err_unlock; } - if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { + if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { + /* Check if the userptr corresponds to another (or third-party) + * device local memory. If so treat is as a doorbell. User + * space will be oblivious of this and will use this doorbell + * BO as a regular userptr BO + */ + mmap_read_lock(current->mm); + vma = find_vma(current->mm, args->mmap_offset); + if (vma && args->mmap_offset >= vma->vm_start && + (vma->vm_flags & VM_IO)) { + unsigned long pfn; + + err = follow_pfn(vma, args->mmap_offset, &pfn); + mmap_read_unlock(current->mm); + if (err) { + pr_debug("Failed to get PFN: %ld\n", err); + goto err_unlock; + } + flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; + flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; + offset = (pfn << PAGE_SHIFT); + } else { + mmap_read_unlock(current->mm); + if (offset & (PAGE_SIZE - 1)) { + pr_debug("Unaligned userptr address:%llx\n", + offset); + err = -EINVAL; + goto err_unlock; + } + cpuva = offset; + } + } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { if (args->size != kfd_doorbell_process_slice(dev->kfd)) { err = -EINVAL; goto err_unlock; @@ -1146,7 +1204,13 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (err) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + mem_type = flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, args->size, cpuva, mem_type, -1); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1190,7 +1254,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, { struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; - void *mem; + struct kfd_bo *buf_obj; int ret; uint64_t size = 0; @@ -1212,15 +1276,15 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, goto err_pdd; } - mem = kfd_process_device_translate_handle( - pdd, GET_IDR_HANDLE(args->handle)); - if (!mem) { + buf_obj = kfd_process_device_find_bo(pdd, + GET_IDR_HANDLE(args->handle)); + if (!buf_obj) { ret = -EINVAL; - goto err_unlock; + goto err_pdd; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, - (struct kgd_mem *)mem, pdd->drm_priv, &size); + buf_obj->mem, pdd->drm_priv, &size); /* If freeing the buffer failed, leave the handle in place for * clean-up during process tear-down. @@ -1248,6 +1312,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, int i; uint32_t *devices_arr = NULL; + trace_kfd_map_memory_to_gpu_start(p); if (!args->n_devices) { pr_debug("Device IDs array empty\n"); return -EINVAL; @@ -1319,6 +1384,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ((struct kgd_mem *)mem)->domain); + goto map_memory_to_gpu_failed; } args->n_success = i+1; @@ -1341,6 +1407,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, } kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Success"); return err; get_process_device_data_failed: @@ -1351,6 +1419,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, mutex_unlock(&p->mutex); copy_from_user_failed: kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Failed"); return err; } @@ -1443,7 +1513,6 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, mutex_unlock(&p->mutex); kfree(devices_arr); - return 0; bind_process_to_device_failed: @@ -1584,7 +1653,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, if (r) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -1604,6 +1674,51 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, return r; } +static int kfd_ioctl_ipc_export_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_export_handle_args *args = data; + struct kfd_process_device *pdd; + int r; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) + return -EINVAL; + + r = kfd_ipc_export_as_handle(pdd->dev, p, args->handle, args->share_handle, + args->flags); + if (r) + pr_err("Failed to export IPC handle\n"); + + return r; +} + +static int kfd_ioctl_ipc_import_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_import_handle_args *args = data; + struct kfd_process_device *pdd; + int r; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) + return -EINVAL; + + r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, + args->va_addr, &args->handle, + &args->mmap_offset, &args->flags, false); + if (r) + pr_err("Failed to import IPC handle\n"); + + return r; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -1656,6 +1771,21 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated DBG API */ +static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, + struct kfd_process *p, void *data) +{ + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; +} + +/* Place holder for deprecated CMA API */ +static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; +} + /* Handle requests for watching SMI events */ static int kfd_ioctl_smi_events(struct file *filep, struct kfd_process *p, void *data) @@ -1713,6 +1843,12 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) struct kfd_ioctl_svm_args *args = data; int r = 0; + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) { + pr_debug("SVM ioctl not supported on non-primary kfd process\n"); + + return -EOPNOTSUPP; + } + pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n", args->start_addr, args->size, args->op, args->nattr); @@ -1738,6 +1874,45 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ioctl_rlc_spm(struct file *filep, + struct kfd_process *p, void *data) +{ + return kfd_rlc_spm(p, data); +} + +static int kfd_ioctl_pc_sample(struct file *filep, + struct kfd_process *p, void __user *data) +{ + struct kfd_ioctl_pc_sample_args *args = data; + struct kfd_process_device *pdd; + int ret = 0; + + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { + pr_err("PC Sampling does not support sched_policy %i", sched_policy); + return -EINVAL; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + + if (!pdd) { + pr_debug("could not find gpu id 0x%x.", args->gpu_id); + ret = -EINVAL; + } else if (args->op == KFD_IOCTL_PCS_OP_START) { + pdd = kfd_bind_process_to_device(pdd->dev, p); + if (IS_ERR(pdd)) { + pr_debug("failed to bind process %p with gpu id 0x%x", p, args->gpu_id); + ret = -ESRCH; + } + } + + if (!ret) + ret = kfd_pc_sample(pdd, args); + mutex_unlock(&p->mutex); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -1830,11 +2005,11 @@ static uint32_t get_process_num_bos(struct kfd_process *p) /* Run over all PDDs of the process */ for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; - void *mem; + struct kfd_bo *buf_obj; int id; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { - struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kgd_mem *kgd_mem = (struct kgd_mem *)buf_obj->mem; if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) num_of_bos++; @@ -1900,7 +2075,7 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct kfd_criu_bo_priv_data *bo_privs; struct file **files = NULL; int ret = 0, pdd_index, bo_index = 0, id; - void *mem; + struct kfd_bo *buf_obj; bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); if (!bo_buckets) @@ -1923,12 +2098,12 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct amdgpu_bo *dumper_bo; struct kgd_mem *kgd_mem; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { struct kfd_criu_bo_bucket *bo_bucket; struct kfd_criu_bo_priv_data *bo_priv; int i, dev_idx = 0; - kgd_mem = (struct kgd_mem *)mem; + kgd_mem = (struct kgd_mem *)buf_obj->mem; dumper_bo = kgd_mem->bo; /* Skip checkpointing BOs that are used for Trap handler @@ -1982,8 +2157,18 @@ static int criu_checkpoint_bos(struct kfd_process *p, bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; } - pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" + if (kgd_mem->ipc_obj) { + bo_priv->ipc_flags = kgd_mem->ipc_obj->flags; + bo_priv->is_imported = kgd_mem->is_imported; + + memcpy(bo_priv->ipc_share_handle, + kgd_mem->ipc_obj->share_handle, + sizeof(kgd_mem->ipc_obj->share_handle)); + } + + pr_debug("[%d]bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx" "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", + bo_index, bo_bucket->size, bo_bucket->addr, bo_bucket->offset, @@ -2291,6 +2476,98 @@ static int criu_restore_devices(struct kfd_process *p, return ret; } +static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, + struct kfd_criu_bo_bucket *bo_bucket, + struct kfd_criu_bo_priv_data *bo_priv, + struct kgd_mem **kgd_mem) +{ + uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); + struct kfd_node *dev = pdd->dev; + struct kfd_bo *kfd_bo; + int ret, idr_handle; + uint64_t offset; + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, &offset, NULL, true); + if (ret) { + unsigned int mem_type; + + if (ret != -EINVAL) { + pr_err("Failed to import IPC handle ret:%d\n", ret); + return ret; + } + + /* kfd_ipc_import_handle returns -EINVAL if the ipc share_handle does not exist. + * In that case create a new BO and create a new ipc share_handle by calling + * amdgpu_amdkfd_gpuvm_export_ipc_obj. + */ + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, + bo_bucket->size, pdd->drm_priv, + kgd_mem, &offset, + bo_bucket->alloc_flags, true); + if (ret) { + pr_err("Could not create the BO\n"); + return ret; + } + + pr_debug("New IPC BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", + bo_bucket->size, bo_bucket->addr, offset); + + mem_type = bo_bucket->alloc_flags & + (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, + bo_bucket->size, 0, mem_type, + bo_priv->idr_handle); + if (idr_handle < 0) { + pr_err("Could not allocate idr\n"); + + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, pdd->drm_priv, + NULL); + return -ENOMEM; + } + + ret = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, *kgd_mem, + &(*kgd_mem)->ipc_obj, bo_priv->ipc_flags, + bo_priv->ipc_share_handle); + if (ret == -EINVAL) { + /* This is a race condition. The other process that owns this same IPC + * handle created the handle before this process. Delete BO and re-use + * import IPC handle created by the other process. + */ + ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, + pdd->drm_priv, NULL); + if (ret) + return ret; + + kfd_process_device_remove_obj_handle(pdd, idr_handle); + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, + bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, + &offset, NULL, true); + if (ret) + return ret; + } + } + + kfd_bo = kfd_process_device_find_bo(pdd, bo_priv->idr_handle); + if (!kfd_bo) { + pr_err("Failed to find BO\n"); + return -EINVAL; + } + + *kgd_mem = kfd_bo->mem; + (*kgd_mem)->is_imported = bo_priv->is_imported; + + bo_bucket->restored_offset = offset; + if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) + /* Update the VRAM usage count */ + atomic64_add(bo_bucket->size, &pdd->vram_usage); + + return 0; +} + static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, struct kfd_criu_bo_bucket *bo_bucket, struct kfd_criu_bo_priv_data *bo_priv, @@ -2299,6 +2576,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, int idr_handle; int ret; const bool criu_resume = true; + unsigned int mem_type = 0; u64 offset; if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { @@ -2335,9 +2613,17 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, bo_bucket->size, bo_bucket->addr, offset); /* Restore previous IDR handle */ - pr_debug("Restoring old IDR handle for the BO"); - idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, - bo_priv->idr_handle + 1, GFP_KERNEL); + mem_type = bo_bucket->alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, + bo_bucket->addr, + bo_bucket->size, + 0, mem_type, + bo_priv->idr_handle); if (idr_handle < 0) { pr_err("Could not allocate idr\n"); @@ -2365,11 +2651,14 @@ static int criu_restore_bo(struct kfd_process *p, struct kfd_criu_bo_priv_data *bo_priv, struct file **file) { + const uint32_t zero_handle[4] = { 0, 0, 0, 0 }; struct kfd_process_device *pdd; struct kgd_mem *kgd_mem; int ret; int j; + BUILD_BUG_ON(sizeof_field(struct kfd_ipc_obj, share_handle) != sizeof(zero_handle)); + pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, bo_priv->idr_handle); @@ -2380,7 +2669,11 @@ static int criu_restore_bo(struct kfd_process *p, return -ENODEV; } - ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (memcmp(bo_priv->ipc_share_handle, zero_handle, sizeof(zero_handle))) + ret = criu_restore_memory_of_gpu_ipc(pdd, bo_bucket, bo_priv, &kgd_mem); + else + ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (ret) return ret; @@ -2575,7 +2868,7 @@ static int criu_restore(struct file *filep, * Set the process to evicted state to avoid running any new queues before all the memory * mappings are ready. */ - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_RESTORE); if (ret) goto exit_unlock; @@ -2694,7 +2987,7 @@ static int criu_process_info(struct file *filep, goto err_unlock; } - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); if (ret) goto err_unlock; @@ -2779,32 +3072,19 @@ static int runtime_enable(struct kfd_process *p, uint64_t r_debug, * SET_SHADER_DEBUGGER clears any stale process context data * saved in MES. */ - if (pdd->dev->kfd->shared_resources.enable_mes) - kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + if (pdd->dev->kfd->shared_resources.enable_mes) { + ret = kfd_dbg_set_mes_debug_mode( + pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + if (ret) + return ret; + } } p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; p->runtime_info.r_debug = r_debug; - p->runtime_info.ttmp_setup = enable_ttmp_setup; - if (p->runtime_info.ttmp_setup) { - for (i = 0; i < p->n_pdds; i++) { - struct kfd_process_device *pdd = p->pdds[i]; - - if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { - amdgpu_gfx_off_ctrl(pdd->dev->adev, false); - pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - true, - pdd->dev->vm_info.last_vmid_kfd); - } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { - pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - false, - 0); - } - } - } + if (enable_ttmp_setup) + kfd_dbg_enable_ttmp_setup(p); retry: if (p->debug_trap_enabled) { @@ -2914,6 +3194,12 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v struct kfd_process_device *pdd = NULL; int r = 0; + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) { + pr_debug("Set debug trap ioctl can not be invoked on non-primary kfd process\n"); + + return -EOPNOTSUPP; + } + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { pr_err("Debugging does not support sched_policy %i", sched_policy); return -EINVAL; @@ -2958,10 +3244,16 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; } + if (target->context_id != KFD_CONTEXT_ID_PRIMARY) { + pr_debug("Set debug trap ioctl not supported on non-primary kfd process\n"); + r = -EOPNOTSUPP; + goto out; + } + /* Check if target is still PTRACED. */ rcu_read_lock(); if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE - && ptrace_parent(target->lead_thread) != current) { + && ptrace_parent(target->lead_thread) != current) { pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); r = -EPERM; } @@ -2971,6 +3263,11 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; mutex_lock(&target->mutex); + if (!!target->pc_sampling_ref) { + pr_debug("Cannot enable debug trap on PID:%d because PC Sampling active\n", args->pid); + r = -EBUSY; + goto unlock_out; + } if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); @@ -3121,6 +3418,224 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v return r; } +/* userspace programs need to invoke this ioctl explicitly on a FD to + * create a secondary kfd_process which replacing its primary kfd_process + */ +static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_process *process; + int ret; + + if (!filep->private_data || !p) + return -EINVAL; + + /* Each FD owns only one kfd_process */ + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) + return -EINVAL; + + mutex_lock(&kfd_processes_mutex); + if (p != filep->private_data) { + mutex_unlock(&kfd_processes_mutex); + return -EINVAL; + } + + process = create_process(current, false); + if (IS_ERR(process)) { + mutex_unlock(&kfd_processes_mutex); + return PTR_ERR(process); + } + + filep->private_data = process; + mutex_unlock(&kfd_processes_mutex); + + ret = kfd_create_process_sysfs(process); + if (ret) + pr_warn("Failed to create sysfs entry for the kfd_process"); + + /* Each open() increases kref of the primary kfd_process, + * so we need to reduce it here when we create a new secondary process replacing it + */ + kfd_unref_process(p); + + return 0; +} + +static inline uint32_t profile_lock_device(struct kfd_process *p, + uint32_t gpu_id, uint32_t op) +{ + struct kfd_process_device *pdd; + struct kfd_dev *kfd; + int status = -EINVAL; + + if (!p) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, gpu_id); + mutex_unlock(&p->mutex); + + if (!pdd || !pdd->dev || !pdd->dev->kfd) + return -EINVAL; + + kfd = pdd->dev->kfd; + + mutex_lock(&kfd->profiler_lock); + if (op == 1) { + if (!kfd->profiler_process) { + kfd->profiler_process = p; + status = 0; + } else if (kfd->profiler_process == p) { + status = -EALREADY; + } else { + status = -EBUSY; + } + } else if (op == 0 && kfd->profiler_process == p) { + kfd->profiler_process = NULL; + status = 0; + } + mutex_unlock(&kfd->profiler_lock); + + return status; +} + +static inline int kfd_profiler_pmc(struct kfd_process *p, + struct kfd_ioctl_pmc_settings *args) +{ + struct kfd_process_device *pdd; + struct device_queue_manager *dqm; + int status; + + /* Check if we have the correct permissions. */ + if (!perfmon_capable()) + return -EPERM; + + /* Lock/Unlock the device based on the parameter given in OP */ + status = profile_lock_device(p, args->gpu_id, args->lock); + if (status != 0) + return status; + + /* Enable/disable perfcount if requested */ + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + dqm = pdd->dev->dqm; + mutex_unlock(&p->mutex); + + dqm->ops.set_perfcount(dqm, args->perfcount_enable); + return status; +} + +static int kfd_ioctl_profiler(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_profiler_args *args = data; + + switch (args->op) { + case KFD_IOC_PROFILER_VERSION: + args->version = KFD_IOC_PROFILER_VERSION_NUM; + return 0; + case KFD_IOC_PROFILER_PC_SAMPLE: + return kfd_ioctl_pc_sample(filep, p, &args->pc_sample); + case KFD_IOC_PROFILER_PMC: + return kfd_profiler_pmc(p, &args->pmc); + } + return -EINVAL; +} + +static int kfd_ioctl_ais(struct file *filep, struct kfd_process *p, void *data) +{ + struct kfd_ioctl_ais_args *args = data; + struct kfd_ais_in_args *in = &args->in; + struct kfd_ais_out_args __user *out = &args->out, out_args = {0}; + struct kfd_process_device *pdd; + struct kfd_node *dev; + struct kfd_bo *buf_obj; + struct amdgpu_bo *bo; + int err; + + if (in->op != KFD_IOC_AIS_READ && in->op != KFD_IOC_AIS_WRITE) { + pr_debug("AIS: Invalid operation: %d\n", in->op); + err = -EINVAL; + goto err_inval; + } + + if (in->fd < 0) { + pr_debug("AIS: fd: %d\n", in->fd); + err = -EINVAL; + goto err_inval; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(in->handle)); + if (!pdd) { + pr_debug("AIS: Could not find gpu id 0x%llx\n", GET_GPU_ID(in->handle)); + err = -EINVAL; + goto err_pdd; + } + dev = pdd->dev; + if (!dev->kfd->ais_initialized) { + dev_dbg(dev->adev->dev, "AIS: is not initialized for device\n"); + err = -ENODEV; + goto err_pdd; + } + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + err = -ESRCH; + goto err_bind_process; + } + + buf_obj = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(in->handle)); + if (!buf_obj) { + err = -EINVAL; + goto err_bind_process; + } + bo = ((struct kgd_mem *)buf_obj->mem)->bo; + + /* Only VRAM BOs are supported */ + if (((struct kgd_mem *)buf_obj->mem)->domain != AMDGPU_GEM_DOMAIN_VRAM) { + dev_dbg(dev->adev->dev, "AIS: BO not in VRAM, but in %d\n", + ((struct kgd_mem *)buf_obj)->domain); + err = -EINVAL; + goto err_bind_process; + } + + /* + * Pin the BO before using it for AIS file I/O operations. + * Take a reference to prevent UAF if the BO is freed + * concurrently via FREE_MEMORY_OF_GPU. The reference ensures the + * BO remains valid until we unpin and release it. + */ + amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, NULL); + + err = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_VRAM); + if (err) { + pr_err("Pinning of buffer failed.\n"); + amdgpu_amdkfd_gpuvm_put_bo_ref(bo); + goto err_bind_process; + } + + mutex_unlock(&p->mutex); + + err = kfd_ais_rw_file(dev->adev, bo, in, pdd, &out_args.size_copied); + if (err) { + pr_err("Failed to %s AIS file: %d\n", + in->op == KFD_IOC_AIS_READ ? "read" : "write", err); + out_args.status = err; + } + + amdgpu_amdkfd_gpuvm_unpin_bo(bo); + amdgpu_amdkfd_gpuvm_put_bo_ref(bo); + memcpy(out, &out_args, sizeof(out_args)); + return err; + +err_pdd: +err_bind_process: + mutex_unlock(&p->mutex); +err_inval: + out_args.status = err; + memcpy(out, &out_args, sizeof(out_args)); + return err; +} + #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \ [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \ .cmd_drv = 0, .name = #ioctl} @@ -3239,9 +3754,35 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, kfd_ioctl_set_debug_trap, 0), -}; -#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_PROCESS, + kfd_ioctl_create_process, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_IMPORT_HANDLE, + kfd_ioctl_ipc_import_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, + kfd_ioctl_ipc_export_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, + kfd_ioctl_rlc_spm, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, + kfd_ioctl_cross_memory_copy_deprecated, 0), + + /* TODO: KFD_IOC_FLAG_PERFMON is not required for host-trap, disable first */ + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PC_SAMPLE, + kfd_ioctl_pc_sample, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PROFILER, + kfd_ioctl_profiler, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_AIS_OP, + kfd_ioctl_ais, 0), +}; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) { @@ -3255,12 +3796,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) int retcode = -EINVAL; bool ptrace_attached = false; - if (nr >= AMDKFD_CORE_IOCTL_COUNT) { - retcode = -ENOTTY; - goto err_i1; - } - - if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { + if (((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) || + ((nr >= AMDKFD_COMMAND_START_2) && (nr < AMDKFD_COMMAND_END_2))) { u32 amdkfd_size; ioctl = &amdkfd_ioctls[nr]; @@ -3319,6 +3856,14 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) } } + /* PC Sampling Monitor */ + if (unlikely(ioctl->flags & KFD_IOC_FLAG_PERFMON)) { + if (!capable(CAP_PERFMON) && !capable(CAP_SYS_ADMIN)) { + retcode = -EACCES; + goto err_i1; + } + } + if (cmd & (IOC_IN | IOC_OUT)) { if (asize <= sizeof(stack_kdata)) { kdata = stack_kdata; @@ -3397,16 +3942,19 @@ static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process, } -static int kfd_mmap(struct file *filp, struct vm_area_struct *vma) +static int kfd_mmap(struct file *filep, struct vm_area_struct *vma) { struct kfd_process *process; struct kfd_node *dev = NULL; unsigned long mmap_offset; unsigned int gpu_id; - process = kfd_get_process(current); - if (IS_ERR(process)) - return PTR_ERR(process); + process = filep->private_data; + if (!process) + return -ESRCH; + + if (process->lead_thread != current->group_leader) + return -EBADF; mmap_offset = vma->vm_pgoff << PAGE_SHIFT; gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 4a7180b46b719..702a08745f13f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1705,6 +1705,7 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): /* Cacheline size not available in IP discovery for gc11. * kfd_fill_gpu_cache_info_from_gfx_config to hard code it */ @@ -1712,6 +1713,7 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc fallthrough; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): + case IP_VERSION(12, 1, 0): num_of_cache_types = kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd, cache_line_size_missing, @@ -1873,8 +1875,6 @@ static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size, static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) { struct crat_header *crat_table = (struct crat_header *)pcrat_image; - struct acpi_table_header *acpi_table; - acpi_status status; struct crat_subtype_generic *sub_type_hdr; int avail_size = *size; int numa_node_id; @@ -1882,6 +1882,10 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) uint32_t entries = 0; #endif int ret = 0; +#ifdef CONFIG_ACPI + struct acpi_table_header *acpi_table; + acpi_status status; +#endif if (!pcrat_image) return -EINVAL; @@ -1898,6 +1902,7 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) sizeof(crat_table->signature)); crat_table->length = sizeof(struct crat_header); +#ifdef CONFIG_ACPI status = acpi_get_table("DSDT", 0, &acpi_table); if (status != AE_OK) pr_warn("DSDT table not found for OEM information\n"); @@ -1909,6 +1914,11 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) CRAT_OEMTABLEID_LENGTH); acpi_put_table(acpi_table); } +#else + crat_table->oem_revision = 0; + memcpy(crat_table->oem_id, "INV", CRAT_OEMID_LENGTH); + memcpy(crat_table->oem_table_id, "UNAVAIL", CRAT_OEMTABLEID_LENGTH); +#endif crat_table->total_entries = 0; crat_table->num_domains = 0; @@ -2060,6 +2070,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) if (pxm > max_pxm) max_pxm = pxm; break; +#ifdef HAVE_ACPI_SRAT_GENERIC_AFFINITY case ACPI_SRAT_TYPE_GENERIC_AFFINITY: gpu = (struct acpi_srat_generic_affinity *)sub_header; bdf = *((u16 *)(&gpu->device_handle[0])) << 16 | @@ -2069,6 +2080,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) numa_node = pxm_to_node(gpu->proximity_domain); } break; +#endif default: break; } @@ -2357,7 +2369,7 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image, if (kdev->kfd->hive_id) { for (nid = 0; nid < proximity_domain; ++nid) { peer_dev = kfd_topology_device_by_proximity_domain_no_lock(nid); - if (!peer_dev->gpu) + if (!peer_dev || !peer_dev->gpu) continue; if (peer_dev->gpu->kfd->hive_id != kdev->kfd->hive_id) continue; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index ba99e0f258aee..fe778b210673f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -357,12 +357,13 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en) return 0; if (!pdd->proc_ctx_cpu_ptr) { - r = amdgpu_amdkfd_alloc_gtt_mem(adev, + r = amdgpu_amdkfd_alloc_kernel_mem(adev, AMDGPU_MES_PROC_CTX_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (r) { dev_err(adev->dev, "failed to allocate process context bo\n"); @@ -371,8 +372,10 @@ int kfd_dbg_set_mes_debug_mode(struct kfd_process_device *pdd, bool sq_trap_en) memset(pdd->proc_ctx_cpu_ptr, 0, AMDGPU_MES_PROC_CTX_SIZE); } - return amdgpu_mes_set_shader_debugger(pdd->dev->adev, pdd->proc_ctx_gpu_addr, spi_dbg_cntl, - pdd->watch_points, flags, sq_trap_en); + return amdgpu_mes_set_shader_debugger(pdd->dev->adev, + pdd->proc_ctx_gpu_addr, spi_dbg_cntl, + pdd->watch_points, flags, sq_trap_en, + ffs(pdd->dev->xcc_mask) - 1); } #define KFD_DEBUGGER_INVALID_WATCH_POINT_ID -1 @@ -401,27 +404,25 @@ static int kfd_dbg_get_dev_watch_id(struct kfd_process_device *pdd, int *watch_i return -ENOMEM; } -static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, int watch_id) +static void kfd_dbg_clear_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id) { spin_lock(&pdd->dev->watch_points_lock); /* process owns device watch point so safe to clear */ - if ((pdd->alloc_watch_ids >> watch_id) & 0x1) { - pdd->alloc_watch_ids &= ~(0x1 << watch_id); - pdd->dev->alloc_watch_ids &= ~(0x1 << watch_id); + if (pdd->alloc_watch_ids & BIT(watch_id)) { + pdd->alloc_watch_ids &= ~BIT(watch_id); + pdd->dev->alloc_watch_ids &= ~BIT(watch_id); } spin_unlock(&pdd->dev->watch_points_lock); } -static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, int watch_id) +static bool kfd_dbg_owns_dev_watch_id(struct kfd_process_device *pdd, u32 watch_id) { bool owns_watch_id = false; spin_lock(&pdd->dev->watch_points_lock); - owns_watch_id = watch_id < MAX_WATCH_ADDRESSES && - ((pdd->alloc_watch_ids >> watch_id) & 0x1); - + owns_watch_id = pdd->alloc_watch_ids & BIT(watch_id); spin_unlock(&pdd->dev->watch_points_lock); return owns_watch_id; @@ -432,6 +433,9 @@ int kfd_dbg_trap_clear_dev_address_watch(struct kfd_process_device *pdd, { int r; + if (watch_id >= MAX_WATCH_ADDRESSES) + return -EINVAL; + if (!kfd_dbg_owns_dev_watch_id(pdd, watch_id)) return -EINVAL; @@ -469,6 +473,9 @@ int kfd_dbg_trap_set_dev_address_watch(struct kfd_process_device *pdd, if (r) return r; + if (*watch_id >= MAX_WATCH_ADDRESSES) + return -EINVAL; + if (!pdd->dev->kfd->shared_resources.enable_mes) { r = debug_lock_and_unmap(pdd->dev->dqm); if (r) { @@ -516,9 +523,15 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags) int i, r = 0, rewind_count = 0; for (i = 0; i < target->n_pdds; i++) { + uint32_t caps; + uint32_t caps2; struct kfd_topology_device *topo_dev = - kfd_topology_device_by_id(target->pdds[i]->dev->id); - uint32_t caps = topo_dev->node_props.capability; + kfd_topology_device_by_id(target->pdds[i]->dev->id); + if (!topo_dev) + return -EINVAL; + + caps = topo_dev->node_props.capability; + caps2 = topo_dev->node_props.capability2; if (!(caps & HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED) && (*flags & KFD_DBG_TRAP_FLAG_SINGLE_MEM_OP)) { @@ -531,6 +544,12 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags) *flags = prev_flags; return -EACCES; } + + if (!(caps2 & HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED) && + (*flags & KFD_DBG_TRAP_FLAG_LDS_OUT_OF_ADDR_RANGE)) { + *flags = prev_flags; + return -EACCES; + } } target->dbg_flags = *flags; @@ -565,9 +584,9 @@ int kfd_dbg_trap_set_flags(struct kfd_process *target, uint32_t *flags) continue; if (!pdd->dev->kfd->shared_resources.enable_mes) - debug_refresh_runlist(pdd->dev->dqm); + (void)debug_refresh_runlist(pdd->dev->dqm); else - kfd_dbg_set_mes_debug_mode(pdd, true); + (void)kfd_dbg_set_mes_debug_mode(pdd, true); } } @@ -627,9 +646,10 @@ void kfd_dbg_trap_deactivate(struct kfd_process *target, bool unwind, int unwind pr_err("Failed to release debug vmid on [%i]\n", pdd->dev->id); if (!pdd->dev->kfd->shared_resources.enable_mes) - debug_refresh_runlist(pdd->dev->dqm); + (void)debug_refresh_runlist(pdd->dev->dqm); else - kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev)); + (void)kfd_dbg_set_mes_debug_mode(pdd, + !kfd_dbg_has_cwsr_workaround(pdd->dev)); } kfd_dbg_set_workaround(target, false); @@ -1071,6 +1091,10 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, for (i = 0; i < tmp_num_devices; i++) { struct kfd_process_device *pdd = target->pdds[i]; struct kfd_topology_device *topo_dev = kfd_topology_device_by_id(pdd->dev->id); + if (!topo_dev) { + r = -EINVAL; + break; + } device_info.gpu_id = pdd->dev->id; device_info.exception_status = pdd->exception_status; @@ -1098,6 +1122,7 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, device_info.num_xcc = NUM_XCC(pdd->dev->xcc_mask); device_info.capability = topo_dev->node_props.capability; device_info.debug_prop = topo_dev->node_props.debug_prop; + device_info.capability2 = topo_dev->node_props.capability2; if (exception_clear_mask) pdd->exception_status &= ~exception_clear_mask; @@ -1150,3 +1175,29 @@ void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, mutex_unlock(&target->event_mutex); } + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p) +{ + int i; + + if (p->runtime_info.ttmp_setup) + return; + + p->runtime_info.ttmp_setup = true; + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + + if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { + amdgpu_gfx_off_ctrl(pdd->dev->adev, false); + pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + true, + pdd->dev->vm_info.last_vmid_kfd); + } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { + pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + false, + 0); + } + } +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h index fbb751821c692..f8996f5431329 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h @@ -92,6 +92,9 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, uint64_t exception_set_mask); + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p); + /* * If GFX off is enabled, chips that do not support RLC restore for the debug * registers will disable GFX off temporarily for the entire debug session. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e9cfb80bd4366..70017594a08e6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_vi.h" @@ -57,6 +58,7 @@ extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; +extern const struct kfd2kgd_calls gfx_v12_1_kfd2kgd; static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, unsigned int chunk_size); @@ -94,6 +96,8 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ + kfd->device_info.num_sdma_queues_per_engine = 8; + break; case IP_VERSION(6, 0, 0): case IP_VERSION(6, 0, 1): case IP_VERSION(6, 0, 2): @@ -102,9 +106,13 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) case IP_VERSION(6, 1, 1): case IP_VERSION(6, 1, 2): case IP_VERSION(6, 1, 3): + case IP_VERSION(6, 1, 4): case IP_VERSION(7, 0, 0): case IP_VERSION(7, 0, 1): + case IP_VERSION(7, 1, 0): kfd->device_info.num_sdma_queues_per_engine = 8; + /* Reserve 1 for paging and 1 for gfx */ + kfd->device_info.num_reserved_sdma_queues_per_engine = 2; break; default: dev_warn(kfd_device, @@ -112,30 +120,6 @@ static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) sdma_version); kfd->device_info.num_sdma_queues_per_engine = 8; } - - bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); - - switch (sdma_version) { - case IP_VERSION(6, 0, 0): - case IP_VERSION(6, 0, 1): - case IP_VERSION(6, 0, 2): - case IP_VERSION(6, 0, 3): - case IP_VERSION(6, 1, 0): - case IP_VERSION(6, 1, 1): - case IP_VERSION(6, 1, 2): - case IP_VERSION(6, 1, 3): - case IP_VERSION(7, 0, 0): - case IP_VERSION(7, 0, 1): - /* Reserve 1 for paging and 1 for gfx */ - kfd->device_info.num_reserved_sdma_queues_per_engine = 2; - /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */ - bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0, - kfd->adev->sdma.num_instances * - kfd->device_info.num_reserved_sdma_queues_per_engine); - break; - default: - break; - } } static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) @@ -183,6 +167,7 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) case IP_VERSION(11, 5, 1): case IP_VERSION(11, 5, 2): case IP_VERSION(11, 5, 3): + case IP_VERSION(11, 5, 4): kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; break; case IP_VERSION(12, 0, 0): @@ -190,6 +175,10 @@ static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) /* GFX12_TODO: Change to v12 version. */ kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; break; + case IP_VERSION(12, 1, 0): + kfd->device_info.event_interrupt_class = + &event_interrupt_class_v12_1; + break; default: dev_warn(kfd_device, "v9 event interrupt handler is set due to " "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); @@ -456,6 +445,10 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) gfx_target_version = 110503; f2g = &gfx_v11_kfd2kgd; break; + case IP_VERSION(11, 5, 4): + gfx_target_version = 110504; + f2g = &gfx_v11_kfd2kgd; + break; case IP_VERSION(12, 0, 0): gfx_target_version = 120000; f2g = &gfx_v12_kfd2kgd; @@ -464,6 +457,10 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) gfx_target_version = 120001; f2g = &gfx_v12_kfd2kgd; break; + case IP_VERSION(12, 1, 0): + gfx_target_version = 120500; + f2g = &gfx_v12_1_kfd2kgd; + break; default: break; } @@ -549,11 +546,16 @@ static void kfd_cwsr_init(struct kfd_dev *kfd) BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); kfd->cwsr_isa = cwsr_trap_gfx11_hex; kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); - } else { + } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 1, 0)) { BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) > KFD_CWSR_TMA_OFFSET); kfd->cwsr_isa = cwsr_trap_gfx12_hex; kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); + } else { + BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_1_0_hex) + > KFD_CWSR_TMA_OFFSET); + kfd->cwsr_isa = cwsr_trap_gfx12_1_0_hex; + kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_1_0_hex); } kfd->cwsr_enabled = true; @@ -603,6 +605,18 @@ static void kfd_smi_init(struct kfd_node *dev) spin_lock_init(&dev->smi_lock); } +static void kfd_pc_sampling_init(struct kfd_node *dev) +{ + mutex_init(&dev->pcs_data.mutex); + idr_init_base(&dev->pcs_data.sampling_idr, 1); +} + +static void kfd_pc_sampling_exit(struct kfd_node *dev) +{ + idr_destroy(&dev->pcs_data.sampling_idr); + mutex_destroy(&dev->pcs_data.mutex); +} + static int kfd_init_node(struct kfd_node *node) { int err = -1; @@ -633,6 +647,7 @@ static int kfd_init_node(struct kfd_node *node) } kfd_smi_init(node); + kfd_pc_sampling_init(node); return 0; @@ -671,6 +686,7 @@ static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) kfd_topology_remove_device(knode); if (knode->gws) amdgpu_amdkfd_free_gws(knode->adev, knode->gws); + kfd_pc_sampling_exit(knode); kfree(knode); kfd->nodes[i] = NULL; } @@ -682,6 +698,7 @@ static void kfd_setup_interrupt_bitmap(struct kfd_node *node, struct amdgpu_device *adev = node->adev; uint32_t xcc_mask = node->xcc_mask; uint32_t xcc, mapped_xcc; + uint32_t bitmap; /* * Interrupt bitmap is setup for processing interrupts from * different XCDs and AIDs. @@ -703,9 +720,22 @@ static void kfd_setup_interrupt_bitmap(struct kfd_node *node, * - AND VMID reported in the interrupt lies within the * VMID range of the node. */ - for_each_inst(xcc, xcc_mask) { - mapped_xcc = GET_INST(GC, xcc); - node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); + switch (KFD_GC_VERSION(node)) { + case IP_VERSION(12, 1, 0): + for_each_inst(xcc, xcc_mask) { + mapped_xcc = GET_INST(GC, xcc); + bitmap = 0x2 | (0x4 << (mapped_xcc % 4)); + if (mapped_xcc/4) + bitmap = bitmap << 8; + node->interrupt_bitmap |= bitmap; + } + break; + default: + for_each_inst(xcc, xcc_mask) { + mapped_xcc = GET_INST(GC, xcc); + node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); + } + break; } dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, node->interrupt_bitmap); @@ -768,7 +798,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, * If the VMID range changes for multi-partition capable GPUs, then * this code MUST be revisited. */ - if (kfd->adev->xcp_mgr) { + if (kfd->adev->xcp_mgr && (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, AMDGPU_XCP_FL_LOCKED); if (partition_mode == AMDGPU_CPX_PARTITION_MODE && @@ -805,12 +835,13 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, /* add another 512KB for all other allocations on gart (HPD, fences) */ size += 512 * 1024; - if (amdgpu_amdkfd_alloc_gtt_mem( - kfd->adev, size, &kfd->gtt_mem, + if (amdgpu_amdkfd_alloc_kernel_mem( + kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT, + &kfd->gtt_mem, &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, - false)) { + false, true)) { dev_err(kfd_device, "Could not allocate %d bytes\n", size); - goto alloc_gtt_mem_failure; + goto alloc_kernel_mem_failure; } dev_info(kfd_device, "Allocated %d bytes on gart\n", size); @@ -846,6 +877,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", kfd->num_nodes); + kfd->profiler_process = NULL; + mutex_init(&kfd->profiler_lock); /* Allocate the KFD nodes */ for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); @@ -875,7 +908,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, } if (partition_mode == AMDGPU_CPX_PARTITION_MODE && - kfd->num_nodes != 1) { + kfd->num_nodes != 1 && + (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { /* For multi-partition capable GPUs and CPX mode, first * XCD gets VMID range 4-9 and second XCD gets VMID * range 10-15. @@ -896,6 +930,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, node->compute_vmid_bitmap = gpu_resources->compute_vmid_bitmap; } + node->max_proc_per_quantum = max_proc_per_quantum; atomic_set(&node->sram_ecc_flag, 0); @@ -918,6 +953,8 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, svm_range_set_max_pages(kfd->adev); + kfd_ais_init(kfd->adev); + kfd->init_complete = true; dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -931,11 +968,12 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, node_alloc_error: kfd_cleanup_nodes(kfd, i); kfd_doorbell_fini(kfd); + mutex_destroy(&kfd->profiler_lock); kfd_doorbell_error: kfd_gtt_sa_fini(kfd); kfd_gtt_sa_init_error: - amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); -alloc_gtt_mem_failure: + amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); +alloc_kernel_mem_failure: dev_err(kfd_device, "device %x:%x NOT added due to errors\n", kfd->adev->pdev->vendor, kfd->adev->pdev->device); @@ -946,16 +984,21 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, void kgd2kfd_device_exit(struct kfd_dev *kfd) { if (kfd->init_complete) { + kfd_ais_deinit(kfd->adev); /* Cleanup KFD nodes */ kfd_cleanup_nodes(kfd, kfd->num_nodes); /* Cleanup common/shared resources */ kfd_doorbell_fini(kfd); ida_destroy(&kfd->doorbell_ida); kfd_gtt_sa_fini(kfd); - amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem); + amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); + mutex_destroy(&kfd->profiler_lock); } kfree(kfd); + + /* after remove a kfd device unlock kfd driver */ + kgd2kfd_unlock_kfd(NULL); } int kgd2kfd_pre_reset(struct kfd_dev *kfd, @@ -972,7 +1015,7 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd, kfd_smi_event_update_gpu_reset(node, false, reset_context); } - kgd2kfd_suspend(kfd, true); + kgd2kfd_suspend(kfd, true, true); for (i = 0; i < kfd->num_nodes; i++) kfd_signal_reset_event(kfd->nodes[i]); @@ -1040,7 +1083,7 @@ bool kfd_is_locked(struct kfd_dev *kfd) return false; } -void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) +void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc, bool force) { struct kfd_node *node; int i; @@ -1049,7 +1092,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) return; if (suspend_proc) - kgd2kfd_suspend_process(kfd); + kgd2kfd_suspend_process(kfd, force); for (i = 0; i < kfd->num_nodes; i++) { node = kfd->nodes[i]; @@ -1059,7 +1102,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) { - int ret, i; + int ret = 0, i; if (!kfd->init_complete) return 0; @@ -1076,7 +1119,7 @@ int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) return ret; } -void kgd2kfd_suspend_process(struct kfd_dev *kfd) +void kgd2kfd_suspend_process(struct kfd_dev *kfd, bool force) { if (!kfd->init_complete) return; @@ -1084,7 +1127,7 @@ void kgd2kfd_suspend_process(struct kfd_dev *kfd) mutex_lock(&kfd_processes_mutex); /* For first KFD device suspend all the KFD processes */ if (++kfd_locked == 1) - kfd_suspend_all_processes(); + kfd_suspend_all_processes(force); mutex_unlock(&kfd_processes_mutex); } @@ -1173,7 +1216,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) return -ESRCH; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); - r = kfd_process_evict_queues(p, trigger); + r = kfd_process_evict_queues(p, true, trigger); kfd_unref_process(p); return r; @@ -1202,12 +1245,13 @@ int kgd2kfd_resume_mm(struct mm_struct *mm) * prepare for safe eviction of KFD BOs that belong to the specified * process. * - * @mm: mm_struct that identifies the specified KFD process + * @mm: mm_struct that identifies a group of KFD processes + * @context_id: an id that identifies a specific KFD context in the above kfd process group * @fence: eviction fence attached to KFD process BOs * */ int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, - struct dma_fence *fence) + u16 context_id, struct dma_fence *fence) { struct kfd_process *p; unsigned long active_time; @@ -1219,7 +1263,7 @@ int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, if (dma_fence_is_signaled(fence)) return 0; - p = kfd_lookup_process_by_mm(mm); + p = kfd_lookup_process_by_id(mm, context_id); if (!p) return -ENODEV; @@ -1539,10 +1583,14 @@ int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) return r; } +/* unlock a kfd dev or kfd driver */ void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) { mutex_lock(&kfd_processes_mutex); - --kfd->kfd_dev_lock; + if (kfd) + --kfd->kfd_dev_lock; + else + --kfd_locked; mutex_unlock(&kfd_processes_mutex); } @@ -1681,6 +1729,10 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr { struct kfd_process *p; u32 cam_index; + u32 src_data_idx; + + src_data_idx = (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) ? + 3 : 2; if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { p = kfd_lookup_process_by_pasid(entry->pasid, NULL); @@ -1689,7 +1741,8 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr if (p->gpu_page_fault && !p->debug_trap_enabled) { if (retry_fault && adev->irq.retry_cam_enabled) { - cam_index = entry->src_data[2] & 0x3ff; + cam_index = entry->src_data[src_data_idx] & 0x3ff; + WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); } @@ -1706,6 +1759,73 @@ bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entr return false; } +/* check if there is kfd process still uses adev */ +static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) +{ + struct kfd_process *p; + struct hlist_node *p_temp; + unsigned int temp; + struct kfd_node *dev; + + mutex_lock(&kfd_processes_mutex); + + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return true; + } + + /* check if there is device still use adev */ + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { + for (int i = 0; i < p->n_pdds; i++) { + dev = p->pdds[i]->dev; + if (dev->adev == adev) { + mutex_unlock(&kfd_processes_mutex); + return false; + } + } + } + + mutex_unlock(&kfd_processes_mutex); + + return true; +} + +/** kgd2kfd_teardown_processes - gracefully tear down existing + * kfd processes that use adev + * + * @adev: amdgpu_device where kfd processes run on and will be + * teardown + * + */ +void kgd2kfd_teardown_processes(struct amdgpu_device *adev) +{ + struct hlist_node *p_temp; + struct kfd_process *p; + struct kfd_node *dev; + unsigned int temp; + + mutex_lock(&kfd_processes_mutex); + + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return; + } + + hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { + for (int i = 0; i < p->n_pdds; i++) { + dev = p->pdds[i]->dev; + if (dev->adev == adev) + kfd_signal_process_terminate_event(p); + } + } + + mutex_unlock(&kfd_processes_mutex); + + /* wait all kfd processes use adev terminate */ + while (!kgd2kfd_check_device_idle(adev)) + cond_resched(); +} + #if defined(CONFIG_DEBUG_FS) /* This function will send a package to HIQ to hang the HWS diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 625ea8ab7a749..afcd2ac980fa1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -137,9 +138,10 @@ static void init_sdma_bitmaps(struct device_queue_manager *dqm) bitmap_set(dqm->xgmi_sdma_bitmap, 0, get_num_xgmi_sdma_queues(dqm)); /* Mask out the reserved queues */ - bitmap_andnot(dqm->sdma_bitmap, dqm->sdma_bitmap, - dqm->dev->kfd->device_info.reserved_sdma_queues_bitmap, - KFD_MAX_SDMA_QUEUES); + bitmap_clear(dqm->sdma_bitmap, 0, kfd_get_num_sdma_engines(dqm->dev) * + dqm->dev->kfd->device_info.num_reserved_sdma_queues_per_engine); + bitmap_clear(dqm->xgmi_sdma_bitmap, 0, kfd_get_num_xgmi_sdma_engines(dqm->dev) * + dqm->dev->kfd->device_info.num_reserved_sdma_queues_per_engine); } void program_sh_mem_settings(struct device_queue_manager *dqm, @@ -155,6 +157,31 @@ void program_sh_mem_settings(struct device_queue_manager *dqm, qpd->sh_mem_bases, xcc_id); } +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + bool busy = false; + struct queue *q; + + dqm_lock(dqm); + list_for_each_entry(q, &qpd->queues_list, list) { + struct mqd_manager *mqd_mgr; + enum KFD_MQD_TYPE type; + + type = get_mqd_type_from_queue_type(q->properties.type); + mqd_mgr = dqm->mqd_mgrs[type]; + if (!mqd_mgr || !mqd_mgr->check_queue_active) + continue; + + busy = mqd_mgr->check_queue_active(q); + if (busy) + break; + } + dqm_unlock(dqm); + + return busy; +} + static void kfd_hws_hang(struct device_queue_manager *dqm) { struct device_process_node *cur; @@ -254,6 +281,9 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, queue_input.queue_type = (uint32_t)queue_type; queue_input.exclusively_scheduled = q->properties.is_gws; + queue_input.sh_mem_config_data = qpd->sh_mem_config; + queue_input.vm_cntx_cntl = qpd->vm_cntx_cntl; + queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; amdgpu_mes_lock(&adev->mes); r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); @@ -284,6 +314,7 @@ static int remove_queue_mes(struct device_queue_manager *dqm, struct queue *q, memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input)); queue_input.doorbell_offset = q->properties.doorbell_off; queue_input.gang_context_addr = q->gang_ctx_gpu_addr; + queue_input.xcc_id = ffs(dqm->dev->xcc_mask) - 1; amdgpu_mes_lock(&adev->mes); r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input); @@ -399,8 +430,7 @@ static void increment_queue_count(struct device_queue_manager *dqm, struct queue *q) { dqm->active_queue_count++; - if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || - q->properties.type == KFD_QUEUE_TYPE_DIQ) + if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) dqm->active_cp_queue_count++; if (q->properties.is_gws) { @@ -414,8 +444,7 @@ static void decrement_queue_count(struct device_queue_manager *dqm, struct queue *q) { dqm->active_queue_count--; - if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || - q->properties.type == KFD_QUEUE_TYPE_DIQ) + if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) dqm->active_cp_queue_count--; if (q->properties.is_gws) { @@ -673,7 +702,7 @@ static int create_queue_nocpsch(struct device_queue_manager *dqm, /* Temporarily release dqm lock to avoid a circular lock dependency */ dqm_unlock(dqm); - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); dqm_lock(dqm); if (!q->mqd_mem_obj) { @@ -856,8 +885,7 @@ static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm, int retval; struct mqd_manager *mqd_mgr; - mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( - q->properties.type)]; + mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type(q->properties.type)]; if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) deallocate_hqd(dqm, q); @@ -940,7 +968,7 @@ static int destroy_queue_nocpsch(struct device_queue_manager *dqm, return retval; } -static int update_queue(struct device_queue_manager *dqm, struct queue *q, +static int update_queue_locked(struct device_queue_manager *dqm, struct queue *q, struct mqd_update_info *minfo) { int retval = 0; @@ -949,11 +977,9 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, struct kfd_process_device *pdd; bool prev_active = false; - dqm_lock(dqm); pdd = kfd_get_process_device_data(q->device, q->process); if (!pdd) { - retval = -ENODEV; - goto out_unlock; + return -ENODEV; } mqd_mgr = dqm->mqd_mgrs[get_mqd_type_from_queue_type( q->properties.type)]; @@ -971,13 +997,12 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, /* queue is reset so inaccessable */ if (pdd->has_reset_queue) { - retval = -EACCES; - goto out_unlock; + return -EACCES; } if (retval) { dev_err(dev, "unmap queue failed\n"); - goto out_unlock; + return retval; } } else if (prev_active && (q->properties.type == KFD_QUEUE_TYPE_COMPUTE || @@ -986,7 +1011,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, if (!dqm->sched_running) { WARN_ONCE(1, "Update non-HWS queue while stopped\n"); - goto out_unlock; + return retval; } retval = mqd_mgr->destroy_mqd(mqd_mgr, q->mqd, @@ -996,7 +1021,7 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, KFD_UNMAP_LATENCY_MS, q->pipe, q->queue); if (retval) { dev_err(dev, "destroy mqd failed\n"); - goto out_unlock; + return retval; } } @@ -1044,11 +1069,43 @@ static int update_queue(struct device_queue_manager *dqm, struct queue *q, &q->properties, current->mm); } -out_unlock: - dqm_unlock(dqm); return retval; } +static int update_queue(struct device_queue_manager *dqm, struct queue *q, + struct mqd_update_info *minfo) +{ + int retval; + + dqm_lock(dqm); + retval = update_queue_locked(dqm, q, minfo); + dqm_unlock(dqm); + + return retval; +} + +static void set_perfcount(struct device_queue_manager *dqm, int enable) +{ + struct device_process_node *cur; + struct qcm_process_device *qpd; + struct queue *q; + struct mqd_update_info minfo = { 0 }; + + if (!dqm) + return; + + minfo.update_flag = (enable == 1 ? UPDATE_FLAG_PERFCOUNT_ENABLE : + UPDATE_FLAG_PERFCOUNT_DISABLE); + dqm_lock(dqm); + list_for_each_entry(cur, &dqm->queues, list) { + qpd = cur->qpd; + list_for_each_entry(q, &qpd->queues_list, list) { + update_queue_locked(dqm, q, &minfo); + } + } + dqm_unlock(dqm); +} + /* suspend_single_queue does not lock the dqm like the * evict_process_queues_cpsch or evict_process_queues_nocpsch. You should * lock the dqm before calling, and unlock after calling. @@ -1433,13 +1490,12 @@ static int register_process(struct device_queue_manager *dqm, static int unregister_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { - int retval; + int retval = 0; struct device_process_node *cur, *next; pr_debug("qpd->queues_list is %s\n", list_empty(&qpd->queues_list) ? "empty" : "not empty"); - retval = 0; dqm_lock(dqm); list_for_each_entry_safe(cur, next, &dqm->queues, list) { @@ -1469,7 +1525,7 @@ set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, unsigned int vmid) { uint32_t xcc_mask = dqm->dev->xcc_mask; - int xcc_id, ret; + int xcc_id, ret = 0; for_each_inst(xcc_id, xcc_mask) { ret = dqm->dev->kfd2kgd->set_pasid_vmid_mapping( @@ -1821,8 +1877,6 @@ static int start_cpsch(struct device_queue_manager *dqm) struct device *dev = dqm->dev->adev->dev; int retval, num_hw_queue_slots; - retval = 0; - dqm_lock(dqm); if (!dqm->dev->kfd->shared_resources.enable_mes) { @@ -2003,7 +2057,7 @@ static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q, dqm->asic_ops.init_sdma_vm(dqm, q, qpd); q->properties.tba_addr = qpd->tba_addr; q->properties.tma_addr = qpd->tma_addr; - q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr->dev, &q->properties); + q->mqd_mem_obj = mqd_mgr->allocate_mqd(mqd_mgr, &q->properties); if (!q->mqd_mem_obj) { retval = -ENOMEM; goto out_deallocate_doorbell; @@ -2395,7 +2449,6 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, if (retval) goto out; } - retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); if (retval) goto out; @@ -2721,7 +2774,7 @@ static int get_wave_state(struct device_queue_manager *dqm, ctl_stack, ctl_stack_used_size, save_area_used_size); } -static void get_queue_checkpoint_info(struct device_queue_manager *dqm, +static int get_queue_checkpoint_info(struct device_queue_manager *dqm, const struct queue *q, u32 *mqd_size, u32 *ctl_stack_size) @@ -2729,6 +2782,7 @@ static void get_queue_checkpoint_info(struct device_queue_manager *dqm, struct mqd_manager *mqd_mgr; enum KFD_MQD_TYPE mqd_type = get_mqd_type_from_queue_type(q->properties.type); + int ret = 0; dqm_lock(dqm); mqd_mgr = dqm->mqd_mgrs[mqd_type]; @@ -2736,9 +2790,11 @@ static void get_queue_checkpoint_info(struct device_queue_manager *dqm, *ctl_stack_size = 0; if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE && mqd_mgr->get_checkpoint_info) - mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); + ret = mqd_mgr->get_checkpoint_info(mqd_mgr, q->mqd, ctl_stack_size); dqm_unlock(dqm); + + return ret; } static int checkpoint_mqd(struct device_queue_manager *dqm, @@ -2774,7 +2830,7 @@ static int checkpoint_mqd(struct device_queue_manager *dqm, static int process_termination_cpsch(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { - int retval; + int retval = 0; struct queue *q; struct device *dev = dqm->dev->adev->dev; struct kernel_queue *kq, *kq_next; @@ -2784,8 +2840,6 @@ static int process_termination_cpsch(struct device_queue_manager *dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES; bool found = false; - retval = 0; - dqm_lock(dqm); /* Clean all kernel queues */ @@ -2902,9 +2956,10 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) (dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * NUM_XCC(dqm->dev->xcc_mask)); - retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, - &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), - (void *)&(mem_obj->cpu_ptr), false); + retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, size, + AMDGPU_GEM_DOMAIN_GTT, + &(mem_obj->mem), &(mem_obj->gpu_addr), + (void *)&(mem_obj->cpu_ptr), false, true); return retval; } @@ -2914,7 +2969,7 @@ static void deallocate_hiq_sdma_mqd(struct kfd_node *dev, { WARN(!mqd, "No hiq sdma mqd trunk to free"); - amdgpu_amdkfd_free_gtt_mem(dev->adev, &mqd->gtt_mem); + amdgpu_amdkfd_free_kernel_mem(dev->adev, &mqd->mem); } struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) @@ -2969,6 +3024,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.reset_queues = reset_queues_cpsch; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; case KFD_SCHED_POLICY_NO_HWS: /* initialize dqm for no cp scheduling */ @@ -2989,6 +3045,7 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.get_wave_state = get_wave_state; dqm->ops.get_queue_checkpoint_info = get_queue_checkpoint_info; dqm->ops.checkpoint_mqd = checkpoint_mqd; + dqm->ops.set_perfcount = set_perfcount; break; default: dev_err(dev->adev->dev, "Invalid scheduling policy %d\n", dqm->sched_policy); @@ -3012,7 +3069,9 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) break; default: - if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0)) + if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 1, 0)) + device_queue_manager_init_v12_1(&dqm->asic_ops); + else if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 0, 0)) device_queue_manager_init_v12(&dqm->asic_ops); else if (KFD_GC_VERSION(dev) >= IP_VERSION(11, 0, 0)) device_queue_manager_init_v11(&dqm->asic_ops); @@ -3457,7 +3516,6 @@ int suspend_queues(struct kfd_process *p, else per_device_suspended++; } else if (err != -EBUSY) { - r = err; queue_ids[q_idx] |= KFD_DBG_QUEUE_ERROR_MASK; break; } @@ -3614,6 +3672,16 @@ int debug_refresh_runlist(struct device_queue_manager *dqm) return debug_map_and_unlock(dqm); } +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param) +{ + dqm_lock(dqm); + if (!dqm->dev->kfd->shared_resources.enable_mes) + execute_queues_cpsch(dqm, filter, filter_param, USE_DEFAULT_GRACE_PERIOD); + dqm_unlock(dqm); +} + bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, int doorbell_off, u32 *queue_format) @@ -3638,6 +3706,7 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, dqm_unlock(dqm); return r; } + #if defined(CONFIG_DEBUG_FS) static void seq_reg_dump(struct seq_file *m, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 74a61b5b2f0b4..61fdd8c5ee6db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -192,7 +192,7 @@ struct device_queue_manager_ops { int (*reset_queues)(struct device_queue_manager *dqm, uint16_t pasid); - void (*get_queue_checkpoint_info)(struct device_queue_manager *dqm, + int (*get_queue_checkpoint_info)(struct device_queue_manager *dqm, const struct queue *q, u32 *mqd_size, u32 *ctl_stack_size); @@ -200,6 +200,8 @@ struct device_queue_manager_ops { const struct queue *q, void *mqd, void *ctl_stack); + void (*set_perfcount)(struct device_queue_manager *dqm, + int enable); }; struct device_queue_manager_asic_ops { @@ -299,6 +301,8 @@ void device_queue_manager_init_v11( struct device_queue_manager_asic_ops *asic_ops); void device_queue_manager_init_v12( struct device_queue_manager_asic_ops *asic_ops); +void device_queue_manager_init_v12_1( + struct device_queue_manager_asic_ops *asic_ops); void program_sh_mem_settings(struct device_queue_manager *dqm, struct qcm_process_device *qpd); unsigned int get_cp_queues_num(struct device_queue_manager *dqm); @@ -306,6 +310,8 @@ unsigned int get_queues_per_pipe(struct device_queue_manager *dqm); unsigned int get_pipes_per_mec(struct device_queue_manager *dqm); unsigned int get_num_sdma_queues(struct device_queue_manager *dqm); unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm); +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); int reserve_debug_trap_vmid(struct device_queue_manager *dqm, struct qcm_process_device *qpd); int release_debug_trap_vmid(struct device_queue_manager *dqm, @@ -328,6 +334,10 @@ bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, int doorbell_off, u32 *queue_format); +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param); + static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { return (pdd->lds_base >> 16) & 0xFF; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c new file mode 100644 index 0000000000000..9e70a5f8a50b0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "kfd_device_queue_manager.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "soc_v1_0_enum.h" + +static int update_qpd_v12_1(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); +static void init_sdma_vm_v12_1(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd); + +void device_queue_manager_init_v12_1( + struct device_queue_manager_asic_ops *asic_ops) +{ + asic_ops->update_qpd = update_qpd_v12_1; + asic_ops->init_sdma_vm = init_sdma_vm_v12_1; + asic_ops->mqd_manager_init = mqd_manager_init_v12_1; +} + +static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd) +{ + uint32_t shared_base = pdd->lds_base >> 48; + uint32_t private_base = pdd->scratch_base >> 58; + + return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) | + (private_base << SH_MEM_BASES__PRIVATE_BASE__SHIFT); +} + +static int update_qpd_v12_1(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + struct kfd_process_device *pdd; + struct amdgpu_device *adev = dqm->dev->adev; + struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; + + pdd = qpd_to_pdd(qpd); + qpd->vm_cntx_cntl = hub->vm_cntx_cntl; + + /* check if sh_mem_config register already configured */ + if (qpd->sh_mem_config == 0) { + qpd->sh_mem_config = + (SH_MEM_ALIGNMENT_MODE_UNALIGNED << + SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | + (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT); + + qpd->sh_mem_config |= + (1 << SH_MEM_CONFIG__F8_MODE__SHIFT); + qpd->sh_mem_ape1_limit = 0; + qpd->sh_mem_ape1_base = 0; + } + + if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) { + if (!pdd->process->xnack_enabled) { + qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; + qpd->vm_cntx_cntl &= + ~(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT); + } else { + qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT); + qpd->vm_cntx_cntl |= + (1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT); + } + } + + qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd); + + pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases); + + return 0; +} + +static void init_sdma_vm_v12_1(struct device_queue_manager *dqm, struct queue *q, + struct qcm_process_device *qpd) +{ + /* Not needed on SDMAv4 onwards any more */ + q->properties.sdma_vm_addr = 0; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 05c74887fd6fd..c171da2dba587 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -103,11 +103,127 @@ void kfd_doorbell_fini(struct kfd_dev *kfd) (void **)&kfd->doorbell_kernel_ptr); } +static void kfd_doorbell_open(struct vm_area_struct *vma) +{ + /* Don't track the parent's PDD in a child process. We do set + * VM_DONTCOPY, but that can be overridden from user mode. + */ + vma->vm_private_data = NULL; +} + +static void kfd_doorbell_close(struct vm_area_struct *vma) +{ + struct kfd_process_device *pdd = vma->vm_private_data; + + if (!pdd) + return; + + mutex_lock(&pdd->qpd.doorbell_lock); + pdd->qpd.doorbell_vma = NULL; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (pdd->qpd.doorbell_mapped == 0) + pdd->qpd.doorbell_mapped = -1; + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +#ifdef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; +#else +static int kfd_doorbell_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#endif + struct kfd_process_device *pdd = vma->vm_private_data; + + if (!pdd) + return VM_FAULT_SIGBUS; + + pr_debug("Process pid %d doorbell vm page fault\n", pdd->process->lead_thread->pid); + + kfd_process_remap_doorbells_locked(pdd->process); + + kfd_process_schedule_restore(pdd->process); + + return VM_FAULT_NOPAGE; +} + +static const struct vm_operations_struct kfd_doorbell_vm_ops = { + .open = kfd_doorbell_open, + .close = kfd_doorbell_close, + .fault = kfd_doorbell_vm_fault, +}; + +static void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + struct vm_area_struct *vma; + size_t size; + + vma = pdd->qpd.doorbell_vma; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (!vma) { + pdd->qpd.doorbell_mapped = -1; + return; + } + + pr_debug("Process pid %d unmapping doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); + + size = kfd_doorbell_process_slice(pdd->dev->kfd); + zap_vma_ptes(vma, vma->vm_start, size); + pdd->qpd.doorbell_mapped = 0; +} + +void kfd_doorbell_unmap(struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->qpd.doorbell_lock); + kfd_doorbell_unmap_locked(pdd); + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +int kfd_doorbell_remap(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + phys_addr_t address; + struct vm_area_struct *vma; + size_t size; + int ret = 0; + + mutex_lock(&pdd->qpd.doorbell_lock); + if (pdd->qpd.doorbell_mapped != 0) + goto out_unlock; + + /* Calculate physical address of doorbell */ + address = kfd_get_process_doorbells(pdd); + vma = pdd->qpd.doorbell_vma; + size = kfd_doorbell_process_slice(pdd->dev->kfd); + + pr_debug("Process pid %d remap doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); + + ret = vm_iomap_memory(vma, address, size); + if (ret) + pr_err("Process pid %d failed to remap doorbell 0x%lx\n", + process->lead_thread->pid, vma->vm_start); + +out_unlock: + pdd->qpd.doorbell_mapped = 1; + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; +} + int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma) { phys_addr_t address; struct kfd_process_device *pdd; + int ret; /* * For simplicitly we only allow mapping of the entire doorbell @@ -129,20 +245,47 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("Mapping doorbell page\n" + pr_debug("Process pid %d mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - (unsigned long long) vma->vm_start, address, vma->vm_flags, - kfd_doorbell_process_slice(dev->kfd)); + process->lead_thread->pid, (unsigned long long) vma->vm_start, + address, vma->vm_flags, kfd_doorbell_process_slice(dev->kfd)); + pdd = kfd_get_process_device_data(dev, process); + if (WARN_ON_ONCE(!pdd)) + return 0; - return io_remap_pfn_range(vma, + mutex_lock(&pdd->qpd.doorbell_lock); + + ret = io_remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT, kfd_doorbell_process_slice(dev->kfd), vma->vm_page_prot); + + if (!ret && keep_idle_process_evicted) { + vma->vm_ops = &kfd_doorbell_vm_ops; + vma->vm_private_data = pdd; + pdd->qpd.doorbell_vma = vma; + + /* If process is evicted before the first queue is created, + * process will be restored by the page fault when the + * doorbell is accessed the first time + */ + if (pdd->qpd.doorbell_mapped == -1) { + pr_debug("Process pid %d evicted, unmapping doorbell\n", + process->lead_thread->pid); + kfd_doorbell_unmap_locked(pdd); + } else { + pdd->qpd.doorbell_mapped = 1; + } + } + + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 5a190dd6be4e2..ee70eb4b63193 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -142,6 +142,7 @@ static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id) * @p: Pointer to struct kfd_process * @id: ID to look up * @bits: Number of valid bits in @id + * @signal_mailbox_updated: flag indicates if FW updates signal mailbox entry * * Finds the first signaled event with a matching partial ID. If no * matching signaled event is found, returns NULL. In that case the @@ -155,7 +156,8 @@ static struct kfd_event *lookup_event_by_id(struct kfd_process *p, uint32_t id) * driver. */ static struct kfd_event *lookup_signaled_event_by_partial_id( - struct kfd_process *p, uint32_t id, uint32_t bits) + struct kfd_process *p, uint32_t id, uint32_t bits, + bool signal_mailbox_updated) { struct kfd_event *ev; @@ -166,7 +168,8 @@ static struct kfd_event *lookup_signaled_event_by_partial_id( * and we only need a single lookup. */ if (bits > 31 || (1U << bits) >= KFD_SIGNAL_EVENT_LIMIT) { - if (page_slots(p->signal_page)[id] == UNSIGNALED_EVENT_SLOT) + if (signal_mailbox_updated && + page_slots(p->signal_page)[id] == UNSIGNALED_EVENT_SLOT) return NULL; return idr_find(&p->event_idr, id); @@ -331,6 +334,12 @@ static int kfd_event_page_set(struct kfd_process *p, void *kernel_address, if (p->signal_page) return -EBUSY; + if (size < KFD_SIGNAL_EVENT_LIMIT * 8) { + pr_err("Event page size %llu is too small, need at least %lu bytes\n", + size, (unsigned long)(KFD_SIGNAL_EVENT_LIMIT * 8)); + return -EINVAL; + } + page = kzalloc(sizeof(*page), GFP_KERNEL); if (!page) return -ENOMEM; @@ -718,7 +727,7 @@ static void set_event_from_interrupt(struct kfd_process *p, } void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, - uint32_t valid_id_bits) + uint32_t valid_id_bits, bool signal_mailbox_updated) { struct kfd_event *ev = NULL; @@ -736,7 +745,8 @@ void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, if (valid_id_bits) ev = lookup_signaled_event_by_partial_id(p, partial_id, - valid_id_bits); + valid_id_bits, + signal_mailbox_updated); if (ev) { set_event_from_interrupt(p, ev); } else if (p->signal_page) { @@ -1380,3 +1390,32 @@ void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid) kfd_unref_process(p); } + +/* signal KFD_EVENT_TYPE_SIGNAL events from process p + * send signal SIGBUS to correspondent user space process + */ +void kfd_signal_process_terminate_event(struct kfd_process *p) +{ + struct kfd_event *ev; + u32 id; + + rcu_read_lock(); + + /* iterate from id 1 for KFD_EVENT_TYPE_SIGNAL events */ + id = 1; + idr_for_each_entry_continue(&p->event_idr, ev, id) + if (ev->type == KFD_EVENT_TYPE_SIGNAL) { + spin_lock(&ev->lock); + set_event(ev); + spin_unlock(&ev->lock); + } + + /* Send SIGBUS to p->lead_thread */ + dev_notice(kfd_device, + "Sending SIGBUS to process %d", + p->lead_thread->pid); + + send_sig(SIGBUS, p->lead_thread, 0); + + rcu_read_unlock(); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.h b/drivers/gpu/drm/amd/amdkfd/kfd_events.h index 52ccfd397c2b3..1dc21c13833b7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.h @@ -85,6 +85,7 @@ struct kfd_event { #define KFD_EVENT_TYPE_MEMORY 8 extern void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, - uint32_t valid_id_bits); + uint32_t valid_id_bits, + bool signal_mailbox_updated); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c index 1d170dc50df33..04c5e26f01ed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c @@ -359,6 +359,25 @@ static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id) pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev); } +static void kfd_init_apertures_v12(struct kfd_process_device *pdd, uint8_t id) +{ + pdd->lds_base = pdd->dev->adev->gmc.shared_aperture_start; + pdd->lds_limit = pdd->dev->adev->gmc.shared_aperture_end; + + pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM; + pdd->gpuvm_limit = + pdd->dev->kfd->shared_resources.gpuvm_size - 1; + + pdd->scratch_base = pdd->dev->adev->gmc.private_aperture_start; + pdd->scratch_limit = pdd->dev->adev->gmc.private_aperture_end; + + /* + * Place TBA/TMA on opposite side of VM hole to prevent + * stray faults from triggering SVM on these pages. + */ + pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev); +} + int kfd_init_apertures(struct kfd_process *process) { uint8_t id = 0; @@ -406,9 +425,11 @@ int kfd_init_apertures(struct kfd_process *process) kfd_init_apertures_vi(pdd, id); break; default: - if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) + if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 1, 0)) { + kfd_init_apertures_v12(pdd, id); + } else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) { kfd_init_apertures_v9(pdd, id); - else { + } else { WARN(1, "Unexpected ASIC family %u", dev->adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c index 3e1ad89747979..19406ab92c5bb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c @@ -211,7 +211,7 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SE2SH || client_id == SOC15_IH_CLIENTID_SE3SH) { if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, true); else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { encoding = REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING); @@ -324,7 +324,7 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23); + kfd_signal_event_interrupt(pasid, context_id0 & 0x7fffff, 23, true); } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { kfd_set_dbg_ev_from_interrupt(dev, pasid, @@ -344,7 +344,7 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SDMA6 || client_id == SOC15_IH_CLIENTID_SDMA7) { if (source_id == SOC15_INTSRC_SDMA_TRAP) { - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); } } else if (client_id == SOC15_IH_CLIENTID_VMC || client_id == SOC15_IH_CLIENTID_VMC1 || diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c index 2788a52714d10..12d81abed7481 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c @@ -353,7 +353,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, /* CP */ if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, true); else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) { u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0); @@ -366,7 +366,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, /* SDMA */ else if (source_id == SOC21_INTSRC_SDMA_TRAP) - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); else if (source_id == SOC21_INTSRC_SDMA_ECC) { event_interrupt_poison_consumption_v11(dev, pasid, source_id); return; @@ -404,7 +404,7 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); + kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24, true); } } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c new file mode 100644 index 0000000000000..47947b94926ba --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v12_1.c @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "kfd_events.h" +#include "soc15_int.h" +#include "kfd_device_queue_manager.h" +#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" +#include "kfd_smi_events.h" +#include "kfd_debug.h" +#include "amdgpu_ras_mgr.h" + +/* + * GFX12.1 SQ Interrupts + * + * There are 3 encoding types of interrupts sourced from SQ sent as a 44-bit + * packet to the Interrupt Handler: + * Auto - Generated by the SQG (various cmd overflows, timestamps etc) + * Wave - Generated by S_SENDMSG through a shader program + * Error - HW generated errors (Illegal instructions, Memviols, EDC etc) + * + * The 44-bit packet is mapped as {context_id1[7:0],context_id0[31:0]} plus + * 4-bits for VMID (SOC15_VMID_FROM_IH_ENTRY) as such: + * + * - context_id1[7:6] + * Encoding type (0 = Auto, 1 = Wave, 2 = Error) + * + * - context_id0[26] + * PRIV bit indicates that Wave S_SEND or error occurred within trap + * + * - context_id0[24:0] + * 25-bit data with the following layout per encoding type: + * Auto - only context_id0[8:0] is used, which reports various interrupts + * generated by SQG. The rest is 0. + * Wave - user data sent from m0 via S_SENDMSG (context_id0[23:0]) + * Error - Error Type (context_id0[24:21]), Error Details (context_id0[20:0]) + * + * The other context_id bits show coordinates (SE/SH/CU/SIMD/WGP) for wave + * S_SENDMSG and Errors. These are 0 for Auto. + */ + +enum SQ_INTERRUPT_WORD_ENCODING { + SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, + SQ_INTERRUPT_WORD_ENCODING_INST, + SQ_INTERRUPT_WORD_ENCODING_ERROR, +}; + +enum SQ_INTERRUPT_ERROR_TYPE { + SQ_INTERRUPT_ERROR_TYPE_EDC_FUE = 0x0, + SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST, + SQ_INTERRUPT_ERROR_TYPE_MEMVIOL, + SQ_INTERRUPT_ERROR_TYPE_EDC_FED, +}; + +/* SQ_INTERRUPT_WORD_AUTO_CTXID */ +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE__SHIFT 0 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT__SHIFT 1 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF0_FULL__SHIFT 2 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF1_FULL__SHIFT 3 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR__SHIFT 8 +#define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING__SHIFT 6 + +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_MASK 0x00000001 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__WLT_MASK 0x00000002 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF0_FULL_MASK 0x00000004 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_BUF1_FULL_MASK 0x00000008 +#define SQ_INTERRUPT_WORD_AUTO_CTXID0__THREAD_TRACE_UTC_ERROR_MASK 0x00000100 +#define SQ_INTERRUPT_WORD_AUTO_CTXID1__ENCODING_MASK 0x000000c0 + +/* SQ_INTERRUPT_WORD_WAVE_CTXID */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA__SHIFT 0 +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SA_ID__SHIFT 25 +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV__SHIFT 26 +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID__SHIFT 27 +#define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID__SHIFT 0 +#define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID__SHIFT 2 +#define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING__SHIFT 6 + +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__DATA_MASK 0x00ffffff /* [23:0] */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__SA_ID_MASK 0x02000000 /* [25] */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__PRIV_MASK 0x04000000 /* [26] */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID0__WAVE_ID_MASK 0xf8000000 /* [31:27] */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID1__SIMD_ID_MASK 0x00000003 /* [33:32] */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID1__WGP_ID_MASK 0x0000003c /* [37:34] */ +#define SQ_INTERRUPT_WORD_WAVE_CTXID1__ENCODING_MASK 0x000000c0 /* [39:38] */ + +/* SQ_INTERRUPT_WORD_ERROR_CTXID */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL__SHIFT 0 +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__MEM_VIOL__SHIFT 19 +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE__SHIFT 21 +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__SA_ID__SHIFT 25 +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV__SHIFT 26 +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID__SHIFT 27 +#define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID__SHIFT 0 +#define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID__SHIFT 2 +#define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING__SHIFT 6 + +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__DETAIL_MASK 0x0007ffff /* [18:0] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__MEM_VIOL_MASK 0x00180000 /* [20:19] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__TYPE_MASK 0x01e00000 /* [24:21] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__SA_ID_MASK 0x02000000 /* [25] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__PRIV_MASK 0x04000000 /* [26] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID0__WAVE_ID_MASK 0xf8000000 /* [31:27] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID1__SIMD_ID_MASK 0x00000003 /* [33:32] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID1__WGP_ID_MASK 0x0000003c /* [37:34] */ +#define SQ_INTERRUPT_WORD_ERROR_CTXID1__ENCODING_MASK 0x000000c0 /* [39:38] */ + +/* + * The debugger will send user data(m0) with PRIV=1 to indicate it requires + * notification from the KFD with the following queue id (DOORBELL_ID) and + * trap code (TRAP_CODE). + */ +#define KFD_CTXID0_TRAP_CODE_SHIFT 10 +#define KFD_CTXID0_TRAP_CODE_MASK 0xfffc00 +#define KFD_CTXID0_CP_BAD_OP_ECODE_MASK 0x3ffffff +#define KFD_CTXID0_DOORBELL_ID_MASK 0x0003ff + +#define KFD_CTXID0_TRAP_CODE(ctxid0) (((ctxid0) & \ + KFD_CTXID0_TRAP_CODE_MASK) >> \ + KFD_CTXID0_TRAP_CODE_SHIFT) +#define KFD_CTXID0_CP_BAD_OP_ECODE(ctxid0) (((ctxid0) & \ + KFD_CTXID0_CP_BAD_OP_ECODE_MASK) >> \ + KFD_CTXID0_TRAP_CODE_SHIFT) +#define KFD_CTXID0_DOORBELL_ID(ctxid0) ((ctxid0) & \ + KFD_CTXID0_DOORBELL_ID_MASK) + +static void print_sq_intr_info_auto(uint32_t context_id0, uint32_t context_id1) +{ + pr_debug_ratelimited( + "sq_intr: auto, ttrace %d, wlt %d, ttrace_buf0_full %d, ttrace_buf1_full %d ttrace_utc_err %d\n", + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, WLT), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_BUF0_FULL), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_BUF1_FULL), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_AUTO_CTXID0, THREAD_TRACE_UTC_ERROR)); +} + +static void print_sq_intr_info_inst(uint32_t context_id0, uint32_t context_id1) +{ + pr_debug_ratelimited( + "sq_intr: inst, data 0x%08x, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n", + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, DATA), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, SA_ID), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID0, WAVE_ID), + REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, SIMD_ID), + REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, WGP_ID)); +} + +static void print_sq_intr_info_error(uint32_t context_id0, uint32_t context_id1) +{ + pr_debug_ratelimited( + "sq_intr: error, detail 0x%08x, type %d, sh %d, priv %d, wave_id %d, simd_id %d, wgp_id %d\n", + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, DETAIL), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, SA_ID), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, PRIV), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID0, WAVE_ID), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, SIMD_ID), + REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_ERROR_CTXID1, WGP_ID)); +} + +static void event_interrupt_poison_consumption_v12_1(struct kfd_node *node, + uint16_t pasid, uint16_t source_id) +{ + enum amdgpu_ras_block block = 0; + int ret = -EINVAL; + uint32_t reset = 0; + u64 event_id = RAS_EVENT_INVALID_ID; + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid, NULL); + + if (!p) + return; + + /* all queues of a process will be unmapped in one time */ + if (atomic_read(&p->poison)) { + kfd_unref_process(p); + return; + } + + atomic_set(&p->poison, 1); + kfd_unref_process(p); + + switch (source_id) { + case SOC15_INTSRC_SQ_INTERRUPT_MSG: + if (node->dqm->ops.reset_queues) + ret = node->dqm->ops.reset_queues(node->dqm, pasid); + block = AMDGPU_RAS_BLOCK__GFX; + if (ret) + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + break; + case SOC21_INTSRC_SDMA_ECC: + default: + block = AMDGPU_RAS_BLOCK__GFX; + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + break; + } + + kfd_signal_poison_consumed_event(node, pasid); + + /* + * resetting queue passes, do page retirement without gpu reset + * resetting queue fails, fallback to gpu reset solution + */ + if (amdgpu_uniras_enabled(node->adev)) + event_id = amdgpu_ras_mgr_gen_ras_event_seqno(node->adev, + RAS_SEQNO_TYPE_POISON_CONSUMPTION); + + RAS_EVENT_LOG(node->adev, event_id, + "poison is consumed by source %d, kick off gpu reset flow\n", source_id); + + amdgpu_amdkfd_ras_pasid_poison_consumption_handler(node->adev, + block, pasid, NULL, NULL, reset); +} + +static bool event_interrupt_isr_v12_1(struct kfd_node *node, + const uint32_t *ih_ring_entry, + uint32_t *patched_ihre, + bool *patched_flag) +{ + uint16_t source_id, client_id, pasid, vmid, node_id; + const uint32_t *data = ih_ring_entry; + uint32_t context_id0; + + node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry); + vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); + + if (!kfd_irq_is_from_node(node, node_id, vmid)) { + pr_debug("Interrupt not for Node, node_id: %d, vmid: %d\n", node_id, vmid); + return false; + } + + source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); + client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); + + /* Only handle interrupts from KFD VMIDs */ + if (!KFD_IRQ_IS_FENCE(client_id, source_id) && + (vmid < node->vm_info.first_vmid_kfd || + vmid > node->vm_info.last_vmid_kfd)) + return false; + + pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); + context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); + + if ((source_id == SOC15_INTSRC_CP_END_OF_PIPE) && + (context_id0 & AMDGPU_FENCE_MES_QUEUE_FLAG)) + return false; + + pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n", + client_id, source_id, vmid, pasid); + pr_debug("%8X, %8X, %8X, %8X, %8X, %8X, %8X, %8X.\n", + data[0], data[1], data[2], data[3], + data[4], data[5], data[6], data[7]); + + /* If there is no valid PASID, it's likely a bug */ + if (WARN_ONCE(pasid == 0, "Bug: No PASID in KFD interrupt")) + return false; + + /* Interrupt types we care about: various signals and faults. + * They will be forwarded to a work queue (see below). + */ + return source_id == SOC15_INTSRC_CP_END_OF_PIPE || + source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG || + source_id == SOC15_INTSRC_CP_BAD_OPCODE || + source_id == SOC21_INTSRC_SDMA_TRAP || + KFD_IRQ_IS_FENCE(client_id, source_id) || + ((client_id == SOC21_IH_CLIENTID_VMC || + client_id == SOC21_IH_CLIENTID_UTCL2) && + !amdgpu_no_queue_eviction_on_vm_fault); +} + +static void event_interrupt_wq_v12_1(struct kfd_node *node, + const uint32_t *ih_ring_entry) +{ + uint16_t source_id, client_id, ring_id, pasid, vmid; + uint32_t context_id0, context_id1; + uint8_t sq_int_enc, sq_int_priv, sq_int_errtype; + struct kfd_vm_fault_info info = {0}; + struct kfd_hsa_memory_exception_data exception_data; + + source_id = SOC15_SOURCE_ID_FROM_IH_ENTRY(ih_ring_entry); + client_id = SOC15_CLIENT_ID_FROM_IH_ENTRY(ih_ring_entry); + ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); + pasid = SOC15_PASID_FROM_IH_ENTRY(ih_ring_entry); + vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry); + context_id0 = SOC15_CONTEXT_ID0_FROM_IH_ENTRY(ih_ring_entry); + context_id1 = SOC15_CONTEXT_ID1_FROM_IH_ENTRY(ih_ring_entry); + + /* VMC, UTCL2 */ + if (client_id == SOC21_IH_CLIENTID_VMC || + client_id == SOC21_IH_CLIENTID_UTCL2) { + info.vmid = vmid; + info.mc_id = client_id; + info.page_addr = ih_ring_entry[4] | + (uint64_t)(ih_ring_entry[5] & 0xf) << 32; + info.prot_valid = ring_id & 0x08; + info.prot_read = ring_id & 0x10; + info.prot_write = ring_id & 0x20; + + memset(&exception_data, 0, sizeof(exception_data)); + exception_data.gpu_id = node->id; + exception_data.va = (info.page_addr) << PAGE_SHIFT; + exception_data.failure.NotPresent = info.prot_valid ? 1 : 0; + exception_data.failure.NoExecute = info.prot_exec ? 1 : 0; + exception_data.failure.ReadOnly = info.prot_write ? 1 : 0; + exception_data.failure.imprecise = 0; + + kfd_set_dbg_ev_from_interrupt(node, pasid, -1, + KFD_EC_MASK(EC_DEVICE_MEMORY_VIOLATION), + &exception_data, sizeof(exception_data)); + kfd_smi_event_update_vmfault(node, pasid); + + /* GRBM, SDMA, SE, PMM */ + } else if (client_id == SOC21_IH_CLIENTID_GRBM_CP || + client_id == SOC21_IH_CLIENTID_GFX) { + + /* CP */ + if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) + kfd_signal_event_interrupt(pasid, context_id0, 32, false); + else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && + KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) { + u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0); + + kfd_set_dbg_ev_from_interrupt(node, pasid, doorbell_id, + KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)), + NULL, 0); + kfd_dqm_suspend_bad_queue_mes(node, pasid, doorbell_id); + } + + /* SDMA */ + else if (source_id == SOC21_INTSRC_SDMA_TRAP) + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); + else if (source_id == SOC21_INTSRC_SDMA_ECC) { + event_interrupt_poison_consumption_v12_1(node, pasid, source_id); + return; + } + + /* SQ */ + else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { + sq_int_enc = REG_GET_FIELD(context_id1, + SQ_INTERRUPT_WORD_WAVE_CTXID1, ENCODING); + switch (sq_int_enc) { + case SQ_INTERRUPT_WORD_ENCODING_AUTO: + print_sq_intr_info_auto(context_id0, context_id1); + break; + case SQ_INTERRUPT_WORD_ENCODING_INST: + print_sq_intr_info_inst(context_id0, context_id1); + sq_int_priv = REG_GET_FIELD(context_id0, + SQ_INTERRUPT_WORD_WAVE_CTXID0, PRIV); + if (sq_int_priv && (kfd_set_dbg_ev_from_interrupt(node, pasid, + KFD_CTXID0_DOORBELL_ID(context_id0), + KFD_CTXID0_TRAP_CODE(context_id0), + NULL, 0))) + return; + break; + case SQ_INTERRUPT_WORD_ENCODING_ERROR: + print_sq_intr_info_error(context_id0, context_id1); + sq_int_errtype = REG_GET_FIELD(context_id0, + SQ_INTERRUPT_WORD_ERROR_CTXID0, TYPE); + if (sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && + sq_int_errtype != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { + event_interrupt_poison_consumption_v12_1( + node, pasid, source_id); + return; + } + break; + default: + break; + } + kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24, true); + } + + } else if (KFD_IRQ_IS_FENCE(client_id, source_id)) { + kfd_process_close_interrupt_drain(pasid); + } +} + +const struct kfd_event_interrupt_class event_interrupt_class_v12_1 = { + .interrupt_isr = event_interrupt_isr_v12_1, + .interrupt_wq = event_interrupt_wq_v12_1, +}; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index d76fb61869c75..1688d8e595f2f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -379,7 +379,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SE2SH || client_id == SOC15_IH_CLIENTID_SE3SH) { if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) - kfd_signal_event_interrupt(pasid, context_id0, 32); + kfd_signal_event_interrupt(pasid, context_id0, 32, true); else if (source_id == SOC15_INTSRC_SQ_INTERRUPT_MSG) { sq_int_data = KFD_CONTEXT_ID_GET_SQ_INT_DATA(context_id0, context_id1); encoding = REG_GET_FIELD(context_id0, SQ_INTERRUPT_WORD_WAVE_CTXID, ENCODING); @@ -513,7 +513,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, sq_int_data, 24); + kfd_signal_event_interrupt(pasid, sq_int_data, 24, true); } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && KFD_DBG_EC_TYPE_IS_PACKET(KFD_DEBUG_CP_BAD_OP_ECODE(context_id0))) { kfd_set_dbg_ev_from_interrupt(dev, pasid, @@ -530,7 +530,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SDMA6 || client_id == SOC15_IH_CLIENTID_SDMA7) { if (source_id == SOC15_INTSRC_SDMA_TRAP) { - kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); + kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28, true); } else if (source_id == SOC15_INTSRC_SDMA_ECC) { event_interrupt_poison_consumption_v9(dev, pasid, client_id); return; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c new file mode 100644 index 0000000000000..055a4c9364471 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -0,0 +1,276 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "kfd_ipc.h" +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" + +#define KFD_IPC_HASH_TABLE_SIZE_SHIFT 4 +#define KFD_IPC_HASH_TABLE_SIZE_MASK ((1 << KFD_IPC_HASH_TABLE_SIZE_SHIFT) - 1) + +static struct kfd_ipc_handles { + DECLARE_HASHTABLE(handles, KFD_IPC_HASH_TABLE_SIZE_SHIFT); + struct mutex lock; +} kfd_ipc_handles; + +/* Since, handles are random numbers, it can be used directly as hashing key. + * The least 4 bits of the handle are used as key. However, during import all + * 128 bits of the handle are checked to prevent handle snooping. + */ +#define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) + +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags, uint32_t *restore_handle) +{ + struct kfd_ipc_obj *obj; + + obj = kmalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + + if (restore_handle) + memcpy(obj->share_handle, restore_handle, sizeof(obj->share_handle)); + else + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + if (restore_handle) { + struct kfd_ipc_obj *entry; + + /* When doing CRIU restore, we may have a race condition where two processes try + * to insert handles with the same key. Make sure this key does not already exist + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)], node) { + if (!memcmp(entry->share_handle, + obj->share_handle, + sizeof(entry->share_handle))) { + mutex_unlock(&kfd_ipc_handles.lock); + kfree(obj); + return -EINVAL; + } + } + } + + /* The initial ref belongs to the allocator process. + * The IPC object store itself does not hold a ref since + * there is no specific moment in time where that ref should + * be dropped, except "when there are no more userspace processes + * holding a ref to the object". Therefore the removal from IPC + * storage happens at ipc_obj release time. + */ + kref_init(&obj->ref); + obj->dmabuf = dmabuf; + obj->flags = flags; + + hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + mutex_unlock(&kfd_ipc_handles.lock); + + if (ipc_obj) + *ipc_obj = obj; + + return 0; +} + +static void ipc_obj_release(struct kref *r) +{ + struct kfd_ipc_obj *obj; + + obj = container_of(r, struct kfd_ipc_obj, ref); + + mutex_lock(&kfd_ipc_handles.lock); + hash_del(&obj->node); + mutex_unlock(&kfd_ipc_handles.lock); + + dma_buf_put(obj->dmabuf); + kfree(obj); +} + +static struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) +{ + if (kref_get_unless_zero(&obj->ref)) + return obj; + return NULL; +} + +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj) +{ + if (*obj) { + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; + } +} + +int kfd_ipc_init(void) +{ + mutex_init(&kfd_ipc_handles.lock); + hash_init(kfd_ipc_handles.handles); + return 0; +} + +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, + struct kfd_process *p, + uint32_t gpu_id, + struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset, bool restore) +{ + int r; + struct kgd_mem *mem; + uint64_t size; + int idr_handle; + struct kfd_process_device *pdd = NULL; + + if (!handle) + return -EINVAL; + + if (!dev) + return -EINVAL; + + if (restore) + idr_handle = GET_IDR_HANDLE(*handle); + else + idr_handle = -1; + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) + return PTR_ERR(pdd); + + r = amdgpu_amdkfd_gpuvm_import_ipcobj(dev->adev, dmabuf, ipc_obj, + va_addr, pdd->drm_priv, + &mem, &size, mmap_offset); + if (r) + return r; + + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + va_addr, size, 0, 0, idr_handle); + if (idr_handle < 0) { + r = -EFAULT; + goto err_free; + } + + *handle = MAKE_HANDLE(gpu_id, idr_handle); + + return 0; + +err_free: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); + return r; +} + +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset, uint32_t *pflags, bool restore) +{ + int r; + struct kfd_ipc_obj *entry, *found = NULL; + + mutex_lock(&kfd_ipc_handles.lock); + /* Convert the user provided handle to hash key and search only in that + * bucket + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { + if (!memcmp(entry->share_handle, share_handle, + sizeof(entry->share_handle))) { + found = ipc_obj_get(entry); + break; + } + } + mutex_unlock(&kfd_ipc_handles.lock); + + if (!found) + return -EINVAL; + + pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); + + if (!restore) { + mutex_lock(&p->mutex); + } + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, + found->dmabuf, found, + va_addr, handle, mmap_offset, + restore); + if (!restore) { + mutex_unlock(&p->mutex); + } + if (r) + goto error_unref; + + if (pflags) + *pflags = found->flags; + + return r; + +error_unref: + kfd_ipc_obj_put(&found); + return r; +} + +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags) +{ + struct kfd_process_device *pdd = NULL; + struct kfd_ipc_obj *ipc_obj; + struct kfd_bo *kfd_bo = NULL; + struct kgd_mem *mem; + int r; + + if (!dev || !ipc_handle) + return -EINVAL; + + /* Protect kgd_mem object from being deleted by another thread */ + mutex_lock(&p->mutex); + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + pr_err("Failed to get pdd\n"); + r = PTR_ERR(pdd); + goto unlock; + } + + kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); + + if (!kfd_bo) { + pr_err("Failed to get bo"); + r = -EINVAL; + goto unlock; + } + mem = (struct kgd_mem *)kfd_bo->mem; + + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, + &ipc_obj, flags, NULL); + if (r) + goto unlock; + + memcpy(ipc_handle, ipc_obj->share_handle, + sizeof(ipc_obj->share_handle)); + +unlock: + mutex_unlock(&p->mutex); + return r; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h new file mode 100644 index 0000000000000..ade507630818d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -0,0 +1,54 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_IPC_H_ +#define KFD_IPC_H_ + +#include +#include + +/* avoid including kfd_priv.h */ +struct kfd_node; +struct kfd_process; + +struct kfd_ipc_obj { + struct hlist_node node; + struct kref ref; + struct dma_buf *dmabuf; + uint32_t share_handle[4]; + uint32_t flags; +}; + +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset, uint32_t *pflags, bool restore); +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags); + +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags, uint32_t *restore_handle); +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); + +#endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index fb3129883a4ca..d987ff7ccfc95 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -57,19 +57,7 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, kq->dev = dev; kq->nop_packet = nop.u32all; - switch (type) { - case KFD_QUEUE_TYPE_DIQ: - kq->mqd_mgr = dev->dqm->mqd_mgrs[KFD_MQD_TYPE_DIQ]; - break; - case KFD_QUEUE_TYPE_HIQ: - kq->mqd_mgr = dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; - break; - default: - WARN(1, "Invalid queue type %d\n", type); - dev_err(dev->adev->dev, "Invalid queue type %d\n", type); - return false; - } - + kq->mqd_mgr = dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]; if (!kq->mqd_mgr) return false; @@ -141,9 +129,8 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, goto err_init_queue; kq->queue->device = dev; - kq->queue->process = kfd_get_process(current); - kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr->dev, + kq->queue->mqd_mem_obj = kq->mqd_mgr->allocate_mqd(kq->mqd_mgr, &kq->queue->properties); if (!kq->queue->mqd_mem_obj) goto err_allocate_mqd; @@ -159,24 +146,11 @@ static bool kq_initialize(struct kernel_queue *kq, struct kfd_node *dev, kq->mqd_mgr->load_mqd(kq->mqd_mgr, kq->queue->mqd, kq->queue->pipe, kq->queue->queue, &kq->queue->properties, NULL); - } else { - /* allocate fence for DIQ */ - - retval = kfd_gtt_sa_allocate(dev, sizeof(uint32_t), - &kq->fence_mem_obj); - - if (retval != 0) - goto err_alloc_fence; - - kq->fence_kernel_address = kq->fence_mem_obj->cpu_ptr; - kq->fence_gpu_addr = kq->fence_mem_obj->gpu_addr; } print_queue(kq->queue); return true; -err_alloc_fence: - kq->mqd_mgr->free_mqd(kq->mqd_mgr, kq->queue->mqd, kq->queue->mqd_mem_obj); err_allocate_mqd: uninit_queue(kq->queue); err_init_queue: @@ -206,8 +180,6 @@ static void kq_uninitialize(struct kernel_queue *kq) kq->queue->queue); up_read(&kq->dev->adev->reset_domain->sem); } - else if (kq->queue->properties.type == KFD_QUEUE_TYPE_DIQ) - kfd_gtt_sa_free(kq->dev, kq->fence_mem_obj); kq->mqd_mgr->free_mqd(kq->mqd_mgr, kq->queue->mqd, kq->queue->mqd_mem_obj); @@ -256,7 +228,7 @@ int kq_acquire_packet_buffer(struct kernel_queue *kq, if (packet_size_in_dwords > available_size) { /* * make sure calling functions know - * acquire_packet_buffer() failed + * kq_acquire_packet_buffer() failed */ goto err_no_space; } @@ -355,34 +327,3 @@ void kernel_queue_uninit(struct kernel_queue *kq) kq_uninitialize(kq); kfree(kq); } - -/* FIXME: Can this test be removed? */ -static __attribute__((unused)) void test_kq(struct kfd_node *dev) -{ - struct kernel_queue *kq; - uint32_t *buffer, i; - int retval; - - dev_err(dev->adev->dev, "Starting kernel queue test\n"); - - kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_HIQ); - if (unlikely(!kq)) { - dev_err(dev->adev->dev, " Failed to initialize HIQ\n"); - dev_err(dev->adev->dev, "Kernel queue test failed\n"); - return; - } - - retval = kq_acquire_packet_buffer(kq, 5, &buffer); - if (unlikely(retval != 0)) { - dev_err(dev->adev->dev, " Failed to acquire packet buffer\n"); - dev_err(dev->adev->dev, "Kernel queue test failed\n"); - return; - } - for (i = 0; i < 5; i++) - buffer[i] = kq->nop_packet; - kq_submit_packet(kq); - - dev_err(dev->adev->dev, "Ending kernel queue test\n"); -} - - diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 6ada7b4af7c68..3ea3c56d4cd08 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -45,7 +45,9 @@ svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, u64 addr) } static int -svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, +svm_migrate_gart_map(struct amdgpu_ring *ring, + struct amdgpu_ttm_buffer_entity *entity, + u64 npages, dma_addr_t *addr, u64 *gart_addr, u64 flags) { struct amdgpu_device *adev = ring->adev; @@ -57,13 +59,12 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, void *cpu_addr; int r; - /* use gart window 0 */ - *gart_addr = adev->gmc.gart_start; + *gart_addr = amdgpu_compute_gart_address(&adev->gmc, entity, 0); num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8); - num_bytes = npages * 8; + num_bytes = npages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; - r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr, + r = amdgpu_job_alloc_with_ib(adev, &entity->base, AMDGPU_FENCE_OWNER_UNDEFINED, num_dw * 4 + num_bytes, AMDGPU_IB_POOL_DELAYED, @@ -76,6 +77,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, src_addr += job->ibs[0].gpu_addr; dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); + dst_addr += (entity->gart_window_offs[0] >> AMDGPU_GPU_PAGE_SHIFT) * 8; amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr, num_bytes, 0); @@ -114,7 +116,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages, * multiple GTT_MAX_PAGES transfer, all sdma operations are serialized, wait for * the last sdma finish fence which is returned to check copy memory is done. * - * Context: Process context, takes and releases gtt_window_lock + * Context: Process context * * Return: * 0 - OK, otherwise error code @@ -128,22 +130,25 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, { const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE; struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; + struct amdgpu_ttm_buffer_entity *entity; u64 gart_s, gart_d; struct dma_fence *next; u64 size; int r; - mutex_lock(&adev->mman.gtt_window_lock); + entity = &adev->mman.move_entity; + + mutex_lock(&entity->lock); while (npages) { size = min(GTT_MAX_PAGES, npages); if (direction == FROM_VRAM_TO_RAM) { gart_s = svm_migrate_direct_mapping_addr(adev, *vram); - r = svm_migrate_gart_map(ring, size, sys, &gart_d, 0); + r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0); } else if (direction == FROM_RAM_TO_VRAM) { - r = svm_migrate_gart_map(ring, size, sys, &gart_s, + r = svm_migrate_gart_map(ring, entity, size, sys, &gart_s, KFD_IOCTL_SVM_FLAG_GPU_RO); gart_d = svm_migrate_direct_mapping_addr(adev, *vram); } @@ -152,8 +157,9 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, goto out_unlock; } - r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE, - NULL, &next, false, true, 0); + r = amdgpu_copy_buffer(adev, entity, + gart_s, gart_d, size * PAGE_SIZE, + NULL, &next, true, 0); if (r) { dev_err(adev->dev, "fail %d to copy memory\n", r); goto out_unlock; @@ -169,7 +175,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys, } out_unlock: - mutex_unlock(&adev->mman.gtt_window_lock); + mutex_unlock(&entity->lock); return r; } @@ -206,7 +212,11 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence) unsigned long svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) { +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr + adev->kfd.pgmap.range.start) >> PAGE_SHIFT; +#else + return (addr + adev->kfd.pgmap.res.start) >> PAGE_SHIFT; +#endif } static void @@ -217,7 +227,11 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; +#ifdef HAVE_PAGE_PGMAP zone_device_page_init(page, page_pgmap(page), 0); +#else + zone_device_page_init(page, page->pgmap, 0); +#endif } static void @@ -236,7 +250,12 @@ svm_migrate_addr(struct amdgpu_device *adev, struct page *page) unsigned long addr; addr = page_to_pfn(page) << PAGE_SHIFT; +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr - adev->kfd.pgmap.range.start); +#else + return (addr - adev->kfd.pgmap.res.start); +#endif + } static struct page * @@ -304,6 +323,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); svm_migrate_get_vram_page(prange, migrate->dst[i]); migrate->dst[i] = migrate_pfn(migrate->dst[i]); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; mpages++; } spage = migrate_pfn_to_page(migrate->src[i]); @@ -404,8 +424,12 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#elif defined(HAVE_DEV_PAGEMAP_OWNER) + migrate.src_owner = NULL; +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t), @@ -566,7 +590,7 @@ svm_migrate_ram_to_vram(struct svm_range *prange, uint32_t best_loc, node->xcp ? node->xcp->id : 0); return r < 0 ? r : 0; } - +#ifdef HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE static void svm_migrate_folio_free(struct folio *folio) { struct page *page = &folio->page; @@ -577,6 +601,17 @@ static void svm_migrate_folio_free(struct folio *folio) svm_range_bo_unref_async(svm_bo); } } +#else +static void svm_migrate_page_free(struct page *page) +{ + struct svm_range_bo *svm_bo = page->zone_device_data; + + if (svm_bo) { + pr_debug_ratelimited("ref: %d\n", kref_read(&svm_bo->kref)); + svm_range_bo_unref_async(svm_bo); + } +} +#endif static int svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, @@ -647,6 +682,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, dst[i] >> PAGE_SHIFT, page_to_pfn(dpage)); migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; j++; } @@ -703,11 +739,17 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else +#endif migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; +#elif defined(HAVE_DEV_PAGEMAP_OWNER) + migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(u64) + sizeof(dma_addr_t), @@ -717,7 +759,9 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.src = buf; migrate.dst = migrate.src + npages; +#ifdef HAVE_MIGRATE_VMA_FAULT_PAGE migrate.fault_page = fault_page; +#endif scratch = (dma_addr_t *)(migrate.dst + npages); kfd_smi_event_migration_start(node, p->lead_thread->pid, @@ -1009,7 +1053,11 @@ static vm_fault_t svm_migrate_to_ram(struct vm_fault *vmf) } static const struct dev_pagemap_ops svm_migrate_pgmap_ops = { +#ifdef HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE .folio_free = svm_migrate_folio_free, +#else + .page_free = svm_migrate_page_free, +#endif .migrate_to_ram = svm_migrate_to_ram, }; @@ -1038,23 +1086,40 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) * should remove reserved size */ size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) { +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = adev->gmc.aper_base; pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#else + pgmap->res.start = adev->gmc.aper_base; + pgmap->res.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#endif pgmap->type = MEMORY_DEVICE_COHERENT; - } else { + } else +#endif + { res = devm_request_free_mem_region(adev->dev, &iomem_resource, size); if (IS_ERR(res)) return PTR_ERR(res); +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = res->start; pgmap->range.end = res->end; +#else + pgmap->res.start = res->start; + pgmap->res.end = res->end; +#endif pgmap->type = MEMORY_DEVICE_PRIVATE; } - pgmap->nr_range = 1; pgmap->ops = &svm_migrate_pgmap_ops; +#ifdef HAVE_DEV_PAGEMAP_OWNER pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif pgmap->flags = 0; + /* Device manager releases device-specific resources, memory region and * pgmap when driver disconnects from device. */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 33aa23450b3f7..2434619cddc1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -53,10 +53,16 @@ static int kfd_init(void) if (err < 0) goto err_topology; + err = kfd_ipc_init(); + if (err < 0) + goto err_ipc; + err = kfd_process_create_wq(); if (err < 0) goto err_create_wq; + kfd_init_peer_direct(); + /* Ignore the return value, so that we can continue * to init the KFD, even if procfs isn't craated */ @@ -67,6 +73,7 @@ static int kfd_init(void) return 0; err_create_wq: +err_ipc: kfd_topology_shutdown(); err_topology: kfd_chardev_exit(); @@ -78,6 +85,7 @@ static int kfd_init(void) static void kfd_exit(void) { kfd_cleanup_processes(); + kfd_close_peer_direct(); kfd_process_destroy_wq(); kfd_debugfs_fini(); kfd_procfs_shutdown(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index d9ae854b69084..d88d0de58edd1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -46,25 +46,27 @@ int pipe_priority_map[] = { KFD_PIPE_PRIORITY_CS_HIGH }; -struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, struct queue_properties *q) +struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q) { struct kfd_mem_obj *mqd_mem_obj; + struct kfd_node *dev = mm->dev; mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); if (!mqd_mem_obj) return NULL; - mqd_mem_obj->gtt_mem = dev->dqm->hiq_sdma_mqd.gtt_mem; + mqd_mem_obj->mem = dev->dqm->hiq_sdma_mqd.mem; mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr; return mqd_mem_obj; } -struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, struct queue_properties *q) { struct kfd_mem_obj *mqd_mem_obj; + struct kfd_node *dev = mm->dev; uint64_t offset; mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); @@ -79,7 +81,7 @@ struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * NUM_XCC(dev->xcc_mask); - mqd_mem_obj->gtt_mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.gtt_mem + mqd_mem_obj->mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.mem + offset); mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t) @@ -91,7 +93,7 @@ struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - WARN_ON(!mqd_mem_obj->gtt_mem); + WARN_ON(!mqd_mem_obj->mem); kfree(mqd_mem_obj); } @@ -224,8 +226,8 @@ int kfd_destroy_mqd_cp(struct mqd_manager *mm, void *mqd, void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj) { - if (mqd_mem_obj->gtt_mem) { - amdgpu_amdkfd_free_gtt_mem(mm->dev->adev, &mqd_mem_obj->gtt_mem); + if (mqd_mem_obj->mem) { + amdgpu_amdkfd_free_kernel_mem(mm->dev->adev, &mqd_mem_obj->mem); kfree(mqd_mem_obj); } else { kfd_gtt_sa_free(mm->dev, mqd_mem_obj); @@ -280,8 +282,8 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj, offset = kfd_hiq_mqd_stride(dev) * virtual_xcc_id; - mqd_mem_obj->gtt_mem = (virtual_xcc_id == 0) ? - dev->dqm->hiq_sdma_mqd.gtt_mem : NULL; + mqd_mem_obj->mem = (virtual_xcc_id == 0) ? + dev->dqm->hiq_sdma_mqd.mem : NULL; mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t) dev->dqm->hiq_sdma_mqd.cpu_ptr + offset); @@ -290,6 +292,9 @@ void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj, uint64_t kfd_mqd_stride(struct mqd_manager *mm, struct queue_properties *q) { + if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0)) + return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + return mm->mqd_size; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 17cc1f25c8d08..33cd46de954fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -68,7 +68,7 @@ */ extern int pipe_priority_map[]; struct mqd_manager { - struct kfd_mem_obj* (*allocate_mqd)(struct kfd_node *kfd, + struct kfd_mem_obj* (*allocate_mqd)(struct mqd_manager *mm, struct queue_properties *q); void (*init_mqd)(struct mqd_manager *mm, void **mqd, @@ -102,7 +102,10 @@ struct mqd_manager { u32 *ctl_stack_used_size, u32 *save_area_used_size); - void (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, uint32_t *ctl_stack_size); + bool (*check_queue_active)(struct queue *q); + + int (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, + uint32_t *ctl_stack_size); void (*checkpoint_mqd)(struct mqd_manager *mm, void *mqd, @@ -115,7 +118,6 @@ struct mqd_manager { const void *mqd_src, const void *ctl_stack_src, const u32 ctl_stack_size); - #if defined(CONFIG_DEBUG_FS) int (*debugfs_show_mqd)(struct seq_file *m, void *data); #endif @@ -153,10 +155,10 @@ struct mqd_user_context_save_area_header { uint32_t wave_state_size; }; -struct kfd_mem_obj *allocate_hiq_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q); -struct kfd_mem_obj *allocate_sdma_mqd(struct kfd_node *dev, +struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, struct queue_properties *q); void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, struct kfd_mem_obj *mqd_mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 05f3ac2eaef9e..2ded29c497eb3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -31,6 +31,7 @@ #include "cik_regs.h" #include "cik_structs.h" #include "oss/oss_2_4_sh_mask.h" +#include "gca/gfx_7_2_sh_mask.h" static inline struct cik_mqd *get_mqd(void *mqd) { @@ -42,6 +43,31 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) return (struct cik_sdma_rlc_registers *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_sdma_rlc_registers *m = get_sdma_mqd(q->mqd); + + rptr = m->sdma_rlc_rb_rptr; + wptr = m->sdma_rlc_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -70,12 +96,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct cik_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct cik_mqd), @@ -199,6 +225,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_pq_control |= NO_UPDATE_RPTR; + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; update_cu_mask(mm, mqd, minfo); set_priority(m, q); @@ -403,6 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; mqd->mqd_size = sizeof(struct cik_mqd); @@ -418,6 +448,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct cik_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -447,6 +478,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 1695dd78ede8e..82f194ea2a211 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -70,12 +70,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v10_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct v10_compute_mqd), @@ -123,10 +123,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, */ m->cp_hqd_hq_scheduler0 = 1 << 14; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -141,6 +140,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -220,6 +225,13 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 3c0ae28c5923b..4d8cf6008a776 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -96,25 +96,16 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v11_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - int size; - - /* - * MES write to areas beyond MQD size. So allocate - * 1 PAGE_SIZE memory for MQD is MES is enabled. - */ - if (node->kfd->shared_resources.enable_mes) - size = PAGE_SIZE; - else - size = sizeof(struct v11_compute_mqd); - if (kfd_gtt_sa_allocate(node, size, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -126,18 +117,13 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v11_compute_mqd *m; - int size; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); uint32_t wa_mask = q->is_dbg_wa ? 0xffff : 0xffffffff; m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - if (mm->dev->kfd->shared_resources.enable_mes) - size = PAGE_SIZE; - else - size = sizeof(struct v11_compute_mqd); - - memset(m, 0, size); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; @@ -177,10 +163,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -195,6 +180,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -272,6 +262,12 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, } if (mm->dev->kfd->cwsr_enabled) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index 565858b9044d4..51dde2c86eb38 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -77,19 +77,16 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v12_compute_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj; - /* - * Allocate one PAGE_SIZE memory for MQD as MES writes to areas beyond - * struct MQD size. - */ - if (kfd_gtt_sa_allocate(node, PAGE_SIZE, &mqd_mem_obj)) + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) return NULL; return mqd_mem_obj; @@ -101,11 +98,12 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, { uint64_t addr; struct v12_compute_mqd *m; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); m = (struct v12_compute_mqd *) mqd_mem_obj->cpu_ptr; addr = mqd_mem_obj->gpu_addr; - memset(m, 0, PAGE_SIZE); + memset(m, 0, mqd_size); m->header = 0xC0310800; m->compute_pipelinestat_enable = 1; @@ -140,10 +138,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) m->cp_hqd_hq_status0 |= 1 << 29; - if (q->format == KFD_QUEUE_FORMAT_AQL) { + if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - } if (mm->dev->kfd->cwsr_enabled) { m->cp_hqd_persistent_state |= @@ -158,6 +155,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -351,6 +353,12 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; + /* Allow context switch so we don't cross-process starve with a massive + * command buffer of long-running SDMA commands + * sdmax_rlcx_ib_cntl represent SDMA_QUEUE0_IB_CNTL register + */ + m->sdmax_rlcx_ib_cntl |= SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK; + q->is_active = QUEUE_IS_ACTIVE(*q); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c new file mode 100644 index 0000000000000..6e591103c3b60 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c @@ -0,0 +1,724 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include "kfd_priv.h" +#include "kfd_mqd_manager.h" +#include "v12_structs.h" +#include "gc/gc_12_1_0_sh_mask.h" +#include "amdgpu_amdkfd.h" +#include "kfd_device_queue_manager.h" + +static inline struct v12_1_compute_mqd *get_mqd(void *mqd) +{ + return (struct v12_1_compute_mqd *)mqd; +} + +static inline struct v12_sdma_mqd *get_sdma_mqd(void *mqd) +{ + return (struct v12_sdma_mqd *)mqd; +} + +static void mqd_symmetrically_map_cu_mask_v12_1(struct mqd_manager *mm, + const uint32_t *cu_mask, uint32_t cu_mask_count, + uint32_t *se_mask, uint32_t inst) +{ + struct amdgpu_cu_info *cu_info = &mm->dev->adev->gfx.cu_info; + struct amdgpu_gfx_config *gfx_info = &mm->dev->adev->gfx.config; + uint32_t cu_per_sh[2][2] = {0}; + uint32_t en_mask = 0x3; + int i, se, sh, cu, cu_inc = 0; + uint32_t cu_active_per_node; + int inc = NUM_XCC(mm->dev->xcc_mask); + int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; + + cu_active_per_node = cu_info->number / mm->dev->kfd->num_nodes; + if (cu_mask_count > cu_active_per_node) + cu_mask_count = cu_active_per_node; + + /* + * Count active CUs per SE/SH. + */ + for (se = 0; se < gfx_info->max_shader_engines; se++) + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) + cu_per_sh[se][sh] = hweight32( + cu_info->bitmap[xcc_inst][se][sh]); + + /* Symmetrically map cu_mask to all SEs & SHs: + * For GFX 12.1.0, the following code only looks at a + * subset of the cu_mask corresponding to the inst parameter. + * If we have n XCCs under one GPU node + * cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0) + * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0) + * .. + * cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0) + * cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0) + * + * For example, if there are 6 XCCs under 1 KFD node, this code + * running for each inst, will look at the bits as: + * inst, inst + 6, inst + 12... + * + * First ensure all CUs are disabled, then enable user specified CUs. + */ + for (i = 0; i < gfx_info->max_shader_engines; i++) + se_mask[i] = 0; + + i = inst; + for (cu = 0; cu < 16; cu++) { + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { + for (se = 0; se < gfx_info->max_shader_engines; se++) { + if (cu_per_sh[se][sh] > cu) { + if (cu_mask[i / 32] & (1U << (i % 32))) { + if (cu == 8 && sh == 0) + se_mask[se] |= en_mask << 30; + else + se_mask[se] |= en_mask << (cu_inc + sh * 16); + } + i += inc; + if (i >= cu_mask_count) + return; + } + } + } + cu_inc += 2; + } +} + +static void update_cu_mask(struct mqd_manager *mm, void *mqd, + struct mqd_update_info *minfo, uint32_t inst) +{ + struct v12_1_compute_mqd *m; + uint32_t se_mask[2] = {0}; + + if (!minfo || !minfo->cu_mask.ptr) + return; + + mqd_symmetrically_map_cu_mask_v12_1(mm, + minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); + + m = get_mqd(mqd); + m->compute_static_thread_mgmt_se0 = se_mask[0]; + m->compute_static_thread_mgmt_se1 = se_mask[1]; + + pr_debug("update cu mask to %#x %#x\n", + m->compute_static_thread_mgmt_se0, + m->compute_static_thread_mgmt_se1); +} + +static void set_priority(struct v12_1_compute_mqd *m, struct queue_properties *q) +{ + m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; +} + +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, + struct queue_properties *q) +{ + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + struct kfd_node *node = mm->dev; + struct kfd_mem_obj *mqd_mem_obj; + + if (q->type == KFD_QUEUE_TYPE_COMPUTE) + mqd_size *= NUM_XCC(node->xcc_mask); + + if (kfd_gtt_sa_allocate(node, mqd_size, &mqd_mem_obj)) + return NULL; + + return mqd_mem_obj; +} + +static void init_mqd(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + uint64_t addr; + struct v12_1_compute_mqd *m; + u32 mqd_size = AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); + + m = (struct v12_1_compute_mqd *) mqd_mem_obj->cpu_ptr; + addr = mqd_mem_obj->gpu_addr; + + memset(m, 0, mqd_size); + + m->header = 0xC0310800; + m->compute_pipelinestat_enable = 1; + m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se4 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se5 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se6 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se7 = 0xFFFFFFFF; + m->compute_static_thread_mgmt_se8 = 0xFFFFFFFF; + + m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK | + 0x63 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT; + + m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT; + + m->cp_mqd_base_addr_lo = lower_32_bits(addr); + m->cp_mqd_base_addr_hi = upper_32_bits(addr); + + m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT | + 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT | + 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT; + + /* Set cp_hqd_hq_status0.c_queue_debug_en to 1 to have the CP set up the + * DISPATCH_PTR. This is required for the kfd debugger + */ + m->cp_hqd_hq_status0 = 1 << 14; + + if (amdgpu_amdkfd_have_atomics_support(mm->dev->adev)) + m->cp_hqd_hq_status0 |= 1 << 29; + + if (q->format == KFD_QUEUE_FORMAT_AQL) { + m->cp_hqd_aql_control = + 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; + } + + if (mm->dev->kfd->cwsr_enabled) { + m->cp_hqd_persistent_state |= + (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT); + m->cp_hqd_ctx_save_base_addr_lo = + lower_32_bits(q->ctx_save_restore_area_address); + m->cp_hqd_ctx_save_base_addr_hi = + upper_32_bits(q->ctx_save_restore_area_address); + m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size; + m->cp_hqd_cntl_stack_size = q->ctl_stack_size; + m->cp_hqd_cntl_stack_offset = q->ctl_stack_size; + m->cp_hqd_wg_state_offset = q->ctl_stack_size; + } + + *mqd = m; + if (gart_addr) + *gart_addr = addr; + mm->update_mqd(mm, m, q, NULL); +} + +static int load_mqd(struct mqd_manager *mm, void *mqd, + uint32_t pipe_id, uint32_t queue_id, + struct queue_properties *p, struct mm_struct *mms) +{ + int r = 0; + /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ + uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); + + r = mm->dev->kfd2kgd->hqd_load(mm->dev->adev, mqd, pipe_id, queue_id, + (uint32_t __user *)p->write_ptr, + wptr_shift, 0, mms, 0); + return r; +} + +static void update_mqd(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, + struct mqd_update_info *minfo) +{ + struct v12_1_compute_mqd *m; + + m = get_mqd(mqd); + + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; + m->cp_hqd_pq_control |= + ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; + pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); + + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); + + if (q->metadata_queue_size) { + /* On GC 12.1 is 64 DWs which is 4 times size of AQL packet */ + if (q->metadata_queue_size == q->queue_size * 4) { + /* + * User application allocates main queue ring and metadata queue ring + * with a single allocation. metadata queue ring starts after main + * queue ring. + */ + m->cp_hqd_kd_base = + lower_32_bits((q->queue_address + q->queue_size) >> 8); + m->cp_hqd_kd_base_hi = + upper_32_bits((q->queue_address + q->queue_size) >> 8); + + m->cp_hqd_kd_cntl |= CP_HQD_KD_CNTL__KD_FETCHER_ENABLE_MASK; + /* KD_SIZE = 2 for metadata packet = 64 DWs */ + m->cp_hqd_kd_cntl |= 2 << CP_HQD_KD_CNTL__KD_SIZE__SHIFT; + } else { + pr_warn("Invalid metadata ring size, metadata queue will be ignored\n"); + } + } + + m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); + m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); + m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); + + m->cp_hqd_pq_doorbell_control = + q->doorbell_off << + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; + pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", + m->cp_hqd_pq_doorbell_control); + + m->cp_hqd_ib_control = 1 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT; + + /* + * HW does not clamp this field correctly. Maximum EOP queue size + * is constrained by per-SE EOP done signal count, which is 8-bit. + * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit + * more than (EOP entry count - 1) so a queue size of 0x800 dwords + * is safe, giving a maximum field value of 0xA. + */ + m->cp_hqd_eop_control = min(0xA, + ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1); + m->cp_hqd_eop_base_addr_lo = + lower_32_bits(q->eop_ring_buffer_address >> 8); + m->cp_hqd_eop_base_addr_hi = + upper_32_bits(q->eop_ring_buffer_address >> 8); + + m->cp_hqd_iq_timer = 0; + + m->cp_hqd_vmid = q->vmid; + + if (q->format == KFD_QUEUE_FORMAT_AQL) { + /* GC 10 removed WPP_CLAMP from PQ Control */ + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | + 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | + 1 << CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT; + m->cp_hqd_pq_doorbell_control |= + 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; + } + if (mm->dev->kfd->cwsr_enabled) + m->cp_hqd_ctx_save_control = 0; + + set_priority(m, q); + + q->is_active = QUEUE_IS_ACTIVE(*q); +} + +static bool check_preemption_failed(struct mqd_manager *mm, void *mqd) +{ + return false; +} + +static int get_wave_state(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, + void __user *ctl_stack, + u32 *ctl_stack_used_size, + u32 *save_area_used_size) +{ + struct v12_1_compute_mqd *m; + struct mqd_user_context_save_area_header header; + + m = get_mqd(mqd); + + /* Control stack is written backwards, while workgroup context data + * is written forwards. Both starts from m->cp_hqd_cntl_stack_size. + * Current position is at m->cp_hqd_cntl_stack_offset and + * m->cp_hqd_wg_state_offset, respectively. + */ + *ctl_stack_used_size = m->cp_hqd_cntl_stack_size - + m->cp_hqd_cntl_stack_offset; + *save_area_used_size = m->cp_hqd_wg_state_offset - + m->cp_hqd_cntl_stack_size; + + /* Control stack is not copied to user mode for GFXv12 because + * it's part of the context save area that is already + * accessible to user mode + */ + header.control_stack_size = *ctl_stack_used_size; + header.wave_state_size = *save_area_used_size; + + header.wave_state_offset = m->cp_hqd_wg_state_offset; + header.control_stack_offset = m->cp_hqd_cntl_stack_offset; + + if (copy_to_user(ctl_stack, &header, sizeof(header))) + return -EFAULT; + + return 0; +} + +static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + struct v12_1_compute_mqd *m; + + init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q); + + m = get_mqd(*mqd); + + m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT | + 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT; +} + +static void init_mqd_sdma(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + struct v12_sdma_mqd *m; + + m = (struct v12_sdma_mqd *) mqd_mem_obj->cpu_ptr; + + memset(m, 0, PAGE_SIZE); + + *mqd = m; + if (gart_addr) + *gart_addr = mqd_mem_obj->gpu_addr; + + mm->update_mqd(mm, m, q, NULL); +} + +#define SDMA_RLC_DUMMY_DEFAULT 0xf + +static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, + struct mqd_update_info *minfo) +{ + struct v12_sdma_mqd *m; + + m = get_sdma_mqd(mqd); + m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1) + << SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | + q->vmid << SDMA0_SDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT | + 1 << SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | + 6 << SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | + 1 << SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT; + + m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); + m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); + m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); + m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); + m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); + m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); + m->sdmax_rlcx_doorbell_offset = + q->doorbell_off << SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; + + m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum + << SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) + & SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; + + m->sdma_engine_id = q->sdma_engine_id; + m->sdma_queue_id = q->sdma_queue_id; + + m->sdmax_rlcx_dummy_reg = SDMA_RLC_DUMMY_DEFAULT; + + /* Allow context switch so we don't cross-process starve with a massive + * command buffer of long-running SDMA commands + * sdmax_rlcx_ib_cntl represent SDMA_QUEUE0_IB_CNTL register + */ + m->sdmax_rlcx_ib_cntl |= SDMA0_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK; + + q->is_active = QUEUE_IS_ACTIVE(*q); +} + +static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, + struct kfd_mem_obj *xcc_mqd_mem_obj, + uint64_t offset) +{ + xcc_mqd_mem_obj->mem = (offset == 0) ? + mqd_mem_obj->mem : NULL; + xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; + xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr + + offset); +} + +static void init_mqd_v12_1(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *q) +{ + struct v12_1_compute_mqd *m; + int xcc = 0; + struct kfd_mem_obj xcc_mqd_mem_obj; + uint64_t xcc_gart_addr = 0; + uint64_t xcc_ctx_save_restore_area_address; + uint64_t offset = mm->mqd_stride(mm, q); + uint32_t local_xcc_start = mm->dev->dqm->current_logical_xcc_start++; + + memset(&xcc_mqd_mem_obj, 0x0, sizeof(struct kfd_mem_obj)); + for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { + get_xcc_mqd(mqd_mem_obj, &xcc_mqd_mem_obj, offset*xcc); + + init_mqd(mm, (void **)&m, &xcc_mqd_mem_obj, &xcc_gart_addr, q); + + m->cp_mqd_stride_size = offset; + + /* + * Update the CWSR address for each XCC if CWSR is enabled + * and CWSR area is allocated in thunk + */ + if (mm->dev->kfd->cwsr_enabled && + q->ctx_save_restore_area_address) { + xcc_ctx_save_restore_area_address = + q->ctx_save_restore_area_address + + (xcc * q->ctx_save_restore_area_size); + + m->cp_hqd_ctx_save_base_addr_lo = + lower_32_bits(xcc_ctx_save_restore_area_address); + m->cp_hqd_ctx_save_base_addr_hi = + upper_32_bits(xcc_ctx_save_restore_area_address); + } + + if (q->format == KFD_QUEUE_FORMAT_AQL) { + m->compute_tg_chunk_size = 1; + m->compute_current_logical_xcc_id = + (local_xcc_start + xcc) % + NUM_XCC(mm->dev->xcc_mask); + } else { + /* PM4 Queue */ + m->compute_current_logical_xcc_id = 0; + m->compute_tg_chunk_size = 0; + m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; + } + + if (xcc == 0) { + /* Set the MQD pointer and gart address to XCC0 MQD */ + *mqd = m; + *gart_addr = xcc_gart_addr; + } + } +} + +static void update_mqd_v12_1(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, struct mqd_update_info *minfo) +{ + struct v12_1_compute_mqd *m; + int xcc = 0; + uint64_t size = mm->mqd_stride(mm, q); + + for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { + m = get_mqd(mqd + size * xcc); + update_mqd(mm, m, q, minfo); + + update_cu_mask(mm, m, minfo, xcc); + + if (q->format == KFD_QUEUE_FORMAT_AQL) { + m->compute_tg_chunk_size = 1; + } else { + /* PM4 Queue */ + m->compute_current_logical_xcc_id = 0; + m->compute_tg_chunk_size = 0; + m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; + } + } +} + +static int destroy_mqd_v12_1(struct mqd_manager *mm, void *mqd, + enum kfd_preempt_type type, unsigned int timeout, + uint32_t pipe_id, uint32_t queue_id) +{ + uint32_t xcc_mask = mm->dev->xcc_mask; + int xcc_id, err, inst = 0; + void *xcc_mqd; + struct v12_1_compute_mqd *m; + uint64_t mqd_offset; + + m = get_mqd(mqd); + mqd_offset = m->cp_mqd_stride_size; + + for_each_inst(xcc_id, xcc_mask) { + xcc_mqd = mqd + mqd_offset * inst; + err = mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, xcc_mqd, + type, timeout, pipe_id, + queue_id, xcc_id); + if (err) { + pr_debug("Destroy MQD failed for xcc: %d\n", inst); + break; + } + ++inst; + } + + return err; +} + +static int load_mqd_v12_1(struct mqd_manager *mm, void *mqd, + uint32_t pipe_id, uint32_t queue_id, + struct queue_properties *p, struct mm_struct *mms) +{ + /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ + uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); + uint32_t xcc_mask = mm->dev->xcc_mask; + int xcc_id, err, inst = 0; + void *xcc_mqd; + uint64_t mqd_stride_size = mm->mqd_stride(mm, p); + + for_each_inst(xcc_id, xcc_mask) { + xcc_mqd = mqd + mqd_stride_size * inst; + err = mm->dev->kfd2kgd->hqd_load( + mm->dev->adev, xcc_mqd, pipe_id, queue_id, + (uint32_t __user *)p->write_ptr, wptr_shift, 0, mms, + xcc_id); + if (err) { + pr_debug("Load MQD failed for xcc: %d\n", inst); + break; + } + ++inst; + } + + return err; +} + +static int get_wave_state_v12_1(struct mqd_manager *mm, void *mqd, + struct queue_properties *q, + void __user *ctl_stack, + u32 *ctl_stack_used_size, + u32 *save_area_used_size) +{ + int xcc, err = 0; + void *xcc_mqd; + void __user *xcc_ctl_stack; + uint64_t mqd_stride_size = mm->mqd_stride(mm, q); + u32 tmp_ctl_stack_used_size = 0, tmp_save_area_used_size = 0; + + for (xcc = 0; xcc < NUM_XCC(mm->dev->xcc_mask); xcc++) { + xcc_mqd = mqd + mqd_stride_size * xcc; + xcc_ctl_stack = (void __user *)((uintptr_t)ctl_stack + + q->ctx_save_restore_area_size * xcc); + + err = get_wave_state(mm, xcc_mqd, q, xcc_ctl_stack, + &tmp_ctl_stack_used_size, + &tmp_save_area_used_size); + if (err) + break; + + /* + * Set the ctl_stack_used_size and save_area_used_size to + * ctl_stack_used_size and save_area_used_size of XCC 0 when + * passing the info to user-space. + * For multi XCC, user-space would have to look at the header + * info of each Control stack area to determine the control + * stack size and save area used. + */ + if (xcc == 0) { + *ctl_stack_used_size = tmp_ctl_stack_used_size; + *save_area_used_size = tmp_save_area_used_size; + } + } + + return err; +} + +#if defined(CONFIG_DEBUG_FS) + +static int debugfs_show_mqd(struct seq_file *m, void *data) +{ + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + data, sizeof(struct v12_1_compute_mqd), false); + return 0; +} + +static int debugfs_show_mqd_sdma(struct seq_file *m, void *data) +{ + seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4, + data, sizeof(struct v12_sdma_mqd), false); + return 0; +} + +#endif + +struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, + struct kfd_node *dev) +{ + struct mqd_manager *mqd; + + if (WARN_ON(type >= KFD_MQD_TYPE_MAX)) + return NULL; + + mqd = kzalloc(sizeof(*mqd), GFP_KERNEL); + if (!mqd) + return NULL; + + mqd->dev = dev; + + switch (type) { + case KFD_MQD_TYPE_CP: + pr_debug("%s@%i\n", __func__, __LINE__); + mqd->allocate_mqd = allocate_mqd; + mqd->init_mqd = init_mqd_v12_1; + mqd->free_mqd = kfd_free_mqd_cp; + mqd->load_mqd = load_mqd_v12_1; + mqd->update_mqd = update_mqd_v12_1; + mqd->destroy_mqd = destroy_mqd_v12_1; + mqd->is_occupied = kfd_is_occupied_cp; + mqd->mqd_size = sizeof(struct v12_1_compute_mqd); + mqd->get_wave_state = get_wave_state_v12_1; + mqd->mqd_stride = kfd_mqd_stride; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif + pr_debug("%s@%i\n", __func__, __LINE__); + break; + case KFD_MQD_TYPE_HIQ: + pr_debug("%s@%i\n", __func__, __LINE__); + mqd->allocate_mqd = allocate_hiq_mqd; + mqd->init_mqd = init_mqd_hiq; + mqd->free_mqd = free_mqd_hiq_sdma; + mqd->load_mqd = kfd_hiq_load_mqd_kiq; + mqd->update_mqd = update_mqd; + mqd->destroy_mqd = kfd_destroy_mqd_cp; + mqd->is_occupied = kfd_is_occupied_cp; + mqd->mqd_size = sizeof(struct v12_1_compute_mqd); + mqd->mqd_stride = kfd_mqd_stride; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif + mqd->check_preemption_failed = check_preemption_failed; + pr_debug("%s@%i\n", __func__, __LINE__); + break; + case KFD_MQD_TYPE_DIQ: + mqd->allocate_mqd = allocate_mqd; + mqd->init_mqd = init_mqd_hiq; + mqd->free_mqd = kfd_free_mqd_cp; + mqd->load_mqd = load_mqd; + mqd->update_mqd = update_mqd; + mqd->destroy_mqd = kfd_destroy_mqd_cp; + mqd->is_occupied = kfd_is_occupied_cp; + mqd->mqd_size = sizeof(struct v12_1_compute_mqd); +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd; +#endif + break; + case KFD_MQD_TYPE_SDMA: + pr_debug("%s@%i\n", __func__, __LINE__); + mqd->allocate_mqd = allocate_mqd; + mqd->init_mqd = init_mqd_sdma; + mqd->free_mqd = kfd_free_mqd_cp; + mqd->load_mqd = kfd_load_mqd_sdma; + mqd->update_mqd = update_mqd_sdma; + mqd->destroy_mqd = kfd_destroy_mqd_sdma; + mqd->is_occupied = kfd_is_occupied_sdma; + mqd->mqd_size = sizeof(struct v12_sdma_mqd); + mqd->mqd_stride = kfd_mqd_stride; +#if defined(CONFIG_DEBUG_FS) + mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; +#endif + pr_debug("%s@%i\n", __func__, __LINE__); + break; + default: + kfree(mqd); + return NULL; + } + + return mqd; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index f2dee320fada4..974688f3f86f6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -42,9 +42,16 @@ static uint64_t mqd_stride_v9(struct mqd_manager *mm, struct queue_properties *q) { if (mm->dev->kfd->cwsr_enabled && - q->type == KFD_QUEUE_TYPE_COMPUTE) - return ALIGN(q->ctl_stack_size, PAGE_SIZE) + - ALIGN(sizeof(struct v9_mqd), PAGE_SIZE); + q->type == KFD_QUEUE_TYPE_COMPUTE) { + + /* On gfxv9, the MQD resides in the first 4K page, + * followed by the control stack. Align both to + * AMDGPU_GPU_PAGE_SIZE to maintain the required 4K boundary. + */ + + return ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + + ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE); + } return mm->mqd_size; } @@ -59,6 +66,49 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) return (struct v9_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t rptr_hi, wptr_hi; + struct v9_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + rptr_hi = m->sdmax_rlcx_rb_rptr_hi; + wptr_hi = m->sdmax_rlcx_rb_wptr_hi; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("rptr_hi=%d, wptr_hi=%d\n", rptr_hi, wptr_hi); + + return (rptr != wptr || rptr_hi != wptr_hi); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct v9_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr_lo % q->properties.queue_size; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo, uint32_t inst) { @@ -106,13 +156,27 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct v9_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, +static bool mqd_on_vram(struct amdgpu_device *adev) +{ + if (adev->apu_prefer_gtt) + return false; + + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 5, 0): + return true; + default: + return false; + } +} + +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { int retval; + struct kfd_node *node = mm->dev; struct kfd_mem_obj *mqd_mem_obj = NULL; /* For V9 only, due to a HW bug, the control stack of a user mode @@ -135,13 +199,15 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); if (!mqd_mem_obj) return NULL; - retval = amdgpu_amdkfd_alloc_gtt_mem(node->adev, - (ALIGN(q->ctl_stack_size, PAGE_SIZE) + - ALIGN(sizeof(struct v9_mqd), PAGE_SIZE)) * + retval = amdgpu_amdkfd_alloc_kernel_mem(node->adev, + (ALIGN(ALIGN(q->ctl_stack_size, AMDGPU_GPU_PAGE_SIZE) + + ALIGN(sizeof(struct v9_mqd), AMDGPU_GPU_PAGE_SIZE), PAGE_SIZE)) * NUM_XCC(node->xcc_mask), - &(mqd_mem_obj->gtt_mem), + mqd_on_vram(node->adev) ? AMDGPU_GEM_DOMAIN_VRAM : + AMDGPU_GEM_DOMAIN_GTT, + &(mqd_mem_obj->mem), &(mqd_mem_obj->gpu_addr), - (void *)&(mqd_mem_obj->cpu_ptr), true); + (void *)&(mqd_mem_obj->cpu_ptr), true, true); if (retval) { kfree(mqd_mem_obj); @@ -204,10 +270,9 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_aql_control = 1 << CP_HQD_AQL_CONTROL__CONTROL0__SHIFT; - if (q->tba_addr) { + if (q->tba_addr) m->compute_pgm_rsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT); - } if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) { m->cp_hqd_persistent_state |= @@ -222,6 +287,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -301,9 +371,19 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_doorbell_control |= 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; } + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 4) && KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 5, 0)) @@ -343,7 +423,7 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, struct kfd_context_save_area_header header; /* Control stack is located one page after MQD. */ - void *mqd_ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); + void *mqd_ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); m = get_mqd(mqd); @@ -369,18 +449,21 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, return 0; } -static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) +static int get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) { struct v9_mqd *m = get_mqd(mqd); - *ctl_stack_size = m->cp_hqd_cntl_stack_size * NUM_XCC(mm->dev->xcc_mask); + if (check_mul_overflow(m->cp_hqd_cntl_stack_size, NUM_XCC(mm->dev->xcc_mask), ctl_stack_size)) + return -EINVAL; + + return 0; } static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) { struct v9_mqd *m; /* Control stack is located one page after MQD. */ - void *ctl_stack = (void *)((uintptr_t)mqd + PAGE_SIZE); + void *ctl_stack = (void *)((uintptr_t)mqd + AMDGPU_GPU_PAGE_SIZE); m = get_mqd(mqd); @@ -426,7 +509,7 @@ static void restore_mqd(struct mqd_manager *mm, void **mqd, *gart_addr = addr; /* Control stack is located one page after MQD. */ - ctl_stack = (void *)((uintptr_t)*mqd + PAGE_SIZE); + ctl_stack = (void *)((uintptr_t)*mqd + AMDGPU_GPU_PAGE_SIZE); memcpy(ctl_stack, ctl_stack_src, ctl_stack_size); m->cp_hqd_pq_doorbell_control = @@ -596,7 +679,7 @@ static int hiq_load_mqd_kiq_v9_4_3(struct mqd_manager *mm, void *mqd, struct queue_properties *p, struct mm_struct *mms) { uint32_t xcc_mask = mm->dev->xcc_mask; - int xcc_id, err, inst = 0; + int xcc_id, err = 0, inst = 0; void *xcc_mqd; uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); @@ -620,7 +703,7 @@ static int destroy_hiq_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id) { uint32_t xcc_mask = mm->dev->xcc_mask; - int xcc_id, err, inst = 0; + int xcc_id, err = 0, inst = 0; uint64_t hiq_mqd_size = kfd_hiq_mqd_stride(mm->dev); struct v9_mqd *m; u32 doorbell_off; @@ -665,8 +748,8 @@ static void get_xcc_mqd(struct kfd_mem_obj *mqd_mem_obj, struct kfd_mem_obj *xcc_mqd_mem_obj, uint64_t offset) { - xcc_mqd_mem_obj->gtt_mem = (offset == 0) ? - mqd_mem_obj->gtt_mem : NULL; + xcc_mqd_mem_obj->mem = (offset == 0) ? + mqd_mem_obj->mem : NULL; xcc_mqd_mem_obj->gpu_addr = mqd_mem_obj->gpu_addr + offset; xcc_mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t)mqd_mem_obj->cpu_ptr + offset); @@ -738,6 +821,9 @@ static void init_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, *gart_addr = xcc_gart_addr; } } + + if (mqd_on_vram(mm->dev->adev)) + amdgpu_device_flush_hdp(mm->dev->adev, NULL); } static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, @@ -774,6 +860,9 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, m->pm4_target_xcc_in_xcp = q->pm4_target_xcc; } } + + if (mqd_on_vram(mm->dev->adev)) + amdgpu_device_flush_hdp(mm->dev->adev, NULL); } static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, @@ -812,13 +901,16 @@ static void restore_mqd_v9_4_3(struct mqd_manager *mm, void **mqd, (uint8_t *)ctl_stack_src + xcc * mqd_ctl_stack_size, mqd_ctl_stack_size); } + + if (mqd_on_vram(mm->dev->adev)) + amdgpu_device_flush_hdp(mm->dev->adev, NULL); } static int destroy_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, enum kfd_preempt_type type, unsigned int timeout, uint32_t pipe_id, uint32_t queue_id) { uint32_t xcc_mask = mm->dev->xcc_mask; - int xcc_id, err, inst = 0; + int xcc_id, err = 0, inst = 0; void *xcc_mqd; struct v9_mqd *m; uint64_t mqd_offset; @@ -848,7 +940,7 @@ static int load_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */ uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0); uint32_t xcc_mask = mm->dev->xcc_mask; - int xcc_id, err, inst = 0; + int xcc_id, err = 0, inst = 0; void *xcc_mqd; uint64_t mqd_stride_size = mm->mqd_stride(mm, p); @@ -945,6 +1037,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->allocate_mqd = allocate_mqd; mqd->free_mqd = kfd_free_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = mqd_stride_v9; @@ -976,6 +1069,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->free_mqd = free_mqd_hiq_sdma; mqd->update_mqd = update_mqd; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -1004,6 +1098,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; @@ -1017,6 +1112,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct v9_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index c1fafc5025158..cdc762c30f8a2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -45,6 +45,45 @@ static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) return (struct vi_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct vi_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct vi_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -73,12 +112,12 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, static void set_priority(struct vi_mqd *m, struct queue_properties *q) { m->cp_hqd_pipe_priority = pipe_priority_map[q->priority]; - m->cp_hqd_queue_priority = q->priority; } -static struct kfd_mem_obj *allocate_mqd(struct kfd_node *kfd, +static struct kfd_mem_obj *allocate_mqd(struct mqd_manager *mm, struct queue_properties *q) { + struct kfd_node *kfd = mm->dev; struct kfd_mem_obj *mqd_mem_obj; if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd), @@ -148,6 +187,11 @@ static void init_mqd(struct mqd_manager *mm, void **mqd, m->cp_hqd_wg_state_offset = q->ctl_stack_size; } + mutex_lock(&mm->dev->kfd->profiler_lock); + if (mm->dev->kfd->profiler_process != NULL) + m->compute_perfcount_enable = 1; + mutex_unlock(&mm->dev->kfd->profiler_lock); + *mqd = m; if (gart_addr) *gart_addr = addr; @@ -225,11 +269,19 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } - + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT; + if (minfo) { + if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_ENABLE) + m->compute_perfcount_enable = 1; + else if (minfo->update_flag == UPDATE_FLAG_PERFCOUNT_DISABLE) + m->compute_perfcount_enable = 0; + } update_cu_mask(mm, mqd, minfo); set_priority(m, q); @@ -274,10 +326,11 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, return 0; } -static void get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) +static int get_checkpoint_info(struct mqd_manager *mm, void *mqd, u32 *ctl_stack_size) { /* Control stack is stored in user mode */ *ctl_stack_size = 0; + return 0; } static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) @@ -461,6 +514,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; mqd->get_wave_state = get_wave_state; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; @@ -477,6 +531,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -492,6 +547,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -506,6 +562,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct vi_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c index 505036968a775..3d2375817c3e5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c @@ -252,10 +252,6 @@ static int pm_map_queues_v9(struct packet_manager *pm, uint32_t *buffer, packet->bitfields2.queue_type = queue_type__mes_map_queues__normal_latency_static_queue_vi; break; - case KFD_QUEUE_TYPE_DIQ: - packet->bitfields2.queue_type = - queue_type__mes_map_queues__debug_interface_queue_vi; - break; case KFD_QUEUE_TYPE_SDMA: case KFD_QUEUE_TYPE_SDMA_XGMI: if (q->properties.sdma_engine_id < 2 && diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c index a1de5d7e173a0..1f0b8ef7c9663 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_vi.c @@ -166,15 +166,10 @@ static int pm_map_queues_vi(struct packet_manager *pm, uint32_t *buffer, packet->bitfields2.queue_type = queue_type__mes_map_queues__normal_latency_static_queue_vi; break; - case KFD_QUEUE_TYPE_DIQ: - packet->bitfields2.queue_type = - queue_type__mes_map_queues__debug_interface_queue_vi; - break; case KFD_QUEUE_TYPE_SDMA: case KFD_QUEUE_TYPE_SDMA_XGMI: packet->bitfields2.engine_sel = q->properties.sdma_engine_id + engine_sel__mes_map_queues__sdma0_vi; - use_static = false; /* no static queues under SDMA */ break; default: WARN(1, "queue type %d", q->properties.type); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c new file mode 100644 index 0000000000000..94f67a8c240ec --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "kfd_pc_sampling.h" +#include "kfd_debug.h" +#include "kfd_device_queue_manager.h" + +#include +/* + * PC Sampling revision change log + * + * 0.1 - Initial revision + * 0.2 - Support gfx9_4_3 Host Trap PC sampling + * 0.3 - Fix gfx9_4_3 SQ hang issue + * 1.1 - Support gfx9_4_3 Stochastic PC sampling + * 1.2 - Support gfx9_5_0 Host Trap PC sampling + * 1.3 - Update 1st level trap handler for Stochastic PC sampling + * 1.4 - Support gfx9_5_0 Stochastic PC sampling + * 1.5 - Support gfx12_0_0 and gfx12_0_1 Host Trap PC sampling + * 1.6 - Increase gfx12_0_0 and gfx12_0_1 Host Trap PC sampling lower bound + * 1.7 - Support gfx9_4_4 Host Trap PC sampling/Stochastic PC sampling + */ +#define KFD_IOCTL_PCS_MAJOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 7 + +struct supported_pc_sample_info { + uint32_t ip_version; + const struct kfd_pc_sample_info *sample_info; +}; + +const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { + 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; + +const struct kfd_pc_sample_info sample_info_hosttrap_12_0_0 = { + 0, 512, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; + +const struct kfd_pc_sample_info sample_info_stoch_cycle_9_4_3 = { + 0, 256, (1ULL << 31), KFD_IOCTL_PCS_FLAG_POWER_OF_2, + KFD_IOCTL_PCS_METHOD_STOCHASTIC, KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES }; + +struct supported_pc_sample_info supported_formats[] = { + { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(9, 4, 4), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 4), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(9, 5, 0), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 5, 0), &sample_info_stoch_cycle_9_4_3 }, + { IP_VERSION(12, 0, 0), &sample_info_hosttrap_12_0_0 }, + { IP_VERSION(12, 0, 1), &sample_info_hosttrap_12_0_0 }, +}; + +static int kfd_pc_sample_thread(void *param) +{ + struct amdgpu_device *adev; + struct kfd_node *node = param; + uint32_t timeout = 0; + ktime_t next_trap_time; + bool need_wait; + uint32_t inst; + + mutex_lock(&node->pcs_data.mutex); + if (node->pcs_data.hosttrap_entry.base.active_count && + node->pcs_data.hosttrap_entry.base.pc_sample_info.interval && + node->kfd2kgd->trigger_pc_sample_trap) { + switch (node->pcs_data.hosttrap_entry.base.pc_sample_info.type) { + case KFD_IOCTL_PCS_TYPE_TIME_US: + timeout = (uint32_t)node->pcs_data.hosttrap_entry.base.pc_sample_info.interval; + break; + default: + pr_debug("PC Sampling type %d not supported.", + node->pcs_data.hosttrap_entry.base.pc_sample_info.type); + } + } + mutex_unlock(&node->pcs_data.mutex); + if (!timeout) + return -EINVAL; + + adev = node->adev; + need_wait = false; + allow_signal(SIGKILL); + + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 1, inst); + + while (!kthread_should_stop() && + !signal_pending(node->pcs_data.hosttrap_entry.pc_sample_thread)) { + if (!need_wait) { + next_trap_time = ktime_add_us(ktime_get_raw(), timeout); + + for_each_inst(inst, node->xcc_mask) { + node->kfd2kgd->trigger_pc_sample_trap(adev, node->vm_info.last_vmid_kfd, + &node->pcs_data.hosttrap_entry.target_simd, + &node->pcs_data.hosttrap_entry.target_wave_slot, + node->pcs_data.hosttrap_entry.base.pc_sample_info.method, + inst); + } + pr_debug_ratelimited("triggered a host trap."); + need_wait = true; + } else { + ktime_t wait_time; + s64 wait_ns, wait_us; + + wait_time = ktime_sub(next_trap_time, ktime_get_raw()); + wait_ns = ktime_to_ns(wait_time); + wait_us = ktime_to_us(wait_time); + if (wait_ns >= 10000) { + usleep_range(wait_us - 10, wait_us); + } else { + schedule(); + if (wait_ns <= 0) + need_wait = false; + } + } + } + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 0, inst); + + node->pcs_data.hosttrap_entry.target_simd = 0; + node->pcs_data.hosttrap_entry.target_wave_slot = 0; + node->pcs_data.hosttrap_entry.pc_sample_thread = NULL; + + return 0; +} + +static int kfd_pc_sample_thread_start(struct kfd_node *node) +{ + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "pcs_%d", node->adev->ddev.render->index); + node->pcs_data.hosttrap_entry.pc_sample_thread = + kthread_run(kfd_pc_sample_thread, node, thread_name); + + if (IS_ERR(node->pcs_data.hosttrap_entry.pc_sample_thread)) { + ret = PTR_ERR(node->pcs_data.hosttrap_entry.pc_sample_thread); + node->pcs_data.hosttrap_entry.pc_sample_thread = NULL; + pr_debug("Failed to create pc sample thread for %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + +static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + uint64_t sample_offset; + int num_method = 0; + int ret; + int i; + const uint32_t user_num_sample_info = user_args->num_sample_info; + + /* use version field to pass back pc sampling revision temporarily, not for upstream */ + user_args->version = KFD_IOCTL_PCS_MAJOR_VERSION << 16 | KFD_IOCTL_PCS_MINOR_VERSION; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) + num_method++; + + if (!num_method) { + pr_debug("PC Sampling not supported on GC_HWIP:0x%x.", + pdd->dev->adev->ip_versions[GC_HWIP][0]); + return -EOPNOTSUPP; + } + + ret = 0; + mutex_lock(&pdd->dev->pcs_data.mutex); + if (user_args->flags != KFD_IOCTL_PCS_QUERY_TYPE_FULL && + (pdd->dev->pcs_data.hosttrap_entry.base.use_count || + pdd->dev->pcs_data.stoch_entry.base.use_count)) { + user_args->num_sample_info = 0; + + /* If we already have a session, restrict returned list to current method */ + if (pdd->dev->pcs_data.stoch_entry.base.use_count) { + user_args->num_sample_info++; + if (user_args->sample_info_ptr && + user_args->num_sample_info <= user_num_sample_info) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + user_args->sample_info_ptr += sizeof(struct kfd_pc_sample_info); + } + } + + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + user_args->num_sample_info++; + if (user_args->sample_info_ptr && + user_args->num_sample_info <= user_num_sample_info) + ret |= copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : 0; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + + user_args->num_sample_info = num_method; + + if (!user_args->sample_info_ptr || !user_num_sample_info) { + /* + * User application is querying the size of buffer needed. Application will + * allocate required buffer size and send a second query. + */ + return 0; + } else if (user_num_sample_info < num_method) { + pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); + return -ENOSPC; + } + + sample_offset = user_args->sample_info_ptr; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) { + ret = copy_to_user((void __user *) sample_offset, + supported_formats[i].sample_info, sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info to user."); + return -EFAULT; + } + sample_offset += sizeof(struct kfd_pc_sample_info); + } + } + + return 0; +} + +static int kfd_pc_sample_start(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) +{ + bool pc_sampling_start = false; + int ret = 0; + + pcs_entry->enabled = true; + mutex_lock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, true); + + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_start = true; + + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + if (!pdd->dev->pcs_data.stoch_entry.base.active_count) + pc_sampling_start = true; + + pdd->dev->pcs_data.stoch_entry.base.active_count++; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + + while (pc_sampling_start) { + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + /* true means pc_sample_thread stop is in progress */ + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread)) { + usleep_range(1000, 2000); + } else { + ret = kfd_pc_sample_thread_start(pdd->dev); + break; + } + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + struct amdgpu_device *adev = pdd->dev->adev; + struct kfd_node *node = pdd->dev; + uint64_t interval; + uint32_t inst; + + interval = node->pcs_data.stoch_entry.base.pc_sample_info.interval; + if (pdd->dev->kfd2kgd->setup_stoch_sampling) + for_each_inst(inst, node->xcc_mask) + pdd->dev->kfd2kgd->setup_stoch_sampling(adev, + node->compute_vmid_bitmap, true, + node->pcs_data.stoch_entry.base.pc_sample_info.type, + interval, + inst); + break; + } + } + return ret; +} + +static int kfd_pc_sample_stop(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) +{ + bool pc_sampling_stop = false; + + pcs_entry->enabled = false; + mutex_lock(&pdd->dev->pcs_data.mutex); + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + pdd->dev->pcs_data.hosttrap_entry.base.active_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_stop = true; + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + pdd->dev->pcs_data.stoch_entry.base.active_count--; + if (!pdd->dev->pcs_data.stoch_entry.base.active_count) + pc_sampling_stop = true; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pcs_entry->method, false); + remap_queue(pdd->dev->dqm, + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0); + + if (pc_sampling_stop) { + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.pc_sample_thread); + } else {/* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + struct amdgpu_device *adev = pdd->dev->adev; + struct kfd_node *node = pdd->dev; + uint32_t inst; + + if (pdd->dev->kfd2kgd->setup_stoch_sampling) { + for_each_inst(inst, node->xcc_mask) + pdd->dev->kfd2kgd->setup_stoch_sampling(adev, + node->compute_vmid_bitmap, false, + node->pcs_data.stoch_entry.base.pc_sample_info.type, + 0, inst); + } + } + } + + return 0; +} + +static int kfd_pc_sample_create(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + struct kfd_pc_sample_info *supported_format = NULL; + struct kfd_pc_sample_info user_info; + struct pc_sampling_entry *pcs_entry; + int ret; + int i; + + if (user_args->num_sample_info != 1) + return -EINVAL; + + ret = copy_from_user(&user_info, (void __user *) user_args->sample_info_ptr, + sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info from user\n"); + return -EFAULT; + } + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version + && user_info.method == supported_formats[i].sample_info->method + && user_info.type == supported_formats[i].sample_info->type + && user_info.interval <= supported_formats[i].sample_info->interval_max + && user_info.interval >= supported_formats[i].sample_info->interval_min) { + supported_format = + (struct kfd_pc_sample_info *)supported_formats[i].sample_info; + break; + } + } + + if (!supported_format) { + pr_debug("Sampling format is not supported!"); + return -EOPNOTSUPP; + } + + if (supported_format->flags == KFD_IOCTL_PCS_FLAG_POWER_OF_2 && + user_info.interval & (user_info.interval - 1)) { + pr_debug("Sampling interval's power is unmatched!"); + return -EINVAL; + } + + mutex_lock(&pdd->dev->pcs_data.mutex); + if (supported_format->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + if (pdd->dev->pcs_data.stoch_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + } + + pcs_entry = kzalloc(sizeof(*pcs_entry), GFP_KERNEL); + if (!pcs_entry) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + return -ENOMEM; + } + + i = idr_alloc_cyclic(&pdd->dev->pcs_data.sampling_idr, + pcs_entry, 1, 0, GFP_KERNEL); + if (i < 0) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + kfree(pcs_entry); + return i; + } + + if (supported_format->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + pdd->dev->pcs_data.hosttrap_entry.base.use_count++; + } else if (supported_format->method == KFD_IOCTL_PCS_METHOD_STOCHASTIC) { + if (!pdd->dev->pcs_data.stoch_entry.base.use_count) + pdd->dev->pcs_data.stoch_entry.base.pc_sample_info = user_info; + pdd->dev->pcs_data.stoch_entry.base.use_count++; + } + + mutex_unlock(&pdd->dev->pcs_data.mutex); + + pcs_entry->pdd = pdd; + pcs_entry->method = supported_format->method; + user_args->trace_id = (uint32_t)i; + + /* + * Set SPI_GDBG_PER_VMID_CNTL.TRAP_EN so that TTMP registers are valid in the sampling data + * p->runtime_info.ttmp_setup will be cleared when user application calls runtime_disable + * on exit. + */ + kfd_dbg_enable_ttmp_setup(pdd->process); + pdd->process->pc_sampling_ref++; + + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x method = %d on gpu 0x%x", + pcs_entry, i, pcs_entry->method, pdd->dev->id); + + return 0; +} + +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id, + struct pc_sampling_entry *pcs_entry) +{ + pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", + pcs_entry, trace_id, pdd->dev->id); + + pdd->process->pc_sampling_ref--; + mutex_lock(&pdd->dev->pcs_data.mutex); + if (pcs_entry->method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + pdd->dev->pcs_data.hosttrap_entry.base.use_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + } else { /* KFD_IOCTL_PCS_METHOD_STOCHASTIC */ + pdd->dev->pcs_data.stoch_entry.base.use_count--; + if (!pdd->dev->pcs_data.stoch_entry.base.use_count) + memset(&pdd->dev->pcs_data.stoch_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + } + + idr_remove(&pdd->dev->pcs_data.sampling_idr, trace_id); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfree(pcs_entry); + + return 0; +} + +void kfd_pc_sample_release(struct kfd_process_device *pdd) +{ + struct pc_sampling_entry *pcs_entry; + struct idr *idp; + uint32_t id; + + /* force to release all PC sampling task for this process */ + idp = &pdd->dev->pcs_data.sampling_idr; + do { + pcs_entry = NULL; + mutex_lock(&pdd->dev->pcs_data.mutex); + idr_for_each_entry(idp, pcs_entry, id) { + if (pcs_entry->pdd != pdd) + continue; + break; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + if (pcs_entry) { + if (pcs_entry->enabled) + kfd_pc_sample_stop(pdd, pcs_entry); + kfd_pc_sample_destroy(pdd, id, pcs_entry); + } + } while (pcs_entry); +} + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args) +{ + struct pc_sampling_entry *pcs_entry; + + if (args->op != KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES && + args->op != KFD_IOCTL_PCS_OP_CREATE) { + + mutex_lock(&pdd->dev->pcs_data.mutex); + pcs_entry = idr_find(&pdd->dev->pcs_data.sampling_idr, + args->trace_id); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + /* pcs_entry is only for this pc sampling process, + * which has kfd_process->mutex protected here. + */ + if (!pcs_entry || + pcs_entry->pdd != pdd) + return -EINVAL; + } else if (pdd->process->debug_trap_enabled) { + pr_debug("Cannot have PC Sampling and debug trap simultaneously"); + return -EBUSY; + } + + switch (args->op) { + case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: + return kfd_pc_sample_query_cap(pdd, args); + + case KFD_IOCTL_PCS_OP_CREATE: + return kfd_pc_sample_create(pdd, args); + + case KFD_IOCTL_PCS_OP_DESTROY: + if (pcs_entry->enabled) + return -EBUSY; + else + return kfd_pc_sample_destroy(pdd, args->trace_id, pcs_entry); + + case KFD_IOCTL_PCS_OP_START: + if (pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_start(pdd, pcs_entry); + + case KFD_IOCTL_PCS_OP_STOP: + if (!pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_stop(pdd, pcs_entry); + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h new file mode 100644 index 0000000000000..6175563ca9bea --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_PC_SAMPLING_H_ +#define KFD_PC_SAMPLING_H_ + +#include "amdgpu.h" +#include "kfd_priv.h" + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args); +void kfd_pc_sample_release(struct kfd_process_device *pdd); + +#endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c new file mode 100644 index 0000000000000..34ddd3c48b95b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -0,0 +1,744 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/* NOTE: + * + * This file contains logic to dynamically detect and enable PeerDirect + * suppor. PeerDirect support is delivered e.g. as part of OFED + * from Mellanox. Because we are not able to rely on the fact that the + * corresponding OFED will be installed we should: + * - copy PeerDirect definitions locally to avoid dependency on + * corresponding header file + * - try dynamically detect address of PeerDirect function + * pointers. + * + * If dynamic detection failed then PeerDirect support should be + * enabled using the standard PeerDirect bridge driver from: + * https://github.com/RadeonOpenCompute/ROCnRDMA + * + * + * Logic to support PeerDirect relies only on official public API to be + * non-intrusive as much as possible. + * + **/ + +#include +#include +#include +#include +#include +#include + +#include "kfd_priv.h" + +/* ----------------------- PeerDirect interface ------------------------------*/ + +/* + * Copyright (c) 2013, Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#define IB_PEER_MEMORY_NAME_MAX 64 +#define IB_PEER_MEMORY_VER_MAX 16 +struct peer_memory_client { + char name[IB_PEER_MEMORY_NAME_MAX]; + char version[IB_PEER_MEMORY_VER_MAX]; + /* acquire return code: 1-mine, 0-not mine */ + int (*acquire)(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, + void **client_context); + int (*get_pages)(unsigned long addr, + size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context); + int (*dma_map)(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap); + int (*dma_unmap)(struct sg_table *sg_head, void *client_context, + struct device *dma_device); + void (*put_pages)(struct sg_table *sg_head, void *client_context); + unsigned long (*get_page_size)(void *client_context); + void (*release)(void *client_context); + void* (*get_context_private_data)(u64 peer_id); + void (*put_context_private_data)(void *context); +}; + +typedef int (*invalidate_peer_memory)(void *reg_handle, + void *core_context); + +void *ib_register_peer_memory_client(struct peer_memory_client *peer_client, + invalidate_peer_memory *invalidate_callback); +void ib_unregister_peer_memory_client(void *reg_handle); + +/*------------------- PeerDirect bridge driver ------------------------------*/ + +#define AMD_PEER_BRIDGE_DRIVER_VERSION "1.0" +#define AMD_PEER_BRIDGE_DRIVER_NAME "amdkfd" + +static char rdma_name[] = "AMD RDMA"; + + +static void* (*pfn_ib_register_peer_memory_client)(struct peer_memory_client + *peer_client, + invalidate_peer_memory + *invalidate_callback); + +static void (*pfn_ib_unregister_peer_memory_client)(void *reg_handle); + +static void *ib_reg_handle; + +struct amd_mem_context { + uint64_t va; + uint64_t size; + unsigned long offset; + struct amdgpu_bo *bo; + struct kfd_node *dev; + + struct sg_table *pages; + struct device *dma_dev; + + + /* Context received from PeerDirect call */ + void *core_context; + + pid_t pid; + uint32_t flags; +}; + +/* Workaround: Mellanox peerdirect driver expects sg lists at + * page granularity. This causes failures when an application tries + * to register size < PAGE_SIZE or addr starts at some offset. Fix + * it by aligning the size to page size and addr to page boundary. + */ +static void align_addr_size(unsigned long *addr, size_t *size) +{ + unsigned long end = ALIGN(*addr + *size, PAGE_SIZE); + + *addr = ALIGN_DOWN(*addr, PAGE_SIZE); + *size = end - *addr; +} + +static int amd_acquire(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, void **client_context) +{ + struct kfd_process *p; + struct amd_mem_context *mem_context; + struct kfd_bo *buf_obj = NULL; + struct kfd_node *dev = NULL; + struct amdgpu_bo *bo = NULL; + unsigned long offset = 0; + uint32_t flags = 0; + + if (peer_mem_name == rdma_name) { + p = peer_mem_private_data; + kref_get(&p->ref); + } else { + p = kfd_lookup_process_by_mm(current->mm); + if (!p) { + pr_debug("Not a KFD process\n"); + return 0; + } + } + + align_addr_size(&addr, &size); + + mutex_lock(&p->mutex); + buf_obj = kfd_process_find_bo_from_interval(p, addr, addr + size - 1); + if (buf_obj) { + offset = addr - buf_obj->it.start; + bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, &flags); + + dev = buf_obj->dev; + } else { + struct vm_area_struct *vma; + struct amdgpu_device *adev; + + mmap_read_lock(p->mm); + vma = find_vma(p->mm, addr); + + if (!vma || + !amdgpu_vma_is_amdgpu_bo(vma) || + vma->vm_start > addr || + vma->vm_end < addr + size) { + mmap_read_unlock(p->mm); + goto out_unlock; + } + + bo = ttm_to_amdgpu_bo(vma->vm_private_data); + drm_gem_object_get(&bo->tbo.base); + mmap_read_unlock(p->mm); + + offset = addr - vma->vm_start; + + flags = bo->kfd_bo->alloc_flags; + adev = amdgpu_ttm_adev(bo->tbo.bdev); + dev = adev->kfd.dev->nodes[bo->xcp_id]; + } + + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (unlikely(!mem_context)) { + drm_gem_object_put(&bo->tbo.base); + goto out_unlock; + } + + mutex_unlock(&p->mutex); + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", addr, size, mem_context->pid); + + mem_context->pid = p->lead_thread->pid; + mem_context->va = addr; + mem_context->size = size; + mem_context->dev = dev; + mem_context->offset = offset; + mem_context->bo = bo; + mem_context->flags = flags; + + /* Return pointer to allocated context */ + *client_context = mem_context; + + kfd_unref_process(p); + + /* Return 1 to inform that this address which will be handled + * by AMD GPU driver + */ + return 1; +out_unlock: + mutex_unlock(&p->mutex); + kfd_unref_process(p); + + return 0; +} + +static int amd_get_pages(unsigned long addr, size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context) +{ + int ret; + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + align_addr_size(&addr, &size); + + pr_debug("addr: %#lx, size: %#lx, core_context: 0x%p\n", + addr, size, core_context); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d\n", mem_context->pid); + + if (addr != mem_context->va) { + pr_warn("Context address (%#llx) is not the same\n", + mem_context->va); + return -EINVAL; + } + + if (size != mem_context->size) { + pr_warn("Context size (%#llx) is not the same\n", + mem_context->size); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo, + mem_context->bo->kfd_bo->domain); + if (ret) { + pr_err("Pinning of buffer failed.\n"); + return ret; + } + + /* Mark the device as active */ + kfd_inc_compute_active(mem_context->dev); + + mem_context->core_context = core_context; + + return 0; +} + + +static int amd_dma_map(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap) +{ + struct sg_table *sg_table_tmp; + struct scatterlist *sg; + int ret; + int i; + + /* + * NOTE/TODO: + * We could have potentially three cases for real memory + * location: + * - all memory in the local + * - all memory in the system (RAM) + * - memory is spread (s/g) between local and system. + * + * In the case of all memory in the system we could use + * iommu driver to build DMA addresses but not in the case + * of local memory because currently iommu driver doesn't + * deal with local/device memory addresses (it requires "struct + * page"). + * + * Accordingly returning assumes that iommu funcutionality + * should be disabled so we can assume that sg_table already + * contains DMA addresses. + * + */ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Build sg_table for buffer being exported, including DMA mapping */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table( + mem_context->dev->adev, mem_context->bo, mem_context->flags, + mem_context->offset, mem_context->size, + dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); + if (ret) { + pr_err("Building of sg_table failed\n"); + return ret; + } + + pr_debug("size 0x%llx nents %d\n", mem_context->size, sg_table_tmp->nents); + for_each_sgtable_sg(sg_table_tmp, sg, i) + pr_debug("segment_%d dma_address 0x%llx length 0x%x dma_length 0x%x\n", + i, sg->dma_address, sg->length, sg->dma_length); + + /* Maintain a copy of the handle to sg_table */ + mem_context->pages = sg_table_tmp; + mem_context->dma_dev = dma_device; + + /* Copy information about previosly allocated sg_table */ + *sg_head = *mem_context->pages; + + /* Return number of sg table segments */ + *nmap = mem_context->pages->nents; + + return ret; +} + +static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, + struct device *dma_device) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_table: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Release the mapped pages of buffer */ + amdgpu_amdkfd_gpuvm_put_sg_table(mem_context->bo, + mem_context->dma_dev, + DMA_BIDIRECTIONAL, + mem_context->pages); + mem_context->pages = NULL; + + return 0; +} + +static void amd_put_pages(struct sg_table *sg_head, void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_unpin_bo(mem_context->bo); + kfd_dec_compute_active(mem_context->dev); +} + +static unsigned long amd_get_page_size(void *client_context) +{ + return PAGE_SIZE; +} + +static void amd_release(void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p\n", client_context); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_put_bo_ref(mem_context->bo); + + kfree(mem_context); +} + + +static struct peer_memory_client amd_mem_client = { + .acquire = amd_acquire, + .get_pages = amd_get_pages, + .dma_map = amd_dma_map, + .dma_unmap = amd_dma_unmap, + .put_pages = amd_put_pages, + .get_page_size = amd_get_page_size, + .release = amd_release, + .get_context_private_data = NULL, + .put_context_private_data = NULL, +}; + +/** Initialize PeerDirect interface with RDMA Network stack. + * + * Because network stack could potentially be loaded later we check + * presence of PeerDirect when HSA process is created. If PeerDirect was + * already initialized we do nothing otherwise try to detect and register. + */ +void kfd_init_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect support was already initialized\n"); + return; + } + + pr_debug("Try to initialize PeerDirect support\n"); + +#if defined(HAVE_KFD_PEERDIRECT_SUPPORT) + pfn_ib_register_peer_memory_client = ib_register_peer_memory_client; + pfn_ib_unregister_peer_memory_client = ib_unregister_peer_memory_client; +#else + pfn_ib_register_peer_memory_client = + (void *(*)(struct peer_memory_client *, + invalidate_peer_memory *)) + symbol_request(ib_register_peer_memory_client); + + pfn_ib_unregister_peer_memory_client = (void (*)(void *)) + symbol_request(ib_unregister_peer_memory_client); + +#endif + if (!pfn_ib_register_peer_memory_client || + !pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect interface was not detected\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + strcpy(amd_mem_client.name, AMD_PEER_BRIDGE_DRIVER_NAME); + strcpy(amd_mem_client.version, AMD_PEER_BRIDGE_DRIVER_VERSION); + + ib_reg_handle = pfn_ib_register_peer_memory_client(&amd_mem_client, NULL); + + if (!ib_reg_handle) { + pr_err("Cannot register peer memory client\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + pr_info("PeerDirect support was initialized successfully\n"); +} + +/** + * Close connection with PeerDirect interface with RDMA Network stack. + * + */ +void kfd_close_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + if (ib_reg_handle) + pfn_ib_unregister_peer_memory_client(ib_reg_handle); +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) + symbol_put(ib_unregister_peer_memory_client); +#endif + } + +#if !defined(HAVE_KFD_PEERDIRECT_SUPPORT) + if (pfn_ib_register_peer_memory_client) + symbol_put(ib_register_peer_memory_client); +#endif + + /* Reset pointers to be safe */ + pfn_ib_unregister_peer_memory_client = NULL; + pfn_ib_register_peer_memory_client = NULL; + ib_reg_handle = NULL; +} + +/* ------------------------- AMD RDMA wrapper --------------------------------*/ + +#include "drm/amd_rdma.h" + +struct rdma_p2p_data { + struct amd_p2p_info p2p_info; + void (*free_callback)(void *client_priv); + void *client_priv; +}; + +/** + * This function makes the pages underlying a range of GPU virtual memory + * accessible for DMA operations from another PCIe device + * + * \param address - The start address in the Unified Virtual Address + * space in the specified process + * \param length - The length of requested mapping + * \param pid - Pointer to structure pid to which address belongs. + * Could be NULL for current process address space. + * \param p2p_data - On return: Pointer to structure describing + * underlying pages/locations + * \param free_callback - Pointer to callback which will be called when access + * to such memory must be stopped immediately: Memory + * was freed, GECC events, etc. + * Client should immediately stop any transfer + * operations and returned as soon as possible. + * After return all resources associated with address + * will be release and no access will be allowed. + * \param client_priv - Pointer to be passed as parameter on + * 'free_callback; + * + * \return 0 if operation was successful + */ +static int rdma_get_pages(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv) +{ + struct rdma_p2p_data *p2p_data; + struct kfd_process *p; + struct sg_table sg_head; + struct amd_mem_context *mem_context; + int nmap; + int r; + + p2p_data = kzalloc(sizeof(*p2p_data), GFP_KERNEL); + if (!p2p_data) + return -ENOMEM; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("pid lookup failed\n"); + r = -ESRCH; + goto err_lookup_process; + } + + r = amd_acquire(address, length, p, rdma_name, (void **)&mem_context); + kfd_unref_process(p); + if (r == 0) { + pr_debug("acquire failed: %d\n", r); + r = -EINVAL; + goto err_acquire; + } + + r = amd_get_pages(address, length, 1, 0, &sg_head, + mem_context, p2p_data); + if (r) { + pr_debug("get_pages failed: %d\n", r); + goto err_get_pages; + } + + r = amd_dma_map(&sg_head, mem_context, dma_dev, 0, &nmap); + if (r) { + pr_debug("dma_map failed: %d\n", r); + goto err_dma_map; + } + + + p2p_data->free_callback = free_callback; + p2p_data->client_priv = client_priv; + p2p_data->p2p_info.va = address; + p2p_data->p2p_info.size = length; + p2p_data->p2p_info.pid = pid; + p2p_data->p2p_info.pages = mem_context->pages; + p2p_data->p2p_info.priv = mem_context; + + *amd_p2p_data = &p2p_data->p2p_info; + + return 0; + +err_dma_map: + amd_put_pages(&sg_head, mem_context); +err_get_pages: + amd_release(mem_context); +err_acquire: +err_lookup_process: + kfree(p2p_data); + + return r; +} + +/** + * + * This function release resources previously allocated by get_pages() call. + * + * \param p_p2p_data - A pointer to pointer to amd_p2p_info entries + * allocated by get_pages() call. + * + * \return 0 if operation was successful + */ +static int rdma_put_pages(struct amd_p2p_info **p_p2p_data) +{ + struct rdma_p2p_data *p2p_data = + container_of(*p_p2p_data, struct rdma_p2p_data, p2p_info); + int r; + + r = amd_dma_unmap(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv, + NULL); + if (r) + return r; + amd_put_pages(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv); + amd_release(p2p_data->p2p_info.priv); + kfree(p2p_data); + + *p_p2p_data = NULL; + + return 0; +} + +/** + * Check if given address belongs to GPU address space. + * + * \param address - Address to check + * \param pid - Process to which given address belongs. + * Could be NULL if current one. + * + * \return 0 - This is not GPU address managed by AMD driver + * 1 - This is GPU address managed by AMD driver + */ +static int rdma_is_gpu_address(uint64_t address, struct pid *pid) +{ + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("Could not find the process\n"); + return 0; + } + + buf_obj = kfd_process_find_bo_from_interval(p, address, address); + + kfd_unref_process(p); + if (!buf_obj) + return 0; + + return 1; +} + +/** + * Return the single page size to be used when building scatter/gather table + * for given range. + * + * \param address - Address + * \param length - Range length + * \param pid - Process id structure. Could be NULL if current one. + * \param page_size - On return: Page size + * + * \return 0 if operation was successful + */ +static int rdma_get_page_size(uint64_t address, uint64_t length, + struct pid *pid, unsigned long *page_size) +{ + /* + * As local memory is always consecutive, we can assume the local + * memory page size to be arbitrary. + * Currently we assume the local memory page size to be the same + * as system memory, which is 4KB. + */ + *page_size = PAGE_SIZE; + + return 0; +} + +/** + * Singleton object: rdma interface function pointers + */ +static const struct amd_rdma_interface rdma_ops = { + .get_pages = rdma_get_pages, + .put_pages = rdma_put_pages, + .is_gpu_address = rdma_is_gpu_address, + .get_page_size = rdma_get_page_size +}; + +/** + * amdkfd_query_rdma_interface - Return interface (function pointers table) for + * rdma interface + * + * + * \param interace - OUT: Pointer to interface + * + * \return 0 if operation was successful. + */ +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **ops) +{ + *ops = &rdma_ops; + + return 0; +} +EXPORT_SYMBOL(amdkfd_query_rdma_interface); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 70ef051511bb1..8014cfec32d75 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -38,14 +38,19 @@ #include #include #include -#include +#include +#include +/* amdkcl: this header file is included in kcl_device_cgroup.h +#include */ #include #include #include #include #include #include +#include +#include "amdgpu_amdkfd.h" #include "amd_shared.h" #include "amdgpu.h" @@ -151,6 +156,19 @@ enum kfd_ioctl_flags { * we also allow ioctls with SYS_ADMIN capability. */ KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), + + /* + * @KFD_IOC_FLAG_PERFMON: + * Performance monitoring feature, GPU performance monitoring can allow users + * to gather some information about other processes. PC sampling can allow + * users to infer information about wavefronts from other processes that are + * running on the same CUs, such as which execution units they are using. As + * such, this type of performance monitoring should be protected and only + * available to users with sufficient capabilities: either CAP_PERFMON, or, + * for backwards compatibility, CAP_SYS_ADMIN. + */ + + KFD_IOC_FLAG_PERFMON = BIT(1), }; /* * Kernel module parameter to specify maximum number of supported queues per @@ -185,6 +203,11 @@ extern int debug_largebar; /* Set sh_mem_config.retry_disable on GFX v9 */ extern int amdgpu_noretry; +/* + * Enable privileged mode for all CP queues including user queues + */ +extern int priv_cp_queues; + /* Halt if HWS hang is detected */ extern int halt_if_hws_hang; @@ -199,6 +222,11 @@ extern int queue_preemption_timeout_ms; */ extern int amdgpu_no_queue_eviction_on_vm_fault; +/* + * Restore evicted process only if queues are active + */ +extern bool keep_idle_process_evicted; + /* Enable eviction debug messages */ extern bool debug_evictions; @@ -215,7 +243,8 @@ enum cache_policy { ((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) || \ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) || \ (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) || \ - (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0))) + (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) || \ + (KFD_GC_VERSION(dev) == IP_VERSION(12, 1, 0))) struct kfd_node; @@ -241,7 +270,6 @@ struct kfd_device_info { uint32_t no_atomic_fw_version; unsigned int num_sdma_queues_per_engine; unsigned int num_reserved_sdma_queues_per_engine; - DECLARE_BITMAP(reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES); }; unsigned int kfd_get_num_sdma_engines(struct kfd_node *kdev); @@ -252,7 +280,7 @@ struct kfd_mem_obj { uint32_t range_end; uint64_t gpu_addr; uint32_t *cpu_ptr; - void *gtt_mem; + void *mem; }; struct kfd_vmid_info { @@ -265,6 +293,31 @@ struct kfd_vmid_info { struct kfd_dev; +struct kfd_dev_pc_sampling_data { + uint32_t use_count; /* Num of PC sampling sessions */ + uint32_t active_count; /* Num of active sessions */ + struct kfd_pc_sample_info pc_sample_info; +}; + +struct kfd_dev_pcs_hosttrap { + struct kfd_dev_pc_sampling_data base; + uint32_t target_simd; /* target simd for trap */ + uint32_t target_wave_slot; /* target wave slot for trap */ + struct task_struct *pc_sample_thread; +}; + +struct kfd_dev_stochastic { + struct kfd_dev_pc_sampling_data base; +}; + +/* Per device PC Sampling data */ +struct kfd_dev_pc_sampling { + struct mutex mutex; + struct idr sampling_idr; + struct kfd_dev_pcs_hosttrap hosttrap_entry; + struct kfd_dev_stochastic stoch_entry; +}; + struct kfd_node { unsigned int node_id; struct amdgpu_device *adev; /* Duplicated here along with keeping @@ -307,6 +360,7 @@ struct kfd_node { /*spm process id */ unsigned int spm_pasid; + struct task_struct *spm_monitor_thread; /* Maximum process number mapped to HW scheduler */ unsigned int max_proc_per_quantum; @@ -320,6 +374,8 @@ struct kfd_node { /* Track per device allocated watch points */ uint32_t alloc_watch_ids; spinlock_t watch_points_lock; + + struct kfd_dev_pc_sampling pcs_data; }; struct kfd_dev { @@ -364,6 +420,9 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /*spm process id */ + unsigned int spm_pasid; + struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -384,6 +443,25 @@ struct kfd_dev { int kfd_dev_lock; atomic_t kfd_processes_count; + + /* Lock for profiler process */ + struct mutex profiler_lock; + /* Process currently holding the lock */ + struct kfd_process *profiler_process; + + /* flag for AIS */ + bool ais_initialized; +}; + +struct kfd_ipc_obj; + +struct kfd_bo { + void *mem; + struct interval_tree_node it; + struct kfd_node *dev; + /* page-aligned VA address */ + uint64_t cpuva; + unsigned int mem_type; }; enum kfd_mempool { @@ -434,7 +512,6 @@ enum kfd_queue_type { KFD_QUEUE_TYPE_COMPUTE, KFD_QUEUE_TYPE_SDMA, KFD_QUEUE_TYPE_HIQ, - KFD_QUEUE_TYPE_DIQ, KFD_QUEUE_TYPE_SDMA_XGMI, KFD_QUEUE_TYPE_SDMA_BY_ENG_ID }; @@ -507,7 +584,8 @@ struct queue_properties { enum kfd_queue_format format; unsigned int queue_id; uint64_t queue_address; - uint64_t queue_size; + uint64_t queue_size; + uint64_t metadata_queue_size; uint32_t priority; uint32_t queue_percent; void __user *read_ptr; @@ -556,6 +634,8 @@ enum mqd_update_flag { UPDATE_FLAG_DBG_WA_ENABLE = 1, UPDATE_FLAG_DBG_WA_DISABLE = 2, UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ + UPDATE_FLAG_PERFCOUNT_ENABLE = 5, + UPDATE_FLAG_PERFCOUNT_DISABLE = 6, }; struct mqd_update_info { @@ -621,6 +701,9 @@ struct queue { /* procfs */ struct kobject kobj; + struct attribute attr_gpuid; + struct attribute attr_size; + struct attribute attr_type; void *gang_ctx_bo; uint64_t gang_ctx_gpu_addr; @@ -698,6 +781,7 @@ struct qcm_process_device { uint32_t num_gws; uint32_t num_oac; uint32_t sh_hidden_private_base; + uint32_t vm_cntx_cntl; /* CWSR memory */ struct kgd_mem *cwsr_mem; @@ -716,6 +800,17 @@ struct qcm_process_device { /* bitmap for dynamic doorbell allocation from the bo */ unsigned long *doorbell_bitmap; + /* doorbell user mmap vma */ + struct vm_area_struct *doorbell_vma; + /* lock to serialize doorbell unmap and remap */ + struct mutex doorbell_lock; + + /* Indicate if doorbell is mapped or unmapped + * -1 means doorbells need to be unmapped because queue is evicted + * 0 means doorbells are unmapped + * 1 means doorbells are mapped + */ + int doorbell_mapped; }; /* KFD Memory Eviction */ @@ -727,6 +822,9 @@ struct qcm_process_device { /* Approx. time before evicting the process again */ #define PROCESS_ACTIVE_TIME_MS 10 +void kfd_process_schedule_restore(struct kfd_process *p); +int kfd_process_remap_doorbells_locked(struct kfd_process *p); + /* 8 byte handle containing GPU ID in the most significant 4 bytes and * idr_handle in the least significant 4 bytes */ @@ -741,7 +839,7 @@ enum kfd_pdd_bound { PDD_BOUND_SUSPENDED, }; -#define MAX_SYSFS_FILENAME_LEN 15 +#define MAX_SYSFS_FILENAME_LEN 31 /* * SDMA counter runs at 100MHz frequency. @@ -750,6 +848,20 @@ enum kfd_pdd_bound { */ #define SDMA_ACTIVITY_DIVISOR 100 +struct pc_sampling_entry { + bool enabled; + enum kfd_ioctl_pc_sample_method method; + struct kfd_process_device *pdd; +}; + +struct ais_counter_entry { + int pci_devfn; + struct attribute attr_bytes_read; + struct attribute attr_bytes_written; + uint64_t bytes_read; + uint64_t bytes_written; +}; + /* Data that is per-process-per device. */ struct kfd_process_device { /* The device that owns this data. */ @@ -797,6 +909,14 @@ struct kfd_process_device { struct attribute attr_sdma; char sdma_filename[MAX_SYSFS_FILENAME_LEN]; + /* spm data */ + struct kfd_spm_cntr *spm_cntr; + struct mutex spm_mutex; + struct work_struct spm_work; + spinlock_t spm_irq_lock; + /* reserve space to fix spm overflow */ + u32 spm_overflow_reserved; + /* Eviction activity tracking */ uint64_t last_evict_timestamp; atomic64_t evict_duration_counter; @@ -838,6 +958,12 @@ struct kfd_process_device { uint64_t page_in; uint64_t page_out; + /* xarray of counters for ais; entries are of type struct ais_counter_entry *, indexed by pci_dev_fn */ +#ifdef HAVE_STRUCT_XARRAY + struct kobject *kobj_ais; + struct xarray ais_counters_xa; +#endif + /* Exception code status*/ uint64_t exception_status; void *vm_fault_exc_data; @@ -923,6 +1049,11 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; +#ifndef HAVE_MMU_NOTIFIER_PUT + /* Use for delayed freeing of kfd_process structure */ + struct rcu_head rcu; +#endif + /* * Array of kfd_process_device pointers, * one for each device the process is using. @@ -946,6 +1077,8 @@ struct kfd_process { size_t signal_event_count; bool signal_event_limit_reached; + struct rb_root_cached bo_interval_tree; + /* Information used for memory eviction */ void *kgd_process_info; /* Eviction fence that is attached to all the BOs of this process. The @@ -963,6 +1096,7 @@ struct kfd_process { * restored after an eviction */ unsigned long last_restore_timestamp; + unsigned long last_evict_timestamp; /* Indicates device process is debug attached with reserved vmid. */ bool debug_trap_enabled; @@ -1018,9 +1152,21 @@ struct kfd_process { /* if gpu page fault sent to KFD */ bool gpu_page_fault; + + /*kfd context id */ + u16 context_id; + + /* The primary kfd_process allocating IDs for its secondary kfd_process, 0 for primary kfd_process */ + struct ida id_table; + + /* Indicates process' PC Sampling ref cnt*/ + uint32_t pc_sampling_ref; }; -#define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ +#define KFD_PROCESS_TABLE_SIZE 8 /* bits: 256 entries */ +#define KFD_CONTEXT_ID_PRIMARY 0xFFFF +#define KFD_CONTEXT_ID_MIN 0 + extern DECLARE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); extern struct srcu_struct kfd_processes_srcu; @@ -1045,14 +1191,16 @@ struct amdkfd_ioctl_desc { }; bool kfd_dev_is_large_bar(struct kfd_node *dev); +struct kfd_process *create_process(const struct task_struct *thread, bool primary); int kfd_process_create_wq(void); void kfd_process_destroy_wq(void); void kfd_cleanup_processes(void); struct kfd_process *kfd_create_process(struct task_struct *thread); -struct kfd_process *kfd_get_process(const struct task_struct *task); +int kfd_create_process_sysfs(struct kfd_process *process); struct kfd_process *kfd_lookup_process_by_pasid(u32 pasid, struct kfd_process_device **pdd); struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm); +struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id); int kfd_process_gpuidx_from_gpuid(struct kfd_process *p, uint32_t gpu_id); int kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, @@ -1067,9 +1215,9 @@ static inline struct kfd_process_device *kfd_process_device_from_gpuidx( } void kfd_unref_process(struct kfd_process *p); -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger); int kfd_process_restore_queues(struct kfd_process *p); -void kfd_suspend_all_processes(void); +void kfd_suspend_all_processes(bool force); int kfd_resume_all_processes(void); struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, @@ -1090,16 +1238,33 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported); int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma); +void kfd_process_notifier_release_internal(struct kfd_process *p); /* KFD process API for creating and translating handles */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem); + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + int preferred_id); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle); +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr); void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); +/* Process device data iterator */ +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p); +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, + struct kfd_process_device *pdd); +bool kfd_has_process_device_data(struct kfd_process *p); + /* PASIDs */ int kfd_pasid_init(void); void kfd_pasid_exit(void); @@ -1112,6 +1277,8 @@ int kfd_doorbell_init(struct kfd_dev *kfd); void kfd_doorbell_fini(struct kfd_dev *kfd); int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma); +void kfd_doorbell_unmap(struct kfd_process_device *pdd); +int kfd_doorbell_remap(struct kfd_process_device *pdd); void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, unsigned int *doorbell_off); void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); @@ -1163,9 +1330,11 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, struct kfd_dev *dev = adev->kfd.dev; uint32_t i; - if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) && - KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) && - KFD_GC_VERSION(dev) != IP_VERSION(9, 5, 0)) + /* + * On multi-aid system, attempt per-node matching. Otherwise, + * fall back to the first node. + */ + if (!amdgpu_is_multi_aid(adev)) return dev->nodes[0]; for (i = 0; i < dev->num_nodes; i++) @@ -1176,6 +1345,7 @@ static inline struct kfd_node *kfd_node_by_irq_ids(struct amdgpu_device *adev, } int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev); int kfd_numa_node_to_apic_id(int numa_node_id); +uint32_t kfd_gpu_node_num(void); /* Interrupts */ #define KFD_IRQ_FENCE_CLIENTID 0xff @@ -1200,6 +1370,8 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, uint64_t tma_addr); void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled); +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled); /* CWSR initialization */ int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); @@ -1232,6 +1404,11 @@ struct kfd_criu_bo_priv_data { uint64_t user_addr; uint32_t idr_handle; uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; + + /* IPC related variables */ + uint32_t is_imported; + uint32_t ipc_flags; + uint32_t ipc_share_handle[4]; }; /* @@ -1341,6 +1518,8 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, struct kfd_node *dev); struct mqd_manager *mqd_manager_init_v12(enum KFD_MQD_TYPE type, struct kfd_node *dev); +struct mqd_manager *mqd_manager_init_v12_1(enum KFD_MQD_TYPE type, + struct kfd_node *dev); struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev); void device_queue_manager_uninit(struct device_queue_manager *dqm); struct kernel_queue *kernel_queue_init(struct kfd_node *dev, @@ -1494,6 +1673,7 @@ extern const struct kfd_event_interrupt_class event_interrupt_class_v9; extern const struct kfd_event_interrupt_class event_interrupt_class_v9_4_3; extern const struct kfd_event_interrupt_class event_interrupt_class_v10; extern const struct kfd_event_interrupt_class event_interrupt_class_v11; +extern const struct kfd_event_interrupt_class event_interrupt_class_v12_1; extern const struct kfd_device_global_init_class device_global_init_class_cik; @@ -1505,7 +1685,7 @@ int kfd_wait_on_events(struct kfd_process *p, bool all, uint32_t *user_timeout_ms, uint32_t *wait_result); void kfd_signal_event_interrupt(u32 pasid, uint32_t partial_id, - uint32_t valid_id_bits); + uint32_t valid_id_bits, bool signal_mailbox_updated); void kfd_signal_hw_exception_event(u32 pasid); int kfd_set_event(struct kfd_process *p, uint32_t event_id); int kfd_reset_event(struct kfd_process *p, uint32_t event_id); @@ -1528,6 +1708,7 @@ void kfd_signal_vm_fault_event(struct kfd_process_device *pdd, void kfd_signal_reset_event(struct kfd_node *dev); void kfd_signal_poison_consumed_event(struct kfd_node *dev, u32 pasid); +void kfd_signal_process_terminate_event(struct kfd_process *p); static inline void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type) @@ -1550,6 +1731,17 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(struct kfd_dev *kfd); +void kfd_spm_init_process_device(struct kfd_process_device *pdd); +void kfd_spm_release_process_device(struct kfd_process_device *pdd); +int kfd_rlc_spm(struct kfd_process *p, void __user *data); + +/* PeerDirect support */ +void kfd_init_peer_direct(void); +void kfd_close_peer_direct(void); + +/* IPC Support */ +int kfd_ipc_init(void); + /* Compute profile */ void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); @@ -1579,6 +1771,13 @@ static inline bool kfd_is_first_node(struct kfd_node *node) return (node == node->kfd->nodes[0]); } +/* AIS Support */ +int kfd_ais_init(struct amdgpu_device *adev); +void kfd_ais_deinit(struct amdgpu_device *adev); +int kfd_ais_rw_file(struct amdgpu_device *adev, struct amdgpu_bo *bo, + struct kfd_ais_in_args *in, struct kfd_process_device *pdd, + uint64_t *size_copied); + /* Debugfs */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index a085faac9fe1a..2677cbe3d364e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -42,8 +42,10 @@ struct mm_struct; #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" +#include "kfd_pc_sampling.h" /* * List of struct kfd_process (field kfd_process). @@ -68,12 +70,13 @@ static struct workqueue_struct *kfd_restore_wq; static struct kfd_process *find_process(const struct task_struct *thread, bool ref); static void kfd_process_ref_release(struct kref *ref); -static struct kfd_process *create_process(const struct task_struct *thread); static void evict_process_worker(struct work_struct *work); static void restore_process_worker(struct work_struct *work); static void kfd_process_device_destroy_cwsr_dgpu(struct kfd_process_device *pdd); +static void kfd_sysfs_create_file(struct kobject *kobj, struct attribute *attr, + char *name); struct kfd_procfs_tree { struct kobject *kobj; @@ -468,28 +471,26 @@ static ssize_t kfd_sysfs_counters_show(struct kobject *kobj, return 0; } -static struct attribute attr_queue_size = { - .name = "size", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_type = { - .name = "type", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_gpuid = { - .name = "gpuid", - .mode = KFD_SYSFS_FILE_MODE -}; +#ifdef HAVE_STRUCT_XARRAY +static ssize_t kfd_sysfs_ais_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct ais_counter_entry *entry; + int len = strlen(attr->name); -static struct attribute *procfs_queue_attrs[] = { - &attr_queue_size, - &attr_queue_type, - &attr_queue_gpuid, - NULL -}; -ATTRIBUTE_GROUPS(procfs_queue); + if (len > 6 && !strcmp(((char *)attr->name) + len - 6, "PCI_in")) { + entry = container_of(attr, struct ais_counter_entry, + attr_bytes_read); + return sysfs_emit(buf, "%llu\n", READ_ONCE(entry->bytes_read)); + } + if (len > 7 && !strcmp(((char *)attr->name) + len - 7, "PCI_out")) { + entry = container_of(attr, struct ais_counter_entry, + attr_bytes_written); + return sysfs_emit(buf, "%llu\n", READ_ONCE(entry->bytes_written)); + } + return 0; +} +#endif static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, @@ -497,7 +498,6 @@ static const struct sysfs_ops procfs_queue_ops = { static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, - .default_groups = procfs_queue_groups, }; static const struct sysfs_ops procfs_stats_ops = { @@ -518,6 +518,17 @@ static const struct kobj_type sysfs_counters_type = { .release = kfd_procfs_kobj_release, }; +#ifdef HAVE_STRUCT_XARRAY +static const struct sysfs_ops sysfs_ais_ops = { + .show = kfd_sysfs_ais_show, +}; + +static const struct kobj_type sysfs_ais_type = { + .sysfs_ops = &sysfs_ais_ops, + .release = kfd_procfs_kobj_release, +}; +#endif + int kfd_procfs_add_queue(struct queue *q) { struct kfd_process *proc; @@ -539,6 +550,10 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } + kfd_sysfs_create_file(&q->kobj, &q->attr_gpuid, "gpuid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); + kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); + return 0; } @@ -586,7 +601,7 @@ static void kfd_procfs_add_sysfs_stats(struct kfd_process *p) ret = kobject_init_and_add(pdd->kobj_stats, &procfs_stats_type, p->kobj, - stats_dir_filename); + "%s", stats_dir_filename); if (ret) { pr_warn("Creating KFD proc/stats_%s folder failed", @@ -633,7 +648,7 @@ static void kfd_procfs_add_sysfs_counters(struct kfd_process *p) return; ret = kobject_init_and_add(kobj_counters, &sysfs_counters_type, - p->kobj, counters_dir_filename); + p->kobj, "%s", counters_dir_filename); if (ret) { pr_warn("Creating KFD proc/%s folder failed", counters_dir_filename); @@ -678,11 +693,54 @@ static void kfd_procfs_add_sysfs_files(struct kfd_process *p) } } +#ifdef HAVE_STRUCT_XARRAY +static void kfd_procfs_add_sysfs_ais(struct kfd_process *p) +{ + int ret = 0; + int i; + char ais_dir_filename[MAX_SYSFS_FILENAME_LEN]; + + if (!p || !p->kobj) + return; + + /* + * Create sysfs files for each GPU which supports SVM + * - proc//ais_/ + * - proc//ais_/XX:XX:XX.XX:PCI_in (created dynamically) + * - proc//ais_/XX:XX:XX.XX:PCI_out (created dynamically) + */ + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + struct kobject *kobj_ais; + + snprintf(ais_dir_filename, MAX_SYSFS_FILENAME_LEN, + "ais_%u", pdd->dev->id); + kobj_ais = kfd_alloc_struct(kobj_ais); + if (!kobj_ais) + return; + + ret = kobject_init_and_add(kobj_ais, &sysfs_ais_type, + p->kobj, ais_dir_filename); + pdd->kobj_ais = kobj_ais; + if (ret) { + pr_warn("Creating KFD proc/%s folder failed", + ais_dir_filename); + kobject_put(kobj_ais); + return; + } + } +} +#endif + void kfd_procfs_del_queue(struct queue *q) { if (!q) return; + sysfs_remove_file(&q->kobj, &q->attr_gpuid); + sysfs_remove_file(&q->kobj, &q->attr_size); + sysfs_remove_file(&q->kobj, &q->attr_type); + kobject_del(&q->kobj); kobject_put(&q->kobj); } @@ -825,6 +883,105 @@ static void kfd_process_device_destroy_ib_mem(struct kfd_process_device *pdd) kfd_process_free_gpuvm(qpd->ib_mem, pdd, &qpd->ib_kaddr); } +int kfd_create_process_sysfs(struct kfd_process *process) +{ + struct kfd_process *primary_process; + int ret; + + if (process->kobj) { + pr_warn("kobject already exists for the kfd_process\n"); + return -EINVAL; + } + + process->kobj = kfd_alloc_struct(process->kobj); + if (!process->kobj) { + pr_warn("Creating procfs kobject failed"); + return -ENOMEM; + } + + if (process->context_id == KFD_CONTEXT_ID_PRIMARY) + ret = kobject_init_and_add(process->kobj, &procfs_type, + procfs.kobj, "%d", + (int)process->lead_thread->pid); + else { + primary_process = kfd_lookup_process_by_mm(process->lead_thread->mm); + if (!primary_process) + return -ESRCH; + + ret = kobject_init_and_add(process->kobj, &procfs_type, + primary_process->kobj, "context_%u", + process->context_id); + kfd_unref_process(primary_process); + } + + if (ret) { + pr_warn("Creating procfs pid directory failed"); + kobject_put(process->kobj); + return ret; + } + + kfd_sysfs_create_file(process->kobj, &process->attr_pasid, + "pasid"); + + process->kobj_queues = kobject_create_and_add("queues", + process->kobj); + if (!process->kobj_queues) + pr_warn("Creating KFD proc/queues folder failed"); + + kfd_procfs_add_sysfs_stats(process); + kfd_procfs_add_sysfs_files(process); + kfd_procfs_add_sysfs_counters(process); +#ifdef HAVE_STRUCT_XARRAY + kfd_procfs_add_sysfs_ais(process); +#endif + + return 0; +} + +static int kfd_process_alloc_id(struct kfd_process *process) +{ + int ret; + struct kfd_process *primary_process; + + /* already assign 0xFFFF when create */ + if (process->context_id == KFD_CONTEXT_ID_PRIMARY) + return 0; + + primary_process = kfd_lookup_process_by_mm(process->lead_thread->mm); + if (!primary_process) + return -ESRCH; + + /* id range: KFD_CONTEXT_ID_MIN to 0xFFFE */ + ret = ida_alloc_range(&primary_process->id_table, KFD_CONTEXT_ID_MIN, + KFD_CONTEXT_ID_PRIMARY - 1, GFP_KERNEL); + if (ret < 0) + goto out; + + process->context_id = ret; + ret = 0; + +out: + kfd_unref_process(primary_process); + + return ret; +} + +static void kfd_process_free_id(struct kfd_process *process) +{ + struct kfd_process *primary_process; + + if (process->context_id != KFD_CONTEXT_ID_PRIMARY) + return; + + primary_process = kfd_lookup_process_by_mm(process->lead_thread->mm); + if (!primary_process) + return; + + ida_free(&primary_process->id_table, process->context_id); + + kfd_unref_process(primary_process); +} + struct kfd_process *kfd_create_process(struct task_struct *thread) { struct kfd_process *process; @@ -854,6 +1011,12 @@ struct kfd_process *kfd_create_process(struct task_struct *thread) */ mutex_lock(&kfd_processes_mutex); + if (kfd_gpu_node_num() <= 0) { + pr_warn("no gpu node! Cannot create KFD process"); + process = ERR_PTR(-EINVAL); + goto out; + } + if (kfd_is_locked(NULL)) { pr_debug("KFD is locked! Cannot create process"); process = ERR_PTR(-EINVAL); @@ -867,38 +1030,16 @@ struct kfd_process *kfd_create_process(struct task_struct *thread) if (process) { pr_debug("Process already found\n"); } else { - process = create_process(thread); + process = create_process(thread, true); if (IS_ERR(process)) goto out; if (!procfs.kobj) goto out; - process->kobj = kfd_alloc_struct(process->kobj); - if (!process->kobj) { - pr_warn("Creating procfs kobject failed"); - goto out; - } - ret = kobject_init_and_add(process->kobj, &procfs_type, - procfs.kobj, "%d", - (int)process->lead_thread->pid); - if (ret) { - pr_warn("Creating procfs pid directory failed"); - kobject_put(process->kobj); - goto out; - } - - kfd_sysfs_create_file(process->kobj, &process->attr_pasid, - "pasid"); - - process->kobj_queues = kobject_create_and_add("queues", - process->kobj); - if (!process->kobj_queues) - pr_warn("Creating KFD proc/queues folder failed"); - - kfd_procfs_add_sysfs_stats(process); - kfd_procfs_add_sysfs_files(process); - kfd_procfs_add_sysfs_counters(process); + ret = kfd_create_process_sysfs(process); + if (ret) + pr_warn("Failed to create sysfs entry for the kfd_process"); kfd_debugfs_add_process(process); @@ -911,31 +1052,13 @@ struct kfd_process *kfd_create_process(struct task_struct *thread) return process; } -struct kfd_process *kfd_get_process(const struct task_struct *thread) -{ - struct kfd_process *process; - - if (!thread->mm) - return ERR_PTR(-EINVAL); - - /* Only the pthreads threading model is supported. */ - if (thread->group_leader->mm != thread->mm) - return ERR_PTR(-EINVAL); - - process = find_process(thread, false); - if (!process) - return ERR_PTR(-EINVAL); - - return process; -} - static struct kfd_process *find_process_by_mm(const struct mm_struct *mm) { struct kfd_process *process; hash_for_each_possible_rcu(kfd_processes_table, process, kfd_processes, (uintptr_t)mm) - if (process->mm == mm) + if (process->mm == mm && process->context_id == KFD_CONTEXT_ID_PRIMARY) return process; return NULL; @@ -985,7 +1108,7 @@ struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid) static void kfd_process_device_free_bos(struct kfd_process_device *pdd) { struct kfd_process *p = pdd->process; - void *mem; + struct kfd_bo *buf_obj; int id; int i; @@ -993,7 +1116,7 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * Remove all handles from idr and release appropriate * local memory object */ - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -1001,11 +1124,11 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->adev, mem, peer_pdd->drm_priv); + peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, - pdd->drm_priv, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, + buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } } @@ -1049,6 +1172,16 @@ static void kfd_process_free_outstanding_kfd_bos(struct kfd_process *p) kfd_process_device_free_bos(p->pdds[i]); } +static void kfd_process_profiler_release(struct kfd_process *p, struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->dev->kfd->profiler_lock); + if (pdd->dev->kfd->profiler_process == p) { + pdd->qpd.dqm->ops.set_perfcount(pdd->qpd.dqm, 0); + pdd->dev->kfd->profiler_process = NULL; + } + mutex_unlock(&pdd->dev->kfd->profiler_lock); +} + static void kfd_process_destroy_pdds(struct kfd_process *p) { int i; @@ -1060,6 +1193,11 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d, for pid %d)\n", pdd->dev->id, p->lead_thread->pid); + + kfd_process_profiler_release(p, pdd); + kfd_pc_sample_release(pdd); + kfd_spm_release_process_device(pdd); + kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); @@ -1071,12 +1209,13 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) get_order(KFD_CWSR_TBA_TMA_SIZE)); idr_destroy(&pdd->alloc_idr); + mutex_destroy(&pdd->qpd.doorbell_lock); kfd_free_process_doorbells(pdd->dev->kfd, pdd); if (pdd->dev->kfd->shared_resources.enable_mes && pdd->proc_ctx_cpu_ptr) - amdgpu_amdkfd_free_gtt_mem(pdd->dev->adev, + amdgpu_amdkfd_free_kernel_mem(pdd->dev->adev, &pdd->proc_ctx_bo); /* * before destroying pdd, make sure to report availability @@ -1133,6 +1272,29 @@ static void kfd_process_remove_sysfs(struct kfd_process *p) kobject_put(pdd->kobj_counters); pdd->kobj_counters = NULL; } +#ifdef HAVE_STRUCT_XARRAY + for (i = 0; i < p->n_pdds; i++) { + pdd = p->pdds[i]; + struct ais_counter_entry *counter; + unsigned long index; + + xa_for_each(&pdd->ais_counters_xa, index, counter) { + const char *read_filename = counter->attr_bytes_read.name; + const char *write_filename = counter->attr_bytes_written.name; + + sysfs_remove_file(pdd->kobj_ais, &counter->attr_bytes_read); + sysfs_remove_file(pdd->kobj_ais, &counter->attr_bytes_written); + kfree(read_filename); + kfree(write_filename); + kfree(counter); + } + + xa_destroy(&pdd->ais_counters_xa); + + kobject_del(pdd->kobj_ais); + kobject_put(pdd->kobj_ais); + } +#endif kobject_del(p->kobj); kobject_put(p->kobj); @@ -1175,7 +1337,11 @@ static void kfd_process_wq_release(struct work_struct *work) if (ef) dma_fence_signal(ef); - kfd_process_remove_sysfs(p); + if (p->context_id != KFD_CONTEXT_ID_PRIMARY) + kfd_process_free_id(p); + else + ida_destroy(&p->id_table); + kfd_debugfs_remove_process(p); kfd_process_kunmap_signal_bo(p); @@ -1191,6 +1357,11 @@ static void kfd_process_wq_release(struct work_struct *work) put_task_struct(p->lead_thread); + /* the last step is removing process entries under /sys + * to indicate the process has been terminated. + */ + kfd_process_remove_sysfs(p); + kfree(p); } @@ -1202,6 +1373,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } +#ifdef HAVE_MMU_NOTIFIER_PUT static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { /* This increments p->ref counter if kfd process p exists */ @@ -1214,11 +1386,42 @@ static void kfd_process_free_notifier(struct mmu_notifier *mn) { kfd_unref_process(container_of(mn, struct kfd_process, mmu_notifier)); } +#else +static void kfd_process_destroy_delayed(struct rcu_head *rcu) +{ + struct kfd_process *p = container_of(rcu, struct kfd_process, rcu); + + kfd_unref_process(p); +} +#endif -static void kfd_process_notifier_release_internal(struct kfd_process *p) +static void kfd_process_table_remove(struct kfd_process *p) +{ + mutex_lock(&kfd_processes_mutex); + /* + * Do early return if table is empty. + * + * This could potentially happen if this function is called concurrently + * by mmu_notifier and by kfd_cleanup_pocesses. + * + */ + if (hash_empty(kfd_processes_table)) { + mutex_unlock(&kfd_processes_mutex); + return; + } + hash_del_rcu(&p->kfd_processes); + mutex_unlock(&kfd_processes_mutex); + synchronize_srcu(&kfd_processes_srcu); +} + +void kfd_process_notifier_release_internal(struct kfd_process *p) { int i; +#ifndef HAVE_MMU_NOTIFIER_PUT + struct mm_struct *mm = p->mm; +#endif + kfd_process_table_remove(p); cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); @@ -1260,7 +1463,15 @@ static void kfd_process_notifier_release_internal(struct kfd_process *p) srcu_read_unlock(&kfd_processes_srcu, idx); } - mmu_notifier_put(&p->mmu_notifier); +#ifdef HAVE_MMU_NOTIFIER_PUT + if (p->context_id == KFD_CONTEXT_ID_PRIMARY) + mmu_notifier_put(&p->mmu_notifier); +#else + if (p->context_id == KFD_CONTEXT_ID_PRIMARY) { + mmu_notifier_unregister_no_release(&p->mmu_notifier, mm); + mmu_notifier_call_srcu(&p->rcu, &kfd_process_destroy_delayed); + } +#endif } static void kfd_process_notifier_release(struct mmu_notifier *mn, @@ -1276,29 +1487,15 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, if (WARN_ON(p->mm != mm)) return; - mutex_lock(&kfd_processes_mutex); - /* - * Do early return if table is empty. - * - * This could potentially happen if this function is called concurrently - * by mmu_notifier and by kfd_cleanup_pocesses. - * - */ - if (hash_empty(kfd_processes_table)) { - mutex_unlock(&kfd_processes_mutex); - return; - } - hash_del_rcu(&p->kfd_processes); - mutex_unlock(&kfd_processes_mutex); - synchronize_srcu(&kfd_processes_srcu); - kfd_process_notifier_release_internal(p); } static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, +#ifdef HAVE_MMU_NOTIFIER_PUT .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, +#endif }; /* @@ -1492,7 +1689,8 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported) * management and memory-manager-related preemptions or * even deadlocks. */ - if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1)) + if (KFD_GC_VERSION(dev) >= IP_VERSION(10, 1, 1) && + KFD_GC_VERSION(dev) < IP_VERSION(12, 1, 0)) return false; if (dev->kfd->noretry) @@ -1502,13 +1700,36 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported) return true; } +/* bit offset in 1st-level TMA's 2nd byte which used for KFD_TRAP_TYPE_BIT */ +enum KFD_TRAP_TYPE_BIT { + KFD_TRAP_TYPE_DEBUG = 0, /* bit 0 for debug trap */ + KFD_TRAP_TYPE_HOST, + KFD_TRAP_TYPE_STOCHASTIC, +}; + void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled) { if (qpd->cwsr_kaddr) { - uint64_t *tma = - (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); - tma[2] = enabled; + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); + else + clear_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); + } +} + +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled) +{ + if (qpd->cwsr_kaddr) { + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(method, &tma[2]); + else + clear_bit(method, &tma[2]); } } @@ -1516,10 +1737,12 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, * On return the kfd_process is fully operational and will be freed when the * mm is released */ -static struct kfd_process *create_process(const struct task_struct *thread) +struct kfd_process *create_process(const struct task_struct *thread, bool primary) { struct kfd_process *process; +#ifdef HAVE_MMU_NOTIFIER_PUT struct mmu_notifier *mn; +#endif int err = -ENOMEM; process = kzalloc(sizeof(*process), GFP_KERNEL); @@ -1532,6 +1755,7 @@ static struct kfd_process *create_process(const struct task_struct *thread) process->lead_thread = thread->group_leader; process->n_pdds = 0; process->queues_paused = false; + INIT_DELAYED_WORK(&process->eviction_work, evict_process_worker); INIT_DELAYED_WORK(&process->restore_work, restore_process_worker); process->last_restore_timestamp = get_jiffies_64(); @@ -1575,20 +1799,44 @@ static struct kfd_process *create_process(const struct task_struct *thread) * After this point, mmu_notifier_put will trigger the cleanup by * dropping the last process reference in the free_notifier. */ - mn = mmu_notifier_get(&kfd_process_mmu_notifier_ops, process->mm); - if (IS_ERR(mn)) { - err = PTR_ERR(mn); - goto err_register_notifier; + if (primary) { + process->context_id = KFD_CONTEXT_ID_PRIMARY; +#ifdef HAVE_MMU_NOTIFIER_PUT + mn = mmu_notifier_get(&kfd_process_mmu_notifier_ops, process->mm); + if (IS_ERR(mn)) { + err = PTR_ERR(mn); + goto err_register_notifier; + } + BUG_ON(mn != &process->mmu_notifier); +#else + /* Must be last, have to use release destruction after this */ + process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops; + err = mmu_notifier_register(&process->mmu_notifier, process->mm); + if (err) + goto err_register_notifier; +#endif + ida_init(&process->id_table); + } + + err = kfd_process_alloc_id(process); + if (err) { + pr_err("Creating kfd process: failed to alloc an id\n"); + goto err_alloc_id; } - BUG_ON(mn != &process->mmu_notifier); kfd_unref_process(process); get_task_struct(process->lead_thread); + /* If PeerDirect interface was not detected try to detect it again + * in case if network driver was loaded later. + */ + kfd_init_peer_direct(); INIT_WORK(&process->debug_event_workarea, debug_event_write_work_handler); return process; +err_alloc_id: + kfd_process_free_id(process); err_register_notifier: hash_del_rcu(&process->kfd_processes); svm_range_list_fini(process); @@ -1636,6 +1884,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->qpd.pqm = &p->pqm; pdd->qpd.evicted = 0; pdd->qpd.mapped_gws_queue = false; + mutex_init(&pdd->qpd.doorbell_lock); pdd->process = p; pdd->bound = PDD_UNBOUND; pdd->already_dequeued = false; @@ -1644,6 +1893,10 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->sdma_past_activity_counter = 0; pdd->user_gpu_id = dev->id; atomic64_set(&pdd->evict_duration_counter, 0); + kfd_spm_init_process_device(pdd); +#ifdef HAVE_STRUCT_XARRAY + xa_init(&pdd->ais_counters_xa); +#endif p->pdds[p->n_pdds++] = pdd; if (kfd_dbg_is_per_vmid_supported(pdd->dev)) @@ -1684,9 +1937,6 @@ int kfd_process_device_init_vm(struct kfd_process_device *pdd, struct kfd_node *dev; int ret; - if (!drm_file) - return -EINVAL; - if (pdd->drm_priv) return -EBUSY; @@ -1791,9 +2041,50 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, * Assumes that the process lock is held. */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem) + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + int preferred_id) { - return idr_alloc(&pdd->alloc_idr, mem, 0, 0, GFP_KERNEL); + int handle; + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + buf_obj = kzalloc(sizeof(*buf_obj), GFP_KERNEL); + + if (!buf_obj) + return -ENOMEM; + + buf_obj->it.start = start; + buf_obj->it.last = start + length - 1; + interval_tree_insert(&buf_obj->it, &p->bo_interval_tree); + + buf_obj->mem = mem; + buf_obj->dev = pdd->dev; + buf_obj->cpuva = cpuva; + buf_obj->mem_type = mem_type; + + if (preferred_id < 0) + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + else + handle = idr_alloc(&pdd->alloc_idr, buf_obj, preferred_id, + preferred_id + 1, GFP_KERNEL); + + if (handle < 0) + kfree(buf_obj); + + return handle; +} + +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle) +{ + if (handle < 0) + return NULL; + + return (struct kfd_bo *)idr_find(&pdd->alloc_idr, handle); } /* Translate specific handle from process local memory idr @@ -1802,10 +2093,40 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, int handle) { - if (handle < 0) + struct kfd_bo *buf_obj; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + if (!buf_obj) + return NULL; + + return buf_obj->mem; +} + +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr) +{ + struct interval_tree_node *it_node; + struct kfd_bo *buf_obj; + + it_node = interval_tree_iter_first(&p->bo_interval_tree, + start_addr, last_addr); + if (!it_node) { + pr_err("0x%llx-0x%llx does not relate to an existing buffer\n", + start_addr, last_addr); return NULL; + } + + if (interval_tree_iter_next(it_node, start_addr, last_addr)) { + pr_err("0x%llx-0x%llx spans more than a single BO\n", + start_addr, last_addr); + return NULL; + } + + buf_obj = container_of(it_node, struct kfd_bo, it); - return idr_find(&pdd->alloc_idr, handle); + return buf_obj; } /* Remove specific handle from process local memory idr @@ -1814,8 +2135,23 @@ void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle) { - if (handle >= 0) - idr_remove(&pdd->alloc_idr, handle); + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + if (handle < 0) + return; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + if (!buf_obj) + return; + + idr_remove(&pdd->alloc_idr, handle); + + interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); + + kfree(buf_obj); } static struct kfd_process_device *kfd_lookup_process_device_by_pasid(u32 pasid) @@ -1880,14 +2216,35 @@ struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm) return p; } +/* This increments the process->ref counter. */ +struct kfd_process *kfd_lookup_process_by_id(const struct mm_struct *mm, u16 id) +{ + struct kfd_process *p, *ret_p = NULL; + unsigned int temp; + + int idx = srcu_read_lock(&kfd_processes_srcu); + + hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { + if (p->mm == mm && p->context_id == id) { + kref_get(&p->ref); + ret_p = p; + break; + } + } + + srcu_read_unlock(&kfd_processes_srcu, idx); + + return ret_p; +} + /* kfd_process_evict_queues - Evict all user queues of a process * * Eviction is reference-counted per process-device. This means multiple * evictions from different sources can be nested safely. */ -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger) { - int r = 0; + int r = 0, r_tmp = 0; int i; unsigned int n_evicted = 0; @@ -1898,15 +2255,17 @@ int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) kfd_smi_event_queue_eviction(pdd->dev, p->lead_thread->pid, trigger); - r = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, + r_tmp = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, &pdd->qpd); /* evict return -EIO if HWS is hang or asic is resetting, in this case * we would like to set all the queues to be in evicted state to prevent * them been add back since they actually not be saved right now. */ - if (r && r != -EIO) { + if (r_tmp && r_tmp != -EIO) { dev_err(dev, "Failed to evict process queues\n"); - goto fail; + r = r_tmp; + if (!force) + goto fail; } n_evicted++; @@ -1987,23 +2346,115 @@ kfd_process_gpuid_from_node(struct kfd_process *p, struct kfd_node *node, return -EINVAL; } -static int signal_eviction_fence(struct kfd_process *p) +static bool signal_eviction_fence(struct kfd_process *p) { struct dma_fence *ef; - int ret; + bool ret; rcu_read_lock(); ef = dma_fence_get_rcu_safe(&p->ef); rcu_read_unlock(); if (!ef) - return -EINVAL; - + return true; +#ifdef HAVE_DMA_FENCE_CHECK_AND_SIGNAL + ret = dma_fence_check_and_signal(ef); +#else ret = dma_fence_signal(ef); +#endif dma_fence_put(ef); return ret; } +void kfd_process_schedule_restore(struct kfd_process *p) +{ + unsigned long evicted_jiffies; + unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); + + /* wait at least PROCESS_RESTORE_TIME_MS before attempting to restore + */ + evicted_jiffies = get_jiffies_64() - p->last_evict_timestamp; + if (delay_jiffies > evicted_jiffies) + delay_jiffies -= evicted_jiffies; + else + delay_jiffies = 0; + + pr_debug("Process pid %d schedule restore work\n", p->lead_thread->pid); + if (mod_delayed_work(kfd_restore_wq, &p->restore_work, delay_jiffies)) + kfd_process_restore_queues(p); +} + +static void kfd_process_unmap_doorbells(struct kfd_process *p) +{ + struct mm_struct *mm = p->mm; + int i; + + mmap_write_lock(mm); + + for (i = 0; i < p->n_pdds; i++) + kfd_doorbell_unmap(p->pdds[i]); + + mmap_write_unlock(mm); +} + +int kfd_process_remap_doorbells_locked(struct kfd_process *p) +{ + int ret = 0; + int i; + + for (i = 0; i < p->n_pdds; i++) + ret = kfd_doorbell_remap(p->pdds[i]); + + return ret; +} + +static int kfd_process_remap_doorbells(struct kfd_process *p) +{ + struct mm_struct *mm = p->mm; + int ret = 0; + + mmap_write_lock(mm); + ret = kfd_process_remap_doorbells_locked(p); + mmap_write_unlock(mm); + + return ret; +} + +/** + * kfd_process_unmap_doorbells_if_idle - Check if queues are active + * + * Returns true if queues are idle, and unmap doorbells. + * Returns false if queues are active + */ +static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) +{ + bool busy = false; + int i; + + if (!keep_idle_process_evicted) + return false; + + /* Unmap doorbell first to avoid race conditions. Otherwise while the + * second queue is checked, the first queue may get more work, but we + * won't detect that since it has been checked + */ + kfd_process_unmap_doorbells(p); + + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); + if (busy) + break; + } + + /* Remap doorbell if process queue is not idle */ + if (busy) + kfd_process_remap_doorbells(p); + + return !busy; +} + static void evict_process_worker(struct work_struct *work) { int ret; @@ -2016,9 +2467,12 @@ static void evict_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, eviction_work); + trace_kfd_evict_process_worker_start(p); + + p->last_evict_timestamp = get_jiffies_64(); pr_debug("Started evicting process pid %d\n", p->lead_thread->pid); - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { /* If another thread already signaled the eviction fence, * they are responsible stopping the queues and scheduling @@ -2032,6 +2486,7 @@ static void evict_process_worker(struct work_struct *work) pr_debug("Finished evicting process pid %d\n", p->lead_thread->pid); } else pr_err("Failed to evict queues of process pid %d\n", p->lead_thread->pid); + trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success"); } static int restore_process_helper(struct kfd_process *p) @@ -2069,7 +2524,15 @@ static void restore_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, restore_work); - pr_debug("Started restoring process pasid %d\n", (int)p->lead_thread->pid); + + if (kfd_process_unmap_doorbells_if_idle(p)) { + pr_debug("Process pid %d queues idle, doorbell unmapped\n", + (int)p->lead_thread->pid); + return; + } + + pr_debug("Started restoring process pid %d\n", (int)p->lead_thread->pid); + trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. * Otherwise this would have to be set by KGD (restore_process_bos) @@ -2090,10 +2553,15 @@ static void restore_process_worker(struct work_struct *work) if (mod_delayed_work(kfd_restore_wq, &p->restore_work, msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? + "Rescheduled restore" : + "Failed to reschedule restore"); + } else { + trace_kfd_restore_process_worker_end(p, "Success"); } } -void kfd_suspend_all_processes(void) +void kfd_suspend_all_processes(bool force) { struct kfd_process *p; unsigned int temp; @@ -2101,7 +2569,7 @@ void kfd_suspend_all_processes(void) WARN(debug_evictions, "Evicting all processes"); hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { - if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) + if (kfd_process_evict_queues(p, force, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) pr_err("Failed to suspend process pid %d\n", p->lead_thread->pid); signal_eviction_fence(p); } @@ -2179,7 +2647,8 @@ int kfd_process_drain_interrupts(struct kfd_process_device *pdd) */ if (KFD_GC_VERSION(pdd->dev->kfd) == IP_VERSION(9, 4, 3) || KFD_GC_VERSION(pdd->dev->kfd) == IP_VERSION(9, 4, 4) || - KFD_GC_VERSION(pdd->dev->kfd) == IP_VERSION(9, 5, 0)) { + KFD_GC_VERSION(pdd->dev->kfd) == IP_VERSION(9, 5, 0) || + KFD_GC_VERSION(pdd->dev->kfd) == IP_VERSION(12, 1, 0)) { node_id = ffs(pdd->dev->interrupt_bitmap) - 1; irq_drain_fence[3] |= node_id << 16; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 7fbb5c274ccc4..1c4a04029b82c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -94,7 +94,8 @@ void kfd_process_dequeue_from_device(struct kfd_process_device *pdd) if (dev->kfd->shared_resources.enable_mes && !!pdd->proc_ctx_gpu_addr && down_read_trylock(&dev->adev->reset_domain->sem)) { amdgpu_mes_flush_shader_debugger(dev->adev, - pdd->proc_ctx_gpu_addr); + pdd->proc_ctx_gpu_addr, + ffs(pdd->dev->xcc_mask) - 1); up_read(&dev->adev->reset_domain->sem); } pdd->already_dequeued = true; @@ -209,8 +210,8 @@ static void pqm_clean_queue_resource(struct process_queue_manager *pqm, } if (dev->kfd->shared_resources.enable_mes) { - amdgpu_amdkfd_free_gtt_mem(dev->adev, &pqn->q->gang_ctx_bo); - amdgpu_amdkfd_free_gtt_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); + amdgpu_amdkfd_free_kernel_mem(dev->adev, &pqn->q->gang_ctx_bo); + amdgpu_amdkfd_free_kernel_mem(dev->adev, (void **)&pqn->q->wptr_bo_gart); } } @@ -264,12 +265,13 @@ static int init_user_queue(struct process_queue_manager *pqm, (*q)->process = pqm->process; if (dev->kfd->shared_resources.enable_mes) { - retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, + retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, AMDGPU_MES_GANG_CTX_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &(*q)->gang_ctx_bo, &(*q)->gang_ctx_gpu_addr, &(*q)->gang_ctx_cpu_ptr, - false); + false, true); if (retval) { pr_err("failed to allocate gang context bo\n"); goto cleanup; @@ -297,7 +299,7 @@ static int init_user_queue(struct process_queue_manager *pqm, return 0; free_gang_ctx_bo: - amdgpu_amdkfd_free_gtt_mem(dev->adev, &(*q)->gang_ctx_bo); + amdgpu_amdkfd_free_kernel_mem(dev->adev, &(*q)->gang_ctx_bo); cleanup: uninit_queue(*q); *q = NULL; @@ -345,7 +347,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, * If we are just about to create DIQ, the is_debug flag is not set yet * Hence we also check the type as well */ - if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ)) + if (pdd->qpd.is_debug) max_queues = dev->kfd->device_info.max_no_of_hqd/2; if (pdd->qpd.queue_count >= max_queues) @@ -367,12 +369,13 @@ int pqm_create_queue(struct process_queue_manager *pqm, /* Allocate proc_ctx_bo only if MES is enabled and this is the first queue */ if (!pdd->proc_ctx_cpu_ptr && dev->kfd->shared_resources.enable_mes) { - retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, + retval = amdgpu_amdkfd_alloc_kernel_mem(dev->adev, AMDGPU_MES_PROC_CTX_SIZE, + AMDGPU_GEM_DOMAIN_GTT, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context bo\n"); return retval; @@ -426,22 +429,6 @@ int pqm_create_queue(struct process_queue_manager *pqm, restore_mqd, restore_ctl_stack); print_queue(q); break; - case KFD_QUEUE_TYPE_DIQ: - kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ); - if (!kq) { - retval = -ENOMEM; - goto err_create_queue; - } - kq->queue->properties.queue_id = *qid; - pqn->kq = kq; - pqn->q = NULL; - retval = kfd_process_drain_interrupts(pdd); - if (retval) - break; - - retval = dev->dqm->ops.create_kernel_queue(dev->dqm, - kq, &pdd->qpd); - break; default: WARN(1, "Invalid queue type %d", type); retval = -EINVAL; @@ -548,6 +535,10 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); + + if (retval == -ERESTARTSYS) + return retval; + if (retval) { pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", pdd->pasid, @@ -603,9 +594,11 @@ int pqm_update_queue_properties(struct process_queue_manager *pqm, return err; if (kfd_queue_buffer_get(vm, (void *)p->queue_address, &p->ring_bo, - p->queue_size)) { + p->queue_size + + pqn->q->properties.metadata_queue_size)) { pr_debug("ring buf 0x%llx size 0x%llx not mapped on GPU\n", p->queue_address, p->queue_size); + amdgpu_bo_unreserve(vm->root.bo); return -EFAULT; } @@ -1082,6 +1075,7 @@ int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, uint32_t *ctl_stack_size) { struct process_queue_node *pqn; + int ret; pqn = get_queue_by_qid(pqm, qid); if (!pqn) { @@ -1094,9 +1088,14 @@ int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm, return -EOPNOTSUPP; } - pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, + ret = pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm, pqn->q, mqd_size, ctl_stack_size); + if (ret) { + pr_debug("amdkfd: Overflow while computing stack size for queue %d\n", qid); + return ret; + } + return 0; } @@ -1131,32 +1130,13 @@ int pqm_debugfs_mqds(struct seq_file *m, void *data) break; default: seq_printf(m, - " Bad user queue type %d on device %x\n", + " Queue node with bad user queue type %d on device %x\n", q->properties.type, q->device->id); continue; } mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type]; size = mqd_mgr->mqd_stride(mqd_mgr, &q->properties); - } else if (pqn->kq) { - q = pqn->kq->queue; - mqd_mgr = pqn->kq->mqd_mgr; - switch (q->properties.type) { - case KFD_QUEUE_TYPE_DIQ: - seq_printf(m, " DIQ on device %x\n", - pqn->kq->dev->id); - break; - default: - seq_printf(m, - " Bad kernel queue type %d on device %x\n", - q->properties.type, - pqn->kq->dev->id); - continue; - } - } else { - seq_printf(m, - " Weird: Queue node with neither kernel nor user queue\n"); - continue; } for (xcc = 0; xcc < num_xccs; xcc++) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c index 80c4fa2b0975d..572b21e39e83c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_queue.c @@ -247,9 +247,12 @@ int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_prope properties->format == KFD_QUEUE_FORMAT_AQL && topo_dev->node_props.gfx_target_version >= 70000 && topo_dev->node_props.gfx_target_version < 90000) - expected_queue_size = properties->queue_size / 2; + /* metadata_queue_size not supported on GFX7/GFX8 */ + expected_queue_size = + PAGE_ALIGN(properties->queue_size / 2); else - expected_queue_size = properties->queue_size; + expected_queue_size = + PAGE_ALIGN(properties->queue_size + properties->metadata_queue_size); vm = drm_priv_to_vm(pdd->drm_priv); err = amdgpu_bo_reserve(vm->root.bo, false); @@ -275,8 +278,8 @@ int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_prope /* EOP buffer is not required for all ASICs */ if (properties->eop_ring_buffer_address) { - if (properties->eop_ring_buffer_size != topo_dev->node_props.eop_buffer_size) { - pr_debug("queue eop bo size 0x%x not equal to node eop buf size 0x%x\n", + if (properties->eop_ring_buffer_size < topo_dev->node_props.eop_buffer_size) { + pr_debug("queue eop bo size 0x%x is less than node eop buf size 0x%x\n", properties->eop_ring_buffer_size, topo_dev->node_props.eop_buffer_size); err = -EINVAL; @@ -284,7 +287,7 @@ int kfd_queue_acquire_buffers(struct kfd_process_device *pdd, struct queue_prope } err = kfd_queue_buffer_get(vm, (void *)properties->eop_ring_buffer_address, &properties->eop_buf_bo, - properties->eop_ring_buffer_size); + ALIGN(properties->eop_ring_buffer_size, PAGE_SIZE)); if (err) goto out_err_unreserve; } @@ -392,12 +395,20 @@ int kfd_queue_unref_bo_vas(struct kfd_process_device *pdd, return 0; } -#define SGPR_SIZE_PER_CU 0x4000 -#define LDS_SIZE_PER_CU 0x10000 -#define HWREG_SIZE_PER_CU 0x1000 #define DEBUGGER_BYTES_ALIGN 64 #define DEBUGGER_BYTES_PER_WAVE 32 +static u32 kfd_get_sgpr_size_per_cu(u32 gfxv) +{ + u32 sgpr_size = 0x4000; + + if (gfxv == 120500 || + gfxv == 120501) + sgpr_size = 0x8000; + + return sgpr_size; +} + static u32 kfd_get_vgpr_size_per_cu(u32 gfxv) { u32 vgpr_size = 0x40000; @@ -413,14 +424,53 @@ static u32 kfd_get_vgpr_size_per_cu(u32 gfxv) gfxv == 120000 || /* GFX_VERSION_GFX1200 */ gfxv == 120001) /* GFX_VERSION_GFX1201 */ vgpr_size = 0x60000; + else if (gfxv == 120500 || /* GFX_VERSION_GFX1250 */ + gfxv == 120501) /* GFX_VERSION_GFX1251 */ + vgpr_size = 0x80000; return vgpr_size; } +static u32 kfd_get_hwreg_size_per_cu(u32 gfxv) +{ + u32 hwreg_size = 0x1000; + + if (gfxv == 120500 || gfxv == 120501) + hwreg_size = 0x8000; + + return hwreg_size; +} + +static u32 kfd_get_lds_size_per_cu(u32 gfxv, struct kfd_node_properties *props) +{ + u32 lds_size = 0x10000; + + if (gfxv == 90500 || gfxv == 120500 || gfxv == 120501) + lds_size = props->lds_size_in_kb << 10; + + return lds_size; +} + +static u32 get_num_waves(struct kfd_node_properties *props, u32 gfxv, u32 cu_num) +{ + u32 wave_num = 0; + + if (gfxv < 100100) + wave_num = min(cu_num * 40, + props->array_count / props->simd_arrays_per_engine * 512); + else if (gfxv < 120500) + wave_num = cu_num * 32; + else if (gfxv <= 120501) + wave_num = cu_num * 64; + + WARN_ON(wave_num == 0); + + return wave_num; +} + #define WG_CONTEXT_DATA_SIZE_PER_CU(gfxv, props) \ - (kfd_get_vgpr_size_per_cu(gfxv) + SGPR_SIZE_PER_CU +\ - (((gfxv) == 90500) ? (props->lds_size_in_kb << 10) : LDS_SIZE_PER_CU) +\ - HWREG_SIZE_PER_CU) + (kfd_get_vgpr_size_per_cu(gfxv) + kfd_get_sgpr_size_per_cu(gfxv) +\ + kfd_get_lds_size_per_cu(gfxv, props) + kfd_get_hwreg_size_per_cu(gfxv)) #define CNTL_STACK_BYTES_PER_WAVE(gfxv) \ ((gfxv) >= 100100 ? 12 : 8) /* GFX_VERSION_NAVI10*/ @@ -440,9 +490,7 @@ void kfd_queue_ctx_save_restore_size(struct kfd_topology_device *dev) return; cu_num = props->simd_count / props->simd_per_cu / NUM_XCC(dev->gpu->xcc_mask); - wave_num = (gfxv < 100100) ? /* GFX_VERSION_NAVI10 */ - min(cu_num * 40, props->array_count / props->simd_arrays_per_engine * 512) - : cu_num * 32; + wave_num = get_num_waves(props, gfxv, cu_num); wg_data_size = ALIGN(cu_num * WG_CONTEXT_DATA_SIZE_PER_CU(gfxv, props), PAGE_SIZE); ctl_stack_size = wave_num * CNTL_STACK_BYTES_PER_WAVE(gfxv) + 8; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index d2bc169e84b0b..66b84d1040c81 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -129,7 +129,7 @@ static ssize_t kfd_smi_ev_write(struct file *filep, const char __user *user, struct kfd_smi_client *client = filep->private_data; uint64_t events; - if (!access_ok(user, size) || size < sizeof(events)) + if (!kcl_access_ok(user, size) || size < sizeof(events)) return -EFAULT; if (copy_from_user(&events, user, sizeof(events))) return -EFAULT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c new file mode 100644 index 0000000000000..87e52194dc258 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -0,0 +1,729 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "amdgpu_irq.h" +#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" +#include "ivsrcid/ivsrcid_vislands30.h" +#include // for use_mm() +#include + +/* + * SPM revision change log + * + * 0.1 - Initial revision + * 0.2 - add kfd_ioctl_spm_buffer_header + * 0.3 - add multiple XCC support + * 0.4 - add gfx_v9_4_3 SPM support + */ +#define KFD_IOCTL_SPM_MAJOR_VERSION 0 +#define KFD_IOCTL_SPM_MINOR_VERSION 4 + +struct user_buf { + uint64_t __user *user_addr; + u32 ubufsize; +}; + +struct kfd_spm_base { + struct user_buf ubuf; + u64 gpu_addr; + u32 ring_size; + u32 ring_rptr; + u32 size_copied; + u32 has_data_loss; + u32 *cpu_addr; + void *spm_obj; + bool has_user_buf; + bool is_user_buf_filled; + bool is_spm_started; + u32 warned_ring_rptr; +}; + +struct kfd_spm_cntr { + struct kfd_spm_base spm[MAX_XCP]; + int spm_use_cnt; + struct mutex spm_worker_mutex; + wait_queue_head_t spm_buf_wq; + u32 have_users_buf_cnt; + bool are_users_buf_filled; +}; + +/* used to detect SPM overflow */ +#define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD + +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); +static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev); + +static int kfd_spm_monitor_thread(void *param) +{ + struct kfd_process_device *pdd = param; + struct kfd_node *node = pdd->dev; + + allow_signal(SIGKILL); + while (!kthread_should_stop() && + !signal_pending(node->spm_monitor_thread) && pdd->spm_cntr) { + bool need_schedule = false; + u32 inst; + + usleep_range(1, 11); + + if (!mutex_trylock(&pdd->spm_cntr->spm_worker_mutex)) + continue; + + for_each_inst(inst, node->xcc_mask) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + u32 warned_ring_rptr; + u32 ring_size; + u32 ring_rptr; + u32 ring_wptr; + + if (!spm->is_spm_started) + continue; + + ring_size = spm->ring_size; + ring_rptr = spm->ring_rptr; + warned_ring_rptr = spm->warned_ring_rptr; + ring_wptr = READ_ONCE(spm->cpu_addr[0]); + + if (need_schedule || (ring_rptr != warned_ring_rptr && + (ring_size + ring_wptr - ring_rptr) % ring_size > + (ring_size >> 1))) { + spm->warned_ring_rptr = ring_rptr; + if (!need_schedule) { + dev_dbg(node->adev->dev, + "[SPM#%d] soft interrupt rptr:0x%08x--wptr:0x%08x", + inst, ring_rptr, ring_wptr); + need_schedule = true; + } + } + } + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + if (need_schedule) + schedule_work(&pdd->spm_work); + } + node->spm_monitor_thread = NULL; + return 0; +} + +static int kfd_spm_monitor_thread_start(struct kfd_process_device *pdd) +{ + struct kfd_node *node = pdd->dev; + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "spm_%d", node->adev->ddev.render->index); + node->spm_monitor_thread = + kthread_run(kfd_spm_monitor_thread, pdd, thread_name); + + if (IS_ERR(node->spm_monitor_thread)) { + ret = PTR_ERR(node->spm_monitor_thread); + node->spm_monitor_thread = NULL; + dev_dbg(node->adev->dev, "Failed to create spm monitor thread %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + +static void kfd_spm_preset(struct kfd_spm_base *spm, u32 size) +{ + uint64_t *overflow_ptr, *overflow_end_ptr; + + overflow_ptr = (uint64_t *)((uint64_t)spm->cpu_addr + + spm->ring_size + 0x20); + overflow_end_ptr = overflow_ptr + (size >> 3); + /* SPM data filling is 0x20 alignment */ + for ( ; overflow_ptr < overflow_end_ptr; overflow_ptr += 4) + *overflow_ptr = SPM_OVERFLOW_MAGIC; +} + +static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy, int inst) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + uint64_t __user *user_address; + uint64_t *ring_buf; + u32 user_buf_space_left; + int ret = 0; + + if (spm->ubuf.user_addr == NULL) + return -EFAULT; + + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); + /* From RLC spec, ring_rptr = 0 points to spm->cpu_addr + 0x20 */ + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); + + if (user_address == NULL) + return -EFAULT; + + user_buf_space_left = spm->ubuf.ubufsize - spm->size_copied; + + if (size_to_copy < user_buf_space_left) { + ret = copy_to_user(user_address, ring_buf, size_to_copy); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + spm->size_copied += size_to_copy; + spm->ring_rptr += size_to_copy; + } else { + ret = copy_to_user(user_address, ring_buf, user_buf_space_left); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + + spm->size_copied = spm->ubuf.ubufsize; + spm->ring_rptr += user_buf_space_left; + spm->is_user_buf_filled = true; + } + + return ret; +} + +static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd, int inst) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + u32 overflow_size = 0; + u32 size_to_copy; + int ret = 0; + u32 ring_wptr; + + ring_wptr = READ_ONCE(spm->cpu_addr[0]); + + /* SPM might stall if we cannot copy data out of SPM ringbuffer. + * spm->has_data_loss is only a hint here since stall is only a + * possibility and data loss might not happen. But it is a useful + * hint for user mode profiler to take extra actions. + */ + if (!spm->has_user_buf || spm->is_user_buf_filled) { + spm->has_data_loss = true; + /* set flag due to there is no flag setup + * when read ring buffer timeout. + */ + if (!spm->is_user_buf_filled) + spm->is_user_buf_filled = true; + dev_dbg(pdd->dev->adev->dev, "[SPM#%d] [%d|%d] rptr:0x%x--wptr:0x%x", inst, + spm->has_user_buf, spm->is_user_buf_filled, spm->ring_rptr, ring_wptr); + goto exit; + } + + if (spm->ring_rptr == ring_wptr) + goto exit; + + spm->warned_ring_rptr = spm->ring_rptr; + if (ring_wptr > spm->ring_rptr) { + size_to_copy = ring_wptr - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); + } else { + uint64_t *ring_start, *ring_end; + + ring_start = (uint64_t *)((uint64_t)spm->cpu_addr + 0x20); + ring_end = ring_start + (spm->ring_size >> 3); + for ( ; overflow_size < pdd->spm_overflow_reserved; overflow_size += 0x20) { + uint64_t *overflow_ptr = ring_end + (overflow_size >> 3); + + if (*overflow_ptr == SPM_OVERFLOW_MAGIC) + break; + } + if (overflow_size) + dev_dbg(pdd->dev->adev->dev, + "SPM ring buffer overflow size 0x%x", overflow_size); + /* move overflow counters into ring buffer to avoid data loss */ + memcpy(ring_start, ring_end, overflow_size); + + size_to_copy = spm->ring_size - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); + + /* correct counter start point */ + if (spm->ring_size == spm->ring_rptr) { + if (ring_wptr == 0) { + /* reset rptr to start point of ring buffer */ + spm->ring_rptr = ring_wptr; + goto exit; + } + spm->ring_rptr = 0; + size_to_copy = ring_wptr - spm->ring_rptr; + if (!ret) + ret = kfd_spm_data_copy(pdd, size_to_copy, inst); + } + } + +exit: + kfd_spm_preset(spm, overflow_size); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, inst, spm->ring_rptr); + return ret; +} + +static void kfd_spm_work(struct work_struct *work) +{ + struct kfd_process_device *pdd = container_of(work, struct kfd_process_device, spm_work); + struct mm_struct *mm = NULL; // referenced + + mm = get_task_mm(pdd->process->lead_thread); + if (mm) { + kthread_use_mm(mm); + { /* attach mm */ + int inst; + + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, false); + for_each_inst(inst, pdd->dev->xcc_mask) { + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + + kfd_spm_read_ring_buffer(pdd, inst); + if (spm->is_user_buf_filled) + WRITE_ONCE(pdd->spm_cntr->are_users_buf_filled, true); + } + if (READ_ONCE(pdd->spm_cntr->are_users_buf_filled)) { + pr_debug("SPM wake up buffer work queue."); + wake_up(&pdd->spm_cntr->spm_buf_wq); + } + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + } /* detach mm */ + kthread_unuse_mm(mm); + /* release the mm structure */ + mmput(mm); + } +} + +void kfd_spm_init_process_device(struct kfd_process_device *pdd) +{ + /* pre-gfx11 spm has a hardware bug to cause overflow */ + if (pdd->dev->adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 1)) + pdd->spm_overflow_reserved = 0x400; + + mutex_init(&pdd->spm_mutex); + pdd->spm_cntr = NULL; +} + +void kfd_spm_release_process_device(struct kfd_process_device *pdd) +{ + struct amdgpu_device *adev = pdd->dev->adev; + + kfd_release_spm(pdd, adev); + mutex_destroy(&pdd->spm_mutex); +} + +static int _kfd_acquire_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + int ret = 0; + + /* allocate 4M spm ring buffer */ + spm->ring_size = order_base_2(4 * 1024 * 1024/4); + spm->ring_size = (1 << spm->ring_size) * 4; + + ret = amdgpu_amdkfd_alloc_kernel_mem(adev, + spm->ring_size, AMDGPU_GEM_DOMAIN_GTT, &spm->spm_obj, + &spm->gpu_addr, (void *)&spm->cpu_addr, + false, false); + + if (ret) + goto out; + + /* reserve space to fix spm overflow */ + spm->ring_size -= pdd->spm_overflow_reserved; + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, inst, drm_priv_to_vm(pdd->drm_priv), + spm->gpu_addr, spm->ring_size); + + /* + * By definition, the last 8 DWs of the buffer are not part of the rings + * and are instead part of the Meta data area. + */ + spm->ring_size -= 0x20; + + if (ret) + goto rlc_spm_acquire_failure; + + kfd_spm_preset(spm, pdd->spm_overflow_reserved); + spm->warned_ring_rptr = ~0; + goto out; + +rlc_spm_acquire_failure: + amdgpu_amdkfd_free_kernel_mem(adev, &spm->spm_obj); + memset(spm, 0, sizeof(*spm)); +out: + return ret; +} + +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + int ret = 0; + int inst; + + mutex_lock(&pdd->spm_mutex); + + if (pdd->spm_cntr) { + ret = -EBUSY; + goto out; + } + + pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); + if (!pdd->spm_cntr) { + ret = -ENOMEM; + goto out; + } + + for_each_inst(inst, pdd->dev->xcc_mask) { + ret = _kfd_acquire_spm(pdd, inst, adev); + if (ret) + goto acquire_spm_failure; + pdd->spm_cntr->spm_use_cnt++; + } + + pdd->spm_cntr->have_users_buf_cnt = 0; + mutex_init(&pdd->spm_cntr->spm_worker_mutex); + + init_waitqueue_head(&pdd->spm_cntr->spm_buf_wq); + INIT_WORK(&pdd->spm_work, kfd_spm_work); + + spin_lock_init(&pdd->spm_irq_lock); + pdd->dev->spm_monitor_thread = NULL; + + goto out; + +acquire_spm_failure: + for_each_inst(inst, pdd->dev->xcc_mask) + _kfd_release_spm(pdd, inst, adev); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + +out: + mutex_unlock(&pdd->spm_mutex); + return ret; +} + +static void _kfd_release_spm(struct kfd_process_device *pdd, int inst, struct amdgpu_device *adev) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + unsigned long flags; + + if (!spm->ring_size) + return; + amdgpu_amdkfd_rlc_spm_release(adev, inst, drm_priv_to_vm(pdd->drm_priv)); + amdgpu_amdkfd_free_kernel_mem(adev, &(spm->spm_obj)); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + memset(spm, 0, sizeof(*spm)); + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + --pdd->spm_cntr->spm_use_cnt; +} + +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +{ + unsigned long flags; + int inst; + int ret = 0; + + mutex_lock(&pdd->spm_mutex); + if (!pdd->spm_cntr) { + ret = -EINVAL; + goto out; + } + + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); + + for_each_inst(inst, pdd->dev->xcc_mask) { + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + pdd->spm_cntr->spm[inst].is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 0); + } + flush_work(&pdd->spm_work); + wake_up_all(&pdd->spm_cntr->spm_buf_wq); + + for_each_inst(inst, pdd->dev->xcc_mask) + _kfd_release_spm(pdd, inst, adev); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + mutex_destroy(&(pdd->spm_cntr->spm_worker_mutex)); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + +out: + mutex_unlock(&pdd->spm_mutex); + return ret; +} + +static int spm_update_dest_info(struct kfd_process_device *pdd, + int inst, struct kfd_ioctl_spm_args *user_spm_data, + struct kfd_ioctl_spm_args *user_spm_ptr) +{ + struct kfd_spm_base *spm = &(pdd->spm_cntr->spm[inst]); + int ret = 0; + + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + if (spm->has_user_buf) { + struct kfd_ioctl_spm_buffer_header spm_header; + uint64_t __user *user_address; + + user_spm_ptr->bytes_copied += spm->size_copied; + user_spm_ptr->has_data_loss += spm->has_data_loss; + + memset(&spm_header, 0, sizeof(spm_header)); + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr - sizeof(spm_header)); + spm_header.version = KFD_IOCTL_SPM_MAJOR_VERSION << 24 | + KFD_IOCTL_SPM_MINOR_VERSION; + spm_header.bytes_copied = spm->size_copied; + spm_header.has_data_loss = spm->has_data_loss; + spm->has_user_buf = false; + pdd->spm_cntr->have_users_buf_cnt--; + + ret = copy_to_user(user_address, &spm_header, sizeof(spm_header)); + if (ret) { + ret = -EFAULT; + goto out; + } + } + if (user_spm_data->dest_buf) { + spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + spm->ubuf.ubufsize = user_spm_data->buf_size; + /* reserve space for kfd_ioctl_spm_buffer_header */ + spm->ubuf.user_addr = (uint64_t *)((uint64_t)spm->ubuf.user_addr + + sizeof(struct kfd_ioctl_spm_buffer_header)); + spm->ubuf.ubufsize -= sizeof(struct kfd_ioctl_spm_buffer_header); + spm->has_data_loss = false; + spm->size_copied = 0; + spm->is_user_buf_filled = false; + spm->has_user_buf = true; + pdd->spm_cntr->are_users_buf_filled = false; + pdd->spm_cntr->have_users_buf_cnt++; + } +out: + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + return ret; +} + +static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm_cntr, + struct kfd_ioctl_spm_args *user_spm_data) +{ + int ret = 0; + + long timeout = msecs_to_jiffies(user_spm_data->timeout); + long start_jiffies = jiffies; + + ret = wait_event_interruptible_timeout(spm_cntr->spm_buf_wq, + (READ_ONCE(spm_cntr->are_users_buf_filled) == true), + timeout); + + switch (ret) { + case -ERESTARTSYS: + /* Subtract elapsed time from timeout so we wait that much + * less when the call gets restarted. + */ + timeout -= (jiffies - start_jiffies); + if (timeout <= 0) { + ret = -ETIME; + timeout = 0; + pr_debug("[%s] interrupted by signal\n", __func__); + } + break; + + case 0: + default: + timeout = ret; + ret = 0; + break; + } + user_spm_data->timeout = jiffies_to_msecs(timeout); + + return ret; +} + +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) +{ + struct kfd_ioctl_spm_args user_spm_data, *user_spm_ptr; + struct kfd_spm_cntr *spm_cntr; + bool need_schedule = false; + unsigned long flags; + u32 ubufsize; + int ret = 0; + int inst; + + dev_dbg(pdd->dev->adev->dev, "SPM start to set new destination buffer."); + mutex_lock(&pdd->spm_mutex); + spm_cntr = pdd->spm_cntr; + if (spm_cntr == NULL) { + ret = -EINVAL; + goto out; + } + + user_spm_ptr = (struct kfd_ioctl_spm_args *) data; + ubufsize = user_spm_ptr->buf_size / spm_cntr->spm_use_cnt; + ubufsize = rounddown(ubufsize, 32); + + if (ubufsize <= sizeof(struct kfd_ioctl_spm_buffer_header)) { + ret = -EINVAL; + goto out; + } + + memcpy(&user_spm_data, user_spm_ptr, sizeof(user_spm_data)); + user_spm_data.buf_size = ubufsize; + + if (user_spm_data.timeout && spm_cntr->have_users_buf_cnt && + !READ_ONCE(spm_cntr->are_users_buf_filled)) { + dev_dbg(pdd->dev->adev->dev, "SPM waiting for fill awake, timeout = %d ms.", + user_spm_data.timeout); + ret = spm_wait_for_fill_awake(spm_cntr, &user_spm_data); + if (ret == -ETIME) { + /* Copy (partial) data to user buffer after a timeout */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + /* This is not an error */ + ret = 0; + } else if (ret) { + /* handle other errors normally, including -ERESTARTSYS */ + goto out; + } + } else if (!user_spm_data.timeout && spm_cntr->have_users_buf_cnt) { + /* Copy (partial) data to user buffer */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + } + + user_spm_ptr->bytes_copied = 0; + user_spm_ptr->has_data_loss = 0; + for_each_inst(inst, pdd->dev->xcc_mask) { + struct kfd_spm_base *spm = &(spm_cntr->spm[inst]); + + if (spm->has_user_buf || user_spm_data.dest_buf) { + /* Get info about filled space in previous output buffer. + * Setup new dest buf if provided. + */ + ret = spm_update_dest_info(pdd, inst, &user_spm_data, user_spm_ptr); + if (ret) + goto out; + } + + if (user_spm_data.dest_buf) { + /* Start SPM if necessary*/ + if (spm->is_spm_started == false) { + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 1); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = true; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and + * wptr will become 0, adjust rptr accordingly. + */ + spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (!pdd->dev->spm_monitor_thread) + kfd_spm_monitor_thread_start(pdd); + } else { + /* If SPM was already started, there may already + * be data in the ring-buffer that needs to be read. + */ + need_schedule = true; + } + user_spm_data.dest_buf += ubufsize; + } else { + amdgpu_amdkfd_rlc_spm_cntl(adev, inst, 0); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = false; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; + spm->warned_ring_rptr = ~0; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + if (pdd->dev->spm_monitor_thread) + kthread_stop(pdd->dev->spm_monitor_thread); + } + } + +out: + mutex_unlock(&pdd->spm_mutex); + if (need_schedule) + schedule_work(&pdd->spm_work); + + dev_dbg(pdd->dev->adev->dev, "SPM finish to set new destination buffer, ret = %d.", ret); + return ret; +} + +int kfd_rlc_spm(struct kfd_process *p, void *data) +{ + struct kfd_ioctl_spm_args *args = data; + struct kfd_node *dev; + struct kfd_process_device *pdd; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) { + pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); + return -EINVAL; + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return -EINVAL; + + switch (args->op) { + case KFD_IOCTL_SPM_OP_ACQUIRE: + dev->spm_pasid = pdd->pasid; + return kfd_acquire_spm(pdd, dev->adev); + + case KFD_IOCTL_SPM_OP_RELEASE: + return kfd_release_spm(pdd, dev->adev); + + case KFD_IOCTL_SPM_OP_SET_DEST_BUF: + return kfd_set_dest_buffer(pdd, dev->adev, data); + + default: + return -EINVAL; + } + + return -EINVAL; +} + +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd, int xcc_id) +{ + struct kfd_process_device *pdd; + struct kfd_node *dev; + uint8_t xcp_id; + uint16_t pasid; + struct kfd_process *p; + unsigned long flags; + + xcp_id = kfd->adev->xcp_mgr ? + fls(amdgpu_xcp_get_partition(kfd->adev->xcp_mgr, AMDGPU_XCP_GFX, xcc_id)) - 1 : 0; + dev = kfd->nodes[xcp_id]; + pasid = dev->spm_pasid; + p = kfd_lookup_process_by_pasid(pasid, &pdd); + + if (!pdd) { + dev_dbg(dev->adev->dev, "kfd_spm_interrupt p = %p\n", p); + return; /* Presumably process exited. */ + } + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + if (pdd->spm_cntr && pdd->spm_cntr->spm[xcc_id].is_spm_started) + pdd->spm_cntr->spm[xcc_id].has_data_loss = true; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + dev_dbg(pdd->dev->adev->dev, "[SPM#%d:%d] ring buffer stall.", xcp_id, xcc_id); + kfd_unref_process(p); +} + diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 79ea138897fcf..1ddccf386ad7e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -33,6 +33,7 @@ #include "amdgpu_hmm.h" #include "amdgpu.h" #include "amdgpu_xgmi.h" +#include "amdgpu_reset.h" #include "kfd_priv.h" #include "kfd_svm.h" #include "kfd_migrate.h" @@ -184,7 +185,11 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange, addr[i] = (hmm_pfns[i] << PAGE_SHIFT) + bo_adev->vm_manager.vram_base_offset - +#ifdef HAVE_DEV_PAGEMAP_RANGE bo_adev->kfd.pgmap.range.start; +#else + bo_adev->kfd.pgmap.res.start; +#endif addr[i] |= SVM_RANGE_VRAM_DOMAIN; pr_debug_ratelimited("vram address: 0x%llx\n", addr[i]); continue; @@ -585,7 +590,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, svm_bo->eviction_fence = amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), mm, - svm_bo); + svm_bo, p->context_id); mmput(mm); INIT_WORK(&svm_bo->eviction_work, svm_range_evict_svm_bo_worker); svm_bo->evicting = 0; @@ -627,7 +632,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, } } - r = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (r) { pr_debug("failed %d to reserve bo\n", r); amdgpu_bo_unreserve(bo); @@ -1218,7 +1223,8 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, bool snoop = (domain != SVM_RANGE_VRAM_DOMAIN); bool coherent = flags & (KFD_IOCTL_SVM_FLAG_COHERENT | KFD_IOCTL_SVM_FLAG_EXT_COHERENT); bool ext_coherent = flags & KFD_IOCTL_SVM_FLAG_EXT_COHERENT; - unsigned int mtype_local; + unsigned int mtype_local, mtype_remote; + bool is_aid_a1, is_local; if (domain == SVM_RANGE_VRAM_DOMAIN) bo_node = prange->svm_bo->node; @@ -1305,6 +1311,26 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, case IP_VERSION(12, 0, 1): mapping_flags |= AMDGPU_VM_MTYPE_NC; break; + case IP_VERSION(12, 1, 0): + is_aid_a1 = (node->adev->rev_id & 0x10); + is_local = (domain == SVM_RANGE_VRAM_DOMAIN) && + (bo_node->adev == node->adev); + + mtype_local = amdgpu_mtype_local == 0 ? AMDGPU_VM_MTYPE_RW : + amdgpu_mtype_local == 1 ? AMDGPU_VM_MTYPE_NC : + is_aid_a1 ? AMDGPU_VM_MTYPE_RW : AMDGPU_VM_MTYPE_NC; + mtype_remote = is_aid_a1 ? AMDGPU_VM_MTYPE_NC : AMDGPU_VM_MTYPE_UC; + snoop = true; + + if (is_local) /* local HBM */ { + mapping_flags |= mtype_local; + } else if (ext_coherent) { + mapping_flags |= AMDGPU_VM_MTYPE_UC; + } else { + /* system memory or remote VRAM */ + mapping_flags |= mtype_remote; + } + break; default: mapping_flags |= coherent ? AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; @@ -1323,6 +1349,11 @@ svm_range_get_pte_flags(struct kfd_node *node, struct amdgpu_vm *vm, pte_flags |= AMDGPU_PTE_READABLE; if (!(flags & KFD_IOCTL_SVM_FLAG_GPU_RO)) pte_flags |= AMDGPU_PTE_WRITEABLE; + + if ((gc_ip_version == IP_VERSION(12, 1, 0)) && + node->adev->have_atomics_support) + pte_flags |= AMDGPU_PTE_BUS_ATOMICS; + return pte_flags; } @@ -1331,12 +1362,17 @@ svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t start, uint64_t last, struct dma_fence **fence) { - uint64_t init_pte_value = 0; + uint64_t init_pte_value = adev->gmc.init_pte_flags; + uint64_t gpu_start, gpu_end; - pr_debug("[0x%llx 0x%llx]\n", start, last); + /* Convert CPU page range to GPU page range */ + gpu_start = start * AMDGPU_GPU_PAGES_IN_CPU_PAGE; + gpu_end = (last + 1) * AMDGPU_GPU_PAGES_IN_CPU_PAGE - 1; - return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, start, - last, init_pte_value, 0, 0, NULL, NULL, + pr_debug("CPU[0x%llx 0x%llx] -> GPU[0x%llx 0x%llx]\n", start, last, + gpu_start, gpu_end); + return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, gpu_start, + gpu_end, init_pte_value, 0, 0, NULL, NULL, fence); } @@ -1344,7 +1380,6 @@ static int svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, unsigned long last, uint32_t trigger) { - DECLARE_BITMAP(bitmap, MAX_GPU_INSTANCE); struct kfd_process_device *pdd; struct dma_fence *fence = NULL; struct kfd_process *p; @@ -1362,11 +1397,9 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, prange->mapped_to_gpu = false; } - bitmap_or(bitmap, prange->bitmap_access, prange->bitmap_aip, - MAX_GPU_INSTANCE); p = container_of(prange->svms, struct kfd_process, svms); - for_each_set_bit(gpuidx, bitmap, MAX_GPU_INSTANCE) { + for_each_or_bit(gpuidx, prange->bitmap_access, prange->bitmap_aip, MAX_GPU_INSTANCE) { pr_debug("unmap from gpu idx 0x%x\n", gpuidx); pdd = kfd_process_device_from_gpuidx(p, gpuidx); if (!pdd) { @@ -1416,6 +1449,9 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange, last_start, last_start + npages - 1, readonly); for (i = offset; i < offset + npages; i++) { + uint64_t gpu_start; + uint64_t gpu_end; + last_domain = dma_addr[i] & SVM_RANGE_VRAM_DOMAIN; dma_addr[i] &= ~SVM_RANGE_VRAM_DOMAIN; @@ -1433,17 +1469,22 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange, if (readonly) pte_flags &= ~AMDGPU_PTE_WRITEABLE; - pr_debug("svms 0x%p map [0x%lx 0x%llx] vram %d PTE 0x%llx\n", - prange->svms, last_start, prange->start + i, - (last_domain == SVM_RANGE_VRAM_DOMAIN) ? 1 : 0, - pte_flags); /* For dGPU mode, we use same vm_manager to allocate VRAM for * different memory partition based on fpfn/lpfn, we should use * same vm_manager.vram_base_offset regardless memory partition. */ + gpu_start = last_start * AMDGPU_GPU_PAGES_IN_CPU_PAGE; + gpu_end = (prange->start + i + 1) * AMDGPU_GPU_PAGES_IN_CPU_PAGE - 1; + + pr_debug("svms 0x%p map CPU[0x%lx 0x%llx] GPU[0x%llx 0x%llx] vram %d PTE 0x%llx\n", + prange->svms, last_start, prange->start + i, + gpu_start, gpu_end, + (last_domain == SVM_RANGE_VRAM_DOMAIN) ? 1 : 0, + pte_flags); + r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, true, - NULL, last_start, prange->start + i, + NULL, gpu_start, gpu_end, pte_flags, (last_start - prange->start) << PAGE_SHIFT, bo_adev ? bo_adev->vm_manager.vram_base_offset : 0, @@ -2349,6 +2390,9 @@ static void svm_range_drain_retry_fault(struct svm_range_list *svms) pr_debug("drain retry fault gpu %d svms %p\n", i, svms); + if (!down_read_trylock(&pdd->dev->adev->reset_domain->sem)) + continue; + amdgpu_ih_wait_on_checkpoint_process_ts(pdd->dev->adev, pdd->dev->adev->irq.retry_cam_enabled ? &pdd->dev->adev->irq.ih : @@ -2358,6 +2402,7 @@ static void svm_range_drain_retry_fault(struct svm_range_list *svms) amdgpu_ih_wait_on_checkpoint_process_ts(pdd->dev->adev, &pdd->dev->adev->irq.ih_soft); + up_read(&pdd->dev->adev->reset_domain->sem); pr_debug("drain retry fault gpu %d svms 0x%p done\n", i, svms); } @@ -2541,7 +2586,7 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, adev = pdd->dev->adev; /* Check and drain ih1 ring if cam not available */ - if (adev->irq.ih1.ring_size) { + if (!adev->irq.retry_cam_enabled && adev->irq.ih1.ring_size) { ih = &adev->irq.ih1; checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); if (ih->rptr != checkpoint_wptr) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3eb32d58a1200..667bbb7814911 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -206,6 +206,8 @@ struct kfd_topology_device *kfd_create_topology_device( sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value) #define sysfs_show_32bit_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%u\n", value) +#define sysfs_show_64bit_val(buffer, offs, value) \ + sysfs_show_gen_prop(buffer, offs, "%llu\n", value) #define sysfs_show_str_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%s\n", value) @@ -295,11 +297,25 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, { int offs = 0; struct kfd_mem_properties *mem; + uint64_t used_mem; /* Making sure that the buffer is an empty string */ buffer[0] = 0; - mem = container_of(attr, struct kfd_mem_properties, attr); + if (strcmp(attr->name, "used_memory") == 0) { + mem = container_of(attr, struct kfd_mem_properties, + attr_used); + if (mem->gpu) { + if (kfd_devcgroup_check_permission(mem->gpu)) + return -EPERM; + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->adev); + return sysfs_show_64bit_val(buffer, offs, used_mem); + } + /* TODO: Report APU/CPU-allocated memory; For now return 0 */ + return 0; + } + + mem = container_of(attr, struct kfd_mem_properties, attr_props); if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type); @@ -571,6 +587,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_mem_properties *mem; struct kfd_perf_properties *perf; + if (dev->kobj_p2plink) { + list_for_each_entry(p2plink, &dev->p2p_link_props, list) + if (p2plink->kobj) { + kfd_remove_sysfs_file(p2plink->kobj, + &p2plink->attr); + p2plink->kobj = NULL; + } + kobject_del(dev->kobj_p2plink); + kobject_put(dev->kobj_p2plink); + dev->kobj_p2plink = NULL; + } + if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) if (iolink->kobj) { @@ -610,7 +638,12 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) if (dev->kobj_mem) { list_for_each_entry(mem, &dev->mem_props, list) if (mem->kobj) { - kfd_remove_sysfs_file(mem->kobj, &mem->attr); + /* TODO: Remove when CPU/APU supported */ + if (dev->node_props.cpu_cores_count == 0) + sysfs_remove_file(mem->kobj, + &mem->attr_used); + kfd_remove_sysfs_file(mem->kobj, + &mem->attr_props); mem->kobj = NULL; } kobject_del(dev->kobj_mem); @@ -646,9 +679,10 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; struct kfd_perf_properties *perf; - int ret; - uint32_t i, num_attrs; + uint32_t num_attrs; struct attribute **attrs; + int ret; + uint32_t i; if (WARN_ON(dev->kobj_node)) return -EEXIST; @@ -721,12 +755,23 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, return ret; } - mem->attr.name = "properties"; - mem->attr.mode = KFD_SYSFS_FILE_MODE; - sysfs_attr_init(&mem->attr); - ret = sysfs_create_file(mem->kobj, &mem->attr); + mem->attr_props.name = "properties"; + mem->attr_props.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_props); + ret = sysfs_create_file(mem->kobj, &mem->attr_props); if (ret < 0) return ret; + + /* TODO: Support APU/CPU memory usage */ + if (dev->node_props.cpu_cores_count == 0) { + mem->attr_used.name = "used_memory"; + mem->attr_used.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_used); + ret = sysfs_create_file(mem->kobj, &mem->attr_used); + if (ret < 0) + return ret; + } + i++; } @@ -931,17 +976,12 @@ static void kfd_debug_print_topology(void) dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list); if (dev) { - if (dev->node_props.cpu_cores_count && - dev->node_props.simd_count) { - pr_info("Topology: Add APU node [0x%0x:0x%0x]\n", - dev->node_props.device_id, - dev->node_props.vendor_id); - } else if (dev->node_props.cpu_cores_count) + if (dev->node_props.cpu_cores_count) pr_info("Topology: Add CPU node\n"); - else if (dev->node_props.simd_count) - pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n", - dev->node_props.device_id, - dev->node_props.vendor_id); + else + pr_info("Topology: Add GPU node [0x%0x:0x%0x]\n", + dev->node_props.vendor_id, + dev->node_props.device_id); } up_read(&topology_lock); } @@ -1045,8 +1085,10 @@ int kfd_topology_init(void) goto err; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED kdev = list_first_entry(&temp_topology_device_list, struct kfd_topology_device, list); +#endif down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, @@ -1220,7 +1262,15 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI) return; - /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */ + /* checkout source dev has atomics support on root. */ + if (dev->gpu && (!dev->gpu->kfd->pci_atomic_requested || + dev->gpu->adev->asic_type == CHIP_HAWAII)) { + link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; + return; + } + + /* check target_gpu_dev is atomics capable. */ if (target_gpu_dev) { uint32_t cap; @@ -1379,6 +1429,27 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } + + /* Create indirect links so apply flags setting to all */ + list_for_each_entry(link, &dev->p2p_link_props, list) { + link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(dev, NULL, link); + peer_dev = kfd_topology_device_by_proximity_domain( + link->node_to); + + if (!peer_dev) + continue; + + list_for_each_entry(inbound_link, &peer_dev->p2p_link_props, + list) { + if (inbound_link->node_to != link->node_from) + continue; + + inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); + kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); + } + } } static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev, @@ -1490,7 +1561,6 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g return ret; } -#if defined(CONFIG_HSA_AMD_P2P) static int kfd_add_peer_prop(struct kfd_topology_device *kdev, struct kfd_topology_device *peer, int from, int to) { @@ -1558,16 +1628,12 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev, return ret; } -#endif static int kfd_dev_create_p2p_links(void) { struct kfd_topology_device *dev; struct kfd_topology_device *new_dev; -#if defined(CONFIG_HSA_AMD_P2P) - uint32_t i; -#endif - uint32_t k; + uint32_t i, k; int ret = 0; k = 0; @@ -1588,7 +1654,6 @@ static int kfd_dev_create_p2p_links(void) goto out; /* create p2p links */ -#if defined(CONFIG_HSA_AMD_P2P) i = 0; list_for_each_entry(dev, &topology_device_list, list) { if (dev == new_dev) @@ -1610,7 +1675,6 @@ static int kfd_dev_create_p2p_links(void) next: i++; } -#endif out: return ret; @@ -2028,6 +2092,13 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev) if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(12, 0, 0)) dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED; + + if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(12, 1, 0)) { + dev->node_props.capability |= + HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED; + dev->node_props.capability2 |= + HSA_CAP2_TRAP_DEBUG_LDS_OUT_OF_ADDR_RANGE_SUPPORTED; + } } kfd_topology_set_dbg_firmware_support(dev); @@ -2336,7 +2407,11 @@ static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask) if (first_cpu_of_numa_node >= nr_cpu_ids) return -1; #ifdef CONFIG_X86_64 +#ifdef HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT return cpu_data(first_cpu_of_numa_node).topo.apicid; +#else + return cpu_data(first_cpu_of_numa_node).apicid; +#endif #else return first_cpu_of_numa_node; #endif @@ -2355,6 +2430,28 @@ int kfd_numa_node_to_apic_id(int numa_node_id) return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id)); } +/* kfd_gpu_node_num - Return kfd gpu node number at system */ +uint32_t kfd_gpu_node_num(void) +{ + struct kfd_node *dev; + u8 gpu_num = 0; + u8 id = 0; + + while (kfd_topology_enum_kfd_devices(id, &dev) == 0) { + if (!dev || kfd_devcgroup_check_permission(dev)) { + /* Skip non GPU devices and devices to which the + * current process have no access to + */ + id++; + continue; + } + id++; + gpu_num++; + } + + return gpu_num; +} + #if defined(CONFIG_DEBUG_FS) int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data) @@ -2408,3 +2505,26 @@ int kfd_debugfs_rls_by_device(struct seq_file *m, void *data) } #endif + +void kfd_update_svm_support_properties(struct amdgpu_device *adev) +{ + struct kfd_topology_device *dev; + int ret; + + down_write(&topology_lock); + list_for_each_entry(dev, &topology_device_list, list) { + if (!dev->gpu || dev->gpu->adev != adev) + continue; + + if (KFD_IS_SVM_API_SUPPORTED(adev)) { + dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED; + ret = kfd_topology_update_sysfs(); + if (!ret) + sys_props.generation_count++; + else + dev_err(adev->dev, "Failed to update SVM support properties. ret=%d\n", ret); + } else + dev->node_props.capability &= ~HSA_CAP_SVMAPI_SUPPORTED; + } + up_write(&topology_lock); +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 3de8ec0043bb4..129b447fcf84d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -92,7 +92,8 @@ struct kfd_mem_properties { uint32_t mem_clk_max; struct kfd_node *gpu; struct kobject *kobj; - struct attribute attr; + struct attribute attr_props; + struct attribute attr_used; }; #define CACHE_SIBLINGMAP_SIZE 128 @@ -201,4 +202,10 @@ struct kfd_topology_device *kfd_create_topology_device( struct list_head *device_list); void kfd_release_topology_device_list(struct list_head *device_list); +#if IS_ENABLED(CONFIG_HSA_AMD) +void kfd_update_svm_support_properties(struct amdgpu_device *adev); +#else +static inline void kfd_update_svm_support_properties(struct amdgpu_device *adev) {} +#endif + #endif /* __KFD_TOPOLOGY_H__ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.c b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c new file mode 100644 index 0000000000000..805a1da90bb15 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c @@ -0,0 +1,26 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#define CREATE_TRACE_POINTS +#include "kfd_trace.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h new file mode 100644 index 0000000000000..5265efb3728be --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -0,0 +1,151 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#if !defined(_AMDKFD_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _KFD_TRACE_H_ + + +#include +#include +#include + +#include "kfd_priv.h" +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM amdkfd +#define TRACE_INCLUDE_FILE kfd_trace + + +TRACE_EVENT(kfd_map_memory_to_gpu_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pid) + ), + TP_fast_assign( + __entry->pid = p->lead_thread->pid; + ), + TP_printk("Process pid =%u", __entry->pid) +); + + +TRACE_EVENT(kfd_map_memory_to_gpu_end, + TP_PROTO(struct kfd_process *p, u32 array_size, char *pStatusMsg), + TP_ARGS(p, array_size, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pid) + __field(unsigned int, array_size) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pid = p->lead_thread->pid; + __entry->array_size = array_size; + __amdkcl_assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("Process pid = %u, array_size = %u, StatusMsg=%s", + __entry->pid, + __entry->array_size, + __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_kgd2kfd_schedule_evict_and_restore_process, + TP_PROTO(struct kfd_process *p, u32 delay_jiffies), + TP_ARGS(p, delay_jiffies), + TP_STRUCT__entry( + __field(unsigned int, pid) + __field(unsigned int, delay_jiffies) + ), + TP_fast_assign( + __entry->pid = p->lead_thread->pid; + __entry->delay_jiffies = delay_jiffies; + ), + TP_printk("Process pid = %u, delay_jiffies = %u", + __entry->pid, + __entry->delay_jiffies) +); + + +TRACE_EVENT(kfd_evict_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pid) + ), + TP_fast_assign( + __entry->pid = p->lead_thread->pid; + ), + TP_printk("Process pid=%u", __entry->pid) +); + + +TRACE_EVENT(kfd_evict_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pid = p->lead_thread->pid; + __amdkcl_assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("Process pid=%u, StatusMsg=%s", + __entry->pid, __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_restore_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pid) + ), + TP_fast_assign( + __entry->pid = p->lead_thread->pid; + ), + TP_printk("Process pid=%u", __entry->pid) +); + +TRACE_EVENT(kfd_restore_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + entry->pid = p->lead_thread->pid; + __amdkcl_assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("Process pid=%u, StatusMsg=%s", + __entry->pid, __get_str(pStatusMsg)) +); + +#endif + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include diff --git a/drivers/gpu/drm/amd/amdxcp/Makefile b/drivers/gpu/drm/amd/amdxcp/Makefile index 870501a4bb8c0..5790475464f02 100644 --- a/drivers/gpu/drm/amd/amdxcp/Makefile +++ b/drivers/gpu/drm/amd/amdxcp/Makefile @@ -23,3 +23,6 @@ amdxcp-y := amdgpu_xcp_drv.o obj-$(CONFIG_DRM_AMDGPU) += amdxcp.o + +AMD_XCP_PATH := $(src) +include $(AMD_XCP_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c index 44009aa8216ed..7231caaa04f1e 100644 --- a/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.c @@ -25,6 +25,10 @@ #include #include #include +#ifndef HAVE_DRM_DRM_MANAGED_H +#include +#include +#endif #include @@ -108,6 +112,10 @@ static void free_xcp_dev(int8_t index) devres_release_group(&pdev->dev, NULL); platform_device_unregister(pdev); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(&(xcp_dev[index]->drm)); + kfree(xcp_dev[index]); +#endif xcp_dev[index] = NULL; pdev_num--; } diff --git a/drivers/gpu/drm/amd/amdxcp/backport/Makefile b/drivers/gpu/drm/amd/amdxcp/backport/Makefile new file mode 100644 index 0000000000000..4217ff962b225 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/Makefile @@ -0,0 +1,10 @@ +BACKPORT_OBJS := kcl_drm_drv.o + +amdxcp-y += $(addprefix ./backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(AMD_XCP_PATH)/ \ + -I$(AMD_XCP_PATH)/backport/include \ + -I$(AMD_XCP_PATH)/../dkms \ + -include config/config.h \ + -include backport/backport.h diff --git a/drivers/gpu/drm/amd/amdxcp/backport/backport.h b/drivers/gpu/drm/amd/amdxcp/backport/backport.h new file mode 100644 index 0000000000000..d23a4e6be9d11 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/backport.h @@ -0,0 +1,3 @@ +#include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_cleanup.h" +#include "kcl/kcl_mutex.h" diff --git a/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..c331d7f60606b --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,42 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..cc1da02e06e84 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -0,0 +1,58 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + drm = container + offset; + ret = drm_dev_init(drm, driver, parent); + if (ret) { + drm_dev_put(drm); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#endif + drm->dev_private = container; + return container; +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile new file mode 100644 index 0000000000000..2d01094326e2c --- /dev/null +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: MIT +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ + kcl_drm_gem.o kcl_drm_file.o kcl_memory.o + +amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(FULL_AMD_PATH) \ + -I$(FULL_AMD_PATH)/backport/include \ + -I$(FULL_AMD_PATH)/dkms \ + -include config/config.h \ + -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h new file mode 100644 index 0000000000000..f2ddb699f6242 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_H +#define AMDGPU_BACKPORT_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +#include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu.h" +#include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_amdgpu_drm_gem.h" +#include "kcl/kcl_drm_gem_ttm_helper.h" +#include "kcl/kcl_mce.h" +#include "kcl/kcl_drm_aperture.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* + * v5.13-rc3-1669-gba6cd766e0bf + * ("drm/plane: Move drm_plane_enable_fb_damage_clips into core") + * move drm_plane_enable_fb_damage_clips() to drm_planer.h. + * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h new file mode 100644 index 0000000000000..33bf87c0568bd --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_H + +#include +#include "amdgpu.h" +#include + +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_get_vblank_counter_kms(drm_crtc); +} + +static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int crtc) +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_enable_vblank_kms(drm_crtc); +} + +static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int crtc) +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_disable_vblank_kms(drm_crtc); +} + +static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); +} + +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, ktime_t *vblank_time, + bool in_vblank_irq) +{ + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); +} +#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ + +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) +{ + return vblank->time; +} + +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..926e4cd441519 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,43 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +void amdkcl_drm_dev_release(struct drm_device *ddev); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h new file mode 100644 index 0000000000000..5212937b89d88 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H + +#include +#include +#include +#include +#include "amdgpu.h" + +#ifndef HAVE_DRM_FB_HELPER_LASTCLOSE +void drm_fb_helper_lastclose(struct drm_device *dev); +void drm_fb_helper_output_poll_changed(struct drm_device *dev); +#endif + +#ifndef HAVE_DRM_FB_HELPER_GEM_IS_FB +bool kcl_drm_fb_helper_gem_is_fb(struct drm_fb_helper *fb_helper, + struct drm_gem_object *obj); +#define drm_fb_helper_gem_is_fb kcl_drm_fb_helper_gem_is_fb +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h new file mode 100644 index 0000000000000..9ad60a7646fa0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h @@ -0,0 +1,49 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return _kcl_drm_gem_mmap(filp, vma); +} + + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return _kcl_drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h new file mode 100644 index 0000000000000..3ff7751079283 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_color_mgmt.h @@ -0,0 +1,32 @@ +#ifndef __AMDGPU_BACKPORT_KCL_DRM_COLOR_MGMT_H__ +#define __AMDGPU_BACKPORT_KCL_DRM_COLOR_MGMT_H__ + +#include + +#ifndef HAVE_STRUCT_DRM_COLOR_LUT32 +struct drm_color_lut32 { + __u32 red; + __u32 green; + __u32 blue; + __u32 reserved; +}; +#endif + +#ifndef HAVE_DRM_COLOR_LUT32_SIZE +static inline int drm_color_lut32_size(const struct drm_property_blob *blob) +{ + return blob->length / sizeof(struct drm_color_lut32); +} +#endif + +#ifndef HAVE_DRM_COLOR_LUT32_EXTRACT +static inline u32 drm_color_lut32_extract(u32 user_input, int bit_precision) +{ + u64 max = (bit_precision >= 64) ? ~0ULL : (1ULL << bit_precision) - 1; + + return DIV_ROUND_CLOSEST_ULL((u64)user_input * max, + (1ULL << 32) - 1); +} +#endif + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h new file mode 100644 index 0000000000000..2472c61b0e26d --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -0,0 +1,37 @@ +#ifndef __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ +#include +#include +#include +#include + +#ifndef HAVE_DRM_SHOW_FDINFO +void drm_show_fdinfo(struct seq_file *m, struct file *f); +#endif + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +struct drm_memory_stats { + u64 shared; + u64 private; + u64 resident; + u64 purgeable; + u64 active; +}; + +void _kcl_drm_print_memory_stats(struct drm_printer *p, + const struct drm_memory_stats *stats, + enum drm_gem_object_status supported_status, + const char *region); +#define drm_print_memory_stats _kcl_drm_print_memory_stats +#endif + +#ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO +int drm_memory_stats_is_zero(const struct drm_memory_stats *stats); +#endif + +#ifndef HAVE_DRM_FILE_ERR +void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...); +#define drm_file_err kcl_drm_file_err +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..aa89982b0c2c7 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H +#define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H + +#include +#include + +#if !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, + void *vaddr); +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +static inline +void amdgpu_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + _kcl_drm_gem_ttm_vunmap(gem, map); +} + +static inline +int amdgpu_drm_gem_ttm_vmap(struct drm_gem_object *obj, + struct dma_buf_map *map) +{ + return _kcl_drm_gem_ttm_vmap(obj, map); +} +#endif + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *obj); +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv); +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..0d243c59b5f6a --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -0,0 +1,62 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include "amdgpu.h" + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + drm = container + offset; + ret = drm_dev_init(drm, driver, parent); + if (ret) { + drm_dev_put(drm); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#endif + drm->dev_private = container; + return container; +} + +void amdkcl_drm_dev_release(struct drm_device *ddev) +{ + drm_dev_put(ddev); +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c new file mode 100644 index 0000000000000..24e3d0b5ffd00 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -0,0 +1,157 @@ +/* + * \author Rickard E. (Rik) Faith + * \author Daryll Strauss + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu_fdinfo.h" +#ifndef HAVE_DRM_SHOW_FDINFO +/** + * drm_show_fdinfo - helper for drm file fops + * @m: output stream + * @f: the device file instance + * + * Helper to implement fdinfo, for userspace to query usage stats, etc, of a + * process using the GPU. See also &drm_driver.show_fdinfo. + * + * For text output format description please see Documentation/gpu/drm-usage-stats.rst + */ +void drm_show_fdinfo(struct seq_file *m, struct file *f) +{ + struct drm_file *file = f->private_data; + struct drm_device *dev = file->minor->dev; + struct drm_printer p = drm_seq_file_printer(m); + + drm_printf(&p, "drm-driver:\t%s\n", dev->driver->name); + + if (dev_is_pci(dev->dev)) { + struct pci_dev *pdev = to_pci_dev(dev->dev); + + drm_printf(&p, "drm-pdev:\t%04x:%02x:%02x.%d\n", + pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + } + + amdgpu_show_fdinfo(&p, file); +} +#endif + +#ifndef HAVE_DRM_PRINT_MEMORY_STATS +static void print_size(struct drm_printer *p, const char *stat, + const char *region, u64 sz) +{ + const char *units[] = {"", " KiB", " MiB"}; + unsigned u; + + for (u = 0; u < ARRAY_SIZE(units) - 1; u++) { + if (sz == 0 || !IS_ALIGNED(sz, SZ_1K)) + break; + sz = div_u64(sz, SZ_1K); + } + + drm_printf(p, "drm-%s-%s:\t%llu%s\n", stat, region, sz, units[u]); +} + +void _kcl_drm_print_memory_stats(struct drm_printer *p, + const struct drm_memory_stats *stats, + enum drm_gem_object_status supported_status, + const char *region) +{ + print_size(p, "total", region, stats->private + stats->shared); + print_size(p, "shared", region, stats->shared); + print_size(p, "active", region, stats->active); + + if (supported_status & DRM_GEM_OBJECT_RESIDENT) + print_size(p, "resident", region, stats->resident); + + if (supported_status & DRM_GEM_OBJECT_PURGEABLE) + print_size(p, "purgeable", region, stats->purgeable); +} +EXPORT_SYMBOL(_kcl_drm_print_memory_stats); +#endif + +#ifndef HAVE_DRM_MEMORY_STATS_IS_ZERO +int drm_memory_stats_is_zero(const struct drm_memory_stats *stats) +{ + return (stats->shared == 0 && + stats->private == 0 && + stats->resident == 0 && + stats->purgeable == 0 && + stats->active == 0); +} +#endif + +#ifndef HAVE_DRM_FILE_ERR +void kcl_drm_file_err(struct drm_file *file_priv, const char *fmt, ...) +{ + va_list args; + struct va_format vaf; + struct pid *pid; + struct task_struct *task; + struct drm_device *dev = file_priv->minor->dev; + + va_start(args, fmt); + vaf.fmt = fmt; + vaf.va = &args; + +#ifdef HAVE_DRM_FILE_CLIENT_NAME + mutex_lock(&file_priv->client_name_lock); +#endif + rcu_read_lock(); + pid = rcu_dereference(file_priv->pid); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PGID); +#endif +#ifdef HAVE_DRM_FILE_CLIENT_NAME + drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", + task ? task->pid : 0, file_priv->client_name ?: "Unset", &vaf); +#else + drm_err(dev, "comm: %s pid: %d client: %s ... %pV", task ? task->comm : "Unset", + task ? task->pid : 0, "Unset", &vaf); +#endif + + va_end(args); + rcu_read_unlock(); +#ifdef HAVE_DRM_FILE_CLIENT_NAME + mutex_unlock(&file_priv->client_name_lock); +#endif +} +EXPORT_SYMBOL(kcl_drm_file_err); +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c new file mode 100644 index 0000000000000..84ffb99293e93 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -0,0 +1,151 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "amdgpu_ttm.h" +#include "amdgpu_dma_buf.h" + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return amdgpu_mmap(filp, vma); +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return amdgpu_gem_prime_mmap(obj, vma); +} + +#else +static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + struct vm_area_struct *vma) +{ + int ret; + + /* Check for valid size. */ + if (obj_size < vma->vm_end - vma->vm_start) + return -EINVAL; + + /* Take a ref for this mapping of the object, so that the fault + * handler can dereference the mmap offset's pointer to the object. + * This reference is cleaned up by the corresponding vm_close + * (which should happen whether the vma was created by this call, or + * by a vm_open due to mremap or partial unmap or whatever). + */ + drm_gem_object_get(obj); + + vma->vm_private_data = obj; + vma->vm_ops = obj->funcs->vm_ops; + + if (obj->funcs->mmap) { + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; + WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (!vma->vm_ops) { + ret = -EINVAL; + goto err_drm_gem_object_put; + } + + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); + vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + } + + return 0; + +err_drm_gem_object_put: + drm_gem_object_put(obj); + return ret; +} + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + struct drm_file *priv = filp->private_data; + struct drm_device *dev = priv->minor->dev; + struct drm_gem_object *obj = NULL; + struct drm_vma_offset_node *node; + int ret; + + if (drm_dev_is_unplugged(dev)) + return -ENODEV; + + drm_vma_offset_lock_lookup(dev->vma_offset_manager); + node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, + vma->vm_pgoff, + vma_pages(vma)); + if (likely(node)) { + obj = container_of(node, struct drm_gem_object, vma_node); + /* + * When the object is being freed, after it hits 0-refcnt it + * proceeds to tear down the object. In the process it will + * attempt to remove the VMA offset and so acquire this + * mgr->vm_lock. Therefore if we find an object with a 0-refcnt + * that matches our range, we know it is in the process of being + * destroyed and will be freed as soon as we release the lock - + * so we have to check for the 0-refcnted object and treat it as + * invalid. + */ + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); + + if (!obj) + return -EINVAL; + + if (!drm_vma_node_is_allowed(node, priv)) { + drm_gem_object_put(obj); + return -EACCES; + } + +#ifdef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD + if (node->readonly) { + if (vma->vm_flags & VM_WRITE) { + drm_gem_object_put(obj); + return -EINVAL; + } + + vma->vm_flags &= ~VM_MAYWRITE; + } +#endif + + ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, + vma); + + drm_gem_object_put(obj); + + return ret; + +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + if (obj->funcs && obj->funcs->mmap) { + vma->vm_ops = obj->funcs->vm_ops; + } + return drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c new file mode 100644 index 0000000000000..3f3a70274a81c --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#include +#include +#include +#include +#include +#include + +#ifndef drm_gem_ttm_of_gem +#define drm_gem_ttm_of_gem(gem_obj) \ + container_of(gem_obj, struct ttm_buffer_object, base) +#endif + +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); + struct iosys_map map; + + ttm_bo_vmap(bo, &map); + return map.vaddr; +} + +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map map; + + map.vaddr = vaddr; + map.is_iomem = bo->resource->bus.is_iomem; + + ttm_bo_vunmap(bo, &map); +} +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) + +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + int r; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + r = ttm_bo_vmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; + return r; +} + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + ttm_bo_vunmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; +} +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_memory.c b/drivers/gpu/drm/amd/backport/kcl_memory.c new file mode 100644 index 0000000000000..2ade0fbdbc8e1 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_memory.c @@ -0,0 +1,33 @@ +#include + +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn) +{ + int ret = -EINVAL; +#ifdef HAVE_FOLLOW_PFNMAP_START + struct follow_pfnmap_args args = { + .vma = vma, + .address = address, + }; + ret = follow_pfnmap_start(&args); + + if (ret) + return ret; + *pfn = args.pfn; + follow_pfnmap_end(&args); +#else + spinlock_t *ptl; + pte_t *ptep; + ret = follow_pte(vma, address, &ptep, &ptl); + + if (ret) + return ret; + *pfn = pte_pfn(ptep_get(ptep)); + pte_unmap_unlock(ptep, ptl); +#endif + return 0; +} + +EXPORT_SYMBOL(_kcl_follow_pfn); +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c old mode 100644 new mode 100755 index a8a59126b2d2b..251b9813b2a72 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -77,6 +77,7 @@ #include #include #include + #include #include @@ -91,10 +92,10 @@ #include #include #include +#include #include #include #include -#include #include #include @@ -152,11 +153,8 @@ MODULE_FIRMWARE(FIRMWARE_DCN_36_DMUB); #define FIRMWARE_DCN_401_DMUB "amdgpu/dcn_4_0_1_dmcub.bin" MODULE_FIRMWARE(FIRMWARE_DCN_401_DMUB); -/* Number of bytes in PSP header for firmware. */ -#define PSP_HEADER_BYTES 0x100 - -/* Number of bytes in PSP footer for firmware. */ -#define PSP_FOOTER_BYTES 0x100 +#define FIRMWARE_DCN_42_DMUB "amdgpu/dcn_4_2_dmcub.bin" +MODULE_FIRMWARE(FIRMWARE_DCN_42_DMUB); /** * DOC: overview @@ -206,10 +204,11 @@ static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) if (aconnector->dc_sink) subconnector = get_subconnector_type(link); - +#ifdef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY drm_object_property_set_value(&connector->base, connector->dev->mode_config.dp_subconnector_property, subconnector); +#endif } /* @@ -233,12 +232,14 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state); +#endif static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); - +static void prepare_flip_isr(struct amdgpu_crtc *acrtc); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); @@ -574,6 +575,12 @@ static void schedule_dc_vmin_vmax(struct amdgpu_device *adev, queue_work(system_wq, &offload_work->work); } +#ifndef HAVE_KTIME_IS_UNION +static inline ktime_t get_drm_vblank_crtc_time(struct drm_vblank_crtc *vblank) +{ + return kcl_amdgpu_get_vblank_time_ns(vblank); +} +#endif static void dm_vupdate_high_irq(void *interrupt_params) { @@ -581,8 +588,10 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; struct drm_device *drm_dev; +#ifndef HAVE_KTIME_IS_UNION struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; +#endif unsigned long flags; int vrr_active; @@ -591,16 +600,19 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); drm_dev = acrtc->base.dev; +#ifndef HAVE_KTIME_IS_UNION vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); - frame_duration_ns = vblank->time - previous_timestamp; + frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; if (frame_duration_ns > 0) { trace_amdgpu_refresh_rate_track(acrtc->base.index, frame_duration_ns, ktime_divns(NSEC_PER_SEC, frame_duration_ns)); - atomic64_set(&irq_params->previous_timestamp, vblank->time); + atomic64_set(&irq_params->previous_timestamp, + get_drm_vblank_crtc_time(vblank)); } +#endif drm_dbg_vbl(drm_dev, "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, @@ -1132,18 +1144,21 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, continue; *enabled = true; +#ifdef HAVE_DRM_CONNECTOR_ELD_MUTEX mutex_lock(&connector->eld_mutex); +#endif ret = drm_eld_size(connector->eld); memcpy(buf, connector->eld, min(max_bytes, ret)); +#ifdef HAVE_DRM_CONNECTOR_ELD_MUTEX mutex_unlock(&connector->eld_mutex); - +#endif break; } drm_connector_list_iter_end(&conn_iter); mutex_unlock(&adev->dm.audio_lock); - DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); + drm_dbg_kms(adev_to_drm(adev), "Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); return ret; } @@ -1237,7 +1252,7 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) struct drm_audio_component *acomp = adev->dm.audio_component; if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { - DRM_DEBUG_KMS("Notify ELD: %d\n", pin); + drm_dbg_kms(adev_to_drm(adev), "Notify ELD: %d\n", pin); acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, pin, -1); @@ -1250,6 +1265,7 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) struct dmub_srv *dmub_srv = adev->dm.dmub_srv; struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; const struct firmware *dmub_fw = adev->dm.dmub_fw; + struct dc *dc = adev->dm.dc; struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; struct abm *abm = adev->dm.dc->res_pool->abm; struct dc_context *ctx = adev->dm.dc->ctx; @@ -1298,15 +1314,14 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) fw_inst_const = dmub_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + - PSP_HEADER_BYTES; + PSP_HEADER_BYTES_256; fw_bss_data = dmub_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + le32_to_cpu(hdr->inst_const_bytes); /* Copy firmware and bios info into FB memory. */ - fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - - PSP_HEADER_BYTES - PSP_FOOTER_BYTES; + fw_inst_const_size = adev->dm.fw_inst_size; fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes); @@ -1343,8 +1358,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) /* Initialize hardware. */ memset(&hw_params, 0, sizeof(hw_params)); - hw_params.fb_base = adev->gmc.fb_start; - hw_params.fb_offset = adev->vm_manager.vram_base_offset; + hw_params.soc_fb_info.fb_base = adev->gmc.fb_start; + hw_params.soc_fb_info.fb_offset = adev->vm_manager.vram_base_offset; /* backdoor load firmware and trigger dmub running */ if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) @@ -1356,24 +1371,22 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev) for (i = 0; i < fb_info->num_fb; ++i) hw_params.fb[i] = &fb_info->fb[i]; - switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { - case IP_VERSION(3, 1, 3): - case IP_VERSION(3, 1, 4): - case IP_VERSION(3, 5, 0): - case IP_VERSION(3, 5, 1): - case IP_VERSION(3, 6, 0): - case IP_VERSION(4, 0, 1): + /* Enable usb4 dpia in the FW APU */ + if (dc->caps.is_apu && + dc->res_pool->usb4_dpia_count != 0 && + !dc->debug.dpia_debug.bits.disable_dpia) { hw_params.dpia_supported = true; - hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia; - break; - default: - break; + hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia; + hw_params.dpia_hpd_int_enable_supported = false; + hw_params.enable_non_transparent_setconfig = dc->config.consolidated_dpia_dp_lt; + hw_params.disable_dpia_bw_allocation = !dc->config.usb4_bw_alloc_support; } switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { case IP_VERSION(3, 5, 0): case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): + case IP_VERSION(4, 2, 0): hw_params.ips_sequential_ono = adev->external_rev_id > 0x10; hw_params.lower_hbr3_phy_ssc = true; break; @@ -1551,7 +1564,7 @@ static void force_connector_state( mutex_unlock(&connector->dev->mode_config.mutex); mutex_lock(&aconnector->hpd_lock); - drm_kms_helper_connector_hotplug_event(connector); + drm_kms_helper_connector_hotplug_event(connector); mutex_unlock(&aconnector->hpd_lock); } @@ -1821,6 +1834,9 @@ static void *dm_dmub_get_vbios_bounding_box(struct amdgpu_device *adev) case IP_VERSION(4, 0, 1): bb_size = sizeof(struct dml2_soc_bb); break; + case IP_VERSION(4, 2, 0): + bb_size = sizeof(struct dml2_soc_bb); + break; default: return NULL; } @@ -1865,6 +1881,9 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode( case IP_VERSION(3, 5, 1): ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; break; + case IP_VERSION(4, 2, 0): + ret = DMUB_IPS_DISABLE_ALL; + break; default: /* ASICs older than DCN35 do not have IPSs */ if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0)) @@ -1890,6 +1909,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); + mutex_init(&adev->dm.audio_lock); if (amdgpu_dm_irq_init(adev)) { @@ -2008,6 +2028,13 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 0, 0)) init_data.num_virtual_links = 1; + /* DCN42 and above dpia switch to unified link training path */ + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(4, 2, 0)) { + init_data.flags.consolidated_dpia_dp_lt = true; + init_data.flags.enable_dpia_pre_training = true; + init_data.flags.unify_link_enc_assignment = true; + init_data.flags.usb4_bw_alloc_support = true; + } retrieve_dmi_info(&adev->dm); if (adev->dm.edp0_on_dp1_quirk) init_data.flags.support_edp0_on_dp1 = true; @@ -2074,6 +2101,25 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ adev->dm.dc->debug.ignore_cable_id = true; +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + /* TODO: There is a new drm mst change where the freedom of + * vc_next_start_slot update is revoked/moved into drm, instead of in + * driver. This forces us to make sure to get vc_next_start_slot updated + * in drm function each time without considering if mst_state is active + * or not. Otherwise, next time hotplug will give wrong start_slot + * number. We are implementing a temporary solution to even notify drm + * mst deallocation when link is no longer of MST type when uncommitting + * the stream so we will have more time to work on a proper solution. + * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we + * should notify drm to do a complete "reset" of its states and stop + * calling further drm mst functions when link is no longer of an MST + * type. This could happen when we unplug an MST hubs/displays. When + * uncommit stream comes later after unplug, we should just reset + * hardware states only. + */ + adev->dm.dc->debug.temp_mst_deallocation_sequence = true; +#endif //HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (adev->dm.dc->caps.dp_hdmi21_pcon_support) drm_info(adev_to_drm(adev), "DP-HDMI FRL PCON supported\n"); @@ -2105,7 +2151,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) drm_err(adev_to_drm(adev), "failed to initialize freesync_module.\n"); } else - drm_dbg_driver(adev_to_drm(adev), "amdgpu: freesync_module init done %p.\n", + drm_dbg_driver(adev_to_drm(adev), "freesync_module init done %p.\n", adev->dm.freesync_module); amdgpu_dm_init_color_mod(); @@ -2127,7 +2173,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (!adev->dm.hdcp_workqueue) drm_err(adev_to_drm(adev), "failed to initialize hdcp_workqueue.\n"); else - drm_dbg_driver(adev_to_drm(adev), "amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue); + drm_dbg_driver(adev_to_drm(adev), + "hdcp_workqueue init done %p.\n", + adev->dm.hdcp_workqueue); dc_init_callbacks(adev->dm.dc, &init_params); } @@ -2276,6 +2324,11 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) &adev->dm.dmub_bo_gpu_addr, &adev->dm.dmub_bo_cpu_addr); + if (adev->dm.boot_time_crc_info.bo_ptr) + amdgpu_bo_free_kernel(&adev->dm.boot_time_crc_info.bo_ptr, + &adev->dm.boot_time_crc_info.gpu_addr, + &adev->dm.boot_time_crc_info.cpu_addr); + if (adev->dm.hpd_rx_offload_wq && adev->dm.dc) { for (i = 0; i < adev->dm.dc->caps.max_links; i++) { if (adev->dm.hpd_rx_offload_wq[i].wq) { @@ -2373,6 +2426,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): return 0; default: break; @@ -2382,7 +2436,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) } if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { - DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n"); + drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not supported on direct or SMU loading\n"); return 0; } @@ -2390,7 +2444,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) "%s", fw_name_dmcu); if (r == -ENODEV) { /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */ - DRM_DEBUG_KMS("dm: DMCU firmware not found\n"); + drm_dbg_kms(adev_to_drm(adev), "dm: DMCU firmware not found\n"); adev->dm.fw_dmcu = NULL; return 0; } @@ -2414,7 +2468,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version); - DRM_DEBUG_KMS("PSP loading DMCU firmware\n"); + drm_dbg_kms(adev_to_drm(adev), "PSP loading DMCU firmware\n"); return 0; } @@ -2437,9 +2491,11 @@ static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address, static int dm_dmub_sw_init(struct amdgpu_device *adev) { struct dmub_srv_create_params create_params; + struct dmub_srv_fw_meta_info_params fw_meta_info_params; struct dmub_srv_region_params region_params; struct dmub_srv_region_info region_info; struct dmub_srv_memory_params memory_params; + struct dmub_fw_meta_info fw_info; struct dmub_srv_fb_info *fb_info; struct dmub_srv *dmub_srv; const struct dmcub_firmware_header_v1_0 *hdr; @@ -2456,6 +2512,8 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_7_SCRATCH_MEM DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_IB_MEM DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_SHARED_STATE + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_LSDMA_BUFFER + DMUB_WINDOW_MEMORY_TYPE_FB, //DMUB_WINDOW_CURSOR_OFFLOAD }; int r; @@ -2504,7 +2562,9 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) case IP_VERSION(4, 0, 1): dmub_asic = DMUB_ASIC_DCN401; break; - + case IP_VERSION(4, 2, 0): + dmub_asic = DMUB_ASIC_DCN42; + break; default: /* ASIC doesn't support DMUB. */ return 0; @@ -2547,22 +2607,37 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) return -EINVAL; } + /* Extract the FW meta info. */ + memset(&fw_meta_info_params, 0, sizeof(fw_meta_info_params)); + + fw_meta_info_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - + PSP_HEADER_BYTES_256; + fw_meta_info_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); + fw_meta_info_params.fw_inst_const = adev->dm.dmub_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + + PSP_HEADER_BYTES_256; + fw_meta_info_params.fw_bss_data = fw_meta_info_params.bss_data_size ? adev->dm.dmub_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes) + + le32_to_cpu(hdr->inst_const_bytes) : NULL; + fw_meta_info_params.custom_psp_footer_size = 0; + + status = dmub_srv_get_fw_meta_info_from_raw_fw(&fw_meta_info_params, &fw_info); + if (status != DMUB_STATUS_OK) { + /* Skip returning early, just log the error. */ + drm_err(adev_to_drm(adev), "Error getting DMUB FW meta info: %d\n", status); + // return -EINVAL; + } + /* Calculate the size of all the regions for the DMUB service. */ memset(®ion_params, 0, sizeof(region_params)); - region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes) - - PSP_HEADER_BYTES - PSP_FOOTER_BYTES; - region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes); + region_params.inst_const_size = fw_meta_info_params.inst_const_size; + region_params.bss_data_size = fw_meta_info_params.bss_data_size; region_params.vbios_size = adev->bios_size; - region_params.fw_bss_data = region_params.bss_data_size ? - adev->dm.dmub_fw->data + - le32_to_cpu(hdr->header.ucode_array_offset_bytes) + - le32_to_cpu(hdr->inst_const_bytes) : NULL; - region_params.fw_inst_const = - adev->dm.dmub_fw->data + - le32_to_cpu(hdr->header.ucode_array_offset_bytes) + - PSP_HEADER_BYTES; + region_params.fw_bss_data = fw_meta_info_params.fw_bss_data; + region_params.fw_inst_const = fw_meta_info_params.fw_inst_const; region_params.window_memory_type = window_memory_type; + region_params.fw_info = (status == DMUB_STATUS_OK) ? &fw_info : NULL; status = dmub_srv_calc_region_info(dmub_srv, ®ion_params, ®ion_info); @@ -2609,6 +2684,7 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) } adev->dm.bb_from_dmub = dm_dmub_get_vbios_bounding_box(adev); + adev->dm.fw_inst_size = fw_meta_info_params.inst_const_size; return 0; } @@ -2702,6 +2778,54 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) return ret; } +static void amdgpu_dm_boot_time_crc_init(struct amdgpu_device *adev) +{ + struct dm_boot_time_crc_info *bootcrc_info = NULL; + struct dmub_srv *dmub = NULL; + union dmub_fw_boot_options option = {0}; + int ret = 0; + const uint32_t fb_size = 3 * 1024 * 1024; /* 3MB for DCC pattern */ + + if (!adev || !adev->dm.dc || !adev->dm.dc->ctx || + !adev->dm.dc->ctx->dmub_srv) { + return; + } + + dmub = adev->dm.dc->ctx->dmub_srv->dmub; + bootcrc_info = &adev->dm.boot_time_crc_info; + + if (!dmub || !dmub->hw_funcs.get_fw_boot_option) { + drm_dbg(adev_to_drm(adev), "failed to init boot time crc buffer\n"); + return; + } + + option = dmub->hw_funcs.get_fw_boot_option(dmub); + + /* Return if boot time CRC is not enabled */ + if (option.bits.bootcrc_en_at_S0i3 == 0) + return; + + /* Create a buffer for boot time CRC */ + ret = amdgpu_bo_create_kernel(adev, fb_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, + &bootcrc_info->bo_ptr, + &bootcrc_info->gpu_addr, + &bootcrc_info->cpu_addr); + + if (ret) { + drm_dbg(adev_to_drm(adev), "failed to create boot time crc buffer\n"); + } else { + bootcrc_info->size = fb_size; + + drm_dbg(adev_to_drm(adev), "boot time crc buffer created addr 0x%llx, size %u\n", + bootcrc_info->gpu_addr, bootcrc_info->size); + + /* Send the buffer info to DMUB */ + dc_dmub_srv_boot_time_crc_init(adev->dm.dc, + bootcrc_info->gpu_addr, bootcrc_info->size); + } +} + static int dm_late_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -2713,6 +2837,11 @@ static int dm_late_init(struct amdgpu_ip_block *ip_block) dmcu = adev->dm.dc->res_pool->dmcu; + /* Init the boot time CRC (skip in resume) */ + if ((adev->in_suspend == 0) && + (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 6, 0))) + amdgpu_dm_boot_time_crc_init(adev); + for (i = 0; i < 16; i++) linear_lut[i] = 0xFFFF * i / 15; @@ -2793,7 +2922,11 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) } } +#ifdef HAVE_DRM_DP_MST_BRANCH_GUID_T guid_copy(&mgr->mst_primary->guid, &guid); +#else + memcpy(mgr->mst_primary->guid, &guid, 16); +#endif out_fail: mutex_unlock(&mgr->lock); @@ -2816,9 +2949,11 @@ void hdmi_cec_set_edid(struct amdgpu_dm_connector *aconnector) if (!n) return; - + +#ifdef HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS cec_notifier_set_phys_addr(n, connector->display_info.source_physical_address); +#endif } static void s3_handle_hdmi_cec(struct drm_device *ddev, bool suspend) @@ -3468,7 +3603,17 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) struct dc_commit_streams_params commit_params = {}; if (dm->dc->caps.ips_support) { + if (!amdgpu_in_reset(adev)) + mutex_lock(&dm->dc_lock); + + /* Need to set POWER_STATE_D0 first or it will not execute + * idle_power_optimizations command to DMUB. + */ + dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false); + + if (!amdgpu_in_reset(adev)) + mutex_unlock(&dm->dc_lock); } if (amdgpu_in_reset(adev)) { @@ -3593,6 +3738,11 @@ static int dm_resume(struct amdgpu_ip_block *ip_block) if (aconnector->mst_root) continue; + /* Skip eDP detection, when there is no sink present */ + if (aconnector->dc_link->connector_signal == SIGNAL_TYPE_EDP && + !aconnector->dc_link->edp_sink_present) + continue; + guard(mutex)(&aconnector->hpd_lock); if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type)) drm_err(adev_to_drm(adev), "KMS: Failed to detect connector\n"); @@ -3706,23 +3856,31 @@ const struct amdgpu_ip_block_version dm_ip_block = { static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .get_format_info = amdgpu_dm_plane_get_format_info, +#endif .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = drm_atomic_helper_commit, }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT .atomic_commit_setup = amdgpu_dm_atomic_setup_commit, +#endif }; static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { +#ifdef HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK const struct drm_panel_backlight_quirk *panel_backlight_quirk; +#endif struct amdgpu_dm_backlight_caps *caps; struct drm_connector *conn_base; struct amdgpu_device *adev; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE struct drm_luminance_range_info *luminance_range; +#endif struct drm_device *drm; if (aconnector->bl_idx == -1 || @@ -3737,6 +3895,12 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps; caps->aux_support = false; +#if defined(HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY) + drm_object_property_set_value(&conn_base->base, + adev_to_drm(adev)->mode_config.panel_type_property, + caps->ext_caps->bits.oled ? DRM_MODE_PANEL_TYPE_OLED : DRM_MODE_PANEL_TYPE_UNKNOWN); +#endif + if (caps->ext_caps->bits.oled == 1 /* * || @@ -3752,6 +3916,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) if (caps->aux_support) aconnector->dc_link->backlight_control_type = BACKLIGHT_CONTROL_AMD_AUX; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE luminance_range = &conn_base->display_info.luminance_range; if (luminance_range->max_luminance) @@ -3763,7 +3928,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_min_input_signal = luminance_range->min_luminance; else caps->aux_min_input_signal = 1; +#endif +#ifdef HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK panel_backlight_quirk = drm_get_panel_backlight_quirk(aconnector->drm_edid); if (!IS_ERR_OR_NULL(panel_backlight_quirk)) { @@ -3782,6 +3949,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) panel_backlight_quirk->brightness_mask; } } +#endif } DEFINE_FREE(sink_release, struct dc_sink *, if (_T) dc_sink_release(_T)) @@ -3829,7 +3997,11 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); amdgpu_dm_update_freesync_caps(connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid); +#else + aconnector->edid); +#endif } else { amdgpu_dm_update_freesync_caps(connector, NULL); if (!aconnector->dc_sink) { @@ -3881,22 +4053,35 @@ void amdgpu_dm_update_connector_after_detect( aconnector->dc_sink = sink; dc_sink_retain(aconnector->dc_sink); +#ifdef HAVE_DRM_DP_MST_EDID_READ + drm_edid_free(aconnector->drm_edid); + aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif if (sink->dc_edid.length == 0) { - aconnector->drm_edid = NULL; hdmi_cec_unset_edid(aconnector); if (aconnector->dc_link->aux_mode) { drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); } } else { +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid = (const struct edid *)sink->dc_edid.raw_edid; - aconnector->drm_edid = drm_edid_alloc(edid, sink->dc_edid.length); drm_edid_connector_update(connector, aconnector->drm_edid); +#else + struct edid *edid = (struct edid *)sink->dc_edid.raw_edid; + aconnector->edid = edid; +#endif hdmi_cec_set_edid(aconnector); if (aconnector->dc_link->aux_mode) +#ifdef HAVE_DRM_DP_CEC_ATTACH drm_dp_cec_attach(&aconnector->dm_dp_aux.aux, connector->display_info.source_physical_address); +#else + drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux, edid); +#endif } if (!aconnector->timing_requested) { @@ -3907,7 +4092,11 @@ void amdgpu_dm_update_connector_after_detect( "failed to create aconnector->requested_timing\n"); } +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_update_freesync_caps(connector, aconnector->drm_edid); +#else + amdgpu_dm_update_freesync_caps(connector, aconnector->edid); +#endif update_connector_ext_caps(aconnector); } else { hdmi_cec_unset_edid(aconnector); @@ -3916,8 +4105,12 @@ void amdgpu_dm_update_connector_after_detect( aconnector->num_modes = 0; dc_sink_release(aconnector->dc_sink); aconnector->dc_sink = NULL; +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(aconnector->drm_edid); aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif kfree(aconnector->timing_requested); aconnector->timing_requested = NULL; /* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */ @@ -4144,7 +4337,7 @@ static void schedule_hpd_rx_offload_work(struct amdgpu_device *adev, struct hpd_ offload_work->adev = adev; queue_work(offload_wq->wq, &offload_work->work); - DRM_DEBUG_KMS("queue work to handle hpd_rx offload work"); + drm_dbg_kms(adev_to_drm(adev), "queue work to handle hpd_rx offload work"); } static void handle_hpd_rx_irq(void *param) @@ -4358,105 +4551,6 @@ static int register_hpd_handlers(struct amdgpu_device *adev) return 0; } -#if defined(CONFIG_DRM_AMD_DC_SI) -/* Register IRQ sources and initialize IRQ callbacks */ -static int dce60_register_irq_handlers(struct amdgpu_device *adev) -{ - struct dc *dc = adev->dm.dc; - struct common_irq_params *c_irq_params; - struct dc_interrupt_params int_params = {0}; - int r; - int i; - unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; - - int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; - int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; - - /* - * Actions of amdgpu_irq_add_id(): - * 1. Register a set() function with base driver. - * Base driver will call set() function to enable/disable an - * interrupt in DC hardware. - * 2. Register amdgpu_dm_irq_handler(). - * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts - * coming from DC hardware. - * amdgpu_dm_irq_handler() will re-direct the interrupt to DC - * for acknowledging and handling. - */ - - /* Use VBLANK interrupt */ - for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i + 1, 0); - - if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || - int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || - int_params.irq_source > DC_IRQ_SOURCE_VBLANK6) { - drm_err(adev_to_drm(adev), "Failed to register vblank irq!\n"); - return -EINVAL; - } - - c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; - - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; - - if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_crtc_high_irq, c_irq_params)) - return -ENOMEM; - } - - /* Use GRPH_PFLIP interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; - i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { - r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add page flip irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); - - if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || - int_params.irq_source < DC_IRQ_SOURCE_PFLIP_FIRST || - int_params.irq_source > DC_IRQ_SOURCE_PFLIP_LAST) { - drm_err(adev_to_drm(adev), "Failed to register pflip irq!\n"); - return -EINVAL; - } - - c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; - - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; - - if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_pflip_high_irq, c_irq_params)) - return -ENOMEM; - } - - /* HPD */ - r = amdgpu_irq_add_id(adev, client_id, - VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add hpd irq id!\n"); - return r; - } - - r = register_hpd_handlers(adev); - - return r; -} -#endif - /* Register IRQ sources and initialize IRQ callbacks */ static int dce110_register_irq_handlers(struct amdgpu_device *adev) { @@ -4465,7 +4559,12 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) struct dc_interrupt_params int_params = {0}; int r; int i; + unsigned int src_id; unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY; + /* Use different interrupts for VBLANK on DCE 6 vs. newer. */ + const unsigned int vblank_d1 = + adev->dm.dc->ctx->dce_version >= DCE_VERSION_8_0 + ? VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 : 1; if (adev->family >= AMDGPU_FAMILY_AI) client_id = SOC15_IH_CLIENTID_DCE; @@ -4486,8 +4585,9 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) */ /* Use VBLANK interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { - r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); + for (i = 0; i < adev->mode_info.num_crtc; i++) { + src_id = vblank_d1 + i; + r = amdgpu_irq_add_id(adev, client_id, src_id, &adev->crtc_irq); if (r) { drm_err(adev_to_drm(adev), "Failed to add crtc irq id!\n"); return r; @@ -4495,7 +4595,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); + dc_interrupt_to_irq_source(dc, src_id, 0); if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || int_params.irq_source < DC_IRQ_SOURCE_VBLANK1 || @@ -4514,33 +4614,36 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) return -ENOMEM; } - /* Use VUPDATE interrupt */ - for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { - r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq); - if (r) { - drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n"); - return r; - } - - int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; - int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); + if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) { + /* Use VUPDATE interrupt */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + src_id = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT + i * 2; + r = amdgpu_irq_add_id(adev, client_id, src_id, &adev->vupdate_irq); + if (r) { + drm_err(adev_to_drm(adev), "Failed to add vupdate irq id!\n"); + return r; + } - if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || - int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || - int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { - drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n"); - return -EINVAL; - } + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, src_id, 0); - c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; + if (int_params.irq_source == DC_IRQ_SOURCE_INVALID || + int_params.irq_source < DC_IRQ_SOURCE_VUPDATE1 || + int_params.irq_source > DC_IRQ_SOURCE_VUPDATE6) { + drm_err(adev_to_drm(adev), "Failed to register vupdate irq!\n"); + return -EINVAL; + } - c_irq_params->adev = adev; - c_irq_params->irq_src = int_params.irq_source; + c_irq_params = &adev->dm.vupdate_params[ + int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; - if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, - dm_vupdate_high_irq, c_irq_params)) - return -ENOMEM; + if (!amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_vupdate_high_irq, c_irq_params)) + return -ENOMEM; + } } /* Use GRPH_PFLIP interrupt */ @@ -4973,7 +5076,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, caps->min_input_signal < 0 || spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || spread < AMDGPU_DM_MIN_SPREAD) { - DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n", + drm_dbg_kms(adev_to_drm(dm->adev), "DM: Invalid backlight caps: min=%d, max=%d\n", caps->min_input_signal, caps->max_input_signal); caps->caps_valid = false; } @@ -5272,12 +5375,14 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) if (aconnector->bl_idx == -1) return; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(drm, "Skipping amdgpu DM backlight registration\n"); /* Try registering an ACPI video backlight device instead. */ acpi_video_register_backlight(); return; } +#endif caps = &dm->backlight_caps[aconnector->bl_idx]; if (get_brightness_range(caps, &min, &max)) { @@ -5395,7 +5500,7 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, caps = &dm->backlight_caps[aconnector->bl_idx]; /* Only offer ABM property when non-OLED and user didn't turn off by module parameter */ - if (!caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) + if (caps->ext_caps && !caps->ext_caps->bits.oled && amdgpu_dm_abm_level < 0) drm_object_attach_property(&aconnector->base.base, dm->adev->mode_info.abm_level_property, ABM_SYSFS_CONTROL); @@ -5512,13 +5617,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): if (register_outbox_irq_handlers(dm->adev)) { drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); goto fail; } break; default: - DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n", + drm_dbg_kms(adev_to_drm(adev), "Unsupported DCN IP version for outbox: 0x%X\n", amdgpu_ip_version(adev, DCE_HWIP, 0)); } @@ -5536,6 +5642,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): psr_feature_enabled = true; break; default: @@ -5668,11 +5775,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_PITCAIRN: case CHIP_VERDE: case CHIP_OLAND: - if (dce60_register_irq_handlers(dm->adev)) { - drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); - goto fail; - } - break; #endif case CHIP_BONAIRE: case CHIP_HAWAII: @@ -5718,6 +5820,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): if (dcn10_register_irq_handlers(dm->adev)) { drm_err(adev_to_drm(adev), "DM: Failed to initialize IRQ\n"); goto fail; @@ -5866,6 +5969,9 @@ static int dm_init_microcode(struct amdgpu_device *adev) case IP_VERSION(4, 0, 1): fw_name_dmub = FIRMWARE_DCN_401_DMUB; break; + case IP_VERSION(4, 2, 0): + fw_name_dmub = FIRMWARE_DCN_42_DMUB; + break; default: /* ASIC doesn't support DMUB. */ return 0; @@ -5993,6 +6099,7 @@ static int dm_early_init(struct amdgpu_ip_block *ip_block) case IP_VERSION(3, 5, 1): case IP_VERSION(3, 6, 0): case IP_VERSION(4, 0, 1): + case IP_VERSION(4, 2, 0): adev->mode_info.num_crtc = 4; adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; @@ -6009,8 +6116,8 @@ static int dm_early_init(struct amdgpu_ip_block *ip_block) adev->mode_info.funcs = &dm_display_funcs; /* - * Note: Do NOT change adev->audio_endpt_rreg and - * adev->audio_endpt_wreg because they are initialised in + * Note: Do NOT change adev->reg.audio_endpt.rreg and + * adev->reg.audio_endpt.wreg because they are initialised in * amdgpu_device_init() */ #if defined(CONFIG_DEBUG_KERNEL_DC) @@ -6048,8 +6155,10 @@ fill_plane_color_attributes(const struct drm_plane_state *plane_state, *color_space = COLOR_SPACE_SRGB; /* Ignore properties when DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE is set */ +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE if (plane_state->state && plane_state->state->plane_color_pipeline) return 0; +#endif /* DRM color properties only affect non-RGB formats. */ if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -6131,9 +6240,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_NV12: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; +#ifdef DRM_FORMAT_P010 case DRM_FORMAT_P010: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; break; +#endif case DRM_FORMAT_XRGB16161616F: case DRM_FORMAT_ARGB16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; @@ -6142,6 +6253,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; break; +#ifdef DRM_FORMAT_XRGB16161616 case DRM_FORMAT_XRGB16161616: case DRM_FORMAT_ARGB16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; @@ -6150,6 +6262,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; break; +#endif default: drm_err(adev_to_drm(adev), "Unsupported screen format %p4cc\n", @@ -6175,7 +6288,6 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, break; } - plane_info->visible = true; plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; @@ -6421,7 +6533,8 @@ static void fill_dc_dirty_rects(struct drm_plane *plane, &flip_addrs->dirty_rect_count, true); } -static void update_stream_scaling_settings(const struct drm_display_mode *mode, +static void update_stream_scaling_settings(struct drm_device *dev, + const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, struct dc_stream_state *stream) { @@ -6471,8 +6584,8 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode, stream->src = src; stream->dst = dst; - DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", - dst.x, dst.y, dst.width, dst.height); + drm_dbg_kms(dev, "Destination Rectangle x:%d y:%d width:%d height:%d\n", + dst.x, dst.y, dst.width, dst.height); } @@ -6482,6 +6595,10 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, { u8 bpc; + bpc = (uint8_t)connector->display_info.bpc; + /* Assume 8 bpc by default if no bpc is specified. */ + bpc = bpc ? bpc : 8; + if (is_y420) { bpc = 8; @@ -6492,10 +6609,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, bpc = 12; else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; - } else { - bpc = (uint8_t)connector->display_info.bpc; - /* Assume 8 bpc by default if no bpc is specified. */ - bpc = bpc ? bpc : 8; } if (requested_bpc > 0) { @@ -6545,6 +6658,7 @@ get_aspect_ratio(const struct drm_display_mode *mode_in) return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; } +#ifdef HAVE_DRM_CONNECTOR_STATE_COLORSPACE static enum dc_color_space get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, const struct drm_connector_state *connector_state) @@ -6578,8 +6692,10 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, default: if (dc_crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB) { color_space = COLOR_SPACE_SRGB; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if (connector_state->hdmi.broadcast_rgb == DRM_HDMI_BROADCAST_RGB_LIMITED) color_space = COLOR_SPACE_SRGB_LIMITED; +#endif /* * 27030khz is the separation point between HDTV and SDTV * according to HDMI spec, we use YCbCr709 and YCbCr601 @@ -6603,6 +6719,51 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, return color_space; } +#else +static enum dc_color_space +get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, + const struct drm_connector_state *connector_state) +{ + enum dc_color_space color_space = COLOR_SPACE_SRGB; + + switch (dc_crtc_timing->pixel_encoding) { + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR444: + case PIXEL_ENCODING_YCBCR420: + { + /* + * 27030khz is the separation point between HDTV and SDTV + * according to HDMI spec, we use YCbCr709 and YCbCr601 + * respectively + */ + if (dc_crtc_timing->pix_clk_100hz > 270300) { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR709_LIMITED; + else + color_space = COLOR_SPACE_YCBCR709; + } else { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR601_LIMITED; + else + color_space = COLOR_SPACE_YCBCR601; + } + + } + break; + case PIXEL_ENCODING_RGB: + color_space = COLOR_SPACE_SRGB; + break; + + default: + WARN_ON(1); + break; + } + + return color_space; +} +#endif static enum display_content_type get_output_content_type(const struct drm_connector_state *connector_state) @@ -6723,12 +6884,18 @@ static void fill_stream_properties_from_drm_display_mode( } if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); if (err < 0) drm_warn_once(connector->dev, "Failed to setup avi infoframe on connector %s: %zd\n", connector->name, err); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in, false); +#else + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; err = drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, @@ -6936,7 +7103,6 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) for (i = 0; i < context->stream_count ; i++) { stream = context->streams[i]; - if (!stream) continue; @@ -7007,7 +7173,6 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, return NULL; } } - highest_refresh = drm_mode_vrefresh(m_pref); /* @@ -7148,8 +7313,15 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, struct dc *dc = sink->ctx->dc; u32 max_supported_bw_in_kbps, timing_bw_in_kbps; u32 dsc_max_supported_bw_in_kbps; +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP u32 max_dsc_target_bpp_limit_override = drm_connector->display_info.max_dsc_bpp; +#else + u32 max_dsc_target_bpp_limit_override = 0; + if (stream->link && stream->link->local_sink) + max_dsc_target_bpp_limit_override = + stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit; +#endif struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(dc, &dsc_options); @@ -7271,7 +7443,6 @@ create_stream_for_sink(struct drm_connector *connector, sink = aconnector->dc_sink; dc_sink_retain(sink); } - stream = dc_create_stream_for_sink(sink); if (stream == NULL) { @@ -7360,7 +7531,7 @@ create_stream_for_sink(struct drm_connector *connector, apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); #endif - update_stream_scaling_settings(&mode, dm_state, stream); + update_stream_scaling_settings(dev, &mode, dm_state, stream); fill_audio_info( &stream->audio_info, @@ -7434,7 +7605,7 @@ amdgpu_dm_connector_poll(struct amdgpu_dm_connector *aconnector, bool force) * * Only allow to poll such a connector again when forcing. */ - if (!force && link->local_sink && link->type == dc_connection_dac_load) + if (!force && link->local_sink && link->type == dc_connection_analog_load) return connector->status; mutex_lock(&aconnector->hpd_lock); @@ -7715,6 +7886,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) return false; +#ifdef HAVE_HDR_SINK_METADATA /* check for OLED panels */ if (amdgpu_dm_connector->bl_idx >= 0) { struct drm_device *drm = amdgpu_dm_connector->base.dev; @@ -7725,6 +7897,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (caps->aux_support) return false; } +#endif return true; } @@ -7735,11 +7908,11 @@ static void amdgpu_dm_connector_unregister(struct drm_connector *connector) if (amdgpu_dm_should_create_sysfs(amdgpu_dm_connector)) sysfs_remove_group(&connector->kdev->kobj, &amdgpu_group); - +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER cec_notifier_conn_unregister(amdgpu_dm_connector->notifier); +#endif drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); } - static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7778,7 +7951,6 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree(aconnector->dm_dp_aux.aux.name); - kfree(connector); } @@ -7800,8 +7972,10 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_hborder = 0; state->underscan_vborder = 0; state->base.max_requested_bpc = 8; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) state->vcpi_slots = 0; state->pbn = 0; +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { if (amdgpu_dm_abm_level <= 0) @@ -7834,8 +8008,10 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) new_state->underscan_enable = state->underscan_enable; new_state->underscan_hborder = state->underscan_hborder; new_state->underscan_vborder = state->underscan_vborder; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) new_state->vcpi_slots = state->vcpi_slots; new_state->pbn = state->pbn; +#endif return &new_state->base; } @@ -7870,14 +8046,16 @@ amdgpu_dm_connector_late_register(struct drm_connector *connector) return 0; } +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dc_link *dc_link = aconnector->dc_link; struct dc_sink *dc_em_sink = aconnector->dc_em_sink; + struct drm_device *dev = connector->dev; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; struct i2c_adapter *ddc; - struct drm_device *dev = connector->dev; if (dc_link && dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; @@ -7887,15 +8065,39 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { +#else + struct edid *edid; + struct i2c_adapter *ddc; + + if (dc_link && dc_link->aux_mode) + ddc = &aconnector->dm_dp_aux.aux.ddc; + else + ddc = &aconnector->i2c->base; + + /* + * Note: drm_get_edid gets edid in the following order: + * 1) override EDID if set via edid_override debugfs, + * 2) firmware EDID if set via edid_firmware module parameter + * 3) regular DDC read. + */ + edid = drm_get_edid(connector, ddc); + if (!edid) { +#endif drm_err(dev, "No EDID found on connector: %s.\n", connector->name); return; } +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid; +#else + aconnector->edid = edid; +#endif /* Update emulated (virtual) sink's EDID */ if (dc_em_sink && dc_link) { +#ifdef HAVE_DRM_DP_MST_EDID_READ // FIXME: Get rid of drm_edid_raw() const struct edid *edid = drm_edid_raw(drm_edid); +#endif memset(&dc_em_sink->edid_caps, 0, sizeof(struct dc_edid_caps)); memmove(dc_em_sink->dc_edid.raw_edid, edid, @@ -7906,6 +8108,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) &dc_em_sink->edid_caps); } } +#endif static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .reset = amdgpu_dm_connector_funcs_reset, @@ -7918,7 +8121,9 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .atomic_get_property = amdgpu_dm_connector_atomic_get_property, .late_register = amdgpu_dm_connector_late_register, .early_unregister = amdgpu_dm_connector_unregister, +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE .force = amdgpu_dm_connector_funcs_force +#endif }; static int get_modes(struct drm_connector *connector) @@ -7934,9 +8139,10 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_VIRTUAL }; + struct i2c_adapter *ddc; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; const struct edid *edid; - struct i2c_adapter *ddc; if (dc_link && dc_link->aux_mode) ddc = &aconnector->dm_dp_aux.aux.ddc; @@ -7946,16 +8152,40 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) { +#else + struct edid *edid; + + if (dc_link->aux_mode) + ddc = &aconnector->dm_dp_aux.aux.ddc; + else + ddc = &aconnector->i2c->base; + + /* + * Note: drm_get_edid gets edid in the following order: + * 1) override EDID if set via edid_override debugfs, + * 2) firmware EDID if set via edid_firmware module parameter + * 3) regular DDC read. + */ + edid = drm_get_edid(connector, ddc); + if (!edid) { +#endif drm_err(connector->dev, "No EDID found on connector: %s.\n", connector->name); return; } +#ifdef HAVE_DRM_DP_MST_EDID_READ if (connector->display_info.is_hdmi) init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; aconnector->drm_edid = drm_edid; edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#else + if (drm_detect_hdmi_monitor(edid)) + init_params.sink_signal = SIGNAL_TYPE_HDMI_TYPE_A; + + aconnector->edid = edid; +#endif aconnector->dc_em_sink = dc_link_add_remote_sink( aconnector->dc_link, (uint8_t *)edid, @@ -8097,7 +8327,7 @@ create_validate_stream_for_sink(struct drm_connector *connector, dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); if (dc_result != DC_OK) { - DRM_DEBUG_KMS("Pruned mode %d x %d (clk %d) %s %s -- %s\n", + drm_dbg_kms(connector->dev, "Pruned mode %d x %d (clk %d) %s %s -- %s\n", drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->clock, @@ -8153,7 +8383,11 @@ create_validate_stream_for_sink(struct drm_connector *connector, } enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode) +#else + struct drm_display_mode *mode) +#endif { int result = MODE_ERROR; struct dc_sink *dc_sink; @@ -8205,6 +8439,7 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec return result; } +#ifdef HDMI_DRM_INFOFRAME_SIZE static int fill_hdr_info_packet(const struct drm_connector_state *state, struct dc_info_packet *out) { @@ -8266,15 +8501,23 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *new_con_state = drm_atomic_get_new_connector_state(state, conn); +#else + struct drm_connector_state *new_con_state) +{ + struct drm_atomic_state *state = new_con_state->state; +#endif struct drm_connector_state *old_con_state = drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; struct drm_crtc_state *new_crtc_state; +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); +#endif int ret; if (WARN_ON(unlikely(!old_con_state || !new_con_state))) @@ -8283,14 +8526,16 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, trace_amdgpu_dm_connector_atomic_check(new_con_state); if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); if (ret < 0) return ret; +#endif } if (!crtc) return 0; - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN if (new_con_state->privacy_screen_sw_state != old_con_state->privacy_screen_sw_state) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8298,7 +8543,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, new_crtc_state->mode_changed = true; } - +#endif if (new_con_state->colorspace != old_con_state->colorspace) { new_crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(new_crtc_state)) @@ -8344,6 +8589,22 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } +#endif + +static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + struct drm_encoder *encoder; + + /* There is only one encoder per connector */ + drm_connector_for_each_possible_encoder(connector, encoder) + return encoder; + + return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif +} static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = { @@ -8355,7 +8616,10 @@ amdgpu_dm_connector_helper_funcs = { */ .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, +#ifdef HDMI_DRM_INFOFRAME_SIZE .atomic_check = amdgpu_dm_connector_atomic_check, +#endif + .best_encoder = amdgpu_dm_connector_to_encoder }; static void dm_encoder_helper_disable(struct drm_encoder *encoder) @@ -8388,6 +8652,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) struct drm_atomic_state *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -8395,7 +8660,9 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) struct drm_dp_mst_topology_state *mst_state; +#endif enum dc_color_depth color_depth; int clock, bpp = 0; bool is_y420 = false; @@ -8426,11 +8693,16 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION mst_state->pbn_div.full = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#else + mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#endif +#endif if (!state->duplicated) { int max_bpc = conn_state->max_requested_bpc; @@ -8442,16 +8714,21 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, max_bpc); bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; clock = adjusted_mode->clock; - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, - dm_new_connector_state->pbn); + dm_new_connector_state->pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(aconnector->dc_link) +#endif + ); if (dm_new_connector_state->vcpi_slots < 0) { - DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); + drm_dbg_atomic(connector->dev, "failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; } +#endif return 0; } @@ -8460,6 +8737,7 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) @@ -8520,14 +8798,22 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, dm_conn_state->vcpi_slots = slot_num; ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, - dm_conn_state->pbn, false); + dm_conn_state->pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + false); if (ret < 0) return ret; continue; } - vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); + vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + true); if (vcpi < 0) return vcpi; @@ -8536,6 +8822,7 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, } return 0; } +#endif static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) { @@ -8550,6 +8837,12 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) return DRM_MODE_CONNECTOR_VGA; case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: + /* External DP bridges have a different connector type. */ + if (connector_id == CONNECTOR_ID_VGA) + return DRM_MODE_CONNECTOR_VGA; + else if (connector_id == CONNECTOR_ID_LVDS) + return DRM_MODE_CONNECTOR_LVDS; + return DRM_MODE_CONNECTOR_DisplayPort; case SIGNAL_TYPE_DVI_DUAL_LINK: case SIGNAL_TYPE_DVI_SINGLE_LINK: @@ -8566,17 +8859,6 @@ static int to_drm_connector_type(enum signal_type st, uint32_t connector_id) } } -static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) -{ - struct drm_encoder *encoder; - - /* There is only one encoder per connector */ - drm_connector_for_each_possible_encoder(connector, encoder) - return encoder; - - return NULL; -} - static void amdgpu_dm_get_native_mode(struct drm_connector *connector) { struct drm_encoder *encoder; @@ -8728,17 +9010,28 @@ static void amdgpu_set_panel_orientation(struct drm_connector *connector) } static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (drm_edid) { +#else + if (edid) { +#endif /* empty probed_modes */ INIT_LIST_HEAD(&connector->probed_modes); amdgpu_dm_connector->num_modes = +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_add_modes(connector); - +#else + drm_add_edid_modes(connector, edid); +#endif /* sorting the probed modes before calling function * amdgpu_dm_get_native_mode() since EDID can have * more than one preferred mode. The modes that are @@ -8754,7 +9047,11 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, * drm_edid_connector_add_modes() and need to be * restored here. */ +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_update_freesync_caps(connector, drm_edid); +#else + amdgpu_dm_update_freesync_caps(connector, edid); +#endif } else { amdgpu_dm_connector->num_modes = 0; } @@ -8821,6 +9118,10 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) num = (unsigned long long)m->clock * 1000 * 1000; den = common_rates[i] * (unsigned long long)m->htotal; target_vtotal = div_u64(num, den); + + if (target_vtotal < m->vtotal) + continue; + target_vtotal_diff = target_vtotal - m->vtotal; /* Check for illegal modes */ @@ -8850,12 +9151,20 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) } static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!(amdgpu_freesync_vid_mode && drm_edid)) +#else + if (!(amdgpu_freesync_vid_mode && edid)) +#endif return; if (!amdgpu_dm_connector->dc_sink || !amdgpu_dm_connector->dc_link) @@ -8879,13 +9188,21 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) to_amdgpu_dm_connector(connector); struct dc_link *dc_link = amdgpu_dm_connector->dc_link; struct drm_encoder *encoder; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid = amdgpu_dm_connector->drm_edid; +#else + struct edid *edid = amdgpu_dm_connector->edid; +#endif struct dc_link_settings *verified_link_cap = &dc_link->verified_link_cap; const struct dc *dc = dc_link->dc; encoder = amdgpu_dm_connector_to_encoder(connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid) { +#else + if (!edid) { +#endif amdgpu_dm_connector->num_modes = drm_add_modes_noedid(connector, 640, 480); if (dc->link_srv->dp_get_encoding_format(verified_link_cap) == DP_128b_132b_ENCODING) @@ -8903,10 +9220,18 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) connector, common_modes[i].w, common_modes[i].h); } } else { +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_ddc_get_modes(connector, drm_edid); +#else + amdgpu_dm_connector_ddc_get_modes(connector, edid); +#endif if (encoder) amdgpu_dm_connector_add_common_modes(encoder, connector); +#ifdef HAVE_DRM_DP_MST_EDID_READ amdgpu_dm_connector_add_freesync_modes(connector, drm_edid); +#else + amdgpu_dm_connector_add_freesync_modes(connector, edid); +#endif } amdgpu_dm_fbc_init(connector); @@ -8996,9 +9321,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, dm->ddev->mode_config.scaling_mode_property, DRM_MODE_SCALE_NONE); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if (connector_type == DRM_MODE_CONNECTOR_HDMIA || (connector_type == DRM_MODE_CONNECTOR_DisplayPort && !aconnector->mst_root)) drm_connector_attach_broadcast_rgb_property(&aconnector->base); +#endif drm_object_attach_property(&aconnector->base.base, adev->mode_info.underscan_property, @@ -9033,18 +9360,27 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_HDMIA || connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_connector_attach_hdr_output_metadata_property(&aconnector->base); if (!aconnector->mst_root) drm_connector_attach_vrr_capable_property(&aconnector->base); if (adev->dm.hdcp_workqueue) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE drm_connector_attach_content_protection_property(&aconnector->base, true); +#else + drm_connector_attach_content_protection_property(&aconnector->base); +#endif } - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN if (connector_type == DRM_MODE_CONNECTOR_eDP) { struct drm_privacy_screen *privacy_screen; +#if defined(HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY) + drm_connector_attach_panel_type_property(&aconnector->base); +#endif + privacy_screen = drm_privacy_screen_get(adev_to_drm(adev)->dev, NULL); if (!IS_ERR(privacy_screen)) { drm_connector_attach_privacy_screen_provider(&aconnector->base, @@ -9053,6 +9389,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_warn(adev_to_drm(adev), "Error getting privacy-screen\n"); } } +#endif } static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -9146,12 +9483,14 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector) } cec_fill_conn_info_from_drm(&conn_info, &aconnector->base); +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER aconnector->notifier = cec_notifier_conn_register(hdmi_dev, NULL, &conn_info); if (!aconnector->notifier) { drm_err(ddev, "Failed to create cec notifier\n"); return -ENOMEM; } +#endif return 0; } @@ -9222,8 +9561,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, connector_type == DRM_MODE_CONNECTOR_HDMIB) amdgpu_dm_initialize_hdmi_connector(aconnector); - if (connector_type == DRM_MODE_CONNECTOR_DisplayPort - || connector_type == DRM_MODE_CONNECTOR_eDP) + if (dc_is_dp_signal(link->connector_signal)) amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index); out_free: @@ -9285,6 +9623,7 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, * backend index - some even map to more than one. * So we have to go through the CRTC to find the right IRQ. */ +#ifdef HAVE_DRM_VBLANK_CRTC_CONFIG int irq_type = amdgpu_display_crtc_idx_to_irq_type( adev, acrtc->crtc_id); @@ -9373,6 +9712,12 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, drm_crtc_vblank_off(&acrtc->base); } +#else + if (acrtc_state) + drm_crtc_vblank_on(&acrtc->base); + else + drm_crtc_vblank_off(&acrtc->base); +#endif } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, @@ -9437,6 +9782,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat new_crtc_state->active_changed, new_crtc_state->connectors_changed); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE /* hdcp content type change */ if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { @@ -9444,6 +9790,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); return true; } +#endif /* CP is being re enabled, ignore this */ if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && @@ -9642,7 +9989,7 @@ static void update_freesync_state_on_stream( new_stream->allow_freesync = mod_freesync_get_freesync_enabled(&vrr_params); if (new_crtc_state->freesync_vrr_info_changed) - DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d", + drm_dbg_kms(adev_to_drm(adev), "VRR packet update: crtc=%u enabled=%d state=%d", new_crtc_state->base.crtc->base.id, (int)new_crtc_state->base.vrr_enabled, (int)vrr_params.state); @@ -9853,7 +10200,7 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, } /* Decrement skip count when SR is enabled and we're doing fast updates. */ - if (acrtc_state->update_type == UPDATE_TYPE_FAST && + if (acrtc_state->update_type <= UPDATE_TYPE_FAST && (psr->psr_feature_enabled || pr->config.replay_supported)) { if (aconn->sr_skip_count > 0) aconn->sr_skip_count--; @@ -9866,7 +10213,8 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach, * a vblank event disable request to enable PSR/RP. PSR SU/RP * can be enabled immediately once OS demonstrates an * adequate number of fast atomic commits to notify KMD - * of update events. See `vblank_control_worker()`. + * of update events. + * See `amdgpu_dm_crtc_vblank_control_worker()`. */ if (!vrr_active && acrtc_attach->dm_irq_params.allow_sr_entry && @@ -10016,7 +10364,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, afb->tmz_surface); drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", - new_plane_state->plane->index, + drm_plane_index(new_plane_state->plane), bundle->plane_infos[planes_count].dcc.enable); bundle->surface_updates[planes_count].plane_info = @@ -10034,8 +10382,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, /* * If the dirty regions changed, PSR-SU need to be disabled temporarily * and enabled it again after dirty regions are stable to avoid video glitch. - * PSR-SU will be enabled in vblank_control_worker() if user pause the video - * during the PSR-SU was disabled. + * PSR-SU will be enabled in + * amdgpu_dm_crtc_vblank_control_worker() if user + * pause the video during the PSR-SU was disabled. */ if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 && acrtc_attach->dm_irq_params.allow_sr_entry && @@ -10060,16 +10409,26 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * dm_crtc_helper_atomic_check() only accepts async flips with * fast updates. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc->state->async_flip && - (acrtc_state->update_type != UPDATE_TYPE_FAST || +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif + (acrtc_state->update_type > UPDATE_TYPE_FAST || get_mem_type(old_plane_state->fb) != get_mem_type(fb))) drm_warn_once(state->dev, "[PLANE:%d:%s] async flip with non-fast update\n", plane->base.id, plane->name); bundle->flip_addrs[planes_count].flip_immediate = +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) crtc->state->async_flip && - acrtc_state->update_type == UPDATE_TYPE_FAST && +#else + (crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif + acrtc_state->update_type <= UPDATE_TYPE_FAST && get_mem_type(old_plane_state->fb) == get_mem_type(fb); timestamp_ns = ktime_get_ns(); @@ -10422,7 +10781,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, } for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { + new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); @@ -10537,7 +10896,58 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, dm_enable_per_frame_crtc_master_sync(dc_state); mutex_lock(&dm->dc_lock); dc_exit_ips_for_hw_access(dm->dc); - WARN_ON(!dc_commit_streams(dm->dc, ¶ms)); + + /* if commit_status isn't DC_OK, the cable has been pushed to its limits */ + enum dc_status commit_status = dc_commit_streams(dm->dc, ¶ms); + + if (commit_status != DC_OK) { + struct drm_plane *plane; + struct drm_plane_state *new_plane_state; + + drm_err(dev, "Display Core failed to commit streams due to link failure! Rolling back pinned framebuffers.\n"); + WARN_ON(1); + + /* release planes, unpin GTT memory */ + for_each_new_plane_in_state(state, plane, new_plane_state, i) { + const struct drm_plane_helper_funcs *funcs = plane->helper_private; + + if (funcs && funcs->cleanup_fb && new_plane_state->fb) { + drm_dbg_atomic(dev, + "Manually freeing stranded plane framebuffer allocation [ID: %d]\n", + plane->base.id); + funcs->cleanup_fb(plane, new_plane_state); + } + } + + /* release streams and vram */ + for (i = 0; i < state->num_connector; i++) { + struct drm_connector_state *new_con_state = state->connectors[i].new_state; + + if (new_con_state && new_con_state->crtc) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_con_state->crtc); + struct dm_crtc_state *dm_new_state = to_dm_crtc_state( + drm_atomic_get_new_crtc_state(state, &acrtc->base) + ); + + if (dm_new_state && dm_new_state->stream) { + dc_stream_release(dm_new_state->stream); + dm_new_state->stream = NULL; + } + } + } + + /* release dc state */ + struct dm_atomic_state *dm_state = dm_atomic_get_new_state(state); + + if (dm_state && dm_state->context) { + dc_state_release(dm_state->context); + dm_state->context = NULL; + } + + /* Release the engine lock safely and abandon the rest of the configuration */ + mutex_unlock(&dm->dc_lock); + return; + } /* Allow idle optimization when vblank count is 0 for display off */ if ((dm->active_vblank_irq_count == 0) && amdgpu_dm_is_headless(dm->adev)) @@ -10648,10 +11058,10 @@ static void dm_set_writeback(struct amdgpu_display_manager *dm, wb_info->dwb_params.capture_rate = dwb_capture_rate_0; - wb_info->dwb_params.scaler_taps.h_taps = 4; - wb_info->dwb_params.scaler_taps.v_taps = 4; - wb_info->dwb_params.scaler_taps.h_taps_c = 2; - wb_info->dwb_params.scaler_taps.v_taps_c = 2; + wb_info->dwb_params.scaler_taps.h_taps = 1; + wb_info->dwb_params.scaler_taps.v_taps = 1; + wb_info->dwb_params.scaler_taps.h_taps_c = 1; + wb_info->dwb_params.scaler_taps.v_taps_c = 1; wb_info->dwb_params.subsample_position = DWB_INTERSTITIAL_SUBSAMPLING; wb_info->mcif_buf_params.luma_pitch = afb->base.pitches[0]; @@ -10767,6 +11177,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) enable_encryption = true; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_link && aconnector->dc_sink && aconnector->dc_link->type == dc_connection_mst_branch) { struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; @@ -10778,6 +11189,7 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) hdcp_w->content_protection[connector->index] = new_con_state->content_protection; } +#endif if (new_crtc_state && new_crtc_state->mode_changed && new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) @@ -10788,11 +11200,17 @@ static void amdgpu_dm_update_hdcp(struct drm_atomic_state *state) if (aconnector->dc_link) hdcp_update_display( adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, - new_con_state->hdcp_content_type, enable_encryption); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + new_con_state->hdcp_content_type, +#else + DRM_MODE_HDCP_CONTENT_TYPE0, +#endif + enable_encryption); } } } +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) { struct drm_crtc *crtc; @@ -10825,6 +11243,7 @@ static int amdgpu_dm_atomic_setup_commit(struct drm_atomic_state *state) return 0; } +#endif /** * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. @@ -10854,7 +11273,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) trace_amdgpu_dm_atomic_commit_tail_begin(state); drm_atomic_helper_update_legacy_modeset_state(dev, state); +#ifdef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES drm_dp_mst_atomic_wait_for_dependencies(state); +#endif dm_state = dm_atomic_get_new_state(state); if (dm_state && dm_state->context) { @@ -10871,9 +11292,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); struct dc_surface_update *dummy_updates; struct dc_stream_update stream_update; - struct dc_info_packet hdr_packet; struct dc_stream_status *status = NULL; - bool abm_changed, hdr_changed, scaling_changed, output_color_space_changed = false; +#ifdef HDMI_DRM_INFOFRAME_SIZE + struct dc_info_packet hdr_packet; + bool hdr_changed; +#endif + bool abm_changed, scaling_changed, output_color_space_changed = false; memset(&stream_update, 0, sizeof(stream_update)); @@ -10892,23 +11316,31 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) scaling_changed = is_scaling_state_different(dm_new_con_state, dm_old_con_state); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB if ((new_con_state->hdmi.broadcast_rgb != old_con_state->hdmi.broadcast_rgb) && (dm_old_crtc_state->stream->output_color_space != get_output_color_space(&dm_new_crtc_state->stream->timing, new_con_state))) output_color_space_changed = true; +#endif abm_changed = dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE hdr_changed = !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); +#endif - if (!scaling_changed && !abm_changed && !hdr_changed && !output_color_space_changed) + if (!scaling_changed && !abm_changed && !output_color_space_changed +#ifdef HDMI_DRM_INFOFRAME_SIZE + && !hdr_changed +#endif + ) continue; stream_update.stream = dm_new_crtc_state->stream; if (scaling_changed) { - update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, + update_stream_scaling_settings(dev, &dm_new_con_state->base.crtc->mode, dm_new_con_state, dm_new_crtc_state->stream); stream_update.src = dm_new_crtc_state->stream->src; @@ -10928,10 +11360,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) stream_update.abm_level = &dm_new_crtc_state->abm_level; } +#ifdef HDMI_DRM_INFOFRAME_SIZE if (hdr_changed) { fill_hdr_info_packet(new_con_state, &hdr_packet); stream_update.hdr_static_metadata = &hdr_packet; } +#endif status = dc_stream_get_status(dm_new_crtc_state->stream); @@ -10951,7 +11385,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) continue; } for (j = 0; j < status->plane_count; j++) - dummy_updates[j].surface = status->plane_states[0]; + dummy_updates[j].surface = status->plane_states[j]; sort(dummy_updates, status->plane_count, sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL); @@ -10965,8 +11399,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) &stream_update); mutex_unlock(&dm->dc_lock); kfree(dummy_updates); - +#ifdef HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN drm_connector_update_privacy_screen(new_con_state); +#endif } /** @@ -11043,7 +11478,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip) +#else + if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) +#endif wait_for_vblank = false; /* update planes when needed per crtc*/ @@ -11462,10 +11901,12 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE ret = fill_hdr_info_packet(drm_new_conn_state, &new_stream->hdr_static_metadata); if (ret) goto fail; +#endif /* * If we already removed the old stream from the context @@ -11588,7 +12029,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dc_stream_retain(new_stream); - DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n", + drm_dbg_atomic(adev_to_drm(adev), "Enabling DRM crtc: %d\n", crtc->base.id); if (dc_state_add_stream( @@ -11627,7 +12068,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, /* Scaling or underscan settings */ if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) || drm_atomic_crtc_needs_modeset(new_crtc_state)) - update_stream_scaling_settings( + update_stream_scaling_settings(adev_to_drm(adev), &new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream); /* ABM settings */ @@ -11667,6 +12108,8 @@ static bool should_reset_plane(struct drm_atomic_state *state, struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state; struct amdgpu_device *adev = drm_to_adev(plane->dev); + struct drm_connector_state *new_con_state; + struct drm_connector *connector; int i; /* @@ -11677,6 +12120,15 @@ static bool should_reset_plane(struct drm_atomic_state *state, state->allow_modeset) return true; + /* Check for writeback commit */ + for_each_new_connector_in_state(state, connector, new_con_state, i) { + if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK) + continue; + + if (new_con_state->writeback_job) + return true; + } + if (amdgpu_in_reset(adev) && state->allow_modeset) return true; @@ -11818,14 +12270,14 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, if (fb->width > new_acrtc->max_cursor_width || fb->height > new_acrtc->max_cursor_height) { - DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n", + drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB size %dx%d\n", new_plane_state->fb->width, new_plane_state->fb->height); return -EINVAL; } if (new_plane_state->src_w != fb->width << 16 || new_plane_state->src_h != fb->height << 16) { - DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); + drm_dbg_atomic(adev_to_drm(adev), "Cropping not supported for cursor plane\n"); return -EINVAL; } @@ -11833,7 +12285,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, pitch = fb->pitches[0] / fb->format->cpp[0]; if (fb->width != pitch) { - DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d", + drm_dbg_atomic(adev_to_drm(adev), "Cursor FB width %d doesn't match pitch %d", fb->width, pitch); return -EINVAL; } @@ -11845,7 +12297,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, /* FB pitch is supported by cursor plane */ break; default: - DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch); + drm_dbg_atomic(adev_to_drm(adev), "Bad cursor FB pitch %d px\n", pitch); return -EINVAL; } @@ -11853,7 +12305,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, * check tiling flags when the FB doesn't have a modifier. */ if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) { - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { linear = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE) == 0; } else if (adev->family >= AMDGPU_FAMILY_AI) { linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0; @@ -11863,7 +12315,7 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; } if (!linear) { - DRM_DEBUG_ATOMIC("Cursor FB not linear"); + drm_dbg_atomic(adev_to_drm(adev), "Cursor FB not linear"); return -EINVAL; } } @@ -11890,7 +12342,7 @@ static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, new_acrtc = to_amdgpu_crtc(new_plane_crtc); if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) { - DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n"); + drm_dbg_atomic(new_plane_crtc->dev, "Cropping not supported for cursor plane\n"); return -EINVAL; } @@ -11989,7 +12441,7 @@ static int dm_update_plane_state(struct dc *dc, if (!dm_old_crtc_state->stream) return 0; - DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", + drm_dbg_atomic(old_plane_crtc->dev, "Disabling DRM plane: %d on DRM crtc %d\n", plane->base.id, old_plane_crtc->base.id); ret = dm_atomic_get_state(state, &dm_state); @@ -12042,7 +12494,7 @@ static int dm_update_plane_state(struct dc *dc, goto out; } - DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n", + drm_dbg_atomic(new_plane_crtc->dev, "Enabling DRM plane: %d on DRM crtc %d\n", plane->base.id, new_plane_crtc->base.id); ret = fill_dc_plane_attributes( @@ -12192,6 +12644,7 @@ static inline struct __drm_planes_state *__get_next_zpos( (old_plane_state) = __i->old_state, \ (new_plane_state) = __i->new_state, 1)) +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) { struct drm_connector *connector; @@ -12221,6 +12674,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); } +#endif /** * DOC: Cursor Modes - Native vs Overlay @@ -12274,11 +12728,11 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, int i; /* Overlay cursor not supported on HW before DCN - * DCN401 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions - * as previous DCN generations, so enable native mode on DCN401 in addition to DCE + * DCN401/420 does not have the cursor-on-scaled-plane or cursor-on-yuv-plane restrictions + * as previous DCN generations, so enable native mode on DCN401/420 */ - if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0 || - amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1) || + amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0)) { *cursor_mode = DM_CURSOR_NATIVE_MODE; return 0; } @@ -12454,7 +12908,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; - trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -12484,7 +12937,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, new_crtc_state->connectors_changed = true; } +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) if (dc_resource_is_dsc_encoding_supported(dc)) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state->mode_changed_independent_from_dsc = new_crtc_state->mode_changed; + } + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { ret = add_affected_mst_dsc_crtcs(state, crtc); @@ -12495,9 +12954,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } +#endif + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); - if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->color_mgmt_changed && old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && @@ -12598,6 +13058,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * need to be added for DC to not disable a plane by mistake */ if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) { + drm_dbg(dev, "Overlay cursor not supported on DCE\n"); + ret = -EINVAL; + goto fail; + } + ret = drm_atomic_add_affected_planes(state, crtc); if (ret) goto fail; @@ -12659,12 +13125,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = pre_validate_dsc(state, &dm_state, vars); if (ret != 0) goto fail; } +#endif #endif /* Run this here since we want to validate the streams we created */ @@ -12692,7 +13160,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, /* Check if rotation or scaling is enabled on DCN401 */ if ((drm_plane_mask(crtc->cursor) & new_crtc_state->plane_mask) && - amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1)) { + (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 2, 0) || + amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(4, 0, 1))) { new_cursor_state = drm_atomic_get_new_plane_state(state, crtc->cursor); is_rotated = new_cursor_state && @@ -12727,6 +13196,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) + /* Perform validation of MST topology in the state*/ + ret = drm_dp_mst_atomic_check(state); + if (ret) + goto fail; +#endif + if (state->legacy_cursor_update) { /* * This is a fast cursor update coming from the plane update @@ -12769,6 +13245,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { struct amdgpu_dm_connector *aconnector; @@ -12776,6 +13253,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) + if (!mgr->mst_state ) + continue; +#endif drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { if (connector->index == mst_state->mgr->conn_base_id) { @@ -12788,7 +13269,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } - +#endif /** * Streams and planes are reset when there are changes that affect * bandwidth. Anything that affects bandwidth needs to go through @@ -12815,6 +13296,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); @@ -12825,12 +13307,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } #endif +#endif +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); if (ret) { drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); goto fail; } +#endif /* * Perform validation of MST topology in the state: @@ -12838,11 +13323,15 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * dc_validate_global_state(), or there is a chance * to get stuck in an infinite loop and hang eventually. */ +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif +#endif status = dc_validate_global_state(dc, dm_state->context, DC_VALIDATE_MODE_ONLY); if (status != DC_OK) { drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", @@ -12872,7 +13361,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, int j = state->num_private_objs-1; dm_atomic_destroy_state(obj, - state->private_objs[i].state_to_destroy); +#ifdef HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY + state->private_objs[i].state_to_destroy +#else + state->private_objs[i].state +#endif + ); /* If i is not at the end of the array then the * last element needs to be moved to where i was @@ -12883,7 +13377,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, state->private_objs[j]; state->private_objs[j].ptr = NULL; +#ifdef HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY state->private_objs[j].state_to_destroy = NULL; +#else + state->private_objs[j].state = NULL; +#endif state->private_objs[j].old_state = NULL; state->private_objs[j].new_state = NULL; @@ -12902,7 +13400,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * Only allow async flips for fast updates that don't change * the FB pitch, the DCC state, rotation, mem_type, etc. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip && +#else + if ((new_crtc_state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif (lock_and_validation_needed || amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) { drm_dbg_atomic(crtc->dev, @@ -13066,6 +13569,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, return ret; } +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE static void parse_edid_displayid_vrr(struct drm_connector *connector, const struct edid *edid) { @@ -13075,7 +13579,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, u16 min_vfreq; u16 max_vfreq; - if (edid == NULL || edid->extensions == 0) + if (!edid || !edid->extensions) return; /* Find DisplayID extension */ @@ -13085,7 +13589,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, break; } - if (edid_ext == NULL) + if (i == edid->extensions) return; while (j < EDID_LENGTH) { @@ -13108,6 +13612,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, j++; } } +#endif static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, const struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) @@ -13115,6 +13620,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, u8 *edid_ext = NULL; int i; int j = 0; + int total_ext_block_len; if (edid == NULL || edid->extensions == 0) return -ENODEV; @@ -13126,15 +13632,31 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, break; } - while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) { + total_ext_block_len = EDID_LENGTH * edid->extensions; + while (j < total_ext_block_len - sizeof(struct amd_vsdb_block)) { struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j]; unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]); if (ieeeId == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID && amd_vsdb->version == HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3) { + u8 panel_type; vsdb_info->replay_mode = (amd_vsdb->feature_caps & AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE) ? true : false; vsdb_info->amd_vsdb_version = HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3; - DRM_DEBUG_KMS("Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); + drm_dbg_kms(aconnector->base.dev, "Panel supports Replay Mode: %d\n", vsdb_info->replay_mode); + panel_type = (amd_vsdb->color_space_eotf_support & AMD_VDSB_VERSION_3_PANEL_TYPE_MASK) >> AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT; + switch (panel_type) { + case AMD_VSDB_PANEL_TYPE_OLED: + aconnector->dc_link->panel_type = PANEL_TYPE_OLED; + break; + case AMD_VSDB_PANEL_TYPE_MINILED: + aconnector->dc_link->panel_type = PANEL_TYPE_MINILED; + break; + default: + aconnector->dc_link->panel_type = PANEL_TYPE_NONE; + break; + } + drm_dbg_kms(aconnector->base.dev, "Panel type: %d\n", + aconnector->dc_link->panel_type); return true; } @@ -13188,7 +13710,11 @@ static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector, * FreeSync parameters. */ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid) +#else + struct edid *edid) +#endif { int i = 0; struct amdgpu_dm_connector *amdgpu_dm_connector = @@ -13197,7 +13723,9 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, struct dc_sink *sink; struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_hdmi_vsdb_info vsdb_info = {0}; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid; +#endif bool freesync_capable = false; enum adaptive_sync_type as_type = ADAPTIVE_SYNC_TYPE_NONE; @@ -13210,9 +13738,15 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->dc_sink : amdgpu_dm_connector->dc_em_sink; +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update(connector, drm_edid); if (!drm_edid || !sink) { +#else + drm_connector_update_edid_property(connector, edid); + + if (!edid || !sink) { +#endif dm_con_state = to_dm_connector_state(connector->state); amdgpu_dm_connector->min_vfreq = 0; @@ -13227,15 +13761,20 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!adev->dm.freesync_module || !dc_supports_vrr(sink->ctx->dce_version)) goto update; +#ifdef HAVE_DRM_DP_MST_EDID_READ edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE /* Some eDP panels only have the refresh rate range info in DisplayID */ if ((connector->display_info.monitor_range.min_vfreq == 0 || connector->display_info.monitor_range.max_vfreq == 0)) parse_edid_displayid_vrr(connector, edid); +#endif if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || sink->sink_signal == SIGNAL_TYPE_EDP)) { +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE if (amdgpu_dm_connector->dc_link && amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; @@ -13243,7 +13782,7 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; } - +#endif parse_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (vsdb_info.replay_mode) { @@ -13252,7 +13791,11 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP; } +#ifdef HAVE_DRM_DP_MST_EDID_READ } else if (drm_edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#else + } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#endif i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (i >= 0 && vsdb_info.freesync_supported) { amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; @@ -13260,8 +13803,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } @@ -13281,8 +13826,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h old mode 100644 new mode 100755 index beb0d04d3e682..d5c193fe4d094 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -55,8 +55,17 @@ #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 +#define AMD_VDSB_VERSION_3_PANEL_TYPE_MASK 0xC0 +#define AMD_VDSB_VERSION_3_PANEL_TYPE_SHIFT 6 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 +enum amd_vsdb_panel_type { + AMD_VSDB_PANEL_TYPE_DEFAULT = 0, + AMD_VSDB_PANEL_TYPE_MINILED, + AMD_VSDB_PANEL_TYPE_OLED, + AMD_VSDB_PANEL_TYPE_RESERVED, +}; + #define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) /* @@ -92,6 +101,8 @@ struct amd_vsdb_block { unsigned char ieee_id[3]; unsigned char version; unsigned char feature_caps; + unsigned char reserved[3]; + unsigned char color_space_eotf_support; }; struct common_irq_params { @@ -112,6 +123,20 @@ struct dm_compressor_info { uint64_t gpu_addr; }; +/** + * struct dm_boot_time_crc_info - Buffer info used by boot time CRC + * @cpu_addr: MMIO cpu addr + * @bo_ptr: Pointer to the buffer object + * @gpu_addr: MMIO gpu addr + * @size: Size of the buffer + */ +struct dm_boot_time_crc_info { + void *cpu_addr; + struct amdgpu_bo *bo_ptr; + uint64_t gpu_addr; + uint32_t size; +}; + typedef void (*dmub_notify_interrupt_callback_t)(struct amdgpu_device *adev, struct dmub_notification *notify); /** @@ -416,6 +441,13 @@ struct amdgpu_display_manager { */ uint32_t dmcub_fw_version; + /** + * @fw_inst_size: + * + * Size of the firmware instruction buffer. + */ + uint32_t fw_inst_size; + /** * @cgs_device: * @@ -467,6 +499,13 @@ struct amdgpu_display_manager { */ bool audio_registered; + /** + * @vblank_lock: + * + * Guards access to deferred vblank work state. + */ + spinlock_t vblank_lock; + /** * @irq_handler_list_low_tab: * @@ -680,6 +719,13 @@ struct amdgpu_display_manager { struct completion replied; char reply_data[0x40]; // Cannot include dmub_cmd here } fused_io[8]; + + /** + * @dm_boot_time_crc_info: + * + * Buffer info for the boot time crc. + */ + struct dm_boot_time_crc_info boot_time_crc_info; }; enum dsc_clock_force_state { @@ -749,7 +795,11 @@ struct amdgpu_dm_connector { /* we need to mind the EDID between detect and get modes due to analog/digital/tvencoder */ +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; +#else + struct edid *edid; +#endif /* shared with amdgpu */ struct amdgpu_hpd hpd; @@ -811,6 +861,7 @@ struct amdgpu_dm_connector { int sr_skip_count; bool disallow_edp_enter_psr; + bool disallow_edp_enter_replay; /* Record progress status of mst*/ uint8_t mst_status; @@ -965,6 +1016,7 @@ struct dm_crtc_state { bool freesync_vrr_info_changed; + bool mode_changed_independent_from_dsc; bool dsc_force_changed; bool vrr_supported; struct mod_freesync_config freesync_config; @@ -1004,8 +1056,10 @@ struct dm_connector_state { bool update_hdcp; bool abm_sysfs_forbidden; uint8_t abm_level; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int vcpi_slots; uint64_t pbn; +#endif }; #define to_dm_connector_state(x)\ @@ -1033,13 +1087,21 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, int link_index); enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT const struct drm_display_mode *mode); +#else + struct drm_display_mode *mode); +#endif void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid); +#else + struct edid *edid); +#endif void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 1dcc79b35225f..863b4d67bd27d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -23,6 +23,9 @@ * Authors: AMD * */ + +#include + #include "amdgpu.h" #include "amdgpu_mode.h" #include "amdgpu_dm.h" @@ -877,6 +880,7 @@ amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) } } +#ifdef HAVE_DRM_DRM_COLOROP_H static enum dc_transfer_func_predefined amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf) { @@ -897,6 +901,7 @@ amdgpu_colorop_tf_to_dc_tf(enum drm_colorop_curve_1d_type tf) return TRANSFER_FUNCTION_LINEAR; } } +#endif static void __to_dc_lut3d_color(struct dc_rgb *rgb, const struct drm_color_lut lut, @@ -1461,6 +1466,7 @@ __set_dm_plane_degamma(struct drm_plane_state *plane_state, return 0; } +#ifdef HAVE_DRM_DRM_COLOROP_H static int __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state, struct drm_colorop_state *colorop_state) @@ -1489,6 +1495,7 @@ __set_colorop_in_tf_1d_curve(struct dc_plane_state *dc_plane_state, return 0; } + static int __set_dm_plane_colorop_degamma(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state, @@ -1814,6 +1821,7 @@ __set_dm_plane_colorop_blend(struct drm_plane_state *plane_state, return 0; } +#endif static int amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, @@ -1865,6 +1873,7 @@ amdgpu_dm_plane_set_color_properties(struct drm_plane_state *plane_state, return 0; } +#ifdef HAVE_DRM_DRM_COLOROP_H static int amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, struct dc_plane_state *dc_plane_state) @@ -1951,7 +1960,7 @@ amdgpu_dm_plane_set_colorop_properties(struct drm_plane_state *plane_state, return 0; } - +#endif /** * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. * @crtc: amdgpu_dm crtc state @@ -2047,9 +2056,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, dc_plane_state->gamut_remap_matrix.enable_remap = false; dc_plane_state->input_csc_color_matrix.enable_adjustment = false; } - + +#ifdef HAVE_DRM_DRM_COLOROP_H if (!amdgpu_dm_plane_set_colorop_properties(plane_state, dc_plane_state)) return 0; +#endif return amdgpu_dm_plane_set_color_properties(plane_state, dc_plane_state); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c index a2de3bba83464..8c03ee28d31d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c @@ -33,6 +33,7 @@ #include "amdgpu_dm_colorop.h" #include "dc.h" +#ifdef HAVE_DRM_DRM_COLOROP_H const u64 amdgpu_dm_supported_degam_tfs = BIT(DRM_COLOROP_1D_CURVE_SRGB_EOTF) | BIT(DRM_COLOROP_1D_CURVE_PQ_125_EOTF) | @@ -209,3 +210,4 @@ int amdgpu_dm_initialize_default_pipeline(struct drm_plane *plane, struct drm_pr return ret; } +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index e20aa74380665..dd79866df1fda 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -32,6 +32,7 @@ #include "dc.h" #include "amdgpu_securedisplay.h" #include "amdgpu_dm_psr.h" +#include "amdgpu_dm_replay.h" static const char *const pipe_crc_sources[] = { "none", @@ -105,7 +106,9 @@ static void update_phy_id_mapping(struct amdgpu_device *adev) continue; if (idx >= AMDGPU_DM_MAX_CRTC) { - DRM_WARN("%s connected connectors exceed max crtc\n", __func__); + drm_warn(adev_to_drm(adev), + "%s connected connectors exceed max crtc\n", + __func__); mutex_unlock(&ddev->mode_config.mutex); return; } @@ -500,23 +503,44 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, { struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc_stream_state *stream_state = dm_crtc_state->stream; + struct amdgpu_dm_connector *aconnector = NULL; bool enable = amdgpu_dm_is_valid_crc_source(source); int ret = 0; + enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16; /* Configuration will be deferred to stream enable. */ if (!stream_state) return -EINVAL; + /* Get connector from stream */ + aconnector = (struct amdgpu_dm_connector *)stream_state->dm_stream_context; + mutex_lock(&adev->dm.dc_lock); - /* For PSR1, check that the panel has exited PSR */ - if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) - amdgpu_dm_psr_wait_disable(stream_state); + + if (enable) { + /* For PSR1, check that the panel has exited PSR */ + if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1) + amdgpu_dm_psr_wait_disable(stream_state); + + /* Set flag to disallow enter replay when CRC source is enabled */ + if (aconnector) + aconnector->disallow_edp_enter_replay = true; + amdgpu_dm_replay_disable(stream_state); + } + + /* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */ + if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && + (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1))) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + crc_poly_mode = acrtc->dm_irq_params.crc_poly_mode; + } /* Enable or disable CRTC CRC generation */ if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) { if (!dc_stream_configure_crc(stream_state->ctx->dc, - stream_state, NULL, enable, enable, 0, true)) { + stream_state, NULL, enable, enable, 0, true, crc_poly_mode)) { ret = -EINVAL; goto unlock; } @@ -534,6 +558,12 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, DYN_EXPANSION_AUTO); } + if (!enable) { + /* Clear flag to allow enter replay when CRC source is disabled */ + if (aconnector) + aconnector->disallow_edp_enter_replay = false; + } + unlock: mutex_unlock(&adev->dm.dc_lock); @@ -782,7 +812,6 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) unsigned long flags1; bool forward_roi_change = false; bool notify_ta = false; - bool all_crc_ready = true; struct dc_stream_state *stream_state; int i; @@ -856,7 +885,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE) /* update ROI via dm*/ dc_stream_configure_crc(stream_state->ctx->dc, stream_state, - &crc_window, true, true, i, false); + &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode); reset_crc_frame_count[i] = true; @@ -880,7 +909,7 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) else if (adev->dm.secure_display_ctx.op_mode == DISPLAY_CRC_MODE) /* Avoid ROI window get changed, keep overwriting. */ dc_stream_configure_crc(stream_state->ctx->dc, stream_state, - &crc_window, true, true, i, false); + &crc_window, true, true, i, false, (enum crc_poly_mode)acrtc->dm_irq_params.crc_poly_mode); /* crc ready for psp to read out */ crtc_ctx->crc_info.crc[i].crc_ready = true; @@ -906,9 +935,6 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) continue; } - if (!crtc_ctx->crc_info.crc[i].crc_ready) - all_crc_ready = false; - if (reset_crc_frame_count[i] || crtc_ctx->crc_info.crc[i].frame_count == UINT_MAX) /* Reset the reference frame count after user update the ROI * or it reaches the maximum value. @@ -918,9 +944,6 @@ void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc) crtc_ctx->crc_info.crc[i].frame_count += 1; } spin_unlock_irqrestore(&crtc_ctx->crc_info.lock, flags1); - - if (all_crc_ready) - complete_all(&crtc_ctx->crc_info.completion); } void amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 95bdb8699d7fa..8538513ea8799 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -70,7 +70,6 @@ struct crc_data { struct crc_info { struct crc_data crc[MAX_CRC_WINDOW_NUM]; - struct completion completion; spinlock_t lock; }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 9fcd72d87d25b..252c4d21c4967 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -307,6 +307,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id); if (enable) { +#ifdef HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG struct dc *dc = adev->dm.dc; struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); struct psr_settings *psr = &acrtc_state->stream->link->psr_settings; @@ -325,6 +326,7 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) dc->config.disable_ips != DMUB_IPS_DISABLE_ALL && sr_supported && vblank->config.disable_immediate) drm_crtc_vblank_restore(crtc); +#endif } if (dc_supports_vrr(dm->dc->ctx->dce_version)) { @@ -571,6 +573,9 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = amdgpu_dm_crtc_reset_state, .destroy = amdgpu_dm_crtc_destroy, +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL + .gamma_set = drm_atomic_helper_legacy_gamma_set, +#endif .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, @@ -578,10 +583,12 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, - .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif @@ -650,10 +657,16 @@ static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, } static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, +#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); +#else + struct drm_crtc_state *crtc_state) +{ + struct drm_atomic_state *state = crtc_state->state; +#endif struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); @@ -684,8 +697,13 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, * Only allow async flips for fast updates that don't change the FB * pitch, the DCC state, rotation, etc. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc_state->async_flip && - dm_crtc_state->update_type != UPDATE_TYPE_FAST) { +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif + dm_crtc_state->update_type > UPDATE_TYPE_FAST) { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] async flips are only supported for fast updates\n", crtc->base.id, crtc->name); @@ -716,7 +734,9 @@ static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { .disable = amdgpu_dm_crtc_helper_disable, .atomic_check = amdgpu_dm_crtc_helper_atomic_check, .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, @@ -765,15 +785,15 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, dm->adev->mode_info.crtcs[crtc_index] = acrtc; /* Don't enable DRM CRTC degamma property for - * 1. Degamma is replaced by color pipeline. - * 2. DCE since it doesn't support programmable degamma anywhere. - * 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor. + * 1. DCE since it doesn't support programmable degamma anywhere. + * 2. DCN401 since pre-blending degamma LUT doesn't apply to cursor. + * Note: DEGAMMA properties are created even if the primary plane has the + * COLOR_PIPELINE property. User space can use either the DEGAMMA properties + * or the COLOR_PIPELINE property. An atomic commit which attempts to enable + * both is rejected. */ - if (plane->color_pipeline_property) - has_degamma = false; - else - has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && - dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; + has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch && + dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01; drm_crtc_enable_color_mgmt(&acrtc->base, has_degamma ? MAX_COLOR_LUT_ENTRIES : 0, true, MAX_COLOR_LUT_ENTRIES); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index a9839485f2a29..ac576dd293fef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "dc.h" #include "amdgpu.h" @@ -46,6 +47,7 @@ #include "amdgpu_dm_psr.h" #endif +#define MULTIPLIER_TO_LR 270000 struct dmub_debugfs_trace_header { uint32_t entry_count; uint32_t reserved[3]; @@ -95,7 +97,7 @@ static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, return -EFAULT; } - /* check number of parameters. isspace could not differ space and \n */ + /* check number of parameters. isspace could not differ space and\n */ while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { /* skip space*/ while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { @@ -302,8 +304,11 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, switch (param[1]) { case LINK_RATE_LOW: + case LINK_RATE_RATE_2: + case LINK_RATE_RATE_3: case LINK_RATE_HIGH: case LINK_RATE_RBR2: + case LINK_RATE_RATE_6: case LINK_RATE_HIGH2: case LINK_RATE_HIGH3: case LINK_RATE_UHBR10: @@ -350,11 +355,20 @@ static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) mgr = &aconnector->mst_root->mst_mgr; port = aconnector->mst_output_port; + /* The base.lock was introduced in version 4.20, while the write + * lock was added in DRM version 5.4.0. Since RHEL 7.9 uses DRM version + * 5.0.10, write operations do not include locking. Consequently, read + * operations here also do not require locking. + */ +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_lock(&mgr->base.lock, NULL); +#endif if (port->pdt == DP_PEER_DEVICE_SST_SINK || port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) is_end_device = true; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_unlock(&mgr->base.lock); +#endif } return is_end_device; @@ -486,7 +500,6 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, kfree(wr_buf); return size; } - /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * @@ -2523,7 +2536,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, return result; } - /* * function description: Read max_requested_bpc property from the connector * @@ -2709,6 +2721,65 @@ static int ips_status_show(struct seq_file *m, void *unused) return 0; } +/* + * IPS residency information from DMUB service. Read only. + * + * For time-window (segment) measurement: + * 1) echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl + * 2) sleep + * 3) echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl + * 4) cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency + */ +static int ips_residency_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = m->private; + struct dc *dc = adev->dm.dc; + uint8_t panel_inst = 0; + enum ips_residency_mode mode; + struct dmub_ips_residency_info info; + + mutex_lock(&adev->dm.dc_lock); + + mode = IPS_RESIDENCY__IPS1_RCG; + if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) { + seq_printf(m, "ISP query failed\n"); + } else { + unsigned int pct, frac; + pct = info.residency_millipercent / 1000; + frac = info.residency_millipercent % 1000; + + seq_printf(m, "IPS residency: %u.%03u%% \n", pct, frac); + seq_printf(m, " entry_counter: %u\n", info.entry_counter); + seq_printf(m, " total_time_us: %llu\n", + (unsigned long long)info.total_time_us); + seq_printf(m, " total_inactive_time_us: %llu\n", + (unsigned long long)info.total_inactive_time_us); + } + mutex_unlock(&adev->dm.dc_lock); + return 0; +} + +static int ips_residency_cntl_get(void *data, u64 *val) +{ + *val = 0; + return 0; +} + +static int ips_residency_cntl_set(void *data, u64 val) +{ + struct amdgpu_device *adev = data; + struct dc *dc = adev->dm.dc; + uint8_t panel_inst = 0; + int ret = 0; + + mutex_lock(&adev->dm.dc_lock); + if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val)) + ret = -EIO; + mutex_unlock(&adev->dm.dc_lock); + + return ret; +} + /* * Backlight at this moment. Read only. * As written to display, taking ABM and backlight lut into account. @@ -2780,11 +2851,15 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) mgr = &aconnector->mst_root->mst_mgr; port = aconnector->mst_output_port; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_lock(&mgr->base.lock, NULL); +#endif if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && port->mcs) role = "branch"; +#ifdef HAVE_DRM_PRIVATE_OBJ_LOCK drm_modeset_unlock(&mgr->base.lock); +#endif } else { role = "no"; @@ -2906,7 +2981,9 @@ static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, } else { if (!aconnector->notifier) return -EINVAL; +#ifdef HAVE_CEC_NOTIFIER_CONN_REGISTER cec_notifier_conn_unregister(aconnector->notifier); +#endif aconnector->notifier = NULL; } @@ -3195,6 +3272,7 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val) return 0; } +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) /* check if kernel disallow eDP enter psr state * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr * 0: allow edp enter psr; 1: disallow @@ -3242,6 +3320,52 @@ static int disallow_edp_enter_psr_set(void *data, u64 val) return 0; } +/* check if kernel disallow eDP enter replay state + * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay + * 0: allow edp enter replay; 1: disallow + */ +static int disallow_edp_enter_replay_get(void *data, u64 *val) +{ + struct amdgpu_dm_connector *aconnector = data; + + *val = (u64) aconnector->disallow_edp_enter_replay; + return 0; +} + +/* set kernel disallow eDP enter replay state + * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay + * 0: allow edp enter replay; 1: disallow + * + * usage: test app read crc from PSR eDP rx. + * + * during kernel boot up, kernel write dpcd 0x37b to + * notify eDP rx replay enable. + * rx fw will start checking crc for rx internal logic. + * crc read count within dpcd 0x246 is not updated and + * value is 0. when eDP tx driver wants to read rx crc + * from dpcd 0x246, 0x270, read count 0 lead tx driver + * timeout. + * + * to avoid this, we add this debugfs to let test app to disbable + * rx replay. then test app can read non-zero crc read count. + * + * expected app sequence is as below: + * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. + * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay + * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but + * without programming dpcd 0x37b. + * 4. read crc from rx dpcd 0x270, 0x246, etc. + * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay. + * this will let eDP back to normal with replay setup dpcd 0x37b. + */ +static int disallow_edp_enter_replay_set(void *data, u64 val) +{ + struct amdgpu_dm_connector *aconnector = data; + + aconnector->disallow_edp_enter_replay = val ? true : false; + return 0; +} + static int dmub_trace_mask_set(void *data, u64 val) { struct amdgpu_device *adev = data; @@ -3320,7 +3444,7 @@ static int dmub_trace_mask_show(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, dmub_trace_mask_set, "0x%llx\n"); - +#endif /* * Set dmcub trace event IRQ enable or disable. * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en @@ -3370,9 +3494,16 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); +DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops, + disallow_edp_enter_replay_get, + disallow_edp_enter_replay_set, "%llu\n"); + +DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, + ips_residency_cntl_set, "%llu\n"); DEFINE_SHOW_ATTRIBUTE(current_backlight); DEFINE_SHOW_ATTRIBUTE(target_backlight); DEFINE_SHOW_ATTRIBUTE(ips_status); +DEFINE_SHOW_ATTRIBUTE(ips_residency); static const struct { char *name; @@ -3442,6 +3573,10 @@ static ssize_t edp_ilr_write(struct file *f, const char __user *buf, uint8_t param_nums = 0; long param[2]; bool valid_input = true; + uint8_t supported_link_rates[16] = {0}; + uint32_t entry = 0; + uint32_t link_rate_in_khz = 0; + uint8_t dpcd_rev = 0; if (size == 0) return -EINVAL; @@ -3486,6 +3621,20 @@ static ssize_t edp_ilr_write(struct file *f, const char __user *buf, return size; } + if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, + supported_link_rates, sizeof(supported_link_rates))) + return -EINVAL; + + dpcd_rev = link->dpcd_caps.dpcd_rev.raw; + if (dpcd_rev < DP_DPCD_REV_13 || + (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) { + return size; + } + + entry = param[1] * 2; + link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 + + supported_link_rates[entry]) * 200; + /* save user force lane_count, link_rate to preferred settings * spread spectrum will not be changed */ @@ -3493,7 +3642,7 @@ static ssize_t edp_ilr_write(struct file *f, const char __user *buf, prefer_link_settings.lane_count = param[0]; prefer_link_settings.use_link_rate_set = true; prefer_link_settings.link_rate_set = param[1]; - prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]]; + prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR; mutex_lock(&adev->dm.dc_lock); dc_link_set_preferred_training_settings(dc, &prefer_link_settings, @@ -3531,6 +3680,7 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) dp_debugfs_entries[i].fops); } } + if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); @@ -3551,6 +3701,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) &allow_edp_hotplug_detection_fops); debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); + debugfs_create_file("disallow_edp_enter_replay", 0644, dir, connector, + &disallow_edp_enter_replay_fops); } for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { @@ -3755,6 +3907,50 @@ static int crc_win_update_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, crc_win_update_set, "%llu\n"); + +/* + * Trigger to set crc polynomial mode + * 0: 16-bit CRC, 1: 32-bit CRC + * only accepts 0 or 1 for supported hwip versions + */ +static int crc_poly_mode_set(void *data, u64 val) +{ + struct drm_crtc *crtc = data; + struct amdgpu_crtc *acrtc; + struct amdgpu_device *adev = drm_to_adev(crtc->dev); + + if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && + (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) && + (val < 2)) { + acrtc = to_amdgpu_crtc(crtc); + mutex_lock(&adev->dm.dc_lock); + spin_lock_irq(&adev_to_drm(adev)->event_lock); + acrtc->dm_irq_params.crc_poly_mode = val; + spin_unlock_irq(&adev_to_drm(adev)->event_lock); + mutex_unlock(&adev->dm.dc_lock); + } + + return 0; +} + +/* + * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC) + */ +static int crc_poly_mode_get(void *data, u64 *val) +{ + struct drm_crtc *crtc = data; + struct drm_device *drm_dev = crtc->dev; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + spin_lock_irq(&drm_dev->event_lock); + *val = acrtc->dm_irq_params.crc_poly_mode; + spin_unlock_irq(&drm_dev->event_lock); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get, + crc_poly_mode_set, "%llu\n"); #endif void crtc_debugfs_init(struct drm_crtc *crtc) { @@ -3774,6 +3970,8 @@ void crtc_debugfs_init(struct drm_crtc *crtc) &crc_win_y_end_fops); debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, &crc_win_update_fops); + debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc, + &crc_poly_mode_fops); dput(dir); #endif debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, @@ -3945,7 +4143,6 @@ static int trigger_hpd_mst_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, trigger_hpd_mst_set, "%llu\n"); - /* * Sets the force_timing_sync debug option from the given string. * All connected displays will be force synchronized immediately. @@ -3978,7 +4175,6 @@ static int force_timing_sync_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, force_timing_sync_set, "%llu\n"); - /* * Disables all HPD and HPD RX interrupt handling in the * driver when set to 1. Default is 0. @@ -4060,6 +4256,8 @@ static int dp_force_sst_get(void *data, u64 *val) return 0; } + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); @@ -4086,6 +4284,7 @@ static int dp_ignore_cable_id_get(void *data, u64 *val) } DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, dp_ignore_cable_id_set, "%llu\n"); +#endif /* * Sets the DC visual confirm debug option from the given string. @@ -4117,7 +4316,6 @@ DEFINE_SHOW_ATTRIBUTE(mst_topo); DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); - /* * Sets the DC skip_detection_link_training debug option from the given string. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training @@ -4236,11 +4434,11 @@ void dtn_debugfs_init(struct amdgpu_device *adev) adev, &capabilities_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); + debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, &dp_set_mst_en_for_sst_ops); debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); - debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); @@ -4271,7 +4469,14 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, &disable_hpd_ops); - if (adev->dm.dc->caps.ips_support) + if (adev->dm.dc->caps.ips_support) { debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, &ips_status_fops); + + debugfs_create_file_unsafe("amdgpu_dm_ips_residency_cntl", 0644, root, adev, + &ips_residency_cntl_fops); + + debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev, + &ips_residency_fops); + } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 85ce558cefc58..c2661d7ce179a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -267,9 +267,11 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms); +#endif } mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); @@ -374,6 +376,7 @@ static void event_property_update(struct work_struct *work) } if (hdcp_work->encryption_status[conn_index] != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (conn_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 && hdcp_work->encryption_status[conn_index] <= @@ -388,6 +391,9 @@ static void event_property_update(struct work_struct *work) drm_hdcp_update_content_protection(connector, DRM_MODE_CONTENT_PROTECTION_ENABLED); } +#else + drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED); +#endif } else { DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); drm_hdcp_update_content_protection(connector, @@ -503,7 +509,8 @@ static bool enable_assr(void *handle, struct dc_link *link) struct ta_dtm_shared_memory *dtm_cmd; if (!psp->dtm_context.context.initialized) { - DRM_INFO("Failed to enable ASSR, DTM TA is not initialized."); + drm_info(adev_to_drm(psp->adev), + "Failed to enable ASSR, DTM TA is not initialized."); return false; } @@ -520,7 +527,8 @@ static bool enable_assr(void *handle, struct dc_link *link) psp_dtm_invoke(psp, dtm_cmd->cmd_id); if (dtm_cmd->dtm_status != TA_DTM_STATUS__SUCCESS) { - DRM_INFO("Failed to enable ASSR"); + drm_info(adev_to_drm(psp->adev), + "Failed to enable ASSR"); return false; } @@ -584,6 +592,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->adjust.hdcp2.use_sw_locality_fallback = dc->debug.hdcp_lc_enable_sw_fallback; hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1, @@ -598,6 +607,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) drm_connector_put(&hdcp_w->aconnector[conn_index]->base); hdcp_w->aconnector[conn_index] = aconnector; process_output(hdcp_w); +#endif } /** @@ -649,7 +659,11 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) * incorrect/corrupted and we should correct our SRM by getting it from PSP */ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct hdcp_workqueue *work; @@ -673,7 +687,11 @@ static ssize_t srm_data_write(struct file *filp, struct kobject *kobj, } static ssize_t srm_data_read(struct file *filp, struct kobject *kobj, +#ifdef HAVE_BIN_ATTR_CONST_ARGS const struct bin_attribute *bin_attr, char *buffer, +#else + struct bin_attribute *bin_attr, char *buffer, +#endif loff_t pos, size_t count) { struct hdcp_workqueue *work; @@ -813,7 +831,7 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, sysfs_bin_attr_init(&hdcp_work[0].attr); if (sysfs_create_bin_file(&adev->dev->kobj, &hdcp_work[0].attr)) - DRM_WARN("Failed to create device file hdcp_srm"); + drm_warn(adev_to_drm(adev), "Failed to create device file hdcp_srm\n"); return hdcp_work; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index e5e993d3ef74a..47f070ff03ee2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -49,6 +49,41 @@ #include "ddc_service_types.h" #include "clk_mgr.h" +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP +struct monitor_patch_info { + unsigned int manufacturer_id; + unsigned int product_id; + void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param); + unsigned int patch_param; +}; +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param); + +static const struct monitor_patch_info monitor_patch_table[] = { +{0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15}, +{0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15}, +}; + +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param) +{ + if (edid_caps) + edid_caps->panel_patch.max_dsc_target_bpp_limit = param; +} + +static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++) + if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id) + && (edid_caps->product_id == monitor_patch_table[i].product_id)) { + monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param); + ret++; + } + + return ret; +} +#endif + static u32 edid_extract_panel_id(struct edid *edid) { return (u32)edid->mfg_id[0] << 24 | @@ -137,7 +172,12 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; +#else + edid_caps->edid_hdmi = drm_detect_hdmi_monitor( + (struct edid *) edid->raw_edid); +#endif if (edid_caps->edid_hdmi) populate_hdmi_info_from_connector(&connector->display_info.hdmi, edid_caps); @@ -173,9 +213,14 @@ enum dc_edid_status dm_helpers_parse_edid_caps( kfree(sads); kfree(sadb); +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP + amdgpu_dm_patch_edid_caps(edid_caps); +#endif + return result; } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void fill_dc_mst_payload_table_from_drm(struct dc_link *link, bool enable, @@ -226,12 +271,50 @@ fill_dc_mst_payload_table_from_drm(struct dc_link *link, /* Overwrite the old table */ *table = new_table; } +#else +static void +fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, + struct dc_dp_mst_stream_allocation_table *proposed_table) +{ + int i; + struct drm_dp_mst_topology_mgr *mst_mgr = + &aconnector->mst_root->mst_mgr; + + mutex_lock(&mst_mgr->payload_lock); + + proposed_table->stream_count = 0; + + /* number of active streams */ + for (i = 0; i < mst_mgr->max_payloads; i++) { + if (mst_mgr->payloads[i].num_slots == 0) + break; /* end of vcp_id table */ + + ASSERT(mst_mgr->payloads[i].payload_state != + DP_PAYLOAD_DELETE_LOCAL); + + if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || + mst_mgr->payloads[i].payload_state == + DP_PAYLOAD_REMOTE) { + + struct dc_dp_mst_stream_allocation *sa = + &proposed_table->stream_allocations[ + proposed_table->stream_count]; + + sa->slot_count = mst_mgr->payloads[i].num_slots; + sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; + proposed_table->stream_count++; + } + } + + mutex_unlock(&mst_mgr->payload_lock); +} +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, const struct dc_link *link) {} - +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void dm_helpers_construct_old_payload( struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_topology_state *mst_state, @@ -239,7 +322,12 @@ static void dm_helpers_construct_old_payload( struct drm_dp_mst_atomic_payload *old_payload) { struct drm_dp_mst_atomic_payload *pos; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + int pbn_per_slot = mst_state->pbn_div; +#endif + u8 next_payload_vc_start = mgr->next_start_slot; u8 payload_vc_start = new_payload->vc_start_slot; u8 allocated_time_slots; @@ -263,6 +351,7 @@ static void dm_helpers_construct_old_payload( old_payload->time_slots = allocated_time_slots; old_payload->pbn = allocated_time_slots * pbn_per_slot; } +#endif /* * Writes payload allocation table in immediate downstream device. @@ -274,9 +363,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( bool enable) { struct amdgpu_dm_connector *aconnector; + struct drm_dp_mst_topology_mgr *mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; - struct drm_dp_mst_topology_mgr *mst_mgr; +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct dm_connector_state *dm_conn_state; +#endif + struct drm_dp_mst_port *mst_port; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int slots = 0; +#endif + bool ret; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int clock; + int bpp = 0; + int pbn = 0; +#endif + u8 link_coding_cap = DP_8b_10b_ENCODING; +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; /* Accessing the connector state is required for vcpi_slots allocation @@ -289,6 +395,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( return false; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); @@ -302,8 +409,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); target_payload = &old_payload; - +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); +#else + drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); +#endif } /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or @@ -312,7 +422,81 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( * sequence. copy DRM MST allocation to dc */ fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); - +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + dm_conn_state = to_dm_connector_state(aconnector->base.state); +#endif + if (!mst_mgr->mst_state) + return false; + + mst_port = aconnector->mst_output_port; + + link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); + + if (enable) { + +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + clock = stream->timing.pix_clk_100hz / 10; + + switch (stream->timing.display_color_depth) { + + case COLOR_DEPTH_666: + bpp = 6; + break; + case COLOR_DEPTH_888: + bpp = 8; + break; + case COLOR_DEPTH_101010: + bpp = 10; + break; + case COLOR_DEPTH_121212: + bpp = 12; + break; + case COLOR_DEPTH_141414: + bpp = 14; + break; + case COLOR_DEPTH_161616: + bpp = 16; + break; + default: + ASSERT(bpp != 0); + break; + } + + bpp = bpp * 3; + + /* TODO need to know link rate */ + pbn = drm_dp_calc_pbn_mode(clock, bpp, false); + + slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, + slots); +#else + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, + dm_conn_state->pbn, + dm_conn_state->vcpi_slots); +#endif + if (!ret) + return false; + + } else { + drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); + } + + /* It's OK for this to fail */ +#ifdef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1); +#else + drm_dp_update_payload_part1(mst_mgr); +#endif + + /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or + * AUX message. The sequence is slot 1-63 allocated sequence for each + * stream. AMD ASIC stream slot allocation should follow the same + * sequence. copy DRM MST allocation to dc */ + + fill_dc_mst_payload_table_from_drm(aconnector, proposed_table); +#endif return true; } @@ -367,9 +551,13 @@ void dm_helpers_dp_mst_send_payload_allocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; - struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_atomic_payload *new_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif + struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; int ret = 0; @@ -380,11 +568,21 @@ void dm_helpers_dp_mst_send_payload_allocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); - ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + mst_port = aconnector->mst_output_port; + if (!mst_mgr->mst_state) + return; +#endif +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) + ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + ret = drm_dp_update_payload_part2(mst_mgr); +#endif if (ret) { amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, false); @@ -401,9 +599,13 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; - struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_topology_mgr *mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *new_payload, old_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; @@ -413,15 +615,26 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); +#endif +#else + mst_port = aconnector->mst_output_port; + if (!mst_mgr->mst_state) + return; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); +#endif } void dm_dtn_log_begin(struct dc_context *ctx, @@ -712,8 +925,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, // read rc data drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); } - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "success = %d\n", success); +#else + DRM_DEBUG_KMS("%s: success = %d\n", __func__, success); +#endif return success; @@ -725,9 +941,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) { unsigned char data[16] = {0}; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Start\n"); - +#else + DRM_DEBUG_KMS("Start %s\n", __func__); +#endif // Step 2 data[0] = 'P'; data[1] = 'R'; @@ -783,8 +1001,11 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) // Step 6 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) return; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Done\n"); +#else + DRM_DEBUG_KMS("Done %s\n", __func__); +#endif } /* MST Dock */ @@ -796,9 +1017,12 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( bool enable) { uint8_t ret = 0; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); +#else + DRM_DEBUG_KMS("MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); +#endif if (enable) { /* When DSC is enabled on previous boot and reboot with the hub, @@ -832,16 +1056,20 @@ bool dm_helpers_dp_write_dsc_enable( const struct dc_stream_state *stream, bool enable) { + struct amdgpu_dm_connector *aconnector = + (struct amdgpu_dm_connector *)stream->dm_stream_context; + struct drm_device *dev = aconnector->base.dev; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) static const uint8_t DSC_DISABLE; static const uint8_t DSC_DECODING = 0x01; static const uint8_t DSC_PASSTHROUGH = 0x02; - struct amdgpu_dm_connector *aconnector = - (struct amdgpu_dm_connector *)stream->dm_stream_context; - struct drm_device *dev = aconnector->base.dev; struct drm_dp_mst_port *port; uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; +#else + uint8_t enable_dsc = enable ? 1 : 0; +#endif uint8_t ret = 0; if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { @@ -854,6 +1082,7 @@ bool dm_helpers_dp_write_dsc_enable( return write_dsc_enable_synaptics_non_virtual_dpcd_mst( aconnector->dsc_aux, stream, enable_dsc); +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) port = aconnector->mst_output_port; if (enable) { @@ -891,6 +1120,11 @@ bool dm_helpers_dp_write_dsc_enable( ret); } } +#else + ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); + DRM_DEBUG_KMS("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); +#endif + } if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { @@ -932,6 +1166,7 @@ bool dm_helpers_is_dp_sink_present(struct dc_link *link) return dp_sink_present; } +#ifdef HAVE_DRM_DP_MST_EDID_READ static int dm_helpers_probe_acpi_edid(void *data, u8 *buf, unsigned int block, size_t len) { @@ -992,6 +1227,7 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector) return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector); } +#endif void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps) { @@ -1004,11 +1240,15 @@ enum dc_edid_status dm_helpers_read_local_edid( struct dc_sink *sink) { struct amdgpu_dm_connector *aconnector = link->priv; +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM struct drm_connector *connector = &aconnector->base; +#endif struct i2c_adapter *ddc; int retry = 25; enum dc_edid_status edid_status = EDID_NO_RESPONSE; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct drm_edid *drm_edid; +#endif const struct edid *edid; if (link->aux_mode) @@ -1016,30 +1256,49 @@ enum dc_edid_status dm_helpers_read_local_edid( else ddc = &aconnector->i2c->base; + if (link->dc->hwss.prepare_ddc) + link->dc->hwss.prepare_ddc(link); + /* some dongles read edid incorrectly the first time, * do check sum and retry to make sure read correct edid. */ do { +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid = dm_helpers_read_acpi_edid(aconnector); if (drm_edid) drm_info(connector->dev, "Using ACPI provided EDID for %s\n", connector->name); else drm_edid = drm_edid_read_ddc(connector, ddc); drm_edid_connector_update(connector, drm_edid); +#else + edid = drm_get_edid(&aconnector->base, ddc); +#endif +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid && connector->edid_corrupt) { +#else + if (!edid && connector->edid_corrupt) { +#endif connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } +#endif +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!drm_edid) +#else + if (!edid) +#endif continue; +#ifdef HAVE_DRM_DP_MST_EDID_READ edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif if (!edid || edid->extensions >= sizeof(sink->dc_edid.raw_edid) / EDID_LENGTH) return EDID_BAD_INPUT; @@ -1048,7 +1307,11 @@ enum dc_edid_status dm_helpers_read_local_edid( memmove(sink->dc_edid.raw_edid, (uint8_t *)edid, sink->dc_edid.length); /* We don't need the original edid anymore */ +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(drm_edid); +#else + kfree(edid); +#endif edid_status = dm_helpers_parse_edid_caps( link, @@ -1087,7 +1350,6 @@ enum dc_edid_status dm_helpers_read_local_edid( DP_TEST_RESPONSE, &test_response.raw, sizeof(test_response)); - } return edid_status; @@ -1121,6 +1383,12 @@ void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) /* TODO: something */ } +void dm_helpers_dmu_timeout(struct dc_context *ctx) +{ + // TODO: + //amdgpu_device_gpu_recover(dc_context->driver-context, NULL); +} + void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us) { // TODO: @@ -1147,11 +1415,19 @@ void dm_helpers_init_panel_settings( void dm_helpers_override_panel_settings( struct dc_context *ctx, - struct dc_panel_config *panel_config) + struct dc_link *link) { + unsigned int panel_inst = 0; + // Feature DSC if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) - panel_config->dsc.disable_dsc_edp = true; + link->panel_config.dsc.disable_dsc_edp = true; + + if (dc_get_edp_link_panel_inst(ctx->dc, link, &panel_inst) && panel_inst == 1) { + link->panel_config.psr.disable_psr = true; + link->panel_config.psr.disallow_psrsu = true; + link->panel_config.psr.disallow_replay = true; + } } void *dm_helpers_allocate_gpu_mem( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index e7b0928bd3db7..5948e2a6219e3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -919,16 +919,15 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) continue; amdgpu_dm_connector = to_amdgpu_dm_connector(connector); + dc_link = amdgpu_dm_connector->dc_link; + if (!dc_link) + continue; /* * Analog connectors may be hot-plugged unlike other connector * types that don't support HPD. Only poll analog connectors. */ - use_polling |= - amdgpu_dm_connector->dc_link && - dc_connector_supports_analog(amdgpu_dm_connector->dc_link->link_id.id); - - dc_link = amdgpu_dm_connector->dc_link; + use_polling |= dc_connector_supports_analog(dc_link->link_id.id); /* * Get a base driver irq reference for hpd ints for the lifetime diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h index 3c9995275cbda..f0c1b0c1faa9f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h @@ -39,6 +39,7 @@ struct dm_irq_params { #ifdef CONFIG_DEBUG_FS enum amdgpu_dm_pipe_crc_source crc_src; + int crc_poly_mode; /* enum crc_poly_mode from timing_generator.h */ #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY struct crc_window_param window_param[MAX_CRC_WINDOW_NUM]; /* At least one CRC window is activated or not*/ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 5e92eaa67aa33..54eea916c1681 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -143,26 +143,50 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, return result; } +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP +static enum drm_connector_status +dm_dp_mst_detect(struct drm_connector *connector, bool force) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct amdgpu_dm_connector *master = aconnector->mst_root; + + enum drm_connector_status status = + drm_dp_mst_detect_port( + connector, + &master->mst_mgr, + aconnector->mst_output_port); + return status; +} +#endif static void dm_dp_mst_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR if (aconnector->dc_sink) { dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); dc_sink_release(aconnector->dc_sink); } +#endif +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_free(aconnector->drm_edid); +#else + kfree(aconnector->edid); +#endif drm_connector_cleanup(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_put_port_malloc(aconnector->mst_output_port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ kfree(aconnector); } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) static int amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) { @@ -181,18 +205,25 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) return 0; } - +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ static inline void amdgpu_dm_mst_reset_mst_connector_setting(struct amdgpu_dm_connector *aconnector) { +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = NULL; +#else + aconnector->edid = NULL; +#endif aconnector->dsc_aux = NULL; +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX aconnector->mst_output_port->passthrough_aux = NULL; +#endif aconnector->mst_local_bw = 0; aconnector->vc_full_pbn = 0; } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) static void amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) { @@ -226,8 +257,12 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) aconnector->mst_status = MST_STATUS_DEFAULT; drm_modeset_unlock(&root->mst_mgr.base.lock); } +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP + .detect = dm_dp_mst_detect, +#endif .fill_modes = drm_helper_probe_single_connector_modes, .destroy = dm_dp_mst_connector_destroy, .reset = amdgpu_dm_connector_funcs_reset, @@ -235,8 +270,12 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_set_property = amdgpu_dm_connector_atomic_set_property, .atomic_get_property = amdgpu_dm_connector_atomic_get_property, +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) .late_register = amdgpu_dm_mst_connector_late_register, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) .early_unregister = amdgpu_dm_mst_connector_early_unregister, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; bool needs_dsc_aux_workaround(struct dc_link *link) @@ -265,6 +304,7 @@ static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_m return false; } +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) { struct dc_sink *dc_sink = aconnector->dc_sink; @@ -274,7 +314,6 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 *dsc_branch_dec_caps = NULL; aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); - /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -310,6 +349,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto return true; } #endif +#endif static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) { @@ -352,8 +392,13 @@ static bool retrieve_branch_specific_data(struct amdgpu_dm_connector *aconnector (branch_desc.ident.oui[1] << 8) + (branch_desc.ident.oui[2]); +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(port->aux.drm_dev, "MST branch oui 0x%x detected at %s\n", aconnector->branch_ieee_oui, connector->name); +#else + DRM_DEBUG_KMS("MST branch oui 0x%x detected at %s\n", + aconnector->branch_ieee_oui, connector->name); +#endif return true; } @@ -366,6 +411,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!aconnector) return drm_add_edid_modes(connector, NULL); +#ifdef HAVE_DRM_DP_MST_EDID_READ if (!aconnector->drm_edid) { const struct drm_edid *drm_edid; @@ -374,12 +420,25 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) aconnector->mst_output_port); if (!drm_edid) { +#else + if (!aconnector->edid) { + struct edid *edid; + edid = drm_dp_mst_get_edid(connector, &aconnector->mst_root->mst_mgr, aconnector->mst_output_port); + + if (!edid) { +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, false); +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update( &aconnector->base, NULL); +#else + drm_connector_update_edid_property( + &aconnector->base, + NULL); +#endif DRM_DEBUG_KMS("Can't get EDID of %s. Add default remote sink.", connector->name); if (!aconnector->dc_sink) { @@ -411,7 +470,11 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) return ret; } +#ifdef HAVE_DRM_DP_MST_EDID_READ aconnector->drm_edid = drm_edid; +#else + aconnector->edid = edid; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID, true); } @@ -426,13 +489,20 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) struct dc_sink_init_data init_params = { .link = aconnector->dc_link, .sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST }; +#ifdef HAVE_DRM_DP_MST_EDID_READ const struct edid *edid; edid = drm_edid_raw(aconnector->drm_edid); // FIXME: Get rid of drm_edid_raw() +#endif dc_sink = dc_link_add_remote_sink( aconnector->dc_link, +#ifdef HAVE_DRM_DP_MST_EDID_READ (uint8_t *)edid, (edid->extensions + 1) * EDID_LENGTH, +#else + (uint8_t *)aconnector->edid, + (aconnector->edid->extensions + 1) * EDID_LENGTH, +#endif &init_params); if (!dc_sink) { @@ -456,6 +526,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) * plugged back with same display index, its hdcp properties * will be retrieved from hdcp_work within dm_dp_mst_get_modes */ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_sink && connector->state) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -471,42 +542,60 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) hdcp_w->content_protection[connector->index]; } } +#endif if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( +#ifdef HAVE_DRM_DP_MST_EDID_READ connector, aconnector->drm_edid); +#else + connector, aconnector->edid); +#endif +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) memset(&aconnector->dc_sink->dsc_caps, 0, sizeof(aconnector->dc_sink->dsc_caps)); #endif - +#endif if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); } } +#ifdef HAVE_DRM_DP_MST_EDID_READ drm_edid_connector_update(&aconnector->base, aconnector->drm_edid); ret = drm_edid_connector_add_modes(connector); +#else + drm_connector_update_edid_property( + &aconnector->base, aconnector->edid); + ret = drm_add_edid_modes(connector, aconnector->edid); +#endif return ret; } static struct drm_encoder * dm_mst_atomic_best_encoder(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); +#else + struct drm_connector_state *connector_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); return &adev->dm.mst_encoders[acrtc->crtc_id].base; } +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP static int dm_dp_mst_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, bool force) @@ -577,23 +666,47 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#endif +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; +#ifndef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS + struct drm_connector_state *new_conn_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_conn_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc_state *new_crtc_state; + + if (!old_conn_state->crtc) + return 0; + if (new_conn_state->crtc) { + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); + if (!new_crtc_state || + !drm_atomic_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->enable) + return 0; + } +#endif return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } +#endif static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP .detect_ctx = dm_dp_mst_detect, +#endif +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, +#endif }; static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) @@ -652,12 +765,20 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_PROBE, true); +#ifdef HAVE_DRM_CONNECTOR_DYNAMIC_INIT if (drm_connector_dynamic_init( +#else + if (drm_connector_init( +#endif dev, connector, &dm_dp_mst_connector_funcs, +#ifdef HAVE_DRM_CONNECTOR_DYNAMIC_INIT DRM_MODE_CONNECTOR_DisplayPort, NULL)) { +#else + DRM_MODE_CONNECTOR_DisplayPort)) { +#endif kfree(aconnector); return NULL; } @@ -691,10 +812,12 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, &connector->base, dev->mode_config.tile_property, 0); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY connector->colorspace_property = master->base.colorspace_property; if (connector->colorspace_property) drm_connector_attach_colorspace_property(connector); - +#endif drm_connector_set_path_property(connector, pathprop); if (!retrieve_branch_specific_data(aconnector)) @@ -706,7 +829,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, */ amdgpu_dm_connector_funcs_reset(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_get_port_malloc(port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ return connector; } @@ -779,6 +904,7 @@ void dm_handle_mst_sideband_msg_ready_event( /* handle MST irq */ if (aconnector->mst_mgr.mst_state) +#ifdef HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, esi, ack, @@ -802,6 +928,29 @@ void dm_handle_mst_sideband_msg_ready_event( } drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); +#else + drm_dp_mst_hpd_irq( + &aconnector->mst_mgr, + esi, + &new_irq_handled); + + if (new_irq_handled) { + /* ACK at DPCD to notify down stream */ + const int ack_dpcd_bytes_to_write = + dpcd_bytes_to_read - 1; + + for (retry = 0; retry < 3; retry++) { + u8 wret; + + wret = drm_dp_dpcd_write( + &aconnector->dm_dp_aux.aux, + dpcd_addr + 1, + &esi[1], + ack_dpcd_bytes_to_write); + if (wret == ack_dpcd_bytes_to_write) + break; + } +#endif new_irq_handled = false; } else { @@ -815,14 +964,75 @@ void dm_handle_mst_sideband_msg_ready_event( DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) { dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#endif + +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR +static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_connector *connector) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + + DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", + aconnector, connector->base.id, aconnector->mst_root); + + if (aconnector->dc_sink) { + amdgpu_dm_update_freesync_caps(connector, NULL); + dc_link_remove_remote_sink(aconnector->dc_link, + aconnector->dc_sink); + dc_sink_release(aconnector->dc_sink); + aconnector->dc_sink = NULL; + mutex_lock(&mgr->lock); + if (!mgr->mst_state) + aconnector->dc_link->cur_link_settings.lane_count = 0; + mutex_unlock(&mgr->lock); + } + drm_connector_unregister(connector); + drm_connector_put(connector); +} +#endif + +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) +static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + + drm_kms_helper_hotplug_event(dev); +} +#endif + +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR +static void dm_dp_mst_register_connector(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + + drm_connector_register(connector); +} +#endif static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + .destroy_connector = dm_dp_destroy_mst_connector, +#endif +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) + .hotplug = dm_dp_mst_hotplug, +#endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + .register_connector = dm_dp_mst_register_connector +#endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, +#endif }; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, @@ -835,13 +1045,17 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", link_index); aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; +#ifdef HAVE_DRM_DP_AUX_DRM_DEV aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; +#endif aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; drm_dp_aux_init(&aconnector->dm_dp_aux.aux); drm_dp_cec_register_connector(&aconnector->dm_dp_aux.aux, &aconnector->base); +#ifdef HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED drm_dp_dpcd_set_probe(&aconnector->dm_dp_aux.aux, false); +#endif if (aconnector->base.connector_type == DRM_MODE_CONNECTOR_eDP) return; @@ -849,7 +1063,12 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); aconnector->mst_mgr.cbs = &dm_mst_cbs; drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), - &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); + &aconnector->dm_dp_aux.aux, 16, 4, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), +#endif + aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); } @@ -870,6 +1089,7 @@ uint32_t dm_mst_get_pbn_divider(struct dc_link *link) return dfixed_const(pbn_div_x100) / 100; } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; @@ -882,6 +1102,7 @@ struct dsc_mst_fairness_params { uint32_t bpp_overwrite; struct amdgpu_dm_connector *aconnector; }; +#endif #if defined(CONFIG_DRM_AMD_DC_FP) static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) @@ -906,6 +1127,7 @@ static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, int count, @@ -919,7 +1141,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p drm_connector = ¶ms[i].aconnector->base; dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); if (vars[i + k].dsc_enabled && dc_dsc_compute_config( @@ -972,7 +1198,11 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); dc_dsc_compute_config( @@ -1000,11 +1230,18 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) + int pbn_per_timeslot; +#endif int link_timeslots_used; int fair_pbn_alloc; int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) + pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); +#endif + for (i = 0; i < count; i++) { if (vars[i + k].dsc_enabled) { initial_slack[i] = @@ -1035,17 +1272,36 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, link_timeslots_used = 0; for (i = 0; i < count; i++) - link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div)); + link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION + dfixed_trunc(mst_state->pbn_div) +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div +#else + pbn_per_timeslot +#endif + ); fair_pbn_alloc = - (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div); + (63 - link_timeslots_used) / remaining_to_increase * +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION + dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div; +#else + pbn_per_timeslot; +#endif if (initial_slack[next_index] > fair_pbn_alloc) { vars[next_index].pbn += fair_pbn_alloc; ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1057,7 +1313,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1066,7 +1326,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1078,7 +1342,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1141,7 +1409,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) { DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", __func__, __LINE__, next_index, ret); @@ -1160,7 +1432,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) { DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", __func__, __LINE__, next_index, ret); @@ -1282,7 +1558,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, - vars[i + k].pbn); + vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } @@ -1304,7 +1584,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = true; vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } else { @@ -1312,7 +1596,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } @@ -1744,9 +2032,11 @@ int pre_validate_dsc(struct drm_atomic_state *state, int ind = find_crtc_index_in_state_by_stream(state, stream); if (ind >= 0) { + struct dm_crtc_state *dm_new_crtc_state = to_dm_crtc_state(state->crtcs[ind].new_state); + DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n", __func__, __LINE__, stream); - state->crtcs[ind].new_state->mode_changed = 0; + dm_new_crtc_state->base.mode_changed = dm_new_crtc_state->mode_changed_independent_from_dsc; } } } @@ -1792,6 +2082,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, return is_dsc_possible; } #endif +#endif /* HAVE_DRM_DP_MST_ATOMIC_CHECK */ #if defined(CONFIG_DRM_AMD_DC_FP) static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw) @@ -1812,9 +2103,13 @@ static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_lin dp_link_encoding = data[DP_MAIN_LINK_CHANNEL_CODING_SET - DP_LINK_BW_SET]; link_bw_set = data[DP_LINK_BW_SET - DP_LINK_BW_SET]; lane_count.raw = data[DP_LANE_COUNT_SET - DP_LINK_BW_SET]; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "MST_DSC downlink setting: %d, 0x%x x %d\n", dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); +#else + DRM_DEBUG_KMS("MST_DSC downlink setting: %d, 0x%x x %d\n", + dp_link_encoding, link_bw_set, lane_count.bits.LANE_COUNT_SET); +#endif switch (dp_link_encoding) { case DP_8b_10b_ENCODING: @@ -1857,6 +2152,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( { #if defined(CONFIG_DRM_AMD_DC_FP) int branch_max_throughput_mps = 0; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) && defined(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP) struct dc_link_settings cur_link_settings; uint32_t end_to_end_bw_in_kbps = 0; uint32_t root_link_bw_in_kbps = 0; @@ -1982,6 +2278,43 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } +#else + int pbn; + /* Check if mode could be supported within max slot + * number of current mst link and full_pbn of mst links. + */ + int pbn_div, slot_num, max_slot_num; + enum dc_link_encoding_format link_encoding; + uint16_t fec_overhead_multiplier_x1000 = + get_fec_overhead_multiplier(stream->link); + uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( + &stream->timing, + dc_link_get_highest_encoding_format(stream->link)); + + pbn = kbps_to_peak_pbn(stream_kbps, fec_overhead_multiplier_x1000); + pbn_div = dm_mst_get_pbn_divider(stream->link); + slot_num = DIV_ROUND_UP(pbn, pbn_div); + + link_encoding = dc_link_get_highest_encoding_format(stream->link); + if (link_encoding == DC_LINK_ENCODING_DP_8b_10b) + max_slot_num = 63; + else if (link_encoding == DC_LINK_ENCODING_DP_128b_132b) + max_slot_num = 64; + else { + DRM_DEBUG_DRIVER("Invalid link encoding format\n"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } + + if (slot_num > max_slot_num || +#ifdef HAVE_DRM_DP_MST_PORT_FULL_PBN + pbn > aconnector->mst_output_port->full_pbn) { +#else + pbn > aconnector->mst_output_port->available_pbn) { +#endif + DRM_DEBUG_DRIVER("Mode can not be supported within mst links!"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } +#endif #endif return DC_OK; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 7c4496fb4b9d4..d4c904f40175b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT /* - * Copyright 2022 Advanced Micro Devices, Inc. + * Copyright 2022-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -55,10 +55,12 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_ABGR2101010, +#ifdef DRM_FORMAT_XRGB16161616 DRM_FORMAT_XRGB16161616, DRM_FORMAT_XBGR16161616, DRM_FORMAT_ARGB16161616, DRM_FORMAT_ABGR16161616, +#endif DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, @@ -93,10 +95,19 @@ enum dm_micro_swizzle { MICRO_SWIZZLE_R = 3 }; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier) { return amdgpu_lookup_format_info(pixel_format, modifier); } +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); +} +#endif +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, @@ -278,7 +289,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, if (!dcc->enable) return 0; - if (adev->family < AMDGPU_FAMILY_GC_12_0_0 && + if (adev->family != AMDGPU_FAMILY_GC_12_0_0 && format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return -EINVAL; @@ -308,6 +319,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, const enum surface_pixel_format format, @@ -358,6 +370,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg return ret; } +#endif static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, @@ -704,21 +717,21 @@ static void amdgpu_dm_plane_add_gfx12_modifiers(struct amdgpu_device *adev, uint8_t max_comp_block[] = {2, 1, 0}; uint64_t max_comp_block_mod[ARRAY_SIZE(max_comp_block)] = {0}; uint8_t i = 0, j = 0; - uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b, DRM_FORMAT_MOD_LINEAR}; + /* Note, linear (no DCC) gets added to the modifier list for all chips by the caller. */ + uint64_t gfx12_modifiers[] = {mod_256k, mod_64k, mod_4k, mod_256b}; for (i = 0; i < ARRAY_SIZE(max_comp_block); i++) max_comp_block_mod[i] = AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block[i]); /* With DCC: Best choice should be kept first. Hence, add all 256k modifiers of different * max compressed blocks first and then move on to the next smaller sized layouts. - * Do not add the linear modifier here, and hence the condition of size-1 for the loop */ - for (j = 0; j < ARRAY_SIZE(gfx12_modifiers) - 1; j++) + for (j = 0; j < ARRAY_SIZE(gfx12_modifiers); j++) for (i = 0; i < ARRAY_SIZE(max_comp_block); i++) amdgpu_dm_plane_add_modifier(mods, size, capacity, ver | dcc | max_comp_block_mod[i] | gfx12_modifiers[j]); - /* Without DCC. Add all modifiers including linear at the end */ + /* Without DCC. */ for (i = 0; i < ARRAY_SIZE(gfx12_modifiers); i++) amdgpu_dm_plane_add_modifier(mods, size, capacity, gfx12_modifiers[i]); @@ -759,6 +772,7 @@ static int amdgpu_dm_plane_get_plane_modifiers(struct amdgpu_device *adev, unsig case AMDGPU_FAMILY_GC_11_0_0: case AMDGPU_FAMILY_GC_11_0_1: case AMDGPU_FAMILY_GC_11_5_0: + case AMDGPU_FAMILY_GC_11_5_4: amdgpu_dm_plane_add_gfx11_modifiers(adev, mods, &size, &capacity); break; case AMDGPU_FAMILY_GC_12_0_0: @@ -800,8 +814,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; + if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; + if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; @@ -901,7 +917,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, upper_32_bits(chroma_addr); } - if (adev->family >= AMDGPU_FAMILY_GC_12_0_0) { + if (adev->family == AMDGPU_FAMILY_GC_12_0_0) { ret = amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, @@ -909,12 +925,14 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, if (ret) return ret; } else if (adev->family >= AMDGPU_FAMILY_AI) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, address); if (ret) return ret; +#endif } else { amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); } @@ -953,7 +971,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); goto error_unlock; @@ -978,9 +996,11 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, goto error_unpin; } +#ifdef HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB r = drm_gem_plane_helper_prepare_fb(plane, new_state); if (unlikely(r != 0)) goto error_unpin; +#endif amdgpu_bo_unreserve(rbo); @@ -1031,7 +1051,7 @@ static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, if (!old_state->fb) return; - rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(old_state->fb, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { DRM_ERROR("failed to reserve rbo before unpin\n"); @@ -1060,10 +1080,17 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, *min_downscale = plane_cap->max_downscale_factor.nv12; break; + /* All 64 bpp formats have the same fp16 scaling limits */ case DRM_FORMAT_XRGB16161616F: case DRM_FORMAT_ARGB16161616F: case DRM_FORMAT_XBGR16161616F: case DRM_FORMAT_ABGR16161616F: +#ifdef DRM_FORMAT_XRGB16161616 + case DRM_FORMAT_XRGB16161616: + case DRM_FORMAT_ARGB16161616: + case DRM_FORMAT_XBGR16161616: + case DRM_FORMAT_ABGR16161616: +#endif *max_upscale = plane_cap->max_upscale_factor.fp16; *min_downscale = plane_cap->max_downscale_factor.fp16; break; @@ -1165,8 +1192,8 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, */ if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && - (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && - (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) + (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && + (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) return -EINVAL; scaling_info->src_rect.width = state->src_w >> 16; @@ -1223,10 +1250,18 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, } static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state = state; +#endif struct amdgpu_device *adev = drm_to_adev(plane->dev); struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state; @@ -1241,9 +1276,13 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = - drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + new_crtc_state = +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif + if (!new_crtc_state) return -EINVAL; @@ -1251,6 +1290,16 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (ret) return ret; +#ifdef HAVE_DRM_DRM_COLOROP_H + /* Reject commits that attempt to use both COLOR_PIPELINE and CRTC DEGAMMA_LUT */ + if (new_plane_state->color_pipeline && new_crtc_state->degamma_lut) { + drm_dbg_atomic(plane->dev, + "[PLANE:%d:%s] COLOR_PIPELINE and CRTC DEGAMMA_LUT cannot be enabled simultaneously\n", + plane->base.id, plane->name); + return -EINVAL; + } +#endif + ret = amdgpu_dm_plane_fill_dc_scaling_info(adev, new_plane_state, &scaling_info); if (ret) return ret; @@ -1262,24 +1311,44 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, } static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS struct drm_atomic_state *state, bool flip) +#elif HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *state) +#endif { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; struct dm_crtc_state *dm_new_crtc_state; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS if (flip) { if (plane->type != DRM_PLANE_TYPE_OVERLAY) return -EINVAL; } else if (plane->type != DRM_PLANE_TYPE_CURSOR) { return -EINVAL; } +#else + /* Only support async updates on cursor planes. */ + if (plane->type != DRM_PLANE_TYPE_CURSOR) + return -EINVAL; +#endif +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS new_plane_state = drm_atomic_get_new_plane_state(state, plane); new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + new_crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); /* Reject overlay cursors for now*/ +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS if (!flip && dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) +#else + if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) +#endif return -EINVAL; return 0; @@ -1403,12 +1472,21 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *new_state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); +#else + struct drm_plane_state *old_state = + drm_atomic_get_old_plane_state(new_state->state, plane); +#endif trace_amdgpu_dm_atomic_update_cursor(new_state); @@ -1426,6 +1504,7 @@ static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, amdgpu_dm_plane_handle_cursor_update(plane, old_state); } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane->state); @@ -1439,6 +1518,7 @@ static void amdgpu_dm_plane_panic_flush(struct drm_plane *plane) dc_plane_force_dcc_and_tiling_disable(dc_plane_state, fb->modifier ? true : false); } +#endif static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, @@ -1454,8 +1534,10 @@ static const struct drm_plane_helper_funcs dm_primary_plane_helper_funcs = { .atomic_check = amdgpu_dm_plane_atomic_check, .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER .get_scanout_buffer = amdgpu_display_get_scanout_buffer, .panic_flush = amdgpu_dm_plane_panic_flush, +#endif }; static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) @@ -1518,6 +1600,7 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct return &dm_plane_state->base; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, uint64_t modifier) @@ -1579,6 +1662,7 @@ static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, return true; } +#endif static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) @@ -1650,7 +1734,7 @@ dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, MAX_COLOR_3DLUT_SIZE); } - if (dpp_color_caps.ogam_ram) { + if (dpp_color_caps.ogam_ram || dm->dc->caps.color.mpc.preblend) { drm_object_attach_property(&plane->base, mode_info.plane_blend_lut_property, 0); drm_object_attach_property(&plane->base, @@ -1676,8 +1760,8 @@ dm_atomic_plane_set_property(struct drm_plane *plane, if (property == adev->mode_info.plane_degamma_lut_property) { ret = drm_property_replace_blob_from_id(plane->dev, &dm_plane_state->degamma_lut, - val, -1, - sizeof(struct drm_color_lut), + val, + -1, -1, sizeof(struct drm_color_lut), &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; @@ -1695,15 +1779,15 @@ dm_atomic_plane_set_property(struct drm_plane *plane, ret = drm_property_replace_blob_from_id(plane->dev, &dm_plane_state->ctm, val, - sizeof(struct drm_color_ctm_3x4), -1, + -1, sizeof(struct drm_color_ctm_3x4), -1, &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; } else if (property == adev->mode_info.plane_shaper_lut_property) { ret = drm_property_replace_blob_from_id(plane->dev, &dm_plane_state->shaper_lut, - val, -1, - sizeof(struct drm_color_lut), + val, + -1, -1, sizeof(struct drm_color_lut), &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; @@ -1715,16 +1799,16 @@ dm_atomic_plane_set_property(struct drm_plane *plane, } else if (property == adev->mode_info.plane_lut3d_property) { ret = drm_property_replace_blob_from_id(plane->dev, &dm_plane_state->lut3d, - val, -1, - sizeof(struct drm_color_lut), + val, + -1, -1, sizeof(struct drm_color_lut), &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; } else if (property == adev->mode_info.plane_blend_lut_property) { ret = drm_property_replace_blob_from_id(plane->dev, &dm_plane_state->blend_lut, - val, -1, - sizeof(struct drm_color_lut), + val, + -1, -1, sizeof(struct drm_color_lut), &replaced); dm_plane_state->base.color_mgmt_changed |= replaced; return ret; @@ -1784,7 +1868,7 @@ dm_atomic_plane_get_property(struct drm_plane *plane, return 0; } #else - +#ifdef HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY #define MAX_COLOR_PIPELINES 5 static int @@ -1803,14 +1887,16 @@ dm_plane_init_colorops(struct drm_plane *plane) /* initialize pipeline */ if (dc->ctx->dce_version >= DCN_VERSION_3_0) { +#ifdef HAVE_DRM_DRM_COLOROP_H ret = amdgpu_dm_initialize_default_pipeline(plane, &pipelines[len]); if (ret) { drm_err(plane->dev, "Failed to create color pipeline for plane %d: %d\n", plane->base.id, ret); goto out; } - len++; + len++; +#endif /* Create COLOR_PIPELINE property and attach */ drm_plane_create_color_pipeline_property(plane, pipelines, len); } @@ -1822,6 +1908,7 @@ dm_plane_init_colorops(struct drm_plane *plane) return ret; } #endif +#endif static const struct drm_plane_funcs dm_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, @@ -1830,7 +1917,9 @@ static const struct drm_plane_funcs dm_plane_funcs = { .reset = amdgpu_dm_plane_drm_plane_reset, .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .format_mod_supported = amdgpu_dm_plane_format_mod_supported, +#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = dm_atomic_plane_set_property, .atomic_get_property = dm_atomic_plane_get_property, @@ -1852,12 +1941,16 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, ARRAY_SIZE(formats)); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); if (res) return res; +#endif +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; +#endif res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, &dm_plane_funcs, formats, num_formats, @@ -1894,7 +1987,8 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_create_zpos_immutable_property(plane, 255); } - if (plane->type == DRM_PLANE_TYPE_PRIMARY && + if ((plane->type == DRM_PLANE_TYPE_PRIMARY || + plane->type == DRM_PLANE_TYPE_OVERLAY) && plane_cap && (plane_cap->pixel_format_support.nv12 || plane_cap->pixel_format_support.p010)) { @@ -1930,9 +2024,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, #ifdef AMD_PRIVATE_COLOR dm_atomic_plane_attach_color_mgmt_properties(dm, plane); #else +#ifdef HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY res = dm_plane_init_colorops(plane); if (res) return res; +#endif #endif /* Create (reset) the plane state */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h index ea2619b507db7..3b583bbca535a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.h @@ -58,7 +58,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, unsigned long possible_crtcs, const struct dc_plane_cap *plane_cap); +#ifdef HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS const struct drm_format_info *amdgpu_dm_plane_get_format_info(u32 pixel_format, u64 modifier); +#else +const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c index fd491b7a3cd70..99d6d6c935610 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c @@ -80,12 +80,20 @@ void amdgpu_dm_set_psr_caps(struct dc_link *link) link->psr_settings.psr_feature_enabled = false; } else { + unsigned int panel_inst = 0; + if (link_supports_psrsu(link)) link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; else link->psr_settings.psr_version = DC_PSR_VERSION_1; link->psr_settings.psr_feature_enabled = true; + + /*disable allow psr/psrsu/replay on eDP1*/ + if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) { + link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; + link->psr_settings.psr_feature_enabled = false; + } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c index da94e3544b657..8c150b0011059 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c @@ -154,14 +154,21 @@ bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) { bool replay_active = true; struct dc_link *link = NULL; + struct amdgpu_dm_connector *aconnector = NULL; if (stream == NULL) return false; + /* Check if replay is disabled by connector flag */ + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + if (!aconnector || aconnector->disallow_edp_enter_replay) { + return false; + } + link = stream->link; if (link) { - link->dc->link_srv->edp_setup_replay(link, stream); + link->dc->link_srv->dp_setup_replay(link, stream); link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0); DRM_DEBUG_DRIVER("Enabling replay...\n"); link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index aa56fd6d56c34..d7b955f964f4f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -41,6 +41,7 @@ #include "dc/inc/hw/optc.h" #include "dc/inc/core_types.h" +#include DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), @@ -88,7 +89,7 @@ TRACE_EVENT(amdgpu_dc_performance, __entry->writes = write_count; __entry->read_delta = read_count - *last_read; __entry->write_delta = write_count - *last_write; - __assign_str(func); + __amdkcl_assign_str(func, func); __entry->line = line; *last_read = read_count; *last_write = write_count; @@ -113,13 +114,19 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __field(uint32_t, crtc_id) __field(uint32_t, best_encoder_id) __field(enum drm_link_status, link_status) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_aware) +#endif __field(enum hdmi_picture_aspect, picture_aspect_ratio) __field(unsigned int, content_type) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __field(unsigned int, hdcp_content_type) +#endif __field(unsigned int, content_protection) __field(unsigned int, scaling_mode) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __field(u32, colorspace) +#endif __field(u8, max_requested_bpc) __field(u8, max_bpc) ), @@ -133,28 +140,52 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __entry->best_encoder_id = state->best_encoder ? state->best_encoder->base.id : 0; __entry->link_status = state->link_status; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_aware = state->self_refresh_aware; +#endif __entry->picture_aspect_ratio = state->picture_aspect_ratio; __entry->content_type = state->content_type; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __entry->hdcp_content_type = state->hdcp_content_type; +#endif __entry->content_protection = state->content_protection; __entry->scaling_mode = state->scaling_mode; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __entry->colorspace = state->colorspace; +#endif __entry->max_requested_bpc = state->max_requested_bpc; __entry->max_bpc = state->max_bpc; ), TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u " - "best_encoder_id=%u link_status=%d self_refresh_aware=%d " + "best_encoder_id=%u link_status=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_aware=%d " +#endif "picture_aspect_ratio=%d content_type=%u " - "hdcp_content_type=%u content_protection=%u scaling_mode=%u " - "colorspace=%u max_requested_bpc=%u max_bpc=%u", +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + "hdcp_content_type=%u " +#endif + "content_protection=%u scaling_mode=%u " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + "colorspace=%u " +#endif + "max_requested_bpc=%u max_bpc=%u", __entry->conn_id, __entry->conn_state, __entry->state, __entry->commit, __entry->crtc_id, __entry->best_encoder_id, - __entry->link_status, __entry->self_refresh_aware, + __entry->link_status, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_aware, +#endif __entry->picture_aspect_ratio, __entry->content_type, - __entry->hdcp_content_type, __entry->content_protection, - __entry->scaling_mode, __entry->colorspace, +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + __entry->hdcp_content_type, +#endif + __entry->content_protection, + __entry->scaling_mode, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + __entry->colorspace, +#endif __entry->max_requested_bpc, __entry->max_bpc) ); @@ -176,9 +207,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __field(bool, zpos_changed) __field(bool, color_mgmt_changed) __field(bool, no_vblank) +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __field(bool, async_flip) +#endif __field(bool, vrr_enabled) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_active) +#endif __field(u32, plane_mask) __field(u32, connector_mask) __field(u32, encoder_mask) @@ -198,9 +233,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __entry->zpos_changed = state->zpos_changed; __entry->color_mgmt_changed = state->color_mgmt_changed; __entry->no_vblank = state->no_vblank; +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __entry->async_flip = state->async_flip; +#endif __entry->vrr_enabled = state->vrr_enabled; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_active = state->self_refresh_active; +#endif __entry->plane_mask = state->plane_mask; __entry->connector_mask = state->connector_mask; __entry->encoder_mask = state->encoder_mask; @@ -208,16 +247,29 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed(" "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) " - "state(enable=%d active=%d async_flip=%d vrr_enabled=%d " - "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x " + "state(enable=%d active=%d " +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + "async_flip=%d " +#endif + "vrr_enabled=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_active=%d " +#endif + "no_vblank=%d) mask(plane=%x conn=%x " "enc=%x)", __entry->crtc_id, __entry->crtc_state, __entry->state, __entry->commit, __entry->planes_changed, __entry->mode_changed, __entry->active_changed, __entry->connectors_changed, __entry->zpos_changed, __entry->color_mgmt_changed, __entry->enable, __entry->active, - __entry->async_flip, __entry->vrr_enabled, - __entry->self_refresh_active, __entry->no_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + __entry->async_flip, +#endif + __entry->vrr_enabled, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_active, +#endif + __entry->no_vblank, __entry->plane_mask, __entry->connector_mask, __entry->encoder_mask) ); @@ -323,7 +375,9 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __field(bool, allow_modeset) __field(bool, legacy_cursor_update) __field(bool, async_update) +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __field(bool, duplicated) +#endif __field(int, num_connector) __field(int, num_private_objs) ), @@ -333,16 +387,26 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __entry->allow_modeset = state->allow_modeset; __entry->legacy_cursor_update = state->legacy_cursor_update; __entry->async_update = state->async_update; +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __entry->duplicated = state->duplicated; +#endif __entry->num_connector = state->num_connector; __entry->num_private_objs = state->num_private_objs; ), TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d " - "async_update=%d duplicated=%d num_connector=%d " + "async_update=%d " +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + "duplicated=%d " +#endif + "num_connector=%d " "num_private_objs=%d", __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update, - __entry->async_update, __entry->duplicated, __entry->num_connector, + __entry->async_update, +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + __entry->duplicated, +#endif + __entry->num_connector, __entry->num_private_objs) ); @@ -621,6 +685,7 @@ TRACE_EVENT(amdgpu_dmub_trace_high_irq, __entry->param0, __entry->param1) ); +#ifndef HAVE_KTIME_IS_UNION TRACE_EVENT(amdgpu_refresh_rate_track, TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz), TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz), @@ -639,6 +704,7 @@ TRACE_EVENT(amdgpu_refresh_rate_track, __entry->refresh_rate_hz, __entry->refresh_rate_ns) ); +#endif TRACE_EVENT(dcn_fpu, TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth), diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index d9527c05fc878..fab8b363e6477 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -80,6 +80,7 @@ static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector) return drm_add_modes_noedid(connector, 3840, 2160); } +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, struct drm_writeback_job *job) { @@ -106,7 +107,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r); goto error_unlock; @@ -164,6 +165,7 @@ static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector, amdgpu_bo_unreserve(rbo); amdgpu_bo_unref(&rbo); } +#endif static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = { .atomic_check = amdgpu_dm_wb_encoder_atomic_check, @@ -179,8 +181,10 @@ static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = { static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = { .get_modes = amdgpu_dm_wb_connector_get_modes, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB .prepare_writeback_job = amdgpu_dm_wb_prepare_job, .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job, +#endif }; int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index e46f8ce41d871..35066ae9acbce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -26,7 +26,24 @@ #include "dc_trace.h" +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT #include +#else +#if defined(CONFIG_X86) +#if defined(HAVE_ASM_FPU_API_H) +#include +#else +#include +#endif +#elif defined(CONFIG_PPC64) +#include +#include +#elif defined(CONFIG_ARM64) +#include +#elif defined(CONFIG_LOONGARCH) +#include +#endif +#endif /** * DOC: DC FPU manipulation overview @@ -79,8 +96,19 @@ void dc_fpu_begin(const char *function_name, const int line) preempt_disable(); depth = __this_cpu_inc_return(fpu_recursion_depth); if (depth == 1) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT BUG_ON(!kernel_fpu_available()); kernel_fpu_begin(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) + kernel_fpu_begin(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + enable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_begin(); +#endif +#endif } TRACE_DCN_FPU(true, function_name, line, depth); @@ -102,7 +130,18 @@ void dc_fpu_end(const char *function_name, const int line) depth = __this_cpu_dec_return(fpu_recursion_depth); if (depth == 0) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + kernel_fpu_end(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) kernel_fpu_end(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + disable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_end(); +#endif +#endif } else { WARN_ON_ONCE(depth < 0); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h index b8275b3979205..4e921632bc4e9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.h @@ -31,4 +31,12 @@ void dc_assert_fp_enabled(void); void dc_fpu_begin(const char *function_name, const int line); void dc_fpu_end(const char *function_name, const int line); +#ifndef _LINUX_FPU_COMPILATION_UNIT +#define DC_FP_START() dc_fpu_begin(__func__, __LINE__) +#define DC_FP_END() dc_fpu_end(__func__, __LINE__) +#else +#define DC_FP_START() BUILD_BUG() +#define DC_FP_END() BUILD_BUG() +#endif + #endif /* __DC_FPU_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 7277ed21552f3..93d02956c5eb5 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -22,7 +22,7 @@ # # Makefile for Display Core (dc) component. -DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link virtual dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg +DC_LIBS = basics bios dml clk_mgr dce gpio hwss irq link dsc resource optc dpp hubbub dccg hubp dio dwb hpo mmhubbub mpc opp pg ifdef CONFIG_DRM_AMD_DC_FP diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 9f11e6ca40510..82877f7b3b6fb 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -780,28 +780,31 @@ static enum bp_result bios_parser_encoder_control( return bp->cmd_tbl.dig_encoder_control(bp, cntl); } +static enum bp_result bios_parser_external_encoder_control( + struct dc_bios *dcb, + struct bp_external_encoder_control *cntl) +{ + struct bios_parser *bp = BP_FROM_DCB(dcb); + + if (!bp->cmd_tbl.external_encoder_control) + return BP_RESULT_UNSUPPORTED; + + return bp->cmd_tbl.external_encoder_control(bp, cntl); +} + static enum bp_result bios_parser_dac_load_detection( struct dc_bios *dcb, - enum engine_id engine_id, - enum dal_device_type device_type, - uint32_t enum_id) + enum engine_id engine_id) { struct bios_parser *bp = BP_FROM_DCB(dcb); struct dc_context *ctx = dcb->ctx; struct bp_load_detection_parameters bp_params = {0}; - enum bp_result bp_result; + enum bp_result bp_result = BP_RESULT_UNSUPPORTED; uint32_t bios_0_scratch; uint32_t device_id_mask = 0; - bp_params.engine_id = engine_id; - bp_params.device_id = get_support_mask_for_device_id(device_type, enum_id); - - if (engine_id != ENGINE_ID_DACA && - engine_id != ENGINE_ID_DACB) - return BP_RESULT_UNSUPPORTED; - - if (!bp->cmd_tbl.dac_load_detection) - return BP_RESULT_UNSUPPORTED; + bp_params.device_id = get_support_mask_for_device_id( + DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1); if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT) device_id_mask = ATOM_S0_CRT1_MASK; @@ -815,7 +818,13 @@ static enum bp_result bios_parser_dac_load_detection( bios_0_scratch &= ~device_id_mask; dm_write_reg(ctx, bp->base.regs->BIOS_SCRATCH_0, bios_0_scratch); - bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + if (engine_id == ENGINE_ID_DACA || engine_id == ENGINE_ID_DACB) { + if (!bp->cmd_tbl.dac_load_detection) + return BP_RESULT_UNSUPPORTED; + + bp_params.engine_id = engine_id; + bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params); + } if (bp_result != BP_RESULT_OK) return bp_result; @@ -2912,6 +2921,8 @@ static const struct dc_vbios_funcs vbios_funcs = { .encoder_control = bios_parser_encoder_control, + .external_encoder_control = bios_parser_external_encoder_control, + .dac_load_detection = bios_parser_dac_load_detection, .transmitter_control = bios_parser_transmitter_control, diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c index 76a3559f0ddc1..f6e22dcecf29e 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c @@ -226,6 +226,28 @@ static enum bp_result encoder_control_dig2_v1( return result; } +static uint8_t dc_color_depth_to_atom(enum dc_color_depth color_depth) +{ + switch (color_depth) { + case COLOR_DEPTH_UNDEFINED: + return PANEL_BPC_UNDEFINE; + case COLOR_DEPTH_666: + return PANEL_6BIT_PER_COLOR; + default: + case COLOR_DEPTH_888: + return PANEL_8BIT_PER_COLOR; + case COLOR_DEPTH_101010: + return PANEL_10BIT_PER_COLOR; + case COLOR_DEPTH_121212: + return PANEL_12BIT_PER_COLOR; + case COLOR_DEPTH_141414: + dm_error("14-bit color not supported by ATOMBIOS\n"); + return PANEL_BPC_UNDEFINE; + case COLOR_DEPTH_161616: + return PANEL_16BIT_PER_COLOR; + } +} + static enum bp_result encoder_control_digx_v3( struct bios_parser *bp, struct bp_encoder_control *cntl) @@ -248,23 +270,7 @@ static enum bp_result encoder_control_digx_v3( cntl->signal, cntl->enable_dp_audio); params.ucLaneNum = (uint8_t)(cntl->lanes_number); - - switch (cntl->color_depth) { - case COLOR_DEPTH_888: - params.ucBitPerColor = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucBitPerColor = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucBitPerColor = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_161616: - params.ucBitPerColor = PANEL_16BIT_PER_COLOR; - break; - default: - break; - } + params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) result = BP_RESULT_OK; @@ -294,23 +300,7 @@ static enum bp_result encoder_control_digx_v4( cntl->signal, cntl->enable_dp_audio)); params.ucLaneNum = (uint8_t)(cntl->lanes_number); - - switch (cntl->color_depth) { - case COLOR_DEPTH_888: - params.ucBitPerColor = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucBitPerColor = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucBitPerColor = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_161616: - params.ucBitPerColor = PANEL_16BIT_PER_COLOR; - break; - default: - break; - } + params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); if (EXEC_BIOS_CMD_TABLE(DIGxEncoderControl, params)) result = BP_RESULT_OK; @@ -334,23 +324,7 @@ static enum bp_result encoder_control_digx_v5( cntl->signal, cntl->enable_dp_audio)); params.ucLaneNum = (uint8_t)(cntl->lanes_number); - - switch (cntl->color_depth) { - case COLOR_DEPTH_888: - params.ucBitPerColor = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucBitPerColor = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucBitPerColor = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_161616: - params.ucBitPerColor = PANEL_16BIT_PER_COLOR; - break; - default: - break; - } + params.ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); if (cntl->signal == SIGNAL_TYPE_HDMI_TYPE_A) switch (cntl->color_depth) { @@ -1797,30 +1771,7 @@ static enum bp_result select_crtc_source_v3( ¶ms.ucEncodeMode)) return BP_RESULT_BADINPUT; - switch (bp_params->color_depth) { - case COLOR_DEPTH_UNDEFINED: - params.ucDstBpc = PANEL_BPC_UNDEFINE; - break; - case COLOR_DEPTH_666: - params.ucDstBpc = PANEL_6BIT_PER_COLOR; - break; - default: - case COLOR_DEPTH_888: - params.ucDstBpc = PANEL_8BIT_PER_COLOR; - break; - case COLOR_DEPTH_101010: - params.ucDstBpc = PANEL_10BIT_PER_COLOR; - break; - case COLOR_DEPTH_121212: - params.ucDstBpc = PANEL_12BIT_PER_COLOR; - break; - case COLOR_DEPTH_141414: - dm_error("14-bit color not supported by SelectCRTC_Source v3\n"); - break; - case COLOR_DEPTH_161616: - params.ucDstBpc = PANEL_16BIT_PER_COLOR; - break; - } + params.ucDstBpc = dc_color_depth_to_atom(bp_params->color_depth); if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) result = BP_RESULT_OK; @@ -1874,8 +1825,7 @@ static void dac_encoder_control_prepare_params( uint8_t dac_standard) { params->ucDacStandard = dac_standard; - if (action == ENCODER_CONTROL_SETUP || - action == ENCODER_CONTROL_INIT) + if (action == ENCODER_CONTROL_INIT) params->ucAction = ATOM_ENCODER_INIT; else if (action == ENCODER_CONTROL_ENABLE) params->ucAction = ATOM_ENABLE; @@ -2570,6 +2520,7 @@ static enum bp_result external_encoder_control_v3( cpu_to_le16((uint16_t)cntl->connector_obj_id.id); break; case EXTERNAL_ENCODER_CONTROL_SETUP: + case EXTERNAL_ENCODER_CONTROL_ENABLE: /* EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 pixel clock unit in * 10KHz * output display device pixel clock frequency in unit of 10KHz. @@ -2586,26 +2537,24 @@ static enum bp_result external_encoder_control_v3( if (is_input_signal_dp) { /* Bit[0]: indicate link rate, =1: 2.7Ghz, =0: 1.62Ghz, * only valid in encoder setup with DP mode. */ - if (LINK_RATE_HIGH == cntl->link_rate) - cntl_params->ucConfig |= 1; + if (cntl->link_rate == LINK_RATE_LOW) + cntl_params->ucConfig |= + EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ; + else if (cntl->link_rate == LINK_RATE_HIGH) + cntl_params->ucConfig |= + EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; + else + dm_error("Link rate not supported by external encoder"); + /* output color depth Indicate encoder data bpc format * in DP mode, only valid in encoder setup in DP mode. */ - cntl_params->ucBitPerColor = - (uint8_t)(cntl->color_depth); + cntl_params->ucBitPerColor = dc_color_depth_to_atom(cntl->color_depth); } /* Indicate how many lanes used by external encoder, only valid * in encoder setup and enableoutput. */ cntl_params->ucLaneNum = (uint8_t)(cntl->lanes_number); break; - case EXTERNAL_ENCODER_CONTROL_ENABLE: - cntl_params->usPixelClock = - cpu_to_le16((uint16_t)(cntl->pixel_clock / 10)); - cntl_params->ucEncoderMode = - (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom( - cntl->signal, false); - cntl_params->ucLaneNum = (uint8_t)cntl->lanes_number; - break; default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 268e2414b34f0..a93a8860535a1 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -84,6 +84,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCN_VERSION_3_51: case DCN_VERSION_3_6: case DCN_VERSION_4_01: + case DCN_VERSION_4_2: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile index 60021671b386a..98911ef56c2ed 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2017-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -29,18 +29,6 @@ AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR)) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR) - -ifdef CONFIG_DRM_AMD_DC_SI -############################################################################### -# DCE 60 -############################################################################### -CLK_MGR_DCE60 = dce60_clk_mgr.o - -AMD_DAL_CLK_MGR_DCE60 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60)) - -AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE60) -endif - ############################################################################### # DCE 100 and DCE8x ############################################################################### @@ -188,4 +176,13 @@ CLK_MGR_DCN401 = dcn401_clk_mgr.o dcn401_clk_mgr_smu_msg.o AMD_DAL_CLK_MGR_DCN401 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn401/,$(CLK_MGR_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN401) + +############################################################################### +# DCN42 +############################################################################### +CLK_MGR_DCN42 = dcn42_smu.o dcn42_clk_mgr.o + +AMD_DAL_CLK_MGR_DCN42 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn42/,$(CLK_MGR_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 15cf13ec53026..d2e2e8f299671 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -34,7 +34,6 @@ #include "dce110/dce110_clk_mgr.h" #include "dce112/dce112_clk_mgr.h" #include "dce120/dce120_clk_mgr.h" -#include "dce60/dce60_clk_mgr.h" #include "dcn10/rv1_clk_mgr.h" #include "dcn10/rv2_clk_mgr.h" #include "dcn20/dcn20_clk_mgr.h" @@ -49,6 +48,7 @@ #include "dcn32/dcn32_clk_mgr.h" #include "dcn35/dcn35_clk_mgr.h" #include "dcn401/dcn401_clk_mgr.h" +#include "dcn42/dcn42_clk_mgr.h" int clk_mgr_helper_get_active_display_cnt( struct dc *dc, @@ -149,18 +149,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p struct hw_asic_id asic_id = ctx->asic_id; switch (asic_id.chip_family) { -#if defined(CONFIG_DRM_AMD_DC_SI) - case FAMILY_SI: { - struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); - - if (clk_mgr == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - dce60_clk_mgr_construct(ctx, clk_mgr); - return &clk_mgr->base; - } -#endif + case FAMILY_SI: case FAMILY_CI: case FAMILY_KV: { struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); @@ -255,6 +244,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p BREAK_TO_DEBUGGER(); return NULL; } + if (ctx->dce_version == DCN_VERSION_2_01) { + dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base; + } if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev)) { dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; @@ -267,10 +260,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } - if (ctx->dce_version == DCN_VERSION_2_01) { - dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); - return &clk_mgr->base; - } dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); return &clk_mgr->base; } @@ -374,6 +363,18 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p return &clk_mgr->base; } break; + case AMDGPU_FAMILY_GC_11_5_4: { + struct clk_mgr_dcn42 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); + + if (clk_mgr == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dcn42_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); + return &clk_mgr->base.base; + } + break; #endif /* CONFIG_DRM_AMD_DC_FP */ default: ASSERT(0); /* Unknown Asic */ @@ -431,6 +432,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) case AMDGPU_FAMILY_GC_12_0_0: dcn401_clk_mgr_destroy(clk_mgr); break; + case AMDGPU_FAMILY_GC_11_5_4: + dcn42_clk_mgr_destroy(clk_mgr); + break; default: break; diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index 6131ede2db7a2..6d41df52d7c9b 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c @@ -62,6 +62,18 @@ static const struct clk_mgr_mask disp_clk_mask = { CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) }; +/* Max clock values for each state indexed by "enum clocks_state": */ +static const struct state_dependent_clocks dce60_max_clks_by_state[] = { +/* ClocksStateInvalid - should not be used */ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/* ClocksStateLow */ +{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, +/* ClocksStateNominal */ +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, +/* ClocksStatePerformance */ +{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; /* Max clock values for each state indexed by "enum clocks_state": */ static const struct state_dependent_clocks dce80_max_clks_by_state[] = { @@ -126,6 +138,20 @@ int dce_adjust_dp_ref_freq_for_ss(struct clk_mgr_internal *clk_mgr_dce, int dp_r return dp_ref_clk_khz; } +static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_context *ctx = clk_mgr_base->ctx; + int dp_ref_clk_khz = 0; + + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) + dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; + else + dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; + + return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); +} + int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) { struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); @@ -134,6 +160,9 @@ int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) int dp_ref_clk_khz; int target_div; + if (clk_mgr_base->ctx->dce_version <= DCE_VERSION_6_4) + return dce60_get_dp_ref_freq_khz(clk_mgr_base); + /* ASSERT DP Reference Clock source is from DFS*/ REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); ASSERT(dprefclk_src_sel == 0); @@ -441,27 +470,37 @@ void dce_clk_mgr_construct( struct clk_mgr *base = &clk_mgr->base; struct dm_pp_static_clock_info static_clk_info = {0}; - memcpy(clk_mgr->max_clks_by_state, - dce80_max_clks_by_state, - sizeof(dce80_max_clks_by_state)); + if (ctx->dce_version <= DCE_VERSION_6_4) + memcpy(clk_mgr->max_clks_by_state, + dce60_max_clks_by_state, + sizeof(dce60_max_clks_by_state)); + else + memcpy(clk_mgr->max_clks_by_state, + dce80_max_clks_by_state, + sizeof(dce80_max_clks_by_state)); + base->ctx = ctx; base->funcs = &dce_funcs; - clk_mgr->regs = &disp_clk_regs; - clk_mgr->clk_mgr_shift = &disp_clk_shift; - clk_mgr->clk_mgr_mask = &disp_clk_mask; - clk_mgr->dfs_bypass_disp_clk = 0; + if (ctx->dce_version >= DCE_VERSION_8_0) { + clk_mgr->regs = &disp_clk_regs; + clk_mgr->clk_mgr_shift = &disp_clk_shift; + clk_mgr->clk_mgr_mask = &disp_clk_mask; + } + clk_mgr->dfs_bypass_disp_clk = 0; clk_mgr->dprefclk_ss_percentage = 0; clk_mgr->dprefclk_ss_divider = 1000; clk_mgr->ss_on_dprefclk = false; - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) - clk_mgr->max_clks_state = static_clk_info.max_clocks_state; - else - clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; + if (ctx->dce_version >= DCE_VERSION_8_0) { + if (dm_pp_get_static_clocks(ctx, &static_clk_info)) + clk_mgr->max_clks_state = static_clk_info.max_clocks_state; + else + clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; + clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; + } base->clks.max_supported_dispclk_khz = clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; @@ -469,4 +508,3 @@ void dce_clk_mgr_construct( dce_clock_read_integrated_info(clk_mgr); dce_clock_read_ss_info(clk_mgr); } - diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c deleted file mode 100644 index 69dd80d9f7388..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright 2020 Mauro Rossi - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - - -#include "dccg.h" -#include "clk_mgr_internal.h" -#include "dce100/dce_clk_mgr.h" -#include "dce110/dce110_clk_mgr.h" -#include "dce60_clk_mgr.h" -#include "reg_helper.h" -#include "dmcu.h" -#include "core_types.h" -#include "dal_asic_id.h" - -/* - * Currently the register shifts and masks in this file are used for dce60 - * which has no DPREFCLK_CNTL register - * TODO: remove this when DENTIST_DISPCLK_CNTL - * is moved to dccg, where it belongs - */ -#include "dce/dce_6_0_d.h" -#include "dce/dce_6_0_sh_mask.h" - -#define REG(reg) \ - (clk_mgr->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name - -/* set register offset */ -#define SR(reg_name)\ - .reg_name = mm ## reg_name - -static const struct clk_mgr_registers disp_clk_regs = { - CLK_COMMON_REG_LIST_DCE60_BASE() -}; - -static const struct clk_mgr_shift disp_clk_shift = { - CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT) -}; - -static const struct clk_mgr_mask disp_clk_mask = { - CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK) -}; - - -/* Max clock values for each state indexed by "enum clocks_state": */ -static const struct state_dependent_clocks dce60_max_clks_by_state[] = { -/* ClocksStateInvalid - should not be used */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateLow */ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, -/* ClocksStateNominal */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, -/* ClocksStatePerformance */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; - -static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) -{ - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - struct dc_context *ctx = clk_mgr_base->ctx; - int dp_ref_clk_khz = 0; - - if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) - dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency; - else - dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz; - - return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); -} - -static void dce60_pplib_apply_display_requirements( - struct dc *dc, - struct dc_state *context) -{ - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - - dce110_fill_display_configs(context, pp_display_cfg); - - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); -} - -static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, - struct dc_state *context, - bool safe_to_lower) -{ - struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); - struct dm_pp_power_level_change_request level_change_req; - const int max_disp_clk = - clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; - int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz); - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { - patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); - clk_mgr_base->clks.dispclk_khz = patched_disp_clk; - } - dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); -} - - - - - - - - -static struct clk_mgr_funcs dce60_funcs = { - .get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz, - .update_clocks = dce60_update_clocks -}; - -void dce60_clk_mgr_construct( - struct dc_context *ctx, - struct clk_mgr_internal *clk_mgr) -{ - struct clk_mgr *base = &clk_mgr->base; - - dce_clk_mgr_construct(ctx, clk_mgr); - - memcpy(clk_mgr->max_clks_by_state, - dce60_max_clks_by_state, - sizeof(dce60_max_clks_by_state)); - - clk_mgr->regs = &disp_clk_regs; - clk_mgr->clk_mgr_shift = &disp_clk_shift; - clk_mgr->clk_mgr_mask = &disp_clk_mask; - clk_mgr->base.funcs = &dce60_funcs; - - base->clks.max_supported_dispclk_khz = - clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz; -} - diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c index ef77fcd164ed3..f2a716e1e732a 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c @@ -547,6 +547,7 @@ void dcn3_clk_mgr_construct( /* in case we don't get a value from the register, use default */ if (clk_mgr->base.dentist_vco_freq_khz == 0) clk_mgr->base.dentist_vco_freq_khz = 3650000; + /* Convert dprefclk units from MHz to KHz */ /* Value already divided by 10, some resolution lost */ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index db687a13174d5..0cb37827a62b6 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -77,7 +77,6 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, #undef DC_LOGGER #define DC_LOGGER \ clk_mgr->base.base.ctx->logger - #define regCLK1_CLK_PLL_REQ 0x0237 #define regCLK1_CLK_PLL_REQ_BASE_IDX 0 @@ -88,70 +87,8 @@ static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L -#define regCLK1_CLK0_DFS_CNTL 0x0269 -#define regCLK1_CLK0_DFS_CNTL_BASE_IDX 0 -#define regCLK1_CLK1_DFS_CNTL 0x026c -#define regCLK1_CLK1_DFS_CNTL_BASE_IDX 0 -#define regCLK1_CLK2_DFS_CNTL 0x026f -#define regCLK1_CLK2_DFS_CNTL_BASE_IDX 0 -#define regCLK1_CLK3_DFS_CNTL 0x0272 -#define regCLK1_CLK3_DFS_CNTL_BASE_IDX 0 -#define regCLK1_CLK4_DFS_CNTL 0x0275 -#define regCLK1_CLK4_DFS_CNTL_BASE_IDX 0 -#define regCLK1_CLK5_DFS_CNTL 0x0278 -#define regCLK1_CLK5_DFS_CNTL_BASE_IDX 0 - -#define regCLK1_CLK0_CURRENT_CNT 0x02fb -#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK1_CURRENT_CNT 0x02fc -#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK2_CURRENT_CNT 0x02fd -#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK3_CURRENT_CNT 0x02fe -#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK4_CURRENT_CNT 0x02ff -#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK5_CURRENT_CNT 0x0300 -#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX 0 - -#define regCLK1_CLK0_BYPASS_CNTL 0x028a -#define regCLK1_CLK0_BYPASS_CNTL_BASE_IDX 0 -#define regCLK1_CLK1_BYPASS_CNTL 0x0293 -#define regCLK1_CLK1_BYPASS_CNTL_BASE_IDX 0 #define regCLK1_CLK2_BYPASS_CNTL 0x029c #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX 0 -#define regCLK1_CLK3_BYPASS_CNTL 0x02a5 -#define regCLK1_CLK3_BYPASS_CNTL_BASE_IDX 0 -#define regCLK1_CLK4_BYPASS_CNTL 0x02ae -#define regCLK1_CLK4_BYPASS_CNTL_BASE_IDX 0 -#define regCLK1_CLK5_BYPASS_CNTL 0x02b7 -#define regCLK1_CLK5_BYPASS_CNTL_BASE_IDX 0 - -#define regCLK1_CLK0_DS_CNTL 0x0283 -#define regCLK1_CLK0_DS_CNTL_BASE_IDX 0 -#define regCLK1_CLK1_DS_CNTL 0x028c -#define regCLK1_CLK1_DS_CNTL_BASE_IDX 0 -#define regCLK1_CLK2_DS_CNTL 0x0295 -#define regCLK1_CLK2_DS_CNTL_BASE_IDX 0 -#define regCLK1_CLK3_DS_CNTL 0x029e -#define regCLK1_CLK3_DS_CNTL_BASE_IDX 0 -#define regCLK1_CLK4_DS_CNTL 0x02a7 -#define regCLK1_CLK4_DS_CNTL_BASE_IDX 0 -#define regCLK1_CLK5_DS_CNTL 0x02b0 -#define regCLK1_CLK5_DS_CNTL_BASE_IDX 0 - -#define regCLK1_CLK0_ALLOW_DS 0x0284 -#define regCLK1_CLK0_ALLOW_DS_BASE_IDX 0 -#define regCLK1_CLK1_ALLOW_DS 0x028d -#define regCLK1_CLK1_ALLOW_DS_BASE_IDX 0 -#define regCLK1_CLK2_ALLOW_DS 0x0296 -#define regCLK1_CLK2_ALLOW_DS_BASE_IDX 0 -#define regCLK1_CLK3_ALLOW_DS 0x029f -#define regCLK1_CLK3_ALLOW_DS_BASE_IDX 0 -#define regCLK1_CLK4_ALLOW_DS 0x02a8 -#define regCLK1_CLK4_ALLOW_DS_BASE_IDX 0 -#define regCLK1_CLK5_ALLOW_DS 0x02b1 -#define regCLK1_CLK5_ALLOW_DS_BASE_IDX 0 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT 0x10 @@ -248,8 +185,6 @@ void dcn314_init_clocks(struct clk_mgr *clk_mgr) { struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; - struct clk_mgr_dcn314 *clk_mgr_dcn314 = TO_CLK_MGR_DCN314(clk_mgr_int); - struct clk_log_info log_info = {0}; memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); // Assumption is that boot state always supports pstate @@ -265,9 +200,6 @@ void dcn314_init_clocks(struct clk_mgr *clk_mgr) dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz); else clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz; - - dcn314_dump_clk_registers(&clk_mgr->boot_snapshot, &clk_mgr_dcn314->base.base, &log_info); - clk_mgr->clks.dispclk_khz = clk_mgr->boot_snapshot.dispclk * 1000; } void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, @@ -278,7 +210,7 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; struct dc *dc = clk_mgr_base->ctx->dc; - int display_count; + int display_count = 0; bool update_dppclk = false; bool update_dispclk = false; bool dpp_clock_lowered = false; @@ -287,7 +219,6 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, return; display_count = dcn314_get_active_display_cnt_wa(dc, context); - /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything * also if safe to lower is false, we just go in the higher state @@ -363,7 +294,7 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && - (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { + (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) { int requested_dispclk_khz = new_clocks->dispclk_khz; dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); @@ -374,7 +305,6 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, dcn314_smu_set_dispclk(clk_mgr, requested_dispclk_khz); clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; - dcn314_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); update_dispclk = true; @@ -462,65 +392,10 @@ bool dcn314_are_clock_states_equal(struct dc_clocks *a, return true; } - -static void dcn314_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base) -{ - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - - // read dtbclk - internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); - internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL); - - // read dcfclk - internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); - internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); - - // read dcf deep sleep divider - internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); - internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); - - // read dppclk - internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); - internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); - - // read dprefclk - internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); - internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); - - // read dispclk - internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); - internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL); -} - -void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, +static void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) { - - struct dcn35_clk_internal internal = {0}; - - dcn314_dump_clk_registers_internal(&internal, clk_mgr_base); - - regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; - regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10; - regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS; - regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; - regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; - regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; - regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; - - regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dppclk_bypass > 4) - regs_and_bypass->dppclk_bypass = 0; - regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dcfclk_bypass > 4) - regs_and_bypass->dcfclk_bypass = 0; - regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dispclk_bypass > 4) - regs_and_bypass->dispclk_bypass = 0; - regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007; - if (regs_and_bypass->dprefclk_bypass > 4) - regs_and_bypass->dprefclk_bypass = 0; - + return; } static struct clk_bw_params dcn314_bw_params = { diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h index 0577eb527bc36..002c28e807208 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.h @@ -65,9 +65,4 @@ void dcn314_clk_mgr_construct(struct dc_context *ctx, void dcn314_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); - -void dcn314_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, - struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info); - - #endif //__DCN314_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c index 3a881451e9da4..c49268db85f68 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c @@ -40,7 +40,7 @@ #include "dm_helpers.h" #include "dc_dmub_srv.h" -#include "reg_helper.h" + #include "logger_types.h" #undef DC_LOGGER #define DC_LOGGER \ @@ -48,43 +48,9 @@ #include "link_service.h" -#define MAX_INSTANCE 7 -#define MAX_SEGMENT 8 - -struct IP_BASE_INSTANCE { - unsigned int segment[MAX_SEGMENT]; -}; - -struct IP_BASE { - struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; -}; - -static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, - { { 0x00016E00, 0x02401C00, 0, 0, 0, 0, 0, 0 } }, - { { 0x00017000, 0x02402000, 0, 0, 0, 0, 0, 0 } }, - { { 0x00017200, 0x02402400, 0, 0, 0, 0, 0, 0 } }, - { { 0x0001B000, 0x0242D800, 0, 0, 0, 0, 0, 0 } }, - { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0, 0, 0 } } } }; - -#define regCLK1_CLK0_CURRENT_CNT 0x0314 -#define regCLK1_CLK0_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK1_CURRENT_CNT 0x0315 -#define regCLK1_CLK1_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK2_CURRENT_CNT 0x0316 -#define regCLK1_CLK2_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK3_CURRENT_CNT 0x0317 -#define regCLK1_CLK3_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK4_CURRENT_CNT 0x0318 -#define regCLK1_CLK4_CURRENT_CNT_BASE_IDX 0 -#define regCLK1_CLK5_CURRENT_CNT 0x0319 -#define regCLK1_CLK5_CURRENT_CNT_BASE_IDX 0 - #define TO_CLK_MGR_DCN315(clk_mgr)\ container_of(clk_mgr, struct clk_mgr_dcn315, base) -#define REG(reg_name) \ - (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) - #define UNSUPPORTED_DCFCLK 10000000 #define MIN_DPP_DISP_CLK 100000 @@ -172,7 +138,7 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, if (dc->work_arounds.skip_clock_update) return; - clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; + display_count = dcn315_get_active_display_cnt_wa(dc, context); /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything * also if safe to lower is false, we just go in the higher state @@ -185,7 +151,6 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, } /* check that we're not already in lower */ if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { - display_count = dcn315_get_active_display_cnt_wa(dc, context); /* if we can go lower, go lower */ if (display_count == 0) { union display_idle_optimization_u idle_info = { 0 }; @@ -279,38 +244,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); } -static void dcn315_dump_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base) -{ - struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); - - // read dtbclk - internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT); - - // read dcfclk - internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); - - // read dppclk - internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); - - // read dprefclk - internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); - - // read dispclk - internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); -} - static void dcn315_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info) { - struct dcn35_clk_internal internal = {0}; - - dcn315_dump_clk_registers_internal(&internal, clk_mgr_base); - - regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10; - regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10; - regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10; - regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; - regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10; return; } @@ -657,32 +593,13 @@ static struct clk_mgr_funcs dcn315_funcs = { .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, .update_clocks = dcn315_update_clocks, - .init_clocks = dcn315_init_clocks, + .init_clocks = dcn31_init_clocks, .enable_pme_wa = dcn315_enable_pme_wa, .are_clock_states_equal = dcn31_are_clock_states_equal, .notify_wm_ranges = dcn315_notify_wm_ranges }; extern struct clk_mgr_funcs dcn3_fpga_funcs; -void dcn315_init_clocks(struct clk_mgr *clk_mgr) -{ - struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); - uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; - struct clk_mgr_dcn315 *clk_mgr_dcn315 = TO_CLK_MGR_DCN315(clk_mgr_int); - struct clk_log_info log_info = {0}; - - memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); - // Assumption is that boot state always supports pstate - clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk - clk_mgr->clks.p_state_change_support = true; - clk_mgr->clks.prev_p_state_change_support = true; - clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; - clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; - - dcn315_dump_clk_registers(&clk_mgr->boot_snapshot, &clk_mgr_dcn315->base.base, &log_info); - clk_mgr->clks.dispclk_khz = clk_mgr->boot_snapshot.dispclk * 1000; -} - void dcn315_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_dcn315 *clk_mgr, @@ -743,7 +660,6 @@ void dcn315_clk_mgr_construct( /* Saved clocks configured at boot for debug purposes */ dcn315_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info); - clk_mgr->base.base.clks.dispclk_khz = clk_mgr->base.base.boot_snapshot.dispclk * 1000; clk_mgr->base.base.dprefclk_khz = 600000; clk_mgr->base.base.dprefclk_khz = dcn315_smu_get_dpref_clk(&clk_mgr->base); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h index 642ae3d4a7909..ac36ddf5dd1af 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h @@ -44,7 +44,6 @@ void dcn315_clk_mgr_construct(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg); -void dcn315_init_clocks(struct clk_mgr *clk_mgr); void dcn315_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); #endif //__DCN315_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index dfd0c9505af09..6fc5247526132 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -186,7 +186,7 @@ static int dcn35_get_active_display_cnt_wa( return display_count; } -static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, +void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool safe_to_lower, bool disable) { struct dc *dc = clk_mgr_base->ctx->dc; @@ -405,7 +405,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); - dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; } @@ -425,7 +424,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); - dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false); clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; } @@ -768,32 +766,32 @@ static struct wm_table ddr5_wm_table = { .wm_inst = WM_A, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, { .wm_inst = WM_B, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, { .wm_inst = WM_C, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, { .wm_inst = WM_D, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.72, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .valid = true, }, } diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h index a12a9bf90806e..83e2263563fe0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.h @@ -64,4 +64,10 @@ void dcn351_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_dcn35 *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg); + +void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower, + bool disable); + #endif //__DCN35_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c index 604d256cb47a6..9d8f81c3d3f05 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c @@ -204,7 +204,7 @@ int dcn35_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispcl khz_to_mhz_ceil(requested_dispclk_khz)); smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", requested_dispclk_khz, actual_dispclk_set_mhz); - return actual_dispclk_set_mhz * 1000; + return (int)((long long)actual_dispclk_set_mhz * 1000); } int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) @@ -221,7 +221,7 @@ int dcn35_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) /* TODO: add code for programing DP DTO, currently this is down by command table */ - return actual_dprefclk_set_mhz * 1000; + return (int)((long long)actual_dprefclk_set_mhz * 1000); } int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) @@ -238,7 +238,7 @@ int dcn35_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requeste smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", requested_dcfclk_khz, actual_dcfclk_set_mhz); - return actual_dcfclk_set_mhz * 1000; + return (int)((long long)actual_dcfclk_set_mhz * 1000); } int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) @@ -255,7 +255,7 @@ int dcn35_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int re smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz); - return actual_min_ds_dcfclk_mhz * 1000; + return (int)((long long)actual_min_ds_dcfclk_mhz * 1000); } int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) @@ -272,7 +272,7 @@ int dcn35_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", requested_dpp_khz, actual_dppclk_set_mhz); - return actual_dppclk_set_mhz * 1000; + return (int)((long long)actual_dppclk_set_mhz * 1000); } void dcn35_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) @@ -424,7 +424,7 @@ int dcn35_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) 0); smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk); - return dprefclk * 1000; + return (int)((long long)dprefclk * 1000); } int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) @@ -439,7 +439,7 @@ int dcn35_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) 0); smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); - return dtbclk * 1000; + return (int)((long long)dtbclk * 1000); } /* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ void dcn35_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c new file mode 100644 index 0000000000000..b4c6522e922c5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c @@ -0,0 +1,1176 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn42_clk_mgr.h" + +#include "dccg.h" +#include "clk_mgr_internal.h" + +// For dce12_get_dp_ref_freq_khz +#include "dce100/dce_clk_mgr.h" + +// For dcn20_update_clocks_update_dpp_dto +#include "dcn20/dcn20_clk_mgr.h" + + + + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn42_smu.h" +#include "dm_helpers.h" + +/* TODO: remove this include once we ported over remaining clk mgr functions*/ +#include "dcn30/dcn30_clk_mgr.h" +#include "dcn31/dcn31_clk_mgr.h" + +#include "dcn35/dcn35_clk_mgr.h" + +#include "dc_dmub_srv.h" +#include "link_service.h" +#include "logger_types.h" + +#include "clk/clk_15_0_0_offset.h" +#include "clk/clk_15_0_0_sh_mask.h" +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" + + +#undef DC_LOGGER +#define DC_LOGGER \ + dc_logger +#define DC_LOGGER_INIT(logger) \ + struct dal_logger *dc_logger = logger + +#define DCN42_CLKIP_REFCLK 48000 + +#undef FN +#define FN(reg_name, field_name) \ + clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name + +#define REG(reg) \ + (clk_mgr->regs->reg) + +// for DCN register access +#define DCN_BASE__INST0_SEG0 0x00000012 +#define DCN_BASE__INST0_SEG1 0x000000C0 + +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name) \ + .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name + +// for CLKIP register access +#define CLK_BASE__INST0_SEG0 0x00016C00 + +#define CLK_BASE_INNER(seg) \ + CLK_BASE__INST0_SEG ## seg + +#define CLK_SR_DCN42(reg_name) \ + .reg_name = CLK_BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name + +static const struct clk_mgr_registers clk_mgr_regs_dcn42 = { + CLK_REG_LIST_DCN42() +}; + +static const struct clk_mgr_shift clk_mgr_shift_dcn42 = { + CLK_COMMON_MASK_SH_LIST_DCN42(__SHIFT) +}; + +static const struct clk_mgr_mask clk_mgr_mask_dcn42 = { + CLK_COMMON_MASK_SH_LIST_DCN42(_MASK) +}; + +#define TO_CLK_MGR_DCN42(clk_mgr_int)\ + container_of(clk_mgr_int, struct clk_mgr_dcn42, base) + +bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context) +{ + int i, active_count = 0; + + for (i = 0; i < context->stream_count; i++) { + const struct dc_stream_state *stream = context->streams[i]; + + /* Checking stream / link detection ensuring that PHY is active*/ + if (dc_is_hdmi_signal(stream->signal) || + dc_is_dvi_signal(stream->signal) || + (dc_is_dp_signal(stream->signal) && !stream->dpms_off)) + active_count++; + } + + for (i = 0; i < dc->link_count; i++) { + const struct dc_link *link = dc->links[i]; + + /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */ + if (link->link_enc && link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) + active_count++; + } + + return active_count > 0; +} + +static uint32_t dcn42_get_clock_freq_from_clkip(struct clk_mgr *clk_mgr_base, enum clock_type clock) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + uint64_t clock_freq_mhz = 0; + uint32_t timer_threshold = 0; + + // always safer to read the timer threshold instead of using cached value + REG_GET(CLK8_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, &timer_threshold); + + if (timer_threshold == 0) { + BREAK_TO_DEBUGGER(); + return 0; + } + + switch (clock) { + case clock_type_dispclk: + clock_freq_mhz = REG_READ(CLK8_CLK0_CURRENT_CNT); + break; + case clock_type_dppclk: + clock_freq_mhz = REG_READ(CLK8_CLK1_CURRENT_CNT); + break; + case clock_type_dprefclk: + clock_freq_mhz = REG_READ(CLK8_CLK2_CURRENT_CNT); + break; + case clock_type_dcfclk: + clock_freq_mhz = REG_READ(CLK8_CLK3_CURRENT_CNT); + break; + case clock_type_dtbclk: + clock_freq_mhz = REG_READ(CLK8_CLK4_CURRENT_CNT); + break; + default: + break; + } + + clock_freq_mhz *= DCN42_CLKIP_REFCLK; + clock_freq_mhz = div_u64(clock_freq_mhz, timer_threshold); + + // there are no DCN clocks over 0xFFFFFFFF MHz + ASSERT(clock_freq_mhz <= 0xFFFFFFFF); + + return (uint32_t)clock_freq_mhz; +} + +void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, + struct dc_state *context, + int ref_dtbclk_khz) +{ + /* DCN42 does not implement set_dtbclk_dto function, so this is a no-op */ +} + +void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, + struct dc_state *context, bool safe_to_lower) +{ + int i; + bool dppclk_active[MAX_PIPES] = {0}; + + + clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; + + dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; + + if (context->res_ctx.pipe_ctx[i].plane_res.dpp) + dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst; + else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { + /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting. + * In this case just continue in loop + */ + continue; + } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) { + /* The software state is not valid if dpp resource is NULL and + * dppclk_khz > 0. + */ + ASSERT(false); + continue; + } + + prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; + + if (safe_to_lower || prev_dppclk_khz < dppclk_khz) + clk_mgr->dccg->funcs->update_dpp_dto( + clk_mgr->dccg, dpp_inst, dppclk_khz); + dppclk_active[dpp_inst] = true; + } + if (safe_to_lower) + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { + struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp; + + if (old_dpp && !dppclk_active[old_dpp->inst]) + clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0); + } +} + +void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower) +{ + union dmub_rb_cmd cmd; + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + struct dc *dc = clk_mgr_base->ctx->dc; + bool update_dppclk = false; + bool update_dispclk = false; + bool dpp_clock_lowered = false; + bool has_active_display; + + if (dc->work_arounds.skip_clock_update) + return; + + has_active_display = dcn42_has_active_display(dc, context); + + if (new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz < 590000) + new_clocks->ref_dtbclk_khz = 600000; + /* + * if it is safe to lower, but we are already in the lower state, we don't have to do anything + * also if safe to lower is false, we just go in the higher state + */ + if (safe_to_lower) { + if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && + new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { + dcn42_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); + clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; + } + + if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { + if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk) + dcn42_smu_set_dtbclk(clk_mgr, false); + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } + /* check that we're not already in lower */ + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { + /* if we can go lower, go lower */ + if (has_active_display == false) + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; + } + } else { + if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && + new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { + dcn42_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); + clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; + } + if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { + int actual_dtbclk = 0; + + dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); + dcn42_smu_set_dtbclk(clk_mgr, true); + actual_dtbclk = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk); + + if (actual_dtbclk > 590000) { + clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; + clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; + } + } + + /* check that we're not already in D0 */ + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { + union display_idle_optimization_u idle_info = { 0 }; + + dcn42_smu_set_display_idle_optimization(clk_mgr, idle_info.data); + /* update power state */ + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; + } + } + if (dc->debug.force_min_dcfclk_mhz > 0) + new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? + new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { + clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; + clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; + clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; + dcn42_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); + } + + if (should_set_clock(safe_to_lower, + new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { + clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + + /* Clamp the requested clock to PMFW based on DCN limit. */ + if (dc->debug.min_deep_sleep_dcfclk_khz > 0 && clk_mgr_base->clks.dcfclk_deep_sleep_khz < dc->debug.min_deep_sleep_dcfclk_khz) + clk_mgr_base->clks.dcfclk_deep_sleep_khz = dc->debug.min_deep_sleep_dcfclk_khz; + + dcn42_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); + } + + // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { + if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) + dpp_clock_lowered = true; + clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; + update_dppclk = true; + } + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) && + (new_clocks->dispclk_khz > 0 || (safe_to_lower && has_active_display == false))) { + int requested_dispclk_khz = new_clocks->dispclk_khz; + + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); + + /* Clamp the requested clock to PMFW based on their limit. */ + if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz) + requested_dispclk_khz = dc->debug.min_disp_clk_khz; + + dcn42_smu_set_dispclk(clk_mgr, requested_dispclk_khz); + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; + dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); + + update_dispclk = true; + } + + /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */ + if (!dc->debug.disable_dtb_ref_clk_switch && + should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, + clk_mgr_base->clks.ref_dtbclk_khz / 1000)) { + dcn42_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz); + clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz; + } + + if (dpp_clock_lowered) { + // increase per DPP DTO before lowering global dppclk + dcn42_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); + dcn42_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + } else { + // increase global DPPCLK before lowering per DPP DTO + if (update_dppclk || update_dispclk) + dcn42_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); + dcn42_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower); + } + // notify DMCUB of latest clocks + memset(&cmd, 0, sizeof(cmd)); + cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR; + cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS; + cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz; + cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz = + clk_mgr_base->clks.dcfclk_deep_sleep_khz; + cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; + cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); +} + + +void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + dcn42_smu_enable_pme_wa(clk_mgr); +} + + +bool dcn42_are_clock_states_equal(struct dc_clocks *a, + struct dc_clocks *b) +{ + if (a->dispclk_khz != b->dispclk_khz) + return false; + else if (a->dppclk_khz != b->dppclk_khz) + return false; + else if (a->dcfclk_khz != b->dcfclk_khz) + return false; + else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz) + return false; + else if (a->zstate_support != b->zstate_support) + return false; + else if (a->dtbclk_en != b->dtbclk_en) + return false; + + return true; +} + +static void dcn42_dump_clk_registers_internal(struct dcn42_clk_internal *internal, struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + REG_GET(CLK8_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, &internal->CLK8_CLK_TICK_CNT__TIMER_THRESHOLD); + + // read dcf deep sleep divider + internal->CLK8_CLK0_DS_CNTL = REG_READ(CLK8_CLK0_DS_CNTL); + internal->CLK8_CLK3_DS_CNTL = REG_READ(CLK8_CLK3_DS_CNTL); + // read dispclk + internal->CLK8_CLK0_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dispclk); + internal->CLK8_CLK0_BYPASS_CNTL = REG_READ(CLK8_CLK0_BYPASS_CNTL); + // read dppclk + internal->CLK8_CLK1_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dppclk); + internal->CLK8_CLK1_BYPASS_CNTL = REG_READ(CLK8_CLK1_BYPASS_CNTL); + // read dprefclk + internal->CLK8_CLK2_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dprefclk); + internal->CLK8_CLK2_BYPASS_CNTL = REG_READ(CLK8_CLK2_BYPASS_CNTL); + // read dcfclk + internal->CLK8_CLK3_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dcfclk); + internal->CLK8_CLK3_BYPASS_CNTL = REG_READ(CLK8_CLK3_BYPASS_CNTL); + // read dtbclk + internal->CLK8_CLK4_CURRENT_CNT = dcn42_get_clock_freq_from_clkip(clk_mgr_base, clock_type_dtbclk); + internal->CLK8_CLK4_BYPASS_CNTL = REG_READ(CLK8_CLK4_BYPASS_CNTL); +} + +static void dcn42_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass, + struct clk_mgr_dcn42 *clk_mgr) +{ + struct dcn42_clk_internal internal = {0}; + char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"}; + + DC_LOGGER_INIT(clk_mgr->base.base.ctx->logger); + (void)dc_logger; + + dcn42_dump_clk_registers_internal(&internal, &clk_mgr->base.base); + regs_and_bypass->timer_threshold = internal.CLK8_CLK_TICK_CNT__TIMER_THRESHOLD; + regs_and_bypass->dcfclk = internal.CLK8_CLK3_CURRENT_CNT / 10; + regs_and_bypass->dcf_deep_sleep_divider = internal.CLK8_CLK3_DS_CNTL / 10; + regs_and_bypass->dcf_deep_sleep_allow = internal.CLK8_CLK3_DS_CNTL & 0x10; /*bit 4: CLK0_ALLOW_DS*/ + regs_and_bypass->dprefclk = internal.CLK8_CLK2_CURRENT_CNT / 10; + regs_and_bypass->dispclk = internal.CLK8_CLK0_CURRENT_CNT / 10; + regs_and_bypass->dppclk = internal.CLK8_CLK1_CURRENT_CNT / 10; + regs_and_bypass->dtbclk = internal.CLK8_CLK4_CURRENT_CNT / 10; + + regs_and_bypass->dispclk_bypass = get_reg_field_value(internal.CLK8_CLK0_BYPASS_CNTL, CLK8_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL); + regs_and_bypass->dppclk_bypass = get_reg_field_value(internal.CLK8_CLK1_BYPASS_CNTL, CLK8_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL); + regs_and_bypass->dprefclk_bypass = get_reg_field_value(internal.CLK8_CLK2_BYPASS_CNTL, CLK8_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL); + regs_and_bypass->dcfclk_bypass = get_reg_field_value(internal.CLK8_CLK3_BYPASS_CNTL, CLK8_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL); + + if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) { + DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n"); + + DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n", + regs_and_bypass->dcfclk, + regs_and_bypass->dcf_deep_sleep_divider, + regs_and_bypass->dcf_deep_sleep_allow, + bypass_clks[(int) regs_and_bypass->dcfclk_bypass]); + + DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n", + regs_and_bypass->dprefclk, + bypass_clks[(int) regs_and_bypass->dprefclk_bypass]); + + DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n", + regs_and_bypass->dispclk, + bypass_clks[(int) regs_and_bypass->dispclk_bypass]); + + //split + DC_LOG_SMU("SPLIT\n"); + + // REGISTER VALUES + DC_LOG_SMU("reg_name,value,clk_type\n"); + DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n", + internal.CLK8_CLK3_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n", + internal.CLK8_CLK3_DS_CNTL); + + DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n", + (internal.CLK8_CLK3_DS_CNTL & 0x10)); + + DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n", + internal.CLK8_CLK2_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk\n", + internal.CLK8_CLK0_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", + internal.CLK8_CLK1_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk\n", + internal.CLK8_CLK4_CURRENT_CNT); + + DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n", + internal.CLK8_CLK3_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n", + internal.CLK8_CLK2_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n", + internal.CLK8_CLK0_BYPASS_CNTL); + + DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n", + internal.CLK8_CLK1_BYPASS_CNTL); + } +} + +bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dc_context *ctx = clk_mgr->base.ctx; + + + if (ctx->dc->config.ignore_dpref_ss) { + /*revert bios's ss info for test only*/ + return (clk_mgr->dprefclk_ss_percentage == 0); + } + /*need to update after BU*/ + return false; +} + +static void init_clk_states(struct clk_mgr *clk_mgr) +{ + uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz; + + memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); + + clk_mgr->clks.dtbclk_en = true; // request DTBCLK disable on first commit + clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk + clk_mgr->clks.p_state_change_support = true; + clk_mgr->clks.prev_p_state_change_support = true; + clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; + clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN; +} + +static void dcn42_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr, + struct dcn42_smu_dpm_clks *smu_dpm_clks) +{ + DpmClocks_t_dcn42 *table = smu_dpm_clks->dpm_clks; + + if (!clk_mgr->smu_ver) + return; + + if (!table || smu_dpm_clks->mc_address.quad_part == 0) + return; + + memset(table, 0, sizeof(*table)); + + dcn42_smu_set_dram_addr_high(clk_mgr, + smu_dpm_clks->mc_address.high_part); + dcn42_smu_set_dram_addr_low(clk_mgr, + smu_dpm_clks->mc_address.low_part); + dcn42_smu_transfer_dpm_table_smu_2_dram(clk_mgr); +} + +void dcn42_init_single_clock(unsigned int *entry_0, + uint32_t *smu_entry_0, + uint8_t num_levels) +{ + int i; + char *entry_i = (char *)entry_0; + + ASSERT(num_levels <= MAX_NUM_DPM_LVL); + if (num_levels > MAX_NUM_DPM_LVL) + num_levels = MAX_NUM_DPM_LVL; + + + for (i = 0; i < num_levels; i++) { + *((unsigned int *)entry_i) = smu_entry_0[i]; + entry_i += sizeof(struct clk_limit_table_entry); + } +} + +unsigned int dcn42_convert_wck_ratio(uint8_t wck_ratio) +{ + switch (wck_ratio) { + case WCK_RATIO_1_2: + return 2; + + case WCK_RATIO_1_4: + return 4; + + default: + break; + } + + return 1; +} + +void dcn42_init_clocks(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); + + DC_LOGGER_INIT(clk_mgr_base->ctx->logger); + (void)dc_logger; + + init_clk_states(clk_mgr_base); + + // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk + if (dcn42_is_spll_ssc_enabled(clk_mgr_base)) + clk_mgr_base->dp_dto_source_clock_in_khz = + dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr_base->dprefclk_khz); + else + clk_mgr_base->dp_dto_source_clock_in_khz = clk_mgr_base->dprefclk_khz; + + DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz); + dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr); + + clk_mgr_base->clks.ref_dtbclk_khz = clk_mgr_base->boot_snapshot.dtbclk * 10; + clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000; +} + +static struct clk_bw_params dcn42_bw_params = { + .vram_type = Ddr4MemType, + .num_channels = 1, + .clk_table = { + .num_entries = 4, + }, + +}; + +static struct wm_table ddr5_wm_table = { + .entries = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.72, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + } +}; + +static struct wm_table lpddr5_wm_table = { + .entries = { + { + .wm_inst = WM_A, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_B, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_C, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + { + .wm_inst = WM_D, + .wm_type = WM_TYPE_PSTATE_CHG, + .pstate_latency_us = 11.65333, + .sr_exit_time_us = 28.0, + .sr_enter_plus_exit_time_us = 30.0, + .valid = true, + }, + } +}; + +struct dcn42_ss_info_table dcn42_ss_info_table = { + .ss_divider = 1000, + .ss_percentage = {0, 0, 375, 375, 375} +}; + +static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr) +{ + uint32_t clock_source; + + clock_source = (REG_READ(CLK8_CLK2_BYPASS_CNTL) & CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK); + // If it's DFS mode, clock_source is 0. + if (dcn42_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(dcn42_ss_info_table.ss_percentage))) { + clk_mgr->dprefclk_ss_percentage = dcn42_ss_info_table.ss_percentage[clock_source]; + + if (clk_mgr->dprefclk_ss_percentage != 0) { + clk_mgr->ss_on_dprefclk = true; + clk_mgr->dprefclk_ss_divider = dcn42_ss_info_table.ss_divider; + } + } +} + +void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table) +{ + int i, num_valid_sets; + + num_valid_sets = 0; + + for (i = 0; i < WM_SET_COUNT; i++) { + /* skip empty entries, the smu array has no holes*/ + if (!bw_params->wm_table.entries[i].valid) + continue; + + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; + /* We will not select WM based on fclk, so leave it as unconstrained */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; + + if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) { + if (i == 0) + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0; + else { + /* add 1 to make it non-overlapping with next lvl */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = + bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; + } + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk = + bw_params->clk_table.entries[i].dcfclk_mhz; + + } else { + /* unconstrained for memory retraining */ + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; + + /* Modify previous watermark range to cover up to max */ + if (num_valid_sets > 0) + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + } + num_valid_sets++; + } + + ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */ + + /* modify the min and max to make sure we cover the whole range*/ + table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0; + table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF; + table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; + + /* This is for writeback only, does not matter currently as no writeback support*/ + table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A; + table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; + table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; + table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0; + table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF; +} + +void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base) +{ + int i = 0; + struct dcn42_watermarks *table = NULL; + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct clk_mgr_dcn42 *clk_mgr_dcn42 = TO_CLK_MGR_DCN42(clk_mgr); + + if (!clk_mgr->smu_ver) + return; + /*send once already skip*/ + if (clk_mgr_base->bw_params->wm_table.entries[WM_A].valid == true) + return; + clk_mgr_dcn42->smu_wm_set.wm_set = (struct dcn42_watermarks *)dm_helpers_allocate_gpu_mem( + clk_mgr->base.ctx, + DC_MEM_ALLOC_TYPE_GART, + sizeof(struct dcn42_watermarks), + &clk_mgr_dcn42->smu_wm_set.mc_address.quad_part); + + ASSERT(clk_mgr_dcn42->smu_wm_set.wm_set); + + table = clk_mgr_dcn42->smu_wm_set.wm_set; + + if (!table || clk_mgr_dcn42->smu_wm_set.mc_address.quad_part == 0) + return; + + memset(table, 0, sizeof(*table)); + /*same as previous asic, set wm valid before building watermark ranges*/ + for (i = 0; i < WM_SET_COUNT; i++) { + clk_mgr_base->bw_params->wm_table.entries[i].wm_inst = i; + + if (i >= clk_mgr_base->bw_params->clk_table.num_entries) { + clk_mgr_base->bw_params->wm_table.entries[i].valid = false; + continue; + } + clk_mgr_base->bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; + clk_mgr_base->bw_params->wm_table.entries[i].valid = true; + } + /* build watermark_range will check this valid range*/ + dcn42_build_watermark_ranges(clk_mgr_base->bw_params, table); + + dcn42_smu_set_dram_addr_high(clk_mgr, + clk_mgr_dcn42->smu_wm_set.mc_address.high_part); + dcn42_smu_set_dram_addr_low(clk_mgr, + clk_mgr_dcn42->smu_wm_set.mc_address.low_part); + dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr); + + if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART, + clk_mgr_dcn42->smu_wm_set.wm_set); + +} + +void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base) +{ + struct dc *dc = clk_mgr_base->ctx->dc; + struct dc_state *context = dc->current_state; + + if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { + /* if we can go lower, go lower */ + if (dcn42_has_active_display(dc, context) == false) + clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; + } + + if (clk_mgr_base->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) { + union display_idle_optimization_u idle_info = { 0 }; + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + idle_info.idle_info.df_request_disabled = 1; + idle_info.idle_info.phy_ref_clk_off = 1; + idle_info.idle_info.s0i2_rdy = 1; + dcn42_smu_set_display_idle_optimization(clk_mgr, idle_info.data); + } +} + +void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base) +{ + +} + +static void dcn42_init_clocks_fpga(struct clk_mgr *clk_mgr) +{ + init_clk_states(clk_mgr); + +} + +static void dcn42_update_clocks_fpga(struct clk_mgr *clk_mgr, + struct dc_state *context, + bool safe_to_lower) +{ + struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr); + struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; + int fclk_adj = new_clocks->fclk_khz; + + /* TODO: remove this after correctly set by DML */ + new_clocks->dcfclk_khz = 400000; + new_clocks->socclk_khz = 400000; + + /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */ + //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; + new_clocks->fclk_khz = 4320000; + + if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) + clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; + + if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) + clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz; + + if (should_set_clock(safe_to_lower, + new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) + clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; + + if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) + clk_mgr->clks.socclk_khz = new_clocks->socclk_khz; + + if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) + clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz; + + if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) + clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz; + + if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) + clk_mgr->clks.fclk_khz = fclk_adj; + + if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) + clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; + + /* Both fclk and ref_dppclk run on the same scemi clock. + * So take the higher value since the DPP DTO is typically programmed + * such that max dppclk is 1:1 with ref_dppclk. + */ + if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) + clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; + if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) + clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; + + // Both fclk and ref_dppclk run on the same scemi clock. + clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; + + /* TODO: set dtbclk in correct place */ + clk_mgr->clks.dtbclk_en = true; + + dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); + dcn42_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower); + + dcn42_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz); +} + +unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + + unsigned int num_clk_levels; + + switch (clk_type) { + case CLK_TYPE_DISPCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 : + clk_mgr->base.boot_snapshot.dispclk; + case CLK_TYPE_DPPCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 : + clk_mgr->base.boot_snapshot.dppclk; + case CLK_TYPE_DSCCLK: + num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels; + return num_clk_levels ? + clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 : + clk_mgr->base.boot_snapshot.dispclk / 3; + default: + break; + } + + return 0; +} + +static int dcn42_get_dispclk_from_dentist(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + uint32_t dispclk_wdivider; + int disp_divider; + + REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); + disp_divider = dentist_get_divider_from_did(dispclk_wdivider); + + /* Return DISPCLK freq in Khz */ + if (disp_divider) + return (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / disp_divider; + + return 0; +} +bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base) +{ + struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); + return clk_mgr->smu_present; +} + +static void dcn42_get_smu_clocks(struct clk_mgr_internal *clk_mgr_int) +{ + struct clk_mgr *clk_mgr_base = &clk_mgr_int->base; + struct dcn42_smu_dpm_clks smu_dpm_clks = { 0 }; + + DC_LOGGER_INIT(clk_mgr_base->ctx->logger); + (void)dc_logger; + + smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn42 *)dm_helpers_allocate_gpu_mem( + clk_mgr_base->ctx, + DC_MEM_ALLOC_TYPE_GART, + sizeof(DpmClocks_t_dcn42), + &smu_dpm_clks.mc_address.quad_part); + + ASSERT(smu_dpm_clks.dpm_clks); + if (clk_mgr_base->ctx->dc->debug.pstate_enabled && smu_dpm_clks.mc_address.quad_part != 0) { + int i; + DpmClocks_t_dcn42 *dpm_clks = smu_dpm_clks.dpm_clks; + + dcn42_get_dpm_table_from_smu(clk_mgr_int, &smu_dpm_clks); + DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n" + "NumDispClkLevelsEnabled: %d\n" + "NumSocClkLevelsEnabled: %d\n" + "VcnClkLevelsEnabled: %d\n" + "FClkLevelsEnabled: %d\n" + "NumMemPstatesEnabled: %d\n" + "MinGfxClk: %d\n" + "MaxGfxClk: %d\n", + dpm_clks->NumDcfClkLevelsEnabled, + dpm_clks->NumDispClkLevelsEnabled, + dpm_clks->NumSocClkLevelsEnabled, + dpm_clks->VcnClkLevelsEnabled, + dpm_clks->NumFclkLevelsEnabled, + dpm_clks->NumMemPstatesEnabled, + dpm_clks->MinGfxClk, + dpm_clks->MaxGfxClk); + + for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->DcfClocks[%d] = %d\n", + i, + dpm_clks->DcfClocks[i]); + } + for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->DispClocks[%d] = %d\n", + i, dpm_clks->DispClocks[i]); + } + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->SocClocks[%d] = %d\n", + i, dpm_clks->SocClocks[i]); + } + for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) { + DC_LOG_SMU("dpm_clks->FclkClocks_Freq[%d] = %d\n", + i, dpm_clks->FclkClocks_Freq[i]); + DC_LOG_SMU("dpm_clks->FclkClocks_Voltage[%d] = %d\n", + i, dpm_clks->FclkClocks_Voltage[i]); + } + for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) + DC_LOG_SMU("dpm_clks->SocVoltage[%d] = %d\n", + i, dpm_clks->SocVoltage[i]); + + for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) { + DC_LOG_SMU("dpm_clks.MemPstateTable[%d].UClk = %d\n" + "dpm_clks->MemPstateTable[%d].MemClk= %d\n" + "dpm_clks->MemPstateTable[%d].Voltage = %d\n", + i, dpm_clks->MemPstateTable[i].UClk, + i, dpm_clks->MemPstateTable[i].MemClk, + i, dpm_clks->MemPstateTable[i].Voltage); + } + + if (clk_mgr_base->ctx->dc_bios->integrated_info && clk_mgr_base->ctx->dc->config.use_default_clock_table == false) { + /* DCFCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, + dpm_clks->DcfClocks, + dpm_clks->NumDcfClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = dpm_clks->NumDcfClkLevelsEnabled; + + /* SOCCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, + dpm_clks->SocClocks, + dpm_clks->NumSocClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_socclk_levels = dpm_clks->NumSocClkLevelsEnabled; + + /* DISPCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, + dpm_clks->DispClocks, + dpm_clks->NumDispClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = dpm_clks->NumDispClkLevelsEnabled; + + /* DPPCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, + dpm_clks->DppClocks, + dpm_clks->NumDispClkLevelsEnabled); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = dpm_clks->NumDispClkLevelsEnabled; + + /* FCLK */ + dcn42_init_single_clock(&clk_mgr_base->bw_params->clk_table.entries[0].fclk_mhz, + dpm_clks->FclkClocks_Freq, + NUM_FCLK_DPM_LEVELS); + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_fclk_levels = dpm_clks->NumFclkLevelsEnabled; + clk_mgr_base->bw_params->clk_table.num_entries = dpm_clks->NumFclkLevelsEnabled; + + /* Memory Pstate table is in reverse order*/ + ASSERT(dpm_clks->NumMemPstatesEnabled <= NUM_MEM_PSTATE_LEVELS); + if (dpm_clks->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) + dpm_clks->NumMemPstatesEnabled = NUM_MEM_PSTATE_LEVELS; + for (i = 0; i < dpm_clks->NumMemPstatesEnabled; i++) { + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].memclk_mhz = dpm_clks->MemPstateTable[i].MemClk; + clk_mgr_base->bw_params->clk_table.entries[dpm_clks->NumMemPstatesEnabled - 1 - i].wck_ratio = dcn42_convert_wck_ratio(dpm_clks->MemPstateTable[i].WckRatio) ; + } + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels = dpm_clks->NumMemPstatesEnabled; + + /* DTBCLK*/ + clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz = 600; /* Fixed on platform */ + clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_dtbclk_levels = 1; + } + } + if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr_base->ctx, DC_MEM_ALLOC_TYPE_GART, + smu_dpm_clks.dpm_clks); +} + +static struct clk_mgr_funcs dcn42_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, + .update_clocks = dcn42_update_clocks, + .init_clocks = dcn42_init_clocks, + .enable_pme_wa = dcn42_enable_pme_wa, + .are_clock_states_equal = dcn42_are_clock_states_equal, + .notify_wm_ranges = dcn42_notify_wm_ranges, + .set_low_power_state = dcn42_set_low_power_state, + .exit_low_power_state = dcn42_exit_low_power_state, + .get_max_clock_khz = dcn42_get_max_clock_khz, + .get_dispclk_from_dentist = dcn42_get_dispclk_from_dentist, + .is_smu_present = dcn42_is_smu_present, +}; + +struct clk_mgr_funcs dcn42_fpga_funcs = { + .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, + .update_clocks = dcn42_update_clocks_fpga, + .init_clocks = dcn42_init_clocks_fpga, + .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz, +}; + +void dcn42_clk_mgr_construct( + struct dc_context *ctx, + struct clk_mgr_dcn42 *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg) +{ + clk_mgr->base.base.ctx = ctx; + clk_mgr->base.base.funcs = &dcn42_funcs; + clk_mgr->base.regs = &clk_mgr_regs_dcn42; + clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn42; + clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn42; + + clk_mgr->base.pp_smu = pp_smu; + + clk_mgr->base.dccg = dccg; + clk_mgr->base.dfs_bypass_disp_clk = 0; + + clk_mgr->base.dprefclk_ss_percentage = 0; + clk_mgr->base.dprefclk_ss_divider = 1000; + clk_mgr->base.ss_on_dprefclk = false; + clk_mgr->base.dfs_ref_freq_khz = 48000; /*sync with pmfw*/ + clk_mgr->base.base.clks.ref_dtbclk_khz = 600000; + + /* Changed from DCN3.2_clock_frequency doc to match + * dcn32_dump_clk_registers from 4 * dentist_vco_freq_khz / + * dprefclk DID divider + */ + clk_mgr->base.base.dprefclk_khz = 600000; + + clk_mgr->base.smu_present = false; + clk_mgr->base.smu_ver = dcn42_smu_get_pmfw_version(&clk_mgr->base); + if (clk_mgr->base.smu_ver && clk_mgr->base.smu_ver != -1) + clk_mgr->base.smu_present = true; + + if (ctx->dc_bios->integrated_info) { + clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; + + if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) + dcn42_bw_params.wm_table = lpddr5_wm_table; + else + dcn42_bw_params.wm_table = ddr5_wm_table; + dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; + dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; + dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1; + clk_mgr->base.base.dprefclk_khz = dcn42_smu_get_dprefclk(&clk_mgr->base); + clk_mgr->base.base.clks.ref_dtbclk_khz = dcn42_smu_get_dtbclk(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); + } + /* in case we don't get a value from the BIOS, use default */ + if (clk_mgr->base.base.dentist_vco_freq_khz == 0) + clk_mgr->base.base.dentist_vco_freq_khz = 3000000; /* 3000MHz */ + + /* Saved clocks configured at boot for debug purposes */ + dcn42_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr); + + dce_clock_read_ss_info(&clk_mgr->base); + /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/ + + dcn42_read_ss_info_from_lut(&clk_mgr->base); + + clk_mgr->base.base.bw_params = &dcn42_bw_params; + if (clk_mgr->base.smu_present) + dcn42_get_smu_clocks(&clk_mgr->base); +} + +void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int) +{ + struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int); + + if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) + dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_GART, + clk_mgr->smu_wm_set.wm_set); +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h new file mode 100644 index 0000000000000..5ad027a9edaf0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DCN42_CLK_MGR_H__ +#define __DCN42_CLK_MGR_H__ +#include "clk_mgr_internal.h" + +#define NUM_CLOCK_SOURCES 5 + +struct dcn42_watermarks; + +struct dcn42_smu_watermark_set { + struct dcn42_watermarks *wm_set; + union large_integer mc_address; +}; + +struct dcn42_ss_info_table { + uint32_t ss_divider; + uint32_t ss_percentage[NUM_CLOCK_SOURCES]; +}; + +struct clk_mgr_dcn42 { + struct clk_mgr_internal base; + struct dcn42_smu_watermark_set smu_wm_set; +}; + +bool dcn42_are_clock_states_equal(struct dc_clocks *a, + struct dc_clocks *b); +void dcn42_init_clocks(struct clk_mgr *clk_mgr); +void dcn42_update_clocks(struct clk_mgr *clk_mgr_base, + struct dc_state *context, + bool safe_to_lower); + +void dcn42_clk_mgr_construct(struct dc_context *ctx, + struct clk_mgr_dcn42 *clk_mgr, + struct pp_smu_funcs *pp_smu, + struct dccg *dccg); + +void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int); + +void dcn42_init_single_clock(unsigned int *entry_0, + uint32_t *smu_entry_0, + uint8_t num_levels); +unsigned int dcn42_convert_wck_ratio(uint8_t wck_ratio); +extern struct dcn42_ss_info_table dcn42_ss_info_table; +void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table); +void dcn42_enable_pme_wa(struct clk_mgr *clk_mgr_base); +void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base); +void dcn42_set_low_power_state(struct clk_mgr *clk_mgr_base); +void dcn42_exit_low_power_state(struct clk_mgr *clk_mgr_base); +unsigned int dcn42_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type); +bool dcn42_is_smu_present(struct clk_mgr *clk_mgr_base); +int dcn42_get_active_display_cnt_wa(struct dc *dc, struct dc_state *context, int *all_active_disps); +void dcn42_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, bool safe_to_lower); +void dcn42_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, struct dc_state *context, int ref_dtbclk_khz); +bool dcn42_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base); +bool dcn42_has_active_display(struct dc *dc, const struct dc_state *context); +#endif //__DCN42_CLK_MGR_H__ diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c new file mode 100644 index 0000000000000..c791bb1edb47e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + + + +#include "core_types.h" +#include "clk_mgr_internal.h" +#include "reg_helper.h" +#include "dm_helpers.h" +#include "dcn42_smu.h" + +#include "mp/mp_15_0_0_offset.h" +#include "mp/mp_15_0_0_sh_mask.h" + +#ifdef BASE_INNER +#undef BASE_INNER +#endif + +#define MP1_BASE__INST0_SEG0 0x00016000 +#define MP1_BASE__INST0_SEG1 0x00016200 +#define MP1_BASE__INST0_SEG2 0x00E00000 +#define MP1_BASE__INST0_SEG3 0x00E80000 +#define MP1_BASE__INST0_SEG4 0x00EC0000 +#define MP1_BASE__INST0_SEG5 0x00F00000 +#define MP1_BASE__INST0_SEG6 0x02400400 +#define MP1_BASE__INST0_SEG7 0x0243F400 +#define MP1_BASE__INST0_SEG8 0x3C004000 +#define MP1_BASE__INST0_SEG9 0x3C3F4000 + +#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#define REG(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) + +#define FN(reg_name, field) \ + FD(reg_name##__##field) + +#include "logger_types.h" +#undef DC_LOGGER +#define DC_LOGGER \ + CTX->logger +#define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } + +// VBIOS and DAL to PMFW Interface + +// DAL to PMFW interface registers +#define DAL_MSG_REG MP1_SMN_C2PMSG_71 +#define DAL_RESP_REG MP1_SMN_C2PMSG_72 +#define DAL_ARG_REG MP1_SMN_C2PMSG_73 + +/** @defgroup ResponseCodes PMFW Response Codes +* @{ +*/ +// SMU Response Codes: +#define DALSMC_Result_OK 0x01 ///< Message Response OK +#define DALSMC_Result_Failed 0xFF ///< Message Response Failed +#define DALSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command +#define DALSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite +#define DALSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message +/** @}*/ + +// Message Definitions: +/** @defgroup definitions Message definitions +* @{ +*/ +#define DALSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team +#define DALSMC_MSG_GetPmfwVersion 0x02 ///< Get version +#define DALSMC_MSG_SetDispclkFreq 0x03 ///< Set display clock frequency in MHZ +#define DALSMC_MSG_SetDppclkFreq 0x04 ///< Set DPP clock frequency in MHZ +#define DALSMC_MSG_SetHardMinDcfclkByFreq 0x05 ///< Set DCF clock frequency hard min in MHZ +#define DALSMC_MSG_SetMinDeepSleepDcfclk 0x06 ///< Set DCF clock minimum frequency in deep sleep in MHZ +#define DALSMC_MSG_UpdatePmeRestore 0x07 ///< To ask PMFW to write into Azalia for PME wake up event +#define DALSMC_MSG_SetDramAddrHigh 0x08 ///< Set DRAM address high 32 bits for WM table transfer +#define DALSMC_MSG_SetDramAddrLow 0x09 ///< Set DRAM address low 32 bits for WM table transfer + +#define DALSMC_MSG_TransferTableSmu2Dram 0x0A ///< Transfer table from PMFW SRAM to system DRAM +#define DALSMC_MSG_TransferTableDram2Smu 0x0B ///< Transfer table from system DRAM to PMFW +#define DALSMC_MSG_SetDisplayIdleOptimizations 0x0C ///< Set Idle state optimization for display off +#define DALSMC_MSG_GetDprefclkFreq 0x0D ///< Get DPREF clock frequency. Return in MHZ +#define DALSMC_MSG_GetDtbclkFreq 0x0E ///< Get DTB clock frequency. Return in MHZ +#define DALSMC_MSG_AllowZstatesEntry 0x0F ///< Inform PMFW of display allowing Zstate entry +#define DALSMC_MSG_SetDtbClk 0x10 ///< Inform PMFW to turn of/off DTB cl0ck. arg = 1: turn DTB on with 600MHZ; arg = 0: turn DTB clk off +#define DALSMC_MSG_DispIPS2Exit 0x11 ///< Display IPS2 exit + +#define DALSMC_MSG_QueryIPS2Support 0x12 ///< Return 1: support; else not supported +#define DALSMC_Message_Count 0x13 ///< Total number of VBIS and DAL messages +/** @}*/ + + +union dcn42_dpia_host_router_bw { + struct { + uint32_t hr_id : 16; + uint32_t bw_mbps : 16; + } bits; + uint32_t all; +}; + +/* + * Function to be used instead of REG_WAIT macro because the wait ends when + * the register is NOT EQUAL to zero, and because `the translation in msg_if.h + * won't work with REG_WAIT. + */ +static uint32_t dcn42_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, + unsigned int delay_us, unsigned int max_retries) +{ + uint32_t res_val; + + do { + res_val = REG_READ(DAL_RESP_REG); + if (res_val != DALSMC_Result_CmdRejectedBusy) + break; + + if (delay_us >= 1000) + msleep(delay_us/1000); + else if (delay_us > 0) + udelay(delay_us); + + if (clk_mgr->base.ctx->dc->debug.disable_timeout) + max_retries++; + } while (max_retries--); + + return res_val; +} + +static int dcn42_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, + unsigned int msg_id, + unsigned int param) +{ + uint32_t result; + + result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000); + + if (result != DALSMC_Result_OK) { + DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id); + + if (result == DALSMC_Result_CmdRejectedBusy) + return -1; + } + + /* First clear response register */ + REG_WRITE(DAL_RESP_REG, DALSMC_Result_CmdRejectedBusy); + + /* Set the parameter register for the SMU message, unit is Mhz */ + REG_WRITE(DAL_ARG_REG, param); + + /* Trigger the message transaction by writing the message ID */ + REG_WRITE(DAL_MSG_REG, msg_id); + + result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000); + + if (result == DALSMC_Result_Failed) { + if (msg_id == DALSMC_MSG_TransferTableDram2Smu && + param == TABLE_WATERMARKS) + DC_LOG_WARNING("Watermarks table not configured properly by SMU"); + REG_WRITE(DAL_RESP_REG, DALSMC_Result_OK); + DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id); + return -1; + } + + if (IS_SMU_TIMEOUT(result)) { + ASSERT(0); + result = dcn42_smu_wait_for_response(clk_mgr, 10, 2000000); + //dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); + DC_LOG_WARNING("SMU response after wait: %d, msg id = %d\n", result, msg_id); + } + + return REG_READ(DAL_ARG_REG); +} + +int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr) +{ + return dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_GetPmfwVersion, + 0); +} + + +int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) +{ + int actual_dispclk_set_mhz; + + if (!clk_mgr->smu_present) + return requested_dispclk_khz; + + /* Unit of SMU msg parameter is Mhz */ + actual_dispclk_set_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDispclkFreq, + khz_to_mhz_ceil(requested_dispclk_khz)); + + smu_print("requested_dispclk_khz = %d, actual_dispclk_set_mhz: %d\n", + requested_dispclk_khz, actual_dispclk_set_mhz); + return (int)((long long)actual_dispclk_set_mhz * 1000); +} + + +int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) +{ + int actual_dcfclk_set_mhz; + + if (!clk_mgr->smu_present) + return requested_dcfclk_khz; + + actual_dcfclk_set_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetHardMinDcfclkByFreq, + khz_to_mhz_ceil(requested_dcfclk_khz)); + + smu_print("requested_dcfclk_khz = %d, actual_dcfclk_set_mhz: %d\n", + requested_dcfclk_khz, actual_dcfclk_set_mhz); + + return (int)((long long)actual_dcfclk_set_mhz * 1000); +} + +int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz) +{ + int actual_min_ds_dcfclk_mhz; + + if (!clk_mgr->smu_present) + return requested_min_ds_dcfclk_khz; + + actual_min_ds_dcfclk_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetMinDeepSleepDcfclk, + khz_to_mhz_ceil(requested_min_ds_dcfclk_khz)); + + smu_print("requested_min_ds_dcfclk_khz = %d, actual_min_ds_dcfclk_mhz: %d\n", + requested_min_ds_dcfclk_khz, actual_min_ds_dcfclk_mhz); + + return (int)((long long)actual_min_ds_dcfclk_mhz * 1000); +} + +int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) +{ + int actual_dppclk_set_mhz; + + if (!clk_mgr->smu_present) + return requested_dpp_khz; + + actual_dppclk_set_mhz = dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDppclkFreq, + khz_to_mhz_ceil(requested_dpp_khz)); + + smu_print("requested_dpp_khz = %d, actual_dppclk_set_mhz: %d\n", + requested_dpp_khz, actual_dppclk_set_mhz); + + return (int)((long long)actual_dppclk_set_mhz * 1000); +} + +void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info) +{ + if (!clk_mgr->base.ctx->dc->debug.pstate_enabled) + return; + + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDisplayIdleOptimizations, + idle_info); + smu_print("%s: SMC_MSG_SetDisplayIdleOptimizations idle_info = %x\n", __func__, idle_info); +} + +void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable) +{ + union display_idle_optimization_u idle_info = { 0 }; + + if (!clk_mgr->smu_present) + return; + + if (enable) { + idle_info.idle_info.df_request_disabled = 1; + idle_info.idle_info.phy_ref_clk_off = 1; + } + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDisplayIdleOptimizations, + idle_info.data); + smu_print("%s smu_enable_phy_refclk_pwrdwn = %d\n", __func__, enable ? 1 : 0); +} + +void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_UpdatePmeRestore, + 0); + smu_print("%s: SMC_MSG_UpdatePmeRestore\n", __func__); +} + +void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetDramAddrHigh, addr_high); +} + +void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_SetDramAddrLow, addr_low); +} + +void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS); +} + +void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS); +} + +void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support) +{ + unsigned int msg_id, param, retv; + + if (!clk_mgr->smu_present) + return; + + switch (support) { + + case DCN_ZSTATE_SUPPORT_ALLOW: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 10) | (1 << 9) | (1 << 8); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW, param = 0x%x\n", __func__, param); + break; + + case DCN_ZSTATE_SUPPORT_DISALLOW: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = 0; + smu_print("%s: SMC_MSG_AllowZstatesEntry msg_id = DISALLOW, param = 0x%x\n", __func__, param); + break; + + + case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 10); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z10_ONLY, param = 0x%x\n", __func__, param); + break; + + case DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 10) | (1 << 8); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_Z10_ONLY, param = 0x%x\n", __func__, param); + break; + + case DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY: + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = (1 << 8); + smu_print("%s: SMC_MSG_AllowZstatesEntry msg = ALLOW_Z8_ONLY, param = 0x%x\n", __func__, param); + break; + + default: //DCN_ZSTATE_SUPPORT_UNKNOWN + msg_id = DALSMC_MSG_AllowZstatesEntry; + param = 0; + break; + } + + + retv = dcn42_smu_send_msg_with_param( + clk_mgr, + msg_id, + param); + smu_print("%s: msg_id = %d, param = 0x%x, return = 0x%x\n", __func__, msg_id, param, retv); +} + +int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr) +{ + int dprefclk; + + if (!clk_mgr->smu_present) + return 0; + + dprefclk = dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDprefclkFreq, + 0); + + smu_print("%s: SMU DPREF clk = %d mhz\n", __func__, dprefclk); + return (int)((long long)dprefclk * 1000); +} + +int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr) +{ + int dtbclk; + + if (!clk_mgr->smu_present) + return 0; + + dtbclk = dcn42_smu_send_msg_with_param(clk_mgr, + DALSMC_MSG_GetDtbclkFreq, + 0); + + smu_print("%s: get_dtbclk = %dmhz\n", __func__, dtbclk); + return (int)((long long)dtbclk * 1000); +} +/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */ +void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable) +{ + if (!clk_mgr->smu_present) + return; + + dcn42_smu_send_msg_with_param( + clk_mgr, + DALSMC_MSG_SetDtbClk, + enable); + smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0); +} + diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h new file mode 100644 index 0000000000000..8ba7ff04dc05a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.h @@ -0,0 +1,190 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef DAL_DC_42_SMU_H_ +#define DAL_DC_42_SMU_H_ + +#include "os_types.h" + +#ifndef PMFW_DRIVER_IF_H +#define PMFW_DRIVER_IF_H +#define PMFW_DRIVER_IF_VERSION 7 + +typedef enum { + DSPCLK_DCFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; // in MHz + uint16_t Vid; // min voltage in SVI3 VID +} DisplayClockTable_t; + +typedef struct { + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t WmType; // Used for normal pstate change or memory retraining + uint8_t Padding[2]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 +#define WM_PSTATE_CHG 0 +#define WM_RETRAINING 1 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + + uint32_t MmHubPadding[7]; // SMU internal use +} Watermarks_t; + +#define NUM_DCFCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS 8 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_VCN_DPM_LEVELS 8 +#define NUM_SOC_VOLTAGE_LEVELS 8 +#define NUM_VPE_DPM_LEVELS 8 +#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_MEM_PSTATE_LEVELS 4 + +typedef enum { + WCK_RATIO_1_1 = 0, // DDR5, Wck:ck is always 1:1; + WCK_RATIO_1_2, + WCK_RATIO_1_4, + WCK_RATIO_MAX +} WCK_RATIO_e; + +typedef struct { + uint32_t UClk; + uint32_t MemClk; + uint32_t Voltage; + uint8_t WckRatio; + uint8_t Spare[3]; +} MemPstateTable_t; + + + // Watermarks + + +// Freq in MHz +// Voltage in milli volts with 2 fractional bits +typedef struct { + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + uint32_t VClocks[NUM_VCN_DPM_LEVELS]; + uint32_t DClocks[NUM_VCN_DPM_LEVELS]; + uint32_t VPEClocks[NUM_VPE_DPM_LEVELS]; + uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS]; + uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS]; + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; + MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS]; + + uint8_t NumDcfClkLevelsEnabled; + uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk + uint8_t NumSocClkLevelsEnabled; + uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk + + uint8_t VpeClkLevelsEnabled; + uint8_t NumMemPstatesEnabled; + uint8_t NumFclkLevelsEnabled; + uint8_t spare; + + uint32_t MinGfxClk; + uint32_t MaxGfxClk; +} DpmClocks_t_dcn42; + +// Throttler Status Bitmask + + +#define TABLE_BIOS_IF 0 // Called by BIOS +#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS +#define TABLE_CUSTOM_DPM 2 // Called by Driver +#define TABLE_SPARE1 3 +#define TABLE_DPMCLOCKS 4 // Called by Driver +#define TABLE_MOMENTARY_PM 5 // Called by Tools +#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log +#define TABLE_SMU_METRICS 7 // Called by Driver +#define TABLE_COUNT 8 + +#endif + +struct dcn42_watermarks { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + uint32_t MmHubPadding[7]; // SMU internal use +}; + +struct dcn42_smu_dpm_clks { + DpmClocks_t_dcn42 *dpm_clks; + union large_integer mc_address; +}; + +struct display_idle_optimization { + unsigned int df_request_disabled : 1; + unsigned int phy_ref_clk_off : 1; + unsigned int s0i2_rdy : 1; + unsigned int reserved : 29; +}; + +union display_idle_optimization_u { + struct display_idle_optimization idle_info; + uint32_t data; +}; + +int dcn42_smu_get_pmfw_version(struct clk_mgr_internal *clk_mgr); +int dcn42_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); +int dcn42_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); +int dcn42_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz); +int dcn42_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); +void dcn42_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info); +void dcn42_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); +void dcn42_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); +void dcn42_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); +void dcn42_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); +void dcn42_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); +void dcn42_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); + +void dcn42_smu_set_zstate_support(struct clk_mgr_internal *clk_mgr, enum dcn_zstate_support_state support); +void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable); +void dcn42_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); + +int dcn42_smu_get_dtbclk(struct clk_mgr_internal *clk_mgr); +int dcn42_smu_get_dprefclk(struct clk_mgr_internal *clk_mgr); + +#endif /* DAL_DC_42_SMU_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8be9cbd43e180..0389c379d0120 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -53,7 +53,7 @@ #include "dpp.h" #include "timing_generator.h" #include "abm.h" -#include "virtual/virtual_link_encoder.h" +#include "dio/virtual/virtual_link_encoder.h" #include "hubp.h" #include "link_hwss.h" @@ -442,75 +442,6 @@ static bool set_long_vtotal(struct dc *dc, struct dc_stream_state *stream, struc return false; } -/** - * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR - * @dc: dc reference - * @stream: Initial dc stream state - * @adjust: Updated parameters for vertical_total_min and vertical_total_max - * - * Looks up the pipe context of dc_stream_state and updates the - * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh - * Rate, which is a power-saving feature that targets reducing panel - * refresh rate while the screen is static - * - * Return: %true if the pipe context is found and adjusted; - * %false if the pipe context is not found. - */ -bool dc_stream_adjust_vmin_vmax(struct dc *dc, - struct dc_stream_state *stream, - struct dc_crtc_timing_adjust *adjust) -{ - int i; - - /* - * Don't adjust DRR while there's bandwidth optimizations pending to - * avoid conflicting with firmware updates. - */ - if (dc->ctx->dce_version > DCE_VERSION_MAX) { - if (dc->optimized_required && - (stream->adjust.v_total_max != adjust->v_total_max || - stream->adjust.v_total_min != adjust->v_total_min)) { - stream->adjust.timing_adjust_pending = true; - return false; - } - } - - dc_exit_ips_for_hw_access(dc); - - stream->adjust.v_total_max = adjust->v_total_max; - stream->adjust.v_total_mid = adjust->v_total_mid; - stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; - stream->adjust.v_total_min = adjust->v_total_min; - stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt; - - if (dc->caps.max_v_total != 0 && - (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) { - stream->adjust.timing_adjust_pending = false; - if (adjust->allow_otg_v_count_halt) - return set_long_vtotal(dc, stream, adjust); - else - return false; - } - - for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; - - if (pipe->stream == stream && pipe->stream_res.tg) { - dc->hwss.set_drr(&pipe, - 1, - *adjust); - stream->adjust.timing_adjust_pending = false; - - if (dc->hwss.notify_cursor_offload_drr_update) - dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); - - return true; - } - } - - return false; -} - /** * dc_stream_get_last_used_drr_vtotal - Looks up the pipe context of * dc_stream_state and gets the last VTOTAL used by DRR (Dynamic Refresh Rate) @@ -701,6 +632,7 @@ dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream, * once. * @idx: Capture CRC on which CRC engine instance * @reset: Reset CRC engine before the configuration + * @crc_poly_mode: CRC polynomial mode * * By default, the entire frame is used to calculate the CRC. * @@ -709,7 +641,7 @@ dc_stream_forward_multiple_crc_window(struct dc_stream_state *stream, */ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, struct crc_params *crc_window, bool enable, bool continuous, - uint8_t idx, bool reset) + uint8_t idx, bool reset, enum crc_poly_mode crc_poly_mode) { struct pipe_ctx *pipe; struct crc_params param; @@ -733,6 +665,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_start = 0; param.windowb_x_end = pipe->stream->timing.h_addressable; param.windowb_y_end = pipe->stream->timing.v_addressable; + param.crc_poly_mode = crc_poly_mode; if (crc_window) { param.windowa_x_start = crc_window->windowa_x_start; @@ -784,7 +717,7 @@ bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, uint8_t id uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) { int i; - struct pipe_ctx *pipe; + struct pipe_ctx *pipe = NULL; struct timing_generator *tg; dc_exit_ips_for_hw_access(dc); @@ -1272,6 +1205,8 @@ static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *conte get_fams2_visual_confirm_color(dc, context, pipe_ctx, &(pipe_ctx->visual_confirm_color)); else if (dc->debug.visual_confirm == VISUAL_CONFIRM_VABC) get_vabc_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) + get_refresh_rate_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); } } } @@ -1321,6 +1256,83 @@ void dc_get_visual_confirm_for_stream( } } +/** + * dc_stream_adjust_vmin_vmax - look up pipe context & update parts of DRR + * @dc: dc reference + * @stream: Initial dc stream state + * @adjust: Updated parameters for vertical_total_min and vertical_total_max + * + * Looks up the pipe context of dc_stream_state and updates the + * vertical_total_min and vertical_total_max of the DRR, Dynamic Refresh + * Rate, which is a power-saving feature that targets reducing panel + * refresh rate while the screen is static + * + * Return: %true if the pipe context is found and adjusted; + * %false if the pipe context is not found. + */ +bool dc_stream_adjust_vmin_vmax(struct dc *dc, + struct dc_stream_state *stream, + struct dc_crtc_timing_adjust *adjust) +{ + int i; + + /* + * Don't adjust DRR while there's bandwidth optimizations pending to + * avoid conflicting with firmware updates. + */ + if (dc->ctx->dce_version > DCE_VERSION_MAX) { + if (dc->optimized_required && + (stream->adjust.v_total_max != adjust->v_total_max || + stream->adjust.v_total_min != adjust->v_total_min)) { + stream->adjust.timing_adjust_pending = true; + return false; + } + } + + dc_exit_ips_for_hw_access(dc); + + stream->adjust.v_total_max = adjust->v_total_max; + stream->adjust.v_total_mid = adjust->v_total_mid; + stream->adjust.v_total_mid_frame_num = adjust->v_total_mid_frame_num; + stream->adjust.v_total_min = adjust->v_total_min; + stream->adjust.allow_otg_v_count_halt = adjust->allow_otg_v_count_halt; + + if (dc->caps.max_v_total != 0 && + (adjust->v_total_max > dc->caps.max_v_total || adjust->v_total_min > dc->caps.max_v_total)) { + stream->adjust.timing_adjust_pending = false; + if (adjust->allow_otg_v_count_halt) + return set_long_vtotal(dc, stream, adjust); + else + return false; + } + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe->stream == stream && pipe->stream_res.tg) { + dc->hwss.set_drr(&pipe, + 1, + *adjust); + stream->adjust.timing_adjust_pending = false; + + if (dc->debug.visual_confirm == VISUAL_CONFIRM_BOOSTED_REFRESH_RATE) { + if (pipe->stream && pipe->plane_state) { + dc_update_visual_confirm_color(dc, dc->current_state, pipe); + dc->hwss.update_visual_confirm_color(dc, pipe, pipe->plane_res.hubp->mpcc_id); + + } + } + + if (dc->hwss.notify_cursor_offload_drr_update) + dc->hwss.notify_cursor_offload_drr_update(dc, dc->current_state, stream); + + return true; + } + } + + return false; +} + static void disable_dangling_plane(struct dc *dc, struct dc_state *context) { int i, j; @@ -2605,6 +2617,16 @@ void dc_post_update_surfaces_to_stream(struct dc *dc) dc->optimized_required = false; } +void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info) +{ + if (!dc || !tiling_info) + return; + if (dc->res_pool && dc->res_pool->funcs && dc->res_pool->funcs->get_default_tiling_info) { + dc->res_pool->funcs->get_default_tiling_info(tiling_info); + return; + } +} + bool dc_set_generic_gpio_for_stereo(bool enable, struct gpio_service *gpio_service) { @@ -2674,7 +2696,7 @@ static bool is_surface_in_context( static struct surface_update_descriptor get_plane_info_update_type(const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; - struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor update_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; if (!u->plane_info) return update_type; @@ -2748,28 +2770,12 @@ static struct surface_update_descriptor get_plane_info_update_type(const struct if (memcmp(tiling, &u->surface->tiling_info, sizeof(*tiling)) != 0) { update_flags->bits.swizzle_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); - switch (tiling->gfxversion) { - case DcGfxVersion9: - case DcGfxVersion10: - case DcGfxVersion11: - if (tiling->gfx9.swizzle != DC_SW_LINEAR) { - update_flags->bits.bandwidth_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - } - break; - case DcGfxAddr3: - if (tiling->gfx_addr3.swizzle != DC_ADDR3_SW_LINEAR) { - update_flags->bits.bandwidth_change = 1; - elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - } - break; - case DcGfxVersion7: - case DcGfxVersion8: - case DcGfxVersionUnknown: - default: - break; + if (tiling->flags.avoid_full_update_on_tiling_change) { + elevate_update_type(&update_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } else { + update_flags->bits.bandwidth_change = 1; + elevate_update_type(&update_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } } @@ -2782,7 +2788,7 @@ static struct surface_update_descriptor get_scaling_info_update_type( const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; - struct surface_update_descriptor update_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor update_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; if (!u->scaling_info) return update_type; @@ -2833,11 +2839,11 @@ static struct surface_update_descriptor get_scaling_info_update_type( return update_type; } -static struct surface_update_descriptor det_surface_update( +static struct surface_update_descriptor check_update_surface( const struct dc_check_config *check_config, struct dc_surface_update *u) { - struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor overall_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; union surface_update_flags *update_flags = &u->surface->update_flags; if (u->surface->force_full_update) { @@ -2857,7 +2863,7 @@ static struct surface_update_descriptor det_surface_update( if (u->flip_addr) { update_flags->bits.addr_update = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_STREAM); if (u->flip_addr->address.tmz_surface != u->surface->address.tmz_surface) { update_flags->bits.tmz_changed = 1; @@ -2871,34 +2877,62 @@ static struct surface_update_descriptor det_surface_update( if (u->input_csc_color_matrix) { update_flags->bits.input_csc_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); + } + + if (u->cursor_csc_color_matrix) { + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->coeff_reduction_factor) { update_flags->bits.coeff_reduction_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->gamut_remap_matrix) { update_flags->bits.gamut_remap_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } - if (u->blend_tf || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { + if (u->cm || (u->gamma && dce_use_lut(u->plane_info ? u->plane_info->format : u->surface->format))) { update_flags->bits.gamma_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } - if (u->lut3d_func || u->func_shaper) { + if (u->cm && (u->cm->flags.bits.lut3d_enable || u->surface->cm.flags.bits.lut3d_enable)) { update_flags->bits.lut_3d = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); + } + + if (u->cm && u->cm->flags.bits.lut3d_dma_enable != u->surface->cm.flags.bits.lut3d_dma_enable && + u->cm->flags.bits.lut3d_enable && u->surface->cm.flags.bits.lut3d_enable) { + /* Toggling 3DLUT loading between DMA and Host is illegal */ + BREAK_TO_DEBUGGER(); + } + + if (u->cm && u->cm->flags.bits.lut3d_enable && !u->cm->flags.bits.lut3d_dma_enable) { + /* Host loading 3DLUT requires full update but only stream lock */ + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_STREAM); } if (u->hdr_mult.value) if (u->hdr_mult.value != u->surface->hdr_mult.value) { - // TODO: Should be fast? update_flags->bits.hdr_mult = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + elevate_update_type(&overall_type, + check_config->enable_legacy_fast_update ? UPDATE_TYPE_MED : UPDATE_TYPE_FAST, + LOCK_DESCRIPTOR_STREAM); } if (u->sdr_white_level_nits) @@ -2908,24 +2942,15 @@ static struct surface_update_descriptor det_surface_update( elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } - if (u->cm2_params) { - if (u->cm2_params->component_settings.shaper_3dlut_setting != u->surface->mcm_shaper_3dlut_setting - || u->cm2_params->component_settings.lut1d_enable != u->surface->mcm_lut1d_enable - || u->cm2_params->cm2_luts.lut3d_data.lut3d_src != u->surface->mcm_luts.lut3d_data.lut3d_src) { - update_flags->bits.mcm_transfer_function_enable_change = 1; - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - } - } - - if (update_flags->bits.lut_3d && - u->surface->mcm_luts.lut3d_data.lut3d_src != DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + if (u->cm_hist_control) { + update_flags->bits.cm_hist_change = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } - if (check_config->enable_legacy_fast_update && (update_flags->bits.gamma_change || update_flags->bits.gamut_remap_change || update_flags->bits.input_csc_change || + update_flags->bits.cm_hist_change || update_flags->bits.coeff_reduction_change)) { elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } @@ -2961,7 +2986,12 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( int surface_count, struct dc_stream_update *stream_update) { - struct surface_update_descriptor overall_type = { UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_NONE }; + struct surface_update_descriptor overall_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE }; + + /* When countdown finishes, promote this flip to full to trigger deferred final transition */ + if (check_config->deferred_transition_state && !check_config->transition_countdown_to_steady_state) { + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } if (stream_update && stream_update->pending_test_pattern) { elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); @@ -3023,7 +3053,18 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( if (su_flags->raw) elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); - // Non-global cases + /* Non-global cases */ + if (stream_update->hdr_static_metadata || + stream_update->vrr_infopacket || + stream_update->vsc_infopacket || + stream_update->vsp_infopacket || + stream_update->hfvsif_infopacket || + stream_update->adaptive_sync_infopacket || + stream_update->vtem_infopacket || + stream_update->avi_infopacket) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + if (stream_update->output_csc_transform) { su_flags->bits.out_csc = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); @@ -3033,11 +3074,32 @@ static struct surface_update_descriptor check_update_surfaces_for_stream( su_flags->bits.out_tf = 1; elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); } + + if (stream_update->periodic_interrupt) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->dither_option) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->cursor_position || stream_update->cursor_attributes) { + elevate_update_type(&overall_type, UPDATE_TYPE_MED, LOCK_DESCRIPTOR_STREAM); + } + + /* TODO - cleanup post blend CM */ + if (stream_update->func_shaper || stream_update->lut3d_func) { + elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM); + } + + if (stream_update->pending_test_pattern) { + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } } for (int i = 0 ; i < surface_count; i++) { struct surface_update_descriptor inner_type = - det_surface_update(check_config, &updates[i]); + check_update_surface(check_config, &updates[i]); elevate_update_type(&overall_type, inner_type.update_type, inner_type.lock_descriptor); } @@ -3058,12 +3120,87 @@ struct surface_update_descriptor dc_check_update_surfaces_for_stream( { if (stream_update) stream_update->stream->update_flags.raw = 0; - for (size_t i = 0; i < surface_count; i++) + for (int i = 0; i < surface_count; i++) updates[i].surface->update_flags.raw = 0; return check_update_surfaces_for_stream(check_config, updates, surface_count, stream_update); } +/* + * check_update_state_and_surfaces_for_stream() - Determine update type (fast, med, or full) + * + * This function performs checks on the DC global state, and is therefore not re-entrant. It + * should not be called from DM. + * + * See :c:type:`enum surface_update_type ` for explanation of update types + */ +static struct surface_update_descriptor check_update_state_and_surfaces_for_stream( + const struct dc *dc, + const struct dc_check_config *check_config, + const struct dc_stream_state *stream, + const struct dc_surface_update *updates, + const int surface_count, + const struct dc_stream_update *stream_update) +{ + const struct dc_state *context = dc->current_state; + + struct surface_update_descriptor overall_type = { UPDATE_TYPE_ADDR_ONLY, LOCK_DESCRIPTOR_NONE}; + + if (updates) + for (int i = 0; i < surface_count; i++) + if (!is_surface_in_context(context, updates[i].surface)) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + + if (stream) { + const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream); + if (stream_status == NULL || stream_status->plane_count != surface_count) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + } + if (dc->idle_optimizations_allowed) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + + if (dc_can_clear_cursor_limit(dc)) + elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); + + return overall_type; +} + +/* + * dc_check_update_state_and_surfaces_for_stream() - Determine update type (fast, med, or full) + * + * This function performs checks on the DC global state, stream and surface update, and is + * therefore not re-entrant. It should not be called from DM. + * + * See :c:type:`enum surface_update_type ` for explanation of update types + */ +static struct surface_update_descriptor dc_check_update_state_and_surfaces_for_stream( + const struct dc *dc, + const struct dc_check_config *check_config, + struct dc_stream_state *stream, + struct dc_surface_update *updates, + int surface_count, + struct dc_stream_update *stream_update) +{ + /* check updates against the entire DC state (global) first */ + struct surface_update_descriptor overall_update_type = check_update_state_and_surfaces_for_stream( + dc, + check_config, + stream, + updates, + surface_count, + stream_update); + + /* check updates for stream and plane */ + struct surface_update_descriptor stream_update_type = dc_check_update_surfaces_for_stream( + check_config, + updates, + surface_count, + stream_update); + elevate_update_type(&overall_update_type, stream_update_type.update_type, stream_update_type.lock_descriptor); + + return overall_update_type; +} + static struct dc_stream_status *stream_get_status( struct dc_state *ctx, struct dc_stream_state *stream) @@ -3152,6 +3289,11 @@ static void copy_surface_update_to_plane( surface->gamma_correction.type = srf_update->gamma->type; } + if (srf_update->cm_hist_control) { + memcpy(&surface->cm_hist_control, + srf_update->cm_hist_control, + sizeof(surface->cm_hist_control)); + } if (srf_update->in_transfer_func) { surface->in_transfer_func.sdr_ref_white_level = @@ -3165,24 +3307,12 @@ static void copy_surface_update_to_plane( sizeof(struct dc_transfer_func_distributed_points)); } - if (srf_update->cm2_params) { - surface->mcm_shaper_3dlut_setting = srf_update->cm2_params->component_settings.shaper_3dlut_setting; - surface->mcm_lut1d_enable = srf_update->cm2_params->component_settings.lut1d_enable; - surface->mcm_luts = srf_update->cm2_params->cm2_luts; - } - - if (srf_update->func_shaper) { - memcpy(&surface->in_shaper_func, srf_update->func_shaper, - sizeof(surface->in_shaper_func)); - - if (surface->mcm_shaper_3dlut_setting >= DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER) - surface->mcm_luts.shaper = &surface->in_shaper_func; + /* Shaper, 3DLUT, 1DLUT */ + if (srf_update->cm) { + memcpy(&surface->cm, srf_update->cm, + sizeof(surface->cm)); } - if (srf_update->lut3d_func) - memcpy(&surface->lut3d_func, srf_update->lut3d_func, - sizeof(surface->lut3d_func)); - if (srf_update->hdr_mult.value) surface->hdr_mult = srf_update->hdr_mult; @@ -3191,17 +3321,6 @@ static void copy_surface_update_to_plane( surface->sdr_white_level_nits = srf_update->sdr_white_level_nits; - if (srf_update->blend_tf) { - memcpy(&surface->blend_tf, srf_update->blend_tf, - sizeof(surface->blend_tf)); - - if (surface->mcm_lut1d_enable) - surface->mcm_luts.lut1d_func = &surface->blend_tf; - } - - if (srf_update->cm2_params || srf_update->blend_tf) - surface->lut_bank_a = !surface->lut_bank_a; - if (srf_update->input_csc_color_matrix) surface->input_csc_color_matrix = *srf_update->input_csc_color_matrix; @@ -3332,6 +3451,7 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->writeback_info[i] = update->wb_update->writeback_info[i]; } + if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3361,6 +3481,10 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->scaler_sharpener_update = *update->scaler_sharpener_update; if (update->sharpening_required) stream->sharpening_required = *update->sharpening_required; + + if (update->drr_trigger_mode) { + stream->drr_trigger_mode = *update->drr_trigger_mode; + } } static void backup_planes_and_stream_state( @@ -3434,12 +3558,48 @@ static void update_seamless_boot_flags(struct dc *dc, } } -static bool full_update_required_weak( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream); +struct pipe_split_policy_backup { + bool dynamic_odm_policy; + bool subvp_policy; + enum pipe_split_policy mpc_policy; + char force_odm[MAX_PIPES]; +}; + +static void backup_and_set_minimal_pipe_split_policy(struct dc *dc, + struct dc_state *context, + struct pipe_split_policy_backup *policy) +{ + int i; + + if (!dc->config.is_vmin_only_asic) { + policy->mpc_policy = dc->debug.pipe_split_policy; + dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; + } + policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy; + dc->debug.enable_single_display_2to1_odm_policy = false; + policy->subvp_policy = dc->debug.force_disable_subvp; + dc->debug.force_disable_subvp = true; + for (i = 0; i < context->stream_count; i++) { + policy->force_odm[i] = context->streams[i]->debug.force_odm_combine_segments; + if (context->streams[i]->debug.allow_transition_for_forced_odm) + context->streams[i]->debug.force_odm_combine_segments = 0; + } +} + +static void restore_minimal_pipe_split_policy(struct dc *dc, + struct dc_state *context, + struct pipe_split_policy_backup *policy) +{ + uint8_t i; + + if (!dc->config.is_vmin_only_asic) + dc->debug.pipe_split_policy = policy->mpc_policy; + dc->debug.enable_single_display_2to1_odm_policy = + policy->dynamic_odm_policy; + dc->debug.force_disable_subvp = policy->subvp_policy; + for (i = 0; i < context->stream_count; i++) + context->streams[i]->debug.force_odm_combine_segments = policy->force_odm[i]; +} /** * update_planes_and_stream_state() - The function takes planes and stream @@ -3467,12 +3627,11 @@ static bool update_planes_and_stream_state(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update, - enum surface_update_type *new_update_type, + struct surface_update_descriptor *update_descriptor, struct dc_state **new_context) { struct dc_state *context; int i, j; - enum surface_update_type update_type; const struct dc_stream_status *stream_status; struct dc_context *dc_ctx = dc->ctx; @@ -3486,17 +3645,20 @@ static bool update_planes_and_stream_state(struct dc *dc, } context = dc->current_state; - update_type = dc_check_update_surfaces_for_stream( - &dc->check_config, srf_updates, surface_count, stream_update).update_type; - if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) - update_type = UPDATE_TYPE_FULL; + *update_descriptor = dc_check_update_state_and_surfaces_for_stream( + dc, + &dc->check_config, + stream, + srf_updates, + surface_count, + stream_update); /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. */ force_immediate_gsl_plane_flip(dc, srf_updates, surface_count); - if (update_type == UPDATE_TYPE_FULL) + if (update_descriptor->update_type == UPDATE_TYPE_FULL) backup_planes_and_stream_state(&dc->scratch.current_state, stream); /* update current stream with the new updates */ @@ -3522,7 +3684,7 @@ static bool update_planes_and_stream_state(struct dc *dc, } } - if (update_type == UPDATE_TYPE_FULL) { + if (update_descriptor->update_type == UPDATE_TYPE_FULL) { if (stream_update) { uint32_t dsc_changed = stream_update->stream->update_flags.bits.dsc_changed; stream_update->stream->update_flags.raw = 0xFFFFFFFF; @@ -3532,13 +3694,13 @@ static bool update_planes_and_stream_state(struct dc *dc, srf_updates[i].surface->update_flags.raw = 0xFFFFFFFF; } - if (update_type >= update_surface_trace_level) + if (update_descriptor->update_type >= update_surface_trace_level) update_surface_trace(dc, srf_updates, surface_count); for (i = 0; i < surface_count; i++) copy_surface_update_to_plane(srf_updates[i].surface, &srf_updates[i]); - if (update_type >= UPDATE_TYPE_FULL) { + if (update_descriptor->update_type >= UPDATE_TYPE_FULL) { struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) @@ -3576,7 +3738,7 @@ static bool update_planes_and_stream_state(struct dc *dc, for (i = 0; i < surface_count; i++) { struct dc_plane_state *surface = srf_updates[i].surface; - if (update_type != UPDATE_TYPE_MED) + if (update_descriptor->update_type != UPDATE_TYPE_MED) continue; if (surface->update_flags.bits.position_change) { for (j = 0; j < dc->res_pool->pipe_count; j++) { @@ -3590,17 +3752,36 @@ static bool update_planes_and_stream_state(struct dc *dc, } } - if (update_type == UPDATE_TYPE_FULL) { + if (update_descriptor->update_type == UPDATE_TYPE_FULL) { + struct pipe_split_policy_backup policy; + bool minimize = false; + + if (dc->check_config.deferred_transition_state) { + if (dc->check_config.transition_countdown_to_steady_state) { + /* During countdown, all new contexts created as minimal transition states */ + minimize = true; + } else { + dc->check_config.deferred_transition_state = false; + } + } + + if (minimize) + backup_and_set_minimal_pipe_split_policy(dc, context, &policy); + if (dc->res_pool->funcs->validate_bandwidth(dc, context, DC_VALIDATE_MODE_AND_PROGRAMMING) != DC_OK) { + if (minimize) + restore_minimal_pipe_split_policy(dc, context, &policy); BREAK_TO_DEBUGGER(); goto fail; } + + if (minimize) + restore_minimal_pipe_split_policy(dc, context, &policy); } update_seamless_boot_flags(dc, context, surface_count, stream); *new_context = context; - *new_update_type = update_type; - if (update_type == UPDATE_TYPE_FULL) + if (update_descriptor->update_type == UPDATE_TYPE_FULL) backup_planes_and_stream_state(&dc->scratch.new_state, stream); return true; @@ -3680,7 +3861,7 @@ static void commit_planes_do_stream_update(struct dc *dc, program_cursor_position(dc, stream); /* Full fe update*/ - if (update_type == UPDATE_TYPE_FAST) + if (update_type <= UPDATE_TYPE_FAST) continue; if (stream_update->dsc_config) @@ -3781,7 +3962,7 @@ static bool dc_dmub_should_send_dirty_rect_cmd(struct dc *dc, struct dc_stream_s void dc_dmub_update_dirty_rect(struct dc *dc, int surface_count, struct dc_stream_state *stream, - struct dc_surface_update *srf_updates, + const struct dc_surface_update *srf_updates, struct dc_state *context) { union dmub_rb_cmd cmd; @@ -3792,7 +3973,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) return; memset(&cmd, 0x0, sizeof(cmd)); @@ -3812,7 +3993,11 @@ void dc_dmub_update_dirty_rect(struct dc *dc, if (srf_updates[i].surface->flip_immediate) continue; - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + if (dc->config.frame_update_cmd_version2) + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + else + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); @@ -3826,6 +4011,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc, update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); } } @@ -3848,7 +4034,7 @@ static void build_dmub_update_dirty_rect( if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream)) return; - if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) + if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst)) return; memset(&cmd, 0x0, sizeof(cmd)); @@ -3867,7 +4053,12 @@ static void build_dmub_update_dirty_rect( /* Do not send in immediate flip mode */ if (srf_updates[i].surface->flip_immediate) continue; - update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; + + if (dc->config.frame_update_cmd_version2) + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + else + update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count; memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects, sizeof(flip_addr->dirty_rects)); @@ -3880,6 +4071,7 @@ static void build_dmub_update_dirty_rect( continue; update_dirty_rect->panel_inst = panel_inst; update_dirty_rect->pipe_idx = j; + update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst; dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd; dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT; (*dmub_cmd_count)++; @@ -3978,7 +4170,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, struct pipe_ctx *top_pipe_to_program = NULL; struct dc_stream_status *stream_status = NULL; bool should_offload_fams2_flip = false; - bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); + bool should_lock_all_pipes = (update_type > UPDATE_TYPE_FAST); if (should_lock_all_pipes) determine_pipe_unlock_order(dc, context); @@ -4038,7 +4230,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, continue; pipe_ctx->plane_state->triplebuffer_flips = false; - if (update_type == UPDATE_TYPE_FAST && + if (update_type <= UPDATE_TYPE_FAST && dc->hwss.program_triplebuffer != NULL && !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { /*triple buffer for VUpdate only*/ @@ -4086,7 +4278,7 @@ static void commit_planes_for_stream_fast(struct dc *dc, } static void commit_planes_for_stream(struct dc *dc, - struct dc_surface_update *srf_updates, + const struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update, @@ -4095,7 +4287,7 @@ static void commit_planes_for_stream(struct dc *dc, { int i, j; struct pipe_ctx *top_pipe_to_program = NULL; - bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); + bool should_lock_all_pipes = (update_type > UPDATE_TYPE_FAST); bool subvp_prev_use = false; bool subvp_curr_use = false; uint8_t current_stream_mask = 0; @@ -4112,7 +4304,7 @@ static void commit_planes_for_stream(struct dc *dc, if (update_type == UPDATE_TYPE_FULL && dc->optimized_required) hwss_process_outstanding_hw_updates(dc, dc->current_state); - if (update_type != UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming) + if (update_type > UPDATE_TYPE_FAST && dc->res_pool->funcs->prepare_mcache_programming) dc->res_pool->funcs->prepare_mcache_programming(dc, context); for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -4174,7 +4366,7 @@ static void commit_planes_for_stream(struct dc *dc, odm_pipe->ttu_regs.min_ttu_vblank = MAX_TTU; } - if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) + if ((update_type > UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program && top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { if (should_use_dmub_inbox1_lock(dc, stream->link)) { @@ -4245,7 +4437,7 @@ static void commit_planes_for_stream(struct dc *dc, } dc->hwss.post_unlock_program_front_end(dc, context); - if (update_type != UPDATE_TYPE_FAST) + if (update_type > UPDATE_TYPE_FAST) if (dc->hwss.commit_subvp_config) dc->hwss.commit_subvp_config(dc, context); @@ -4261,7 +4453,7 @@ static void commit_planes_for_stream(struct dc *dc, return; } - if (update_type != UPDATE_TYPE_FAST) { + if (update_type > UPDATE_TYPE_FAST) { for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -4289,7 +4481,7 @@ static void commit_planes_for_stream(struct dc *dc, if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; pipe_ctx->plane_state->triplebuffer_flips = false; - if (update_type == UPDATE_TYPE_FAST && + if (update_type <= UPDATE_TYPE_FAST && dc->hwss.program_triplebuffer != NULL && !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { /*triple buffer for VUpdate only*/ @@ -4316,7 +4508,7 @@ static void commit_planes_for_stream(struct dc *dc, continue; /* Full fe update*/ - if (update_type == UPDATE_TYPE_FAST) + if (update_type <= UPDATE_TYPE_FAST) continue; stream_status = @@ -4335,7 +4527,7 @@ static void commit_planes_for_stream(struct dc *dc, continue; /* Full fe update*/ - if (update_type == UPDATE_TYPE_FAST) + if (update_type <= UPDATE_TYPE_FAST) continue; ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); @@ -4346,7 +4538,7 @@ static void commit_planes_for_stream(struct dc *dc, } } - if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) { + if (dc->hwss.program_front_end_for_ctx && update_type > UPDATE_TYPE_FAST) { dc->hwss.program_front_end_for_ctx(dc, context); //Pipe busy until some frame and line # @@ -4374,7 +4566,7 @@ static void commit_planes_for_stream(struct dc *dc, } // Update Type FAST, Surface updates - if (update_type == UPDATE_TYPE_FAST) { + if (update_type <= UPDATE_TYPE_FAST) { if (dc->hwss.set_flip_control_gsl) for (i = 0; i < surface_count; i++) { struct dc_plane_state *plane_state = srf_updates[i].surface; @@ -4407,13 +4599,11 @@ static void commit_planes_for_stream(struct dc *dc, if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; - if (srf_updates[i].cm2_params && - srf_updates[i].cm2_params->cm2_luts.lut3d_data.lut3d_src == - DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM && - srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting == - DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT && + if (srf_updates[i].cm && + srf_updates[i].cm->flags.bits.lut3d_enable && + srf_updates[i].cm->flags.bits.lut3d_dma_enable && dc->hwss.trigger_3dlut_dma_load) - dc->hwss.trigger_3dlut_dma_load(dc, pipe_ctx); + dc->hwss.trigger_3dlut_dma_load(pipe_ctx); /*program triple buffer after lock based on flip type*/ if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { @@ -4433,7 +4623,7 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); } - if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) + if ((update_type > UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed) if (top_pipe_to_program && top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) { top_pipe_to_program->stream_res.tg->funcs->wait_for_state( @@ -4466,13 +4656,13 @@ static void commit_planes_for_stream(struct dc *dc, /* If enabling subvp or transitioning from subvp->subvp, enable the * phantom streams before we program front end for the phantom pipes. */ - if (update_type != UPDATE_TYPE_FAST) { + if (update_type > UPDATE_TYPE_FAST) { if (dc->hwss.enable_phantom_streams) dc->hwss.enable_phantom_streams(dc, context); } } - if (update_type != UPDATE_TYPE_FAST) + if (update_type > UPDATE_TYPE_FAST) dc->hwss.post_unlock_program_front_end(dc, context); if (subvp_prev_use && !subvp_curr_use) { @@ -4485,7 +4675,7 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.disable_phantom_streams(dc, context); } - if (update_type != UPDATE_TYPE_FAST) + if (update_type > UPDATE_TYPE_FAST) if (dc->hwss.commit_subvp_config) dc->hwss.commit_subvp_config(dc, context); /* Since phantom pipe programming is moved to post_unlock_program_front_end, @@ -4622,48 +4812,6 @@ static bool could_mpcc_tree_change_for_active_pipes(struct dc *dc, return force_minimal_pipe_splitting; } -struct pipe_split_policy_backup { - bool dynamic_odm_policy; - bool subvp_policy; - enum pipe_split_policy mpc_policy; - char force_odm[MAX_PIPES]; -}; - -static void backup_and_set_minimal_pipe_split_policy(struct dc *dc, - struct dc_state *context, - struct pipe_split_policy_backup *policy) -{ - int i; - - if (!dc->config.is_vmin_only_asic) { - policy->mpc_policy = dc->debug.pipe_split_policy; - dc->debug.pipe_split_policy = MPC_SPLIT_AVOID; - } - policy->dynamic_odm_policy = dc->debug.enable_single_display_2to1_odm_policy; - dc->debug.enable_single_display_2to1_odm_policy = false; - policy->subvp_policy = dc->debug.force_disable_subvp; - dc->debug.force_disable_subvp = true; - for (i = 0; i < context->stream_count; i++) { - policy->force_odm[i] = context->streams[i]->debug.force_odm_combine_segments; - if (context->streams[i]->debug.allow_transition_for_forced_odm) - context->streams[i]->debug.force_odm_combine_segments = 0; - } -} - -static void restore_minimal_pipe_split_policy(struct dc *dc, - struct dc_state *context, - struct pipe_split_policy_backup *policy) -{ - uint8_t i; - - if (!dc->config.is_vmin_only_asic) - dc->debug.pipe_split_policy = policy->mpc_policy; - dc->debug.enable_single_display_2to1_odm_policy = - policy->dynamic_odm_policy; - dc->debug.force_disable_subvp = policy->subvp_policy; - for (i = 0; i < context->stream_count; i++) - context->streams[i]->debug.force_odm_combine_segments = policy->force_odm[i]; -} static void release_minimal_transition_state(struct dc *dc, struct dc_state *minimal_transition_context, @@ -4773,6 +4921,7 @@ static int initialize_empty_surface_updates( static bool commit_minimal_transition_based_on_new_context(struct dc *dc, struct dc_state *new_context, struct dc_stream_state *stream, + struct dc_stream_update *stream_update, struct dc_surface_update *srf_updates, int surface_count) { @@ -4790,7 +4939,7 @@ static bool commit_minimal_transition_based_on_new_context(struct dc *dc, new_context)) { DC_LOG_DC("commit minimal transition state: base = new state\n"); commit_planes_for_stream(dc, srf_updates, - surface_count, stream, NULL, + surface_count, stream, stream_update, UPDATE_TYPE_FULL, intermediate_context); swap_and_release_current_context( dc, intermediate_context, stream); @@ -4884,8 +5033,8 @@ static bool commit_minimal_transition_state_in_dc_update(struct dc *dc, int surface_count) { bool success = commit_minimal_transition_based_on_new_context( - dc, new_context, stream, srf_updates, - surface_count); + dc, new_context, stream, NULL, + srf_updates, surface_count); if (!success) success = commit_minimal_transition_based_on_current_context(dc, new_context, stream); @@ -4998,184 +5147,12 @@ static bool commit_minimal_transition_state(struct dc *dc, return true; } -void populate_fast_updates(struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_update *stream_update) -{ - int i = 0; - - if (stream_update) { - fast_update[0].out_transfer_func = stream_update->out_transfer_func; - fast_update[0].output_csc_transform = stream_update->output_csc_transform; - } else { - fast_update[0].out_transfer_func = NULL; - fast_update[0].output_csc_transform = NULL; - } - - for (i = 0; i < surface_count; i++) { - fast_update[i].flip_addr = srf_updates[i].flip_addr; - fast_update[i].gamma = srf_updates[i].gamma; - fast_update[i].gamut_remap_matrix = srf_updates[i].gamut_remap_matrix; - fast_update[i].input_csc_color_matrix = srf_updates[i].input_csc_color_matrix; - fast_update[i].coeff_reduction_factor = srf_updates[i].coeff_reduction_factor; - fast_update[i].cursor_csc_color_matrix = srf_updates[i].cursor_csc_color_matrix; - } -} - -static bool fast_updates_exist(const struct dc_fast_update *fast_update, int surface_count) -{ - int i; - - if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) - return true; - - for (i = 0; i < surface_count; i++) { - if (fast_update[i].flip_addr || - fast_update[i].gamma || - fast_update[i].gamut_remap_matrix || - fast_update[i].input_csc_color_matrix || - fast_update[i].cursor_csc_color_matrix || - fast_update[i].coeff_reduction_factor) - return true; - } - - return false; -} - -bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count) -{ - int i; - - if (fast_update[0].out_transfer_func || - fast_update[0].output_csc_transform) - return true; - - for (i = 0; i < surface_count; i++) { - if (fast_update[i].input_csc_color_matrix || - fast_update[i].gamma || - fast_update[i].gamut_remap_matrix || - fast_update[i].coeff_reduction_factor || - fast_update[i].cursor_csc_color_matrix) - return true; - } - - return false; -} - -static bool full_update_required_weak( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - const struct dc_state *context = dc->current_state; - if (srf_updates) - for (int i = 0; i < surface_count; i++) - if (!is_surface_in_context(context, srf_updates[i].surface)) - return true; - - if (stream) { - const struct dc_stream_status *stream_status = dc_stream_get_status_const(stream); - if (stream_status == NULL || stream_status->plane_count != surface_count) - return true; - } - if (dc->idle_optimizations_allowed) - return true; - - if (dc_can_clear_cursor_limit(dc)) - return true; - - return false; -} - -static bool full_update_required( - const struct dc *dc, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - if (full_update_required_weak(dc, srf_updates, surface_count, stream_update, stream)) - return true; - - for (int i = 0; i < surface_count; i++) { - if (srf_updates && - (srf_updates[i].plane_info || - srf_updates[i].scaling_info || - (srf_updates[i].hdr_mult.value && - srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) || - (srf_updates[i].sdr_white_level_nits && - srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || - srf_updates[i].in_transfer_func || - srf_updates[i].func_shaper || - srf_updates[i].lut3d_func || - srf_updates[i].surface->force_full_update || - (srf_updates[i].flip_addr && - srf_updates[i].flip_addr->address.tmz_surface != srf_updates[i].surface->address.tmz_surface) || - (srf_updates[i].cm2_params && - (srf_updates[i].cm2_params->component_settings.shaper_3dlut_setting != srf_updates[i].surface->mcm_shaper_3dlut_setting || - srf_updates[i].cm2_params->component_settings.lut1d_enable != srf_updates[i].surface->mcm_lut1d_enable)))) - return true; - } - - if (stream_update && - (((stream_update->src.height != 0 && stream_update->src.width != 0) || - (stream_update->dst.height != 0 && stream_update->dst.width != 0) || - stream_update->integer_scaling_update) || - stream_update->hdr_static_metadata || - stream_update->abm_level || - stream_update->periodic_interrupt || - stream_update->vrr_infopacket || - stream_update->vsc_infopacket || - stream_update->vsp_infopacket || - stream_update->hfvsif_infopacket || - stream_update->vtem_infopacket || - stream_update->adaptive_sync_infopacket || - stream_update->avi_infopacket || - stream_update->dpms_off || - stream_update->allow_freesync || - stream_update->vrr_active_variable || - stream_update->vrr_active_fixed || - stream_update->gamut_remap || - stream_update->output_color_space || - stream_update->dither_option || - stream_update->wb_update || - stream_update->dsc_config || - stream_update->mst_bw_update || - stream_update->func_shaper || - stream_update->lut3d_func || - stream_update->pending_test_pattern || - stream_update->crtc_timing_adjust || - stream_update->scaler_sharpener_update || - stream_update->hw_cursor_req)) - return true; - - return false; -} - -static bool fast_update_only( - const struct dc *dc, - const struct dc_fast_update *fast_update, - const struct dc_surface_update *srf_updates, - int surface_count, - const struct dc_stream_update *stream_update, - const struct dc_stream_state *stream) -{ - return fast_updates_exist(fast_update, surface_count) - && !full_update_required(dc, srf_updates, surface_count, stream_update, stream); -} - static bool update_planes_and_stream_v2(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { struct dc_state *context; - enum surface_update_type update_type; - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; /* In cases where MPO and split or ODM are used transitions can * cause underflow. Apply stream configuration with minimal pipe @@ -5183,11 +5160,9 @@ static bool update_planes_and_stream_v2(struct dc *dc, */ bool force_minimal_pipe_splitting = 0; bool is_plane_addition = 0; - bool is_fast_update_only; - populate_fast_updates(fast_update, srf_updates, surface_count, stream_update); - is_fast_update_only = fast_update_only(dc, fast_update, srf_updates, - surface_count, stream_update, stream); + struct surface_update_descriptor update_descriptor = {0}; + force_minimal_pipe_splitting = could_mpcc_tree_change_for_active_pipes( dc, stream, @@ -5206,7 +5181,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, surface_count, stream, stream_update, - &update_type, + &update_descriptor, &context)) return false; @@ -5216,7 +5191,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, dc_state_release(context); return false; } - update_type = UPDATE_TYPE_FULL; + elevate_update_type(&update_descriptor, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL); } if (dc->hwss.is_pipe_topology_transition_seamless && @@ -5225,13 +5200,13 @@ static bool update_planes_and_stream_v2(struct dc *dc, commit_minimal_transition_state_in_dc_update(dc, context, stream, srf_updates, surface_count); - if (is_fast_update_only && !dc->check_config.enable_legacy_fast_update) { + if (update_descriptor.update_type <= UPDATE_TYPE_FAST) { commit_planes_for_stream_fast(dc, srf_updates, surface_count, stream, stream_update, - update_type, + update_descriptor.update_type, context); } else { if (!stream_update && @@ -5247,7 +5222,7 @@ static bool update_planes_and_stream_v2(struct dc *dc, surface_count, stream, stream_update, - update_type, + update_descriptor.update_type, context); } if (dc->current_state != context) @@ -5261,14 +5236,8 @@ static void commit_planes_and_stream_update_on_current_context(struct dc *dc, struct dc_stream_update *stream_update, enum surface_update_type update_type) { - struct dc_fast_update fast_update[MAX_SURFACES] = {0}; - ASSERT(update_type < UPDATE_TYPE_FULL); - populate_fast_updates(fast_update, srf_updates, surface_count, - stream_update); - if (fast_update_only(dc, fast_update, srf_updates, surface_count, - stream_update, stream) && - !dc->check_config.enable_legacy_fast_update) + if (update_type <= UPDATE_TYPE_FAST) commit_planes_for_stream_fast(dc, srf_updates, surface_count, @@ -5294,32 +5263,63 @@ static void commit_planes_and_stream_update_with_new_context(struct dc *dc, enum surface_update_type update_type, struct dc_state *new_context) { + bool skip_new_context = false; ASSERT(update_type >= UPDATE_TYPE_FULL); - if (!dc->hwss.is_pipe_topology_transition_seamless(dc, - dc->current_state, new_context)) - /* - * It is required by the feature design that all pipe topologies - * using extra free pipes for power saving purposes such as - * dynamic ODM or SubVp shall only be enabled when it can be - * transitioned seamlessly to AND from its minimal transition - * state. A minimal transition state is defined as the same dc - * state but with all power saving features disabled. So it uses - * the minimum pipe topology. When we can't seamlessly - * transition from state A to state B, we will insert the - * minimal transition state A' or B' in between so seamless - * transition between A and B can be made possible. - */ - commit_minimal_transition_state_in_dc_update(dc, new_context, - stream, srf_updates, surface_count); + /* + * It is required by the feature design that all pipe topologies + * using extra free pipes for power saving purposes such as + * dynamic ODM or SubVp shall only be enabled when it can be + * transitioned seamlessly to AND from its minimal transition + * state. A minimal transition state is defined as the same dc + * state but with all power saving features disabled. So it uses + * the minimum pipe topology. When we can't seamlessly + * transition from state A to state B, we will insert the + * minimal transition state A' or B' in between so seamless + * transition between A and B can be made possible. + * + * To optimize for the time it takes to execute flips, + * the transition from the minimal state to the final state is + * deferred until a steady state (no more transitions) is reached. + */ + if (!dc->hwss.is_pipe_topology_transition_seamless(dc, dc->current_state, new_context)) { + if (!dc->debug.disable_deferred_minimal_transitions) { + dc->check_config.deferred_transition_state = true; + dc->check_config.transition_countdown_to_steady_state = + dc->debug.num_fast_flips_to_steady_state_override ? + dc->debug.num_fast_flips_to_steady_state_override : + NUM_FAST_FLIPS_TO_STEADY_STATE; + + if (commit_minimal_transition_based_on_new_context(dc, new_context, stream, stream_update, + srf_updates, surface_count)) { + skip_new_context = true; + dc_state_release(new_context); + new_context = dc->current_state; + } else { + /* + * In this case a new mpo plane is being enabled on pipes that were + * previously in use, and the surface update to the existing plane + * includes an alpha box where the new plane will be, so the update + * from minimal to final cannot be deferred as the alpha box would + * be visible to the user + */ + commit_minimal_transition_based_on_current_context(dc, new_context, stream); + } + } else { + commit_minimal_transition_state_in_dc_update(dc, new_context, stream, + srf_updates, surface_count); + } + } else if (dc->check_config.deferred_transition_state) { + /* reset countdown as steady state not reached */ + dc->check_config.transition_countdown_to_steady_state = + dc->debug.num_fast_flips_to_steady_state_override ? + dc->debug.num_fast_flips_to_steady_state_override : + NUM_FAST_FLIPS_TO_STEADY_STATE; + } - commit_planes_for_stream( - dc, - srf_updates, - surface_count, - stream, - stream_update, - update_type, - new_context); + if (!skip_new_context) { + commit_planes_for_stream(dc, srf_updates, surface_count, stream, stream_update, update_type, new_context); + swap_and_release_current_context(dc, new_context, stream); + } } static bool update_planes_and_stream_v3(struct dc *dc, @@ -5328,7 +5328,7 @@ static bool update_planes_and_stream_v3(struct dc *dc, struct dc_stream_update *stream_update) { struct dc_state *new_context; - enum surface_update_type update_type; + struct surface_update_descriptor update_descriptor = {0}; /* * When this function returns true and new_context is not equal to @@ -5340,20 +5340,26 @@ static bool update_planes_and_stream_v3(struct dc *dc, * replaced by a newer context. Refer to the use of * swap_and_free_current_context below. */ - if (!update_planes_and_stream_state(dc, srf_updates, surface_count, - stream, stream_update, &update_type, + if (!update_planes_and_stream_state(dc, + srf_updates, + surface_count, + stream, + stream_update, + &update_descriptor, &new_context)) return false; if (new_context == dc->current_state) { commit_planes_and_stream_update_on_current_context(dc, srf_updates, surface_count, stream, - stream_update, update_type); + stream_update, update_descriptor.update_type); + + if (dc->check_config.transition_countdown_to_steady_state) + dc->check_config.transition_countdown_to_steady_state--; } else { commit_planes_and_stream_update_with_new_context(dc, srf_updates, surface_count, stream, - stream_update, update_type, new_context); - swap_and_release_current_context(dc, new_context, stream); + stream_update, update_descriptor.update_type, new_context); } return true; @@ -5377,35 +5383,23 @@ bool dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - bool ret = false; + struct dc_update_scratch_space *scratch = dc_update_planes_and_stream_init( + dc, + srf_updates, + surface_count, + stream, + stream_update + ); + bool more = true; - dc_exit_ips_for_hw_access(dc); - /* - * update planes and stream version 3 separates FULL and FAST updates - * to their own sequences. It aims to clean up frequent checks for - * update type resulting unnecessary branching in logic flow. It also - * adds a new commit minimal transition sequence, which detects the need - * for minimal transition based on the actual comparison of current and - * new states instead of "predicting" it based on per feature software - * policy.i.e could_mpcc_tree_change_for_active_pipes. The new commit - * minimal transition sequence is made universal to any power saving - * features that would use extra free pipes such as Dynamic ODM/MPC - * Combine, MPO or SubVp. Therefore there is no longer a need to - * specially handle compatibility problems with transitions among those - * features as they are now transparent to the new sequence. - */ - if (dc->ctx->dce_version >= DCN_VERSION_4_01 || dc->ctx->dce_version == DCN_VERSION_3_2 || - dc->ctx->dce_version == DCN_VERSION_3_21) - ret = update_planes_and_stream_v3(dc, srf_updates, - surface_count, stream, stream_update); - else - ret = update_planes_and_stream_v2(dc, srf_updates, - surface_count, stream, stream_update); - if (ret && (dc->ctx->dce_version >= DCN_VERSION_3_2 || - dc->ctx->dce_version == DCN_VERSION_3_01)) - clear_update_flags(srf_updates, surface_count, stream); + while (more) { + if (!dc_update_planes_and_stream_prepare(scratch)) + return false; - return ret; + dc_update_planes_and_stream_execute(scratch); + more = dc_update_planes_and_stream_cleanup(scratch); + } + return true; } void dc_commit_updates_for_stream(struct dc *dc, @@ -5476,6 +5470,9 @@ void dc_power_down_on_boot(struct dc *dc) { if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW && dc->hwss.power_down_on_boot) { + if (dc->current_state->stream_count > 0) + return; + if (dc->caps.ips_support) dc_exit_ips_for_hw_access(dc); dc->hwss.power_down_on_boot(dc); @@ -5487,12 +5484,12 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state) if (!dc->current_state) return; + dc_exit_ips_for_hw_access(dc); + switch (power_state) { case DC_ACPI_CM_POWER_STATE_D0: dc_state_construct(dc, dc->current_state); - dc_exit_ips_for_hw_access(dc); - dc_z10_restore(dc); dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state); @@ -5868,6 +5865,7 @@ bool dc_is_dmub_outbox_supported(struct dc *dc) case AMDGPU_FAMILY_GC_11_0_1: case AMDGPU_FAMILY_GC_11_5_0: + case AMDGPU_FAMILY_GC_11_5_4: if (!dc->debug.dpia_debug.bits.disable_dpia) return true; break; @@ -6820,7 +6818,7 @@ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_softwa struct dc_plane_state *plane_state = pipe_ctx->plane_state; /* MPCC blending tree and mode control - capture actual blend configuration */ - state->mpc.mpcc_mode[i] = (plane_state->blend_tf.type != TF_TYPE_BYPASS) ? 1 : 0; + state->mpc.mpcc_mode[i] = (plane_state->cm.blend_func.type != TF_TYPE_BYPASS) ? 1 : 0; state->mpc.mpcc_alpha_blend_mode[i] = plane_state->per_pixel_alpha ? 1 : 0; state->mpc.mpcc_alpha_multiplied_mode[i] = plane_state->pre_multiplied_alpha ? 1 : 0; state->mpc.mpcc_blnd_active_overlap_only[i] = 0; /* Default - no overlap restriction */ @@ -7091,3 +7089,384 @@ void dc_log_preos_dmcub_info(const struct dc *dc) { dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv); } + +bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info) +{ + const struct dc_clocks *clk = &dc->current_state->bw_ctx.bw.dcn.clk; + struct memory_qos qos; + + memset(info, 0, sizeof(*info)); + + // Check if measurement function is available + if (!dc->hwss.measure_memory_qos) { + return false; + } + + // Call unified measurement function + dc->hwss.measure_memory_qos(dc, &qos); + + // Populate info from measured qos + info->actual_peak_bw_in_mbps = qos.peak_bw_mbps; + info->actual_avg_bw_in_mbps = qos.avg_bw_mbps; + info->actual_min_latency_in_ns = qos.min_latency_ns; + info->actual_max_latency_in_ns = qos.max_latency_ns; + info->actual_avg_latency_in_ns = qos.avg_latency_ns; + info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64); + + return true; +} + +enum update_v3_flow { + UPDATE_V3_FLOW_INVALID, + UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST, + UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL, + UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS, + UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW, + UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT, +}; + +struct dc_update_scratch_space { + struct dc *dc; + struct dc_surface_update *surface_updates; + int surface_count; + struct dc_stream_state *stream; + struct dc_stream_update *stream_update; + bool update_v3; + bool do_clear_update_flags; + struct surface_update_descriptor update_descriptor; + struct dc_state *new_context; + enum update_v3_flow flow; + struct dc_state *backup_context; + struct dc_state *intermediate_context; + struct pipe_split_policy_backup intermediate_policy; + struct dc_surface_update intermediate_updates[MAX_SURFACES]; + int intermediate_count; +}; + +size_t dc_update_scratch_space_size(void) +{ + return sizeof(struct dc_update_scratch_space); +} + +static bool update_planes_and_stream_prepare_v2( + struct dc_update_scratch_space *scratch +) +{ + // v2 is too tangled to break into stages, so just execute everything under lock + dc_exit_ips_for_hw_access(scratch->dc); + return update_planes_and_stream_v2( + scratch->dc, + scratch->surface_updates, + scratch->surface_count, + scratch->stream, + scratch->stream_update + ); +} + +static void update_planes_and_stream_execute_v2( + const struct dc_update_scratch_space *scratch +) +{ + // Nothing to do, see `update_planes_and_stream_prepare_v2` + (void) scratch; +} + +static bool update_planes_and_stream_cleanup_v2( + const struct dc_update_scratch_space *scratch +) +{ + if (scratch->do_clear_update_flags) + clear_update_flags(scratch->surface_updates, scratch->surface_count, scratch->stream); + + return false; +} + +static void update_planes_and_stream_cleanup_v3_release_minimal( + struct dc_update_scratch_space *scratch, + bool backup +); + +static bool update_planes_and_stream_prepare_v3_intermediate_seamless( + struct dc_update_scratch_space *scratch +) +{ + return is_pipe_topology_transition_seamless_with_intermediate_step( + scratch->dc, + scratch->dc->current_state, + scratch->intermediate_context, + scratch->new_context + ); +} + +static void transition_countdown_init(struct dc *dc) +{ + dc->check_config.transition_countdown_to_steady_state = + dc->debug.num_fast_flips_to_steady_state_override ? + dc->debug.num_fast_flips_to_steady_state_override : + NUM_FAST_FLIPS_TO_STEADY_STATE; +} + +static bool update_planes_and_stream_prepare_v3( + struct dc_update_scratch_space *scratch +) +{ + if (scratch->flow == UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS) { + return true; + } + ASSERT(scratch->flow == UPDATE_V3_FLOW_INVALID); + dc_exit_ips_for_hw_access(scratch->dc); + + if (!update_planes_and_stream_state( + scratch->dc, + scratch->surface_updates, + scratch->surface_count, + scratch->stream, + scratch->stream_update, + &scratch->update_descriptor, + &scratch->new_context + )) { + return false; + } + + if (scratch->new_context == scratch->dc->current_state) { + ASSERT(scratch->update_descriptor.update_type < UPDATE_TYPE_FULL); + + scratch->flow = scratch->update_descriptor.update_type <= UPDATE_TYPE_FAST + ? UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST + : UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL; + return true; + } + + ASSERT(scratch->update_descriptor.update_type >= UPDATE_TYPE_FULL); + + const bool seamless = scratch->dc->hwss.is_pipe_topology_transition_seamless( + scratch->dc, + scratch->dc->current_state, + scratch->new_context + ); + if (seamless) { + scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS; + if (scratch->dc->check_config.deferred_transition_state) + /* reset countdown as steady state not reached */ + transition_countdown_init(scratch->dc); + return true; + } + + if (!scratch->dc->debug.disable_deferred_minimal_transitions) { + scratch->dc->check_config.deferred_transition_state = true; + transition_countdown_init(scratch->dc); + } + + scratch->intermediate_context = create_minimal_transition_state( + scratch->dc, + scratch->new_context, + &scratch->intermediate_policy + ); + if (scratch->intermediate_context) { + if (update_planes_and_stream_prepare_v3_intermediate_seamless(scratch)) { + scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW; + return true; + } + + update_planes_and_stream_cleanup_v3_release_minimal(scratch, false); + } + + scratch->backup_context = scratch->dc->current_state; + restore_planes_and_stream_state(&scratch->dc->scratch.current_state, scratch->stream); + dc_state_retain(scratch->backup_context); + scratch->intermediate_context = create_minimal_transition_state( + scratch->dc, + scratch->backup_context, + &scratch->intermediate_policy + ); + if (scratch->intermediate_context) { + if (update_planes_and_stream_prepare_v3_intermediate_seamless(scratch)) { + scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT; + scratch->intermediate_count = initialize_empty_surface_updates( + scratch->stream, scratch->intermediate_updates + ); + return true; + } + + update_planes_and_stream_cleanup_v3_release_minimal(scratch, true); + } + + scratch->flow = UPDATE_V3_FLOW_INVALID; + dc_state_release(scratch->backup_context); + restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream); + return false; +} + +static void update_planes_and_stream_execute_v3_commit( + const struct dc_update_scratch_space *scratch, + bool intermediate_update, + bool intermediate_context, + bool use_stream_update +) +{ + commit_planes_for_stream( + scratch->dc, + intermediate_update ? scratch->intermediate_updates : scratch->surface_updates, + intermediate_update ? scratch->intermediate_count : scratch->surface_count, + scratch->stream, + use_stream_update ? scratch->stream_update : NULL, + intermediate_context ? UPDATE_TYPE_FULL : scratch->update_descriptor.update_type, + // `dc->current_state` only used in `NO_NEW_CONTEXT`, where it is equal to `new_context` + intermediate_context ? scratch->intermediate_context : scratch->new_context + ); +} + +static void update_planes_and_stream_execute_v3( + const struct dc_update_scratch_space *scratch +) +{ + switch (scratch->flow) { + case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST: + commit_planes_for_stream_fast( + scratch->dc, + scratch->surface_updates, + scratch->surface_count, + scratch->stream, + scratch->stream_update, + scratch->update_descriptor.update_type, + scratch->new_context + ); + break; + + case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL: + case UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS: + update_planes_and_stream_execute_v3_commit(scratch, false, false, true); + break; + + case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW: + update_planes_and_stream_execute_v3_commit(scratch, false, true, + scratch->dc->check_config.deferred_transition_state); + break; + + case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT: + update_planes_and_stream_execute_v3_commit(scratch, true, true, false); + break; + + case UPDATE_V3_FLOW_INVALID: + default: + ASSERT(false); + } +} + +static void update_planes_and_stream_cleanup_v3_release_minimal( + struct dc_update_scratch_space *scratch, + bool backup +) +{ + release_minimal_transition_state( + scratch->dc, + scratch->intermediate_context, + backup ? scratch->backup_context : scratch->new_context, + &scratch->intermediate_policy + ); +} + +static void update_planes_and_stream_cleanup_v3_intermediate( + struct dc_update_scratch_space *scratch, + bool backup +) +{ + swap_and_release_current_context(scratch->dc, scratch->intermediate_context, scratch->stream); + dc_state_retain(scratch->dc->current_state); + update_planes_and_stream_cleanup_v3_release_minimal(scratch, backup); +} + +static bool update_planes_and_stream_cleanup_v3( + struct dc_update_scratch_space *scratch +) +{ + switch (scratch->flow) { + case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FAST: + case UPDATE_V3_FLOW_NO_NEW_CONTEXT_CONTEXT_FULL: + if (scratch->dc->check_config.transition_countdown_to_steady_state) + scratch->dc->check_config.transition_countdown_to_steady_state--; + break; + + case UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS: + swap_and_release_current_context(scratch->dc, scratch->new_context, scratch->stream); + break; + + case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_NEW: + update_planes_and_stream_cleanup_v3_intermediate(scratch, false); + if (scratch->dc->check_config.deferred_transition_state) { + dc_state_release(scratch->new_context); + } else { + scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS; + return true; + } + break; + + case UPDATE_V3_FLOW_NEW_CONTEXT_MINIMAL_CURRENT: + update_planes_and_stream_cleanup_v3_intermediate(scratch, true); + dc_state_release(scratch->backup_context); + restore_planes_and_stream_state(&scratch->dc->scratch.new_state, scratch->stream); + scratch->flow = UPDATE_V3_FLOW_NEW_CONTEXT_SEAMLESS; + return true; + + case UPDATE_V3_FLOW_INVALID: + default: + ASSERT(false); + } + + if (scratch->do_clear_update_flags) + clear_update_flags(scratch->surface_updates, scratch->surface_count, scratch->stream); + + return false; +} + +struct dc_update_scratch_space *dc_update_planes_and_stream_init( + struct dc *dc, + struct dc_surface_update *surface_updates, + int surface_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update +) +{ + const enum dce_version version = dc->ctx->dce_version; + struct dc_update_scratch_space *scratch = stream->update_scratch; + + *scratch = (struct dc_update_scratch_space){ + .dc = dc, + .surface_updates = surface_updates, + .surface_count = surface_count, + .stream = stream, + .stream_update = stream_update, + .update_v3 = version >= DCN_VERSION_4_01 || version == DCN_VERSION_3_2 || version == DCN_VERSION_3_21, + .do_clear_update_flags = version >= DCN_VERSION_1_0, + }; + + return scratch; +} + +bool dc_update_planes_and_stream_prepare( + struct dc_update_scratch_space *scratch +) +{ + return scratch->update_v3 + ? update_planes_and_stream_prepare_v3(scratch) + : update_planes_and_stream_prepare_v2(scratch); +} + +void dc_update_planes_and_stream_execute( + const struct dc_update_scratch_space *scratch +) +{ + scratch->update_v3 + ? update_planes_and_stream_execute_v3(scratch) + : update_planes_and_stream_execute_v2(scratch); +} + +bool dc_update_planes_and_stream_cleanup( + struct dc_update_scratch_space *scratch +) +{ + return scratch->update_v3 + ? update_planes_and_stream_cleanup_v3(scratch) + : update_planes_and_stream_cleanup_v2(scratch); +} + diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index e2763b60482a0..5b3695e72e196 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -741,6 +741,7 @@ void hwss_build_fast_sequence(struct dc *dc, struct dce_hwseq *hws = dc->hwseq; struct pipe_ctx *current_pipe = NULL; struct pipe_ctx *current_mpc_pipe = NULL; + bool is_dmub_lock_required = false; unsigned int i = 0; *num_steps = 0; // Initialize to 0 @@ -763,11 +764,12 @@ void hwss_build_fast_sequence(struct dc *dc, (*num_steps)++; } if (dc->hwss.dmub_hw_control_lock_fast) { + is_dmub_lock_required = dc_state_is_fams2_in_use(dc, context) || + dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link); + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = true; - block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = - dc_state_is_fams2_in_use(dc, context) || - dmub_hw_lock_mgr_does_link_require_lock(dc, stream->link); + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required; block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; (*num_steps)++; } @@ -844,6 +846,16 @@ void hwss_build_fast_sequence(struct dc *dc, block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE; (*num_steps)++; } + if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) { + block_sequence[*num_steps].params.control_cm_hist_params.dpp + = current_mpc_pipe->plane_res.dpp; + block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control + = current_mpc_pipe->plane_state->cm_hist_control; + block_sequence[*num_steps].params.control_cm_hist_params.color_space + = current_mpc_pipe->plane_state->color_space; + block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST; + (*num_steps)++; + } } if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) { block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc; @@ -906,7 +918,7 @@ void hwss_build_fast_sequence(struct dc *dc, if (dc->hwss.dmub_hw_control_lock_fast) { block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.dc = dc; block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.lock = false; - block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = dc_state_is_fams2_in_use(dc, context); + block_sequence[*num_steps].params.dmub_hw_control_lock_fast_params.is_required = is_dmub_lock_required; block_sequence[*num_steps].func = DMUB_HW_CONTROL_LOCK_FAST; (*num_steps)++; } @@ -1027,6 +1039,9 @@ void hwss_execute_sequence(struct dc *dc, case HUBP_PROGRAM_MCACHE_ID: hwss_program_mcache_id_and_split_coordinate(params); break; + case DPP_PROGRAM_CM_HIST: + hwss_program_cm_hist(params); + break; case PROGRAM_CURSOR_UPDATE_NOW: dc->hwss.program_cursor_offload_now( params->program_cursor_update_now_params.dc, @@ -2052,6 +2067,16 @@ void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *pa } +void hwss_program_cm_hist(union block_sequence_params *params) +{ + struct dpp *dpp = params->control_cm_hist_params.dpp; + + if (dpp && dpp->funcs->dpp_cm_hist_control) + dpp->funcs->dpp_cm_hist_control(dpp, + params->control_cm_hist_params.cm_hist_control, + params->control_cm_hist_params.color_space); +} + void get_surface_tile_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color) @@ -3368,6 +3393,20 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s } } +void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct cm_hist_control cm_hist_control, + enum dc_color_space color_space) +{ + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { + seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST; + seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp; + seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control; + seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space; + (*seq_state->num_steps)++; + } +} + void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, struct dc *dc, bool enable) @@ -4069,3 +4108,24 @@ void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state, (*seq_state->num_steps)++; } } + + +void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + unsigned int refresh_rate = 0; + uint32_t scaling_factor = 0; + if (pipe_ctx && pipe_ctx->stream && color) { + refresh_rate = (pipe_ctx->stream->timing.pix_clk_100hz * 100) / (pipe_ctx->stream->adjust.v_total_max * pipe_ctx->stream->timing.h_total); + + uint32_t min_refresh_rate = pipe_ctx->stream->timing.min_refresh_in_uhz / 1000000; + uint32_t max_refresh_rate = pipe_ctx->stream->timing.max_refresh_in_uhz / 1000000; + + if (max_refresh_rate - min_refresh_rate) + scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate); + + pipe_ctx->visual_confirm_color.color_r_cr = color_value; + pipe_ctx->visual_confirm_color.color_g_y = scaling_factor; + pipe_ctx->visual_confirm_color.color_b_cb = color_value; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c index 9acd300197173..7bb4504889be7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c @@ -491,6 +491,28 @@ bool dc_link_get_replay_state(const struct dc_link *link, uint64_t *state) return link->dc->link_srv->edp_get_replay_state(link, state); } +bool dc_link_set_pr_enable(struct dc_link *link, bool enable) +{ + return link->dc->link_srv->dp_pr_enable(link, enable); +} + +bool dc_link_update_pr_state(struct dc_link *link, + struct dmub_cmd_pr_update_state_data *update_state_data) +{ + return link->dc->link_srv->dp_pr_update_state(link, update_state_data); +} + +bool dc_link_set_pr_general_cmd(struct dc_link *link, + struct dmub_cmd_pr_general_cmd_data *general_cmd_data) +{ + return link->dc->link_srv->dp_pr_set_general_cmd(link, general_cmd_data); +} + +bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state) +{ + return link->dc->link_srv->dp_pr_get_state(link, state); +} + bool dc_link_wait_for_t12(struct dc_link *link) { return link->dc->link_srv->edp_wait_for_t12(link); @@ -527,4 +549,3 @@ void dc_link_get_alpm_support(struct dc_link *link, { link->dc->link_srv->edp_get_alpm_support(link, auxless_support, auxwake_support); } - diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 848c267ef11e7..727bcf08a84fb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -37,7 +37,7 @@ #include "dpp.h" #include "core_types.h" #include "set_mode_types.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dpcd_defs.h" #include "link_enc_cfg.h" #include "link_service.h" @@ -45,7 +45,7 @@ #include "dc_state_priv.h" #include "dc_stream_priv.h" -#include "virtual/virtual_link_hwss.h" +#include "link/hwss/link_hwss_virtual.h" #include "link/hwss/link_hwss_dio.h" #include "link/hwss/link_hwss_dpia.h" #include "link/hwss/link_hwss_hpo_dp.h" @@ -78,6 +78,7 @@ #include "dcn351/dcn351_resource.h" #include "dcn36/dcn36_resource.h" #include "dcn401/dcn401_resource.h" +#include "dcn42/dcn42_resource.h" #if defined(CONFIG_DRM_AMD_DC_FP) #include "dc_spl_translate.h" #endif @@ -252,6 +253,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev)) dc_version = DCN_VERSION_4_01; break; + case AMDGPU_FAMILY_GC_11_5_4: + dc_version = DCN_VERSION_4_2; + break; default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -368,6 +372,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, case DCN_VERSION_4_01: res_pool = dcn401_create_resource_pool(init_data, dc); break; + case DCN_VERSION_4_2: + res_pool = dcn42_create_resource_pool(init_data, dc); + break; #endif /* CONFIG_DRM_AMD_DC_FP */ default: break; @@ -742,10 +749,10 @@ struct clock_source *resource_find_used_clk_src_for_sharing( return NULL; } -static enum pixel_format convert_pixel_format_to_dalsurface( +static enum dc_pixel_format convert_pixel_format_to_dalsurface( enum surface_pixel_format surface_pixel_format) { - enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; + enum dc_pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN; switch (surface_pixel_format) { case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: @@ -2424,7 +2431,6 @@ static void resource_log_pipe_for_stream(struct dc *dc, struct dc_state *state, int slice_idx, dpp_idx, plane_idx, slice_count, dpp_count; bool is_primary; - DC_LOGGER_INIT(dc->ctx->logger); slice_count = resource_get_opp_heads_for_otg_master(otg_master, &state->res_ctx, opp_heads); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 129cd5f849837..87ecef6e699fa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -151,6 +151,7 @@ static void dc_stream_free(struct kref *kref) struct dc_stream_state *stream = container_of(kref, struct dc_stream_state, refcount); dc_stream_destruct(stream); + kfree(stream->update_scratch); kfree(stream); } @@ -164,26 +165,34 @@ void dc_stream_release(struct dc_stream_state *stream) struct dc_stream_state *dc_create_stream_for_sink( struct dc_sink *sink) { - struct dc_stream_state *stream; + struct dc_stream_state *stream = NULL; if (sink == NULL) - return NULL; + goto fail; + + stream = kzalloc(sizeof(struct dc_stream_state), GFP_ATOMIC); - stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); if (stream == NULL) - goto alloc_fail; + goto fail; + + stream->update_scratch = kzalloc((int32_t) dc_update_scratch_space_size(), GFP_ATOMIC); + + if (stream->update_scratch == NULL) + goto fail; if (dc_stream_construct(stream, sink) == false) - goto construct_fail; + goto fail; kref_init(&stream->refcount); return stream; -construct_fail: - kfree(stream); +fail: + if (stream) { + kfree(stream->update_scratch); + kfree(stream); + } -alloc_fail: return NULL; } @@ -195,6 +204,16 @@ struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream) if (!new_stream) return NULL; + // Scratch is not meant to be reused across copies, as might have self-referential pointers + new_stream->update_scratch = kzalloc( + (int32_t) dc_update_scratch_space_size(), + GFP_KERNEL + ); + if (!new_stream->update_scratch) { + kfree(new_stream); + return NULL; + } + if (new_stream->sink) dc_sink_retain(new_stream->sink); @@ -228,7 +247,6 @@ const struct dc_stream_status *dc_stream_get_status_const( const struct dc_stream_state *stream) { struct dc *dc = stream->ctx->dc; - return dc_state_get_stream_status(dc->current_state, stream); } @@ -498,6 +516,23 @@ bool dc_stream_program_cursor_position( } } + if (stream->drr_trigger_mode == DRR_TRIGGER_ON_FLIP_AND_CURSOR) { + /* apply manual trigger */ + int i; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + /* trigger event on first pipe with current stream */ + if (stream == pipe_ctx->stream && + pipe_ctx->stream_res.tg->funcs->program_manual_trigger) { + pipe_ctx->stream_res.tg->funcs->program_manual_trigger( + pipe_ctx->stream_res.tg); + break; + } + } + } + return true; } @@ -952,7 +987,6 @@ void dc_stream_release_3dlut_for_stream( if (rmcm_3dlut) { rmcm_3dlut->isInUse = false; rmcm_3dlut->stream = NULL; - rmcm_3dlut->protection_bits = 0; } } @@ -964,7 +998,6 @@ void dc_stream_init_rmcm_3dlut(struct dc *dc) for (int i = 0; i < num_rmcm; i++) { dc->res_pool->rmcm_3dlut[i].isInUse = false; dc->res_pool->rmcm_3dlut[i].stream = NULL; - dc->res_pool->rmcm_3dlut[i].protection_bits = 0; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 0971dfa258454..5d3a8a63b7cdb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -139,6 +139,9 @@ const struct dc_plane_status *dc_plane_get_status( if (pipe_ctx->plane_state && flags.bits.address) pipe_ctx->plane_state->status.is_flip_pending = false; + if (pipe_ctx->plane_state && flags.bits.histogram) + memset(&pipe_ctx->plane_state->status.cm_hist, 0, + sizeof(pipe_ctx->plane_state->status.cm_hist)); break; } @@ -154,6 +157,12 @@ const struct dc_plane_status *dc_plane_get_status( if (flags.bits.address) dc->hwss.update_pending_status(pipe_ctx); + if (flags.bits.histogram) { + struct dpp *dpp = pipe_ctx->plane_res.dpp; + + if (dpp && dpp->funcs->dpp_cm_hist_read) + dpp->funcs->dpp_cm_hist_read(dpp, &pipe_ctx->plane_state->status.cm_hist); + } } return plane_status; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 29edfa51ea2cc..d682b32c4bd86 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-2023 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -63,7 +63,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.359" +#define DC_VER "3.2.375" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC @@ -82,6 +82,8 @@ struct dcn_dccg_reg_state; #define MAX_DPIA_PER_HOST_ROUTER 3 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) +#define NUM_FAST_FLIPS_TO_STEADY_STATE 20 + /* Display Core Interfaces */ struct dc_versions { const char *dc_ver; @@ -293,6 +295,9 @@ struct dc_check_config { */ unsigned int max_optimizable_video_width; bool enable_legacy_fast_update; + + bool deferred_transition_state; + unsigned int transition_countdown_to_steady_state; }; struct dc_caps { @@ -462,6 +467,7 @@ struct dc_static_screen_params { */ enum surface_update_type { + UPDATE_TYPE_ADDR_ONLY, /* only surface address is being updated, no other programming needed */ UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ UPDATE_TYPE_FULL, /* may need to shuffle resources */ @@ -500,7 +506,6 @@ union allow_lttpr_non_transparent_mode { } bits; unsigned char raw; }; - /* Structure to hold configuration flags set by dm at dc creation. */ struct dc_config { bool gpu_vm_support; @@ -555,8 +560,10 @@ struct dc_config { bool enable_dpia_pre_training; bool unify_link_enc_assignment; bool enable_cursor_offload; + bool frame_update_cmd_version2; struct spl_sharpness_range dcn_sharpness_range; struct spl_sharpness_range dcn_override_sharpness_range; + bool no_native422_support; }; enum visual_confirm { @@ -576,6 +583,7 @@ enum visual_confirm { VISUAL_CONFIRM_HW_CURSOR = 20, VISUAL_CONFIRM_VABC = 21, VISUAL_CONFIRM_DCC = 22, + VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, VISUAL_CONFIRM_EXPLICIT = 0x80000000, }; @@ -728,6 +736,8 @@ struct dc_clocks { struct { uint8_t base_efficiency; //LP1 uint8_t low_power_efficiency; //LP2 + uint8_t z8_stutter_efficiency; + int z8_stutter_period; } stutter_efficiency; }; @@ -951,6 +961,19 @@ struct dc_bounding_box_overrides { int min_dcfclk_mhz; }; +struct dc_qos_info { + uint32_t actual_peak_bw_in_mbps; + uint32_t qos_bandwidth_lb_in_mbps; + uint32_t actual_avg_bw_in_mbps; + uint32_t calculated_avg_bw_in_mbps; + uint32_t actual_max_latency_in_ns; + uint32_t actual_min_latency_in_ns; + uint32_t qos_max_latency_ub_in_ns; + uint32_t actual_avg_latency_in_ns; + uint32_t qos_avg_latency_ub_in_ns; + uint32_t dcn_bandwidth_ub_in_mbps; +}; + struct dc_state; struct resource_pool; struct dce_hwseq; @@ -965,7 +988,6 @@ struct link_service; * causing an issue or not. */ struct dc_debug_options { - bool native422_support; bool disable_dsc; enum visual_confirm visual_confirm; int visual_confirm_rect_height; @@ -1130,6 +1152,9 @@ struct dc_debug_options { unsigned int min_prefetch_in_strobe_ns; bool disable_unbounded_requesting; bool dig_fifo_off_in_blank; + #ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + bool temp_mst_deallocation_sequence; + #endif bool override_dispclk_programming; bool otg_crc_db; bool disallow_dispclk_dppclk_ds; @@ -1188,6 +1213,13 @@ struct dc_debug_options { short auxless_alpm_lfps_t1t2_offset_us; bool disable_stutter_for_wm_program; bool enable_block_sequence_programming; + uint32_t custom_psp_footer_size; + bool disable_deferred_minimal_transitions; + unsigned int num_fast_flips_to_steady_state_override; + bool enable_dmu_recovery; + unsigned int force_vmin_threshold; + bool enable_otg_frame_sync_pwa; + unsigned int min_deep_sleep_dcfclk_khz; }; @@ -1377,15 +1409,50 @@ struct lut_mem_mapping { struct dc_rmcm_3dlut { bool isInUse; const struct dc_stream_state *stream; - uint8_t protection_bits; }; struct dc_3dlut { struct kref refcount; struct tetrahedral_params lut_3d; - struct fixed31_32 hdr_multiplier; union dc_3dlut_state state; }; + +/* 3DLUT DMA (Fast Load) params */ +struct dc_3dlut_dma { + struct dc_plane_address addr; + enum dc_cm_lut_swizzle swizzle; + enum dc_cm_lut_pixel_format format; + uint16_t bias; /* FP1.5.10 */ + uint16_t scale; /* FP1.5.10 */ + enum dc_cm_lut_size size; +}; + +/* color manager */ +union dc_plane_cm_flags { + unsigned int all; + struct { + unsigned int shaper_enable : 1; + unsigned int lut3d_enable : 1; + unsigned int blend_enable : 1; + /* whether legacy (lut3d_func) or DMA is valid */ + unsigned int lut3d_dma_enable : 1; + /* RMCM lut to be used instead of MCM */ + unsigned int rmcm_enable : 1; + unsigned int reserved: 27; + } bits; +}; + +struct dc_plane_cm { + struct kref refcount; + struct dc_transfer_func shaper_func; + union { + struct dc_3dlut lut3d_func; + struct dc_3dlut_dma lut3d_dma; + }; + struct dc_transfer_func blend_func; + union dc_plane_cm_flags flags; +}; + /* * This structure is filled in by dc_surface_get_status and contains * the last requested address and the currently active address so the called @@ -1396,6 +1463,7 @@ struct dc_plane_status { struct dc_plane_address current_address; bool is_flip_pending; bool is_right_eye; + struct cm_hist cm_hist; }; union surface_update_flags { @@ -1432,6 +1500,7 @@ union surface_update_flags { uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ uint32_t full_update:1; uint32_t sdr_white_level_nits:1; + uint32_t cm_hist_change:1; } bits; uint32_t raw; @@ -1461,14 +1530,18 @@ struct dc_plane_state { struct fixed31_32 hdr_mult; struct colorspace_transform gamut_remap_matrix; - // TODO: No longer used, remove - struct dc_hdr_static_metadata hdr_static_ctx; - enum dc_color_space color_space; + bool lut_bank_a; + struct dc_hdr_static_metadata hdr_static_ctx; struct dc_3dlut lut3d_func; struct dc_transfer_func in_shaper_func; struct dc_transfer_func blend_tf; + enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; + bool mcm_lut1d_enable; + struct dc_cm2_func_luts mcm_luts; + enum mpcc_movable_cm_location mcm_location; + struct dc_plane_cm cm; struct dc_transfer_func *gamcor_tf; enum surface_pixel_format format; @@ -1505,17 +1578,13 @@ struct dc_plane_state { bool is_statically_allocated; enum chroma_cositing cositing; - enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; - bool mcm_lut1d_enable; - struct dc_cm2_func_luts mcm_luts; - bool lut_bank_a; - enum mpcc_movable_cm_location mcm_location; struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; int adaptive_sharpness_policy; int sharpness_level; enum linear_light_scaling linear_light_scaling; unsigned int sdr_white_level_nits; + struct cm_hist_control cm_hist_control; struct spl_sharpness_range sharpness_range; enum sharpness_range_source sharpness_source; }; @@ -1659,6 +1728,10 @@ struct dc_scratch_space { struct panel_cntl *panel_cntl; struct link_encoder *link_enc; struct graphics_object_id link_id; + + /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ + struct graphics_object_id ext_enc_id; + /* Endpoint type distinguishes display endpoints which do not have entries * in the BIOS connector table from those that do. Helps when tracking link * encoder to display endpoint assignments. @@ -1707,13 +1780,13 @@ struct dc_scratch_space { struct dc_link_status link_status; struct dprx_states dprx_states; - struct gpio *hpd_gpio; enum dc_link_fec_state fec_state; bool is_dds; bool is_display_mux_present; bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly struct dc_panel_config panel_config; + enum dc_panel_type panel_type; struct phy_state phy_state; uint32_t phy_transition_bitmask; // BW ALLOCATON USB4 ONLY @@ -1811,17 +1884,6 @@ struct dc_scaling_info { struct scaling_taps scaling_quality; }; -struct dc_fast_update { - const struct dc_flip_addrs *flip_addr; - const struct dc_gamma *gamma; - const struct colorspace_transform *gamut_remap_matrix; - const struct dc_csc_transform *input_csc_color_matrix; - const struct fixed31_32 *coeff_reduction_factor; - struct dc_transfer_func *out_transfer_func; - struct dc_csc_transform *output_csc_transform; - const struct dc_csc_transform *cursor_csc_color_matrix; -}; - struct dc_surface_update { struct dc_plane_state *surface; @@ -1849,9 +1911,11 @@ struct dc_surface_update { * change cm2_params.cm2_luts: Fast update */ const struct dc_cm2_parameters *cm2_params; + const struct dc_plane_cm *cm; const struct dc_csc_transform *cursor_csc_color_matrix; unsigned int sdr_white_level_nits; struct dc_bias_and_scale bias_and_scale; + struct cm_hist_control *cm_hist_control; }; struct dc_underflow_debug_data { @@ -1892,9 +1956,22 @@ struct dc_3dlut *dc_create_3dlut_func(void); void dc_3dlut_func_release(struct dc_3dlut *lut); void dc_3dlut_func_retain(struct dc_3dlut *lut); +struct dc_plane_cm *dc_plane_cm_create(void); +void dc_plane_cm_release(struct dc_plane_cm *cm); +void dc_plane_cm_retain(struct dc_plane_cm *cm); + void dc_post_update_surfaces_to_stream( struct dc *dc); +/* + * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling + * description for (typically) linear surfaces. + * + * This is used by OS/DM paths that need a valid, fully-initialized tiling + * description without hardcoding gfx-version specifics in the caller. + */ +void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); + /** * struct dc_validation_set - Struct to store surface/stream associations for validation */ @@ -1945,12 +2022,7 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); void get_audio_check(struct audio_info *aud_modes, struct audio_check *aud_chk); -bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); -void populate_fast_updates(struct dc_fast_update *fast_update, - struct dc_surface_update *srf_updates, - int surface_count, - struct dc_stream_update *stream_update); -/* + /* * Set up streams and links associated to drive sinks * The streams parameter is an absolute set of all active streams. * @@ -2455,6 +2527,48 @@ bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); +/* + * Enable or disable Panel Replay on the specified link: + * + * @link: pointer to the dc_link struct instance + * @enable: enable or disable Panel Replay + * + * return: true if successful, false otherwise + */ +bool dc_link_set_pr_enable(struct dc_link *link, bool enable); + +/* + * Update Panel Replay state parameters: + * + * @link: pointer to the dc_link struct instance + * @update_state_data: pointer to state update data structure + * + * return: true if successful, false otherwise + */ +bool dc_link_update_pr_state(struct dc_link *link, + struct dmub_cmd_pr_update_state_data *update_state_data); + +/* + * Send general command to Panel Replay firmware: + * + * @link: pointer to the dc_link struct instance + * @general_cmd_data: pointer to general command data structure + * + * return: true if successful, false otherwise + */ +bool dc_link_set_pr_general_cmd(struct dc_link *link, + struct dmub_cmd_pr_general_cmd_data *general_cmd_data); + +/* + * Get Panel Replay state: + * + * @link: pointer to the dc_link struct instance + * @state: pointer to store the Panel Replay state + * + * return: true if successful, false otherwise + */ +bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); + /* On eDP links this function call will stall until T12 has elapsed. * If the panel is not in power off state, this function will return * immediately. @@ -2793,7 +2907,7 @@ void dc_get_underflow_debug_data_for_otg(struct dc *dc, int primary_otg_inst, st void dc_get_power_feature_status(struct dc *dc, int primary_otg_inst, struct power_features *out_data); -/** +/* * Software state variables used to program register fields across the display pipeline */ struct dc_register_software_state { @@ -3280,4 +3394,28 @@ struct dc_register_software_state { */ bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); +/** + * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core + * @dc: DC context containing current display configuration + * @info: Pointer to dc_qos_info structure to populate with QoS metrics + * + * This function retrieves QoS metrics from the display core that can be used by + * benchmark tools to analyze display system performance. The function may take + * several milliseconds to execute due to hardware measurement requirements. + * + * QoS information includes: + * - Bandwidth bounds (lower limits in Mbps) + * - Latency bounds (upper limits in nanoseconds) + * - Hardware-measured bandwidth metrics (peak/average in Mbps) + * - Hardware-measured latency metrics (maximum/average in nanoseconds) + * + * The function will populate the provided dc_qos_info structure with current + * QoS measurements. If hardware measurement functions are not available for + * the current DCN version, the function returns false with zero'd info structure. + * + * Return: true if QoS information was successfully retrieved, false if measurement + * functions are unavailable or hardware measurements cannot be performed + */ +bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); + #endif /* DC_INTERFACE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h index 40d7a7d83c406..6f96c5cf39fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h @@ -97,11 +97,12 @@ struct dc_vbios_funcs { enum bp_result (*encoder_control)( struct dc_bios *bios, struct bp_encoder_control *cntl); + enum bp_result (*external_encoder_control)( + struct dc_bios *bios, + struct bp_external_encoder_control *cntl); enum bp_result (*dac_load_detection)( struct dc_bios *bios, - enum engine_id engine_id, - enum dal_device_type device_type, - uint32_t enum_id); + enum engine_id engine_id); enum bp_result (*transmitter_control)( struct dc_bios *bios, struct bp_transmitter_control *cntl); diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 7b09af1cb306e..d6a08064456b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -41,6 +41,8 @@ #define DC_LOGGER CTX->logger #define GPINT_RETRY_NUM 20 +#define MAX_WAIT_US 100000 + static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, struct dmub_srv *dmub) { @@ -48,6 +50,13 @@ static void dc_dmub_srv_construct(struct dc_dmub_srv *dc_srv, struct dc *dc, dc_srv->ctx = dc->ctx; } +static void dc_dmub_srv_handle_failure(struct dc_dmub_srv *dc_dmub_srv) +{ + dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + if (dc_dmub_srv->ctx->dc->debug.enable_dmu_recovery) + dm_helpers_dmu_timeout(dc_dmub_srv->ctx); +} + struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub) { struct dc_dmub_srv *dc_srv = @@ -84,12 +93,12 @@ bool dc_dmub_srv_wait_for_pending(struct dc_dmub_srv *dc_dmub_srv) dmub = dc_dmub_srv->dmub; do { - status = dmub_srv_wait_for_pending(dmub, 100000); + status = dmub_srv_wait_for_pending(dmub, MAX_WAIT_US); } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); if (status != DMUB_STATUS_OK) { DC_ERROR("Error waiting for DMUB idle: status=%d\n", status); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } return status == DMUB_STATUS_OK; @@ -104,7 +113,7 @@ void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) status = dmub_srv_clear_inbox0_ack(dmub); if (status != DMUB_STATUS_OK) { DC_ERROR("Error clearing INBOX0 ack: status=%d\n", status); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } } @@ -114,10 +123,10 @@ void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dc_dmub_srv) struct dc_context *dc_ctx = dc_dmub_srv->ctx; enum dmub_status status = DMUB_STATUS_OK; - status = dmub_srv_wait_for_inbox0_ack(dmub, 100000); + status = dmub_srv_wait_for_inbox0_ack(dmub, MAX_WAIT_US); if (status != DMUB_STATUS_OK) { DC_ERROR("Error waiting for INBOX0 HW Lock Ack\n"); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } } @@ -131,7 +140,7 @@ void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dc_dmub_srv, status = dmub_srv_send_inbox0_cmd(dmub, data); if (status != DMUB_STATUS_OK) { DC_ERROR("Error sending INBOX0 cmd\n"); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } } @@ -153,7 +162,7 @@ static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_s for (i = 0 ; i < count; i++) { /* confirm no messages pending */ do { - status = dmub_srv_wait_for_idle(dmub, 100000); + status = dmub_srv_wait_for_idle(dmub, MAX_WAIT_US); } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); /* queue command */ @@ -169,7 +178,7 @@ static bool dc_dmub_srv_reg_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_s if (status != DMUB_STATUS_OK) { if (status != DMUB_STATUS_POWER_STATE_D3) { DC_ERROR("Error starting DMUB execution: status=%d\n", status); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } return false; } @@ -208,7 +217,7 @@ static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_sr return false; do { - status = dmub_srv_wait_for_inbox_free(dmub, 100000, count - i); + status = dmub_srv_wait_for_inbox_free(dmub, MAX_WAIT_US, count - i); } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); /* Requeue the command. */ @@ -218,7 +227,7 @@ static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_sr if (status != DMUB_STATUS_OK) { if (status != DMUB_STATUS_POWER_STATE_D3) { DC_ERROR("Error queueing DMUB command: status=%d\n", status); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } return false; } @@ -228,7 +237,7 @@ static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_sr if (status != DMUB_STATUS_OK) { if (status != DMUB_STATUS_POWER_STATE_D3) { DC_ERROR("Error starting DMUB execution: status=%d\n", status); - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); } return false; } @@ -271,7 +280,7 @@ bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, // Wait for DMUB to process command if (wait_type != DM_DMUB_WAIT_TYPE_NO_WAIT) { do { - status = dmub_srv_wait_for_idle(dmub, 100000); + status = dmub_srv_wait_for_idle(dmub, MAX_WAIT_US); } while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status != DMUB_STATUS_OK); if (status != DMUB_STATUS_OK) { @@ -282,7 +291,7 @@ bool dc_dmub_srv_wait_for_idle(struct dc_dmub_srv *dc_dmub_srv, dmub->debug.timeout_info.timeout_cmd = *cmd_list; dmub->debug.timeout_info.timestamp = dm_get_timestamp(dc_dmub_srv->ctx); } - dc_dmub_srv_log_diagnostic_data(dc_dmub_srv); + dc_dmub_srv_handle_failure(dc_dmub_srv); return false; } @@ -999,6 +1008,7 @@ void dc_dmub_srv_log_diagnostic_data(struct dc_dmub_srv *dc_dmub_srv) DC_LOG_DEBUG(" is_traceport_en : %d", dc_dmub_srv->dmub->debug.is_traceport_en); DC_LOG_DEBUG(" is_cw0_en : %d", dc_dmub_srv->dmub->debug.is_cw0_enabled); DC_LOG_DEBUG(" is_cw6_en : %d", dc_dmub_srv->dmub->debug.is_cw6_enabled); + DC_LOG_DEBUG(" is_pwait : %d", dc_dmub_srv->dmub->debug.is_pwait); } static bool dc_dmub_should_update_cursor_data(struct pipe_ctx *pipe_ctx) @@ -1024,12 +1034,19 @@ static void dc_build_cursor_update_payload0( struct pipe_ctx *pipe_ctx, uint8_t p_idx, struct dmub_cmd_update_cursor_payload0 *payload) { + struct dc *dc = pipe_ctx->stream->ctx->dc; struct hubp *hubp = pipe_ctx->plane_res.hubp; unsigned int panel_inst = 0; - if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, - pipe_ctx->stream->link, &panel_inst)) - return; + if (dc->config.frame_update_cmd_version2 == true) { + /* Don't need panel_inst for command version2 */ + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2; + } else { + if (!dc_get_edp_link_panel_inst(hubp->ctx->dc, + pipe_ctx->stream->link, &panel_inst)) + return; + payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1; + } /* Payload: Cursor Rect is built from position & attribute * x & y are obtained from postion @@ -1042,8 +1059,8 @@ static void dc_build_cursor_update_payload0( payload->enable = hubp->pos.cur_ctl.bits.cur_enable; payload->pipe_idx = p_idx; - payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; payload->panel_inst = panel_inst; + payload->otg_inst = pipe_ctx->stream_res.tg->inst; } static void dc_build_cursor_position_update_payload0( @@ -1833,9 +1850,10 @@ static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc, /* apply feature configuration based on current driver state */ global_cmd->config.global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2; - global_cmd->config.global.features.bits.enable = enable; + global_cmd->config.global.features.bits.enable = enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; + global_cmd->config.global.features.bits.enable_ppt_check = dc->debug.fams2_config.bits.enable_ppt_check; - if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { + if (enable) { /* set multi pending for global, and unset for last stream cmd */ global_cmd->header.multi_cmd_pending = 1; cmd[2 * context->bw_ctx.bw.dcn.fams2_global_config.num_streams].fams2_config.header.multi_cmd_pending = 0; @@ -1862,16 +1880,16 @@ static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc, cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr; cmd.ib_fams2_config.ib_data.size = sizeof(*config); - if (enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable) { + if (enable) { + /* send global configuration parameters */ + memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config, + sizeof(struct dmub_cmd_fams2_global_config)); + /* copy static feature configuration overrides */ config->global.features.bits.enable_stall_recovery = dc->debug.fams2_config.bits.enable_stall_recovery; config->global.features.bits.enable_offload_flip = dc->debug.fams2_config.bits.enable_offload_flip; config->global.features.bits.enable_debug = dc->debug.fams2_config.bits.enable_debug; - /* send global configuration parameters */ - memcpy(&config->global, &context->bw_ctx.bw.dcn.fams2_global_config, - sizeof(struct dmub_cmd_fams2_global_config)); - /* construct per-stream configs */ for (i = 0; i < context->bw_ctx.bw.dcn.fams2_global_config.num_streams; i++) { /* copy stream static base state */ @@ -1887,7 +1905,8 @@ static void dc_dmub_srv_ib_based_fams2_update_config(struct dc *dc, } config->global.features.bits.enable_visual_confirm = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS2; - config->global.features.bits.enable = enable; + config->global.features.bits.enable = enable && context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; + config->global.features.bits.enable_ppt_check = dc->debug.fams2_config.bits.enable_ppt_check; dm_execute_dmub_cmd_list(dc->ctx, 1, &cmd, DM_DMUB_WAIT_TYPE_WAIT); } @@ -2330,6 +2349,33 @@ bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc) return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled; } +void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size) +{ + struct dc_dmub_srv *dc_dmub_srv; + struct dc_context *dc_ctx; + union dmub_rb_cmd cmd = {0}; + bool result = false; + + if (!dc || !dc->ctx || !dc->ctx->dmub_srv || size == 0) + return; + + dc_dmub_srv = dc->ctx->dmub_srv; + dc_ctx = dc_dmub_srv->ctx; + + memset(&cmd, 0, sizeof(cmd)); + cmd.boot_time_crc_init.header.type = DMUB_CMD__BOOT_TIME_CRC; + cmd.boot_time_crc_init.header.sub_type = DMUB_CMD__BOOT_TIME_CRC_INIT_MEM; + cmd.boot_time_crc_init.header.payload_bytes = + sizeof(struct dmub_rb_cmd_boot_time_crc_init); + cmd.boot_time_crc_init.data.buffer_addr.quad_part = gpu_addr; + cmd.boot_time_crc_init.data.buffer_size = size; + + result = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT); + + if (!result) + DC_ERROR("Boot time crc init failed in DMUB"); +} + void dc_dmub_srv_release_hw(const struct dc *dc) { struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 72e0a41f39f04..6579cf9cce3c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -361,6 +361,15 @@ void dc_dmub_srv_program_cursor_now(struct dc *dc, const struct pipe_ctx *pipe); */ bool dc_dmub_srv_is_cursor_offload_enabled(const struct dc *dc); +/** + * dc_dmub_srv_boot_time_crc_init() - Initializes DMUB boot time CRC. + * + * @dc - pointer to DC object + * @gpu_addr - address for the boot time CRC buffer + * @size - size of the boot time CRC buffer + */ +void dc_dmub_srv_boot_time_crc_init(const struct dc *dc, uint64_t gpu_addr, uint32_t size); + /** * dc_dmub_srv_release_hw() - Notifies DMUB service that HW access is no longer required. * diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 79e1696def630..7fa336bf1115d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -947,8 +947,8 @@ union dp_tun_cap_support { /* DPCD[0xE000E] DP_IN_ADAPTER_INFO register. */ union dpia_info { struct { - uint8_t dpia_num :5; - uint8_t rsvd :3; + uint8_t dpia_num :6; + uint8_t rsvd :2; } bits; uint8_t raw; }; @@ -1167,6 +1167,25 @@ union dpcd_panel_replay_capability_supported { unsigned char raw; }; +union dpcd_panel_replay_capability { + struct { + unsigned char RESERVED :2; + unsigned char DSC_DECODE_NOT_SUPPORTED :1; + unsigned char ASYNC_VIDEO_TIMING_NOT_SUPPORTED :1; + unsigned char DSC_CRC_OF_MULTI_SU_SUPPORTED :1; + unsigned char PR_SU_GRANULARITY_NEEDED :1; + unsigned char SU_Y_GRANULARITY_EXT_CAP_SUPPORTED :1; + unsigned char LINK_OFF_SUPPORTED_IN_PR_ACTIVE :1; + } bits; + unsigned char raw; +}; + +struct dpcd_panel_replay_selective_update_info { + uint16_t pr_su_x_granularity; + uint8_t pr_su_y_granularity; + uint16_t pr_su_y_granularity_extended_caps; +}; + enum dpcd_downstream_port_max_bpc { DOWN_STREAM_MAX_8BPC = 0, DOWN_STREAM_MAX_10BPC, @@ -1290,12 +1309,15 @@ struct dpcd_caps { struct edp_psr_info psr_info; struct replay_info pr_info; - union dpcd_panel_replay_capability_supported pr_caps_supported; + union dpcd_panel_replay_capability_supported vesa_replay_caps_supported; + union dpcd_panel_replay_capability vesa_replay_caps; + struct dpcd_panel_replay_selective_update_info vesa_replay_su_info; uint16_t edp_oled_emission_rate; union dp_receive_port0_cap receive_port0_cap; /* Indicates the number of SST links supported by MSO (Multi-Stream Output) */ uint8_t mso_cap_sst_links_supported; uint8_t dp_edp_general_cap_2; + uint16_t drr_granularity; }; union dpcd_sink_ext_caps { @@ -1352,7 +1374,7 @@ union dpcd_replay_configuration { unsigned char DESYNC_ERROR_STATUS : 1; unsigned char SINK_DEVICE_REPLAY_STATUS : 3; unsigned char SINK_FRAME_LOCKED : 2; - unsigned char RESERVED : 1; + unsigned char FRAME_SKIPPING_ERROR_STATUS : 1; } bits; unsigned char raw; }; @@ -1401,6 +1423,17 @@ union dpcd_sink_active_vtotal_control_mode { unsigned char raw; }; +union pr_error_status { + struct { + unsigned char LINK_CRC_ERROR :1; + unsigned char RFB_STORAGE_ERROR :1; + unsigned char VSC_SDP_ERROR :1; + unsigned char ASSDP_MISSING_ERROR :1; + unsigned char RESERVED :4; + } bits; + unsigned char raw; +}; + union psr_error_status { struct { unsigned char LINK_CRC_ERROR :1; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 9d18f1c080791..101bce6b8de64 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -52,6 +52,7 @@ struct dc_dsc_policy { uint32_t max_target_bpp; uint32_t min_target_bpp; bool enable_dsc_when_not_needed; + bool ycbcr422_simple; }; struct dc_dsc_config_options { diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index 5a365bd19933f..9e6ff518b6785 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -28,8 +28,6 @@ */ #include -#include - #include "dm_services.h" #include "dc.h" @@ -751,6 +749,8 @@ char *dce_version_to_string(const int version) return "DCN 3.6"; case DCN_VERSION_4_01: return "DCN 4.0.1"; + case DCN_VERSION_4_2: + return "DCN 4.2"; default: return "Unknown"; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 6678525172461..c2ca08d26e371 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -218,7 +218,7 @@ enum surface_pixel_format { /* Pixel format */ -enum pixel_format { +enum dc_pixel_format { /*graph*/ PIXEL_FORMAT_UNINITIALIZED, PIXEL_FORMAT_INDEX8, @@ -271,6 +271,15 @@ enum tile_split_values_new { DC_SURF_TILE_SPLIT_1KB = 0x4, }; +enum otg_pwa_sync_mode { + DC_OTG_PWA_FRAME_SYNC_MODE_VSYNC = 0x0, + DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP = 0x1, +}; +struct otc_pwa_frame_sync { + enum otg_pwa_sync_mode pwa_sync_mode; + uint32_t pwa_frame_sync_line_offset; +}; + /* TODO: These values come from hardware spec. We need to readdress this * if they ever change. */ @@ -436,6 +445,10 @@ enum dc_gfxversion { enum swizzle_mode_addr3_values swizzle; } gfx_addr3;/*gfx with addr3 and above*/ }; + + struct { + bool avoid_full_update_on_tiling_change; + } flags; }; /* Rotation angle */ @@ -491,6 +504,12 @@ struct dc_cursor_position { * for each plane. */ bool translate_by_source; + + /** + * @use_viewport_for_clip: Use viewport position for clip_x calculation + * instead of clip_rect. Required to protect against clip being overwritten + */ + bool use_viewport_for_clip; }; struct dc_cursor_mi_param { @@ -1131,6 +1150,7 @@ struct mcif_buf_params { unsigned int warmup_pitch; unsigned int swlock; unsigned int p_vmid; + uint8_t tmz_id; }; @@ -1156,5 +1176,68 @@ struct phy_state { enum symclk_state symclk_state; }; +enum cm_hist_tap_point { + CM_HIST_TAP_POINT_1, + CM_HIST_TAP_POINT_2, + CM_HIST_TAP_POINT_3, + CM_HIST_TAP_POINT_4, +}; + +enum cm_hist_src { + CM_HIST_SRC1, + CM_HIST_SRC2, + CM_HIST_SRC3, +}; + +enum cm_hist_format { + CM_HIST_FORMAT_FIXED_POINT, + CM_HIST_FORMAT_FP16_POS, + CM_HIST_FORMAT_FP16_POS_AND_NEG, +}; + +enum cm_hist_read_channel_mask { + CM_HIST_READ_DISABLED, + CM_HIST_READ_CH1, + CM_HIST_READ_CH2, + CM_HIST_READ_CH1_CH2, + CM_HIST_READ_CH3, + CM_HIST_READ_CH1_CH3, + CM_HIST_READ_CH2_CH3, + CM_HIST_READ_ALL, +}; + +enum cm_hist_src1_mode { + CM_HIST_SRC1_MODE_R_OR_CR, + CM_HIST_SRC1_MODE_MAX_RGB, +}; + +enum cm_hist_src2_mode { + CM_HIST_SRC2_MODE_G_OR_Y, + CM_HIST_SRC2_MODE_RGB_TO_Y, +}; + +enum cm_hist_src3_mode { + CM_HIST_SRC3_MODE_B_OR_CB, + CM_HIST_SRC3_MODE_MIN_RGB, +}; + +struct cm_hist_control { + enum cm_hist_tap_point tap_point; + uint32_t channels_enabled; + enum cm_hist_src1_mode src_1_select; + enum cm_hist_src2_mode src_2_select; + enum cm_hist_src3_mode src_3_select; + enum cm_hist_src ch1_src; + enum cm_hist_src ch2_src; + enum cm_hist_src ch3_src; + enum cm_hist_format format; + enum cm_hist_read_channel_mask read_channel_mask; +}; + +struct cm_hist { + uint32_t ch1[256]; + uint32_t ch2[256]; + uint32_t ch3[256]; +}; #endif /* DC_HW_TYPES_H */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/dc_plane.h index 14feb843e6940..2ad6d9318566e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_plane.h +++ b/drivers/gpu/drm/amd/display/dc/dc_plane.h @@ -31,6 +31,7 @@ union dc_plane_status_update_flags { struct { uint32_t address : 1; + uint32_t histogram : 1; } bits; uint32_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 37d1a79e8241e..52ed8deebf635 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -63,7 +63,8 @@ static void populate_inits_from_splinits(struct scl_inits *inits, inits->h_c = dc_fixpt_from_int_dy(spl_inits->h_filter_init_int_c, spl_inits->h_filter_init_frac_c >> 5, 0, 19); inits->v_c = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int_c, spl_inits->v_filter_init_frac_c >> 5, 0, 19); } -static void populate_splformat_from_format(enum spl_pixel_format *spl_pixel_format, const enum pixel_format pixel_format) +static void populate_splformat_from_format(enum spl_pixel_format *spl_pixel_format, + const enum dc_pixel_format pixel_format) { if (pixel_format < PIXEL_FORMAT_INVALID) *spl_pixel_format = (enum spl_pixel_format)pixel_format; @@ -89,6 +90,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->callbacks = dcn32_spl_callbacks; break; case DCN_VERSION_4_01: + case DCN_VERSION_4_2: spl_in->callbacks = dcn401_spl_callbacks; break; default: diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 321cfe92d799a..86394203cee79 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -183,6 +183,11 @@ struct luminance_data { int dm_max_decrease_from_nominal; }; +enum dc_drr_trigger_mode { + DRR_TRIGGER_ON_FLIP = 0, + DRR_TRIGGER_ON_FLIP_AND_CURSOR, +}; + struct dc_stream_state { // sink is deprecated, new code should not reference // this pointer @@ -315,6 +320,10 @@ struct dc_stream_state { struct luminance_data lumin_data; bool scaler_sharpener_update; bool sharpening_required; + + enum dc_drr_trigger_mode drr_trigger_mode; + + struct dc_update_scratch_space *update_scratch; }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 @@ -364,6 +373,8 @@ struct dc_stream_update { bool *hw_cursor_req; bool *scaler_sharpener_update; bool *sharpening_required; + + enum dc_drr_trigger_mode *drr_trigger_mode; }; bool dc_is_stream_unchanged( @@ -390,6 +401,33 @@ bool dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); +struct dc_update_scratch_space; + +size_t dc_update_scratch_space_size(void); + +struct dc_update_scratch_space *dc_update_planes_and_stream_init( + struct dc *dc, + struct dc_surface_update *surface_updates, + int surface_count, + struct dc_stream_state *dc_stream, + struct dc_stream_update *stream_update +); + +// Locked, false is failed +bool dc_update_planes_and_stream_prepare( + struct dc_update_scratch_space *scratch +); + +// Unlocked +void dc_update_planes_and_stream_execute( + const struct dc_update_scratch_space *scratch +); + +// Locked, true if call again +bool dc_update_planes_and_stream_cleanup( + struct dc_update_scratch_space *scratch +); + /* * Set up surface attributes and associate to a stream * The surfaces parameter is an absolute set of all surface active for the stream. @@ -555,7 +593,8 @@ bool dc_stream_configure_crc(struct dc *dc, bool enable, bool continuous, uint8_t idx, - bool reset); + bool reset, + enum crc_poly_mode crc_poly_mode); bool dc_stream_get_crc(struct dc *dc, struct dc_stream_state *stream, @@ -597,7 +636,7 @@ struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream); void dc_dmub_update_dirty_rect(struct dc *dc, int surface_count, struct dc_stream_state *stream, - struct dc_surface_update *srf_updates, + const struct dc_surface_update *srf_updates, struct dc_state *context); bool dc_stream_is_cursor_limit_pending(struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dc_trace.h b/drivers/gpu/drm/amd/display/dc/dc_trace.h index bbec308a3a5e2..b7a011646d533 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_trace.h +++ b/drivers/gpu/drm/amd/display/dc/dc_trace.h @@ -23,8 +23,8 @@ #include "amdgpu_dm_trace.h" -#define TRACE_DC_PIPE_STATE(pipe_ctx, index, max_pipes) \ - for (index = 0; index < max_pipes; ++index) { \ +#define TRACE_DC_PIPE_STATE(pipe_ctx, max_pipes) \ + for (int index = 0; index < max_pipes; ++index) { \ struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[index]; \ if (pipe_ctx->plane_state) \ trace_amdgpu_dm_dc_pipe_state(pipe_ctx->pipe_idx, pipe_ctx->plane_state, \ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index f46039f642034..fd8ec16603125 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -275,6 +275,7 @@ enum dc_timing_source { TIMING_SOURCE_CV, TIMING_SOURCE_TV, TIMING_SOURCE_HDMI_VIC, + TIMING_SOURCE_CEA_VIC, /* implicitly specified by display device, still safe but less important*/ TIMING_SOURCE_DEFAULT, @@ -354,7 +355,7 @@ enum dc_connection_type { dc_connection_single, dc_connection_mst_branch, dc_connection_sst_branch, - dc_connection_dac_load + dc_connection_analog_load }; struct dc_csc_adjustments { @@ -963,6 +964,13 @@ struct display_endpoint_id { enum display_endpoint_type ep_type; }; +enum dc_panel_type { + PANEL_TYPE_NONE = 0, // UNKONWN, not determined yet + PANEL_TYPE_LCD = 1, + PANEL_TYPE_OLED = 2, + PANEL_TYPE_MINILED = 3, +}; + enum backlight_control_type { BACKLIGHT_CONTROL_PWM = 0, BACKLIGHT_CONTROL_VESA_AUX = 1, @@ -1078,6 +1086,7 @@ enum replay_coasting_vtotal_type { PR_COASTING_TYPE_STATIC, PR_COASTING_TYPE_FULL_SCREEN_VIDEO, PR_COASTING_TYPE_TEST_HARNESS, + PR_COASTING_TYPE_VIDEO_CONFERENCING_V2, PR_COASTING_TYPE_NUM, }; @@ -1099,7 +1108,6 @@ enum replay_FW_Message_type { Replay_Set_Residency_Frameupdate_Timer, Replay_Set_Pseudo_VTotal, Replay_Disabled_Adaptive_Sync_SDP, - Replay_Set_Version, Replay_Set_General_Cmd, }; @@ -1134,6 +1142,19 @@ union replay_low_refresh_rate_enable_options { unsigned int raw; }; +union replay_optimization { + struct { + //BIT[0-1]: Replay Teams Optimization + unsigned int TEAMS_OPTIMIZATION_VER_1 :1; + unsigned int TEAMS_OPTIMIZATION_VER_2 :1; + //BIT[2]: Replay Live Capture with CVT + unsigned int LIVE_CAPTURE_WITH_CVT :1; + unsigned int RESERVED_3 :1; + } bits; + + unsigned int raw; +}; + struct replay_config { /* Replay version */ enum dc_replay_version replay_version; @@ -1171,6 +1192,14 @@ struct replay_config { enum dc_alpm_mode alpm_mode; /* Replay full screen only */ bool os_request_force_ffu; + /* Replay optimization */ + union replay_optimization replay_optimization; + /* Replay sub feature Frame Skipping is supported */ + bool frame_skip_supported; + /* Replay Received Frame Skipping Error HPD. */ + bool received_frame_skipping_error_hpd; + /* Live capture with CVT is activated */ + bool live_capture_with_cvt_activated; }; /* Replay feature flags*/ @@ -1207,6 +1236,8 @@ struct replay_settings { uint32_t replay_desync_error_fail_count; /* The frame skip number dal send to DMUB */ uint16_t frame_skip_number; + /* Current Panel Replay events */ + uint32_t replay_events; }; /* To split out "global" and "per-panel" config settings. @@ -1231,7 +1262,7 @@ struct dc_panel_config { unsigned int max_nonboost_brightness_millinits; unsigned int min_brightness_millinits; } nits_brightness; - /* PSR */ + /* PSR/Replay */ struct psr { bool disable_psr; bool disallow_psrsu; @@ -1241,6 +1272,8 @@ struct dc_panel_config { bool rc_allow_fullscreen_VPB; bool read_psrcap_again; unsigned int replay_enable_option; + bool enable_frame_skipping; + bool enable_teams_optimization; } psr; /* ABM */ struct varib { @@ -1257,6 +1290,27 @@ struct dc_panel_config { struct ilr { bool optimize_edp_link_rate; /* eDP ILR */ } ilr; + /* Adaptive VariBright*/ + struct adaptive_vb { + bool disable_adaptive_vb; + unsigned int default_abm_vb_levels; // default value = 0xDCAA6414 + unsigned int default_cacp_vb_levels; + unsigned int default_abm_vb_hdr_levels; // default value = 0xB4805A40 + unsigned int default_cacp_vb_hdr_levels; + unsigned int abm_scaling_factors; // default value = 0x23210012 + unsigned int cacp_scaling_factors; + unsigned int battery_life_configures; // default value = 0x0A141E + unsigned int abm_backlight_adaptive_pwl_1; // default value = 0x6A4F7244 + unsigned int abm_backlight_adaptive_pwl_2; // default value = 0x4C615659 + unsigned int abm_backlight_adaptive_pwl_3; // default value = 0x0064 + unsigned int cacp_backlight_adaptive_pwl_1; + unsigned int cacp_backlight_adaptive_pwl_2; + unsigned int cacp_backlight_adaptive_pwl_3; + } adaptive_vb; + /* Ramless Idle Opt*/ + struct rio { + bool disable_rio; + } rio; }; #define MAX_SINKS_PER_LINK 4 @@ -1298,6 +1352,7 @@ enum dc_cm2_gpu_mem_layout { enum dc_cm2_gpu_mem_pixel_component_order { DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA, + DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA }; enum dc_cm2_gpu_mem_format { @@ -1319,6 +1374,9 @@ struct dc_cm2_gpu_mem_format_parameters { enum dc_cm2_gpu_mem_size { DC_CM2_GPU_MEM_SIZE_171717, + DC_CM2_GPU_MEM_SIZE_333333, + DC_CM2_GPU_MEM_SIZE_454545, + DC_CM2_GPU_MEM_SIZE_656565, DC_CM2_GPU_MEM_SIZE_TRANSFORMED, }; @@ -1429,4 +1487,28 @@ struct dc_validation_dpia_set { uint32_t required_bw; }; +enum dc_cm_lut_swizzle { + CM_LUT_3D_SWIZZLE_LINEAR_RGB, + CM_LUT_3D_SWIZZLE_LINEAR_BGR, + CM_LUT_1D_PACKED_LINEAR +}; + +enum dc_cm_lut_pixel_format { + CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB, + CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB, + CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB, + CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB, + CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10, + CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10 +}; + +enum dc_cm_lut_size { + CM_LUT_SIZE_NONE, + CM_LUT_SIZE_999, + CM_LUT_SIZE_171717, + CM_LUT_SIZE_333333, + CM_LUT_SIZE_454545, + CM_LUT_SIZE_656565, +}; + #endif /* DC_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/Makefile b/drivers/gpu/drm/amd/display/dc/dccg/Makefile index 1d5cf0f8e79d6..bf7e71166b5ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dccg/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -100,4 +100,13 @@ DCCG_DCN401 = dcn401_dccg.o AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401) + +############################################################################### +# DCN42 +############################################################################### +DCCG_DCN42 = dcn42_dccg.o + +AMD_DAL_DCCG_DCN42 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn42/,$(DCCG_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c index 33d8bd91cb014..733b85d450d99 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c @@ -131,6 +131,54 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg) { + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* Hardcoded register values for DCN20 + * These are specific to 100Mhz refclk + * Different ASICs with different refclk may override this in their own init + */ + REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264); + REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0); + REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c); + + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); +} + +void dccg2_refclk_setup(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* REFCLK programming that must occur after hubbub initialization */ + if (REG(REFCLK_CNTL)) + REG_WRITE(REFCLK_CNTL, 0); +} + +bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464; +} + +void dccg2_allow_clock_gating(struct dccg *dccg, bool allow) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (allow) { + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + } else { + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF); + REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); + } +} + +void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1); } static const struct dccg_funcs dccg2_funcs = { @@ -139,7 +187,11 @@ static const struct dccg_funcs dccg2_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg2_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 8bdffd9ff31b1..088cf305a772c 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 Advanced Micro Devices, Inc. + * Copyright 2018-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,7 +37,12 @@ SR(REFCLK_CNTL),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\ - SR(DISPCLK_FREQ_CHANGE_CNTL) + SR(DISPCLK_FREQ_CHANGE_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV),\ + SR(MILLISECOND_TIME_BASE_DIV),\ + SR(DCCG_GATE_DISABLE_CNTL),\ + SR(DCCG_GATE_DISABLE_CNTL2) #define DCCG_REG_LIST_DCN2() \ DCCG_COMMON_REG_LIST_DCN_BASE(),\ @@ -81,7 +86,8 @@ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ - DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) + DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\ + DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) @@ -130,7 +136,8 @@ type DISPCLK_CHG_FWD_CORR_DISABLE;\ type DISPCLK_FREQ_CHANGE_CNTL;\ type OTG_ADD_PIXEL[MAX_PIPES];\ - type OTG_DROP_PIXEL[MAX_PIPES]; + type OTG_DROP_PIXEL[MAX_PIPES];\ + type DC_MEM_GLOBAL_PWR_REQ_DIS; #define DCCG3_REG_FIELD_LIST(type) \ type HDMICHARCLK0_EN;\ @@ -359,6 +366,17 @@ type SYMCLK32_LE3_EN;\ type DP_DTO_ENABLE[MAX_PIPES]; +#define DCCG42_REG_FIELD_LIST(type) \ + type OTG0_ADD_PIXEL;\ + type OTG1_ADD_PIXEL;\ + type OTG2_ADD_PIXEL;\ + type OTG0_DROP_PIXEL;\ + type OTG1_DROP_PIXEL;\ + type OTG2_DROP_PIXEL;\ + type OTG3_ADD_PIXEL;\ + type OTG3_DROP_PIXEL;\ + type RESYNC_FIFO_LEVEL_ADJUST_EN; + struct dccg_shift { DCCG_REG_FIELD_LIST(uint8_t) DCCG3_REG_FIELD_LIST(uint8_t) @@ -367,6 +385,7 @@ struct dccg_shift { DCCG32_REG_FIELD_LIST(uint8_t) DCCG35_REG_FIELD_LIST(uint8_t) DCCG401_REG_FIELD_LIST(uint8_t) + DCCG42_REG_FIELD_LIST(uint8_t) }; struct dccg_mask { @@ -377,6 +396,7 @@ struct dccg_mask { DCCG32_REG_FIELD_LIST(uint32_t) DCCG35_REG_FIELD_LIST(uint32_t) DCCG401_REG_FIELD_LIST(uint32_t) + DCCG42_REG_FIELD_LIST(uint32_t) }; #define DCCG_REG_VARIABLE_LIST \ @@ -490,6 +510,7 @@ struct dccg_mask { struct dccg_registers { DCCG_REG_VARIABLE_LIST; + uint32_t OTG_ADD_DROP_PIXEL_CNTL; }; struct dcn_dccg { @@ -515,6 +536,11 @@ void dccg2_otg_drop_pixel(struct dccg *dccg, void dccg2_init(struct dccg *dccg); +void dccg2_refclk_setup(struct dccg *dccg); +void dccg2_allow_clock_gating(struct dccg *dccg, bool allow); +void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable); +bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg); + struct dccg *dccg2_create( struct dc_context *ctx, const struct dccg_registers *regs, diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c index 9a3402148fde0..79d14ce19393a 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c @@ -24,6 +24,7 @@ */ #include "dcn201_dccg.h" +#include "dcn20/dcn20_dccg.h" #include "reg_helper.h" #include "core_types.h" @@ -56,7 +57,11 @@ static const struct dccg_funcs dccg201_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg201_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c index d07c04458d31a..bdc3ce5d4f473 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c @@ -96,6 +96,25 @@ static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppcl dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; } +/* + * On DCN21 S0i3 resume, BIOS programs MICROSECOND_TIME_BASE_DIV to + * 0x00120464 as a marker that golden init has already been done. + * dcn21_s0i3_golden_init_wa() reads this marker later in bios_golden_init() + * to decide whether to skip golden init. + * + * dccg2_init() unconditionally overwrites MICROSECOND_TIME_BASE_DIV to + * 0x00120264, destroying the marker before it can be read. + * + * Guard the call: if the S0i3 marker is present, skip dccg2_init() so the + * WA can function correctly. bios_golden_init() will handle init in that case. + */ +static void dccg21_init(struct dccg *dccg) +{ + if (dccg2_is_s0i3_golden_init_wa_done(dccg)) + return; + + dccg2_init(dccg); +} static const struct dccg_funcs dccg21_funcs = { .update_dpp_dto = dccg21_update_dpp_dto, @@ -103,7 +122,11 @@ static const struct dccg_funcs dccg21_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg21_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg21_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c index d445dfefc047a..adec7c3c2d494 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c @@ -49,7 +49,11 @@ static const struct dccg_funcs dccg3_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg3_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c index 97e9be87afd9e..fc9bddd94b508 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c @@ -48,7 +48,11 @@ static const struct dccg_funcs dccg301_funcs = { .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, .otg_add_pixel = dccg2_otg_add_pixel, .otg_drop_pixel = dccg2_otg_drop_pixel, - .dccg_init = dccg2_init + .dccg_init = dccg2_init, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg301_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h index 067e49cb238ec..e2381ca0be0b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.h @@ -34,7 +34,13 @@ DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ DCCG_SRII(DTO_PARAM, DPPCLK, 2),\ DCCG_SRII(DTO_PARAM, DPPCLK, 3),\ - SR(REFCLK_CNTL) + SR(REFCLK_CNTL),\ + SR(DISPCLK_FREQ_CHANGE_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV),\ + SR(MILLISECOND_TIME_BASE_DIV),\ + SR(DCCG_GATE_DISABLE_CNTL),\ + SR(DCCG_GATE_DISABLE_CNTL2) #define DCCG_MASK_SH_LIST_DCN301(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c index 97df04b7e39d1..c647dff5234a0 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c @@ -26,6 +26,7 @@ #include "reg_helper.h" #include "core_types.h" #include "dcn31_dccg.h" +#include "dcn20/dcn20_dccg.h" #include "dal_asic_id.h" #define TO_DCN_DCCG(dccg)\ @@ -850,6 +851,10 @@ static const struct dccg_funcs dccg31_funcs = { .disable_dsc = dccg31_disable_dscclk, .enable_dsc = dccg31_enable_dscclk, .dccg_read_reg_state = dccg31_read_reg_state, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg31_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h index bf659920d4cc2..b5e3849ef12a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h @@ -64,9 +64,12 @@ SR(DSCCLK1_DTO_PARAM),\ SR(DSCCLK2_DTO_PARAM),\ SR(DSCCLK_DTO_CTRL),\ + SR(DCCG_GATE_DISABLE_CNTL),\ SR(DCCG_GATE_DISABLE_CNTL2),\ SR(DCCG_GATE_DISABLE_CNTL3),\ - SR(HDMISTREAMCLK0_DTO_PARAM) + SR(HDMISTREAMCLK0_DTO_PARAM),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV) #define DCCG_MASK_SH_LIST_DCN31(mask_sh) \ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c index ef3db6beba25c..2e9c4b13988a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c @@ -29,6 +29,7 @@ #include "dcn31/dcn31_dccg.h" #include "dcn314_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -378,7 +379,11 @@ static const struct dccg_funcs dccg314_funcs = { .trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync, .set_valid_pixel_rate = dccg314_set_valid_pixel_rate, .set_dtbclk_p_src = dccg314_set_dtbclk_p_src, - .dccg_read_reg_state = dccg31_read_reg_state + .dccg_read_reg_state = dccg31_read_reg_state, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg314_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h index a609635f35dbd..ecbdc05f7c459 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h @@ -70,11 +70,14 @@ SR(DSCCLK2_DTO_PARAM),\ SR(DSCCLK3_DTO_PARAM),\ SR(DSCCLK_DTO_CTRL),\ + SR(DCCG_GATE_DISABLE_CNTL),\ SR(DCCG_GATE_DISABLE_CNTL2),\ SR(DCCG_GATE_DISABLE_CNTL3),\ SR(HDMISTREAMCLK0_DTO_PARAM),\ SR(OTG_PIXEL_RATE_DIV),\ - SR(DTBCLK_P_CNTL) + SR(DTBCLK_P_CNTL),\ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL),\ + SR(MICROSECOND_TIME_BASE_DIV) #define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \ DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c index 21a6ca5ca1927..ce697c3249fbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c @@ -26,6 +26,7 @@ #include "reg_helper.h" #include "core_types.h" #include "dcn32_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -347,6 +348,10 @@ static const struct dccg_funcs dccg32_funcs = { .get_pixel_rate_div = dccg32_get_pixel_rate_div, .trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync, .set_dtbclk_p_src = dccg32_set_dtbclk_p_src, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; struct dccg *dccg32_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index bd2f528137b20..943ec19830764 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -26,6 +26,7 @@ #include "core_types.h" #include "resource.h" #include "dcn35_dccg.h" +#include "dcn20/dcn20_dccg.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -1105,7 +1106,7 @@ static void dccg35_enable_dpstreamclk_new(struct dccg *dccg, dccg35_set_dpstreamclk_src_new(dccg, src, inst); } -static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) +void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); uint32_t dispclk_rdivider_value = 0; @@ -1114,6 +1115,7 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) if (dispclk_rdivider_value != 0) REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); } + static void dccg35_wait_for_dentist_change_done( struct dccg *dccg) { @@ -1151,8 +1153,7 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg, } -static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, - int req_dppclk) +void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1498,11 +1499,7 @@ static void dccg35_set_dpstreamclk( __func__, dp_hpo_inst, (src == REFCLK) ? 0 : 1, otg_inst); } - -static void dccg35_set_dpstreamclk_root_clock_gating( - struct dccg *dccg, - int dp_hpo_inst, - bool enable) +void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1669,10 +1666,7 @@ static void dccg35_set_valid_pixel_rate( dccg35_set_dtbclk_dto(dccg, &dto_params); } -static void dccg35_dpp_root_clock_control( - struct dccg *dccg, - unsigned int dpp_inst, - bool clock_on) +void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1704,9 +1698,7 @@ static void dccg35_dpp_root_clock_control( DC_LOG_DEBUG("%s: dpp_inst(%d) clock_on = %d\n", __func__, dpp_inst, clock_on); } -static void dccg35_disable_symclk32_se( - struct dccg *dccg, - int hpo_se_inst) +void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1813,7 +1805,7 @@ void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value) REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); } -static void dccg35_enable_dscclk(struct dccg *dccg, int inst) +void dccg35_enable_dscclk(struct dccg *dccg, int inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1860,8 +1852,7 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst) udelay(10); } -static void dccg35_disable_dscclk(struct dccg *dccg, - int inst) +void dccg35_disable_dscclk(struct dccg *dccg, int inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -1906,7 +1897,7 @@ static void dccg35_disable_dscclk(struct dccg *dccg, udelay(10); } -static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) +void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -2013,7 +2004,7 @@ static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg * return num_enabled_symclk_fe; } -static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) +void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) { uint8_t num_enabled_symclk_fe = 0; struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); @@ -2421,6 +2412,10 @@ static const struct dccg_funcs dccg35_funcs_new = { .enable_symclk_se = dccg35_enable_symclk_se_cb, .disable_symclk_se = dccg35_disable_symclk_se_cb, .set_dtbclk_p_src = dccg35_set_dtbclk_p_src_cb, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */ }; static const struct dccg_funcs dccg35_funcs = { @@ -2452,8 +2447,12 @@ static const struct dccg_funcs dccg35_funcs = { .enable_symclk_se = dccg35_enable_symclk_se, .disable_symclk_se = dccg35_disable_symclk_se, .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, + .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */ + .allow_clock_gating = dccg2_allow_clock_gating, + .enable_memory_low_power = dccg2_enable_memory_low_power, + .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done, /* Deprecated - for backward compatibility only */ .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, - .dccg_read_reg_state = dccg31_read_reg_state, + .dccg_read_reg_state = dccg31_read_reg_state }; struct dccg *dccg35_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h index 7b9c36456cd9b..554700287c1ab 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h @@ -249,8 +249,25 @@ struct dccg *dccg35_create( void dccg35_init(struct dccg *dccg); +void dccg35_trigger_dio_fifo_resync(struct dccg *dccg); + +void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk); + void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value); void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); +void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst, bool enable); + +void dccg35_set_hdmistreamclk_root_clock_gating(struct dccg *dccg, bool enable); + +void dccg35_dpp_root_clock_control(struct dccg *dccg, unsigned int dpp_inst, bool clock_on); + +void dccg35_disable_symclk32_se(struct dccg *dccg, int hpo_se_inst); + +void dccg35_enable_dscclk(struct dccg *dccg, int inst); +void dccg35_disable_dscclk(struct dccg *dccg, int inst); + +void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); +void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst); #endif //__DCN35_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 663a18ee51628..0cdf93c614b77 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -27,6 +27,7 @@ #include "core_types.h" #include "dcn401_dccg.h" #include "dcn31/dcn31_dccg.h" +#include "dcn20/dcn20_dccg.h" /* #include "dmub_common.h" @@ -595,16 +596,6 @@ void dccg401_set_dp_dto( bool enable = false; - if (params->otg_inst > 3) { - /* dcn401 only has 4 instances */ - BREAK_TO_DEBUGGER(); - return; - } - if (!params->refclk_hz) { - BREAK_TO_DEBUGGER(); - return; - } - if (!dc_is_tmds_signal(params->signal)) { uint64_t dto_integer; uint64_t dto_phase_hz; @@ -612,6 +603,11 @@ void dccg401_set_dp_dto( enable = true; + if (!params->refclk_hz) { + BREAK_TO_DEBUGGER(); + return; + } + /* Set DTO values: * int = target_pix_rate / reference_clock * phase = target_pix_rate - int * reference_clock, @@ -831,6 +827,16 @@ void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint3 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, 1); break; + case 4: + if (dccg_dcn->dccg_mask->SYMCLKE_FE_ROOT_GATE_DISABLE) { + REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE, + SYMCLKE_FE_EN, 1, + SYMCLKE_FE_SRC_SEL, link_enc_inst); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 1); + } + break; + default: + return; } } @@ -859,6 +865,16 @@ void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint SYMCLKD_FE_EN, 0, SYMCLKD_FE_SRC_SEL, 0); break; + case 4: + if (dccg_dcn->dccg_mask->SYMCLKE_FE_ROOT_GATE_DISABLE) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, 0); + REG_UPDATE_2(SYMCLKE_CLOCK_ENABLE, + SYMCLKE_FE_EN, 0, + SYMCLKE_FE_SRC_SEL, 0); + } + break; + default: + return; } } @@ -866,6 +882,7 @@ static const struct dccg_funcs dccg401_funcs = { .update_dpp_dto = dccg401_update_dpp_dto, .get_dccg_ref_freq = dccg401_get_dccg_ref_freq, .dccg_init = dccg401_init, + .allow_clock_gating = dccg2_allow_clock_gating, .set_dpstreamclk = dccg401_set_dpstreamclk, .enable_symclk32_se = dccg31_enable_symclk32_se, .disable_symclk32_se = dccg31_disable_symclk32_se, diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c new file mode 100644 index 0000000000000..19dfc3fe5c3a4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn35/dcn35_dccg.h" +#include "dcn42_dccg.h" + +#define TO_DCN_DCCG(dccg)\ + container_of(dccg, struct dcn_dccg, base) + +#define REG(reg) \ + (dccg_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name + +#define CTX \ + dccg_dcn->base.ctx +#define DC_LOGGER \ + dccg->ctx->logger + +void dccg42_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (otg_inst) { + case 0: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG0_ADD_PIXEL, 1); + break; + case 1: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG1_ADD_PIXEL, 1); + break; + case 2: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG2_ADD_PIXEL, 1); + break; + case 3: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG3_ADD_PIXEL, 1); + break; + default: + ASSERT(0); + } +} + +void dccg42_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (otg_inst) { + case 0: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG0_DROP_PIXEL, 1); + break; + case 1: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG1_DROP_PIXEL, 1); + break; + case 2: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG2_DROP_PIXEL, 1); + break; + case 3: + REG_UPDATE(OTG_ADD_DROP_PIXEL_CNTL, + OTG3_DROP_PIXEL, 1); + break; + default: + ASSERT(0); + } +} + +void dccg42_enable_global_fgcg(struct dccg *dccg, bool value) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + if (dccg->ctx->dc->debug.disable_clock_gate) + value = false; + REG_UPDATE(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, !value); +} + +void dccg42_set_physymclk( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + switch (phy_inst) { + case 0: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYASYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, + PHYASYMCLK_EN, 1, + PHYASYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYASYMCLK_CLOCK_CNTL, + PHYASYMCLK_EN, 0, + PHYASYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYASYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 1: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYBSYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, + PHYBSYMCLK_EN, 1, + PHYBSYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYBSYMCLK_CLOCK_CNTL, + PHYBSYMCLK_EN, 0, + PHYBSYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYBSYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 2: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYCSYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, + PHYCSYMCLK_EN, 1, + PHYCSYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYCSYMCLK_CLOCK_CNTL, + PHYCSYMCLK_EN, 0, + PHYCSYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYCSYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 3: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYDSYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, + PHYDSYMCLK_EN, 1, + PHYDSYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYDSYMCLK_CLOCK_CNTL, + PHYDSYMCLK_EN, 0, + PHYDSYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYDSYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + case 4: + if (force_enable) { + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYESYMCLK_ROOT_GATE_DISABLE, 1); + REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, + PHYESYMCLK_EN, 1, + PHYESYMCLK_SRC_SEL, clk_src); + } else { + REG_UPDATE_2(PHYESYMCLK_CLOCK_CNTL, + PHYESYMCLK_EN, 0, + PHYESYMCLK_SRC_SEL, 0); + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + PHYESYMCLK_ROOT_GATE_DISABLE, + dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk ? 0 : 1); + } + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +void dccg42_set_pixel_rate_div( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div tmds_div, + enum pixel_rate_div unused) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + uint32_t cur_tmds_div = PIXEL_RATE_DIV_NA; + uint32_t dp_dto_int; + uint32_t reg_val; + + // only 2 and 4 are valid on dcn401 + if (tmds_div != PIXEL_RATE_DIV_BY_2 && tmds_div != PIXEL_RATE_DIV_BY_4) { + return; + } + + dccg401_get_pixel_rate_div(dccg, otg_inst, &cur_tmds_div, &dp_dto_int); + if (tmds_div == cur_tmds_div) + return; + + // encode enum to register value + reg_val = tmds_div == PIXEL_RATE_DIV_BY_4 ? 1 : 0; + + switch (otg_inst) { + case 0: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG0_TMDS_PIXEL_RATE_DIV, reg_val); + break; + case 1: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG1_TMDS_PIXEL_RATE_DIV, reg_val); + break; + case 2: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG2_TMDS_PIXEL_RATE_DIV, reg_val); + break; + case 3: + REG_UPDATE(OTG_PIXEL_RATE_DIV, + OTG3_TMDS_PIXEL_RATE_DIV, reg_val); + break; + default: + BREAK_TO_DEBUGGER(); + return; + } +} + +void dccg42_trigger_dio_fifo_resync(struct dccg *dccg) +{ + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, RESYNC_FIFO_LEVEL_ADJUST_EN, 1); + REG_UPDATE(DISPCLK_FREQ_CHANGE_CNTL, RESYNC_FIFO_LEVEL_ADJUST_EN, 0); + REG_WAIT(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, 1, 50, 2000); +} + +static void dccg42_init(struct dccg *dccg) +{ + int otg_inst; + struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + + /* Set HPO stream encoder to use refclk to avoid case where PHY is + * disabled and SYMCLK32 for HPO SE is sourced from PHYD32CLK which + * will cause DCN to hang. + */ + for (otg_inst = 0; otg_inst < 4; otg_inst++) + dccg35_disable_symclk32_se(dccg, otg_inst); + + if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) { + dccg401_disable_symclk32_le(dccg, 0); + dccg401_disable_symclk32_le(dccg, 1); + dccg401_disable_symclk32_le(dccg, 2); + dccg401_disable_symclk32_le(dccg, 3); + } + + if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) { + dccg401_disable_dpstreamclk(dccg, 0); + dccg401_disable_dpstreamclk(dccg, 1); + dccg401_disable_dpstreamclk(dccg, 2); + dccg401_disable_dpstreamclk(dccg, 3); + } + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) { + REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, + PHYASYMCLK_ROOT_GATE_DISABLE, 1, + PHYBSYMCLK_ROOT_GATE_DISABLE, 1, + PHYCSYMCLK_ROOT_GATE_DISABLE, 1, + PHYDSYMCLK_ROOT_GATE_DISABLE, 1, + PHYESYMCLK_ROOT_GATE_DISABLE, 1); + } +} + + +static const struct dccg_funcs dccg42_funcs = { + .update_dpp_dto = dccg35_update_dpp_dto, + .dpp_root_clock_control = dccg35_dpp_root_clock_control, + .get_dccg_ref_freq = dccg401_get_dccg_ref_freq, + .dccg_init = dccg42_init, + .set_dpstreamclk = dccg401_set_dpstreamclk, + /* Redundant with above^ */ + /* .set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating, */ + .enable_symclk32_se = dccg31_enable_symclk32_se, + .disable_symclk32_se = dccg35_disable_symclk32_se, + .enable_symclk32_le = dccg401_enable_symclk32_le, + .disable_symclk32_le = dccg401_disable_symclk32_le, + .set_symclk32_le_root_clock_gating = dccg31_set_symclk32_le_root_clock_gating, + .set_physymclk = dccg42_set_physymclk, + .set_dtbclk_dto = NULL, + .set_dto_dscclk = dccg401_set_dto_dscclk, + .set_ref_dscclk = dccg401_set_ref_dscclk, + .set_valid_pixel_rate = NULL, + .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en, + .set_audio_dtbclk_dto = NULL, + .otg_add_pixel = dccg42_otg_add_pixel, + .otg_drop_pixel = dccg42_otg_drop_pixel, + .disable_dsc = dccg35_disable_dscclk, + .enable_dsc = dccg35_enable_dscclk, + .set_pixel_rate_div = dccg42_set_pixel_rate_div, + .get_pixel_rate_div = dccg401_get_pixel_rate_div, + .trigger_dio_fifo_resync = dccg42_trigger_dio_fifo_resync, + .set_dp_dto = dccg401_set_dp_dto, + .enable_symclk_se = dccg35_enable_symclk_se, + .disable_symclk_se = dccg35_disable_symclk_se, + .set_dtbclk_p_src = dccg401_set_dtbclk_p_src, + .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, + .dccg_read_reg_state = dccg31_read_reg_state, + .dccg_enable_global_fgcg = dccg42_enable_global_fgcg, +}; + +struct dccg *dccg42_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask) +{ + struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL); + struct dccg *base; + + if (dccg_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &dccg_dcn->base; + base->ctx = ctx; + base->funcs = &dccg42_funcs; + + dccg_dcn->regs = regs; + dccg_dcn->dccg_shift = dccg_shift; + dccg_dcn->dccg_mask = dccg_mask; + + return &dccg_dcn->base; +} diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h new file mode 100644 index 0000000000000..2076565b1caab --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.h @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024-2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DCN42_DCCG_H__ +#define __DCN42_DCCG_H__ + +#include "dcn401/dcn401_dccg.h" + +#define DCCG_MASK_SH_LIST_DCN42_COMMON(mask_sh) \ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\ + DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK0_EN, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK1_EN, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK2_EN, mask_sh),\ + DCCG_SF(DPPCLK_CTRL, DPPCLK3_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ + DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_EN, mask_sh),\ + DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_EN, mask_sh),\ + DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_EN, mask_sh),\ + DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_EN, mask_sh),\ + DCCG_SF(PHYDSYMCLK_CLOCK_CNTL, PHYDSYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_EN, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK1_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK2_SRC_SEL, mask_sh),\ + DCCG_SF(DPSTREAMCLK_CNTL, DPSTREAMCLK3_SRC_SEL, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_EN, mask_sh),\ + DCCG_SF(HDMISTREAMCLK_CNTL, HDMISTREAMCLK0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE1_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE2_EN, mask_sh),\ + DCCG_SF(SYMCLK32_SE_CNTL, SYMCLK32_SE3_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE2_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE3_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE0_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE1_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE2_EN, mask_sh),\ + DCCG_SF(SYMCLK32_LE_CNTL, SYMCLK32_LE3_EN, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG0_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG1_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG2_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG3_ADD_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG0_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG1_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG2_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_ADD_DROP_PIXEL_CNTL, OTG3_DROP_PIXEL, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG0_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO0_INT, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG1_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO1_INT, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG2_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO2_INT, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, OTG3_TMDS_PIXEL_RATE_DIV, mask_sh),\ + DCCG_SF(OTG_PIXEL_RATE_DIV, DPDTO3_INT, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P0_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P1_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P2_EN, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\ + DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ + DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ + DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_MODE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GLOBAL_FGCG_REP_CNTL, DCCG_GLOBAL_FGCG_REP_DIS, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 0, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 1, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 2, mask_sh),\ + DCCG_SFII(OTG, PIXEL_RATE_CNTL, PIPE, DTO_SRC_SEL, 3, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK0_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK1_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK2_EN, mask_sh),\ + DCCG_SF(DSCCLK_DTO_CTRL, DSCCLK3_EN, mask_sh),\ + DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK0_DTO_PARAM, DSCCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK1_DTO_PARAM, DSCCLK1_DTO_MODULO, mask_sh),\ + DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK2_DTO_PARAM, DSCCLK2_DTO_MODULO, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL, DISPCLK_DCCG_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, HDMISTREAMCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_SE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_LE3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, HDMICHARCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYA_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYB_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYC_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYD_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK1_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK2_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK1_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK2_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DPPCLK3_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, HDMISTREAMCLK0_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh) + +#define DCCG_MASK_SH_LIST_DCN42(mask_sh) \ + DCCG_MASK_SH_LIST_DCN42_COMMON(mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_EN, mask_sh),\ + DCCG_SF(PHYESYMCLK_CLOCK_CNTL, PHYESYMCLK_SRC_SEL, mask_sh),\ + DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\ + DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_PHASE, mask_sh),\ + DCCG_SF(DSCCLK3_DTO_PARAM, DSCCLK3_DTO_MODULO, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL4, PHYE_REFCLK_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_FE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(DCCG_GATE_DISABLE_CNTL6, DSCCLK3_ROOT_GATE_DISABLE, mask_sh),\ + DCCG_SF(SYMCLKA_CLOCK_ENABLE, SYMCLKA_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_SRC_SEL, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, mask_sh),\ + DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\ + DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, RESYNC_FIFO_LEVEL_ADJUST_EN, mask_sh) + + +void dccg42_otg_add_pixel(struct dccg *dccg, + uint32_t otg_inst); + +void dccg42_otg_drop_pixel(struct dccg *dccg, + uint32_t otg_inst); +void dccg42_enable_global_fgcg(struct dccg *dccg, bool value); + +void dccg42_set_physymclk( + struct dccg *dccg, + int phy_inst, + enum physymclk_clock_source clk_src, + bool force_enable); + +void dccg42_set_pixel_rate_div( + struct dccg *dccg, + uint32_t otg_inst, + enum pixel_rate_div tmds_div, + enum pixel_rate_div unused); + +void dccg42_trigger_dio_fifo_resync(struct dccg *dccg); + +struct dccg *dccg42_create( + struct dc_context *ctx, + const struct dccg_registers *regs, + const struct dccg_shift *dccg_shift, + const struct dccg_mask *dccg_mask); + +#endif //__DCN42_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 3d819fc5654cd..1e9ab5ff3a31e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-16 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -300,6 +300,64 @@ ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \ ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh) +#define ABM_MASK_SH_LIST_DCN42(mask_sh) \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \ + ABM1_ACE_SLOPE_DATA, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \ + ABM1_ACE_OFFSET_DATA, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \ + ABM1_ACE_LOCK, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \ + ABM1_HG_RESULT_DATA, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \ + ABM1_HG_RESULT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \ + ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \ + ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \ + ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \ + ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \ + ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh) + #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ type ABM1_HG_VMAX_SEL; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index fcad61c618a1a..1276f19164b38 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -1150,98 +1150,6 @@ void dce_aud_wall_dto_setup( } } -#if defined(CONFIG_DRM_AMD_DC_SI) -static void dce60_aud_wall_dto_setup( - struct audio *audio, - enum signal_type signal, - const struct audio_crtc_info *crtc_info, - const struct audio_pll_info *pll_info) -{ - struct dce_audio *aud = DCE_AUD(audio); - - struct azalia_clock_info clock_info = { 0 }; - - if (dc_is_hdmi_signal(signal)) { - uint32_t src_sel; - - /*DTO0 Programming goal: - -generate 24MHz, 128*Fs from 24MHz - -use DTO0 when an active HDMI port is connected - (optionally a DP is connected) */ - - /* calculate DTO settings */ - get_azalia_clock_info_hdmi( - crtc_info->requested_pixel_clock_100Hz, - crtc_info->calculated_pixel_clock_100Hz, - &clock_info); - - DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ - "calculated_pixel_clock_100Hz =%d\n"\ - "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ - crtc_info->requested_pixel_clock_100Hz,\ - crtc_info->calculated_pixel_clock_100Hz,\ - clock_info.audio_dto_module,\ - clock_info.audio_dto_phase); - - /* On TN/SI, Program DTO source select and DTO select before - programming DTO modulo and DTO phase. These bits must be - programmed first, otherwise there will be no HDMI audio at boot - up. This is a HW sequence change (different from old ASICs). - Caution when changing this programming sequence. - - HDMI enabled, using DTO0 - program master CRTC for DTO0 */ - src_sel = pll_info->dto_source - DTO_SOURCE_ID0; - REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, - DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, - DCCG_AUDIO_DTO_SEL, 0); - - /* module */ - REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, - DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); - - /* phase */ - REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, - DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); - } else { - /*DTO1 Programming goal: - -generate 24MHz, 128*Fs from 24MHz (DCE6 does not support 512*Fs) - -default is to used DTO1, and switch to DTO0 when an audio - master HDMI port is connected - -use as default for DP - - calculate DTO settings */ - get_azalia_clock_info_dp( - crtc_info->requested_pixel_clock_100Hz, - pll_info, - &clock_info); - - /* Program DTO select before programming DTO modulo and DTO - phase. default to use DTO1 */ - - REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, - DCCG_AUDIO_DTO_SEL, 1); - - /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) - * Cannot select 512fs for DP - * - * DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask - */ - - /* module */ - REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, - DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); - - /* phase */ - REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, - DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); - - /* DCE6 has no DCCG_AUDIO_DTO2_USE_512FBR_DTO mask in DCCG_AUDIO_DTO_SOURCE reg */ - - } -} -#endif - static bool dce_aud_endpoint_valid(struct audio *audio) { uint32_t value; @@ -1303,18 +1211,6 @@ static const struct audio_funcs funcs = { .destroy = dce_aud_destroy, }; -#if defined(CONFIG_DRM_AMD_DC_SI) -static const struct audio_funcs dce60_funcs = { - .endpoint_valid = dce_aud_endpoint_valid, - .hw_init = dce_aud_hw_init, - .wall_dto_setup = dce60_aud_wall_dto_setup, - .az_enable = dce_aud_az_enable, - .az_disable = dce_aud_az_disable, - .az_configure = dce_aud_az_configure, - .destroy = dce_aud_destroy, -}; -#endif - void dce_aud_destroy(struct audio **audio) { struct dce_audio *aud = DCE_AUD(*audio); @@ -1347,30 +1243,3 @@ struct audio *dce_audio_create( audio->masks = masks; return &audio->base; } - -#if defined(CONFIG_DRM_AMD_DC_SI) -struct audio *dce60_audio_create( - struct dc_context *ctx, - unsigned int inst, - const struct dce_audio_registers *reg, - const struct dce_audio_shift *shifts, - const struct dce_audio_mask *masks - ) -{ - struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); - - if (audio == NULL) { - ASSERT_CRITICAL(audio); - return NULL; - } - - audio->base.ctx = ctx; - audio->base.inst = inst; - audio->base.funcs = &dce60_funcs; - - audio->regs = reg; - audio->shifts = shifts; - audio->masks = masks; - return &audio->base; -} -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h index 1b7b8b079af44..3f1d161a0045a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h @@ -151,15 +151,6 @@ struct audio *dce_audio_create( const struct dce_audio_shift *shifts, const struct dce_audio_mask *masks); -#if defined(CONFIG_DRM_AMD_DC_SI) -struct audio *dce60_audio_create( - struct dc_context *ctx, - unsigned int inst, - const struct dce_audio_registers *reg, - const struct dce_audio_shift *shifts, - const struct dce_audio_mask *masks); -#endif - void dce_aud_destroy(struct audio **audio); void dce_aud_hw_init(struct audio *audio); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c deleted file mode 100644 index e7acd6eec1fd6..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c +++ /dev/null @@ -1,967 +0,0 @@ -/* - * Copyright 2012-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include - -#include "dce_clk_mgr.h" - -#include "reg_helper.h" -#include "dmcu.h" -#include "core_types.h" -#include "dal_asic_id.h" - -#define TO_DCE_CLK_MGR(clocks)\ - container_of(clocks, struct dce_clk_mgr, base) - -#define REG(reg) \ - (clk_mgr_dce->regs->reg) - -#undef FN -#define FN(reg_name, field_name) \ - clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name - -#define CTX \ - clk_mgr_dce->base.ctx -#define DC_LOGGER \ - clk_mgr->ctx->logger - -/* Max clock values for each state indexed by "enum clocks_state": */ -static const struct state_dependent_clocks dce80_max_clks_by_state[] = { -/* ClocksStateInvalid - should not be used */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateUltraLow - not expected to be used for DCE 8.0 */ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/* ClocksStateLow */ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000}, -/* ClocksStateNominal */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, -/* ClocksStatePerformance */ -{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; - -static const struct state_dependent_clocks dce110_max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 467000, .pixel_clk_khz = 400000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; - -static const struct state_dependent_clocks dce112_max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 389189, .pixel_clk_khz = 346672 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 459000, .pixel_clk_khz = 400000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 667000, .pixel_clk_khz = 600000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; - -static const struct state_dependent_clocks dce120_max_clks_by_state[] = { -/*ClocksStateInvalid - should not be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ -{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, -/*ClocksStateLow*/ -{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 }, -/*ClocksStateNominal*/ -{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, -/*ClocksStatePerformance*/ -{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; - -int dentist_get_divider_from_did(int did) -{ - if (did < DENTIST_BASE_DID_1) - did = DENTIST_BASE_DID_1; - if (did > DENTIST_MAX_DID) - did = DENTIST_MAX_DID; - - if (did < DENTIST_BASE_DID_2) { - return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP - * (did - DENTIST_BASE_DID_1); - } else if (did < DENTIST_BASE_DID_3) { - return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP - * (did - DENTIST_BASE_DID_2); - } else if (did < DENTIST_BASE_DID_4) { - return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP - * (did - DENTIST_BASE_DID_3); - } else { - return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP - * (did - DENTIST_BASE_DID_4); - } -} - -/* SW will adjust DP REF Clock average value for all purposes - * (DP DTO / DP Audio DTO and DP GTC) - if clock is spread for all cases: - -if SS enabled on DP Ref clock and HW de-spreading enabled with SW - calculations for DS_INCR/DS_MODULO (this is planned to be default case) - -if SS enabled on DP Ref clock and HW de-spreading enabled with HW - calculations (not planned to be used, but average clock should still - be valid) - -if SS enabled on DP Ref clock and HW de-spreading disabled - (should not be case with CIK) then SW should program all rates - generated according to average value (case as with previous ASICs) - */ -static int clk_mgr_adjust_dp_ref_freq_for_ss(struct dce_clk_mgr *clk_mgr_dce, int dp_ref_clk_khz) -{ - if (clk_mgr_dce->ss_on_dprefclk && clk_mgr_dce->dprefclk_ss_divider != 0) { - struct fixed31_32 ss_percentage = dc_fixpt_div_int( - dc_fixpt_from_fraction(clk_mgr_dce->dprefclk_ss_percentage, - clk_mgr_dce->dprefclk_ss_divider), 200); - struct fixed31_32 adj_dp_ref_clk_khz; - - ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage); - adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz); - dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz); - } - return dp_ref_clk_khz; -} - -static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - int dprefclk_wdivider; - int dprefclk_src_sel; - int dp_ref_clk_khz = 600000; - int target_div; - - /* ASSERT DP Reference Clock source is from DFS*/ - REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); - ASSERT(dprefclk_src_sel == 0); - - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ - REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); - - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ - target_div = dentist_get_divider_from_did(dprefclk_wdivider); - - /* Calculate the current DFS clock, in kHz.*/ - dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR - * clk_mgr_dce->dentist_vco_freq_khz) / target_div; - - return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, dp_ref_clk_khz); -} - -int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - - return clk_mgr_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_dce->dprefclk_khz); -} - -/* unit: in_khz before mode set, get pixel clock from context. ASIC register - * may not be programmed yet - */ -static uint32_t get_max_pixel_clock_for_all_paths(struct dc_state *context) -{ - uint32_t max_pix_clk = 0; - int i; - - for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - - if (pipe_ctx->stream == NULL) - continue; - - /* do not check under lay */ - if (pipe_ctx->top_pipe) - continue; - - if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; - - /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS - * logic for HBR3 still needs Nominal (0.8V) on VDDC rail - */ - if (dc_is_dp_signal(pipe_ctx->stream->signal) && - pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) - max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; - } - - return max_pix_clk; -} - -static enum dm_pp_clocks_state dce_get_required_clocks_state( - struct clk_mgr *clk_mgr, - struct dc_state *context) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - int i; - enum dm_pp_clocks_state low_req_clk; - int max_pix_clk = get_max_pixel_clock_for_all_paths(context); - - /* Iterate from highest supported to lowest valid state, and update - * lowest RequiredState with the lowest state that satisfies - * all required clocks - */ - for (i = clk_mgr_dce->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) - if (context->bw_ctx.bw.dce.dispclk_khz > - clk_mgr_dce->max_clks_by_state[i].display_clk_khz - || max_pix_clk > - clk_mgr_dce->max_clks_by_state[i].pixel_clk_khz) - break; - - low_req_clk = i + 1; - if (low_req_clk > clk_mgr_dce->max_clks_state) { - /* set max clock state for high phyclock, invalid on exceeding display clock */ - if (clk_mgr_dce->max_clks_by_state[clk_mgr_dce->max_clks_state].display_clk_khz - < context->bw_ctx.bw.dce.dispclk_khz) - low_req_clk = DM_PP_CLOCKS_STATE_INVALID; - else - low_req_clk = clk_mgr_dce->max_clks_state; - } - - return low_req_clk; -} - -static int dce_set_clock( - struct clk_mgr *clk_mgr, - int requested_clk_khz) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct bp_pixel_clock_parameters pxl_clk_params = { 0 }; - struct dc_bios *bp = clk_mgr->ctx->dc_bios; - int actual_clock = requested_clk_khz; - struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu; - - /* Make sure requested clock isn't lower than minimum threshold*/ - if (requested_clk_khz > 0) - requested_clk_khz = max(requested_clk_khz, - clk_mgr_dce->dentist_vco_freq_khz / 64); - - /* Prepare to program display clock*/ - pxl_clk_params.target_pixel_clock_100hz = requested_clk_khz * 10; - pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; - - if (clk_mgr_dce->dfs_bypass_active) - pxl_clk_params.flags.SET_DISPCLK_DFS_BYPASS = true; - - bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); - - if (clk_mgr_dce->dfs_bypass_active) { - /* Cache the fixed display clock*/ - clk_mgr_dce->dfs_bypass_disp_clk = - pxl_clk_params.dfs_bypass_display_clock; - actual_clock = pxl_clk_params.dfs_bypass_display_clock; - } - - /* from power down, we need mark the clock state as ClocksStateNominal - * from HWReset, so when resume we will call pplib voltage regulator.*/ - if (requested_clk_khz == 0) - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - - if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) - dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7); - - return actual_clock; -} - -int dce112_set_clock(struct clk_mgr *clk_mgr, int requested_clk_khz) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct bp_set_dce_clock_parameters dce_clk_params; - struct dc_bios *bp = clk_mgr->ctx->dc_bios; - struct dc *core_dc = clk_mgr->ctx->dc; - struct dmcu *dmcu = core_dc->res_pool->dmcu; - int actual_clock = requested_clk_khz; - /* Prepare to program display clock*/ - memset(&dce_clk_params, 0, sizeof(dce_clk_params)); - - /* Make sure requested clock isn't lower than minimum threshold*/ - if (requested_clk_khz > 0) - requested_clk_khz = max(requested_clk_khz, - clk_mgr_dce->dentist_vco_freq_khz / 62); - - dce_clk_params.target_clock_frequency = requested_clk_khz; - dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; - dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; - - bp->funcs->set_dce_clock(bp, &dce_clk_params); - actual_clock = dce_clk_params.target_clock_frequency; - - /* from power down, we need mark the clock state as ClocksStateNominal - * from HWReset, so when resume we will call pplib voltage regulator.*/ - if (requested_clk_khz == 0) - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - - /*Program DP ref Clock*/ - /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ - dce_clk_params.target_clock_frequency = 0; - dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; - - if (!((clk_mgr->ctx->asic_id.chip_family == FAMILY_AI) && - ASICREV_IS_VEGA20_P(clk_mgr->ctx->asic_id.hw_internal_rev))) - dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = - (dce_clk_params.pll_id == - CLOCK_SOURCE_COMBO_DISPLAY_PLL0); - else - dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; - - bp->funcs->set_dce_clock(bp, &dce_clk_params); - - if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { - if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) { - if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock) - dmcu->funcs->set_psr_wait_loop(dmcu, - actual_clock / 1000 / 7); - } - } - - clk_mgr_dce->dfs_bypass_disp_clk = actual_clock; - return actual_clock; -} - -static void dce_clock_read_integrated_info(struct dce_clk_mgr *clk_mgr_dce) -{ - struct dc_debug_options *debug = &clk_mgr_dce->base.ctx->dc->debug; - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - struct integrated_info info = { { { 0 } } }; - struct dc_firmware_info fw_info = { { 0 } }; - int i; - - if (bp->integrated_info) - info = *bp->integrated_info; - - clk_mgr_dce->dentist_vco_freq_khz = info.dentist_vco_freq; - if (clk_mgr_dce->dentist_vco_freq_khz == 0) { - bp->funcs->get_firmware_info(bp, &fw_info); - clk_mgr_dce->dentist_vco_freq_khz = - fw_info.smu_gpu_pll_output_freq; - if (clk_mgr_dce->dentist_vco_freq_khz == 0) - clk_mgr_dce->dentist_vco_freq_khz = 3600000; - } - - /*update the maximum display clock for each power state*/ - for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { - enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; - - switch (i) { - case 0: - clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; - break; - - case 1: - clk_state = DM_PP_CLOCKS_STATE_LOW; - break; - - case 2: - clk_state = DM_PP_CLOCKS_STATE_NOMINAL; - break; - - case 3: - clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; - break; - - default: - clk_state = DM_PP_CLOCKS_STATE_INVALID; - break; - } - - /*Do not allow bad VBIOS/SBIOS to override with invalid values, - * check for > 100MHz*/ - if (info.disp_clk_voltage[i].max_supported_clk >= 100000) - clk_mgr_dce->max_clks_by_state[clk_state].display_clk_khz = - info.disp_clk_voltage[i].max_supported_clk; - } - - if (!debug->disable_dfs_bypass && bp->integrated_info) - if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) - clk_mgr_dce->dfs_bypass_enabled = true; -} - -void dce_clock_read_ss_info(struct dce_clk_mgr *clk_mgr_dce) -{ - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - int ss_info_num = bp->funcs->get_ss_entry_number( - bp, AS_SIGNAL_TYPE_GPU_PLL); - - if (ss_info_num) { - struct spread_spectrum_info info = { { 0 } }; - enum bp_result result = bp->funcs->get_spread_spectrum_info( - bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info); - - /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS - * even if SS not enabled and in that case - * SSInfo.spreadSpectrumPercentage !=0 would be sign - * that SS is enabled - */ - if (result == BP_RESULT_OK && - info.spread_spectrum_percentage != 0) { - clk_mgr_dce->ss_on_dprefclk = true; - clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* TODO: Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - clk_mgr_dce->dprefclk_ss_percentage = - info.spread_spectrum_percentage; - } - - return; - } - - result = bp->funcs->get_spread_spectrum_info( - bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info); - - /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS - * even if SS not enabled and in that case - * SSInfo.spreadSpectrumPercentage !=0 would be sign - * that SS is enabled - */ - if (result == BP_RESULT_OK && - info.spread_spectrum_percentage != 0) { - clk_mgr_dce->ss_on_dprefclk = true; - clk_mgr_dce->dprefclk_ss_divider = info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - clk_mgr_dce->dprefclk_ss_percentage = - info.spread_spectrum_percentage; - } - if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss) - clk_mgr_dce->dprefclk_ss_percentage = 0; - } - } -} - -/** - * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info - * @clk_mgr: clock manager base structure - * - * Reads from VBIOS the XGMI spread spectrum info and saves it within - * the dce clock manager. This operation will overwrite the existing dprefclk - * SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also - * sets the ->xgmi_enabled flag. - */ -void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - enum bp_result result; - struct spread_spectrum_info info = { { 0 } }; - struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; - - clk_mgr_dce->xgmi_enabled = false; - - result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI, - 0, &info); - if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) { - clk_mgr_dce->xgmi_enabled = true; - clk_mgr_dce->ss_on_dprefclk = true; - clk_mgr_dce->dprefclk_ss_divider = - info.spread_percentage_divider; - - if (info.type.CENTER_MODE == 0) { - /* Currently for DP Reference clock we - * need only SS percentage for - * downspread */ - clk_mgr_dce->dprefclk_ss_percentage = - info.spread_spectrum_percentage; - } - } -} - -void dce110_fill_display_configs( - const struct dc_state *context, - struct dm_pp_display_configuration *pp_display_cfg) -{ - int j; - int num_cfgs = 0; - - for (j = 0; j < context->stream_count; j++) { - int k; - - const struct dc_stream_state *stream = context->streams[j]; - struct dm_pp_single_disp_config *cfg = - &pp_display_cfg->disp_configs[num_cfgs]; - const struct pipe_ctx *pipe_ctx = NULL; - - for (k = 0; k < MAX_PIPES; k++) - if (stream == context->res_ctx.pipe_ctx[k].stream) { - pipe_ctx = &context->res_ctx.pipe_ctx[k]; - break; - } - - ASSERT(pipe_ctx != NULL); - - /* only notify active stream */ - if (stream->dpms_off) - continue; - - num_cfgs++; - cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; - cfg->src_height = stream->src.height; - cfg->src_width = stream->src.width; - cfg->ddi_channel_mapping = - stream->link->ddi_channel_mapping.raw; - cfg->transmitter = - stream->link->link_enc->transmitter; - cfg->link_settings.lane_count = - stream->link->cur_link_settings.lane_count; - cfg->link_settings.link_rate = - stream->link->cur_link_settings.link_rate; - cfg->link_settings.link_spread = - stream->link->cur_link_settings.link_spread; - cfg->sym_clock = stream->phy_pix_clk; - /* Round v_refresh*/ - cfg->v_refresh = stream->timing.pix_clk_100hz * 100; - cfg->v_refresh /= stream->timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) - / stream->timing.v_total; - } - - pp_display_cfg->display_count = num_cfgs; -} - -static uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) -{ - uint8_t j; - uint32_t min_vertical_blank_time = -1; - - for (j = 0; j < context->stream_count; j++) { - struct dc_stream_state *stream = context->streams[j]; - uint32_t vertical_blank_in_pixels = 0; - uint32_t vertical_blank_time = 0; - - vertical_blank_in_pixels = stream->timing.h_total * - (stream->timing.v_total - - stream->timing.v_addressable); - - vertical_blank_time = vertical_blank_in_pixels - * 10000 / stream->timing.pix_clk_100hz; - - if (min_vertical_blank_time > vertical_blank_time) - min_vertical_blank_time = vertical_blank_time; - } - - return min_vertical_blank_time; -} - -static int determine_sclk_from_bounding_box( - const struct dc *dc, - int required_sclk) -{ - int i; - - /* - * Some asics do not give us sclk levels, so we just report the actual - * required sclk - */ - if (dc->sclk_lvls.num_levels == 0) - return required_sclk; - - for (i = 0; i < dc->sclk_lvls.num_levels; i++) { - if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) - return dc->sclk_lvls.clocks_in_khz[i]; - } - /* - * even maximum level could not satisfy requirement, this - * is unexpected at this stage, should have been caught at - * validation time - */ - ASSERT(0); - return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; -} - -static void dce_pplib_apply_display_requirements( - struct dc *dc, - struct dc_state *context) -{ - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - - pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context); - - dce110_fill_display_configs(context, pp_display_cfg); - - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); -} - -static void dce11_pplib_apply_display_requirements( - struct dc *dc, - struct dc_state *context) -{ - struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; - - pp_display_cfg->all_displays_in_sync = - context->bw_ctx.bw.dce.all_displays_in_sync; - pp_display_cfg->nb_pstate_switch_disable = - context->bw_ctx.bw.dce.nbp_state_change_enable == false; - pp_display_cfg->cpu_cc6_disable = - context->bw_ctx.bw.dce.cpuc_state_change_enable == false; - pp_display_cfg->cpu_pstate_disable = - context->bw_ctx.bw.dce.cpup_state_change_enable == false; - pp_display_cfg->cpu_pstate_separation_time = - context->bw_ctx.bw.dce.blackout_recovery_time_us; - - pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz - / MEMORY_TYPE_MULTIPLIER_CZ; - - pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( - dc, - context->bw_ctx.bw.dce.sclk_khz); - - /* - * As workaround for >4x4K lightup set dcfclock to min_engine_clock value. - * This is not required for less than 5 displays, - * thus don't request decfclk in dc to avoid impact - * on power saving. - * - */ - pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ? - pp_display_cfg->min_engine_clock_khz : 0; - - pp_display_cfg->min_engine_clock_deep_sleep_khz - = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; - - pp_display_cfg->avail_mclk_switch_time_us = - dce110_get_min_vblank_time_us(context); - /* TODO: dce11.2*/ - pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; - - pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; - - dce110_fill_display_configs(context, pp_display_cfg); - - /* TODO: is this still applicable?*/ - if (pp_display_cfg->display_count == 1) { - const struct dc_crtc_timing *timing = - &context->streams[0]->timing; - - pp_display_cfg->crtc_index = - pp_display_cfg->disp_configs[0].pipe_idx; - pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; - } - - if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) - dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); -} - -static void dce_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - patched_disp_clk = dce_set_clock(clk_mgr, patched_disp_clk); - clk_mgr->clks.dispclk_khz = patched_disp_clk; - } - dce_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static void dce11_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk); - clk_mgr->clks.dispclk_khz = patched_disp_clk; - } - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static void dce112_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_power_level_change_request level_change_req; - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context); - /* get max clock state from PPLIB */ - if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) - || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { - if (dm_pp_apply_power_level_change_request(clk_mgr->ctx, &level_change_req)) - clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; - } - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - patched_disp_clk = dce112_set_clock(clk_mgr, patched_disp_clk); - clk_mgr->clks.dispclk_khz = patched_disp_clk; - } - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static void dce12_update_clocks(struct clk_mgr *clk_mgr, - struct dc_state *context, - bool safe_to_lower) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); - struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; - int max_pix_clk = get_max_pixel_clock_for_all_paths(context); - int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; - - /*TODO: W/A for dal3 linux, investigate why this works */ - if (!clk_mgr_dce->dfs_bypass_active) - patched_disp_clk = patched_disp_clk * 115 / 100; - - if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) { - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; - /* - * When xGMI is enabled, the display clk needs to be adjusted - * with the WAFL link's SS percentage. - */ - if (clk_mgr_dce->xgmi_enabled) - patched_disp_clk = clk_mgr_adjust_dp_ref_freq_for_ss( - clk_mgr_dce, patched_disp_clk); - clock_voltage_req.clocks_in_khz = patched_disp_clk; - clk_mgr->clks.dispclk_khz = dce112_set_clock(clk_mgr, patched_disp_clk); - - dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req); - } - - if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { - clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; - clock_voltage_req.clocks_in_khz = max_pix_clk; - clk_mgr->clks.phyclk_khz = max_pix_clk; - - dm_pp_apply_clock_for_voltage_request(clk_mgr->ctx, &clock_voltage_req); - } - dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context); -} - -static const struct clk_mgr_funcs dce120_funcs = { - .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, - .update_clocks = dce12_update_clocks -}; - -static const struct clk_mgr_funcs dce112_funcs = { - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, - .update_clocks = dce112_update_clocks -}; - -static const struct clk_mgr_funcs dce110_funcs = { - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, - .update_clocks = dce11_update_clocks, -}; - -static const struct clk_mgr_funcs dce_funcs = { - .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, - .update_clocks = dce_update_clocks -}; - -static void dce_clk_mgr_construct( - struct dce_clk_mgr *clk_mgr_dce, - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct clk_mgr *base = &clk_mgr_dce->base; - struct dm_pp_static_clock_info static_clk_info = {0}; - - base->ctx = ctx; - base->funcs = &dce_funcs; - - clk_mgr_dce->regs = regs; - clk_mgr_dce->clk_mgr_shift = clk_shift; - clk_mgr_dce->clk_mgr_mask = clk_mask; - - clk_mgr_dce->dfs_bypass_disp_clk = 0; - - clk_mgr_dce->dprefclk_ss_percentage = 0; - clk_mgr_dce->dprefclk_ss_divider = 1000; - clk_mgr_dce->ss_on_dprefclk = false; - - - if (dm_pp_get_static_clocks(ctx, &static_clk_info)) - clk_mgr_dce->max_clks_state = static_clk_info.max_clocks_state; - else - clk_mgr_dce->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; - clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; - - dce_clock_read_integrated_info(clk_mgr_dce); - dce_clock_read_ss_info(clk_mgr_dce); -} - -struct clk_mgr *dce_clk_mgr_create( - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce80_max_clks_by_state, - sizeof(dce80_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, regs, clk_shift, clk_mask); - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce110_clk_mgr_create( - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce110_max_clks_by_state, - sizeof(dce110_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, regs, clk_shift, clk_mask); - - clk_mgr_dce->base.funcs = &dce110_funcs; - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce112_clk_mgr_create( - struct dc_context *ctx, - const struct clk_mgr_registers *regs, - const struct clk_mgr_shift *clk_shift, - const struct clk_mgr_mask *clk_mask) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce112_max_clks_by_state, - sizeof(dce112_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, regs, clk_shift, clk_mask); - - clk_mgr_dce->base.funcs = &dce112_funcs; - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce120_clk_mgr_create(struct dc_context *ctx) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, - dce120_max_clks_by_state, - sizeof(dce120_max_clks_by_state)); - - dce_clk_mgr_construct( - clk_mgr_dce, ctx, NULL, NULL, NULL); - - clk_mgr_dce->dprefclk_khz = 600000; - clk_mgr_dce->base.funcs = &dce120_funcs; - - return &clk_mgr_dce->base; -} - -struct clk_mgr *dce121_clk_mgr_create(struct dc_context *ctx) -{ - struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), - GFP_KERNEL); - - if (clk_mgr_dce == NULL) { - BREAK_TO_DEBUGGER(); - return NULL; - } - - memcpy(clk_mgr_dce->max_clks_by_state, dce120_max_clks_by_state, - sizeof(dce120_max_clks_by_state)); - - dce_clk_mgr_construct(clk_mgr_dce, ctx, NULL, NULL, NULL); - - clk_mgr_dce->dprefclk_khz = 625000; - clk_mgr_dce->base.funcs = &dce120_funcs; - - return &clk_mgr_dce->base; -} - -void dce_clk_mgr_destroy(struct clk_mgr **clk_mgr) -{ - struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(*clk_mgr); - - kfree(clk_mgr_dce); - *clk_mgr = NULL; -} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 87dbb8d7ed27d..a368802ba51db 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -102,6 +102,7 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .enable_dp_output = dce110_link_encoder_enable_dp_output, .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, .disable_output = dce110_link_encoder_disable_output, .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, @@ -117,6 +118,35 @@ static const struct link_encoder_funcs dce110_lnk_enc_funcs = { .destroy = dce110_link_encoder_destroy, .get_max_link_cap = dce110_link_encoder_get_max_link_cap, .get_dig_frontend = dce110_get_dig_frontend, + .get_hpd_state = dce110_get_hpd_state, + .program_hpd_filter = dce110_program_hpd_filter, +}; + +static const struct link_encoder_funcs dce110_lnk_enc_funcs_no_hpd = { + .validate_output_with_stream = + dce110_link_encoder_validate_output_with_stream, + .hw_init = dce110_link_encoder_hw_init, + .setup = dce110_link_encoder_setup, + .enable_tmds_output = dce110_link_encoder_enable_tmds_output, + .enable_dp_output = dce110_link_encoder_enable_dp_output, + .enable_dp_mst_output = dce110_link_encoder_enable_dp_mst_output, + .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, + .disable_output = dce110_link_encoder_disable_output, + .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dce110_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dce110_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dce110_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dce110_psr_program_secondary_packet, + .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, + .is_dig_enabled = dce110_is_dig_enabled, + .destroy = dce110_link_encoder_destroy, + .get_max_link_cap = dce110_link_encoder_get_max_link_cap, + .get_dig_frontend = dce110_get_dig_frontend, + .get_hpd_state = dce110_get_hpd_state, + .program_hpd_filter = dce110_program_hpd_filter, }; static enum bp_result link_transmitter_control( @@ -131,6 +161,21 @@ static enum bp_result link_transmitter_control( return result; } +static enum bp_result link_dac_encoder_control( + struct dce110_link_encoder *link_enc, + enum bp_encoder_control_action action, + uint32_t pix_clk_100hz) +{ + struct dc_bios *bios = link_enc->base.ctx->dc_bios; + struct bp_encoder_control encoder_control = {0}; + + encoder_control.action = action; + encoder_control.engine_id = link_enc->base.analog_engine; + encoder_control.pixel_clock = pix_clk_100hz / 10; + + return bios->funcs->encoder_control(bios, &encoder_control); +} + static void enable_phy_bypass_mode( struct dce110_link_encoder *enc110, bool enable) @@ -847,10 +892,15 @@ void dce110_link_encoder_construct( const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; enum bp_result result = BP_RESULT_OK; - enc110->base.funcs = &dce110_lnk_enc_funcs; + if (hpd_regs) + enc110->base.funcs = &dce110_lnk_enc_funcs; + else + enc110->base.funcs = &dce110_lnk_enc_funcs_no_hpd; enc110->base.ctx = init_data->ctx; enc110->base.id = init_data->encoder; + enc110->base.analog_id = init_data->analog_encoder; + enc110->base.hpd_gpio = init_data->hpd_gpio; enc110->base.hpd_source = init_data->hpd_source; enc110->base.connector = init_data->connector; @@ -1017,6 +1067,16 @@ void dce110_link_encoder_hw_init( cntl.coherent = false; cntl.hpd_sel = enc110->base.hpd_source; + if (enc110->base.analog_engine != ENGINE_ID_UNKNOWN) { + result = link_dac_encoder_control(enc110, ENCODER_CONTROL_INIT, 0); + if (result != BP_RESULT_OK) { + DC_LOG_ERROR("%s: Failed to execute VBIOS command table for DAC!\n", + __func__); + BREAK_TO_DEBUGGER(); + return; + } + } + /* The code below is only applicable to encoders with a digital transmitter. */ if (enc110->base.transmitter == TRANSMITTER_UNKNOWN) return; @@ -1053,6 +1113,11 @@ void dce110_link_encoder_hw_init( void dce110_link_encoder_destroy(struct link_encoder **enc) { + if ((*enc)->hpd_gpio) { + dal_gpio_destroy_irq(&(*enc)->hpd_gpio); + (*enc)->hpd_gpio = NULL; + } + kfree(TO_DCE110_LINK_ENC(*enc)); *enc = NULL; } @@ -1166,6 +1231,22 @@ void dce110_link_encoder_enable_lvds_output( } } +void dce110_link_encoder_enable_analog_output( + struct link_encoder *enc, + uint32_t pixel_clock) +{ + struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); + enum bp_result result; + + result = link_dac_encoder_control(enc110, ENCODER_CONTROL_ENABLE, pixel_clock); + + if (result != BP_RESULT_OK) { + DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", + __func__); + BREAK_TO_DEBUGGER(); + } +} + /* enables DP PHY output */ void dce110_link_encoder_enable_dp_output( struct link_encoder *enc, @@ -1336,19 +1417,8 @@ void dce110_link_encoder_disable_output( struct bp_transmitter_control cntl = { 0 }; enum bp_result result; - switch (enc->analog_engine) { - case ENGINE_ID_DACA: - REG_UPDATE(DAC_ENABLE, DAC_ENABLE, 0); - break; - case ENGINE_ID_DACB: - /* DACB doesn't seem to be present on DCE6+, - * although there are references to it in the register file. - */ - DC_LOG_ERROR("%s DACB is unsupported\n", __func__); - break; - default: - break; - } + if (enc->analog_engine != ENGINE_ID_UNKNOWN) + link_dac_encoder_control(enc110, ENCODER_CONTROL_DISABLE, 0); /* The code below only applies to connectors that support digital signals. */ if (enc->transmitter == TRANSMITTER_UNKNOWN) @@ -1751,6 +1821,40 @@ void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, *link_settings = max_link_cap; } +bool dce110_get_hpd_state(struct link_encoder *enc) +{ + uint32_t state = 0; + + if (!enc->hpd_gpio) + return false; + + dal_gpio_lock_pin(enc->hpd_gpio); + dal_gpio_get_value(enc->hpd_gpio, &state); + dal_gpio_unlock_pin(enc->hpd_gpio); + + return state; +} + +bool dce110_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms) +{ + /* Setup HPD filtering */ + if (enc->hpd_gpio && dal_gpio_lock_pin(enc->hpd_gpio) == GPIO_RESULT_OK) { + struct gpio_hpd_config config; + + config.delay_on_connect = delay_on_connect_in_ms; + config.delay_on_disconnect = delay_on_disconnect_in_ms; + + dal_irq_setup_hpd_filter(enc->hpd_gpio, &config); + + dal_gpio_unlock_pin(enc->hpd_gpio); + + return true; + } else { + ASSERT(0); + return false; + } +} + #if defined(CONFIG_DRM_AMD_DC_SI) static const struct link_encoder_funcs dce60_lnk_enc_funcs = { .validate_output_with_stream = @@ -1761,6 +1865,7 @@ static const struct link_encoder_funcs dce60_lnk_enc_funcs = { .enable_dp_output = dce60_link_encoder_enable_dp_output, .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, .disable_output = dce110_link_encoder_disable_output, .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, @@ -1775,7 +1880,36 @@ static const struct link_encoder_funcs dce60_lnk_enc_funcs = { .is_dig_enabled = dce110_is_dig_enabled, .destroy = dce110_link_encoder_destroy, .get_max_link_cap = dce110_link_encoder_get_max_link_cap, - .get_dig_frontend = dce110_get_dig_frontend + .get_dig_frontend = dce110_get_dig_frontend, + .get_hpd_state = dce110_get_hpd_state, + .program_hpd_filter = dce110_program_hpd_filter, +}; + +static const struct link_encoder_funcs dce60_lnk_enc_funcs_no_hpd = { + .validate_output_with_stream = + dce110_link_encoder_validate_output_with_stream, + .hw_init = dce110_link_encoder_hw_init, + .setup = dce110_link_encoder_setup, + .enable_tmds_output = dce110_link_encoder_enable_tmds_output, + .enable_dp_output = dce60_link_encoder_enable_dp_output, + .enable_dp_mst_output = dce60_link_encoder_enable_dp_mst_output, + .enable_lvds_output = dce110_link_encoder_enable_lvds_output, + .enable_analog_output = dce110_link_encoder_enable_analog_output, + .disable_output = dce110_link_encoder_disable_output, + .dp_set_lane_settings = dce110_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dce60_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dce110_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dce110_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dce110_psr_program_secondary_packet, + .connect_dig_be_to_fe = dce110_link_encoder_connect_dig_be_to_fe, + .is_dig_enabled = dce110_is_dig_enabled, + .destroy = dce110_link_encoder_destroy, + .get_max_link_cap = dce110_link_encoder_get_max_link_cap, + .get_dig_frontend = dce110_get_dig_frontend, + .get_hpd_state = dce110_get_hpd_state, + .program_hpd_filter = dce110_program_hpd_filter, }; void dce60_link_encoder_construct( @@ -1790,10 +1924,15 @@ void dce60_link_encoder_construct( const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; enum bp_result result = BP_RESULT_OK; - enc110->base.funcs = &dce60_lnk_enc_funcs; + if (hpd_regs) + enc110->base.funcs = &dce60_lnk_enc_funcs; + else + enc110->base.funcs = &dce60_lnk_enc_funcs_no_hpd; enc110->base.ctx = init_data->ctx; enc110->base.id = init_data->encoder; + enc110->base.analog_id = init_data->analog_encoder; + enc110->base.hpd_gpio = init_data->hpd_gpio; enc110->base.hpd_source = init_data->hpd_source; enc110->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index c58b69bc319b7..8841000361fb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -101,8 +101,7 @@ SRI(DP_SEC_CNTL, DP, id), \ SRI(DP_VID_STREAM_CNTL, DP, id), \ SRI(DP_DPHY_FAST_TRAINING, DP, id), \ - SRI(DP_SEC_CNTL1, DP, id), \ - SR(DAC_ENABLE) + SRI(DP_SEC_CNTL1, DP, id) #endif #define LE_DCE80_REG_LIST(id)\ @@ -130,11 +129,6 @@ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ SR(DCI_MEM_PWR_STATUS) -#define LE_DCN10_REG_LIST(id)\ - LE_COMMON_REG_LIST_BASE(id), \ - SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) struct dce110_link_enc_aux_registers { uint32_t AUX_CONTROL; @@ -273,6 +267,11 @@ void dce110_link_encoder_enable_lvds_output( enum clock_source_id clock_source, uint32_t pixel_clock); +/* enables analog output from the DAC */ +void dce110_link_encoder_enable_analog_output( + struct link_encoder *enc, + uint32_t pixel_clock); + /* disable PHY output */ void dce110_link_encoder_disable_output( struct link_encoder *enc, @@ -319,4 +318,7 @@ bool dce110_is_dig_enabled(struct link_encoder *enc); void dce110_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_link_settings *link_settings); +bool dce110_get_hpd_state(struct link_encoder *enc); +bool dce110_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); + #endif /* __DC_LINK_ENCODER__DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 574618d5d4a4e..87c19f17c799f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -1498,7 +1498,10 @@ static void dig_connect_to_otg( { struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); - REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); + if (enc->id == ENGINE_ID_DACA || enc->id == ENGINE_ID_DACB) + REG_UPDATE(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, tg_inst); + else + REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); } static unsigned int dig_source_otg( @@ -1507,7 +1510,10 @@ static unsigned int dig_source_otg( uint32_t tg_inst = 0; struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); - REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); + if (enc->id == ENGINE_ID_DACA || enc->id == ENGINE_ID_DACB) + REG_GET(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, &tg_inst); + else + REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); return tg_inst; } @@ -1568,16 +1574,25 @@ void dce110_stream_encoder_construct( enc110->se_mask = se_mask; } -static const struct stream_encoder_funcs dce110_an_str_enc_funcs = {}; +static const struct stream_encoder_funcs dce110_an_str_enc_funcs = { + .dig_connect_to_otg = dig_connect_to_otg, + .dig_source_otg = dig_source_otg, +}; void dce110_analog_stream_encoder_construct( struct dce110_stream_encoder *enc110, struct dc_context *ctx, struct dc_bios *bp, - enum engine_id eng_id) + enum engine_id eng_id, + const struct dce110_stream_enc_registers *regs, + const struct dce_stream_encoder_shift *se_shift, + const struct dce_stream_encoder_mask *se_mask) { enc110->base.funcs = &dce110_an_str_enc_funcs; enc110->base.ctx = ctx; enc110->base.id = eng_id; enc110->base.bp = bp; + enc110->regs = regs; + enc110->se_shift = se_shift; + enc110->se_mask = se_mask; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index 068de1392121e..342c0afe6a949 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -65,6 +65,7 @@ SRI(AFMT_60958_1, DIG, id), \ SRI(AFMT_60958_2, DIG, id), \ SRI(DIG_FE_CNTL, DIG, id), \ + SR(DAC_SOURCE_SELECT), \ SRI(HDMI_CONTROL, DIG, id), \ SRI(HDMI_GC, DIG, id), \ SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ @@ -290,7 +291,8 @@ #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ - SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh) + SE_SF(TMDS_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DAC_SOURCE_SELECT, DAC_SOURCE_SELECT, mask_sh) #define SE_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ @@ -494,6 +496,7 @@ struct dce_stream_encoder_shift { uint8_t DP_VID_N_MUL; uint8_t DP_VID_M_DOUBLE_VALUE_EN; uint8_t DIG_SOURCE_SELECT; + uint8_t DAC_SOURCE_SELECT; }; struct dce_stream_encoder_mask { @@ -626,6 +629,7 @@ struct dce_stream_encoder_mask { uint32_t DP_VID_N_MUL; uint32_t DP_VID_M_DOUBLE_VALUE_EN; uint32_t DIG_SOURCE_SELECT; + uint32_t DAC_SOURCE_SELECT; }; struct dce110_stream_enc_registers { @@ -653,6 +657,7 @@ struct dce110_stream_enc_registers { uint32_t AFMT_60958_1; uint32_t AFMT_60958_2; uint32_t DIG_FE_CNTL; + uint32_t DAC_SOURCE_SELECT; uint32_t DP_MSE_RATE_CNTL; uint32_t DP_MSE_RATE_UPDATE; uint32_t DP_PIXEL_FORMAT; @@ -712,7 +717,10 @@ void dce110_analog_stream_encoder_construct( struct dce110_stream_encoder *enc110, struct dc_context *ctx, struct dc_bios *bp, - enum engine_id eng_id); + enum engine_id eng_id, + const struct dce110_stream_enc_registers *regs, + const struct dce_stream_encoder_shift *se_shift, + const struct dce_stream_encoder_mask *se_mask); void dce110_se_audio_mute_control( struct stream_encoder *enc, bool mute); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c index 5bfa2b0d2afdc..d0ffa99f1fe0d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c @@ -28,6 +28,14 @@ #include "dc_types.h" #include "core_types.h" +static bool dmub_hw_lock_has_inbox0_lock(const struct dc *dc) +{ + return dc->ctx && dc->ctx->dmub_srv && + dc->hwss.dmub_hw_control_lock && + dc->hwss.dmub_hw_control_lock_fast && + dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support; +} + void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv, bool lock, union dmub_hw_lock_flags *hw_locks, @@ -69,7 +77,7 @@ bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct d if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) return true; - if (link->replay_settings.replay_feature_enabled) + if (link->replay_settings.replay_feature_enabled && dc_is_embedded_signal(link->connector_signal)) return true; if (link->psr_settings.psr_version == DC_PSR_VERSION_1) { @@ -105,5 +113,13 @@ bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link if (dc->ctx->dce_version >= DCN_VERSION_4_01) return false; + if (dmub_hw_lock_has_inbox0_lock(dc)) + return false; + return dmub_hw_lock_mgr_does_link_require_lock(dc, link); } + +bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link) +{ + return dmub_hw_lock_has_inbox0_lock(dc) && dmub_hw_lock_mgr_does_link_require_lock(dc, link); +} diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h index 4c80ca8484ad3..3e8caa9303906 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h @@ -46,7 +46,38 @@ void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv, * Return: true if the inbox1 lock should be used, false otherwise */ bool should_use_dmub_inbox1_lock(const struct dc *dc, const struct dc_link *link); + +/** + * dmub_hw_lock_mgr_does_link_require_lock() - Returns true if the link has a feature that needs the HW lock. + * + * @dc: Pointer to DC object + * @link: The link to check + * + * Return: true if the link has a feature that needs the HW lock, false otherwise + */ bool dmub_hw_lock_mgr_does_link_require_lock(const struct dc *dc, const struct dc_link *link); + +/** + * dmub_hw_lock_mgr_does_context_require_lock() - Returns true if the context has any stream that needs the HW lock. + * + * @dc: Pointer to DC object + * @context: The context to check + * + * Return: true if the context has any stream that needs the HW lock, false otherwise + */ bool dmub_hw_lock_mgr_does_context_require_lock(const struct dc *dc, const struct dc_state *context); +/** + * should_use_dmub_inbox0_lock_for_link() - Checks if the inbox0 interlock with DMU should be used. + * + * Is not functionally equivalent to inbox1 as DMUB will not own programming of the relevant locking + * registers. + * + * @dc: pointer to DC object + * @link: optional pointer to the link object to check for enabled link features + * + * Return: true if the inbox0 lock should be used, false otherwise + */ +bool should_use_dmub_inbox0_lock_for_link(const struct dc *dc, const struct dc_link *link); + #endif /*_DMUB_HW_LOCK_MGR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index 87af4fdc04a6f..d672231495ef5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -380,7 +380,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); - /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index cf1372aaff6c9..fd8244c946874 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -387,19 +387,6 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub, cmd.replay_disabled_adaptive_sync_sdp.data.force_disabled = cmd_element->disabled_adaptive_sync_sdp_data.force_disabled; break; - case Replay_Set_Version: - //Header - cmd.replay_set_version.header.sub_type = - DMUB_CMD__REPLAY_SET_VERSION; - cmd.replay_set_version.header.payload_bytes = - sizeof(struct dmub_rb_cmd_replay_set_version) - - sizeof(struct dmub_cmd_header); - //Cmd Body - cmd.replay_set_version.replay_set_version_data.panel_inst = - cmd_element->version_data.panel_inst; - cmd.replay_set_version.replay_set_version_data.version = - cmd_element->version_data.version; - break; case Replay_Set_General_Cmd: //Header cmd.replay_set_general_cmd.header.sub_type = diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 8d31fa131cd60..9459e8f283384 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -104,6 +104,8 @@ static const struct link_encoder_funcs dcn201_link_enc_funcs = { .fec_is_active = enc2_fec_is_active, .is_in_alt_mode = dcn201_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn201_link_encoder_get_max_link_cap, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn201_link_encoder_construct( @@ -125,6 +127,7 @@ void dcn201_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index eb9abb9f96986..36456c9971c84 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -325,6 +325,8 @@ static const struct link_encoder_funcs dcn21_link_enc_funcs = { .get_dig_frontend = dcn10_get_dig_frontend, .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn21_link_encoder_construct( @@ -346,6 +348,7 @@ void dcn21_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/Makefile b/drivers/gpu/drm/amd/display/dc/dio/Makefile index 0dfd480976f77..4832533b9514a 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dio/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -23,11 +23,20 @@ # # +############################################################################### +# VIRTUAL +############################################################################### +DIO_VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o + +AMD_DAL_DIO_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/dio/virtual/,$(DIO_VIRTUAL)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DIO_VIRTUAL) + ifdef CONFIG_DRM_AMD_DC_FP ############################################################################### # DCN10 ############################################################################### -DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o +DIO_DCN10 = dcn10_link_encoder.o dcn10_stream_encoder.o dcn10_dio.o AMD_DAL_DIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/dio/dcn10/,$(DIO_DCN10)) @@ -114,4 +123,13 @@ DIO_DCN401 = dcn401_dio_link_encoder.o dcn401_dio_stream_encoder.o AMD_DAL_DIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/dio/dcn401/,$(DIO_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN401) + +############################################################################### +# DCN42 +############################################################################### +DIO_DCN42 = dcn42_dio_link_encoder.o dcn42_dio_stream_encoder.o + +AMD_DAL_DIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/dio/dcn42/,$(DIO_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c new file mode 100644 index 0000000000000..edcf4e67483bb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#include "dc_hw_types.h" +#include "dm_services.h" +#include "reg_helper.h" +#include "dcn10_dio.h" + +#define CTX \ + dio10->base.ctx +#define REG(reg)\ + dio10->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + dio10->shifts->field_name, dio10->masks->field_name + +static void dcn10_dio_mem_pwr_ctrl(struct dio *dio, bool enable_i2c_light_sleep) +{ + struct dcn10_dio *dio10 = TO_DCN10_DIO(dio); + + /* power AFMT HDMI memory */ + REG_WRITE(DIO_MEM_PWR_CTRL, 0); + + if (enable_i2c_light_sleep) + REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); +} + +static const struct dio_funcs dcn10_dio_funcs = { + .mem_pwr_ctrl = dcn10_dio_mem_pwr_ctrl, +}; + +void dcn10_dio_construct( + struct dcn10_dio *dio10, + struct dc_context *ctx, + const struct dcn_dio_registers *regs, + const struct dcn_dio_shift *shifts, + const struct dcn_dio_mask *masks) +{ + dio10->base.ctx = ctx; + dio10->base.funcs = &dcn10_dio_funcs; + + dio10->regs = regs; + dio10->shifts = shifts; + dio10->masks = masks; +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h new file mode 100644 index 0000000000000..369c5996326eb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_dio.h @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef __DCN10_DIO_H__ +#define __DCN10_DIO_H__ + +#include "dio.h" + +#define TO_DCN10_DIO(dio_base) \ + container_of(dio_base, struct dcn10_dio, base) + +#define DIO_REG_LIST_DCN10()\ + SR(DIO_MEM_PWR_CTRL) + +struct dcn_dio_registers { + uint32_t DIO_MEM_PWR_CTRL; +}; + +struct dcn_dio_shift { + uint8_t I2C_LIGHT_SLEEP_FORCE; +}; + +struct dcn_dio_mask { + uint32_t I2C_LIGHT_SLEEP_FORCE; +}; + +struct dcn10_dio { + struct dio base; + const struct dcn_dio_registers *regs; + const struct dcn_dio_shift *shifts; + const struct dcn_dio_mask *masks; +}; + +void dcn10_dio_construct( + struct dcn10_dio *dio10, + struct dc_context *ctx, + const struct dcn_dio_registers *regs, + const struct dcn_dio_shift *shifts, + const struct dcn_dio_mask *masks); + +#endif /* __DCN10_DIO_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c index 1c12281164877..13e14aad3daac 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c @@ -88,8 +88,11 @@ static const struct link_encoder_funcs dcn10_lnk_enc_funcs = { .get_dig_mode = dcn10_get_dig_mode, .destroy = dcn10_link_encoder_destroy, .get_max_link_cap = dcn10_link_encoder_get_max_link_cap, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; + static enum bp_result link_transmitter_control( struct dcn10_link_encoder *enc10, struct bp_transmitter_control *cntl) @@ -682,6 +685,7 @@ void dcn10_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; @@ -873,6 +877,11 @@ void dcn10_link_encoder_hw_init( void dcn10_link_encoder_destroy(struct link_encoder **enc) { + if ((*enc)->hpd_gpio) { + dal_gpio_destroy_irq(&(*enc)->hpd_gpio); + (*enc)->hpd_gpio = NULL; + } + kfree(TO_DCN10_LINK_ENC(*enc)); *enc = NULL; } @@ -1472,3 +1481,37 @@ void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc, *link_settings = max_link_cap; } + +bool dcn10_get_hpd_state(struct link_encoder *enc) +{ + uint32_t state = 0; + + if (!enc->hpd_gpio) + return false; + + dal_gpio_lock_pin(enc->hpd_gpio); + dal_gpio_get_value(enc->hpd_gpio, &state); + dal_gpio_unlock_pin(enc->hpd_gpio); + + return state; +} + +bool dcn10_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms) +{ + /* Setup HPD filtering */ + if (enc->hpd_gpio && dal_gpio_lock_pin(enc->hpd_gpio) == GPIO_RESULT_OK) { + struct gpio_hpd_config config; + + config.delay_on_connect = delay_on_connect_in_ms; + config.delay_on_disconnect = delay_on_disconnect_in_ms; + + dal_irq_setup_hpd_filter(enc->hpd_gpio, &config); + + dal_gpio_unlock_pin(enc->hpd_gpio); + + return true; + } else { + ASSERT(0); + return false; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h index b7a89c39f4459..eedbd5d2756e4 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h @@ -79,6 +79,8 @@ struct dcn10_link_enc_aux_registers { struct dcn10_link_enc_hpd_registers { uint32_t DC_HPD_CONTROL; + uint32_t DC_HPD_INT_STATUS; + uint32_t DC_HPD_TOGGLE_FILT_CNTL; }; struct dcn10_link_enc_registers { @@ -274,7 +276,10 @@ struct dcn10_link_enc_registers { type TMDS_CTL0;\ type AUX_HPD_SEL;\ type AUX_LS_READ_EN;\ - type AUX_RX_RECEIVE_WINDOW + type AUX_RX_RECEIVE_WINDOW;\ + type DC_HPD_SENSE;\ + type DC_HPD_CONNECT_INT_DELAY;\ + type DC_HPD_DISCONNECT_INT_DELAY #define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \ @@ -656,4 +661,8 @@ enum signal_type dcn10_get_dig_mode( void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc, struct dc_link_settings *link_settings); + +bool dcn10_get_hpd_state(struct link_encoder *enc); +bool dcn10_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); + #endif /* __DC_LINK_ENCODER__DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h index 54a6a4ebd6363..7553675065563 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -190,6 +190,7 @@ struct dcn10_stream_enc_registers { uint32_t DIG_FE_CLK_CNTL; uint32_t DIG_FE_EN_CNTL; uint32_t STREAM_MAPPER_CONTROL; + uint32_t DIG_FE_AUDIO_CNTL; }; @@ -598,6 +599,11 @@ struct dcn10_stream_enc_registers { type DP_VID_N_INTERVAL;\ type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;\ type DP_STEER_FIFO_ENABLE + +#define SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(type) \ + type DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\ + type APG_CLOCK_ENABLE + struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN1_0(uint8_t); uint8_t HDMI_ACP_SEND; @@ -606,6 +612,7 @@ struct dcn10_stream_encoder_shift { SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t); SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t); SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t); + SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t); }; struct dcn10_stream_encoder_mask { @@ -616,6 +623,7 @@ struct dcn10_stream_encoder_mask { SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t); SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t); SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t); + SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t); }; struct dcn10_stream_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index 51a57dae18114..7d22618f90d2d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -194,7 +194,7 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } - + /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -384,6 +384,8 @@ static const struct link_encoder_funcs dcn20_link_enc_funcs = { .get_dig_frontend = dcn10_get_dig_frontend, .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn20_link_encoder_construct( @@ -405,6 +407,7 @@ void dcn20_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index bec0b4aaeb2b9..c29c8f33d2167 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } - /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index b8e31b5ea1140..57b9ae5fca1dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -84,6 +84,8 @@ static const struct link_encoder_funcs dcn30_link_enc_funcs = { .get_dig_mode = dcn10_get_dig_mode, .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn30_link_encoder_construct( @@ -105,6 +107,7 @@ void dcn30_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index 1b39a6e8a1ac5..47d84a2a48ce8 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -73,6 +73,8 @@ static const struct link_encoder_funcs dcn301_link_enc_funcs = { .get_dig_mode = dcn10_get_dig_mode, .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn301_link_encoder_construct( @@ -94,6 +96,7 @@ void dcn301_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 84cc2ddc52fe8..07d362ef0daf3 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -276,6 +276,8 @@ static const struct link_encoder_funcs dcn31_link_enc_funcs = { .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn31_link_encoder_get_max_link_cap, .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn31_link_encoder_construct( @@ -297,6 +299,7 @@ void dcn31_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 3e85e9c3d2cb2..20fbddf074c50 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -466,9 +466,7 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .set_avmute = enc1_stream_encoder_set_avmute, .dig_connect_to_otg = enc1_dig_connect_to_otg, .dig_source_otg = enc1_dig_source_otg, - .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, - .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index 06907e8a4eda1..65d28cb07b046 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -188,9 +188,18 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, if (!query_dp_alt_from_dmub(enc, &cmd)) return; - if (cmd.query_dp_alt.data.is_usb && - cmd.query_dp_alt.data.is_dp4 == 0) - link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); + /* + * USB-C DisplayPort Alt Mode lane count limitation logic: + * When USB and DP share the same USB-C connector, hardware must allocate + * some lanes for USB data, limiting DP to maximum 2 lanes instead of 4. + * This ensures USB functionality remains available while DP is active. + */ + if (cmd.query_dp_alt.data.is_dp_alt_disable == 0 && + cmd.query_dp_alt.data.is_usb && + cmd.query_dp_alt.data.is_dp4 == 0) { + link_settings->lane_count = + MIN(LANE_COUNT_TWO, link_settings->lane_count); + } } @@ -224,6 +233,8 @@ static const struct link_encoder_funcs dcn32_link_enc_funcs = { .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn32_link_encoder_construct( @@ -245,6 +256,7 @@ void dcn32_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index 2ed382a8e79c6..968f89295b64c 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -89,6 +89,8 @@ static const struct link_encoder_funcs dcn321_link_enc_funcs = { .is_in_alt_mode = dcn20_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn20_link_encoder_get_max_link_cap, .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn321_link_encoder_construct( @@ -110,6 +112,7 @@ void dcn321_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c index 9972911330b65..20bf04dac609a 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn35/dcn35_dio_link_encoder.c @@ -120,7 +120,6 @@ void dcn35_link_encoder_setup( void dcn35_link_encoder_init(struct link_encoder *enc) { enc31_hw_init(enc); - dcn35_link_encoder_set_fgcg(enc, enc->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dio); } void dcn35_link_encoder_set_fgcg(struct link_encoder *enc, bool enable) @@ -162,6 +161,8 @@ static const struct link_encoder_funcs dcn35_link_enc_funcs = { .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, .enable_dpia_output = dcn35_link_encoder_enable_dpia_output, .disable_dpia_output = dcn35_link_encoder_disable_dpia_output, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn35_link_encoder_construct( @@ -183,6 +184,7 @@ void dcn35_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c index 7e558ca195ef0..e1f0a1bf10756 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_link_encoder.c @@ -215,6 +215,8 @@ static const struct link_encoder_funcs dcn401_link_enc_funcs = { .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .get_hpd_state = dcn10_get_hpd_state, + .program_hpd_filter = dcn10_program_hpd_filter, }; void dcn401_link_encoder_construct( @@ -236,6 +238,7 @@ void dcn401_link_encoder_construct( enc10->base.ctx = init_data->ctx; enc10->base.id = init_data->encoder; + enc10->base.hpd_gpio = init_data->hpd_gpio; enc10->base.hpd_source = init_data->hpd_source; enc10->base.connector = init_data->connector; diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c new file mode 100644 index 0000000000000..35dfe3bb0c555 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" + +#include "core_types.h" +#include "link_encoder.h" +#include "dcn35/dcn35_dio_link_encoder.h" +#include "dcn42_dio_link_encoder.h" + +#ifndef MIN +#define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) +#endif + +#define CTX \ + enc10->base.ctx +#define DC_LOGGER \ + enc10->base.ctx->logger + +#define REG(reg)\ + (enc10->link_regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc10->link_shift->field_name, enc10->link_mask->field_name + +#define HPD_REG(reg)\ + (enc10->hpd_regs->reg) + +#define HPD_REG_GET(reg_name, field, val) \ + generic_reg_get(CTX, HPD_REG(reg_name), \ + FN(reg_name, field), val) + +#define HPD_REG_SET_N(reg_name, n, initial_val, ...) \ + generic_reg_set_ex(CTX, \ + HPD_REG(reg_name), \ + initial_val, \ + n, __VA_ARGS__) + +#define HPD_REG_SET_2(reg, init_value, f1, v1, f2, v2) \ + HPD_REG_SET_N(reg, 2, init_value, \ + FN(reg, f1), v1,\ + FN(reg, f2), v2) + +bool dcn42_get_hpd_state(struct link_encoder *enc) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + uint32_t state; + + HPD_REG_GET(DC_HPD_INT_STATUS, DC_HPD_SENSE, &state); + + return state; +} + +bool dcn42_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms) +{ + struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); + + HPD_REG_SET_2(DC_HPD_TOGGLE_FILT_CNTL, 0, + DC_HPD_CONNECT_INT_DELAY, delay_on_connect_in_ms, + DC_HPD_DISCONNECT_INT_DELAY, delay_on_disconnect_in_ms); + + return true; +} + +static const struct link_encoder_funcs dcn42_link_enc_funcs = { + .read_state = link_enc2_read_state, + .validate_output_with_stream = + dcn30_link_encoder_validate_output_with_stream, + .hw_init = dcn35_link_encoder_init, + .setup = dcn35_link_encoder_setup, + .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, + .enable_dp_output = dcn35_link_encoder_enable_dp_output, + .enable_dp_mst_output = dcn35_link_encoder_enable_dp_mst_output, + .disable_output = dcn35_link_encoder_disable_output, + .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, + .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, + .update_mst_stream_allocation_table = + dcn10_link_encoder_update_mst_stream_allocation_table, + .psr_program_dp_dphy_fast_training = + dcn10_psr_program_dp_dphy_fast_training, + .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, + .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, + .enable_hpd = dcn10_link_encoder_enable_hpd, + .disable_hpd = dcn10_link_encoder_disable_hpd, + .is_dig_enabled = dcn35_is_dig_enabled, + .destroy = dcn10_link_encoder_destroy, + .fec_set_enable = enc2_fec_set_enable, + .fec_set_ready = enc2_fec_set_ready, + .fec_is_active = enc2_fec_is_active, + .get_dig_frontend = dcn10_get_dig_frontend, + .get_dig_mode = dcn401_get_dig_mode, + .is_in_alt_mode = dcn32_link_encoder_is_in_alt_mode, + .get_max_link_cap = dcn32_link_encoder_get_max_link_cap, + .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux, + .enable_dpia_output = dcn35_link_encoder_enable_dpia_output, + .disable_dpia_output = dcn35_link_encoder_disable_dpia_output, + .get_hpd_state = dcn42_get_hpd_state, + .program_hpd_filter = dcn42_program_hpd_filter, +}; + +void dcn42_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask) +{ + struct bp_connector_speed_cap_info bp_cap_info = {0}; + const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; + enum bp_result result = BP_RESULT_OK; + struct dcn10_link_encoder *enc10 = &enc20->enc10; + + enc10->base.funcs = &dcn42_link_enc_funcs; + enc10->base.ctx = init_data->ctx; + enc10->base.id = init_data->encoder; + + enc10->base.hpd_source = init_data->hpd_source; + enc10->base.connector = init_data->connector; + + + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + + enc10->base.features = *enc_features; + if (enc10->base.connector.id == CONNECTOR_ID_USBC) + enc10->base.features.flags.bits.DP_IS_USB_C = 1; + + enc10->base.transmitter = init_data->transmitter; + + /* set the flag to indicate whether driver poll the I2C data pin + * while doing the DP sink detect + */ + +/* if (dal_adapter_service_is_feature_supported(as, + FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) + enc10->base.features.flags.bits. + DP_SINK_DETECT_POLL_DATA_PIN = true;*/ + + enc10->base.output_signals = + SIGNAL_TYPE_DVI_SINGLE_LINK | + SIGNAL_TYPE_DVI_DUAL_LINK | + SIGNAL_TYPE_LVDS | + SIGNAL_TYPE_DISPLAY_PORT | + SIGNAL_TYPE_DISPLAY_PORT_MST | + SIGNAL_TYPE_EDP | + SIGNAL_TYPE_HDMI_TYPE_A; + + enc10->link_regs = link_regs; + enc10->aux_regs = aux_regs; + enc10->hpd_regs = hpd_regs; + enc10->link_shift = link_shift; + enc10->link_mask = link_mask; + + switch (enc10->base.transmitter) { + case TRANSMITTER_UNIPHY_A: + enc10->base.preferred_engine = ENGINE_ID_DIGA; + break; + case TRANSMITTER_UNIPHY_B: + enc10->base.preferred_engine = ENGINE_ID_DIGB; + break; + case TRANSMITTER_UNIPHY_C: + enc10->base.preferred_engine = ENGINE_ID_DIGC; + break; + case TRANSMITTER_UNIPHY_D: + enc10->base.preferred_engine = ENGINE_ID_DIGD; + break; + case TRANSMITTER_UNIPHY_E: + enc10->base.preferred_engine = ENGINE_ID_DIGE; + break; + default: + ASSERT_CRITICAL(false); + enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; + } + + /* default to one to mirror Windows behavior */ + enc10->base.features.flags.bits.HDMI_6GB_EN = 1; + + if (bp_funcs->get_connector_speed_cap_info) + result = bp_funcs->get_connector_speed_cap_info(enc10->base.ctx->dc_bios, + enc10->base.connector, &bp_cap_info); + + /* Override features with DCE-specific values */ + if (result == BP_RESULT_OK) { + enc10->base.features.flags.bits.IS_HBR2_CAPABLE = + bp_cap_info.DP_HBR2_EN; + enc10->base.features.flags.bits.IS_HBR3_CAPABLE = + bp_cap_info.DP_HBR3_EN; + enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; + enc10->base.features.flags.bits.IS_DP2_CAPABLE = 1; + enc10->base.features.flags.bits.IS_UHBR10_CAPABLE = bp_cap_info.DP_UHBR10_EN; + enc10->base.features.flags.bits.IS_UHBR13_5_CAPABLE = bp_cap_info.DP_UHBR13_5_EN; + enc10->base.features.flags.bits.IS_UHBR20_CAPABLE = bp_cap_info.DP_UHBR20_EN; + } else { + DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", + __func__, + result); + } + if (enc10->base.ctx->dc->debug.hdmi20_disable) { + enc10->base.features.flags.bits.HDMI_6GB_EN = 0; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h new file mode 100644 index 0000000000000..4b5a9594f2790 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DC_LINK_ENCODER__DCN42_H__ +#define __DC_LINK_ENCODER__DCN42_H__ + +#include "dcn401/dcn401_dio_link_encoder.h" + +#define LINK_ENCODER_MASK_SH_LIST_DCN42(mask_sh) \ + LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_BE_ENABLE, mask_sh),\ + LE_SF(DIG0_DIG_BE_CNTL, DIG_RB_SWITCH_EN, mask_sh),\ + LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ + LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_MODE, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_CLK_EN, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SOFT_RESET, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, HDCP_SOFT_RESET, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_CLOCK_ON, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_HDCP_CLOCK_ON, mask_sh),\ + LE_SF(DIG0_DIG_BE_CLK_CNTL, DIG_BE_SYMCLK_G_TMDS_CLOCK_ON, mask_sh),\ + LE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ + LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ + LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ + LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ + LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ + LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ + LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ + LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ + LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ + LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ + LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ + LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ + LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ + LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ + LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ + LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ + LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ + LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ + LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ + LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ + LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ + LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh),\ + LE_SF(HPD0_DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\ + LE_SF(HPD0_DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\ + LE_SF(HPD0_DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_EN, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, mask_sh),\ + LE_SF(DP0_DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, mask_sh),\ + LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_START_WINDOW, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_HALF_SYM_DETECT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_TRANSITION_FILTER_EN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_START, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_ALLOW_BELOW_THRESHOLD_STOP, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_PHASE_DETECT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_DETECTION_THRESHOLD, mask_sh), \ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_TX_PRECHARGE_SYMBOLS, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_TX_CONTROL, AUX_MODE_DET_CHECK_DELAY, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_PRECHARGE_SKIP, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, mask_sh),\ + LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN_MUL, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DISPCLK_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DISPCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, REFCLK_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, REFCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SOCCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_FE_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_FE_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_R_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLK_G_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DIO_FGCG_REP_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, DISPCLK_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKA_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKB_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\ + LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh) + +void dcn42_link_encoder_construct( + struct dcn20_link_encoder *enc20, + const struct encoder_init_data *init_data, + const struct encoder_feature_support *enc_features, + const struct dcn10_link_enc_registers *link_regs, + const struct dcn10_link_enc_aux_registers *aux_regs, + const struct dcn10_link_enc_hpd_registers *hpd_regs, + const struct dcn10_link_enc_shift *link_shift, + const struct dcn10_link_enc_mask *link_mask); + +bool dcn42_get_hpd_state(struct link_encoder *enc); +bool dcn42_program_hpd_filter(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); + +#endif /* __DC_LINK_ENCODER__DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c new file mode 100644 index 0000000000000..65afbfcaa96b0 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c @@ -0,0 +1,522 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dc_bios_types.h" +#include "dcn30/dcn30_dio_stream_encoder.h" +#include "dcn32/dcn32_dio_stream_encoder.h" +#include "dcn35/dcn35_dio_stream_encoder.h" +#include "dcn401/dcn401_dio_stream_encoder.h" +#include "dcn31/dcn31_apg.h" + +#include "dcn42_dio_stream_encoder.h" +#include "reg_helper.h" +#include "hw_shared.h" +#include "link_service.h" +#include "dpcd_defs.h" + +#define DC_LOGGER \ + enc1->base.ctx->logger + +#define REG(reg)\ + (enc1->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc1->se_shift->field_name, enc1->se_mask->field_name + +#define VBI_LINE_0 0 +#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 + +#define CTX \ + enc1->base.ctx + +/* setup stream encoder in hdmi mode */ +static void enc42_stream_encoder_hdmi_set_stream_attribute( + struct stream_encoder *enc, + struct dc_crtc_timing *crtc_timing, + int actual_pix_clk_khz, + bool enable_audio) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { + struct bp_encoder_control cntl = {0}; + + cntl.action = ENCODER_CONTROL_SETUP; + cntl.engine_id = enc1->base.id; + cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; + cntl.enable_dp_audio = enable_audio; + cntl.pixel_clock = actual_pix_clk_khz; + cntl.lanes_number = LANE_COUNT_FOUR; + + if (enc1->base.bp->funcs->encoder_control( + enc1->base.bp, &cntl) != BP_RESULT_OK) + return; + + } else { + + //Set pattern for clock channel, default vlue 0x63 does not work + REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F); + + //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup + + //DIG_SOURCE_SELECT is already set in dig_connect_to_otg + + /* DIG_START is removed from the register spec */ + } + + /* Configure pixel encoding */ + enc401_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); + + /* setup HDMI engine */ + REG_UPDATE_4(HDMI_CONTROL, + HDMI_DEEP_COLOR_ENABLE, 0, + HDMI_DATA_SCRAMBLE_EN, 0, + HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1, + HDMI_CLOCK_CHANNEL_RATE, 0); + + /* Configure color depth */ + switch (crtc_timing->display_color_depth) { + case COLOR_DEPTH_888: + REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); + break; + case COLOR_DEPTH_101010: + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 1, + HDMI_DEEP_COLOR_ENABLE, 1); + } + break; + case COLOR_DEPTH_121212: + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 0); + } else { + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 2, + HDMI_DEEP_COLOR_ENABLE, 1); + } + break; + case COLOR_DEPTH_161616: + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DEEP_COLOR_DEPTH, 3, + HDMI_DEEP_COLOR_ENABLE, 1); + break; + default: + break; + } + + if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { + /* enable HDMI data scrambler + * HDMI_CLOCK_CHANNEL_RATE_MORE_340M + * Clock channel frequency is 1/4 of character rate. + */ + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DATA_SCRAMBLE_EN, 1, + HDMI_CLOCK_CHANNEL_RATE, 1); + } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { + + /* TODO: New feature for DCE11, still need to implement */ + + /* enable HDMI data scrambler + * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE + * Clock channel frequency is the same + * as character rate + */ + REG_UPDATE_2(HDMI_CONTROL, + HDMI_DATA_SCRAMBLE_EN, 1, + HDMI_CLOCK_CHANNEL_RATE, 0); + } + + /* Enable transmission of General Control packet on every frame */ + REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, + HDMI_GC_CONT, 1, + HDMI_GC_SEND, 1, + HDMI_NULL_SEND, 1); + + /* Disable Audio Content Protection packet transmission */ + REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0); + /* following belongs to audio */ + /* Enable Audio InfoFrame packet transmission. */ + REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); + + /* Select line number on which to send Audio InfoFrame packets */ + REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_LINE, + VBI_LINE_0 + 2); + + /* set HDMI GC AVMUTE */ + REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); +} + +static void enc42_stream_encoder_stop_dp_info_packets( + struct stream_encoder *enc) +{ + /* stop generic packets on DP */ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t value = 0; + + REG_SET_9(DP_SEC_CNTL, 0, + DP_SEC_GSP0_ENABLE, 0, + DP_SEC_GSP1_ENABLE, 0, + DP_SEC_GSP2_ENABLE, 0, + DP_SEC_GSP3_ENABLE, 0, + DP_SEC_GSP4_ENABLE, 0, + DP_SEC_GSP5_ENABLE, 0, + DP_SEC_GSP6_ENABLE, 0, + DP_SEC_GSP7_ENABLE, 0, + DP_SEC_STREAM_ENABLE, 0); + + /* this register shared with audio info frame. + * therefore we need to keep master enabled + * if at least one of the fields is not 0 + */ + value = REG_READ(DP_SEC_CNTL); + if (value) + REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); +} + +static void enc42_stream_encoder_update_hdmi_info_packets( + struct stream_encoder *enc, + const struct encoder_info_frame *info_frame) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); + REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, 1); + + /*Always add mandatory packets first followed by optional ones*/ + enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi); + enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif); + enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); + enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); + enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd); + enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); + enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem); +} + +static void enc42_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps, + bool immediate_update) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + if (enable) { + struct dc_info_packet pps_sdp; + int i; + + /* Configure for PPS packet size (128 bytes) */ + REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1); + + /* Load PPS into infoframe (SDP) registers */ + pps_sdp.valid = true; + pps_sdp.hb0 = 0; + pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; + pps_sdp.hb2 = 127; + pps_sdp.hb3 = 0; + + for (i = 0; i < 4; i++) { + memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32); + enc1->base.vpg->funcs->update_generic_info_packet( + enc1->base.vpg, + 11 + i, + &pps_sdp, + immediate_update); + } + + /* SW should make sure VBID[6] update line number is bigger + * than PPS transmit line number + */ + REG_UPDATE(DP_GSP11_CNTL, + DP_SEC_GSP11_LINE_NUM, 2); + REG_UPDATE_2(DP_MSA_VBID_MISC, + DP_VBID6_LINE_REFERENCE, 0, + DP_VBID6_LINE_NUM, 3); + + /* Send PPS data at the line number specified above. + * DP spec requires PPS to be sent only when it changes, however since + * decoder has to be able to handle its change on every frame, we're + * sending it always (i.e. on every frame) to reduce the chance it'd be + * missed by decoder. If it turns out required to send PPS only when it + * changes, we can use DP_SEC_GSP11_SEND register. + */ + REG_UPDATE(DP_GSP11_CNTL, + DP_SEC_GSP11_ENABLE, 1); + REG_UPDATE(DP_SEC_CNTL, + DP_SEC_STREAM_ENABLE, 1); + } else { + /* Disable Generic Stream Packet 11 (GSP) transmission */ + REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0); + REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0); + } +} + +static void enc42_se_dp_audio_setup( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + enc42_se_enable_audio_clock(enc, true); + + REG_UPDATE(DIG_FE_AUDIO_CNTL, + DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst); + + enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info); +} + +#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 +#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 + +static void enc42_se_setup_dp_audio( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + /* --- DP Audio packet configurations --- */ + + /* ATP Configuration */ + REG_SET(DP_SEC_AUD_N, 0, + DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); + + /* Async/auto-calc timestamp mode */ + REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, + DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); +} + +static void enc42_se_dp_audio_enable( + struct stream_encoder *enc) +{ + ASSERT (enc->apg); + enc42_se_enable_audio_clock(enc, true); + /*APG_CONTROL2 for DP*/ + enc42_se_setup_dp_audio(enc); + /*DP_SEC_CNTL programming*/ + enc1_se_enable_dp_audio(enc); + /*APG_en*/ + enc->apg->funcs->enable_apg(enc->apg); + +} + +static void enc42_se_disable_dp_audio( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t value = 0; + + /* Disable Audio packets */ + REG_UPDATE_5(DP_SEC_CNTL, + DP_SEC_ASP_ENABLE, 0, + DP_SEC_ATP_ENABLE, 0, + DP_SEC_AIP_ENABLE, 0, + DP_SEC_ACM_ENABLE, 0, + DP_SEC_STREAM_ENABLE, 0); + + /* This register shared with encoder info frame. Therefore we need to + * keep master enabled if at least on of the fields is not 0 + */ + value = REG_READ(DP_SEC_CNTL); + if (value != 0) + REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); +} + +static void enc42_se_dp_audio_disable( + struct stream_encoder *enc) +{ + + enc->apg->funcs->disable_apg(enc->apg); + enc42_se_disable_dp_audio(enc); + enc42_se_enable_audio_clock(enc, false); +} + +static void enc42_se_setup_hdmi_audio( + struct stream_encoder *enc, + const struct audio_crtc_info *crtc_info) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + struct audio_clock_info audio_clock_info = {0}; + + /* HDMI_AUDIO_PACKET_CONTROL */ + REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, + HDMI_AUDIO_DELAY_EN, 1); + + /* HDMI_ACR_PACKET_CONTROL */ + REG_UPDATE_2(HDMI_ACR_PACKET_CONTROL, + HDMI_ACR_AUTO_SEND, 1, + HDMI_ACR_SOURCE, 0); + + /* Program audio clock sample/regeneration parameters */ + get_audio_clock_info(crtc_info->color_depth, + crtc_info->requested_pixel_clock_100Hz, + crtc_info->calculated_pixel_clock_100Hz, + &audio_clock_info); + DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d" \ + "calculated_pixel_clock_100Hz = %d\n", __func__,\ + crtc_info->requested_pixel_clock_100Hz, \ + crtc_info->calculated_pixel_clock_100Hz); + + /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ + REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); + + /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ + REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); + + /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ + REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); + + /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ + REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); + + /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ + REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); + + /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ + REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); + + /* Video driver cannot know in advance which sample rate will + * be used by HD Audio driver + * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is + * programmed below in interruppt callback + */ +} + +static void enc42_se_hdmi_audio_disable( + struct stream_encoder *enc) +{ + ASSERT (enc->apg); + enc->apg->funcs->disable_apg(enc->apg); + enc42_se_enable_audio_clock(enc, false); +} + +void enc42_se_enable_audio_clock( + struct stream_encoder *enc, + bool enable) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, !!enable); +} + + +static void enc42_se_hdmi_audio_setup( + struct stream_encoder *enc, + unsigned int az_inst, + struct audio_info *info, + struct audio_crtc_info *audio_crtc_info) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + ASSERT (enc->apg); + enc42_se_enable_audio_clock(enc, true); + /*ACR setup*/ + enc42_se_setup_hdmi_audio(enc, audio_crtc_info); + + REG_UPDATE(DIG_FE_AUDIO_CNTL, + DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst); + + /*APG_DBG_GEN_CONTROL*/ + enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info); + /*APG enable*/ + enc->apg->funcs->enable_apg(enc->apg); +} + +static void enc42_audio_mute_control( + struct stream_encoder *enc, + bool mute) +{ + if (mute) + enc->apg->funcs->disable_apg(enc->apg); + else + enc->apg->funcs->enable_apg(enc->apg); +} +void enc42_reset_hdmi_stream_attribute( + struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + + REG_UPDATE_3(HDMI_CONTROL, + HDMI_DEEP_COLOR_ENABLE, 0, + HDMI_DATA_SCRAMBLE_EN, 0, + HDMI_CLOCK_CHANNEL_RATE, 0); +} + +static const struct stream_encoder_funcs dcn42_str_enc_funcs = { + .dp_set_stream_attribute = + enc401_stream_encoder_dp_set_stream_attribute, + .hdmi_set_stream_attribute = + enc42_stream_encoder_hdmi_set_stream_attribute, + .dvi_set_stream_attribute = + enc401_stream_encoder_dvi_set_stream_attribute, + .set_throttled_vcp_size = + enc1_stream_encoder_set_throttled_vcp_size, + .update_hdmi_info_packets = + enc42_stream_encoder_update_hdmi_info_packets, + .stop_hdmi_info_packets = + enc3_stream_encoder_stop_hdmi_info_packets, + .update_dp_info_packets_sdp_line_num = + enc3_stream_encoder_update_dp_info_packets_sdp_line_num, + .update_dp_info_packets = + enc3_stream_encoder_update_dp_info_packets, + .stop_dp_info_packets = + enc42_stream_encoder_stop_dp_info_packets, + .dp_blank = + enc1_stream_encoder_dp_blank, + .dp_unblank = + enc401_stream_encoder_dp_unblank, + .audio_mute_control = enc42_audio_mute_control, + + .dp_audio_setup = enc42_se_dp_audio_setup, + .dp_audio_enable = enc42_se_dp_audio_enable, + .dp_audio_disable = enc42_se_dp_audio_disable, + + .hdmi_audio_setup = enc42_se_hdmi_audio_setup, + .hdmi_audio_disable = enc42_se_hdmi_audio_disable, + .setup_stereo_sync = enc1_setup_stereo_sync, + .set_avmute = enc1_stream_encoder_set_avmute, + .dig_connect_to_otg = enc1_dig_connect_to_otg, + .dig_source_otg = enc1_dig_source_otg, + + .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, + + .enc_read_state = enc401_read_state, + .dp_set_dsc_config = NULL, + .dp_set_dsc_pps_info_packet = enc42_dp_set_dsc_pps_info_packet, + .set_dynamic_metadata = enc401_set_dynamic_metadata, + .hdmi_reset_stream_attribute = enc42_reset_hdmi_stream_attribute, + .enable_stream = enc401_stream_encoder_enable, + + .set_input_mode = enc401_set_dig_input_mode, + .enable_fifo = enc35_enable_fifo, + .disable_fifo = enc35_disable_fifo, + .map_stream_to_link = enc401_stream_encoder_map_to_link, +}; + +void dcn42_dio_stream_encoder_construct( + struct dcn10_stream_encoder *enc1, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id, + struct vpg *vpg, + struct apg *apg, + const struct dcn10_stream_enc_registers *regs, + const struct dcn10_stream_encoder_shift *se_shift, + const struct dcn10_stream_encoder_mask *se_mask) +{ + enc1->base.funcs = &dcn42_str_enc_funcs; + enc1->base.ctx = ctx; + enc1->base.id = eng_id; + enc1->base.bp = bp; + enc1->base.vpg = vpg; + enc1->base.apg = apg; + enc1->regs = regs; + enc1->se_shift = se_shift; + enc1->se_mask = se_mask; + enc1->base.stream_enc_inst = vpg->inst; +} diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h new file mode 100644 index 0000000000000..7a98fee46081f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 - Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_DIO_STREAM_ENCODER_DCN42_H__ +#define __DC_DIO_STREAM_ENCODER_DCN42_H__ + +#include "dcn30/dcn30_vpg.h" +#include "stream_encoder.h" +#include "dcn20/dcn20_stream_encoder.h" + +#define SE_COMMON_MASK_SH_LIST_DCN42(mask_sh)\ + SE_SF(DP0_DP_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_FORMAT, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, COMPRESSED_PIXEL_FORMAT, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ + SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ + SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ + SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ + SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(DIG1_HDMI_CONTROL, TMDS_PIXEL_ENCODING, mask_sh),\ + SE_SF(DIG1_HDMI_CONTROL, TMDS_COLOR_FORMAT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP11_PPS, mask_sh),\ + SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, mask_sh),\ + SE_SF(DP0_DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, mask_sh),\ + SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ + SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_N_INTERVAL, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh), \ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC2_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC3_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC4_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC5_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC6_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC7_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC8_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC9_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC10_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC11_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC12_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC13_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL6, HDMI_GENERIC14_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC0_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL1, HDMI_GENERIC1_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC2_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL2, HDMI_GENERIC3_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC4_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL3, HDMI_GENERIC5_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC6_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL4, HDMI_GENERIC7_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC8_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL7, HDMI_GENERIC9_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC10_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL8, HDMI_GENERIC11_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC12_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL9, HDMI_GENERIC13_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL10, HDMI_GENERIC14_LINE, mask_sh),\ + SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_ENGINE_EN, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_HUBP_REQUESTOR_ID, mask_sh),\ + SE_SF(DME0_DME_CONTROL, METADATA_STREAM_TYPE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ + SE_SF(DP0_DP_SEC_METADATA_TRANSMISSION, DP_SEC_METADATA_PACKET_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE_REFERENCE, mask_sh),\ + SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, DOLBY_VISION_EN, mask_sh),\ + SE_SF(DIG0_DIG_FE_EN_CNTL, DIG_FE_ENABLE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_MODE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_CLK_EN, mask_sh),\ + SE_SF(DIG0_DIG_FE_CLK_CNTL, DIG_FE_SOFT_RESET, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\ + SE_SF(DP0_DP_SEC_FRAMING4, DP_SST_SDP_SPLITTING, mask_sh),\ + SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET, mask_sh),\ + SE_SF(DIG0_DIG_FIFO_CTRL0, DIG_FIFO_RESET_DONE, mask_sh),\ + SE_SF(DIG0_STREAM_MAPPER_CONTROL, DIG_STREAM_LINK_TARGET, mask_sh),\ + SE_SF(DIG0_DIG_FE_AUDIO_CNTL, DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, mask_sh),\ + SE_SF(DIG0_DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, mask_sh) + +void dcn42_dio_stream_encoder_construct( + struct dcn10_stream_encoder *enc1, + struct dc_context *ctx, + struct dc_bios *bp, + enum engine_id eng_id, + struct vpg *vpg, + struct apg *apg, + const struct dcn10_stream_enc_registers *regs, + const struct dcn10_stream_encoder_shift *se_shift, + const struct dcn10_stream_encoder_mask *se_mask); + +void enc42_se_enable_audio_clock( + struct stream_encoder *enc, + bool enable); + +void enc42_reset_hdmi_stream_attribute( + struct stream_encoder *enc); +#endif /* __DC_DIO_STREAM_ENCODER_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c index 1d226e0519a56..2655bc194a359 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.c @@ -128,5 +128,3 @@ bool virtual_link_encoder_construct( return true; } - - diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.h rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_link_encoder.h diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c similarity index 99% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c index ad088d70e1893..c5d2e9404d943 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.c @@ -171,4 +171,3 @@ struct stream_encoder *virtual_stream_encoder_create( kfree(enc); return NULL; } - diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.h similarity index 100% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.h rename to drivers/gpu/drm/amd/display/dc/dio/virtual/virtual_stream_encoder.h diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 9d160b39e8c5a..2818df555e627 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -197,6 +197,7 @@ void dm_set_phyd32clk(struct dc_context *ctx, int freq_khz); bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable); +void dm_helpers_dmu_timeout(struct dc_context *ctx); void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigned int param, unsigned int timeout_us); // 0x1 = Result_OK, 0xFE = Result_UnkmownCmd, 0x0 = Status_Busy @@ -208,7 +209,7 @@ void dm_helpers_init_panel_settings( struct dc_sink *sink); void dm_helpers_override_panel_settings( struct dc_context *ctx, - struct dc_panel_config *config); + struct dc_link *link); int dm_helper_dmub_aux_transfer_sync( struct dc_context *ctx, const struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 268b5fbdb48bd..e6883e2f0c325 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -24,9 +24,49 @@ # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. - +# +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml_ccflags := $(dml_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml_ccflags := -mfpu=64 +dml_rcflags := -msoft-float +endif + +include $(src)/../dkms/Makefile.compiler + +ifdef CONFIG_CC_IS_GCC +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml_ccflags += -mpreferred-stack-boundary=4 +else +dml_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index cd8cca6514196..48905ca39b706 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -5304,7 +5304,7 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( double LinesInDETC; unsigned int LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX]; unsigned int LinesInDETCRoundedDownToSwath; - double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; + double FullDETBufferingTimeY[DC__NUM_DPP__MAX] = { 0 }; double FullDETBufferingTimeC; double ActiveDRAMClockChangeLatencyMarginY; double ActiveDRAMClockChangeLatencyMarginC; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index 0748ef36a16a2..19b142412a84b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -459,8 +459,8 @@ void dml32_CalculateSwathAndDETConfiguration( { unsigned int MaximumSwathHeightY[DC__NUM_DPP__MAX]; unsigned int MaximumSwathHeightC[DC__NUM_DPP__MAX]; - unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX]; - unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX]; + unsigned int RoundedUpMaxSwathSizeBytesY[DC__NUM_DPP__MAX] = { 0 }; + unsigned int RoundedUpMaxSwathSizeBytesC[DC__NUM_DPP__MAX] = { 0 }; unsigned int RoundedUpSwathSizeBytesY; unsigned int RoundedUpSwathSizeBytesC; double SwathWidthdoubleDPP[DC__NUM_DPP__MAX]; @@ -2988,7 +2988,7 @@ void dml32_UseMinimumDCFCLK( for (j = 0; j <= 1; ++j) { double PixelDCFCLKCyclesRequiredInPrefetch[DC__NUM_DPP__MAX]; double PrefetchPixelLinesTime[DC__NUM_DPP__MAX]; - double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX]; + double DCFCLKRequiredForPeakBandwidthPerSurface[DC__NUM_DPP__MAX] = { 0 }; double DynamicMetadataVMExtraLatency[DC__NUM_DPP__MAX]; double MinimumTWait = 0.0; double DPTEBandwidth; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c index 817a370e80a77..8a177d5ae213e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c @@ -164,8 +164,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = { }, }, .num_states = 5, - .sr_exit_time_us = 28.0, - .sr_enter_plus_exit_time_us = 30.0, + .sr_exit_time_us = 31.0, + .sr_enter_plus_exit_time_us = 33.0, .sr_exit_z8_time_us = 250.0, .sr_enter_plus_exit_z8_time_us = 350.0, .fclk_change_latency_us = 24.0, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index ef75eb7d5adc3..bf01d8a9e538b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -257,4 +257,3 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } - diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile index 97e068b6bf6b6..d681d4f09850b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/Makefile @@ -24,8 +24,46 @@ # # Makefile for dml2. +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml2_ccflags := $(CC_FLAGS_FPU) dml2_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml2_ccflags := $(dml2_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml2_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml2_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml2_ccflags := -mfpu=64 +dml2_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml2_ccflags += -mpreferred-stack-boundary=4 +else +dml2_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) @@ -55,7 +93,7 @@ subdir-ccflags-y += -I$(FULL_AMD_DISPLAY_PATH)/dc/dml2_0/dml21/ CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_ccflags) $(frame_warn_flag) CFLAGS_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_ccflags) @@ -65,7 +103,7 @@ CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_ccflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_core.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/display_mode_util.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_wrapper_fpu.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_utils.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_policy.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_translation_helper.o := $(dml2_rcflags) @@ -73,7 +111,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_mall_phantom.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml_display_rq_dlg_calc.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml2_dc_resource_mgmt.o := $(dml2_rcflags) -DML2 = display_mode_core.o display_mode_util.o dml2_wrapper.o \ +DML2 = display_mode_core.o display_mode_util.o dml2_wrapper_fpu.o dml2_wrapper.o \ dml2_utils.o dml2_policy.o dml2_translation_helper.o dml2_dc_resource_mgmt.o dml2_mall_phantom.o \ dml_display_rq_dlg_calc.o @@ -90,12 +128,12 @@ CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.o := $(dml2 CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) +CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_ccflags) @@ -108,12 +146,12 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_top/dml2_top_soc15.o := $(d CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn3.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/src/dml21_wrapper.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_translation_helper.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2_0/dml21/dml21_utils.o := $(dml2_rcflags) @@ -126,6 +164,7 @@ DML21 += src/dml2_core/dml2_core_dcn4_calcs.o DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o DML21 += src/dml2_dpmm/dml2_dpmm_factory.o DML21 += src/dml2_mcg/dml2_mcg_dcn4.o +DML21 += src/dml2_mcg/dml2_mcg_dcn42.o DML21 += src/dml2_mcg/dml2_mcg_factory.o DML21 += src/dml2_pmo/dml2_pmo_dcn3.o DML21 += src/dml2_pmo/dml2_pmo_factory.o diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c index 09303c282495b..8e8935995fca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c @@ -4089,8 +4089,8 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st dml_uint_t MaximumSwathHeightC[__DML_NUM_PLANES__]; dml_uint_t RoundedUpMaxSwathSizeBytesY[__DML_NUM_PLANES__]; dml_uint_t RoundedUpMaxSwathSizeBytesC[__DML_NUM_PLANES__]; - dml_uint_t RoundedUpSwathSizeBytesY[__DML_NUM_PLANES__]; - dml_uint_t RoundedUpSwathSizeBytesC[__DML_NUM_PLANES__]; + dml_uint_t RoundedUpSwathSizeBytesY[__DML_NUM_PLANES__] = { 0 }; + dml_uint_t RoundedUpSwathSizeBytesC[__DML_NUM_PLANES__] = { 0 }; dml_uint_t SwathWidthSingleDPP[__DML_NUM_PLANES__]; dml_uint_t SwathWidthSingleDPPChroma[__DML_NUM_PLANES__]; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c index 89890c88fd66f..4022f91193ed9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c @@ -655,7 +655,7 @@ __DML_DLL_EXPORT__ void dml_print_soc_bounding_box(const struct soc_bounding_box dml_print("DML: soc_bbox: refclk_mhz = %f\n", soc->refclk_mhz); dml_print("DML: soc_bbox: amclk_mhz = %f\n", soc->amclk_mhz); - dml_print("DML: soc_bbox: max_outstanding_reqs = %f\n", soc->max_outstanding_reqs); + dml_print("DML: soc_bbox: max_outstanding_reqs = %d\n", soc->max_outstanding_reqs); dml_print("DML: soc_bbox: pct_ideal_sdp_bw_after_urgent = %f\n", soc->pct_ideal_sdp_bw_after_urgent); dml_print("DML: soc_bbox: pct_ideal_fabric_bw_after_urgent = %f\n", soc->pct_ideal_fabric_bw_after_urgent); dml_print("DML: soc_bbox: pct_ideal_dram_bw_after_urgent_pixel_only = %f\n", soc->pct_ideal_dram_bw_after_urgent_pixel_only); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c index bf5e7f4e04167..847fab5087503 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c @@ -45,6 +45,9 @@ static enum dml2_project_id dml21_dcn_revision_to_dml2_project_id(enum dce_versi case DCN_VERSION_4_01: project_id = dml2_project_dcn4x_stage2_auto_drr_svp; break; + case DCN_VERSION_4_2: + project_id = dml2_project_dcn42; + break; default: project_id = dml2_project_invalid; DC_ERR("unsupported dcn version for DML21!"); @@ -598,29 +601,31 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm plane->composition.viewport.stationary = false; - if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { + if (plane_state->cm.flags.bits.lut3d_dma_enable) { plane->tdlut.setup_for_tdlut = true; - switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.layout) { - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: + switch (plane_state->cm.lut3d_dma.swizzle) { + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: plane->tdlut.tdlut_addressing_mode = dml2_tdlut_sw_linear; break; - case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: + case CM_LUT_1D_PACKED_LINEAR: + default: plane->tdlut.tdlut_addressing_mode = dml2_tdlut_simple_linear; break; } - switch (plane_state->mcm_luts.lut3d_data.gpu_mem_params.size) { - case DC_CM2_GPU_MEM_SIZE_171717: - plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; + switch (plane_state->cm.lut3d_dma.size) { + case CM_LUT_SIZE_333333: + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_33_cube; break; - case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: + case CM_LUT_SIZE_171717: default: - //plane->tdlut.tdlut_width_mode = dml2_tdlut_width_flatten; // dml2_tdlut_width_flatten undefined + plane->tdlut.tdlut_width_mode = dml2_tdlut_width_17_cube; break; } } + plane->tdlut.setup_for_tdlut |= dml_ctx->config.force_tdlut_enable; plane->dynamic_meta_data.enable = false; @@ -734,8 +739,12 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); dml_dispcfg->gpuvm_enable = dml_ctx->config.gpuvm_enable; - dml_dispcfg->gpuvm_max_page_table_levels = 4; - dml_dispcfg->hostvm_enable = false; + if (dml_ctx->v21.dml_init.soc_bb.gpuvm_max_page_table_levels) + dml_dispcfg->gpuvm_max_page_table_levels = dml_ctx->v21.dml_init.soc_bb.gpuvm_max_page_table_levels; + else + dml_dispcfg->gpuvm_max_page_table_levels = 4; + dml_dispcfg->hostvm_enable = dml_ctx->config.hostvm_enable; + dml_dispcfg->hostvm_max_non_cached_page_table_levels = dml_ctx->v21.dml_init.soc_bb.hostvm_max_non_cached_page_table_levels; dml_dispcfg->minimize_det_reallocation = true; dml_dispcfg->overrides.enable_subvp_implicit_pmo = true; @@ -820,6 +829,9 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz; context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency; context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency; + context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period; + context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/ } static struct dml2_dchub_watermark_regs *wm_set_index_to_dc_wm_set(union dcn_watermark_set *watermarks, const enum dml2_dchub_watermark_reg_set_index wm_index) @@ -927,3 +939,31 @@ void dml21_set_dc_p_state_type( } } +void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context) +{ + unsigned int lowest_dpm_state_index = 0; + struct dc_clocks *min_clocks = &context->bw_ctx.bw.dcn.clk; + + min_clocks->dispclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dispclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->dppclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dppclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->dcfclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.dcfclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->dramclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.uclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->fclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.fclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->idle_dramclk_khz = 0; + min_clocks->idle_fclk_khz = 0; + min_clocks->dcfclk_deep_sleep_khz = 0; + min_clocks->fclk_p_state_change_support = true; + min_clocks->p_state_change_support = true; + min_clocks->dtbclk_en = false; + min_clocks->ref_dtbclk_khz = 0; + min_clocks->socclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.socclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->subvp_prefetch_dramclk_khz = 0; + min_clocks->subvp_prefetch_fclk_khz = 0; + min_clocks->phyclk_khz = in_ctx->v21.dml_init.soc_bb.clk_table.phyclk.clk_values_khz[lowest_dpm_state_index]; + min_clocks->stutter_efficiency.base_efficiency = 1; + min_clocks->stutter_efficiency.low_power_efficiency = 1; + min_clocks->stutter_efficiency.z8_stutter_efficiency = 1; + min_clocks->stutter_efficiency.z8_stutter_period = 100000; + min_clocks->zstate_support = DCN_ZSTATE_SUPPORT_ALLOW; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h index 9880d3e0398e2..f51d3d8a52c3f 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.h @@ -25,4 +25,5 @@ void dml21_map_hw_resources(struct dml2_context *dml_ctx); void dml21_get_pipe_mcache_config(struct dc_state *context, struct pipe_ctx *pipe_ctx, struct dml2_per_plane_programming *pln_prog, struct dml2_pipe_configuration_descriptor *mcache_pipe_config); void dml21_set_dc_p_state_type(struct pipe_ctx *pipe_ctx, struct dml2_per_stream_programming *stream_programming, bool sub_vp_enabled); unsigned int map_plane_to_dml21_display_cfg(const struct dml2_context *dml_ctx, unsigned int stream_id, const struct dc_plane_state *plane, const struct dc_state *context); +void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_state *context); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c index ee721606b8839..ab7ec24268bea 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c @@ -374,127 +374,136 @@ void dml21_handle_phantom_streams_planes(const struct dc *dc, struct dc_state *c dml2_map_dc_pipes(dml_ctx, context, NULL, &dml_ctx->v21.dml_to_dc_pipe_mapping, dc->current_state); } -void dml21_build_fams2_programming(const struct dc *dc, + +static unsigned int dml21_build_fams2_stream_programming_v2(const struct dc *dc, struct dc_state *context, struct dml2_context *dml_ctx) { - int i, j, k; + int dc_stream_idx, dc_plane_idx, dc_pipe_idx; unsigned int num_fams2_streams = 0; - /* reset fams2 data */ - memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); - memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); - memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES); - memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)); + for (dc_stream_idx = 0; dc_stream_idx < context->stream_count; dc_stream_idx++) { + int dml_stream_idx; + struct dc_stream_state *phantom_stream; + struct dc_stream_status *phantom_status; + enum fams2_stream_type type = 0; - if (dml_ctx->v21.mode_programming.programming->fams2_required) { - for (i = 0; i < context->stream_count; i++) { - int dml_stream_idx; - struct dc_stream_state *phantom_stream; - struct dc_stream_status *phantom_status; - enum fams2_stream_type type = 0; + union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams]; + union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams]; - union dmub_cmd_fams2_config *static_base_state = &context->bw_ctx.bw.dcn.fams2_stream_base_params[num_fams2_streams]; - union dmub_cmd_fams2_config *static_sub_state = &context->bw_ctx.bw.dcn.fams2_stream_sub_params[num_fams2_streams]; + struct dc_stream_state *stream = context->streams[dc_stream_idx]; - struct dc_stream_state *stream = context->streams[i]; + if (context->stream_status[dc_stream_idx].plane_count == 0 || + dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) { + /* can ignore blanked or phantom streams */ + continue; + } - if (context->stream_status[i].plane_count == 0 || - dml_ctx->config.svp_pstate.callbacks.get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) { - /* can ignore blanked or phantom streams */ - continue; - } + dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream->stream_id); + if (dml_stream_idx < 0) { + ASSERT(dml_stream_idx >= 0); + continue; + } - dml_stream_idx = dml21_helper_find_dml_pipe_idx_by_stream_id(dml_ctx, stream->stream_id); - if (dml_stream_idx < 0) { - ASSERT(dml_stream_idx >= 0); - continue; + /* copy static state from PMO */ + memcpy(static_base_state, + &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, + sizeof(union dmub_cmd_fams2_config)); + + memcpy(static_sub_state, + &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params, + sizeof(union dmub_cmd_fams2_config)); + + switch (dc->debug.fams_version.minor) { + case 1: + default: + type = static_base_state->stream_v1.base.type; + + /* get information from context */ + static_base_state->stream_v1.base.num_planes = context->stream_status[dc_stream_idx].plane_count; + static_base_state->stream_v1.base.otg_inst = context->stream_status[dc_stream_idx].primary_otg_inst; + + /* populate pipe masks for planes */ + for (dc_plane_idx = 0; dc_plane_idx < context->stream_status[dc_stream_idx].plane_count; dc_plane_idx++) { + for (dc_pipe_idx = 0; dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) { + if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream && + context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == stream->stream_id && + context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == context->stream_status[dc_stream_idx].plane_states[dc_plane_idx]) { + static_base_state->stream_v1.base.pipe_mask |= (1 << dc_pipe_idx); + static_base_state->stream_v1.base.plane_pipe_masks[dc_plane_idx] |= (1 << dc_pipe_idx); + } + } } + } - /* copy static state from PMO */ - memcpy(static_base_state, - &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_base_params, - sizeof(union dmub_cmd_fams2_config)); - - if (dc->debug.fams_version.major == 3) { - memcpy(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2[num_fams2_streams], - &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params_v2, - sizeof(union dmub_fams2_stream_static_sub_state_v2)); - } else { - memcpy(static_sub_state, - &dml_ctx->v21.mode_programming.programming->stream_programming[dml_stream_idx].fams2_sub_params, - sizeof(union dmub_cmd_fams2_config)); - } + + /* get per method programming */ + switch (type) { + case FAMS2_STREAM_TYPE_VBLANK: + case FAMS2_STREAM_TYPE_VACTIVE: + case FAMS2_STREAM_TYPE_DRR: + break; + case FAMS2_STREAM_TYPE_SUBVP: + phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream); + if (!phantom_stream) + break; + + phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream); + + /* phantom status should always be present */ + ASSERT(phantom_status); + if (!phantom_status) + break; switch (dc->debug.fams_version.minor) { case 1: default: - type = static_base_state->stream_v1.base.type; - - /* get information from context */ - static_base_state->stream_v1.base.num_planes = context->stream_status[i].plane_count; - static_base_state->stream_v1.base.otg_inst = context->stream_status[i].primary_otg_inst; - - /* populate pipe masks for planes */ - for (j = 0; j < context->stream_status[i].plane_count; j++) { - for (k = 0; k < dc->res_pool->pipe_count; k++) { - if (context->res_ctx.pipe_ctx[k].stream && - context->res_ctx.pipe_ctx[k].stream->stream_id == stream->stream_id && - context->res_ctx.pipe_ctx[k].plane_state == context->stream_status[i].plane_states[j]) { - static_base_state->stream_v1.base.pipe_mask |= (1 << k); - static_base_state->stream_v1.base.plane_pipe_masks[j] |= (1 << k); + static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; + + /* populate pipe masks for phantom planes */ + for (dc_plane_idx = 0; dc_plane_idx < phantom_status->plane_count; dc_plane_idx++) { + for (dc_pipe_idx = 0; dc_pipe_idx < dc->res_pool->pipe_count; dc_pipe_idx++) { + if (context->res_ctx.pipe_ctx[dc_pipe_idx].stream && + context->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id == phantom_stream->stream_id && + context->res_ctx.pipe_ctx[dc_pipe_idx].plane_state == phantom_status->plane_states[dc_plane_idx]) { + switch (dc->debug.fams_version.minor) { + case 1: + default: + static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << dc_pipe_idx); + static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[dc_plane_idx] |= (1 << dc_pipe_idx); + } } } } } + break; + default: + ASSERT(false); + break; + } + num_fams2_streams++; + } - /* get per method programming */ - switch (type) { - case FAMS2_STREAM_TYPE_VBLANK: - case FAMS2_STREAM_TYPE_VACTIVE: - case FAMS2_STREAM_TYPE_DRR: - break; - case FAMS2_STREAM_TYPE_SUBVP: - phantom_stream = dml_ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, stream); - if (!phantom_stream) - break; - - phantom_status = dml_ctx->config.callbacks.get_stream_status(context, phantom_stream); - - /* phantom status should always be present */ - ASSERT(phantom_status); - if (!phantom_status) - break; - - switch (dc->debug.fams_version.minor) { - case 1: - default: - static_sub_state->stream_v1.sub_state.subvp.phantom_otg_inst = phantom_status->primary_otg_inst; - - /* populate pipe masks for phantom planes */ - for (j = 0; j < phantom_status->plane_count; j++) { - for (k = 0; k < dc->res_pool->pipe_count; k++) { - if (context->res_ctx.pipe_ctx[k].stream && - context->res_ctx.pipe_ctx[k].stream->stream_id == phantom_stream->stream_id && - context->res_ctx.pipe_ctx[k].plane_state == phantom_status->plane_states[j]) { - switch (dc->debug.fams_version.minor) { - case 1: - default: - static_sub_state->stream_v1.sub_state.subvp.phantom_pipe_mask |= (1 << k); - static_sub_state->stream_v1.sub_state.subvp.phantom_plane_pipe_masks[j] |= (1 << k); - } - } - } - } - } - break; - default: - ASSERT(false); - break; - } + return num_fams2_streams; +} + +void dml21_build_fams2_programming(const struct dc *dc, + struct dc_state *context, + struct dml2_context *dml_ctx) +{ + unsigned int num_fams2_streams = 0; + + /* reset fams2 data */ + memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); + memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * DML2_MAX_PLANES); + memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params_v2, 0, sizeof(union dmub_fams2_stream_static_sub_state_v2) * DML2_MAX_PLANES); + memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)); - num_fams2_streams++; + if (dml_ctx->v21.mode_programming.programming->fams2_required || + dml_ctx->v21.mode_programming.programming->legacy_pstate_info_for_dmu) { + if (dc->debug.fams_version.major == 2) { + num_fams2_streams = dml21_build_fams2_stream_programming_v2(dc, context, dml_ctx); } } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h index 4bff52eaaef8d..bff945a4ab3a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.h @@ -9,6 +9,7 @@ struct dc_state; struct dc_plane_state; struct pipe_ctx; +struct dc_dmub_srv; struct dml2_context; struct dml2_display_rq_regs; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c index 798abb2b2e676..2623e917ec28c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.c @@ -9,16 +9,21 @@ #include "dml21_utils.h" #include "dml21_translation_helper.h" #include "dml2_dc_resource_mgmt.h" +#include "dc_fpu.h" + +#if !defined(DC_RUN_WITH_PREEMPTION_ENABLED) +#define DC_RUN_WITH_PREEMPTION_ENABLED(code) code +#endif // !DC_RUN_WITH_PREEMPTION_ENABLED #define INVALID -1 static bool dml21_allocate_memory(struct dml2_context **dml_ctx) { - *dml_ctx = vzalloc(sizeof(struct dml2_context)); + DC_RUN_WITH_PREEMPTION_ENABLED(*dml_ctx = vzalloc(sizeof(struct dml2_context))); if (!(*dml_ctx)) return false; - (*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance)); + DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.dml_init.dml2_instance = vzalloc(sizeof(struct dml2_instance))); if (!((*dml_ctx)->v21.dml_init.dml2_instance)) return false; @@ -28,7 +33,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; - (*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming)); + DC_RUN_WITH_PREEMPTION_ENABLED((*dml_ctx)->v21.mode_programming.programming = vzalloc(sizeof(struct dml2_display_cfg_programming))); if (!((*dml_ctx)->v21.mode_programming.programming)) return false; @@ -70,8 +75,9 @@ static void dml21_init(const struct dc *in_dc, struct dml2_context *dml_ctx, con bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config) { /* Allocate memory for initializing DML21 instance */ - if (!dml21_allocate_memory(dml_ctx)) + if (!dml21_allocate_memory(dml_ctx)) { return false; + } dml21_init(in_dc, *dml_ctx, config); @@ -215,6 +221,7 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_s return true; if (context->stream_count == 0) { + dml21_init_min_clocks_for_dc_state(dml_ctx, context); dml21_build_fams2_programming(in_dc, context, dml_ctx); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h index 15f92029d2e59..b508bbcc0e16a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h @@ -17,9 +17,9 @@ struct dml2_context; enum dc_validate_mode; /** - * dml2_create - Creates dml21_context. + * dml21_create - Creates dml21_context. * @in_dc: dc. - * @dml2: Created dml21 context. + * @dml_ctx: Created dml21 context. * @config: dml21 configuration options. * * Create of DML21 is done as part of dc_state creation. @@ -40,6 +40,7 @@ void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const st * dml21_validate - Determines if a display configuration is supported or not. * @in_dc: dc. * @context: dc_state to be validated. + * @dml_ctx: dml21 context. * @validate_mode: DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX * will not populate context.res_ctx. * @@ -53,7 +54,7 @@ void dml21_reinit(const struct dc *in_dc, struct dml2_context *dml_ctx, const st * -dml21_check_mode_support - for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX option * Calculates if dc_state can be supported for the input display * config. - + * * Context: Two threads may not invoke this function concurrently unless they reference * separate dc_states for validation. * Return: True if mode is supported, false otherwise. diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h new file mode 100644 index 0000000000000..c75778ea7a2c4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: MIT */ +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#ifndef __DML_DML_DCN42_SOC_BB__ +#define __DML_DML_DCN42_SOC_BB__ + +#include "dml_top_soc_parameter_types.h" + +static const struct dml2_soc_qos_parameters dml_dcn42_variant_a_soc_qos_params = { + .derate_table = { + .system_active_urgent = { + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, + }, + .system_active_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, + }, + .dcn_mall_prefetch_urgent = { + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, + }, + .dcn_mall_prefetch_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, + }, + .system_idle_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, + }, + }, + .writeback = { + .base_latency_us = 12, + .scaling_factor_us = 0, + .scaling_factor_mhz = 0, + }, + .qos_params = { + .dcn32x = { + .loaded_round_trip_latency_fclk_cycles = 106, + .urgent_latency_us = { + .base_latency_us = 4, + .base_latency_pixel_vm_us = 4, + .base_latency_vm_us = 4, + .scaling_factor_fclk_us = 0, + .scaling_factor_mhz = 0, + }, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, + }, + }, + .qos_type = dml2_qos_param_type_dcn3, +}; + +static const struct dml2_soc_bb dml2_socbb_dcn42 = { + .clk_table = { + .wck_ratio = { + .clk_values_khz = {2}, + }, + .uclk = { + .clk_values_khz = {400000}, + .num_clk_values = 1, + }, + .fclk = { + .clk_values_khz = {400000}, + .num_clk_values = 1, + }, + .dcfclk = { + .clk_values_khz = {200000}, + .num_clk_values = 1, + }, + .dispclk = { + .clk_values_khz = {1500000}, + .num_clk_values = 1, + }, + .dppclk = { + .clk_values_khz = {1500000}, + .num_clk_values = 1, + }, + .dtbclk = { + .clk_values_khz = {600000}, + .num_clk_values = 1, + }, + .phyclk = { + .clk_values_khz = {810000}, + .num_clk_values = 1, + }, + .socclk = { + .clk_values_khz = {600000}, + .num_clk_values = 1, + }, + .dscclk = { + .clk_values_khz = {500000}, + .num_clk_values = 1, + }, + .phyclk_d18 = { + .clk_values_khz = {667000}, + .num_clk_values = 1, + }, + .phyclk_d32 = { + .clk_values_khz = {625000}, + .num_clk_values = 1, + }, + .dram_config = { + .channel_width_bytes = 4, + .channel_count = 4, + .alt_clock_bw_conversion = true, + }, + }, + + .qos_parameters = { + .derate_table = { + .system_active_urgent = { + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, + }, + .system_active_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, + }, + .dcn_mall_prefetch_urgent = { + .dram_derate_percent_pixel = 65, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 60, + .fclk_derate_percent = 80, + .dcfclk_derate_percent = 80, + }, + .dcn_mall_prefetch_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, + }, + .system_idle_average = { + .dram_derate_percent_pixel = 30, + .dram_derate_percent_vm = 30, + .dram_derate_percent_pixel_and_vm = 30, + .fclk_derate_percent = 60, + .dcfclk_derate_percent = 60, + }, + }, + .writeback = { + .base_latency_us = 12, + .scaling_factor_us = 0, + .scaling_factor_mhz = 0, + }, + .qos_params = { + .dcn32x = { + .loaded_round_trip_latency_fclk_cycles = 106, + .urgent_latency_us = { + .base_latency_us = 4, + .base_latency_pixel_vm_us = 4, + .base_latency_vm_us = 4, + .scaling_factor_fclk_us = 0, + .scaling_factor_mhz = 0, + }, + .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096, + .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096, + .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096, + }, + }, + .qos_type = dml2_qos_param_type_dcn3, + }, + + .power_management_parameters = { + .dram_clk_change_blackout_us = 29, + .fclk_change_blackout_us = 0, + .g7_ppt_blackout_us = 0, + .stutter_enter_plus_exit_latency_us = 11, + .stutter_exit_latency_us = 9, + .z8_stutter_enter_plus_exit_latency_us = 300, + .z8_stutter_exit_latency_us = 200, + }, + + .vmin_limit = { + .dispclk_khz = 632 * 1000, + }, + + .dprefclk_mhz = 600, + .xtalclk_mhz = 24, + .pcie_refclk_mhz = 100, + .dchub_refclk_mhz = 50, + .mall_allocated_for_dcn_mbytes = 64, + .max_outstanding_reqs = 256, + .fabric_datapath_to_dcn_data_return_bytes = 32, + .return_bus_width_bytes = 64, + .hostvm_min_page_size_kbytes = 4, + .gpuvm_min_page_size_kbytes = 256, + .gpuvm_max_page_table_levels = 1, + .hostvm_max_non_cached_page_table_levels = 2, + .phy_downspread_percent = 0.38, + .dcn_downspread_percent = 0.38, + .dispclk_dppclk_vco_speed_mhz = 3000, + .do_urgent_latency_adjustment = 0, + .mem_word_bytes = 32, + .num_dcc_mcaches = 8, + .mcache_size_bytes = 2048, + .mcache_line_size_bytes = 32, + .max_fclk_for_uclk_dpm_khz = 2200 * 1000, +}; + +static const struct dml2_ip_capabilities dml2_dcn42_max_ip_caps = { + .pipe_count = 4, + .otg_count = 4, + .num_dsc = 4, + .max_num_dp2p0_streams = 4, + .max_num_hdmi_frl_outputs = 1, + .max_num_dp2p0_outputs = 4, + .rob_buffer_size_kbytes = 64, + .config_return_buffer_size_in_kbytes = 1792, + .config_return_buffer_segment_size_in_kbytes = 64, + .meta_fifo_size_in_kentries = 32, + .compressed_buffer_segment_size_in_kbytes = 64, + .cursor_buffer_size = 24, + .max_flip_time_us = 110, + .max_flip_time_lines = 50, + .hostvm_mode = 0, + .subvp_drr_scheduling_margin_us = 100, + .subvp_prefetch_end_to_mall_start_us = 15, + .subvp_fw_processing_delay = 15, + .max_vactive_det_fill_delay_us = 400, + + .fams2 = { + .max_allow_delay_us = 100 * 1000, + .scheduling_delay_us = 550, + .vertical_interrupt_ack_delay_us = 40, + .allow_programming_delay_us = 18, + .min_allow_width_us = 20, + .subvp_df_throttle_delay_us = 100, + .subvp_programming_delay_us = 200, + .subvp_prefetch_to_mall_delay_us = 18, + .drr_programming_delay_us = 35, + + .lock_timeout_us = 5000, + .recovery_timeout_us = 5000, + .flip_programming_delay_us = 300, + }, +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h index 35aa954248cdc..4e9abe1a568d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_display_cfg_types.h @@ -27,6 +27,19 @@ enum dml2_swizzle_mode { dml2_gfx11_sw_256kb_d_x, dml2_gfx11_sw_256kb_r_x, + dml2_sw_linear_256b, // GFX10 SW_LINEAR only accepts 256 byte aligned pitch + dml2_gfx10_sw_64kb_r_x, + dml2_gfx102_sw_64kb_s, + dml2_gfx102_sw_64kb_s_t, + dml2_gfx102_sw_64kb_s_x, + dml2_gfx102_sw_64kb_r_x, + + dml2_linear_64elements, // GFX7 LINEAR_ALIGNED accepts pitch alignment of the maximum of 64 elements or 256 bytes + dml2_gfx7_1d_thin, + dml2_gfx7_2d_thin_gen_zero, + dml2_gfx7_2d_thin_gen_one, + dml2_gfx7_2d_thin_arlene, + dml2_gfx7_2d_thin_anubis }; enum dml2_source_format_class { @@ -407,6 +420,7 @@ struct dml2_plane_parameters { unsigned int hostvm_min_page_size_kbytes; enum dml2_svp_mode_override legacy_svp_config; //TODO remove in favor of svp_config + bool use_max_lsw; struct { // HW specific overrides, there's almost no reason to mess with these diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h index 1fbc520c25404..6152155d60735 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h @@ -115,9 +115,12 @@ struct dml2_dram_params { unsigned int channel_width_bytes; unsigned int channel_count; unsigned int transactions_per_clock; + bool alt_clock_bw_conversion; }; +#define ENABLE_WCK struct dml2_soc_state_table { + struct dml2_clk_table wck_ratio; struct dml2_clk_table uclk; struct dml2_clk_table fclk; struct dml2_clk_table dcfclk; @@ -157,6 +160,8 @@ struct dml2_soc_bb { unsigned long return_bus_width_bytes; unsigned long hostvm_min_page_size_kbytes; unsigned long gpuvm_min_page_size_kbytes; + unsigned int hostvm_max_non_cached_page_table_levels; + unsigned int gpuvm_max_page_table_levels; double phy_downspread_percent; double dcn_downspread_percent; double dispclk_dppclk_vco_speed_mhz; @@ -187,6 +192,7 @@ struct dml2_ip_capabilities { unsigned int max_flip_time_us; unsigned int max_flip_time_lines; unsigned int hostvm_mode; + bool dcn_mrq_present; unsigned int subvp_drr_scheduling_margin_us; unsigned int subvp_prefetch_end_to_mall_start_us; unsigned int subvp_fw_processing_delay; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h index 452e4a2e72c01..98b26116cdc14 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h @@ -19,6 +19,8 @@ enum dml2_project_id { dml2_project_dcn4x_stage1, dml2_project_dcn4x_stage2, dml2_project_dcn4x_stage2_auto_drr_svp, + dml2_project_dcn40, + dml2_project_dcn42, }; enum dml2_pstate_change_support { @@ -79,6 +81,7 @@ struct dml2_options { struct dml2_pmo_options pmo_options; }; + struct dml2_initialize_instance_in_out { struct dml2_instance *dml2_instance; struct dml2_options options; @@ -418,6 +421,7 @@ struct dml2_display_cfg_programming { /* indicates this configuration requires FW to support */ bool fams2_required; + bool legacy_pstate_info_for_dmu; struct dmub_cmd_fams2_global_config fams2_global_config; struct { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c index eba948e187c11..99fc2f0666e2b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.c @@ -78,6 +78,86 @@ struct dml2_core_ip_params core_dcn4_ip_caps_base = { .subvp_swath_height_margin_lines = 16, }; +struct dml2_core_ip_params core_dcn42_ip_caps_base = { + .vblank_nom_default_us = 668, + .remote_iommu_outstanding_translations = 256, + .rob_buffer_size_kbytes = 64, + .config_return_buffer_size_in_kbytes = 1792, + .config_return_buffer_segment_size_in_kbytes = 64, + .compressed_buffer_segment_size_in_kbytes = 64, + .dpte_buffer_size_in_pte_reqs_luma = 68, + .dpte_buffer_size_in_pte_reqs_chroma = 36, + .pixel_chunk_size_kbytes = 8, + .alpha_pixel_chunk_size_kbytes = 4, + .min_pixel_chunk_size_bytes = 1024, + .writeback_chunk_size_kbytes = 8, + .line_buffer_size_bits = 1171920, + .max_line_buffer_lines = 32, + .writeback_interface_buffer_size_kbytes = 90, + + //Number of pipes after DCN Pipe harvesting + .max_num_dpp = 4, + .max_num_otg = 4, + .max_num_opp = 4, + .max_num_wb = 1, + .max_dchub_pscl_bw_pix_per_clk = 4, + .max_pscl_lb_bw_pix_per_clk = 2, + .max_lb_vscl_bw_pix_per_clk = 4, + .max_vscl_hscl_bw_pix_per_clk = 4, + .max_hscl_ratio = 6, + .max_vscl_ratio = 6, + .max_hscl_taps = 8, + .max_vscl_taps = 8, + .dispclk_ramp_margin_percent = 1, + .dppclk_delay_subtotal = 47, + .dppclk_delay_scl = 50, + .dppclk_delay_scl_lb_only = 16, + .dppclk_delay_cnvc_formatter = 28, + .dppclk_delay_cnvc_cursor = 6, + .cursor_buffer_size = 42, + .cursor_chunk_size = 2, + .dispclk_delay_subtotal = 125, + .max_inter_dcn_tile_repeaters = 8, + .writeback_max_hscl_ratio = 1, + .writeback_max_vscl_ratio = 1, + .writeback_min_hscl_ratio = 1, + .writeback_min_vscl_ratio = 1, + .writeback_max_hscl_taps = 1, + .writeback_max_vscl_taps = 1, + .writeback_line_buffer_buffer_size = 0, + .num_dsc = 4, + .maximum_dsc_bits_per_component = 12, + .maximum_pixels_per_line_per_dsc_unit = 5760, + .dsc422_native_support = true, + .dcc_supported = true, + .ptoi_supported = false, + + .cursor_64bpp_support = true, + .dynamic_metadata_vm_enabled = false, + + .max_num_hdmi_frl_outputs = 0, + .max_num_dp2p0_outputs = 2, + .max_num_dp2p0_streams = 4, + .imall_supported = 1, + .max_flip_time_us = 110, + .max_flip_time_lines = 50, + .words_per_channel = 16, + + .subvp_fw_processing_delay_us = 15, + .subvp_pstate_allow_width_us = 20, + .subvp_swath_height_margin_lines = 16, + + .dcn_mrq_present = 1, + .zero_size_buffer_entries = 512, + .compbuf_reserved_space_zs = 64, + .dcc_meta_buffer_size_bytes = 6272, + .meta_chunk_size_kbytes = 2, + .min_meta_chunk_size_bytes = 256, + + .dchub_arb_to_ret_delay = 102, + .hostvm_mode = 1, +}; + static void patch_ip_caps_with_explicit_ip_params(struct dml2_ip_capabilities *ip_caps, const struct dml2_core_ip_params *ip_params) { ip_caps->pipe_count = ip_params->max_num_dpp; @@ -107,6 +187,7 @@ static void patch_ip_params_with_ip_caps(struct dml2_core_ip_params *ip_params, { ip_params->max_num_dpp = ip_caps->pipe_count; ip_params->max_num_otg = ip_caps->otg_count; + ip_params->max_num_opp = ip_caps->otg_count; ip_params->num_dsc = ip_caps->num_dsc; ip_params->max_num_dp2p0_streams = ip_caps->max_num_dp2p0_streams; ip_params->max_num_dp2p0_outputs = ip_caps->max_num_dp2p0_outputs; @@ -153,6 +234,37 @@ bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out) return true; } +bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out) +{ + struct dml2_core_instance *core = in_out->instance; + + if (!in_out->minimum_clock_table) + return false; + else + core->minimum_clock_table = in_out->minimum_clock_table; + + if (in_out->explicit_ip_bb && in_out->explicit_ip_bb_size > 0) { + memcpy(&core->clean_me_up.mode_lib.ip, in_out->explicit_ip_bb, in_out->explicit_ip_bb_size); + + // FIXME_STAGE2: + // DV still uses stage1 ip_param_st for each variant, need to patch the ip_caps with ip_param info + // Should move DV to use ip_caps but need move more overrides to ip_caps + patch_ip_caps_with_explicit_ip_params(in_out->ip_caps, in_out->explicit_ip_bb); + core->clean_me_up.mode_lib.ip.subvp_pstate_allow_width_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us; + core->clean_me_up.mode_lib.ip.subvp_fw_processing_delay_us = core_dcn4_ip_caps_base.subvp_pstate_allow_width_us; + core->clean_me_up.mode_lib.ip.subvp_swath_height_margin_lines = core_dcn4_ip_caps_base.subvp_swath_height_margin_lines; + } else { + memcpy(&core->clean_me_up.mode_lib.ip, &core_dcn42_ip_caps_base, sizeof(struct dml2_core_ip_params)); + patch_ip_params_with_ip_caps(&core->clean_me_up.mode_lib.ip, in_out->ip_caps); + core->clean_me_up.mode_lib.ip.imall_supported = false; + } + + memcpy(&core->clean_me_up.mode_lib.soc, in_out->soc_bb, sizeof(struct dml2_soc_bb)); + memcpy(&core->clean_me_up.mode_lib.ip_caps, in_out->ip_caps, sizeof(struct dml2_ip_capabilities)); + + return true; +} + static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main, const struct dml2_implicit_svp_meta *meta) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h index a68bb001a3465..5c26d819a6739 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4.h @@ -5,6 +5,7 @@ #ifndef __DML2_CORE_DCN4_H__ #define __DML2_CORE_DCN4_H__ bool core_dcn4_initialize(struct dml2_core_initialize_in_out *in_out); +bool core_dcn42_initialize(struct dml2_core_initialize_in_out *in_out); bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out); bool core_dcn4_mode_programming(struct dml2_core_mode_programming_in_out *in_out); bool core_dcn4_populate_informative(struct dml2_core_populate_informative_in_out *in_out); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index a02e9fd6b5ca4..f6402e199354e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -202,7 +202,7 @@ static unsigned int dml_round_to_multiple(unsigned int num, unsigned int multipl return (num - remainder); } -static unsigned int dml_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info) +static unsigned int dml_get_num_active_pipes(unsigned int num_planes, const struct core_display_cfg_support_info *cfg_support_info) { unsigned int num_active_pipes = 0; @@ -326,6 +326,7 @@ dml_get_var_func(stutter_efficiency, double, mode_lib->mp.StutterEfficiency); dml_get_var_func(stutter_efficiency_no_vblank, double, mode_lib->mp.StutterEfficiencyNotIncludingVBlank); dml_get_var_func(stutter_num_bursts, double, mode_lib->mp.NumberOfStutterBurstsPerFrame); dml_get_var_func(stutter_efficiency_z8, double, mode_lib->mp.Z8StutterEfficiency); +dml_get_var_func(stutter_efficiency_no_vblank_z8, double, mode_lib->mp.Z8StutterEfficiencyNotIncludingVBlank); dml_get_var_func(stutter_num_bursts_z8, double, mode_lib->mp.Z8NumberOfStutterBurstsPerFrame); dml_get_var_func(stutter_period, double, mode_lib->mp.StutterPeriod); dml_get_var_func(stutter_efficiency_z8_bestcase, double, mode_lib->mp.Z8StutterEfficiencyBestCase); @@ -545,9 +546,9 @@ static bool dml_is_vertical_rotation(enum dml2_rotation_angle Scan) return is_vert; } -static int unsigned dml_get_gfx_version(enum dml2_swizzle_mode sw_mode) +static unsigned int dml_get_gfx_version(enum dml2_swizzle_mode sw_mode) { - int unsigned version = 0; + unsigned int version = 0; if (sw_mode == dml2_sw_linear || sw_mode == dml2_sw_256b_2d || @@ -1760,7 +1761,7 @@ static unsigned int CalculateVMAndRowBytes(struct dml2_core_shared_calculate_vm_ *p->PixelPTEBytesPerRow = (unsigned int)((double)*p->dpte_row_width_ub / (double)*p->PixelPTEReqWidth * *p->PTERequestSize); // VBA_DELTA, VBA doesn't have programming value for pte row height linear. - *p->dpte_row_height_linear = (unsigned int)1 << (unsigned int)math_floor2(math_log((float)(p->PTEBufferSizeInRequests * PixelPTEReqWidth_linear / p->Pitch), 2.0), 1); + *p->dpte_row_height_linear = 1U << (unsigned int)math_floor2(math_log((float)(p->PTEBufferSizeInRequests * PixelPTEReqWidth_linear / p->Pitch), 2.0), 1); if (*p->dpte_row_height_linear > 128) *p->dpte_row_height_linear = 128; @@ -3376,7 +3377,7 @@ static void calculate_cursor_req_attributes( DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_line = %d\n", __func__, *cursor_bytes_per_line); DML_LOG_VERBOSE("DML::%s: cursor_bytes_per_chunk = %d\n", __func__, *cursor_bytes_per_chunk); DML_LOG_VERBOSE("DML::%s: cursor_bytes = %d\n", __func__, *cursor_bytes); - DML_LOG_VERBOSE("DML::%s: cursor_pitch = %d\n", __func__, cursor_bpp == 2 ? 256 : (unsigned int)1 << (unsigned int)math_ceil2(math_log((float)cursor_width, 2), 1)); + DML_LOG_VERBOSE("DML::%s: cursor_pitch = %d\n", __func__, cursor_bpp == 2 ? 256 : 1U << (unsigned int)math_ceil2(math_log((float)cursor_width, 2), 1)); #endif } @@ -7076,10 +7077,21 @@ static void calculate_excess_vactive_bandwidth_required( } } -static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config) +static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) { double bw_mbps = 0; - bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; + unsigned int i; + + if (!dram_config->alt_clock_bw_conversion) + bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0; + else + for (i = 0; i < dram_bw_table->num_entries; i++) + if (dram_bw_table->entries[i].min_uclk_khz >= uclk_khz) { + bw_mbps = (double)dram_bw_table->entries[i].pre_derate_dram_bw_kbps / 1000.0; + break; + } + + DML_ASSERT(bw_mbps > 0); return bw_mbps; } @@ -7963,7 +7975,9 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.max_dispclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dispclk / 1000; mode_lib->ms.max_dscclk_freq_mhz = (double)min_clk_table->max_clocks_khz.dscclk / 1000; mode_lib->ms.max_dppclk_freq_mhz = (double)min_clk_table->max_ss_clocks_khz.dppclk / 1000; - mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config); + mode_lib->ms.uclk_freq_mhz = (double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz / 1000.0; + if (!mode_lib->ms.uclk_freq_mhz) + mode_lib->ms.uclk_freq_mhz = dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config); mode_lib->ms.dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps / 1000); mode_lib->ms.max_dram_bw_mbps = ((double)min_clk_table->dram_bw_table.entries[min_clk_table->dram_bw_table.num_entries - 1].pre_derate_dram_bw_kbps / 1000); mode_lib->ms.qos_param_index = get_qos_param_index((unsigned int) (mode_lib->ms.uclk_freq_mhz * 1000.0), mode_lib->soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params); @@ -10406,7 +10420,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex mode_lib->mp.Dcfclk = programming->min_clocks.dcn4x.active.dcfclk_khz / 1000.0; mode_lib->mp.FabricClock = programming->min_clocks.dcn4x.active.fclk_khz / 1000.0; - mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz, &mode_lib->soc.clk_table.dram_config); + mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz, &mode_lib->soc.clk_table.dram_config, &min_clk_table->dram_bw_table); mode_lib->mp.uclk_freq_mhz = programming->min_clocks.dcn4x.active.uclk_khz / 1000.0; mode_lib->mp.GlobalDPPCLK = programming->min_clocks.dcn4x.dpprefclk_khz / 1000.0; s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; @@ -10484,7 +10498,10 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); DML_LOG_VERBOSE("DML::%s: min_clk_index = %0d\n", __func__, in_out_params->min_clk_index); DML_LOG_VERBOSE("DML::%s: min_clk_table min_fclk_khz = %ld\n", __func__, min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_fclk_khz); - DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config)); + if (min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz) + DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_uclk_khz / 1000.0); + else + DML_LOG_VERBOSE("DML::%s: min_clk_table uclk_mhz = %f\n", __func__, dram_bw_kbps_to_uclk_mhz(min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].pre_derate_dram_bw_kbps, &mode_lib->soc.clk_table.dram_config)); for (k = 0; k < mode_lib->mp.num_active_pipes; ++k) { DML_LOG_VERBOSE("DML::%s: pipe=%d is in plane=%d\n", __func__, k, mode_lib->mp.pipe_plane[k]); DML_LOG_VERBOSE("DML::%s: Per-plane DPPPerSurface[%0d] = %d\n", __func__, k, mode_lib->mp.NoOfDPP[k]); @@ -12188,15 +12205,15 @@ static void rq_dlg_get_wm_regs(const struct dml2_display_cfg *display_cfg, const { double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz; - wm_regs->fclk_pstate = (int unsigned)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz); - wm_regs->sr_enter = (int unsigned)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz); - wm_regs->sr_exit = (int unsigned)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz); - wm_regs->sr_enter_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz); - wm_regs->sr_exit_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz); - wm_regs->temp_read_or_ppt = (int unsigned)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz); - wm_regs->uclk_pstate = (int unsigned)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz); - wm_regs->urgent = (int unsigned)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); - wm_regs->usr = (int unsigned)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz); + wm_regs->fclk_pstate = (unsigned int)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz); + wm_regs->sr_enter = (unsigned int)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + wm_regs->sr_exit = (unsigned int)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz); + wm_regs->sr_enter_z8 = (unsigned int)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + wm_regs->sr_exit_z8 = (unsigned int)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz); + wm_regs->temp_read_or_ppt = (unsigned int)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz); + wm_regs->uclk_pstate = (unsigned int)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz); + wm_regs->urgent = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + wm_regs->usr = (unsigned int)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz); wm_regs->refcyc_per_trip_to_mem = (unsigned int)(mode_lib->mp.UrgentLatency * refclk_freq_in_mhz); wm_regs->refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib->mp.MetaTripToMemory * refclk_freq_in_mhz); wm_regs->frac_urg_bw_flip = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthImmediateFlip * 1000); @@ -12245,11 +12262,15 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, unsigned int pixel_chunk_bytes = 0; unsigned int min_pixel_chunk_bytes = 0; + unsigned int meta_chunk_bytes = 0; + unsigned int min_meta_chunk_bytes = 0; unsigned int dpte_group_bytes = 0; unsigned int mpte_group_bytes = 0; unsigned int p1_pixel_chunk_bytes = 0; unsigned int p1_min_pixel_chunk_bytes = 0; + unsigned int p1_meta_chunk_bytes = 0; + unsigned int p1_min_meta_chunk_bytes = 0; unsigned int p1_dpte_group_bytes = 0; unsigned int p1_mpte_group_bytes = 0; @@ -12270,8 +12291,13 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, dpte_group_bytes = (unsigned int)(dml_get_dpte_group_size_in_bytes(mode_lib, pipe_idx)); mpte_group_bytes = (unsigned int)(dml_get_vm_group_size_in_bytes(mode_lib, pipe_idx)); + meta_chunk_bytes = (unsigned int)(mode_lib->ip.meta_chunk_size_kbytes * 1024); + min_meta_chunk_bytes = (unsigned int)(mode_lib->ip.min_meta_chunk_size_bytes); + p1_pixel_chunk_bytes = pixel_chunk_bytes; p1_min_pixel_chunk_bytes = min_pixel_chunk_bytes; + p1_meta_chunk_bytes = meta_chunk_bytes; + p1_min_meta_chunk_bytes = min_meta_chunk_bytes; p1_dpte_group_bytes = dpte_group_bytes; p1_mpte_group_bytes = mpte_group_bytes; @@ -12292,6 +12318,19 @@ static void rq_dlg_get_rq_reg(struct dml2_display_rq_regs *rq_regs, else rq_regs->rq_regs_c.min_chunk_size = log_and_substract_if_non_zero(p1_min_pixel_chunk_bytes, 8 - 1); + rq_regs->rq_regs_l.meta_chunk_size = log_and_substract_if_non_zero(meta_chunk_bytes, 10); + rq_regs->rq_regs_c.meta_chunk_size = log_and_substract_if_non_zero(p1_meta_chunk_bytes, 10); + + if (min_meta_chunk_bytes == 0) + rq_regs->rq_regs_l.min_meta_chunk_size = 0; + else + rq_regs->rq_regs_l.min_meta_chunk_size = log_and_substract_if_non_zero(min_meta_chunk_bytes, 6 - 1); + + if (min_meta_chunk_bytes == 0) + rq_regs->rq_regs_c.min_meta_chunk_size = 0; + else + rq_regs->rq_regs_c.min_meta_chunk_size = log_and_substract_if_non_zero(p1_min_meta_chunk_bytes, 6 - 1); + rq_regs->rq_regs_l.dpte_group_size = log_and_substract_if_non_zero(dpte_group_bytes, 6); rq_regs->rq_regs_l.mpte_group_size = log_and_substract_if_non_zero(mpte_group_bytes, 6); rq_regs->rq_regs_c.dpte_group_size = log_and_substract_if_non_zero(p1_dpte_group_bytes, 6); @@ -12653,7 +12692,7 @@ static void rq_dlg_get_dlg_reg( disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(math_pow(2, 23) - 1); - DML_ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8); + DML_ASSERT(disp_dlg_regs->dst_y_after_scaler < 8U); DML_ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)math_pow(2, 13)); if (disp_dlg_regs->dst_y_per_pte_row_nom_l >= (unsigned int)math_pow(2, 17)) { @@ -13198,8 +13237,8 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.power_management.stutter_efficiency_with_vblank = dml_get_stutter_efficiency(mode_lib); out->informative.power_management.stutter_num_bursts = dml_get_stutter_num_bursts(mode_lib); - out->informative.power_management.z8.stutter_efficiency = dml_get_stutter_efficiency_z8(mode_lib); - out->informative.power_management.z8.stutter_efficiency_with_vblank = dml_get_stutter_efficiency(mode_lib); + out->informative.power_management.z8.stutter_efficiency = dml_get_stutter_efficiency_no_vblank_z8(mode_lib); + out->informative.power_management.z8.stutter_efficiency_with_vblank = dml_get_stutter_efficiency_z8(mode_lib); out->informative.power_management.z8.stutter_num_bursts = dml_get_stutter_num_bursts_z8(mode_lib); out->informative.power_management.z8.stutter_period = dml_get_stutter_period(mode_lib); @@ -13209,7 +13248,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.misc.cstate_max_cap_mode = dml_get_cstate_max_cap_mode(mode_lib); - out->min_clocks.dcn4x.dpprefclk_khz = (int unsigned)dml_get_global_dppclk_khz(mode_lib); + out->min_clocks.dcn4x.dpprefclk_khz = (unsigned int)dml_get_global_dppclk_khz(mode_lib); out->informative.qos.max_active_fclk_change_latency_supported = dml_get_fclk_change_latency(mode_lib); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c index cc4f0663c6d67..6cad99c21139b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c @@ -21,6 +21,7 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance case dml2_project_dcn4x_stage1: result = false; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->initialize = &core_dcn4_initialize; @@ -30,6 +31,14 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance out->calculate_mcache_allocation = &core_dcn4_calculate_mcache_allocation; result = true; break; + case dml2_project_dcn42: + out->initialize = &core_dcn42_initialize; + out->mode_support = &core_dcn4_mode_support; + out->mode_programming = &core_dcn4_mode_programming; + out->populate_informative = &core_dcn4_populate_informative; + out->calculate_mcache_allocation = &core_dcn4_calculate_mcache_allocation; + result = true; + break; case dml2_project_invalid: default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h index 1087a8c926ff1..953f40fde1e15 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h @@ -1950,6 +1950,7 @@ struct dml2_core_calcs_CalculatePrefetchSchedule_params { double Ttrip; double Turg; bool setup_for_tdlut; + bool use_max_lsw; unsigned int tdlut_pte_bytes_per_frame; unsigned int tdlut_bytes_per_frame; double tdlut_opt_time; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c index b57d0f6ea6a1c..6930ba7ce5b76 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c @@ -428,6 +428,9 @@ bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_c unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) { + if (dml2_core_utils_get_gfx_version(sw_mode) == 10 || dml2_core_utils_get_gfx_version(sw_mode) == 7) { + return dml2_core_utils_get_tile_block_size_bytes_backcompat(sw_mode, byte_per_pixel); + } if (sw_mode == dml2_sw_linear) return 256; @@ -459,14 +462,56 @@ unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw }; } +unsigned int dml2_core_utils_get_tile_block_size_bytes_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) +{ + if (sw_mode == dml2_sw_linear_256b) + return 256; + else if (sw_mode == dml2_gfx10_sw_64kb_r_x) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_s) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_s_t) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_s_x) + return 65536; + else if (sw_mode == dml2_gfx102_sw_64kb_r_x) + return 65536; + else if (sw_mode == dml2_linear_64elements) + return 256; + else if (sw_mode == dml2_gfx7_1d_thin) + return 256; + else if (sw_mode == dml2_gfx7_2d_thin_gen_zero) + return (128 * 64 * byte_per_pixel); + else if (sw_mode == dml2_gfx7_2d_thin_gen_one) + return (128 * 128 * byte_per_pixel); + else if (sw_mode == dml2_gfx7_2d_thin_arlene) + return (64 * 32 * byte_per_pixel); + else if (sw_mode == dml2_gfx7_2d_thin_anubis) + return (128 * 128 * byte_per_pixel); + else { + DML_ASSERT(0); + return 256; + }; +} + bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) { - return (byte_per_pixel != 2); + if (dml2_core_utils_get_gfx_version(sw_mode) == 10 || dml2_core_utils_get_gfx_version(sw_mode) == 7) { + return dml2_core_utils_get_segment_horizontal_contiguous_backcompat(sw_mode, byte_per_pixel); + } else { + return (byte_per_pixel != 2); + } +} + +bool dml2_core_utils_get_segment_horizontal_contiguous_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel) +{ + return !((byte_per_pixel == 4) && + ((sw_mode == dml2_gfx10_sw_64kb_r_x) || (sw_mode == dml2_gfx102_sw_64kb_s) || (sw_mode == dml2_gfx102_sw_64kb_s_t) || (sw_mode == dml2_gfx102_sw_64kb_s_x))); } bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode) { - return sw_mode == dml2_sw_linear; + return (sw_mode == dml2_sw_linear || sw_mode == dml2_sw_linear_256b || sw_mode == dml2_linear_64elements); }; @@ -499,6 +544,20 @@ int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode) sw_mode == dml2_gfx11_sw_256kb_d_x || sw_mode == dml2_gfx11_sw_256kb_r_x) version = 11; + else if (sw_mode == dml2_sw_linear_256b || + sw_mode == dml2_gfx10_sw_64kb_r_x || + sw_mode == dml2_gfx102_sw_64kb_s || + sw_mode == dml2_gfx102_sw_64kb_s_t || + sw_mode == dml2_gfx102_sw_64kb_s_x || + sw_mode == dml2_gfx102_sw_64kb_r_x) + version = 10; + else if (sw_mode == dml2_linear_64elements || + sw_mode == dml2_gfx7_1d_thin || + sw_mode == dml2_gfx7_2d_thin_gen_zero || + sw_mode == dml2_gfx7_2d_thin_gen_one || + sw_mode == dml2_gfx7_2d_thin_arlene || + sw_mode == dml2_gfx7_2d_thin_anubis) + version = 7; else { DML_LOG_VERBOSE("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode); DML_ASSERT(0); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h index 95f0d017add45..471e73ed671cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h @@ -22,6 +22,8 @@ void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_in bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg); unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); bool dml2_core_utils_get_segment_horizontal_contiguous(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); +unsigned int dml2_core_utils_get_tile_block_size_bytes_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); +bool dml2_core_utils_get_segment_horizontal_contiguous_backcompat(enum dml2_swizzle_mode sw_mode, unsigned int byte_per_pixel); bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan); bool dml2_core_utils_is_linear(enum dml2_swizzle_mode sw_mode); int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c index 22969a533a7b5..d17e59d684fd1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c @@ -7,14 +7,24 @@ #include "dml_top_types.h" #include "lib_float_math.h" -static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config) +static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const struct dml2_dram_params *dram_config, struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table) { double uclk_khz = 0; - unsigned long uclk_mbytes_per_tick = 0; - uclk_mbytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; + if (!dram_config->alt_clock_bw_conversion) { + unsigned long uclk_bytes_per_tick = 0; - uclk_khz = (double)bandwidth_kbps / uclk_mbytes_per_tick; + uclk_bytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock; + uclk_khz = (double)bandwidth_kbps / uclk_bytes_per_tick; + } else { + unsigned int i; + /* For lpddr5 bytes per tick changes with mpstate, use table to find uclk*/ + for (i = 0; i < dram_bw_table->num_entries; i++) + if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) { + uclk_khz = dram_bw_table->entries[i].min_uclk_khz; + break; + } + } return uclk_khz; } @@ -34,7 +44,7 @@ static void get_minimum_clocks_for_latency(struct dml2_dpmm_map_mode_to_soc_dpm_ *dcfclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_dcfclk_khz; *fclk = in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].min_fclk_khz; *uclk = dram_bw_kbps_to_uclk_khz(in_out->min_clk_table->dram_bw_table.entries[min_clock_index_for_latency].pre_derate_dram_bw_kbps, - &in_out->soc_bb->clk_table.dram_config); + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); } static unsigned long dml_round_up(double a) @@ -53,14 +63,18 @@ static void calculate_system_active_minimums(struct dml2_dpmm_map_mode_to_soc_dp double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); if (in_out->display_cfg->display_config.hostvm_enable) - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); else - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -97,11 +111,13 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; /* assumes DF throttling is enabled */ - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -128,11 +144,13 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency); /* assumes DF throttling is disabled */ - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); - min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_urgent = (double)min_uclk_urgent / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100); + min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg; @@ -167,8 +185,9 @@ static void calculate_idle_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_ double min_uclk_latency, min_fclk_latency, min_dcfclk_latency; const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result; - min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps, &in_out->soc_bb->clk_table.dram_config); - min_uclk_avg = (double)min_uclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100); + min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps + / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100)), + &in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table); min_fclk_avg = (double)mode_support_result->global.active.average_bw_sdp_kbps / in_out->soc_bb->fabric_datapath_to_dcn_data_return_bytes; min_fclk_avg = (double)min_fclk_avg / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.fclk_derate_percent / 100); @@ -783,3 +802,36 @@ bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_ return true; } +bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out) +{ + const struct dml2_display_cfg *display_cfg = &in_out->display_cfg->display_config; + const struct dml2_core_internal_display_mode_lib *mode_lib = &in_out->core->clean_me_up.mode_lib; + struct dml2_dchub_global_register_set *dchubbub_regs = &in_out->programming->global_regs; + + double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz; + + /* set A */ + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].fclk_pstate = (int unsigned)(mode_lib->mp.Watermark.FCLKChangeWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter = (int unsigned)(mode_lib->mp.Watermark.StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit = (int unsigned)(mode_lib->mp.Watermark.StutterExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_enter_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterEnterPlusExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].sr_exit_z8 = (int unsigned)(mode_lib->mp.Watermark.Z8StutterExitWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].temp_read_or_ppt = (int unsigned)(mode_lib->mp.Watermark.temp_read_or_ppt_watermark_us * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].uclk_pstate = (int unsigned)(mode_lib->mp.Watermark.DRAMClockChangeWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].urgent = (int unsigned)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].usr = (int unsigned)(mode_lib->mp.Watermark.USRRetrainingWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_trip_to_mem = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].refcyc_per_meta_trip_to_mem = (unsigned int)(mode_lib->mp.Watermark.UrgentWatermark * refclk_freq_in_mhz); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_flip = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthImmediateFlip * 1000); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_nom = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidth * 1000); + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A].frac_urg_bw_mall = (unsigned int)(mode_lib->mp.FractionOfUrgentBandwidthMALL * 1000); + + /* set B */ + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_B] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A]; + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_C] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A]; + dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_D] = dchubbub_regs->wm_regs[DML2_DCHUB_WATERMARK_SET_A]; + + dchubbub_regs->num_watermark_sets = 4; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h index e7b58f2efda4b..5fbd07e238a8c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.h @@ -10,5 +10,6 @@ bool dpmm_dcn3_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); bool dpmm_dcn4_map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); bool dpmm_dcn4_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out); +bool dpmm_dcn42_map_watermarks(struct dml2_dpmm_map_watermarks_params_in_out *in_out); #endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index dfd01440737df..1f2d9e97f5fdb 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -31,6 +31,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance out->map_watermarks = &dummy_map_watermarks; result = true; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->map_mode_to_soc_dpm = &dpmm_dcn3_map_mode_to_soc_dpm; out->map_watermarks = &dummy_map_watermarks; @@ -41,6 +42,11 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance out->map_watermarks = &dpmm_dcn4_map_watermarks; result = true; break; + case dml2_project_dcn42: + out->map_mode_to_soc_dpm = &dpmm_dcn4_map_mode_to_soc_dpm; + out->map_watermarks = &dpmm_dcn42_map_watermarks; + result = true; + break; case dml2_project_invalid: default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h index f54fde8fba906..02da6f45cbf75 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn4.h @@ -10,4 +10,4 @@ bool mcg_dcn4_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); bool mcg_dcn4_unit_test(void); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c new file mode 100644 index 0000000000000..1f67cbc2c2366 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dml2_mcg_dcn42.h" +#include "dml_top_soc_parameter_types.h" + +static unsigned long long uclk_to_dram_bw_kbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, unsigned long wck_ratio) +{ + unsigned long long bw_kbps = 0; + + bw_kbps = (unsigned long long) uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * wck_ratio * 2; + return bw_kbps; +} + +static bool build_min_clk_table_coarse_grained(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table) +{ + int i; + + for (i = 0; i < soc_bb->clk_table.fclk.num_clk_values; i++) { + if (i < soc_bb->clk_table.uclk.num_clk_values) { + min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = + uclk_to_dram_bw_kbps(soc_bb->clk_table.uclk.clk_values_khz[i], &soc_bb->clk_table.dram_config, soc_bb->clk_table.wck_ratio.clk_values_khz[i]); + min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[i]; + } else { + min_table->dram_bw_table.entries[i].pre_derate_dram_bw_kbps = min_table->dram_bw_table.entries[soc_bb->clk_table.uclk.num_clk_values - 1].pre_derate_dram_bw_kbps; + min_table->dram_bw_table.entries[i].min_uclk_khz = soc_bb->clk_table.uclk.clk_values_khz[soc_bb->clk_table.uclk.num_clk_values - 1]; + } + + min_table->dram_bw_table.entries[i].min_dcfclk_khz = soc_bb->clk_table.dcfclk.clk_values_khz[i]; + min_table->dram_bw_table.entries[i].min_fclk_khz = soc_bb->clk_table.fclk.clk_values_khz[i]; + } + min_table->dram_bw_table.num_entries = soc_bb->clk_table.fclk.num_clk_values; + + return true; +} + +static bool build_min_clock_table(const struct dml2_soc_bb *soc_bb, struct dml2_mcg_min_clock_table *min_table) +{ + bool result; + + if (!soc_bb || !min_table) + return false; + + + if (soc_bb->clk_table.uclk.num_clk_values > DML_MCG_MAX_CLK_TABLE_SIZE) + return false; + + min_table->fixed_clocks_khz.amclk = 0; + min_table->fixed_clocks_khz.dprefclk = soc_bb->dprefclk_mhz * 1000; + min_table->fixed_clocks_khz.pcierefclk = soc_bb->pcie_refclk_mhz * 1000; + min_table->fixed_clocks_khz.dchubrefclk = soc_bb->dchub_refclk_mhz * 1000; + min_table->fixed_clocks_khz.xtalclk = soc_bb->xtalclk_mhz * 1000; + + min_table->max_clocks_khz.dispclk = soc_bb->clk_table.dispclk.clk_values_khz[soc_bb->clk_table.dispclk.num_clk_values - 1]; + min_table->max_clocks_khz.dppclk = soc_bb->clk_table.dppclk.clk_values_khz[soc_bb->clk_table.dppclk.num_clk_values - 1]; + min_table->max_clocks_khz.dscclk = soc_bb->clk_table.dscclk.clk_values_khz[soc_bb->clk_table.dscclk.num_clk_values - 1]; + min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values - 1]; + min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phyclk.num_clk_values - 1]; + + min_table->max_ss_clocks_khz.dispclk = (unsigned int)((double)min_table->max_clocks_khz.dispclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); + min_table->max_ss_clocks_khz.dppclk = (unsigned int)((double)min_table->max_clocks_khz.dppclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); + min_table->max_ss_clocks_khz.dtbclk = (unsigned int)((double)min_table->max_clocks_khz.dtbclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); + + min_table->max_clocks_khz.dcfclk = soc_bb->clk_table.dcfclk.clk_values_khz[soc_bb->clk_table.dcfclk.num_clk_values - 1]; + min_table->max_clocks_khz.fclk = soc_bb->clk_table.fclk.clk_values_khz[soc_bb->clk_table.fclk.num_clk_values - 1]; + + result = build_min_clk_table_coarse_grained(soc_bb, min_table); + + return result; +} + +bool mcg_dcn42_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out) +{ + return build_min_clock_table(in_out->soc_bb, in_out->min_clk_table); +} diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h new file mode 100644 index 0000000000000..d4ea49e3e6744 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_dcn42.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#ifndef __DML2_MCG_DCN42_H__ +#define __DML2_MCG_DCN42_H__ + +#include "dml2_internal_shared_types.h" + +bool mcg_dcn42_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c index c60b8fe90819d..3dcd2c250633a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c @@ -4,6 +4,7 @@ #include "dml2_mcg_factory.h" #include "dml2_mcg_dcn4.h" +#include "dml2_mcg_dcn42.h" #include "dml2_external_lib_deps.h" static bool dummy_build_min_clock_table(struct dml2_mcg_build_min_clock_table_params_in_out *in_out) @@ -25,11 +26,16 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance * out->build_min_clock_table = &dummy_build_min_clock_table; result = true; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: out->build_min_clock_table = &mcg_dcn4_build_min_clock_table; result = true; break; + case dml2_project_dcn42: + out->build_min_clock_table = &mcg_dcn42_build_min_clock_table; + result = true; + break; case dml2_project_invalid: default: break; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index c26e100fcaf2e..e8691983c0eba 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -23,6 +23,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = { .allow_state_increase = true, }, + // Then VBlank { .per_stream_pstate_method = { dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na, dml2_pstate_method_na }, @@ -53,6 +54,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_2_display[] = { .allow_state_increase = true, }, + // Then VActive + VBlank { .per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vblank, dml2_pstate_method_na, dml2_pstate_method_na }, @@ -113,6 +115,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_3_display[] = { .allow_state_increase = true, }, + // VActive + 1 VBlank { .per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vblank, dml2_pstate_method_na }, @@ -149,6 +152,7 @@ static const struct dml2_pmo_pstate_strategy base_strategy_list_4_display[] = { .allow_state_increase = true, }, + // VActive + 1 VBlank { .per_stream_pstate_method = { dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vactive, dml2_pstate_method_vblank }, @@ -1651,6 +1655,7 @@ static bool validate_pstate_support_strategy_cofunctionality(struct dml2_pmo_ins if (svp_count > 0 && (pmo->options->disable_svp || !all_timings_support_svp(pmo, display_cfg, svp_stream_mask))) return false; + return is_config_schedulable(pmo, display_cfg, pstate_strategy); } @@ -1980,6 +1985,7 @@ static void reset_display_configuration(struct display_configuation_with_meta *d } } + static void setup_planes_for_drr_by_mask(struct display_configuation_with_meta *display_config, struct dml2_pmo_instance *pmo, int plane_mask) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c index 55d2464365d04..4d687fa86caab 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c @@ -3,8 +3,8 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dml2_pmo_factory.h" -#include "dml2_pmo_dcn4_fams2.h" #include "dml2_pmo_dcn3.h" +#include "dml2_pmo_dcn4_fams2.h" #include "dml2_external_lib_deps.h" static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out) @@ -37,6 +37,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * out->optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache; result = true; break; + case dml2_project_dcn40: case dml2_project_dcn4x_stage2: out->initialize = pmo_dcn3_initialize; @@ -56,6 +57,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * result = true; break; + case dml2_project_dcn42: case dml2_project_dcn4x_stage2_auto_drr_svp: out->initialize = pmo_dcn4_fams2_initialize; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h index b90f6263cd85d..7218de1824cca 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.h @@ -10,4 +10,4 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *out); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c index e17b5ceba4471..3bb835b5585ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_standalone_libraries/lib_float_math.c @@ -4,7 +4,9 @@ #include "lib_float_math.h" +#ifndef ASSERT #define ASSERT(condition) +#endif #define isNaN(number) ((number) != (number)) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c index 5a33e2f357f45..a6c5031f69c19 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c @@ -17,6 +17,8 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out) case dml2_project_dcn4x_stage1: case dml2_project_dcn4x_stage2: case dml2_project_dcn4x_stage2_auto_drr_svp: + case dml2_project_dcn40: + case dml2_project_dcn42: return dml2_top_soc15_initialize_instance(in_out); case dml2_project_invalid: default: diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c index 5e14d85821e27..0e3177fe9d27e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_legacy.c @@ -3,7 +3,6 @@ // Copyright 2024 Advanced Micro Devices, Inc. #include "dml2_top_legacy.h" -#include "dml2_top_soc15.h" #include "dml2_core_factory.h" #include "dml2_pmo_factory.h" #include "display_mode_core_structs.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h index 1a6c0727cd2af..d328d92240b4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/inc/dml2_internal_shared_types.h @@ -16,6 +16,7 @@ struct dram_bw_to_min_clk_table_entry { unsigned long long pre_derate_dram_bw_kbps; + unsigned long min_uclk_khz; unsigned long min_fclk_khz; unsigned long min_dcfclk_khz; }; @@ -409,6 +410,7 @@ struct dml2_core_mode_support_in_out { } legacy; }; + struct dml2_core_mode_programming_in_out { /* * Inputs @@ -500,6 +502,7 @@ struct dml2_core_instance { bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); + struct { struct dml2_core_internal_display_mode_lib mode_lib; } clean_me_up; @@ -752,6 +755,7 @@ struct dml2_pmo_instance { bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); + struct dml2_pmo_init_data init_data; struct dml2_pmo_scratch scratch; }; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c index 4cfe64aa84927..fd3c61509f1b4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_dc_resource_mgmt.c @@ -143,7 +143,7 @@ static unsigned int find_pipes_assigned_to_plane(struct dml2_context *ctx, { int i; unsigned int num_found = 0; - unsigned int plane_id_assigned_to_pipe = -1; + unsigned int plane_id_assigned_to_pipe = UINT_MAX; for (i = 0; i < ctx->config.dcn_pipe_count; i++) { struct pipe_ctx *pipe = &state->res_ctx.pipe_ctx[i]; @@ -909,10 +909,10 @@ static unsigned int get_source_mpc_factor(const struct dml2_context *ctx, const struct dc_plane_state *plane) { struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0}; - int dpp_pipe_count = ctx->config.callbacks.get_dpp_pipes_for_plane(plane, - &state->res_ctx, dpp_pipes); - ASSERT(dpp_pipe_count > 0); + if (ctx->config.callbacks.get_dpp_pipes_for_plane(plane, &state->res_ctx, dpp_pipes) <= 0) + ASSERT(false); + return ctx->config.callbacks.get_mpc_slice_count(dpp_pipes[0]); } diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c index 66040c877d68a..d56e58ce26c7a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c @@ -357,7 +357,7 @@ static bool enough_pipes_for_subvp(struct dml2_context *ctx, struct dc_state *st */ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *context) { - struct pipe_ctx *subvp_pipes[2]; + struct pipe_ctx *subvp_pipes[2] = { NULL, NULL }; struct dc_stream_state *phantom = NULL; uint32_t microschedule_lines = 0; uint32_t index = 0; @@ -369,6 +369,9 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; uint32_t time_us = 0; + if (pipe == NULL || pipe->stream == NULL) + continue; + /* Loop to calculate the maximum microschedule time between the two SubVP pipes, * and also to store the two main SubVP pipe pointers in subvp_pipes[2]. */ @@ -386,14 +389,19 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c if (time_us > max_microschedule_us) max_microschedule_us = time_us; - subvp_pipes[index] = pipe; - index++; + if (index < 2) + subvp_pipes[index++] = pipe; // Maximum 2 SubVP pipes if (index == 2) break; } } + + /* Minimal guard to avoid C6001 before subvp_pipes[0]/[1] dereference */ + if (index < 2 || !subvp_pipes[0] || !subvp_pipes[1]) + return false; + vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) / (double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000; vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) / @@ -459,6 +467,11 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context break; } + if (pipe == NULL || pipe->stream == NULL) { + // Defensive: should never happen, try to catch in debug + ASSERT(0); + return false; + } phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream); main_timing = &pipe->stream->timing; phantom_timing = &phantom_stream->timing; @@ -549,6 +562,13 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state * if (!subvp_pipe && pipe_mall_type == SUBVP_MAIN) subvp_pipe = pipe; } + + if (subvp_pipe == NULL) { + // Defensive: should never happen, catch in debug + ASSERT(0); + return false; + } + // Use ignore_msa_timing_param flag to identify as DRR if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) { // SUBVP + DRR case @@ -753,6 +773,12 @@ static void enable_phantom_plane(struct dml2_context *ctx, return; } + /* Minimal NULL guard for C6011 */ + if (!phantom_plane) { + ASSERT(0); + continue; + } + memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address)); memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality, sizeof(phantom_plane->scaling_quality)); @@ -880,6 +906,11 @@ bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_s if (ctx->config.svp_pstate.force_disable_subvp) return false; + if (!state) { + ASSERT(0); + return false; + } + if (!all_pipes_have_stream_and_plane(ctx, state)) return false; @@ -898,6 +929,10 @@ bool dml2_svp_add_phantom_pipe_to_dc_state(struct dml2_context *ctx, struct dc_s } if (enough_pipes_for_subvp(ctx, state) && assign_subvp_pipe(ctx, state, &dc_pipe_idx)) { + if (state->res_ctx.pipe_ctx[dc_pipe_idx].stream == NULL) { + ASSERT(0); + return false; + } dml_pipe_idx = dml2_helper_find_dml_pipe_idx_by_stream_id(ctx, state->res_ctx.pipe_ctx[dc_pipe_idx].stream->stream_id); svp_height = mode_support_info->SubViewportLinesNeededInMALL[dml_pipe_idx]; vstartup = dml_get_vstartup_calculated(&ctx->v20.dml_core_ctx, dml_pipe_idx); diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c index d834cb595afab..e25b88f2d6b9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c @@ -1174,12 +1174,12 @@ static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2 const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index) { unsigned int plane_id; - int i = 0; - int location = -1; + unsigned int i = 0; + unsigned int location = UINT_MAX; if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) { ASSERT(false); - return -1; + return UINT_MAX; } for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c index 9deb03a18ccc8..408559d6fb2d6 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.c @@ -1,549 +1,12 @@ -/* SPDX-License-Identifier: MIT */ +// SPDX-License-Identifier: MIT /* - * Copyright 2023 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. + * Copyright 2025 Advanced Micro Devices, Inc. * * Authors: AMD - * */ -#include "display_mode_core.h" #include "dml2_internal_types.h" -#include "dml2_utils.h" -#include "dml2_policy.h" -#include "dml2_translation_helper.h" -#include "dml2_mall_phantom.h" -#include "dml2_dc_resource_mgmt.h" -#include "dml21_wrapper.h" - -static void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) -{ - if (dml2->config.use_native_soc_bb_construction) - dml2_init_ip_params(dml2, in_dc, out); - else - dml2_translate_ip_params(in_dc, out); -} - -static void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out) -{ - if (dml2->config.use_native_soc_bb_construction) - dml2_init_socbb_params(dml2, in_dc, out); - else - dml2_translate_socbb_params(in_dc, out); -} - -static void initialize_dml2_soc_states(struct dml2_context *dml2, - const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out) -{ - if (dml2->config.use_native_soc_bb_construction) - dml2_init_soc_states(dml2, in_dc, in_bbox, out); - else - dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); -} - -static void map_hw_resources(struct dml2_context *dml2, - struct dml_display_cfg_st *in_out_display_cfg, struct dml_mode_support_info_st *mode_support_info) -{ - unsigned int num_pipes = 0; - int i, j; - - for (i = 0; i < __DML_NUM_PLANES__; i++) { - in_out_display_cfg->hw.ODMMode[i] = mode_support_info->ODMMode[i]; - in_out_display_cfg->hw.DPPPerSurface[i] = mode_support_info->DPPPerSurface[i]; - in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; - in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i]; - in_out_display_cfg->hw.DLGRefClkFreqMHz = 24; - if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && - dml2->v20.dml_core_ctx.project != dml_project_dcn36 && - dml2->v20.dml_core_ctx.project != dml_project_dcn351) { - /*dGPU default as 50Mhz*/ - in_out_display_cfg->hw.DLGRefClkFreqMHz = 50; - } - for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) { - if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) { - dml_print("DML::%s: Index out of bounds: i=%d, __DML2_WRAPPER_MAX_STREAMS_PLANES__=%d\n", - __func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__); - break; - } - dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i]; - dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true; - dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i]; - dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true; - num_pipes++; - } - } -} - -static unsigned int pack_and_call_dml_mode_support_ex(struct dml2_context *dml2, - const struct dml_display_cfg_st *display_cfg, - struct dml_mode_support_info_st *evaluation_info, - enum dc_validate_mode validate_mode) -{ - struct dml2_wrapper_scratch *s = &dml2->v20.scratch; - - s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx; - s->mode_support_params.in_display_cfg = display_cfg; - if (validate_mode == DC_VALIDATE_MODE_ONLY) - s->mode_support_params.in_start_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; - else - s->mode_support_params.in_start_state_idx = 0; - s->mode_support_params.out_evaluation_info = evaluation_info; - - memset(evaluation_info, 0, sizeof(struct dml_mode_support_info_st)); - s->mode_support_params.out_lowest_state_idx = 0; - - return dml_mode_support_ex(&s->mode_support_params); -} - -static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrapper_optimize_configuration_params *p) -{ - int unused_dpps = p->ip_params->max_num_dpp; - int i; - int odms_needed; - int largest_blend_and_timing = 0; - bool optimization_done = false; - - for (i = 0; i < (int) p->cur_display_config->num_timings; i++) { - if (p->cur_display_config->plane.BlendingAndTiming[i] > largest_blend_and_timing) - largest_blend_and_timing = p->cur_display_config->plane.BlendingAndTiming[i]; - } - - if (p->new_policy != p->cur_policy) - *p->new_policy = *p->cur_policy; - - if (p->new_display_config != p->cur_display_config) - *p->new_display_config = *p->cur_display_config; - - - // Optimize Clocks - if (!optimization_done) { - if (largest_blend_and_timing == 0 && p->cur_policy->ODMUse[0] == dml_odm_use_policy_combine_as_needed && dml2->config.minimize_dispclk_using_odm) { - odms_needed = dml2_util_get_maximum_odm_combine_for_output(dml2->config.optimize_odm_4to1, - p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1; - - if (odms_needed <= unused_dpps) { - if (odms_needed == 1) { - p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_2to1; - optimization_done = true; - } else if (odms_needed == 3) { - p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_4to1; - optimization_done = true; - } else - optimization_done = false; - } - } - } - - return optimization_done; -} - -static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state, - enum dc_validate_mode validate_mode) -{ - struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch; - struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch; - - unsigned int dml_result = 0; - int result = -1, i, j; - - build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); - - /* Zero out before each call before proceeding */ - memset(s, 0, sizeof(struct dml2_calculate_lowest_supported_state_for_temp_read_scratch)); - memset(&s_global->mode_support_params, 0, sizeof(struct dml_mode_support_ex_params_st)); - memset(&s_global->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); - - for (i = 0; i < dml2->config.dcn_pipe_count; i++) { - /* Calling resource_build_scaling_params will populate the pipe params - * with the necessary information needed for correct DML calculations - * This is also done in DML1 driver code path and hence display_state - * cannot be const. - */ - struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; - - if (pipe->plane_state) { - if (!dml2->config.callbacks.build_scaling_params(pipe)) { - ASSERT(false); - return false; - } - } - } - - map_dc_state_into_dml_display_cfg(dml2, display_state, &s->cur_display_config); - - for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { - s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us; - } - - for (i = 0; i < 4; i++) { - for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { - dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us; - } - - dml_result = pack_and_call_dml_mode_support_ex(dml2, &s->cur_display_config, &s->evaluation_info, - validate_mode); - - if (dml_result && s->evaluation_info.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive) { - map_hw_resources(dml2, &s->cur_display_config, &s->evaluation_info); - dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); - - ASSERT(dml_result); - - dml2_extract_watermark_set(&dml2->v20.g6_temp_read_watermark_set, &dml2->v20.dml_core_ctx); - dml2->v20.g6_temp_read_watermark_set.cstate_pstate.fclk_pstate_change_ns = dml2->v20.g6_temp_read_watermark_set.cstate_pstate.pstate_change_ns; - - result = s_global->mode_support_params.out_lowest_state_idx; - - while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram_speed_mts) - result++; - - break; - } - } - - for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { - dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latencies[i]; - } - - return result; -} - -static void copy_dummy_pstate_table(struct dummy_pstate_entry *dest, struct dummy_pstate_entry *src, unsigned int num_entries) -{ - for (int i = 0; i < num_entries; i++) { - dest[i] = src[i]; - } -} - -static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, - const struct dml_mode_support_info_st *evaluation_info) -{ - unsigned int planes_per_timing[__DML_NUM_PLANES__] = {0}; - int i; - - for (i = 0; i < display_cfg->num_surfaces; i++) - planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; - - for (i = 0; i < __DML_NUM_PLANES__; i++) { - if (planes_per_timing[i] > 1 && evaluation_info->ODMMode[i] != dml_odm_mode_bypass) - return true; - } - - return false; -} - -static bool does_configuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, - const struct dml_mode_support_info_st *evaluation_info) -{ - bool pass = true; - - if (!ctx->config.enable_windowed_mpo_odm) { - if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) - pass = false; - } - - return pass; -} - -static bool dml_mode_support_wrapper(struct dml2_context *dml2, - struct dc_state *display_state, - enum dc_validate_mode validate_mode) -{ - struct dml2_wrapper_scratch *s = &dml2->v20.scratch; - unsigned int result = 0, i; - unsigned int optimized_result = true; - - build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); - - /* Zero out before each call before proceeding */ - memset(&s->cur_display_config, 0, sizeof(struct dml_display_cfg_st)); - memset(&s->mode_support_params, 0, sizeof(struct dml_mode_support_ex_params_st)); - memset(&s->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); - memset(&s->optimize_configuration_params, 0, sizeof(struct dml2_wrapper_optimize_configuration_params)); - - for (i = 0; i < dml2->config.dcn_pipe_count; i++) { - /* Calling resource_build_scaling_params will populate the pipe params - * with the necessary information needed for correct DML calculations - * This is also done in DML1 driver code path and hence display_state - * cannot be const. - */ - struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; - - if (pipe->plane_state) { - if (!dml2->config.callbacks.build_scaling_params(pipe)) { - ASSERT(false); - return false; - } - } - } - - map_dc_state_into_dml_display_cfg(dml2, display_state, &s->cur_display_config); - if (!dml2->config.skip_hw_state_mapping) - dml2_apply_det_buffer_allocation_policy(dml2, &s->cur_display_config); - - result = pack_and_call_dml_mode_support_ex(dml2, - &s->cur_display_config, - &s->mode_support_info, - validate_mode); - - if (result) - result = does_configuration_meet_sw_policies(dml2, &s->cur_display_config, &s->mode_support_info); - - // Try to optimize - if (result) { - s->cur_policy = dml2->v20.dml_core_ctx.policy; - s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx; - s->optimize_configuration_params.config = &dml2->config; - s->optimize_configuration_params.ip_params = &dml2->v20.dml_core_ctx.ip; - s->optimize_configuration_params.cur_display_config = &s->cur_display_config; - s->optimize_configuration_params.cur_mode_support_info = &s->mode_support_info; - s->optimize_configuration_params.cur_policy = &s->cur_policy; - s->optimize_configuration_params.new_display_config = &s->new_display_config; - s->optimize_configuration_params.new_policy = &s->new_policy; - - while (optimized_result && optimize_configuration(dml2, &s->optimize_configuration_params)) { - dml2->v20.dml_core_ctx.policy = s->new_policy; - optimized_result = pack_and_call_dml_mode_support_ex(dml2, - &s->new_display_config, - &s->mode_support_info, - validate_mode); - - if (optimized_result) - optimized_result = does_configuration_meet_sw_policies(dml2, &s->new_display_config, &s->mode_support_info); - - // If the new optimized state is supposed, then set current = new - if (optimized_result) { - s->cur_display_config = s->new_display_config; - s->cur_policy = s->new_policy; - } else { - // Else, restore policy to current - dml2->v20.dml_core_ctx.policy = s->cur_policy; - } - } - - // Optimize ended with a failed config, so we need to restore DML state to last passing - if (!optimized_result) { - result = pack_and_call_dml_mode_support_ex(dml2, - &s->cur_display_config, - &s->mode_support_info, - validate_mode); - } - } - - if (result) - map_hw_resources(dml2, &s->cur_display_config, &s->mode_support_info); - - return result; -} - -static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode validate_mode) -{ - unsigned int result = 0; - unsigned int min_state = 0; - int min_state_for_g6_temp_read = 0; - - - if (!context) - return false; - - struct dml2_context *dml2 = context->bw_ctx.dml2; - struct dml2_wrapper_scratch *s = &dml2->v20.scratch; - - if (!context->streams[0]->sink->link->dc->caps.is_apu) { - min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context, - validate_mode); - - ASSERT(min_state_for_g6_temp_read >= 0); - } - - result = dml_mode_support_wrapper(dml2, context, validate_mode); - - /* Upon trying to sett certain frequencies in FRL, min_state_for_g6_temp_read is reported as -1. This leads to an invalid value of min_state causing crashes later on. - * Use the default logic for min_state only when min_state_for_g6_temp_read is a valid value. In other cases, use the value calculated by the DML directly. - */ - if (!context->streams[0]->sink->link->dc->caps.is_apu) { - if (min_state_for_g6_temp_read >= 0) - min_state = min_state_for_g6_temp_read > s->mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s->mode_support_params.out_lowest_state_idx; - else - min_state = s->mode_support_params.out_lowest_state_idx; - } - - if (result) { - if (!context->streams[0]->sink->link->dc->caps.is_apu) { - result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true); - } else { - result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); - } - } - return result; -} - -static bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context, - enum dc_validate_mode validate_mode) -{ - struct dml2_context *dml2 = context->bw_ctx.dml2; - struct dml2_wrapper_scratch *s = &dml2->v20.scratch; - struct dml2_dcn_clocks out_clks; - unsigned int result = 0; - bool need_recalculation = false; - uint32_t cstate_enter_plus_exit_z8_ns; - - if (context->stream_count == 0) { - unsigned int lowest_state_idx = 0; - - out_clks.p_state_supported = true; - out_clks.dispclk_khz = 0; /* No requirement, and lowest index will generally be maximum dispclk. */ - out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; - out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; - out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; - out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; - out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000; - out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; - context->bw_ctx.bw.dcn.clk.dtbclk_en = false; - dml2_copy_clocks_to_dc_state(&out_clks, context); - return true; - } - - /* Zero out before each call before proceeding */ - memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch)); - memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st)); - memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st)); - memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st)); - - /* Initialize DET scratch */ - dml2_initialize_det_scratch(dml2); - - copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); - - result = call_dml_mode_support_and_programming(context, validate_mode); - /* Call map dc pipes to map the pipes based on the DML output. For correctly determining if recalculation - * is required or not, the resource context needs to correctly reflect the number of active pipes. We would - * only know the correct number if active pipes after dml2_map_dc_pipes is called. - */ - if (result && !dml2->config.skip_hw_state_mapping) - dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state); - - /* Verify and update DET Buffer configuration if needed. dml2_verify_det_buffer_configuration will check if DET Buffer - * size needs to be updated. If yes it will update the DETOverride variable and set need_recalculation flag to true. - * Based on that flag, run mode support again. Verification needs to be run after dml_mode_programming because the getters - * return correct det buffer values only after dml_mode_programming is called. - */ - if (result && !dml2->config.skip_hw_state_mapping) { - need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch); - if (need_recalculation) { - /* Engage the DML again if recalculation is required. */ - call_dml_mode_support_and_programming(context, validate_mode); - if (!dml2->config.skip_hw_state_mapping) { - dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state); - } - need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch); - ASSERT(need_recalculation == false); - } - } - - if (result) { - unsigned int lowest_state_idx = s->mode_support_params.out_lowest_state_idx; - out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000; - out_clks.p_state_supported = s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported; - if (in_dc->config.use_default_clock_table && - (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { - lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; - out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000; - } - - out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; - out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; - out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; - out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; - out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000; - out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; - context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context); - - if (!dml2->config.skip_hw_state_mapping) { - /* Call dml2_calculate_rq_and_dlg_params */ - dml2_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml2, in_dc->res_pool->pipe_count); - } - - dml2_copy_clocks_to_dc_state(&out_clks, context); - dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); - dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx); - if (context->streams[0]->sink->link->dc->caps.is_apu) - dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx); - else - memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c)); - dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx); - dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx); - //copy for deciding zstate use - context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; - - cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns; - - if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && - cstate_enter_plus_exit_z8_ns < in_dc->debug.minimum_z8_residency_time * 1000) - cstate_enter_plus_exit_z8_ns = in_dc->debug.minimum_z8_residency_time * 1000; - - context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns; - } - - return result; -} - -static bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode) -{ - struct dml2_context *dml2; - unsigned int result = 0; - - if (!context || context->stream_count == 0) - return true; - - dml2 = context->bw_ctx.dml2; - - /* Zero out before each call before proceeding */ - memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch)); - memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st)); - memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st)); - memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st)); - - build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); - - map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config); - if (!dml2->config.skip_hw_state_mapping) - dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config); - - result = pack_and_call_dml_mode_support_ex(dml2, - &dml2->v20.scratch.cur_display_config, - &dml2->v20.scratch.mode_support_info, - validate_mode); - - if (result) - result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info); - - return result == 1; -} - -static void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) -{ - if (dc->debug.override_odm_optimization) { - dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm; - } -} +#include "dml2_wrapper_fpu.h" bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2, enum dc_validate_mode validate_mode) @@ -573,11 +36,6 @@ bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2 return out; } -static inline struct dml2_context *dml2_allocate_memory(void) -{ - return (struct dml2_context *) vzalloc(sizeof(struct dml2_context)); -} - static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) { if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) { @@ -626,8 +84,9 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) { // TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete. - if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) + if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) { return dml21_create(in_dc, dml2, config); + } // Allocate Mode Lib Ctx *dml2 = dml2_allocate_memory(); @@ -640,57 +99,6 @@ bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options return true; } -void dml2_destroy(struct dml2_context *dml2) -{ - if (!dml2) - return; - - if (dml2->architecture == dml2_architecture_21) - dml21_destroy(dml2); - vfree(dml2); -} - -void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, - unsigned int *fclk_change_support, unsigned int *dram_clk_change_support) -{ - *fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0]; - *dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0]; -} - -void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2) -{ - if (dml2->architecture == dml2_architecture_21) - dml21_prepare_mcache_programming(in_dc, context, dml2); -} - -void dml2_copy(struct dml2_context *dst_dml2, - struct dml2_context *src_dml2) -{ - if (src_dml2->architecture == dml2_architecture_21) { - dml21_copy(dst_dml2, src_dml2); - return; - } - /* copy Mode Lib Ctx */ - memcpy(dst_dml2, src_dml2, sizeof(struct dml2_context)); -} - -bool dml2_create_copy(struct dml2_context **dst_dml2, - struct dml2_context *src_dml2) -{ - if (src_dml2->architecture == dml2_architecture_21) - return dml21_create_copy(dst_dml2, src_dml2); - /* Allocate Mode Lib Ctx */ - *dst_dml2 = dml2_allocate_memory(); - - if (!(*dst_dml2)) - return false; - - /* copy Mode Lib Ctx */ - dml2_copy(*dst_dml2, src_dml2); - - return true; -} - void dml2_reinit(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h index c384e141cebc8..5ee489682f2ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h @@ -239,6 +239,7 @@ struct dml2_configuration_options { bool use_clock_dc_limits; bool gpuvm_enable; + bool hostvm_enable; bool force_tdlut_enable; void *bb_from_dmub; }; @@ -306,4 +307,13 @@ bool dml2_validate(const struct dc *in_dc, void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, unsigned int *fclk_change_support, unsigned int *dram_clk_change_support); void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2); + +void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2); +bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode); +bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context, + enum dc_validate_mode validate_mode); + +struct dml2_context *dml2_allocate_memory(void); + #endif //_DML2_WRAPPER_H_ + diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c new file mode 100644 index 0000000000000..203eef747262a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.c @@ -0,0 +1,604 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "display_mode_core.h" +#include "dml2_internal_types.h" +#include "dml2_utils.h" +#include "dml2_policy.h" +#include "dml2_translation_helper.h" +#include "dml2_mall_phantom.h" +#include "dml2_dc_resource_mgmt.h" +#include "dml21_wrapper.h" +#include "dml2_wrapper_fpu.h" + +void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out) +{ + if (dml2->config.use_native_soc_bb_construction) + dml2_init_ip_params(dml2, in_dc, out); + else + dml2_translate_ip_params(in_dc, out); +} + +void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out) +{ + if (dml2->config.use_native_soc_bb_construction) + dml2_init_socbb_params(dml2, in_dc, out); + else + dml2_translate_socbb_params(in_dc, out); +} + +void initialize_dml2_soc_states(struct dml2_context *dml2, + const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out) +{ + if (dml2->config.use_native_soc_bb_construction) + dml2_init_soc_states(dml2, in_dc, in_bbox, out); + else + dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); +} + +static void map_hw_resources(struct dml2_context *dml2, + struct dml_display_cfg_st *in_out_display_cfg, struct dml_mode_support_info_st *mode_support_info) +{ + unsigned int num_pipes = 0; + int i, j; + + for (i = 0; i < __DML_NUM_PLANES__; i++) { + in_out_display_cfg->hw.ODMMode[i] = mode_support_info->ODMMode[i]; + in_out_display_cfg->hw.DPPPerSurface[i] = mode_support_info->DPPPerSurface[i]; + in_out_display_cfg->hw.DSCEnabled[i] = mode_support_info->DSCEnabled[i]; + in_out_display_cfg->hw.NumberOfDSCSlices[i] = mode_support_info->NumberOfDSCSlices[i]; + in_out_display_cfg->hw.DLGRefClkFreqMHz = 24; + if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 && + dml2->v20.dml_core_ctx.project != dml_project_dcn36 && + dml2->v20.dml_core_ctx.project != dml_project_dcn351) { + /*dGPU default as 50Mhz*/ + in_out_display_cfg->hw.DLGRefClkFreqMHz = 50; + } + for (j = 0; j < mode_support_info->DPPPerSurface[i]; j++) { + if (i >= __DML2_WRAPPER_MAX_STREAMS_PLANES__) { + dml_print("DML::%s: Index out of bounds: i=%d, __DML2_WRAPPER_MAX_STREAMS_PLANES__=%d\n", + __func__, i, __DML2_WRAPPER_MAX_STREAMS_PLANES__); + break; + } + dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_stream_id[i]; + dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_stream_id_valid[num_pipes] = true; + dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id[num_pipes] = dml2->v20.scratch.dml_to_dc_pipe_mapping.disp_cfg_to_plane_id[i]; + dml2->v20.scratch.dml_to_dc_pipe_mapping.dml_pipe_idx_to_plane_id_valid[num_pipes] = true; + num_pipes++; + } + } +} + +static unsigned int pack_and_call_dml_mode_support_ex(struct dml2_context *dml2, + const struct dml_display_cfg_st *display_cfg, + struct dml_mode_support_info_st *evaluation_info, + enum dc_validate_mode validate_mode) +{ + struct dml2_wrapper_scratch *s = &dml2->v20.scratch; + + s->mode_support_params.mode_lib = &dml2->v20.dml_core_ctx; + s->mode_support_params.in_display_cfg = display_cfg; + if (validate_mode == DC_VALIDATE_MODE_ONLY) + s->mode_support_params.in_start_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; + else + s->mode_support_params.in_start_state_idx = 0; + s->mode_support_params.out_evaluation_info = evaluation_info; + + memset(evaluation_info, 0, sizeof(struct dml_mode_support_info_st)); + s->mode_support_params.out_lowest_state_idx = 0; + + return dml_mode_support_ex(&s->mode_support_params); +} + +static bool optimize_configuration(struct dml2_context *dml2, struct dml2_wrapper_optimize_configuration_params *p) +{ + int unused_dpps = p->ip_params->max_num_dpp; + int i; + int odms_needed; + int largest_blend_and_timing = 0; + bool optimization_done = false; + + for (i = 0; i < (int) p->cur_display_config->num_timings; i++) { + if (p->cur_display_config->plane.BlendingAndTiming[i] > largest_blend_and_timing) + largest_blend_and_timing = p->cur_display_config->plane.BlendingAndTiming[i]; + } + + if (p->new_policy != p->cur_policy) + *p->new_policy = *p->cur_policy; + + if (p->new_display_config != p->cur_display_config) + *p->new_display_config = *p->cur_display_config; + + + // Optimize Clocks + if (!optimization_done) { + if (largest_blend_and_timing == 0 && p->cur_policy->ODMUse[0] == dml_odm_use_policy_combine_as_needed && dml2->config.minimize_dispclk_using_odm) { + odms_needed = dml2_util_get_maximum_odm_combine_for_output(dml2->config.optimize_odm_4to1, + p->cur_display_config->output.OutputEncoder[0], p->cur_mode_support_info->DSCEnabled[0]) - 1; + + if (odms_needed <= unused_dpps) { + if (odms_needed == 1) { + p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_2to1; + optimization_done = true; + } else if (odms_needed == 3) { + p->new_policy->ODMUse[0] = dml_odm_use_policy_combine_4to1; + optimization_done = true; + } else + optimization_done = false; + } + } + } + + return optimization_done; +} + +static int calculate_lowest_supported_state_for_temp_read(struct dml2_context *dml2, struct dc_state *display_state, + enum dc_validate_mode validate_mode) +{ + struct dml2_calculate_lowest_supported_state_for_temp_read_scratch *s = &dml2->v20.scratch.dml2_calculate_lowest_supported_state_for_temp_read_scratch; + struct dml2_wrapper_scratch *s_global = &dml2->v20.scratch; + + unsigned int dml_result = 0; + int result = -1, i, j; + + build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); + + /* Zero out before each call before proceeding */ + memset(s, 0, sizeof(struct dml2_calculate_lowest_supported_state_for_temp_read_scratch)); + memset(&s_global->mode_support_params, 0, sizeof(struct dml_mode_support_ex_params_st)); + memset(&s_global->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); + + for (i = 0; i < dml2->config.dcn_pipe_count; i++) { + /* Calling resource_build_scaling_params will populate the pipe params + * with the necessary information needed for correct DML calculations + * This is also done in DML1 driver code path and hence display_state + * cannot be const. + */ + struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; + + if (pipe->plane_state) { + if (!dml2->config.callbacks.build_scaling_params(pipe)) { + ASSERT(false); + return false; + } + } + } + + map_dc_state_into_dml_display_cfg(dml2, display_state, &s->cur_display_config); + + for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { + s->uclk_change_latencies[i] = dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us; + } + + for (i = 0; i < 4; i++) { + for (j = 0; j < dml2->v20.dml_core_ctx.states.num_states; j++) { + dml2->v20.dml_core_ctx.states.state_array[j].dram_clock_change_latency_us = s_global->dummy_pstate_table[i].dummy_pstate_latency_us; + } + + dml_result = pack_and_call_dml_mode_support_ex(dml2, &s->cur_display_config, &s->evaluation_info, + validate_mode); + + if (dml_result && s->evaluation_info.DRAMClockChangeSupport[0] == dml_dram_clock_change_vactive) { + map_hw_resources(dml2, &s->cur_display_config, &s->evaluation_info); + dml_result = dml_mode_programming(&dml2->v20.dml_core_ctx, s_global->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); + + ASSERT(dml_result); + + dml2_extract_watermark_set(&dml2->v20.g6_temp_read_watermark_set, &dml2->v20.dml_core_ctx); + dml2->v20.g6_temp_read_watermark_set.cstate_pstate.fclk_pstate_change_ns = dml2->v20.g6_temp_read_watermark_set.cstate_pstate.pstate_change_ns; + + result = s_global->mode_support_params.out_lowest_state_idx; + + while (dml2->v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram_speed_mts) + result++; + + break; + } + } + + for (i = 0; i < dml2->v20.dml_core_ctx.states.num_states; i++) { + dml2->v20.dml_core_ctx.states.state_array[i].dram_clock_change_latency_us = s->uclk_change_latencies[i]; + } + + return result; +} + +static void copy_dummy_pstate_table(struct dummy_pstate_entry *dest, struct dummy_pstate_entry *src, unsigned int num_entries) +{ + for (int i = 0; i < num_entries; i++) { + dest[i] = src[i]; + } +} + +static bool are_timings_requiring_odm_doing_blending(const struct dml_display_cfg_st *display_cfg, + const struct dml_mode_support_info_st *evaluation_info) +{ + unsigned int planes_per_timing[__DML_NUM_PLANES__] = {0}; + int i; + + for (i = 0; i < display_cfg->num_surfaces; i++) + planes_per_timing[display_cfg->plane.BlendingAndTiming[i]]++; + + for (i = 0; i < __DML_NUM_PLANES__; i++) { + if (planes_per_timing[i] > 1 && evaluation_info->ODMMode[i] != dml_odm_mode_bypass) + return true; + } + + return false; +} + +static bool does_configuration_meet_sw_policies(struct dml2_context *ctx, const struct dml_display_cfg_st *display_cfg, + const struct dml_mode_support_info_st *evaluation_info) +{ + bool pass = true; + + if (!ctx->config.enable_windowed_mpo_odm) { + if (are_timings_requiring_odm_doing_blending(display_cfg, evaluation_info)) + pass = false; + } + + return pass; +} + +static bool dml_mode_support_wrapper(struct dml2_context *dml2, + struct dc_state *display_state, + enum dc_validate_mode validate_mode) +{ + struct dml2_wrapper_scratch *s = &dml2->v20.scratch; + unsigned int result = 0, i; + unsigned int optimized_result = true; + + build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); + + /* Zero out before each call before proceeding */ + memset(&s->cur_display_config, 0, sizeof(struct dml_display_cfg_st)); + memset(&s->mode_support_params, 0, sizeof(struct dml_mode_support_ex_params_st)); + memset(&s->dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping)); + memset(&s->optimize_configuration_params, 0, sizeof(struct dml2_wrapper_optimize_configuration_params)); + + for (i = 0; i < dml2->config.dcn_pipe_count; i++) { + /* Calling resource_build_scaling_params will populate the pipe params + * with the necessary information needed for correct DML calculations + * This is also done in DML1 driver code path and hence display_state + * cannot be const. + */ + struct pipe_ctx *pipe = &display_state->res_ctx.pipe_ctx[i]; + + if (pipe->plane_state) { + if (!dml2->config.callbacks.build_scaling_params(pipe)) { + ASSERT(false); + return false; + } + } + } + + map_dc_state_into_dml_display_cfg(dml2, display_state, &s->cur_display_config); + if (!dml2->config.skip_hw_state_mapping) + dml2_apply_det_buffer_allocation_policy(dml2, &s->cur_display_config); + + result = pack_and_call_dml_mode_support_ex(dml2, + &s->cur_display_config, + &s->mode_support_info, + validate_mode); + + if (result) + result = does_configuration_meet_sw_policies(dml2, &s->cur_display_config, &s->mode_support_info); + + // Try to optimize + if (result) { + s->cur_policy = dml2->v20.dml_core_ctx.policy; + s->optimize_configuration_params.dml_core_ctx = &dml2->v20.dml_core_ctx; + s->optimize_configuration_params.config = &dml2->config; + s->optimize_configuration_params.ip_params = &dml2->v20.dml_core_ctx.ip; + s->optimize_configuration_params.cur_display_config = &s->cur_display_config; + s->optimize_configuration_params.cur_mode_support_info = &s->mode_support_info; + s->optimize_configuration_params.cur_policy = &s->cur_policy; + s->optimize_configuration_params.new_display_config = &s->new_display_config; + s->optimize_configuration_params.new_policy = &s->new_policy; + + while (optimized_result && optimize_configuration(dml2, &s->optimize_configuration_params)) { + dml2->v20.dml_core_ctx.policy = s->new_policy; + optimized_result = pack_and_call_dml_mode_support_ex(dml2, + &s->new_display_config, + &s->mode_support_info, + validate_mode); + + if (optimized_result) + optimized_result = does_configuration_meet_sw_policies(dml2, &s->new_display_config, &s->mode_support_info); + + // If the new optimized state is supposed, then set current = new + if (optimized_result) { + s->cur_display_config = s->new_display_config; + s->cur_policy = s->new_policy; + } else { + // Else, restore policy to current + dml2->v20.dml_core_ctx.policy = s->cur_policy; + } + } + + // Optimize ended with a failed config, so we need to restore DML state to last passing + if (!optimized_result) { + result = pack_and_call_dml_mode_support_ex(dml2, + &s->cur_display_config, + &s->mode_support_info, + validate_mode); + } + } + + if (result) + map_hw_resources(dml2, &s->cur_display_config, &s->mode_support_info); + + return result; +} + +static bool call_dml_mode_support_and_programming(struct dc_state *context, enum dc_validate_mode validate_mode) +{ + unsigned int result = 0; + unsigned int min_state = 0; + int min_state_for_g6_temp_read = 0; + + + if (!context) + return false; + + struct dml2_context *dml2 = context->bw_ctx.dml2; + struct dml2_wrapper_scratch *s = &dml2->v20.scratch; + + if (!context->streams[0]->sink->link->dc->caps.is_apu) { + min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context, + validate_mode); + + ASSERT(min_state_for_g6_temp_read >= 0); + } + + result = dml_mode_support_wrapper(dml2, context, validate_mode); + + /* Upon trying to sett certain frequencies in FRL, min_state_for_g6_temp_read is reported as -1. This leads to an invalid value of min_state causing crashes later on. + * Use the default logic for min_state only when min_state_for_g6_temp_read is a valid value. In other cases, use the value calculated by the DML directly. + */ + if (!context->streams[0]->sink->link->dc->caps.is_apu) { + if (min_state_for_g6_temp_read >= 0) + min_state = min_state_for_g6_temp_read > s->mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s->mode_support_params.out_lowest_state_idx; + else + min_state = s->mode_support_params.out_lowest_state_idx; + } + + if (result) { + if (!context->streams[0]->sink->link->dc->caps.is_apu) { + result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true); + } else { + result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); + } + } + return result; +} + +bool dml2_validate_and_build_resource(const struct dc *in_dc, struct dc_state *context, + enum dc_validate_mode validate_mode) +{ + struct dml2_context *dml2 = context->bw_ctx.dml2; + struct dml2_wrapper_scratch *s = &dml2->v20.scratch; + struct dml2_dcn_clocks out_clks; + unsigned int result = 0; + bool need_recalculation = false; + uint32_t cstate_enter_plus_exit_z8_ns; + + if (context->stream_count == 0) { + unsigned int lowest_state_idx = 0; + + out_clks.p_state_supported = true; + out_clks.dispclk_khz = 0; /* No requirement, and lowest index will generally be maximum dispclk. */ + out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; + out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; + out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; + out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; + out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000; + out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.dtbclk_en = false; + dml2_copy_clocks_to_dc_state(&out_clks, context); + return true; + } + + /* Zero out before each call before proceeding */ + memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch)); + memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st)); + memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st)); + memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st)); + + /* Initialize DET scratch */ + dml2_initialize_det_scratch(dml2); + + copy_dummy_pstate_table(s->dummy_pstate_table, in_dc->clk_mgr->bw_params->dummy_pstate_table, 4); + + result = call_dml_mode_support_and_programming(context, validate_mode); + /* Call map dc pipes to map the pipes based on the DML output. For correctly determining if recalculation + * is required or not, the resource context needs to correctly reflect the number of active pipes. We would + * only know the correct number if active pipes after dml2_map_dc_pipes is called. + */ + if (result && !dml2->config.skip_hw_state_mapping) + dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state); + + /* Verify and update DET Buffer configuration if needed. dml2_verify_det_buffer_configuration will check if DET Buffer + * size needs to be updated. If yes it will update the DETOverride variable and set need_recalculation flag to true. + * Based on that flag, run mode support again. Verification needs to be run after dml_mode_programming because the getters + * return correct det buffer values only after dml_mode_programming is called. + */ + if (result && !dml2->config.skip_hw_state_mapping) { + need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch); + if (need_recalculation) { + /* Engage the DML again if recalculation is required. */ + call_dml_mode_support_and_programming(context, validate_mode); + if (!dml2->config.skip_hw_state_mapping) { + dml2_map_dc_pipes(dml2, context, &s->cur_display_config, &s->dml_to_dc_pipe_mapping, in_dc->current_state); + } + need_recalculation = dml2_verify_det_buffer_configuration(dml2, context, &dml2->det_helper_scratch); + ASSERT(need_recalculation == false); + } + } + + if (result) { + unsigned int lowest_state_idx = s->mode_support_params.out_lowest_state_idx; + out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.mp.Dispclk_calculated * 1000; + out_clks.p_state_supported = s->mode_support_info.DRAMClockChangeSupport[0] != dml_dram_clock_change_unsupported; + if (in_dc->config.use_default_clock_table && + (lowest_state_idx < dml2->v20.dml_core_ctx.states.num_states - 1)) { + lowest_state_idx = dml2->v20.dml_core_ctx.states.num_states - 1; + out_clks.dispclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dispclk_mhz * 1000; + } + + out_clks.dcfclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dcfclk_mhz * 1000; + out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabricclk_mhz * 1000; + out_clks.uclk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; + out_clks.phyclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].phyclk_mhz * 1000; + out_clks.socclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].socclk_mhz * 1000; + out_clks.ref_dtbclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dtbclk_mhz * 1000; + context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(in_dc, context); + + if (!dml2->config.skip_hw_state_mapping) { + /* Call dml2_calculate_rq_and_dlg_params */ + dml2_calculate_rq_and_dlg_params(in_dc, context, &context->res_ctx, dml2, in_dc->res_pool->pipe_count); + } + + dml2_copy_clocks_to_dc_state(&out_clks, context); + dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.a, &dml2->v20.dml_core_ctx); + dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.b, &dml2->v20.dml_core_ctx); + if (context->streams[0]->sink->link->dc->caps.is_apu) + dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.dml_core_ctx); + else + memcpy(&context->bw_ctx.bw.dcn.watermarks.c, &dml2->v20.g6_temp_read_watermark_set, sizeof(context->bw_ctx.bw.dcn.watermarks.c)); + dml2_extract_watermark_set(&context->bw_ctx.bw.dcn.watermarks.d, &dml2->v20.dml_core_ctx); + dml2_extract_writeback_wm(context, &dml2->v20.dml_core_ctx); + //copy for deciding zstate use + context->bw_ctx.dml.vba.StutterPeriod = context->bw_ctx.dml2->v20.dml_core_ctx.mp.StutterPeriod; + + cstate_enter_plus_exit_z8_ns = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns; + + if (context->bw_ctx.dml.vba.StutterPeriod < in_dc->debug.minimum_z8_residency_time && + cstate_enter_plus_exit_z8_ns < in_dc->debug.minimum_z8_residency_time * 1000) + cstate_enter_plus_exit_z8_ns = in_dc->debug.minimum_z8_residency_time * 1000; + + context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = cstate_enter_plus_exit_z8_ns; + } + + return result; +} + +bool dml2_validate_only(struct dc_state *context, enum dc_validate_mode validate_mode) +{ + struct dml2_context *dml2; + unsigned int result = 0; + + if (!context || context->stream_count == 0) + return true; + + dml2 = context->bw_ctx.dml2; + + /* Zero out before each call before proceeding */ + memset(&dml2->v20.scratch, 0, sizeof(struct dml2_wrapper_scratch)); + memset(&dml2->v20.dml_core_ctx.policy, 0, sizeof(struct dml_mode_eval_policy_st)); + memset(&dml2->v20.dml_core_ctx.ms, 0, sizeof(struct mode_support_st)); + memset(&dml2->v20.dml_core_ctx.mp, 0, sizeof(struct mode_program_st)); + + build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); + + map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config); + if (!dml2->config.skip_hw_state_mapping) + dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config); + + result = pack_and_call_dml_mode_support_ex(dml2, + &dml2->v20.scratch.cur_display_config, + &dml2->v20.scratch.mode_support_info, + validate_mode); + + if (result) + result = does_configuration_meet_sw_policies(dml2, &dml2->v20.scratch.cur_display_config, &dml2->v20.scratch.mode_support_info); + + return result == 1; +} + +void dml2_apply_debug_options(const struct dc *dc, struct dml2_context *dml2) +{ + if (dc->debug.override_odm_optimization) { + dml2->config.minimize_dispclk_using_odm = dc->debug.minimize_dispclk_using_odm; + } +} + +inline struct dml2_context *dml2_allocate_memory(void) +{ + return (struct dml2_context *) vzalloc(sizeof(struct dml2_context)); +} + +void dml2_destroy(struct dml2_context *dml2) +{ + if (!dml2) + return; + + if (dml2->architecture == dml2_architecture_21) + dml21_destroy(dml2); + vfree(dml2); +} + +void dml2_extract_dram_and_fclk_change_support(struct dml2_context *dml2, + unsigned int *fclk_change_support, unsigned int *dram_clk_change_support) +{ + *fclk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.FCLKChangeSupport[0]; + *dram_clk_change_support = (unsigned int) dml2->v20.dml_core_ctx.ms.support.DRAMClockChangeSupport[0]; +} + +void dml2_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2) +{ + if (dml2->architecture == dml2_architecture_21) + dml21_prepare_mcache_programming(in_dc, context, dml2); +} + +void dml2_copy(struct dml2_context *dst_dml2, + struct dml2_context *src_dml2) +{ + if (src_dml2->architecture == dml2_architecture_21) { + dml21_copy(dst_dml2, src_dml2); + return; + } + /* copy Mode Lib Ctx */ + memcpy(dst_dml2, src_dml2, sizeof(struct dml2_context)); +} + +bool dml2_create_copy(struct dml2_context **dst_dml2, + struct dml2_context *src_dml2) +{ + if (src_dml2->architecture == dml2_architecture_21) + return dml21_create_copy(dst_dml2, src_dml2); + /* Allocate Mode Lib Ctx */ + *dst_dml2 = dml2_allocate_memory(); + + if (!(*dst_dml2)) + return false; + + /* copy Mode Lib Ctx */ + dml2_copy(*dst_dml2, src_dml2); + + return true; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h new file mode 100644 index 0000000000000..573df874b901e --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper_fpu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Authors: AMD + */ + +#ifndef _DML2_WRAPPER_FPU_H_ +#define _DML2_WRAPPER_FPU_H_ + +#include "os_types.h" + +struct dml2_context; +struct dc; +struct ip_params_st; +struct soc_bounding_box_st; +struct soc_states_st; + +void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_params_st *out); +void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_bounding_box_st *out); +void initialize_dml2_soc_states(struct dml2_context *dml2, + const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out); + +#endif //_DML2_WRAPPER_FPU_H_ + diff --git a/drivers/gpu/drm/amd/display/dc/dpp/Makefile b/drivers/gpu/drm/amd/display/dc/dpp/Makefile index 8324a56fe7dbf..2595b2504f9d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dpp/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -80,4 +80,12 @@ AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN401) +############################################################################### +# DCN42 +############################################################################### +DPP_DCN42 = dcn42_dpp.o + +AMD_DAL_DPP_DCN42 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn42/,$(DPP_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c index ce91e5d289567..0e70ffc784b19 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c @@ -172,10 +172,14 @@ bool dpp1_get_optimal_number_of_taps( scl_data->taps.h_taps_c = in_taps->h_taps_c; if (!dpp->ctx->dc->debug.always_scale) { - if (IDENTITY_RATIO(scl_data->ratios.horz)) + if (IDENTITY_RATIO(scl_data->ratios.horz)) { scl_data->taps.h_taps = 1; - if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.h_taps_c = 1; + } + if (IDENTITY_RATIO(scl_data->ratios.vert)) { scl_data->taps.v_taps = 1; + scl_data->taps.v_taps_c = 1; + } if (IDENTITY_RATIO(scl_data->ratios.horz_c)) scl_data->taps.h_taps_c = 1; if (IDENTITY_RATIO(scl_data->ratios.vert_c)) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h index b12f34345a586..890d04b1ddaf9 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h @@ -545,6 +545,7 @@ type SCL_COEF_RAM_SELECT_CURRENT; \ type LUT_MEM_PWR_FORCE; \ type LUT_MEM_PWR_STATE; \ + type LUT_MEM_PWR_DIS; \ type CM_GAMUT_REMAP_MODE; \ type CM_GAMUT_REMAP_C11; \ type CM_GAMUT_REMAP_C12; \ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c index 808bca9fb8044..0d2c9fcd3362c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c @@ -102,7 +102,7 @@ static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) } } -static bool dpp1_dscl_is_video_format(enum pixel_format format) +static bool dpp1_dscl_is_video_format(enum dc_pixel_format format) { if (format >= PIXEL_FORMAT_VIDEO_BEGIN && format <= PIXEL_FORMAT_VIDEO_END) @@ -111,7 +111,7 @@ static bool dpp1_dscl_is_video_format(enum pixel_format format) return false; } -static bool dpp1_dscl_is_420_format(enum pixel_format format) +static bool dpp1_dscl_is_420_format(enum dc_pixel_format format) { if (format == PIXEL_FORMAT_420BPP8 || format == PIXEL_FORMAT_420BPP10) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index ef4a161171814..8a146968ee156 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -376,10 +376,10 @@ void dpp3_cnv_setup ( tbl_entry.color_space = input_color_space; - if (color_space >= COLOR_SPACE_YCBCR601) - select = INPUT_CSC_SELECT_ICSC; - else + if (dpp3_should_bypass_post_csc_for_colorspace(color_space)) select = INPUT_CSC_SELECT_BYPASS; + else + select = INPUT_CSC_SELECT_ICSC; dpp3_program_post_csc(dpp_base, color_space, select, &tbl_entry); @@ -524,10 +524,14 @@ bool dpp3_get_optimal_number_of_taps( scl_data->taps.v_taps_c = max_taps_c; if (!dpp->ctx->dc->debug.always_scale) { - if (IDENTITY_RATIO(scl_data->ratios.horz)) + if (IDENTITY_RATIO(scl_data->ratios.horz)) { scl_data->taps.h_taps = 1; - if (IDENTITY_RATIO(scl_data->ratios.vert)) + scl_data->taps.h_taps_c = 1; + } + if (IDENTITY_RATIO(scl_data->ratios.vert)) { scl_data->taps.v_taps = 1; + scl_data->taps.v_taps_c = 1; + } if (IDENTITY_RATIO(scl_data->ratios.horz_c)) scl_data->taps.h_taps_c = 1; if (IDENTITY_RATIO(scl_data->ratios.vert_c)) @@ -1541,3 +1545,18 @@ bool dpp3_construct( return true; } +bool dpp3_should_bypass_post_csc_for_colorspace(enum dc_color_space dc_color_space) +{ + switch (dc_color_space) { + case COLOR_SPACE_UNKNOWN: + case COLOR_SPACE_SRGB: + case COLOR_SPACE_XR_RGB: + case COLOR_SPACE_SRGB_LIMITED: + case COLOR_SPACE_MSREF_SCRGB: + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + return true; + default: + return false; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h index d4a70b4379eaf..6a61b99d6a798 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h @@ -644,4 +644,8 @@ void dpp3_program_cm_dealpha( void dpp3_cm_get_gamut_remap(struct dpp *dpp_base, struct dpp_grph_csc_adjustment *adjust); + +bool dpp3_should_bypass_post_csc_for_colorspace( + enum dc_color_space dc_color_space); + #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c index 82eca0e7b7d05..3284084ca7ad4 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c @@ -132,6 +132,8 @@ static void dpp3_power_on_gamcor_lut( if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.cm) { if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, 0); + if (dpp_base->ctx->dc->caps.ips_v2_support) + REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, 1); REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5); } else { dpp_base->ctx->dc->optimized_required = true; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c index 96c2c853de42c..2d6a646462e21 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c @@ -206,10 +206,10 @@ void dpp401_dpp_setup( tbl_entry.color_space = input_color_space; - if (color_space >= COLOR_SPACE_YCBCR601) - select = INPUT_CSC_SELECT_ICSC; - else + if (dpp3_should_bypass_post_csc_for_colorspace(color_space)) select = INPUT_CSC_SELECT_BYPASS; + else + select = INPUT_CSC_SELECT_ICSC; dpp3_program_post_csc(dpp_base, color_space, select, &tbl_entry); diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h index 5f6b431ec3980..debcf308cb3b0 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h @@ -1,4 +1,5 @@ -/* Copyright 2023 Advanced Micro Devices, Inc. +/* SPDX-License-Identifier: MIT */ +/* Copyright 2023-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -41,6 +42,7 @@ TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\ TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\ TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\ TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\ TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\ TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\ @@ -208,6 +210,7 @@ TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, mask_sh),\ TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\ TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\ TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\ @@ -336,6 +339,9 @@ TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\ TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\ TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_DIS, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_STATE, mask_sh),\ TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\ TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\ TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\ @@ -558,6 +564,9 @@ type ISHARP_DELTA_LUT_SELECT; \ type ISHARP_DELTA_LUT_SELECT_CURRENT; \ type ISHARP_DELTA_LUT_HOST_SELECT; \ + type ISHARP_DELTA_LUT_MEM_PWR_DIS; \ + type ISHARP_DELTA_LUT_MEM_PWR_FORCE;\ + type ISHARP_DELTA_LUT_MEM_PWR_STATE;\ type ISHARP_DELTA_DATA; \ type ISHARP_DELTA_INDEX; \ type ISHARP_NLDELTA_SCLIP_EN_P; \ @@ -629,6 +638,7 @@ uint32_t DSCL_SC_MATRIX_C0C1; \ uint32_t DSCL_SC_MATRIX_C2C3; \ uint32_t ISHARP_MODE; \ + uint32_t ISHARP_DELTA_LUT_MEM_PWR_CTRL; \ uint32_t ISHARP_NOISEDET_THRESHOLD; \ uint32_t ISHARP_NOISE_GAIN_PWL; \ uint32_t ISHARP_LBA_PWL_SEG0; \ @@ -644,6 +654,8 @@ struct dcn401_dpp_registers { DPP_REG_VARIABLE_LIST_DCN401; + uint32_t ALPHA_2BIT_LUT01; + uint32_t ALPHA_2BIT_LUT23; }; struct dcn401_dpp_shift { diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 6df3419f825f4..8b7e55e337d35 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -94,7 +94,7 @@ static int dpp401_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) } } -static bool dpp401_dscl_is_video_format(enum pixel_format format) +static bool dpp401_dscl_is_video_format(enum dc_pixel_format format) { if (format >= PIXEL_FORMAT_VIDEO_BEGIN && format <= PIXEL_FORMAT_VIDEO_END) @@ -103,7 +103,7 @@ static bool dpp401_dscl_is_video_format(enum pixel_format format) return false; } -static bool dpp401_dscl_is_420_format(enum pixel_format format) +static bool dpp401_dscl_is_420_format(enum dc_pixel_format format) { if (format == PIXEL_FORMAT_420BPP8 || format == PIXEL_FORMAT_420BPP10) @@ -155,7 +155,12 @@ static void dpp401_power_on_dscl( if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { if (power_on) { REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0); - REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); + if (dpp->base.ctx->dc->caps.ips_v2_support) { + /*hw default changes to LS*/ + REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, 1); + REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 100); + } else + REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); } else { if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { dpp->base.ctx->dc->optimized_required = true; @@ -956,6 +961,15 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, *bs_coeffs_updated = false; PERF_TRACE(); + /*power on isharp_delta_mem first*/ + if (dpp_base->ctx->dc->caps.ips_v2_support) { + /*HW default is LS, need to wake up*/ + REG_UPDATE_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, + ISHARP_DELTA_LUT_MEM_PWR_DIS, 1); + REG_WAIT(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_STATE, 0, 1, 100); + } /* ISHARP_MODE */ REG_SET_6(ISHARP_MODE, 0, ISHARP_EN, scl_data->dscl_prog_data.isharp_en, @@ -966,62 +980,57 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm); /* Skip remaining register programming if ISHARP is disabled */ - if (!scl_data->dscl_prog_data.isharp_en) { - PERF_TRACE(); - return; - } - - /* ISHARP_NOISEDET_THRESHOLD */ - REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0, - ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold, - ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold); - - /* ISHARP_NOISE_GAIN_PWL */ - REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0, - ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in, - ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in, - ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope); - - /* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */ - REG_SET_3(ISHARP_LBA_PWL_SEG0, 0, - ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0], - ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0], - ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]); - REG_SET_3(ISHARP_LBA_PWL_SEG1, 0, - ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1], - ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1], - ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]); - REG_SET_3(ISHARP_LBA_PWL_SEG2, 0, - ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2], - ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2], - ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]); - REG_SET_3(ISHARP_LBA_PWL_SEG3, 0, - ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3], - ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3], - ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]); - REG_SET_3(ISHARP_LBA_PWL_SEG4, 0, - ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4], - ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4], - ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]); - REG_SET_2(ISHARP_LBA_PWL_SEG5, 0, - ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5], - ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); - - /* ISHARP_DELTA_LUT */ - if (!program_isharp_1dlut) - dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); + if (scl_data->dscl_prog_data.isharp_en) { + /* ISHARP_NOISEDET_THRESHOLD */ + REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0, + ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold, + ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold); + + /* ISHARP_NOISE_GAIN_PWL */ + REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0, + ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in, + ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in, + ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope); + + /* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */ + REG_SET_3(ISHARP_LBA_PWL_SEG0, 0, + ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0], + ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0], + ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]); + REG_SET_3(ISHARP_LBA_PWL_SEG1, 0, + ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1], + ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1], + ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]); + REG_SET_3(ISHARP_LBA_PWL_SEG2, 0, + ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2], + ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2], + ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]); + REG_SET_3(ISHARP_LBA_PWL_SEG3, 0, + ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3], + ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3], + ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]); + REG_SET_3(ISHARP_LBA_PWL_SEG4, 0, + ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4], + ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4], + ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]); + REG_SET_2(ISHARP_LBA_PWL_SEG5, 0, + ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5], + ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); - /* ISHARP_NLDELTA_SOFT_CLIP */ - REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0, - ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p, - ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p, - ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p, - ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n, - ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n, - ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n); + /* ISHARP_DELTA_LUT */ + if (!program_isharp_1dlut) + dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); + + /* ISHARP_NLDELTA_SOFT_CLIP */ + REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0, + ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p, + ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p, + ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p, + ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n, + ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n, + ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n); /* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */ - if (scl_data->dscl_prog_data.isharp_en) { if (scl_data->dscl_prog_data.filter_blur_scale_v) { dpp401_dscl_set_scaler_filter( dpp, scl_data->taps.v_taps, @@ -1037,6 +1046,14 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, *bs_coeffs_updated = true; } } + + /*power on isharp_delta_mem first*/ + if (dpp_base->ctx->dc->caps.ips_v2_support) { + /*HW default is LS, need to wake up*/ + REG_UPDATE_SEQ_2(ISHARP_DELTA_LUT_MEM_PWR_CTRL, + ISHARP_DELTA_LUT_MEM_PWR_FORCE, 0, + ISHARP_DELTA_LUT_MEM_PWR_DIS, 0); + } PERF_TRACE(); } // dpp401_dscl_program_isharp /** diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c new file mode 100644 index 0000000000000..c126fb9d5bfa9 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "core_types.h" +#include "reg_helper.h" +#include "dcn42_dpp.h" +#include "dcn35/dcn35_dpp.h" + +#define REG(reg)\ + dpp->tf_regs->reg + +#define CTX \ + dpp->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + dpp->tf_shift->field_name, dpp->tf_mask->field_name + +static const uint32_t *get_hist_rgb_luma_coefs(enum dc_color_space color_space) +{ + // Coefs in s.6.12. + // Y = 0.2126R + 0.7152G + 0.0722B + static const uint32_t luma_transform_bt_709[] = {0x1cb36, 0x1e6e2, 0x1b27b}; + // Y = 0.2627R + 0.678G + 0.0593B + static const uint32_t luma_transform_bt_2020[] = {0x1d0d0, 0x1e5b2, 0x1ae5c}; + + switch (color_space) { + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + return luma_transform_bt_2020; + default: + return luma_transform_bt_709; + } +} + +static void dpp42_dpp_cm_hist_control( + struct dpp *dpp_base, + struct cm_hist_control cntl, + enum dc_color_space color_space) +{ + struct dcn42_dpp *dpp = TO_DCN42_DPP(dpp_base); + + REG_UPDATE_10( + CM_HIST_CNTL, + CM_HIST_SEL, cntl.tap_point, + CM_HIST_CH_EN, cntl.channels_enabled, + CM_HIST_SRC1_SEL, cntl.src_1_select, + CM_HIST_SRC2_SEL, cntl.src_2_select, + CM_HIST_SRC3_SEL, cntl.src_3_select, + CM_HIST_CH1_XBAR, cntl.ch1_src, + CM_HIST_CH2_XBAR, cntl.ch2_src, + CM_HIST_CH3_XBAR, cntl.ch3_src, + CM_HIST_FORMAT, cntl.format, + CM_HIST_READ_CHANNEL_MASK, cntl.read_channel_mask); + + if (cntl.src_2_select == CM_HIST_SRC2_MODE_RGB_TO_Y) { + const uint32_t *luma_transform = get_hist_rgb_luma_coefs(color_space); + + REG_UPDATE(CM_HIST_COEFA_SRC2, CM_HIST_COEFA_SRC2, luma_transform[0]); + REG_UPDATE(CM_HIST_COEFB_SRC2, CM_HIST_COEFB_SRC2, luma_transform[1]); + REG_UPDATE(CM_HIST_COEFC_SRC2, CM_HIST_COEFC_SRC2, luma_transform[2]); + } else { + REG_UPDATE(CM_HIST_COEFA_SRC2, CM_HIST_COEFA_SRC2, 0); + REG_UPDATE(CM_HIST_COEFB_SRC2, CM_HIST_COEFB_SRC2, 0x1f000); // 1 in s.6.12 + REG_UPDATE(CM_HIST_COEFC_SRC2, CM_HIST_COEFC_SRC2, 0); + } +} + +static bool dpp42_dpp_cm_hist_read(struct dpp *dpp_base, struct cm_hist *hist_out) +{ + struct dcn42_dpp *dpp = TO_DCN42_DPP(dpp_base); + uint32_t channel_mask = 0; + uint32_t rdy_status = 0, rdy_status_a = 0, rdy_status_b = 0; + bool ch1, ch2, ch3; + + if (hist_out == NULL) + return false; + + + REG_GET(CM_HIST_CNTL, CM_HIST_READ_CHANNEL_MASK, &channel_mask); + ch1 = (channel_mask & 1) > 0; + ch2 = (channel_mask & 2) > 0; + ch3 = (channel_mask & 4) > 0; + + REG_GET(CM_HIST_STATUS, CM_HIST_BUFA_RDY_STATUS, &rdy_status_a); + REG_GET(CM_HIST_STATUS, CM_HIST_BUFB_RDY_STATUS, &rdy_status_b); + + rdy_status = rdy_status_a || rdy_status_b; + + if (rdy_status) { + REG_UPDATE(CM_HIST_LOCK, CM_HIST_LOCK, 1); + REG_UPDATE(CM_HIST_INDEX, CM_HIST_INDEX, 0); + for (int i = 0; i < 256; i++) { + uint32_t temp; + + if (ch1) { + REG_GET(CM_HIST_DATA, CM_HIST_DATA, &temp); + hist_out->ch1[i] += temp; + } + if (ch2) { + REG_GET(CM_HIST_DATA, CM_HIST_DATA, &temp); + hist_out->ch2[i] += temp; + } + if (ch3) { + REG_GET(CM_HIST_DATA, CM_HIST_DATA, &temp); + hist_out->ch3[i] += temp; + } + } + REG_UPDATE(CM_HIST_LOCK, CM_HIST_LOCK, 0); + return true; + } else { + return false; + } +} + +static void dpp42_dpp_setup( + struct dpp *dpp_base, + enum surface_pixel_format format, + enum expansion_mode mode, + struct dc_csc_transform input_csc_color_matrix, + enum dc_color_space input_color_space, + struct cnv_alpha_2bit_lut *alpha_2bit_lut) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + uint32_t pixel_format = 0; + uint32_t alpha_en = 1; + enum dc_color_space color_space = COLOR_SPACE_SRGB; + enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS; + uint32_t is_2bit = 0; + uint32_t alpha_plane_enable = 0; + uint32_t dealpha_en = 0, dealpha_ablnd_en = 0; + uint32_t realpha_en = 0, realpha_ablnd_en = 0; + struct out_csc_color_matrix tbl_entry; + int i; + + REG_SET_2(FORMAT_CONTROL, 0, + CNVC_BYPASS, 0, + FORMAT_EXPANSION_MODE, mode); + + REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0); + REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0); + REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0); + REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0); + + REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2); + + switch (format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + pixel_format = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + pixel_format = 3; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + pixel_format = 8; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + pixel_format = 10; + is_2bit = 1; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + pixel_format = 65; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + pixel_format = 64; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + pixel_format = 67; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + pixel_format = 66; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: + pixel_format = 26; /* ARGB16161616_UNORM */ + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + pixel_format = 24; + break; + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: + pixel_format = 25; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + pixel_format = 12; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + pixel_format = 112; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + pixel_format = 113; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + pixel_format = 114; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + is_2bit = 1; + break; + case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: + pixel_format = 115; + color_space = COLOR_SPACE_YCBCR709; + select = INPUT_CSC_SELECT_ICSC; + is_2bit = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE: + pixel_format = 116; + alpha_plane_enable = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + pixel_format = 116; + alpha_plane_enable = 1; + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + pixel_format = 118; + alpha_en = 0; + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + pixel_format = 119; + alpha_en = 0; + break; + default: + break; + } + + /* Set default color space based on format if none is given. */ + color_space = input_color_space ? input_color_space : color_space; + + if (is_2bit == 1 && alpha_2bit_lut != NULL) { + REG_UPDATE(ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0); + REG_UPDATE(ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1); + REG_UPDATE(ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); + REG_UPDATE(ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3); + } + + REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0, + CNVC_SURFACE_PIXEL_FORMAT, pixel_format, + CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable); + REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); + + REG_SET_2(PRE_DEALPHA, 0, + PRE_DEALPHA_EN, dealpha_en, + PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en); + REG_SET_2(PRE_REALPHA, 0, + PRE_REALPHA_EN, realpha_en, + PRE_REALPHA_ABLND_EN, realpha_ablnd_en); + + /* If input adjustment exists, program the ICSC with those values. */ + if (input_csc_color_matrix.enable_adjustment == true) { + for (i = 0; i < 12; i++) + tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; + + tbl_entry.color_space = input_color_space; + + if (color_space >= COLOR_SPACE_YCBCR601) + select = INPUT_CSC_SELECT_ICSC; + else + select = INPUT_CSC_SELECT_BYPASS; + + dpp3_program_post_csc(dpp_base, color_space, select, + &tbl_entry); + } else { + dpp3_program_post_csc(dpp_base, color_space, select, NULL); + } +} + +static struct dpp_funcs dcn42_dpp_funcs = { + .dpp_program_gamcor_lut = dpp3_program_gamcor_lut, + .dpp_read_state = dpp401_read_state, + .dpp_reset = dpp_reset, + .dpp_set_scaler = dpp401_dscl_set_scaler_manual_scale, + .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps, + .dpp_set_pre_degam = dpp3_set_pre_degam, + .dpp_setup = dpp42_dpp_setup, + .dpp_program_cm_dealpha = dpp3_program_cm_dealpha, + .dpp_program_cm_bias = dpp3_program_cm_bias, + .dpp_program_bias_and_scale = dpp35_program_bias_and_scale_fcnv, + .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer, + .set_cursor_attributes = dpp401_set_cursor_attributes, + .set_cursor_position = dpp401_set_cursor_position, + .set_optional_cursor_attributes = dpp401_set_optional_cursor_attributes, + .dpp_dppclk_control = dpp35_dppclk_control, + .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier, + .set_cursor_matrix = dpp401_set_cursor_matrix, + .dpp_cm_hist_control = dpp42_dpp_cm_hist_control, + .dpp_cm_hist_read = dpp42_dpp_cm_hist_read, + .dpp_read_reg_state = dpp30_read_reg_state, +}; + + +static struct dpp_caps dcn42_dpp_cap = { + .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT, + .max_lb_partitions = 63, + .dscl_calc_lb_num_partitions = dscl401_calc_lb_num_partitions, +}; + +bool dpp42_construct( + struct dcn42_dpp *dpp, + struct dc_context *ctx, + uint32_t inst, + const struct dcn42_dpp_registers *tf_regs, + const struct dcn42_dpp_shift *tf_shift, + const struct dcn42_dpp_mask *tf_mask) +{ + dpp->base.ctx = ctx; + + dpp->base.inst = inst; + dpp->base.funcs = &dcn42_dpp_funcs; + dpp->base.caps = &dcn42_dpp_cap; + + dpp->tf_regs = tf_regs; + dpp->tf_shift = tf_shift; + dpp->tf_mask = tf_mask; + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h new file mode 100644 index 0000000000000..f4ee419eabf77 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DCN42_DPP_H__ +#define __DCN42_DPP_H__ + +#include "dcn401/dcn401_dpp.h" + +#define TO_DCN42_DPP(dpp)\ + container_of(dpp, struct dcn42_dpp, base) + +#define DPP_REG_LIST_SH_MASK_DCN42_COMMON(mask_sh)\ + TF_SF(CM0_CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, mask_sh),\ + TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_EN, mask_sh),\ + TF_SF(CM0_CM_DEALPHA, CM_DEALPHA_ABLND, mask_sh),\ + TF_SF(CM0_CM_BIAS_CR_R, CM_BIAS_CR_R, mask_sh),\ + TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_Y_G, mask_sh),\ + TF_SF(CM0_CM_BIAS_Y_G_CB_B, CM_BIAS_CB_B, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_FORCE, mask_sh),\ + TF_SF(CM0_CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, mask_sh),\ + TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_MODE, mask_sh),\ + TF_SF(CNVC_CFG0_PRE_DEGAM, PRE_DEGAM_SELECT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_PWL_DISABLE, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_MODE_CURRENT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_CONTROL, CM_GAMCOR_SELECT_CURRENT, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_INDEX, CM_GAMCOR_LUT_INDEX, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_DATA, CM_GAMCOR_LUT_DATA, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_WRITE_COLOR_MASK, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_COLOR_SEL, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_READ_DBG, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_HOST_SEL, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_LUT_CONTROL, CM_GAMCOR_LUT_CONFIG_MODE, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL1_B, CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_END_CNTL2_B, CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_OFFSET_B, CM_GAMCOR_RAMA_OFFSET_B, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + TF_SF(CM0_CM_GAMCOR_RAMA_REGION_0_1, CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\ + TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\ + TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\ + TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\ + TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\ + TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\ + TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\ + TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\ + TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\ + TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\ + TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\ + TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\ + TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\ + TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\ + TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\ + TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\ + TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\ + TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\ + TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\ + TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\ + TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\ + TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_DEALPHA, PRE_DEALPHA_ABLND_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_REALPHA, PRE_REALPHA_ABLND_EN, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_MODE, PRE_CSC_MODE_CURRENT, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C11, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C11_C12, PRE_CSC_C12, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C33, mask_sh), \ + TF_SF(CNVC_CFG0_PRE_CSC_C33_C34, PRE_CSC_C34, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_CONTROL, CM_POST_CSC_MODE_CURRENT, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C11, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C11_C12, CM_POST_CSC_C12, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C33, mask_sh), \ + TF_SF(CM0_CM_POST_CSC_C33_C34, CM_POST_CSC_C34, mask_sh), \ + TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ + TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \ + TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_ALPHA_PLANE_ENABLE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_BIAS_G_Y, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y, CUR0_FP_SCALE_G_Y, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_BIAS_RB_CRCB, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB, CUR0_FP_SCALE_RB_CRCB, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_MODE_CURRENT, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_MODE, CUR0_MATRIX_COEF_FORMAT, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C11_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C11_C12_A, CUR0_MATRIX_C12_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C13_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C13_C14_A, CUR0_MATRIX_C14_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C21_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C21_C22_A, CUR0_MATRIX_C22_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C23_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C23_C24_A, CUR0_MATRIX_C24_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C31_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C31_C32_A, CUR0_MATRIX_C32_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C33_A, mask_sh), \ + TF_SF(CM_CUR0_CUR0_MATRIX_C33_C34_A, CUR0_MATRIX_C34_A, mask_sh), \ + TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ + TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh), \ + TF_SF(CM0_CM_CONTROL, CM_BYPASS, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH_EN, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SRC1_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SRC2_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_SRC3_SEL, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH1_XBAR, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH2_XBAR, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_CH3_XBAR, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_FORMAT, mask_sh), \ + TF_SF(CM0_CM_HIST_CNTL, CM_HIST_READ_CHANNEL_MASK, mask_sh), \ + TF_SF(CM0_CM_HIST_LOCK, CM_HIST_LOCK, mask_sh), \ + TF_SF(CM0_CM_HIST_INDEX, CM_HIST_INDEX, mask_sh), \ + TF_SF(CM0_CM_HIST_DATA, CM_HIST_DATA, mask_sh), \ + TF_SF(CM0_CM_HIST_DATA, CM_HIST_DATA, mask_sh), \ + TF_SF(CM0_CM_HIST_STATUS, CM_HIST_BUFA_RDY_STATUS, mask_sh), \ + TF_SF(CM0_CM_HIST_STATUS, CM_HIST_BUFB_RDY_STATUS, mask_sh), \ + TF_SF(CM0_CM_HIST_SCALE_SRC1, CM_HIST_SCALE_SRC1, mask_sh), \ + TF_SF(CM0_CM_HIST_COEFA_SRC2, CM_HIST_COEFA_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_COEFB_SRC2, CM_HIST_COEFB_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_COEFC_SRC2, CM_HIST_COEFC_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_SCALE_SRC3, CM_HIST_SCALE_SRC3, mask_sh), \ + TF_SF(CM0_CM_HIST_BIAS_SRC1, CM_HIST_BIAS_SRC1, mask_sh), \ + TF_SF(CM0_CM_HIST_BIAS_SRC2, CM_HIST_BIAS_SRC2, mask_sh), \ + TF_SF(CM0_CM_HIST_BIAS_SRC3, CM_HIST_BIAS_SRC3, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ + TF_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_R, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_G, mask_sh), \ + TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CROSSBAR_B, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT0, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT01, ALPHA_2BIT_LUT1, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT2, mask_sh), \ + TF_SF(CNVC_CFG0_ALPHA_2BIT_LUT23, ALPHA_2BIT_LUT3, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_BIAS_R, FCNV_FP_BIAS_R, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_BIAS_G, FCNV_FP_BIAS_G, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_BIAS_B, FCNV_FP_BIAS_B, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_SCALE_R, FCNV_FP_SCALE_R, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_SCALE_G, FCNV_FP_SCALE_G, mask_sh), \ + TF_SF(CNVC_CFG0_FCNV_FP_SCALE_B, FCNV_FP_SCALE_B, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_EN, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, LUMA_KEYER_EN, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_CONTROL, COLOR_KEYER_MODE, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_ALPHA, COLOR_KEYER_ALPHA_HIGH, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_RED, COLOR_KEYER_RED_HIGH, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_GREEN, COLOR_KEYER_GREEN_HIGH, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_LOW, mask_sh), \ + TF_SF(CNVC_CFG0_COLOR_KEYER_BLUE, COLOR_KEYER_BLUE_HIGH, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ + TF_SF(CM_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\ + TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_DIS, mask_sh),\ + TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_MATRIX_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MODE, SCL_SC_LTONL_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_RINGEST_FORCE_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_MODE, SCL_EASF_H_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF1_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF3_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT1_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_FLAT2_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_CNTL, SCL_EASF_H_BF2_ROC_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN, SCL_EASF_H_RINGEST_EVENTAP_GAIN2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MAXB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN, SCL_EASF_H_BF_MINB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG0, SCL_EASF_H_BF1_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG1, SCL_EASF_H_BF1_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG2, SCL_EASF_H_BF1_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG3, SCL_EASF_H_BF1_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG4, SCL_EASF_H_BF1_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG5, SCL_EASF_H_BF1_PWL_SLOPE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_IN_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_BASE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG6, SCL_EASF_H_BF1_PWL_SLOPE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_IN_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF1_PWL_SEG7, SCL_EASF_H_BF1_PWL_BASE_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG0, SCL_EASF_H_BF3_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG1, SCL_EASF_H_BF3_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG2, SCL_EASF_H_BF3_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG3, SCL_EASF_H_BF3_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG4, SCL_EASF_H_BF3_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_H_BF3_PWL_SEG5, SCL_EASF_H_BF3_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_RINGEST_FORCE_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_MODE, SCL_EASF_V_2TAP_SHARP_FACTOR, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF1_EN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF3_MODE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT1_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_FLAT2_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_CNTL, SCL_EASF_V_BF2_ROC_GAIN, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1, SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2, SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3, SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN, SCL_EASF_V_RINGEST_EVENTAP_GAIN2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MAXB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINA, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN, SCL_EASF_V_BF_MINB, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG0, SCL_EASF_V_BF1_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG1, SCL_EASF_V_BF1_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG2, SCL_EASF_V_BF1_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG3, SCL_EASF_V_BF1_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG4, SCL_EASF_V_BF1_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG5, SCL_EASF_V_BF1_PWL_SLOPE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_IN_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_BASE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG6, SCL_EASF_V_BF1_PWL_SLOPE_SEG6, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_IN_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF1_PWL_SEG7, SCL_EASF_V_BF1_PWL_BASE_SEG7, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG0, SCL_EASF_V_BF3_PWL_SLOPE_SEG0, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG1, SCL_EASF_V_BF3_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG2, SCL_EASF_V_BF3_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG3, SCL_EASF_V_BF3_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG4, SCL_EASF_V_BF3_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_EASF_V_BF3_PWL_SEG5, SCL_EASF_V_BF3_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C0, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C0C1, SCL_SC_MATRIX_C1, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C2, mask_sh),\ + TF_SF(DSCL0_DSCL_SC_MATRIX_C2C3, SCL_SC_MATRIX_C3, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_DIS, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_FORCE, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL, ISHARP_DELTA_LUT_MEM_PWR_STATE, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_DATA, ISHARP_DELTA_DATA, mask_sh),\ + TF_SF(DSCL0_ISHARP_DELTA_INDEX, ISHARP_DELTA_INDEX, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_EN, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_EN, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_NOISEDET_MODE, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_LBA_MODE, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_MODE, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_FMT_NORM, mask_sh),\ + TF_SF(DSCL0_ISHARP_MODE, ISHARP_DELTA_LUT_SELECT_CURRENT, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_IN_SEG0, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_BASE_SEG0, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG0, ISHARP_LBA_PWL_SLOPE_SEG0, mask_sh), \ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_IN_SEG1, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_BASE_SEG1, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG1, ISHARP_LBA_PWL_SLOPE_SEG1, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_IN_SEG2, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_BASE_SEG2, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG2, ISHARP_LBA_PWL_SLOPE_SEG2, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_IN_SEG3, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_BASE_SEG3, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG3, ISHARP_LBA_PWL_SLOPE_SEG3, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_IN_SEG4, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_BASE_SEG4, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG4, ISHARP_LBA_PWL_SLOPE_SEG4, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_IN_SEG5, mask_sh),\ + TF_SF(DSCL0_ISHARP_LBA_PWL_SEG5, ISHARP_LBA_PWL_BASE_SEG5, mask_sh),\ + TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_UTHRE, mask_sh),\ + TF_SF(DSCL0_ISHARP_NOISEDET_THRESHOLD, ISHARP_NOISEDET_DTHRE, mask_sh), \ + TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_START_IN, mask_sh), \ + TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_END_IN, mask_sh), \ + TF_SF(DSCL0_ISHARP_NOISE_GAIN_PWL, ISHARP_NOISEDET_PWL_SLOPE, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_P, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_P, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_P, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_EN_N, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_PIVOT_N, mask_sh), \ + TF_SF(DSCL0_ISHARP_NLDELTA_SOFT_CLIP, ISHARP_NLDELTA_SCLIP_SLOPE_N, mask_sh), \ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\ + TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh) + +#define DPP_REG_FIELD_LIST_DCN42(type) \ + DPP_REG_FIELD_LIST_DCN401(type); \ + type CM_HIST_SEL; \ + type CM_HIST_CH_EN; \ + type CM_HIST_SRC1_SEL; \ + type CM_HIST_SRC2_SEL; \ + type CM_HIST_SRC3_SEL; \ + type CM_HIST_CH1_XBAR; \ + type CM_HIST_CH2_XBAR; \ + type CM_HIST_CH3_XBAR; \ + type CM_HIST_FORMAT; \ + type CM_HIST_READ_CHANNEL_MASK; \ + type CM_HIST_LOCK; \ + type CM_HIST_INDEX; \ + type CM_HIST_DATA; \ + type CM_HIST_BUFA_RDY_STATUS; \ + type CM_HIST_BUFB_RDY_STATUS; \ + type CM_HIST_SCALE_SRC1; \ + type CM_HIST_COEFA_SRC2; \ + type CM_HIST_COEFB_SRC2; \ + type CM_HIST_COEFC_SRC2; \ + type CM_HIST_SCALE_SRC3; \ + type CM_HIST_BIAS_SRC1; \ + type CM_HIST_BIAS_SRC2; \ + type CM_HIST_BIAS_SRC3 + + +#define DPP_REG_VARIABLE_LIST_DCN42 \ + DPP_REG_VARIABLE_LIST_DCN401; \ + uint32_t ALPHA_2BIT_LUT01; \ + uint32_t ALPHA_2BIT_LUT23; \ + uint32_t CM_HIST_CNTL; \ + uint32_t CM_HIST_INDEX; \ + uint32_t CM_HIST_LOCK; \ + uint32_t CM_HIST_DATA; \ + uint32_t CM_HIST_STATUS; \ + uint32_t CM_HIST_SCALE_SRC1; \ + uint32_t CM_HIST_COEFA_SRC2; \ + uint32_t CM_HIST_COEFB_SRC2; \ + uint32_t CM_HIST_COEFC_SRC2; \ + uint32_t CM_HIST_SCALE_SRC3; \ + uint32_t CM_HIST_BIAS_SRC1; \ + uint32_t CM_HIST_BIAS_SRC2; \ + uint32_t CM_HIST_BIAS_SRC3 + +struct dcn42_dpp_registers { + DPP_REG_VARIABLE_LIST_DCN42; +}; + +struct dcn42_dpp_shift { + DPP_REG_FIELD_LIST_DCN42(uint8_t); +}; + +struct dcn42_dpp_mask { + DPP_REG_FIELD_LIST_DCN42(uint32_t); +}; +struct dcn42_dpp { + struct dpp base; + const struct dcn42_dpp_registers *tf_regs; + const struct dcn42_dpp_shift *tf_shift; + const struct dcn42_dpp_mask *tf_mask; + const uint16_t *filter_v; + const uint16_t *filter_h; + const uint16_t *filter_v_c; + const uint16_t *filter_h_c; + int lb_pixel_depth_supported; + int lb_memory_size; + int lb_bits_per_entry; + bool is_write_to_ram_a_safe; + struct scaler_data scl_data; + struct pwl_params pwl_data; +}; + +bool dpp42_construct(struct dcn42_dpp *dpp42, + struct dc_context *ctx, + uint32_t inst, + const struct dcn42_dpp_registers *tf_regs, + const struct dcn42_dpp_shift *tf_shift, + const struct dcn42_dpp_mask *tf_mask); + + +#endif /* __DCN42_DPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index e4144b2443324..8dfb6dd14eb29 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -680,9 +680,6 @@ static void get_dsc_enc_caps( } else { build_dsc_enc_caps(dsc, dsc_enc_caps); } - - if (dsc->ctx->dc->debug.native422_support) - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; } /* Returns 'false' if no intersection was found for at least one capability. @@ -1100,13 +1097,14 @@ static bool setup_dsc_config( branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps; break; case PIXEL_ENCODING_YCBCR422: - is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; - sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; - branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; - if (!is_dsc_possible) { + if (policy.ycbcr422_simple) { is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422; dsc_cfg->ycbcr422_simple = is_dsc_possible; sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps; + } else { + is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422; + sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps; + branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps; } break; case PIXEL_ENCODING_YCBCR420: @@ -1157,7 +1155,7 @@ static bool setup_dsc_config( if (!is_dsc_possible) goto done; - /* increase miniumum slice count to meet sink slice width limitations */ + /* increase minimum slice count to meet sink slice width limitations */ min_slices_h = dc_fixpt_ceil(dc_fixpt_max( dc_fixpt_div_int(dc_fixpt_from_int(pic_width), dsc_common_caps.max_slice_width), // sink min dc_fixpt_from_int(min_slices_h))); // source min @@ -1406,6 +1404,7 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, policy->min_target_bpp = 8; /* DP specs limits to 3 x bpc */ policy->max_target_bpp = 3 * bpc; + policy->ycbcr422_simple = true; break; case PIXEL_ENCODING_YCBCR420: /* DP specs limits to 6 */ diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 242f1e6f0d8f7..91d205f01beba 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -100,7 +100,7 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) dsc_enc_caps->color_formats.bits.RGB = 1; dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; @@ -297,7 +297,9 @@ void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *p DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); +#endif DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); DC_LOG_DSC("\tpic_height %d", pps->pic_height); @@ -435,7 +437,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); +#endif calc_rc_params(&rc, &dsc_reg_vals->pps); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index 2337c3a972357..e32299982bbec 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -616,4 +616,3 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif - diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c index e712985f7abdb..17acb64a9d804 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c @@ -128,7 +128,7 @@ void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int m dsc_enc_caps->color_formats.bits.RGB = 1; dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index c1bdbb38c690b..bbb8b5b18a4e6 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -78,7 +78,7 @@ static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsign dsc_enc_caps->color_formats.bits.RGB = 1; dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; - dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; + dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1; dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h index 81c83d5fe0422..ad7ef83694ea1 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dsc.h @@ -115,6 +115,7 @@ struct dsc_funcs { void (*dsc_disconnect)(struct display_stream_compressor *dsc); void (*dsc_wait_disconnect_pending_clear)(struct display_stream_compressor *dsc); void (*dsc_get_single_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz); + void (*set_fgcg)(struct display_stream_compressor *dsc, bool enable); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 64cee8c80110c..25ea69bd2e820 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -47,9 +47,14 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) int slice_width = pps->slice_width; int slice_height = pps->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : (pps->native_422 ? CM_422 : pps->native_420 ? CM_420 : CM_444)); +#else + mode = pps->convert_rgb ? CM_RGB : (pps->native_422 ? CM_422 : + pps->native_420 ? CM_420 : CM_444); +#endif bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) ? BPC_10 : BPC_12; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 59864130cf83b..6f5ad09ad1404 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -33,7 +33,9 @@ static void copy_pps_fields(struct drm_dsc_config *to, const struct drm_dsc_conf to->convert_rgb = from->convert_rgb; to->slice_width = from->slice_width; to->slice_height = from->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 to->simple_422 = from->simple_422; +#endif to->native_422 = from->native_422; to->native_420 = from->native_420; to->pic_width = from->pic_width; @@ -119,4 +121,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } - diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index b72e2a9f9a28e..f8142ebf363f3 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2017-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -132,3 +132,14 @@ AMD_DAL_GPIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn401/,$(GPIO_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN401) +############################################################################### +# DCN 4.2 +############################################################################### + +GPIO_DCN42 = hw_translate_dcn42.o hw_factory_dcn42.o + +AMD_DAL_GPIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn42/,$(GPIO_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN42) + + diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c new file mode 100644 index 0000000000000..7d2090c7870e6 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.c @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "include/gpio_types.h" +#include "../hw_factory.h" + + +#include "../hw_gpio.h" +#include "../hw_ddc.h" +#include "../hw_hpd.h" +#include "../hw_generic.h" + + + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" +#include "dpcs/dpcs_4_0_0_offset.h" +#include "dpcs/dpcs_4_0_0_sh_mask.h" + +#include "reg_helper.h" +#include "../hpd_regs.h" +#include "hw_factory_dcn42.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +/* begin ********************* + * macros to expend register list macro defined in HW object header file */ + +/* DCN */ +#define block HPD +#define reg_num 0 + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + + + +#define REG(reg_name)\ + (BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name) + +#define SF_HPD(reg_name, field_name, post_fix)\ + .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix + +#define REGI(reg_name, block, id)\ + (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name) + +#define SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +/* macros to expend register list macro defined in HW object header file + * end *********************/ + +// DC_GPIO_HPD_* registers are gone. +#undef HPD_REG_LIST +#define HPD_REG_LIST(id) \ + .int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\ + .toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id) + +#define hpd_regs(id) \ +{\ + HPD_REG_LIST(id)\ +} + +static const struct hpd_registers hpd_regs[] = { + hpd_regs(0), + hpd_regs(1), + hpd_regs(2), + hpd_regs(3), + hpd_regs(4), +}; + +static const struct hpd_sh_mask hpd_shift = { + HPD_MASK_SH_LIST(__SHIFT) +}; + +static const struct hpd_sh_mask hpd_mask = { + HPD_MASK_SH_LIST(_MASK) +}; + +#include "../ddc_regs.h" + + /* set field name */ +#define SF_DDC(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +static const struct ddc_registers ddc_data_regs_dcn[] = { + ddc_data_regs_dcn2(1), + ddc_data_regs_dcn2(2), + ddc_data_regs_dcn2(3), + ddc_data_regs_dcn2(4), + ddc_data_regs_dcn2(5), + { + // add a dummy entry for cases no such port + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + }, + { + DDC_GPIO_VGA_REG_LIST(DATA), + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + } +}; + +static const struct ddc_registers ddc_clk_regs_dcn[] = { + ddc_clk_regs_dcn2(1), + ddc_clk_regs_dcn2(2), + ddc_clk_regs_dcn2(3), + ddc_clk_regs_dcn2(4), + ddc_clk_regs_dcn2(5), + { + // add a dummy entry for cases no such port + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + }, + { + DDC_GPIO_VGA_REG_LIST(CLK), + .ddc_setup = 0, + .phy_aux_cntl = 0, + .dc_gpio_aux_ctrl_5 = 0 + } +}; + +static const struct ddc_sh_mask ddc_shift[] = { + DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), + DDC_MASK_SH_LIST_DCN2(__SHIFT, 6), + DDC_MASK_SH_LIST_DCN2_VGA(__SHIFT) +}; + +static const struct ddc_sh_mask ddc_mask[] = { + DDC_MASK_SH_LIST_DCN2(_MASK, 1), + DDC_MASK_SH_LIST_DCN2(_MASK, 2), + DDC_MASK_SH_LIST_DCN2(_MASK, 3), + DDC_MASK_SH_LIST_DCN2(_MASK, 4), + DDC_MASK_SH_LIST_DCN2(_MASK, 5), + DDC_MASK_SH_LIST_DCN2(_MASK, 6), + DDC_MASK_SH_LIST_DCN2_VGA(_MASK) +}; + +#include "../generic_regs.h" + +/* set field name */ +#define SF_GENERIC(reg_name, field_name, post_fix)\ + .field_name = 0 + +static const struct generic_registers generic_regs[] = { + {{ 0 }}, + {{ 0 }}, +}; + +static const struct generic_sh_mask generic_shift[] = { + { 0 }, + { 0 }, +}; + +static const struct generic_sh_mask generic_mask[] = { + { 0 }, + { 0 }, +}; + +static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en) +{ + struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin); + + generic->regs = &generic_regs[en]; + generic->shifts = &generic_shift[en]; + generic->masks = &generic_mask[en]; + generic->base.regs = &generic_regs[en].gpio; +} + +static void define_ddc_registers( + struct hw_gpio_pin *pin, + uint32_t en) +{ + struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin); + + switch (pin->id) { + case GPIO_ID_DDC_DATA: + ddc->regs = &ddc_data_regs_dcn[en]; + ddc->base.regs = &ddc_data_regs_dcn[en].gpio; + break; + case GPIO_ID_DDC_CLOCK: + ddc->regs = &ddc_clk_regs_dcn[en]; + ddc->base.regs = &ddc_clk_regs_dcn[en].gpio; + break; + default: + ASSERT_CRITICAL(false); + return; + } + + ddc->shifts = &ddc_shift[en]; + ddc->masks = &ddc_mask[en]; + +} + +static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en) +{ + struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin); + + hpd->regs = &hpd_regs[en]; + hpd->shifts = &hpd_shift; + hpd->masks = &hpd_mask; + hpd->base.regs = &hpd_regs[en].gpio; +} + + +/* function table */ +static const struct hw_factory_funcs funcs = { + .init_ddc_data = dal_hw_ddc_init, + .init_generic = dal_hw_generic_init, + .init_hpd = dal_hw_hpd_init, + .get_ddc_pin = dal_hw_ddc_get_pin, + .get_hpd_pin = dal_hw_hpd_get_pin, + .get_generic_pin = dal_hw_generic_get_pin, + .define_hpd_registers = define_hpd_registers, + .define_ddc_registers = define_ddc_registers, + .define_generic_registers = define_generic_registers +}; + +/* + * dal_hw_factory_dcn42_init + * + * @brief + * Initialize HW factory function pointers and pin info + * + * @param + * struct hw_factory *factory - [out] struct of function pointers + */ +void dal_hw_factory_dcn42_init(struct hw_factory *factory) +{ + factory->number_of_pins[GPIO_ID_DDC_DATA] = 8; + factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8; + factory->number_of_pins[GPIO_ID_GENERIC] = 4; + factory->number_of_pins[GPIO_ID_HPD] = 5; + factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28; + factory->number_of_pins[GPIO_ID_VIP_PAD] = 0; + factory->number_of_pins[GPIO_ID_SYNC] = 0; + factory->number_of_pins[GPIO_ID_GSL] = 0;/*add this*/ + + factory->funcs = &funcs; +} diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h new file mode 100644 index 0000000000000..b723380eb17f5 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_factory_dcn42.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DAL_HW_FACTORY_DCN42_H__ +#define __DAL_HW_FACTORY_DCN42_H__ + +/* Initialize HW factory function pointers and pin info */ +void dal_hw_factory_dcn42_init(struct hw_factory *factory); + +#endif /* __DAL_HW_FACTORY_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c new file mode 100644 index 0000000000000..dcbcf6b85abff --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "hw_translate_dcn42.h" + +#include "dm_services.h" +#include "include/gpio_types.h" +#include "../hw_translate.h" + + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" +#include "dpcs/dpcs_4_0_0_offset.h" +#include "dpcs/dpcs_4_0_0_sh_mask.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +/* begin ********************* + * macros to expend register list macro defined in HW object header file */ + +/* DCN */ +#define block HPD +#define reg_num 0 + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +#define BASE(seg) BASE_INNER(seg) + +#undef REG +#define REG(reg_name)\ + (BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name) +#define SF_HPD(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + + +/* macros to expend register list macro defined in HW object header file + * end *********************/ + + +static bool offset_to_id( + uint32_t offset, + uint32_t mask, + enum gpio_id *id, + uint32_t *en) +{ + switch (offset) { + /* HPD */ + case REG(HPD0_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_1; + return true; + case REG(HPD1_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_2; + return true; + case REG(HPD2_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_3; + return true; + case REG(HPD3_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_4; + return true; + case REG(HPD4_DC_HPD_INT_STATUS): + *id = GPIO_ID_HPD; + *en = GPIO_HPD_5; + return true; + /* DDC */ + /* we don't care about the GPIO_ID for DDC + * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK + * directly in the create method + */ + case REG(DC_GPIO_DDC1_A): + *en = GPIO_DDC_LINE_DDC1; + return true; + case REG(DC_GPIO_DDC2_A): + *en = GPIO_DDC_LINE_DDC2; + return true; + case REG(DC_GPIO_DDC3_A): + *en = GPIO_DDC_LINE_DDC3; + return true; + case REG(DC_GPIO_DDC4_A): + *en = GPIO_DDC_LINE_DDC4; + return true; + case REG(DC_GPIO_DDC5_A): + *en = GPIO_DDC_LINE_DDC5; + return true; + case REG(DC_GPIO_DDCVGA_A): + *en = GPIO_DDC_LINE_DDC_VGA; + return true; + default: + ASSERT_CRITICAL(false); + return false; + } +} + + +static bool id_to_offset( + enum gpio_id id, + uint32_t en, + struct gpio_pin_info *info) +{ + bool result = true; + + switch (id) { + case GPIO_ID_DDC_DATA: + info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK; + switch (en) { + case GPIO_DDC_LINE_DDC1: + info->offset = REG(DC_GPIO_DDC1_A); + break; + case GPIO_DDC_LINE_DDC2: + info->offset = REG(DC_GPIO_DDC2_A); + break; + case GPIO_DDC_LINE_DDC3: + info->offset = REG(DC_GPIO_DDC3_A); + break; + case GPIO_DDC_LINE_DDC4: + info->offset = REG(DC_GPIO_DDC4_A); + break; + case GPIO_DDC_LINE_DDC5: + info->offset = REG(DC_GPIO_DDC5_A); + break; + case GPIO_DDC_LINE_DDC_VGA: + info->offset = REG(DC_GPIO_DDCVGA_A); + break; + case GPIO_DDC_LINE_I2C_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_DDC_CLOCK: + info->mask = DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK; + switch (en) { + case GPIO_DDC_LINE_DDC1: + info->offset = REG(DC_GPIO_DDC1_A); + break; + case GPIO_DDC_LINE_DDC2: + info->offset = REG(DC_GPIO_DDC2_A); + break; + case GPIO_DDC_LINE_DDC3: + info->offset = REG(DC_GPIO_DDC3_A); + break; + case GPIO_DDC_LINE_DDC4: + info->offset = REG(DC_GPIO_DDC4_A); + break; + case GPIO_DDC_LINE_DDC5: + info->offset = REG(DC_GPIO_DDC5_A); + break; + case GPIO_DDC_LINE_DDC_VGA: + info->offset = REG(DC_GPIO_DDCVGA_A); + break; + case GPIO_DDC_LINE_I2C_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + break; + case GPIO_ID_SYNC: + case GPIO_ID_VIP_PAD: + default: + ASSERT_CRITICAL(false); + result = false; + } + + if (result) { + info->offset_y = info->offset + 2; + info->offset_en = info->offset + 1; + info->offset_mask = info->offset - 1; + + info->mask_y = info->mask; + info->mask_en = info->mask; + info->mask_mask = info->mask; + } + + return result; +} + + +/* function table */ +static const struct hw_translate_funcs funcs = { + .offset_to_id = offset_to_id, + .id_to_offset = id_to_offset, +}; + + +/* + * dal_hw_translate_dcn42_init + * + * @brief + * Initialize Hw translate function pointers. + * + * @param + * struct hw_translate *tr - [out] struct of function pointers + * + */ +void dal_hw_translate_dcn42_init(struct hw_translate *tr) +{ + tr->funcs = &funcs; +} + + diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h new file mode 100644 index 0000000000000..007b4d55fef1f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn42/hw_translate_dcn42.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __DAL_HW_TRANSLATE_DCN42_H__ +#define __DAL_HW_TRANSLATE_DCN42_H__ + +struct hw_translate; + +/* Initialize Hw translate function pointers */ +void dal_hw_translate_dcn42_init(struct hw_translate *tr); +#ifdef DAL_EMULATION_SUPPORTED +void dal_emulated_hw_translate_dcn42_init(struct hw_translate *tr); +#endif + +#endif /* __DAL_HW_TRANSLATE_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 8bc67ca421977..f3d562c8df4c9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -53,6 +53,7 @@ #include "dcn315/hw_factory_dcn315.h" #include "dcn32/hw_factory_dcn32.h" #include "dcn401/hw_factory_dcn401.h" +#include "dcn42/hw_factory_dcn42.h" bool dal_hw_factory_init( struct hw_factory *factory, @@ -118,6 +119,9 @@ bool dal_hw_factory_init( case DCN_VERSION_4_01: dal_hw_factory_dcn401_init(factory); return true; + case DCN_VERSION_4_2: + dal_hw_factory_dcn42_init(factory); + return true; default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index cb79a28322877..1c977fc4d0e36 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -53,6 +53,7 @@ #include "dcn315/hw_translate_dcn315.h" #include "dcn32/hw_translate_dcn32.h" #include "dcn401/hw_translate_dcn401.h" +#include "dcn42/hw_translate_dcn42.h" /* * This unit @@ -119,6 +120,9 @@ bool dal_hw_translate_init( case DCN_VERSION_4_01: dal_hw_translate_dcn401_init(translate); return true; + case DCN_VERSION_4_2: + dal_hw_translate_dcn42_init(translate); + return true; default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/hpo/Makefile b/drivers/gpu/drm/amd/display/dc/hpo/Makefile index 7f2c9ee0dff1d..25b196714bd8c 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hpo/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -47,4 +47,13 @@ HPO_DCN32 = dcn32_hpo_dp_link_encoder.o AMD_DAL_HPO_DCN32 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn32/,$(HPO_DCN32)) AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN32) + +############################################################################### +# DCN42 +############################################################################### +HPO_DCN42 = dcn42_hpo_dp_link_encoder.o + +AMD_DAL_HPO_DCN42 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn42/,$(HPO_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 759b453385c46..92ed130aeaec9 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -640,6 +640,11 @@ static void dcn31_hpo_dp_stream_enc_audio_setup( REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, az_inst); + if (enc3->hpo_se_mask->DP_STREAM_ENC_APG_CLOCK_EN) { + /*enable apg clk*/ + REG_UPDATE(DP_STREAM_ENC_AUDIO_CONTROL, + DP_STREAM_ENC_APG_CLOCK_EN, 1); + } ASSERT(enc->apg); enc->apg->funcs->se_audio_setup(enc->apg, az_inst, info); } diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h index 82c3b3ac1f0d0..d96fcc59cc0ee 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2019-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -208,17 +208,24 @@ type CRC_CONT_MODE_ENABLE;\ type HBLANK_MINIMUM_SYMBOL_WIDTH +#define DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \ + type DP_STREAM_ENC_APG_CLOCK_EN +#define DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\ + DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh),\ + SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_APG_CLOCK_EN, mask_sh) struct dcn31_hpo_dp_stream_encoder_registers { DCN3_1_HPO_DP_STREAM_ENC_REGS; }; struct dcn31_hpo_dp_stream_encoder_shift { DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t); + DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t); }; struct dcn31_hpo_dp_stream_encoder_mask { DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t); + DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t); }; struct dcn31_hpo_dp_stream_encoder { @@ -241,5 +248,4 @@ void dcn31_hpo_dp_stream_encoder_construct( const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift, const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask); - #endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__ diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c new file mode 100644 index 0000000000000..4b86b1bf6503f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dc_bios_types.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32/dcn32_hpo_dp_link_encoder.h" +#include "dcn42_hpo_dp_link_encoder.h" +#include "reg_helper.h" +#include "stream_encoder.h" + +#define DC_LOGGER \ + enc3->base.ctx->logger + +#define REG(reg)\ + (enc3->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + enc3->hpo_le_shift->field_name, enc3->hpo_le_mask->field_name + + +#define CTX \ + enc3->base.ctx + + +static void dcn42_hpo_dp_link_enc_read_state( + struct hpo_dp_link_encoder *enc, + struct hpo_dp_link_enc_state *state) +{ + struct dcn31_hpo_dp_link_encoder *enc3 = DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(enc); + + ASSERT(state); + + REG_GET(DP_DPHY_SYM32_STATUS, + STATUS, &state->link_enc_enabled); + REG_GET(DP_DPHY_SYM32_CONTROL, + NUM_LANES, &state->lane_count); + REG_GET(DP_DPHY_SYM32_CONTROL, + MODE, (uint32_t *)&state->link_mode); + + REG_GET_2(DP_DPHY_SYM32_SAT_VC0, + SAT_STREAM_SOURCE, &state->stream_src[0], + SAT_SLOT_COUNT, &state->slot_count[0]); + REG_GET_2(DP_DPHY_SYM32_SAT_VC1, + SAT_STREAM_SOURCE, &state->stream_src[1], + SAT_SLOT_COUNT, &state->slot_count[1]); + REG_GET_2(DP_DPHY_SYM32_SAT_VC2, + SAT_STREAM_SOURCE, &state->stream_src[2], + SAT_SLOT_COUNT, &state->slot_count[2]); + + REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL0, + STREAM_VC_RATE_X, &state->vc_rate_x[0], + STREAM_VC_RATE_Y, &state->vc_rate_y[0]); + REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL1, + STREAM_VC_RATE_X, &state->vc_rate_x[1], + STREAM_VC_RATE_Y, &state->vc_rate_y[1]); + REG_GET_2(DP_DPHY_SYM32_VC_RATE_CNTL2, + STREAM_VC_RATE_X, &state->vc_rate_x[2], + STREAM_VC_RATE_Y, &state->vc_rate_y[2]); +} + +static struct hpo_dp_link_encoder_funcs dcn42_hpo_dp_link_encoder_funcs = { + .enable_link_phy = dcn31_hpo_dp_link_enc_enable_dp_output, + .disable_link_phy = dcn31_hpo_dp_link_enc_disable_output, + .link_enable = dcn31_hpo_dp_link_enc_enable, + .link_disable = dcn31_hpo_dp_link_enc_disable, + .set_link_test_pattern = dcn31_hpo_dp_link_enc_set_link_test_pattern, + .update_stream_allocation_table = dcn31_hpo_dp_link_enc_update_stream_allocation_table, + .set_throttled_vcp_size = dcn31_hpo_dp_link_enc_set_throttled_vcp_size, + .is_in_alt_mode = dcn32_hpo_dp_link_enc_is_in_alt_mode, + .read_state = dcn42_hpo_dp_link_enc_read_state, + .set_ffe = dcn31_hpo_dp_link_enc_set_ffe, +}; + +void hpo_dp_link_encoder42_construct(struct dcn31_hpo_dp_link_encoder *enc31, + struct dc_context *ctx, + uint32_t inst, + const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, + const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, + const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask) +{ + enc31->base.ctx = ctx; + + enc31->base.inst = inst; + enc31->base.funcs = &dcn42_hpo_dp_link_encoder_funcs; + enc31->base.hpd_source = HPD_SOURCEID_UNKNOWN; + enc31->base.transmitter = TRANSMITTER_UNKNOWN; + + enc31->regs = hpo_le_regs; + enc31->hpo_le_shift = hpo_le_shift; + enc31->hpo_le_mask = hpo_le_mask; +} diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h new file mode 100644 index 0000000000000..3e84d016507cf --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn42/dcn42_hpo_dp_link_encoder.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + + +#ifndef __DAL_DCN42_HPO_DP_LINK_ENCODER_H__ +#define __DAL_DCN42_HPO_DP_LINK_ENCODER_H__ + +#include "link_encoder.h" + +void hpo_dp_link_encoder42_construct(struct dcn31_hpo_dp_link_encoder *enc31, + struct dc_context *ctx, + uint32_t inst, + const struct dcn31_hpo_dp_link_encoder_registers *hpo_le_regs, + const struct dcn31_hpo_dp_link_encoder_shift *hpo_le_shift, + const struct dcn31_hpo_dp_link_encoder_mask *hpo_le_mask); + +#endif // __DAL_DCN32_HPO_DP_LINK_ENCODER_H__ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile index 66ca5a6a0415e..29c8e2651442b 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hubbub/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -101,4 +101,12 @@ AMD_DAL_HUBBUB_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn401/,$(HUBBUB_DCN AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN401) ############################################################################### +# DCN42 +############################################################################### +HUBBUB_DCN42 = dcn42_hubbub.o + +AMD_DAL_HUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubbub/dcn42/,$(HUBBUB_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HUBBUB_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c index 7847c1c4927bf..97ef8281a476e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c @@ -944,3 +944,21 @@ void hubbub1_construct(struct hubbub *hubbub, hubbub1->debug_test_index_pstate = 0xB; } +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + if (refdiv > 0) + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, refdiv); + + REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, enable ? 1 : 0); +} + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value) +{ + struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub); + + REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, fb_base_value); + REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, fb_offset_value); +} + diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index fa5c4c18ed598..ff9a1ae29474f 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -1,5 +1,5 @@ /* - * Copyright 2016 Advanced Micro Devices, Inc. + * Copyright 2016-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -437,8 +437,12 @@ struct dcn_hubbub_registers { type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_A;\ type DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B;\ type DCHUBBUB_ARB_FRAC_URG_BW_MALL_A;\ - type DCHUBBUB_ARB_FRAC_URG_BW_MALL_B + type DCHUBBUB_ARB_FRAC_URG_BW_MALL_B;\ + type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE;\ + type DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE +#define HUBBUB_REG_FIELD_LIST_DCN4_2(type) \ + type URGENT_ZERO_SIZE_REQ_EN struct dcn_hubbub_shift { DCN_HUBBUB_REG_FIELD_LIST(uint8_t); HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); @@ -447,6 +451,8 @@ struct dcn_hubbub_shift { HUBBUB_REG_FIELD_LIST_DCN32(uint8_t); HUBBUB_REG_FIELD_LIST_DCN35(uint8_t); HUBBUB_REG_FIELD_LIST_DCN4_01(uint8_t); + HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t); + }; struct dcn_hubbub_mask { @@ -457,6 +463,8 @@ struct dcn_hubbub_mask { HUBBUB_REG_FIELD_LIST_DCN32(uint32_t); HUBBUB_REG_FIELD_LIST_DCN35(uint32_t); HUBBUB_REG_FIELD_LIST_DCN4_01(uint32_t); + HUBBUB_REG_FIELD_LIST_DCN4_2(uint8_t); + }; struct dc; @@ -515,4 +523,8 @@ bool hubbub1_program_pstate_watermarks( unsigned int refclk_mhz, bool safe_to_lower); +void dcn10_hubbub_global_timer_enable(struct hubbub *hubbub, bool enable, uint32_t refdiv); + +void dcn10_hubbub_read_fb_aperture(struct hubbub *hubbub, uint32_t *fb_base_value, uint32_t *fb_offset_value); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index d11afd1ce72a2..b0a4b68cf359a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -41,7 +41,7 @@ #define FN(reg_name, field_name) \ hubbub2->shifts->field_name, hubbub2->masks->field_name -static void dcn401_init_crb(struct hubbub *hubbub) +void dcn401_init_crb(struct hubbub *hubbub) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1110,7 +1110,7 @@ bool hubbub401_get_dcc_compression_cap(struct hubbub *hubbub, return true; } -static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg) +void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1147,12 +1147,10 @@ static void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, un } } -static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase) +void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); - unsigned int cur_compbuf_size_seg = 0; - if (safe_to_increase || compbuf_size_seg <= hubbub2->compbuf_size_segments) { if (compbuf_size_seg > hubbub2->compbuf_size_segments) { REG_WAIT(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, hubbub2->det0_size, 1, 100); @@ -1165,12 +1163,10 @@ static void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned comp + hubbub2->det3_size + compbuf_size_seg <= hubbub2->crb_size_segs); REG_UPDATE(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, compbuf_size_seg); hubbub2->compbuf_size_segments = compbuf_size_seg; - - ASSERT(REG_GET(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, &cur_compbuf_size_seg) && !cur_compbuf_size_seg); } } -static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) +void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); @@ -1192,7 +1188,7 @@ static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) } } -static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower) +bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h index b1d9ea9d1c3d6..f487155444299 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h @@ -194,6 +194,11 @@ bool hubbub401_get_dcc_compression_cap( const struct dc_dcc_surface_param *input, struct dc_surface_dcc_cap *output); +bool dcn401_program_arbiter( + struct hubbub *hubbub, + struct dml2_display_arb_regs *arb_regs, + bool safe_to_lower); + void hubbub401_construct(struct dcn20_hubbub *hubbub2, struct dc_context *ctx, const struct dcn_hubbub_registers *hubbub_regs, @@ -203,4 +208,9 @@ void hubbub401_construct(struct dcn20_hubbub *hubbub2, int pixel_chunk_size_kb, int config_return_buffer_size_kb); +void dcn401_program_det_segments(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); +void dcn401_program_compbuf_segments(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); +void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst); +void dcn401_init_crb(struct hubbub *hubbub); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c new file mode 100644 index 0000000000000..a436fa71d4b43 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.c @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn30/dcn30_hubbub.h" +#include "dcn31/dcn31_hubbub.h" +#include "dcn32/dcn32_hubbub.h" +#include "dcn35/dcn35_hubbub.h" +#include "dcn401/dcn401_hubbub.h" +#include "dcn42/dcn42_hubbub.h" +#include "dm_services.h" +#include "reg_helper.h" + +#define DCN42_CRB_SEGMENT_SIZE_KB 64 + +#define CTX \ + hubbub2->base.ctx +#define DC_LOGGER \ + hubbub2->base.ctx->logger +#define REG(reg)\ + hubbub2->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hubbub2->shifts->field_name, hubbub2->masks->field_name + +static bool hubbub42_program_urgent_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* Repeat for water mark set A, B, C and D. */ + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.urgent > hubbub2->watermarks.dcn4x.a.urgent) { + hubbub2->watermarks.dcn4x.a.urgent = watermarks->dcn4x.a.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, watermarks->dcn4x.a.urgent); + } else if (watermarks->dcn4x.a.urgent < hubbub2->watermarks.dcn4x.a.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip = watermarks->dcn4x.a.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->dcn4x.a.frac_urg_bw_flip); + } else if (watermarks->dcn4x.a.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.a.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.a.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.a.frac_urg_bw_nom = watermarks->dcn4x.a.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, watermarks->dcn4x.a.frac_urg_bw_nom); + } else if (watermarks->dcn4x.a.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.a.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.a.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.a.refcyc_per_trip_to_mem = watermarks->dcn4x.a.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, watermarks->dcn4x.a.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.a.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.a.refcyc_per_trip_to_mem) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.urgent > hubbub2->watermarks.dcn4x.b.urgent) { + hubbub2->watermarks.dcn4x.b.urgent = watermarks->dcn4x.b.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, watermarks->dcn4x.b.urgent); + } else if (watermarks->dcn4x.b.urgent < hubbub2->watermarks.dcn4x.b.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.b.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.b.frac_urg_bw_flip = watermarks->dcn4x.b.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, watermarks->dcn4x.b.frac_urg_bw_flip); + } else if (watermarks->dcn4x.b.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.b.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.b.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.b.frac_urg_bw_nom = watermarks->dcn4x.b.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, watermarks->dcn4x.b.frac_urg_bw_nom); + } else if (watermarks->dcn4x.b.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.b.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.b.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.b.refcyc_per_trip_to_mem = watermarks->dcn4x.b.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, watermarks->dcn4x.b.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.b.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.b.refcyc_per_trip_to_mem) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.urgent > hubbub2->watermarks.dcn4x.c.urgent) { + hubbub2->watermarks.dcn4x.c.urgent = watermarks->dcn4x.c.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, watermarks->dcn4x.c.urgent); + } else if (watermarks->dcn4x.c.urgent < hubbub2->watermarks.dcn4x.c.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.c.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.c.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.c.frac_urg_bw_flip = watermarks->dcn4x.c.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, watermarks->dcn4x.c.frac_urg_bw_flip); + } else if (watermarks->dcn4x.c.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.c.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.c.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.c.frac_urg_bw_nom = watermarks->dcn4x.c.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, watermarks->dcn4x.c.frac_urg_bw_nom); + } else if (watermarks->dcn4x.c.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.c.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.c.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.c.refcyc_per_trip_to_mem = watermarks->dcn4x.c.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, watermarks->dcn4x.c.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.c.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.c.refcyc_per_trip_to_mem) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.urgent > hubbub2->watermarks.dcn4x.d.urgent) { + hubbub2->watermarks.dcn4x.d.urgent = watermarks->dcn4x.d.urgent; + REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0, + DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, watermarks->dcn4x.d.urgent); + } else if (watermarks->dcn4x.d.urgent < hubbub2->watermarks.dcn4x.d.urgent) + wm_pending = true; + + /* determine the transfer time for a quantity of data for a particular requestor.*/ + if (safe_to_lower || watermarks->dcn4x.d.frac_urg_bw_flip > hubbub2->watermarks.dcn4x.d.frac_urg_bw_flip) { + hubbub2->watermarks.dcn4x.d.frac_urg_bw_flip = watermarks->dcn4x.d.frac_urg_bw_flip; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, watermarks->dcn4x.d.frac_urg_bw_flip); + } else if (watermarks->dcn4x.d.frac_urg_bw_flip < hubbub2->watermarks.dcn4x.d.frac_urg_bw_flip) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.frac_urg_bw_nom > hubbub2->watermarks.dcn4x.d.frac_urg_bw_nom) { + hubbub2->watermarks.dcn4x.d.frac_urg_bw_nom = watermarks->dcn4x.d.frac_urg_bw_nom; + REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, 0, + DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, watermarks->dcn4x.d.frac_urg_bw_nom); + } else if (watermarks->dcn4x.d.frac_urg_bw_nom < hubbub2->watermarks.dcn4x.d.frac_urg_bw_nom) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.refcyc_per_trip_to_mem > hubbub2->watermarks.dcn4x.d.refcyc_per_trip_to_mem) { + hubbub2->watermarks.dcn4x.d.refcyc_per_trip_to_mem = watermarks->dcn4x.d.refcyc_per_trip_to_mem; + REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 0, + DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, watermarks->dcn4x.d.refcyc_per_trip_to_mem); + } else if (watermarks->dcn4x.d.refcyc_per_trip_to_mem < hubbub2->watermarks.dcn4x.d.refcyc_per_trip_to_mem) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_stutter_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.sr_enter > hubbub2->watermarks.dcn4x.a.sr_enter) { + hubbub2->watermarks.dcn4x.a.sr_enter = watermarks->dcn4x.a.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, watermarks->dcn4x.a.sr_enter); + } else if (watermarks->dcn4x.a.sr_enter < hubbub2->watermarks.dcn4x.a.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.sr_exit > hubbub2->watermarks.dcn4x.a.sr_exit) { + hubbub2->watermarks.dcn4x.a.sr_exit = watermarks->dcn4x.a.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, watermarks->dcn4x.a.sr_exit); + } else if (watermarks->dcn4x.a.sr_exit < hubbub2->watermarks.dcn4x.a.sr_exit) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.sr_enter > hubbub2->watermarks.dcn4x.b.sr_enter) { + hubbub2->watermarks.dcn4x.b.sr_enter = watermarks->dcn4x.b.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, watermarks->dcn4x.b.sr_enter); + } else if (watermarks->dcn4x.b.sr_enter < hubbub2->watermarks.dcn4x.b.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.sr_exit > hubbub2->watermarks.dcn4x.b.sr_exit) { + hubbub2->watermarks.dcn4x.b.sr_exit = watermarks->dcn4x.b.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, watermarks->dcn4x.b.sr_exit); + } else if (watermarks->dcn4x.b.sr_exit < hubbub2->watermarks.dcn4x.b.sr_exit) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.sr_enter > hubbub2->watermarks.dcn4x.c.sr_enter) { + hubbub2->watermarks.dcn4x.c.sr_enter = watermarks->dcn4x.c.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, watermarks->dcn4x.c.sr_enter); + } else if (watermarks->dcn4x.c.sr_enter < hubbub2->watermarks.dcn4x.c.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.sr_exit > hubbub2->watermarks.dcn4x.c.sr_exit) { + hubbub2->watermarks.dcn4x.c.sr_exit = watermarks->dcn4x.c.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, watermarks->dcn4x.c.sr_exit); + } else if (watermarks->dcn4x.c.sr_exit < hubbub2->watermarks.dcn4x.c.sr_exit) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.sr_enter > hubbub2->watermarks.dcn4x.d.sr_enter) { + hubbub2->watermarks.dcn4x.d.sr_enter = watermarks->dcn4x.d.sr_enter; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, watermarks->dcn4x.d.sr_enter); + } else if (watermarks->dcn4x.d.sr_enter < hubbub2->watermarks.dcn4x.d.sr_enter) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.sr_exit > hubbub2->watermarks.dcn4x.d.sr_exit) { + hubbub2->watermarks.dcn4x.d.sr_exit = watermarks->dcn4x.d.sr_exit; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, watermarks->dcn4x.d.sr_exit); + } else if (watermarks->dcn4x.d.sr_exit < hubbub2->watermarks.dcn4x.d.sr_exit) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_pstate_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* Section for UCLK_PSTATE_CHANGE_WATERMARKS */ + /* UCLK state A */ + if (safe_to_lower || watermarks->dcn4x.a.uclk_pstate > hubbub2->watermarks.dcn4x.a.uclk_pstate) { + hubbub2->watermarks.dcn4x.a.uclk_pstate = watermarks->dcn4x.a.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, watermarks->dcn4x.a.uclk_pstate); + } else if (watermarks->dcn4x.a.uclk_pstate < hubbub2->watermarks.dcn4x.a.uclk_pstate) + wm_pending = true; + + /* UCLK state B */ + if (safe_to_lower || watermarks->dcn4x.b.uclk_pstate > hubbub2->watermarks.dcn4x.b.uclk_pstate) { + hubbub2->watermarks.dcn4x.b.uclk_pstate = watermarks->dcn4x.b.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, watermarks->dcn4x.b.uclk_pstate); + } else if (watermarks->dcn4x.b.uclk_pstate < hubbub2->watermarks.dcn4x.b.uclk_pstate) + wm_pending = true; + + /* UCLK state C */ + if (safe_to_lower || watermarks->dcn4x.c.uclk_pstate > hubbub2->watermarks.dcn4x.c.uclk_pstate) { + hubbub2->watermarks.dcn4x.c.uclk_pstate = watermarks->dcn4x.c.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, watermarks->dcn4x.c.uclk_pstate); + } else if (watermarks->dcn4x.c.uclk_pstate < hubbub2->watermarks.dcn4x.c.uclk_pstate) + wm_pending = true; + + /* UCLK state D */ + if (safe_to_lower || watermarks->dcn4x.d.uclk_pstate > hubbub2->watermarks.dcn4x.d.uclk_pstate) { + hubbub2->watermarks.dcn4x.d.uclk_pstate = watermarks->dcn4x.d.uclk_pstate; + REG_SET(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, watermarks->dcn4x.d.uclk_pstate); + } else if (watermarks->dcn4x.d.uclk_pstate < hubbub2->watermarks.dcn4x.d.uclk_pstate) + wm_pending = true; + + /* Section for FCLK_PSTATE_CHANGE_WATERMARKS */ + /* FCLK state A */ + if (safe_to_lower || watermarks->dcn4x.a.fclk_pstate > hubbub2->watermarks.dcn4x.a.fclk_pstate) { + hubbub2->watermarks.dcn4x.a.fclk_pstate = watermarks->dcn4x.a.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, watermarks->dcn4x.a.fclk_pstate); + } else if (watermarks->dcn4x.a.fclk_pstate < hubbub2->watermarks.dcn4x.a.fclk_pstate) + wm_pending = true; + + /* FCLK state B */ + if (safe_to_lower || watermarks->dcn4x.b.fclk_pstate > hubbub2->watermarks.dcn4x.b.fclk_pstate) { + hubbub2->watermarks.dcn4x.b.fclk_pstate = watermarks->dcn4x.b.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, watermarks->dcn4x.b.fclk_pstate); + } else if (watermarks->dcn4x.b.fclk_pstate < hubbub2->watermarks.dcn4x.b.fclk_pstate) + wm_pending = true; + + /* FCLK state C */ + if (safe_to_lower || watermarks->dcn4x.c.fclk_pstate > hubbub2->watermarks.dcn4x.c.fclk_pstate) { + hubbub2->watermarks.dcn4x.c.fclk_pstate = watermarks->dcn4x.c.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, watermarks->dcn4x.c.fclk_pstate); + } else if (watermarks->dcn4x.c.fclk_pstate < hubbub2->watermarks.dcn4x.c.fclk_pstate) + wm_pending = true; + + /* FCLK state D */ + if (safe_to_lower || watermarks->dcn4x.d.fclk_pstate > hubbub2->watermarks.dcn4x.d.fclk_pstate) { + hubbub2->watermarks.dcn4x.d.fclk_pstate = watermarks->dcn4x.d.fclk_pstate; + REG_SET(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, 0, + DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, watermarks->dcn4x.d.fclk_pstate); + } else if (watermarks->dcn4x.d.fclk_pstate < hubbub2->watermarks.dcn4x.d.fclk_pstate) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_usr_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.usr > hubbub2->watermarks.dcn4x.a.usr) { + hubbub2->watermarks.dcn4x.a.usr = watermarks->dcn4x.a.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, watermarks->dcn4x.a.usr); + } else if (watermarks->dcn4x.a.usr < hubbub2->watermarks.dcn4x.a.usr) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.usr > hubbub2->watermarks.dcn4x.b.usr) { + hubbub2->watermarks.dcn4x.b.usr = watermarks->dcn4x.b.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, watermarks->dcn4x.b.usr); + } else if (watermarks->dcn4x.b.usr < hubbub2->watermarks.dcn4x.b.usr) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.usr > hubbub2->watermarks.dcn4x.c.usr) { + hubbub2->watermarks.dcn4x.c.usr = watermarks->dcn4x.c.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, watermarks->dcn4x.c.usr); + } else if (watermarks->dcn4x.c.usr < hubbub2->watermarks.dcn4x.c.usr) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.usr > hubbub2->watermarks.dcn4x.d.usr) { + hubbub2->watermarks.dcn4x.d.usr = watermarks->dcn4x.d.usr; + REG_SET(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, 0, + DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, watermarks->dcn4x.d.usr); + } else if (watermarks->dcn4x.d.usr < hubbub2->watermarks.dcn4x.d.usr) + wm_pending = true; + + return wm_pending; +} + +static bool hubbub42_program_stutter_z8_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + + /* clock state A */ + if (safe_to_lower || watermarks->dcn4x.a.sr_enter_z8 > hubbub2->watermarks.dcn4x.a.sr_enter_z8) { + hubbub2->watermarks.dcn4x.a.sr_enter_z8 = watermarks->dcn4x.a.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, watermarks->dcn4x.a.sr_enter_z8); + } else if (watermarks->dcn4x.a.sr_enter_z8 < hubbub2->watermarks.dcn4x.a.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.a.sr_exit_z8 > hubbub2->watermarks.dcn4x.a.sr_exit_z8) { + hubbub2->watermarks.dcn4x.a.sr_exit_z8 = watermarks->dcn4x.a.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, watermarks->dcn4x.a.sr_exit_z8); + } else if (watermarks->dcn4x.a.sr_exit_z8 < hubbub2->watermarks.dcn4x.a.sr_exit_z8) + wm_pending = true; + + /* clock state B */ + if (safe_to_lower || watermarks->dcn4x.b.sr_enter_z8 > hubbub2->watermarks.dcn4x.b.sr_enter_z8) { + hubbub2->watermarks.dcn4x.b.sr_enter_z8 = watermarks->dcn4x.b.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, watermarks->dcn4x.b.sr_enter_z8); + } else if (watermarks->dcn4x.b.sr_enter_z8 < hubbub2->watermarks.dcn4x.b.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.b.sr_exit_z8 > hubbub2->watermarks.dcn4x.b.sr_exit_z8) { + hubbub2->watermarks.dcn4x.b.sr_exit_z8 = watermarks->dcn4x.b.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, watermarks->dcn4x.b.sr_exit_z8); + } else if (watermarks->dcn4x.b.sr_exit_z8 < hubbub2->watermarks.dcn4x.b.sr_exit_z8) + wm_pending = true; + + /* clock state C */ + if (safe_to_lower || watermarks->dcn4x.c.sr_enter_z8 > hubbub2->watermarks.dcn4x.c.sr_enter_z8) { + hubbub2->watermarks.dcn4x.c.sr_enter_z8 = watermarks->dcn4x.c.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, watermarks->dcn4x.c.sr_enter_z8); + } else if (watermarks->dcn4x.c.sr_enter_z8 < hubbub2->watermarks.dcn4x.c.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.c.sr_exit_z8 > hubbub2->watermarks.dcn4x.c.sr_exit_z8) { + hubbub2->watermarks.dcn4x.c.sr_exit_z8 = watermarks->dcn4x.c.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, watermarks->dcn4x.c.sr_exit_z8); + } else if (watermarks->dcn4x.c.sr_exit_z8 < hubbub2->watermarks.dcn4x.c.sr_exit_z8) + wm_pending = true; + + /* clock state D */ + if (safe_to_lower || watermarks->dcn4x.d.sr_enter_z8 > hubbub2->watermarks.dcn4x.d.sr_enter_z8) { + hubbub2->watermarks.dcn4x.d.sr_enter_z8 = watermarks->dcn4x.d.sr_enter_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, 0, + DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, watermarks->dcn4x.d.sr_enter_z8); + } else if (watermarks->dcn4x.d.sr_enter_z8 < hubbub2->watermarks.dcn4x.d.sr_enter_z8) + wm_pending = true; + + if (safe_to_lower || watermarks->dcn4x.d.sr_exit_z8 > hubbub2->watermarks.dcn4x.d.sr_exit_z8) { + hubbub2->watermarks.dcn4x.d.sr_exit_z8 = watermarks->dcn4x.d.sr_exit_z8; + REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, 0, + DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, watermarks->dcn4x.d.sr_exit_z8); + } else if (watermarks->dcn4x.d.sr_exit_z8 < hubbub2->watermarks.dcn4x.d.sr_exit_z8) + wm_pending = true; + + return wm_pending; +} + +static void hubbub42_allow_self_refresh_control(struct hubbub *hubbub, bool allow) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + /* + * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter + * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter + */ + + REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0, + DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow); +} +static void hubbub42_set_sdp_control(struct hubbub *hubbub, bool dc_control) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + REG_UPDATE(DCHUBBUB_SDPIF_CFG0, + SDPIF_PORT_CONTROL, dc_control); +} + +static bool hubbub42_program_watermarks( + struct hubbub *hubbub, + union dcn_watermark_set *watermarks, + unsigned int refclk_mhz, + bool safe_to_lower) +{ + bool wm_pending = false; + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + if (!safe_to_lower && hubbub->ctx->dc->debug.disable_stutter_for_wm_program) { + /* before raising watermarks, SDP control give to DF, stutter must be disabled */ + wm_pending = true; + hubbub42_set_sdp_control(hubbub, false); + hubbub42_allow_self_refresh_control(hubbub, false); + } + if (hubbub42_program_urgent_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_stutter_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_pstate_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_usr_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + if (hubbub42_program_stutter_z8_watermarks(hubbub, watermarks, safe_to_lower)) + wm_pending = true; + + REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, + DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz); + REG_UPDATE_2(DCHUBBUB_ARB_DF_REQ_OUTSTAND, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 0xFF, + DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, 0xA);/*hw delta*/ + REG_UPDATE(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, 0xF); + + if (safe_to_lower || hubbub->ctx->dc->debug.disable_stutter) + hubbub42_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter); + if (safe_to_lower && hubbub->ctx->dc->debug.disable_stutter_for_wm_program) { + hubbub42_set_sdp_control(hubbub, true); + } + hubbub32_force_usr_retraining_allow(hubbub, hubbub->ctx->dc->debug.force_usr_allow); + + return wm_pending; +} + +static void hubbub42_set_request_limit(struct hubbub *hubbub, int memory_channel_count, int words_per_channel) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + uint32_t request_limit = 96; //MAX(12 * memory_channel_count, 96); + + REG_UPDATE(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, request_limit); +} + +static bool dcn42_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, + bool safe_to_lower) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + bool wm_pending = false; + uint32_t temp; + + /* request backpressure and outstanding return threshold (unused)*/ + //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); + + /* 401 delta: do not update P-State stall threshold (handled by fw) */ + // REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); + + if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + + /* only update the required bits */ + REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); + if (hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + temp |= (1 << 5); + } else { + temp &= ~(1 << 5); + } + REG_UPDATE(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, temp); + } else { + wm_pending = true; + } + + return wm_pending; +} + +static const struct hubbub_funcs hubbub42_funcs = { + .update_dchub = hubbub2_update_dchub, + .init_dchub_sys_ctx = hubbub31_init_dchub_sys_ctx, + .init_vm_ctx = hubbub2_init_vm_ctx, + .dcc_support_swizzle = hubbub3_dcc_support_swizzle, + .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format, + .get_dcc_compression_cap = hubbub3_get_dcc_compression_cap, + .wm_read_state = hubbub35_wm_read_state, + .get_dchub_ref_freq = hubbub35_get_dchub_ref_freq, + .program_watermarks = hubbub42_program_watermarks, + .allow_self_refresh_control = hubbub42_allow_self_refresh_control, + .is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled, + .force_wm_propagate_to_pipes = hubbub32_force_wm_propagate_to_pipes, + .force_pstate_change_control = hubbub3_force_pstate_change_control, + .init_watermarks = hubbub35_init_watermarks, + .init_crb = dcn401_init_crb, + .dchvm_init = dcn35_dchvm_init, + .hubbub_read_state = hubbub2_read_state, + .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow, + .set_request_limit = hubbub42_set_request_limit, + .program_det_segments = dcn401_program_det_segments, + .program_compbuf_segments = dcn401_program_compbuf_segments, + .wait_for_det_update = dcn401_wait_for_det_update, + .program_arbiter = dcn42_program_arbiter, + .hubbub_read_reg_state = hubbub3_read_reg_state +}; + +void hubbub42_construct(struct dcn20_hubbub *hubbub2, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb) +{ + hubbub2->base.ctx = ctx; + hubbub2->base.funcs = &hubbub42_funcs; + hubbub2->regs = hubbub_regs; + hubbub2->shifts = hubbub_shift; + hubbub2->masks = hubbub_mask; + + hubbub2->detile_buf_size = det_size_kb * 1024; + hubbub2->pixel_chunk_size = pixel_chunk_size_kb * 1024; + hubbub2->crb_size_segs = config_return_buffer_size_kb / DCN42_CRB_SEGMENT_SIZE_KB; +} diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h new file mode 100644 index 0000000000000..926ddc156a2b3 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn42/dcn42_hubbub.h @@ -0,0 +1,268 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBBUB_DCN42_H__ +#define __DC_HUBBUB_DCN42_H__ + +#include "dcn32/dcn32_hubbub.h" + +#define DCN42_CRB_SIZE_KB 1792 +#define DCN42_DEFAULT_DET_SIZE 320 +#define DCN42_CRB_SEGMENT_SIZE_KB 64 + +#define HUBBUB_REG_LIST_DCN42(id)\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ + SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ + SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ + SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ + SR(DCHUBBUB_ARB_SAT_LEVEL),\ + SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DCHUBBUB_SOFT_RESET),\ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DCN_VM_FB_LOCATION_BASE),\ + SR(DCN_VM_FB_LOCATION_TOP),\ + SR(DCN_VM_FB_OFFSET),\ + SR(DCN_VM_AGP_BOT),\ + SR(DCN_VM_AGP_TOP),\ + SR(DCN_VM_AGP_BASE),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ + SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ + SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ + SR(DCHUBBUB_DET0_CTRL),\ + SR(DCHUBBUB_DET1_CTRL),\ + SR(DCHUBBUB_DET2_CTRL),\ + SR(DCHUBBUB_DET3_CTRL),\ + SR(DCHUBBUB_COMPBUF_CTRL),\ + SR(COMPBUF_RESERVED_SPACE),\ + SR(DCHUBBUB_DEBUG_CTRL_0),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ + SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ + SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ + SR(DCN_VM_FAULT_ADDR_MSB),\ + SR(DCN_VM_FAULT_ADDR_LSB),\ + SR(DCN_VM_FAULT_CNTL),\ + SR(DCN_VM_FAULT_STATUS),\ + SR(SDPIF_REQUEST_RATE_LIMIT),\ + SR(DCHUBBUB_CLOCK_CNTL),\ + SR(DCHUBBUB_SDPIF_CFG0),\ + SR(DCHUBBUB_SDPIF_CFG1),\ + SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\ + SR(DCHUBBUB_ARB_HOSTVM_CNTL),\ + SR(DCHVM_CTRL0),\ + SR(DCHVM_MEM_CTRL),\ + SR(DCHVM_CLK_CTRL),\ + SR(DCHVM_RIOMMU_CTRL0),\ + SR(DCHVM_RIOMMU_STAT0),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ + SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ + SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ + SR(DCHUBBUB_ARB_QOS_FORCE) + +#define HUBBUB_MASK_SH_LIST_DCN4_2(mask_sh)\ + HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \ + HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ + HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ + HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MAX_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_SOFT_RESET, DCHUBBUB_GLOBAL_SOFT_RESET, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MAX_REQ_OUTSTAND, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_LOCATION_TOP, FB_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BOT, AGP_BOT, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_TOP, AGP_TOP, mask_sh), \ + HUBBUB_SF(DCN_VM_AGP_BASE, AGP_BASE, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_DEBUG_CTRL_0, DET_DEPTH, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET0_CTRL, DET0_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET1_CTRL, DET1_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET2_CTRL, DET2_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_DET3_CTRL, DET3_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ + HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_CNTL, DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D, mask_sh),\ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ + HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_ADDR_MSB, DCN_VM_FAULT_ADDR_MSB, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_ADDR_LSB, DCN_VM_FAULT_ADDR_LSB, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_CLEAR, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_STATUS_MODE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_ERROR_INTERRUPT_ENABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_RANGE_FAULT_DISABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_CNTL, DCN_VM_PRQ_FAULT_DISABLE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_STATUS, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_VMID, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_TABLE_LEVEL, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_PIPE, mask_sh), \ + HUBBUB_SF(DCN_VM_FAULT_STATUS, DCN_VM_ERROR_INTERRUPT_STATUS, mask_sh),\ + HUBBUB_SF(SDPIF_REQUEST_RATE_LIMIT, SDPIF_REQUEST_RATE_LIMIT, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DISPCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\ + HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\ + HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_ERROR_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_CLEAR, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, URGENT_ZERO_SIZE_REQ_EN, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, CSTATE_SWATH_CHK_GOOD_MODE, mask_sh) + +void hubbub42_construct(struct dcn20_hubbub *hubbub2, + struct dc_context *ctx, + const struct dcn_hubbub_registers *hubbub_regs, + const struct dcn_hubbub_shift *hubbub_shift, + const struct dcn_hubbub_mask *hubbub_mask, + int det_size_kb, + int pixel_chunk_size_kb, + int config_return_buffer_size_kb); +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hubp/Makefile b/drivers/gpu/drm/amd/display/dc/hubp/Makefile index a2d1128de7a18..e0799bb873e69 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hubp/Makefile @@ -1,5 +1,5 @@ -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -94,4 +94,12 @@ AMD_DAL_HUBP_DCN401 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn401/,$(HUBP_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN401) +############################################################################### + +HUBP_DCN42 = dcn42_hubp.o + +AMD_DAL_HUBP_DCN42 = $(addprefix $(AMDDALPATH)/dc/hubp/dcn42/,$(HUBP_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HUBP_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h index 7062e6653062a..80be394a8852d 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-17 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -288,16 +288,22 @@ type MCACHEID_MALL_PREF_2H_P1;\ type HUBP_FGCG_REP_DIS +#define DCN42_HUBP_REG_FIELD_VARIABLE_LIST(type) \ + type HUBP_3DLUT_CROSSBAR_SEL_G;\ + type HUBP_3DLUT_CROSSBAR_SEL_B;\ + type HUBP_3DLUT_CROSSBAR_SEL_R struct dcn_hubp2_registers { DCN401_HUBP_REG_COMMON_VARIABLE_LIST; }; struct dcn_hubp2_shift { DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); + DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); }; struct dcn_hubp2_mask { DCN401_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); + DCN42_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); }; struct dcn20_hubp { diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c index f01eae50d02f7..263e0c4d34f66 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c @@ -41,12 +41,12 @@ hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name void hubp401_program_3dlut_fl_addr(struct hubp *hubp, - const struct dc_plane_address address) + const struct dc_plane_address *address) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address.lut3d.addr.high_part); - REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address.lut3d.addr.low_part); + REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, address->lut3d.addr.high_part); + REG_WRITE(HUBP_3DLUT_ADDRESS_LOW, address->lut3d.addr.low_part); } void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group) @@ -72,33 +72,46 @@ int hubp401_get_3dlut_fl_done(struct hubp *hubp) return ret; } -void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode) +static void hubp401_get_3dlut_fl_xbar_map( + const enum dc_cm_lut_pixel_format format, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, addr_mode); + switch (format) { + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: + /* BGRA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: + default: + /* RGBA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } } -void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width) +void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, + const enum dc_cm_lut_pixel_format format) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, width); -} + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r = 0; -void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - - REG_UPDATE(HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, protection_bits); -} - -void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r) -{ - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + hubp401_get_3dlut_fl_xbar_map(format, + &bit_slice_y_g, + &bit_slice_cb_b, + &bit_slice_cr_r); REG_UPDATE_3(HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SELECT_Y_G, bit_slice_y_g, @@ -106,62 +119,122 @@ void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, HUBP_3DLUT_CROSSBAR_SELECT_CR_R, bit_slice_cr_r); } -void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale) +static enum hubp_3dlut_fl_width hubp401_get_3dlut_fl_width( + const enum dc_cm_lut_size size, + const enum dc_cm_lut_swizzle swizzle) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_width width = 0; + + switch (size) { + case CM_LUT_SIZE_333333: + ASSERT(swizzle != CM_LUT_1D_PACKED_LINEAR); + width = hubp_3dlut_fl_width_33; + break; + case CM_LUT_SIZE_171717: + if (swizzle != CM_LUT_1D_PACKED_LINEAR) { + width = hubp_3dlut_fl_width_17; + } else { + width = hubp_3dlut_fl_width_17_transformed; + } + break; + default: + width = 0; + break; + } - REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, bias, HUBP0_3DLUT_FL_SCALE, scale); + return width; } -void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode) +static enum hubp_3dlut_fl_format hubp401_get_3dlut_fl_format( + const enum dc_cm_lut_pixel_format dc_format) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_format hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mode); + switch (dc_format) { + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: + hubp_format = hubp_3dlut_fl_format_unorm_12msb_bitslice; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: + hubp_format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: + hubp_format = hubp_3dlut_fl_format_float_fp1_5_10; + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + return hubp_format; } -void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format) +static enum hubp_3dlut_fl_addressing_mode hubp401_get_3dlut_fl_addr_mode( + const enum dc_cm_lut_swizzle swizzle) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_addressing_mode addr_mode; + + switch (swizzle) { + case CM_LUT_1D_PACKED_LINEAR: + addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; + break; + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: + default: + addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; + break; + } - REG_UPDATE(_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, format); + return addr_mode; } -void hubp401_program_3dlut_fl_config( - struct hubp *hubp, - struct hubp_fl_3dlut_config *cfg) +static enum hubp_3dlut_fl_mode hubp401_get_3dlut_fl_mode( + const enum dc_cm_lut_swizzle swizzle) { - struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + enum hubp_3dlut_fl_mode mode; + + switch (swizzle) { + case CM_LUT_3D_SWIZZLE_LINEAR_RGB: + mode = hubp_3dlut_fl_mode_native_1; + break; + case CM_LUT_3D_SWIZZLE_LINEAR_BGR: + mode = hubp_3dlut_fl_mode_native_2; + break; + case CM_LUT_1D_PACKED_LINEAR: + mode = hubp_3dlut_fl_mode_transform; + break; + default: + mode = hubp_3dlut_fl_mode_disable; + break; + } - uint32_t mpc_width = {(cfg->width == 17) ? 0 : 1}; - uint32_t width = {cfg->width}; + return mode; +} + +void hubp401_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - if (cfg->layout == DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR) - width = (cfg->width == 17) ? 4916 : 35940; + enum hubp_3dlut_fl_width width = hubp401_get_3dlut_fl_width(config->size, config->swizzle); + enum hubp_3dlut_fl_format format = hubp401_get_3dlut_fl_format(config->format); + enum hubp_3dlut_fl_addressing_mode addr_mode = hubp401_get_3dlut_fl_addr_mode(config->swizzle); + enum hubp_3dlut_fl_mode mode = hubp401_get_3dlut_fl_mode(config->swizzle); REG_UPDATE_2(_3DLUT_FL_CONFIG, - HUBP0_3DLUT_FL_MODE, cfg->mode, - HUBP0_3DLUT_FL_FORMAT, cfg->format); + HUBP0_3DLUT_FL_MODE, mode, + HUBP0_3DLUT_FL_FORMAT, format); REG_UPDATE_2(_3DLUT_FL_BIAS_SCALE, - HUBP0_3DLUT_FL_BIAS, cfg->bias, - HUBP0_3DLUT_FL_SCALE, cfg->scale); - - REG_UPDATE(HUBP_3DLUT_ADDRESS_HIGH, - HUBP_3DLUT_ADDRESS_HIGH, cfg->address.lut3d.addr.high_part); - REG_UPDATE(HUBP_3DLUT_ADDRESS_LOW, - HUBP_3DLUT_ADDRESS_LOW, cfg->address.lut3d.addr.low_part); - - //cross bar - REG_UPDATE_8(HUBP_3DLUT_CONTROL, - HUBP_3DLUT_MPC_WIDTH, mpc_width, - HUBP_3DLUT_WIDTH, width, - HUBP_3DLUT_CROSSBAR_SELECT_CR_R, cfg->crossbar_bit_slice_cr_r, - HUBP_3DLUT_CROSSBAR_SELECT_Y_G, cfg->crossbar_bit_slice_y_g, - HUBP_3DLUT_CROSSBAR_SELECT_CB_B, cfg->crossbar_bit_slice_cb_b, - HUBP_3DLUT_ADDRESSING_MODE, cfg->addr_mode, - HUBP_3DLUT_TMZ, cfg->protection_bits, - HUBP_3DLUT_ENABLE, cfg->enabled ? 1 : 0); + HUBP0_3DLUT_FL_BIAS, config->bias, + HUBP0_3DLUT_FL_SCALE, config->scale); + + REG_UPDATE_3(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_WIDTH, width, + HUBP_3DLUT_ADDRESSING_MODE, addr_mode, + HUBP_3DLUT_TMZ, config->addr.tmz_surface); } void hubp401_update_mall_sel(struct hubp *hubp, uint32_t mall_sel, bool c_cursor) @@ -733,25 +806,22 @@ void hubp401_cursor_set_position( const struct dc_cursor_mi_param *param) { struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); - int x_pos = pos->x - param->recout.x; - int y_pos = pos->y - param->recout.y; - int rec_x_offset = x_pos - pos->x_hotspot; - int rec_y_offset = y_pos - pos->y_hotspot; + int rec_x_offset = pos->x - pos->x_hotspot; + int rec_y_offset = pos->y - pos->y_hotspot; int dst_x_offset; int x_pos_viewport = 0; int x_hot_viewport = 0; uint32_t cur_en = pos->enable ? 1 : 0; - + uint32_t x_hotspot_clamped = pos->x_hotspot; hubp->curs_pos = *pos; - /* Recout is zero for pipes if the entire dst_rect is contained * within preceeding ODM slices. */ if (param->recout.width) { - x_pos_viewport = x_pos * param->viewport.width / param->recout.width; + x_pos_viewport = pos->x * param->viewport.width / param->recout.width; x_hot_viewport = pos->x_hotspot * param->viewport.width / param->recout.width; } else { - ASSERT(!cur_en || x_pos == 0); + ASSERT(!cur_en || pos->x == 0); ASSERT(!cur_en || pos->x_hotspot == 0); } @@ -774,6 +844,8 @@ void hubp401_cursor_set_position( ASSERT(param->h_scale_ratio.value); + if (x_hotspot_clamped > 0xFF) + x_hotspot_clamped = 0xFF; if (param->h_scale_ratio.value) dst_x_offset = dc_fixpt_floor(dc_fixpt_div( dc_fixpt_from_int(dst_x_offset), @@ -790,11 +862,11 @@ void hubp401_cursor_set_position( if (!hubp->cursor_offload) { REG_SET_2(CURSOR_POSITION, 0, - CURSOR_X_POSITION, x_pos, - CURSOR_Y_POSITION, y_pos); + CURSOR_X_POSITION, pos->x, + CURSOR_Y_POSITION, pos->y); REG_SET_2(CURSOR_HOT_SPOT, 0, - CURSOR_HOT_SPOT_X, pos->x_hotspot, + CURSOR_HOT_SPOT_X, x_hotspot_clamped, CURSOR_HOT_SPOT_Y, pos->y_hotspot); REG_SET(CURSOR_DST_OFFSET, 0, @@ -1060,19 +1132,13 @@ static struct hubp_funcs dcn401_hubp_funcs = { .hubp_update_mall_sel = hubp401_update_mall_sel, .hubp_prepare_subvp_buffering = hubp32_prepare_subvp_buffering, .hubp_program_mcache_id_and_split_coordinate = hubp401_program_mcache_id_and_split_coordinate, - .hubp_update_3dlut_fl_bias_scale = hubp401_update_3dlut_fl_bias_scale, - .hubp_program_3dlut_fl_mode = hubp401_program_3dlut_fl_mode, - .hubp_program_3dlut_fl_format = hubp401_program_3dlut_fl_format, .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, - .hubp_program_3dlut_fl_addressing_mode = hubp401_program_3dlut_fl_addressing_mode, - .hubp_program_3dlut_fl_width = hubp401_program_3dlut_fl_width, - .hubp_program_3dlut_fl_tmz_protected = hubp401_program_3dlut_fl_tmz_protected, .hubp_program_3dlut_fl_crossbar = hubp401_program_3dlut_fl_crossbar, .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, .hubp_clear_tiling = hubp401_clear_tiling, - .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, .hubp_read_reg_state = hubp3_read_reg_state }; diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h index 4570b8016de5a..043948f64b862 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.h @@ -328,32 +328,17 @@ int hubp401_get_3dlut_fl_done(struct hubp *hubp); void hubp401_set_unbounded_requesting(struct hubp *hubp, bool enable); -void hubp401_update_3dlut_fl_bias_scale(struct hubp *hubp, uint16_t bias, uint16_t scale); - void hubp401_program_3dlut_fl_crossbar(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); - -void hubp401_program_3dlut_fl_tmz_protected(struct hubp *hubp, uint8_t protection_bits); - -void hubp401_program_3dlut_fl_width(struct hubp *hubp, enum hubp_3dlut_fl_width width); - -void hubp401_program_3dlut_fl_addressing_mode(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); + const enum dc_cm_lut_pixel_format format); void hubp401_enable_3dlut_fl(struct hubp *hubp, bool enable); void hubp401_program_3dlut_fl_dlg_param(struct hubp *hubp, int refcyc_per_3dlut_group); -void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address address); +void hubp401_program_3dlut_fl_addr(struct hubp *hubp, const struct dc_plane_address *address); -void hubp401_program_3dlut_fl_format(struct hubp *hubp, enum hubp_3dlut_fl_format format); - -void hubp401_program_3dlut_fl_mode(struct hubp *hubp, enum hubp_3dlut_fl_mode mode); - -void hubp401_program_3dlut_fl_config( - struct hubp *hubp, - struct hubp_fl_3dlut_config *cfg); +void hubp401_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config); void hubp401_clear_tiling(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c new file mode 100644 index 0000000000000..d85a4ab957a40 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.c @@ -0,0 +1,741 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn401/dcn401_hubp.h" +#include "dcn42_hubp.h" +#include "reg_helper.h" + +#define REG(reg) \ + hubp2->hubp_regs->reg + +#define CTX \ + hubp2->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name + +static void hubp42_set_fgcg(struct hubp *hubp, bool enable) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, !enable); +} + +static void hubp42_init(struct hubp *hubp) +{ + hubp3_init(hubp); + + hubp42_set_fgcg(hubp, hubp->ctx->dc->debug.enable_fine_grain_clock_gating.bits.dchub); + + /*do nothing for now for dcn3.5 or later*/ +} + +static void hubp42_program_pixel_format( + struct hubp *hubp, + enum surface_pixel_format format) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + uint32_t green_bar = 1; + uint32_t red_bar = 3; + uint32_t blue_bar = 2; + + /* swap for ABGR format */ + if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010 + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 + || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) { + red_bar = 2; + blue_bar = 3; + } + + REG_UPDATE_3(HUBPRET_CONTROL, + CROSSBAR_SRC_Y_G, green_bar, + CROSSBAR_SRC_CB_B, blue_bar, + CROSSBAR_SRC_CR_R, red_bar); + + /* Mapping is same as ipp programming (cnvc) */ + + switch (format) { + case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 1); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB565: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 3); + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 8); + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 10); + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: /* we use crossbar already */ + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 26); /* ARGB16161616_UNORM */ + break; + case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: + case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/ + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 24); + break; + + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 65); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 64); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 67); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 66); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 12); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 112); + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 113); + break; + case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 114); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 118); + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 119); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE: + REG_UPDATE_2(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 116, + ALPHA_PLANE_EN, 0); + break; + case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA: + REG_UPDATE_2(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 116, + ALPHA_PLANE_EN, 1); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + /* don't see the need of program the xbar in DCN 1.0 */ +} + +static void hubp42_program_deadline( + struct hubp *hubp, + struct dml2_display_dlg_regs *dlg_attr, + struct dml2_display_ttu_regs *ttu_attr) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + /* put DLG in mission mode */ + REG_WRITE(HUBPREQ_DEBUG_DB, 0); + + /* DLG - Per hubp */ + REG_SET_2(BLANK_OFFSET_0, 0, + REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end, + DLG_V_BLANK_END, dlg_attr->dlg_vblank_end); + + REG_SET(BLANK_OFFSET_1, 0, + MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start); + + REG_SET(DST_DIMENSIONS, 0, + REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal); + + REG_SET_2(DST_AFTER_SCALER, 0, + REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler, + DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler); + + REG_SET(REF_FREQ_TO_PIX_FREQ, 0, + REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq); + + /* DLG - Per luma/chroma */ + REG_SET(VBLANK_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l); + + if (REG(NOM_PARAMETERS_0)) + REG_SET(NOM_PARAMETERS_0, 0, + DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l); + + if (REG(NOM_PARAMETERS_1)) + REG_SET(NOM_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l); + + REG_SET(NOM_PARAMETERS_4, 0, + DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l); + + REG_SET(NOM_PARAMETERS_5, 0, + REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l); + + REG_SET_2(PER_LINE_DELIVERY, 0, + REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l, + REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c); + + REG_SET(VBLANK_PARAMETERS_2, 0, + REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c); + + if (REG(NOM_PARAMETERS_2)) + REG_SET(NOM_PARAMETERS_2, 0, + DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c); + + if (REG(NOM_PARAMETERS_3)) + REG_SET(NOM_PARAMETERS_3, 0, + REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c); + + REG_SET(NOM_PARAMETERS_6, 0, + DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c); + + REG_SET(NOM_PARAMETERS_7, 0, + REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c); + + /* TTU - per hubp */ + REG_SET_2(DCN_TTU_QOS_WM, 0, + QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm, + QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm); + + /* TTU - per luma/chroma */ + /* Assumed surf0 is luma and 1 is chroma */ + + REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l); + + REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c); + + REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, + REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0, + QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0, + QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0); + + REG_SET(FLIP_PARAMETERS_1, 0, + REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l); + REG_SET(HUBP_3DLUT_DLG_PARAM, 0, REFCYC_PER_3DLUT_GROUP, dlg_attr->refcyc_per_tdlut_group); + + REG_UPDATE(DCN_DMDATA_VM_CNTL, + REFCYC_PER_VM_DMDATA, dlg_attr->refcyc_per_vm_dmdata); +} + +void hubp42_program_requestor( + struct hubp *hubp, + struct dml2_display_rq_regs *rq_regs) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + REG_UPDATE(HUBPRET_CONTROL, + DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address); + REG_SET_4(DCN_EXPANSION_MODE, 0, + DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode, + PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode, + MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode, + CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode); + REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0, + CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, + MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, + META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, + MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, + DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, + VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, + SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, + PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); + REG_SET_7(DCHUBP_REQ_SIZE_CONFIG_C, 0, + CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size, + MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size, + META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size, + MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size, + DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size, + SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height, + PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear); +} + + +void hubp42_setup( + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *pipe_regs, + union dml2_global_sync_programming *pipe_global_sync, + struct dc_crtc_timing *timing) +{ + /* otg is locked when this func is called. Register are double buffered. + * disable the requestors is not needed + */ + hubp401_vready_at_or_After_vsync(hubp, pipe_global_sync, timing); + hubp42_program_requestor(hubp, &pipe_regs->rq_regs); + hubp42_program_deadline(hubp, &pipe_regs->dlg_regs, &pipe_regs->ttu_regs); +} +static void hubp42_program_surface_config( + struct hubp *hubp, + enum surface_pixel_format format, + struct dc_tiling_info *tiling_info, + struct plane_size *plane_size, + enum dc_rotation_angle rotation, + struct dc_plane_dcc_param *dcc, + bool horizontal_mirror, + unsigned int compat_level) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + hubp3_dcc_control_sienna_cichlid(hubp, dcc); + hubp3_program_tiling(hubp2, tiling_info, format); + hubp2_program_size(hubp, format, plane_size, dcc); + hubp2_program_rotation(hubp, rotation, horizontal_mirror); + hubp42_program_pixel_format(hubp, format); +} + +static void hubp42_get_3dlut_fl_xbar_map( + const enum dc_cm_lut_pixel_format format, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice *bit_slice_cr_r) +{ + switch (format) { + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10: + /* BGRA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_32_47; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_0_15; + break; + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB: + case CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10: + default: + /* RGBA */ + *bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; + *bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; + *bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; + break; + } +} + +void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, + const enum dc_cm_lut_pixel_format format) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_g = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_b = 0; + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_r = 0; + + hubp42_get_3dlut_fl_xbar_map(format, + &bit_slice_g, + &bit_slice_b, + &bit_slice_r); + + REG_UPDATE_3(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_CROSSBAR_SEL_R, bit_slice_r, + HUBP_3DLUT_CROSSBAR_SEL_G, bit_slice_g, + HUBP_3DLUT_CROSSBAR_SEL_B, bit_slice_b); +} + +static uint32_t hubp42_get_3dlut_fl_mpc_width( + const enum dc_cm_lut_size size) +{ + uint32_t width = 0; + + switch (size) { + case CM_LUT_SIZE_333333: + width = 1; + break; + case CM_LUT_SIZE_171717: + default: + width = 0; + break; + } + + return width; +} + +void hubp42_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + uint32_t mpc_width = hubp42_get_3dlut_fl_mpc_width(config->size); + + REG_UPDATE(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_MPC_WIDTH, mpc_width); + + hubp401_program_3dlut_fl_config(hubp, config); +} + +static bool hubp42_program_surface_flip_and_addr( + struct hubp *hubp, + const struct dc_plane_address *address, + bool flip_immediate) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + + //program flip type + REG_UPDATE(DCSURF_FLIP_CONTROL, + SURFACE_FLIP_TYPE, flip_immediate); + + // Program VMID reg + if (flip_immediate == 0) + REG_UPDATE(VMID_SETTINGS_0, + VMID, address->vmid); + + if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) { + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0); + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1); + + } else { + // turn off stereo if not in stereo + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0); + REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0); + } + + /* HW automatically latch rest of address register on write to + * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used + * + * program high first and then the low addr, order matters! + */ + switch (address->type) { + case PLN_ADDR_TYPE_GRAPHICS: + /* DCN1.0 does not support const color + * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1 + * base on address->grph.dcc_const_color + * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma + * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma + */ + + if (address->grph.addr.quad_part == 0) + break; + + REG_UPDATE_2(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface); + + if (address->grph.meta_addr.quad_part != 0) { + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->grph.meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->grph.meta_addr.low_part); + } + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->grph.addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->grph.addr.low_part); + break; + case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: + if (address->video_progressive.luma_addr.quad_part == 0 + || address->video_progressive.chroma_addr.quad_part == 0) + break; + + REG_UPDATE_4(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); + + if (address->video_progressive.luma_meta_addr.quad_part != 0) { + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, + address->video_progressive.chroma_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, + PRIMARY_META_SURFACE_ADDRESS_C, + address->video_progressive.chroma_meta_addr.low_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->video_progressive.luma_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->video_progressive.luma_meta_addr.low_part); + } + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_SURFACE_ADDRESS_HIGH_C, + address->video_progressive.chroma_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, + PRIMARY_SURFACE_ADDRESS_C, + address->video_progressive.chroma_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->video_progressive.luma_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->video_progressive.luma_addr.low_part); + break; + case PLN_ADDR_TYPE_GRPH_STEREO: + if (address->grph_stereo.left_addr.quad_part == 0) + break; + if (address->grph_stereo.right_addr.quad_part == 0) + break; + + REG_UPDATE_8(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface, + SECONDARY_SURFACE_TMZ, address->tmz_surface, + SECONDARY_SURFACE_TMZ_C, address->tmz_surface, + SECONDARY_META_SURFACE_TMZ, address->tmz_surface, + SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface); + + if (address->grph_stereo.right_meta_addr.quad_part != 0) { + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C, 0, + SECONDARY_META_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.right_alpha_meta_addr.high_part); + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_C, 0, + SECONDARY_META_SURFACE_ADDRESS_C, + address->grph_stereo.right_alpha_meta_addr.low_part); + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, + SECONDARY_META_SURFACE_ADDRESS_HIGH, + address->grph_stereo.right_meta_addr.high_part); + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0, + SECONDARY_META_SURFACE_ADDRESS, + address->grph_stereo.right_meta_addr.low_part); + } + if (address->grph_stereo.left_meta_addr.quad_part != 0) { + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.left_alpha_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, + PRIMARY_META_SURFACE_ADDRESS_C, + address->grph_stereo.left_alpha_meta_addr.low_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->grph_stereo.left_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->grph_stereo.left_meta_addr.low_part); + } + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C, 0, + SECONDARY_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.right_alpha_addr.high_part); + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_C, 0, + SECONDARY_SURFACE_ADDRESS_C, + address->grph_stereo.right_alpha_addr.low_part); + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0, + SECONDARY_SURFACE_ADDRESS_HIGH, + address->grph_stereo.right_addr.high_part); + + REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0, + SECONDARY_SURFACE_ADDRESS, + address->grph_stereo.right_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_SURFACE_ADDRESS_HIGH_C, + address->grph_stereo.left_alpha_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, + PRIMARY_SURFACE_ADDRESS_C, + address->grph_stereo.left_alpha_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->grph_stereo.left_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->grph_stereo.left_addr.low_part); + break; + case PLN_ADDR_TYPE_RGBEA: + if (address->rgbea.addr.quad_part == 0 + || address->rgbea.alpha_addr.quad_part == 0) + break; + + REG_UPDATE_4(DCSURF_SURFACE_CONTROL, + PRIMARY_SURFACE_TMZ, address->tmz_surface, + PRIMARY_SURFACE_TMZ_C, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ, address->tmz_surface, + PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface); + + if (address->rgbea.meta_addr.quad_part != 0) { + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, + address->rgbea.alpha_meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0, + PRIMARY_META_SURFACE_ADDRESS_C, + address->rgbea.alpha_meta_addr.low_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, + address->rgbea.meta_addr.high_part); + + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0, + PRIMARY_META_SURFACE_ADDRESS, + address->rgbea.meta_addr.low_part); + } + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_SURFACE_ADDRESS_HIGH_C, + address->rgbea.alpha_addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0, + PRIMARY_SURFACE_ADDRESS_C, + address->rgbea.alpha_addr.low_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_SURFACE_ADDRESS_HIGH, + address->rgbea.addr.high_part); + + REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0, + PRIMARY_SURFACE_ADDRESS, + address->rgbea.addr.low_part); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + hubp->request_address = *address; + + return true; +} + +struct hubp_funcs dcn42_hubp_funcs = { + .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, + .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, + .hubp_program_surface_flip_and_addr = hubp42_program_surface_flip_and_addr, + .hubp_program_surface_config = hubp42_program_surface_config, + .hubp_is_flip_pending = hubp2_is_flip_pending, + .hubp_setup2 = hubp42_setup, + .hubp_setup_interdependent2 = hubp401_setup_interdependent, + .hubp_set_vm_system_aperture_settings = hubp3_set_vm_system_aperture_settings, + .set_blank = hubp2_set_blank, + .set_blank_regs = hubp2_set_blank_regs, + .dcc_control = hubp3_dcc_control, + .hubp_reset = hubp_reset, + .mem_program_viewport = min_set_viewport, + .set_cursor_attributes = hubp32_cursor_set_attributes, + .set_cursor_position = hubp401_cursor_set_position, + .hubp_clk_cntl = hubp2_clk_cntl, + .hubp_vtg_sel = hubp2_vtg_sel, + .dmdata_set_attributes = hubp3_dmdata_set_attributes, + .dmdata_load = hubp2_dmdata_load, + .dmdata_status_done = hubp2_dmdata_status_done, + .hubp_read_state = hubp42_read_state, + .hubp_clear_underflow = hubp2_clear_underflow, + .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl, + .hubp_init = hubp42_init, + .set_unbounded_requesting = hubp31_set_unbounded_requesting, + .hubp_soft_reset = hubp31_soft_reset, + .hubp_set_flip_int = hubp1_set_flip_int, + .hubp_in_blank = hubp1_in_blank, + .program_extended_blank = hubp31_program_extended_blank_value, + .hubp_program_3dlut_fl_addr = hubp401_program_3dlut_fl_addr, + .hubp_program_3dlut_fl_config = hubp42_program_3dlut_fl_config, + .hubp_program_3dlut_fl_dlg_param = hubp401_program_3dlut_fl_dlg_param, + .hubp_enable_3dlut_fl = hubp401_enable_3dlut_fl, + .hubp_program_3dlut_fl_crossbar = hubp42_program_3dlut_fl_crossbar, + .hubp_get_3dlut_fl_done = hubp401_get_3dlut_fl_done, + .hubp_clear_tiling = hubp3_clear_tiling, + .hubp_program_3dlut_fl_config = hubp401_program_3dlut_fl_config, + .hubp_read_reg_state = hubp3_read_reg_state +}; + +bool hubp42_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask) +{ + hubp2->base.funcs = &dcn42_hubp_funcs; + hubp2->base.ctx = ctx; + hubp2->hubp_regs = hubp_regs; + hubp2->hubp_shift = hubp_shift; + hubp2->hubp_mask = hubp_mask; + hubp2->base.inst = inst; + hubp2->base.opp_id = OPP_ID_INVALID; + hubp2->base.mpcc_id = 0xf; + + return true; +} + + +void hubp42_read_state(struct hubp *hubp) +{ + struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp); + struct dcn_hubp_state *s = &hubp2->state; + struct dcn_fl_regs_st *fl_regs = &s->fl_regs; + + hubp401_read_state(hubp); + + /* CONTROL */ + REG_GET_5(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_ENABLE, &fl_regs->lut_enable, + HUBP_3DLUT_DONE, &fl_regs->lut_done, + HUBP_3DLUT_ADDRESSING_MODE, &fl_regs->lut_addr_mode, + HUBP_3DLUT_WIDTH, &fl_regs->lut_width, + HUBP_3DLUT_MPC_WIDTH, &fl_regs->lut_mpc_width); + + REG_GET_4(HUBP_3DLUT_CONTROL, + HUBP_3DLUT_TMZ, &fl_regs->lut_tmz, + HUBP_3DLUT_CROSSBAR_SEL_R, &fl_regs->lut_crossbar_sel_r, + HUBP_3DLUT_CROSSBAR_SEL_G, &fl_regs->lut_crossbar_sel_g, + HUBP_3DLUT_CROSSBAR_SEL_B, &fl_regs->lut_crossbar_sel_b); + + /* ADDR */ + REG_GET(HUBP_3DLUT_ADDRESS_HIGH, + HUBP_3DLUT_ADDRESS_HIGH, &fl_regs->lut_addr_hi); + REG_GET(HUBP_3DLUT_ADDRESS_LOW, + HUBP_3DLUT_ADDRESS_LOW, &fl_regs->lut_addr_lo); + /* CLK */ + REG_GET(HUBP_3DLUT_DLG_PARAM, + REFCYC_PER_3DLUT_GROUP, &fl_regs->refcyc_3dlut_group); + /* FL */ + REG_GET_2(_3DLUT_FL_BIAS_SCALE, + HUBP0_3DLUT_FL_BIAS, &fl_regs->lut_fl_bias, + HUBP0_3DLUT_FL_SCALE, &fl_regs->lut_fl_scale); + REG_GET_2(_3DLUT_FL_CONFIG, + HUBP0_3DLUT_FL_MODE, &fl_regs->lut_fl_mode, + HUBP0_3DLUT_FL_FORMAT, &fl_regs->lut_fl_format); +} diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h new file mode 100644 index 0000000000000..88bb1337ab9d6 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn42/dcn42_hubp.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_HUBP_DCN42_H__ +#define __DC_HUBP_DCN42_H__ + +#include "dcn35/dcn35_hubp.h" + +#define HUBP_MASK_SH_LIST_DCN42(mask_sh)\ + HUBP_MASK_SH_LIST_DCN35(mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_MODE, mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_CONFIG, HUBP0_3DLUT_FL_FORMAT, mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_BIAS, mask_sh),\ + HUBP_SF(HUBP0_3DLUT_FL_BIAS_SCALE, HUBP0_3DLUT_FL_SCALE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ENABLE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_DONE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_ADDRESSING_MODE, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_WIDTH, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_MPC_WIDTH, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_TMZ, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_B, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_G, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_CONTROL, HUBP_3DLUT_CROSSBAR_SEL_R, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH, HUBP_3DLUT_ADDRESS_HIGH, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW, HUBP_3DLUT_ADDRESS_LOW, mask_sh),\ + HUBP_SF(CURSOR0_0_HUBP_3DLUT_DLG_PARAM, REFCYC_PER_3DLUT_GROUP, mask_sh) + +struct dml2_display_rq_regs; + +bool hubp42_construct( + struct dcn20_hubp *hubp2, + struct dc_context *ctx, + uint32_t inst, + const struct dcn_hubp2_registers *hubp_regs, + const struct dcn_hubp2_shift *hubp_shift, + const struct dcn_hubp2_mask *hubp_mask); + +void hubp42_program_3dlut_fl_crossbar(struct hubp *hubp, + const enum dc_cm_lut_pixel_format format); + +void hubp42_program_3dlut_fl_config(struct hubp *hubp, + const struct dc_3dlut_dma *config); + +void hubp42_read_state(struct hubp *hubp); + +void hubp42_program_requestor( + struct hubp *hubp, + struct dml2_display_rq_regs *rq_regs); + +void hubp42_setup( + struct hubp *hubp, + struct dml2_dchub_per_pipe_register_set *pipe_regs, + union dml2_global_sync_programming *pipe_global_sync, + struct dc_crtc_timing *timing); + +#endif /* __DC_HUBP_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/Makefile b/drivers/gpu/drm/amd/display/dc/hwss/Makefile index bee617ca0838c..08cbbf87a19fa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/Makefile +++ b/drivers/gpu/drm/amd/display/dc/hwss/Makefile @@ -1,5 +1,4 @@ - -# Copyright 2022 Advanced Micro Devices, Inc. +# Copyright 2022-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -199,4 +198,13 @@ HWSS_DCN401 = dcn401_hwseq.o dcn401_init.o AMD_DAL_HWSS_DCN401 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn401/,$(HWSS_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN401) + +############################################################################### + +HWSS_DCN42 = dcn42_hwseq.o dcn42_init.o + +AMD_DAL_HWSS_DCN42 = $(addprefix $(AMDDALPATH)/dc/hwss/dcn42/,$(HWSS_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_HWSS_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h index f66a38f43a091..dc8feca578c5b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h @@ -1,5 +1,5 @@ /* - * Copyright 2016 Advanced Micro Devices, Inc. + * Copyright 2016, 2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -700,6 +700,8 @@ struct dce_hwseq_registers { uint32_t DOMAIN23_PG_STATUS; uint32_t DOMAIN24_PG_STATUS; uint32_t DOMAIN25_PG_STATUS; + uint32_t DOMAIN26_PG_CONFIG; + uint32_t DOMAIN26_PG_STATUS; }; /* set field name */ #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ @@ -1245,6 +1247,13 @@ struct dce_hwseq_registers { type DOMAIN25_PGFSM_PWR_STATUS; \ type DOMAIN_DESIRED_PWR_STATE; +#define HWSEQ_DCN42_REG_FIELD_LIST(type) \ + type DPIASYMCLK4_GATE_DISABLE;\ + type DPIASYMCLK5_GATE_DISABLE;\ + type DOMAIN26_POWER_FORCEON; \ + type DOMAIN26_POWER_GATE; \ + type DOMAIN26_PGFSM_PWR_STATUS; + struct dce_hwseq_shift { HWSEQ_REG_FIELD_LIST(uint8_t) HWSEQ_DCN_REG_FIELD_LIST(uint8_t) @@ -1253,6 +1262,7 @@ struct dce_hwseq_shift { HWSEQ_DCN31_REG_FIELD_LIST(uint8_t) HWSEQ_DCN35_REG_FIELD_LIST(uint8_t) HWSEQ_DCN401_REG_FIELD_LIST(uint8_t) + HWSEQ_DCN42_REG_FIELD_LIST(uint8_t) }; struct dce_hwseq_mask { @@ -1263,6 +1273,7 @@ struct dce_hwseq_mask { HWSEQ_DCN31_REG_FIELD_LIST(uint32_t) HWSEQ_DCN35_REG_FIELD_LIST(uint32_t) HWSEQ_DCN401_REG_FIELD_LIST(uint32_t) + HWSEQ_DCN42_REG_FIELD_LIST(uint32_t) }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index ebd74b43e935e..8a17cc036399a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -59,6 +59,7 @@ #include "dc_state_priv.h" #include "dpcd_defs.h" #include "dsc.h" +#include "dc_dp_types.h" /* include DCE11 register header files */ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" @@ -85,9 +86,9 @@ hws->ctx #define DC_LOGGER \ - ctx->logger -#define DC_LOGGER_INIT() \ - struct dc_context *ctx = dc->ctx + dc_ctx->logger +#define DC_LOGGER_INIT(ctx) \ + struct dc_context *dc_ctx = ctx #define REG(reg)\ hws->regs->reg @@ -669,10 +670,20 @@ dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable) encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE; encoder_control.engine_id = link->link_enc->analog_engine; encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10; - bios->funcs->encoder_control(bios, &encoder_control); } +static bool +dce110_dac_load_detect(struct dc_link *link) +{ + struct dc_bios *bios = link->ctx->dc_bios; + struct link_encoder *link_enc = link->link_enc; + enum bp_result bp_result; + + bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine); + return bp_result == BP_RESULT_OK; +} + void dce110_enable_stream(struct pipe_ctx *pipe_ctx) { enum dc_lane_count lane_count = @@ -685,6 +696,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) uint32_t early_control = 0; struct timing_generator *tg = pipe_ctx->stream_res.tg; + link_hwss->setup_stream_attribute(pipe_ctx); link_hwss->setup_stream_encoder(pipe_ctx); dc->hwss.update_info_frame(pipe_ctx); @@ -726,14 +738,14 @@ void dce110_edp_wait_for_hpd_ready( struct dc_link *link, bool power_up) { - struct dc_context *ctx = link->ctx; struct graphics_object_id connector = link->link_enc->connector; - struct gpio *hpd; bool edp_hpd_high = false; uint32_t time_elapsed = 0; uint32_t timeout = power_up ? PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; + DC_LOGGER_INIT(link->ctx); + if (dal_graphics_object_id_get_connector_id(connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); @@ -752,31 +764,16 @@ void dce110_edp_wait_for_hpd_ready( * we need to wait until SENSE bit is high/low. */ - /* obtain HPD */ - /* TODO what to do with this? */ - hpd = ctx->dc->link_srv->get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service); - - if (!hpd) { - BREAK_TO_DEBUGGER(); - return; - } - if (link->panel_config.pps.extra_t3_ms > 0) { int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms; msleep(extra_t3_in_ms); } - dal_gpio_open(hpd, GPIO_MODE_INTERRUPT); - /* wait until timeout or panel detected */ do { - uint32_t detected = 0; - - dal_gpio_get_value(hpd, &detected); - - if (!(detected ^ power_up)) { + if (!(link->dc->link_srv->get_hpd_state(link) ^ power_up)) { edp_hpd_high = true; break; } @@ -786,10 +783,6 @@ void dce110_edp_wait_for_hpd_ready( time_elapsed += HPD_CHECK_INTERVAL; } while (time_elapsed < timeout); - dal_gpio_close(hpd); - - dal_gpio_destroy_irq(&hpd); - /* ensure that the panel is detected */ if (!edp_hpd_high) DC_LOG_DC("%s: wait timed out!\n", __func__); @@ -804,6 +797,7 @@ void dce110_edp_power_control( enum bp_result bp_result; uint8_t pwrseq_instance; + DC_LOGGER_INIT(ctx); if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { @@ -972,6 +966,8 @@ void dce110_edp_backlight_control( unsigned int pre_T11_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0); unsigned int post_T7_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0); + DC_LOGGER_INIT(ctx); + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) { BREAK_TO_DEBUGGER(); @@ -1602,7 +1598,6 @@ static enum dc_status dce110_enable_stream_timing( return DC_OK; } - static void dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) { @@ -1613,12 +1608,10 @@ dce110_select_crtc_source(struct pipe_ctx *pipe_ctx) if (dc_is_rgb_signal(pipe_ctx->stream->signal)) engine_id = link->link_enc->analog_engine; - crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth; crtc_source_select.engine_id = engine_id; crtc_source_select.sink_signal = pipe_ctx->stream->signal; - bios->funcs->select_crtc_source(bios, &crtc_source_select); } @@ -1779,20 +1772,25 @@ static void power_down_encoders(struct dc *dc) int i; for (i = 0; i < dc->link_count; i++) { - enum signal_type signal = dc->links[i]->connector_signal; - - dc->link_srv->blank_dp_stream(dc->links[i], false); + struct dc_link *link = dc->links[i]; + struct link_encoder *link_enc = link->link_enc; + enum signal_type signal = link->connector_signal; + dc->link_srv->blank_dp_stream(link, false); if (signal != SIGNAL_TYPE_EDP) signal = SIGNAL_TYPE_NONE; - if (dc->links[i]->ep_type == DISPLAY_ENDPOINT_PHY) - dc->links[i]->link_enc->funcs->disable_output( - dc->links[i]->link_enc, signal); + if (link->ep_type == DISPLAY_ENDPOINT_PHY) + link_enc->funcs->disable_output(link_enc, signal); - dc->links[i]->link_status.link_active = false; - memset(&dc->links[i]->cur_link_settings, 0, - sizeof(dc->links[i]->cur_link_settings)); + if (link->fec_state == dc_link_fec_enabled) { + link_enc->funcs->fec_set_enable(link_enc, false); + link_enc->funcs->fec_set_ready(link_enc, false); + link->fec_state = dc_link_fec_not_ready; + } + + link->link_status.link_active = false; + memset(&link->cur_link_settings, 0, sizeof(link->cur_link_settings)); } } @@ -1840,6 +1838,9 @@ static void disable_vga_and_power_gate_all_controllers( struct timing_generator *tg; struct dc_context *ctx = dc->ctx; + if (dc->caps.ips_support) + return; + for (i = 0; i < dc->res_pool->timing_generator_count; i++) { tg = dc->res_pool->timing_generators[i]; @@ -1916,13 +1917,16 @@ static void clean_up_dsc_blocks(struct dc *dc) /* disable DSC in OPTC */ if (i < dc->res_pool->timing_generator_count) { tg = dc->res_pool->timing_generators[i]; - tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0); + if (tg->funcs->set_dsc_config) + tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0); } /* disable DSC in stream encoder */ if (i < dc->res_pool->stream_enc_count) { se = dc->res_pool->stream_enc[i]; - se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0); - se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true); + if (se->funcs->dp_set_dsc_config) + se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0); + if (se->funcs->dp_set_dsc_pps_info_packet) + se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true); } /* disable DSC block */ if (dccg->funcs->set_ref_dscclk) @@ -1936,6 +1940,35 @@ static void clean_up_dsc_blocks(struct dc *dc) } } +static void dc_hwss_enable_otg_pwa( + struct dc *dc, + struct pipe_ctx *pipe_ctx) +{ + struct timing_generator *tg = NULL; + + if (dc->debug.enable_otg_frame_sync_pwa == 0) + return; + + if (pipe_ctx == NULL || pipe_ctx->stream_res.tg == NULL) + return; + tg = pipe_ctx->stream_res.tg; + + /*only enable this if one active*/ + if (tg->funcs->enable_otg_pwa) { + struct otc_pwa_frame_sync pwa_param = {0}; + + DC_LOGGER_INIT(dc->ctx); + /* mode 1 to choose generate pwa sync signal on line 0 counting + * from vstartup at very beginning of the frame + */ + pwa_param.pwa_frame_sync_line_offset = 0; + pwa_param.pwa_sync_mode = DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP; + /*frame sync line for generating high frame sync*/ + tg->funcs->enable_otg_pwa(tg, &pwa_param); + DC_LOG_DC("Enable OTG PWA frame sync on TG %d\n", tg->inst); + } +} + /* * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: * 1. Power down all DC HW blocks @@ -1961,8 +1994,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) bool keep_edp_vdd_on = false; bool should_clean_dsc_block = true; struct dc_bios *dcb = dc->ctx->dc_bios; - DC_LOGGER_INIT(); - + DC_LOGGER_INIT(dc->ctx); get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); dc_get_edp_links(dc, edp_links, &edp_num); @@ -1972,8 +2004,8 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) get_edp_streams(context, edp_streams, &edp_stream_num); - /* Check fastboot support, disable on DCE 6-8 because of blank screens */ - if (edp_num && edp_stream_num && dc->ctx->dce_version < DCE_VERSION_10_0) { + /* Check fastboot support, disable on DCE 6-8-10 because of blank screens */ + if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) { for (i = 0; i < edp_num; i++) { edp_link = edp_links[i]; if (edp_link != edp_streams[0]->link) @@ -2013,6 +2045,7 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) // If VBios supports it, we check it from reigster or other flags. pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1; } + dc_hwss_enable_otg_pwa(dc, pipe_ctx); } break; } @@ -2582,6 +2615,18 @@ enum dc_status dce110_apply_ctx_to_hw( #endif } + + if (dc->debug.enable_otg_frame_sync_pwa && context->stream_count == 1) { + /* only enable this on one OTG*/ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx && pipe_ctx->stream != NULL) { + dc_hwss_enable_otg_pwa(dc, pipe_ctx); + break; + } + } + } if (dc->fbc_compressor) enable_fbc(dc, dc->current_state); @@ -2728,7 +2773,6 @@ static bool wait_for_reset_trigger_to_occur( struct dc_context *dc_ctx, struct timing_generator *tg) { - struct dc_context *ctx = dc_ctx; bool rc = false; /* To avoid endless loop we wait at most @@ -2770,10 +2814,9 @@ static void dce110_enable_timing_synchronization( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct dcp_gsl_params gsl_params = { 0 }; int i; - DC_LOGGER_INIT(); + DC_LOGGER_INIT(dc->ctx); DC_SYNC_INFO("GSL: Setting-up...\n"); @@ -2816,10 +2859,9 @@ static void dce110_enable_per_frame_crtc_position_reset( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct dcp_gsl_params gsl_params = { 0 }; int i; - DC_LOGGER_INIT(); + DC_LOGGER_INIT(dc->ctx); gsl_params.gsl_group = 0; gsl_params.gsl_master = 0; @@ -3450,6 +3492,7 @@ static const struct hw_sequencer_funcs dce110_funcs = { .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, .disable_link_output = dce110_disable_link_output, + .dac_load_detect = dce110_dac_load_detect, }; static const struct hwseq_private_funcs dce110_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index fa62e40a98586..ffeec61824f51 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -50,6 +50,7 @@ #include "link_hwss.h" #include "dpcd_defs.h" #include "dsc.h" +#include "dio/dcn10/dcn10_dio.h" #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" @@ -59,9 +60,9 @@ #include "dc_state_priv.h" #define DC_LOGGER \ - dc_logger -#define DC_LOGGER_INIT(logger) \ - struct dal_logger *dc_logger = logger + dc_ctx->logger +#define DC_LOGGER_INIT(ctx) \ + struct dc_context *dc_ctx = ctx #define CTX \ hws->ctx @@ -1008,7 +1009,7 @@ static void power_on_plane_resources( struct dce_hwseq *hws, int plane_id) { - DC_LOGGER_INIT(hws->ctx->logger); + DC_LOGGER_INIT(hws->ctx); if (hws->funcs.dpp_root_clock_control) hws->funcs.dpp_root_clock_control(hws, plane_id, true); @@ -1285,7 +1286,7 @@ static void dcn10_reset_back_end_for_pipe( { int i; struct dc_link *link; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; @@ -1421,12 +1422,10 @@ void dcn10_verify_allow_pstate_change_high(struct dc *dc) return; if (!hubbub->funcs->verify_allow_pstate_change_high(hubbub)) { - int i = 0; - if (should_log_hw_state) dcn10_log_hw_state(dc, NULL); - TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES); + TRACE_DC_PIPE_STATE(pipe_ctx, MAX_PIPES); BREAK_TO_DEBUGGER(); if (dcn10_hw_wa_force_recovery(dc)) { /*check again*/ @@ -1489,7 +1488,7 @@ void dcn10_plane_atomic_power_down(struct dc *dc, struct hubp *hubp) { struct dce_hwseq *hws = dc->hwseq; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (REG(DC_IP_REQUEST_CNTL)) { REG_SET(DC_IP_REQUEST_CNTL, 0, @@ -1553,7 +1552,7 @@ void dcn10_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) { struct dce_hwseq *hws = dc->hwseq; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return; @@ -1881,13 +1880,13 @@ void dcn10_init_hw(struct dc *dc) /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ if (!is_optimized_init_done) - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } @@ -2267,8 +2266,6 @@ static bool wait_for_reset_trigger_to_occur( { bool rc = false; - DC_LOGGER_INIT(dc_ctx->logger); - /* To avoid endless loop we wait at most * frames_to_wait_on_triggered_reset frames for the reset to occur. */ const uint32_t frames_to_wait_on_triggered_reset = 10; @@ -2383,7 +2380,6 @@ static uint8_t get_clock_divider(struct pipe_ctx *pipe, static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; int i, master = -1, embedded = -1; struct dc_crtc_timing *hw_crtc_timing; uint64_t phase[MAX_PIPES]; @@ -2396,7 +2392,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size, uint32_t dp_ref_clk_100hz = dc->res_pool->dp_clock_source->ctx->dc->clk_mgr->dprefclk_khz*10; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); hw_crtc_timing = kcalloc(MAX_PIPES, sizeof(*hw_crtc_timing), GFP_KERNEL); if (!hw_crtc_timing) @@ -2476,12 +2472,11 @@ void dcn10_enable_vblanks_synchronization( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct output_pixel_processor *opp; struct timing_generator *tg; int i, width = 0, height = 0, master; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); for (i = 1; i < group_size; i++) { opp = grouped_pipes[i]->stream_res.opp; @@ -2542,12 +2537,11 @@ void dcn10_enable_timing_synchronization( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; struct output_pixel_processor *opp; struct timing_generator *tg; int i, width = 0, height = 0; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); DC_SYNC_INFO("Setting up OTG reset trigger\n"); @@ -2623,10 +2617,9 @@ void dcn10_enable_per_frame_crtc_position_reset( int group_size, struct pipe_ctx *grouped_pipes[]) { - struct dc_context *dc_ctx = dc->ctx; int i; - DC_LOGGER_INIT(dc_ctx->logger); + DC_LOGGER_INIT(dc->ctx); DC_SYNC_INFO("Setting up\n"); for (i = 0; i < group_size; i++) @@ -2678,8 +2671,7 @@ static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1, uint32_t fb_base_value; uint32_t fb_offset_value; - REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); - REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); + dcn10_hubbub_read_fb_aperture(hws->ctx->dc->res_pool->hubbub, &fb_base_value, &fb_offset_value); REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part); @@ -3474,7 +3466,7 @@ void dcn10_set_static_screen_control(struct pipe_ctx **pipe_ctx, triggers, params->num_frames); } -static void dcn10_config_stereo_parameters( +void dcn10_config_stereo_parameters( struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { enum view_3d_format view_format = stream->view_format; @@ -3666,7 +3658,11 @@ void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx) int y_plane = pipe_ctx->plane_state->dst_rect.y; int x_pos = pos_cpy.x; int y_pos = pos_cpy.y; - int clip_x = pipe_ctx->plane_state->clip_rect.x; + bool is_primary_plane = (pipe_ctx->plane_state->layer_index == 0); + + int clip_x = (pos_cpy.use_viewport_for_clip && is_primary_plane && + !odm_combine_on && !pipe_split_on && param.viewport.x != 0) + ? param.viewport.x : pipe_ctx->plane_state->clip_rect.x; int clip_width = pipe_ctx->plane_state->clip_rect.width; if ((pipe_ctx->top_pipe != NULL) || (pipe_ctx->bottom_pipe != NULL)) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h index 57d30ea225f2b..476095c5dd0cd 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h @@ -217,5 +217,7 @@ void dcn10_update_visual_confirm_color( void dcn10_reset_surface_dcc_and_tiling(struct pipe_ctx *pipe_ctx, struct dc_plane_state *plane_state, bool clear_tiling); +void dcn10_config_stereo_parameters( + struct dc_stream_state *stream, struct crtc_stereo_flags *flags); #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index c8ff8ae85a030..307e8f8060e6d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -46,6 +46,7 @@ #include "dchubbub.h" #include "reg_helper.h" #include "dcn10/dcn10_cm_common.h" +#include "dcn10/dcn10_hubbub.h" #include "vm_helper.h" #include "dccg.h" #include "dc_dmub_srv.h" @@ -356,26 +357,10 @@ void dcn20_enable_power_gating_plane( void dcn20_dccg_init(struct dce_hwseq *hws) { - /* - * set MICROSECOND_TIME_BASE_DIV - * 100Mhz refclk -> 0x120264 - * 27Mhz refclk -> 0x12021b - * 48Mhz refclk -> 0x120230 - * - */ - REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264); - - /* - * set MILLISECOND_TIME_BASE_DIV - * 100Mhz refclk -> 0x1186a0 - * 27Mhz refclk -> 0x106978 - * 48Mhz refclk -> 0x10bb80 - * - */ - REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0); + struct dc *dc = hws->ctx->dc; - /* This value is dependent on the hardware pipeline delay so set once per SOC */ - REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init) + dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg); } void dcn20_disable_vga( @@ -3058,9 +3043,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); } } else { - if (dccg->funcs->enable_symclk_se) - dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, + if (dccg->funcs->enable_symclk_se && link_enc) { + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA + && link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN + && !link->link_status.link_active) { + if (dccg->funcs->disable_symclk_se) + dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, + link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } else + dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } } if (dc->res_pool->dccg->funcs->set_pixel_rate_div) @@ -3145,12 +3138,13 @@ void dcn20_fpga_init_hw(struct dc *dc) REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF); REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF); - hws->funcs.dccg_init(hws); + dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2); + + if (hws->funcs.dccg_init) + hws->funcs.dccg_init(hws); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2); - REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1); - if (REG(REFCLK_CNTL)) - REG_WRITE(REFCLK_CNTL, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup) + dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg); // diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c index 1635e5a552ad2..ce18d75fd9918 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c @@ -39,6 +39,9 @@ #include "dccg.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" +#include "dio/dcn10/dcn10_dio.h" + #define CTX \ hws->ctx @@ -359,13 +362,13 @@ void dcn201_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index e2269211553ce..062745389d9a4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -33,6 +33,7 @@ #include "vmid.h" #include "reg_helper.h" #include "hw/clk_mgr.h" +#include "hw/dccg.h" #include "dc_dmub_srv.h" #include "abm.h" #include "link_service.h" @@ -87,12 +88,10 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_ bool dcn21_s0i3_golden_init_wa(struct dc *dc) { - struct dce_hwseq *hws = dc->hwseq; - uint32_t value = 0; + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done) + return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg); - value = REG_READ(MICROSECOND_TIME_BASE_DIV); - - return value != 0x00120464; + return false; } void dcn21_exit_optimized_pwr_state( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index f2d4cd527874d..d04cfd403b7ee 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -36,6 +36,7 @@ #include "dcn10/dcn10_cm_common.h" #include "dcn30/dcn30_cm_common.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "clk_mgr.h" #include "hubp.h" @@ -52,6 +53,7 @@ #include "dcn30/dcn30_resource.h" #include "link_service.h" #include "dc_state_priv.h" +#include "dio/dcn10/dcn10_dio.h" #define TO_DCN_DCCG(dccg)\ container_of(dccg, struct dcn_dccg, base) @@ -794,13 +796,13 @@ void dcn30_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index d7ff55669bac0..5cbae0cdda962 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -143,7 +143,6 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 8d7ceb7b32b86..33cc48cd01962 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -140,7 +140,6 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index d1ecdb92b072b..2c91a60f3334c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" @@ -52,6 +53,7 @@ #include "dcn30/dcn30_vpg.h" #include "dce/dce_i2c_hw.h" #include "dce/dmub_abm_lcd.h" +#include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER_INIT(logger) @@ -236,21 +238,17 @@ void dcn31_init_hw(struct dc *dc) abms[i]->funcs->abm_init(abms[i], backlight, user_level); } - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - // Set i2c to light sleep until engine is setup - if (dc->debug.enable_mem_low_power.bits.i2c) - REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1); + /* Power on DIO memory (AFMT HDMI) and set I2C to light sleep */ + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, dc->debug.enable_mem_low_power.bits.i2c); if (hws->funcs.setup_hpo_hw_control) hws->funcs.setup_hpo_hw_control(hws, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } @@ -515,7 +513,6 @@ static void dcn31_reset_back_end_for_pipe( { struct dc_link *link; - DC_LOGGER_INIT(dc->ctx->logger); if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; @@ -539,15 +536,28 @@ static void dcn31_reset_back_end_for_pipe( pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); - pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + /* + * TODO - convert symclk_ref_cnts for otg to a bit map to solve + * the case where the same symclk is shared across multiple otg + * instances + */ if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) - pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0; + link->phy_state.symclk_ref_cnts.otg = 0; + + if (pipe_ctx->top_pipe == NULL) { + if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + + link_hwss->disable_link_output(link, &pipe_ctx->link_res, pipe_ctx->stream->signal); + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; + } + } set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index 5a6a459da224a..e56b9a46aecfe 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -144,7 +144,6 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 4ee6ed610de0b..3e239124c17d8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -108,7 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; + dsc_cfg.dsc_padding = 0; dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 79faab1125d40..9900c87b4567f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -149,7 +149,6 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_blend_lut = dcn30_set_blend_lut, .set_shaper_3dlut = dcn20_set_shaper_3dlut, .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index be1f3caf4096f..bbd6f6e93bc03 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -52,6 +52,7 @@ #include "link_service.h" #include "../dcn20/dcn20_hwseq.h" #include "dc_state_priv.h" +#include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER_INIT(logger) @@ -82,6 +83,9 @@ void dcn32_dsc_pg_control( if (!dc->debug.enable_double_buffered_dsc_pg_support) return; + if (dc->debug.ignore_pg) + return; + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); @@ -129,7 +133,6 @@ void dcn32_dsc_pg_control( REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, bool enable) @@ -168,6 +171,9 @@ void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool p if (hws->ctx->dc->debug.disable_hubp_power_gate) return; + if (hws->ctx->dc->debug.ignore_pg) + return; + if (REG(DOMAIN0_PG_CONFIG) == 0) return; @@ -479,7 +485,7 @@ bool dcn32_set_mcm_luts( struct dpp *dpp_base = pipe_ctx->plane_res.dpp; int mpcc_id = pipe_ctx->plane_res.hubp->inst; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; - bool result = true; + bool rval, result; const struct pwl_params *lut_params = NULL; // 1D LUT @@ -502,10 +508,10 @@ bool dcn32_set_mcm_luts( lut_params = &plane_state->in_shaper_func.pwl; else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { // TODO: dpp_base replace - cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, &plane_state->in_shaper_func, &dpp_base->shaper_params, true); - lut_params = &dpp_base->shaper_params; + lut_params = rval ? &dpp_base->shaper_params : NULL; } mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); @@ -750,6 +756,9 @@ static void dcn32_initialize_min_clocks(struct dc *dc) { struct dc_clocks *clocks = &dc->current_state->bw_ctx.bw.dcn.clk; + if (!dc->clk_mgr || !dc->clk_mgr->bw_params || !dc->clk_mgr->funcs) + return; + clocks->dcfclk_deep_sleep_khz = DCN3_2_DCFCLK_DS_INIT_KHZ; clocks->dcfclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz * 1000; clocks->socclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].socclk_mhz * 1000; @@ -758,9 +767,10 @@ static void dcn32_initialize_min_clocks(struct dc *dc) clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; clocks->fclk_p_state_change_support = true; clocks->p_state_change_support = true; + if (dc->debug.disable_boot_optimizations) { clocks->dispclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dispclk_mhz * 1000; - } else { + } else if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { /* Even though DPG_EN = 1 for the connected display, it still requires the * correct timing so we cannot set DISPCLK to min freq or it could cause * audio corruption. Read current DISPCLK from DENTIST and request the same @@ -769,10 +779,10 @@ static void dcn32_initialize_min_clocks(struct dc *dc) clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); } - dc->clk_mgr->funcs->update_clocks( - dc->clk_mgr, - dc->current_state, - true); + if (dc->clk_mgr->funcs->update_clocks) + dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, + dc->current_state, + true); } void dcn32_init_hw(struct dc *dc) @@ -951,13 +961,13 @@ void dcn32_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } @@ -1000,7 +1010,8 @@ void dcn32_init_hw(struct dc *dc) DMUB_FW_VERSION(7, 0, 35)) { /* FAMS2 is disabled */ dc->debug.fams2_config.bits.enable = false; - if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box) { + if (dc->debug.using_dml2 && dc->res_pool->funcs->update_bw_bounding_box && + dc->clk_mgr && dc->clk_mgr->bw_params) { /* update bounding box if FAMS2 disabled */ dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); } @@ -1063,7 +1074,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; + dsc_cfg.dsc_padding = 0; if (should_use_dto_dscclk) dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index c19ef075c8823..849dae18b7384 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -154,7 +154,6 @@ static const struct hwseq_private_funcs dcn32_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_mcm_luts = dcn32_set_mcm_luts, .program_mall_pipe_config = dcn32_program_mall_pipe_config, .update_force_pstate = dcn32_update_force_pstate, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 7aa0f452e8f7a..b5f60f59382ea 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -32,6 +32,7 @@ #include "dce/dce_hwseq.h" #include "clk_mgr.h" #include "reg_helper.h" +#include "dcn10/dcn10_hubbub.h" #include "abm.h" #include "hubp.h" #include "dchubbub.h" @@ -52,21 +53,22 @@ #include "dcn30/dcn30_vpg.h" #include "dce/dce_i2c_hw.h" #include "dsc.h" +#include "dio/dcn10/dcn10_dio.h" #include "dcn20/dcn20_optc.h" #include "dcn30/dcn30_cm_common.h" #include "dcn31/dcn31_hwseq.h" #include "dcn20/dcn20_hwseq.h" #include "dc_state_priv.h" -#define DC_LOGGER_INIT(logger) \ - struct dal_logger *dc_logger = logger +#define DC_LOGGER \ + dc_ctx->logger +#define DC_LOGGER_INIT(ctx) \ + struct dc_context *dc_ctx = ctx #define CTX \ hws->ctx #define REG(reg)\ hws->regs->reg -#define DC_LOGGER \ - dc_logger #undef FN @@ -271,12 +273,9 @@ void dcn35_init_hw(struct dc *dc) } } - /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); - - // Set i2c to light sleep until engine is setup - if (dc->debug.enable_mem_low_power.bits.i2c) - REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 0); + /* Power on DIO memory (AFMT HDMI) and optionally disable I2C light sleep */ + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, !dc->debug.enable_mem_low_power.bits.i2c); if (hws->funcs.setup_hpo_hw_control) hws->funcs.setup_hpo_hw_control(hws, false); @@ -287,7 +286,8 @@ void dcn35_init_hw(struct dc *dc) } if (dc->debug.disable_mem_low_power) { - REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power) + dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false); } if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); @@ -331,7 +331,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) struct pipe_ctx *odm_pipe; int opp_cnt = 1; - DC_LOGGER_INIT(stream->ctx->logger); + DC_LOGGER_INIT(stream->ctx); ASSERT(dsc); for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) @@ -364,7 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; + dsc_cfg.dsc_padding = 0; dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); @@ -897,7 +897,7 @@ void dcn35_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx bool is_phantom = dc_state_get_pipe_subvp_type(state, pipe_ctx) == SUBVP_PHANTOM; struct timing_generator *tg = is_phantom ? pipe_ctx->stream_res.tg : NULL; - DC_LOGGER_INIT(dc->ctx->logger); + DC_LOGGER_INIT(dc->ctx); if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return; @@ -1631,6 +1631,7 @@ void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pip payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads); cs->offload_streams[stream_idx].payloads[payload_idx].write_idx_start = write_idx; + cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask = 0; if (pipe->plane_res.hubp) pipe->plane_res.hubp->cursor_offload = true; @@ -1726,3 +1727,55 @@ void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe { dc_dmub_srv_program_cursor_now(dc, pipe); } + +static void disable_link_output_symclk_on_tx_off(struct dc_link *link, enum dp_link_encoding link_encoding) +{ + struct dc *dc = link->ctx->dc; + struct pipe_ctx *pipe_ctx = NULL; + uint8_t i; + + for (i = 0; i < MAX_PIPES; i++) { + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { + pipe_ctx->clock_source->funcs->program_pix_clk( + pipe_ctx->clock_source, + &pipe_ctx->stream_res.pix_clk_params, + link_encoding, + &pipe_ctx->pll_settings); + break; + } + } +} + +void dcn35_disable_link_output(struct dc_link *link, + const struct link_resource *link_res, + enum signal_type signal) +{ + struct dc *dc = link->ctx->dc; + const struct link_hwss *link_hwss = get_link_hwss(link, link_res); + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (signal == SIGNAL_TYPE_EDP && + link->dc->hwss.edp_backlight_control && + !link->skip_implict_edp_power_control) + link->dc->hwss.edp_backlight_control(link, false); + else if (dmcu != NULL && dmcu->funcs->lock_phy) + dmcu->funcs->lock_phy(dmcu); + + if (dc_is_tmds_signal(signal) && link->phy_state.symclk_ref_cnts.otg > 0) { + disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING); + link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; + } else { + link_hwss->disable_link_output(link, link_res, signal); + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; + } + /* + * Add the logic to extract BOTH power up and power down sequences + * from enable/disable link output and only call edp panel control + * in enable_link_dp and disable_link_dp once. + */ + if (dmcu != NULL && dmcu->funcs->unlock_phy) + dmcu->funcs->unlock_phy(dmcu); + + dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h index 1ff41dba556c0..e3459546a908a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h @@ -108,5 +108,8 @@ void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context, const struct dc_stream_state *stream); void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe); +void dcn35_disable_link_output(struct dc_link *link, + const struct link_resource *link_res, + enum signal_type signal); #endif /* __DC_HWSS_DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index 5a66c9db26709..6ac8ad97cf135 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -113,7 +113,7 @@ static const struct hw_sequencer_funcs dcn35_funcs = { .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, - .disable_link_output = dcn32_disable_link_output, + .disable_link_output = dcn35_disable_link_output, .z10_restore = dcn35_z10_restore, .z10_save_init = dcn31_z10_save_init, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, @@ -164,7 +164,6 @@ static const struct hwseq_private_funcs dcn35_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_mcm_luts = dcn32_set_mcm_luts, .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index 09e60158f0b5a..04c260015eec3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -153,7 +153,6 @@ static const struct hwseq_private_funcs dcn351_private_funcs = { .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_mcm_luts = dcn32_set_mcm_luts, .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, .calculate_dccg_k1_k2_values = dcn32_calculate_dccg_k1_k2_values, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 5eda7648d0d2b..a72284c3fa1c9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -39,6 +39,7 @@ #include "dc_state_priv.h" #include "link_enc_cfg.h" #include "../hw_sequencer.h" +#include "dio/dcn10/dcn10_dio.h" #define DC_LOGGER_INIT(logger) @@ -71,7 +72,11 @@ void dcn401_initialize_min_clocks(struct dc *dc) * audio corruption. Read current DISPCLK from DENTIST and request the same * freq to ensure that the timing is valid and unchanged. */ - clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); + if (dc->clk_mgr->funcs->get_dispclk_from_dentist) { + clocks->dispclk_khz = dc->clk_mgr->funcs->get_dispclk_from_dentist(dc->clk_mgr); + } else { + clocks->dispclk_khz = dc->clk_mgr->boot_snapshot.dispclk * 1000; + } } clocks->ref_dtbclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dtbclk_mhz * 1000; clocks->fclk_p_state_change_support = true; @@ -90,10 +95,6 @@ void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; - //For now assert if location is not pre-blend - if (pipe_ctx->plane_state) - ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); - // program MPCC_MCM_FIRST_GAMUT_REMAP memset(&mpc_adjust, 0, sizeof(mpc_adjust)); mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -287,6 +288,8 @@ void dcn401_init_hw(struct dc *dc) for (i = 0; i < dc->link_count; i++) { struct dc_link *link = dc->links[i]; + if (link->ep_type != DISPLAY_ENDPOINT_PHY) + continue; if (link->link_enc->funcs->is_dig_enabled && link->link_enc->funcs->is_dig_enabled(link->link_enc) && hws->funcs.power_down) { @@ -319,13 +322,13 @@ void dcn401_init_hw(struct dc *dc) } /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ - REG_WRITE(DIO_MEM_PWR_CTRL, 0); + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); + if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating) + dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true); REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } @@ -366,293 +369,200 @@ void dcn401_init_hw(struct dc *dc) } } -static void dcn401_get_mcm_lut_xable_from_pipe_ctx(struct dc *dc, struct pipe_ctx *pipe_ctx, - enum MCM_LUT_XABLE *shaper_xable, - enum MCM_LUT_XABLE *lut3d_xable, - enum MCM_LUT_XABLE *lut1d_xable) +void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx) { - enum dc_cm2_shaper_3dlut_setting shaper_3dlut_setting = DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL; - bool lut1d_enable = false; - struct mpc *mpc = dc->res_pool->mpc; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; + const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx); + struct hubp *primary_hubp = primary_dpp_pipe_ctx ? + primary_dpp_pipe_ctx->plane_res.hubp : NULL; - if (!pipe_ctx->plane_state) - return; - shaper_3dlut_setting = pipe_ctx->plane_state->mcm_shaper_3dlut_setting; - lut1d_enable = pipe_ctx->plane_state->mcm_lut1d_enable; - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; - - *lut1d_xable = lut1d_enable ? MCM_LUT_ENABLE : MCM_LUT_DISABLE; - - switch (shaper_3dlut_setting) { - case DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL: - *lut3d_xable = *shaper_xable = MCM_LUT_DISABLE; - break; - case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER: - *lut3d_xable = MCM_LUT_DISABLE; - *shaper_xable = MCM_LUT_ENABLE; - break; - case DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT: - *lut3d_xable = *shaper_xable = MCM_LUT_ENABLE; - break; + if (primary_hubp && primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); } } -void dcn401_populate_mcm_luts(struct dc *dc, - struct pipe_ctx *pipe_ctx, - struct dc_cm2_func_luts mcm_luts, - bool lut_bank_a) +bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) { + struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; + const struct pipe_ctx *primary_dpp_pipe_ctx = resource_get_primary_dpp_pipe(pipe_ctx); struct dpp *dpp_base = pipe_ctx->plane_res.dpp; struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct hubp *primary_hubp = primary_dpp_pipe_ctx ? + primary_dpp_pipe_ctx->plane_res.hubp : NULL; + const struct dc_plane_cm *cm = &plane_state->cm; int mpcc_id = hubp->inst; struct mpc *mpc = dc->res_pool->mpc; union mcm_lut_params m_lut_params; - enum dc_cm2_transfer_func_source lut3d_src = mcm_luts.lut3d_data.lut3d_src; - enum hubp_3dlut_fl_format format = 0; - enum hubp_3dlut_fl_mode mode; - enum hubp_3dlut_fl_width width = 0; - enum hubp_3dlut_fl_addressing_mode addr_mode; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g = 0; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b = 0; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r = 0; - enum MCM_LUT_XABLE shaper_xable = MCM_LUT_DISABLE; - enum MCM_LUT_XABLE lut3d_xable = MCM_LUT_DISABLE; - enum MCM_LUT_XABLE lut1d_xable = MCM_LUT_DISABLE; + struct dc_3dlut_dma lut3d_dma; + bool lut_enable; + bool lut_bank_a; bool rval; + bool result = true; - dcn401_get_mcm_lut_xable_from_pipe_ctx(dc, pipe_ctx, &shaper_xable, &lut3d_xable, &lut1d_xable); + /* decide LUT bank based on current in use */ + mpc->funcs->get_lut_mode(mpc, MCM_LUT_1DLUT, mpcc_id, &lut_enable, &lut_bank_a); + if (!lut_enable) { + mpc->funcs->get_lut_mode(mpc, MCM_LUT_SHAPER, mpcc_id, &lut_enable, &lut_bank_a); + } + if (!lut_enable) { + mpc->funcs->get_lut_mode(mpc, MCM_LUT_3DLUT, mpcc_id, &lut_enable, &lut_bank_a); + } + + /* switch to the next bank */ + if (lut_enable) { + lut_bank_a = !lut_bank_a; + } + + /* MCM location fixed to pre-blend */ + mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); /* 1D LUT */ - if (mcm_luts.lut1d_func) { - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts.lut1d_func->type == TF_TYPE_HWPWL) - m_lut_params.pwl = &mcm_luts.lut1d_func->pwl; - else if (mcm_luts.lut1d_func->type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, - mcm_luts.lut1d_func, - &dpp_base->regamma_params, false); + lut_enable = cm->flags.bits.blend_enable; + memset(&m_lut_params, 0, sizeof(m_lut_params)); + if (lut_enable) { + if (cm->blend_func.type == TF_TYPE_HWPWL) + m_lut_params.pwl = &cm->blend_func.pwl; + else if (cm->blend_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &cm->blend_func, + &dpp_base->regamma_params, + false); m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; } - if (m_lut_params.pwl) { - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, m_lut_params, lut_bank_a, mpcc_id); + + if (!m_lut_params.pwl) { + lut_enable = false; } - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut1d_xable && m_lut_params.pwl, lut_bank_a, mpcc_id); + } else { + lut_enable = false; } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); + if (lut_enable && mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_1DLUT, &m_lut_params, lut_bank_a, mpcc_id); + /* Shaper */ - if (mcm_luts.shaper && mcm_luts.lut3d_data.mpc_3dlut_enable) { + lut_enable = cm->flags.bits.shaper_enable; + if (lut_enable) { memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (mcm_luts.shaper->type == TF_TYPE_HWPWL) - m_lut_params.pwl = &mcm_luts.shaper->pwl; - else if (mcm_luts.shaper->type == TF_TYPE_DISTRIBUTED_POINTS) { + if (cm->shaper_func.type == TF_TYPE_HWPWL) + m_lut_params.pwl = &cm->shaper_func.pwl; + else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { ASSERT(false); - rval = cm3_helper_translate_curve_to_hw_format(mpc->ctx, - mcm_luts.shaper, - &dpp_base->regamma_params, true); - m_lut_params.pwl = rval ? &dpp_base->regamma_params : NULL; + rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, + &cm->shaper_func, + &dpp_base->shaper_params, + true); + m_lut_params.pwl = rval ? &dpp_base->shaper_params : NULL; } - if (m_lut_params.pwl) { - if (mpc->funcs->mcm.populate_lut) - mpc->funcs->mcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_ENABLE, lut_bank_a, mpcc_id); + if (!m_lut_params.pwl) { + lut_enable = false; } + } else { + lut_enable = false; } - /* 3DLUT */ - switch (lut3d_src) { - case DC_CM2_TRANSFER_FUNC_SOURCE_SYSMEM: - memset(&m_lut_params, 0, sizeof(m_lut_params)); - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, false); - - if (mcm_luts.lut3d_data.lut3d_func && mcm_luts.lut3d_data.lut3d_func->state.bits.initialized) { - m_lut_params.lut3d = &mcm_luts.lut3d_data.lut3d_func->lut_3d; - if (mpc->funcs->populate_lut) - mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, m_lut_params, lut_bank_a, mpcc_id); - if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, - mpcc_id); - } - break; - case DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM: - switch (mcm_luts.lut3d_data.gpu_mem_params.size) { - case DC_CM2_GPU_MEM_SIZE_171717: - width = hubp_3dlut_fl_width_17; - break; - case DC_CM2_GPU_MEM_SIZE_TRANSFORMED: - width = hubp_3dlut_fl_width_transformed; - break; - default: - //TODO: handle default case - break; - } + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, lut_enable, lut_bank_a, CM_LUT_SIZE_NONE, mpcc_id); + if (lut_enable && mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_SHAPER, &m_lut_params, lut_bank_a, mpcc_id); - //check for support - if (mpc->funcs->mcm.is_config_supported && - !mpc->funcs->mcm.is_config_supported(width)) - break; + /* NOTE: Toggling from DMA->Host is not supported atomically as hardware + * blocks writes until 3DLUT FL mode is cleared from HUBP on VUpdate. + * Expectation is either option is used consistently. + */ - if (mpc->funcs->program_lut_read_write_control) - mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, mpcc_id); + /* 3DLUT */ + lut_enable = cm->flags.bits.lut3d_enable; + if (lut_enable && cm->flags.bits.lut3d_dma_enable) { + /* Fast (DMA) Load Mode */ + /* MPC */ if (mpc->funcs->program_lut_mode) - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut3d_xable, lut_bank_a, mpcc_id); - - if (hubp->funcs->hubp_program_3dlut_fl_addr) - hubp->funcs->hubp_program_3dlut_fl_addr(hubp, mcm_luts.lut3d_data.gpu_mem_params.addr); + mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, lut_enable, lut_bank_a, cm->lut3d_dma.size, mpcc_id); - if (mpc->funcs->mcm.program_bit_depth) - mpc->funcs->mcm.program_bit_depth(mpc, mcm_luts.lut3d_data.gpu_mem_params.bit_depth, mpcc_id); - - switch (mcm_luts.lut3d_data.gpu_mem_params.layout) { - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_RGB: - mode = hubp_3dlut_fl_mode_native_1; - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_3D_SWIZZLE_LINEAR_BGR: - mode = hubp_3dlut_fl_mode_native_2; - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - case DC_CM2_GPU_MEM_LAYOUT_1D_PACKED_LINEAR: - mode = hubp_3dlut_fl_mode_transform; - addr_mode = hubp_3dlut_fl_addressing_mode_simple_linear; - break; - default: - mode = hubp_3dlut_fl_mode_disable; - addr_mode = hubp_3dlut_fl_addressing_mode_sw_linear; - break; - } - if (hubp->funcs->hubp_program_3dlut_fl_mode) - hubp->funcs->hubp_program_3dlut_fl_mode(hubp, mode); + /* only supports 12 bit */ + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, 12, mpcc_id); - if (hubp->funcs->hubp_program_3dlut_fl_addressing_mode) - hubp->funcs->hubp_program_3dlut_fl_addressing_mode(hubp, addr_mode); + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, primary_hubp->inst); - switch (mcm_luts.lut3d_data.gpu_mem_params.format_params.format) { - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12MSB: - format = hubp_3dlut_fl_format_unorm_12msb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_UNORM_12LSB: - format = hubp_3dlut_fl_format_unorm_12lsb_bitslice; - break; - case DC_CM2_GPU_MEM_FORMAT_16161616_FLOAT_FP1_5_10: - format = hubp_3dlut_fl_format_float_fp1_5_10; - break; - } - if (hubp->funcs->hubp_program_3dlut_fl_format) - hubp->funcs->hubp_program_3dlut_fl_format(hubp, format); - if (hubp->funcs->hubp_update_3dlut_fl_bias_scale && - mpc->funcs->mcm.program_bias_scale) { - mpc->funcs->mcm.program_bias_scale(mpc, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale, - mpcc_id); - hubp->funcs->hubp_update_3dlut_fl_bias_scale(hubp, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.bias, - mcm_luts.lut3d_data.gpu_mem_params.format_params.float_params.scale); - } - - //navi 4x has a bug and r and blue are swapped and need to be worked around here in - //TODO: need to make a method for get_xbar per asic OR do the workaround in program_crossbar for 4x - switch (mcm_luts.lut3d_data.gpu_mem_params.component_order) { - case DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA: - default: - crossbar_bit_slice_cr_r = hubp_3dlut_fl_crossbar_bit_slice_0_15; - crossbar_bit_slice_y_g = hubp_3dlut_fl_crossbar_bit_slice_16_31; - crossbar_bit_slice_cb_b = hubp_3dlut_fl_crossbar_bit_slice_32_47; - break; - } + /* HUBP */ + if (primary_hubp->inst == hubp->inst) { + /* only program if this is the primary dpp pipe for the given plane */ + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); - if (hubp->funcs->hubp_program_3dlut_fl_crossbar) - hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, - crossbar_bit_slice_cr_r, - crossbar_bit_slice_y_g, - crossbar_bit_slice_cb_b); + if (hubp->funcs->hubp_program_3dlut_fl_crossbar) + hubp->funcs->hubp_program_3dlut_fl_crossbar(hubp, cm->lut3d_dma.format); - if (mpc->funcs->mcm.program_lut_read_write_control) - mpc->funcs->mcm.program_lut_read_write_control(mpc, MCM_LUT_3DLUT, lut_bank_a, true, mpcc_id); + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); - if (mpc->funcs->mcm.program_3dlut_size) - mpc->funcs->mcm.program_3dlut_size(mpc, width, mpcc_id); + if (hubp->funcs->hubp_enable_3dlut_fl) { + hubp->funcs->hubp_enable_3dlut_fl(hubp, true); + } else { + /* GPU memory only supports fast load path */ + BREAK_TO_DEBUGGER(); + lut_enable = false; + result = false; + } + } else { + /* re-trigger priamry HUBP to load 3DLUT */ + if (primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); + } - if (mpc->funcs->update_3dlut_fast_load_select) - mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, hubp->inst); + /* clear FL setup on this pipe's HUBP */ + memset(&lut3d_dma, 0, sizeof(lut3d_dma)); + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); - if (hubp->funcs->hubp_enable_3dlut_fl) - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - else { - if (mpc->funcs->program_lut_mode) { - mpc->funcs->program_lut_mode(mpc, MCM_LUT_SHAPER, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - mpc->funcs->program_lut_mode(mpc, MCM_LUT_3DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - mpc->funcs->program_lut_mode(mpc, MCM_LUT_1DLUT, MCM_LUT_DISABLE, lut_bank_a, mpcc_id); - } + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); } - break; + } else { + /* Legacy (Host) Load Mode */ + memset(&m_lut_params, 0, sizeof(m_lut_params)); - } -} + if (cm->flags.bits.lut3d_enable && cm->lut3d_func.state.bits.initialized) { + m_lut_params.lut3d = &cm->lut3d_func.lut_3d; + } else { + lut_enable = false; + } -void dcn401_trigger_3dlut_dma_load(struct dc *dc, struct pipe_ctx *pipe_ctx) -{ - struct hubp *hubp = pipe_ctx->plane_res.hubp; + /* MPC */ + if (mpc->funcs->program_lut_mode) + mpc->funcs->program_lut_mode(mpc, + MCM_LUT_3DLUT, + lut_enable, + lut_bank_a, + cm->lut3d_func.lut_3d.use_tetrahedral_9 ? CM_LUT_SIZE_999 : CM_LUT_SIZE_171717, + mpcc_id); + + if (lut_enable) { + if (mpc->funcs->program_lut_read_write_control) + mpc->funcs->program_lut_read_write_control(mpc, + MCM_LUT_3DLUT, + lut_bank_a, + cm->lut3d_func.lut_3d.use_12bits ? 12 : 10, + mpcc_id); - if (hubp->funcs->hubp_enable_3dlut_fl) { - hubp->funcs->hubp_enable_3dlut_fl(hubp, true); - } -} + if (mpc->funcs->update_3dlut_fast_load_select) + mpc->funcs->update_3dlut_fast_load_select(mpc, mpcc_id, 0xf); -bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *plane_state) -{ - struct dpp *dpp_base = pipe_ctx->plane_res.dpp; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; - struct mpc *mpc = dc->res_pool->mpc; - bool result; - const struct pwl_params *lut_params = NULL; - bool rval; + if (mpc->funcs->populate_lut) + mpc->funcs->populate_lut(mpc, MCM_LUT_3DLUT, &m_lut_params, lut_bank_a, mpcc_id); + } - if (plane_state->mcm_luts.lut3d_data.lut3d_src == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM) { - dcn401_populate_mcm_luts(dc, pipe_ctx, plane_state->mcm_luts, plane_state->lut_bank_a); - return true; - } + /* HUBP */ + memset(&lut3d_dma, 0, sizeof(lut3d_dma)); + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &lut3d_dma); - mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id); - pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE; - // 1D LUT - if (plane_state->blend_tf.type == TF_TYPE_HWPWL) - lut_params = &plane_state->blend_tf.pwl; - else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) { - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &plane_state->blend_tf, - &dpp_base->regamma_params, false); - lut_params = rval ? &dpp_base->regamma_params : NULL; - } - result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id); - lut_params = NULL; - - // Shaper - if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL) - lut_params = &plane_state->in_shaper_func.pwl; - else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { - // TODO: dpp_base replace - rval = cm3_helper_translate_curve_to_hw_format(plane_state->ctx, - &plane_state->in_shaper_func, - &dpp_base->shaper_params, true); - lut_params = rval ? &dpp_base->shaper_params : NULL; - } - result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id); - - // 3D - if (mpc->funcs->program_3dlut) { - if (plane_state->lut3d_func.state.bits.initialized == 1) - result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id); - else - result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id); + if (hubp->funcs->hubp_enable_3dlut_fl) + hubp->funcs->hubp_enable_3dlut_fl(hubp, false); } return result; @@ -917,10 +827,10 @@ static void dcn401_enable_stream_calc( pipe_ctx->stream->link->cur_link_settings.lane_count; uint32_t active_total_with_borders; - if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) + if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { *dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; - - *phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link); + *phyd32clk = get_phyd32clk_src(pipe_ctx->stream->link); + } if (dc_is_tmds_signal(pipe_ctx->stream->signal)) dcn401_calculate_dccg_tmds_div_value(pipe_ctx, tmds_div); @@ -949,7 +859,7 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); struct dc *dc = pipe_ctx->stream->ctx->dc; struct dccg *dccg = dc->res_pool->dccg; - enum phyd32clk_clock_source phyd32clk; + enum phyd32clk_clock_source phyd32clk = PHYD32CLKA; int dp_hpo_inst = 0; unsigned int tmds_div = PIXEL_RATE_DIV_NA; unsigned int unused_div = PIXEL_RATE_DIV_NA; @@ -976,6 +886,8 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) } } + link_hwss->setup_stream_attribute(pipe_ctx); + if (dc->res_pool->dccg->funcs->set_pixel_rate_div) { dc->res_pool->dccg->funcs->set_pixel_rate_div( dc->res_pool->dccg, @@ -1200,6 +1112,25 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) x_pos = pos_cpy.x - param.recout.x; y_pos = pos_cpy.y - param.recout.y; + /** + * If the cursor position is negative after recout adjustment, we need + * to shift the hotspot to compensate and clamp position to 0. This + * handles the case where cursor straddles the left/top edge of an + * overlay plane - the cursor is partially visible and needs correct + * hotspot adjustment to render the visible portion. + */ + if (x_pos < 0) { + pos_cpy.x_hotspot -= x_pos; + if (hubp->curs_attr.attribute_flags.bits.ENABLE_MAGNIFICATION) + adjust_hotspot_between_slices_for_2x_magnify(hubp->curs_attr.width, &pos_cpy); + x_pos = 0; + } + + if (y_pos < 0) { + pos_cpy.y_hotspot -= y_pos; + y_pos = 0; + } + recout_x_pos = x_pos - pos_cpy.x_hotspot; recout_y_pos = y_pos - pos_cpy.y_hotspot; @@ -1215,6 +1146,9 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) if (recout_y_pos + (int)hubp->curs_attr.height <= 0) pos_cpy.enable = false; /* not visible beyond top edge*/ + pos_cpy.x = x_pos; + pos_cpy.y = y_pos; + hubp->funcs->set_cursor_position(hubp, &pos_cpy, ¶m); dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.height); } @@ -1459,7 +1393,7 @@ void dcn401_optimize_bandwidth( dc->clk_mgr, context, true); - if (context->bw_ctx.bw.dcn.clk.zstate_support == DCN_ZSTATE_SUPPORT_ALLOW) { + if (context->bw_ctx.bw.dcn.clk.zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW) { for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; @@ -1467,7 +1401,7 @@ void dcn401_optimize_bandwidth( && pipe_ctx->stream->adjust.v_total_min == pipe_ctx->stream->adjust.v_total_max && pipe_ctx->stream->adjust.v_total_max > pipe_ctx->stream->timing.v_total) pipe_ctx->plane_res.hubp->funcs->program_extended_blank(pipe_ctx->plane_res.hubp, - pipe_ctx->dlg_regs.min_dst_y_next_start); + pipe_ctx->hubp_regs.dlg_regs.min_dst_y_next_start); } } } @@ -1510,14 +1444,15 @@ void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params) void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable) { - bool fams2_required; + bool fams2_info_required; if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable) return; - fams2_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; + fams2_info_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable; + fams2_info_required |= context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2; - dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_required); + dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_info_required); } static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context, @@ -1771,7 +1706,8 @@ void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, void dcn401_hardware_release(struct dc *dc) { if (!dc->debug.disable_force_pstate_allow_on_hw_release) { - dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); + if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable) + dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); /* If pstate unsupported, or still supported * by firmware, force it supported by dcn @@ -1791,7 +1727,9 @@ void dcn401_hardware_release(struct dc *dc) dc->clk_mgr->clks.p_state_change_support = false; dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true); } - dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); + + if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable) + dc_dmub_srv_fams2_update_config(dc, dc->current_state, false); } } @@ -1892,43 +1830,41 @@ void dcn401_perform_3dlut_wa_unlock(struct pipe_ctx *pipe_ctx) * This is meant to work around a known HW issue where VREADY will cancel the pending 3DLUT_ENABLE signal regardless * of whether OTG lock is currently being held or not. */ - struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL }; - struct pipe_ctx *odm_pipe, *mpc_pipe; - int i, wa_pipe_ct = 0; - - for (odm_pipe = pipe_ctx; odm_pipe != NULL; odm_pipe = odm_pipe->next_odm_pipe) { - for (mpc_pipe = odm_pipe; mpc_pipe != NULL; mpc_pipe = mpc_pipe->bottom_pipe) { - if (mpc_pipe->plane_state && mpc_pipe->plane_state->mcm_luts.lut3d_data.lut3d_src - == DC_CM2_TRANSFER_FUNC_SOURCE_VIDMEM - && mpc_pipe->plane_state->mcm_shaper_3dlut_setting - == DC_CM2_SHAPER_3DLUT_SETTING_ENABLE_SHAPER_3DLUT) { - wa_pipes[wa_pipe_ct++] = mpc_pipe; - } - } + const struct pipe_ctx *otg_master_pipe_ctx = resource_get_otg_master(pipe_ctx); + struct timing_generator *tg = otg_master_pipe_ctx ? + otg_master_pipe_ctx->stream_res.tg : NULL; + const struct pipe_ctx *primary_dpp_pipe_ctx = resource_is_pipe_type(pipe_ctx, DPP_PIPE) ? + resource_get_primary_dpp_pipe(pipe_ctx) : pipe_ctx; + struct hubp *primary_hubp = primary_dpp_pipe_ctx ? + primary_dpp_pipe_ctx->plane_res.hubp : NULL; + + if (!otg_master_pipe_ctx && !tg) { + return; } - if (wa_pipe_ct > 0) { - if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout) - pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, true); + if (primary_dpp_pipe_ctx && + primary_dpp_pipe_ctx->plane_state && + primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_enable && + primary_dpp_pipe_ctx->plane_state->cm.flags.bits.lut3d_dma_enable) { + if (tg->funcs->set_vupdate_keepout) + tg->funcs->set_vupdate_keepout(tg, true); - for (i = 0; i < wa_pipe_ct; ++i) { - if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl) - wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); + if (primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); } - pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); - if (pipe_ctx->stream_res.tg->funcs->wait_update_lock_status) - pipe_ctx->stream_res.tg->funcs->wait_update_lock_status(pipe_ctx->stream_res.tg, false); + tg->funcs->unlock(tg); + if (tg->funcs->wait_update_lock_status) + tg->funcs->wait_update_lock_status(tg, false); - for (i = 0; i < wa_pipe_ct; ++i) { - if (wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl) - wa_pipes[i]->plane_res.hubp->funcs->hubp_enable_3dlut_fl(wa_pipes[i]->plane_res.hubp, true); + if (primary_hubp->funcs->hubp_enable_3dlut_fl) { + primary_hubp->funcs->hubp_enable_3dlut_fl(primary_hubp, true); } - if (pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout) - pipe_ctx->stream_res.tg->funcs->set_vupdate_keepout(pipe_ctx->stream_res.tg, false); + if (tg->funcs->set_vupdate_keepout) + tg->funcs->set_vupdate_keepout(tg, false); } else { - pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); + tg->funcs->unlock(tg); } } @@ -1950,7 +1886,6 @@ void dcn401_reset_back_end_for_pipe( struct dc_link *link = pipe_ctx->stream->link; const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); - DC_LOGGER_INIT(dc->ctx->logger); if (pipe_ctx->stream_res.stream_enc == NULL) { pipe_ctx->stream = NULL; return; @@ -2029,6 +1964,22 @@ void dcn401_reset_back_end_for_pipe( DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); } +static void dc_hwss_disable_otg_pwa(struct dc *dc) +{ + if (dc->debug.enable_otg_frame_sync_pwa) { + int i; + + /*reset all the otg*/ + for (i = dc->res_pool->timing_generator_count - 1; i >= 0 ; i--) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + + if (tg->funcs->disable_otg_pwa) { + tg->funcs->disable_otg_pwa(tg); + DC_LOG_DC("otg frame sync pwa disabled on otg%d\n", tg->inst); + } + } + } +} void dcn401_reset_hw_ctx_wrap( struct dc *dc, @@ -2037,6 +1988,7 @@ void dcn401_reset_hw_ctx_wrap( int i; struct dce_hwseq *hws = dc->hwseq; + dc_hwss_disable_otg_pwa(dc); /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = @@ -2227,6 +2179,10 @@ void dcn401_program_pipe( pipe_ctx->stream_res.test_pattern_params.height, pipe_ctx->stream_res.test_pattern_params.offset); } + if (pipe_ctx->plane_state + && pipe_ctx->plane_state->update_flags.bits.cm_hist_change + && hws->funcs.program_cm_hist) + hws->funcs.program_cm_hist(dc, pipe_ctx, pipe_ctx->plane_state); } /* @@ -2378,6 +2334,13 @@ void dcn401_program_pipe_sequence( pipe_ctx->stream_res.test_pattern_params.offset); } + if (pipe_ctx->plane_state + && pipe_ctx->plane_state->update_flags.bits.cm_hist_change + && hws->funcs.program_cm_hist) { + + hwss_add_dpp_program_cm_hist(seq_state, pipe_ctx->plane_res.dpp, + pipe_ctx->plane_state->cm_hist_control, pipe_ctx->plane_state->color_space); + } } void dcn401_program_front_end_for_ctx( @@ -2390,8 +2353,6 @@ void dcn401_program_front_end_for_ctx( struct dce_hwseq *hws = dc->hwseq; struct pipe_ctx *pipe = NULL; - DC_LOGGER_INIT(dc->ctx->logger); - if (resource_is_pipe_topology_changed(dc->current_state, context)) resource_log_pipe_topology_update(dc, context); @@ -2555,8 +2516,6 @@ void dcn401_post_unlock_program_front_end( struct dce_hwseq *hwseq = dc->hwseq; int i; - DC_LOGGER_INIT(dc->ctx->logger); - for (i = 0; i < dc->res_pool->pipe_count; i++) if (resource_is_pipe_type(&dc->current_state->res_ctx.pipe_ctx[i], OPP_HEAD) && !resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], OPP_HEAD)) @@ -2936,8 +2895,6 @@ void dcn401_plane_atomic_power_down(struct dc *dc, struct dce_hwseq *hws = dc->hwseq; uint32_t org_ip_request_cntl = 0; - DC_LOGGER_INIT(dc->ctx->logger); - if (REG(DC_IP_REQUEST_CNTL)) { REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); if (org_ip_request_cntl == 0) @@ -3029,8 +2986,6 @@ void dcn401_plane_atomic_power_down_sequence(struct dc *dc, struct dce_hwseq *hws = dc->hwseq; uint32_t org_ip_request_cntl = 0; - DC_LOGGER_INIT(dc->ctx->logger); - /* Check and set DC_IP_REQUEST_CNTL if needed */ if (REG(DC_IP_REQUEST_CNTL)) { REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index f78162ab859b4..b9a03ffa27179 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -41,8 +41,7 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx, bool dcn401_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); -void dcn401_trigger_3dlut_dma_load(struct dc *dc, - struct pipe_ctx *pipe_ctx); +void dcn401_trigger_3dlut_dma_load(struct pipe_ctx *pipe_ctx); void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx, unsigned int *tmds_div); enum dc_status dcn401_enable_stream_timing( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 162096ce0bdfb..5d0dfb36f3e1b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -156,7 +156,6 @@ static const struct hwseq_private_funcs dcn401_private_funcs = { .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .verify_allow_pstate_change_high_sequence = dcn401_verify_allow_pstate_change_high_sequence, .wait_for_blank_complete = dcn20_wait_for_blank_complete, - .dccg_init = dcn20_dccg_init, .set_mcm_luts = dcn401_set_mcm_luts, .program_mall_pipe_config = dcn32_program_mall_pipe_config, .program_mall_pipe_config_sequence = dcn401_program_mall_pipe_config_sequence, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c new file mode 100644 index 0000000000000..7f9c121c00e67 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -0,0 +1,1102 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dm_helpers.h" +#include "core_types.h" +#include "resource.h" +#include "dccg.h" +#include "dce/dce_hwseq.h" +#include "dcn30/dcn30_cm_common.h" +#include "reg_helper.h" +#include "abm.h" +#include "hubp.h" +#include "dchubbub.h" +#include "timing_generator.h" +#include "opp.h" +#include "ipp.h" +#include "mpc.h" +#include "mcif_wb.h" +#include "dc_dmub_srv.h" +#include "link_hwss.h" +#include "dpcd_defs.h" +#include "dcn401/dcn401_hwseq.h" +#include "dcn42_hwseq.h" +#include "clk_mgr.h" +#include "dsc.h" +#include "dcn20/dcn20_optc.h" +#include "dce/dmub_hw_lock_mgr.h" +#include "dcn42/dcn42_resource.h" +#include "link_service.h" +#include "../dcn10/dcn10_hwseq.h" +#include "../dcn20/dcn20_hwseq.h" +#include "dc_state_priv.h" +#include "dc_stream_priv.h" +#include "dcn35/dcn35_hwseq.h" +#include "dcn42/dcn42_hwseq.h" +#include "dce/dmub_hw_lock_mgr.h" +#include "dio/dcn10/dcn10_dio.h" + +#define DC_LOGGER \ + ctx->logger + +#define CTX \ + hws->ctx + +#define REG(reg)\ + hws->regs->reg + +#undef FN +#define FN(reg_name, field_name) \ + hws->shifts->field_name, hws->masks->field_name + + +static void print_pg_status(struct dc *dc, const char *debug_func, const char *debug_log) +{ + if (dc->debug.enable_pg_cntl_debug_logs && dc->res_pool->pg_cntl) { + if (dc->res_pool->pg_cntl->funcs->print_pg_status) + dc->res_pool->pg_cntl->funcs->print_pg_status(dc->res_pool->pg_cntl, debug_func, debug_log); + } +} +void dcn42_init_hw(struct dc *dc) +{ + struct abm **abms = dc->res_pool->multiple_abms; + struct dce_hwseq *hws = dc->hwseq; + struct dc_bios *dcb = dc->ctx->dc_bios; + struct resource_pool *res_pool = dc->res_pool; + int i; + int edp_num; + uint32_t backlight = MAX_BACKLIGHT_LEVEL; + uint32_t user_level = MAX_BACKLIGHT_LEVEL; + bool dchub_ref_freq_changed; + int current_dchub_ref_freq = 0; + + if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->init_clocks) { + dc->clk_mgr->funcs->init_clocks(dc->clk_mgr); + + // mark dcmode limits present if any clock has distinct AC and DC values from SMU + dc->caps.dcmode_power_limits_present = dc->clk_mgr->funcs->is_dc_mode_present && + dc->clk_mgr->funcs->is_dc_mode_present(dc->clk_mgr); + } + + // Initialize the dccg + if (res_pool->dccg->funcs->dccg_init) + res_pool->dccg->funcs->dccg_init(res_pool->dccg); + + // Disable DMUB Initialization until IPS state programming is finalized + //if (!dcb->funcs->is_accelerated_mode(dcb)) { + // hws->funcs.bios_golden_init(dc); + //} + + // Set default OPTC memory power states + if (dc->debug.enable_mem_low_power.bits.optc) { + // Shutdown when unassigned and light sleep in VBLANK + REG_SET_2(ODM_MEM_PWR_CTRL3, 0, ODM_MEM_UNASSIGNED_PWR_MODE, 3, ODM_MEM_VBLANK_PWR_MODE, 1); + } + + if (dc->debug.enable_mem_low_power.bits.vga) { + // Power down VGA memory + REG_UPDATE(MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, 1); + } + + if (dc->ctx->dc_bios->fw_info_valid) { + res_pool->ref_clocks.xtalin_clock_inKhz = + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency; + + if (res_pool->hubbub) { + (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, + dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency, + &res_pool->ref_clocks.dccg_ref_clock_inKhz); + + current_dchub_ref_freq = res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; + + (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, + res_pool->ref_clocks.dccg_ref_clock_inKhz, + &res_pool->ref_clocks.dchub_ref_clock_inKhz); + } else { + // Not all ASICs have DCCG sw component + res_pool->ref_clocks.dccg_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + res_pool->ref_clocks.dchub_ref_clock_inKhz = + res_pool->ref_clocks.xtalin_clock_inKhz; + } + } else + ASSERT_CRITICAL(false); + + for (i = 0; i < dc->link_count; i++) { + /* Power up AND update implementation according to the + * required signal (which may be different from the + * default signal on connector). + */ + struct dc_link *link = dc->links[i]; + + if (link->ep_type != DISPLAY_ENDPOINT_PHY) + continue; + + link->link_enc->funcs->hw_init(link->link_enc); + + /* Check for enabled DIG to identify enabled display */ + if (link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc)) { + link->link_status.link_active = true; + link->phy_state.symclk_state = SYMCLK_ON_TX_ON; + if (link->link_enc->funcs->fec_is_active && + link->link_enc->funcs->fec_is_active(link->link_enc)) + link->fec_state = dc_link_fec_enabled; + } + } + + /* enable_power_gating_plane before dsc_pg_control because + * FORCEON = 1 with hw default value on bootup, resume from s3 + */ + if (hws->funcs.enable_power_gating_plane) + hws->funcs.enable_power_gating_plane(dc->hwseq, true); + + /* we want to turn off all dp displays before doing detection */ + dc->link_srv->blank_all_dp_displays(dc); + + /* If taking control over from VBIOS, we may want to optimize our first + * mode set, so we need to skip powering down pipes until we know which + * pipes we want to use. + * Otherwise, if taking control is not possible, we need to power + * everything down. + */ + if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) { + /* Disable boot optimizations means power down everything including PHY, DIG, + * and OTG (i.e. the boot is not optimized because we do a full power down). + */ + if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations) + dc->hwss.enable_accelerated_mode(dc, dc->current_state); + else + hws->funcs.init_pipes(dc, dc->current_state); + + if (dc->res_pool->hubbub->funcs->allow_self_refresh_control) + dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, + !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); + + } + + /* In headless boot cases, DIG may be turned + * on which causes HW/SW discrepancies. + * To avoid this, power down hardware on boot + * if DIG is turned on and seamless boot not enabled + */ + if (!dc->config.seamless_boot_edp_requested) { + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link; + + dc_get_edp_links(dc, edp_links, &edp_num); + if (edp_num) { + for (i = 0; i < edp_num; i++) { + edp_link = edp_links[i]; + if (edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwss.edp_backlight_control && + hws->funcs.power_down && + dc->hwss.edp_power_control) { + dc->hwss.edp_backlight_control(edp_link, false); + hws->funcs.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } + } + } else { + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link && link->link_enc && + link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc) && + hws->funcs.power_down) { + hws->funcs.power_down(dc); + break; + } + + } + } + } + + for (i = 0; i < res_pool->audio_count; i++) { + struct audio *audio = res_pool->audios[i]; + + audio->funcs->hw_init(audio); + } + + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->panel_cntl) { + backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); + user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL; + } + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (abms[i] != NULL && abms[i]->funcs != NULL) + abms[i]->funcs->abm_init(abms[i], backlight, user_level); + } + + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ + if (dc->res_pool->dio && dc->res_pool->dio->funcs->mem_pwr_ctrl) + dc->res_pool->dio->funcs->mem_pwr_ctrl(dc->res_pool->dio, false); + + if (!dc->debug.disable_clock_gate) { + /* enable all DCN clock gating */ + REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); + + REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); + } + + dcn401_setup_hpo_hw_control(hws, true); + + if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks) + dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub); + + if (dc->clk_mgr && dc->clk_mgr->funcs && dc->clk_mgr->funcs->notify_wm_ranges) + dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr); + + if (dc->res_pool->hubbub->funcs->force_pstate_change_control) + dc->res_pool->hubbub->funcs->force_pstate_change_control( + dc->res_pool->hubbub, false, false); + + if (dc->res_pool->hubbub->funcs->init_crb) + dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); + + if (dc->res_pool->hubbub->funcs->set_request_limit && + dc->clk_mgr && dc->clk_mgr->bw_params && + dc->config.sdpif_request_limit_words_per_umc > 0) + dc->res_pool->hubbub->funcs->set_request_limit(dc->res_pool->hubbub, + dc->clk_mgr->bw_params->num_channels, + dc->config.sdpif_request_limit_words_per_umc); + + // Get DMCUB capabilities + if (dc->ctx->dmub_srv) { + dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv); + dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr; + dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0; + dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; + + /* sw and fw FAMS versions must match for support */ + dc->debug.fams2_config.bits.enable &= + dc->caps.dmub_caps.fams_ver == dc->debug.fams_version.ver; + dchub_ref_freq_changed = + res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000 != current_dchub_ref_freq; + + if ((!dc->debug.fams2_config.bits.enable || dchub_ref_freq_changed) && + dc->res_pool->funcs->update_bw_bounding_box && + dc->clk_mgr && dc->clk_mgr->bw_params) { + /* update bounding box if FAMS2 disabled, or if dchub clk has changed */ + dc->res_pool->funcs->update_bw_bounding_box(dc, dc->clk_mgr->bw_params); + } + } + if (dc->res_pool->pg_cntl) { + if (dc->res_pool->pg_cntl->funcs->init_pg_status) + dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl); + } + print_pg_status(dc, __func__, ": after init_pg_status"); +} + +void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) +{ + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct mpcc_blnd_cfg blnd_cfg = {0}; + bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha; + int mpcc_id; + struct mpcc *new_mpcc; + struct mpc *mpc = dc->res_pool->mpc; + struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); + + + blnd_cfg.overlap_only = false; + blnd_cfg.global_gain = 0xfff; + + if (per_pixel_alpha) { + blnd_cfg.pre_multiplied_alpha = pipe_ctx->plane_state->pre_multiplied_alpha; + if (pipe_ctx->plane_state->global_alpha) { + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN; + blnd_cfg.global_gain = pipe_ctx->plane_state->global_alpha_value; + } else { + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; + } + } else { + blnd_cfg.pre_multiplied_alpha = false; + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA; + } + + if (pipe_ctx->plane_state->global_alpha) + blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value; + else + blnd_cfg.global_alpha = 0xfff; + + blnd_cfg.background_color_bpc = 4; + blnd_cfg.bottom_gain_mode = 0; + blnd_cfg.top_gain = 0x1f000; + blnd_cfg.bottom_inside_gain = 0x1f000; + blnd_cfg.bottom_outside_gain = 0x1f000; + + if (pipe_ctx->plane_state->format + == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA) + blnd_cfg.pre_multiplied_alpha = false; + + /* + * TODO: remove hack + * Note: currently there is a bug in init_hw such that + * on resume from hibernate, BIOS sets up MPCC0, and + * we do mpcc_remove but the mpcc cannot go to idle + * after remove. This cause us to pick mpcc1 here, + * which causes a pstate hang for yet unknown reason. + */ + mpcc_id = hubp->inst; + + /* If there is no full update, don't need to touch MPC tree*/ + if (!pipe_ctx->plane_state->update_flags.bits.full_update && + !pipe_ctx->update_flags.bits.mpcc) { + mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); + return; + } + + /* check if this MPCC is already being used */ + new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id); + /* remove MPCC if being used */ + if (new_mpcc != NULL) + mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc); + else + if (dc->debug.sanity_checks) + mpc->funcs->assert_mpcc_idle_before_connect( + dc->res_pool->mpc, mpcc_id); + + /* Call MPC to insert new plane */ + new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc, + mpc_tree_params, + &blnd_cfg, + NULL, + NULL, + hubp->inst, + mpcc_id); + dc->hwss.update_visual_confirm_color(dc, pipe_ctx, mpcc_id); + + ASSERT(new_mpcc != NULL); + hubp->opp_id = pipe_ctx->stream_res.opp->inst; + hubp->mpcc_id = mpcc_id; +} + +void dcn42_program_cm_hist( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) +{ + struct dpp *dpp = pipe_ctx->plane_res.dpp; + + if (dpp && dpp->funcs->dpp_cm_hist_control) + dpp->funcs->dpp_cm_hist_control(dpp, + plane_state->cm_hist_control, plane_state->color_space); +} + +static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) +{ + if (mpc->funcs->rmcm.power_on_shaper_3dlut && + mpc->funcs->rmcm.fl_3dlut_configure && + hubp->funcs->hubp_program_3dlut_fl_config) + return true; + + return false; +} + +bool dcn42_program_rmcm_luts( + struct hubp *hubp, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_cm *cm, + struct mpc *mpc, + int mpcc_id) +{ + struct dpp *dpp_base = pipe_ctx->plane_res.dpp; + union mcm_lut_params m_lut_params = {0}; + + struct dc *dc = hubp->ctx->dc; + struct mpc_fl_3dlut_config mpc_fl_config; + + struct dc_stream_state *stream = pipe_ctx->stream; + bool bypass_rmcm_shaper = false; + // true->false when it can be allocated at DI time + struct dc_rmcm_3dlut *rmcm_3dlut = dc_stream_get_3dlut_for_stream(dc, stream, false); + + bool lut_bank_a = true; // TODO get from HW + + //check to see current pipe is part of a stream with allocated rmcm 3dlut + if (!rmcm_3dlut) + return false; + + /* Shaper */ + if (cm->flags.bits.shaper_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + + if (cm->shaper_func.type == TF_TYPE_HWPWL) { + m_lut_params.pwl = &cm->shaper_func.pwl; + } else if (cm->shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) { + ASSERT(false); + cm_helper_translate_curve_to_hw_format( + dc->ctx, + &cm->shaper_func, + &dpp_base->shaper_params, true); + m_lut_params.pwl = &dpp_base->shaper_params; + } + if (m_lut_params.pwl) { + if (mpc->funcs->rmcm.populate_lut) + mpc->funcs->rmcm.populate_lut(mpc, m_lut_params, lut_bank_a, mpcc_id); + if (mpc->funcs->rmcm.program_lut_mode) + mpc->funcs->rmcm.program_lut_mode(mpc, !bypass_rmcm_shaper, lut_bank_a, mpcc_id); + } else { + //RMCM 3dlut won't work without its shaper + return false; + } + } + + /* 3DLUT */ + if (!cm->flags.bits.lut3d_dma_enable) { + memset(&m_lut_params, 0, sizeof(m_lut_params)); + // Don't know what to do in this case. + } else { + if (!dc_is_rmcm_3dlut_supported(hubp, mpc)) + return false; + + //seems to be only for the MCM + mpc_fl_config.enabled = cm->flags.bits.lut3d_enable; + mpc_fl_config.size = cm->lut3d_dma.size; + mpc_fl_config.select_lut_bank_a = lut_bank_a; + mpc_fl_config.bit_depth = 0; + mpc_fl_config.hubp_index = hubp->inst; + mpc_fl_config.bias = cm->lut3d_dma.bias; + mpc_fl_config.scale = cm->lut3d_dma.scale; + + //1. power down the block + mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, false); + + //2. program RMCM - 3dlut reg programming + mpc->funcs->rmcm.fl_3dlut_configure(mpc, &mpc_fl_config, mpcc_id); + + /* HUBP */ + if (hubp->funcs->hubp_program_3dlut_fl_config) + hubp->funcs->hubp_program_3dlut_fl_config(hubp, &cm->lut3d_dma); + + if (hubp->funcs->hubp_program_3dlut_fl_addr) + hubp->funcs->hubp_program_3dlut_fl_addr(hubp, &cm->lut3d_dma.addr); + + //3. power on the block + mpc->funcs->rmcm.power_on_shaper_3dlut(mpc, mpcc_id, true); + } + + return true; +} + +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state) +{ + struct dc *dc = pipe_ctx->plane_res.hubp->ctx->dc; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + const struct dc_plane_cm *cm = &plane_state->cm; + struct mpc *mpc = dc->res_pool->mpc; + int mpcc_id = hubp->inst; + bool result; + + /* MCM */ + result = dcn401_set_mcm_luts(pipe_ctx, plane_state); + + /* RMCM */ + if (cm->flags.bits.rmcm_enable && cm->flags.bits.lut3d_dma_enable) { + /* TODO - move RMCM to its own block */ + dcn42_program_rmcm_luts( + hubp, + pipe_ctx, + cm, + mpc, + mpcc_id); + } + + return result; +} +void dcn42_hardware_release(struct dc *dc) +{ + dcn35_hardware_release(dc); + +} +static int count_active_streams(const struct dc *dc) +{ + int i, count = 0; + + for (i = 0; i < dc->current_state->stream_count; ++i) { + struct dc_stream_state *stream = dc->current_state->streams[i]; + + if (stream && (!stream->dpms_off || dc->config.disable_ips_in_dpms_off)) + count += 1; + } + + return count; +} + +void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state) +{ + bool hpo_frl_stream_enc_acquired = false; + bool hpo_dp_stream_enc_acquired = false; + int i = 0, j = 0; + + memset(update_state, 0, sizeof(struct pg_block_update)); + + update_state->pg_res_update[PG_DIO] = true; + + for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && + dc->res_pool->hpo_dp_stream_enc[i]) { + hpo_dp_stream_enc_acquired = true; + break; + } + } + + if (!hpo_frl_stream_enc_acquired && !hpo_dp_stream_enc_acquired) + update_state->pg_res_update[PG_HPO] = true; + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) + update_state->pg_pipe_res_update[j][i] = true; + + if (!pipe_ctx) + continue; + + if (pipe_ctx->plane_res.hubp) + update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false; + + if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp) + update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false; + + if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp) + update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false; + + if (pipe_ctx->stream_res.dsc) { + update_state->pg_pipe_res_update[PG_DSC][pipe_ctx->stream_res.dsc->inst] = false; + if (dc->caps.sequential_ono) { + update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->stream_res.dsc->inst] = false; + update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->stream_res.dsc->inst] = false; + } + } + if (pipe_ctx->stream_res.opp) + update_state->pg_pipe_res_update[PG_OPP][pipe_ctx->stream_res.opp->inst] = false; + + if (pipe_ctx->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[PG_DPSTREAM][pipe_ctx->stream_res.hpo_dp_stream_enc->inst] = false; + + if (pipe_ctx->link_res.dio_link_enc) { + update_state->pg_res_update[PG_DIO] = false; + } + if (pipe_ctx->link_res.hpo_dp_link_enc) { + update_state->pg_res_update[PG_HPO] = false; + } + } + + + for (i = 0; i < dc->link_count; i++) { + update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; + if (dc->links[i]->type != dc_connection_none) + update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = false; + } + + /*domain24 controls all the otg, mpc, opp, as long as one otg is still up, avoid enabling OTG PG*/ + for (i = 0; i < dc->res_pool->timing_generator_count; i++) { + struct timing_generator *tg = dc->res_pool->timing_generators[i]; + if (tg && tg->funcs->is_tg_enabled(tg)) { + update_state->pg_pipe_res_update[PG_OPTC][i] = false; + } else { + // Update pg_pipe_res_enable state + if (dc->res_pool->pg_cntl->funcs->optc_pg_control) + dc->res_pool->pg_cntl->funcs->optc_pg_control(dc->res_pool->pg_cntl, i, false); + } + } + +} + +void dcn42_prepare_bandwidth( + struct dc *dc, + struct dc_state *context) +{ + + struct pg_block_update pg_update_state; + + if (dc->hwss.calc_blocks_to_ungate) { + dc->hwss.calc_blocks_to_ungate(dc, context, &pg_update_state); + + if (dc->hwss.root_clock_control) + dc->hwss.root_clock_control(dc, &pg_update_state, true); + /*power up required HW block*/ + if (dc->hwss.hw_block_power_up) + dc->hwss.hw_block_power_up(dc, &pg_update_state); + } + + dcn401_prepare_bandwidth(dc, context); +} + +void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context) +{ + struct pg_block_update pg_update_state; + + print_pg_status(dc, __func__, ": before rcg and power up"); + + dcn401_optimize_bandwidth(dc, context); + + if (dc->hwss.calc_blocks_to_gate) { + dc->hwss.calc_blocks_to_gate(dc, context, &pg_update_state); + /*try to power down unused block*/ + if (dc->hwss.hw_block_power_down) + dc->hwss.hw_block_power_down(dc, &pg_update_state); + + if (dc->hwss.root_clock_control) + dc->hwss.root_clock_control(dc, &pg_update_state, false); + } + + print_pg_status(dc, __func__, ": after rcg and power up"); + +} + +void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state) +{ + bool hpo_dp_stream_enc_acquired = false; + int i = 0, j = 0; + + memset(update_state, 0, sizeof(struct pg_block_update)); + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *cur_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; + + if (cur_pipe == NULL || new_pipe == NULL) + continue; + + if ((!cur_pipe->plane_state && new_pipe->plane_state) || + (!cur_pipe->stream && new_pipe->stream) || + (cur_pipe->stream != new_pipe->stream && new_pipe->stream)) { + // New pipe addition + for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) { + if (j == PG_HUBP && new_pipe->plane_res.hubp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true; + + if (j == PG_DPP && new_pipe->plane_res.dpp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true; + + if (j == PG_MPCC && new_pipe->plane_res.dpp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true; + + if (j == PG_DSC && new_pipe->stream_res.dsc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true; + + if (j == PG_OPP && new_pipe->stream_res.opp) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true; + + if (j == PG_OPTC && new_pipe->stream_res.tg) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true; + + if (j == PG_DPSTREAM && new_pipe->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true; + } + } else if (cur_pipe->plane_state == new_pipe->plane_state || + cur_pipe == new_pipe) { + //unchanged pipes + for (j = 0; j < PG_HW_PIPE_RESOURCES_NUM_ELEMENT; j++) { + if (j == PG_HUBP && + cur_pipe->plane_res.hubp != new_pipe->plane_res.hubp && + new_pipe->plane_res.hubp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.hubp->inst] = true; + + if (j == PG_DPP && + cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp && + new_pipe->plane_res.dpp) + update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true; + + if (j == PG_OPP && + cur_pipe->stream_res.opp != new_pipe->stream_res.opp && + new_pipe->stream_res.opp) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.opp->inst] = true; + + if (j == PG_DSC && + cur_pipe->stream_res.dsc != new_pipe->stream_res.dsc && + new_pipe->stream_res.dsc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.dsc->inst] = true; + + if (j == PG_OPTC && + cur_pipe->stream_res.tg != new_pipe->stream_res.tg && + new_pipe->stream_res.tg) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.tg->inst] = true; + + if (j == PG_DPSTREAM && + cur_pipe->stream_res.hpo_dp_stream_enc != new_pipe->stream_res.hpo_dp_stream_enc && + new_pipe->stream_res.hpo_dp_stream_enc) + update_state->pg_pipe_res_update[j][new_pipe->stream_res.hpo_dp_stream_enc->inst] = true; + } + } + } + + for (i = 0; i < dc->link_count; i++) + if (dc->links[i]->type != dc_connection_none) + update_state->pg_pipe_res_update[PG_PHYSYMCLK][dc->links[i]->link_enc_hw_inst] = true; + + for (i = 0; i < dc->res_pool->stream_enc_count; i++) { + if (dc->current_state->res_ctx.is_stream_enc_acquired[i]) { + update_state->pg_res_update[PG_DIO] = true; + break; + } + } + for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i] && + dc->res_pool->hpo_dp_stream_enc[i]) { + hpo_dp_stream_enc_acquired = true; + break; + } + } + + if (hpo_dp_stream_enc_acquired) + update_state->pg_res_update[PG_HPO] = true; + + if (count_active_streams(dc) > 0) { + update_state->pg_res_update[PG_DCCG] = true; + update_state->pg_res_update[PG_DCIO] = true; + update_state->pg_res_update[PG_DCHUBBUB] = true; + update_state->pg_res_update[PG_DCHVM] = true; + update_state->pg_res_update[PG_DCOH] = true; + } +} +/** + * dcn42_hw_block_power_down() - power down sequence + * + * The following sequence describes the ON-OFF (ONO) for power down: + * + * ONO Region 4, DCPG 25: hpo + * ONO Region 11, DCPG 3: dchubp3, dpp3 + * ONO Region 9, DCPG 2: dchubp2, dpp2 + * ONO Region 7, DCPG 1: dchubp1, dpp1 + * ONO Region 5, DCPG 0: dchubp0, dpp0 + * ONO Region 2, DCPG 23: dchubbub, dchububmem, dchvm + * ONO Region 12, DCPG 19: dsc3 + * ONO Region 10, DCPG 18: dsc2 + * ONO Region 8, DCPG 17: dsc1 + * ONO Region 6, DCPG 16: dsc0 + * ONO Region 3, DCPG 24: mpc, opp, optc, dwb + * ONO Region 1, DCPG 26: dio + * ONO Region 0, DCPG 22: dccg dcio dcoh - SKIPPED + * + * No seuential ONO power up/down order for DCN42 + * Driver PG should only be limited to DCHUBP/DPP, DSC, HPO and DIO, so further optimization can be done + * + * @dc: Current DC state + * @update_state: update PG sequence states for HW block + */ + void dcn42_hw_block_power_down(struct dc *dc, + struct pg_block_update *update_state) +{ + int i = 0; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + bool block_disabled = true; + + if (!pg_cntl) + return; + if (dc->debug.ignore_pg) + return; + + if (update_state->pg_res_update[PG_HPO]) { + if (pg_cntl->funcs->hpo_pg_control) + pg_cntl->funcs->hpo_pg_control(pg_cntl, false); + } + + for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (pg_cntl->funcs->hubp_dpp_pg_control) + pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false); + } + } + + if (update_state->pg_res_update[PG_DCHUBBUB]) { + if (pg_cntl->funcs->mem_pg_control) + pg_cntl->funcs->mem_pg_control(pg_cntl, false); + } + + for (i = dc->res_pool->res_cap->num_dsc-1; i >= 0; i--) { + if (update_state->pg_pipe_res_update[PG_DSC][i]) { + if (pg_cntl->funcs->dsc_pg_control) + pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false); + } + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (!update_state->pg_pipe_res_update[PG_MPCC][i] || + !update_state->pg_pipe_res_update[PG_OPP][i] || + !update_state->pg_pipe_res_update[PG_OPTC][i]) { + block_disabled = false; + break; + } + } + + if (block_disabled) { + if (pg_cntl->funcs->plane_otg_pg_control) + pg_cntl->funcs->plane_otg_pg_control(pg_cntl, false); + } + + if (update_state->pg_res_update[PG_DIO]) { + if (pg_cntl->funcs->dio_pg_control) + pg_cntl->funcs->dio_pg_control(pg_cntl, false); + } + + if (update_state->pg_res_update[PG_DCCG] && + update_state->pg_res_update[PG_DCIO] && + update_state->pg_res_update[PG_DCOH]) { + // Driver PG should not power down DCCG, DCIO, DCOH. This is handled by IPS. + if (pg_cntl->funcs->io_clk_pg_control) + pg_cntl->funcs->io_clk_pg_control(pg_cntl, false); + } +} + +/** + * dcn42_hw_block_power_up() - power up sequence + * + * The following sequence describes the ON-OFF (ONO) for power up: + * + * ONO Region 0, DCPG 22: dccg dcio dcoh + * ONO Region 1, DCPG 26: dio + * ONO Region 3, DCPG 24: mpc, opp, optc, dwb + * ONO Region 6, DCPG 16: dsc0 + * ONO Region 8, DCPG 17: dsc1 + * ONO Region 10, DCPG 18: dsc2 + * ONO Region 12, DCPG 19: dsc3 + * ONO Region 2, DCPG 23: dchubbub, dchububmem, dchvm + * ONO Region 5, DCPG 0: dchubp0, dpp0 + * ONO Region 7, DCPG 1: dchubp1, dpp1 + * ONO Region 9, DCPG 2: dchubp2, dpp2 + * ONO Region 11, DCPG 3: dchubp3, dpp3 + * ONO Region 4, DCPG 25: hpo + * + * No sequential power up/down ordering for DCN42 + * + * @dc: Current DC state + * @update_state: update PG sequence states for HW block + */ +void dcn42_hw_block_power_up(struct dc *dc, + struct pg_block_update *update_state) +{ + int i = 0; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + bool block_enabled = false; + + if (!pg_cntl) + return; + if (dc->debug.ignore_pg) + return; + + if (update_state->pg_res_update[PG_DCCG] || + update_state->pg_res_update[PG_DCIO] || + update_state->pg_res_update[PG_DCOH]) { + if (pg_cntl->funcs->io_clk_pg_control) + pg_cntl->funcs->io_clk_pg_control(pg_cntl, true); + } + + if (update_state->pg_res_update[PG_DIO]) { + if (pg_cntl->funcs->dio_pg_control) + pg_cntl->funcs->dio_pg_control(pg_cntl, true); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_MPCC][i] || + update_state->pg_pipe_res_update[PG_OPP][i] || + update_state->pg_pipe_res_update[PG_OPTC][i]) { + block_enabled = true; + break; + } + } + if (block_enabled) { + if (pg_cntl->funcs->plane_otg_pg_control) + pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true); + } + + for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + if (update_state->pg_pipe_res_update[PG_DSC][i]) { + if (pg_cntl->funcs->dsc_pg_control) + pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true); + } + } + + if (update_state->pg_res_update[PG_DCHUBBUB]) { + if (pg_cntl->funcs->mem_pg_control) + pg_cntl->funcs->mem_pg_control(pg_cntl, true); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (pg_cntl->funcs->hubp_dpp_pg_control) + pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true); + } + } + if (update_state->pg_res_update[PG_HPO]) { + if (pg_cntl->funcs->hpo_pg_control) + pg_cntl->funcs->hpo_pg_control(pg_cntl, true); + } +} +void dcn42_root_clock_control(struct dc *dc, + struct pg_block_update *update_state, bool power_on) +{ + int i = 0; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + + if (!pg_cntl) + return; + /*enable root clock first when power up*/ + if (power_on) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (dc->hwseq->funcs.dpp_root_clock_control) + dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on); + } + if (update_state->pg_pipe_res_update[PG_DPSTREAM][i]) + if (dc->hwseq->funcs.dpstream_root_clock_control) + dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on); + } + + for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) + if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i]) + if (dc->hwseq->funcs.physymclk_root_clock_control) + dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); + + } + for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + if (update_state->pg_pipe_res_update[PG_DSC][i]) { + if (power_on) { + if (dc->res_pool->dccg->funcs->enable_dsc) + dc->res_pool->dccg->funcs->enable_dsc(dc->res_pool->dccg, i); + } else { + if (dc->res_pool->dccg->funcs->disable_dsc) + dc->res_pool->dccg->funcs->disable_dsc(dc->res_pool->dccg, i); + } + } + } + /*disable root clock first when power down*/ + if (!power_on) { + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (update_state->pg_pipe_res_update[PG_HUBP][i] && + update_state->pg_pipe_res_update[PG_DPP][i]) { + if (dc->hwseq->funcs.dpp_root_clock_control) + dc->hwseq->funcs.dpp_root_clock_control(dc->hwseq, i, power_on); + } + if (update_state->pg_pipe_res_update[PG_DPSTREAM][i]) + if (dc->hwseq->funcs.dpstream_root_clock_control) + dc->hwseq->funcs.dpstream_root_clock_control(dc->hwseq, i, power_on); + } + + for (i = 0; i < dc->res_pool->dig_link_enc_count; i++) + if (update_state->pg_pipe_res_update[PG_PHYSYMCLK][i]) + if (dc->hwseq->funcs.physymclk_root_clock_control) + dc->hwseq->funcs.physymclk_root_clock_control(dc->hwseq, i, power_on); + + } +} +void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) +{ + struct crtc_stereo_flags flags = { 0 }; + struct dc_stream_state *stream = pipe_ctx->stream; + + dcn10_config_stereo_parameters(stream, &flags); + + pipe_ctx->stream_res.opp->funcs->opp_program_stereo( + pipe_ctx->stream_res.opp, + flags.PROGRAM_STEREO == 1, + &stream->timing); + + pipe_ctx->stream_res.tg->funcs->program_stereo( + pipe_ctx->stream_res.tg, + &stream->timing, + &flags); + + return; +} +void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock) +{ + + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + + if (!dc->ctx || !dc->ctx->dmub_srv) + return; + + /* Use helper to check PSR/Replay for all streams in context */ + + if (!dc->debug.fams2_config.bits.enable && !dc_dmub_srv_is_cursor_offload_enabled(dc) + && !dmub_hw_lock_mgr_does_context_require_lock(dc, context)) + return; + + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); +} + +void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params) +{ + struct dc *dc = params->dmub_hw_control_lock_fast_params.dc; + bool lock = params->dmub_hw_control_lock_fast_params.lock; + + /* Use helper to check PSR/Replay for the given stream in fast path */ + if (params->dmub_hw_control_lock_fast_params.is_required) { + union dmub_inbox0_cmd_lock_hw hw_lock_cmd = { 0 }; + hw_lock_cmd.bits.command_code = DMUB_INBOX0_CMD__HW_LOCK; + hw_lock_cmd.bits.hw_lock_client = HW_LOCK_CLIENT_DRIVER; + hw_lock_cmd.bits.lock = lock; + hw_lock_cmd.bits.should_release = !lock; + dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd); + } +} + +/* In headless boot cases, DIG may be turned + * on which causes HW/SW discrepancies. + * To avoid this, power down hardware on boot + * if DIG is turned on + */ +void dcn42_power_down_on_boot(struct dc *dc) +{ + struct dc_link *edp_links[MAX_NUM_EDP]; + struct dc_link *edp_link = NULL; + int edp_num; + int i = 0; + + dc_get_edp_links(dc, edp_links, &edp_num); + if (edp_num) + edp_link = edp_links[0]; + + if (edp_link && edp_link->link_enc->funcs->is_dig_enabled && + edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && + dc->hwseq->funcs.edp_backlight_control && + dc->hwseq->funcs.power_down && + dc->hwss.edp_power_control) { + dc->hwseq->funcs.edp_backlight_control(edp_link, false); + dc->hwseq->funcs.power_down(dc); + dc->hwss.edp_power_control(edp_link, false); + } else { + for (i = 0; i < dc->link_count; i++) { + struct dc_link *link = dc->links[i]; + + if (link->link_enc && link->link_enc->funcs->is_dig_enabled && + link->link_enc->funcs->is_dig_enabled(link->link_enc) && + dc->hwseq->funcs.power_down) { + dc->hwseq->funcs.power_down(dc); + break; + } + + } + } + + /* + * Call update_clocks with empty context + * to send DISPLAY_OFF + * Otherwise DISPLAY_OFF may not be asserted + */ + if (dc->clk_mgr->funcs->set_low_power_state) + dc->clk_mgr->funcs->set_low_power_state(dc->clk_mgr); +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h new file mode 100644 index 0000000000000..c4cfeed45b190 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DC_HWSS_DCN42_H__ +#define __DC_HWSS_DCN42_H__ + +#include "dc.h" +#include "hw_sequencer_private.h" + +void dcn42_init_hw(struct dc *dc); +void dcn42_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx); + +void dcn42_program_cm_hist( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); + +bool dcn42_set_mcm_luts(struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); + +bool dcn42_program_rmcm_luts( + struct hubp *hubp, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_cm *cm, + struct mpc *mpc, + int mpcc_id); +void dcn42_hardware_release(struct dc *dc); + +void dcn42_prepare_bandwidth( + struct dc *dc, + struct dc_state *context); +void dcn42_optimize_bandwidth(struct dc *dc, struct dc_state *context); +void dcn42_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state); +void dcn42_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context, + struct pg_block_update *update_state); +void dcn42_hw_block_power_down(struct dc *dc, + struct pg_block_update *update_state); +void dcn42_hw_block_power_up(struct dc *dc, + struct pg_block_update *update_state); +void dcn42_root_clock_control(struct dc *dc, + struct pg_block_update *update_state, bool power_on); +void dcn42_dmub_hw_control_lock(struct dc *dc, struct dc_state *context, bool lock); +void dcn42_dmub_hw_control_lock_fast(union block_sequence_params *params); +void dcn42_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc); +void dcn42_power_down_on_boot(struct dc *dc); +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c new file mode 100644 index 0000000000000..b324a2195e8a6 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dce110/dce110_hwseq.h" +#include "dcn10/dcn10_hwseq.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn21/dcn21_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dcn31/dcn31_hwseq.h" +#include "dcn32/dcn32_hwseq.h" +#include "dcn314/dcn314_hwseq.h" +#include "dcn35/dcn35_hwseq.h" +#include "dcn401/dcn401_hwseq.h" +#include "dcn42/dcn42_hwseq.h" +#include "dcn42_init.h" + +static const struct hw_sequencer_funcs dcn42_funcs = { + .program_gamut_remap = dcn401_program_gamut_remap, + .init_hw = dcn42_init_hw, + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .power_down_on_boot = dcn42_power_down_on_boot, + .apply_ctx_for_surface = NULL, + .program_front_end_for_ctx = dcn401_program_front_end_for_ctx, + .clear_surface_dcc_and_tiling = dcn10_reset_surface_dcc_and_tiling, + .wait_for_pending_cleared = dcn10_wait_for_pending_cleared, + .post_unlock_program_front_end = dcn401_post_unlock_program_front_end, + .update_plane_addr = dcn20_update_plane_addr, + .update_dchub = dcn10_update_dchub, + .update_pending_status = dcn10_update_pending_status, + .program_output_csc = dcn20_program_output_csc, + .trigger_3dlut_dma_load = dcn401_trigger_3dlut_dma_load, + .enable_accelerated_mode = dce110_enable_accelerated_mode, + .enable_timing_synchronization = dcn10_enable_timing_synchronization, + .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, + .update_info_frame = dcn31_update_info_frame, + .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, + .enable_stream = dcn401_enable_stream, + .disable_stream = dce110_disable_stream, + .unblank_stream = dcn401_unblank_stream, + .blank_stream = dce110_blank_stream, + .enable_audio_stream = dce110_enable_audio_stream, + .disable_audio_stream = dce110_disable_audio_stream, + .disable_plane = dcn35_disable_plane, + .pipe_control_lock = dcn20_pipe_control_lock, + .interdependent_update_lock = dcn401_interdependent_update_lock, + .cursor_lock = dcn10_cursor_lock, + .prepare_bandwidth = dcn42_prepare_bandwidth, + .optimize_bandwidth = dcn42_optimize_bandwidth, + .update_bandwidth = dcn401_update_bandwidth, + .set_drr = dcn35_set_drr, + .get_position = dcn10_get_position, + .set_static_screen_control = dcn35_set_static_screen_control, + .setup_stereo = dcn42_setup_stereo, + .set_avmute = dcn30_set_avmute, + .log_hw_state = dcn10_log_hw_state, + .get_hw_state = dcn10_get_hw_state, + .clear_status_bits = dcn10_clear_status_bits, + .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .edp_backlight_control = dce110_edp_backlight_control, + .edp_power_control = dce110_edp_power_control, + .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, + .edp_wait_for_T12 = dce110_edp_wait_for_T12, + .set_cursor_position = dcn401_set_cursor_position, + .set_cursor_attribute = dcn10_set_cursor_attribute, + .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, + .abort_cursor_offload_update = dcn35_abort_cursor_offload_update, + .begin_cursor_offload_update = dcn35_begin_cursor_offload_update, + .commit_cursor_offload_update = dcn35_commit_cursor_offload_update, + .update_cursor_offload_pipe = dcn401_update_cursor_offload_pipe, + .notify_cursor_offload_drr_update = dcn35_notify_cursor_offload_drr_update, + .program_cursor_offload_now = dcn35_program_cursor_offload_now, + .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, + .set_clock = dcn10_set_clock, + .get_clock = dcn10_get_clock, + .program_triplebuffer = dcn20_program_triple_buffer, + .enable_writeback = dcn30_enable_writeback, + .disable_writeback = dcn30_disable_writeback, + .update_writeback = dcn30_update_writeback, + .dmdata_status_done = dcn20_dmdata_status_done, + .program_dmdata_engine = dcn30_program_dmdata_engine, + .set_dmdata_attributes = dcn20_set_dmdata_attributes, + .init_sys_ctx = dcn31_init_sys_ctx, + .init_vm_ctx = dcn20_init_vm_ctx, + .set_flip_control_gsl = dcn20_set_flip_control_gsl, + .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, + .calc_vupdate_position = dcn10_calc_vupdate_position, + .apply_idle_power_optimizations = dcn35_apply_idle_power_optimizations, + .does_plane_fit_in_mall = NULL, + .set_backlight_level = dcn31_set_backlight_level, + .set_abm_immediate_disable = dcn21_set_abm_immediate_disable, + .hardware_release = dcn42_hardware_release, + .set_pipe = dcn21_set_pipe, + .enable_lvds_link_output = dce110_enable_lvds_link_output, + .enable_tmds_link_output = dce110_enable_tmds_link_output, + .enable_dp_link_output = dce110_enable_dp_link_output, + .disable_link_output = dcn401_disable_link_output, + .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, + .optimize_pwr_state = dcn21_optimize_pwr_state, + .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, + .get_dcc_en_bits = dcn10_get_dcc_en_bits, + .enable_phantom_streams = dcn32_enable_phantom_streams, + .disable_phantom_streams = dcn32_disable_phantom_streams, + .update_visual_confirm_color = dcn10_update_visual_confirm_color, + .update_phantom_vp_position = dcn32_update_phantom_vp_position, + .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, + .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation, + .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, + .dmub_hw_control_lock = dcn42_dmub_hw_control_lock, + .fams2_update_config = dcn401_fams2_update_config, + .dmub_hw_control_lock_fast = dcn42_dmub_hw_control_lock_fast, + .program_outstanding_updates = dcn401_program_outstanding_updates, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, + .detect_pipe_changes = dcn401_detect_pipe_changes, + .enable_plane = dcn35_enable_plane, + .update_dchubp_dpp = dcn20_update_dchubp_dpp, + .post_unlock_reset_opp = dcn20_post_unlock_reset_opp, + .get_underflow_debug_data = dcn30_get_underflow_debug_data, + // Driver PG + .hw_block_power_up = dcn42_hw_block_power_up, + .hw_block_power_down = dcn42_hw_block_power_down, + .root_clock_control = dcn42_root_clock_control, + .calc_blocks_to_gate = dcn42_calc_blocks_to_gate, + .calc_blocks_to_ungate = dcn42_calc_blocks_to_ungate, + +}; + +static const struct hwseq_private_funcs dcn42_private_funcs = { + .init_pipes = dcn35_init_pipes, + .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, + .update_mpcc = dcn42_update_mpcc, + .set_input_transfer_func = dcn32_set_input_transfer_func, + .set_output_transfer_func = dcn401_set_output_transfer_func, + .power_down = dce110_power_down, + .enable_display_power_gating = dcn10_dummy_display_power_gating, + .blank_pixel_data = dcn20_blank_pixel_data, + .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap, + .enable_stream_timing = dcn401_enable_stream_timing, + .edp_backlight_control = dce110_edp_backlight_control, + .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, + .did_underflow_occur = dcn10_did_underflow_occur, + .init_blank = dcn32_init_blank, + .disable_vga = dcn20_disable_vga, + .bios_golden_init = dcn10_bios_golden_init, + .plane_atomic_disable = dcn35_plane_atomic_disable, + .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, + .update_odm = dcn401_update_odm, + .dsc_pg_status = dcn32_dsc_pg_status, + .set_hdr_multiplier = dcn10_set_hdr_multiplier, + .wait_for_blank_complete = dcn20_wait_for_blank_complete, + .set_mcm_luts = dcn42_set_mcm_luts, + .program_mall_pipe_config = dcn32_program_mall_pipe_config, + .update_mall_sel = dcn32_update_mall_sel, + .calculate_dccg_k1_k2_values = NULL, + .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, + .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe, + .populate_mcm_luts = NULL, + .perform_3dlut_wa_unlock = dcn401_perform_3dlut_wa_unlock, + .program_cm_hist = dcn42_program_cm_hist, + .dpp_root_clock_control = dcn35_dpp_root_clock_control, + .dpstream_root_clock_control = dcn35_dpstream_root_clock_control, + .physymclk_root_clock_control = dcn35_physymclk_root_clock_control, + .resync_fifo_dccg_dio = dcn314_resync_fifo_dccg_dio, + .wait_for_pipe_update_if_needed = dcn10_wait_for_pipe_update_if_needed, + .set_wait_for_update_needed_for_pipe = dcn10_set_wait_for_update_needed_for_pipe, +}; + +void dcn42_hw_sequencer_init_functions(struct dc *dc) +{ + dc->hwss = dcn42_funcs; + dc->hwseq->funcs = dcn42_private_funcs; + +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h new file mode 100644 index 0000000000000..f66eb752eeebf --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_init.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DC_DCN42_INIT_H__ +#define __DC_DCN42_INIT_H__ + +struct dc; + +void dcn42_hw_sequencer_init_functions(struct dc *dc); + +#endif /* __DC_DCN401_INIT_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 8ed9eea40c564..98abe0d2d30f6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -52,7 +52,7 @@ struct drr_params; struct dc_underflow_debug_data; struct dsc_optc_config; struct vm_system_aperture_param; - +struct memory_qos; struct subvp_pipe_control_lock_fast_params { struct dc *dc; bool lock; @@ -174,6 +174,12 @@ struct program_mcache_id_and_split_coordinate { struct dml2_hubp_pipe_mcache_regs *mcache_regs; }; +struct control_cm_hist_params { + struct dpp *dpp; + struct cm_hist_control cm_hist_control; + enum dc_color_space color_space; +}; + struct program_cursor_update_now_params { struct dc *dc; struct pipe_ctx *pipe_ctx; @@ -755,6 +761,7 @@ union block_sequence_params { struct dmub_hw_control_lock_fast_params dmub_hw_control_lock_fast_params; struct program_surface_config_params program_surface_config_params; struct program_mcache_id_and_split_coordinate program_mcache_id_and_split_coordinate; + struct control_cm_hist_params control_cm_hist_params; struct program_cursor_update_now_params program_cursor_update_now_params; struct hubp_wait_pipe_read_start_params hubp_wait_pipe_read_start_params; struct apply_update_flags_for_phantom_params apply_update_flags_for_phantom_params; @@ -879,6 +886,7 @@ enum block_sequence_func { DMUB_HW_CONTROL_LOCK_FAST, HUBP_PROGRAM_SURFACE_CONFIG, HUBP_PROGRAM_MCACHE_ID, + DPP_PROGRAM_CM_HIST, PROGRAM_CURSOR_UPDATE_NOW, HUBP_WAIT_PIPE_READ_START, HWS_APPLY_UPDATE_FLAGS_FOR_PHANTOM, @@ -1112,7 +1120,7 @@ struct hw_sequencer_funcs { void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id); - void (*trigger_3dlut_dma_load)(struct dc *dc, struct pipe_ctx *pipe_ctx); + void (*trigger_3dlut_dma_load)(struct pipe_ctx *pipe_ctx); /* VM Related */ int (*init_sys_ctx)(struct dce_hwseq *hws, @@ -1184,9 +1192,13 @@ struct hw_sequencer_funcs { const struct link_resource *link_res, enum clock_source_id clock_source, uint32_t pixel_clock); + void (*enable_analog_link_output)(struct dc_link *link, + uint32_t pixel_clock); void (*disable_link_output)(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal); + bool (*dac_load_detect)(struct dc_link *link); + void (*prepare_ddc)(struct dc_link *link); void (*get_dcc_en_bits)(struct dc *dc, int *dcc_en_bits); @@ -1287,6 +1299,17 @@ struct hw_sequencer_funcs { void (*get_underflow_debug_data)(const struct dc *dc, struct timing_generator *tg, struct dc_underflow_debug_data *out_data); + + /** + * measure_memory_qos - Measure memory QoS metrics + * @dc: DC structure + * @qos: Pointer to memory_qos struct to populate with measured values + * + * Populates the provided memory_qos struct with peak bandwidth, average bandwidth, + * max latency, min latency, and average latency from hardware performance counters. + */ + void (*measure_memory_qos)(struct dc *dc, struct memory_qos *qos); + }; void color_space_to_black_color( @@ -1342,6 +1365,10 @@ void get_dcc_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); +void get_refresh_rate_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); + void set_p_state_switch_method( struct dc *dc, struct dc_state *context, @@ -1400,6 +1427,8 @@ void hwss_program_surface_config(union block_sequence_params *params); void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *params); +void hwss_program_cm_hist(union block_sequence_params *params); + void hwss_set_odm_combine(union block_sequence_params *params); void hwss_set_odm_bypass(union block_sequence_params *params); @@ -1750,6 +1779,11 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s bool use_default_params, struct pipe_ctx *pipe_ctx); +void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state, + struct dpp *dpp, + struct cm_hist_control cm_hist_control, + enum dc_color_space color_space); + void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state, struct dc *dc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h index 406db231bc72a..8e3f54fb53fd6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h @@ -1,5 +1,5 @@ /* - * Copyright 2015 Advanced Micro Devices, Inc. + * Copyright 2015-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -222,6 +222,9 @@ struct hwseq_private_funcs { void (*wait_for_pipe_update_if_needed)(struct dc *dc, struct pipe_ctx *pipe_ctx, bool is_surface_update_only); void (*set_wait_for_update_needed_for_pipe)(struct dc *dc, struct pipe_ctx *pipe_ctx); void (*dc_ip_request_cntl)(struct dc *dc, bool enable); + void (*program_cm_hist)(struct dc *dc, + struct pipe_ctx *pipe_ctx, + const struct dc_plane_state *plane_state); }; struct dce_hwseq { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 5ed2cd3448040..0d59903c4a6bd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -35,6 +35,7 @@ #include "hubp.h" #include "mpc.h" #include "dwb.h" +#include "hw/dio.h" #include "mcif_wb.h" #include "panel_cntl.h" #include "dmub/inc/dmub_cmd.h" @@ -200,7 +201,6 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); - enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); @@ -213,6 +213,7 @@ struct resource_funcs { unsigned int index); void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); + void (*get_default_tiling_info)(struct dc_tiling_info *tiling_info); void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); /* * Get indicator of power from a context that went through full validation @@ -250,6 +251,7 @@ struct resource_pool { struct timing_generator *timing_generators[MAX_PIPES]; struct stream_encoder *stream_enc[MAX_PIPES * 2]; struct hubbub *hubbub; + struct dio *dio; struct mpc *mpc; struct pp_smu_funcs *pp_smu; struct dce_aux *engines[MAX_PIPES]; @@ -704,4 +706,12 @@ struct dc_bounding_box_max_clk { int max_phyclk_mhz; }; +struct memory_qos { + uint32_t peak_bw_mbps; + uint32_t avg_bw_mbps; + uint32_t max_latency_ns; + uint32_t min_latency_ns; + uint32_t avg_latency_ns; +}; + #endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 2c9a4a12bd8a7..21224fd6b36d6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2012-16 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -95,6 +96,26 @@ struct dcn301_clk_internal { uint32_t CLK1_CLK3_BYPASS_CNTL; //dcfclk bypass }; +struct dcn42_clk_internal { + int dummy; + uint32_t CLK8_CLK0_CURRENT_CNT; //dispclk + uint32_t CLK8_CLK1_CURRENT_CNT; //dppclk + uint32_t CLK8_CLK2_CURRENT_CNT; //dprefclk + uint32_t CLK8_CLK3_CURRENT_CNT; //dcfclk + uint32_t CLK8_CLK4_CURRENT_CNT; //dtbclk + uint32_t CLK8_CLK0_DS_CNTL; //dispclk deep_sleep_divider + uint32_t CLK8_CLK1_DS_CNTL; //dppclk deep_sleep_divider + uint32_t CLK8_CLK2_DS_CNTL; //dprefclk deep_sleep_divider + uint32_t CLK8_CLK3_DS_CNTL; //dcfclk deep_sleep_divider + uint32_t CLK8_CLK4_DS_CNTL; //dtbclk deep_sleep_divider + uint32_t CLK8_CLK0_BYPASS_CNTL; //dispclk bypass + uint32_t CLK8_CLK1_BYPASS_CNTL; //dppclk bypass + uint32_t CLK8_CLK2_BYPASS_CNTL; //dprefclk bypass + uint32_t CLK8_CLK3_BYPASS_CNTL; //dcfclk bypass + uint32_t CLK8_CLK4_BYPASS_CNTL; //dtbclk bypass + uint32_t CLK8_CLK_TICK_CNT__TIMER_THRESHOLD; +}; + /* Will these bw structures be ASIC specific? */ #define MAX_NUM_DPM_LVL 8 @@ -194,6 +215,7 @@ struct clk_state_registers_and_bypass { uint32_t dcfclk_bypass; uint32_t dprefclk_bypass; uint32_t dispclk_bypass; + uint32_t timer_threshold; }; struct rv1_clk_internal { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index bac8febad69a5..c69ccfcebeb5a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2018 Advanced Micro Devices, Inc. + * Copyright 2018-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -89,11 +90,6 @@ enum dentist_divider_range { .DPREFCLK_CNTL = mmDPREFCLK_CNTL, \ .DENTIST_DISPCLK_CNTL = mmDENTIST_DISPCLK_CNTL -#if defined(CONFIG_DRM_AMD_DC_SI) -#define CLK_COMMON_REG_LIST_DCE60_BASE() \ - SR(DENTIST_DISPCLK_CNTL) -#endif - #define CLK_COMMON_REG_LIST_DCN_BASE() \ SR(DENTIST_DISPCLK_CNTL) @@ -119,12 +115,6 @@ enum dentist_divider_range { CLK_SF(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_SI) -#define CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \ - CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ - CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) -#endif - #define CLK_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, mask_sh),\ CLK_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh) @@ -234,6 +224,45 @@ enum dentist_divider_range { #define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \ CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) +#define CLK_REG_LIST_DCN42() \ + SR(DENTIST_DISPCLK_CNTL), \ + CLK_SR_DCN42(CLK8_CLK_TICK_CNT_CONFIG_REG), \ + CLK_SR_DCN42(CLK8_CLK0_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK1_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK2_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK3_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK4_CURRENT_CNT), \ + CLK_SR_DCN42(CLK8_CLK0_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK1_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK2_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK3_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK4_BYPASS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK0_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK1_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK2_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK3_DS_CNTL), \ + CLK_SR_DCN42(CLK8_CLK4_DS_CNTL) + +#define CLK_COMMON_MASK_SH_LIST_DCN42(mask_sh) \ + CLK_SF(CLK8_CLK_TICK_CNT_CONFIG_REG, TIMER_THRESHOLD, mask_sh), \ + CLK_SF(CLK8_CLK0_BYPASS_CNTL, CLK0_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK1_BYPASS_CNTL, CLK1_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK3_BYPASS_CNTL, CLK3_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK4_BYPASS_CNTL, CLK4_BYPASS_SEL, mask_sh), \ + CLK_SF(CLK8_CLK0_DS_CNTL, CLK0_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK1_DS_CNTL, CLK1_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK2_DS_CNTL, CLK2_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK3_DS_CNTL, CLK3_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK4_DS_CNTL, CLK4_DS_DIV_ID, mask_sh), \ + CLK_SF(CLK8_CLK0_DS_CNTL, CLK0_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK1_DS_CNTL, CLK1_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK2_DS_CNTL, CLK2_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK3_DS_CNTL, CLK3_ALLOW_DS, mask_sh), \ + CLK_SF(CLK8_CLK4_DS_CNTL, CLK4_ALLOW_DS, mask_sh), \ + + + #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ type DENTIST_DPREFCLK_WDIVIDER; \ @@ -246,6 +275,42 @@ enum dentist_divider_range { type FbMult_int; \ type FbMult_frac; +#define CLK42_REG_LIST(clkip_num, type) \ + type CLK ## clkip_num ## _CLK_TICK_CNT_CONFIG_REG; \ + type CLK ## clkip_num ## _CLK0_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK1_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK2_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK3_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK4_CURRENT_CNT; \ + type CLK ## clkip_num ## _CLK0_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK1_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK2_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK3_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK4_BYPASS_CNTL; \ + type CLK ## clkip_num ## _CLK0_DS_CNTL; \ + type CLK ## clkip_num ## _CLK1_DS_CNTL; \ + type CLK ## clkip_num ## _CLK2_DS_CNTL; \ + type CLK ## clkip_num ## _CLK3_DS_CNTL; \ + type CLK ## clkip_num ## _CLK4_DS_CNTL; + +#define CLK42_REG_FIELD_LIST(type) \ + type TIMER_THRESHOLD; \ + type CLK0_BYPASS_SEL; \ + type CLK1_BYPASS_SEL; \ + type CLK2_BYPASS_SEL; \ + type CLK3_BYPASS_SEL; \ + type CLK4_BYPASS_SEL; \ + type CLK0_DS_DIV_ID; \ + type CLK1_DS_DIV_ID; \ + type CLK2_DS_DIV_ID; \ + type CLK3_DS_DIV_ID; \ + type CLK4_DS_DIV_ID; \ + type CLK0_ALLOW_DS; \ + type CLK1_ALLOW_DS; \ + type CLK2_ALLOW_DS; \ + type CLK3_ALLOW_DS; \ + type CLK4_ALLOW_DS; + /* *************************************************************************************** ****************** Clock Manager Private Structures *********************************** @@ -277,10 +342,10 @@ struct clk_mgr_registers { uint32_t CLK2_CLK2_DFS_CNTL; uint32_t CLK1_CLK0_CURRENT_CNT; - uint32_t CLK1_CLK1_CURRENT_CNT; - uint32_t CLK1_CLK2_CURRENT_CNT; - uint32_t CLK1_CLK3_CURRENT_CNT; - uint32_t CLK1_CLK4_CURRENT_CNT; + uint32_t CLK1_CLK1_CURRENT_CNT; + uint32_t CLK1_CLK2_CURRENT_CNT; + uint32_t CLK1_CLK3_CURRENT_CNT; + uint32_t CLK1_CLK4_CURRENT_CNT; uint32_t CLK1_CLK5_CURRENT_CNT; uint32_t CLK0_CLK0_DFS_CNTL; @@ -309,16 +374,19 @@ struct clk_mgr_registers { uint32_t CLK1_CLK5_ALLOW_DS; uint32_t CLK5_spll_field_8; uint32_t CLK6_spll_field_8; + CLK42_REG_LIST(8, uint32_t) }; struct clk_mgr_shift { CLK_REG_FIELD_LIST(uint8_t) CLK20_REG_FIELD_LIST(uint8_t) + CLK42_REG_FIELD_LIST(uint8_t) }; struct clk_mgr_mask { CLK_REG_FIELD_LIST(uint32_t) CLK20_REG_FIELD_LIST(uint32_t) + CLK42_REG_FIELD_LIST(uint32_t) }; enum clock_type { @@ -333,6 +401,8 @@ enum clock_type { clock_type_dscclk, clock_type_uclk, clock_type_dramclk, + clock_type_dprefclk, + clock_type_dtbclk, }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index 500a601e99b50..d6f5e01a0b66c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -224,6 +224,10 @@ struct dccg_funcs { void (*otg_drop_pixel)(struct dccg *dccg, uint32_t otg_inst); void (*dccg_init)(struct dccg *dccg); + void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */ + void (*allow_clock_gating)(struct dccg *dccg, bool allow); + void (*enable_memory_low_power)(struct dccg *dccg, bool enable); + bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg); void (*set_dpstreamclk_root_clock_gating)( struct dccg *dccg, int dp_hpo_inst, @@ -333,6 +337,7 @@ struct dccg_funcs { void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state); + void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable); }; #endif //__DAL_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 1ddfa30411c83..4307362749f05 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -254,30 +254,38 @@ struct hubbub_funcs { bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); void (*dchvm_init)(struct hubbub *hubbub); + /* Performance monitoring related functions */ struct hubbub_perfmon_funcs { void (*reset)(struct hubbub *hubbub); - void (*start_measuring_max_memory_latency_ns)( + void (*start_measuring_memory_latencies)( struct hubbub *hubbub); - uint32_t (*get_max_memory_latency_ns)(struct hubbub *hubbub, - uint32_t refclk_mhz, uint32_t *sample_count); - void (*start_measuring_average_memory_latency_ns)( + uint32_t (*get_memory_latencies_ns)(struct hubbub *hubbub, + uint32_t refclk_mhz, uint32_t *min_latency_ns, + uint32_t *max_latency_ns, uint32_t *avg_latency_ns); + void (*start_measuring_urgent_assertion_count)( struct hubbub *hubbub); - uint32_t (*get_average_memory_latency_ns)(struct hubbub *hubbub, - uint32_t refclk_mhz, uint32_t *sample_count); - void (*start_measuring_urgent_ramp_latency_ns)( + bool (*get_urgent_assertion_count)(struct hubbub *hubbub, + uint32_t refclk_mhz, + uint32_t *assertion_count, + uint32_t *deassertion_count, + uint32_t *timestamp_us); + void (*start_measuring_urgent_ramp_latency)( struct hubbub *hubbub, const struct hubbub_urgent_latency_params *params); uint32_t (*get_urgent_ramp_latency_ns)(struct hubbub *hubbub, uint32_t refclk_mhz); - void (*start_measuring_unbounded_bandwidth_mbps)( + void (*start_measuring_unbounded_bandwidth)( struct hubbub *hubbub); uint32_t (*get_unbounded_bandwidth_mbps)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t *duration_ns); - void (*start_measuring_average_bandwidth_mbps)( + void (*start_measuring_in_order_bandwidth)( struct hubbub *hubbub); - uint32_t (*get_average_bandwidth_mbps)(struct hubbub *hubbub, + uint32_t (*get_in_order_bandwidth_mbps)(struct hubbub *hubbub, uint32_t refclk_mhz, uint32_t min_duration_ns, uint32_t *duration_ns); + void (*start_measuring_prefetch_data_size)( + struct hubbub *hubbub); + uint32_t (*get_prefetch_data_size)(struct hubbub *hubbub); } perfmon; struct hubbub_qos_funcs { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dio.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dio.h new file mode 100644 index 0000000000000..532bf54cf2c48 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dio.h @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2025 Advanced Micro Devices, Inc. + +#ifndef __DC_DIO_H__ +#define __DC_DIO_H__ + +#include "dc_types.h" + +struct dc_context; +struct dio; + +struct dio_funcs { + void (*mem_pwr_ctrl)(struct dio *dio, bool enable_i2c_light_sleep); +}; + +struct dio { + const struct dio_funcs *funcs; + struct dc_context *ctx; +}; + +#endif /* __DC_DIO_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index d88b57d4f5125..39215ecb480e4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -367,6 +367,14 @@ struct dpp_funcs { void (*dpp_force_disable_cursor)(struct dpp *dpp_base); + void (*dpp_cm_hist_control)( + struct dpp *dpp_base, + struct cm_hist_control cm_hist_control, + enum dc_color_space color_space); + + bool (*dpp_cm_hist_read)( + struct dpp *dpp_base, + struct cm_hist *cm_hist); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index a79019365af8c..2a5a81d159507 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -89,7 +89,7 @@ enum hubp_3dlut_fl_addressing_mode { enum hubp_3dlut_fl_width { hubp_3dlut_fl_width_17 = 17, hubp_3dlut_fl_width_33 = 33, - hubp_3dlut_fl_width_transformed = 4916, //mpc default + hubp_3dlut_fl_width_17_transformed = 4916, //mpc default }; enum hubp_3dlut_fl_crossbar_bit_slice { @@ -99,22 +99,6 @@ enum hubp_3dlut_fl_crossbar_bit_slice { hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 }; -struct hubp_fl_3dlut_config { - bool enabled; - enum hubp_3dlut_fl_width width; - enum hubp_3dlut_fl_mode mode; - enum hubp_3dlut_fl_format format; - uint16_t bias; - uint16_t scale; - struct dc_plane_address address; - enum hubp_3dlut_fl_addressing_mode addr_mode; - enum dc_cm2_gpu_mem_layout layout; - uint8_t protection_bits; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b; - enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r; -}; - struct hubp { const struct hubp_funcs *funcs; struct dc_context *ctx; @@ -243,7 +227,6 @@ struct hubp_funcs { void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp); unsigned int (*hubp_get_underflow_status)(struct hubp *hubp); void (*hubp_init)(struct hubp *hubp); - void (*dmdata_set_attributes)( struct hubp *hubp, const struct dc_dmdata_attributes *attr); @@ -290,24 +273,15 @@ struct hubp_funcs { void (*hubp_wait_pipe_read_start)(struct hubp *hubp); void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs); - void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); - void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, - enum hubp_3dlut_fl_mode mode); - void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, - enum hubp_3dlut_fl_format format); void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, - const struct dc_plane_address address); + const struct dc_plane_address *address); + void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, + const struct dc_3dlut_dma *config); void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); - void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); - void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); - void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits); void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, - enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + enum dc_cm_lut_pixel_format format); int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); - void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg); void (*hubp_clear_tiling)(struct hubp *hubp); uint32_t (*hubp_get_current_read_line)(struct hubp *hubp); uint32_t (*hubp_get_det_config_error)(struct hubp *hubp); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index a61d12ec61bc4..51581c10fd6bf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -152,6 +152,13 @@ struct dc_rgb { uint32_t blue; }; +struct tetrahedral_33x33x33 { + struct dc_rgb lut0[8985]; + struct dc_rgb lut1[8984]; + struct dc_rgb lut2[8984]; + struct dc_rgb lut3[8984]; +}; + struct tetrahedral_17x17x17 { struct dc_rgb lut0[1229]; struct dc_rgb lut1[1228]; @@ -165,14 +172,23 @@ struct tetrahedral_9x9x9 { struct dc_rgb lut3[182]; }; +enum lut_dimension { + LUT_DIM_INVALID = 0, + LUT_DIM_9 = 9, + LUT_DIM_17 = 17, + LUT_DIM_33 = 33, +}; + struct tetrahedral_params { union { +//TODO: Uncomment when in use. +// struct tetrahedral_33x33x33 tetrahedral_33; struct tetrahedral_17x17x17 tetrahedral_17; struct tetrahedral_9x9x9 tetrahedral_9; }; bool use_tetrahedral_9; bool use_12bits; - + enum lut_dimension lut_dim; }; /* arr_curve_points - regamma regions/segments specification @@ -240,7 +256,7 @@ struct default_adjustment { enum dc_color_space out_color_space; enum dc_color_space in_color_space; enum dc_color_depth color_depth; - enum pixel_format surface_pixel_format; + enum dc_pixel_format surface_pixel_format; enum graphics_csc_adjust_type csc_adjust_type; bool force_hw_default; }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index df512920a9fab..5abbf485d273e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -44,9 +44,11 @@ struct pipe_ctx; struct encoder_init_data { enum channel_id channel; struct graphics_object_id connector; + struct gpio *hpd_gpio; enum hpd_source_id hpd_source; /* TODO: in DAL2, here was pointer to EventManagerInterface */ struct graphics_object_id encoder; + struct graphics_object_id analog_encoder; enum engine_id analog_engine; struct dc_context *ctx; enum transmitter transmitter; @@ -81,12 +83,14 @@ struct link_encoder { int32_t aux_channel_offset; struct dc_context *ctx; struct graphics_object_id id; + struct graphics_object_id analog_id; struct graphics_object_id connector; uint32_t output_signals; enum engine_id preferred_engine; enum engine_id analog_engine; struct encoder_feature_support features; enum transmitter transmitter; + struct gpio *hpd_gpio; enum hpd_source_id hpd_source; bool usbc_combo_phy; }; @@ -128,6 +132,8 @@ struct link_encoder_funcs { void (*enable_lvds_output)(struct link_encoder *enc, enum clock_source_id clock_source, uint32_t pixel_clock); + void (*enable_analog_output)(struct link_encoder *enc, + uint32_t pixel_clock); void (*disable_output)(struct link_encoder *link_enc, enum signal_type signal); void (*dp_set_lane_settings)(struct link_encoder *enc, @@ -178,6 +184,8 @@ struct link_encoder_funcs { void (*disable_dpia_output)(struct link_encoder *link_enc, uint8_t dpia_id, uint8_t digmode); + bool (*get_hpd_state)(struct link_encoder *enc); + bool (*program_hpd_filter)(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); }; /* diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index a8d1abe20f62c..f5617674bea8e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -54,6 +54,7 @@ #include "dc_hw_types.h" #include "hw_shared.h" #include "transform.h" +#include "dc_types.h" #define MAX_MPCC 6 #define MAX_OPP 6 @@ -66,7 +67,6 @@ enum mpc_output_csc_mode { MPC_OUTPUT_CSC_COEF_B }; - enum mpcc_blend_mode { MPCC_BLEND_MODE_BYPASS, MPCC_BLEND_MODE_TOP_LAYER_PASSTHROUGH, @@ -102,13 +102,6 @@ enum mpcc_movable_cm_location { MPCC_MOVABLE_CM_LOCATION_AFTER, }; -enum MCM_LUT_XABLE { - MCM_LUT_DISABLE, - MCM_LUT_DISABLED = MCM_LUT_DISABLE, - MCM_LUT_ENABLE, - MCM_LUT_ENABLED = MCM_LUT_ENABLE, -}; - enum MCM_LUT_ID { MCM_LUT_3DLUT, MCM_LUT_1DLUT, @@ -117,7 +110,7 @@ enum MCM_LUT_ID { struct mpc_fl_3dlut_config { bool enabled; - uint16_t width; + enum dc_cm_lut_size size; bool select_lut_bank_a; uint16_t bit_depth; int hubp_index; @@ -1042,6 +1035,24 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); + /** + * @get_3dlut_fast_load_status: + * + * Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id + * - [in/out] done + * - [in/out] soft_underflow + * - [in/out] hard_underflow + * + * Return: + * + * void + */ + void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); + /** * @populate_lut: * @@ -1058,8 +1069,11 @@ struct mpc_funcs { * * void */ - void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id); + void (*populate_lut)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const union mcm_lut_params *params, + const bool lut_bank_a, + const int mpcc_id); /** * @program_lut_read_write_control: @@ -1070,13 +1084,18 @@ struct mpc_funcs { * - [in/out] mpc - MPC context. * - [in] id * - [in] lut_bank_a + * - [in] bit_depth * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); + void (*program_lut_read_write_control)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const bool lut_bank_a, + const unsigned int bit_depth, + const int mpcc_id); /** * @program_lut_mode: @@ -1086,33 +1105,44 @@ struct mpc_funcs { * Parameters: * - [in/out] mpc - MPC context. * - [in] id - * - [in] xable + * - [in] enable * - [in] lut_bank_a + * - [in] size * - [in] mpcc_id * * Return: * * void */ - void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, - bool lut_bank_a, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const bool enable, + const bool lut_bank_a, + const enum dc_cm_lut_size size, + const int mpcc_id); - /** - * @mcm: - * - * MPC MCM new HW sequential programming functions - */ - struct { - void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); - void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); - void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); - bool (*is_config_supported)(uint32_t width); - void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, - bool lut_bank_a, bool enabled, int mpcc_id); - void (*populate_lut)(struct mpc *mpc, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id); - } mcm; + /** + * @get_lut_mode: + * + * Obtains enablement and ram bank status. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] mpcc_id + * - [out] enable + * - [out] lut_bank_a + * + * Return: + * + * void + */ + void (*get_lut_mode)(struct mpc *mpc, + const enum MCM_LUT_ID id, + const int mpcc_id, + bool *enable, + bool *lut_bank_a); /** * @rmcm: @@ -1125,9 +1155,11 @@ struct mpc_funcs { void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, bool enabled, int mpcc_id); - void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_XABLE xable, - bool lut_bank_a, int mpcc_id); - void (*program_3dlut_size)(struct mpc *mpc, uint32_t width, int mpcc_id); + void (*program_lut_mode)(struct mpc *mpc, + bool enable, + bool lut_bank_a, + int mpcc_id); + void (*program_3dlut_size)(struct mpc *mpc, const enum dc_cm_lut_size size, int mpcc_id); void (*program_bias_scale)(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id); void (*program_bit_depth)(struct mpc *mpc, uint16_t bit_depth, int mpcc_id); bool (*is_config_supported)(uint32_t width); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index da7bf59c4b9d1..2f70bb476c97b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -122,6 +122,12 @@ enum timing_synchronization_type { VBLANK_SYNCHRONIZABLE }; +enum crc_poly_mode { + CRC_POLY_MODE_16, + CRC_POLY_MODE_32, + CRC_POLY_MODE_MAX, +}; + struct crc_params { /* Regions used to calculate CRC*/ uint16_t windowa_x_start; @@ -144,6 +150,7 @@ struct crc_params { uint8_t crc_eng_inst; bool reset; + enum crc_poly_mode crc_poly_mode; }; struct dcn_otg_state { @@ -511,6 +518,8 @@ struct timing_generator_funcs { bool (*wait_update_lock_status)(struct timing_generator *tg, bool locked); void (*read_otg_state)(struct timing_generator *tg, struct dcn_otg_state *s); void (*optc_read_reg_state)(struct timing_generator *tg, struct dcn_optc_reg_state *optc_reg_state); + void (*enable_otg_pwa)(struct timing_generator *tg, struct otc_pwa_frame_sync *pwa_param); + void (*disable_otg_pwa)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 5a1d9b708a9d9..30990355985dd 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -160,7 +160,7 @@ struct scaler_data { struct scaling_ratios ratios; struct scl_inits inits; struct sharpness_adj sharpness; - enum pixel_format format; + enum dc_pixel_format format; struct line_buffer_params lb_params; // Below struct holds the scaler values to program hw registers struct dscl_prog_data dscl_prog_data; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_service.h b/drivers/gpu/drm/amd/display/dc/inc/link_service.h index 6f94e48a24d1b..540fbc174eec0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link_service.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link_service.h @@ -114,9 +114,6 @@ struct link_service { struct dc_sink_init_data *init_data); void (*remove_remote_sink)(struct dc_link *link, struct dc_sink *sink); bool (*get_hpd_state)(struct dc_link *link); - struct gpio *(*get_hpd_gpio)(struct dc_bios *dcb, - struct graphics_object_id link_id, - struct gpio_service *gpio_service); void (*enable_hpd)(const struct dc_link *link); void (*disable_hpd)(const struct dc_link *link); void (*enable_hpd_filter)(struct dc_link *link, bool enable); @@ -168,7 +165,6 @@ struct link_service { bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable); bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx); - /*************************** DDC **************************************/ struct ddc_service *(*create_ddc_service)( struct ddc_service_init_data *ddc_init_data); @@ -231,9 +227,9 @@ struct link_service { const struct link_resource *link_res, struct link_training_settings *lt_settings); void (*dpcd_write_rx_power_ctrl)(struct dc_link *link, bool on); + - - /*************************** DP IRQ Handler ***************************/ + /*************************** DP IRQ Handler ***************************/ bool (*dp_parse_link_loss_status)( struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data); @@ -286,8 +282,6 @@ struct link_service { bool (*edp_set_replay_allow_active)(struct dc_link *dc_link, const bool *enable, bool wait, bool force_static, const unsigned int *power_opts); - bool (*edp_setup_replay)(struct dc_link *link, - const struct dc_stream_state *stream); bool (*edp_send_replay_cmd)(struct dc_link *link, enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_data); @@ -307,6 +301,12 @@ struct link_service { bool (*edp_receiver_ready_T9)(struct dc_link *link); bool (*edp_receiver_ready_T7)(struct dc_link *link); bool (*edp_power_alpm_dpcd_enable)(struct dc_link *link, bool enable); + bool (*dp_setup_replay)(struct dc_link *link, const struct dc_stream_state *stream); + bool (*dp_pr_get_panel_inst)(const struct dc *dc, const struct dc_link *link, unsigned int *inst_out); + bool (*dp_pr_enable)(struct dc_link *link, bool enable); + bool (*dp_pr_update_state)(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data); + bool (*dp_pr_set_general_cmd)(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data); + bool (*dp_pr_get_state)(const struct dc_link *link, uint64_t *state); void (*edp_set_panel_power)(struct dc_link *link, bool powerOn); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 79746d931471a..cecd3282a29f7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -60,6 +60,7 @@ struct resource_caps { int num_hpo_dp_stream_encoder; int num_hpo_dp_link_encoder; int num_mpc_3dlut; + int num_rmcm; }; struct resource_straps { diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index b5e14d7923784..807b73c2a758b 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -198,3 +198,12 @@ IRQ_DCN401 = irq_service_dcn401.o AMD_DAL_IRQ_DCN401= $(addprefix $(AMDDALPATH)/dc/irq/dcn401/,$(IRQ_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN401) + +############################################################################### +# DCN 42 +############################################################################### +IRQ_DCN42 = irq_service_dcn42.o + +AMD_DAL_IRQ_DCN42= $(addprefix $(AMDDALPATH)/dc/irq/dcn42/,$(IRQ_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN42) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c new file mode 100644 index 0000000000000..19e0741c62cda --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.c @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "include/logger_interface.h" +#include "../dce110/irq_service_dce110.h" + +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" + +#include "irq_service_dcn42.h" + +#define DCN_BASE__INST0_SEG2 0x000034C0 + +static enum dc_irq_source to_dal_irq_source_dcn42( + struct irq_service *irq_service, + uint32_t src_id, + uint32_t ext_id) +{ + switch (src_id) { + case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK1; + case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK2; + case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK3; + case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK4; + case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK5; + case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: + return DC_IRQ_SOURCE_VBLANK6; + case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC1_VLINE0; + case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC2_VLINE0; + case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC3_VLINE0; + case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC4_VLINE0; + case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC5_VLINE0; + case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL: + return DC_IRQ_SOURCE_DC6_VLINE0; + case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP1; + case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP2; + case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP3; + case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP4; + case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP5; + case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: + return DC_IRQ_SOURCE_PFLIP6; + case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE1; + case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE2; + case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE3; + case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE4; + case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE5; + case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: + return DC_IRQ_SOURCE_VUPDATE6; + case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT: + return DC_IRQ_SOURCE_DMCUB_OUTBOX; + case DCN_1_0__SRCID__DC_HPD1_INT: + /* generic src_id for all HPD and HPDRX interrupts */ + switch (ext_id) { + case DCN_1_0__CTXID__DC_HPD1_INT: + return DC_IRQ_SOURCE_HPD1; + case DCN_1_0__CTXID__DC_HPD2_INT: + return DC_IRQ_SOURCE_HPD2; + case DCN_1_0__CTXID__DC_HPD3_INT: + return DC_IRQ_SOURCE_HPD3; + case DCN_1_0__CTXID__DC_HPD4_INT: + return DC_IRQ_SOURCE_HPD4; + case DCN_1_0__CTXID__DC_HPD5_INT: + return DC_IRQ_SOURCE_HPD5; + case DCN_1_0__CTXID__DC_HPD6_INT: + return DC_IRQ_SOURCE_HPD6; + case DCN_1_0__CTXID__DC_HPD1_RX_INT: + return DC_IRQ_SOURCE_HPD1RX; + case DCN_1_0__CTXID__DC_HPD2_RX_INT: + return DC_IRQ_SOURCE_HPD2RX; + case DCN_1_0__CTXID__DC_HPD3_RX_INT: + return DC_IRQ_SOURCE_HPD3RX; + case DCN_1_0__CTXID__DC_HPD4_RX_INT: + return DC_IRQ_SOURCE_HPD4RX; + case DCN_1_0__CTXID__DC_HPD5_RX_INT: + return DC_IRQ_SOURCE_HPD5RX; + case DCN_1_0__CTXID__DC_HPD6_RX_INT: + return DC_IRQ_SOURCE_HPD6RX; + default: + return DC_IRQ_SOURCE_INVALID; + } + break; + default: + return DC_IRQ_SOURCE_INVALID; + } + +} + +static struct irq_source_info_funcs hpd_irq_info_funcs = { + .set = NULL, + .ack = hpd0_ack +}; + +static struct irq_source_info_funcs hpd_rx_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs pflip_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vblank_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs outbox_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vline0_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vline1_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +static struct irq_source_info_funcs vline2_irq_info_funcs = { + .set = NULL, + .ack = NULL +}; + +#undef BASE_INNER +#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg + +/* compile time expand base address. */ +#define BASE(seg) \ + BASE_INNER(seg) + +#define SRI(reg_name, block, id)\ + (BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ + reg ## block ## id ## _ ## reg_name) + +#define SRI_DMUB(reg_name)\ + (BASE(reg ## reg_name ## _BASE_IDX) + \ + reg ## reg_name) + +#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ + .enable_reg = SRI(reg1, block, reg_num),\ + .enable_mask = \ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ + ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI(reg2, block, reg_num),\ + .ack_mask = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ + +#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ + .enable_reg = SRI_DMUB(reg1),\ + .enable_mask = \ + reg1 ## __ ## mask1 ## _MASK,\ + .enable_value = {\ + reg1 ## __ ## mask1 ## _MASK,\ + ~reg1 ## __ ## mask1 ## _MASK \ + },\ + .ack_reg = SRI_DMUB(reg2),\ + .ack_mask = \ + reg2 ## __ ## mask2 ## _MASK,\ + .ack_value = \ + reg2 ## __ ## mask2 ## _MASK \ + +#define hpd_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_irq_info_funcs\ + } + +#define hpd_rx_int_entry(reg_num)\ + [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ + IRQ_REG_ENTRY(HPD, reg_num,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ + DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ + .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ + .funcs = &hpd_rx_irq_info_funcs\ + } +#define pflip_int_entry(reg_num)\ + [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ + IRQ_REG_ENTRY(HUBPREQ, reg_num,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ + DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ + .funcs = &pflip_irq_info_funcs\ + } + +#define vblank_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ + .funcs = &vblank_irq_info_funcs\ + } + +#define vupdate_no_lock_int_entry(reg_num)\ + [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ + OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ + .funcs = &vupdate_no_lock_irq_info_funcs\ + } + +#define vline0_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\ + .funcs = &vline0_irq_info_funcs\ + } +#define vline1_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE1 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_CLEAR),\ + .funcs = &vline1_irq_info_funcs\ + } +#define vline2_int_entry(reg_num)\ + [DC_IRQ_SOURCE_DC1_VLINE2 + reg_num] = {\ + IRQ_REG_ENTRY(OTG, reg_num,\ + OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE,\ + OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_CLEAR),\ + .funcs = &vline2_irq_info_funcs\ + } +#define dmub_outbox_int_entry()\ + [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\ + IRQ_REG_ENTRY_DMUB(\ + DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\ + DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\ + .funcs = &outbox_irq_info_funcs\ + } + +#define dummy_irq_entry() \ + {\ + .funcs = &dummy_irq_info_funcs\ + } + +#define i2c_int_entry(reg_num) \ + [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() + +#define dp_sink_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() + +#define gpio_pad_int_entry(reg_num) \ + [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() + +#define dc_underflow_int_entry(reg_num) \ + [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() + +static struct irq_source_info_funcs dummy_irq_info_funcs = { + .set = dal_irq_service_dummy_set, + .ack = dal_irq_service_dummy_ack +}; + +static const struct irq_source_info irq_source_info_dcn42[DAL_IRQ_SOURCES_NUMBER] = { + [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), + /* HPD (1-4) */ + hpd_int_entry(0), + hpd_int_entry(1), + hpd_int_entry(2), + hpd_int_entry(3), + /* HPD RX (1-4) */ + hpd_rx_int_entry(0), + hpd_rx_int_entry(1), + hpd_rx_int_entry(2), + hpd_rx_int_entry(3), + /* I2C (1-6) */ + i2c_int_entry(1), + i2c_int_entry(2), + i2c_int_entry(3), + i2c_int_entry(4), + i2c_int_entry(5), + i2c_int_entry(6), + /* DP sink (1-6) keep table shape */ + dp_sink_int_entry(1), + dp_sink_int_entry(2), + dp_sink_int_entry(3), + dp_sink_int_entry(4), + dp_sink_int_entry(5), + dp_sink_int_entry(6), + [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), + /* PFLIP (1-4) */ + pflip_int_entry(0), + pflip_int_entry(1), + pflip_int_entry(2), + pflip_int_entry(3), + [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), + [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), + /* GPIO pads */ + gpio_pad_int_entry(0), + gpio_pad_int_entry(1), + gpio_pad_int_entry(2), + gpio_pad_int_entry(3), + gpio_pad_int_entry(4), + gpio_pad_int_entry(5), + gpio_pad_int_entry(6), + gpio_pad_int_entry(7), + gpio_pad_int_entry(8), + gpio_pad_int_entry(9), + gpio_pad_int_entry(10), + gpio_pad_int_entry(11), + gpio_pad_int_entry(12), + gpio_pad_int_entry(13), + gpio_pad_int_entry(14), + gpio_pad_int_entry(15), + gpio_pad_int_entry(16), + gpio_pad_int_entry(17), + gpio_pad_int_entry(18), + gpio_pad_int_entry(19), + gpio_pad_int_entry(20), + gpio_pad_int_entry(21), + gpio_pad_int_entry(22), + gpio_pad_int_entry(23), + gpio_pad_int_entry(24), + gpio_pad_int_entry(25), + gpio_pad_int_entry(26), + gpio_pad_int_entry(27), + gpio_pad_int_entry(28), + gpio_pad_int_entry(29), + gpio_pad_int_entry(30), + /* Underflow (1-4 active, keep 5-6 dummy) */ + dc_underflow_int_entry(1), + dc_underflow_int_entry(2), + dc_underflow_int_entry(3), + dc_underflow_int_entry(4), + dc_underflow_int_entry(5), + dc_underflow_int_entry(6), + [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), + [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), + vblank_int_entry(0), + vblank_int_entry(1), + vblank_int_entry(2), + vblank_int_entry(3), + [DC_IRQ_SOURCE_DC5_VLINE1] = dummy_irq_entry(), + [DC_IRQ_SOURCE_DC6_VLINE1] = dummy_irq_entry(), + dmub_outbox_int_entry(), + vupdate_no_lock_int_entry(0), + vupdate_no_lock_int_entry(1), + vupdate_no_lock_int_entry(2), + vupdate_no_lock_int_entry(3), + vline0_int_entry(0), + vline0_int_entry(1), + vline0_int_entry(2), + vline0_int_entry(3), + vline1_int_entry(0), + vline1_int_entry(1), + vline1_int_entry(2), + vline1_int_entry(3), + vline2_int_entry(0), + vline2_int_entry(1), + vline2_int_entry(2), + vline2_int_entry(3), +}; + +static const struct irq_service_funcs irq_service_funcs_dcn42 = { + .to_dal_irq_source = to_dal_irq_source_dcn42 +}; + +static void dcn42_irq_construct(struct irq_service *irq_service, + struct irq_service_init_data *init_data) +{ + dal_irq_service_construct(irq_service, init_data); + irq_service->info = irq_source_info_dcn42; + irq_service->funcs = &irq_service_funcs_dcn42; +} + +struct irq_service *dal_irq_service_dcn42_create(struct irq_service_init_data *init_data) +{ + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), GFP_KERNEL); + + if (!irq_service) + return NULL; + + dcn42_irq_construct(irq_service, init_data); + return irq_service; +} diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h new file mode 100644 index 0000000000000..a3f70bce3a618 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn42/irq_service_dcn42.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * DCN4.2 IRQ service interface (dal-dev only) + */ +#ifndef __IRQ_SERVICE_DCN42_H__ +#define __IRQ_SERVICE_DCN42_H__ + +#include "../dce110/irq_service_dce110.h" + +struct irq_service *dal_irq_service_dcn42_create( + struct irq_service_init_data *init_data); + +#endif /* __IRQ_SERVICE_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/Makefile b/drivers/gpu/drm/amd/display/dc/link/Makefile index 84c7af5fa5891..0f3670e302325 100644 --- a/drivers/gpu/drm/amd/display/dc/link/Makefile +++ b/drivers/gpu/drm/amd/display/dc/link/Makefile @@ -43,7 +43,8 @@ AMD_DISPLAY_FILES += $(AMD_DAL_LINK_ACCESSORIES) # hwss ############################################################################### LINK_HWSS = link_hwss_dio.o link_hwss_dpia.o link_hwss_hpo_dp.o \ -link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o +link_hwss_dio_fixed_vs_pe_retimer.o link_hwss_hpo_fixed_vs_pe_retimer_dp.o \ +link_hwss_virtual.o AMD_DAL_LINK_HWSS = $(addprefix $(AMDDALPATH)/dc/link/hwss/, \ $(LINK_HWSS)) @@ -56,7 +57,7 @@ LINK_PROTOCOLS = link_hpd.o link_ddc.o link_dpcd.o link_dp_dpia.o \ link_dp_training.o link_dp_training_8b_10b.o link_dp_training_128b_132b.o \ link_dp_training_dpia.o link_dp_training_auxless.o \ link_dp_training_fixed_vs_pe_retimer.o link_dp_phy.o link_dp_capability.o \ -link_edp_panel_control.o link_dp_irq_handler.o link_dp_dpia_bw.o +link_edp_panel_control.o link_dp_panel_replay.o link_dp_irq_handler.o link_dp_dpia_bw.o AMD_DAL_LINK_PROTOCOLS = $(addprefix $(AMDDALPATH)/dc/link/protocols/, \ $(LINK_PROTOCOLS)) diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index 1045c268672e2..693d852b1c403 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -81,7 +81,8 @@ static void dp_retrain_link_dp_test(struct dc_link *link, struct dc *dc = (struct dc *)link->dc; needs_divider_update = (link->dc->link_srv->dp_get_encoding_format(link_setting) != - link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings)); + link->dc->link_srv->dp_get_encoding_format((const struct dc_link_settings *) &link->cur_link_settings)) + || link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA; udelay(100); diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c similarity index 98% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c rename to drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c index 4f7f99156897b..64742c24f7e6e 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.c @@ -23,7 +23,7 @@ * */ -#include "virtual_link_hwss.h" +#include "link_hwss_virtual.h" void virtual_setup_stream_encoder(struct pipe_ctx *pipe_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h similarity index 92% rename from drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h rename to drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h index fbcbc5afb47d6..f6e448c89751a 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_hwss.h +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_virtual.h @@ -22,8 +22,8 @@ * Authors: AMD * */ -#ifndef __DC_VIRTUAL_LINK_HWSS_H__ -#define __DC_VIRTUAL_LINK_HWSS_H__ +#ifndef __DC_LINK_HWSS_VIRTUAL_H__ +#define __DC_LINK_HWSS_VIRTUAL_H__ #include "core_types.h" @@ -32,4 +32,4 @@ void virtual_setup_stream_attribute(struct pipe_ctx *pipe_ctx); void virtual_reset_stream_encoder(struct pipe_ctx *pipe_ctx); const struct link_hwss *get_virtual_link_hwss(void); -#endif /* __DC_VIRTUAL_LINK_HWSS_H__ */ +#endif /* __DC_LINK_HWSS_VIRTUAL_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 7fa6bc97a9193..7f1761080aba0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -150,14 +150,6 @@ static enum signal_type get_basic_signal_type(struct graphics_object_id encoder, default: return SIGNAL_TYPE_NONE; } - } else if (downstream.type == OBJECT_TYPE_ENCODER) { - switch (downstream.id) { - case ENCODER_ID_EXTERNAL_NUTMEG: - case ENCODER_ID_EXTERNAL_TRAVIS: - return SIGNAL_TYPE_DISPLAY_PORT; - default: - return SIGNAL_TYPE_NONE; - } } return SIGNAL_TYPE_NONE; @@ -171,8 +163,13 @@ static enum signal_type link_detect_sink_signal_type(struct dc_link *link, enum dc_detect_reason reason) { enum signal_type result; + struct audio_support *aud_support; struct graphics_object_id enc_id; + /* External DP bridges should use DP signal regardless of connector type. */ + if (link->ext_enc_id.id) + return SIGNAL_TYPE_DISPLAY_PORT; + if (link->is_dig_mapping_flexible) enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN}; else @@ -183,53 +180,51 @@ static enum signal_type link_detect_sink_signal_type(struct dc_link *link, if (link->ep_type != DISPLAY_ENDPOINT_PHY) return result; - /* Internal digital encoder will detect only dongles + /* + * Internal digital encoder will detect only dongles * that require digital signal */ - /* Detection mechanism is different + /* + * Detection mechanism is different * for different native connectors. * LVDS connector supports only LVDS signal; * PCIE is a bus slot, the actual connector needs to be detected first; * eDP connector supports only eDP signal; * HDMI should check straps for audio */ - - /* PCIE detects the actual connector on add-on board */ - if (link->link_id.id == CONNECTOR_ID_PCIE) { - /* ZAZTODO implement PCIE add-on card detection */ - } - switch (link->link_id.id) { - case CONNECTOR_ID_HDMI_TYPE_A: { - /* check audio support: + case CONNECTOR_ID_HDMI_TYPE_A: + /* + * check audio support: * if native HDMI is not supported, switch to DVI */ - struct audio_support *aud_support = - &link->dc->res_pool->audio_support; + aud_support = &link->dc->res_pool->audio_support; if (!aud_support->hdmi_audio_native) - if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A) - result = SIGNAL_TYPE_DVI_SINGLE_LINK; - } - break; + result = SIGNAL_TYPE_DVI_SINGLE_LINK; + break; case CONNECTOR_ID_DISPLAY_PORT: - case CONNECTOR_ID_USBC: { - /* DP HPD short pulse. Passive DP dongle will not + case CONNECTOR_ID_USBC: + /* + * DP HPD short pulse. Passive DP dongle will not * have short pulse */ if (reason != DETECT_REASON_HPDRX) { - /* Check whether DP signal detected: if not - + /* + * Check whether DP signal detected: if not - * we assume signal is DVI; it could be corrected * to HDMI after dongle detection */ if (!dm_helpers_is_dp_sink_present(link)) result = SIGNAL_TYPE_DVI_SINGLE_LINK; } - } - break; + break; + case CONNECTOR_ID_PCIE: + /* ZAZTODO implement PCIE add-on card detection */ + break; default: - break; + break; } return result; @@ -357,7 +352,7 @@ static void query_dp_dual_mode_adaptor( *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE; sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK; - CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf), + CONN_DATA_DETECT(link, type2_dongle_buf, sizeof(type2_dongle_buf), "DP-DVI passive dongle %dMhz: ", DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000); return; @@ -621,11 +616,22 @@ static bool detect_dp(struct dc_link *link, link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.raw = 0; } + if (link->ext_enc_id.id) { + /* Fix number of connected sinks reported by external DP bridge */ + link->dpcd_caps.sink_count.bits.SINK_COUNT = 1; + /* NUTMEG requires that we use HBR, doesn't work with RBR. */ + if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_00001A) + link->preferred_link_setting.link_rate = LINK_RATE_HIGH; + } + return true; } static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) { + if (old_edid == NULL || new_edid == NULL) + return false; + if (old_edid->length != new_edid->length) return false; @@ -651,8 +657,6 @@ static bool wait_for_entering_dp_alt_mode(struct dc_link *link) unsigned long long time_taken_in_ns; int tries_taken; - DC_LOGGER_INIT(link->ctx->logger); - /** * this function will only exist if we are on dcn21 (is_in_alt_mode is a * function pointer, so checking to see if it is equal to 0 is the same @@ -723,8 +727,6 @@ static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason reason) { - DC_LOGGER_INIT(link->ctx->logger); - LINK_INFO("link=%d, mst branch is now Connected\n", link->link_index); @@ -744,8 +746,6 @@ static bool discover_dp_mst_topology(struct dc_link *link, enum dc_detect_reason bool link_reset_cur_dp_mst_topology(struct dc_link *link) { - DC_LOGGER_INIT(link->ctx->logger); - LINK_INFO("link=%d, mst branch is now Disconnected\n", link->link_index); @@ -781,7 +781,6 @@ static void restore_phy_clocks_for_destructive_link_verification(const struct dc } static void verify_link_capability_destructive(struct dc_link *link, - struct dc_sink *sink, enum dc_detect_reason reason) { bool should_prepare_phy_clocks = @@ -855,11 +854,11 @@ static bool should_verify_link_capability_destructively(struct dc_link *link, return destrictive; } -static void verify_link_capability(struct dc_link *link, struct dc_sink *sink, +static void verify_link_capability(struct dc_link *link, enum dc_detect_reason reason) { if (should_verify_link_capability_destructively(link, reason)) - verify_link_capability_destructive(link, sink, reason); + verify_link_capability_destructive(link, reason); else verify_link_capability_non_destructive(link); } @@ -901,11 +900,21 @@ static bool link_detect_evaluate_edid_header(uint8_t edid_header[8]) */ static bool link_detect_ddc_probe(struct dc_link *link) { + enum signal_type signal = link_detect_sink_signal_type(link, DETECT_REASON_HPD); + enum ddc_transaction_type transaction_type = get_ddc_transaction_type(signal); + uint8_t edid_header[8] = {0}; + uint8_t zero = 0; + bool ddc_probed; + if (!link->ddc) return false; - uint8_t edid_header[8] = {0}; - bool ddc_probed = i2c_read(link->ddc, 0x50, edid_header, sizeof(edid_header)); + if (link->dc->hwss.prepare_ddc) + link->dc->hwss.prepare_ddc(link); + + set_ddc_transaction_type(link->ddc, transaction_type); + + ddc_probed = link_query_ddc_data(link->ddc, 0x50, &zero, 1, edid_header, sizeof(edid_header)); if (!ddc_probed) return false; @@ -930,28 +939,10 @@ static bool link_detect_ddc_probe(struct dc_link *link) */ static bool link_detect_dac_load_detect(struct dc_link *link) { - struct dc_bios *bios = link->ctx->dc_bios; - struct link_encoder *link_enc = link->link_enc; - enum engine_id engine_id = link_enc->preferred_engine; - enum dal_device_type device_type = DEVICE_TYPE_CRT; - enum bp_result bp_result = BP_RESULT_UNSUPPORTED; - uint32_t enum_id; - - switch (engine_id) { - case ENGINE_ID_DACB: - enum_id = 2; - break; - case ENGINE_ID_DACA: - default: - engine_id = ENGINE_ID_DACA; - enum_id = 1; - break; - } - - if (bios->funcs->dac_load_detection) - bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id); + if (!link->dc->hwss.dac_load_detect) + return false; - return bp_result == BP_RESULT_OK; + return link->dc->hwss.dac_load_detect(link); } /* @@ -979,8 +970,6 @@ static bool detect_link_and_local_sink(struct dc_link *link, enum dc_connection_type new_connection_type = dc_connection_none; const uint32_t post_oui_delay = 30; // 30ms - DC_LOGGER_INIT(link->ctx->logger); - if (dc_is_virtual_signal(link->connector_signal)) return false; @@ -1173,19 +1162,20 @@ static bool detect_link_and_local_sink(struct dc_link *link, * - cheap DVI-A cable or adapter that doesn't connect DDC */ if (dc_connector_supports_analog(link->link_id.id)) { - /* If we didn't do DAC load detection yet, do it now - * to verify there really is a display connected. + /* If we didn't already detect a display using + * DAC load detection, we know it isn't connected. */ - if (link->type != dc_connection_dac_load && - !link_detect_dac_load_detect(link)) { + if (link->type != dc_connection_analog_load) { if (prev_sink) dc_sink_release(prev_sink); link_disconnect_sink(link); return false; } - DC_LOG_INFO("%s detected analog display without EDID\n", __func__); - link->type = dc_connection_dac_load; + LINK_INFO("link=%d, analog display detected without EDID\n", + link->link_index); + + link->type = dc_connection_analog_load; sink->edid_caps.analog = true; break; } @@ -1330,7 +1320,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, // Pickup base DM settings dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink); // Override dc_panel_config if system has specific settings - dm_helpers_override_panel_settings(dc_ctx, &link->panel_config); + dm_helpers_override_panel_settings(dc_ctx, link); //sink only can use supported link rate table, we are foreced to enable it if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN) @@ -1367,17 +1357,17 @@ static bool detect_link_and_local_sink(struct dc_link *link, } /** - * link_detect_analog() - Determines if an analog sink is connected. + * link_detect_connection_type_analog() - Determines if an analog sink is connected. * * @link: DC link to evaluate (must support analog signalling). * @type: Updated with the detected connection type: * dc_connection_single (analog via DDC), - * dc_connection_dac_load (via load-detect), + * dc_connection_analog_load (via load-detect), * or dc_connection_none. * * Return: true if detection completed. */ -static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *type) +static bool link_detect_connection_type_analog(struct dc_link *link, enum dc_connection_type *type) { /* Don't care about connectors that don't support an analog signal. */ ASSERT(dc_connector_supports_analog(link->link_id.id)); @@ -1388,7 +1378,7 @@ static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *ty } if (link_detect_dac_load_detect(link)) { - *type = dc_connection_dac_load; + *type = dc_connection_analog_load; return true; } @@ -1405,8 +1395,6 @@ static bool link_detect_analog(struct dc_link *link, enum dc_connection_type *ty */ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type *type) { - uint32_t is_hpd_high = 0; - if (link->connector_signal == SIGNAL_TYPE_LVDS) { *type = dc_connection_single; return true; @@ -1421,7 +1409,7 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type * * (So it's high even when no display is connected.) */ if (dc_connector_supports_analog(link->link_id.id)) - return link_detect_analog(link, type); + return link_detect_connection_type_analog(link, type); if (link->connector_signal == SIGNAL_TYPE_EDP) { /*in case it is not on*/ @@ -1441,10 +1429,7 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type * } - if (!query_hpd_status(link, &is_hpd_high)) - goto hpd_gpio_failure; - - if (is_hpd_high) { + if (link_get_hpd_state(link)) { *type = dc_connection_single; /* TODO: need to do the actual detection */ } else { @@ -1457,9 +1442,6 @@ bool link_detect_connection_type(struct dc_link *link, enum dc_connection_type * } return true; - -hpd_gpio_failure: - return false; } bool link_detect(struct dc_link *link, enum dc_detect_reason reason) @@ -1468,12 +1450,11 @@ bool link_detect(struct dc_link *link, enum dc_detect_reason reason) bool is_delegated_to_mst_top_mgr = false; enum dc_connection_type pre_link_type = link->type; - DC_LOGGER_INIT(link->ctx->logger); - is_local_sink_detect_success = detect_link_and_local_sink(link, reason); - if (is_local_sink_detect_success && link->local_sink) - verify_link_capability(link, link->local_sink, reason); + if (is_local_sink_detect_success && link->local_sink) { + verify_link_capability(link, reason); + } DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__, link->link_index, is_local_sink_detect_success, pre_link_type, link->type); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 6ae1341476171..dc3398ad5835e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -46,6 +46,7 @@ #include "protocols/link_dp_capability.h" #include "protocols/link_dp_training.h" #include "protocols/link_edp_panel_control.h" +#include "protocols/link_dp_panel_replay.h" #include "protocols/link_dp_dpia_bw.h" #include "dm_helpers.h" @@ -180,7 +181,8 @@ void link_set_all_streams_dpms_off_for_link(struct dc_link *link) /* link can be also enabled by vbios. In this case it is not recorded * in pipe_ctx. Disable link phy here to make sure it is completely off */ - dp_disable_link_phy(link, &link_res, link->connector_signal); + if (dc_is_dp_signal(link->connector_signal)) + dp_disable_link_phy(link, &link_res, link->connector_signal); } void link_resume(struct dc_link *link) @@ -222,16 +224,32 @@ void link_get_master_pipes_with_dpms_on(const struct dc_link *link, } } -static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, - enum engine_id eng_id, - struct ext_hdmi_settings *settings) +static struct ext_hdmi_settings create_ext_hdmi_settings( + uint8_t address, + uint8_t reg_num, + uint8_t reg_num_6g, + const struct i2c_reg_info *reg_settings, + const struct i2c_reg_info *reg_settings_6g +) { - bool result = false; - int i = 0; - struct integrated_info *integrated_info = - pipe_ctx->stream->ctx->dc_bios->integrated_info; + struct ext_hdmi_settings result = { + .slv_addr = address, + .reg_num = reg_num, + .reg_num_6g = reg_num_6g, + }; + + memcpy(result.reg_settings, reg_settings, sizeof(result.reg_settings)); + memcpy(result.reg_settings_6g, reg_settings_6g, sizeof(result.reg_settings_6g)); + return result; +} - if (integrated_info == NULL) +static bool get_ext_hdmi_settings( + const struct integrated_info *info, + enum engine_id eng_id, + struct ext_hdmi_settings *settings +) +{ + if (!settings || !info) return false; /* @@ -241,422 +259,268 @@ static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, */ // Check if current bios contains ext Hdmi settings - if (integrated_info->gpu_cap_info & 0x20) { - switch (eng_id) { - case ENGINE_ID_DIGA: - settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp0_ext_hdmi_reg_settings, - sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp0_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); - result = true; - break; - case ENGINE_ID_DIGB: - settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp1_ext_hdmi_reg_settings, - sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp1_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); - result = true; - break; - case ENGINE_ID_DIGC: - settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp2_ext_hdmi_reg_settings, - sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp2_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); - result = true; - break; - case ENGINE_ID_DIGD: - settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; - settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; - settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; - memmove(settings->reg_settings, - integrated_info->dp3_ext_hdmi_reg_settings, - sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); - memmove(settings->reg_settings_6g, - integrated_info->dp3_ext_hdmi_6g_reg_settings, - sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); - result = true; - break; - default: - break; - } + if (!(info->gpu_cap_info & 0x20)) + return false; - if (result == true) { - // Validate settings from bios integrated info table - if (settings->slv_addr == 0) - return false; - if (settings->reg_num > 9) - return false; - if (settings->reg_num_6g > 3) - return false; + switch (eng_id) { + case ENGINE_ID_DIGA: + *settings = create_ext_hdmi_settings( + info->dp0_ext_hdmi_slv_addr, + info->dp0_ext_hdmi_reg_num, + info->dp0_ext_hdmi_6g_reg_num, + info->dp0_ext_hdmi_reg_settings, + info->dp0_ext_hdmi_6g_reg_settings + ); + break; + case ENGINE_ID_DIGB: + *settings = create_ext_hdmi_settings( + info->dp1_ext_hdmi_slv_addr, + info->dp1_ext_hdmi_reg_num, + info->dp1_ext_hdmi_6g_reg_num, + info->dp1_ext_hdmi_reg_settings, + info->dp1_ext_hdmi_6g_reg_settings + ); + break; + case ENGINE_ID_DIGC: + *settings = create_ext_hdmi_settings( + info->dp2_ext_hdmi_slv_addr, + info->dp2_ext_hdmi_reg_num, + info->dp2_ext_hdmi_6g_reg_num, + info->dp2_ext_hdmi_reg_settings, + info->dp2_ext_hdmi_6g_reg_settings + ); + break; + case ENGINE_ID_DIGD: + *settings = create_ext_hdmi_settings( + info->dp3_ext_hdmi_slv_addr, + info->dp3_ext_hdmi_reg_num, + info->dp3_ext_hdmi_6g_reg_num, + info->dp3_ext_hdmi_reg_settings, + info->dp3_ext_hdmi_6g_reg_settings + ); + break; + default: + return false; + } - for (i = 0; i < settings->reg_num; i++) { - if (settings->reg_settings[i].i2c_reg_index > 0x20) - return false; - } + // Validate settings from bios integrated info table + if ( + !settings->slv_addr + || settings->reg_num > ARRAY_SIZE(settings->reg_settings) + || settings->reg_num_6g > ARRAY_SIZE(settings->reg_settings_6g) + ) { + return false; + } - for (i = 0; i < settings->reg_num_6g; i++) { - if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) - return false; - } - } + for (size_t i = 0; i < settings->reg_num; i++) { + if (settings->reg_settings[i].i2c_reg_index > 0x20) + return false; } - return result; + for (size_t i = 0; i < settings->reg_num_6g; i++) { + if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) + return false; + } + return true; } -static bool write_i2c(struct pipe_ctx *pipe_ctx, - uint8_t address, uint8_t *buffer, uint32_t length) +static bool write_i2c( + const struct dc_link *link, + uint8_t address, + uint8_t *buffer, + uint32_t length +) { - struct i2c_command cmd = {0}; - struct i2c_payload payload = {0}; + struct i2c_payload payload = { + .write = true, + .address = address, + .length = length, + .data = buffer, + }; + struct i2c_command cmd = { + .payloads = &payload, + .number_of_payloads = 1, + .engine = I2C_COMMAND_ENGINE_DEFAULT, + .speed = link->ctx->dc->caps.i2c_speed_in_khz, + }; + + return dm_helpers_submit_i2c(link->ctx, link, &cmd); +} - memset(&payload, 0, sizeof(payload)); - memset(&cmd, 0, sizeof(cmd)); +static bool write_i2c_retimer_offset_value( + const struct dc_link *link, + uint8_t address, + uint8_t offset, + uint8_t value +) +{ + DC_LOGGER_INIT(link->ctx->logger); + uint8_t buffer[] = { offset, value }; + const bool success = write_i2c(link, address, buffer, sizeof(buffer)); + + RETIMER_REDRIVER_INFO( + "Retimer write, address: 0x%x, offset: 0x%x, value: 0x%x, success: %d\n", + address, offset, value, success + ); + return success; +} - cmd.number_of_payloads = 1; - cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; - cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; +static bool write_i2c_retimer_vga( + const struct dc_link *link, + uint8_t address +) +{ + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t vga_data[][2] = { + { 0xFF, 0x01 }, + { 0x00, 0x23 }, + { 0xFF, 0x00 }, + }; + + for (size_t i = 0; i < ARRAY_SIZE(vga_data); i++) { + if (!write_i2c_retimer_offset_value(link, address, vga_data[i][0], vga_data[i][1])) { + DC_LOG_ERROR("Set retimer failed, vga index: %zu\n", i); + return false; + } + } + return true; +} - payload.address = address; - payload.data = buffer; - payload.length = length; - payload.write = true; - cmd.payloads = &payload; +static bool write_i2c_retimer_byte( + const struct dc_link *link, + uint8_t address, + uint8_t index, + uint8_t value +) +{ + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t apply_rx_tx_change = 0x4; - if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, - pipe_ctx->stream->link, &cmd)) + if (index > 0x20) return true; - return false; + if (!write_i2c_retimer_offset_value(link, address, index, value)) { + DC_LOG_ERROR("Set retimer failed, 3g index: 0x%x, value: 0x%x\n", index, value); + return false; + } + + // Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A + // needs to be set to 1 on every 0x0A-0x0C write. + if (0x0A <= index && index <= 0x0C) { + uint8_t offset = 0x0A; + + // Query current value from offset 0x0A + if (index == 0x0A) { + // Just written correct value, so no need to read it back + } else { + if (!link_query_ddc_data( + link->ddc, address, &offset, 1, &value, 1 + )) { + DC_LOG_ERROR("Set retimer failed, link_query_ddc_data\n"); + return false; + } + } + + value |= apply_rx_tx_change; + if (!write_i2c_retimer_offset_value(link, address, offset, value)) { + DC_LOG_ERROR("Set retimer failed, 3g offset: 0x%x, value: 0x%x\n", offset, value); + return false; + } + } + return true; } -static void write_i2c_retimer_setting( - struct pipe_ctx *pipe_ctx, +static bool write_i2c_retimer_setting( + const struct dc_link *link, bool is_vga_mode, bool is_over_340mhz, struct ext_hdmi_settings *settings) { - uint8_t slave_address = (settings->slv_addr >> 1); - uint8_t buffer[2]; - const uint8_t apply_rx_tx_change = 0x4; - uint8_t offset = 0xA; - uint8_t value = 0; - int i = 0; - bool i2c_success = false; - DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); - - memset(&buffer, 0, sizeof(buffer)); - - /* Start Ext-Hdmi programming*/ - - for (i = 0; i < settings->reg_num; i++) { - /* Apply 3G settings */ - if (settings->reg_settings[i].i2c_reg_index <= 0x20) { - - buffer[0] = settings->reg_settings[i].i2c_reg_index; - buffer[1] = settings->reg_settings[i].i2c_reg_val; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - - if (!i2c_success) - goto i2c_write_fail; + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t address = settings->slv_addr >> 1; - /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A - * needs to be set to 1 on every 0xA-0xC write. - */ - if (settings->reg_settings[i].i2c_reg_index == 0xA || - settings->reg_settings[i].i2c_reg_index == 0xB || - settings->reg_settings[i].i2c_reg_index == 0xC) { - - /* Query current value from offset 0xA */ - if (settings->reg_settings[i].i2c_reg_index == 0xA) - value = settings->reg_settings[i].i2c_reg_val; - else { - i2c_success = - link_query_ddc_data( - pipe_ctx->stream->link->ddc, - slave_address, &offset, 1, &value, 1); - if (!i2c_success) - goto i2c_write_fail; - } + for (size_t i = 0; i < settings->reg_num; i++) { + const uint8_t index = settings->reg_settings[i].i2c_reg_index; + uint8_t value = settings->reg_settings[i].i2c_reg_val; - buffer[0] = offset; - /* Set APPLY_RX_TX_CHANGE bit to 1 */ - buffer[1] = value | apply_rx_tx_change; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - } + if (!write_i2c_retimer_byte(link, address, index, value)) { + DC_LOG_ERROR("Set retimer failed, index: %zu\n", i); + return false; } } - /* Apply 3G settings */ if (is_over_340mhz) { - for (i = 0; i < settings->reg_num_6g; i++) { - /* Apply 3G settings */ - if (settings->reg_settings[i].i2c_reg_index <= 0x20) { - - buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; - buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - - if (!i2c_success) - goto i2c_write_fail; - - /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A - * needs to be set to 1 on every 0xA-0xC write. - */ - if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || - settings->reg_settings_6g[i].i2c_reg_index == 0xB || - settings->reg_settings_6g[i].i2c_reg_index == 0xC) { - - /* Query current value from offset 0xA */ - if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) - value = settings->reg_settings_6g[i].i2c_reg_val; - else { - i2c_success = - link_query_ddc_data( - pipe_ctx->stream->link->ddc, - slave_address, &offset, 1, &value, 1); - if (!i2c_success) - goto i2c_write_fail; - } + for (size_t i = 0; i < settings->reg_num_6g; i++) { + const uint8_t index = settings->reg_settings_6g[i].i2c_reg_index; + uint8_t value = settings->reg_settings_6g[i].i2c_reg_val; - buffer[0] = offset; - /* Set APPLY_RX_TX_CHANGE bit to 1 */ - buffer[1] = value | apply_rx_tx_change; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - } + if (!write_i2c_retimer_byte(link, address, index, value)) { + DC_LOG_ERROR("Set retimer failed, 6g index: %zu\n", i); + return false; } } } if (is_vga_mode) { - /* Program additional settings if using 640x480 resolution */ - - /* Write offset 0xFF to 0x01 */ - buffer[0] = 0xff; - buffer[1] = 0x01; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x00 to 0x23 */ - buffer[0] = 0x00; - buffer[1] = 0x23; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0xff to 0x00 */ - buffer[0] = 0xff; - buffer[1] = 0x00; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - } - - return; - -i2c_write_fail: - DC_LOG_DEBUG("Set retimer failed"); + return write_i2c_retimer_vga(link, address); + } + return true; } -static void write_i2c_default_retimer_setting( - struct pipe_ctx *pipe_ctx, +static bool write_i2c_default_retimer_setting( + const struct dc_link *link, bool is_vga_mode, bool is_over_340mhz) { - uint8_t slave_address = (0xBA >> 1); - uint8_t buffer[2]; - bool i2c_success = false; - DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); + const uint8_t address = 0xBA >> 1; - memset(&buffer, 0, sizeof(buffer)); - - /* Program Slave Address for tuning single integrity */ - /* Write offset 0x0A to 0x13 */ - buffer[0] = 0x0A; - buffer[1] = 0x13; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0A to 0x17 */ - buffer[0] = 0x0A; - buffer[1] = 0x17; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0B to 0xDA or 0xD8 */ - buffer[0] = 0x0B; - buffer[1] = is_over_340mhz ? 0xDA : 0xD8; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0A to 0x17 */ - buffer[0] = 0x0A; - buffer[1] = 0x17; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0C to 0x1D or 0x91 */ - buffer[0] = 0x0C; - buffer[1] = is_over_340mhz ? 0x1D : 0x91; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x0A to 0x17 */ - buffer[0] = 0x0A; - buffer[1] = 0x17; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t data[][2] = { + { 0x0A, 0x13 }, + { 0x0A, 0x17 }, + { 0x0B, is_over_340mhz ? 0xDA : 0xD8 }, + { 0x0A, 0x17 }, + { 0x0C, is_over_340mhz ? 0x1D : 0x91 }, + { 0x0A, 0x17 }, + }; + + for (size_t i = 0; i < ARRAY_SIZE(data); i++) { + if (!write_i2c_retimer_offset_value(link, address, data[i][0], data[i][1])) { + DC_LOG_ERROR("Set default retimer failed, index: %zu\n", i); + return false; + } + } if (is_vga_mode) { - /* Program additional settings if using 640x480 resolution */ - - /* Write offset 0xFF to 0x01 */ - buffer[0] = 0xff; - buffer[1] = 0x01; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0x00 to 0x23 */ - buffer[0] = 0x00; - buffer[1] = 0x23; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - - /* Write offset 0xff to 0x00 */ - buffer[0] = 0xff; - buffer[1] = 0x00; - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ - offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", - slave_address, buffer[0], buffer[1], i2c_success?1:0); - if (!i2c_success) - goto i2c_write_fail; - } - - return; - -i2c_write_fail: - DC_LOG_DEBUG("Set default retimer failed"); + return write_i2c_retimer_vga(link, address); + } + return true; } -static void write_i2c_redriver_setting( - struct pipe_ctx *pipe_ctx, +static bool write_i2c_redriver_setting( + const struct dc_link *link, bool is_over_340mhz) { - uint8_t slave_address = (0xF0 >> 1); - uint8_t buffer[16]; - bool i2c_success = false; - DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); - - memset(&buffer, 0, sizeof(buffer)); - - // Program Slave Address for tuning single integrity - buffer[3] = 0x4E; - buffer[4] = 0x4E; - buffer[5] = 0x4E; - buffer[6] = is_over_340mhz ? 0x4E : 0x4A; - - i2c_success = write_i2c(pipe_ctx, slave_address, - buffer, sizeof(buffer)); - RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ - \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ - offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ - i2c_success = %d\n", - slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); - - if (!i2c_success) - DC_LOG_DEBUG("Set redriver failed"); + DC_LOGGER_INIT(link->ctx->logger); + const uint8_t address = 0xF0 >> 1; + uint8_t buffer[16] = { + [3] = 0x4E, + [4] = 0x4E, + [5] = 0x4E, + [6] = is_over_340mhz ? 0x4E : 0x4A, + }; + + const bool success = write_i2c(link, address, buffer, sizeof(buffer)); + + RETIMER_REDRIVER_INFO( + "Redriver write, address: 0x%x, buffer: { [3]: 0x%x, 0x%x, 0x%x, 0x%x }, success: %d\n", + address, buffer[3], buffer[4], buffer[5], buffer[6], success + ); + + if (!success) + DC_LOG_ERROR("Set redriver failed"); + return success; } static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) @@ -841,7 +705,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; + dsc_cfg.dsc_padding = 0; if (should_use_dto_dscclk) dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); @@ -857,6 +721,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) } dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; dsc_cfg.pic_width *= opp_cnt; + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED; @@ -1329,7 +1194,31 @@ static void remove_stream_from_alloc_table( } } -static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) +static void print_mst_streams(struct dc_link *link) +{ + int i; + + DC_LOGGER_INIT(link->ctx->logger); + + DC_LOG_MST("%s stream_count: %d:\n", + __func__, + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { + DC_LOG_MST("stream_enc[%d]: %p\n", i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc); + DC_LOG_MST("stream[%d].hpo_dp_stream_enc: %p\n", i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc); + DC_LOG_MST("stream[%d].vcp_id: %d\n", i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id); + DC_LOG_MST("stream[%d].slot_count: %d\n", i, + link->mst_stream_alloc_table.stream_allocations[i].slot_count); + } +} + +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART +static enum dc_status deallocate_mst_payload_with_temp_drm_wa( + struct pipe_ctx *pipe_ctx) { struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->link; @@ -1337,10 +1226,90 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); int i; bool mst_mode = (link->type == dc_connection_mst_branch); + /* adjust for drm changes*/ + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + const struct dc_link_settings empty_link_settings = {0}; + DC_LOGGER_INIT(link->ctx->logger); + + if (link_hwss->ext.set_throttled_vcp_size) + link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); + if (link_hwss->ext.set_hblank_min_symbol_width) + link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, + &empty_link_settings, + avg_time_slots_per_mtp); + + if (dm_helpers_dp_mst_write_payload_allocation_table( + stream->ctx, + stream, + &proposed_table, + false)) + update_mst_stream_alloc_table( + link, + pipe_ctx->stream_res.stream_enc, + pipe_ctx->stream_res.hpo_dp_stream_enc, + &proposed_table); + else + DC_LOG_WARNING("Failed to update" + "MST allocation table for" + "pipe idx:%d\n", + pipe_ctx->pipe_idx); + + DC_LOG_MST("%s" + "stream_count: %d: ", + __func__, + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { + DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].hpo_dp_stream_enc: %p " + "stream[%d].vcp_id: %d " + "stream[%d].slot_count: %d\n", + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, + i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id, + i, + link->mst_stream_alloc_table.stream_allocations[i].slot_count); + } + + if (link_hwss->ext.update_stream_allocation_table == NULL || + link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { + DC_LOG_DEBUG("Unknown encoding format\n"); + return DC_ERROR_UNEXPECTED; + } + + link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, + &link->mst_stream_alloc_table); + + if (mst_mode) { + dm_helpers_dp_mst_poll_for_allocation_change_trigger( + stream->ctx, + stream); + } + + dm_helpers_dp_mst_update_mst_mgr_for_deallocation(stream->ctx, stream); + + return DC_OK; +} +#endif + +static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) +{ + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; + struct dc_dp_mst_stream_allocation_table proposed_table = {0}; + struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); + bool mst_mode = (link->type == dc_connection_mst_branch); const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); const struct dc_link_settings empty_link_settings = {0}; DC_LOGGER_INIT(link->ctx->logger); +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (link->dc->debug.temp_mst_deallocation_sequence) + return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); +#endif /* deallocate_mst_payload is called before disable link. When mode or * disable/enable monitor, new stream is created which is not in link * stream[] yet. For this, payload is not allocated yet, so de-alloc @@ -1371,9 +1340,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.hpo_dp_stream_enc, &proposed_table); else - DC_LOG_WARNING("Failed to update" - "MST allocation table for" - "pipe idx:%d\n", + DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", pipe_ctx->pipe_idx); } else { /* when link is no longer in mst mode (mst hub unplugged), @@ -1383,25 +1350,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.hpo_dp_stream_enc); } - DC_LOG_MST("%s" - "stream_count: %d: ", - __func__, - link->mst_stream_alloc_table.stream_count); - - for (i = 0; i < MAX_CONTROLLER_NUM; i++) { - DC_LOG_MST("stream_enc[%d]: %p " - "stream[%d].hpo_dp_stream_enc: %p " - "stream[%d].vcp_id: %d " - "stream[%d].slot_count: %d\n", - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, - i, - link->mst_stream_alloc_table.stream_allocations[i].vcp_id, - i, - link->mst_stream_alloc_table.stream_allocations[i].slot_count); - } + print_mst_streams(link); /* update mst stream allocation table hardware state */ if (link_hwss->ext.update_stream_allocation_table == NULL || @@ -1436,7 +1385,6 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) struct fixed31_32 avg_time_slots_per_mtp; struct fixed31_32 pbn; struct fixed31_32 pbn_per_slot; - int i; enum act_return_status ret; const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); DC_LOGGER_INIT(link->ctx->logger); @@ -1458,30 +1406,10 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) pipe_ctx->stream_res.hpo_dp_stream_enc, &proposed_table); else - DC_LOG_WARNING("Failed to update" - "MST allocation table for" - "pipe idx:%d\n", + DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", pipe_ctx->pipe_idx); - DC_LOG_MST("%s " - "stream_count: %d: \n ", - __func__, - link->mst_stream_alloc_table.stream_count); - - for (i = 0; i < MAX_CONTROLLER_NUM; i++) { - DC_LOG_MST("stream_enc[%d]: %p " - "stream[%d].hpo_dp_stream_enc: %p " - "stream[%d].vcp_id: %d " - "stream[%d].slot_count: %d\n", - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, - i, - link->mst_stream_alloc_table.stream_allocations[i].vcp_id, - i, - link->mst_stream_alloc_table.stream_allocations[i].slot_count); - } + print_mst_streams(link); ASSERT(proposed_table.stream_count > 0); @@ -1746,7 +1674,6 @@ enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in struct fixed31_32 pbn; struct fixed31_32 pbn_per_slot; struct dc_dp_mst_stream_allocation_table proposed_table = {0}; - uint8_t i; const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); DC_LOGGER_INIT(link->ctx->logger); @@ -1780,31 +1707,11 @@ enum dc_status link_reduce_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_in pipe_ctx->stream_res.hpo_dp_stream_enc, &proposed_table); } else { - DC_LOG_WARNING("Failed to update" - "MST allocation table for" - "pipe idx:%d\n", + DC_LOG_WARNING("Failed to update MST allocation table for idx %d\n", pipe_ctx->pipe_idx); } - DC_LOG_MST("%s " - "stream_count: %d: \n ", - __func__, - link->mst_stream_alloc_table.stream_count); - - for (i = 0; i < MAX_CONTROLLER_NUM; i++) { - DC_LOG_MST("stream_enc[%d]: %p " - "stream[%d].hpo_dp_stream_enc: %p " - "stream[%d].vcp_id: %d " - "stream[%d].slot_count: %d\n", - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, - i, - link->mst_stream_alloc_table.stream_allocations[i].vcp_id, - i, - link->mst_stream_alloc_table.stream_allocations[i].slot_count); - } + print_mst_streams(link); ASSERT(proposed_table.stream_count > 0); @@ -1834,7 +1741,6 @@ enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_ struct fixed31_32 pbn; struct fixed31_32 pbn_per_slot; struct dc_dp_mst_stream_allocation_table proposed_table = {0}; - uint8_t i; enum act_return_status ret; const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); DC_LOGGER_INIT(link->ctx->logger); @@ -1853,25 +1759,7 @@ enum dc_status link_increase_mst_payload(struct pipe_ctx *pipe_ctx, uint32_t bw_ &proposed_table); } - DC_LOG_MST("%s " - "stream_count: %d: \n ", - __func__, - link->mst_stream_alloc_table.stream_count); - - for (i = 0; i < MAX_CONTROLLER_NUM; i++) { - DC_LOG_MST("stream_enc[%d]: %p " - "stream[%d].hpo_dp_stream_enc: %p " - "stream[%d].vcp_id: %d " - "stream[%d].slot_count: %d\n", - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, - i, - (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, - i, - link->mst_stream_alloc_table.stream_allocations[i].vcp_id, - i, - link->mst_stream_alloc_table.stream_allocations[i].slot_count); - } + print_mst_streams(link); ASSERT(proposed_table.stream_count > 0); @@ -1930,10 +1818,9 @@ static void disable_link_dp(struct dc_link *link, link->dc->hwss.edp_power_control(link, false); } - if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) + if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->sink_count == 0) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); - if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, link_res, false); @@ -1991,16 +1878,14 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) /* DP159, Retimer settings */ eng_id = pipe_ctx->stream_res.stream_enc->id; - if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { - write_i2c_retimer_setting(pipe_ctx, - is_vga_mode, is_over_340mhz, &settings); + if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) { + write_i2c_retimer_setting(link, is_vga_mode, is_over_340mhz, &settings); } else { - write_i2c_default_retimer_setting(pipe_ctx, - is_vga_mode, is_over_340mhz); + write_i2c_default_retimer_setting(link, is_vga_mode, is_over_340mhz); } } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { /* PI3EQX1204, Redriver settings */ - write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); + write_i2c_redriver_setting(link, is_over_340mhz); } } @@ -2081,7 +1966,12 @@ static enum dc_status enable_link_dp(struct dc_state *state, pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && link->dc->debug.set_mst_en_for_sst) { enable_mst_on_sink(link, true); + } else if (link->dpcd_caps.is_mst_capable && + pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) { + /* disable mst on sink */ + enable_mst_on_sink(link, false); } + if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { /*in case it is not on*/ if (!link->dc->config.edp_no_power_sequencing) @@ -2208,6 +2098,18 @@ static enum dc_status enable_link_dp_mst( return enable_link_dp(state, pipe_ctx); } +static enum dc_status enable_link_analog( + struct dc_state *state, + struct pipe_ctx *pipe_ctx) +{ + struct dc_link *link = pipe_ctx->stream->link; + + link->dc->hwss.enable_analog_link_output( + link, pipe_ctx->stream->timing.pix_clk_100hz); + + return DC_OK; +} + static enum dc_status enable_link_virtual(struct pipe_ctx *pipe_ctx) { struct dc_link *link = pipe_ctx->stream->link; @@ -2263,7 +2165,7 @@ static enum dc_status enable_link( status = DC_OK; break; case SIGNAL_TYPE_RGB: - status = DC_OK; + status = enable_link_analog(state, pipe_ctx); break; case SIGNAL_TYPE_VIRTUAL: status = enable_link_virtual(pipe_ctx); @@ -2367,9 +2269,9 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) if (pipe_ctx->stream->sink) { if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { - DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__, + DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, pipe_ctx->stream->sink->edid_caps.display_name, - pipe_ctx->stream->signal, link->link_index); + pipe_ctx->stream->signal, link->link_index, link->sink_count); } } @@ -2405,15 +2307,13 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) false); if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { /* DP159, Retimer settings */ - if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) - write_i2c_retimer_setting(pipe_ctx, - false, false, &settings); + if (get_ext_hdmi_settings(stream->ctx->dc_bios->integrated_info, eng_id, &settings)) + write_i2c_retimer_setting(link, false, false, &settings); else - write_i2c_default_retimer_setting(pipe_ctx, - false, false); + write_i2c_default_retimer_setting(link, false, false); } else if (masked_chip_caps == AMD_EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { /* PI3EQX1204, Redriver settings */ - write_i2c_redriver_setting(pipe_ctx, false); + write_i2c_redriver_setting(link, false); } } @@ -2483,10 +2383,11 @@ void link_set_dpms_on( if (pipe_ctx->stream->sink) { if (pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_VIRTUAL && pipe_ctx->stream->sink->sink_signal != SIGNAL_TYPE_NONE) { - DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d\n", __func__, + DC_LOG_DC("%s pipe_ctx dispname=%s signal=%x link=%d sink_count=%d\n", __func__, pipe_ctx->stream->sink->edid_caps.display_name, pipe_ctx->stream->signal, - link->link_index); + link->link_index, + link->sink_count); } } @@ -2582,6 +2483,9 @@ void link_set_dpms_on( link_set_dsc_enable(pipe_ctx, true); } + if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal)) + dp_setup_replay(link, stream); + status = enable_link(state, pipe_ctx); if (status != DC_OK) { diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index a6e2b0821969b..9912615d742f8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -41,6 +41,7 @@ #include "protocols/link_dp_phy.h" #include "protocols/link_dp_training.h" #include "protocols/link_edp_panel_control.h" +#include "protocols/link_dp_panel_replay.h" #include "protocols/link_hpd.h" #include "gpio_service_interface.h" #include "atomfirmware.h" @@ -73,7 +74,6 @@ static void construct_link_service_detection(struct link_service *link_srv) link_srv->add_remote_sink = link_add_remote_sink; link_srv->remove_remote_sink = link_remove_remote_sink; link_srv->get_hpd_state = link_get_hpd_state; - link_srv->get_hpd_gpio = link_get_hpd_gpio; link_srv->enable_hpd = link_enable_hpd; link_srv->disable_hpd = link_disable_hpd; link_srv->enable_hpd_filter = link_enable_hpd_filter; @@ -215,7 +215,6 @@ static void construct_link_service_edp_panel_control(struct link_service *link_s link_srv->edp_get_replay_state = edp_get_replay_state; link_srv->edp_set_replay_allow_active = edp_set_replay_allow_active; - link_srv->edp_setup_replay = edp_setup_replay; link_srv->edp_send_replay_cmd = edp_send_replay_cmd; link_srv->edp_set_coasting_vtotal = edp_set_coasting_vtotal; link_srv->edp_replay_residency = edp_replay_residency; @@ -232,6 +231,18 @@ static void construct_link_service_edp_panel_control(struct link_service *link_s link_srv->edp_set_panel_power = edp_set_panel_power; } +/* link dp panel replay implements DP panel replay functionality. + */ +static void construct_link_service_dp_panel_replay(struct link_service *link_srv) +{ + link_srv->dp_setup_replay = dp_setup_replay; + link_srv->dp_pr_get_panel_inst = dp_pr_get_panel_inst; + link_srv->dp_pr_enable = dp_pr_enable; + link_srv->dp_pr_update_state = dp_pr_update_state; + link_srv->dp_pr_set_general_cmd = dp_pr_set_general_cmd; + link_srv->dp_pr_get_state = dp_pr_get_state; +} + /* link dp cts implements dp compliance test automation protocols and manual * testing interfaces for debugging and certification purpose. */ @@ -284,6 +295,7 @@ static void construct_link_service(struct link_service *link_srv) construct_link_service_dp_phy_or_dpia(link_srv); construct_link_service_dp_irq_handler(link_srv); construct_link_service_edp_panel_control(link_srv); + construct_link_service_dp_panel_replay(link_srv); construct_link_service_dp_cts(link_srv); construct_link_service_dp_trace(link_srv); } @@ -350,26 +362,20 @@ static enum transmitter translate_encoder_to_transmitter( return TRANSMITTER_UNKNOWN; } break; + default: + return TRANSMITTER_UNKNOWN; + } +} + +static bool encoder_is_external_dp( + struct graphics_object_id encoder) +{ + switch (encoder.id) { case ENCODER_ID_EXTERNAL_NUTMEG: - switch (encoder.enum_id) { - case ENUM_ID_1: - return TRANSMITTER_NUTMEG_CRT; - default: - return TRANSMITTER_UNKNOWN; - } - break; case ENCODER_ID_EXTERNAL_TRAVIS: - switch (encoder.enum_id) { - case ENUM_ID_1: - return TRANSMITTER_TRAVIS_CRT; - case ENUM_ID_2: - return TRANSMITTER_TRAVIS_LCD; - default: - return TRANSMITTER_UNKNOWN; - } - break; + return true; default: - return TRANSMITTER_UNKNOWN; + return false; } } @@ -377,11 +383,6 @@ static void link_destruct(struct dc_link *link) { int i; - if (link->hpd_gpio) { - dal_gpio_destroy_irq(&link->hpd_gpio); - link->hpd_gpio = NULL; - } - if (link->ddc) link_destroy_ddc_service(&link->ddc); @@ -451,20 +452,19 @@ static enum channel_id get_ddc_line(struct dc_link *link) return channel; } -static enum engine_id find_analog_engine(struct dc_link *link) +static enum engine_id find_analog_engine(struct dc_link *link, struct graphics_object_id *enc) { struct dc_bios *bp = link->ctx->dc_bios; - struct graphics_object_id encoder = {0}; enum bp_result bp_result = BP_RESULT_OK; int i; for (i = 0; i < 3; i++) { - bp_result = bp->funcs->get_src_obj(bp, link->link_id, i, &encoder); + bp_result = bp->funcs->get_src_obj(bp, link->link_id, i, enc); if (bp_result != BP_RESULT_OK) return ENGINE_ID_UNKNOWN; - switch (encoder.id) { + switch (enc->id) { case ENCODER_ID_INTERNAL_DAC1: case ENCODER_ID_INTERNAL_KLDSCP_DAC1: return ENGINE_ID_DACA; @@ -474,17 +474,10 @@ static enum engine_id find_analog_engine(struct dc_link *link) } } + memset(enc, 0, sizeof(*enc)); return ENGINE_ID_UNKNOWN; } -static bool transmitter_supported(const enum transmitter transmitter) -{ - return transmitter != TRANSMITTER_UNKNOWN && - transmitter != TRANSMITTER_NUTMEG_CRT && - transmitter != TRANSMITTER_TRAVIS_CRT && - transmitter != TRANSMITTER_TRAVIS_LCD; -} - static bool analog_engine_supported(const enum engine_id engine_id) { return engine_id == ENGINE_ID_DACA || @@ -502,6 +495,9 @@ static bool construct_phy(struct dc_link *link, struct dc_bios *bios = init_params->dc->ctx->dc_bios; const struct dc_vbios_funcs *bp_funcs = bios->funcs; struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 }; + struct graphics_object_id link_encoder = { 0 }; + enum transmitter transmitter_from_encoder; + enum engine_id link_analog_engine; DC_LOGGER_INIT(dc_ctx->logger); @@ -522,21 +518,28 @@ static bool construct_phy(struct dc_link *link, link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); + link->ep_type = DISPLAY_ENDPOINT_PHY; + + DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id); + /* Determine early if the link has any supported encoders, * so that we avoid initializing DDC and HPD, etc. */ - bp_funcs->get_src_obj(bios, link->link_id, 0, &enc_init_data.encoder); - enc_init_data.transmitter = translate_encoder_to_transmitter(enc_init_data.encoder); - enc_init_data.analog_engine = find_analog_engine(link); + bp_funcs->get_src_obj(bios, link->link_id, 0, &link_encoder); - link->ep_type = DISPLAY_ENDPOINT_PHY; + if (encoder_is_external_dp(link_encoder)) { + /* External DP bridge encoders: find the actual link encoder and use that. */ + link->ext_enc_id = link_encoder; + bp_funcs->get_src_obj(bios, link->ext_enc_id, 0, &link_encoder); + } - DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id); + transmitter_from_encoder = translate_encoder_to_transmitter(link_encoder); + link_analog_engine = find_analog_engine(link, &enc_init_data.analog_encoder); - if (!transmitter_supported(enc_init_data.transmitter) && - !analog_engine_supported(enc_init_data.analog_engine)) { + if (transmitter_from_encoder == TRANSMITTER_UNKNOWN && + !analog_engine_supported(link_analog_engine)) { DC_LOG_WARNING("link_id %d has unsupported encoder\n", link->link_id.id); - goto unsupported_fail; + goto create_fail; } if (bios->funcs->get_disp_connector_caps_info) { @@ -555,25 +558,78 @@ static bool construct_phy(struct dc_link *link, if (link->dc->res_pool->funcs->link_init) link->dc->res_pool->funcs->link_init(link); - link->hpd_gpio = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, - link->ctx->gpio_service); + ddc_service_init_data.ctx = link->ctx; + ddc_service_init_data.id = link->link_id; + ddc_service_init_data.link = link; + link->ddc = link_create_ddc_service(&ddc_service_init_data); - if (link->hpd_gpio) { - dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT); - dal_gpio_unlock_pin(link->hpd_gpio); - link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio); + if (!link->ddc) { + DC_ERROR("Failed to create ddc_service!\n"); + goto ddc_create_fail; + } - DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id); - DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en); + if (!link->ddc->ddc_pin) { + DC_ERROR("Failed to get I2C info for connector!\n"); + goto ddc_create_fail; } + link->ddc_hw_inst = + dal_ddc_get_line(get_ddc_pin(link->ddc)); + + enc_init_data.ctx = dc_ctx; + enc_init_data.connector = link->link_id; + enc_init_data.channel = get_ddc_line(link); + enc_init_data.transmitter = transmitter_from_encoder; + enc_init_data.encoder = link_encoder; + enc_init_data.analog_engine = link_analog_engine; + if (link->ctx->dce_version <= DCN_VERSION_4_01) + enc_init_data.hpd_gpio = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, + link->ctx->gpio_service); + else + enc_init_data.hpd_gpio = NULL; + if (enc_init_data.hpd_gpio) { + dal_gpio_open(enc_init_data.hpd_gpio, GPIO_MODE_INTERRUPT); + dal_gpio_unlock_pin(enc_init_data.hpd_gpio); + link->irq_source_hpd = dal_irq_get_source(enc_init_data.hpd_gpio); + enc_init_data.hpd_source = get_hpd_line(link); + link->hpd_src = enc_init_data.hpd_source; + + DC_LOG_DC("BIOS object table - hpd_gpio id: %d", enc_init_data.hpd_gpio->id); + DC_LOG_DC("BIOS object table - hpd_gpio en: %d", enc_init_data.hpd_gpio->en); + } else { + struct graphics_object_hpd_info hpd_info; + + if (link->ctx->dc_bios->funcs->get_hpd_info(link->ctx->dc_bios, link->link_id, &hpd_info) == BP_RESULT_OK) { + link->hpd_src = hpd_info.hpd_int_gpio_uid - 1; + link->irq_source_hpd = DC_IRQ_SOURCE_HPD1 + link->hpd_src; + enc_init_data.hpd_source = link->hpd_src; + DC_LOG_DC("BIOS object table - hpd_int_gpio_uid id: %d", hpd_info.hpd_int_gpio_uid); + } else { + ASSERT(0); + enc_init_data.hpd_source = HPD_SOURCEID_UNKNOWN; + } + } + + link->link_enc = + link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); + + if (!link->link_enc) { + DC_ERROR("Failed to create link encoder!\n"); + goto link_enc_create_fail; + } + + DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C); + DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE); + switch (link->link_id.id) { case CONNECTOR_ID_HDMI_TYPE_A: link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A; - if (link->hpd_gpio) + if (link->link_enc->hpd_gpio) link->irq_source_read_request = - dal_irq_get_read_request(link->hpd_gpio); + dal_irq_get_read_request(link->link_enc->hpd_gpio); + else if (link->hpd_src != HPD_SOURCEID_UNKNOWN) + link->irq_source_read_request = DC_IRQ_SOURCE_DCI2C_RR_DDC1 + link->hpd_src; break; case CONNECTOR_ID_SINGLE_LINK_DVID: case CONNECTOR_ID_SINGLE_LINK_DVII: @@ -591,9 +647,11 @@ static bool construct_phy(struct dc_link *link, case CONNECTOR_ID_USBC: link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; - if (link->hpd_gpio) + if (link->link_enc->hpd_gpio) link->irq_source_hpd_rx = - dal_irq_get_rx_source(link->hpd_gpio); + dal_irq_get_rx_source(link->link_enc->hpd_gpio); + else if (link->hpd_src != HPD_SOURCEID_UNKNOWN) + link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src; break; case CONNECTOR_ID_EDP: @@ -603,37 +661,45 @@ static bool construct_phy(struct dc_link *link, goto create_fail; link->connector_signal = SIGNAL_TYPE_EDP; + if (!link->dc->config.allow_edp_hotplug_detection + && !is_smartmux_suported(link)) + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; - if (link->hpd_gpio) { - if (!link->dc->config.allow_edp_hotplug_detection - && !is_smartmux_suported(link)) - link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; - - switch (link->dc->config.allow_edp_hotplug_detection) { - case HPD_EN_FOR_ALL_EDP: + switch (link->dc->config.allow_edp_hotplug_detection) { + case HPD_EN_FOR_ALL_EDP: + if (link->link_enc->hpd_gpio) { link->irq_source_hpd_rx = - dal_irq_get_rx_source(link->hpd_gpio); - break; - case HPD_EN_FOR_PRIMARY_EDP_ONLY: - if (link->link_index == 0) + dal_irq_get_rx_source(link->link_enc->hpd_gpio); + } else if (link->hpd_src != HPD_SOURCEID_UNKNOWN) { + link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src; + } + break; + case HPD_EN_FOR_PRIMARY_EDP_ONLY: + if (link->link_index == 0) { + if (link->link_enc->hpd_gpio) { link->irq_source_hpd_rx = - dal_irq_get_rx_source(link->hpd_gpio); - else - link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; - break; - case HPD_EN_FOR_SECONDARY_EDP_ONLY: - if (link->link_index == 1) + dal_irq_get_rx_source(link->link_enc->hpd_gpio); + } else if (link->hpd_src != HPD_SOURCEID_UNKNOWN) { + link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src; + } + } else + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + break; + case HPD_EN_FOR_SECONDARY_EDP_ONLY: + if (link->link_index == 1) { + if (link->link_enc->hpd_gpio) { link->irq_source_hpd_rx = - dal_irq_get_rx_source(link->hpd_gpio); - else - link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; - break; - default: + dal_irq_get_rx_source(link->link_enc->hpd_gpio); + } else if (link->hpd_src != HPD_SOURCEID_UNKNOWN) { + link->irq_source_hpd_rx = DC_IRQ_SOURCE_HPD1RX + link->hpd_src; + } + } else link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; - break; - } + break; + default: + link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; + break; } - break; case CONNECTOR_ID_LVDS: link->connector_signal = SIGNAL_TYPE_LVDS; @@ -644,46 +710,17 @@ static bool construct_phy(struct dc_link *link, goto create_fail; } + /* For external DP bridge encoders: + * Set the connector signal to DisplayPort so that they can work with + * the pre-existing code paths for DP without a lot of code churn. + */ + if (link->ext_enc_id.id != ENCODER_ID_UNKNOWN) + link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; + LINK_INFO("Connector[%d] description: signal: %s\n", init_params->connector_index, signal_type_to_string(link->connector_signal)); - ddc_service_init_data.ctx = link->ctx; - ddc_service_init_data.id = link->link_id; - ddc_service_init_data.link = link; - link->ddc = link_create_ddc_service(&ddc_service_init_data); - - if (!link->ddc) { - DC_ERROR("Failed to create ddc_service!\n"); - goto ddc_create_fail; - } - - if (!link->ddc->ddc_pin) { - DC_ERROR("Failed to get I2C info for connector!\n"); - goto ddc_create_fail; - } - - link->ddc_hw_inst = - dal_ddc_get_line(get_ddc_pin(link->ddc)); - - enc_init_data.ctx = dc_ctx; - enc_init_data.connector = link->link_id; - enc_init_data.channel = get_ddc_line(link); - enc_init_data.hpd_source = get_hpd_line(link); - - link->hpd_src = enc_init_data.hpd_source; - - link->link_enc = - link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); - - if (!link->link_enc) { - DC_ERROR("Failed to create link encoder!\n"); - goto link_enc_create_fail; - } - - DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C); - DC_LOG_DC("BIOS object table - IS_DP2_CAPABLE: %d", link->link_enc->features.flags.bits.IS_DP2_CAPABLE); - /* Update link encoder tracking variables. These are used for the dynamic * assignment of link encoders to streams. */ @@ -724,7 +761,8 @@ static bool construct_phy(struct dc_link *link, link->device_tag.dev_id)) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT && - link->connector_signal != SIGNAL_TYPE_RGB) + link->connector_signal != SIGNAL_TYPE_RGB && + link->ext_enc_id.id == ENCODER_ID_UNKNOWN) continue; if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD && link->connector_signal == SIGNAL_TYPE_RGB) @@ -792,21 +830,17 @@ static bool construct_phy(struct dc_link *link, DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__); return true; device_tag_fail: - link->link_enc->funcs->destroy(&link->link_enc); link_enc_create_fail: - if (link->panel_cntl != NULL) - link->panel_cntl->funcs->destroy(&link->panel_cntl); panel_cntl_create_fail: - link_destroy_ddc_service(&link->ddc); ddc_create_fail: create_fail: + if (link->ddc) + link_destroy_ddc_service(&link->ddc); + if (link->panel_cntl) + link->panel_cntl->funcs->destroy(&link->panel_cntl); + if (link->link_enc) + link->link_enc->funcs->destroy(&link->link_enc); - if (link->hpd_gpio) { - dal_gpio_destroy_irq(&link->hpd_gpio); - link->hpd_gpio = NULL; - } - -unsupported_fail: DC_LOG_DC("BIOS object table - %s failed.\n", __func__); return false; } diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index acdc162de5353..975894d1f0b5c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -144,11 +144,9 @@ static bool dp_active_dongle_validate_timing( return false; } } - if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { - if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index ad90a0106938c..937e390fa4ad1 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -161,7 +161,7 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) uint32_t dp_get_closest_lttpr_offset(uint8_t lttpr_count) { /* Calculate offset for LTTPR closest to DPTX which is highest in the chain - * Offset is 0 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 + * Offset is 1 for single LTTPR cases as base LTTPR DPCD addresses target LTTPR 1 */ return DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE * (lttpr_count - 1); } @@ -743,6 +743,8 @@ static bool decide_dp_link_settings(struct dc_link *link, struct dc_link_setting { struct dc_link_settings initial_link_setting = { LANE_COUNT_ONE, LINK_RATE_LOW, LINK_SPREAD_DISABLED, false, 0}; + if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) + initial_link_setting.link_rate = link->preferred_link_setting.link_rate; struct dc_link_settings current_link_setting = initial_link_setting; uint32_t link_bw; @@ -831,6 +833,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } + bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -1593,6 +1596,41 @@ static bool dpcd_read_sink_ext_caps(struct dc_link *link) return true; } +static void retrieve_vesa_replay_su_info(struct dc_link *link) +{ + uint8_t dpcd_data = 0; + + core_link_read_dpcd(link, + DP_PR_SU_X_GRANULARITY_LOW, + &dpcd_data, + sizeof(dpcd_data)); + link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity = dpcd_data; + + core_link_read_dpcd(link, + DP_PR_SU_X_GRANULARITY_HIGH, + &dpcd_data, + sizeof(dpcd_data)); + link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity |= (dpcd_data << 8); + + core_link_read_dpcd(link, + DP_PR_SU_Y_GRANULARITY, + &dpcd_data, + sizeof(dpcd_data)); + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity = dpcd_data; + + core_link_read_dpcd(link, + DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW, + &dpcd_data, + sizeof(dpcd_data)); + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps = dpcd_data; + + core_link_read_dpcd(link, + DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH, + &dpcd_data, + sizeof(dpcd_data)); + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps |= (dpcd_data << 8); +} + enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link) { uint8_t lttpr_dpcd_data[10] = {0}; @@ -2094,8 +2132,16 @@ static bool retrieve_link_cap(struct dc_link *link) core_link_read_dpcd(link, DP_PANEL_REPLAY_CAPABILITY_SUPPORT, - &link->dpcd_caps.pr_caps_supported.raw, - sizeof(link->dpcd_caps.pr_caps_supported.raw)); + &link->dpcd_caps.vesa_replay_caps_supported.raw, + sizeof(link->dpcd_caps.vesa_replay_caps_supported.raw)); + + core_link_read_dpcd(link, + DP_PANEL_REPLAY_CAPABILITY, + &link->dpcd_caps.vesa_replay_caps.raw, + sizeof(link->dpcd_caps.vesa_replay_caps.raw)); + + /* Read VESA Panel Replay Selective Update caps */ + retrieve_vesa_replay_su_info(link); /* Read DP tunneling information. */ status = dpcd_get_tunneling_device_data(link); @@ -2219,6 +2265,13 @@ void detect_edp_sink_caps(struct dc_link *link) (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate, sizeof(link->dpcd_caps.edp_oled_emission_rate)); + /* + * Read DRR granularity + */ + core_link_read_dpcd(link, DP_SINK_DRR_GRANULARITY, + (uint8_t *)&link->dpcd_caps.drr_granularity, + sizeof(link->dpcd_caps.drr_granularity)); + /* * Read Multi-SST (Single Stream Transport) capability * for eDP version 1.4 or higher. diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c index 9b2f1a7da1d12..766b54631c798 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c @@ -71,7 +71,7 @@ enum dc_status dpcd_get_tunneling_device_data(struct dc_link *link) link->dpcd_caps.usb4_dp_tun_info.dpia_info.raw = dpcd_dp_tun_data[DP_IN_ADAPTER_INFO - DP_TUNNELING_CAPABILITIES_SUPPORT]; link->dpcd_caps.usb4_dp_tun_info.usb4_driver_id = - dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT]; + dpcd_dp_tun_data[DP_USB4_DRIVER_ID - DP_TUNNELING_CAPABILITIES_SUPPORT] & 0x0F; if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc) { status = core_link_read_dpcd(link, USB4_DRIVER_BW_CAPABILITY, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c index 4b01ab0a5a7f0..1860d44f63c1f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c @@ -34,10 +34,12 @@ #include "link_dp_training.h" #include "link_dp_capability.h" #include "link_edp_panel_control.h" +#include "link_dp_panel_replay.h" #include "link/accessories/link_dp_trace.h" #include "link/link_dpms.h" #include "dm_helpers.h" #include "link_dp_dpia_bw.h" +#include "link_dp_panel_replay.h" #define DC_LOGGER \ link->ctx->logger @@ -185,9 +187,46 @@ static bool handle_hpd_irq_psr_sink(struct dc_link *link) return false; } -static void handle_hpd_irq_replay_sink(struct dc_link *link) +static void handle_hpd_irq_vesa_replay_sink(struct dc_link *link) +{ + union pr_error_status pr_error_status = {0}; + + if (!link->replay_settings.replay_feature_enabled || + link->replay_settings.config.replay_version != DC_VESA_PANEL_REPLAY) + return; + + dm_helpers_dp_read_dpcd( + link->ctx, + link, + DP_PR_ERROR_STATUS, + &pr_error_status.raw, + sizeof(pr_error_status.raw)); + + if (pr_error_status.bits.LINK_CRC_ERROR || + pr_error_status.bits.RFB_STORAGE_ERROR || + pr_error_status.bits.VSC_SDP_ERROR || + pr_error_status.bits.ASSDP_MISSING_ERROR) { + + /* Acknowledge and clear error bits */ + dm_helpers_dp_write_dpcd( + link->ctx, + link, + DP_PR_ERROR_STATUS, /*DpcdAddress_PR_Error_Status*/ + &pr_error_status.raw, + sizeof(pr_error_status.raw)); + + /* Replay error, disable and re-enable Replay */ + if (link->replay_settings.replay_allow_active) { + dp_pr_enable(link, false); + dp_pr_enable(link, true); + } + } +} + +static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable) { union dpcd_replay_configuration replay_configuration = {0}; + union dpcd_replay_configuration replay_sink_status = {0}; /*AMD Replay version reuse DP_PSR_ERROR_STATUS for REPLAY_ERROR status.*/ union psr_error_status replay_error_status = {0}; bool ret = false; @@ -196,6 +235,11 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link) if (!link->replay_settings.replay_feature_enabled) return; + if (link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY) { + handle_hpd_irq_vesa_replay_sink(link); + return; + } + while (retries < 10) { ret = dm_helpers_dp_read_dpcd( link->ctx, @@ -222,9 +266,17 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link) &replay_error_status.raw, sizeof(replay_error_status.raw)); + dm_helpers_dp_read_dpcd( + link->ctx, + link, + DP_PR_REPLAY_SINK_STATUS, + &replay_sink_status.raw, + 1); + if (replay_error_status.bits.LINK_CRC_ERROR || replay_configuration.bits.DESYNC_ERROR_STATUS || - replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) { + replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS || + replay_sink_status.bits.SINK_DEVICE_REPLAY_STATUS == 0x7) { bool allow_active; link->replay_settings.config.replay_error_status.raw |= replay_error_status.raw; @@ -256,8 +308,7 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link) if (link->replay_settings.replay_allow_active) { allow_active = false; edp_set_replay_allow_active(link, &allow_active, true, false, NULL); - allow_active = true; - edp_set_replay_allow_active(link, &allow_active, true, false, NULL); + *need_re_enable = true; } } } @@ -417,6 +468,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, union device_service_irq device_service_clear = {0}; enum dc_status result; bool status = false; + bool replay_re_enable_needed = false; if (out_link_loss) *out_link_loss = false; @@ -476,7 +528,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, /* PSR-related error was detected and handled */ return true; - handle_hpd_irq_replay_sink(link); + handle_hpd_irq_replay_sink(link, &replay_re_enable_needed); /* If PSR-related error handled, Main link may be off, * so do not handle as a normal sink status change interrupt. @@ -495,16 +547,16 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, return false; } - /* For now we only handle 'Downstream port status' case. + /* Handle 'Downstream port status' case for all DP link types. * If we got sink count changed it means * Downstream port status changed, * then DM should call DC to do the detection. - * NOTE: Do not handle link loss on eDP since it is internal link + * NOTE: Now includes eDP link loss detection and retraining */ - if ((link->connector_signal != SIGNAL_TYPE_EDP) && - dp_parse_link_loss_status( - link, - &hpd_irq_dpcd_data)) { + + if (dp_parse_link_loss_status( + link, + &hpd_irq_dpcd_data)) { /* Connectivity log: link loss */ CONN_DATA_LINK_LOSS(link, hpd_irq_dpcd_data.raw, @@ -533,6 +585,11 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link, != link->dpcd_sink_count) status = true; + if (replay_re_enable_needed) { + bool allow_active = true; + + edp_set_replay_allow_active(link, &allow_active, true, false, NULL); + } /* reasons for HPD RX: * 1. Link Loss - ie Re-train the Link * 2. MST sideband message diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c new file mode 100644 index 0000000000000..96afce4ffbfa2 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c @@ -0,0 +1,416 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "link_dp_panel_replay.h" +#include "link_edp_panel_control.h" +#include "link_dpcd.h" +#include "dm_helpers.h" +#include "dc/dc_dmub_srv.h" +#include "dce/dmub_replay.h" + +#define DC_LOGGER \ + link->ctx->logger + +#define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B +#define DP_SINK_ENABLE_FRAME_SKIPPING_MODE_SHIFT (5) + +static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz) +{ + // at least 2 frames for static screen + unsigned int num_frames = 2; + + // get number of frames for at least 50ms + if (vsync_rate_hz > 40) + num_frames = (vsync_rate_hz + 10) / 20; + + return num_frames; +} + +static void dp_pr_set_static_screen_param(struct dc_link *link) +{ + struct dc_static_screen_params params = {0}; + struct dc *dc = link->ctx->dc; + // only support DP sst for now + if (!dc_is_dp_sst_signal(link->connector_signal)) + return; + + for (int i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream && + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { + struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; + unsigned int vsync_rate_hz = div64_u64(div64_u64( + (stream->timing.pix_clk_100hz * (u64)100), + stream->timing.v_total), + stream->timing.h_total); + + params.triggers.cursor_update = true; + params.triggers.overlay_update = true; + params.triggers.surface_update = true; + params.num_frames = dp_pr_calc_num_static_frames(vsync_rate_hz); + + dc_stream_set_static_screen_params(dc, &stream, 1, ¶ms); + break; + } + } +} + +static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) +{ + /* To-do: Setup Replay */ + struct dc *dc; + struct dmub_replay *replay; + int i; + unsigned int panel_inst; + struct replay_context replay_context = { 0 }; + unsigned int lineTimeInNs = 0; + + union panel_replay_enable_and_configuration_1 pr_config_1 = { 0 }; + union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 }; + + union dpcd_alpm_configuration alpm_config; + uint8_t data = 0; + + replay_context.controllerId = CONTROLLER_ID_UNDEFINED; + + if (!link) + return false; + + //Clear Panel Replay enable & config + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, + (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, + (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); + + if (!(link->replay_settings.config.replay_supported)) + return false; + + dc = link->ctx->dc; + + //not sure should keep or not + replay = dc->res_pool->replay; + + if (!replay) + return false; + + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) + return false; + + replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; + replay_context.digbe_inst = link->link_enc->transmitter; + replay_context.digfe_inst = link->link_enc->preferred_engine; + + for (i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream + == stream) { + /* dmcu -1 for all controller id values, + * therefore +1 here + */ + replay_context.controllerId = + dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; + break; + } + } + + lineTimeInNs = + ((stream->timing.h_total * 1000000) / + (stream->timing.pix_clk_100hz / 10)) + 1; + + replay_context.line_time_in_ns = lineTimeInNs; + + link->replay_settings.replay_feature_enabled = dp_pr_copy_settings(link, &replay_context); + + if (link->replay_settings.replay_feature_enabled) { + if (dc_is_embedded_signal(link->connector_signal)) { + pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; + pr_config_1.bits.PANEL_REPLAY_CRC_ENABLE = 1; + pr_config_1.bits.IRQ_HPD_ASSDP_MISSING = 1; + pr_config_1.bits.IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR = 1; + pr_config_1.bits.IRQ_HPD_RFB_ERROR = 1; + pr_config_1.bits.IRQ_HPD_ACTIVE_FRAME_CRC_ERROR = 1; + pr_config_1.bits.PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE = 1; + pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1; + } else { + pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; + } + + pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0; + + if (link->dpcd_caps.vesa_replay_caps.bits.SU_Y_GRANULARITY_EXT_CAP_SUPPORTED) + pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 1; + + pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0; + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, + (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, + (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); + + //ALPM Setup + memset(&alpm_config, 0, sizeof(alpm_config)); + alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0; + + if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { + alpm_config.bits.ALPM_MODE_SEL = 1; + alpm_config.bits.ACDS_PERIOD_DURATION = 1; + } + + dm_helpers_dp_write_dpcd( + link->ctx, + link, + DP_RECEIVER_ALPM_CONFIG, + &alpm_config.raw, + sizeof(alpm_config.raw)); + + //Enable frame skipping + if (link->replay_settings.config.frame_skip_supported) + data = data | (1 << DP_SINK_ENABLE_FRAME_SKIPPING_MODE_SHIFT); + + dm_helpers_dp_write_dpcd(link->ctx, link, + DP_SINK_PR_ENABLE_AND_CONFIGURATION, + (uint8_t *)&(data), sizeof(uint8_t)); + } + + return true; +} + + +bool dp_pr_get_panel_inst(const struct dc *dc, + const struct dc_link *link, + unsigned int *inst_out) +{ + if (!dc || !link || !inst_out) + return false; + + if (dc->config.frame_update_cmd_version2 == false) + return dc_get_edp_link_panel_inst(dc, link, inst_out); + + if (!dc_is_dp_sst_signal(link->connector_signal)) /* only supoprt DP sst (eDP included) for now */ + return false; + + for (unsigned int i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream && + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) { + /* *inst_out is equal to otg number */ + if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg) + *inst_out = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst; + else + *inst_out = 0; + + return true; + } + } + + return false; +} + +bool dp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream) +{ + if (!link) + return false; + if (link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) + return dp_setup_panel_replay(link, stream); + else if (link->replay_settings.config.replay_version == DC_FREESYNC_REPLAY) + return edp_setup_freesync_replay(link, stream); + else + return false; +} + +bool dp_pr_enable(struct dc_link *link, bool enable) +{ + struct dc *dc = link->ctx->dc; + unsigned int panel_inst = 0; + union dmub_rb_cmd cmd; + + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) + return false; + + if (link->replay_settings.replay_allow_active == enable) + return true; + + if (enable && !dc_is_embedded_signal(link->connector_signal)) + dp_pr_set_static_screen_param(link); + + // for sending PR enable commands to DMUB + memset(&cmd, 0, sizeof(cmd)); + + cmd.pr_enable.header.type = DMUB_CMD__PR; + cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE; + cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data); + cmd.pr_enable.data.panel_inst = panel_inst; + cmd.pr_enable.data.enable = enable ? 1 : 0; + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + + link->replay_settings.replay_allow_active = enable; + + return true; +} + +bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_context) +{ + struct dc *dc = link->ctx->dc; + unsigned int panel_inst = 0; + union dmub_rb_cmd cmd; + struct pipe_ctx *pipe_ctx = NULL; + + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) + return false; + + for (unsigned int i = 0; i < MAX_PIPES; i++) { + if (dc->current_state->res_ctx.pipe_ctx[i].stream && + dc->current_state->res_ctx.pipe_ctx[i].stream->link && + dc->current_state->res_ctx.pipe_ctx[i].stream->link == link && + dc_is_dp_sst_signal(dc->current_state->res_ctx.pipe_ctx[i].stream->link->connector_signal)) { + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + /* todo: need update for MST */ + break; + } + } + + if (!pipe_ctx) + return false; + + memset(&cmd, 0, sizeof(cmd)); + cmd.pr_copy_settings.header.type = DMUB_CMD__PR; + cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS; + cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data); + cmd.pr_copy_settings.data.panel_inst = panel_inst; + // HW inst + cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst; + cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst; + cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst; + if (pipe_ctx->plane_res.dpp) + cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst; + else + cmd.pr_copy_settings.data.dpp_inst = 0; + if (pipe_ctx->stream_res.tg) + cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst; + else + cmd.pr_copy_settings.data.otg_inst = 0; + + cmd.pr_copy_settings.data.dpphy_inst = link->link_enc->transmitter; + + cmd.pr_copy_settings.data.line_time_in_ns = replay_context->line_time_in_ns; + cmd.pr_copy_settings.data.flags.bitfields.fec_enable_status = (link->fec_state == dc_link_fec_enabled); + cmd.pr_copy_settings.data.flags.bitfields.dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); + cmd.pr_copy_settings.data.debug.u32All = link->replay_settings.config.debug_flags; + + cmd.pr_copy_settings.data.su_granularity_needed = link->dpcd_caps.vesa_replay_caps.bits.PR_SU_GRANULARITY_NEEDED; + cmd.pr_copy_settings.data.su_x_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_x_granularity; + cmd.pr_copy_settings.data.su_y_granularity = link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity; + cmd.pr_copy_settings.data.su_y_granularity_extended_caps = + link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps; + + if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0) + cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable + + pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) / + pipe_ctx->stream->timing.dsc_cfg.num_slices_v; + + if (dc_is_embedded_signal(link->connector_signal)) + cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1C; + else + // For external DP, use option 1-A + cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1A; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + return true; +} + +bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data) +{ + struct dc *dc = link->ctx->dc; + unsigned int panel_inst = 0; + union dmub_rb_cmd cmd; + + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) + return false; + + memset(&cmd, 0, sizeof(cmd)); + memcpy(&cmd.pr_update_state.data, update_state_data, sizeof(struct dmub_cmd_pr_update_state_data)); + + cmd.pr_update_state.header.type = DMUB_CMD__PR; + cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE; + cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data); + cmd.pr_update_state.data.panel_inst = panel_inst; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + return true; +} + +bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data) +{ + struct dc *dc = link->ctx->dc; + unsigned int panel_inst = 0; + union dmub_rb_cmd cmd; + + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) + return false; + + memset(&cmd, 0, sizeof(cmd)); + memcpy(&cmd.pr_general_cmd.data, general_cmd_data, sizeof(struct dmub_cmd_pr_general_cmd_data)); + + cmd.pr_general_cmd.header.type = DMUB_CMD__PR; + cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD; + cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data); + cmd.pr_general_cmd.data.panel_inst = panel_inst; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); + return true; +} + +bool dp_pr_get_state(const struct dc_link *link, uint64_t *state) +{ + const struct dc *dc = link->ctx->dc; + unsigned int panel_inst = 0; + uint32_t retry_count = 0; + uint32_t replay_state = PR_STATE_INVALID; + + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) + return false; + + do { + // Send gpint command and wait for ack + if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst, + &replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) { + // Return invalid state when GPINT times out + replay_state = PR_STATE_INVALID; + } + /* Copy 32-bit result into 64-bit output */ + *state = replay_state; + } while (++retry_count <= 1000 && *state == PR_STATE_INVALID); + + // Assert if max retry hit + if (retry_count >= 1000 && *state == PR_STATE_INVALID) { + ASSERT(0); + /* To-do: Add retry fail log */ + } + + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.h new file mode 100644 index 0000000000000..5522d5911fd13 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.h @@ -0,0 +1,38 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#ifndef __DC_LINK_DP_PANEL_REPLAY_H__ +#define __DC_LINK_DP_PANEL_REPLAY_H__ + +#include "link_service.h" + +bool dp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream); +bool dp_pr_get_panel_inst(const struct dc *dc, const struct dc_link *link, unsigned int *inst_out); +bool dp_pr_enable(struct dc_link *link, bool enable); +bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_context); +bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_data *update_state_data); +bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_data *general_cmd_data); +bool dp_pr_get_state(const struct dc_link *link, uint64_t *state); + +#endif /* __DC_LINK_DP_PANEL_REPLAY_H__ */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h index 58e1544945825..3d70e9bd4a81d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h @@ -48,7 +48,6 @@ void dp_set_drive_settings( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings); - enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 08e2b572e0ff6..2af51afef82ab 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -777,6 +777,7 @@ void override_training_settings( lt_settings->pattern_for_eq = *overrides->pattern_for_eq; if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; + if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c index ce174ce5579c0..6a7c4a59ff4c7 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c @@ -271,7 +271,7 @@ enum link_training_result dp_perform_fixed_vs_pe_training_sequence( rate = get_dpcd_link_rate(<_settings->link_settings); // Only perform toggle if FIXED_VS LTTPR reports no IEEE OUI - if (memcmp("\x0,\x0,\x0", &link->dpcd_caps.lttpr_caps.lttpr_ieee_oui[0], 3) == 0) { + if (memcmp("\x00\x00\x00", &link->dpcd_caps.lttpr_caps.lttpr_ieee_oui[0], 3) == 0) { /* Vendor specific: Toggle link rate */ toggle_rate = (rate == 0x6) ? 0xA : 0x6; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index c56e69eb27efe..4a2699a374b7e 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -39,6 +39,7 @@ #include "dce/dmub_replay.h" #include "abm.h" #include "resource.h" +#include "link_dp_panel_replay.h" #define DC_LOGGER \ link->ctx->logger #define DC_LOGGER_INIT(logger) @@ -91,20 +92,15 @@ void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode) } link->panel_mode = panel_mode; - DC_LOG_DETECTION_DP_CAPS("Link: %d eDP panel mode supported: %d " - "eDP panel mode enabled: %d \n", - link->link_index, - link->dpcd_caps.panel_mode_edp, - panel_mode_edp); + DC_LOG_DETECTION_DP_CAPS("%d eDP panel mode supported: %d, enabled: %d\n", + link->link_index, + link->dpcd_caps.panel_mode_edp, + panel_mode_edp); } enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) { - /* We need to explicitly check that connector - * is not DP. Some Travis_VGA get reported - * by video bios as DP. - */ - if (link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) { + if (link->ext_enc_id.id) { switch (link->dpcd_caps.branch_dev_id) { case DP_BRANCH_DEVICE_ID_0022B9: @@ -124,7 +120,7 @@ enum dp_panel_mode dp_get_panel_mode(struct dc_link *link) } break; case DP_BRANCH_DEVICE_ID_00001A: - /* alternate scrambler reset is required for Travis + /* alternate scrambler reset is required for NUTMEG * for the case when external chip does not provide * sink device id, alternate scrambler scheme will * be overriden later by querying Encoder feature @@ -851,6 +847,7 @@ bool edp_setup_psr(struct dc_link *link, case FAMILY_YELLOW_CARP: case AMDGPU_FAMILY_GC_10_3_6: case AMDGPU_FAMILY_GC_11_0_1: + case AMDGPU_FAMILY_GC_11_5_4: if (dc->debug.disable_z10 || dc->debug.psr_skip_crtc_disable) psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; break; @@ -943,7 +940,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active, if (replay == NULL && force_static) return false; - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; /* Set power optimization flag */ @@ -974,7 +971,7 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state) unsigned int panel_inst; enum replay_state pr_state = REPLAY_STATE_0; - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; if (replay != NULL && link->replay_settings.replay_feature_enabled) @@ -984,117 +981,8 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state) return true; } -static bool edp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream) -{ - /* To-do: Setup Replay */ - struct dc *dc; - struct dmub_replay *replay; - int i; - unsigned int panel_inst; - struct replay_context replay_context = { 0 }; - unsigned int lineTimeInNs = 0; - - union panel_replay_enable_and_configuration_1 pr_config_1 = { 0 }; - union panel_replay_enable_and_configuration_2 pr_config_2 = { 0 }; - - union dpcd_alpm_configuration alpm_config; - - replay_context.controllerId = CONTROLLER_ID_UNDEFINED; - - if (!link) - return false; - - //Clear Panel Replay enable & config - dm_helpers_dp_write_dpcd(link->ctx, link, - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, - (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); - - dm_helpers_dp_write_dpcd(link->ctx, link, - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, - (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); - - if (!(link->replay_settings.config.replay_supported)) - return false; - - dc = link->ctx->dc; - - //not sure should keep or not - replay = dc->res_pool->replay; - - if (!replay) - return false; - - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) - return false; - - replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; - replay_context.digbe_inst = link->link_enc->transmitter; - replay_context.digfe_inst = link->link_enc->preferred_engine; - - for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_state->res_ctx.pipe_ctx[i].stream - == stream) { - /* dmcu -1 for all controller id values, - * therefore +1 here - */ - replay_context.controllerId = - dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; - break; - } - } - - lineTimeInNs = - ((stream->timing.h_total * 1000000) / - (stream->timing.pix_clk_100hz / 10)) + 1; - - replay_context.line_time_in_ns = lineTimeInNs; - - link->replay_settings.replay_feature_enabled = - replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst); - if (link->replay_settings.replay_feature_enabled) { - pr_config_1.bits.PANEL_REPLAY_ENABLE = 1; - pr_config_1.bits.PANEL_REPLAY_CRC_ENABLE = 1; - pr_config_1.bits.IRQ_HPD_ASSDP_MISSING = 1; - pr_config_1.bits.IRQ_HPD_VSCSDP_UNCORRECTABLE_ERROR = 1; - pr_config_1.bits.IRQ_HPD_RFB_ERROR = 1; - pr_config_1.bits.IRQ_HPD_ACTIVE_FRAME_CRC_ERROR = 1; - pr_config_1.bits.PANEL_REPLAY_SELECTIVE_UPDATE_ENABLE = 1; - pr_config_1.bits.PANEL_REPLAY_EARLY_TRANSPORT_ENABLE = 1; - - pr_config_2.bits.SINK_REFRESH_RATE_UNLOCK_GRANTED = 0; - pr_config_2.bits.SU_Y_GRANULARITY_EXT_VALUE_ENABLED = 0; - pr_config_2.bits.SU_REGION_SCAN_LINE_CAPTURE_INDICATION = 0; - - dm_helpers_dp_write_dpcd(link->ctx, link, - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1, - (uint8_t *)&(pr_config_1.raw), sizeof(uint8_t)); - - dm_helpers_dp_write_dpcd(link->ctx, link, - DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2, - (uint8_t *)&(pr_config_2.raw), sizeof(uint8_t)); - - //ALPM Setup - memset(&alpm_config, 0, sizeof(alpm_config)); - alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0; - - if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) { - alpm_config.bits.ALPM_MODE_SEL = 1; - alpm_config.bits.ACDS_PERIOD_DURATION = 1; - } - - dm_helpers_dp_write_dpcd( - link->ctx, - link, - DP_RECEIVER_ALPM_CONFIG, - &alpm_config.raw, - sizeof(alpm_config.raw)); - } - - return true; -} - -static bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream) +bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream) { /* To-do: Setup Replay */ struct dc *dc; @@ -1130,7 +1018,7 @@ static bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stre if (!replay) return false; - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; replay_context.aux_inst = link->ddc->ddc_pin->hw_info.ddc_channel; @@ -1190,17 +1078,6 @@ static bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stre return true; } -bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream) -{ - if (!link) - return false; - if (link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) - return edp_setup_panel_replay(link, stream); - else if (link->replay_settings.config.replay_version == DC_FREESYNC_REPLAY) - return edp_setup_freesync_replay(link, stream); - else - return false; -} /* * This is general Interface for Replay to set an 32 bit variable to dmub @@ -1218,9 +1095,7 @@ bool edp_send_replay_cmd(struct dc_link *link, if (!replay) return false; - DC_LOGGER_INIT(link->ctx->logger); - - if (dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (dp_pr_get_panel_inst(dc, link, &panel_inst)) cmd_data->panel_inst = panel_inst; else { DC_LOG_DC("%s(): get edp panel inst fail ", __func__); @@ -1241,7 +1116,7 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uin if (!replay) return false; - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal || @@ -1261,7 +1136,7 @@ bool edp_replay_residency(const struct dc_link *link, struct dmub_replay *replay = dc->res_pool->replay; unsigned int panel_inst; - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; if (!residency) @@ -1282,7 +1157,7 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, struct dmub_replay *replay = dc->res_pool->replay; unsigned int panel_inst; - if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst)) + if (!dp_pr_get_panel_inst(dc, link, &panel_inst)) return false; /* Only both power and coasting vtotal changed, this func could return true */ @@ -1305,6 +1180,7 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link, return true; } + static struct abm *get_abm_from_stream_res(const struct dc_link *link) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h index dd79c7cd2828d..8fdb76d9953ec 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h @@ -54,8 +54,6 @@ bool edp_set_sink_vtotal_in_psr_active(const struct dc_link *link, void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum psr_residency_mode mode); bool edp_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, bool wait, bool force_static, const unsigned int *power_opts); -bool edp_setup_replay(struct dc_link *link, - const struct dc_stream_state *stream); bool edp_send_replay_cmd(struct dc_link *link, enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_data); @@ -75,6 +73,7 @@ void edp_add_delay_for_T9(struct dc_link *link); bool edp_receiver_ready_T9(struct dc_link *link); bool edp_receiver_ready_T7(struct dc_link *link); bool edp_power_alpm_dpcd_enable(struct dc_link *link, bool enable); +bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_state *stream); void edp_set_panel_power(struct dc_link *link, bool powerOn); void edp_set_panel_assr(struct dc_link *link, struct pipe_ctx *pipe_ctx, enum dp_panel_mode *panel_mode, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c index caa617883f62e..b157d05b67ad2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.c @@ -35,62 +35,75 @@ bool link_get_hpd_state(struct dc_link *link) { - uint32_t state = 0; - - dal_gpio_lock_pin(link->hpd_gpio); - dal_gpio_get_value(link->hpd_gpio, &state); - dal_gpio_unlock_pin(link->hpd_gpio); - - return state; + if (link->link_enc) + return link->link_enc->funcs->get_hpd_state(link->link_enc); + else + return false; } void link_enable_hpd(const struct dc_link *link) { - struct link_encoder *encoder = link->link_enc; - - if (encoder != NULL && encoder->funcs->enable_hpd != NULL) - encoder->funcs->enable_hpd(encoder); + if (link->link_enc) + link->link_enc->funcs->enable_hpd(link->link_enc); } void link_disable_hpd(const struct dc_link *link) { - struct link_encoder *encoder = link->link_enc; - - if (encoder != NULL && encoder->funcs->enable_hpd != NULL) - encoder->funcs->disable_hpd(encoder); + if (link->link_enc) + link->link_enc->funcs->disable_hpd(link->link_enc); } void link_enable_hpd_filter(struct dc_link *link, bool enable) { - struct gpio *hpd; - if (enable) { link->is_hpd_filter_disabled = false; program_hpd_filter(link); } else { link->is_hpd_filter_disabled = true; - /* Obtain HPD handle */ - hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); - - if (!hpd) - return; - - /* Setup HPD filtering */ - if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) { - struct gpio_hpd_config config; + if (link->link_enc) + link->link_enc->funcs->program_hpd_filter(link->link_enc, 0, 0); + } +} - config.delay_on_connect = 0; - config.delay_on_disconnect = 0; +bool program_hpd_filter(const struct dc_link *link) +{ + int delay_on_connect_in_ms = 0; + int delay_on_disconnect_in_ms = 0; - dal_irq_setup_hpd_filter(hpd, &config); + if (link->is_hpd_filter_disabled || !link->link_enc) { + ASSERT(link->link_enc); + return false; + } - dal_gpio_close(hpd); - } else { - ASSERT_CRITICAL(false); - } - /* Release HPD handle */ - dal_gpio_destroy_irq(&hpd); + /* Verify feature is supported */ + switch (link->connector_signal) { + case SIGNAL_TYPE_DVI_SINGLE_LINK: + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_HDMI_TYPE_A: + /* Program hpd filter */ + delay_on_connect_in_ms = 500; + delay_on_disconnect_in_ms = 100; + break; + case SIGNAL_TYPE_DISPLAY_PORT: + case SIGNAL_TYPE_DISPLAY_PORT_MST: + /* Program hpd filter to allow DP signal to settle */ + /* 500: not able to detect MST <-> SST switch as HPD is low for + * only 100ms on DELL U2413 + * 0: some passive dongle still show aux mode instead of i2c + * 20-50: not enough to hide bouncing HPD with passive dongle. + * also see intermittent i2c read issues. + */ + delay_on_connect_in_ms = 80; + delay_on_disconnect_in_ms = 0; + break; + case SIGNAL_TYPE_LVDS: + case SIGNAL_TYPE_EDP: + default: + /* Don't program hpd filter */ + return false; } + + return link->link_enc->funcs->program_hpd_filter(link->link_enc, delay_on_connect_in_ms, delay_on_disconnect_in_ms); } struct gpio *link_get_hpd_gpio(struct dc_bios *dcb, @@ -108,7 +121,6 @@ struct gpio *link_get_hpd_gpio(struct dc_bios *dcb, hpd_info.hpd_int_gpio_uid, &pin_info); if (bp_result != BP_RESULT_OK) { - ASSERT(bp_result == BP_RESULT_NORECORD); return NULL; } @@ -117,21 +129,6 @@ struct gpio *link_get_hpd_gpio(struct dc_bios *dcb, pin_info.mask); } -bool query_hpd_status(struct dc_link *link, uint32_t *is_hpd_high) -{ - struct gpio *hpd_pin = link_get_hpd_gpio( - link->ctx->dc_bios, link->link_id, - link->ctx->gpio_service); - if (!hpd_pin) - return false; - - dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT); - dal_gpio_get_value(hpd_pin, is_hpd_high); - dal_gpio_close(hpd_pin); - dal_gpio_destroy_irq(&hpd_pin); - return true; -} - enum hpd_source_id get_hpd_line(struct dc_link *link) { struct gpio *hpd; @@ -139,8 +136,13 @@ enum hpd_source_id get_hpd_line(struct dc_link *link) hpd_id = HPD_SOURCEID_UNKNOWN; - hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, - link->ctx->gpio_service); + /* Use GPIO path where supported, otherwise use hardware encoder path */ + if (link->ctx && link->ctx->dce_version <= DCN_VERSION_4_01) { + hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, + link->ctx->gpio_service); + } else { + hpd = NULL; + } if (hpd) { switch (dal_irq_get_source(hpd)) { @@ -172,69 +174,3 @@ enum hpd_source_id get_hpd_line(struct dc_link *link) return hpd_id; } - -bool program_hpd_filter(const struct dc_link *link) -{ - bool result = false; - struct gpio *hpd; - int delay_on_connect_in_ms = 0; - int delay_on_disconnect_in_ms = 0; - - if (link->is_hpd_filter_disabled) - return false; - /* Verify feature is supported */ - switch (link->connector_signal) { - case SIGNAL_TYPE_DVI_SINGLE_LINK: - case SIGNAL_TYPE_DVI_DUAL_LINK: - case SIGNAL_TYPE_HDMI_TYPE_A: - /* Program hpd filter */ - delay_on_connect_in_ms = 500; - delay_on_disconnect_in_ms = 100; - break; - case SIGNAL_TYPE_DISPLAY_PORT: - case SIGNAL_TYPE_DISPLAY_PORT_MST: - /* Program hpd filter to allow DP signal to settle */ - /* 500: not able to detect MST <-> SST switch as HPD is low for - * only 100ms on DELL U2413 - * 0: some passive dongle still show aux mode instead of i2c - * 20-50: not enough to hide bouncing HPD with passive dongle. - * also see intermittent i2c read issues. - */ - delay_on_connect_in_ms = 80; - delay_on_disconnect_in_ms = 0; - break; - case SIGNAL_TYPE_LVDS: - case SIGNAL_TYPE_EDP: - default: - /* Don't program hpd filter */ - return false; - } - - /* Obtain HPD handle */ - hpd = link_get_hpd_gpio(link->ctx->dc_bios, link->link_id, - link->ctx->gpio_service); - - if (!hpd) - return result; - - /* Setup HPD filtering */ - if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) { - struct gpio_hpd_config config; - - config.delay_on_connect = delay_on_connect_in_ms; - config.delay_on_disconnect = delay_on_disconnect_in_ms; - - dal_irq_setup_hpd_filter(hpd, &config); - - dal_gpio_close(hpd); - - result = true; - } else { - ASSERT_CRITICAL(false); - } - - /* Release HPD handle */ - dal_gpio_destroy_irq(&hpd); - - return result; -} diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h index af529328ba177..b4e449de960ec 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hpd.h @@ -43,7 +43,6 @@ bool program_hpd_filter(const struct dc_link *link); * Returns true if HPD high. */ bool dpia_query_hpd_status(struct dc_link *link); -bool query_hpd_status(struct dc_link *link, uint32_t *is_hpd_high); bool link_get_hpd_state(struct dc_link *link); struct gpio *link_get_hpd_gpio(struct dc_bios *dcb, struct graphics_object_id link_id, diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile index 2d4b7a85847de..afc376defa0b0 100644 --- a/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -52,3 +52,11 @@ AMD_DAL_MMHUBBUB_DCN35 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn35/,$(MMHUBBUB AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN35) endif +############################################################################### +# DCN42 +############################################################################### +MMHUBBUB_DCN42 = dcn42_mmhubbub.o + +AMD_DAL_MMHUBBUB_DCN42 = $(addprefix $(AMDDALPATH)/dc/mmhubbub/dcn42/,$(MMHUBBUB_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_MMHUBBUB_DCN42) diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c new file mode 100644 index 0000000000000..4700bdc8701df --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn35/dcn35_mmhubbub.h" +#include "dcn42_mmhubbub.h" +#include "reg_helper.h" + +#define REG(reg) \ + ((const struct dcn35_mmhubbub_registers *)(mcif_wb30->mcif_wb_regs)) \ + ->reg + +#define CTX mcif_wb30->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + ((const struct dcn35_mmhubbub_shift *)(mcif_wb30->mcif_wb_shift)) \ + ->field_name, \ + ((const struct dcn35_mmhubbub_mask *)(mcif_wb30->mcif_wb_mask)) \ + ->field_name + +void dcn42_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled) +{ + REG_UPDATE(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, !enabled); +} diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h new file mode 100644 index 0000000000000..0dd1f0d2eb889 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn42/dcn42_mmhubbub.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + + +#ifndef __DCN42_MMHUBBUB_H +#define __DCN42_MMHUBBUB_H + +#include "mcif_wb.h" +#include "dcn32/dcn32_mmhubbub.h" +#include "dcn35/dcn35_mmhubbub.h" + +void dcn42_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled); +#endif // __DCN42_MMHUBBUB_H diff --git a/drivers/gpu/drm/amd/display/dc/mpc/Makefile b/drivers/gpu/drm/amd/display/dc/mpc/Makefile index 5402c3529f5ee..cc23aae3728a1 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/mpc/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -69,4 +69,12 @@ AMD_DAL_MPC_DCN401 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn401/,$(MPC_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN401) +############################################################################### +# DCN42 +############################################################################### +MPC_DCN42 = dcn42_mpc.o + +AMD_DAL_MPC_DCN42 = $(addprefix $(AMDDALPATH)/dc/mpc/dcn42/,$(MPC_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_MPC_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c index b23c64004dd53..27e6532348509 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn10/dcn10_mpc.c @@ -118,9 +118,7 @@ void mpc1_assert_idle_mpcc(struct mpc *mpc, int id) struct mpcc *mpc1_get_mpcc(struct mpc *mpc, int mpcc_id) { - struct dcn10_mpc *mpc10 = TO_DCN10_MPC(mpc); - - ASSERT(mpcc_id < mpc10->num_mpcc); + ASSERT(mpcc_id < TO_DCN10_MPC(mpc)->num_mpcc); return &(mpc->mpcc_array[mpcc_id]); } diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c index 83bbbf34bcac7..badcef027b846 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn32/dcn32_mpc.c @@ -724,8 +724,7 @@ bool mpc32_program_shaper( return false; } - if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) - mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); current_mode = mpc32_get_shaper_current(mpc, mpcc_id); diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c index eeac13fdd6f55..e0617db2d0c1d 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.c @@ -1,5 +1,5 @@ /* - * Copyright 2023 Advanced Micro Devices, Inc. + * Copyright 2023-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -47,6 +47,16 @@ void mpc401_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, MPCC_MCM_3DLUT_FL_SEL, hubp_idx); } +void mpc401_get_3dlut_fast_load_status(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow) +{ + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + REG_GET_3(MPCC_MCM_3DLUT_FAST_LOAD_STATUS[mpcc_id], + MPCC_MCM_3DLUT_FL_DONE, done, + MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, soft_underflow, + MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, hard_underflow); +} + void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id) { struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); @@ -63,56 +73,15 @@ void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_locati } } -static enum dc_lut_mode get3dlut_config( - struct mpc *mpc, - bool *is_17x17x17, - bool *is_12bits_color_channel, - int mpcc_id) -{ - uint32_t i_mode, i_enable_10bits, lut_size; - enum dc_lut_mode mode; - struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); - - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], - MPCC_MCM_3DLUT_MODE_CURRENT, &i_mode); - - REG_GET(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], - MPCC_MCM_3DLUT_30BIT_EN, &i_enable_10bits); - - switch (i_mode) { - case 0: - mode = LUT_BYPASS; - break; - case 1: - mode = LUT_RAM_A; - break; - case 2: - mode = LUT_RAM_B; - break; - default: - mode = LUT_BYPASS; - break; - } - if (i_enable_10bits > 0) - *is_12bits_color_channel = false; - else - *is_12bits_color_channel = true; - - REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_SIZE, &lut_size); - - if (lut_size == 0) - *is_17x17x17 = true; - else - *is_17x17x17 = false; - - return mode; -} - -void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, bool lut_bank_a, int mpcc_id) +void mpc401_populate_lut(struct mpc *mpc, + const enum MCM_LUT_ID id, + const union mcm_lut_params *params, + const bool lut_bank_a, + const int mpcc_id) { const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; - const struct pwl_params *lut1d = params.pwl; - const struct pwl_params *lut_shaper = params.pwl; + const struct pwl_params *lut1d = params->pwl; + const struct pwl_params *lut_shaper = params->pwl; bool is_17x17x17; bool is_12bits_color_channel; const struct dc_rgb *lut0; @@ -121,7 +90,7 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union const struct dc_rgb *lut3; int lut_size0; int lut_size; - const struct tetrahedral_params *lut3d = params.lut3d; + const struct tetrahedral_params *lut3d = params->lut3d; switch (id) { case MCM_LUT_1DLUT: @@ -164,8 +133,6 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mpc32_power_on_shaper_3dlut(mpc, mpcc_id, true); - get3dlut_config(mpc, &is_17x17x17, &is_12bits_color_channel, mpcc_id); - is_17x17x17 = !lut3d->use_tetrahedral_9; is_12bits_color_channel = lut3d->use_12bits; if (is_17x17x17) { @@ -188,8 +155,6 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union sizeof(lut3d->tetrahedral_9.lut1[0]); } - mpc32_select_3dlut_ram(mpc, next_mode, - is_12bits_color_channel, mpcc_id); mpc32_select_3dlut_ram_mask(mpc, 0x1, mpcc_id); if (is_12bits_color_channel) mpc32_set3dlut_ram12(mpc, lut0, lut_size0, mpcc_id); @@ -222,46 +187,69 @@ void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union } +static uint32_t mpc401_cm_lut_size_to_3dlut_size(const enum dc_cm_lut_size cm_size) +{ + uint32_t size = 0; + + switch (cm_size) { + case CM_LUT_SIZE_999: + size = 1; + break; + case CM_LUT_SIZE_171717: + size = 0; + break; + default: + /* invalid LUT size */ + ASSERT(false); + size = 0; + break; + } + + return size; +} + void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const enum MCM_LUT_XABLE xable, - bool lut_bank_a, - int mpcc_id) + const bool enable, + const bool lut_bank_a, + const enum dc_cm_lut_size size, + const int mpcc_id) { + uint32_t lut_size; struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: - switch (xable) { - case MCM_LUT_DISABLE: + if (enable) { + lut_size = mpc401_cm_lut_size_to_3dlut_size(size); + REG_UPDATE_2(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2, + MPCC_MCM_3DLUT_SIZE, lut_size); + } else { + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, 0); - break; - case MCM_LUT_ENABLE: - REG_UPDATE(MPCC_MCM_3DLUT_MODE[mpcc_id], MPCC_MCM_3DLUT_MODE, lut_bank_a ? 1 : 2); - break; } break; case MCM_LUT_SHAPER: - switch (xable) { - case MCM_LUT_DISABLE: - REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0); - break; - case MCM_LUT_ENABLE: + if (enable) { REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); - break; + } else { + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_shaper_3dlut(mpc, mpcc_id, false); + REG_UPDATE(MPCC_MCM_SHAPER_CONTROL[mpcc_id], MPCC_MCM_SHAPER_LUT_MODE, 0); } break; case MCM_LUT_1DLUT: - switch (xable) { - case MCM_LUT_DISABLE: - REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], - MPCC_MCM_1DLUT_MODE, 0); - break; - case MCM_LUT_ENABLE: + if (enable) { REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_MODE, 2); - break; + } else { + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc32_power_on_blnd_lut(mpc, mpcc_id, false); + REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], + MPCC_MCM_1DLUT_MODE, 0); } REG_UPDATE(MPCC_MCM_1DLUT_CONTROL[mpcc_id], MPCC_MCM_1DLUT_SELECT, lut_bank_a ? 0 : 1); @@ -269,14 +257,20 @@ void mpc401_program_lut_mode( } } -void mpc401_program_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id) +void mpc401_program_lut_read_write_control(struct mpc *mpc, + const enum MCM_LUT_ID id, + const bool lut_bank_a, + const unsigned int bit_depth, + const int mpcc_id) { struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); switch (id) { case MCM_LUT_3DLUT: mpc32_select_3dlut_ram_mask(mpc, 0xf, mpcc_id); - REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); + REG_UPDATE_2(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPCC_MCM_3DLUT_30BIT_EN, (bit_depth == 10) ? 1 : 0, + MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); break; case MCM_LUT_SHAPER: mpc32_configure_shaper_lut(mpc, lut_bank_a, mpcc_id); @@ -568,6 +562,44 @@ void mpc401_get_gamut_remap(struct mpc *mpc, arr_reg_val, ARRAY_SIZE(arr_reg_val)); } +void mpc401_get_lut_mode(struct mpc *mpc, + const enum MCM_LUT_ID id, + const int mpcc_id, + bool *enable, + bool *lut_bank_a) +{ + struct dcn401_mpc *mpc401 = TO_DCN401_MPC(mpc); + + uint32_t lut_mode = 0; + uint32_t lut_select = 0; + + *enable = false; + *lut_bank_a = true; + + switch (id) { + case MCM_LUT_SHAPER: + REG_GET(MPCC_MCM_SHAPER_CONTROL[mpcc_id], + MPCC_MCM_SHAPER_MODE_CURRENT, &lut_mode); + *enable = lut_mode != 0; + *lut_bank_a = lut_mode != 2; + break; + case MCM_LUT_1DLUT: + REG_GET_2(MPCC_MCM_1DLUT_CONTROL[mpcc_id], + MPCC_MCM_1DLUT_MODE_CURRENT, &lut_mode, + MPCC_MCM_1DLUT_SELECT_CURRENT, &lut_select); + *enable = lut_mode != 0; + *lut_bank_a = lut_mode == 0 || lut_select == 0; + break; + case MCM_LUT_3DLUT: + default: + REG_GET(MPCC_MCM_3DLUT_MODE[mpcc_id], + MPCC_MCM_3DLUT_MODE_CURRENT, &lut_mode); + *enable = lut_mode != 0; + *lut_bank_a = lut_mode != 2; + break; + } +} + static const struct mpc_funcs dcn401_mpc_funcs = { .read_mpcc_state = mpc1_read_mpcc_state, .insert_plane = mpc1_insert_plane, @@ -602,9 +634,11 @@ static const struct mpc_funcs dcn401_mpc_funcs = { .set_bg_color = mpc1_set_bg_color, .set_movable_cm_location = mpc401_set_movable_cm_location, .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select, + .get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status, .populate_lut = mpc401_populate_lut, .program_lut_read_write_control = mpc401_program_lut_read_write_control, .program_lut_mode = mpc401_program_lut_mode, + .get_lut_mode = mpc401_get_lut_mode, }; diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h index fdc42f8ab3ff5..c16560c84453e 100644 --- a/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn401/dcn401_mpc.h @@ -1,5 +1,5 @@ /* - * Copyright 2023 Advanced Micro Devices, Inc. + * Copyright 2023-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -184,6 +184,7 @@ struct dcn401_mpc_mask { struct dcn401_mpc_registers { MPC_REG_VARIABLE_LIST_DCN4_01 + uint32_t MPCC_CONTROL2[MAX_MPCC]; }; struct dcn401_mpc { @@ -205,21 +206,32 @@ void dcn401_mpc_construct(struct dcn401_mpc *mpc401, int num_rmu); void mpc401_set_movable_cm_location(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); -void mpc401_populate_lut(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, - bool lut_bank_a, int mpcc_id); +void mpc401_populate_lut(struct mpc *mpc, + const enum MCM_LUT_ID id, + const union mcm_lut_params *params, + bool lut_bank_a, + int mpcc_id); void mpc401_program_lut_mode( struct mpc *mpc, const enum MCM_LUT_ID id, - const enum MCM_LUT_XABLE xable, - bool lut_bank_a, - int mpcc_id); + const bool enable, + const bool lut_bank_a, + const enum dc_cm_lut_size size, + const int mpcc_id); + +void mpc401_get_lut_mode(struct mpc *mpc, + const enum MCM_LUT_ID id, + const int mpcc_id, + bool *enable, + bool *lut_bank_a); void mpc401_program_lut_read_write_control( struct mpc *mpc, const enum MCM_LUT_ID id, - bool lut_bank_a, - int mpcc_id); + const bool lut_bank_a, + const unsigned int bit_depth, + const int mpcc_id); void mpc401_set_gamut_remap( struct mpc *mpc, @@ -249,6 +261,13 @@ void mpc_read_gamut_remap(struct mpc *mpc, enum mpcc_gamut_remap_id gamut_remap_block_id, uint32_t *mode_select); +void mpc401_get_3dlut_fast_load_status( + struct mpc *mpc, + int mpcc_id, + uint32_t *done, + uint32_t *soft_underflow, + uint32_t *hard_underflow); + void mpc401_update_3dlut_fast_load_select( struct mpc *mpc, int mpcc_id, diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c new file mode 100644 index 0000000000000..507dbdbea6008 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.c @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" +#include "dc.h" +#include "dcn42_mpc.h" +#include "dcn10/dcn10_cm_common.h" +#include "basics/conversion.h" +#include "mpc.h" + +#define REG(reg)\ + mpc42->mpc_regs->reg + +#define CTX \ + mpc42->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + mpc42->mpc_shift->field_name, mpc42->mpc_mask->field_name + + +void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst) +{ + mpcc->mpcc_id = mpcc_inst; + mpcc->dpp_id = 0xf; + mpcc->mpcc_bot = NULL; + mpcc->blnd_cfg.overlap_only = false; + mpcc->blnd_cfg.global_alpha = 0xfff; + mpcc->blnd_cfg.global_gain = 0xfff; + mpcc->blnd_cfg.background_color_bpc = 4; + mpcc->blnd_cfg.bottom_gain_mode = 0; + mpcc->blnd_cfg.top_gain = 0x1f000; + mpcc->blnd_cfg.bottom_inside_gain = 0x1f000; + mpcc->blnd_cfg.bottom_outside_gain = 0x1f000; + mpcc->sm_cfg.enable = false; + mpcc->shared_bottom = false; +} + +void mpc42_update_blending( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + struct mpcc *mpcc = mpc1_get_mpcc(mpc, mpcc_id); + + REG_UPDATE_5(MPCC_CONTROL[mpcc_id], + MPCC_ALPHA_BLND_MODE, blnd_cfg->alpha_mode, + MPCC_ALPHA_MULTIPLIED_MODE, blnd_cfg->pre_multiplied_alpha, + MPCC_BLND_ACTIVE_OVERLAP_ONLY, blnd_cfg->overlap_only, + MPCC_BG_BPC, blnd_cfg->background_color_bpc, + MPCC_BOT_GAIN_MODE, blnd_cfg->bottom_gain_mode); + REG_UPDATE_2(MPCC_CONTROL2[mpcc_id], + MPCC_GLOBAL_ALPHA, blnd_cfg->global_alpha, + MPCC_GLOBAL_GAIN, blnd_cfg->global_gain); + + REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain); + REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain); + REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain); + + mpcc->blnd_cfg = *blnd_cfg; +} + +/* RMCM Shaper functions */ +void mpc42_power_on_rmcm_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on) +{ + uint32_t power_status_shaper = 2; + uint32_t power_status_3dlut = 2; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + int max_retries = 10; + + REG_SET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], 0, + MPC_RMCM_3DLUT_MEM_PWR_DIS, power_on == true ? 0 : 1); + REG_SET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], 0, + MPC_RMCM_SHAPER_MEM_PWR_DIS, power_on == true ? 0 : 1); + /* wait for memory to fully power up */ + if (power_on && mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) { + REG_WAIT(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_SHAPER_MEM_PWR_STATE, 0, 1, max_retries); + REG_WAIT(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_STATE, 0, 1, max_retries); + } + + /*read status is not mandatory, it is just for debugging*/ + REG_GET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_SHAPER_MEM_PWR_STATE, &power_status_shaper); + REG_GET(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_STATE, &power_status_3dlut); + + if (power_status_shaper != 0 && power_on == true) + BREAK_TO_DEBUGGER(); + + if (power_status_3dlut != 0 && power_on == true) + BREAK_TO_DEBUGGER(); +} + +void mpc42_configure_rmcm_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_id], + MPC_RMCM_SHAPER_SCALE_B, 0x7000); + REG_UPDATE(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_id], + MPC_RMCM_SHAPER_SCALE_G, 0x7000); + REG_UPDATE(MPC_RMCM_SHAPER_SCALE_R[mpcc_id], + MPC_RMCM_SHAPER_SCALE_R, 0x7000); + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7); + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_SEL, is_ram_a == true ? 0:1); + REG_SET(MPC_RMCM_SHAPER_LUT_INDEX[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_INDEX, 0); +} + +void mpc42_program_rmcm_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + const struct gamma_curve *curve; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); + + curve = params->arr_curve_points; + if (curve) { + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_0_1[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_2_3[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_4_5[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_6_7[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_8_9[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_10_11[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_12_13[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_14_15[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_16_17[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_18_19[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_20_21[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_22_23[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_24_25[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_26_27[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_28_29[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_30_31[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMA_REGION_32_33[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } +} + + +void mpc42_program_rmcm_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id) +{ + const struct gamma_curve *curve; + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].green.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_START_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, params->corner_points[0].red.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, 0); + + REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_B[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].blue.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].blue.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_G[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].green.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].green.custom_float_y); + REG_SET_2(MPC_RMCM_SHAPER_RAMB_END_CNTL_R[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, params->corner_points[1].red.custom_float_x, + MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, params->corner_points[1].red.custom_float_y); + + curve = params->arr_curve_points; + if (curve) { + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_0_1[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_2_3[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_4_5[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_6_7[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_8_9[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_10_11[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_12_13[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_14_15[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_16_17[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_18_19[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_20_21[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_22_23[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_24_25[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_26_27[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_28_29[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_30_31[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + + curve += 2; + REG_SET_4(MPC_RMCM_SHAPER_RAMB_REGION_32_33[mpcc_id], 0, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset, + MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num); + } +} + +void mpc42_program_rmcm_shaper_lut( + struct mpc *mpc, + const struct pwl_result_data *rgb, + uint32_t num, + uint32_t mpcc_id) +{ + uint32_t i, red, green, blue; + uint32_t red_delta, green_delta, blue_delta; + uint32_t red_value, green_value, blue_value; + + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + for (i = 0; i < num; i++) { + + red = rgb[i].red_reg; + green = rgb[i].green_reg; + blue = rgb[i].blue_reg; + + red_delta = rgb[i].delta_red_reg; + green_delta = rgb[i].delta_green_reg; + blue_delta = rgb[i].delta_blue_reg; + + red_value = ((red_delta & 0x3ff) << 14) | (red & 0x3fff); + green_value = ((green_delta & 0x3ff) << 14) | (green & 0x3fff); + blue_value = ((blue_delta & 0x3ff) << 14) | (blue & 0x3fff); + + REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, red_value); + REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, green_value); + REG_SET(MPC_RMCM_SHAPER_LUT_DATA[mpcc_id], 0, MPC_RMCM_SHAPER_LUT_DATA, blue_value); + } +} + +void mpc42_enable_3dlut_fl(struct mpc *mpc, bool enable, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + //if enabled cho0se mpc 0, else: off (default value) + REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, enable ? 0 : 0xF); //0xF is not connected + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPC_RMCM_3DLUT_WRITE_EN_MASK, 0); + + REG_UPDATE(MPC_RMCM_MEM_PWR_CTRL[mpcc_id], MPC_RMCM_3DLUT_MEM_PWR_DIS, enable ? 0 : 3); +} + +void mpc42_update_3dlut_fast_load_select(struct mpc *mpc, int mpcc_id, int hubp_idx) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_SET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, + MPC_RMCM_3DLUT_FL_SEL, + hubp_idx); +} + +void mpc42_populate_rmcm_lut(struct mpc *mpc, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id) +{ + const enum dc_lut_mode next_mode = lut_bank_a ? LUT_RAM_A : LUT_RAM_B; + const struct pwl_params *lut_shaper = params.pwl; + + if (lut_shaper == NULL) + return; + if (mpc->ctx->dc->debug.enable_mem_low_power.bits.mpc) + mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, true); + + mpc42_configure_rmcm_shaper_lut(mpc, next_mode == LUT_RAM_A, mpcc_id); + + if (next_mode == LUT_RAM_A) + mpc42_program_rmcm_shaper_luta_settings(mpc, lut_shaper, mpcc_id); + else + mpc42_program_rmcm_shaper_lutb_settings(mpc, lut_shaper, mpcc_id); + + mpc42_program_rmcm_shaper_lut( + mpc, lut_shaper->rgb_resulted, lut_shaper->hw_points_num, mpcc_id); + + mpc42_power_on_rmcm_shaper_3dlut(mpc, mpcc_id, false); +} + +void mpc42_program_rmcm_lut_read_write_control(struct mpc *mpc, const enum MCM_LUT_ID id, + bool lut_bank_a, bool enabled, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + switch (id) { + case MCM_LUT_3DLUT: + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], MPC_RMCM_3DLUT_MODE, + (!enabled) ? 0 : + (lut_bank_a) ? 1 : 2); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_RAM_SEL, + (lut_bank_a) ? 0 : 1); + break; + case MCM_LUT_SHAPER: + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, 7); + + REG_UPDATE(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_id], + MPC_RMCM_SHAPER_LUT_WRITE_SEL, + lut_bank_a == true ? 0:1); + + REG_SET(MPC_RMCM_SHAPER_LUT_INDEX[mpcc_id], 0, + MPC_RMCM_SHAPER_LUT_INDEX, 0); + break; + default: + break; + } +} + +void mpc42_program_lut_mode(struct mpc *mpc, + bool enable, + bool lut_bank_a, + int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + if (enable) { + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, lut_bank_a ? 1 : 2); + } else { + REG_UPDATE(MPC_RMCM_SHAPER_CONTROL[mpcc_id], MPC_RMCM_SHAPER_LUT_MODE, 0); + } +} + +static uint32_t mpc42_get_rmcm_3dlut_width( + const enum dc_cm_lut_size size) +{ + uint32_t width = 0; + + switch (size) { + case CM_LUT_SIZE_333333: + width = 2; + break; + case CM_LUT_SIZE_171717: + default: + width = 0; + break; + } + + return width; +} + +void mpc42_program_rmcm_3dlut_size(struct mpc *mpc, + const enum dc_cm_lut_size size, + int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + uint32_t width = mpc42_get_rmcm_3dlut_width(size); + + REG_UPDATE(MPC_RMCM_3DLUT_MODE[mpcc_id], + MPC_RMCM_3DLUT_SIZE, width); +} + +void mpc42_program_rmcm_3dlut_fast_load_bias_scale(struct mpc *mpc, uint16_t bias, uint16_t scale, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_R, bias, + MPC_RMCM_3DLUT_OUT_SCALE_R, scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_G, bias, + MPC_RMCM_3DLUT_OUT_SCALE_G, scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_B, bias, + MPC_RMCM_3DLUT_OUT_SCALE_B, scale); +} + +void mpc42_program_rmcm_bit_depth(struct mpc *mpc, uint16_t bit_depth, int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPC_RMCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_30BIT_EN, + (bit_depth == 10) ? 1 : 0); +} + +void mpc42_set_fl_config( + struct mpc *mpc, + struct mpc_fl_3dlut_config *cfg, + int mpcc_id) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + uint32_t width = mpc42_get_rmcm_3dlut_width(cfg->size); + /* + From: Jie Zhou + + To program any of the memories content. The following sequence is used. + Set the MPCC_OGAM/SHAPER/3DLUT/1DLUT_PWR_DIS to 1 (Only need to set the one + that is being programmed) Set DISPCLK_G_PIPE_GATE_DISABLE to 1 for the + MPCC pipe that’s being used, so the memory’s clock is ungated. Program the + target memory. Set the MPCC_OGAM/SHAPER/3DLUT/1DLUT_PWR_DIS back to 0. + Set DISPCLK_G_PIPE_GATE_DISABLE back to 0 + */ + + //disconnect fl from mpc + REG_SET(MPCC_MCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, + MPCC_MCM_3DLUT_FL_SEL, 0xF); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_WRITE_EN_MASK, 0xF); + + //program bit_depth + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_30BIT_EN, (cfg->bit_depth == 10) ? 1 : 0); + + REG_UPDATE(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], + MPC_RMCM_3DLUT_RAM_SEL, (cfg->select_lut_bank_a) ? 0 : 1); + + //bias and scale + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_R, cfg->bias, + MPC_RMCM_3DLUT_OUT_SCALE_R, cfg->scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_G[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_G, cfg->bias, + MPC_RMCM_3DLUT_OUT_SCALE_G, cfg->scale); + + REG_UPDATE_2(MPC_RMCM_3DLUT_OUT_OFFSET_B[mpcc_id], + MPC_RMCM_3DLUT_OUT_OFFSET_B, cfg->bias, + MPC_RMCM_3DLUT_OUT_SCALE_B, cfg->scale); + + //width + REG_UPDATE_2(MPC_RMCM_3DLUT_MODE[mpcc_id], + MPC_RMCM_3DLUT_SIZE, width, + MPC_RMCM_3DLUT_MODE, (!cfg->enabled) ? 0 : (cfg->select_lut_bank_a) ? 1 : 2); + + //connect to hubp + REG_SET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_id], 0, + MPC_RMCM_3DLUT_FL_SEL, cfg->hubp_index); + + //ENABLE + //if enabled pick mpc 0, else: off (0xF) + //in future we'll select specific MPC + REG_UPDATE(MPC_RMCM_CNTL[mpcc_id], MPC_RMCM_CNTL, cfg->enabled ? 0 : 0xF); +} + +void mpc42_read_mpcc_state( + struct mpc *mpc, + int mpcc_inst, + struct mpcc_state *s) +{ + struct dcn42_mpc *mpc42 = TO_DCN42_MPC(mpc); + + mpc1_read_mpcc_state(mpc, mpcc_inst, s); + + if (mpcc_inst < 2) { + /* RMCM 3DLUT Status */ + REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_3DLUT_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_force, + MPC_RMCM_3DLUT_MEM_PWR_DIS, &s->rmcm_regs.rmcm_3dlut_mem_pwr_dis, + MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_mode, + MPC_RMCM_3DLUT_MEM_PWR_STATE, &s->rmcm_regs.rmcm_3dlut_mem_pwr_state); + + REG_GET_3(MPC_RMCM_3DLUT_MODE[mpcc_inst], MPC_RMCM_3DLUT_SIZE, &s->rmcm_regs.rmcm_3dlut_size, + MPC_RMCM_3DLUT_MODE, &s->rmcm_regs.rmcm_3dlut_mode, + MPC_RMCM_3DLUT_MODE_CURRENT, &s->rmcm_regs.rmcm_3dlut_mode_cur); + + REG_GET_4(MPC_RMCM_3DLUT_READ_WRITE_CONTROL[mpcc_inst], MPC_RMCM_3DLUT_READ_SEL, &s->rmcm_regs.rmcm_3dlut_read_sel, + MPC_RMCM_3DLUT_30BIT_EN, &s->rmcm_regs.rmcm_3dlut_30bit_en, + MPC_RMCM_3DLUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_3dlut_wr_en_mask, + MPC_RMCM_3DLUT_RAM_SEL, &s->rmcm_regs.rmcm_3dlut_ram_sel); + + REG_GET(MPC_RMCM_3DLUT_OUT_NORM_FACTOR[mpcc_inst], MPC_RMCM_3DLUT_OUT_NORM_FACTOR, &s->rmcm_regs.rmcm_3dlut_out_norm_factor); + + REG_GET(MPC_RMCM_3DLUT_FAST_LOAD_SELECT[mpcc_inst], MPC_RMCM_3DLUT_FL_SEL, &s->rmcm_regs.rmcm_3dlut_fl_sel); + + REG_GET_2(MPC_RMCM_3DLUT_OUT_OFFSET_R[mpcc_inst], MPC_RMCM_3DLUT_OUT_OFFSET_R, &s->rmcm_regs.rmcm_3dlut_out_offset_r, + MPC_RMCM_3DLUT_OUT_SCALE_R, &s->rmcm_regs.rmcm_3dlut_out_scale_r); + + REG_GET_3(MPC_RMCM_3DLUT_FAST_LOAD_STATUS[mpcc_inst], MPC_RMCM_3DLUT_FL_DONE, &s->rmcm_regs.rmcm_3dlut_fl_done, + MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW, &s->rmcm_regs.rmcm_3dlut_fl_soft_underflow, + MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW, &s->rmcm_regs.rmcm_3dlut_fl_hard_underflow); + + /* RMCM Shaper Status */ + REG_GET_4(MPC_RMCM_MEM_PWR_CTRL[mpcc_inst], MPC_RMCM_SHAPER_MEM_PWR_FORCE, &s->rmcm_regs.rmcm_shaper_mem_pwr_force, + MPC_RMCM_SHAPER_MEM_PWR_DIS, &s->rmcm_regs.rmcm_shaper_mem_pwr_dis, + MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE, &s->rmcm_regs.rmcm_shaper_mem_pwr_mode, + MPC_RMCM_SHAPER_MEM_PWR_STATE, &s->rmcm_regs.rmcm_shaper_mem_pwr_state); + + REG_GET_2(MPC_RMCM_SHAPER_CONTROL[mpcc_inst], MPC_RMCM_SHAPER_LUT_MODE, &s->rmcm_regs.rmcm_shaper_lut_mode, + MPC_RMCM_SHAPER_MODE_CURRENT, &s->rmcm_regs.rmcm_shaper_mode_cur); + + REG_GET_2(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[mpcc_inst], MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, &s->rmcm_regs.rmcm_shaper_lut_write_en_mask, + MPC_RMCM_SHAPER_LUT_WRITE_SEL, &s->rmcm_regs.rmcm_shaper_lut_write_sel); + + REG_GET(MPC_RMCM_SHAPER_OFFSET_B[mpcc_inst], MPC_RMCM_SHAPER_OFFSET_B, &s->rmcm_regs.rmcm_shaper_offset_b); + + REG_GET(MPC_RMCM_SHAPER_SCALE_G_B[mpcc_inst], MPC_RMCM_SHAPER_SCALE_B, &s->rmcm_regs.rmcm_shaper_scale_b); + + REG_GET_2(MPC_RMCM_SHAPER_RAMA_START_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_b, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_start_seg_b); + + REG_GET_2(MPC_RMCM_SHAPER_RAMA_END_CNTL_B[mpcc_inst], MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_b, + MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, &s->rmcm_regs.rmcm_shaper_rama_exp_region_end_base_b); + + REG_GET(MPC_RMCM_CNTL[mpcc_inst], MPC_RMCM_CNTL, &s->rmcm_regs.rmcm_cntl); + } +} + +static const struct mpc_funcs dcn42_mpc_funcs = { + .read_mpcc_state = mpc42_read_mpcc_state, + .insert_plane = mpc1_insert_plane, + .remove_mpcc = mpc1_remove_mpcc, + .mpc_init = mpc32_mpc_init, + .mpc_init_single_inst = mpc3_mpc_init_single_inst, + .update_blending = mpc42_update_blending, + .cursor_lock = mpc1_cursor_lock, + .get_mpcc_for_dpp = mpc1_get_mpcc_for_dpp, + .wait_for_idle = mpc2_assert_idle_mpcc, + .assert_mpcc_idle_before_connect = mpc2_assert_mpcc_idle_before_connect, + .init_mpcc_list_from_hw = mpc1_init_mpcc_list_from_hw, + .set_denorm = mpc3_set_denorm, + .set_denorm_clamp = mpc3_set_denorm_clamp, + .set_output_csc = mpc3_set_output_csc, + .set_ocsc_default = mpc3_set_ocsc_default, + .set_output_gamma = mpc3_set_output_gamma, + .set_dwb_mux = mpc3_set_dwb_mux, + .disable_dwb_mux = mpc3_disable_dwb_mux, + .is_dwb_idle = mpc3_is_dwb_idle, + .set_gamut_remap = mpc401_set_gamut_remap, + .program_shaper = mpc32_program_shaper, + .program_3dlut = mpc32_program_3dlut, + .program_1dlut = mpc32_program_post1dlut, + .power_on_mpc_mem_pwr = mpc3_power_on_ogam_lut, + .get_mpc_out_mux = mpc1_get_mpc_out_mux, + .mpc_read_reg_state = mpc3_read_reg_state, + .set_bg_color = mpc1_set_bg_color, + .set_movable_cm_location = mpc401_set_movable_cm_location, + .update_3dlut_fast_load_select = mpc401_update_3dlut_fast_load_select, + .get_3dlut_fast_load_status = mpc401_get_3dlut_fast_load_status, + .populate_lut = mpc401_populate_lut, + .program_lut_read_write_control = mpc401_program_lut_read_write_control, + .program_lut_mode = mpc401_program_lut_mode, + .get_lut_mode = mpc401_get_lut_mode, + .rmcm = { + .enable_3dlut_fl = mpc42_enable_3dlut_fl, + .update_3dlut_fast_load_select = mpc42_update_3dlut_fast_load_select, + .program_lut_read_write_control = mpc42_program_rmcm_lut_read_write_control, + .program_lut_mode = mpc42_program_lut_mode, + .program_3dlut_size = mpc42_program_rmcm_3dlut_size, + .program_bias_scale = mpc42_program_rmcm_3dlut_fast_load_bias_scale, + .program_bit_depth = mpc42_program_rmcm_bit_depth, + .power_on_shaper_3dlut = mpc42_power_on_rmcm_shaper_3dlut, + .populate_lut = mpc42_populate_rmcm_lut, + .fl_3dlut_configure = mpc42_set_fl_config, + }, +}; + +void dcn42_mpc_construct(struct dcn42_mpc *mpc42, + struct dc_context *ctx, + const struct dcn42_mpc_registers *mpc_regs, + const struct dcn42_mpc_shift *mpc_shift, + const struct dcn42_mpc_mask *mpc_mask, + int num_mpcc, + int num_rmu) +{ + int i; + + mpc42->base.ctx = ctx; + + mpc42->base.funcs = &dcn42_mpc_funcs; + + mpc42->mpc_regs = mpc_regs; + mpc42->mpc_shift = mpc_shift; + mpc42->mpc_mask = mpc_mask; + + mpc42->mpcc_in_use_mask = 0; + mpc42->num_mpcc = num_mpcc; + mpc42->num_rmu = num_rmu; + + for (i = 0; i < MAX_MPCC; i++) + mpc42_init_mpcc(&mpc42->base.mpcc_array[i], i); +} diff --git a/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h new file mode 100644 index 0000000000000..a5f7f4f2bb3bc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/mpc/dcn42/dcn42_mpc.h @@ -0,0 +1,962 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef __DC_MPCC_DCN42_H__ +#define __DC_MPCC_DCN42_H__ + +#include "dcn401/dcn401_mpc.h" + +#define TO_DCN42_MPC(mpc_base) \ + container_of(mpc_base, struct dcn42_mpc, base) + +#define MPC_COMMON_MASK_SH_LIST_DCN42(mask_sh) \ + SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ + SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ + SF(MPCC0_MPCC_CONTROL2, MPCC_GLOBAL_ALPHA, mask_sh),\ + SF(MPCC0_MPCC_CONTROL2, MPCC_GLOBAL_GAIN, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ + SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ + SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ + SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ + SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ + SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\ + SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BG_BPC, mask_sh),\ + SF(MPCC0_MPCC_CONTROL, MPCC_BOT_GAIN_MODE, mask_sh),\ + SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\ + SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\ + SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL, mask_sh),\ + SF(MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL, MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, mask_sh),\ + SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\ + SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\ + SF(MPCC0_MPCC_STATUS, MPCC_DISABLED, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_DIS, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC0_MPCC_MEM_PWR_CTRL, MPCC_OGAM_MEM_PWR_STATE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_MODE, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MAX_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CONTROL, MPC_OUT_DENORM_CLAMP_MIN_R_CR, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MAX_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_G_Y, MPC_OUT_DENORM_CLAMP_MIN_G_Y, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\ + SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE, MPCC_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT, MPCC_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C11_A, mask_sh),\ + SF(MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A, MPCC_GAMUT_REMAP_C12_A, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX, mask_sh),\ + SF(MPC_DWB0_MUX, MPC_DWB0_MUX_STATUS, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_RATE_CONTROL_DISABLE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_MODE, mask_sh),\ + SF(MPC_OUT0_MUX, MPC_OUT_FLOW_CONTROL_COUNT, mask_sh), \ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1, MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B, MPCC_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B, MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B, MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B, MPCC_OGAM_RAMA_OFFSET_B, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G, MPCC_OGAM_RAMA_OFFSET_G, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R, MPCC_OGAM_RAMA_OFFSET_R, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_INDEX, MPCC_OGAM_LUT_INDEX, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_PWL_DISABLE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_MODE_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_CONTROL, MPCC_OGAM_SELECT_CURRENT, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_HOST_SEL, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL, MPCC_OGAM_LUT_CONFIG_MODE, mask_sh),\ + SF(MPCC_OGAM0_MPCC_OGAM_LUT_DATA, MPCC_OGAM_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_SIZE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_MODE, MPCC_MCM_3DLUT_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_WRITE_EN_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_30BIT_EN, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_READ_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_INDEX, MPCC_MCM_3DLUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA0, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA, MPCC_MCM_3DLUT_DATA1, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT, MPCC_MCM_3DLUT_DATA_30BIT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_LUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL, MPCC_MCM_SHAPER_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R, MPCC_MCM_SHAPER_OFFSET_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G, MPCC_MCM_SHAPER_OFFSET_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B, MPCC_MCM_SHAPER_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R, MPCC_MCM_SHAPER_SCALE_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B, MPCC_MCM_SHAPER_SCALE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX, MPCC_MCM_SHAPER_LUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA, MPCC_MCM_SHAPER_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, MPCC_MCM_SHAPER_LUT_WRITE_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B, MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1, MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_SELECT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_PWL_DISABLE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_MODE_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL, MPCC_MCM_1DLUT_SELECT_CURRENT, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX, MPCC_MCM_1DLUT_LUT_INDEX, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA, MPCC_MCM_1DLUT_LUT_DATA, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_HOST_SEL, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL, MPCC_MCM_1DLUT_LUT_CONFIG_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B, MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B, MPCC_MCM_1DLUT_RAMA_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1, MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_SHAPER_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_3DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL, MPCC_MCM_1DLUT_MEM_PWR_STATE, mask_sh),\ + SF(CUR_VUPDATE_LOCK_SET0, CUR_VUPDATE_LOCK_SET, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE, MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C11_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A, MPCC_MCM_FIRST_GAMUT_REMAP_C12_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C13_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A, MPCC_MCM_FIRST_GAMUT_REMAP_C14_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C21_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A, MPCC_MCM_FIRST_GAMUT_REMAP_C22_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C23_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A, MPCC_MCM_FIRST_GAMUT_REMAP_C24_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C31_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A, MPCC_MCM_FIRST_GAMUT_REMAP_C32_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C33_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A, MPCC_MCM_FIRST_GAMUT_REMAP_C34_A, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE, MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C11_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A, MPCC_MCM_SECOND_GAMUT_REMAP_C12_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C13_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A, MPCC_MCM_SECOND_GAMUT_REMAP_C14_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C21_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A, MPCC_MCM_SECOND_GAMUT_REMAP_C22_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C23_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A, MPCC_MCM_SECOND_GAMUT_REMAP_C24_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C31_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A, MPCC_MCM_SECOND_GAMUT_REMAP_C32_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C33_A, mask_sh), \ + SF(MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A, MPCC_MCM_SECOND_GAMUT_REMAP_C34_A, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT, MPCC_MCM_3DLUT_FL_SEL, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_DONE, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS, MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh), \ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM_3DLUT_OUT_OFFSET_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R, MPCC_MCM_3DLUT_OUT_SCALE_R, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM_3DLUT_OUT_OFFSET_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G, MPCC_MCM_3DLUT_OUT_SCALE_G, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM_3DLUT_OUT_OFFSET_B, mask_sh),\ + SF(MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B, MPCC_MCM_3DLUT_OUT_SCALE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL, MPC_RMCM_SHAPER_LUT_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL, MPC_RMCM_SHAPER_MODE_CURRENT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R, MPC_RMCM_SHAPER_OFFSET_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G, MPC_RMCM_SHAPER_OFFSET_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B, MPC_RMCM_SHAPER_OFFSET_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R, MPC_RMCM_SHAPER_SCALE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM_SHAPER_SCALE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM_SHAPER_SCALE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX, MPC_RMCM_SHAPER_LUT_INDEX, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA, MPC_RMCM_SHAPER_LUT_DATA, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM_SHAPER_LUT_WRITE_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_MODE, MPC_RMCM_3DLUT_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_MODE, MPC_RMCM_3DLUT_SIZE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_MODE, MPC_RMCM_3DLUT_MODE_CURRENT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_INDEX, MPC_RMCM_3DLUT_INDEX, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_DATA, MPC_RMCM_3DLUT_DATA0, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_DATA, MPC_RMCM_3DLUT_DATA1, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT, MPC_RMCM_3DLUT_DATA_30BIT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_WRITE_EN_MASK, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_RAM_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_30BIT_EN, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM_3DLUT_READ_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR, MPC_RMCM_3DLUT_OUT_NORM_FACTOR, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM_3DLUT_OUT_OFFSET_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM_3DLUT_OUT_SCALE_R, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM_3DLUT_OUT_OFFSET_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM_3DLUT_OUT_SCALE_G, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM_3DLUT_OUT_OFFSET_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM_3DLUT_OUT_SCALE_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM_GAMUT_REMAP_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM_GAMUT_REMAP_C11_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM_GAMUT_REMAP_C12_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM_GAMUT_REMAP_C13_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM_GAMUT_REMAP_C14_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM_GAMUT_REMAP_C21_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM_GAMUT_REMAP_C22_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM_GAMUT_REMAP_C23_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM_GAMUT_REMAP_C24_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM_GAMUT_REMAP_C31_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM_GAMUT_REMAP_C32_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM_GAMUT_REMAP_C33_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM_GAMUT_REMAP_C34_A, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM_GAMUT_REMAP_C11_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM_GAMUT_REMAP_C12_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM_GAMUT_REMAP_C13_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM_GAMUT_REMAP_C14_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM_GAMUT_REMAP_C21_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM_GAMUT_REMAP_C22_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM_GAMUT_REMAP_C23_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM_GAMUT_REMAP_C24_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM_GAMUT_REMAP_C31_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM_GAMUT_REMAP_C32_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM_GAMUT_REMAP_C33_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM_GAMUT_REMAP_C34_B, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_PWR_FORCE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_PWR_DIS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_PWR_FORCE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_PWR_DIS, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_SHAPER_MEM_PWR_STATE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM_3DLUT_MEM_PWR_STATE, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT, MPC_RMCM_3DLUT_FL_SEL, mask_sh),\ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM_3DLUT_FL_DONE, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_CNTL, MPC_RMCM_CNTL, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM_TEST_DEBUG_INDEX, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM_TEST_DEBUG_WRITE_EN, mask_sh), \ + SF(MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA, MPC_RMCM_TEST_DEBUG_DATA, mask_sh) + +#define MPC_RMCM_REG_LIST_DCN42(inst)\ + SRII(MPC_RMCM_SHAPER_CONTROL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_OFFSET_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_OFFSET_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_OFFSET_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_SCALE_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_SCALE_G_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_LUT_INDEX, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_LUT_DATA, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_START_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_END_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_0_1, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_2_3, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_4_5, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_6_7, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_8_9, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_10_11, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_12_13, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_14_15, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_16_17, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_18_19, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_20_21, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_22_23, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_24_25, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_26_27, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_28_29, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_30_31, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMA_REGION_32_33, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_START_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_END_CNTL_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_0_1, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_2_3, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_4_5, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_6_7, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_8_9, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_10_11, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_12_13, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_14_15, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_16_17, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_18_19, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_20_21, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_22_23, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_24_25, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_26_27, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_28_29, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_30_31, MPC_RMCM, inst),\ + SRII(MPC_RMCM_SHAPER_RAMB_REGION_32_33, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_MODE, MPC_RMCM, inst), /*TODO: may need to add other 3DLUT regs*/\ + SRII(MPC_RMCM_3DLUT_INDEX, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_DATA, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_DATA_30BIT, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_READ_WRITE_CONTROL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_NORM_FACTOR, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_OFFSET_R, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_OFFSET_G, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_OUT_OFFSET_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_COEF_FORMAT, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_MODE, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C11_C12_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C13_C14_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C21_C22_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C23_C24_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C31_C32_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C33_C34_A, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C11_C12_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C13_C14_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C21_C22_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C23_C24_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C31_C32_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_GAMUT_REMAP_C33_C34_B, MPC_RMCM, inst),\ + SRII(MPC_RMCM_MEM_PWR_CTRL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_FAST_LOAD_SELECT, MPC_RMCM, inst),\ + SRII(MPC_RMCM_3DLUT_FAST_LOAD_STATUS, MPC_RMCM, inst),\ + SRII(MPC_RMCM_CNTL, MPC_RMCM, inst),\ + SRII(MPC_RMCM_TEST_DEBUG_INDEX, MPC_RMCM, inst),\ + SRII(MPC_RMCM_TEST_DEBUG_DATA, MPC_RMCM, inst) + + +#define MPC_REG_LIST_DCN42(inst) \ + MPC_REG_LIST_DCN4_01_RI(inst),\ + SRII(MPCC_CONTROL2, MPCC, inst) + +#define MPC_REG_FIELD_LIST_DCN42(type) \ + MPC_REG_FIELD_LIST_DCN4_01(type); \ + type MPCC_MCM_3DLUT_OUT_OFFSET_R;\ + type MPCC_MCM_3DLUT_OUT_SCALE_R;\ + type MPCC_MCM_3DLUT_OUT_OFFSET_G;\ + type MPCC_MCM_3DLUT_OUT_SCALE_G;\ + type MPCC_MCM_3DLUT_OUT_OFFSET_B;\ + type MPCC_MCM_3DLUT_OUT_SCALE_B;\ + type MPC_RMCM_SHAPER_LUT_MODE;\ + type MPC_RMCM_SHAPER_MODE_CURRENT;\ + type MPC_RMCM_SHAPER_OFFSET_R;\ + type MPC_RMCM_SHAPER_OFFSET_G;\ + type MPC_RMCM_SHAPER_OFFSET_B;\ + type MPC_RMCM_SHAPER_SCALE_R;\ + type MPC_RMCM_SHAPER_SCALE_G;\ + type MPC_RMCM_SHAPER_SCALE_B;\ + type MPC_RMCM_SHAPER_LUT_INDEX;\ + type MPC_RMCM_SHAPER_LUT_DATA;\ + type MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK;\ + type MPC_RMCM_SHAPER_LUT_WRITE_SEL; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET;\ + type MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS;\ + type MPC_RMCM_3DLUT_MODE;\ + type MPC_RMCM_3DLUT_SIZE;\ + type MPC_RMCM_3DLUT_MODE_CURRENT;\ + type MPC_RMCM_3DLUT_INDEX; \ + type MPC_RMCM_3DLUT_DATA0; \ + type MPC_RMCM_3DLUT_DATA1; \ + type MPC_RMCM_3DLUT_DATA_30BIT; \ + type MPC_RMCM_3DLUT_WRITE_EN_MASK;\ + type MPC_RMCM_3DLUT_RAM_SEL;\ + type MPC_RMCM_3DLUT_30BIT_EN;\ + type MPC_RMCM_3DLUT_READ_SEL;\ + type MPC_RMCM_3DLUT_OUT_NORM_FACTOR;\ + type MPC_RMCM_3DLUT_OUT_OFFSET_R;\ + type MPC_RMCM_3DLUT_OUT_SCALE_R; \ + type MPC_RMCM_3DLUT_OUT_OFFSET_G; \ + type MPC_RMCM_3DLUT_OUT_SCALE_G; \ + type MPC_RMCM_3DLUT_OUT_OFFSET_B; \ + type MPC_RMCM_3DLUT_OUT_SCALE_B;\ + type MPC_RMCM_GAMUT_REMAP_COEF_FORMAT;\ + type MPC_RMCM_GAMUT_REMAP_MODE;\ + type MPC_RMCM_GAMUT_REMAP_MODE_CURRENT;\ + type MPC_RMCM_GAMUT_REMAP_C11_A;\ + type MPC_RMCM_GAMUT_REMAP_C12_A;\ + type MPC_RMCM_GAMUT_REMAP_C13_A; \ + type MPC_RMCM_GAMUT_REMAP_C14_A; \ + type MPC_RMCM_GAMUT_REMAP_C21_A; \ + type MPC_RMCM_GAMUT_REMAP_C22_A; \ + type MPC_RMCM_GAMUT_REMAP_C23_A;\ + type MPC_RMCM_GAMUT_REMAP_C24_A;\ + type MPC_RMCM_GAMUT_REMAP_C31_A;\ + type MPC_RMCM_GAMUT_REMAP_C32_A;\ + type MPC_RMCM_GAMUT_REMAP_C33_A;\ + type MPC_RMCM_GAMUT_REMAP_C34_A;\ + type MPC_RMCM_GAMUT_REMAP_C11_B;\ + type MPC_RMCM_GAMUT_REMAP_C12_B;\ + type MPC_RMCM_GAMUT_REMAP_C13_B; \ + type MPC_RMCM_GAMUT_REMAP_C14_B; \ + type MPC_RMCM_GAMUT_REMAP_C21_B; \ + type MPC_RMCM_GAMUT_REMAP_C22_B; \ + type MPC_RMCM_GAMUT_REMAP_C23_B;\ + type MPC_RMCM_GAMUT_REMAP_C24_B;\ + type MPC_RMCM_GAMUT_REMAP_C31_B;\ + type MPC_RMCM_GAMUT_REMAP_C32_B;\ + type MPC_RMCM_GAMUT_REMAP_C33_B;\ + type MPC_RMCM_GAMUT_REMAP_C34_B;\ + type MPC_RMCM_SHAPER_MEM_PWR_FORCE; \ + type MPC_RMCM_SHAPER_MEM_PWR_DIS; \ + type MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE; \ + type MPC_RMCM_3DLUT_MEM_PWR_FORCE;\ + type MPC_RMCM_3DLUT_MEM_PWR_DIS;\ + type MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE;\ + type MPC_RMCM_SHAPER_MEM_PWR_STATE;\ + type MPC_RMCM_3DLUT_MEM_PWR_STATE;\ + type MPC_RMCM_3DLUT_FL_SEL;\ + type MPC_RMCM_3DLUT_FL_DONE; \ + type MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW; \ + type MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW; \ + type MPC_RMCM_CNTL; \ + type MPC_RMCM_TEST_DEBUG_INDEX;\ + type MPC_RMCM_TEST_DEBUG_WRITE_EN;\ + type MPC_RMCM_TEST_DEBUG_DATA + +#define MPC_REG_VARIABLE_LIST_DCN42 \ + MPC_REG_VARIABLE_LIST_DCN4_01 \ + uint32_t MPCC_CONTROL2[MAX_MPCC];\ + uint32_t MPC_RMCM_SHAPER_CONTROL[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_OFFSET_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_OFFSET_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_OFFSET_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_SCALE_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_SCALE_G_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_LUT_INDEX[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_LUT_DATA[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_START_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_START_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_START_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_END_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_END_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_END_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_0_1[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_2_3[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_4_5[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_6_7[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_8_9[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_10_11[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_12_13[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_14_15[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_16_17[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_18_19[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_20_21[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_22_23[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_24_25[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_26_27[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_28_29[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_30_31[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMA_REGION_32_33[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_START_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_START_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_START_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_END_CNTL_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_END_CNTL_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_END_CNTL_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_0_1[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_2_3[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_4_5[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_6_7[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_8_9[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_10_11[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_12_13[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_14_15[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_16_17[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_18_19[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_20_21[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_22_23[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_24_25[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_26_27[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_28_29[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_30_31[MAX_MPCC]; \ + uint32_t MPC_RMCM_SHAPER_RAMB_REGION_32_33[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_MODE[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_INDEX[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_DATA[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_DATA_30BIT[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_READ_WRITE_CONTROL[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_NORM_FACTOR[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_OFFSET_R[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_OFFSET_G[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_OUT_OFFSET_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_COEF_FORMAT[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_MODE[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C11_C12_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C13_C14_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C21_C22_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C23_C24_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C31_C32_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C33_C34_A[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C11_C12_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C13_C14_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C21_C22_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C23_C24_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C31_C32_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_GAMUT_REMAP_C33_C34_B[MAX_MPCC]; \ + uint32_t MPC_RMCM_MEM_PWR_CTRL[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_FAST_LOAD_SELECT[MAX_MPCC]; \ + uint32_t MPC_RMCM_3DLUT_FAST_LOAD_STATUS[MAX_MPCC]; \ + uint32_t MPC_RMCM_CNTL[MAX_MPCC]; \ + uint32_t MPC_RMCM_TEST_DEBUG_INDEX[MAX_MPCC]; \ + uint32_t MPC_RMCM_TEST_DEBUG_DATA[MAX_MPCC] + +struct dcn42_mpc_shift { + MPC_REG_FIELD_LIST_DCN42(uint8_t); +}; + +struct dcn42_mpc_mask { + MPC_REG_FIELD_LIST_DCN42(uint32_t); +}; + +struct dcn42_mpc_registers { + MPC_REG_VARIABLE_LIST_DCN42; +}; + +struct dcn42_mpc { + struct mpc base; + + int mpcc_in_use_mask; + int num_mpcc; + const struct dcn42_mpc_registers *mpc_regs; + const struct dcn42_mpc_shift *mpc_shift; + const struct dcn42_mpc_mask *mpc_mask; + int num_rmu; +}; +void dcn42_mpc_construct(struct dcn42_mpc *mpc401, + struct dc_context *ctx, + const struct dcn42_mpc_registers *mpc_regs, + const struct dcn42_mpc_shift *mpc_shift, + const struct dcn42_mpc_mask *mpc_mask, + int num_mpcc, + int num_rmu); + +void mpc42_init_mpcc(struct mpcc *mpcc, int mpcc_inst); + +/* RMCM */ +void mpc42_program_rmcm_shaper_lut( + struct mpc *mpc, + const struct pwl_result_data *rgb, + uint32_t num, + uint32_t mpcc_id); +void mpc42_program_rmcm_shaper_lutb_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_program_rmcm_shaper_luta_settings( + struct mpc *mpc, + const struct pwl_params *params, + uint32_t mpcc_id); +void mpc42_configure_rmcm_shaper_lut( + struct mpc *mpc, + bool is_ram_a, + uint32_t mpcc_id); +void mpc42_power_on_rmcm_shaper_3dlut( + struct mpc *mpc, + uint32_t mpcc_id, + bool power_on); +void mpc42_enable_3dlut_fl( + struct mpc *mpc, + bool enable, + int mpcc_id); +void mpc42_update_3dlut_fast_load_select( + struct mpc *mpc, + int mpcc_id, + int hubp_idx); +void mpc42_populate_rmcm_lut( + struct mpc *mpc, + const union mcm_lut_params params, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_rmcm_lut_read_write_control( + struct mpc *mpc, + const enum MCM_LUT_ID id, + bool lut_bank_a, + bool enabled, + int mpcc_id); +void mpc42_program_lut_mode( + struct mpc *mpc, + bool enable, + bool lut_bank_a, + int mpcc_id); +void mpc42_program_rmcm_3dlut_size( + struct mpc *mpc, + const enum dc_cm_lut_size size, + int mpcc_id); +void mpc42_program_rmcm_3dlut_fast_load_bias_scale( + struct mpc *mpc, + uint16_t bias, + uint16_t scale, + int mpcc_id); +void mpc42_program_rmcm_bit_depth( + struct mpc *mpc, + uint16_t bit_depth, + int mpcc_id); + +void mpc42_set_fl_config( + struct mpc *mpc, + struct mpc_fl_3dlut_config *cfg, + int mpcc_id); + +void mpc42_read_mpcc_state( + struct mpc *mpc, + int mpcc_inst, + struct mpcc_state *s); + +void mpc42_update_blending( + struct mpc *mpc, + struct mpcc_blnd_cfg *blnd_cfg, + int mpcc_id); + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/Makefile b/drivers/gpu/drm/amd/display/dc/optc/Makefile index 29fb610c8660f..06c98d70eabcc 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/optc/Makefile @@ -104,11 +104,19 @@ AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN35) ############################################################################### -############################################################################### OPTC_DCN401 = dcn401_optc.o AMD_DAL_OPTC_DCN401 = $(addprefix $(AMDDALPATH)/dc/optc/dcn401/,$(OPTC_DCN401)) AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN401) + +############################################################################### + +OPTC_DCN42 = dcn42_optc.o + +AMD_DAL_OPTC_DCN42 = $(addprefix $(AMDDALPATH)/dc/optc/dcn42/,$(OPTC_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_OPTC_DCN42) + endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 803bcc25601c0..138081e6cc977 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -1,5 +1,5 @@ /* - * Copyright 2012-15 Advanced Micro Devices, Inc. + * Copyright 2012-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -218,7 +218,7 @@ uint32_t OTG_CRC_SIG_BLUE_CONTROL_MASK; \ uint32_t OTG_CRC_SIG_RED_GREEN_MASK; \ uint32_t OTG_DLPC_CONTROL; \ - uint32_t OTG_DRR_CONTROL2; \ + uint32_t OTG_DRR_CONTOL2; \ uint32_t OTG_DRR_TIMING_INT_STATUS; \ uint32_t OTG_GLOBAL_CONTROL3; \ uint32_t OTG_GLOBAL_SYNC_STATUS; \ @@ -244,11 +244,29 @@ uint32_t OTG_TRIGB_MANUAL_TRIG; \ uint32_t OTG_UPDATE_LOCK; \ uint32_t OTG_V_TOTAL_INT_STATUS; \ - uint32_t OTG_VSYNC_NOM_INT_STATUS + uint32_t OTG_VSYNC_NOM_INT_STATUS; \ + uint32_t OTG_CRC0_DATA_R32; \ + uint32_t OTG_CRC0_DATA_G32; \ + uint32_t OTG_CRC0_DATA_B32; \ + uint32_t OTG_CRC1_DATA_R32; \ + uint32_t OTG_CRC1_DATA_G32; \ + uint32_t OTG_CRC1_DATA_B32 +#define OPTC_REG_VARIABLE_LIST_DCN42 \ + uint32_t OTG_PWA_FRAME_SYNC_CONTROL; \ + uint32_t OTG_CRC0_DATA_R; \ + uint32_t OTG_CRC1_DATA_R; \ + uint32_t OTG_CRC2_DATA_R; \ + uint32_t OTG_CRC3_DATA_R; \ + uint32_t OTG_CRC0_DATA_G; \ + uint32_t OTG_CRC1_DATA_G; \ + uint32_t OTG_CRC2_DATA_G; \ + uint32_t OTG_CRC3_DATA_G + struct dcn_optc_registers { OPTC_REG_VARIABLE_LIST_DCN; + OPTC_REG_VARIABLE_LIST_DCN42; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -657,6 +675,19 @@ struct dcn_optc_registers { type OTG_V_COUNT_STOP;\ type OTG_V_COUNT_STOP_TIMER; +#define TG_REG_FIELD_LIST_DCN3_6(type) \ + type OPTC_RSMU_UNDERFLOW_CLEAR;\ + type OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS;\ + type OPTC_RSMU_UNDERFLOW_INT_EN;\ + type OPTC_RSMU_UNDERFLOW_INT_STATUS;\ + type OTG_CRC_POLY_SEL; \ + type CRC0_R_CR32; \ + type CRC0_G_Y32; \ + type CRC0_B_CB32; \ + type CRC1_R_CR32; \ + type CRC1_G_Y32; \ + type CRC1_B_CB32; + #define TG_REG_FIELD_LIST_DCN401(type) \ type OPTC_SEGMENT_WIDTH_LAST;\ type OTG_PSTATE_KEEPOUT_START;\ @@ -664,13 +695,19 @@ struct dcn_optc_registers { type OTG_UNBLANK;\ type OTG_PSTATE_ALLOW_WIDTH_MIN; +#define TG_REG_FIELD_LIST_DCN42(type) \ + type OTG_PWA_FRAME_SYNC_EN;\ + type OTG_PWA_FRAME_SYNC_VCOUNT_MODE;\ + type OTG_PWA_FRAME_SYNC_LINE; struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) TG_REG_FIELD_LIST_DCN2_0(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) + TG_REG_FIELD_LIST_DCN3_6(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) + TG_REG_FIELD_LIST_DCN42(uint8_t) }; struct dcn_optc_mask { @@ -678,7 +715,9 @@ struct dcn_optc_mask { TG_REG_FIELD_LIST_DCN2_0(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) + TG_REG_FIELD_LIST_DCN3_6(uint32_t) TG_REG_FIELD_LIST_DCN401(uint32_t) + TG_REG_FIELD_LIST_DCN42(uint32_t) }; void dcn10_timing_generator_init(struct optc *optc); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index c6417538090f2..893d2aff1f826 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -363,7 +363,7 @@ void optc31_read_reg_state(struct timing_generator *optc, struct dcn_optc_reg_st optc_reg_state->otg_crc3_data_rg = REG_READ(OTG_CRC3_DATA_RG); optc_reg_state->otg_dlpc_control = REG_READ(OTG_DLPC_CONTROL); optc_reg_state->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL); - optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTROL2); + optc_reg_state->otg_drr_control2 = REG_READ(OTG_DRR_CONTOL2); optc_reg_state->otg_drr_control = REG_READ(OTG_DRR_CONTROL); optc_reg_state->otg_drr_timing_int_status = REG_READ(OTG_DRR_TIMING_INT_STATUS); optc_reg_state->otg_drr_trigger_window = REG_READ(OTG_DRR_TRIGGER_WINDOW); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c index f699e95059f3e..5aafd0eedf668 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c @@ -180,7 +180,97 @@ static void optc35_phantom_crtc_post_enable(struct timing_generator *optc) REG_WAIT(OTG_CLOCK_CONTROL, OTG_BUSY, 0, 1, 100000); } -static bool optc35_configure_crc(struct timing_generator *optc, +/** + * optc35_get_crc - Capture CRC result per component + * + * @optc: timing_generator instance. + * @idx: index of crc engine to get CRC from + * @r_cr: primary CRC signature for red data. + * @g_y: primary CRC signature for green data. + * @b_cb: primary CRC signature for blue data. + * + * This function reads the CRC signature from the OPTC registers. Notice that + * we have three registers to keep the CRC result per color component (RGB). + * + * For different DCN versions: + * - If CRC32 registers (OTG_CRC0_DATA_R32/G32/B32) are available, read from + * 32-bit CRC registers. DCN 3.6+ supports both CRC-32 and CRC-16 polynomials + * selectable via OTG_CRC_POLY_SEL. + * - Otherwise, read from legacy 16-bit CRC registers (OTG_CRC0_DATA_RG/B) + * which only support CRC-16 polynomial. + * + * Returns: + * If CRC is disabled, return false; otherwise, return true, and the CRC + * results in the parameters. + */ +static bool optc35_get_crc(struct timing_generator *optc, uint8_t idx, + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) +{ + uint32_t field = 0; + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + + /* Early return if CRC is not enabled for this CRTC */ + if (!field) + return false; + + if (optc1->tg_mask->CRC0_R_CR32 != 0 && optc1->tg_mask->CRC1_R_CR32 != 0 && + optc1->tg_mask->CRC0_G_Y32 != 0 && optc1->tg_mask->CRC1_G_Y32 != 0 && + optc1->tg_mask->CRC0_B_CB32 != 0 && optc1->tg_mask->CRC1_B_CB32 != 0) { + switch (idx) { + case 0: + /* OTG_CRC0_DATA_R32/G32/B32 has the CRC32 results */ + REG_GET(OTG_CRC0_DATA_R32, + CRC0_R_CR32, r_cr); + REG_GET(OTG_CRC0_DATA_G32, + CRC0_G_Y32, g_y); + REG_GET(OTG_CRC0_DATA_B32, + CRC0_B_CB32, b_cb); + break; + case 1: + /* OTG_CRC1_DATA_R32/G32/B32 has the CRC32 results */ + REG_GET(OTG_CRC1_DATA_R32, + CRC1_R_CR32, r_cr); + REG_GET(OTG_CRC1_DATA_G32, + CRC1_G_Y32, g_y); + REG_GET(OTG_CRC1_DATA_B32, + CRC1_B_CB32, b_cb); + break; + default: + return false; + } + } else { + switch (idx) { + case 0: + /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */ + REG_GET_2(OTG_CRC0_DATA_RG, + CRC0_R_CR, r_cr, + CRC0_G_Y, g_y); + + /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC0_DATA_B, + CRC0_B_CB, b_cb); + break; + case 1: + /* OTG_CRC1_DATA_RG has the CRC16 results for the red and green component */ + REG_GET_2(OTG_CRC1_DATA_RG, + CRC1_R_CR, r_cr, + CRC1_G_Y, g_y); + + /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC1_DATA_B, + CRC1_B_CB, b_cb); + break; + default: + return false; + } + } + + return true; +} + +bool optc35_configure_crc(struct timing_generator *optc, const struct crc_params *params) { struct optc *optc1 = DCN10TG_FROM_TG(optc); @@ -266,6 +356,10 @@ static bool optc35_configure_crc(struct timing_generator *optc, default: return false; } + if (optc1->tg_mask->OTG_CRC_POLY_SEL != 0) { + REG_UPDATE(OTG_CRC_CNTL, + OTG_CRC_POLY_SEL, params->crc_poly_mode); + } return true; } @@ -343,7 +437,7 @@ void optc35_set_drr( REG_WRITE(OTG_V_COUNT_STOP_CONTROL2, 0); } -static void optc35_set_long_vtotal( +void optc35_set_long_vtotal( struct timing_generator *optc, const struct long_vtotal_params *params) { @@ -430,7 +524,7 @@ static void optc35_set_long_vtotal( } } -static void optc35_wait_otg_disable(struct timing_generator *optc) +void optc35_wait_otg_disable(struct timing_generator *optc) { struct optc *optc1; uint32_t is_master_en; @@ -488,7 +582,7 @@ static const struct timing_generator_funcs dcn35_tg_funcs = { .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, .clear_optc_underflow = optc1_clear_optc_underflow, .setup_global_swap_lock = NULL, - .get_crc = optc1_get_crc, + .get_crc = optc35_get_crc, .configure_crc = optc35_configure_crc, .set_dsc_config = optc3_set_dsc_config, .get_dsc_status = optc2_get_dsc_status, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h index 733a2f149d9a9..82e0818c8f9f4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h @@ -74,10 +74,29 @@ SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh) +#define OPTC_COMMON_MASK_SH_LIST_DCN3_6(mask_sh)\ + OPTC_COMMON_MASK_SH_LIST_DCN3_5(mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_POLY_SEL, mask_sh),\ + SF(OTG_CRC320_OTG_CRC0_DATA_R32, CRC0_R_CR32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC0_DATA_G32, CRC0_G_Y32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC0_DATA_B32, CRC0_B_CB32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC1_DATA_R32, CRC1_R_CR32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC1_DATA_G32, CRC1_G_Y32, mask_sh),\ + SF(OTG_CRC320_OTG_CRC1_DATA_B32, CRC1_B_CB32, mask_sh) + void dcn35_timing_generator_init(struct optc *optc1); void dcn35_timing_generator_set_fgcg(struct optc *optc1, bool enable); void optc35_set_drr(struct timing_generator *optc, const struct drr_params *params); +void optc35_set_long_vtotal( + struct timing_generator *optc, + const struct long_vtotal_params *params); + +bool optc35_configure_crc(struct timing_generator *optc, + const struct crc_params *params); + +void optc35_wait_otg_disable(struct timing_generator *optc); + #endif /* __DC_OPTC_DCN35_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c new file mode 100644 index 0000000000000..ed66a2bbb8aeb --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.c @@ -0,0 +1,291 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dcn42_optc.h" +#include "dcn30/dcn30_optc.h" +#include "dcn31/dcn31_optc.h" +#include "dcn32/dcn32_optc.h" +#include "dcn35/dcn35_optc.h" +#include "dcn401/dcn401_optc.h" +#include "reg_helper.h" +#include "dc.h" +#include "dcn_calc_math.h" +#include "dc_dmub_srv.h" +#include "dc_trace.h" + +#define REG(reg)\ + optc1->tg_regs->reg + +#define CTX \ + optc1->base.ctx + +#undef FN +#define FN(reg_name, field_name) \ + optc1->tg_shift->field_name, optc1->tg_mask->field_name + +/* + * optc42_get_crc - Capture CRC result per component + * + * @optc: timing_generator instance. + * @r_cr: 16-bit primary CRC signature for red data. + * @g_y: 16-bit primary CRC signature for green data. + * @b_cb: 16-bit primary CRC signature for blue data. + * + * This function reads the CRC signature from the OPTC registers. Notice that + * we have three registers to keep the CRC result per color component (RGB). + * + * Returns: + * If CRC is disabled, return false; otherwise, return true, and the CRC + * results in the parameters. + */ + +static bool optc42_get_crc(struct timing_generator *optc, uint8_t idx, + uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb) +{ + uint32_t field = 0; + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field); + + /* Early return if CRC is not enabled for this CRTC */ + if (!field) + return false; + + + switch (idx) { + case 0: + /* OTG_CRC0_DATA_RG has the CRC16 results for the red component */ + REG_GET(OTG_CRC0_DATA_R, + CRC0_R_CR, r_cr); + + /* OTG_CRC0_DATA_RG has the CRC16 results for the green component */ + REG_GET(OTG_CRC0_DATA_G, + CRC0_G_Y, g_y); + + /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC0_DATA_B, + CRC0_B_CB, b_cb); + break; + case 1: + /* OTG_CRC1_DATA_RG has the CRC16 results for the red component */ + REG_GET(OTG_CRC1_DATA_R, + CRC0_R_CR, r_cr); + + /* OTG_CRC1_DATA_RG has the CRC16 results for the green component */ + REG_GET(OTG_CRC1_DATA_G, + CRC0_G_Y, g_y); + + /* OTG_CRC1_DATA_B has the CRC16 results for the blue component */ + REG_GET(OTG_CRC1_DATA_B, + CRC0_B_CB, b_cb); + break; + default: + return false; + } + return true; +} + +void optc42_enable_pwa(struct timing_generator *optc, struct otc_pwa_frame_sync *pwa_sync_param) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + /*VCOUNT_MODE : + 00 OTG_PWA_FRAME_SYNC_VCOUNT_0 Vcount counting from VSYNC. + 01 OTG_PWA_FRAME_SYNC_VCOUNT_1 Vcount counting from VSTARTUP.*/ + + if (pwa_sync_param == NULL) + return; + if (optc1->base.ctx->dc->debug.enable_otg_frame_sync_pwa) { + /*take mode 1, use line number from vstartup to get output frame as earlier as possible*/ + REG_UPDATE_3(OTG_PWA_FRAME_SYNC_CONTROL, + OTG_PWA_FRAME_SYNC_EN, 1, + OTG_PWA_FRAME_SYNC_VCOUNT_MODE, pwa_sync_param->pwa_sync_mode, + OTG_PWA_FRAME_SYNC_LINE, pwa_sync_param->pwa_frame_sync_line_offset); + } +} +void optc42_disable_pwa(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_UPDATE(OTG_PWA_FRAME_SYNC_CONTROL, + OTG_PWA_FRAME_SYNC_EN, 0); +} +void optc42_clear_optc_underflow(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1); + REG_UPDATE(OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_CLEAR, 1); +} +bool optc42_is_optc_underflow_occurred(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t underflow_occurred = 0, rsmu_underflow_occurred = 0; + + REG_GET(OPTC_INPUT_GLOBAL_CONTROL, + OPTC_UNDERFLOW_OCCURRED_STATUS, + &underflow_occurred); + + REG_GET(OPTC_RSMU_UNDERFLOW, + OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS, + &rsmu_underflow_occurred); + return (underflow_occurred == 1 || rsmu_underflow_occurred); +} +/* disable_crtc */ +bool optc42_disable_crtc(struct timing_generator *optc) +{ + optc401_disable_crtc(optc); + optc42_clear_optc_underflow(optc); + + return true; +} +static void optc42_set_timing_double_buffer(struct timing_generator *optc, bool enable) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t mode = enable ? 2 : 0; + /* actually we have 4 modes now, use as the same as previous dcn3x + * 00 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 Double buffer update occurs at any time in a frame. + * 01 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 Double buffer update occurs at OTG start of frame. + * 02 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 Double buffer occurs DP start of frame. + * 03 OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 Reserved. + */ + + REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, + OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode); +} +void optc42_tg_init(struct timing_generator *optc) +{ + optc42_set_timing_double_buffer(optc, true); + optc42_clear_optc_underflow(optc); +} + +void optc42_lock_doublebuffer_enable(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t v_blank_start = 0; + uint32_t v_blank_end = 0; + uint32_t h_blank_start = 0; + uint32_t h_blank_end = 0; + + REG_GET_2(OTG_V_BLANK_START_END, + OTG_V_BLANK_START, &v_blank_start, + OTG_V_BLANK_END, &v_blank_end); + REG_GET_2(OTG_H_BLANK_START_END, + OTG_H_BLANK_START, &h_blank_start, + OTG_H_BLANK_END, &h_blank_end); + + REG_UPDATE_2(OTG_GLOBAL_CONTROL1, + MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start, + MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start); + REG_UPDATE_2(OTG_GLOBAL_CONTROL4, + DIG_UPDATE_POSITION_X, 20, + DIG_UPDATE_POSITION_Y, v_blank_start); + REG_UPDATE_3(OTG_GLOBAL_CONTROL0, + MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1, + MASTER_UPDATE_LOCK_DB_END_X, h_blank_end, + MASTER_UPDATE_LOCK_DB_EN, 1); + REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1); + + REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, + MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0, + MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100, + OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); + + TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true); +} + +static struct timing_generator_funcs dcn42_tg_funcs = { + .validate_timing = optc1_validate_timing, + .program_timing = optc1_program_timing, + .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, + .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, + .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, + .program_global_sync = optc401_program_global_sync, + .enable_crtc = optc401_enable_crtc, + .disable_crtc = optc42_disable_crtc, + .phantom_crtc_post_enable = optc401_phantom_crtc_post_enable, + .disable_phantom_crtc = optc401_disable_phantom_otg, + /* used by enable_timing_synchronization. Not need for FPGA */ + .is_counter_moving = optc1_is_counter_moving, + .get_position = optc1_get_position, + .get_frame_count = optc1_get_vblank_counter, + .get_scanoutpos = optc1_get_crtc_scanoutpos, + .get_otg_active_size = optc1_get_otg_active_size, + .set_early_control = optc1_set_early_control, + /* used by enable_timing_synchronization. Not need for FPGA */ + .wait_for_state = optc1_wait_for_state, + .set_blank_color = optc3_program_blank_color, + .did_triggered_reset_occur = optc1_did_triggered_reset_occur, + .triplebuffer_lock = optc3_triplebuffer_lock, + .triplebuffer_unlock = optc2_triplebuffer_unlock, + .enable_reset_trigger = optc1_enable_reset_trigger, + .enable_crtc_reset = optc1_enable_crtc_reset, + .disable_reset_trigger = optc1_disable_reset_trigger, + .lock = optc3_lock, + .unlock = optc1_unlock, + .lock_doublebuffer_enable = optc42_lock_doublebuffer_enable, + .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, + .enable_optc_clock = optc1_enable_optc_clock, + .set_drr = optc401_set_drr, + .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal, + .set_vtotal_min_max = optc401_set_vtotal_min_max, + .set_static_screen_control = optc1_set_static_screen_control, + .program_stereo = optc1_program_stereo, + .is_stereo_left_eye = optc1_is_stereo_left_eye, + .tg_init = optc42_tg_init, + .is_tg_enabled = optc1_is_tg_enabled, + .is_optc_underflow_occurred = optc42_is_optc_underflow_occurred, + .clear_optc_underflow = optc42_clear_optc_underflow, + .setup_global_swap_lock = NULL, + .get_crc = optc42_get_crc, + .configure_crc = optc35_configure_crc, + .set_dsc_config = optc3_set_dsc_config, + .get_dsc_status = optc2_get_dsc_status, + .set_dwb_source = NULL, + .set_odm_bypass = optc401_set_odm_bypass, + .set_odm_combine = optc401_set_odm_combine, + .wait_odm_doublebuffer_pending_clear = optc32_wait_odm_doublebuffer_pending_clear, + .set_h_timing_div_manual_mode = optc401_set_h_timing_div_manual_mode, + .get_optc_source = optc2_get_optc_source, + .wait_otg_disable = optc35_wait_otg_disable, + .set_out_mux = optc401_set_out_mux, + .set_drr_trigger_window = optc3_set_drr_trigger_window, + .set_vtotal_change_limit = optc3_set_vtotal_change_limit, + .set_gsl = optc2_set_gsl, + .set_gsl_source_select = optc2_set_gsl_source_select, + .set_vtg_params = optc1_set_vtg_params, + .program_manual_trigger = optc2_program_manual_trigger, + .setup_manual_trigger = optc2_setup_manual_trigger, + .get_hw_timing = optc1_get_hw_timing, + .init_odm = optc3_init_odm, + .set_long_vtotal = optc35_set_long_vtotal, + .is_two_pixels_per_container = optc1_is_two_pixels_per_container, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, + .set_vupdate_keepout = optc401_set_vupdate_keepout, + .wait_update_lock_status = optc401_wait_update_lock_status, + .optc_read_reg_state = optc31_read_reg_state, + .read_otg_state = optc31_read_otg_state, + .enable_otg_pwa = optc42_enable_pwa, + .disable_otg_pwa = optc42_disable_pwa, +}; + +void dcn42_timing_generator_init(struct optc *optc1) +{ + optc1->base.funcs = &dcn42_tg_funcs; + + optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; + optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; + + optc1->min_h_blank = 32; + optc1->min_v_blank = 3; + optc1->min_v_blank_interlace = 5; + optc1->min_h_sync_width = 4; + optc1->min_v_sync_width = 1; + optc1->max_frame_count = 0xFFFFFF; + + dcn35_timing_generator_set_fgcg( + optc1, CTX->dc->debug.enable_fine_grain_clock_gating.bits.optc); +} + diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h new file mode 100644 index 0000000000000..fc7192f01b336 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_OPTC_DCN42_H__ +#define __DC_OPTC_DCN42_H__ + +#include "dcn10/dcn10_optc.h" + +#define OPTC_COMMON_MASK_SH_LIST_DCN42(mask_sh)\ + SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ + SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ + SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ + SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_START_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_END_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_START_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_END_Y, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_X, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL4, DIG_UPDATE_POSITION_Y, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ + SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ + SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ + SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ + SF(OTG0_OTG_CONTROL, OTG_OUT_MUX, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ + SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ + SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MIN_EN, mask_sh),\ + SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ + SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ + SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ + SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ + SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ + SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO0, OTG_M_CONST_DTO_PHASE, mask_sh),\ + SF(OTG0_OTG_M_CONST_DTO1, OTG_M_CONST_DTO_MODULO, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ + SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ + SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_CLEAR, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_INT_EN, mask_sh),\ + SF(ODM0_OPTC_RSMU_UNDERFLOW, OPTC_RSMU_UNDERFLOW_INT_STATUS, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ + SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ + SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_R, CRC0_R_CR, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_G, CRC0_G_Y, mask_sh),\ + SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ + SF(OTG0_OTG_CRC1_DATA_R, CRC1_R_CR, mask_sh),\ + SF(OTG0_OTG_CRC1_DATA_G, CRC1_G_Y, mask_sh),\ + SF(OTG0_OTG_CRC1_DATA_B, CRC1_B_CB, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_X_CONTROL, OTG_CRC1_WINDOWA_X_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWA_Y_CONTROL, OTG_CRC1_WINDOWA_Y_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_X_CONTROL, OTG_CRC1_WINDOWB_X_END, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_START, mask_sh),\ + SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL, OTG_CRC1_WINDOWB_Y_END, mask_sh),\ + SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ + SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ + SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_END_Y, mask_sh),\ + SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ + SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_MODE, mask_sh), \ + SF(OTG0_OTG_GSL_CONTROL, OTG_MASTER_UPDATE_LOCK_GSL_EN, mask_sh), \ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG0_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG1_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG2_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SEG3_SRC_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_NUM_OF_INPUT_SEGMENT, mask_sh),\ + SF(ODM0_OPTC_MEMORY_CONFIG, OPTC_MEM_SEL, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, mask_sh),\ + SF(ODM0_OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, mask_sh),\ + SF(ODM0_OPTC_BYTES_PER_PIXEL, OPTC_DSC_BYTES_PER_PIXEL, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\ + SF(ODM0_OPTC_WIDTH_CONTROL2, OPTC_SEGMENT_WIDTH_LAST, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_START_X, mask_sh),\ + SF(OTG0_OTG_DRR_TRIGGER_WINDOW, OTG_DRR_TRIGGER_WINDOW_END_X, mask_sh),\ + SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ + SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\ + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ + SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_EN, mask_sh),\ + SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_VCOUNT_MODE, mask_sh),\ + SF(OTG0_OTG_PWA_FRAME_SYNC_CONTROL, OTG_PWA_FRAME_SYNC_LINE, mask_sh),\ + SF(OTG0_INTERRUPT_DEST, OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST, mask_sh),\ + SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh) + +void dcn42_timing_generator_init(struct optc *optc1); +void optc42_enable_pwa(struct timing_generator *optc, struct otc_pwa_frame_sync *pwa_sync_param); +void optc42_disable_pwa(struct timing_generator *optc); +void optc42_tg_init(struct timing_generator *optc); +void optc42_clear_optc_underflow(struct timing_generator *optc); +bool optc42_is_optc_underflow_occurred(struct timing_generator *optc); +bool optc42_disable_crtc(struct timing_generator *optc); +void optc42_lock_doublebuffer_enable(struct timing_generator *optc); +#endif /* __DC_OPTC_DCN42_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h index 782316348941b..6af831710489e 100644 --- a/drivers/gpu/drm/amd/display/dc/os_types.h +++ b/drivers/gpu/drm/amd/display/dc/os_types.h @@ -55,8 +55,6 @@ #if defined(CONFIG_DRM_AMD_DC_FP) #include "amdgpu_dm/dc_fpu.h" -#define DC_FP_START() dc_fpu_begin(__func__, __LINE__) -#define DC_FP_END() dc_fpu_end(__func__, __LINE__) #endif /* CONFIG_DRM_AMD_DC_FP */ /* diff --git a/drivers/gpu/drm/amd/display/dc/pg/Makefile b/drivers/gpu/drm/amd/display/dc/pg/Makefile index ec11d3157a57f..56f610cc84065 100644 --- a/drivers/gpu/drm/amd/display/dc/pg/Makefile +++ b/drivers/gpu/drm/amd/display/dc/pg/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2020 Advanced Micro Devices, Inc. +# Copyright 2020, 2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -32,4 +32,12 @@ PG_DCN35 = dcn35_pg_cntl.o AMD_DAL_PG_DCN35 = $(addprefix $(AMDDALPATH)/dc/pg/dcn35/,$(PG_DCN35)) AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN35) +############################################################################### +# DCN42 +############################################################################### +PG_DCN42 = dcn42_pg_cntl.o + +AMD_DAL_PG_DCN42 = $(addprefix $(AMDDALPATH)/dc/pg/dcn42/,$(PG_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_PG_DCN42) endif diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c new file mode 100644 index 0000000000000..96290538a889d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.c @@ -0,0 +1,649 @@ +// SPDX-License-Identifier: MIT + +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "reg_helper.h" +#include "core_types.h" +#include "dcn42_pg_cntl.h" +#include "dccg.h" + +#define TO_DCN_PG_CNTL(pg_cntl)\ + container_of(pg_cntl, struct dcn_pg_cntl, base) + +#define REG(reg) \ + (pg_cntl_dcn->regs->reg) + +#undef FN +#define FN(reg_name, field_name) \ + pg_cntl_dcn->pg_cntl_shift->field_name, pg_cntl_dcn->pg_cntl_mask->field_name + +#define CTX \ + pg_cntl_dcn->base.ctx +#define DC_LOGGER \ + pg_cntl->ctx->logger + +static bool pg_cntl42_dsc_pg_status(struct pg_cntl *pg_cntl, unsigned int dsc_inst) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + if (pg_cntl->ctx->dc->debug.ignore_pg) + return true; + + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_GET(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 1: /* DSC1 */ + REG_GET(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 2: /* DSC2 */ + REG_GET(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 3: /* DSC3 */ + REG_GET(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + return pwr_status == 0; +} + +void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl = 0; + bool block_enabled; + + /*need to enable dscclk regardless DSC_PG*/ + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) + pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( + pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_dsc_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, dsc_inst); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + switch (dsc_inst) { + case 0: /* DSC0 */ + REG_UPDATE(DOMAIN16_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN16_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 1: /* DSC1 */ + REG_UPDATE(DOMAIN17_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN17_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 2: /* DSC2 */ + REG_UPDATE(DOMAIN18_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN18_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + case 3: /* DSC3 */ + REG_UPDATE(DOMAIN19_PG_CONFIG, + DOMAIN_POWER_GATE, power_gate); + + REG_WAIT(DOMAIN19_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, pwr_status, + 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + + if (dsc_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_DSC][dsc_inst] = power_on; + + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { + /*this is to disable dscclk*/ + pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( + pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); + } +} + +static bool pg_cntl42_hubp_dpp_pg_status(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + switch (hubp_dpp_inst) { + case 0: + /* DPP0 & HUBP0 */ + REG_GET(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 1: + /* DPP1 & HUBP1 */ + REG_GET(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 2: + /* DPP2 & HUBP2 */ + REG_GET(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + case 3: + /* DPP3 & HUBP3 */ + REG_GET(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + return pwr_status == 0; +} + +void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, unsigned int hubp_dpp_inst, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + bool block_enabled; + bool skip_pg = pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hubp_power_gate || + pg_cntl->ctx->dc->debug.disable_dpp_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed; + + if (skip_pg && !power_on) + return; + + block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, hubp_dpp_inst); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + + switch (hubp_dpp_inst) { + case 0: + /* DPP0 & HUBP0 */ + REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 1: + /* DPP1 & HUBP1 */ + REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 2: + /* DPP2 & HUBP2 */ + REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + case 3: + /* DPP3 & HUBP3 */ + REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + break; + default: + BREAK_TO_DEBUGGER(); + break; + } + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + DC_LOG_DEBUG("HUBP DPP instance %d, power %s", hubp_dpp_inst, + power_on ? "ON" : "OFF"); + + if (hubp_dpp_inst < MAX_PIPES) { + pg_cntl->pg_pipe_res_enable[PG_HUBP][hubp_dpp_inst] = power_on; + pg_cntl->pg_pipe_res_enable[PG_DPP][hubp_dpp_inst] = power_on; + } +} + +static bool pg_cntl42_hpo_pg_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN25_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + uint32_t power_forceon; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_hpo_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_hpo_pg_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); + if (power_forceon) + return; + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + REG_UPDATE(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + pg_cntl->pg_res_enable[PG_HPO] = power_on; +} + +static bool pg_cntl42_io_clk_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN22_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + uint32_t power_forceon; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_io_clk_power_gate) + return; + + block_enabled = pg_cntl42_io_clk_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); + if (power_forceon) + return; + + if (!power_on) { + if (!pg_cntl->pg_res_enable[PG_DCCG] || !pg_cntl->pg_res_enable[PG_DCIO] || !pg_cntl->pg_res_enable[PG_DCOH]) + return; + } + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + /* DCCG, DCOH, DCIO */ + REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + pg_cntl->pg_res_enable[PG_DCCG] = power_on; + pg_cntl->pg_res_enable[PG_DCOH] = power_on; + pg_cntl->pg_res_enable[PG_DCIO] = power_on; +} + +static bool pg_cntl42_plane_otg_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN24_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl, + unsigned int mpcc_inst, bool power_on) +{ + if (pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + if (mpcc_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on; +} + +void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl, + unsigned int opp_inst, bool power_on) +{ + if (pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + if (opp_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on; +} + +void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl, + unsigned int optc_inst, bool power_on) +{ + // Defer the ONO domain power up/down to plane_otg_pg_control + if (pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + if (optc_inst < MAX_PIPES) + pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on; +} +static bool pg_cntl42_mem_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN23_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + uint32_t power_forceon; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_mem_power_gate) + return; + + block_enabled = pg_cntl42_mem_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, &power_forceon); + if (power_forceon) + return; + + if (!power_on) { + if (!pg_cntl->pg_res_enable[PG_DCHUBBUB] || !pg_cntl->pg_res_enable[PG_DCHVM]) + return; + } + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + /* DCHUBBUB, DCHUBBUBMEMn, DCHVM */ + REG_UPDATE(DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + pg_cntl->pg_res_enable[PG_DCHUBBUB] = power_on; + pg_cntl->pg_res_enable[PG_DCHVM] = power_on; +} +static bool pg_cntl42_dio_pg_status(struct pg_cntl *pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t pwr_status = 0; + + REG_GET(DOMAIN26_PG_STATUS, + DOMAIN_PGFSM_PWR_STATUS, &pwr_status); + + return pwr_status == 0; +} + +void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + bool block_enabled; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->idle_optimizations_allowed || + pg_cntl->ctx->dc->debug.disable_dio_power_gate) + return; + + block_enabled = pg_cntl42_dio_pg_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, false); + } + /* DIO */ + REG_UPDATE(DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + if (power_on) { + if (pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg) + pg_cntl->ctx->dc->res_pool->dccg->funcs->dccg_enable_global_fgcg(pg_cntl->ctx->dc->res_pool->dccg, true); + } + pg_cntl->pg_res_enable[PG_DIO] = power_on; + +} + +void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl); + uint32_t power_gate = power_on ? 0 : 1; + uint32_t pwr_status = power_on ? 0 : 2; + uint32_t org_ip_request_cntl; + int i; + bool block_enabled; + bool all_mpcc_disabled = true, all_opp_disabled = true; + bool all_optc_disabled = true, all_stream_disabled = true; + + if (pg_cntl->ctx->dc->debug.ignore_pg || + pg_cntl->ctx->dc->debug.disable_optc_power_gate || + pg_cntl->ctx->dc->idle_optimizations_allowed) + return; + + block_enabled = pg_cntl42_plane_otg_status(pg_cntl); + if (power_on) { + if (block_enabled) + return; + } else { + if (!block_enabled) + return; + } + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &pg_cntl->ctx->dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx) { + if (pipe_ctx->stream) + all_stream_disabled = false; + } + + if (pg_cntl->pg_pipe_res_enable[PG_MPCC][i]) + all_mpcc_disabled = false; + + if (pg_cntl->pg_pipe_res_enable[PG_OPP][i]) + all_opp_disabled = false; + + if (pg_cntl->pg_pipe_res_enable[PG_OPTC][i]) + all_optc_disabled = false; + } + + if (!power_on) { + if (!all_mpcc_disabled || !all_opp_disabled || !all_optc_disabled + || !all_stream_disabled) + return; + } + + REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl); + if (org_ip_request_cntl == 0) + REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); + + /* MPC, OPP, OPTC, DWB */ + REG_UPDATE(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, power_gate); + REG_WAIT(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, pwr_status, 1, 1000); + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = power_on; + pg_cntl->pg_pipe_res_enable[PG_OPP][i] = power_on; + pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = power_on; + } +} + + +void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl) +{ + int i = 0; + bool block_enabled; + + pg_cntl->pg_res_enable[PG_HPO] = pg_cntl42_hpo_pg_status(pg_cntl); + + block_enabled = pg_cntl42_io_clk_status(pg_cntl); + pg_cntl->pg_res_enable[PG_DCCG] = block_enabled; + pg_cntl->pg_res_enable[PG_DCIO] = block_enabled; + pg_cntl->pg_res_enable[PG_DCOH] = block_enabled; + + block_enabled = pg_cntl42_dio_pg_status(pg_cntl); + pg_cntl->pg_res_enable[PG_DIO] = block_enabled; + + block_enabled = pg_cntl42_mem_status(pg_cntl); + pg_cntl->pg_res_enable[PG_DCHUBBUB] = block_enabled; + pg_cntl->pg_res_enable[PG_DCHVM] = block_enabled; + + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + block_enabled = pg_cntl42_hubp_dpp_pg_status(pg_cntl, i); + pg_cntl->pg_pipe_res_enable[PG_HUBP][i] = block_enabled; + pg_cntl->pg_pipe_res_enable[PG_DPP][i] = block_enabled; + + block_enabled = pg_cntl42_dsc_pg_status(pg_cntl, i); + pg_cntl->pg_pipe_res_enable[PG_DSC][i] = block_enabled; + } + + block_enabled = pg_cntl42_plane_otg_status(pg_cntl); + for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { + pg_cntl->pg_pipe_res_enable[PG_MPCC][i] = block_enabled; + pg_cntl->pg_pipe_res_enable[PG_OPP][i] = block_enabled; + pg_cntl->pg_pipe_res_enable[PG_OPTC][i] = block_enabled; + } +} + +static const struct pg_cntl_funcs pg_cntl42_funcs = { + .init_pg_status = pg_cntl42_init_pg_status, + .dsc_pg_control = pg_cntl42_dsc_pg_control, + .hubp_dpp_pg_control = pg_cntl42_hubp_dpp_pg_control, + .hpo_pg_control = pg_cntl42_hpo_pg_control, + .io_clk_pg_control = pg_cntl42_io_clk_pg_control, + .plane_otg_pg_control = pg_cntl42_plane_otg_pg_control, + .mpcc_pg_control = pg_cntl42_mpcc_pg_control, + .opp_pg_control = pg_cntl42_opp_pg_control, + .optc_pg_control = pg_cntl42_optc_pg_control, + .mem_pg_control = pg_cntl42_mem_pg_control, + .dio_pg_control = pg_cntl42_dio_pg_control +}; + +struct pg_cntl *pg_cntl42_create( + struct dc_context *ctx, + const struct pg_cntl_registers *regs, + const struct pg_cntl_shift *pg_cntl_shift, + const struct pg_cntl_mask *pg_cntl_mask) +{ + struct dcn_pg_cntl *pg_cntl_dcn = kzalloc(sizeof(*pg_cntl_dcn), GFP_KERNEL); + struct pg_cntl *base; + + if (pg_cntl_dcn == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + base = &pg_cntl_dcn->base; + base->ctx = ctx; + base->funcs = &pg_cntl42_funcs; + + pg_cntl_dcn->regs = regs; + pg_cntl_dcn->pg_cntl_shift = pg_cntl_shift; + pg_cntl_dcn->pg_cntl_mask = pg_cntl_mask; + + memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); + memset(base->pg_res_enable, 0, PG_HW_RESOURCES_NUM_ELEMENT * sizeof(bool)); + + return &pg_cntl_dcn->base; +} + +void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl) +{ + struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(*pg_cntl); + + kfree(pg_cntl_dcn); + *pg_cntl = NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h new file mode 100644 index 0000000000000..a0aa14a796f4c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/pg/dcn42/dcn42_pg_cntl.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2026 Advanced Micro Devices, Inc.*/ + +#ifndef __DCN42_PG_CNTL_H__ +#define __DCN42_PG_CNTL_H__ + +#include "pg_cntl.h" + +#define PG_CNTL_REG_LIST_DCN42()\ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN19_PG_CONFIG), \ + SR(DOMAIN22_PG_CONFIG), \ + SR(DOMAIN23_PG_CONFIG), \ + SR(DOMAIN24_PG_CONFIG), \ + SR(DOMAIN25_PG_CONFIG), \ + SR(DOMAIN26_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(DOMAIN19_PG_STATUS), \ + SR(DOMAIN22_PG_STATUS), \ + SR(DOMAIN23_PG_STATUS), \ + SR(DOMAIN24_PG_STATUS), \ + SR(DOMAIN25_PG_STATUS), \ + SR(DOMAIN26_PG_STATUS), \ + SR(DC_IP_REQUEST_CNTL) + +#define PG_CNTL_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix + +#define PG_CNTL_MASK_SH_LIST_DCN42(mask_sh) \ + PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_STATUS, DOMAIN_DESIRED_PWR_STATE, mask_sh), \ + PG_CNTL_SF(DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + PG_CNTL_SF(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) + +struct pg_cntl_shift { + uint8_t IP_REQUEST_EN; + uint8_t DOMAIN_POWER_FORCEON; + uint8_t DOMAIN_POWER_GATE; + uint8_t DOMAIN_DESIRED_PWR_STATE; + uint8_t DOMAIN_PGFSM_PWR_STATUS; +}; +struct pg_cntl_mask { + uint32_t IP_REQUEST_EN; + uint32_t DOMAIN_POWER_FORCEON; + uint32_t DOMAIN_POWER_GATE; + uint32_t DOMAIN_DESIRED_PWR_STATE; + uint32_t DOMAIN_PGFSM_PWR_STATUS; +}; + +struct pg_cntl_registers { + uint32_t LONO_STATE; + uint32_t DC_IP_REQUEST_CNTL; + uint32_t DOMAIN0_PG_CONFIG; + uint32_t DOMAIN1_PG_CONFIG; + uint32_t DOMAIN2_PG_CONFIG; + uint32_t DOMAIN3_PG_CONFIG; + uint32_t DOMAIN16_PG_CONFIG; + uint32_t DOMAIN17_PG_CONFIG; + uint32_t DOMAIN18_PG_CONFIG; + uint32_t DOMAIN19_PG_CONFIG; + uint32_t DOMAIN22_PG_CONFIG; + uint32_t DOMAIN23_PG_CONFIG; + uint32_t DOMAIN24_PG_CONFIG; + uint32_t DOMAIN25_PG_CONFIG; + uint32_t DOMAIN26_PG_CONFIG; + uint32_t DOMAIN0_PG_STATUS; + uint32_t DOMAIN1_PG_STATUS; + uint32_t DOMAIN2_PG_STATUS; + uint32_t DOMAIN3_PG_STATUS; + uint32_t DOMAIN16_PG_STATUS; + uint32_t DOMAIN17_PG_STATUS; + uint32_t DOMAIN18_PG_STATUS; + uint32_t DOMAIN19_PG_STATUS; + uint32_t DOMAIN22_PG_STATUS; + uint32_t DOMAIN23_PG_STATUS; + uint32_t DOMAIN24_PG_STATUS; + uint32_t DOMAIN25_PG_STATUS; + uint32_t DOMAIN26_PG_STATUS; +}; + +struct dcn_pg_cntl { + struct pg_cntl base; + const struct pg_cntl_registers *regs; + const struct pg_cntl_shift *pg_cntl_shift; + const struct pg_cntl_mask *pg_cntl_mask; +}; + +void pg_cntl42_dsc_pg_control(struct pg_cntl *pg_cntl, unsigned int dsc_inst, bool power_on); +void pg_cntl42_hubp_dpp_pg_control(struct pg_cntl *pg_cntl, + unsigned int hubp_dpp_inst, bool power_on); +void pg_cntl42_hpo_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_plane_otg_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_mpcc_pg_control(struct pg_cntl *pg_cntl, + unsigned int mpcc_inst, bool power_on); +void pg_cntl42_opp_pg_control(struct pg_cntl *pg_cntl, + unsigned int opp_inst, bool power_on); +void pg_cntl42_optc_pg_control(struct pg_cntl *pg_cntl, + unsigned int optc_inst, bool power_on); +void pg_cntl42_mem_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void pg_cntl42_dio_pg_control(struct pg_cntl *pg_cntl, bool power_on); +void dcn42_pg_cntl_destroy(struct pg_cntl **pg_cntl); +void pg_cntl42_init_pg_status(struct pg_cntl *pg_cntl); + +struct pg_cntl *pg_cntl42_create( + struct dc_context *ctx, + const struct pg_cntl_registers *regs, + const struct pg_cntl_shift *pg_cntl_shift, + const struct pg_cntl_mask *pg_cntl_mask); + +void dcn_pg_cntl_destroy(struct pg_cntl **pg_cntl); + +#endif /* DCN42_PG_CNTL */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/Makefile b/drivers/gpu/drm/amd/display/dc/resource/Makefile index 5b42da8b79c2e..1a17a885fe84b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/Makefile +++ b/drivers/gpu/drm/amd/display/dc/resource/Makefile @@ -222,4 +222,22 @@ AMD_DAL_RESOURCE_DCN401 = $(addprefix $(AMDDALPATH)/dc/resource/dcn401/,$(RESOUR AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN401) +############################################################################### +# DCN42 +############################################################################### +RESOURCE_DCN42 = dcn42_resource.o dcn42_resource_fpu.o + +AMD_DAL_RESOURCE_DCN42 = $(addprefix $(AMDDALPATH)/dc/resource/dcn42/,$(RESOURCE_DCN42)) + +AMD_DISPLAY_FILES += $(AMD_DAL_RESOURCE_DCN42) + +# FPU Compile Flags for FPU files +resource_ccflags := $(CC_FLAGS_FPU) +resource_rcflags := $(CC_FLAGS_NO_FPU) + +CFLAGS_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_ccflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/resource/dcn42/dcn42_resource_fpu.o := $(resource_rcflags) + +############################################################################### endif + diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c index d40d91ec2035f..2b884e28727ba 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c @@ -31,7 +31,7 @@ #include "resource.h" #include "clk_mgr.h" #include "include/irq_service_interface.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce110/dce110_timing_generator.h" #include "irq/dce110/irq_service_dce110.h" @@ -226,7 +226,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), link_regs(6), - { .DAC_ENABLE = mmDAC_ENABLE }, + {0} }; #define stream_enc_regs(id)\ @@ -242,7 +242,8 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(3), stream_enc_regs(4), stream_enc_regs(5), - stream_enc_regs(6) + stream_enc_regs(6), + {SR(DAC_SOURCE_SELECT),} /* DACA */ }; static const struct dce_stream_encoder_shift se_shift = { @@ -491,7 +492,8 @@ static struct stream_encoder *dce100_stream_encoder_create( return NULL; if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { - dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; } @@ -638,7 +640,8 @@ static struct link_encoder *dce100_link_encoder_create( if (!enc110) return NULL; - if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + if (enc_init_data->connector.id == CONNECTOR_ID_VGA && + enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) { dce110_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, @@ -648,9 +651,6 @@ static struct link_encoder *dce100_link_encoder_create( return &enc110->base; } - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) - return NULL; - link_regs_id = map_transmitter_id_to_phy_instance(enc_init_data->transmitter); @@ -659,7 +659,8 @@ static struct link_encoder *dce100_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } @@ -978,7 +979,10 @@ struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link( struct dc_link *link = stream->link; enum engine_id preferred_engine = link->link_enc->preferred_engine; - if (dc_is_rgb_signal(stream->signal)) + /* Prefer analog engine if the link encoder has one. + * Otherwise, it's an external encoder. + */ + if (dc_is_rgb_signal(stream->signal) && link->link_enc->analog_engine != ENGINE_ID_UNKNOWN) preferred_engine = link->link_enc->analog_engine; for (i = 0; i < pool->stream_enc_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c index cd54382c0af3e..d957598911cbc 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c @@ -672,7 +672,7 @@ static struct link_encoder *dce110_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) return NULL; link_regs_id = @@ -683,7 +683,8 @@ static struct link_encoder *dce110_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } @@ -895,6 +896,8 @@ static void get_pixel_clock_parameters( */ pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; pixel_clk_params->encoder_object_id = stream->link->link_enc->id; + if (dc_is_rgb_signal(pipe_ctx->stream->signal)) + pixel_clk_params->encoder_object_id = stream->link->link_enc->analog_id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; /* TODO: un-hardcode*/ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c index 3f0a6bc4dcc23..1cce903d477aa 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c @@ -633,7 +633,7 @@ static struct link_encoder *dce112_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) return NULL; link_regs_id = @@ -644,7 +644,8 @@ static struct link_encoder *dce112_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c index b1570b6b1af30..8b568be20a77b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c @@ -35,7 +35,7 @@ #include "dce112/dce112_resource.h" #include "dce110/dce110_resource.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce120/dce120_timing_generator.h" #include "irq/dce120/irq_service_dce120.h" #include "dce/dce_opp.h" @@ -717,7 +717,7 @@ static struct link_encoder *dce120_link_encoder_create( kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc110 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + if (!enc110) return NULL; link_regs_id = @@ -728,7 +728,8 @@ static struct link_encoder *dce120_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c index f0152933bee2c..2f5ee9d8536af 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c @@ -243,7 +243,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), {0}, - { .DAC_ENABLE = mmDAC_ENABLE }, + {0} }; #define stream_enc_regs(id)\ @@ -258,7 +258,9 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(2), stream_enc_regs(3), stream_enc_regs(4), - stream_enc_regs(5) + stream_enc_regs(5), + {0}, + {SR(DAC_SOURCE_SELECT),} /* DACA */ }; static const struct dce_stream_encoder_shift se_shift = { @@ -495,7 +497,7 @@ static void read_dce_straps( static struct audio *create_audio( struct dc_context *ctx, unsigned int inst) { - return dce60_audio_create(ctx, inst, + return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask); } @@ -607,7 +609,8 @@ static struct stream_encoder *dce60_stream_encoder_create( return NULL; if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { - dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; } @@ -733,8 +736,9 @@ static struct link_encoder *dce60_link_encoder_create( if (!enc110) return NULL; - if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { - dce110_link_encoder_construct(enc110, + if (enc_init_data->connector.id == CONNECTOR_ID_VGA && + enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) { + dce60_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, &link_enc_regs[ENGINE_ID_DACA], @@ -743,18 +747,16 @@ static struct link_encoder *dce60_link_encoder_create( return &enc110->base; } - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) - return NULL; - link_regs_id = map_transmitter_id_to_phy_instance(enc_init_data->transmitter); dce60_link_encoder_construct(enc110, - enc_init_data, - &link_enc_feature, - &link_enc_regs[link_regs_id], - &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data, + &link_enc_feature, + &link_enc_regs[link_regs_id], + &link_enc_aux_regs[enc_init_data->channel - 1], + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c index 8687104cabb72..406705fac7d64 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c @@ -242,7 +242,7 @@ static const struct dce110_link_enc_registers link_enc_regs[] = { link_regs(4), link_regs(5), link_regs(6), - { .DAC_ENABLE = mmDAC_ENABLE }, + {0} }; #define stream_enc_regs(id)\ @@ -258,7 +258,8 @@ static const struct dce110_stream_enc_registers stream_enc_regs[] = { stream_enc_regs(3), stream_enc_regs(4), stream_enc_regs(5), - stream_enc_regs(6) + stream_enc_regs(6), + {SR(DAC_SOURCE_SELECT),} /* DACA */ }; static const struct dce_stream_encoder_shift se_shift = { @@ -614,7 +615,8 @@ static struct stream_encoder *dce80_stream_encoder_create( return NULL; if (eng_id == ENGINE_ID_DACA || eng_id == ENGINE_ID_DACB) { - dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id); + dce110_analog_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, + &stream_enc_regs[eng_id], &se_shift, &se_mask); return &enc110->base; } @@ -740,7 +742,8 @@ static struct link_encoder *dce80_link_encoder_create( if (!enc110) return NULL; - if (enc_init_data->connector.id == CONNECTOR_ID_VGA) { + if (enc_init_data->connector.id == CONNECTOR_ID_VGA && + enc_init_data->analog_engine != ENGINE_ID_UNKNOWN) { dce110_link_encoder_construct(enc110, enc_init_data, &link_enc_feature, @@ -750,9 +753,6 @@ static struct link_encoder *dce80_link_encoder_create( return &enc110->base; } - if (enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) - return NULL; - link_regs_id = map_transmitter_id_to_phy_instance(enc_init_data->transmitter); @@ -761,7 +761,8 @@ static struct link_encoder *dce80_link_encoder_create( &link_enc_feature, &link_enc_regs[link_regs_id], &link_enc_aux_regs[enc_init_data->channel - 1], - &link_enc_hpd_regs[enc_init_data->hpd_source]); + enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs) ? + NULL : &link_enc_hpd_regs[enc_init_data->hpd_source]); return &enc110->base; } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index f12367adf1451..9c1a57a1f989e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -48,7 +48,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" #include "dcn10/dcn10_hubp.h" @@ -1275,6 +1275,12 @@ static const struct dc_cap_funcs cap_funcs = { .get_dcc_compression_cap = dcn10_get_dcc_compression_cap }; +void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info) +{ + tiling_info->gfxversion = DcGfxVersion9; + tiling_info->gfx9.swizzle = DC_SW_LINEAR; +} + static const struct resource_funcs dcn10_res_pool_funcs = { .destroy = dcn10_destroy_resource_pool, .link_enc_create = dcn10_link_encoder_create, @@ -1286,7 +1292,8 @@ static const struct resource_funcs dcn10_res_pool_funcs = { .add_stream_to_ctx = dcn10_add_stream_to_ctx, .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static uint32_t read_pipe_fuses(struct dc_context *ctx) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h index 7bc1be53e8009..c7409298caa9a 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.h @@ -53,5 +53,7 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( unsigned int dcn10_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); +void dcn10_get_default_tiling_info(struct dc_tiling_info *tiling_info); + #endif /* __DC_RESOURCE_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 6679c1a14f2fe..e954c340e08d2 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -55,7 +55,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn20/dcn20_dccg.h" @@ -1057,7 +1057,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } - struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1079,7 +1078,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) *dsc = NULL; } - static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { unsigned int i; @@ -1322,7 +1320,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } - void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1372,8 +1369,6 @@ void dcn20_release_dsc(struct resource_context *res_ctx, } } - - enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) @@ -1430,7 +1425,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, return DC_OK; } - enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -1527,7 +1521,6 @@ bool dcn20_split_stream_for_odm( if (next_odm_pipe->stream_res.dsc == NULL) return false; } - return true; } @@ -1660,8 +1653,8 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) continue; - dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left - + stream->timing.h_border_right) / opp_cnt; + dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding + + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; @@ -1669,7 +1662,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding; + dsc_cfg.dsc_padding = 0; if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) return false; @@ -2022,9 +2015,7 @@ bool dcn20_fast_validate_bw( dcn20_merge_pipes_for_validate(dc, context); - DC_FP_START(); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); - DC_FP_END(); *pipe_cnt_out = pipe_cnt; @@ -2233,7 +2224,8 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .set_mcif_arb_params = dcn20_set_mcif_arb_params, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) @@ -2344,8 +2336,6 @@ static bool init_soc_bounding_box(struct dc *dc, struct _vcs_dpi_ip_params_st *loaded_ip = get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); - DC_LOGGER_INIT(dc->ctx->logger); - if (pool->base.pp_smu) { struct pp_smu_nv_clock_table max_clocks = {0}; unsigned int uclk_states[8] = {0}; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index 055107843a70a..5f0b592a3dc7e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -51,7 +51,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dce/dce_aux.h" #include "dce/dce_i2c.h" @@ -1081,7 +1081,8 @@ static struct resource_funcs dcn201_res_pool_funcs = { .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .set_mcif_arb_params = dcn20_set_mcif_arb_params, .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn201_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 2060acd5ae098..d5b53ab5e2675 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -57,7 +57,7 @@ #include "dce/dce_clock_source.h" #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn20/dcn20_dccg.h" #include "dcn21/dcn21_dccg.h" @@ -785,9 +785,7 @@ bool dcn21_fast_validate_bw(struct dc *dc, dcn20_merge_pipes_for_validate(dc, context); - DC_FP_START(); pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, validate_mode); - DC_FP_END(); *pipe_cnt_out = pipe_cnt; @@ -1088,7 +1086,6 @@ static void read_dce_straps( } - static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1381,7 +1378,8 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, .update_bw_bounding_box = dcn21_update_bw_bounding_box, .get_panel_config_defaults = dcn21_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn21_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index d0ebb733e8024..66b1a1c2db1da 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -55,7 +55,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn30/dcn30_dccg.h" @@ -2252,7 +2252,8 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .update_bw_bounding_box = dcn30_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn30_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; #define CTX ctx diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 3ad6a3d4858e7..ff3c4e5c5cf0d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -54,7 +54,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn301/dcn301_dccg.h" @@ -1240,7 +1240,6 @@ static struct display_stream_compressor *dcn301_dsc_create( return &dsc->base; } - static void dcn301_destroy_resource_pool(struct resource_pool **pool) { struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool); @@ -1404,7 +1403,8 @@ static struct resource_funcs dcn301_res_pool_funcs = { .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut, .update_bw_bounding_box = dcn301_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info, }; static bool dcn301_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index c0d4a1dc94f8a..7c4c5c8aa4b69 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -1155,7 +1155,8 @@ static struct resource_funcs dcn302_res_pool_funcs = { .update_bw_bounding_box = dcn302_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn302_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static struct dc_cap_funcs cap_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 75e09c2c283e0..360934bc54818 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -1099,7 +1099,8 @@ static struct resource_funcs dcn303_res_pool_funcs = { .update_bw_bounding_box = dcn303_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn303_get_panel_config_defaults, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static struct dc_cap_funcs cap_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index 0d667b54ccf81..95c7ecdb34961 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -64,7 +64,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" @@ -1855,6 +1855,7 @@ static struct resource_funcs dcn31_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, + .get_default_tiling_info = dcn10_get_default_tiling_info, .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params }; @@ -1966,6 +1967,8 @@ static bool dcn31_resource_construct( dc->config.use_pipe_ctx_sync_logic = true; dc->config.disable_hbr_audio_dp2 = true; + dc->config.no_native422_support = true; + /* read VBIOS LTTPR caps */ { if (ctx->dc_bios->funcs->get_lttpr_caps) { @@ -2250,12 +2253,15 @@ enum dc_status dcn31_update_dc_state_for_encoder_switch(struct dc_link *link, int i; #if defined(CONFIG_DRM_AMD_DC_FP) - for (i = 0; i < state->stream_count; i++) - if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) - link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]); + if (link->dc->hwss.calculate_pix_rate_divider) { + for (i = 0; i < state->stream_count; i++) + if (state->streams[i] && state->streams[i]->link && state->streams[i]->link == link) + link->dc->hwss.calculate_pix_rate_divider((struct dc *)link->dc, state, state->streams[i]); + } for (i = 0; i < pipe_count; i++) { - link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]); + if (link->dc->res_pool->funcs->build_pipe_pix_clk_params) + link->dc->res_pool->funcs->build_pipe_pix_clk_params(&pipes[i]); // Setup audio if (pipes[i].stream_res.audio != NULL) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 3ccde75a4ecbf..803b87986802b 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -66,7 +66,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" @@ -1786,7 +1786,8 @@ static struct resource_funcs dcn314_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static struct clock_source *dcn30_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 4e962f522f1be..e488fa6f32e67 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -63,7 +63,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" @@ -1230,12 +1230,12 @@ static struct stream_encoder *dcn315_stream_encoder_create( /*PHYB is wired off in HW, allow front end to remapping, otherwise needs more changes*/ /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); @@ -1850,7 +1850,8 @@ static struct resource_funcs dcn315_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn315_resource_construct( @@ -1928,6 +1929,8 @@ static bool dcn315_resource_construct( dc->caps.color.mpc.ogam_rom_caps.hlg = 0; dc->caps.color.mpc.ocsc = 1; + dc->config.no_native422_support = true; + /* read VBIOS LTTPR caps */ { if (ctx->dc_bios->funcs->get_lttpr_caps) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 5a95dd54cb429..f6ec8708f2bf8 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -63,7 +63,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dml/dcn31/dcn31_fpu.h" @@ -557,6 +557,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; + #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -1223,12 +1224,12 @@ static struct stream_encoder *dcn316_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); @@ -1725,7 +1726,8 @@ static struct resource_funcs dcn316_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn316_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index b276fec3e479a..5c0658a609a81 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -65,7 +65,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" @@ -1211,12 +1211,12 @@ static struct stream_encoder *dcn32_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn32_vpg_create(ctx, vpg_inst); afmt = dcn32_afmt_create(ctx, afmt_inst); @@ -1789,7 +1789,10 @@ static bool dml1_validate(struct dc *dc, struct dc_state *context, enum dc_valid dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel); + DC_FP_START(); dcn32_override_min_req_memclk(dc, context); + DC_FP_END(); + dcn32_override_min_req_dcfclk(dc, context); BW_VAL_TRACE_END_WATERMARKS(); @@ -2113,6 +2116,7 @@ static struct resource_funcs dcn32_res_pool_funcs = { .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .add_phantom_pipes = dcn32_add_phantom_pipes, + .get_default_tiling_info = dcn10_get_default_tiling_info, .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 99f0432288b44..91be493e0bb6d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -317,7 +317,10 @@ unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc, AUX_REG_LIST_RI(id), SRI_ARR(AUX_DPHY_TX_CONTROL, DP_AUX, id) /* HDP */ -#define HPD_REG_LIST_RI(id) SRI_ARR(DC_HPD_CONTROL, HPD, id) +#define HPD_REG_LIST_RI(id) \ + (SRI_ARR(DC_HPD_CONTROL, HPD, id), \ + SRI_ARR(DC_HPD_INT_STATUS, HPD, id), \ + SRI_ARR(DC_HPD_TOGGLE_FILT_CNTL, HPD, id)) /* Link encoder */ #define LE_DCN3_REG_LIST_RI(id) \ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 3466ca34c93fe..d3c60bed7735f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -68,7 +68,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn32/dcn32_dccg.h" #include "dcn10/dcn10_resource.h" @@ -445,7 +445,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; - static struct dcn30_mpc_registers mpc_regs; #define dcn_mpc_regs_init()\ MPC_REG_LIST_DCN3_2_RI(0),\ @@ -1192,12 +1191,12 @@ static struct stream_encoder *dcn321_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn321_vpg_create(ctx, vpg_inst); afmt = dcn321_afmt_create(ctx, afmt_inst); @@ -1376,7 +1375,6 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } - if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); pool->base.mpc = NULL; @@ -1623,6 +1621,7 @@ static struct resource_funcs dcn321_res_pool_funcs = { .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, + .get_default_tiling_info = dcn10_get_default_tiling_info, }; static uint32_t read_pipe_fuses(struct dc_context *ctx) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index d056e5fd54587..f7e2e79bc0e15 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -70,7 +70,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn35/dcn35_dccg.h" @@ -788,7 +788,7 @@ static const struct dc_debug_options debug_defaults_drv = { }; static const struct dc_check_config config_defaults = { - .enable_legacy_fast_update = true, + .enable_legacy_fast_update = false, }; static const struct dc_panel_config panel_config_defaults = { @@ -1274,12 +1274,12 @@ static struct stream_encoder *dcn35_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); @@ -1805,7 +1805,8 @@ static struct resource_funcs dcn35_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn35_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 9fab3169069c4..5dffaf12a7c0d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -49,7 +49,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn35/dcn35_dccg.h" @@ -768,7 +768,7 @@ static const struct dc_debug_options debug_defaults_drv = { }; static const struct dc_check_config config_defaults = { - .enable_legacy_fast_update = true, + .enable_legacy_fast_update = false, }; static const struct dc_panel_config panel_config_defaults = { @@ -1254,12 +1254,12 @@ static struct stream_encoder *dcn35_stream_encoder_create( int afmt_inst; /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */ - if (eng_id <= ENGINE_ID_DIGF) { - vpg_inst = eng_id; - afmt_inst = eng_id; - } else + if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs)) return NULL; + vpg_inst = eng_id; + afmt_inst = eng_id; + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); vpg = dcn31_vpg_create(ctx, vpg_inst); afmt = dcn31_afmt_create(ctx, afmt_inst); @@ -1778,7 +1778,8 @@ static struct resource_funcs dcn351_res_pool_funcs = { .get_det_buffer_size = dcn31_get_det_buffer_size, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info }; static bool dcn351_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c index 6469d5fe2e6d4..40894afd990e4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c @@ -49,7 +49,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" #include "dml/display_mode_vba.h" #include "dcn35/dcn35_dccg.h" @@ -460,16 +460,22 @@ static const struct dcn30_mpc_mask mpc_mask = { }; #define optc_regs_init(id)\ - OPTC_COMMON_REG_LIST_DCN3_5_RI(id) + OPTC_COMMON_REG_LIST_DCN3_5_RI(id),\ + SRI_ARR(OTG_CRC0_DATA_R32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC0_DATA_G32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC0_DATA_B32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC1_DATA_R32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC1_DATA_G32, OTG_CRC32, id),\ + SRI_ARR(OTG_CRC1_DATA_B32, OTG_CRC32, id) static struct dcn_optc_registers optc_regs[4]; static const struct dcn_optc_shift optc_shift = { - OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT) + OPTC_COMMON_MASK_SH_LIST_DCN3_6(__SHIFT) }; static const struct dcn_optc_mask optc_mask = { - OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK) + OPTC_COMMON_MASK_SH_LIST_DCN3_6(_MASK) }; #define hubp_regs_init(id)\ @@ -769,7 +775,7 @@ static const struct dc_debug_options debug_defaults_drv = { }; static const struct dc_check_config config_defaults = { - .enable_legacy_fast_update = true, + .enable_legacy_fast_update = false, }; static const struct dc_panel_config panel_config_defaults = { @@ -1778,7 +1784,8 @@ static struct resource_funcs dcn36_res_pool_funcs = { .get_preferred_eng_id_dpia = dcn36_get_preferred_eng_id_dpia, .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch, - .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params + .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, + .get_default_tiling_info = dcn10_get_default_tiling_info, }; static bool dcn36_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 875ae97489d32..7ac2f38bfde8d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -21,6 +21,7 @@ #include "dcn401/dcn401_hubbub.h" #include "dcn401/dcn401_mpc.h" #include "dcn401/dcn401_hubp.h" +#include "dio/dcn10/dcn10_dio.h" #include "irq/dcn401/irq_service_dcn401.h" #include "dcn401/dcn401_dpp.h" #include "dcn401/dcn401_optc.h" @@ -46,7 +47,7 @@ #include "dce/dce_audio.h" #include "dce/dce_hwseq.h" #include "clk_mgr.h" -#include "virtual/virtual_stream_encoder.h" +#include "dio/virtual/virtual_stream_encoder.h" #include "dml/display_mode_vba.h" #include "dcn401/dcn401_dccg.h" #include "dcn10/dcn10_resource.h" @@ -634,6 +635,22 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; +#define dio_regs_init() \ + DIO_REG_LIST_DCN10() + +static struct dcn_dio_registers dio_regs; + +#define DIO_MASK_SH_LIST_DCN401(mask_sh)\ + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh) + +static const struct dcn_dio_shift dio_shift = { + DIO_MASK_SH_LIST_DCN401(__SHIFT) +}; + +static const struct dcn_dio_mask dio_mask = { + DIO_MASK_SH_LIST_DCN401(_MASK) +}; + static const struct resource_caps res_cap_dcn4_01 = { .num_timing_generator = 4, .num_opp = 4, @@ -881,6 +898,22 @@ static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx) return &hubbub2->base; } +static struct dio *dcn401_dio_create(struct dc_context *ctx) +{ + struct dcn10_dio *dio10 = kzalloc(sizeof(struct dcn10_dio), GFP_KERNEL); + + if (!dio10) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT dio_regs + dio_regs_init(); + + dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask); + + return &dio10->base; +} + static struct hubp *dcn401_hubp_create( struct dc_context *ctx, uint32_t inst) @@ -1499,6 +1532,11 @@ static void dcn401_resource_destruct(struct dcn401_resource_pool *pool) if (pool->base.dccg != NULL) dcn_dccg_destroy(&pool->base.dccg); + if (pool->base.dio != NULL) { + kfree(TO_DCN10_DIO(pool->base.dio)); + pool->base.dio = NULL; + } + if (pool->base.oem_device != NULL) { struct dc *dc = pool->base.oem_device->ctx->dc; @@ -1756,7 +1794,7 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) } } -static int dcn401_get_power_profile(const struct dc_state *context) +int dcn401_get_power_profile(const struct dc_state *context) { int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; int dpm_level = 0; @@ -1772,7 +1810,7 @@ static int dcn401_get_power_profile(const struct dc_state *context) return dpm_level; } -static unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) +unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx) { return pipe_ctx->global_sync.dcn4x.vstartup_lines; } @@ -1805,9 +1843,16 @@ static struct resource_funcs dcn401_res_pool_funcs = { .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, .get_power_profile = dcn401_get_power_profile, .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, - .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size + .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, + .get_default_tiling_info = dcn401_get_default_tiling_info }; +void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info) +{ + tiling_info->gfxversion = DcGfxAddr3; + tiling_info->gfx_addr3.swizzle = DC_ADDR3_SW_LINEAR; +} + static uint32_t read_pipe_fuses(struct dc_context *ctx) { uint32_t value = REG_READ(CC_DC_PIPE_DIS); @@ -2071,6 +2116,14 @@ static bool dcn401_resource_construct( goto create_fail; } + /* DIO */ + pool->base.dio = dcn401_dio_create(ctx); + if (pool->base.dio == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dio!\n"); + goto create_fail; + } + /* HUBPs, DPPs, OPPs, TGs, ABMs */ for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index e1fa2e80a15ac..47f82b8182627 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -28,6 +28,11 @@ enum dc_status dcn401_validate_bandwidth(struct dc *dc, void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); +void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info); + +unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx); + +int dcn401_get_power_profile(const struct dc_state *context); /* Following are definitions for run time init of reg offsets */ /* HUBP */ @@ -394,6 +399,7 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \ SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \ SRI_ARR(ISHARP_MODE, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \ SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \ SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \ SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c new file mode 100644 index 0000000000000..6328b3dc35f9d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c @@ -0,0 +1,2340 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "dm_services.h" +#include "dc.h" + +#include "dcn32/dcn32_init.h" +#include "dcn42/dcn42_init.h" + +#include "resource.h" +#include "include/irq_service_interface.h" + +#include "dcn42_resource.h" +#include "dcn42_resource_fpu.h" +#include "dcn20/dcn20_resource.h" +#include "dcn30/dcn30_resource.h" +#include "dcn31/dcn31_resource.h" +#include "dcn32/dcn32_resource.h" +#include "dcn35/dcn35_resource.h" +#include "dcn321/dcn321_resource.h" +#include "dcn401/dcn401_resource.h" + +#include "dcn10/dcn10_ipp.h" +#include "dcn35/dcn35_hubbub.h" +#include "dcn42/dcn42_hubbub.h" +#include "dcn401/dcn401_mpc.h" +#include "dcn42/dcn42_mpc.h" +#include "dcn35/dcn35_hubp.h" +#include "dcn42/dcn42_hubp.h" +#include "irq/dcn42/irq_service_dcn42.h" +#include "dcn42/dcn42_dpp.h" +#include "dcn401/dcn401_dsc.h" +#include "dcn42/dcn42_optc.h" +#include "dcn20/dcn20_hwseq.h" +#include "dcn30/dcn30_hwseq.h" +#include "dce110/dce110_hwseq.h" +#include "dcn35/dcn35_opp.h" +#include "dcn30/dcn30_vpg.h" +#include "dcn31/dcn31_vpg.h" +#include "dcn42/dcn42_dio_stream_encoder.h" +#include "dcn42/dcn42_pg_cntl.h" +#include "dcn31/dcn31_hpo_dp_stream_encoder.h" +#include "dcn31/dcn31_hpo_dp_link_encoder.h" +#include "dcn32/dcn32_hpo_dp_link_encoder.h" +#include "dcn42/dcn42_hpo_dp_link_encoder.h" +#include "dcn31/dcn31_apg.h" +#include "dcn31/dcn31_dio_link_encoder.h" +#include "dcn401/dcn401_dio_link_encoder.h" +#include "dcn10/dcn10_link_encoder.h" +#include "dcn321/dcn321_dio_link_encoder.h" +#include "dce/dce_clock_source.h" +#include "dce/dce_audio.h" +#include "dce/dce_hwseq.h" +#include "clk_mgr.h" +#include "dio/virtual/virtual_stream_encoder.h" +#include "dml/display_mode_vba.h" +#include "dcn42/dcn42_dccg.h" +#include "dcn10/dcn10_resource.h" +#include "link_service.h" +#include "dcn31/dcn31_panel_cntl.h" + +#include "dcn30/dcn30_dwb.h" +#include "dcn42/dcn42_mmhubbub.h" +#include "dcn42/dcn42_dio_link_encoder.h" + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" +#include "dpcs/dpcs_4_0_0_offset.h" +#include "dpcs/dpcs_4_0_0_sh_mask.h" + +#include "reg_helper.h" +#include "dce/dmub_abm.h" +#include "dce/dmub_psr.h" +#include "dce/dmub_replay.h" +#include "dce/dce_aux.h" +#include "dce/dce_i2c.h" + +#include "dml/dcn30/display_mode_vba_30.h" +#include "vm_helper.h" +#include "dcn20/dcn20_vmid.h" + +#include "dc_state_priv.h" +#include "link_enc_cfg.h" + +#include "dml2_0/dml2_wrapper.h" + +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 + +#define DC_LOGGER_INIT(logger) + +enum dcn401_clk_src_array_id { + DCN401_CLK_SRC_PLL0, + DCN401_CLK_SRC_PLL1, + DCN401_CLK_SRC_PLL2, + DCN401_CLK_SRC_PLL3, + DCN401_CLK_SRC_PLL4, + DCN401_CLK_SRC_TOTAL +}; + +/* begin + * macros to expend register list macro defined in HW object header file + */ + +/* DCN */ +#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] + +#define BASE(seg) BASE_INNER(seg) + +#define SR(reg_name) \ + REG_STRUCT.reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name +#define SR_ARR(reg_name, id) \ + REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name +#define SR_ARR_INIT(reg_name, id, value) \ + REG_STRUCT[id].reg_name = value + +#define SRI(reg_name, block, id) \ + REG_STRUCT.reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRI_ARR(reg_name, block, id) \ + REG_STRUCT[id].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +/* + * Used when a reg_name would otherwise begin with an integer + */ +#define SRI_ARR_US(reg_name, block, id) \ + REG_STRUCT[id].reg_name = BASE(reg##block##id##reg_name##_BASE_IDX) + \ + reg##block##id##reg_name +#define SR_ARR_I2C(reg_name, id) \ + REG_STRUCT[id - 1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name + +#define SRI_ARR_I2C(reg_name, block, id) \ + REG_STRUCT[id - 1].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + + +#define SRI_ARR_ALPHABET(reg_name, block, index, id) \ + REG_STRUCT[index].reg_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRI2(reg_name, block, id) \ + .reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name +#define SRI2_ARR(reg_name, block, id) \ + REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + \ + reg##reg_name + +#define SRIR(var_name, reg_name, block, id) \ + .var_name = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII(reg_name, block, id) \ + REG_STRUCT.reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII_ARR_2(reg_name, block, id, inst) \ + REG_STRUCT[inst].reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII_MPC_RMU(reg_name, block, id) \ + .RMU##_##reg_name[id] = BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SRII_DWB(reg_name, temp_name, block, id) \ + REG_STRUCT.reg_name[id] = \ + BASE(reg##block##id##_##temp_name##_BASE_IDX) + \ + reg##block##id##_##temp_name + +#define DCCG_SRII(reg_name, block, id) \ + REG_STRUCT.block##_##reg_name[id] = \ + BASE(reg##block##id##_##reg_name##_BASE_IDX) + \ + reg##block##id##_##reg_name + +#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ + .field_name = reg_name##__##field_name##post_fix + +#define VUPDATE_SRII(reg_name, block, id) \ + REG_STRUCT.reg_name[id] = BASE(reg##reg_name##_##block##id##_BASE_IDX) + \ + reg##reg_name##_##block##id + +/* NBIO */ +#define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] + +#define NBIO_BASE(seg) \ + NBIO_BASE_INNER(seg) + +#define NBIO_SR(reg_name) \ + REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ + regBIF_BX0_##reg_name +#define NBIO_SR_ARR(reg_name, id) \ + REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_##reg_name##_BASE_IDX) + \ + regBIF_BX0_##reg_name + +#define CTX ctx +#define REG(reg_name) \ + (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name) + +static struct bios_registers bios_regs; + +#define bios_regs_init() \ + NBIO_SR(BIOS_SCRATCH_3), \ + NBIO_SR(BIOS_SCRATCH_6) + +#define clk_src_regs_init(index, pllid) \ + CS_COMMON_REG_LIST_DCN42_RI(index, pllid) + +static struct dce110_clk_src_regs clk_src_regs[5]; + +static const struct dce110_clk_src_shift cs_shift = { + CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT) +}; +static const struct dce110_clk_src_mask cs_mask = { + CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK) +}; +#define abm_regs_init(id) \ + ABM_DCN42_REG_LIST_RI(id) + +static struct dce_abm_registers abm_regs[4]; + +static const struct dce_abm_shift abm_shift = { + ABM_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dce_abm_mask abm_mask = { + ABM_MASK_SH_LIST_DCN42(_MASK)}; + +#define audio_regs_init(id) \ + AUD_COMMON_REG_LIST_RI(id) + +static struct dce_audio_registers audio_regs[5]; + +static const struct dce_audio_shift audio_shift = { + DCN42_AUD_COMMON_MASK_SH_LIST(__SHIFT) +}; + +static const struct dce_audio_mask audio_mask = { + DCN42_AUD_COMMON_MASK_SH_LIST(_MASK) +}; + +#define vpg_regs_init(id) \ + VPG_DCN401_REG_LIST_RI(id) + +static struct dcn31_vpg_registers vpg_regs[10]; + +static const struct dcn31_vpg_shift vpg_shift = { + DCN31_VPG_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_vpg_mask vpg_mask = { + DCN31_VPG_MASK_SH_LIST(_MASK)}; + +#define apg_regs_init(id) \ + APG_DCN31_REG_LIST_RI(id) + +static struct dcn31_apg_registers apg_regs[10]; + +static const struct dcn31_apg_shift apg_shift = { + DCN31_APG_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_apg_mask apg_mask = { + DCN31_APG_MASK_SH_LIST(_MASK)}; + +#define stream_enc_regs_init(id) \ + SE_DCN42_REG_LIST_RI(id) + +static struct dcn10_stream_enc_registers stream_enc_regs[5]; + +static const struct dcn10_stream_encoder_shift se_shift = { + SE_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn10_stream_encoder_mask se_mask = { + SE_COMMON_MASK_SH_LIST_DCN42(_MASK)}; + +#define aux_regs_init(id) \ + DCN2_AUX_REG_LIST_RI(id) + +static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; + +#define hpd_regs_init(id) \ + HPD_REG_LIST_RI(id) + +static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; + +#define link_regs_init(id, phyid) \ + LE_DCN401_REG_LIST_RI(id) + +static struct dcn10_link_enc_registers link_enc_regs[5]; + +static const struct dcn10_link_enc_shift le_shift = { + LINK_ENCODER_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn10_link_enc_mask le_mask = { + LINK_ENCODER_MASK_SH_LIST_DCN42(_MASK)}; + +#define hpo_dp_stream_encoder_reg_init(id) \ + DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) + +static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; + +static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { + DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { + DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)}; + +#define hpo_dp_link_encoder_reg_init(id) \ + DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) + +static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4]; + +static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { + DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)}; + +#define dpp_regs_init(id) \ + DPP_REG_LIST_DCN42_COMMON_RI(id) + +static struct dcn42_dpp_registers dpp_regs[4]; + +static const struct dcn42_dpp_shift tf_shift = { + DPP_REG_LIST_SH_MASK_DCN42_COMMON(__SHIFT)}; + +static const struct dcn42_dpp_mask tf_mask = { + DPP_REG_LIST_SH_MASK_DCN42_COMMON(_MASK)}; + +#define opp_regs_init(id) \ + OPP_REG_LIST_DCN401_RI(id) + +static struct dcn20_opp_registers opp_regs[4]; + +static const struct dcn20_opp_shift opp_shift = { + OPP_MASK_SH_LIST_DCN20(__SHIFT)}; + +static const struct dcn20_opp_mask opp_mask = { + OPP_MASK_SH_LIST_DCN20(_MASK)}; + +#define aux_engine_regs_init(id) \ + AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ + SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ + SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \ + SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) + +static struct dce110_aux_registers aux_engine_regs[5]; + +static const struct dce110_aux_registers_shift aux_shift = { + DCN_AUX_MASK_SH_LIST(__SHIFT)}; + +static const struct dce110_aux_registers_mask aux_mask = { + DCN_AUX_MASK_SH_LIST(_MASK)}; + +#define dwbc_regs_dcn401_init(id) \ + DWBC_COMMON_REG_LIST_DCN30_RI(id) + +static struct dcn30_dwbc_registers dwbc401_regs[1]; + +static const struct dcn30_dwbc_shift dwbc401_shift = { + DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)}; + +static const struct dcn30_dwbc_mask dwbc401_mask = { + DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)}; + +#define mcif_wb_regs_dcn3_init(id) \ + MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id) + +static struct dcn35_mmhubbub_registers mcif_wb35_regs[1]; + +static const struct dcn35_mmhubbub_shift mcif_wb35_shift = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)}; + +static const struct dcn35_mmhubbub_mask mcif_wb35_mask = { + MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)}; + +#define dsc_regs_init(id) \ + DSC_REG_LIST_DCN401_RI(id) + +static struct dcn401_dsc_registers dsc_regs[4]; + +static const struct dcn401_dsc_shift dsc_shift = { + DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)}; + +static const struct dcn401_dsc_mask dsc_mask = { + DSC_REG_LIST_SH_MASK_DCN401(_MASK)}; + +static struct dcn42_mpc_registers mpc_regs; + +#define dcn_mpc_regs_init() \ + MPC_REG_LIST_DCN42(0), \ + MPC_REG_LIST_DCN42(1), \ + MPC_REG_LIST_DCN42(2), \ + MPC_REG_LIST_DCN42(3), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2), \ + MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3), \ + MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0), \ + MPC_RMCM_REG_LIST_DCN42(0), \ + MPC_RMCM_REG_LIST_DCN42(1) + +static const struct dcn42_mpc_shift mpc_shift = { + MPC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn42_mpc_mask mpc_mask = { + MPC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; + +#define optc_regs_init(id) \ + OPTC_COMMON_REG_LIST_DCN42_RI(id) + +static struct dcn_optc_registers optc_regs[4]; + +static const struct dcn_optc_shift optc_shift = { + OPTC_COMMON_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn_optc_mask optc_mask = { + OPTC_COMMON_MASK_SH_LIST_DCN42(_MASK)}; + +#define hubp_regs_init(id) \ + HUBP_REG_LIST_DCN42_RI(id) + +static struct dcn_hubp2_registers hubp_regs[4]; + +static const struct dcn_hubp2_shift hubp_shift = { + HUBP_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dcn_hubp2_mask hubp_mask = { + HUBP_MASK_SH_LIST_DCN42(_MASK)}; + +static struct dcn_hubbub_registers hubbub_reg; + +#define hubbub_reg_init() \ + HUBBUB_REG_LIST_DCN42(0) + +static const struct dcn_hubbub_shift hubbub_shift = { + HUBBUB_MASK_SH_LIST_DCN4_2(__SHIFT)}; + +static const struct dcn_hubbub_mask hubbub_mask = { + HUBBUB_MASK_SH_LIST_DCN4_2(_MASK)}; + +static struct dccg_registers dccg_regs; + +#define dccg_regs_init() \ + DCCG_REG_LIST_DCN42_RI() + +static const struct dccg_shift dccg_shift = { + DCCG_MASK_SH_LIST_DCN42(__SHIFT)}; + +static const struct dccg_mask dccg_mask = { + DCCG_MASK_SH_LIST_DCN42(_MASK)}; + +static struct pg_cntl_registers pg_cntl_regs; + +#define pg_cntl_dcn42_regs_init() \ + PG_CNTL_REG_LIST_DCN42() + +static const struct pg_cntl_shift pg_cntl_shift = { + PG_CNTL_MASK_SH_LIST_DCN42(__SHIFT) +}; + +static const struct pg_cntl_mask pg_cntl_mask = { + PG_CNTL_MASK_SH_LIST_DCN42(_MASK) +}; +#define SRII2(reg_name_pre, reg_name_post, id) \ + .reg_name_pre##_##reg_name_post[id] = \ + BASE(reg##reg_name_pre##id##_##reg_name_post##_BASE_IDX) + \ + reg##reg_name_pre##id##_##reg_name_post + +#define HWSEQ_DCN42_REG_LIST() \ + SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ + SR(DIO_MEM_PWR_CTRL), \ + SR(ODM_MEM_PWR_CTRL3), \ + SR(MMHUBBUB_MEM_PWR_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCFCLK_CNTL), \ + SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1), \ + SRII(PIXEL_RATE_CNTL, OTG, 2), \ + SRII(PIXEL_RATE_CNTL, OTG, 3),\ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2), \ + SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\ + SR(MICROSECOND_TIME_BASE_DIV), \ + SR(MILLISECOND_TIME_BASE_DIV), \ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(RBBMIF_TIMEOUT_DIS), \ + SR(RBBMIF_TIMEOUT_DIS_2), \ + SR(DCHUBBUB_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_CTRL), \ + SR(DPP_TOP0_DPP_CRC_VAL_R), \ + SR(DPP_TOP0_DPP_CRC_VAL_G), \ + SR(DPP_TOP0_DPP_CRC_VAL_B), \ + SR(MPC_CRC_CTRL), \ + SR(MPC_CRC_RESULT_R), \ + SR(MPC_CRC_RESULT_G), \ + SR(MPC_CRC_RESULT_B), \ + SR(MPC_CRC_RESULT_A), \ + SR(DOMAIN0_PG_CONFIG), \ + SR(DOMAIN1_PG_CONFIG), \ + SR(DOMAIN2_PG_CONFIG), \ + SR(DOMAIN3_PG_CONFIG), \ + SR(DOMAIN16_PG_CONFIG), \ + SR(DOMAIN17_PG_CONFIG), \ + SR(DOMAIN18_PG_CONFIG), \ + SR(DOMAIN19_PG_CONFIG), \ + SR(DOMAIN22_PG_CONFIG), \ + SR(DOMAIN23_PG_CONFIG), \ + SR(DOMAIN24_PG_CONFIG), \ + SR(DOMAIN25_PG_CONFIG), \ + SR(DOMAIN26_PG_CONFIG), \ + SR(DOMAIN0_PG_STATUS), \ + SR(DOMAIN1_PG_STATUS), \ + SR(DOMAIN2_PG_STATUS), \ + SR(DOMAIN3_PG_STATUS), \ + SR(DOMAIN16_PG_STATUS), \ + SR(DOMAIN17_PG_STATUS), \ + SR(DOMAIN18_PG_STATUS), \ + SR(DOMAIN19_PG_STATUS), \ + SR(DOMAIN22_PG_STATUS), \ + SR(DOMAIN23_PG_STATUS), \ + SR(DOMAIN24_PG_STATUS), \ + SR(DOMAIN25_PG_STATUS), \ + SR(DOMAIN26_PG_STATUS), \ + SR(DC_IP_REQUEST_CNTL), \ + SR(AZALIA_AUDIO_DTO), \ + SR(HPO_TOP_HW_CONTROL), \ + SR(AZALIA_CONTROLLER_CLOCK_GATING) + +static struct dce_hwseq_registers hwseq_reg; + +#define hwseq_reg_init() \ + HWSEQ_DCN42_REG_LIST() + +#define HWSEQ_DCN42_MASK_SH_LIST(mask_sh) \ + HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ + HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \ + HWS_SF(, DOMAIN26_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \ + HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DOMAIN26_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \ + HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ + HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ + HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ + HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ + HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ + HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \ + HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\ + HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \ + HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK4_GATE_DISABLE, mask_sh),\ + HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK5_GATE_DISABLE, mask_sh) + +static const struct dce_hwseq_shift hwseq_shift = { + HWSEQ_DCN42_MASK_SH_LIST(__SHIFT)}; + +static const struct dce_hwseq_mask hwseq_mask = { + HWSEQ_DCN42_MASK_SH_LIST(_MASK)}; + +#define vmid_regs_init(id) \ + DCN20_VMID_REG_LIST_RI(id) + +static struct dcn_vmid_registers vmid_regs[16]; + +static const struct dcn20_vmid_shift vmid_shifts = { + DCN20_VMID_MASK_SH_LIST(__SHIFT)}; + +static const struct dcn20_vmid_mask vmid_masks = { + DCN20_VMID_MASK_SH_LIST(_MASK)}; + +static const struct resource_caps res_cap_dcn42 = { + .num_timing_generator = 4, + .num_opp = 4, + .num_dpp = 4, + .num_video_plane = 4, + .num_audio = 5, + .num_stream_encoder = 5, + .num_dig_link_enc = 5, + .num_usb4_dpia = 6, + .num_hpo_dp_stream_encoder = 4, + .num_hpo_dp_link_encoder = 4, + .num_pll = 5, + .num_dwb = 1, + .num_ddc = 5, + .num_vmid = 16, + .num_mpc_3dlut = 2, + .num_dsc = 4, + .num_rmcm = 2, +}; + +static const struct dc_plane_cap plane_cap = { + .type = DC_PLANE_TYPE_DCN_UNIVERSAL, + .per_pixel_alpha = true, + + .pixel_format_support = { + .argb8888 = true, + .nv12 = true, + .fp16 = true, + .p010 = true, + .ayuv = false, + }, + + .max_upscale_factor = {.argb8888 = 16000, .nv12 = 16000, .fp16 = 16000}, + + // 6:1 downscaling ratio: 1000/6 = 166.666 + .max_downscale_factor = {.argb8888 = 167, .nv12 = 167, .fp16 = 167}, + + .min_width = 64, + .min_height = 64}; + +static const struct dc_debug_options debug_defaults_drv = { + .disable_dmcu = true, + .force_abm_enable = false, + .clock_trace = true, + .disable_pplib_clock_request = false, + .disable_dpp_power_gate = true, + .disable_hubp_power_gate = true, + .disable_optc_power_gate = true, + .pipe_split_policy = MPC_SPLIT_AVOID, + .force_single_disp_pipe_split = false, + .disable_dcc = DCC_ENABLE, + .vsr_support = true, + .performance_trace = false, + .max_downscale_src_width = 4096, /*up to 4K for APU*/ + .disable_pplib_wm_range = false, + .scl_reset_length10 = true, + .sanity_checks = false, + .underflow_assert_delay_us = 0xFFFFFFFF, + .dwb_fi_phase = -1, // -1 = disable, + .dmub_command_table = true, + .pstate_enabled = true, + .enable_mem_low_power = { + .bits = { + .vga = false, + .i2c = true, + .dscl = true, + .cm = true, + .mpc = true, + .optc = true, + .vpg = true, + }}, + .root_clock_optimization = { + .bits = { + .dpp = true, + .dsc = true,/*dscclk and dsc pg*/ + .hdmistream = false, + .hdmichar = true, + .dpstream = true, + .symclk32_se = true, + .symclk32_le = true, + .symclk_fe = true, + .physymclk = false, + .dpiasymclk = true, + } + }, + .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT, + .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/ + .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */ + .support_eDP1_5 = true, + .use_max_lb = true, + .force_disable_subvp = false, + .exit_idle_opt_for_cursor_updates = true, + .using_dml2 = true, + .using_dml21 = true, + .enable_single_display_2to1_odm_policy = true, + + // must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions + .enable_double_buffered_dsc_pg_support = true, + .enable_dp_dig_pixel_rate_div_policy = 1, + .allow_sw_cursor_fallback = false, + .psp_disabled_wa = true, + .alloc_extra_way_for_cursor = true, + .min_prefetch_in_strobe_ns = 60000, // 60us + .disable_unbounded_requesting = false, + .dcc_meta_propagation_delay_us = 10, + .disable_timeout = true, + .min_disp_clk_khz = 50000, + .static_screen_wait_frames = 2, + .disable_z10 = false, + .ignore_pg = true, + .disable_stutter_for_wm_program = true, + .min_deep_sleep_dcfclk_khz = 8000, +}; + +static const struct dc_check_config config_defaults = { + .enable_legacy_fast_update = false, +}; + +static struct dce_aux *dcn42_aux_engine_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct aux_engine_dce110 *aux_engine = + kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); + + if (!aux_engine) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT aux_engine_regs + aux_engine_regs_init(0), + aux_engine_regs_init(1), + aux_engine_regs_init(2), + aux_engine_regs_init(3), + aux_engine_regs_init(4); + + dce110_aux_engine_construct(aux_engine, ctx, inst, + SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, + &aux_engine_regs[inst], + &aux_mask, + &aux_shift, + ctx->dc->caps.extended_aux_timeout_support); + + return &aux_engine->base; +} + +#define i2c_inst_regs_init(id) \ + I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) + +static struct dce_i2c_registers i2c_hw_regs[5]; + +static const struct dce_i2c_shift i2c_shifts = { + I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT) +}; +static const struct dce_i2c_mask i2c_masks = { + I2C_COMMON_MASK_SH_LIST_DCN35(_MASK) +}; + +/* ========================================================== */ + +/* + * DPIA index | Preferred Encoder | Host Router + * 0 | C | 0 + * 1 | First Available | 0 + * 2 | D | 1 + * 3 | First Available | 1 + * 4 | E | 2 + * 5 | First Available | 2 + */ +/* ========================================================== */ +static const enum engine_id dpia_to_preferred_enc_id_table[] = { + ENGINE_ID_DIGC, + ENGINE_ID_DIGC, + ENGINE_ID_DIGD, + ENGINE_ID_DIGD, + ENGINE_ID_DIGE, + ENGINE_ID_DIGE +}; + +static enum engine_id dcn42_get_preferred_eng_id_dpia(unsigned int dpia_index) +{ + return dpia_to_preferred_enc_id_table[dpia_index]; +} + +static struct dce_i2c_hw *dcn42_i2c_hw_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dce_i2c_hw *dce_i2c_hw = + kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); + + if (!dce_i2c_hw) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT i2c_hw_regs + i2c_inst_regs_init(1), + i2c_inst_regs_init(2), + i2c_inst_regs_init(3), + i2c_inst_regs_init(4), + i2c_inst_regs_init(5); + dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, + &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); + + return dce_i2c_hw; +} + +static struct clock_source *dcn42_clock_source_create( + struct dc_context *ctx, + struct dc_bios *bios, + enum clock_source_id id, + const struct dce110_clk_src_regs *regs, + bool dp_clk_src) +{ + struct dce110_clk_src *clk_src = + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); + + if (!clk_src) + return NULL; + + if (dcn401_clk_src_construct(clk_src, ctx, bios, id, + regs, &cs_shift, &cs_mask)) { + clk_src->base.dp_clk_src = dp_clk_src; + return &clk_src->base; + } + + kfree(clk_src); + BREAK_TO_DEBUGGER(); + return NULL; +} + +static struct hubbub *dcn42_hubbub_create(struct dc_context *ctx) +{ + int i; + + struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), + GFP_KERNEL); + + if (!hubbub3) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT hubbub_reg + hubbub_reg_init(); + +#undef REG_STRUCT +#define REG_STRUCT vmid_regs + vmid_regs_init(0), + vmid_regs_init(1), + vmid_regs_init(2), + vmid_regs_init(3), + vmid_regs_init(4), + vmid_regs_init(5), + vmid_regs_init(6), + vmid_regs_init(7), + vmid_regs_init(8), + vmid_regs_init(9), + vmid_regs_init(10), + vmid_regs_init(11), + vmid_regs_init(12), + vmid_regs_init(13), + vmid_regs_init(14), + vmid_regs_init(15); + + hubbub42_construct(hubbub3, ctx, + &hubbub_reg, + &hubbub_shift, + &hubbub_mask, + DCN42_DEFAULT_DET_SIZE, + 8, + DCN42_CRB_SIZE_KB); + for (i = 0; i < res_cap_dcn42.num_vmid; i++) { + struct dcn20_vmid *vmid = &hubbub3->vmid[i]; + + vmid->ctx = ctx; + + vmid->regs = &vmid_regs[i]; + vmid->shifts = &vmid_shifts; + vmid->masks = &vmid_masks; + } + + return &hubbub3->base; +} + +static struct hubp *dcn42_hubp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn20_hubp *hubp2 = + kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL); + + if (!hubp2) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT hubp_regs + hubp_regs_init(0), + hubp_regs_init(1), + hubp_regs_init(2), + hubp_regs_init(3); + + if (hubp42_construct(hubp2, ctx, inst, + &hubp_regs[inst], &hubp_shift, &hubp_mask)) + return &hubp2->base; + + BREAK_TO_DEBUGGER(); + kfree(hubp2); + return NULL; +} +static const struct dc_panel_config dcn42_panel_config_defaults = { + .psr = { + .disable_psr = false, + .disallow_psrsu = false, + .disallow_replay = false, + }, + .ilr = { + .optimize_edp_link_rate = true, + }, +}; + +static void dcn42_dpp_destroy(struct dpp **dpp) +{ + kfree(TO_DCN42_DPP(*dpp)); + *dpp = NULL; +} + +static struct dpp *dcn42_dpp_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn42_dpp *dpp42 = + kzalloc(sizeof(struct dcn42_dpp), GFP_KERNEL); + + if (!dpp42) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT dpp_regs + dpp_regs_init(0), + dpp_regs_init(1), + dpp_regs_init(2), + dpp_regs_init(3); + + if (dpp42_construct(dpp42, ctx, inst, + &dpp_regs[inst], &tf_shift, &tf_mask)) + return &dpp42->base; + + BREAK_TO_DEBUGGER(); + kfree(dpp42); + return NULL; +} + +static struct mpc *dcn42_mpc_create( + struct dc_context *ctx, + int num_mpcc, + int num_rmu) +{ + struct dcn42_mpc *mpc401 = kzalloc(sizeof(struct dcn42_mpc), + GFP_KERNEL); + + if (!mpc401) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT mpc_regs + dcn_mpc_regs_init(); + + dcn42_mpc_construct(mpc401, ctx, + &mpc_regs, + &mpc_shift, + &mpc_mask, + num_mpcc, + num_rmu); + + return &mpc401->base; +} + +static struct output_pixel_processor *dcn42_opp_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn20_opp *opp4 = + kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL); + + if (!opp4) { + BREAK_TO_DEBUGGER(); + return NULL; + } + +#undef REG_STRUCT +#define REG_STRUCT opp_regs + opp_regs_init(0), + opp_regs_init(1), + opp_regs_init(2), + opp_regs_init(3); + dcn20_opp_construct(opp4, ctx, inst, + &opp_regs[inst], &opp_shift, &opp_mask); + return &opp4->base; +} + +static struct timing_generator *dcn42_timing_generator_create( + struct dc_context *ctx, + uint32_t instance) +{ + struct optc *tgn10 = + kzalloc(sizeof(struct optc), GFP_KERNEL); + + if (!tgn10) + return NULL; +#undef REG_STRUCT +#define REG_STRUCT optc_regs + optc_regs_init(0), + optc_regs_init(1), + optc_regs_init(2), + optc_regs_init(3); + tgn10->base.inst = instance; + tgn10->base.ctx = ctx; + + tgn10->tg_regs = &optc_regs[instance]; + tgn10->tg_shift = &optc_shift; + tgn10->tg_mask = &optc_mask; + + dcn42_timing_generator_init(tgn10); + + return &tgn10->base; +} + +static const struct encoder_feature_support link_enc_feature = { + .max_hdmi_deep_color = COLOR_DEPTH_121212, + .max_hdmi_pixel_clock = 600000, + .hdmi_ycbcr420_supported = true, + .dp_ycbcr420_supported = true, + .fec_supported = true, + .flags.bits.IS_HBR2_CAPABLE = true, + .flags.bits.IS_HBR3_CAPABLE = true, + .flags.bits.IS_TPS3_CAPABLE = true, + .flags.bits.IS_TPS4_CAPABLE = true}; + +static struct link_encoder *dcn42_link_encoder_create( + struct dc_context *ctx, + const struct encoder_init_data *enc_init_data) +{ + struct dcn20_link_encoder *enc20 = + kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + + if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT link_enc_aux_regs + aux_regs_init(0), + aux_regs_init(1), + aux_regs_init(2), + aux_regs_init(3), + aux_regs_init(4); +#undef REG_STRUCT +#define REG_STRUCT link_enc_hpd_regs + hpd_regs_init(0), + hpd_regs_init(1), + hpd_regs_init(2), + hpd_regs_init(3), + hpd_regs_init(4); +#undef REG_STRUCT +#define REG_STRUCT link_enc_regs + link_regs_init(0, A), + link_regs_init(1, B), + link_regs_init(2, C), + link_regs_init(3, D), + link_regs_init(4, E); + + dcn42_link_encoder_construct(enc20, + enc_init_data, + &link_enc_feature, + &link_enc_regs[enc_init_data->transmitter], + &link_enc_aux_regs[enc_init_data->channel - 1], + &link_enc_hpd_regs[enc_init_data->hpd_source], + &le_shift, + &le_mask); + return &enc20->enc10.base; +} + +static void read_dce_straps( + struct dc_context *ctx, + struct resource_straps *straps) +{ + generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), + FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); +} + +static struct audio *dcn42_create_audio( + struct dc_context *ctx, unsigned int inst) +{ + +#undef REG_STRUCT +#define REG_STRUCT audio_regs + audio_regs_init(0), + audio_regs_init(1), + audio_regs_init(2), + audio_regs_init(3), + audio_regs_init(4); + + return dce_audio_create(ctx, inst, + &audio_regs[inst], &audio_shift, &audio_mask); +} + +static struct vpg *dcn42_vpg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL); + + if (!vpg4) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT vpg_regs + vpg_regs_init(0), + vpg_regs_init(1), + vpg_regs_init(2), + vpg_regs_init(3), + vpg_regs_init(4), + vpg_regs_init(5), + vpg_regs_init(6), + vpg_regs_init(7), + vpg_regs_init(8), + vpg_regs_init(9); + vpg31_construct(vpg4, ctx, inst, + &vpg_regs[inst], + &vpg_shift, + &vpg_mask); + + return &vpg4->base; +} + +static struct apg *dcn42_apg_create( + struct dc_context *ctx, + uint32_t inst) +{ + struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL); + + if (!apg31) + return NULL; + +#undef REG_STRUCT +#define REG_STRUCT apg_regs + apg_regs_init(0), + apg_regs_init(1), + apg_regs_init(2), + apg_regs_init(3), + apg_regs_init(4), + apg_regs_init(5), + apg_regs_init(6), + apg_regs_init(7), + apg_regs_init(8), + apg_regs_init(9); + + apg31_construct(apg31, ctx, inst, + &apg_regs[inst], + &apg_shift, + &apg_mask); + + return &apg31->base; +} + +static struct stream_encoder *dcn42_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn10_stream_encoder *enc1; + struct vpg *vpg; + struct apg *apg; + + uint32_t vpg_inst; + uint32_t apg_inst; + + /* Mapping of VPG, DME register blocks to DIO block instance */ + if (eng_id <= ENGINE_ID_DIGE) { + vpg_inst = eng_id; + apg_inst = eng_id; + } else + return NULL; + + enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); + vpg = dcn42_vpg_create(ctx, vpg_inst); + apg = dcn42_apg_create(ctx, apg_inst); + + if (!enc1 || !vpg || !apg) { + kfree(enc1); + kfree(vpg); + kfree(apg); + return NULL; + } +#undef REG_STRUCT +#define REG_STRUCT stream_enc_regs + stream_enc_regs_init(0), + stream_enc_regs_init(1), + stream_enc_regs_init(2), + stream_enc_regs_init(3), + stream_enc_regs_init(4); + + dcn42_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, + eng_id, vpg, apg, + &stream_enc_regs[eng_id], + &se_shift, &se_mask); + return &enc1->base; +} + +static struct hpo_dp_stream_encoder *dcn42_hpo_dp_stream_encoder_create( + enum engine_id eng_id, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31; + struct vpg *vpg; + struct apg *apg; + uint32_t hpo_dp_inst; + uint32_t vpg_inst; + uint32_t apg_inst; + + ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); + hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; + + /* Mapping of VPG register blocks to HPO DP block instance: + * VPG[5] -> HPO_DP[0] + * VPG[6] -> HPO_DP[1] + * VPG[7] -> HPO_DP[2] + * VPG[8] -> HPO_DP[3] + */ + vpg_inst = hpo_dp_inst + 5; + + /* Mapping of APG register blocks to HPO DP block instance: + * APG[6] -> HPO_DP[0] + * APG[7] -> HPO_DP[1] + * APG[8] -> HPO_DP[2] + * APG[9] -> HPO_DP[3] + */ + apg_inst = hpo_dp_inst + 5; + + /* allocate HPO stream encoder and create VPG sub-block */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL); + vpg = dcn42_vpg_create(ctx, vpg_inst); + apg = dcn42_apg_create(ctx, apg_inst); + + if (!hpo_dp_enc31 || !vpg || !apg) { + kfree(hpo_dp_enc31); + kfree(vpg); + kfree(apg); + return NULL; + } + +#undef REG_STRUCT +#define REG_STRUCT hpo_dp_stream_enc_regs + hpo_dp_stream_encoder_reg_init(0), + hpo_dp_stream_encoder_reg_init(1), + hpo_dp_stream_encoder_reg_init(2), + hpo_dp_stream_encoder_reg_init(3); + + dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios, + hpo_dp_inst, eng_id, vpg, apg, + &hpo_dp_stream_enc_regs[hpo_dp_inst], + &hpo_dp_se_shift, &hpo_dp_se_mask); + + return &hpo_dp_enc31->base; +} + +static struct hpo_dp_link_encoder *dcn42_hpo_dp_link_encoder_create( + uint8_t inst, + struct dc_context *ctx) +{ + struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31; + + /* allocate HPO link encoder */ + hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL); + if (!hpo_dp_enc31) + return NULL; /* out of memory */ + +#undef REG_STRUCT +#define REG_STRUCT hpo_dp_link_enc_regs + hpo_dp_link_encoder_reg_init(0), + hpo_dp_link_encoder_reg_init(1), + hpo_dp_link_encoder_reg_init(2), + hpo_dp_link_encoder_reg_init(3); + + hpo_dp_link_encoder42_construct(hpo_dp_enc31, ctx, inst, + &hpo_dp_link_enc_regs[inst], + &hpo_dp_le_shift, &hpo_dp_le_mask); + + return &hpo_dp_enc31->base; +} + +static struct dce_hwseq *dcn42_hwseq_create( + struct dc_context *ctx) +{ + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); + +#undef REG_STRUCT +#define REG_STRUCT hwseq_reg + hwseq_reg_init(); + + if (hws) { + hws->ctx = ctx; + hws->regs = &hwseq_reg; + hws->shifts = &hwseq_shift; + hws->masks = &hwseq_mask; + } + + return hws; +} + +static const struct resource_create_funcs res_create_funcs = { + .read_dce_straps = read_dce_straps, + .create_audio = dcn42_create_audio, + .create_stream_encoder = dcn42_stream_encoder_create, + .create_hpo_dp_stream_encoder = dcn42_hpo_dp_stream_encoder_create, + .create_hpo_dp_link_encoder = dcn42_hpo_dp_link_encoder_create, + .create_hwseq = dcn42_hwseq_create, +}; + +static void dcn42_dsc_destroy(struct display_stream_compressor **dsc) +{ + kfree(container_of(*dsc, struct dcn401_dsc, base)); + *dsc = NULL; +} + +static void dcn42_resource_destruct(struct dcn42_resource_pool *pool) +{ + unsigned int i; + + for (i = 0; i < pool->base.stream_enc_count; i++) { + if (pool->base.stream_enc[i] != NULL) { + if (pool->base.stream_enc[i]->vpg != NULL) { + kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); + pool->base.stream_enc[i]->vpg = NULL; + } + if (pool->base.stream_enc[i]->apg != NULL) { + kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); + pool->base.stream_enc[i]->apg = NULL; + } + kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); + pool->base.stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { + if (pool->base.hpo_dp_stream_enc[i] != NULL) { + if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { + kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); + pool->base.hpo_dp_stream_enc[i]->vpg = NULL; + } + if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { + kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); + pool->base.hpo_dp_stream_enc[i]->apg = NULL; + } + kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); + pool->base.hpo_dp_stream_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { + if (pool->base.hpo_dp_link_enc[i] != NULL) { + kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); + pool->base.hpo_dp_link_enc[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + if (pool->base.dscs[i] != NULL) + dcn42_dsc_destroy(&pool->base.dscs[i]); + } + + if (pool->base.mpc != NULL) { + kfree(TO_DCN20_MPC(pool->base.mpc)); + pool->base.mpc = NULL; + } + if (pool->base.hubbub != NULL) { + kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); + pool->base.hubbub = NULL; + } + for (i = 0; i < pool->base.pipe_count; i++) { + if (pool->base.dpps[i] != NULL) + dcn42_dpp_destroy(&pool->base.dpps[i]); + + if (pool->base.ipps[i] != NULL) + pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); + + if (pool->base.hubps[i] != NULL) { + kfree(TO_DCN20_HUBP(pool->base.hubps[i])); + pool->base.hubps[i] = NULL; + } + + if (pool->base.irqs != NULL) + dal_irq_service_destroy(&pool->base.irqs); + } + + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + if (pool->base.engines[i] != NULL) + dce110_engine_destroy(&pool->base.engines[i]); + if (pool->base.hw_i2cs[i] != NULL) { + kfree(pool->base.hw_i2cs[i]); + pool->base.hw_i2cs[i] = NULL; + } + if (pool->base.sw_i2cs[i] != NULL) { + kfree(pool->base.sw_i2cs[i]); + pool->base.sw_i2cs[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_opp; i++) { + if (pool->base.opps[i] != NULL) + pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.timing_generators[i] != NULL) { + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + pool->base.timing_generators[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_dwb; i++) { + if (pool->base.dwbc[i] != NULL) { + kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); + pool->base.dwbc[i] = NULL; + } + if (pool->base.mcif_wb[i] != NULL) { + kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i])); + pool->base.mcif_wb[i] = NULL; + } + } + + for (i = 0; i < pool->base.audio_count; i++) { + if (pool->base.audios[i]) + dce_aud_destroy(&pool->base.audios[i]); + } + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] != NULL) { + dcn20_clock_source_destroy(&pool->base.clock_sources[i]); + pool->base.clock_sources[i] = NULL; + } + } + + for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { + if (pool->base.mpc_lut[i] != NULL) { + dc_3dlut_func_release(pool->base.mpc_lut[i]); + pool->base.mpc_lut[i] = NULL; + } + if (pool->base.mpc_shaper[i] != NULL) { + dc_transfer_func_release(pool->base.mpc_shaper[i]); + pool->base.mpc_shaper[i] = NULL; + } + } + + if (pool->base.dp_clock_source != NULL) { + dcn20_clock_source_destroy(&pool->base.dp_clock_source); + pool->base.dp_clock_source = NULL; + } + + for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { + if (pool->base.multiple_abms[i] != NULL) + dce_abm_destroy(&pool->base.multiple_abms[i]); + } + + if (pool->base.psr != NULL) + dmub_psr_destroy(&pool->base.psr); + + if (pool->base.pg_cntl != NULL) + dcn_pg_cntl_destroy(&pool->base.pg_cntl); + if (pool->base.dccg != NULL) + dcn_dccg_destroy(&pool->base.dccg); + + if (pool->base.oem_device != NULL) { + struct dc *dc = pool->base.oem_device->ctx->dc; + + dc->link_srv->destroy_ddc_service(&pool->base.oem_device); + } +} + +static void dcn42_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) +{ + const struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; + struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; + struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; + + pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; + + if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0) + pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz; + + if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment) + link_enc = link_enc_cfg_get_link_enc(link); + if (link_enc) + pixel_clk_params->encoder_object_id = link_enc->id; + + pixel_clk_params->signal_type = pipe_ctx->stream->signal; + pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; + /* TODO: un-hardcode*/ + + /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ + + pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * + LINK_RATE_REF_FREQ_IN_KHZ; + pixel_clk_params->flags.ENABLE_SS = 0; + pixel_clk_params->color_depth = + stream->timing.display_color_depth; + pixel_clk_params->flags.DISPLAY_BLANKED = 1; + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; + + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + pixel_clk_params->color_depth = COLOR_DEPTH_888; + + if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) + pixel_clk_params->requested_pix_clk_100hz *= 2; + if (dc_is_tmds_signal(stream->signal) && + stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + pixel_clk_params->requested_pix_clk_100hz /= 2; + + pipe_ctx->clock_source->funcs->get_pix_clk_dividers( + pipe_ctx->clock_source, + &pipe_ctx->stream_res.pix_clk_params, + &pipe_ctx->pll_settings); + + pixel_clk_params->dio_se_pix_per_cycle = 1; + if (dc_is_tmds_signal(stream->signal) && + stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + pixel_clk_params->dio_se_pix_per_cycle = 2; + } else if (dc_is_dp_signal(stream->signal)) { + /* round up to nearest power of 2, or max at 8 pixels per cycle */ + if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + pixel_clk_params->dio_se_pix_per_cycle = 8; + } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + pixel_clk_params->dio_se_pix_per_cycle = 4; + } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) { + pixel_clk_params->dio_se_pix_per_cycle = 2; + } else { + pixel_clk_params->dio_se_pix_per_cycle = 1; + } + } +} + +static bool dcn42_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t dwb_count = pool->res_cap->num_dwb; + + for (i = 0; i < dwb_count; i++) { + struct dcn30_dwbc *dwbc42 = kzalloc(sizeof(struct dcn30_dwbc), + GFP_KERNEL); + + if (!dwbc42) { + dm_error("DC: failed to create dwbc42!\n"); + return false; + } + +#undef REG_STRUCT +#define REG_STRUCT dwbc401_regs + dwbc_regs_dcn401_init(0); + + dcn30_dwbc_construct(dwbc42, ctx, + &dwbc401_regs[i], + &dwbc401_shift, + &dwbc401_mask, + i); + + pool->dwbc[i] = &dwbc42->base; + } + return true; +} + +static void dcn42_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30, + struct dc_context *ctx) +{ + dcn42_mmhubbub_set_fgcg( + mcif_wb30, + ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub); +} + +static bool dcn42_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) +{ + int i; + uint32_t pipe_count = pool->res_cap->num_dwb; + + for (i = 0; i < pipe_count; i++) { + struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), + GFP_KERNEL); + + if (!mcif_wb30) { + dm_error("DC: failed to create mcif_wb30!\n"); + return false; + } + +#undef REG_STRUCT +#define REG_STRUCT mcif_wb35_regs + mcif_wb_regs_dcn3_init(0); + + dcn35_mmhubbub_construct(mcif_wb30, ctx, + &mcif_wb35_regs[i], + &mcif_wb35_shift, + &mcif_wb35_mask, + i); + + dcn42_mmhubbub_init(mcif_wb30, ctx); + + pool->mcif_wb[i] = &mcif_wb30->base; + } + return true; +} + +static struct display_stream_compressor *dcn42_dsc_create( + struct dc_context *ctx, uint32_t inst) +{ + struct dcn401_dsc *dsc = + kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL); + + if (!dsc) { + BREAK_TO_DEBUGGER(); + return NULL; + } + +#undef REG_STRUCT +#define REG_STRUCT dsc_regs + dsc_regs_init(0), + dsc_regs_init(1), + dsc_regs_init(2), + dsc_regs_init(3); + + dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); + dsc401_set_fgcg(dsc, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc); + + dsc->max_image_width = 5760; + + return &dsc->base; +} + +static void dcn42_destroy_resource_pool(struct resource_pool **pool) +{ + struct dcn42_resource_pool *dcn42_pool = TO_DCN42_RES_POOL(*pool); + + dcn42_resource_destruct(dcn42_pool); + kfree(dcn42_pool); + *pool = NULL; +} + +static struct dc_cap_funcs cap_funcs = { + .get_dcc_compression_cap = dcn20_get_dcc_compression_cap}; + +static void dcn42_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) +{ + DC_FP_START(); + if (dc->current_state && dc->current_state->bw_ctx.dml2) + dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); + DC_FP_END(); +} + +enum dc_status dcn42_validate_bandwidth(struct dc *dc, + struct dc_state *context, + enum dc_validate_mode validate_mode) +{ + bool out = false; + + out = dml2_validate(dc, context, context->bw_ctx.dml2, + validate_mode); + DC_FP_START(); + if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING) { + /*not required for mode enumeration*/ + dcn42_decide_zstate_support(dc, context); + } + DC_FP_END(); + return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE; +} +void dcn42_prepare_mcache_programming(struct dc *dc, + struct dc_state *context) +{ + if (dc->debug.using_dml21) + dml2_prepare_mcache_programming(dc, context, + context->power_source == DC_POWER_SOURCE_DC ? + context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2); +} +/* Create a minimal link encoder object not associated with a particular + * physical connector. + * resource_funcs.link_enc_create_minimal + */ +static struct link_encoder *dcn42_link_enc_create_minimal( + struct dc_context *ctx, enum engine_id eng_id) +{ + struct dcn20_link_encoder *enc20; + + if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) + return NULL; + + enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); + if (!enc20) + return NULL; + + dcn31_link_encoder_construct_minimal( + enc20, + ctx, + &link_enc_feature, + &link_enc_regs[eng_id - ENGINE_ID_DIGA], + eng_id); + + return &enc20->enc10.base; +} +static void dcn42_get_panel_config_defaults(struct dc_panel_config *panel_config) +{ + *panel_config = dcn42_panel_config_defaults; +} +static unsigned int dcn42_get_max_hw_cursor_size(const struct dc *dc, + struct dc_state *state, + const struct dc_stream_state *stream) +{ + return dc->caps.max_cursor_size; +} +static struct resource_funcs dcn42_res_pool_funcs = { + .destroy = dcn42_destroy_resource_pool, + .link_enc_create = dcn42_link_encoder_create, + .link_enc_create_minimal = dcn42_link_enc_create_minimal, + .link_encs_assign = link_enc_cfg_link_encs_assign, + .link_enc_unassign = link_enc_cfg_link_enc_unassign, + .panel_cntl_create = dcn32_panel_cntl_create, + .validate_bandwidth = dcn42_validate_bandwidth, + .calculate_wm_and_dlg = NULL, + .populate_dml_pipes = NULL, + .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, + .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, + .release_pipe = dcn20_release_pipe, + .add_stream_to_ctx = dcn30_add_stream_to_ctx, + .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, + .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, + .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, + .set_mcif_arb_params = dcn30_set_mcif_arb_params, + .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, + .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, + .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, + .update_bw_bounding_box = dcn42_update_bw_bounding_box, + .patch_unknown_plane_state = dcn401_patch_unknown_plane_state, + .get_panel_config_defaults = dcn42_get_panel_config_defaults, + .get_preferred_eng_id_dpia = dcn42_get_preferred_eng_id_dpia, + .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, + .add_phantom_pipes = dcn32_add_phantom_pipes, + .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, + .prepare_mcache_programming = dcn42_prepare_mcache_programming, + .build_pipe_pix_clk_params = dcn42_build_pipe_pix_clk_params, + .get_power_profile = dcn401_get_power_profile, + .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe, + .get_max_hw_cursor_size = dcn42_get_max_hw_cursor_size, + .get_default_tiling_info = dcn10_get_default_tiling_info +}; + +static uint32_t read_pipe_fuses(struct dc_context *ctx) +{ + uint32_t value = REG_READ(CC_DC_PIPE_DIS); + + if (value == 0 && ctx->dce_environment == DCE_ENV_DIAG) + value = 0xF; + /* DCN401 support max 4 pipes */ + value = value & 0xf; + return value; +} + +static bool dcn42_resource_construct( + uint8_t num_virtual_links, + struct dc *dc, + struct dcn42_resource_pool *pool) +{ + int i, j; + struct dc_context *ctx = dc->ctx; + struct irq_service_init_data init_data; + uint32_t pipe_fuses; + uint32_t num_pipes; + +#undef REG_STRUCT +#define REG_STRUCT bios_regs + bios_regs_init(); + +#undef REG_STRUCT +#define REG_STRUCT clk_src_regs + clk_src_regs_init(0, A), + clk_src_regs_init(1, B), + clk_src_regs_init(2, C), + clk_src_regs_init(3, D), + clk_src_regs_init(4, E); + +#undef REG_STRUCT +#define REG_STRUCT abm_regs + abm_regs_init(0), + abm_regs_init(1), + abm_regs_init(2), + abm_regs_init(3); +#undef REG_STRUCT +#define REG_STRUCT dccg_regs + dccg_regs_init(); + + ctx->dc_bios->regs = &bios_regs; + + pool->base.res_cap = &res_cap_dcn42; + + /* max number of pipes for ASIC before checking for pipe fuses */ + num_pipes = pool->base.res_cap->num_dpp; + pipe_fuses = read_pipe_fuses(ctx); + + for (i = 0; i < pool->base.res_cap->num_dpp; i++) + if (pipe_fuses & 1 << i) + num_pipes--; + + if (pipe_fuses & 1) + ASSERT(0); // Unexpected - Pipe 0 should always be fully functional! + + if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) + ASSERT(0); // Entire DCN is harvested! + + pool->base.funcs = &dcn42_res_pool_funcs; + + /************************************************* + * Resource + asic cap harcoding * + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; + pool->base.pipe_count = num_pipes; + pool->base.mpcc_count = num_pipes; + dc->caps.ips_v2_support = true; + dc->caps.max_downscale_ratio = 600; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/ + /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ + dc->caps.max_cursor_size = 64; + dc->caps.max_buffered_cursor_size = 64; + dc->caps.cursor_not_scaled = true; + dc->caps.min_horizontal_blanking_period = 80; + dc->caps.dmdata_alloc_size = 2048; + dc->caps.mall_size_per_mem_channel = 4; + /* total size = mall per channel * num channels * 1024 * 1024 */ + dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * + dc->ctx->dc_bios->vram_info.num_chans * 1048576; + dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; + dc->caps.cache_line_size = 64; + dc->caps.cache_num_ways = 16; + + /* Calculate the available MALL space */ + dc->caps.max_cab_allocation_bytes = + dcn32_calc_num_avail_chans_for_mall(dc, dc->ctx->dc_bios->vram_info.num_chans) * + dc->caps.mall_size_per_mem_channel * 1024 * 1024; + dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; + + dc->caps.subvp_fw_processing_delay_us = 15; + dc->caps.subvp_drr_max_vblank_margin_us = 40; + dc->caps.subvp_prefetch_end_to_mall_start_us = 15; + dc->caps.subvp_swath_height_margin_lines = 16; + dc->caps.subvp_pstate_allow_width_us = 20; + dc->caps.subvp_vertical_int_margin_us = 30; + dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin + + dc->caps.max_slave_planes = 2; + dc->caps.max_slave_yuv_planes = 2; + dc->caps.max_slave_rgb_planes = 2; + dc->caps.post_blend_color_processing = true; + dc->caps.force_dp_tps4_for_cp2520 = true; + if (dc->config.forceHBR2CP2520) + dc->caps.force_dp_tps4_for_cp2520 = false; + dc->caps.dp_hdmi21_pcon_support = true; + dc->caps.dp_hpo = true; + dc->caps.edp_dsc_support = true; + dc->caps.extended_aux_timeout_support = true; + dc->caps.dmcub_support = true; + dc->caps.is_apu = true; + dc->caps.seamless_odm = true; + dc->caps.zstate_support = true; + dc->caps.ips_support = true; + dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; + + dc->caps.seamless_odm = true; + dc->caps.zstate_support = true; + dc->caps.ips_support = true; + dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; + + /* Color pipeline capabilities */ + dc->caps.color.dpp.dcn_arch = 1; + dc->caps.color.dpp.input_lut_shared = 0; + dc->caps.color.dpp.icsc = 1; + dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr + dc->caps.color.dpp.dgam_rom_caps.srgb = 1; + dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; + dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; + dc->caps.color.dpp.dgam_rom_caps.pq = 1; + dc->caps.color.dpp.dgam_rom_caps.hlg = 1; + dc->caps.color.dpp.post_csc = 1; + dc->caps.color.dpp.gamma_corr = 1; + dc->caps.color.dpp.dgam_rom_for_yuv = 0; + + dc->caps.color.dpp.hw_3d_lut = 0; + dc->caps.color.dpp.ogam_ram = 0; + // no OGAM ROM on DCN2 and later ASICs + dc->caps.color.dpp.ogam_rom_caps.srgb = 0; + dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; + dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.dpp.ogam_rom_caps.pq = 0; + dc->caps.color.dpp.ogam_rom_caps.hlg = 0; + dc->caps.color.dpp.ocsc = 0; + + dc->caps.color.mpc.gamut_remap = 1; + //configurable to be before or after BLND in MPCC + dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; + dc->caps.color.mpc.num_rmcm_3dluts = 2; + dc->caps.color.mpc.ogam_ram = 1; + dc->caps.color.mpc.ogam_rom_caps.srgb = 0; + dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; + dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; + dc->caps.color.mpc.ogam_rom_caps.pq = 0; + dc->caps.color.mpc.ogam_rom_caps.hlg = 0; + dc->caps.color.mpc.ocsc = 1; + dc->caps.color.mpc.preblend = true; + dc->caps.color.mpc.mcm_3d_lut_caps.dma_3d_lut = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_9 = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.linear_1d = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; + dc->caps.color.mpc.mcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.dma_3d_lut = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33 = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.linear_1d = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_bgr = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_layout_support.swizzle_3d_rgb = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12msb = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.unorm_12lsb = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_format_support.float_fp1_5_10 = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_rgba = 1; + dc->caps.color.mpc.rmcm_3d_lut_caps.mem_pixel_order_support.order_bgra = 1; + + dc->caps.num_of_host_routers = 3; + dc->caps.num_of_dpias_per_host_router = 2; + + /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order + * to provide some margin. + * It's expected for furture ASIC to have equal or higher value, in order to + * have determinstic power improvement from generate to genration. + * (i.e., we should not expect new ASIC generation with lower vmin rate) + */ + dc->caps.max_disp_clock_khz_at_vmin = 650000; + dc->config.use_spl = true; + dc->config.prefer_easf = true; + + dc->config.dcn_sharpness_range.sdr_rgb_min = 0; + dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; + dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; + dc->config.dcn_sharpness_range.sdr_yuv_min = 0; + dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; + dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; + dc->config.dcn_sharpness_range.hdr_rgb_min = 0; + dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; + dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; + + dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; + dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; + dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; + dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; + dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; + dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; + dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; + dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; + dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; + + dc->config.use_pipe_ctx_sync_logic = true; + dc->config.dc_mode_clk_limit_support = false; + dc->config.enable_windowed_mpo_odm = true; + /* Use psp mailbox to enable assr */ + dc->config.use_assr_psp_message = true; + /* dcn42 and afterward always support external panel replay */ + dc->config.frame_update_cmd_version2 = true; + + /* read VBIOS LTTPR caps */ + { + if (ctx->dc_bios->funcs->get_lttpr_caps) { + enum bp_result bp_query_result; + uint8_t is_vbios_lttpr_enable = 0; + + bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); + dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; + } + + dc->caps.vbios_lttpr_aware = true; + } + dc->check_config = config_defaults; + + if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) + dc->debug = debug_defaults_drv; + + /*HW default is to have all the FGCG enabled, SW no need to program them*/ + dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF; + // Init the vm_helper + if (dc->vm_helper) + vm_helper_init(dc->vm_helper, 16); + + /************************************************* + * Create resources * + *************************************************/ + + /* Clock Sources for Pixel Clock*/ + pool->base.clock_sources[DCN401_CLK_SRC_PLL0] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL0, + &clk_src_regs[0], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL1] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL1, + &clk_src_regs[1], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL2] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL2, + &clk_src_regs[2], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL3] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL3, + &clk_src_regs[3], false); + pool->base.clock_sources[DCN401_CLK_SRC_PLL4] = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_COMBO_PHY_PLL4, + &clk_src_regs[4], false); + + pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL; + + /* todo: not reuse phy_pll registers */ + pool->base.dp_clock_source = + dcn42_clock_source_create(ctx, ctx->dc_bios, + CLOCK_SOURCE_ID_DP_DTO, + &clk_src_regs[0], true); + + for (i = 0; i < pool->base.clk_src_count; i++) { + if (pool->base.clock_sources[i] == NULL) { + dm_error("DC: failed to create clock sources!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + } + + /* DCCG */ + pool->base.dccg = dccg42_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); + if (pool->base.dccg == NULL) { + dm_error("DC: failed to create dccg!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + +#undef REG_STRUCT +#define REG_STRUCT pg_cntl_regs + pg_cntl_dcn42_regs_init(); + + pool->base.pg_cntl = pg_cntl42_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask); + if (pool->base.pg_cntl == NULL) { + dm_error("DC: failed to create power gate control!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + /* IRQ Service */ + init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dcn42_create(&init_data); + if (!pool->base.irqs) + goto create_fail; + + /* HUBBUB */ + pool->base.hubbub = dcn42_hubbub_create(ctx); + if (pool->base.hubbub == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create hubbub!\n"); + goto create_fail; + } + + /* HUBPs, DPPs, OPPs, TGs, ABMs */ + for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) { + /* if pipe is disabled, skip instance of HW pipe, + * i.e, skip ASIC register instance + */ + if (pipe_fuses & 1 << i) + continue; + + pool->base.hubps[j] = dcn42_hubp_create(ctx, i); + if (pool->base.hubps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create hubps!\n"); + goto create_fail; + } + + pool->base.dpps[j] = dcn42_dpp_create(ctx, i); + if (pool->base.dpps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create dpps!\n"); + goto create_fail; + } + + pool->base.opps[j] = dcn42_opp_create(ctx, i); + if (pool->base.opps[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC: failed to create output pixel processor!\n"); + goto create_fail; + } + + pool->base.timing_generators[j] = dcn42_timing_generator_create( + ctx, i); + if (pool->base.timing_generators[j] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create tg!\n"); + goto create_fail; + } + + pool->base.multiple_abms[j] = dmub_abm_create(ctx, + &abm_regs[i], + &abm_shift, + &abm_mask); + if (pool->base.multiple_abms[j] == NULL) { + dm_error("DC: failed to create abm for pipe %d!\n", i); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* index for resource pool arrays for next valid pipe */ + j++; + } + + /* PSR */ + pool->base.psr = dmub_psr_create(ctx); + if (pool->base.psr == NULL) { + dm_error("DC: failed to create psr obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* Replay */ + pool->base.replay = dmub_replay_create(ctx); + if (pool->base.replay == NULL) { + dm_error("DC: failed to create replay obj!\n"); + BREAK_TO_DEBUGGER(); + goto create_fail; + } + + /* MPCCs */ + pool->base.mpc = dcn42_mpc_create(ctx, pool->base.res_cap->num_timing_generator, + pool->base.res_cap->num_mpc_3dlut); + if (pool->base.mpc == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mpc!\n"); + goto create_fail; + } + + /* DSCs */ + for (i = 0; i < pool->base.res_cap->num_dsc; i++) { + pool->base.dscs[i] = dcn42_dsc_create(ctx, i); + if (pool->base.dscs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create display stream compressor %d!\n", i); + goto create_fail; + } + } + + /* DWB */ + if (!dcn42_dwbc_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create dwbc!\n"); + goto create_fail; + } + + /* MMHUBBUB */ + if (!dcn42_mmhubbub_create(ctx, &pool->base)) { + BREAK_TO_DEBUGGER(); + dm_error("DC: failed to create mcif_wb!\n"); + goto create_fail; + } + + /* AUX and I2C */ + for (i = 0; i < pool->base.res_cap->num_ddc; i++) { + pool->base.engines[i] = dcn42_aux_engine_create(ctx, i); + + if (pool->base.engines[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create aux engine!!\n"); + goto create_fail; + } + pool->base.hw_i2cs[i] = dcn42_i2c_hw_create(ctx, i); + if (pool->base.hw_i2cs[i] == NULL) { + BREAK_TO_DEBUGGER(); + dm_error( + "DC:failed to create hw i2c!!\n"); + goto create_fail; + } + pool->base.sw_i2cs[i] = NULL; + } + /* DCN4.2 has 6 DPIA */ + pool->base.usb4_dpia_count = dc->caps.num_of_host_routers * dc->caps.num_of_dpias_per_host_router; + if (dc->debug.dpia_debug.bits.disable_dpia) + pool->base.usb4_dpia_count = 0; + + /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ + if (!resource_construct(num_virtual_links, dc, &pool->base, + &res_create_funcs)) + goto create_fail; + + /* HW Sequencer init functions and Plane caps */ + dcn42_hw_sequencer_init_functions(dc); + + dc->caps.max_planes = pool->base.pipe_count; + + for (i = 0; i < dc->caps.max_planes; ++i) + dc->caps.planes[i] = plane_cap; + + dc->caps.max_odm_combine_factor = 4; + + dc->cap_funcs = cap_funcs; + dc->dcn_ip->max_num_dpp = pool->base.pipe_count; + + // For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided + if (dc->config.sdpif_request_limit_words_per_umc == 0) + dc->config.sdpif_request_limit_words_per_umc = 16; + + dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; + /*this will use real soc clock table*/ + dc->dml2_options.use_native_soc_bb_construction = true; + dc->dml2_options.minimize_dispclk_using_odm = false; + if (dc->config.EnableMinDispClkODM) + dc->dml2_options.minimize_dispclk_using_odm = true; + dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm; + dc->dml2_options.map_dc_pipes_with_callbacks = true; + dc->dml2_options.force_tdlut_enable = true; + + resource_init_common_dml2_callbacks(dc, &dc->dml2_options); + dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = + &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; + dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc; + dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = + pool->base.funcs->calculate_mall_ways_from_bytes; + + dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us; + dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us; + dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us; + dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines; + + dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp; + dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch; + + dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size; + dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways; + dc->dml2_options.mall_cfg.max_cab_allocation_bytes = + dc->caps.max_cab_allocation_bytes; + dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE; + dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE; + dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES; + dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH; + + dc->dml2_options.max_segments_per_hubp = 24; + dc->dml2_options.det_segment_size = DCN42_CRB_SEGMENT_SIZE_KB; + dc->dml2_options.gpuvm_enable = true; + dc->dml2_options.hostvm_enable = true; + + /* SPL */ + dc->caps.scl_caps.sharpener_support = true; + + return true; + +create_fail: + + dcn42_resource_destruct(pool); + + return false; +} +struct resource_pool *dcn42_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc) +{ + struct dcn42_resource_pool *pool = + kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL); + + if (!pool) + return NULL; + + if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool)) + return &pool->base; + + BREAK_TO_DEBUGGER(); + kfree(pool); + return NULL; +} diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h new file mode 100644 index 0000000000000..60acf0e423d97 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.h @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef _DCN42_RESOURCE_H_ +#define _DCN42_RESOURCE_H_ + +#include "core_types.h" + +#define TO_DCN42_RES_POOL(pool) \ + container_of(pool, struct dcn42_resource_pool, base) + +/* DPP */ +#define DPP_REG_LIST_DCN42_COMMON_RI(id) \ + SRI_ARR(CM_DEALPHA, CM, id), SRI_ARR(CM_MEM_PWR_STATUS, CM, id), \ + SRI_ARR(CM_BIAS_CR_R, CM, id), SRI_ARR(CM_BIAS_Y_G_CB_B, CM, id), \ + SRI_ARR(PRE_DEGAM, CNVC_CFG, id), SRI_ARR(CM_GAMCOR_CONTROL, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_CONTROL, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_INDEX, CM, id), \ + SRI_ARR(CM_GAMCOR_LUT_DATA, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL1_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_END_CNTL2_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_REGION_0_1, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_REGION_32_33, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_OFFSET_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_OFFSET_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_OFFSET_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMB_START_BASE_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_SLOPE_CNTL_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL1_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_END_CNTL2_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_REGION_0_1, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_REGION_32_33, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_OFFSET_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_OFFSET_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_OFFSET_R, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_B, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_G, CM, id), \ + SRI_ARR(CM_GAMCOR_RAMA_START_BASE_CNTL_R, CM, id), \ + SRI_ARR(CM_HIST_CNTL, CM, id), \ + SRI_ARR(CM_HIST_LOCK, CM, id), \ + SRI_ARR(CM_HIST_INDEX, CM, id), \ + SRI_ARR(CM_HIST_DATA, CM, id), \ + SRI_ARR(CM_HIST_STATUS, CM, id), \ + SRI_ARR(CM_HIST_SCALE_SRC1, CM, id), \ + SRI_ARR(CM_HIST_COEFA_SRC2, CM, id), \ + SRI_ARR(CM_HIST_COEFB_SRC2, CM, id), \ + SRI_ARR(CM_HIST_COEFC_SRC2, CM, id), \ + SRI_ARR(CM_HIST_SCALE_SRC3, CM, id), \ + SRI_ARR(CM_HIST_BIAS_SRC1, CM, id), \ + SRI_ARR(CM_HIST_BIAS_SRC2, CM, id), \ + SRI_ARR(CM_HIST_BIAS_SRC3, CM, id), \ + SRI_ARR(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \ + SRI_ARR(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \ + SRI_ARR(OTG_H_BLANK, DSCL, id), SRI_ARR(OTG_V_BLANK, DSCL, id), \ + SRI_ARR(SCL_MODE, DSCL, id), SRI_ARR(LB_DATA_FORMAT, DSCL, id), \ + SRI_ARR(LB_MEMORY_CTRL, DSCL, id), SRI_ARR(DSCL_AUTOCAL, DSCL, id), \ + SRI_ARR(SCL_TAP_CONTROL, DSCL, id), \ + SRI_ARR(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \ + SRI_ARR(SCL_COEF_RAM_TAP_DATA, DSCL, id), \ + SRI_ARR(DSCL_2TAP_CONTROL, DSCL, id), SRI_ARR(MPC_SIZE, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_INIT, DSCL, id), \ + SRI_ARR(SCL_HORZ_FILTER_INIT_C, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT_C, DSCL, id), \ + SRI_ARR(RECOUT_START, DSCL, id), SRI_ARR(RECOUT_SIZE, DSCL, id), \ + SRI_ARR(PRE_DEALPHA, CNVC_CFG, id), SRI_ARR(PRE_REALPHA, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_MODE, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_C11_C12, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_C33_C34, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_B_C11_C12, CNVC_CFG, id), \ + SRI_ARR(PRE_CSC_B_C33_C34, CNVC_CFG, id), \ + SRI_ARR(CM_POST_CSC_CONTROL, CM, id), \ + SRI_ARR(CM_POST_CSC_C11_C12, CM, id), \ + SRI_ARR(CM_POST_CSC_C33_C34, CM, id), \ + SRI_ARR(CM_POST_CSC_B_C11_C12, CM, id), \ + SRI_ARR(CM_POST_CSC_B_C33_C34, CM, id), \ + SRI_ARR(CM_MEM_PWR_CTRL, CM, id), SRI_ARR(CM_CONTROL, CM, id), \ + SRI_ARR(CM_TEST_DEBUG_INDEX, CM, id), \ + SRI_ARR(CM_TEST_DEBUG_DATA, CM, id), \ + SRI_ARR(FORMAT_CONTROL, CNVC_CFG, id), \ + SRI_ARR(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ + SRI_ARR(CURSOR0_CONTROL, CM_CUR, id), \ + SRI_ARR(CURSOR0_COLOR0, CM_CUR, id), \ + SRI_ARR(CURSOR0_COLOR1, CM_CUR, id), \ + SRI_ARR(CURSOR0_FP_SCALE_BIAS_G_Y, CM_CUR, id), \ + SRI_ARR(CURSOR0_FP_SCALE_BIAS_RB_CRCB, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_MODE, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C11_C12_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C13_C14_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C21_C22_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C23_C24_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C31_C32_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C33_C34_A, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C11_C12_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C13_C14_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C21_C22_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C23_C24_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C31_C32_B, CM_CUR, id), \ + SRI_ARR(CUR0_MATRIX_C33_C34_B, CM_CUR, id), \ + SRI_ARR(DPP_CONTROL, DPP_TOP, id), SRI_ARR(CM_HDR_MULT_COEF, CM, id), \ + SRI_ARR(CURSOR_CONTROL, CURSOR0_, id), \ + SRI_ARR(ALPHA_2BIT_LUT01, CNVC_CFG, id), \ + SRI_ARR(ALPHA_2BIT_LUT23, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_BIAS_R, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_BIAS_G, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_BIAS_B, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_SCALE_R, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_SCALE_G, CNVC_CFG, id), \ + SRI_ARR(FCNV_FP_SCALE_B, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_CONTROL, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_ALPHA, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_RED, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_GREEN, CNVC_CFG, id), \ + SRI_ARR(COLOR_KEYER_BLUE, CNVC_CFG, id), \ + SRI_ARR(OBUF_MEM_PWR_CTRL, DSCL, id), \ + SRI_ARR(DSCL_MEM_PWR_STATUS, DSCL, id), \ + SRI_ARR(DSCL_MEM_PWR_CTRL, DSCL, id), \ + SRI_ARR(DSCL_CONTROL, DSCL, id), \ + SRI_ARR(DSCL_SC_MODE, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_MODE, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF_CNTL, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF_FINAL_MAX_MIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG6, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF1_PWL_SEG7, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_H_BF3_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_MODE, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF_CNTL, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL1, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL2, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_3TAP_CNTL3, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF_FINAL_MAX_MIN, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG6, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF1_PWL_SEG7, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG0, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG1, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG2, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG3, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG4, DSCL, id), \ + SRI_ARR(DSCL_EASF_V_BF3_PWL_SEG5, DSCL, id), \ + SRI_ARR(DSCL_SC_MATRIX_C0C1, DSCL, id), \ + SRI_ARR(DSCL_SC_MATRIX_C2C3, DSCL, id), \ + SRI_ARR(ISHARP_MODE, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_LUT_MEM_PWR_CTRL, DSCL, id), \ + SRI_ARR(ISHARP_NOISEDET_THRESHOLD, DSCL, id), \ + SRI_ARR(ISHARP_NOISE_GAIN_PWL, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG0, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG1, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG2, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG3, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG4, DSCL, id), \ + SRI_ARR(ISHARP_LBA_PWL_SEG5, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_CTRL, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_DATA, DSCL, id), \ + SRI_ARR(ISHARP_DELTA_INDEX, DSCL, id), \ + SRI_ARR(ISHARP_NLDELTA_SOFT_CLIP, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \ + SRI_ARR(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id) + +/* Stream encoder */ +#define SE_DCN42_REG_LIST_RI(id) \ + SRI_ARR(HDMI_CONTROL, DIG, id), SRI_ARR(HDMI_DB_CONTROL, DIG, id), \ + SRI_ARR(HDMI_GC, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL5, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL6, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL7, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL8, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL9, DIG, id), \ + SRI_ARR(HDMI_GENERIC_PACKET_CONTROL10, DIG, id), \ + SRI_ARR(HDMI_INFOFRAME_CONTROL0, DIG, id), \ + SRI_ARR(HDMI_VBI_PACKET_CONTROL, DIG, id), \ + SRI_ARR(HDMI_AUDIO_PACKET_CONTROL, DIG, id), \ + SRI_ARR(HDMI_ACR_PACKET_CONTROL, DIG, id), \ + SRI_ARR(HDMI_ACR_32_0, DIG, id), SRI_ARR(HDMI_ACR_32_1, DIG, id), \ + SRI_ARR(HDMI_ACR_44_0, DIG, id), SRI_ARR(HDMI_ACR_44_1, DIG, id), \ + SRI_ARR(HDMI_ACR_48_0, DIG, id), SRI_ARR(HDMI_ACR_48_1, DIG, id), \ + SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \ + SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \ + SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \ + SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \ + SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \ + SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \ + SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \ + SRI_ARR(DP_STEER_FIFO, DP, id), SRI_ARR(DP_VID_M, DP, id), \ + SRI_ARR(DP_VID_N, DP, id), SRI_ARR(DP_VID_STREAM_CNTL, DP, id), \ + SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \ + SRI_ARR(DP_SEC_TIMESTAMP, DP, id), \ + SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ + SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ + SRI_ARR(DP_SEC_FRAMING4, DP, id), SRI_ARR(DP_GSP11_CNTL, DP, id), \ + SRI_ARR(DME_CONTROL, DME, id), \ + SRI_ARR(DP_SEC_METADATA_TRANSMISSION, DP, id), \ + SRI_ARR(HDMI_METADATA_PACKET_CONTROL, DIG, id), \ + SRI_ARR(DIG_FE_CNTL, DIG, id), \ + SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \ + SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \ + SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \ + SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \ + SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id),\ + SRI_ARR(DIG_FE_AUDIO_CNTL, DIG, id) + +/* HPO DP stream encoder */ +#define DCN42_HPO_DP_STREAM_ENC_REG_LIST_RI(id) \ + SR_ARR(DP_STREAM_MAPPER_CONTROL0, id), \ + SR_ARR(DP_STREAM_MAPPER_CONTROL1, id), \ + SR_ARR(DP_STREAM_MAPPER_CONTROL2, id), \ + SR_ARR(DP_STREAM_MAPPER_CONTROL3, id), \ + SRI_ARR(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id), \ + SRI_ARR(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id), \ + SRI_ARR(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id), \ + SRI_ARR(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \ + SRI_ARR(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id) + +/*HPO DP link encoder regs */ +#define DCN42_HPO_DP_LINK_ENC_REG_LIST_RI(id) \ + SRI_ARR(DP_LINK_ENC_CLOCK_CONTROL, DP_LINK_ENC, id), \ + SRI_ARR(DP_DPHY_SYM32_CONTROL, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_STATUS, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CONFIG, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_PRBS_SEED3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_SQ_PULSE, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM4, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM5, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM6, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM7, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM8, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM9, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_TP_CUSTOM10, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_VC3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL0, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL1, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL2, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_VC_RATE_CNTL3, DP_DPHY_SYM32, id), \ + SRI_ARR(DP_DPHY_SYM32_SAT_UPDATE, DP_DPHY_SYM32, id) + +#define VPG_DCN42_REG_LIST_RI(id) \ + SRI(VPG_GENERIC_STATUS, VPG, id), \ + SRI(VPG_GENERIC_PACKET_ACCESS_CTRL, VPG, id), \ + SRI(VPG_GENERIC_PACKET_DATA, VPG, id), \ + SRI(VPG_GSP_FRAME_UPDATE_CTRL, VPG, id), \ + SRI(VPG_GSP_IMMEDIATE_UPDATE_CTRL, VPG, id), \ + SRI(VPG_MEM_PWR, VPG, id) + +/* DCCG */ +#define DCCG_REG_LIST_DCN42_RI() \ + SR(DPPCLK_DTO_CTRL), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 0), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 1), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 2), \ + DCCG_SRII(DTO_PARAM, DPPCLK, 3), \ + DCCG_SRII(CLOCK_CNTL, HDMICHARCLK, 0), \ + SR(HDMISTREAMCLK0_DTO_PARAM),\ + SR(DCCG_GLOBAL_FGCG_REP_CNTL),\ + SR(DISPCLK_FREQ_CHANGE_CNTL), \ + SR(PHYASYMCLK_CLOCK_CNTL), \ + SR(PHYBSYMCLK_CLOCK_CNTL), \ + SR(PHYCSYMCLK_CLOCK_CNTL), \ + SR(PHYDSYMCLK_CLOCK_CNTL), \ + SR(PHYESYMCLK_CLOCK_CNTL), \ + SR(DPSTREAMCLK_CNTL), \ + SR(HDMISTREAMCLK_CNTL), \ + SR(SYMCLK32_SE_CNTL), \ + SR(SYMCLK32_LE_CNTL), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2), \ + DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3), \ + SR(OTG_PIXEL_RATE_DIV), \ + SR(DTBCLK_P_CNTL), \ + SR(DCCG_AUDIO_DTO_SOURCE), \ + SR(DENTIST_DISPCLK_CNTL), \ + SR(DPPCLK_CTRL), \ + DCCG_SRII(MODULO, DP_DTO, 0), \ + DCCG_SRII(MODULO, DP_DTO, 1), \ + DCCG_SRII(MODULO, DP_DTO, 2), \ + DCCG_SRII(MODULO, DP_DTO, 3), \ + DCCG_SRII(PHASE, DP_DTO, 0), \ + DCCG_SRII(PHASE, DP_DTO, 1), \ + DCCG_SRII(PHASE, DP_DTO, 2), \ + DCCG_SRII(PHASE, DP_DTO, 3), \ + SR(OTG_ADD_DROP_PIXEL_CNTL), \ + SR(DSCCLK0_DTO_PARAM), \ + SR(DSCCLK1_DTO_PARAM), \ + SR(DSCCLK2_DTO_PARAM), \ + SR(DSCCLK3_DTO_PARAM), \ + SR(DSCCLK_DTO_CTRL), \ + SR(DCCG_GATE_DISABLE_CNTL), \ + SR(DCCG_GATE_DISABLE_CNTL2), \ + SR(DCCG_GATE_DISABLE_CNTL3), \ + SR(DCCG_GATE_DISABLE_CNTL4), \ + SR(DCCG_GATE_DISABLE_CNTL5), \ + SR(DCCG_GATE_DISABLE_CNTL6), \ + SR(SYMCLKA_CLOCK_ENABLE), \ + SR(SYMCLKB_CLOCK_ENABLE), \ + SR(SYMCLKC_CLOCK_ENABLE), \ + SR(SYMCLKD_CLOCK_ENABLE), \ + SR(SYMCLKE_CLOCK_ENABLE) + +#define DCN42_AUD_COMMON_MASK_SH_LIST(mask_sh) \ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh), \ + SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\ + SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\ + SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ + SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ + SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ + SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\ + SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\ + SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\ + SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) + + /* HPO FRL stream encoder */ +#define DCN42_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) \ + DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id), \ + SR_ARR(HDMI_STREAM_ENC_AUDIO_CONTROL, id),\ + SR_ARR(HDMI_TB_ENC_MEM_CTRL, id),\ + SR_ARR(HDMI_FRL_ENC_MEM_CTRL, id) +/* OPTC */ +#define OPTC_COMMON_REG_LIST_DCN42_RI(inst) \ + SRI_ARR(OTG_VSTARTUP_PARAM, OTG, inst), \ + SRI_ARR(OTG_VUPDATE_PARAM, OTG, inst), \ + SRI_ARR(OTG_VREADY_PARAM, OTG, inst), \ + SRI_ARR(OTG_MASTER_UPDATE_LOCK, OTG, inst), \ + SRI_ARR(OTG_MASTER_UPDATE_MODE, OTG, inst), \ + SRI_ARR(OTG_V_COUNT_STOP_CONTROL, OTG, inst), \ + SRI_ARR(OTG_V_COUNT_STOP_CONTROL2, OTG, inst), \ + SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ + SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\ + SRI_ARR(OTG_GLOBAL_CONTROL0, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL4, OTG, inst), \ + SRI_ARR(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst), \ + SRI_ARR(OTG_H_TOTAL, OTG, inst), \ + SRI_ARR(OTG_H_BLANK_START_END, OTG, inst), \ + SRI_ARR(OTG_H_SYNC_A, OTG, inst),\ + SRI_ARR(OTG_H_SYNC_A_CNTL, OTG, inst), \ + SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL, OTG, inst), \ + SRI_ARR(OTG_V_BLANK_START_END, OTG, inst), \ + SRI_ARR(OTG_V_SYNC_A, OTG, inst), \ + SRI_ARR(OTG_V_SYNC_A_CNTL, OTG, inst), \ + SRI_ARR(OTG_CONTROL, OTG, inst), \ + SRI_ARR(OTG_STEREO_CONTROL, OTG, inst), \ + SRI_ARR(OTG_3D_STRUCTURE_CONTROL, OTG, inst), \ + SRI_ARR(OTG_STEREO_STATUS, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL_MAX, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL_MIN, OTG, inst), \ + SRI_ARR(OTG_V_TOTAL_CONTROL, OTG, inst), \ + SRI_ARR(OTG_TRIGA_CNTL, OTG, inst), \ + SRI_ARR(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst), \ + SRI_ARR(OTG_STATIC_SCREEN_CONTROL, OTG, inst), \ + SRI_ARR(OTG_STATUS_FRAME_COUNT, OTG, inst), \ + SRI_ARR(OTG_STATUS, OTG, inst), \ + SRI_ARR(OTG_STATUS_POSITION, OTG, inst), \ + SRI_ARR(OTG_NOM_VERT_POSITION, OTG, inst), \ + SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \ + SRI_ARR(OTG_M_CONST_DTO1, OTG, inst), \ + SRI_ARR(OTG_CLOCK_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst), \ + SRI_ARR(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst), \ + SRI_ARR(OPTC_INPUT_CLOCK_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_DATA_SOURCE_SELECT, ODM, inst), \ + SRI_ARR(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_RSMU_UNDERFLOW, ODM, inst), \ + SRI_ARR(OPTC_UNDERFLOW_THRESHOLD, ODM, inst), \ + SRI_ARR(CONTROL, VTG, inst), \ + SRI_ARR(OTG_VERT_SYNC_CONTROL, OTG, inst), \ + SRI_ARR(OTG_GSL_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC_CNTL, OTG, inst), \ + SRI_ARR(OTG_CRC0_DATA_R, OTG, inst), \ + SRI_ARR(OTG_CRC0_DATA_G, OTG, inst), \ + SRI_ARR(OTG_CRC0_DATA_B, OTG, inst), \ + SRI_ARR(OTG_CRC1_DATA_R, OTG, inst), \ + SRI_ARR(OTG_CRC1_DATA_G, OTG, inst), \ + SRI_ARR(OTG_CRC1_DATA_B, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL, OTG, inst), \ + SRI_ARR(OTG_CRC0_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC0_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC0_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC0_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWA_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWA_Y_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWB_X_CONTROL_READBACK, OTG, inst),\ + SRI_ARR(OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG, inst),\ + SR_ARR(GSL_SOURCE_SELECT, inst), \ + SRI_ARR(OTG_TRIGA_MANUAL_TRIG, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL1, OTG, inst), \ + SRI_ARR(OTG_GLOBAL_CONTROL2, OTG, inst), \ + SRI_ARR(OTG_GSL_WINDOW_X, OTG, inst), \ + SRI_ARR(OTG_GSL_WINDOW_Y, OTG, inst), \ + SRI_ARR(OTG_VUPDATE_KEEPOUT, OTG, inst), \ + SRI_ARR(OTG_DRR_TRIGGER_WINDOW, OTG, inst), \ + SRI_ARR(OTG_DRR_V_TOTAL_CHANGE, OTG, inst), \ + SRI_ARR(OPTC_DATA_FORMAT_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ + SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ + SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ + SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ + SRI_ARR(OTG_PWA_FRAME_SYNC_CONTROL, OTG, inst),\ + SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst),\ + SRI_ARR(INTERRUPT_DEST, OTG, inst) + +/* CLK SRC */ +#define CS_COMMON_REG_LIST_DCN42_RI(index, pllid) \ + SRI_ARR_ALPHABET(PIXCLK_RESYNC_CNTL, PHYPLL, index, pllid), \ + SRII_ARR_2(PHASE, DP_DTO, 0, index), \ + SRII_ARR_2(PHASE, DP_DTO, 1, index), \ + SRII_ARR_2(PHASE, DP_DTO, 2, index), \ + SRII_ARR_2(PHASE, DP_DTO, 3, index), \ + SRII_ARR_2(MODULO, DP_DTO, 0, index), \ + SRII_ARR_2(MODULO, DP_DTO, 1, index), \ + SRII_ARR_2(MODULO, DP_DTO, 2, index), \ + SRII_ARR_2(MODULO, DP_DTO, 3, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 0, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 1, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 2, index), \ + SRII_ARR_2(PIXEL_RATE_CNTL, OTG, 3, index) + +/* ABM */ +#define ABM_DCN42_REG_LIST_RI(id) \ + SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ + SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ + SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \ + SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ + SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ + SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ + SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ + SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \ + SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ + SRI_ARR(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_HG_RESULT_DATA, ABM, id), \ + SRI_ARR(DC_ABM1_HG_RESULT_INDEX, ABM, id), \ + SRI_ARR(DC_ABM1_ACE_OFFSET_SLOPE_DATA, ABM, id), \ + SRI_ARR(DC_ABM1_ACE_PWL_CNTL, ABM, id) + +/* HUBP */ +#define HUBP_REG_LIST_DCN42_RI(id) \ + HUBP_REG_LIST_DCN30_RI(id), SRI_ARR(DCHUBP_MALL_CONFIG, HUBP, id), \ + SRI_ARR(DCHUBP_VMPG_CONFIG, HUBP, id), \ + SRI_ARR(UCLK_PSTATE_FORCE, HUBPREQ, id), \ + SRI_ARR(HUBP_3DLUT_DLG_PARAM, CURSOR0_, id), \ + HUBP_3DLUT_FL_REG_LIST_DCN401(id) +struct dcn42_resource_pool { + struct resource_pool base; +}; +struct resource_pool *dcn42_create_resource_pool( + const struct dc_init_data *init_data, + struct dc *dc); + +enum dc_status dcn42_validate_bandwidth(struct dc *dc, + struct dc_state *context, + enum dc_validate_mode validate_mode); + +void dcn42_prepare_mcache_programming(struct dc *dc, struct dc_state *context); +int dcn42_get_power_profile(const struct dc_state *context); + +#endif /* _DCN42_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c new file mode 100644 index 0000000000000..33b9775420d3d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + + + +#include "dc.h" +#include "dcn42_resource_fpu.h" + +#define DC_LOGGER_INIT(logger) + + +void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context) +{ + enum dcn_zstate_support_state support = DCN_ZSTATE_SUPPORT_DISALLOW; + unsigned int i, plane_count = 0; + + DC_LOGGER_INIT(dc->ctx->logger); + + dc_assert_fp_enabled(); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + if (context->res_ctx.pipe_ctx[i].plane_state) + plane_count++; + } + /*dcn42 has no z10*/ + if (context->stream_count == 0 || plane_count == 0) { + support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY; + } else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) { + struct dc_link *link = context->streams[0]->sink->link; + bool is_psr = (link && (link->psr_settings.psr_version == DC_PSR_VERSION_1 || + link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) && !link->panel_config.psr.disable_psr); + bool is_replay = link && link->replay_settings.replay_feature_enabled; + + if (is_psr || is_replay) + support = DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY; + else { + /*here we allow z8 for eDP based on dml21 output*/ + support = context->bw_ctx.bw.dcn.clk.zstate_support ? DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY : DCN_ZSTATE_SUPPORT_DISALLOW; + } + + DC_LOG_SMU("zstate_support: %d, StutterPeriod: %d\n, z8_stutter_efficiency: %d\n", + support, (int)context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period, + (int)context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency); + } + context->bw_ctx.bw.dcn.clk.zstate_support = support; + +} diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h similarity index 78% rename from drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h rename to drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h index eca3e5168089b..e321032205073 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource_fpu.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2020 Mauro Rossi + * Copyright 2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,18 +20,14 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * - * Authors: AMD - * */ -#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_ -#define DAL_DC_DCE_DCE60_CLK_MGR_H_ +#ifndef _DCN42_RESOURCE_FPU_H_ +#define _DCN42_RESOURCE_FPU_H_ -#include "dc.h" +#include "core_types.h" -void dce60_clk_mgr_construct( - struct dc_context *ctx, - struct clk_mgr_internal *clk_mgr_dce); +void dcn42_decide_zstate_support(struct dc *dc, struct dc_state *context); -#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */ +#endif /* _DCN42_RESOURCE_FPU_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile index bc93356a0b5b9..f905b4d224488 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/Makefile @@ -4,15 +4,56 @@ # Makefile for bounding box component. # Floating point required due to nature of bounding box values +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT soc_and_ip_translator_ccflags := $(CC_FLAGS_FPU) soc_and_ip_translator_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +soc_and_ip_translator_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +soc_and_ip_translator_ccflags := $(soc_and_ip_translator_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +soc_and_ip_translator_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +soc_and_ip_translator_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +soc_and_ip_translator_ccflags := -mfpu=64 +soc_and_ip_translator_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +soc_and_ip_translator_ccflags += -mpreferred-stack-boundary=4 +else +soc_and_ip_translator_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) +CFLAGS_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.o := $(soc_and_ip_translator_ccflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.o := $(soc_and_ip_translator_rcflags) +CFLAGS_REMOVE_$(AMDDALPATH)/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.o := $(soc_and_ip_translator_rcflags) soc_and_ip_translator := soc_and_ip_translator.o soc_and_ip_translator += dcn401/dcn401_soc_and_ip_translator.o +soc_and_ip_translator += dcn42/dcn42_soc_and_ip_translator.o AMD_DAL_soc_and_ip_translator := $(addprefix $(AMDDALPATH)/dc/soc_and_ip_translator/, $(soc_and_ip_translator)) diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c index 3190c76eb4820..1b397fa7e05c9 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c @@ -102,6 +102,9 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table( } } else { dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; + #ifdef ENABLE_WCK + dml_clk_table->wck_ratio.clk_values_khz[i] = dc_clk_table->entries[i].wck_ratio; + #endif } } else { dml_clk_table->uclk.clk_values_khz[i] = 0; diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c index c9e224d262c90..1c04171b296c2 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c @@ -3,7 +3,7 @@ // Copyright 2025 Advanced Micro Devices, Inc. #include "dcn42_soc_and_ip_translator.h" -#include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h" +#include "../dcn401/dcn401_soc_and_ip_translator.h" #include "bounding_boxes/dcn42_soc_bb.h" /* soc_and_ip_translator component used to get up-to-date values for bounding box. @@ -11,13 +11,179 @@ * This component provides an interface to get DCN-specific bounding box values. */ +static void get_default_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc) +{ + { + memcpy(soc_bb, &dml2_socbb_dcn42, sizeof(struct dml2_soc_bb)); + memcpy(&soc_bb->qos_parameters, &dml_dcn42_variant_a_soc_qos_params, sizeof(struct dml2_soc_qos_parameters)); + } +} + +/* + * DC clock table is obtained from SMU during runtime. + * SMU stands for System Management Unit. It is a power management processor. + * It owns the initialization of dc's clock table and programming of clock values + * based on dc's requests. + * Our clock values in base soc bb is a dummy placeholder. The real clock values + * are retrieved from SMU firmware to dc clock table at runtime. + * This function overrides our dummy placeholder values with real values in dc + * clock table. + */ +static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table( + struct dml2_soc_state_table *dml_clk_table, + struct dml2_soc_vmin_clock_limits *vmin_limit, + const struct clk_bw_params *dc_bw_params) +{ + int i; + const struct clk_limit_table *dc_clk_table; + + if (dc_bw_params == NULL) + /* skip if bw params could not be obtained from smu */ + return; + + dc_clk_table = &dc_bw_params->clk_table; + + /* fclk/dcfclk - dcn42 pmfw table can have 0 entries for inactive dpm levels + * for use with dml we need to fill in using an active value aiming for >= 2x DCFCLK + */ + if (dc_clk_table->num_entries_per_clk.num_fclk_levels && dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dc_clk_table->num_entries_per_clk.num_dcfclk_levels) { + int j, max_fclk = 0; + + dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000; + for (j = 0; j < MAX_NUM_DPM_LVL; j++) { + if (dc_clk_table->entries[j].fclk_mhz * 1000 > max_fclk) + max_fclk = dc_clk_table->entries[j].fclk_mhz * 1000; + dml_clk_table->fclk.clk_values_khz[i] = max_fclk; + if (max_fclk >= 2 * dml_clk_table->dcfclk.clk_values_khz[i]) + break; + } + } else { + dml_clk_table->dcfclk.clk_values_khz[i] = 0; + dml_clk_table->fclk.clk_values_khz[i] = 0; + } + } + } + + /* uclk */ + if (dc_clk_table->num_entries_per_clk.num_memclk_levels) { + dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->uclk.num_clk_values) { + dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000; + dml_clk_table->wck_ratio.clk_values_khz[i] = dc_clk_table->entries[i].wck_ratio; + } else { + dml_clk_table->uclk.clk_values_khz[i] = 0; + dml_clk_table->wck_ratio.clk_values_khz[i] = 0; + } + } + } + + /* dispclk */ + if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) { + dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dispclk.num_clk_values) { + dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; + } else { + dml_clk_table->dispclk.clk_values_khz[i] = 0; + } + } + vmin_limit->dispclk_khz = min(dc_clk_table->entries[0].dispclk_mhz * 1000, vmin_limit->dispclk_khz); + /* dispclk is always fine-grain */ + dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels >= 2 ? 2 : 1; + dml_clk_table->dispclk.clk_values_khz[0] = 0; + dml_clk_table->dispclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk.num_dispclk_levels - 1].dispclk_mhz * 1000; + } + + /* dppclk */ + if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) { + dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dppclk.num_clk_values) { + dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000; + } else { + dml_clk_table->dppclk.clk_values_khz[i] = 0; + } + } + /* dppclk is always fine-grain */ + dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels >= 2 ? 2 : 1; + dml_clk_table->dppclk.clk_values_khz[0] = 0; + dml_clk_table->dppclk.clk_values_khz[1] = dc_clk_table->entries[dc_clk_table->num_entries_per_clk.num_dppclk_levels - 1].dppclk_mhz * 1000; + } + + /* dtbclk */ + if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) { + dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->dtbclk.num_clk_values) { + dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; + } else { + dml_clk_table->dtbclk.clk_values_khz[i] = 0; + } + } + } + + /* socclk */ + if (dc_clk_table->num_entries_per_clk.num_socclk_levels) { + dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels; + for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) { + if (i < dml_clk_table->socclk.num_clk_values) { + dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000; + } else { + dml_clk_table->socclk.clk_values_khz[i] = 0; + } + } + } + + /* dram config */ + dml_clk_table->dram_config.channel_count = dc_bw_params->num_channels; + dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes; +} + +static void dcn42_update_soc_bb_with_values_from_clk_mgr(struct dml2_soc_bb *soc_bb, const struct dc *dc) +{ + soc_bb->dprefclk_mhz = dc->clk_mgr->dprefclk_khz / 1000; + soc_bb->dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; + soc_bb->mall_allocated_for_dcn_mbytes = dc->caps.mall_size_total / (1024 * 1024); + + if (dc->clk_mgr->funcs->is_smu_present && + dc->clk_mgr->funcs->is_smu_present(dc->clk_mgr)) { + dcn42_convert_dc_clock_table_to_soc_bb_clock_table(&soc_bb->clk_table, &soc_bb->vmin_limit, + dc->clk_mgr->bw_params); + } +} + +static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + /* Individual modification can be overwritten even if it was obtained by a previous function. + * Modifications are acquired in order of priority (lowest to highest). + */ + dc_assert_fp_enabled(); + + dcn42_update_soc_bb_with_values_from_clk_mgr(soc_bb, dc); + dcn401_update_soc_bb_with_values_from_vbios(soc_bb, dc); + dcn401_update_soc_bb_with_values_from_software_policy(soc_bb, dc); +} + +void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config) +{ + //get default soc_bb with static values + get_default_soc_bb(soc_bb, dc); + //update soc_bb values with more accurate values + apply_soc_bb_updates(soc_bb, dc, config); +} + static void dcn42_get_ip_caps(struct dml2_ip_capabilities *ip_caps) { *ip_caps = dml2_dcn42_max_ip_caps; } static struct soc_and_ip_translator_funcs dcn42_translator_funcs = { - .get_soc_bb = dcn401_get_soc_bb, + .get_soc_bb = dcn42_get_soc_bb, .get_ip_caps = dcn42_get_ip_caps, }; @@ -25,3 +191,4 @@ void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and { soc_and_ip_translator->translator_funcs = &dcn42_translator_funcs; } + diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h index 914dcbb369a75..1dded54261521 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h @@ -12,5 +12,6 @@ #include "soc_and_ip_translator.h" void dcn42_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator); +void dcn42_get_soc_bb(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config); #endif /* _DCN42_SOC_AND_IP_TRANSLATOR_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c index 0fc0e5a6c171c..bc1487d4ebda8 100644 --- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c +++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/soc_and_ip_translator.c @@ -4,6 +4,7 @@ #include "soc_and_ip_translator.h" #include "soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.h" +#include "soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.h" static void dc_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc_and_ip_translator, enum dce_version dc_version) @@ -12,6 +13,9 @@ static void dc_construct_soc_and_ip_translator(struct soc_and_ip_translator *soc case DCN_VERSION_4_01: dcn401_construct_soc_and_ip_translator(soc_and_ip_translator); break; + case DCN_VERSION_4_2: + dcn42_construct_soc_and_ip_translator(soc_and_ip_translator); + break; default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c index 7a839984dbc00..d8aebaff7c3fb 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c @@ -7,7 +7,7 @@ #include "dc_spl_isharp_filters.h" #include "spl_debug.h" -#define IDENTITY_RATIO(ratio) (spl_fixpt_u3d19(ratio) == (1 << 19)) +#define IDENTITY_RATIO(ratio) (SPL_NAMESPACE(spl_fixpt_u3d19(ratio)) == (1 << 19)) #define MIN_VIEWPORT_SIZE 12 static bool spl_is_yuv420(enum spl_pixel_format format) @@ -161,22 +161,24 @@ static struct spl_rect calculate_plane_rec_in_timing_active( struct spl_fixed31_32 temp; - temp = spl_fixpt_from_fraction(rec_in->x * (long long)stream_dst->width, - stream_src->width); + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( + rec_in->x * (long long)stream_dst->width, + stream_src->width)); rec_out.x = stream_dst->x + spl_fixpt_round(temp); - temp = spl_fixpt_from_fraction( + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( (rec_in->x + rec_in->width) * (long long)stream_dst->width, - stream_src->width); + stream_src->width)); rec_out.width = stream_dst->x + spl_fixpt_round(temp) - rec_out.x; - temp = spl_fixpt_from_fraction(rec_in->y * (long long)stream_dst->height, - stream_src->height); + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( + rec_in->y * (long long)stream_dst->height, + stream_src->height)); rec_out.y = stream_dst->y + spl_fixpt_round(temp); - temp = spl_fixpt_from_fraction( + temp = SPL_NAMESPACE(spl_fixpt_from_fraction( (rec_in->y + rec_in->height) * (long long)stream_dst->height, - stream_src->height); + stream_src->height)); rec_out.height = stream_dst->y + spl_fixpt_round(temp) - rec_out.y; return rec_out; @@ -224,7 +226,8 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( /* extra pixels in the division remainder need to go to pipes after * the extra pixel index minus one(epimo) defined here as: */ - if (mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) { + if ((use_recout_width_aligned == false) && + mpc_slice_idx > epimo && spl_in->basic_in.custom_width == 0) { mpc_rec.x += mpc_slice_idx - epimo - 1; mpc_rec.width += 1; } @@ -442,12 +445,12 @@ static void spl_calculate_scaling_ratios(struct spl_in *spl_in, spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) spl_swap(surf_src.height, surf_src.width); - spl_scratch->scl_data.ratios.horz = spl_fixpt_from_fraction( + spl_scratch->scl_data.ratios.horz = SPL_NAMESPACE(spl_fixpt_from_fraction( surf_src.width, - spl_in->basic_in.dst_rect.width); - spl_scratch->scl_data.ratios.vert = spl_fixpt_from_fraction( + spl_in->basic_in.dst_rect.width)); + spl_scratch->scl_data.ratios.vert = SPL_NAMESPACE(spl_fixpt_from_fraction( surf_src.height, - spl_in->basic_in.dst_rect.height); + spl_in->basic_in.dst_rect.height)); if (spl_in->basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE) spl_scratch->scl_data.ratios.horz.value *= 2; @@ -480,14 +483,14 @@ static void spl_calculate_scaling_ratios(struct spl_in *spl_in, * that is output/input. Currently we calculate input/output * Store 1/ratio in recip_ratio for those lookups */ - spl_scratch->scl_data.recip_ratios.horz = spl_fixpt_recip( - spl_scratch->scl_data.ratios.horz); - spl_scratch->scl_data.recip_ratios.vert = spl_fixpt_recip( - spl_scratch->scl_data.ratios.vert); - spl_scratch->scl_data.recip_ratios.horz_c = spl_fixpt_recip( - spl_scratch->scl_data.ratios.horz_c); - spl_scratch->scl_data.recip_ratios.vert_c = spl_fixpt_recip( - spl_scratch->scl_data.ratios.vert_c); + spl_scratch->scl_data.recip_ratios.horz = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.horz)); + spl_scratch->scl_data.recip_ratios.vert = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.vert)); + spl_scratch->scl_data.recip_ratios.horz_c = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.horz_c)); + spl_scratch->scl_data.recip_ratios.vert_c = SPL_NAMESPACE(spl_fixpt_recip( + spl_scratch->scl_data.ratios.vert_c)); } /* Calculate Viewport size */ @@ -646,11 +649,11 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, switch (spl_in->basic_in.cositing) { case CHROMA_COSITING_TOPLEFT: - init_adj_h = spl_fixpt_from_fraction(h_sign, 4); - init_adj_v = spl_fixpt_from_fraction(v_sign, 4); + init_adj_h = SPL_NAMESPACE(spl_fixpt_from_fraction(h_sign, 4)); + init_adj_v = SPL_NAMESPACE(spl_fixpt_from_fraction(v_sign, 4)); break; case CHROMA_COSITING_LEFT: - init_adj_h = spl_fixpt_from_fraction(h_sign, 4); + init_adj_h = SPL_NAMESPACE(spl_fixpt_from_fraction(h_sign, 4)); init_adj_v = spl_fixpt_zero; break; case CHROMA_COSITING_NONE: @@ -939,16 +942,16 @@ static void spl_get_taps_non_adaptive_scaler( * Max downscale supported is 6.0x. Add ASSERT to catch if go beyond that */ check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.horz, - spl_fixpt_from_fraction(6, 1)); + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); SPL_ASSERT(check_max_downscale); check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.vert, - spl_fixpt_from_fraction(6, 1)); + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); SPL_ASSERT(check_max_downscale); check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.horz_c, - spl_fixpt_from_fraction(6, 1)); + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); SPL_ASSERT(check_max_downscale); check_max_downscale = spl_fixpt_le(spl_scratch->scl_data.ratios.vert_c, - spl_fixpt_from_fraction(6, 1)); + SPL_NAMESPACE(spl_fixpt_from_fraction(6, 1))); SPL_ASSERT(check_max_downscale); @@ -1194,35 +1197,39 @@ static void spl_set_manual_ratio_init_data(struct dscl_prog_data *dscl_prog_data { struct spl_fixed31_32 bot; - dscl_prog_data->ratios.h_scale_ratio = spl_fixpt_u3d19(scl_data->ratios.horz) << 5; - dscl_prog_data->ratios.v_scale_ratio = spl_fixpt_u3d19(scl_data->ratios.vert) << 5; - dscl_prog_data->ratios.h_scale_ratio_c = spl_fixpt_u3d19(scl_data->ratios.horz_c) << 5; - dscl_prog_data->ratios.v_scale_ratio_c = spl_fixpt_u3d19(scl_data->ratios.vert_c) << 5; + dscl_prog_data->ratios.h_scale_ratio = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.horz)) << 5; + dscl_prog_data->ratios.v_scale_ratio = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.vert)) << 5; + dscl_prog_data->ratios.h_scale_ratio_c = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.horz_c)) << 5; + dscl_prog_data->ratios.v_scale_ratio_c = SPL_NAMESPACE(spl_fixpt_u3d19( + scl_data->ratios.vert_c)) << 5; /* * 0.24 format for fraction, first five bits zeroed */ dscl_prog_data->init.h_filter_init_frac = - spl_fixpt_u0d19(scl_data->inits.h) << 5; + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.h)) << 5; dscl_prog_data->init.h_filter_init_int = spl_fixpt_floor(scl_data->inits.h); dscl_prog_data->init.h_filter_init_frac_c = - spl_fixpt_u0d19(scl_data->inits.h_c) << 5; + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.h_c)) << 5; dscl_prog_data->init.h_filter_init_int_c = spl_fixpt_floor(scl_data->inits.h_c); dscl_prog_data->init.v_filter_init_frac = - spl_fixpt_u0d19(scl_data->inits.v) << 5; + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.v)) << 5; dscl_prog_data->init.v_filter_init_int = spl_fixpt_floor(scl_data->inits.v); dscl_prog_data->init.v_filter_init_frac_c = - spl_fixpt_u0d19(scl_data->inits.v_c) << 5; + SPL_NAMESPACE(spl_fixpt_u0d19(scl_data->inits.v_c)) << 5; dscl_prog_data->init.v_filter_init_int_c = spl_fixpt_floor(scl_data->inits.v_c); bot = spl_fixpt_add(scl_data->inits.v, scl_data->ratios.vert); - dscl_prog_data->init.v_filter_init_bot_frac = spl_fixpt_u0d19(bot) << 5; + dscl_prog_data->init.v_filter_init_bot_frac = SPL_NAMESPACE(spl_fixpt_u0d19(bot)) << 5; dscl_prog_data->init.v_filter_init_bot_int = spl_fixpt_floor(bot); bot = spl_fixpt_add(scl_data->inits.v_c, scl_data->ratios.vert_c); - dscl_prog_data->init.v_filter_init_bot_frac_c = spl_fixpt_u0d19(bot) << 5; + dscl_prog_data->init.v_filter_init_bot_frac_c = SPL_NAMESPACE(spl_fixpt_u0d19(bot)) << 5; dscl_prog_data->init.v_filter_init_bot_int_c = spl_fixpt_floor(bot); } @@ -1270,7 +1277,7 @@ static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *sp // Set viewport_c dscl_prog_data->viewport_c = spl_scratch->scl_data.viewport_c; // Set filters data - spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h); + SPL_NAMESPACE(spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h)); } /* Calculate C0-C3 coefficients based on HDR_mult */ @@ -1286,28 +1293,31 @@ static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint3 else hdr_multx100_int = 100; /* default for 80 nits otherwise */ - hdr_mult = spl_fixpt_from_fraction((long long)hdr_multx100_int, 100LL); - c0_mult = spl_fixpt_from_fraction(2126LL, 10000LL); - c1_mult = spl_fixpt_from_fraction(7152LL, 10000LL); - c2_mult = spl_fixpt_from_fraction(722LL, 10000LL); + hdr_mult = SPL_NAMESPACE(spl_fixpt_from_fraction((long long)hdr_multx100_int, 100LL)); + c0_mult = SPL_NAMESPACE(spl_fixpt_from_fraction(2126LL, 10000LL)); + c1_mult = SPL_NAMESPACE(spl_fixpt_from_fraction(7152LL, 10000LL)); + c2_mult = SPL_NAMESPACE(spl_fixpt_from_fraction(722LL, 10000LL)); - c0_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c0_mult, spl_fixpt_from_fraction( - 16384LL, 125LL))); - c1_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c1_mult, spl_fixpt_from_fraction( - 16384LL, 125LL))); - c2_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c2_mult, spl_fixpt_from_fraction( - 16384LL, 125LL))); + c0_calc = SPL_NAMESPACE(spl_fixpt_mul(hdr_mult, SPL_NAMESPACE(spl_fixpt_mul(c0_mult, + SPL_NAMESPACE(spl_fixpt_from_fraction(16384LL, 125LL)))))); + c1_calc = SPL_NAMESPACE(spl_fixpt_mul(hdr_mult, SPL_NAMESPACE(spl_fixpt_mul(c1_mult, + SPL_NAMESPACE(spl_fixpt_from_fraction(16384LL, 125LL)))))); + c2_calc = SPL_NAMESPACE(spl_fixpt_mul(hdr_mult, SPL_NAMESPACE(spl_fixpt_mul(c2_mult, + SPL_NAMESPACE(spl_fixpt_from_fraction(16384LL, 125LL)))))); fmt.exponenta_bits = 5; fmt.mantissa_bits = 10; fmt.sign = true; // fp1.5.10, C0 coefficient (LN_rec709: HDR_MULT * 0.212600 * 2^14/125) - spl_convert_to_custom_float_format(c0_calc, &fmt, &dscl_prog_data->easf_matrix_c0); + SPL_NAMESPACE(spl_convert_to_custom_float_format(c0_calc, &fmt, + &dscl_prog_data->easf_matrix_c0)); // fp1.5.10, C1 coefficient (LN_rec709: HDR_MULT * 0.715200 * 2^14/125) - spl_convert_to_custom_float_format(c1_calc, &fmt, &dscl_prog_data->easf_matrix_c1); + SPL_NAMESPACE(spl_convert_to_custom_float_format(c1_calc, &fmt, + &dscl_prog_data->easf_matrix_c1)); // fp1.5.10, C2 coefficient (LN_rec709: HDR_MULT * 0.072200 * 2^14/125) - spl_convert_to_custom_float_format(c2_calc, &fmt, &dscl_prog_data->easf_matrix_c2); + SPL_NAMESPACE(spl_convert_to_custom_float_format(c2_calc, &fmt, + &dscl_prog_data->easf_matrix_c2)); dscl_prog_data->easf_matrix_c3 = 0x0; // fp1.5.10, C3 coefficient } @@ -1325,48 +1335,48 @@ static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *s dscl_prog_data->easf_v_bf1_en = 1; // 1-bit, BF1 calculation enable, 0=disable, 1=enable dscl_prog_data->easf_v_bf2_mode = 0xF; // 4-bit, BF2 calculation mode /* 2-bit, BF3 chroma mode correction calculation mode */ - dscl_prog_data->easf_v_bf3_mode = spl_get_v_bf3_mode( - spl_scratch->scl_data.recip_ratios.vert); + dscl_prog_data->easf_v_bf3_mode = SPL_NAMESPACE(spl_get_v_bf3_mode( + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10 [ minCoef ]*/ dscl_prog_data->easf_v_ringest_3tap_dntilt_uptilt = - spl_get_3tap_dntilt_uptilt_offset(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_3tap_dntilt_uptilt_offset(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10 [ upTiltMaxVal ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt_max = - spl_get_3tap_uptilt_maxval(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_3tap_uptilt_maxval(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10 [ dnTiltSlope ]*/ dscl_prog_data->easf_v_ringest_3tap_dntilt_slope = - spl_get_3tap_dntilt_slope(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_3tap_dntilt_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10 [ upTilt1Slope ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt1_slope = - spl_get_3tap_uptilt1_slope(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_3tap_uptilt1_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10 [ upTilt2Slope ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt2_slope = - spl_get_3tap_uptilt2_slope(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_3tap_uptilt2_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10 [ upTilt2Offset ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt2_offset = - spl_get_3tap_uptilt2_offset(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_3tap_uptilt2_offset(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */ dscl_prog_data->easf_v_ringest_eventap_reduceg1 = - spl_get_reducer_gain4(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_reducer_gain4(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */ dscl_prog_data->easf_v_ringest_eventap_reduceg2 = - spl_get_reducer_gain6(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_reducer_gain6(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */ dscl_prog_data->easf_v_ringest_eventap_gain1 = - spl_get_gainRing4(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_gainRing4(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); /* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */ dscl_prog_data->easf_v_ringest_eventap_gain2 = - spl_get_gainRing6(spl_scratch->scl_data.taps.v_taps, - spl_scratch->scl_data.recip_ratios.vert); + SPL_NAMESPACE(spl_get_gainRing6(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert)); dscl_prog_data->easf_v_bf_maxa = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 0 dscl_prog_data->easf_v_bf_maxb = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 1 dscl_prog_data->easf_v_bf_mina = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 0 @@ -1491,24 +1501,24 @@ static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *s dscl_prog_data->easf_h_bf2_mode = 0xF; // 4-bit, BF2 calculation mode /* 2-bit, BF3 chroma mode correction calculation mode */ - dscl_prog_data->easf_h_bf3_mode = spl_get_h_bf3_mode( - spl_scratch->scl_data.recip_ratios.horz); + dscl_prog_data->easf_h_bf3_mode = SPL_NAMESPACE(spl_get_h_bf3_mode( + spl_scratch->scl_data.recip_ratios.horz)); /* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */ dscl_prog_data->easf_h_ringest_eventap_reduceg1 = - spl_get_reducer_gain4(spl_scratch->scl_data.taps.h_taps, - spl_scratch->scl_data.recip_ratios.horz); + SPL_NAMESPACE(spl_get_reducer_gain4(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); /* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */ dscl_prog_data->easf_h_ringest_eventap_reduceg2 = - spl_get_reducer_gain6(spl_scratch->scl_data.taps.h_taps, - spl_scratch->scl_data.recip_ratios.horz); + SPL_NAMESPACE(spl_get_reducer_gain6(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); /* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */ dscl_prog_data->easf_h_ringest_eventap_gain1 = - spl_get_gainRing4(spl_scratch->scl_data.taps.h_taps, - spl_scratch->scl_data.recip_ratios.horz); + SPL_NAMESPACE(spl_get_gainRing4(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); /* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */ dscl_prog_data->easf_h_ringest_eventap_gain2 = - spl_get_gainRing6(spl_scratch->scl_data.taps.h_taps, - spl_scratch->scl_data.recip_ratios.horz); + SPL_NAMESPACE(spl_get_gainRing6(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz)); dscl_prog_data->easf_h_bf_maxa = 63; //Horz Max BF value A in U0.6 format.Selected if H_FCNTL==0 dscl_prog_data->easf_h_bf_maxb = 63; //Horz Max BF value B in U0.6 format.Selected if H_FCNTL==1 dscl_prog_data->easf_h_bf_mina = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==0 @@ -1689,9 +1699,9 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, return; } - spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness, - scale_to_sharpness_policy); - memcpy(dscl_prog_data->isharp_delta, spl_get_pregen_filter_isharp_1D_lut(setup), + SPL_NAMESPACE(spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness, + scale_to_sharpness_policy)); + memcpy(dscl_prog_data->isharp_delta, SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(setup)), sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; @@ -1810,7 +1820,7 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, } // Set the values as per lookup table - spl_set_blur_scale_data(dscl_prog_data, data); + SPL_NAMESPACE(spl_set_blur_scale_data(dscl_prog_data, data)); } /* Calculate recout, scaling ratio, and viewport, then get optimal number of taps */ @@ -1922,4 +1932,3 @@ bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_out spl_set_taps_data(dscl_prog_data, data); return res; } - diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h index d621c42a237ee..f9503c368db52 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl.h @@ -9,14 +9,6 @@ #define BLACK_OFFSET_RGB_Y 0x0 #define BLACK_OFFSET_CBCR 0x8000 -#ifndef SPL_PFX_ -#define SPL_PFX_ -#endif - -#define SPL_EXPAND2(a, b) a##b -#define SPL_EXPAND(a, b) SPL_EXPAND2(a, b) -#define SPL_NAMESPACE(symbol) SPL_EXPAND(SPL_PFX_, symbol) - /* SPL interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c index 99238644e0a11..088aba3c00a1d 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.c @@ -4,8 +4,8 @@ #include "dc_spl_filters.h" -void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, - uint16_t *s1_12_filter, int num_taps) +void SPL_NAMESPACE(convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, + uint16_t *s1_12_filter, int num_taps)) { int num_entries = NUM_PHASES_COEFF * num_taps; int i; diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h index 20439cdbdb105..f3ee51c42bf29 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_filters.h @@ -9,7 +9,7 @@ #define NUM_PHASES_COEFF 33 -void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, - uint16_t *s1_12_filter, int num_taps); +void SPL_NAMESPACE(convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, + uint16_t *s1_12_filter, int num_taps)); #endif /* __DC_SPL_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c index 12acdd34e6a6e..a75ab23b0726a 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c @@ -293,7 +293,7 @@ static const uint16_t filter_isharp_bs_3tap_64p_s1_12[99] = { }; /* Pre-generated 1DLUT for given setup and sharpness level */ -struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { +static struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { { 0, 0, { @@ -332,7 +332,7 @@ struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = }, }; -struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = { +static struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = { {1125, 1000, 0}, {11, 10, 1}, {1075, 1000, 2}, @@ -367,8 +367,8 @@ static unsigned int spl_calculate_sharpness_level_adj(struct spl_fixed31_32 rati sharpness_level_down_adj = 0; lookup_ptr = sharpness_level_adj; while (j < NUM_SHARPNESS_ADJ_LEVELS) { - ratio_level = spl_fixpt_from_fraction(lookup_ptr->ratio_numer, - lookup_ptr->ratio_denom); + ratio_level = SPL_NAMESPACE(spl_fixpt_from_fraction(lookup_ptr->ratio_numer, + lookup_ptr->ratio_denom)); if (ratio.value >= ratio_level.value) { sharpness_level_down_adj = lookup_ptr->level_down_adj; break; @@ -447,8 +447,9 @@ static unsigned int spl_calculate_sharpness_level(struct spl_fixed31_32 ratio, return sharpness_level; } -void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, - struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy) +void SPL_NAMESPACE(spl_build_isharp_1dlut_from_reference_curve( + struct spl_fixed31_32 ratio, enum system_setup setup, + struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy)) { uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst; struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level; @@ -461,7 +462,7 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en unsigned int sharpnessX1000 = spl_calculate_sharpness_level(ratio, sharpness.sharpness_level, setup, sharpness.sharpness_range, scale_to_sharpness_policy); - sharp_level = spl_fixpt_from_fraction(sharpnessX1000, 1000); + sharp_level = SPL_NAMESPACE(spl_fixpt_from_fraction(sharpnessX1000, 1000)); /* * Check if pregen 1dlut table is already precalculated @@ -486,10 +487,11 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en memset(byte_ptr_1dlut_dst, 0, size_1dlut); for (j = 0; j < size_1dlut; j++) { sharp_base = spl_fixpt_from_int((int)*byte_ptr_1dlut_src); - sharp_calc = spl_fixpt_mul(sharp_base, sharp_level); + sharp_calc = SPL_NAMESPACE(spl_fixpt_mul(sharp_base, sharp_level)); sharp_calc = spl_fixpt_div(sharp_calc, spl_fixpt_from_int(3)); sharp_calc = spl_fixpt_min(spl_fixpt_from_int(255), sharp_calc); - sharp_calc = spl_fixpt_add(sharp_calc, spl_fixpt_from_fraction(1, 2)); + sharp_calc = spl_fixpt_add(sharp_calc, + SPL_NAMESPACE(spl_fixpt_from_fraction(1, 2))); sharp_calc_int = spl_fixpt_floor(sharp_calc); /* Clamp it at 0x7F so it doesn't wrap */ if (sharp_calc_int > 127) @@ -506,12 +508,12 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en filter_isharp_1D_lut_pregen[setup].sharpness_denom = 1000; } -uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup) +uint32_t *SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup)) { return filter_isharp_1D_lut_pregen[setup].value; } -const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps) +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(int taps)) { if (taps == 3) return filter_isharp_bs_3tap_64p_s1_12; @@ -526,7 +528,7 @@ const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps) } } -const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps) +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps)) { if (taps == 3) return filter_isharp_bs_3tap_64p; @@ -541,13 +543,12 @@ const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps) } } -void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, - const struct spl_scaler_data *data) +void SPL_NAMESPACE(spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data)) { dscl_prog_data->filter_blur_scale_h = - spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps); + SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps)); dscl_prog_data->filter_blur_scale_v = - spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps); + SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps)); } - diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h index f5e3d3ecc9132..d4082d4969e4b 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h @@ -28,15 +28,17 @@ enum system_setup { NUM_SHARPNESS_SETUPS }; -void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, - const struct spl_scaler_data *data); +void SPL_NAMESPACE(spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data)); -void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, - struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy); -uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup); +void SPL_NAMESPACE(spl_build_isharp_1dlut_from_reference_curve( + struct spl_fixed31_32 ratio, enum system_setup setup, + struct adaptive_sharpness sharpness, + enum scale_to_sharpness_policy scale_to_sharpness_policy)); +uint32_t *SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup)); // public API -const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps); -const uint16_t *spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p(int taps)); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_blur_scale_coeffs_64p_s1_10(int taps)); #endif /* __DC_SPL_ISHARP_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c index 0d1bd81ff04a1..de16ee5860738 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c @@ -2194,19 +2194,19 @@ static struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_offset_lookup[] static const uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) return easf_filter_3tap_64p_ratio_0_30_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) return easf_filter_3tap_64p_ratio_0_40_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) return easf_filter_3tap_64p_ratio_0_50_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) return easf_filter_3tap_64p_ratio_0_60_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) return easf_filter_3tap_64p_ratio_0_70_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) return easf_filter_3tap_64p_ratio_0_80_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) return easf_filter_3tap_64p_ratio_0_90_s1_12; else return easf_filter_3tap_64p_ratio_1_00_s1_12; @@ -2214,19 +2214,19 @@ static const uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio) static const uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) return easf_filter_4tap_64p_ratio_0_30_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) return easf_filter_4tap_64p_ratio_0_40_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) return easf_filter_4tap_64p_ratio_0_50_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) return easf_filter_4tap_64p_ratio_0_60_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) return easf_filter_4tap_64p_ratio_0_70_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) return easf_filter_4tap_64p_ratio_0_80_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) return easf_filter_4tap_64p_ratio_0_90_s1_12; else return easf_filter_4tap_64p_ratio_1_00_s1_12; @@ -2234,25 +2234,26 @@ static const uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio) static const uint16_t *spl_get_easf_filter_6tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) return easf_filter_6tap_64p_ratio_0_30_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) return easf_filter_6tap_64p_ratio_0_40_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) return easf_filter_6tap_64p_ratio_0_50_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) return easf_filter_6tap_64p_ratio_0_60_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) return easf_filter_6tap_64p_ratio_0_70_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) return easf_filter_6tap_64p_ratio_0_80_s1_12; - else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) return easf_filter_6tap_64p_ratio_0_90_s1_12; else return easf_filter_6tap_64p_ratio_1_00_s1_12; } -const uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio) +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)) { if (taps == 6) return spl_get_easf_filter_6tap_64p(ratio); @@ -2269,19 +2270,19 @@ const uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31 static const uint16_t *spl_get_easf_filter_3tap_64p_s1_10(struct spl_fixed31_32 ratio) { - if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) return easf_filter_3tap_64p_ratio_0_30; - else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) return easf_filter_3tap_64p_ratio_0_40; - else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) return easf_filter_3tap_64p_ratio_0_50; - else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) return easf_filter_3tap_64p_ratio_0_60; - else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) return easf_filter_3tap_64p_ratio_0_70; - else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) return easf_filter_3tap_64p_ratio_0_80; - else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) return easf_filter_3tap_64p_ratio_0_90; else return easf_filter_3tap_64p_ratio_1_00; @@ -2289,19 +2290,19 @@ static const uint16_t *spl_get_easf_filter_3tap_64p_s1_10(struct spl_fixed31_32 static const uint16_t *spl_get_easf_filter_4tap_64p_s1_10(struct spl_fixed31_32 ratio) { - if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) return easf_filter_4tap_64p_ratio_0_30; - else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) return easf_filter_4tap_64p_ratio_0_40; - else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) return easf_filter_4tap_64p_ratio_0_50; - else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) return easf_filter_4tap_64p_ratio_0_60; - else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) return easf_filter_4tap_64p_ratio_0_70; - else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) return easf_filter_4tap_64p_ratio_0_80; - else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) return easf_filter_4tap_64p_ratio_0_90; else return easf_filter_4tap_64p_ratio_1_00; @@ -2309,25 +2310,26 @@ static const uint16_t *spl_get_easf_filter_4tap_64p_s1_10(struct spl_fixed31_32 static const uint16_t *spl_get_easf_filter_6tap_64p_s1_10(struct spl_fixed31_32 ratio) { - if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(3, 10)).value) return easf_filter_6tap_64p_ratio_0_30; - else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 10)).value) return easf_filter_6tap_64p_ratio_0_40; - else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 10)).value) return easf_filter_6tap_64p_ratio_0_50; - else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(6, 10)).value) return easf_filter_6tap_64p_ratio_0_60; - else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(7, 10)).value) return easf_filter_6tap_64p_ratio_0_70; - else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(8, 10)).value) return easf_filter_6tap_64p_ratio_0_80; - else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(9, 10)).value) return easf_filter_6tap_64p_ratio_0_90; else return easf_filter_6tap_64p_ratio_1_00; } -const uint16_t *spl_dscl_get_easf_filter_coeffs_64p_s1_10(int taps, struct spl_fixed31_32 ratio) +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p_s1_10( + int taps, struct spl_fixed31_32 ratio)) { if (taps == 6) return spl_get_easf_filter_6tap_64p_s1_10(ratio); @@ -2342,39 +2344,39 @@ const uint16_t *spl_dscl_get_easf_filter_coeffs_64p_s1_10(int taps, struct spl_f } } -void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, +void SPL_NAMESPACE(spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, const struct spl_scaler_data *data, bool enable_easf_v, - bool enable_easf_h) + bool enable_easf_h)) { /* * Old coefficients calculated scaling ratio = input / output * New coefficients are calculated based on = output / input */ if (enable_easf_h) { - dscl_prog_data->filter_h = spl_dscl_get_easf_filter_coeffs_64p( - data->taps.h_taps, data->recip_ratios.horz); + dscl_prog_data->filter_h = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.h_taps, data->recip_ratios.horz)); - dscl_prog_data->filter_h_c = spl_dscl_get_easf_filter_coeffs_64p( - data->taps.h_taps_c, data->recip_ratios.horz_c); + dscl_prog_data->filter_h_c = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.h_taps_c, data->recip_ratios.horz_c)); } else { - dscl_prog_data->filter_h = spl_dscl_get_filter_coeffs_64p( - data->taps.h_taps, data->ratios.horz); + dscl_prog_data->filter_h = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.h_taps, data->ratios.horz)); - dscl_prog_data->filter_h_c = spl_dscl_get_filter_coeffs_64p( - data->taps.h_taps_c, data->ratios.horz_c); + dscl_prog_data->filter_h_c = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.h_taps_c, data->ratios.horz_c)); } if (enable_easf_v) { - dscl_prog_data->filter_v = spl_dscl_get_easf_filter_coeffs_64p( - data->taps.v_taps, data->recip_ratios.vert); + dscl_prog_data->filter_v = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.v_taps, data->recip_ratios.vert)); - dscl_prog_data->filter_v_c = spl_dscl_get_easf_filter_coeffs_64p( - data->taps.v_taps_c, data->recip_ratios.vert_c); + dscl_prog_data->filter_v_c = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + data->taps.v_taps_c, data->recip_ratios.vert_c)); } else { - dscl_prog_data->filter_v = spl_dscl_get_filter_coeffs_64p( - data->taps.v_taps, data->ratios.vert); + dscl_prog_data->filter_v = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.v_taps, data->ratios.vert)); - dscl_prog_data->filter_v_c = spl_dscl_get_filter_coeffs_64p( - data->taps.v_taps_c, data->ratios.vert_c); + dscl_prog_data->filter_v_c = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + data->taps.v_taps_c, data->ratios.vert_c)); } } @@ -2395,9 +2397,9 @@ static uint32_t spl_easf_get_scale_ratio_to_reg_value(struct spl_fixed31_32 rati if (lookup_table_index_ptr->numer < 0) break; - if (ratio.value < spl_fixpt_from_fraction( + if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction( lookup_table_index_ptr->numer, - lookup_table_index_ptr->denom).value) { + lookup_table_index_ptr->denom)).value) { value = lookup_table_index_ptr->reg_value; break; } @@ -2406,7 +2408,7 @@ static uint32_t spl_easf_get_scale_ratio_to_reg_value(struct spl_fixed31_32 rati } return value; } -uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_v_bf3_mode(struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries = sizeof(easf_v_bf3_mode_lookup) / @@ -2415,7 +2417,7 @@ uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio) easf_v_bf3_mode_lookup, num_entries); return value; } -uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_h_bf3_mode(struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries = sizeof(easf_h_bf3_mode_lookup) / @@ -2424,7 +2426,7 @@ uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio) easf_h_bf3_mode_lookup, num_entries); return value; } -uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2443,7 +2445,7 @@ uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2462,7 +2464,7 @@ uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2481,7 +2483,7 @@ uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2500,7 +2502,8 @@ uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_uptilt_offset( + int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2514,7 +2517,7 @@ uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio value = 0; return value; } -uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2528,7 +2531,7 @@ uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2542,7 +2545,7 @@ uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2556,7 +2559,7 @@ uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; @@ -2570,7 +2573,7 @@ uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio) value = 0; return value; } -uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio) +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio)) { uint32_t value; unsigned int num_entries; diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h index 321ae22a04d4c..ba1cdb8be4172 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h @@ -13,25 +13,28 @@ struct scale_ratio_to_reg_value_lookup { const uint32_t reg_value; }; -void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, +void SPL_NAMESPACE(spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, const struct spl_scaler_data *data, bool enable_easf_v, - bool enable_easf_h); - -uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio); -uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio); -uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio); -uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio); + bool enable_easf_h)); + +uint32_t SPL_NAMESPACE(spl_get_v_bf3_mode(struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_h_bf3_mode(struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_uptilt_offset( + int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio)); +uint32_t SPL_NAMESPACE(spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio)); /* public API */ -const uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio); -const uint16_t *spl_dscl_get_easf_filter_coeffs_64p_s1_10(int taps, struct spl_fixed31_32 ratio); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p_s1_10( + int taps, struct spl_fixed31_32 ratio)); #endif /* __DC_SPL_SCL_EASF_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c index 5e52bdf1ad445..2d73d0dce5ffd 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.c @@ -1134,9 +1134,9 @@ static const uint16_t *spl_get_filter_3tap_64p(struct spl_fixed31_32 ratio) { if (ratio.value < spl_fixpt_one.value) return filter_3tap_64p_upscale; - else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) return filter_3tap_64p_116; - else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) return filter_3tap_64p_149; else return filter_3tap_64p_183; @@ -1146,9 +1146,9 @@ static const uint16_t *spl_get_filter_4tap_64p(struct spl_fixed31_32 ratio) { if (ratio.value < spl_fixpt_one.value) return filter_4tap_64p_upscale; - else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) return filter_4tap_64p_116; - else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) return filter_4tap_64p_149; else return filter_4tap_64p_183; @@ -1158,9 +1158,9 @@ static const uint16_t *spl_get_filter_5tap_64p(struct spl_fixed31_32 ratio) { if (ratio.value < spl_fixpt_one.value) return filter_5tap_64p_upscale; - else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) return filter_5tap_64p_116; - else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) return filter_5tap_64p_149; else return filter_5tap_64p_183; @@ -1170,9 +1170,9 @@ static const uint16_t *spl_get_filter_6tap_64p(struct spl_fixed31_32 ratio) { if (ratio.value < spl_fixpt_one.value) return filter_6tap_64p_upscale; - else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) return filter_6tap_64p_116; - else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) return filter_6tap_64p_149; else return filter_6tap_64p_183; @@ -1182,9 +1182,9 @@ static const uint16_t *spl_get_filter_7tap_64p(struct spl_fixed31_32 ratio) { if (ratio.value < spl_fixpt_one.value) return filter_7tap_64p_upscale; - else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) return filter_7tap_64p_116; - else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) return filter_7tap_64p_149; else return filter_7tap_64p_183; @@ -1194,9 +1194,9 @@ static const uint16_t *spl_get_filter_8tap_64p(struct spl_fixed31_32 ratio) { if (ratio.value < spl_fixpt_one.value) return filter_8tap_64p_upscale; - else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(4, 3)).value) return filter_8tap_64p_116; - else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) + else if (ratio.value < SPL_NAMESPACE(spl_fixpt_from_fraction(5, 3)).value) return filter_8tap_64p_149; else return filter_8tap_64p_183; @@ -1207,7 +1207,8 @@ static const uint16_t *spl_get_filter_2tap_64p(void) return filter_2tap_64p; } -const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio) +const uint16_t *SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)) { if (taps == 8) return spl_get_filter_8tap_64p(ratio); diff --git a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h index c315a438d0645..445d626863c2e 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_filters.h @@ -8,6 +8,7 @@ #include "dc_spl_types.h" /* public API */ -const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio); +const uint16_t *SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p( + int taps, struct spl_fixed31_32 ratio)); #endif /* __DC_SPL_SCL_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c b/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c index be2f34d034c5c..0700b3dbbda76 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.c @@ -14,8 +14,8 @@ static bool spl_build_custom_float(struct spl_fixed31_32 value, uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; const struct spl_fixed31_32 mantissa_constant_plus_max_fraction = - spl_fixpt_from_fraction((1LL << (format->mantissa_bits + 1)) - 1, - 1LL << format->mantissa_bits); + SPL_NAMESPACE(spl_fixpt_from_fraction((1LL << (format->mantissa_bits + 1)) - 1, + 1LL << format->mantissa_bits)); struct spl_fixed31_32 mantiss; @@ -134,9 +134,10 @@ static bool spl_setup_custom_float(const struct spl_custom_float_format *format, return true; } -bool spl_convert_to_custom_float_format(struct spl_fixed31_32 value, - const struct spl_custom_float_format *format, - uint32_t *result) +bool SPL_NAMESPACE(spl_convert_to_custom_float_format( + struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + uint32_t *result)) { uint32_t mantissa; uint32_t exponenta; diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h index cdc4e107b9de4..f3fd8d30e6380 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/spl_custom_float.h @@ -21,9 +21,9 @@ struct spl_custom_float_value { bool negative; }; -bool spl_convert_to_custom_float_format( +bool SPL_NAMESPACE(spl_convert_to_custom_float_format( struct spl_fixed31_32 value, const struct spl_custom_float_format *format, - uint32_t *result); + uint32_t *result)); #endif //SPL_CUSTOM_FLOAT_H_ diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c index ebf0287417e0e..ff0bdc3c33c80 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.c @@ -44,7 +44,8 @@ static inline unsigned long long spl_complete_integer_division_u64( #define GET_FRACTIONAL_PART(x) \ (FRACTIONAL_PART_MASK & (x)) -struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long denominator) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_fraction( + long long numerator, long long denominator)) { struct spl_fixed31_32 res; @@ -96,7 +97,8 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long den return res; } -struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_mul( + struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)) { struct spl_fixed31_32 res; @@ -147,7 +149,7 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed return res; } -struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sqr(struct spl_fixed31_32 arg)) { struct spl_fixed31_32 res; @@ -187,19 +189,19 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) return res; } -struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_recip(struct spl_fixed31_32 arg)) { /* * @note * Good idea to use Newton's method */ - return spl_fixpt_from_fraction( + return SPL_NAMESPACE(spl_fixpt_from_fraction( spl_fixpt_one.value, - arg.value); + arg.value)); } -struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sinc(struct spl_fixed31_32 arg)) { struct spl_fixed31_32 square; @@ -221,15 +223,15 @@ struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg) spl_fixpt_two_pi.value))); } - square = spl_fixpt_sqr(arg_norm); + square = SPL_NAMESPACE(spl_fixpt_sqr(arg_norm)); do { res = spl_fixpt_sub( spl_fixpt_one, spl_fixpt_div_int( - spl_fixpt_mul( + SPL_NAMESPACE(spl_fixpt_mul( square, - res), + res)), n * (n - 1))); n -= 2; @@ -237,24 +239,24 @@ struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg) if (arg.value != arg_norm.value) res = spl_fixpt_div( - spl_fixpt_mul(res, arg_norm), + SPL_NAMESPACE(spl_fixpt_mul(res, arg_norm)), arg); return res; } -struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sin(struct spl_fixed31_32 arg)) { - return spl_fixpt_mul( + return SPL_NAMESPACE(spl_fixpt_mul( arg, - spl_fixpt_sinc(arg)); + SPL_NAMESPACE(spl_fixpt_sinc(arg)))); } -struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_cos(struct spl_fixed31_32 arg)) { /* TODO implement argument normalization */ - const struct spl_fixed31_32 square = spl_fixpt_sqr(arg); + const struct spl_fixed31_32 square = SPL_NAMESPACE(spl_fixpt_sqr(arg)); struct spl_fixed31_32 res = spl_fixpt_one; @@ -264,9 +266,9 @@ struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg) res = spl_fixpt_sub( spl_fixpt_one, spl_fixpt_div_int( - spl_fixpt_mul( + SPL_NAMESPACE(spl_fixpt_mul( square, - res), + res)), n * (n - 1))); n -= 2; @@ -286,9 +288,9 @@ static struct spl_fixed31_32 spl_fixed31_32_exp_from_taylor_series(struct spl_fi { unsigned int n = 9; - struct spl_fixed31_32 res = spl_fixpt_from_fraction( + struct spl_fixed31_32 res = SPL_NAMESPACE(spl_fixpt_from_fraction( n + 2, - n + 1); + n + 1)); /* TODO find correct res */ SPL_ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); @@ -297,20 +299,20 @@ static struct spl_fixed31_32 spl_fixed31_32_exp_from_taylor_series(struct spl_fi res = spl_fixpt_add( spl_fixpt_one, spl_fixpt_div_int( - spl_fixpt_mul( + SPL_NAMESPACE(spl_fixpt_mul( arg, - res), + res)), n)); while (--n != 1); return spl_fixpt_add( spl_fixpt_one, - spl_fixpt_mul( + SPL_NAMESPACE(spl_fixpt_mul( arg, - res)); + res))); } -struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_exp(struct spl_fixed31_32 arg)) { /* * @brief @@ -353,7 +355,7 @@ struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg) return spl_fixpt_one; } -struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg) +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_log(struct spl_fixed31_32 arg)) { struct spl_fixed31_32 res = spl_fixpt_neg(spl_fixpt_one); /* TODO improve 1st estimation */ @@ -371,7 +373,7 @@ struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg) spl_fixpt_one), spl_fixpt_div( arg, - spl_fixpt_exp(res))); + SPL_NAMESPACE(spl_fixpt_exp(res)))); error = spl_fixpt_sub( res, @@ -427,37 +429,37 @@ static inline unsigned int spl_clamp_ux_dy( return min_clamp; } -unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg) +unsigned int SPL_NAMESPACE(spl_fixpt_u4d19(struct spl_fixed31_32 arg)) { return spl_ux_dy(arg.value, 4, 19); } -unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg) +unsigned int SPL_NAMESPACE(spl_fixpt_u3d19(struct spl_fixed31_32 arg)) { return spl_ux_dy(arg.value, 3, 19); } -unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg) +unsigned int SPL_NAMESPACE(spl_fixpt_u2d19(struct spl_fixed31_32 arg)) { return spl_ux_dy(arg.value, 2, 19); } -unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg) +unsigned int SPL_NAMESPACE(spl_fixpt_u0d19(struct spl_fixed31_32 arg)) { return spl_ux_dy(arg.value, 0, 19); } -unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg) +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg)) { return spl_clamp_ux_dy(arg.value, 0, 14, 1); } -unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg) +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg)) { return spl_clamp_ux_dy(arg.value, 0, 10, 1); } -int spl_fixpt_s4d19(struct spl_fixed31_32 arg) +int SPL_NAMESPACE(spl_fixpt_s4d19(struct spl_fixed31_32 arg)) { if (arg.value < 0) return -(int)spl_ux_dy(spl_fixpt_abs(arg).value, 4, 19); @@ -465,9 +467,9 @@ int spl_fixpt_s4d19(struct spl_fixed31_32 arg) return spl_ux_dy(arg.value, 4, 19); } -struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value, +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_ux_dy(unsigned int value, unsigned int integer_bits, - unsigned int fractional_bits) + unsigned int fractional_bits)) { struct spl_fixed31_32 fixpt_value = spl_fixpt_zero; struct spl_fixed31_32 fixpt_int_value = spl_fixpt_zero; @@ -481,10 +483,10 @@ struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value, return fixpt_value; } -struct spl_fixed31_32 spl_fixpt_from_int_dy(unsigned int int_value, +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_int_dy(unsigned int int_value, unsigned int frac_value, unsigned int integer_bits, - unsigned int fractional_bits) + unsigned int fractional_bits)) { struct spl_fixed31_32 fixpt_value = spl_fixpt_from_int(int_value); diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h index 9f349ffe91485..b0e639d6e97de 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/spl_fixpt31_32.h @@ -60,7 +60,8 @@ static const struct spl_fixed31_32 spl_fixpt_one = { 0x100000000LL }; * @brief * result = numerator / denominator */ -struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long denominator); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_fraction( + long long numerator, long long denominator)); /* * @brief @@ -280,7 +281,8 @@ static inline struct spl_fixed31_32 spl_fixpt_sub_int(struct spl_fixed31_32 arg1 * @brief * result = arg1 * arg2 */ -struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_mul( + struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2)); /* @@ -289,14 +291,14 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed */ static inline struct spl_fixed31_32 spl_fixpt_mul_int(struct spl_fixed31_32 arg1, int arg2) { - return spl_fixpt_mul(arg1, spl_fixpt_from_int(arg2)); + return SPL_NAMESPACE(spl_fixpt_mul(arg1, spl_fixpt_from_int(arg2))); } /* * @brief * result = square(arg) := arg * arg */ -struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sqr(struct spl_fixed31_32 arg)); /* * @brief @@ -304,7 +306,8 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg); */ static inline struct spl_fixed31_32 spl_fixpt_div_int(struct spl_fixed31_32 arg1, long long arg2) { - return spl_fixpt_from_fraction(arg1.value, spl_fixpt_from_int((int)arg2).value); + return SPL_NAMESPACE(spl_fixpt_from_fraction(arg1.value, + spl_fixpt_from_int((int)arg2).value)); } /* @@ -313,7 +316,7 @@ static inline struct spl_fixed31_32 spl_fixpt_div_int(struct spl_fixed31_32 arg1 */ static inline struct spl_fixed31_32 spl_fixpt_div(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) { - return spl_fixpt_from_fraction(arg1.value, arg2.value); + return SPL_NAMESPACE(spl_fixpt_from_fraction(arg1.value, arg2.value)); } /* @@ -328,7 +331,7 @@ static inline struct spl_fixed31_32 spl_fixpt_div(struct spl_fixed31_32 arg1, st * @note * No special actions taken in case argument is zero. */ -struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_recip(struct spl_fixed31_32 arg)); /* * @brief @@ -343,7 +346,7 @@ struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg); * Argument specified in radians, * internally it's normalized to [-2pi...2pi] range. */ -struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sinc(struct spl_fixed31_32 arg)); /* * @brief @@ -353,7 +356,7 @@ struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg); * Argument specified in radians, * internally it's normalized to [-2pi...2pi] range. */ -struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_sin(struct spl_fixed31_32 arg)); /* * @brief @@ -365,7 +368,7 @@ struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg); * passing arguments outside that range * will cause incorrect result! */ -struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_cos(struct spl_fixed31_32 arg)); /* * @brief @@ -379,7 +382,7 @@ struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg); * @note * Currently, function is verified for abs(arg) <= 1. */ -struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_exp(struct spl_fixed31_32 arg)); /* * @brief @@ -391,7 +394,7 @@ struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg); * Currently, no special actions taken * in case of invalid argument(s). Take care! */ -struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_log(struct spl_fixed31_32 arg)); /* * @brief @@ -410,10 +413,10 @@ static inline struct spl_fixed31_32 spl_fixpt_pow(struct spl_fixed31_32 arg1, st if (arg1.value == 0) return arg2.value == 0 ? spl_fixpt_one : spl_fixpt_zero; - return spl_fixpt_exp( - spl_fixpt_mul( - spl_fixpt_log(arg1), - arg2)); + return SPL_NAMESPACE(spl_fixpt_exp( + SPL_NAMESPACE(spl_fixpt_mul( + SPL_NAMESPACE(spl_fixpt_log(arg1)), + arg2)))); } /* @@ -482,19 +485,19 @@ static inline int spl_fixpt_ceil(struct spl_fixed31_32 arg) * fractional */ -unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg); +unsigned int SPL_NAMESPACE(spl_fixpt_u4d19(struct spl_fixed31_32 arg)); -unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg); +unsigned int SPL_NAMESPACE(spl_fixpt_u3d19(struct spl_fixed31_32 arg)); -unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg); +unsigned int SPL_NAMESPACE(spl_fixpt_u2d19(struct spl_fixed31_32 arg)); -unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg); +unsigned int SPL_NAMESPACE(spl_fixpt_u0d19(struct spl_fixed31_32 arg)); -unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg); +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg)); -unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg); +unsigned int SPL_NAMESPACE(spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg)); -int spl_fixpt_s4d19(struct spl_fixed31_32 arg); +int SPL_NAMESPACE(spl_fixpt_s4d19(struct spl_fixed31_32 arg)); static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg, unsigned int frac_bits) { @@ -513,10 +516,11 @@ static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg return arg; } -struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value, unsigned int integer_bits, unsigned int fractional_bits); -struct spl_fixed31_32 spl_fixpt_from_int_dy(unsigned int int_value, +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_ux_dy(unsigned int value, + unsigned int integer_bits, unsigned int fractional_bits)); +struct spl_fixed31_32 SPL_NAMESPACE(spl_fixpt_from_int_dy(unsigned int int_value, unsigned int frac_value, unsigned int integer_bits, - unsigned int fractional_bits); + unsigned int fractional_bits)); #endif diff --git a/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h index 2e6ba71960acf..ae2d24c856cf5 100644 --- a/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h +++ b/drivers/gpu/drm/amd/display/dc/sspl/spl_os_types.h @@ -53,4 +53,13 @@ static inline int64_t spl_div64_s64(int64_t dividend, int64_t divisor) #define spl_min(a, b) (((a) < (b)) ? (a):(b)) #endif +/* SPL namespace macros */ +#ifndef SPL_PFX_ +#define SPL_PFX_ +#endif + +#define SPL_EXPAND2(a, b) a##b +#define SPL_EXPAND(a, b) SPL_EXPAND2(a, b) +#define SPL_NAMESPACE(symbol) SPL_EXPAND(SPL_PFX_, symbol) + #endif /* _SPL_OS_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 9d0168986fe7a..c18ff8f00bb85 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -1,5 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2019-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -72,6 +73,9 @@ /* Default tracebuffer size if meta is absent. */ #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) +#define PSP_HEADER_BYTES_256 0x100 // 256 bytes +#define PSP_FOOTER_BYTES_256 0x100 // 256 bytes + /* Forward declarations */ struct dmub_srv; struct dmub_srv_common_regs; @@ -116,6 +120,7 @@ enum dmub_asic { DMUB_ASIC_DCN351, DMUB_ASIC_DCN36, DMUB_ASIC_DCN401, + DMUB_ASIC_DCN42, DMUB_ASIC_MAX, }; @@ -227,6 +232,23 @@ struct dmub_srv_region_params { const uint8_t *fw_inst_const; const uint8_t *fw_bss_data; const enum dmub_window_memory_type *window_memory_type; + const struct dmub_fw_meta_info *fw_info; +}; + +/** + * struct dmub_srv_fw_meta_info_params - params used for fetching fw meta info from fw_image + * @inst_const_size: size of the fw inst const section + * @bss_data_size: size of the fw bss data section + * @fw_inst_const: raw firmware inst const section + * @fw_bss_data: raw firmware bss data section + * @custom_psp_footer_size: custom psp footer size to use when indexing for fw meta info + */ +struct dmub_srv_fw_meta_info_params { + uint32_t inst_const_size; + uint32_t bss_data_size; + const uint8_t *fw_inst_const; + const uint8_t *fw_bss_data; + uint32_t custom_psp_footer_size; }; /** @@ -249,6 +271,7 @@ struct dmub_srv_region_info { uint32_t gart_size; uint8_t num_regions; struct dmub_region regions[DMUB_WINDOW_TOTAL]; + uint32_t verified_psp_footer_size; }; /** @@ -286,6 +309,16 @@ struct dmub_srv_fb_info { struct dmub_fb fb[DMUB_WINDOW_TOTAL]; }; +/** + * struct dmub_soc_fb_info - relevant addresses from the frame buffer + * @fb_base: base of the framebuffer aperture + * @fb_offset: offset of the framebuffer aperture + */ +struct dmub_soc_fb_info { + uint64_t fb_base; + uint64_t fb_offset; +}; + /* * struct dmub_srv_hw_params - params for dmub hardware initialization * @fb: framebuffer info for each region @@ -296,8 +329,7 @@ struct dmub_srv_fb_info { */ struct dmub_srv_hw_params { struct dmub_fb *fb[DMUB_WINDOW_TOTAL]; - uint64_t fb_base; - uint64_t fb_offset; + struct dmub_soc_fb_info soc_fb_info; uint32_t psp_version; bool load_inst_const; bool skip_panel_power_sequence; @@ -572,6 +604,7 @@ struct dmub_srv { struct dmub_srv_dcn32_regs *regs_dcn32; struct dmub_srv_dcn35_regs *regs_dcn35; const struct dmub_srv_dcn401_regs *regs_dcn401; + struct dmub_srv_dcn42_regs *regs_dcn42; struct dmub_srv_base_funcs funcs; struct dmub_srv_hw_funcs hw_funcs; struct dmub_srv_inbox inbox1; @@ -589,8 +622,7 @@ struct dmub_srv { bool hw_init; bool dpia_supported; - uint64_t fb_base; - uint64_t fb_offset; + struct dmub_soc_fb_info soc_fb_info; uint32_t psp_version; /* Feature capabilities reported by fw */ @@ -1098,4 +1130,16 @@ enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub); */ bool dmub_srv_get_preos_info(struct dmub_srv *dmub); +/** + * dmub_srv_get_fw_meta_info_from_raw_fw() - Fetch firmware metadata info from raw firmware image + * @params: parameters for fetching firmware metadata info + * @fw_info_out: output buffer for firmware metadata info + * + * Return: + * DMUB_STATUS_OK - success + * DMUB_STATUS_INVALID - no FW meta info found + */ +enum dmub_status dmub_srv_get_fw_meta_info_from_raw_fw(struct dmub_srv_fw_meta_info_params *params, + struct dmub_fw_meta_info *fw_info_out); + #endif /* _DMUB_SRV_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 3f2a0ed02c599..8fbd179a4c87a 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -139,6 +139,33 @@ */ #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 +/** + * + * dirty rect cmd version legacy + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0 +/** + * dirty rect cmd version with multi edp support + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1 +/** + * dirty rect cmd version with external monitor support + */ +#define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2 + +/** + * + * Cursor update cmd version legacy + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0 +/** + * Cursor update cmd version with multi edp support + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1 +/** + * Cursor update cmd version with external monitor support + */ +#define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2 /** * ABM control version legacy @@ -636,17 +663,29 @@ union pr_debug_flags { /** * 0x10 (bit 4) - * @skip_crtc_disabled: CRTC disable skipped + * @visual_confirm_rate_control: Enable Visual Confirm rate control detection */ - uint32_t skip_crtc_disabled : 1; + uint32_t visual_confirm_rate_control : 1; - /* + /** * 0x20 (bit 5) - * @visual_confirm_rate_control: Enable Visual Confirm rate control detection + * @force_full_frame_update: Force all selective updates to be full frame updates */ - uint32_t visual_confirm_rate_control : 1; + uint32_t force_full_frame_update : 1; + + /** + * 0x40 (bit 6) + * @force_dpg_on: Force DPG on + */ + uint32_t force_dpg_on : 1; - uint32_t reserved : 26; + /** + * 0x80 (bit 7) + * @force_hubp_on: Force Hubp on + */ + uint32_t force_hubp_on : 1; + + uint32_t reserved : 24; } bitfields; uint32_t u32All; @@ -669,19 +708,12 @@ union pr_hw_flags { * @fec_enable_status: receive fec enable/disable status from driver */ uint32_t fec_enable_status : 1; - /* * @smu_optimizations_en: SMU power optimization. * Only when active display is Replay capable and display enters Replay. * Trigger interrupt to SMU to powerup/down. */ uint32_t smu_optimizations_en : 1; - - /** - * @phy_power_state: Indicates current phy power state - */ - uint32_t phy_power_state : 1; - /** * @link_power_state: Indicates current link power state */ @@ -698,11 +730,22 @@ union pr_hw_flags { * @alpm_mode: Indicates ALPM mode selected */ uint32_t alpm_mode : 2; + uint32_t reserved : 23; } bitfields; uint32_t u32All; }; +/** + * Definition of Panel Replay ML Activity Options + */ +enum pr_ml_activity_option { + OPTION_DEFAULT = 0x00, // VESA Option Default (1C) + OPTION_1A = 0x01, // VESA Option 1A + OPTION_1B = 0x02, // VESA Option 1B + OPTION_1C = 0x03, // VESA Option 1C +}; + union fw_assisted_mclk_switch_version { struct { uint8_t minor : 5; @@ -866,7 +909,8 @@ union dmub_fw_meta_feature_bits { struct { uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */ - uint32_t reserved : 30; + uint32_t inbox0_lock_support: 1; /**< 1 supports inbox0 lock mechanism */ + uint32_t reserved : 29; } bits; /**< status bits */ uint32_t all; /**< 32-bit access to status bits */ }; @@ -1085,7 +1129,10 @@ union dmub_fw_boot_options { uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */ uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */ - uint32_t reserved : 4; /**< reserved */ + uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/ + uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/ + uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/ + uint32_t reserved : 1; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; @@ -1489,14 +1536,12 @@ enum dmub_gpint_command { * 1 - Enable ips measurement */ DMUB_GPINT__IPS_RESIDENCY = 121, - /** * DESC: Enable measurements for various task duration * ARGS: 0 - Disable measurement * 1 - Enable measurement */ DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, - /** * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency @@ -1506,21 +1551,18 @@ enum dmub_gpint_command { * RETURN: Total residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, - /** * DESC: Gets IPS1 histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, - /** * DESC: Gets IPS2 histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, - /** * DESC: Gets IPS residency * ARGS: 0 - Return IPS1 residency @@ -1530,21 +1572,18 @@ enum dmub_gpint_command { * RETURN: Total residency in milli-percent. */ DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, - /** * DESC: Gets IPS1_RCG histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, - /** * DESC: Gets IPS1_ONO2_ON histogram counts * ARGS: Bucket index * RETURN: Total count for the bucket */ DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, - /** * DESC: Gets IPS entry counter during residency measurement * ARGS: 0 - Return IPS1 entry counts @@ -1554,7 +1593,6 @@ enum dmub_gpint_command { * RETURN: Entry counter for selected IPS mode */ DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, - /** * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency @@ -1564,7 +1602,6 @@ enum dmub_gpint_command { * RETURN: Total inactive residency in microseconds - lower 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, - /** * DESC: Gets IPS inactive residency in microseconds * ARGS: 0 - Return IPS1_MAX residency @@ -1574,7 +1611,6 @@ enum dmub_gpint_command { * RETURN: Total inactive residency in microseconds - upper 32 bits */ DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, - /** * DESC: Gets IPS residency in microseconds * ARGS: 0 - Return IPS1 residency @@ -1592,6 +1628,11 @@ enum dmub_gpint_command { * DESC: Initiates IPS wake sequence. */ DMUB_GPINT__IPS_DEBUG_WAKE = 137, + /** + * DESC: Do panel power off sequence + * ARGS: 1 - Power off + */ + DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138, }; /** @@ -1626,7 +1667,7 @@ union dmub_inbox0_cmd_lock_hw { uint32_t lock_dig: 1; uint32_t triple_buffer_lock: 1; - uint32_t lock: 1; /**< Lock */ + uint32_t lock: 1; /**< Lock */ uint32_t should_release: 1; /**< Release */ uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ } bits; @@ -1846,6 +1887,15 @@ enum dmub_cmd_type { */ DMUB_CMD__PR = 94, + /** + * Command type used for all IHC commands. + */ + DMUB_CMD__IHC = 95, + + /** + * Command type use for boot time crc commands. + */ + DMUB_CMD__BOOT_TIME_CRC = 96, /** * Command type use for VBIOS shared commands. @@ -2496,6 +2546,7 @@ struct dmub_fams2_drr_stream_static_state { struct dmub_fams2_cmd_legacy_stream_static_state { uint16_t vactive_det_fill_delay_otg_vlines; uint16_t programming_delay_otg_vlines; + uint32_t disallow_time_us; }; //v1 struct dmub_fams2_cmd_subvp_stream_static_state { @@ -2558,9 +2609,9 @@ struct dmub_fams2_stream_static_state { uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline union { struct { - uint8_t is_drr: 1; // stream is DRR enabled - uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal - uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank + uint8_t is_drr : 1; // stream is DRR enabled + uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal + uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank } bits; uint8_t all; } config; @@ -2630,7 +2681,8 @@ union dmub_fams2_global_feature_config { uint32_t enable_offload_flip: 1; uint32_t enable_visual_confirm: 1; uint32_t allow_delay_check_mode: 2; - uint32_t reserved: 24; + uint32_t legacy_method_no_fams2 : 1; + uint32_t reserved : 23; } bits; uint32_t all; }; @@ -2647,7 +2699,6 @@ struct dmub_cmd_fams2_global_config { union dmub_cmd_fams2_config { struct dmub_cmd_fams2_global_config global; -// coverity[cert_dcl37_c_violation:FALSE] errno.h, stddef.h, stdint.h not included in atombios.h struct dmub_fams2_stream_static_state stream; //v0 union { struct dmub_fams2_cmd_stream_static_base_state base; @@ -3667,7 +3718,7 @@ struct dmub_cmd_psr_copy_settings_data { /** * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities */ - uint8_t rate_control_caps ; + uint8_t rate_control_caps; /* * Force PSRSU always doing full frame update */ @@ -3919,7 +3970,7 @@ struct dmub_cmd_update_dirty_rect_data { */ union dmub_psr_su_debug_flags debug_flags; /** - * OTG HW instance. + * Pipe index. */ uint8_t pipe_idx; /** @@ -3927,7 +3978,7 @@ struct dmub_cmd_update_dirty_rect_data { */ uint8_t dirty_rect_count; /** - * PSR control version. + * dirty rects cmd version. */ uint8_t cmd_version; /** @@ -3936,6 +3987,14 @@ struct dmub_cmd_update_dirty_rect_data { * Currently the support is only for 0 or 1 */ uint8_t panel_inst; + /** + * OTG HW instance + */ + uint8_t otg_inst; + /** + * Padding for 4 byte alignment + */ + uint8_t padding[3]; }; /** @@ -4061,11 +4120,11 @@ struct dmub_cmd_update_cursor_payload0 { */ uint8_t enable; /** - * OTG HW instance. + * Pipe index. */ uint8_t pipe_idx; /** - * PSR control version. + * Cursor update cmd version. */ uint8_t cmd_version; /** @@ -4079,6 +4138,14 @@ struct dmub_cmd_update_cursor_payload0 { * Registers contains Hubp & Dpp modules */ struct dmub_cursor_position_cfg position_cfg; + /** + * OTG HW instance + */ + uint8_t otg_inst; + /** + * Padding for 4 byte alignment + */ + uint8_t padding[3]; }; struct dmub_cmd_update_cursor_payload1 { @@ -4277,7 +4344,7 @@ enum pr_state { // Active and Pending Power Up PR_STATE_2_PENDING_POWER_UP = 0x33, // Active and Powered Up, Pending DPG latch - PR_STATE_2_PENDING_LOCK_FOR_DPG_POWER_ON = 0x34, + PR_STATE_2_PENDING_LOCK = 0x34, // Active and Powered Up, Pending SDP and Unlock PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35, // Pending transmission of AS SDP for timing sync, but no rfb update @@ -4326,10 +4393,6 @@ enum dmub_cmd_replay_type { * Set adaptive sync sdp enabled */ DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, - /** - * Set version - */ - DMUB_CMD__REPLAY_SET_VERSION = 9, /** * Set Replay General command. */ @@ -4349,6 +4412,7 @@ enum dmub_cmd_panel_replay_type { enum dmub_cmd_panel_replay_state_update_subtype { PR_STATE_UPDATE_COASTING_VTOTAL = 0x1, PR_STATE_UPDATE_SYNC_MODE = 0x2, + PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3, }; enum dmub_cmd_panel_replay_general_subtype { @@ -4371,6 +4435,9 @@ enum dmub_cmd_replay_general_subtype { REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, REPLAY_GENERAL_CMD_VIDEO_CONFERENCING, + REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC, + REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE, + REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT, }; struct dmub_alpm_auxless_data { @@ -4497,40 +4564,6 @@ enum replay_version { REPLAY_VERSION_UNSUPPORTED = 0xFF, }; -/** - * Data passed from driver to FW in a DMUB_CMD___SET_REPLAY_VERSION command. - */ -struct dmub_cmd_replay_set_version_data { - /** - * Panel Instance. - * Panel instance to identify which psr_state to use - * Currently the support is only for 0 or 1 - */ - uint8_t panel_inst; - /** - * Replay version that FW should implement. - */ - enum replay_version version; - /** - * Explicit padding to 4 byte boundary. - */ - uint8_t pad[3]; -}; - -/** - * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. - */ -struct dmub_rb_cmd_replay_set_version { - /** - * Command header. - */ - struct dmub_cmd_header header; - /** - * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_VERSION command. - */ - struct dmub_cmd_replay_set_version_data replay_set_version_data; -}; - /** * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. */ @@ -4623,6 +4656,18 @@ struct dmub_rb_cmd_replay_enable_data { * This does not support HDMI/DP2 for now. */ uint8_t phy_rate; + /** + * @hpo_stream_enc_inst: HPO stream encoder instance + */ + uint8_t hpo_stream_enc_inst; + /** + * @hpo_link_enc_inst: HPO link encoder instance + */ + uint8_t hpo_link_enc_inst; + /** + * @pad: Align structure to 4 byte boundary. + */ + uint8_t pad[2]; }; /** @@ -4921,16 +4966,58 @@ union dmub_replay_cmd_set { * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. */ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; - /** - * Definition of DMUB_CMD__REPLAY_SET_VERSION command data. - */ - struct dmub_cmd_replay_set_version_data version_data; /** * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. */ struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; }; +/** + * IHC command sub-types. + */ +enum dmub_cmd_ihc_type { + /** + * Set DIG HDCP interrupt destination. + */ + DMUB_CMD__IHC_SET_DIG_HDCP_INTERRUPT_DEST = 0, +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__IHC command. + */ +struct dmub_cmd_ihc_data { + /** + * DIG engine ID (0-3). + */ + uint8_t dig_id; + /** + * 1 = route to DMU, 0 = route to CPU. + */ + uint8_t to_dmu : 1; + /** + * Reserved bits. + */ + uint8_t reserved : 7; + /** + * Padding. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__IHC command. + */ +struct dmub_rb_cmd_ihc { + /** + * Command header. + */ + struct dmub_cmd_header header; + /** + * IHC command data. + */ + struct dmub_cmd_ihc_data data; +}; + /** * SMART POWER OLED command sub-types. */ @@ -6603,10 +6690,6 @@ struct dmub_cmd_pr_copy_settings_data { * Currently the support is only for 0 or 1 */ uint8_t panel_inst; - /** - * Length of each horizontal line in ns. - */ - uint32_t line_time_in_ns; /** * PHY instance. */ @@ -6615,10 +6698,10 @@ struct dmub_cmd_pr_copy_settings_data { * Determines if SMU optimzations are enabled/disabled. */ uint8_t smu_optimizations_en; - /* - * Use FSM state for Replay power up/down + /** + * Length of each horizontal line in ns. */ - uint8_t use_phy_fsm; + uint32_t line_time_in_ns; /* * Use FSFT afftet pixel clk */ @@ -6631,6 +6714,14 @@ struct dmub_cmd_pr_copy_settings_data { * Use for AUX-less ALPM LFPS wake operation */ struct dmub_alpm_auxless_data auxless_alpm_data; + /** + * DSC Slice height. + */ + uint16_t dsc_slice_height; + /* + * Use FSM state for Replay power up/down + */ + uint8_t use_phy_fsm; /** * @hpo_stream_enc_inst: HPO stream encoder instance */ @@ -6639,10 +6730,26 @@ struct dmub_cmd_pr_copy_settings_data { * @hpo_link_enc_inst: HPO link encoder instance */ uint8_t hpo_link_enc_inst; + /* + * Selective Update granularity needed. + */ + uint8_t su_granularity_needed; + /* + * Horizontal granularity for Selective Update. + */ + uint16_t su_x_granularity; + /* + * Extended caps of vertical granularity for Selective Update. + */ + uint16_t su_y_granularity_extended_caps; + /* + * Vertical granularity for Selective Update. + */ + uint8_t su_y_granularity; /** - * @pad: Align structure to 4 byte boundary. + * @main_link_activity_option: Indicates main link activity option selected */ - uint8_t pad[2]; + uint8_t main_link_activity_option; }; /** @@ -6659,6 +6766,13 @@ struct dmub_rb_cmd_pr_copy_settings { struct dmub_cmd_pr_copy_settings_data data; }; +union dmub_pr_runtime_flags { + struct { + uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR + } bitfields; + uint32_t u32All; +}; + struct dmub_cmd_pr_update_state_data { /** * Panel Instance. @@ -6677,6 +6791,8 @@ struct dmub_cmd_pr_update_state_data { */ uint32_t coasting_vtotal; uint32_t sync_mode; + + union dmub_pr_runtime_flags pr_runtime_flags; }; struct dmub_cmd_pr_general_cmd_data { @@ -6728,6 +6844,29 @@ struct dmub_rb_cmd_pr_general_cmd { struct dmub_cmd_pr_general_cmd_data data; }; +/** + * Command type of a DMUB_CMD__BOOT_TIME_CRC command + */ +enum dmub_cmd_boot_time_crc_type { + DMUB_CMD__BOOT_TIME_CRC_INIT_MEM = 0 +}; + +/** + * Data passed from driver to FW in a DMUB_CMD__BOOT_TIME_CRC_INIT command. + */ +struct dmub_cmd_boot_time_crc_init_data { + union dmub_addr buffer_addr; + uint32_t buffer_size; +}; + +/** + * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. + */ +struct dmub_rb_cmd_boot_time_crc_init { + struct dmub_cmd_header header; + struct dmub_cmd_boot_time_crc_init_data data; +}; + /** * union dmub_rb_cmd - DMUB inbox command. */ @@ -6992,10 +7131,6 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. */ struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; - /** - * Definition of a DMUB_CMD__REPLAY_SET_VERSION command. - */ - struct dmub_rb_cmd_replay_set_version replay_set_version; /* * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. */ @@ -7089,6 +7224,14 @@ union dmub_rb_cmd { struct dmub_rb_cmd_pr_update_state pr_update_state; struct dmub_rb_cmd_pr_general_cmd pr_general_cmd; + /** + * Definition of a DMUB_CMD__IHC command. + */ + struct dmub_rb_cmd_ihc ihc; + /** + * Definition of a DMUB_CMD__BOOT_TIME_CRC_INIT command. + */ + struct dmub_rb_cmd_boot_time_crc_init boot_time_crc_init; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/src/Makefile b/drivers/gpu/drm/amd/display/dmub/src/Makefile index 468b768c11aeb..ac7b17d8fb0fd 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/Makefile +++ b/drivers/gpu/drm/amd/display/dmub/src/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Advanced Micro Devices, Inc. +# Copyright 2019-2026 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -28,6 +28,7 @@ DMUB += dmub_dcn35.o DMUB += dmub_dcn351.o DMUB += dmub_dcn36.o DMUB += dmub_dcn401.o +DMUB += dmub_dcn42.o AMD_DAL_DMUB = $(addprefix $(AMDDALPATH)/dmub/src/,$(DMUB)) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c index 73888c1bea935..54df2147e4dcf 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c @@ -63,9 +63,9 @@ static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub, { uint32_t tmp; - if (dmub->fb_base || dmub->fb_offset) { - *fb_base = dmub->fb_base; - *fb_offset = dmub->fb_offset; + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; return; } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c index a4abe951c8382..84a6eb3f677de 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c @@ -63,9 +63,9 @@ static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub, { uint32_t tmp; - if (dmub->fb_base || dmub->fb_offset) { - *fb_base = dmub->fb_base; - *fb_offset = dmub->fb_offset; + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; return; } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c index cd04d7c756c3d..a0cefc03b21da 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c @@ -59,9 +59,9 @@ static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub, { uint32_t tmp; - if (dmub->fb_base || dmub->fb_offset) { - *fb_base = dmub->fb_base; - *fb_offset = dmub->fb_offset; + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; return; } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c index 7e98562899108..2f99a2772599e 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c @@ -65,9 +65,9 @@ static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub, { uint32_t tmp; - if (dmub->fb_base || dmub->fb_offset) { - *fb_base = dmub->fb_base; - *fb_offset = dmub->fb_offset; + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; return; } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index e13557ed97be5..639f9835e5e96 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -63,9 +63,9 @@ static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub, uint32_t tmp; /* - if (dmub->fb_base || dmub->fb_offset) { - *fb_base = dmub->fb_base; - *fb_offset = dmub->fb_offset; + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; return; } */ @@ -419,6 +419,9 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; + boot_options.bits.bootcrc_en_at_preos = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_preos; + boot_options.bits.bootcrc_en_at_S0i3 = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_S0i3; + boot_options.bits.bootcrc_boot_mode = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_boot_mode; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c index 95542299e3b38..16ed07f0e96d7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c @@ -39,9 +39,9 @@ static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub, { uint32_t tmp; - if (dmub->fb_base || dmub->fb_offset) { - *fb_base = dmub->fb_base; - *fb_offset = dmub->fb_offset; + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; return; } diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c new file mode 100644 index 0000000000000..7833a4fb7fbfe --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c @@ -0,0 +1,753 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2026 Advanced Micro Devices, Inc. + +#include "../dmub_srv.h" +#include "dmub_reg.h" +#include "dmub_dcn35.h" +#include "dmub_dcn401.h" +#include "dmub_dcn42.h" + +#include "dcn/dcn_4_2_0_offset.h" +#include "dcn/dcn_4_2_0_sh_mask.h" + +#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] +#define CTX dmub +#define REGS dmub->regs_dcn42 +#define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) + +void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) +{ + struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42; +#define REG_STRUCT regs + +#define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); + DMUB_DCN42_REGS() + DMCUB_INTERNAL_REGS() +#undef DMUB_SR + +#define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); + DMUB_DCN42_FIELDS() +#undef DMUB_SF + +#define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); + DMUB_DCN42_FIELDS() +#undef DMUB_SF +#undef REG_STRUCT +} + +void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) +{ + union dmub_fw_boot_options boot_options = {0}; + + if (!dmub->dpia_supported) { + dmub->dpia_supported = dmub_dcn42_get_fw_boot_option(dmub).bits.enable_dpia; + } + + boot_options.bits.z10_disable = params->disable_z10; + boot_options.bits.dpia_supported = params->dpia_supported; + boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia; + boot_options.bits.usb4_cm_version = params->usb4_cm_version; + boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; + boot_options.bits.power_optimization = params->power_optimization; + boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds; + boot_options.bits.disable_clk_gate = params->disable_clock_gate; + boot_options.bits.ips_disable = params->disable_ips; + boot_options.bits.ips_sequential_ono = params->ips_sequential_ono; + boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; + boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; + boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; + boot_options.bits.skip_phy_access = params->disallow_phy_access; + boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; + + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +static void dmub_dcn42_get_fb_base_offset(struct dmub_srv *dmub, + uint64_t *fb_base, + uint64_t *fb_offset) +{ + uint32_t tmp; + + /* + if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { + *fb_base = dmub->soc_fb_info.fb_base; + *fb_offset = dmub->soc_fb_info.fb_offset; + return; + } + */ + + REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); + *fb_base = (uint64_t)tmp << 24; + + REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); + *fb_offset = (uint64_t)tmp << 24; +} + +static inline void dmub_dcn42_translate_addr(const union dmub_addr *addr_in, + uint64_t fb_base, + uint64_t fb_offset, + union dmub_addr *addr_out) +{ + addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; +} + +void dmub_dcn42_reset(struct dmub_srv *dmub) +{ + union dmub_gpint_data_register cmd; + const uint32_t timeout = 100000; + uint32_t in_reset, is_enabled, scratch, i, pwait_mode; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); + + if (in_reset == 0 && is_enabled != 0) { + cmd.bits.status = 1; + cmd.bits.command_code = DMUB_GPINT__STOP_FW; + cmd.bits.param = 0; + + dmub->hw_funcs.set_gpint(dmub, cmd); + + for (i = 0; i < timeout; ++i) { + if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) + break; + + udelay(1); + } + + for (i = 0; i < timeout; ++i) { + scratch = REG_READ(DMCUB_SCRATCH7); + if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) + break; + + udelay(1); + } + + for (i = 0; i < timeout; ++i) { + REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); + if (pwait_mode & (1 << 0)) + break; + + udelay(1); + } + /* Force reset in case we timed out, DMCUB is likely hung. */ + } + + if (is_enabled) { + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); + udelay(1); + REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); + } + + REG_WRITE(DMCUB_INBOX1_RPTR, 0); + REG_WRITE(DMCUB_INBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); + REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); + REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); + REG_WRITE(DMCUB_SCRATCH0, 0); + + /* Clear the GPINT command manually so we don't send anything during boot. */ + cmd.all = 0; + dmub->hw_funcs.set_gpint(dmub, cmd); +} + +void dmub_dcn42_reset_release(struct dmub_srv *dmub) +{ + REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); + + REG_UPDATE_3(DMU_CLK_CNTL, + LONO_DISPCLK_GATE_DISABLE, 1, + LONO_SOCCLK_GATE_DISABLE, 1, + LONO_DMCUBCLK_GATE_DISABLE, 1); + + REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); + REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); + REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); +} + +void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + uint64_t fb_base, fb_offset; + + dmub_dcn42_get_fb_base_offset(dmub, &fb_base, &fb_offset); + + dmub_dcn42_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + + dmub_dcn42_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); + + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + + /* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */ + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0); +} + +void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, + const struct dmub_window *cw0, + const struct dmub_window *cw1) +{ + union dmub_addr offset; + + REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); + offset = cw0->offset; + REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); + REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, + DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, + DMCUB_REGION3_CW0_ENABLE, 1); + offset = cw1->offset; + REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); + REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, + DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, + DMCUB_REGION3_CW1_ENABLE, 1); + REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, + 0x20); +} +void dmub_dcn42_setup_windows(struct dmub_srv *dmub, + const struct dmub_window *cw2, + const struct dmub_window *cw3, + const struct dmub_window *cw4, + const struct dmub_window *cw5, + const struct dmub_window *cw6, + const struct dmub_window *region6) +{ + union dmub_addr offset; + + offset = cw3->offset; + + REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); + REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, + DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, + DMCUB_REGION3_CW3_ENABLE, 1); + + offset = cw4->offset; + + REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); + REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, + DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, + DMCUB_REGION3_CW4_ENABLE, 1); + + offset = cw5->offset; + + REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); + REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, + DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, + DMCUB_REGION3_CW5_ENABLE, 1); + + REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, + DMCUB_REGION5_TOP_ADDRESS, + cw5->region.top - cw5->region.base - 1, + DMCUB_REGION5_ENABLE, 1); + + offset = cw6->offset; + + REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); + REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, + DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, + DMCUB_REGION3_CW6_ENABLE, 1); + + offset = region6->offset; + + REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, + DMCUB_REGION6_TOP_ADDRESS, + region6->region.top - region6->region.base - 1, + DMCUB_REGION6_ENABLE, 1); +} + +uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_INBOX1_WPTR); +} + +uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_INBOX1_RPTR); +} + +void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, + const struct dmub_region *outbox1) +{ + REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); + REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); +} + +uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub) +{ + /** + * outbox1 wptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + return REG_READ(DMCUB_OUTBOX1_WPTR); +} + +void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + /** + * outbox1 rptr register is accessed without locks (dal & dc) + * and to be called only by dmub_srv_stat_get_notification() + */ + REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); +} + +bool dmub_dcn42_is_supported(struct dmub_srv *dmub) +{ + uint32_t supported = 0; + + REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); + + return supported; +} + +union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub) +{ + union dmub_fw_boot_options option; + + option.all = REG_READ(DMCUB_SCRATCH14); + return option; +} + +void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0) +{ + REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); + + REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); +} + +bool dmub_dcn42_should_detect(struct dmub_srv *dmub) +{ + uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0); + bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0; + return should_detect; +} + +void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) +{ + REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); +} + +uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH17); +} + +bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + uint32_t is_enable; + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); + if (is_enable == 0) + return false; + + status.all = REG_READ(DMCUB_SCRATCH0); + + return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) || + (!status.bits.dal_fw && status.bits.mailbox_rdy); +} + +void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) +{ + REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); +} + +bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + uint32_t is_hw_init; + + status.all = REG_READ(DMCUB_SCRATCH0); + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); + + return is_hw_init != 0 && status.bits.dal_fw; +} + +union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub) +{ + union dmub_fw_boot_status status; + + status.all = REG_READ(DMCUB_SCRATCH0); + return status; +} + +void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) +{ + union dmub_fw_boot_options boot_options; + boot_options.all = REG_READ(DMCUB_SCRATCH14); + boot_options.bits.skip_phy_init_panel_sequence = skip; + REG_WRITE(DMCUB_SCRATCH14, boot_options.all); +} + +void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub) +{ + /* DMCUB_REGION3_TMR_AXI_SPACE values: + * 0b011 (0x3) - FB physical address + * 0b100 (0x4) - GPU virtual address + * + * Default value is 0x3 (FB Physical address for TMR). When programming + * DMUB to be in system memory, change to 0x4. The system memory allocated + * is accessible by both GPU and CPU, so we use GPU virtual address. + */ + REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); +} + +void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub) +{ + REG_WRITE(DMCUB_SCRATCH17, 0); +} + +void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, + union dmub_rb_cmd *cmd) +{ + uint32_t *dwords = (uint32_t *)cmd; + int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; + uint32_t msg_index; + static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); + + /* read remaining data based on payload size */ + for (msg_index = 0; msg_index < 15; msg_index++) { + if (payload_size_bytes <= msg_index * 4) { + break; + } + + switch (msg_index) { + case 0: + REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]); + break; + case 1: + REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]); + break; + case 2: + REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]); + break; + case 3: + REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]); + break; + case 4: + REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]); + break; + case 5: + REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]); + break; + case 6: + REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]); + break; + case 7: + REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]); + break; + case 8: + REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]); + break; + case 9: + REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]); + break; + case 10: + REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]); + break; + case 11: + REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]); + break; + case 12: + REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]); + break; + case 13: + REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]); + break; + case 14: + REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]); + break; + } + } + + /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY + * interrupt. + */ + REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]); +} + +uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub) +{ + uint32_t status; + + REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status); + return status; +} + +void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, + union dmub_rb_cmd *cmd) +{ + uint32_t *dwords = (uint32_t *)cmd; + + static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); + + dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP); + dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0); + dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1); + dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2); + dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3); + dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4); + dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5); + dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6); + dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7); + dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8); + dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9); + dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10); + dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11); + dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12); + dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13); + dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14); +} + +void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1); +} + +void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0); +} + +void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0); +} + +void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1); + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0); +} + +void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg) +{ + *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0); +} + + +void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable) +{ + REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0); +} + +uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub) +{ + uint32_t status; + + REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status); + return status; +} + +void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, + const struct dmub_region *inbox1) +{ + REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); + REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); +} + +void dmub_dcn42_set_gpint(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); +} + +bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, + union dmub_gpint_data_register reg) +{ + union dmub_gpint_data_register test; + + reg.bits.status = 0; + test.all = REG_READ(DMCUB_GPINT_DATAIN1); + + return test.all == reg.all; +} + +uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_SCRATCH7); +} + +uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub) +{ + uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); + + REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); + + REG_WRITE(DMCUB_GPINT_DATAOUT, 0); + REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); + REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); + + REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); + + return dataout; +} + +uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_OUTBOX0_WPTR); +} + +void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) +{ + REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); +} + +uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub) +{ + return REG_READ(DMCUB_TIMER_CURRENT); +} + +void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub) +{ + uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait; + uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; + struct dmub_timeout_info timeout = {0}; + + if (!dmub) + return; + + /* timeout data filled externally, cache before resetting memory */ + timeout = dmub->debug.timeout_info; + memset(&dmub->debug, 0, sizeof(dmub->debug)); + dmub->debug.timeout_info = timeout; + + dmub->debug.dmcub_version = dmub->fw_version; + + dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); + dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); + dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); + dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); + dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); + dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); + dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); + dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); + dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); + dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); + dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); + dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); + dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); + dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); + dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); + dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); + dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); + + dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); + dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); + dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); + + dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); + dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); + dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); + + dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); + dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); + dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); + + dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); + dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); + dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); + dmub->debug.is_dmcub_enabled = is_dmub_enabled; + + REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); + dmub->debug.is_pwait = is_pwait; + + REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); + dmub->debug.is_dmcub_soft_reset = is_soft_reset; + + REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); + dmub->debug.is_dmcub_secure_reset = is_sec_reset; + + REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); + dmub->debug.is_traceport_en = is_traceport_enabled; + + REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); + dmub->debug.is_cw0_enabled = is_cw0_enabled; + + REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); + dmub->debug.is_cw6_enabled = is_cw6_enabled; + + dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); +} + +bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub) +{ + uint64_t region3_cw5_offset; + uint32_t top_addr, top_addr_enable, offset_low; + uint32_t offset_high, base_addr, fw_version; + bool is_vbios_fw = false; + + memset(&dmub->preos_info, 0, sizeof(dmub->preos_info)); + + fw_version = REG_READ(DMCUB_SCRATCH1); + is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false; + if (!is_vbios_fw) + return false; + + dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0); + dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1); + dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14); + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, + DMCUB_REGION3_CW5_ENABLE, &top_addr_enable); + if (top_addr_enable) { + dmub_dcn42_get_fb_base_offset(dmub, + &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset); + offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET); + offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH); + region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low; + dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset + - dmub->preos_info.fb_base + dmub->preos_info.fb_offset; + + REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, + DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr); + base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF; + dmub->preos_info.trace_buffer_size = + (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0; + } + + return true; +} + +void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp) +{ + REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp); +} + +uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub) +{ + uint32_t status; + + REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status); + return status; +} diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h new file mode 100644 index 0000000000000..a49d88ab0455f --- /dev/null +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _DMUB_DCN42_H_ +#define _DMUB_DCN42_H_ + +#include "dmub_dcn35.h" +#include "dmub_dcn401.h" + + +struct dmub_srv; + +/* DCN42 register definitions. */ + +#define DMUB_DCN42_REGS() \ + DMUB_DCN35_REGS() \ + DMUB_SR(DMCUB_INTERRUPT_STATUS) \ + DMUB_SR(DMCUB_REG_INBOX0_RDY) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG0) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG1) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG2) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG3) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG4) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG5) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG6) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG7) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG8) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG9) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG10) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG11) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG12) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG13) \ + DMUB_SR(DMCUB_REG_INBOX0_MSG14) \ + DMUB_SR(DMCUB_REG_INBOX0_RSP) \ + DMUB_SR(DMCUB_REG_OUTBOX0_RDY) \ + DMUB_SR(DMCUB_REG_OUTBOX0_MSG0) \ + DMUB_SR(DMCUB_REG_OUTBOX0_RSP) \ + DMUB_SR(HOST_INTERRUPT_CSR) + +#define DMUB_DCN42_FIELDS() \ + DMUB_DCN35_FIELDS() \ + DMUB_SF(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT) \ + DMUB_SF(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN) + +struct dmub_srv_dcn42_reg_offset { +#define DMUB_SR(reg) uint32_t reg; + DMUB_DCN42_REGS() + DMCUB_INTERNAL_REGS() +#undef DMUB_SR +}; + +struct dmub_srv_dcn42_reg_shift { +#define DMUB_SF(reg, field) uint8_t reg##__##field; + DMUB_DCN42_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn42_reg_mask { +#define DMUB_SF(reg, field) uint32_t reg##__##field; + DMUB_DCN42_FIELDS() +#undef DMUB_SF +}; + +struct dmub_srv_dcn42_regs { + struct dmub_srv_dcn42_reg_offset offset; + struct dmub_srv_dcn42_reg_mask mask; + struct dmub_srv_dcn42_reg_shift shift; +}; + +/* Function declarations */ + +/* Initialization and configuration */ +void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx); +void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params); +void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip); +void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub); + +/* Reset and control */ +void dmub_dcn42_reset(struct dmub_srv *dmub); +void dmub_dcn42_reset_release(struct dmub_srv *dmub); + +/* Firmware loading */ +void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); +void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1); +void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6); + +/* Mailbox operations - Inbox1 */ +void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1); +uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub); +uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub); +void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset); + +/* Mailbox operations - Outbox1 */ +void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1); +uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub); +void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +/* Mailbox operations - Outbox0 */ +void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0); +uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub); +void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + +/* Mailbox operations - Inbox0 */ +void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data); +void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub); +uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub); + +/* REG Inbox0/Outbox0 operations */ +void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); +uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub); +void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd); +void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); +void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub); +void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable); + +void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub); +void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg); +void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp); +uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub); +void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable); +uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub); + +/* GPINT operations */ +void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg); +bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg); +uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub); +uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub); + +/* Status and detection */ +bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub); +bool dmub_dcn42_is_supported(struct dmub_srv *dmub); +bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub); +bool dmub_dcn42_should_detect(struct dmub_srv *dmub); + + +/* Firmware boot status and options */ +union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub); +union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub); + +/* Timing and diagnostics */ +uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub); +void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub); +bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub); + +#endif /* _DMUB_DCN42_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c index ca0c8a54b635e..88bf59ee5fea7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c @@ -63,11 +63,18 @@ static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, } } +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask, uint8_t shift) { return (mask & reg_value) >> shift; } +#endif void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index 123d1704670ee..10a87a277be22 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -28,6 +28,14 @@ #include "../inc/dmub_cmd.h" +#ifdef REG_SET +#undef REG_SET +#endif + +#ifdef REG_GET +#undef REG_GET +#endif + struct dmub_srv; /* Register offset and field lookup. */ @@ -42,7 +50,14 @@ struct dmub_srv; #define REG(reg) (REGS)->offset.reg +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field +#endif #define FN(reg_name, field) FD(reg_name##__##field) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c index a6ae1d2e9685b..3bba256a288d7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c @@ -1,5 +1,6 @@ +// SPDX-License-Identifier: MIT /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright 2019-2026 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -22,7 +23,6 @@ * Authors: AMD * */ - #include "../dmub_srv.h" #include "dmub_dcn20.h" #include "dmub_dcn21.h" @@ -40,6 +40,7 @@ #include "dmub_dcn351.h" #include "dmub_dcn36.h" #include "dmub_dcn401.h" +#include "dmub_dcn42.h" #include "os_types.h" /* * Note: the DMUB service is standalone. No additional headers should be @@ -66,7 +67,7 @@ #define DMUB_SCRATCH_MEM_SIZE (1024) /* Default indirect buffer size. */ -#define DMUB_IB_MEM_SIZE (2560) +#define DMUB_IB_MEM_SIZE (sizeof(struct dmub_fams2_config_v2)) /* Default LSDMA ring buffer size. */ #define DMUB_LSDMA_RB_SIZE (64 * 1024) @@ -87,6 +88,7 @@ static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; +struct dmub_srv_dcn42_regs dmub_srv_dcn42_regs; static inline uint32_t dmub_align(uint32_t val, uint32_t factor) { @@ -134,7 +136,7 @@ dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_ } static const struct dmub_fw_meta_info * -dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) +dmub_get_fw_meta_info(const struct dmub_srv_fw_meta_info_params *params) { const struct dmub_fw_meta_info *info = NULL; @@ -159,6 +161,46 @@ dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) return info; } +enum dmub_status +dmub_srv_get_fw_meta_info_from_raw_fw(struct dmub_srv_fw_meta_info_params *params, + struct dmub_fw_meta_info *fw_info_out) +{ + const struct dmub_fw_meta_info *fw_info = NULL; + uint32_t inst_const_size_temp = params->inst_const_size; + + /* First try custom psp footer size, if present */ + if (params->custom_psp_footer_size) { + params->inst_const_size -= params->custom_psp_footer_size; + fw_info = dmub_get_fw_meta_info(params); + if (fw_info) { + memcpy(fw_info_out, fw_info, sizeof(*fw_info)); + return DMUB_STATUS_OK; + } + params->inst_const_size = inst_const_size_temp; + } + + /* Try 256-byte psp footer size */ + params->inst_const_size -= PSP_FOOTER_BYTES_256; + fw_info = dmub_get_fw_meta_info(params); + if (fw_info) { + memcpy(fw_info_out, fw_info, sizeof(*fw_info)); + return DMUB_STATUS_OK; + } + + /* Try 512-byte psp footer size - final attempt */ + params->inst_const_size -= PSP_FOOTER_BYTES_256; // 256 bytes already subtracted, subtract 256 again + fw_info = dmub_get_fw_meta_info(params); + if (fw_info) { + memcpy(fw_info_out, fw_info, sizeof(*fw_info)); + return DMUB_STATUS_OK; + } + + /* Restore original inst_const_size and subtract default PSP footer size - default behaviour */ + params->inst_const_size = inst_const_size_temp - PSP_FOOTER_BYTES_256; + + return DMUB_STATUS_INVALID; +} + static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) { struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; @@ -370,6 +412,64 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; funcs->should_detect = dmub_dcn35_should_detect; break; + case DMUB_ASIC_DCN42: + dmub->regs_dcn42 = &dmub_srv_dcn42_regs; + funcs->configure_dmub_in_system_memory = dmub_dcn42_configure_dmub_in_system_memory; + funcs->send_inbox0_cmd = dmub_dcn42_send_inbox0_cmd; + funcs->clear_inbox0_ack_register = dmub_dcn42_clear_inbox0_ack_register; + funcs->read_inbox0_ack_register = dmub_dcn42_read_inbox0_ack_register; + funcs->reset = dmub_dcn42_reset; + funcs->reset_release = dmub_dcn42_reset_release; + funcs->backdoor_load = dmub_dcn42_backdoor_load; + funcs->backdoor_load_zfb_mode = dmub_dcn42_backdoor_load_zfb_mode; + funcs->setup_windows = dmub_dcn42_setup_windows; + funcs->setup_mailbox = dmub_dcn42_setup_mailbox; + funcs->get_inbox1_wptr = dmub_dcn42_get_inbox1_wptr; + funcs->get_inbox1_rptr = dmub_dcn42_get_inbox1_rptr; + funcs->set_inbox1_wptr = dmub_dcn42_set_inbox1_wptr; + funcs->setup_out_mailbox = dmub_dcn42_setup_out_mailbox; + funcs->get_outbox1_wptr = dmub_dcn42_get_outbox1_wptr; + funcs->set_outbox1_rptr = dmub_dcn42_set_outbox1_rptr; + funcs->is_supported = dmub_dcn42_is_supported; + funcs->is_hw_init = dmub_dcn42_is_hw_init; + funcs->set_gpint = dmub_dcn42_set_gpint; + funcs->is_gpint_acked = dmub_dcn42_is_gpint_acked; + funcs->get_gpint_response = dmub_dcn42_get_gpint_response; + funcs->get_gpint_dataout = dmub_dcn42_get_gpint_dataout; + funcs->get_fw_status = dmub_dcn42_get_fw_boot_status; + funcs->get_fw_boot_option = dmub_dcn42_get_fw_boot_option; + funcs->enable_dmub_boot_options = dmub_dcn42_enable_dmub_boot_options; + funcs->skip_dmub_panel_power_sequence = dmub_dcn42_skip_dmub_panel_power_sequence; + /*outbox0 call stacks*/ + funcs->setup_outbox0 = dmub_dcn42_setup_outbox0; + funcs->get_outbox0_wptr = dmub_dcn42_get_outbox0_wptr; + funcs->set_outbox0_rptr = dmub_dcn42_set_outbox0_rptr; + + funcs->get_current_time = dmub_dcn42_get_current_time; + funcs->get_diagnostic_data = dmub_dcn42_get_diagnostic_data; + funcs->get_preos_fw_info = dmub_dcn42_get_preos_fw_info; + + /*carried from dcn401*/ + funcs->send_reg_inbox0_cmd_msg = dmub_dcn42_send_reg_inbox0_cmd_msg; + funcs->read_reg_inbox0_rsp_int_status = dmub_dcn42_read_reg_inbox0_rsp_int_status; + funcs->read_reg_inbox0_cmd_rsp = dmub_dcn42_read_reg_inbox0_cmd_rsp; + funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn42_write_reg_inbox0_rsp_int_ack; + funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn42_clear_reg_inbox0_rsp_int_ack; + funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; + default_inbox_type = DMUB_CMD_INTERFACE_FB; /*still default to FB for now*/ + + funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn42_write_reg_outbox0_rdy_int_ack; + funcs->read_reg_outbox0_msg = dmub_dcn42_read_reg_outbox0_msg; + funcs->write_reg_outbox0_rsp = dmub_dcn42_write_reg_outbox0_rsp; + funcs->read_reg_outbox0_rdy_int_status = dmub_dcn42_read_reg_outbox0_rdy_int_status; + funcs->read_reg_outbox0_rsp_int_status = dmub_dcn42_read_reg_outbox0_rsp_int_status; + funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; + funcs->enable_reg_outbox0_rdy_int = dmub_dcn42_enable_reg_outbox0_rdy_int; + funcs->init_reg_offsets = dmub_srv_dcn42_regs_init; + + funcs->is_hw_powered_up = dmub_dcn42_is_hw_powered_up; + funcs->should_detect = dmub_dcn42_should_detect; + break; case DMUB_ASIC_DCN401: dmub->regs_dcn401 = &dmub_srv_dcn401_regs; @@ -524,7 +624,6 @@ enum dmub_status const struct dmub_srv_region_params *params, struct dmub_srv_region_info *out) { - const struct dmub_fw_meta_info *fw_info; uint32_t fw_state_size = DMUB_FW_STATE_SIZE; uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; @@ -538,14 +637,12 @@ enum dmub_status out->num_regions = DMUB_NUM_WINDOWS; - fw_info = dmub_get_fw_meta_info(params); - - if (fw_info) { - memcpy(&dmub->meta_info, fw_info, sizeof(*fw_info)); + if (params->fw_info) { + memcpy(&dmub->meta_info, params->fw_info, sizeof(*params->fw_info)); - fw_state_size = fw_info->fw_region_size; - trace_buffer_size = fw_info->trace_buffer_size; - shared_state_size = fw_info->shared_state_size; + fw_state_size = params->fw_info->fw_region_size; + trace_buffer_size = params->fw_info->trace_buffer_size; + shared_state_size = params->fw_info->shared_state_size; /** * If DM didn't fill in a version, then fill it in based on @@ -555,7 +652,7 @@ enum dmub_status * pass during creation. */ if (dmub->fw_version == 0) - dmub->fw_version = fw_info->fw_version; + dmub->fw_version = params->fw_info->fw_version; } window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; @@ -566,7 +663,7 @@ enum dmub_status window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = dmub_align(DMUB_SCRATCH_MEM_SIZE, 64); - window_sizes[DMUB_WINDOW_IB_MEM] = DMUB_IB_MEM_SIZE; + window_sizes[DMUB_WINDOW_IB_MEM] = dmub_align(DMUB_IB_MEM_SIZE, 64); window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); window_sizes[DMUB_WINDOW_LSDMA_BUFFER] = DMUB_LSDMA_RB_SIZE; window_sizes[DMUB_WINDOW_CURSOR_OFFLOAD] = dmub_align(sizeof(struct dmub_cursor_offload_v1), 64); @@ -672,8 +769,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, } } - dmub->fb_base = params->fb_base; - dmub->fb_offset = params->fb_offset; + memcpy(&dmub->soc_fb_info, ¶ms->soc_fb_info, sizeof(params->soc_fb_info)); dmub->psp_version = params->psp_version; if (dmub->hw_funcs.reset) diff --git a/drivers/gpu/drm/amd/display/include/bios_parser_types.h b/drivers/gpu/drm/amd/display/include/bios_parser_types.h index f40dc612ec73b..b5d97b394131b 100644 --- a/drivers/gpu/drm/amd/display/include/bios_parser_types.h +++ b/drivers/gpu/drm/amd/display/include/bios_parser_types.h @@ -93,6 +93,8 @@ enum bp_external_encoder_control_action { EXTERNAL_ENCODER_CONTROL_SETUP = 0xf, EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10, EXTERNAL_ENCODER_CONTROL_BLANK = 0x11, + EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT = 0x12, + EXTERNAL_ENCODER_CONTROL_DDC_SETUP = 0x14, }; enum bp_pipe_control_action { diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 8aea50aa95330..92510af1bd653 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -252,6 +252,7 @@ enum { #define AMDGPU_FAMILY_GC_11_0_0 145 #define AMDGPU_FAMILY_GC_11_0_1 148 #define AMDGPU_FAMILY_GC_11_5_0 150 +#define AMDGPU_FAMILY_GC_11_5_4 154 #define GC_11_0_0_A0 0x1 #define GC_11_0_2_A0 0x10 #define GC_11_0_3_A0 0x20 diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index a021d12acd741..d30eb24cf11e3 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -65,6 +65,7 @@ enum dce_version { DCN_VERSION_3_51, DCN_VERSION_3_6, DCN_VERSION_4_01, + DCN_VERSION_4_2, DCN_VERSION_MAX }; diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index 07b937b92efc7..4a8ca0ac12666 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -37,6 +37,21 @@ #ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h #define DP_PANEL_REPLAY_CAPABILITY 0x0b1 #endif /* DP_PANEL_REPLAY_CAPABILITY */ +#ifndef DP_PR_SU_X_GRANULARITY_LOW // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_SU_X_GRANULARITY_LOW 0x0b2 +#endif /* DP_PR_SU_X_GRANULARITY_LOW */ +#ifndef DP_PR_SU_X_GRANULARITY_HIGH // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_SU_X_GRANULARITY_HIGH 0x0b3 +#endif /* DP_PR_SU_X_GRANULARITY_HIGH */ +#ifndef DP_PR_SU_Y_GRANULARITY // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_SU_Y_GRANULARITY 0x0b4 +#endif /* DP_PR_SU_Y_GRANULARITY */ +#ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW 0x0b5 +#endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW */ +#ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH 0x0b6 +#endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH */ #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 // can remove this once the define gets into linux drm_dp_helper.h #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 0x1b0 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */ @@ -46,6 +61,24 @@ #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */ +#ifndef DP_PR_ERROR_STATUS // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_ERROR_STATUS 0x2020 /* DP 2.0 */ +#endif /* DP_PR_ERROR_STATUS */ +#ifndef DP_PR_REPLAY_SINK_STATUS // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_REPLAY_SINK_STATUS 0x2022 +#endif /* DP_PR_REPLAY_SINK_STATUS */ +#ifndef DP_PR_LINK_CRC_ERROR // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_LINK_CRC_ERROR (1 << 0) +#endif /* DP_PR_LINK_CRC_ERROR */ +#ifndef DP_PR_RFB_STORAGE_ERROR // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_RFB_STORAGE_ERROR (1 << 1) +#endif /* DP_PR_RFB_STORAGE_ERROR */ +#ifndef DP_PR_VSC_SDP_UNCORRECTABLE_ERROR // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ +#endif /* DP_PR_VSC_SDP_UNCORRECTABLE_ERROR */ +#ifndef DP_PR_ASSDP_MISSING_ERROR // can remove this once the define gets into linux drm_dp_helper.h +#define DP_PR_ASSDP_MISSING_ERROR (1 << 3) /* eDP 1.5 */ +#endif /* DP_PR_ASSDP_MISSING_ERROR */ enum dpcd_revision { DPCD_REV_10 = 0x10, @@ -188,11 +221,13 @@ enum dpcd_psr_sink_states { #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 #define DP_SOURCE_BACKLIGHT_CONTROL 0x32E #define DP_SOURCE_BACKLIGHT_ENABLE 0x32F +#define DP_SINK_DRR_GRANULARITY 0x33B #define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340 #define DP_SINK_PR_REPLAY_STATUS 0x378 #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A #define DP_SINK_EMISSION_RATE 0x37E +#define DP_SINK_PR_FRAME_SKIP_COUNT 0x337 /* Remove once drm_dp_helper.h is updated upstream */ #ifndef DP_TOTAL_LTTPR_CNT diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c index a71df052cf252..0f9e8a11df0d9 100644 --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c @@ -896,6 +896,7 @@ static void build_de_pq(struct pwl_float_data_ex *de_pq, uint32_t hw_points_num, const struct hw_x_point *coordinate_x) { + (void)coordinate_x; uint32_t i; struct fixed31_32 output; struct fixed31_32 *de_pq_table = mod_color_get_table(type_de_pq_table); @@ -1339,6 +1340,7 @@ static void scale_gamma_dx(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) { + (void)dividers; uint32_t i; struct fixed31_32 min = dc_fixpt_zero; struct fixed31_32 max = dc_fixpt_one; diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 1aae46d703ba0..b7e03dda700c8 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -114,6 +114,7 @@ static unsigned int calc_duration_in_us_from_v_total( const struct mod_vrr_params *in_vrr, unsigned int v_total) { + (void)in_vrr; unsigned int duration_in_us = (unsigned int)(div64_u64(((unsigned long long)(v_total) * 10000) * stream->timing.h_total, @@ -218,6 +219,7 @@ static void update_v_total_for_static_ramp( const struct dc_stream_state *stream, struct mod_vrr_params *in_out_vrr) { + (void)core_freesync; unsigned int v_total = 0; unsigned int current_duration_in_us = calc_duration_in_us_from_v_total( @@ -292,6 +294,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, unsigned int last_render_time_in_us, struct mod_vrr_params *in_out_vrr) { + (void)core_freesync; unsigned int inserted_frame_duration_in_us = 0; unsigned int mid_point_frames_ceil = 0; unsigned int mid_point_frames_floor = 0; @@ -447,6 +450,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, unsigned int last_render_time_in_us, struct mod_vrr_params *in_out_vrr) { + (void)core_freesync; bool update = false; unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us; @@ -545,6 +549,7 @@ static bool vrr_settings_require_update(struct core_freesync *core_freesync, unsigned int max_refresh_in_uhz, struct mod_vrr_params *in_vrr) { + (void)core_freesync; if (in_vrr->state != in_config->state) { return true; } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED && @@ -946,6 +951,7 @@ void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, struct dc_info_packet *infopacket, bool pack_sdp_v1_3) { + (void)mod_freesync; /* SPD info packet for FreeSync * VTEM info packet for HdmiVRR * Check if Freesync is supported. Return if false. If true, diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h index 26a351a184f33..d07387a961dd9 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h @@ -501,6 +501,7 @@ static inline void callback_in_ms(uint16_t time, struct mod_hdcp_output *output) static inline void set_watchdog_in_ms(struct mod_hdcp *hdcp, uint16_t time, struct mod_hdcp_output *output) { + (void)hdcp; output->watchdog_timer_needed = 1; output->watchdog_timer_delay = time; } diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h index 66dc9a19aebe5..ddd64b7e4c047 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_info_packet.h @@ -33,6 +33,12 @@ struct dc_stream_state; struct dc_info_packet; struct mod_vrr_params; +void set_vsc_packet_colorimetry_data( + const struct dc_stream_state *stream, + struct dc_info_packet *info_packet, + enum dc_color_space cs, + enum color_transfer_func tf); + void mod_build_vsc_infopacket(const struct dc_stream_state *stream, struct dc_info_packet *info_packet, enum dc_color_space cs, diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c index b3d55cac35694..00473c6284d5c 100644 --- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c +++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c @@ -42,6 +42,10 @@ enum vsc_packet_revision { vsc_packet_rev4 = 4, //05h = 3D stereo + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry Format vsc_packet_rev5 = 5, + //06h = 3D stereo + PR + Y-coordinate + vsc_packet_rev6 = 6, + //07h = 3D stereo + PR + Y-coordinate + Pixel Encoding/Colorimetry Format + vsc_packet_rev7 = 7, }; #define HDMI_INFOFRAME_TYPE_VENDOR 0x81 @@ -130,6 +134,163 @@ enum ColorimetryYCCDP { ColorimetryYCC_DP_ITU2020YCbCr = 7, }; +/* Helper function to set VSC packet colorimetry data */ +void set_vsc_packet_colorimetry_data( + const struct dc_stream_state *stream, + struct dc_info_packet *info_packet, + enum dc_color_space cs, + enum color_transfer_func tf) +{ + /* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs + * Data Bytes DB 18~16 + * Bits 3:0 (Colorimetry Format) | Bits 7:4 (Pixel Encoding) + * ---------------------------------------------------------------------------------------------------- + * 0x0 = sRGB | 0 = RGB + * 0x1 = RGB Wide Gamut Fixed Point + * 0x2 = RGB Wide Gamut Floating Point + * 0x3 = AdobeRGB + * 0x4 = DCI-P3 + * 0x5 = CustomColorProfile + * (others reserved) + * ---------------------------------------------------------------------------------------------------- + * 0x0 = ITU-R BT.601 | 1 = YCbCr444 + * 0x1 = ITU-R BT.709 + * 0x2 = xvYCC601 + * 0x3 = xvYCC709 + * 0x4 = sYCC601 + * 0x5 = AdobeYCC601 + * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc + * 0x7 = ITU-R BT.2020 Y'C'bC'r + * (others reserved) + * ---------------------------------------------------------------------------------------------------- + * 0x0 = ITU-R BT.601 | 2 = YCbCr422 + * 0x1 = ITU-R BT.709 + * 0x2 = xvYCC601 + * 0x3 = xvYCC709 + * 0x4 = sYCC601 + * 0x5 = AdobeYCC601 + * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc + * 0x7 = ITU-R BT.2020 Y'C'bC'r + * (others reserved) + * ---------------------------------------------------------------------------------------------------- + * 0x0 = ITU-R BT.601 | 3 = YCbCr420 + * 0x1 = ITU-R BT.709 + * 0x2 = xvYCC601 + * 0x3 = xvYCC709 + * 0x4 = sYCC601 + * 0x5 = AdobeYCC601 + * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc + * 0x7 = ITU-R BT.2020 Y'C'bC'r + * (others reserved) + * ---------------------------------------------------------------------------------------------------- + * 0x0 =DICOM Part14 Grayscale | 4 = Yonly + * Display Function + * (others reserved) + */ + unsigned int pixelEncoding = 0; + unsigned int colorimetryFormat = 0; + + /* Set Pixel Encoding */ + switch (stream->timing.pixel_encoding) { + case PIXEL_ENCODING_RGB: + pixelEncoding = 0x0; /* RGB = 0h */ + break; + case PIXEL_ENCODING_YCBCR444: + pixelEncoding = 0x1; /* YCbCr444 = 1h */ + break; + case PIXEL_ENCODING_YCBCR422: + pixelEncoding = 0x2; /* YCbCr422 = 2h */ + break; + case PIXEL_ENCODING_YCBCR420: + pixelEncoding = 0x3; /* YCbCr420 = 3h */ + break; + default: + pixelEncoding = 0x0; /* default RGB = 0h */ + break; + } + + /* Set Colorimetry format based on pixel encoding */ + switch (stream->timing.pixel_encoding) { + case PIXEL_ENCODING_RGB: + if ((cs == COLOR_SPACE_SRGB) || + (cs == COLOR_SPACE_SRGB_LIMITED)) + colorimetryFormat = ColorimetryRGB_DP_sRGB; + else if (cs == COLOR_SPACE_ADOBERGB) + colorimetryFormat = ColorimetryRGB_DP_AdobeRGB; + else if ((cs == COLOR_SPACE_2020_RGB_FULLRANGE) || + (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE)) + colorimetryFormat = ColorimetryRGB_DP_ITU_R_BT2020RGB; + break; + + case PIXEL_ENCODING_YCBCR444: + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR420: + /* Note: xvYCC probably not supported correctly here on DP since colorspace translation + * loses distinction between BT601 vs xvYCC601 in translation + */ + if (cs == COLOR_SPACE_YCBCR601) + colorimetryFormat = ColorimetryYCC_DP_ITU601; + else if (cs == COLOR_SPACE_YCBCR709) + colorimetryFormat = ColorimetryYCC_DP_ITU709; + else if (cs == COLOR_SPACE_ADOBERGB) + colorimetryFormat = ColorimetryYCC_DP_AdobeYCC; + else if (cs == COLOR_SPACE_2020_YCBCR_LIMITED) + colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr; + + if (cs == COLOR_SPACE_2020_YCBCR_LIMITED && tf == TRANSFER_FUNC_GAMMA_22) + colorimetryFormat = ColorimetryYCC_DP_ITU709; + break; + + default: + colorimetryFormat = ColorimetryRGB_DP_sRGB; + break; + } + + info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat; + + /* Set color depth */ + switch (stream->timing.display_color_depth) { + case COLOR_DEPTH_666: + /* NOTE: This is actually not valid for YCbCr pixel encoding to have 6 bpc + * as of DP1.4 spec, but value of 0 probably reserved here for potential future use. + */ + info_packet->sb[17] = 0; + break; + case COLOR_DEPTH_888: + info_packet->sb[17] = 1; + break; + case COLOR_DEPTH_101010: + info_packet->sb[17] = 2; + break; + case COLOR_DEPTH_121212: + info_packet->sb[17] = 3; + break; + /*case COLOR_DEPTH_141414: -- NO SUCH FORMAT IN DP SPEC */ + case COLOR_DEPTH_161616: + info_packet->sb[17] = 4; + break; + default: + info_packet->sb[17] = 0; + break; + } + + /* all YCbCr are always limited range */ + if ((cs == COLOR_SPACE_SRGB_LIMITED) || + (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE) || + (pixelEncoding != 0x0)) { + info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */ + } + + /* Content Type (Bits 2:0) + * 0 = Not defined. + * 1 = Graphics. + * 2 = Photo. + * 3 = Video. + * 4 = Game. + */ + info_packet->sb[18] = 0; +} + void mod_build_vsc_infopacket(const struct dc_stream_state *stream, struct dc_info_packet *info_packet, enum dc_color_space cs, @@ -137,8 +298,6 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, { unsigned int vsc_packet_revision = vsc_packet_undefined; unsigned int i; - unsigned int pixelEncoding = 0; - unsigned int colorimetryFormat = 0; bool stereo3dSupport = false; if (stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE && stream->view_format != VIEW_3D_FORMAT_NONE) { @@ -158,12 +317,38 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, if (stream->use_vsc_sdp_for_colorimetry) vsc_packet_revision = vsc_packet_rev5; + /* Check for Panel Replay (highest priority) */ + if (stream->link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) + vsc_packet_revision = stream->use_vsc_sdp_for_colorimetry ? vsc_packet_rev7 : vsc_packet_rev6; + /* VSC packet not needed based on the features * supported by this DP display */ if (vsc_packet_revision == vsc_packet_undefined) return; + if (vsc_packet_revision == vsc_packet_rev6) { + /* Secondary-data Packet ID = 0*/ + info_packet->hb0 = 0x00; + /* 07h - Packet Type Value indicating Video + * Stream Configuration packet + */ + info_packet->hb1 = 0x07; + /* 06h = VSC SDP supporting 3D stereo + PR + */ + info_packet->hb2 = 0x06; + /* 0Eh = VSC SDP supporting 3D stereo + PR + * (HB2 = 06h), with Y-coordinate of first scan + * line of the SU region + */ + info_packet->hb3 = 0x10; + + for (i = 0; i < 28; i++) + info_packet->sb[i] = 0; + + info_packet->valid = true; + } + if (vsc_packet_revision == vsc_packet_rev4) { /* Secondary-data Packet ID = 0*/ info_packet->hb0 = 0x00; @@ -292,152 +477,22 @@ void mod_build_vsc_infopacket(const struct dc_stream_state *stream, info_packet->valid = true; - /* Set VSC SDP fields for pixel encoding and colorimetry format from DP 1.3 specs - * Data Bytes DB 18~16 - * Bits 3:0 (Colorimetry Format) | Bits 7:4 (Pixel Encoding) - * ---------------------------------------------------------------------------------------------------- - * 0x0 = sRGB | 0 = RGB - * 0x1 = RGB Wide Gamut Fixed Point - * 0x2 = RGB Wide Gamut Floating Point - * 0x3 = AdobeRGB - * 0x4 = DCI-P3 - * 0x5 = CustomColorProfile - * (others reserved) - * ---------------------------------------------------------------------------------------------------- - * 0x0 = ITU-R BT.601 | 1 = YCbCr444 - * 0x1 = ITU-R BT.709 - * 0x2 = xvYCC601 - * 0x3 = xvYCC709 - * 0x4 = sYCC601 - * 0x5 = AdobeYCC601 - * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc - * 0x7 = ITU-R BT.2020 Y'C'bC'r - * (others reserved) - * ---------------------------------------------------------------------------------------------------- - * 0x0 = ITU-R BT.601 | 2 = YCbCr422 - * 0x1 = ITU-R BT.709 - * 0x2 = xvYCC601 - * 0x3 = xvYCC709 - * 0x4 = sYCC601 - * 0x5 = AdobeYCC601 - * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc - * 0x7 = ITU-R BT.2020 Y'C'bC'r - * (others reserved) - * ---------------------------------------------------------------------------------------------------- - * 0x0 = ITU-R BT.601 | 3 = YCbCr420 - * 0x1 = ITU-R BT.709 - * 0x2 = xvYCC601 - * 0x3 = xvYCC709 - * 0x4 = sYCC601 - * 0x5 = AdobeYCC601 - * 0x6 = ITU-R BT.2020 Y'cC'bcC'rc - * 0x7 = ITU-R BT.2020 Y'C'bC'r - * (others reserved) - * ---------------------------------------------------------------------------------------------------- - * 0x0 =DICOM Part14 Grayscale | 4 = Yonly - * Display Function - * (others reserved) - */ - - /* Set Pixel Encoding */ - switch (stream->timing.pixel_encoding) { - case PIXEL_ENCODING_RGB: - pixelEncoding = 0x0; /* RGB = 0h */ - break; - case PIXEL_ENCODING_YCBCR444: - pixelEncoding = 0x1; /* YCbCr444 = 1h */ - break; - case PIXEL_ENCODING_YCBCR422: - pixelEncoding = 0x2; /* YCbCr422 = 2h */ - break; - case PIXEL_ENCODING_YCBCR420: - pixelEncoding = 0x3; /* YCbCr420 = 3h */ - break; - default: - pixelEncoding = 0x0; /* default RGB = 0h */ - break; - } - - /* Set Colorimetry format based on pixel encoding */ - switch (stream->timing.pixel_encoding) { - case PIXEL_ENCODING_RGB: - if ((cs == COLOR_SPACE_SRGB) || - (cs == COLOR_SPACE_SRGB_LIMITED)) - colorimetryFormat = ColorimetryRGB_DP_sRGB; - else if (cs == COLOR_SPACE_ADOBERGB) - colorimetryFormat = ColorimetryRGB_DP_AdobeRGB; - else if ((cs == COLOR_SPACE_2020_RGB_FULLRANGE) || - (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE)) - colorimetryFormat = ColorimetryRGB_DP_ITU_R_BT2020RGB; - break; - - case PIXEL_ENCODING_YCBCR444: - case PIXEL_ENCODING_YCBCR422: - case PIXEL_ENCODING_YCBCR420: - /* Note: xvYCC probably not supported correctly here on DP since colorspace translation - * loses distinction between BT601 vs xvYCC601 in translation - */ - if (cs == COLOR_SPACE_YCBCR601) - colorimetryFormat = ColorimetryYCC_DP_ITU601; - else if (cs == COLOR_SPACE_YCBCR709) - colorimetryFormat = ColorimetryYCC_DP_ITU709; - else if (cs == COLOR_SPACE_ADOBERGB) - colorimetryFormat = ColorimetryYCC_DP_AdobeYCC; - else if (cs == COLOR_SPACE_2020_YCBCR_LIMITED) - colorimetryFormat = ColorimetryYCC_DP_ITU2020YCbCr; - - if (cs == COLOR_SPACE_2020_YCBCR_LIMITED && tf == TRANSFER_FUNC_GAMMA_22) - colorimetryFormat = ColorimetryYCC_DP_ITU709; - break; - - default: - colorimetryFormat = ColorimetryRGB_DP_sRGB; - break; - } - - info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat; + set_vsc_packet_colorimetry_data(stream, info_packet, cs, tf); + } - /* Set color depth */ - switch (stream->timing.display_color_depth) { - case COLOR_DEPTH_666: - /* NOTE: This is actually not valid for YCbCr pixel encoding to have 6 bpc - * as of DP1.4 spec, but value of 0 probably reserved here for potential future use. - */ - info_packet->sb[17] = 0; - break; - case COLOR_DEPTH_888: - info_packet->sb[17] = 1; - break; - case COLOR_DEPTH_101010: - info_packet->sb[17] = 2; - break; - case COLOR_DEPTH_121212: - info_packet->sb[17] = 3; - break; - /*case COLOR_DEPTH_141414: -- NO SUCH FORMAT IN DP SPEC */ - case COLOR_DEPTH_161616: - info_packet->sb[17] = 4; - break; - default: - info_packet->sb[17] = 0; - break; - } + if (vsc_packet_revision == vsc_packet_rev7) { + /* Secondary-data Packet ID = 0 */ + info_packet->hb0 = 0x00; + /* 07h - Packet Type Value indicating Video Stream Configuration packet */ + info_packet->hb1 = 0x07; + /* 07h = VSC SDP supporting 3D stereo, PR, and Pixel Encoding/Colorimetry Format indication. */ + info_packet->hb2 = 0x07; + /* 13h = VSC SDP supporting 3D stereo, + PR, + Pixel Encoding/Colorimetry Format indication (HB2 = 07h). */ + info_packet->hb3 = 0x13; - /* all YCbCr are always limited range */ - if ((cs == COLOR_SPACE_SRGB_LIMITED) || - (cs == COLOR_SPACE_2020_RGB_LIMITEDRANGE) || - (pixelEncoding != 0x0)) { - info_packet->sb[17] |= 0x80; /* DB17 bit 7 set to 1 for CEA timing. */ - } + info_packet->valid = true; - /* Content Type (Bits 2:0) - * 0 = Not defined. - * 1 = Graphics. - * 2 = Photo. - * 3 = Video. - * 4 = Game. - */ - info_packet->sb[18] = 0; + set_vsc_packet_colorimetry_data(stream, info_packet, cs, tf); } } @@ -537,7 +592,11 @@ void mod_build_adaptive_sync_infopacket(const struct dc_stream_state *stream, break; case FREESYNC_TYPE_PCON_IN_WHITELIST: case ADAPTIVE_SYNC_TYPE_EDP: - mod_build_adaptive_sync_infopacket_v1(info_packet); + if (stream && stream->link->replay_settings.config.replay_supported && + stream->link->replay_settings.config.replay_version == DC_VESA_PANEL_REPLAY) + mod_build_adaptive_sync_infopacket_v2(stream, param, info_packet); + else + mod_build_adaptive_sync_infopacket_v1(info_packet); break; case ADAPTIVE_SYNC_TYPE_NONE: case FREESYNC_TYPE_PCON_NOT_IN_WHITELIST: @@ -567,13 +626,15 @@ void mod_build_adaptive_sync_infopacket_v2(const struct dc_stream_state *stream, info_packet->hb2 = AS_SDP_VER_2; info_packet->hb3 = AS_DP_SDP_LENGTH; - //Payload - info_packet->sb[0] = param->supportMode; //1: AVT; 0: FAVT - info_packet->sb[1] = (stream->timing.v_total & 0x00FF); - info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8; - //info_packet->sb[3] = 0x00; Target RR, not use fot AVT - info_packet->sb[4] = (param->increase.support << 6 | param->decrease.support << 7); - info_packet->sb[5] = param->increase.frame_duration_hex; - info_packet->sb[6] = param->decrease.frame_duration_hex; + if (param) { + //Payload + info_packet->sb[0] = param->supportMode; //1: AVT; 0: FAVT + info_packet->sb[1] = (stream->timing.v_total & 0x00FF); + info_packet->sb[2] = (stream->timing.v_total & 0xFF00) >> 8; + //info_packet->sb[3] = 0x00; Target RR, not use fot AVT + info_packet->sb[4] = (param->increase.support << 6 | param->decrease.support << 7); + info_packet->sb[5] = param->increase.frame_duration_hex; + info_packet->sb[6] = param->decrease.frame_duration_hex; + } } diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c index fd139b219bf9a..df3b8383b06de 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c @@ -984,7 +984,13 @@ void set_replay_frame_skip_number(struct dc_link *link, uint32_t *frame_skip_number_array = NULL; uint32_t frame_skip_number = 0; - if (link == NULL || flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0) + if (link == NULL) + return; + + if (false == link->replay_settings.config.frame_skip_supported) + return; + + if (flicker_free_refresh_rate_mhz == 0 || coasting_vtotal_refresh_rate_mhz == 0) return; if (is_defer) diff --git a/drivers/gpu/drm/amd/dkms/Kbuild b/drivers/gpu/drm/amd/dkms/Kbuild new file mode 100644 index 0000000000000..96a6424ce8378 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Kbuild @@ -0,0 +1,88 @@ +ifeq ($(CC), gcc) +GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) +GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) +# CONFIG_GCC_VERSION returns x.xx.xx as the version format +GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) + +KERNEL_MAJ=$(VERSION) +KERNEL_PATCHLEVEL=$(PATCHLEVEL) +KERNEL_SUBLEVEL=$(SUBLEVEL) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) + +kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +ifdef CONFIG_CC_IS_GCC +ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) +$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") +$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") +endif +else +export CONFIG_CC_IS_GCC=y +export CONFIG_GCC_VERSION=$(GCCSTR) +$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") +endif + +endif + +include $(src)/amd/dkms/dkms-config.mk + +_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) +LINUX_SRCTREE_INCLUDE := \ + $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) + +# In the peerdirect m4, we determine if the p2p symbols are in the ofa_kernel's Module.symvers +# If so, we need to include the path for the function pointers, as well as the include path for +# rdma/peer_mem.h, since the ofa_kernel isn't integrated into the base kernel in that configuration +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(call _is_kcl_macro_defined,HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH),y) +KBUILD_EXTRA_SYMBOLS += /usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/Module.symvers +USER_INCLUDE += -I/usr/src/ofa_kernel/x86_64/$(KERNELRELEASE)/include +endif + +LINUXINCLUDE := \ + -I$(src)/include \ + -I$(src)/include/kcl/header \ + -include $(src)/include/kcl/kcl_version.h \ + -include $(src)/include/rename_symbol.h \ + -include $(src)/amd/dkms/config/config.h \ + $(LINUX_SRCTREE_INCLUDE) \ + -I$(src)/include/uapi \ + $(USER_INCLUDE) + +export CONFIG_DRM_TTM=m +export CONFIG_DRM_AMDGPU=m +export CONFIG_DRM_SCHED=m + +subdir-ccflags-y += -Wno-error + +# Trying to enable DCN2/3 with core2 optimizations will result in +# older versions of GCC hanging during building/installing. Check +# if the compiler is using core2 optimizations and only build DCN2/3 +# if core2 isn't in the compiler flags +ifndef CONFIG_ARM64 + ifeq ($(CC), clang) + export CONFIG_DRM_AMD_DC_FP=y + subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP + else ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) + export CONFIG_DRM_AMD_DC_FP=y + subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP + endif +endif + +# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) +# Upstream patches now uses gnu11/gnu99 as the default C standard version. +# However, gcc in legacy OS still uses gnu89, which will introduce a standard +# build gap leading to a DKMS build failure possibly. So add below check to +# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. +ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) +KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) +$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +endif + +include $(src)/amd/dkms/Makefile.drm_ttm_helper +include $(src)/amd/dkms/Makefile.drm_exec +include $(src)/amd/dkms/Makefile.drm_buddy + +obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile new file mode 100644 index 0000000000000..7a9682c51f0c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -0,0 +1,75 @@ +ifneq ($(KERNELRELEASE),) +include $(src)/amd/dkms/Kbuild +else +KERNELVER := $(shell uname -r) +kernel_build_dir := /lib/modules/$(KERNELVER)/build +module_src_dir := $(CURDIR) +module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) +module_build_flags := +num_cpu_cores := $(shell which nproc > /dev/null && nproc || echo "1") +CC := gcc +Q := @ + +ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) +$(error "invalid kernel obj dir, is kernel-devel installed?") +endif + +.PHONY: modules sanity-check pre-build clean +modules: + +include $(kernel_build_dir)/include/config/auto.conf + +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU_AMDKCL)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + +ifneq ($(CONFIG_CC_IS_CLANG),) +ifeq ($(shell command -v clang > /dev/null && echo "y"),) +$(error "clang is not installed, exit...") +endif +ifeq ($(shell command -v ld.lld > /dev/null && echo "y"),) +$(error "ld.lld is not installed, exit...") +endif + +CC := clang +module_build_flags += CC=clang +module_build_flags += LD=ld.lld +module_build_flags += LLVM=1 +endif + +dkms-config ?= amd/dkms/dkms-config.mk +config-file ?= amd/dkms/config/config.h +rename_header ?= include/rename_symbol.h +KCL_MACRO_CHECK_COMMAND=$(shell grep $(1) $(config-file) | grep -q "define" && echo "y") + +modules: sanity-check $(dkms-config) + $(Q)$(shell cat $(module_build_dir)/.env) make -j$(num_cpu_cores) \ + TTM_NAME=amdttm \ + SCHED_NAME=amd-sched \ + -C $(kernel_build_dir) \ + M=$(module_build_dir) $(module_build_flags) + $(Q)amd/dkms/post-build.sh $(module_build_dir) + +sanity-check: pre-build $(config-file) $(rename_header) + $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_DMA_RESV_SEQ_BUG), $(error dma_resv->seq is missing. exit...)) + $(if $(call KCL_MACRO_CHECK_COMMAND, HAVE_RESERVATION_WW_CLASS_BUG), $(error reservation_ww_class is missing. exit...)) + +$(dkms-config): pre-build + $(Q)amd/dkms/dkms-config.sh $@ $(KERNELVER) $(CC) + +pre-build: + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(module_build_dir) $(CC) + +clean: + $(Q)echo "Cleaning build files..." + $(Q)make -C $(kernel_build_dir) M=$(module_src_dir) clean + $(Q)rm -f $(dkms-config) $(config-file) $(rename_header) +endif diff --git a/drivers/gpu/drm/amd/dkms/Makefile.compiler b/drivers/gpu/drm/amd/dkms/Makefile.compiler new file mode 100644 index 0000000000000..9c546ebcbee5a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.compiler @@ -0,0 +1,3 @@ +ifndef gcc-min-version +gcc-min-version = $(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config new file mode 100644 index 0000000000000..211fd393987e3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -0,0 +1,21 @@ +dkmstree := drivers/gpu/drm/amd/dkms +srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) + +all: config clean + +config: force + @( \ + cd $(srctree)/$(dkmstree); \ + ./autogen.sh; \ + ./configure \ + --enable-linux-builtin \ + --with-linux=$(srctree) \ + ) + +clean: force + @( \ + cd $(srctree)/$(dkmstree); \ + rm -rf aclocal.m4 config.* configure config/*.in* build_*\ + ) + +.PHONY: all force diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy new file mode 100644 index 0000000000000..6af49f111bc9c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy @@ -0,0 +1,7 @@ +export CONFIG_DRM_BUDDY=m + +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -include $(src)/amd/dkms/backport_drm_buddy.h \ + -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_exec b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec new file mode 100644 index 0000000000000..2177496115aa2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_exec @@ -0,0 +1,7 @@ +export CONFIG_DRM_EXEC=m + +subdir-ccflags-y += -DCONFIG_DRM_EXEC +CFLAGS_drm_exec.o += -include $(src)/amd/dkms/backport_drm_exec.h \ + -include linux/module.h -DHAVE_CONFIG_H +amddrm_exec-y := drm_exec.o +obj-$(CONFIG_DRM_EXEC) += amddrm_exec.o diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper new file mode 100644 index 0000000000000..b76db38d020a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper @@ -0,0 +1,8 @@ +export CONFIG_DRM_TTM_HELPER=m + +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh new file mode 100755 index 0000000000000..d72f86b5a2f97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +autoreconf -fiv +[[ $? -eq 0 ]] || exit $? +rm -Rf autom4te.cache diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h new file mode 100644 index 0000000000000..32e17b11c0a7b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/backport_drm_buddy.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_DRM_BUDDY_H +#define _KCL_BACKPORT_DRM_BUDDY_H + +#include +#include +#include + +#endif diff --git a/drivers/gpu/drm/amd/dkms/backport_drm_exec.h b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h new file mode 100644 index 0000000000000..5a0c2434244c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/backport_drm_exec.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_DRM_EXEC_H +#define _KCL_BACKPORT_DRM_EXEC_H + +#include +#include +#include +#include +#include +#include + +#endif diff --git a/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk b/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk new file mode 100644 index 0000000000000..9968b0a30aa2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/cmd_mod_fix.mk @@ -0,0 +1,27 @@ +# Fix E2BIG/ENAMETOOLONG for amdgpu on kernels < 5.19: use $(file) instead +# of shell echo in cmd_mod, and write one .o per line in .mod files. +# +# $(subst $(space),$(newline),...) inside $(file) silently drops newlines, +# so we use $(file >) for the first entry and $(file >>) for the rest. + +ifndef _amdgpu_cmd_mod_fix_included +_amdgpu_cmd_mod_fix_included := 1 + +_kbuild_makefile_build := $(srctree)/scripts/Makefile.build +_cmd_mod_needs_fix := $(shell grep -q 'cmd_mod = printf' $(_kbuild_makefile_build) 2>/dev/null || echo 1) + +ifeq ($(_cmd_mod_needs_fix),1) + +_amdgpu_mod_objs = $(sort $(strip $(if $($*-objs)$($*-y)$($*-m),$(addprefix $(obj)/,$($*-objs) $($*-y) $($*-m)),$(@:.mod=.o)))) + +override quiet_cmd_mod = MOD $@ +override cmd_mod = $(file >$@,$(firstword $(_amdgpu_mod_objs))) \ + $(foreach o,$(wordlist 2,$(words $(_amdgpu_mod_objs)),$(_amdgpu_mod_objs)),$(file >>$@,$(o))) \ + true $(if $(cmd_undef_syms),; $(cmd_undef_syms)) + +override quiet_cmd_link_multi-m = LD [M] $@ +override cmd_link_multi-m = $(file >$@.args, $(filter %.o,$^)) \ + $(LD) $(ld_flags) -r -o $@ @$@.args + +endif +endif diff --git a/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h new file mode 100644 index 0000000000000..9ff8bd1cb6a04 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h @@ -0,0 +1,3 @@ +/* + * This file is managed by DKMS build. Do not edit. + */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h new file mode 100644 index 0000000000000..c55660f6ad4e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -0,0 +1,1354 @@ +/* config/config.h. Generated from config.h.in by configure. */ +/* config/config.h.in. Generated from configure.ac by autoheader. */ + +/* whether invalidate_range_start() wants 2 args */ +#define HAVE_2ARGS_INVALIDATE_RANGE_START 1 + +/* whether invalidate_range_start() wants 5 args */ +/* #undef HAVE_5ARGS_INVALIDATE_RANGE_START */ + +/* whether access_ok(x, x) is available */ +#define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 + +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 + +/* acpi_put_table() is available */ +#define HAVE_ACPI_PUT_TABLE 1 + +/* struct acpi_srat_generic_affinity is available */ +#define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + +/* acpi_video_backlight_use_native() is available */ +#define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 + +/* acpi_video_register_backlight() is available */ +#define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 + +/* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ +#define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 + +/* *FLAGS_.o support to take the path relative to $(obj) */ +#define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 + +/* hmm support is enabled */ +#define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 + +/* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ +/* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ + +/* amd_iommu_pc_get_max_banks() declared */ +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED */ + +/* amd_iommu_pc_get_max_banks() arg is unsigned int */ +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ + +/* amd_iommu_pc_supported() is available */ +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ + +/* aperture_remove_conflicting_pci_device() is available */ +#define HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES 1 + +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 + +/* arch_io_{reserve/free}_memtype_wc() are available */ +#define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_FPU_API_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_SET_MEMORY_H 1 + +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + +/* bin_attrs in struct attribute_group is const */ +#define HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW 1 + +/* bin_attribute.read is const args */ +#define HAVE_BIN_ATTR_CONST_ARGS 1 + +/* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ +#define HAVE_BITMAP_FUNCS 1 + +/* bitmap_read() is available */ +#define HAVE_BITMAP_READ 1 + +/* bitmap_to_arr32() is available */ +#define HAVE_BITMAP_TO_ARR32 1 + +/* struct block_device has member named 'bd_device' */ +#define HAVE_BLOCK_DEVICE_BD_DEVICE 1 + +/* cancel_work() is available */ +#define HAVE_CANCEL_WORK 1 + +/* struct cec_connector_info is available */ +#define HAVE_CEC_CONNECTOR_INFO 1 + +/* cec_notifier_conn_register() is available */ +#define HAVE_CEC_NOTIFIER_CONN_REGISTER 1 + +/* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ +#define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 + +/* compat_ptr_ioctl() is available */ +#define HAVE_COMPAT_PTR_IOCTL 1 + +/* need a const argument in member func .is_bin_visible */ +#define HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE 1 + +/* cpuinfo_x86.topo is available */ +#define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 + +/* drm_edid_raw() is available */ +#define HAVE_CRTC_DRM_VBLANK_CRTC 1 + +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 + +/* devcgroup_check_permission() is available */ +#define HAVE_DEVCGROUP_CHECK_PERMISSION 1 + +/* MEMORY_DEVICE_COHERENT is availablea */ +#define HAVE_DEVICE_COHERENT 1 + +/* devm_i2c_add_adapter() is available */ +#define HAVE_DEVM_I2C_ADD_ADAPTER 1 + +/* dev_is_removable() is available */ +#define HAVE_DEV_IS_REMOVABLE 1 + +/* dev_pagemap_ops has folio_free member */ +#define HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE 1 + +/* dev_pagemap->owner is available */ +#define HAVE_DEV_PAGEMAP_OWNER 1 + +/* there is 'range' field within dev_pagemap structure */ +#define HAVE_DEV_PAGEMAP_RANGE 1 + +/* dma_buf_is_dynamic() is available */ +#define HAVE_DMA_BUF_IS_DYNAMIC 1 + +/* dma_buf->dynamic_mapping is available */ +/* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ + +/* dma_buf->dynamic_mapping is not available */ +/* #undef HAVE_DMA_BUF_OPS_LEGACY */ + +/* dma_fence_array_first() is available */ +#define HAVE_DMA_FENCE_ARRAY_FIRST 1 + +/* dma_fence_chain_alloc() is available */ +#define HAVE_DMA_FENCE_CHAIN_ALLOC 1 + +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + +/* dma_fence_check_and_signal() is available */ +#define HAVE_DMA_FENCE_CHECK_AND_SIGNAL 1 + +/* dma_fence_dedup_array() is available */ +#define HAVE_DMA_FENCE_DEDUP_ARRAY 1 + +/* dma_fence_unwrap_merge() is available */ +#define HAVE_DMA_FENCE_UNWRAP_MERGE 1 + +/* dma_fence_describe() is available */ +#define HAVE_DMA_FENCE_DESCRIBE 1 + +/* dma_fence_init64() is available */ +#define HAVE_DMA_FENCE_INIT64 1 + +/* dma_fence_is_container() is available */ +#define HAVE_DMA_FENCE_IS_CONTAINER 1 + +/* dma_fence_is_later_or_same() is available */ +#define HAVE_DMA_FENCE_IS_LATER_OR_SAME 1 + +/* struct dma_fence_ops has callback set_deadline */ +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 + +/* struct dma_fence_ops has use_64bit_seqno field */ +/* #undef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO */ + +/* test whether dma_fence_begin_signalling are available */ +#define HAVE_DMA_FENCE_SIGNALLING 1 + +/* dma_fence_TIMESTAMP() is available */ +#define HAVE_DMA_FENCE_TIMESTAMP 1 + +/* dma_map_sgtable() is enabled */ +#define HAVE_DMA_MAP_SGTABLE 1 + +/* dma_resv->fences is available */ +#define HAVE_DMA_RESV_FENCES 1 + +/* dma_resv->seq is available */ +/* #undef HAVE_DMA_RESV_SEQ */ + +/* dma_resv->seq is seqcount_ww_mutex_t */ +/* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ + +/* Reporting dma_resv->seq bug */ +/* #undef HAVE_DMA_RESV_SEQ_BUG */ + +/* down_read_killable() is available */ +#define HAVE_DOWN_READ_KILLABLE 1 + +/* drmm_cgroup_register_region() is available */ +#define HAVE_DRMM_CGROUP_REGISTER_REGION 1 + +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_AMDGPU_PCIID_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_AMD_ASIC_TYPE_H 1 + +/* drm_aperture_remove_conflicting_pci_framebuffers() second arg is + drm_driver* */ +/* #undef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ + +/* drm_atomic_helper_calc_timestamping_constants() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 + +/* drm_atomic_plane_enabling() is available */ +#define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 + +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H 1 + +/* drm_client_dev_resume() is available */ +#define HAVE_DRM_CLIENT_DEV_RESUME 1 + +/* drm_client_register() is available */ +#define HAVE_DRM_CLIENT_REGISTER 1 + +/* drm_client_setup() is available */ +#define HAVE_DRM_CLIENT_SETUP 1 + +/* struct drm_color_ctm_3x4 is available */ +#define HAVE_DRM_COLOR_CTM_3X4 1 + +/* drm_color_lut32_extract() is available */ +#define HAVE_DRM_COLOR_LUT32_EXTRACT 1 + +/* drm_color_lut32_size() is available */ +#define HAVE_DRM_COLOR_LUT32_SIZE 1 + +/* drm_connector_atomic_hdr_metadata_equal() is available */ +#define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 + +/* drm_connector_attach_hdr_output_metadata_property() is available */ +#define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 + +/* drm_connector_dynamic_init is available */ +#define HAVE_DRM_CONNECTOR_DYNAMIC_INIT 1 + +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + +/* drm_connector->eld_mutex is available */ +#define HAVE_DRM_CONNECTOR_ELD_MUTEX 1 + +/* drm_connector_for_each_possible_encoder() wants 2 arguments */ +#define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 + +/* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state + */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state + arg */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* .mode_valid need a const drm_display_mode argument */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT 1 + +/* drm_connector_helper_funcs->prepare_writeback_job is available */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB 1 + +/* drm_connector_init_with_ddc() is available */ +#define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 + +/* drm_connector_set_panel_orientation_with_quirk() is available */ +#define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 + +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + +/* struct drm_connector_state has hdcp_content_type member */ +#define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 + +/* drm_connector_state->hdmi.broadcast_rgb is available */ +#define HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB 1 + +/* struct drm_connector_state has hdr_output_metadata member */ +#define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 + +/* drm_connector_update_privacy_screen() is available */ +#define HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN 1 + +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 + +/* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants + struct drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct + drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 + +/* drm_crtc_helper_mode_valid_fixed() is available */ +#define HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED 1 + +/* drm_dbg_printer() is available */ +#define HAVE_DRM_DBG_PRINTER 1 + +/* enum drm_debug_category is available */ +#define HAVE_DRM_DEBUG_CATEGORY 1 + +/* drm_debug_enabled() is available */ +#define HAVE_DRM_DEBUG_ENABLED 1 + +/* drm_device->open_count is int */ +/* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ + +/* struct drm_device has pdev member */ +/* #undef HAVE_DRM_DEVICE_PDEV */ + +/* drm_dev_wedged_event() is available */ +#define HAVE_DRM_DEV_WEDGED_EVENT 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 + +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H 1 + +/* display_info->edid_hdmi_rgb444_dc_modes is available */ +#define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 + +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 + +/* display_info->luminance_range is available */ +#define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 + +/* display_info->max_dsc_bpp is available */ +#define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 + +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + +/* struct drm_display_info->source_physical_address is available */ +#define HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS 1 + +/* drm_dp_add_payload_part2 has three arguments */ +/* #undef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS */ + +/* drm_dp_atomic_find_time_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 + +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ + +/* drm_dp_atomic_release_time_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS 1 + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is + available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ + +/* drm_dp_mst_atomic_setup_commit() is available */ +#define HAVE_DRM_DP_ATOMIC_SETUP_COMMIT 1 + +/* drm_dp_mst_atomic_wait_for_dependencies() is available */ +#define HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES 1 + +/* drm_dp_aux->dpcd_probe_disabled is available */ +#define HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED 1 + +/* struct drm_dp_aux has member named 'drm_dev' */ +#define HAVE_DRM_DP_AUX_DRM_DEV 1 + +/* drm_dp_calc_pbn_mode() wants 3 args */ +/* #undef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS */ + +/* drm_dp_cec_attach() is available */ +#define HAVE_DRM_DP_CEC_ATTACH 1 + +/* drm_dp_cec_register_connector() wants p,p interface */ +#define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ + +/* drm_dp_link_train_channel_eq_delay() has 2 args */ +#define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 + +/* drm_dp_link_train_clock_recovery_delay() has 2 args */ +#define HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS 1 + +/* drm_dp_mst_add_affected_dsc_crtcs() is available */ +#define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 + +/* drm_dp_mst_atomic_check() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_CHECK 1 + +/* drm_dp_mst_atomic_enable_dsc() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 + +/* drm_dp_mst_atomic_enable_dsc() wants 5args */ +/* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ + +/* the guid of struct drm_dp_mst_branch is guid_t */ +#define HAVE_DRM_DP_MST_BRANCH_GUID_T 1 + +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 + +/* drm_dp_mst_detect_port() wants p,p,p,p args */ +#define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 + +/* drm_dp_mst_dsc_aux_for_port() is available */ +#define HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT 1 + +/* drm_dp_mst_edid_read() is available */ +#define HAVE_DRM_DP_MST_EDID_READ 1 + +/* drm_dp_mst_{get,put}_port_malloc() is available */ +#define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 + +/* drm_dp_mst_hpd_irq_handle_event() is available */ +#define HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT 1 + +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + +/* struct drm_dp_mst_port has passthrough_aux member */ +#define HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX 1 + +/* drm_dp_mst_root_conn_atomic_check() is available */ +#define HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK 1 + +/* struct drm_dp_mst_topology_cbs->destroy_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ + +/* struct drm_dp_mst_topology_cbs has hotplug member */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ + +/* struct drm_dp_mst_topology_cbs->poll_hpd_irq is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ 1 + +/* struct drm_dp_mst_topology_cbs->register_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ + +/* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ + +/* drm_dp_mst_topology_mgr_resume() wants 2 args */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 + +/* drm_dp_mst_topology_queue_probe() is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE 1 + +/* struct drm_dp_mst_topology_state has member payloads */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 + +/* struct drm_dp_mst_topology_state has member pbn_div */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT */ + +/* struct drm_dp_mst_topology_state has union member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION 1 + +/* struct drm_dp_mst_topology_state has member total_avail_slots */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 + +/* drm_dp_read_dpcd_caps() is available */ +#define HAVE_DRM_DP_READ_DPCD_CAPS 1 + +/* drm_dp_remove_payload_part{1,2}() is available */ +#define HAVE_DRM_DP_REMOVE_RAYLOAD_PART 1 + +/* drm_dp_send_real_edid_checksum() is available */ +#define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 + +/* drm_dp_update_payload_part1() function has start_slot argument */ +/* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ + +/* drm_driver->date is available */ +/* #undef HAVE_DRM_DRIVER_DATE */ + +/* drm_driver->gem_prime_mmap() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_MMAP */ + +/* drm_driver->gem_prime_res_obj() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ + +/* drm_driver->show_fdinfo() is available */ +#define HAVE_DRM_DRIVER_SHOW_FDINFO 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRMP_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_APERTURE_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_BACKPORT_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CLIENT_EVENT_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_CLIENT_SETUP_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_COLOROP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ELD_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_FBDEV_GENERIC_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_TTM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_MANAGED_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PANIC_H 1 + +/* Define to 1 if you have the header + file. */ +#define HAVE_DRM_DRM_PRIVACY_SCREEN_CONSUMER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PROBE_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_SUBALLOC_H 1 + +/* drm_driver_feature DRIVER_IRQ_SHARED is available */ +/* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ + +/* drm_driver_feature DRIVER_PRIME is available */ +/* #undef HAVE_DRM_DRV_DRIVER_PRIME */ + +/* drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available */ +#define HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE 1 + +/* drm_gem_prime_export() with p,i arg is available */ +#define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 + +/* drm_dsc_compute_rc_parameters() is available */ +#define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 + +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + +/* drm_edid_connector_add_modes is available */ +#define HAVE_DRM_EDID_CONNECTOR_ADD_MODES 1 + +/* drm_edid_connector_update is available */ +#define HAVE_DRM_EDID_CONNECTOR_UPDATE 1 + +/* drm_edid_is_digital is available */ +#define HAVE_DRM_EDID_IS_DIGITAL 1 + +/* drm_edid_alloc() is available */ +#define HAVE_DRM_EDID_MALLOC 1 + +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + +/* drm_edid_raw() is available */ +#define HAVE_DRM_EDID_RAW 1 + +/* drm_edid_valid() is available */ +#define HAVE_DRM_EDID_VALID 1 + +/* fb_create has const struct drm_format_info * parameter */ +#define HAVE_DRM_FB_CREATE_FORMAT_INFO 1 + +/* drm_fb_helper_fill_info() is available */ +#define HAVE_DRM_FB_HELPER_FILL_INFO 1 + +/* drm_fb_helper_gem_is_fb is available */ +#define HAVE_DRM_FB_HELPER_GEM_IS_FB 1 + +/* drm_fb_helper_init() has 2 args */ +#define HAVE_DRM_FB_HELPER_INIT_2ARGS 1 + +/* drm_fb_helper_init() has 3 args */ +/* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ + +/* struct drm_file->client_id is available */ +#define HAVE_DRM_FILE_CLIENT_ID 1 + +/* struct drm_file->client_name is available */ +#define HAVE_DRM_FILE_CLIENT_NAME 1 + +/* drm_file_err() is available */ +#define HAVE_DRM_FILE_ERR 1 + +/* drm_firmware_drivers_only() is available */ +#define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 + +/* drm_format_info.block_w and rm_format_info.block_h is available */ +#define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 + +/* drm_gem_dmabuf_vmap() has struct iosys_map arg */ +#define HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG 1 + +/* drm_gem_is_imported() is available */ +#define HAVE_DRM_GEM_IS_IMPORTED 1 + +/* drm_gem_object_funcs->vmap() has 2 args */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 + +/* drm_gem_object_funcs.vmap hsa iosys_map arg */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 + +/* drm_gem_object_is_shared_for_memory_stats() is available */ +#define HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS 1 + +/* drm_gem_object_put() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT 1 + +/* drm_gem_object_put() is exported */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ + +/* drm_gem_object->resv/_resv is available */ +#define HAVE_DRM_GEM_OBJECT_RESV 1 + +/* drm_gem_plane_helper_prepare_fb() is available */ +#define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 + +/* drm_gem_prime_handle_to_dmabuf() is available */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF 1 + +/* drm_gem_prime_handle_to_fd() is available */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 + +/* get_format_info uses pixel_format and modifier parameters */ +#define HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS 1 + +/* drm_get_panel_backlight_quirk() is available */ +#define HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK 1 + +/* drm_hdcp_update_content_protection is available */ +#define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ +/* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface */ +#define HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 + +/* drm_helper_force_disable_all() is available */ +#define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 + +/* drm_helper_mode_fill_fb_struct() wants 4 arguments */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS 1 + +/* drm_kms_helper_connector_hotplug_event() function is available */ +#define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 + +/* drm_memcpy_from_wc() is availablea */ +/* #undef HAVE_DRM_MEMCPY_FROM_WC */ + +/* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ +#define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 + +/* drm_memory_stats_is_zero() is available */ +#define HAVE_DRM_MEMORY_STATS_IS_ZERO 1 + +/* drm_mode_config->dp_subconnector_property is available */ +#define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 + +/* drm_mode_config->fb_base is available */ +/* #undef HAVE_DRM_MODE_CONFIG_FB_BASE */ + +/* drm_mode_config->fb_modifiers_not_supported is available */ +#define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 + +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_init() is available */ +#define HAVE_DRM_MODE_INIT 1 + +/* drm_need_swiotlb() is availablea */ +#define HAVE_DRM_NEED_SWIOTLB 1 + +/* drm_plane->color_pipeline_property is available */ +#define HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY 1 + +/* drm_plane_helper_destroy() is available */ +#define HAVE_DRM_PLANE_HELPER_DESTROY 1 + +/* drm_prime_pages_to_sg() wants 3 arguments */ +#define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 + +/* drm_prime_sg_to_dma_addr_array() is available */ +#define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 + +/* drm_print_bits() is available */ +#define HAVE_DRM_PRINT_BITS 1 + +/* drm_print_bits() has 4 args */ +#define HAVE_DRM_PRINT_BITS_4ARGS 1 + +/* drm_print_memory_stats() is available */ +#define HAVE_DRM_PRINT_MEMORY_STATS 1 + +/* struct drm_private_obj.lock is available */ +#define HAVE_DRM_PRIVATE_OBJ_LOCK 1 + +/* drm_show_fdinfo() is available */ +#define HAVE_DRM_SHOW_FDINFO 1 + +/* drm_simple_encoder is available */ +#define HAVE_DRM_SIMPLE_ENCODER_INIT 1 + +/* Has function drm_suballoc_manager_init() */ +#define HAVE_DRM_SUBALLOC_MANAGER_INIT 1 + +/* drm_syncobj_add_point() is available */ +#define HAVE_DRM_SYNCOBJ_ADD_POINT 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_TASK_BARRIER_H 1 + +/* drm_vblank_crtc_config is available */ +#define HAVE_DRM_VBLANK_CRTC_CONFIG 1 + +/* struct vblank->config is available */ +#define HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG 1 + +/* struct drm_vma_offset_node has readonly field */ +/* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ + +/* drm_writeback_connector_init() has 7 args */ +#define HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS 1 + +/* fault_flag_allow_retry_first() is available */ +#define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 + +/* fd_empty is available */ +#define HAVE_FD_EMPTY 1 + +/* file_operation->fop_flags is available */ +#define HAVE_FILE_OPERATION_FOP_FLAGS 1 + +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + +/* follow_pfnmap_start() is available */ +#define HAVE_FOLLOW_PFNMAP_START 1 + +/* fsleep() is available */ +#define HAVE_FSLEEP 1 + +/* fs_reclaim_acquire() is available */ +#define HAVE_FS_RECLAIM_ACQUIRE 1 + +/* generic_handle_domain_irq() is available */ +#define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 + +/* get_user_pages_remote() wants gup_flags parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ + +/* get_user_pages_remote() is introduced with initial prototype */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_INTRODUCED */ + +/* get_user_pages_remote() wants locked parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ + +/* get_user_pages_remote() remove task_struct pointer */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT */ + +/* get_user_pages_remote() remove argument vmas */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS 1 + +/* get_user_pages() remove vmas argument */ +#define HAVE_GET_USER_PAGES_REMOVE_VMAS 1 + +/* hmm remove the customizable pfn format */ +#define HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT 1 + +/* hmm_range_fault() wants 1 arg */ +#define HAVE_HMM_RANGE_FAULT_1ARG 1 + +/* hrtimer_setup() is available */ +#define HAVE_HRTIMER_SETUP 1 + +/* i2c_new_client_device() is enabled */ +#define HAVE_I2C_NEW_CLIENT_DEVICE 1 + +/* idr_init_base() is available */ +#define HAVE_IDR_INIT_BASE 1 + +/* import_guid() is available */ +#define HAVE_IMPORT_GUID 1 + +/* io_mapping_map_local_wc() is available */ +#define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 + +/* io_mapping_unmap_local() is available */ +#define HAVE_IO_MAPPING_UNMAP_LOCAL 1 + +/* is_cow_mapping() is available */ +#define HAVE_IS_COW_MAPPING 1 + +/* jiffies64_to_msecs() is available */ +#define HAVE_JIFFIES64_TO_MSECS 1 + +/* kallsyms_lookup_name is available */ +/* #undef HAVE_KALLSYMS_LOOKUP_NAME */ + +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 + +/* HAVE_KFD_PEERDIRECT_SUPPORT is available */ +/* #undef HAVE_KFD_PEERDIRECT_SUPPORT */ + +/* HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path */ +/* #undef HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH */ + +/* kfifo_out_linear() available */ +#define HAVE_KFIFO_OUT_LINEAR 1 + +/* kmalloc_size_roundup is available */ +#define HAVE_KMALLOC_SIZE_ROUNDUP 1 + +/* kmap_local_* is available */ +#define HAVE_KMAP_LOCAL 1 + +/* kmap_local_page_try_from_panic() is available */ +#define HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC 1 + +/* krealloc_array() is available */ +#define HAVE_KREALLOC_ARRAY 1 + +/* ksys_fd() is available */ +/* #undef HAVE_KSYS_CLOSE_FD */ + +/* ksys_sync_helper() is available */ +#define HAVE_KSYS_SYNC_HELPER 1 + +/* kthread_{use,unuse}_mm() is available */ +#define HAVE_KTHREAD_USE_MM 1 + +/* ktime_get_boottime_ns() is available */ +#define HAVE_KTIME_GET_BOOTTIME_NS 1 + +/* ktime_get_ns is available */ +#define HAVE_KTIME_GET_NS 1 + +/* ktime_t is union */ +/* #undef HAVE_KTIME_IS_UNION */ + +/* Define to 1 if you have the header file. */ +#define HAVE_KUNIT_TEST_BUG_H 1 + +/* kvrealloc() has 3 arguments */ +#define HAVE_KVREALLOC_3ARG 1 + +/* kvrealloc() has 4 arguments */ +/* #undef HAVE_KVREALLOC_4ARG */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ACPI_AMD_WBRF_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APERTURE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APPLE_GMUX_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ARGS_H 1 + +/* atomic_long_try_cmpxchg() is available */ +#define HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BITS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BUILD_BUG_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CC_PLATFORM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CGROUP_DMEM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CLEANUP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CONTAINER_OF_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEVICE_CLASS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEV_PRINTK_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_DMA_ATTRS_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_DMA_BUF_MAP_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_UNWRAP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_MAP_OPS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_RESV_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_FENCE_ARRAY_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IOSYS_MAP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 + +/* local_try_cmpchg() is available */ +#define HAVE_LINUX_LOCAL_TRY_CMPXCHG 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MINMAX_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MMAP_LOCK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PCI_P2PDMA_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PGTABLE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PROCESSOR_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_STDARG_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNALIGNED_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNITS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_XARRAY_H 1 + +/* list_cmp_func() is const param */ +#define HAVE_LIST_CMP_FUNC_IS_CONST_PARAM 1 + +/* list_is_first() is available */ +#define HAVE_LIST_IS_FIRST 1 + +/* list_is_head() is available */ +#define HAVE_LIST_IS_HEAD 1 + +/* list_rotate_to_front() is available */ +#define HAVE_LIST_ROTATE_TO_FRONT 1 + +/* enum MCE_PRIO_UC is available */ +#define HAVE_MCE_PRIO_UC 1 + +/* memalloc_noreclaim_save() is available */ +#define HAVE_MEMALLOC_NORECLAIM_SAVE 1 + +/* mempool_alloc_preallocated() is available */ +#define HAVE_MEMPOOL_ALLOC_PREALLOCATED 1 + +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 + +/* struct migrate_vma has fault_page */ +#define HAVE_MIGRATE_VMA_FAULT_PAGE 1 + +/* migrate_vma->pgmap_owner is available */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 + +/* mmap_assert_write_locked() is available */ +/* #undef HAVE_MMAP_ASSERT_WRITE_LOCKED */ + +/* mmput_async() is available */ +#define HAVE_MMPUT_ASYNC 1 + +/* mmu_notifier_call_srcu() is available */ +/* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ + +/* mmu_notifier_put() is available */ +#define HAVE_MMU_NOTIFIER_PUT 1 + +/* mmu_notifier_range_blockable() is available */ +#define HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE 1 + +/* mmu_notifier_synchronize() is available */ +#define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 + +/* MODULE_IMPORT_NS() wants a string arguments */ +#define HAVE_MODULE_IMPORT_NS_NEED_A_STRING 1 + +/* kvrealloc() isn't available */ +/* #undef HAVE_NO_KVREALLOC */ + +/* class_create has one argument */ +#define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 + +/* page_pgmap() is available */ +#define HAVE_PAGE_PGMAP 1 + +/* pcie_aspm_enabled() is available */ +#define HAVE_PCIE_ASPM_ENABLED 1 + +/* PCI driver handles extended tags */ +#define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 + +/* pci_dev_id() is available */ +#define HAVE_PCI_DEV_ID 1 + +/* pci_dev_is_disconnected is available */ +#define HAVE_PCI_DEV_IS_DISCONNECTED 1 + +/* struct pci_driver has field dev_groups */ +#define HAVE_PCI_DRIVER_DEV_GROUPS 1 + +/* pci_get_base_class() is available */ +#define HAVE_PCI_GET_BASE_CLASS 1 + +/* pci_pr3_present() is available */ +#define HAVE_PCI_PR3_PRESENT 1 + +/* pci_rebar_bytes_to_size() is available */ +#define HAVE_PCI_REBAR_BYTES_TO_SIZE 1 + +/* pci_rebar_get_max_size() is available */ +#define HAVE_PCI_REBAR_GET_MAX_SIZE 1 + +/* pci_resize_resource() has align parameter */ +#define HAVE_PCI_RESIZE_RESOURCE_ALIGN 1 + +/* PIDTYPE is availablea */ +#define HAVE_PIDTYPE_TGID 1 + +/* pm_hibernate_is_recovering() is available */ +#define HAVE_PM_HIBERNATE_IS_RECOVERING 1 + +/* pm_hibernation_mode_is_suspend() is available */ +#define HAVE_PM_HIBERNATION_MODE_IS_SUSPEND 1 + +/* pm_runtime_get_if_active() has one parameters */ +#define HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS 1 + +/* pm_runtime_get_if_active() has two parameters */ +/* #undef HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS */ + +/* pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy */ +#define HAVE_PM_RUNTIME_PUT_AUTOSUSPEND_MARK_LAST_BUSY 1 + +/* pm_runtime_resume_and_get() is available */ +#define HAVE_PM_RUNTIME_RESUME_AND_GET 1 + +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 + +/* pxm_to_node() is available */ +#define HAVE_PXM_TO_NODE 1 + +/* queue_work_node() is available */ +#define HAVE_QUEUE_WORK_NODE 1 + +/* range_overflows() is available */ +#define HAVE_RANGE_OVERFLOWS 1 + +/* ratelimit_state_reset_interval() is available */ +#define HAVE_RATELIMIT_STATE_RESET_INTERVAL 1 + +/* rb_add_cached is available */ +#define HAVE_RB_ADD_CACHED 1 + +/* whether register_shrinker(x, x) is available */ +/* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ + +/* remove_conflicting_pci_framebuffers() wants p,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ + +/* Reporting reservation_ww_class missing */ +/* #undef HAVE_RESERVATION_WW_CLASS_BUG */ + +/* sg_alloc_table_from_pages_segment() is available */ +#define HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT 1 + +/* shmem_file_setup() takes vma_flags_t arg */ +/* #undef HAVE_SHMEM_FILE_SETUP_VMA_FLAGS */ + +/* shmem_read_folio() is available */ +#define HAVE_SHMEM_READ_FOLIO 1 + +/* shmem_writeout() is available */ +/* #undef HAVE_SHMEM_WRITEOUT */ + +/* shmem_writeout() wants 3 arguments */ +#define HAVE_SHMEM_WRITEOUT_WANT_3_ARGS 1 + +/* shrinker_register() is available */ +#define HAVE_SHRINKER_REGISTER 1 + +/* size_mul() is available */ +#define HAVE_SIZE_MUL 1 + +/* smca_get_bank_type(x) is available */ +/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ + +/* whether smca_get_bank_type(x, x) is available */ +#define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 + +/* enum SMCA_UMC_V2 is available */ +#define HAVE_SMCA_UMC_V2 1 + +/* strscpy() allows two arguments */ +#define HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS 1 + +/* struct dma_buf_attach_ops->allow_peer2peer is available */ +#define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 + +/* struct dma_buf_ops->pin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 + +/* struct dma_fence_chain is available */ +#define HAVE_STRUCT_DMA_FENCE_CHAIN 1 + +/* struct drm_connector_state->duplicated is available */ +#define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 + +/* struct drm_atomic_state->plane_color_pipeline is available */ +#define HAVE_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE 1 + +/* struct drm_color_lut32 is available */ +#define HAVE_STRUCT_DRM_COLOR_LUT32 1 + +/* struct drm_connector_state->colorspace is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE 1 + +/* struct drm_connector_state->self_refresh_aware is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 + +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 + +/* struct drm_crtc_funcs->get_vblank_timestamp() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 + +/* struct drm_crtc_state->async_flip is available */ +#define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 + +/* drm_gem_open_object is defined in struct drm_drv */ +/* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + +/* struct drm_memory_stats is defined */ +#define HAVE_STRUCT_DRM_MEMORY_STATS 1 + +/* struct drm_mode_config has member panel_type_property */ +#define HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY 1 + +/* drm_plane_helper_funcs->atomic_async_check() have three arguments */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS 1 + +/* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state + arg */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 + +/* struct drm_plane_helper_funcs->get_scanout_buffer is available */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER 1 + +/* struct __drm_private_objs_state->state_to_destroy is available */ +#define HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY 1 + +/* ide->idr_base is available */ +#define HAVE_STRUCT_IDE_IDR_BASE 1 + +/* struct smca_bank is available */ +/* #undef HAVE_STRUCT_SMCA_BANK */ + +/* struct xarray is available */ +#define HAVE_STRUCT_XARRAY 1 + +/* zone->managed_pages is available */ +/* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ + +/* str_read_write() is defined */ +#define HAVE_STR_READ_WRITE 1 + +/* str_yes_no() is defined */ +#define HAVE_STR_YES_NO 1 + +/* synchronize_shrinkers() is available */ +/* #undef HAVE_SYNCHRONIZE_SHRINKERS */ + +/* sysfs_emit() and sysfs_emit_at() are available */ +#define HAVE_SYSFS_EMIT 1 + +/* system_percpu_wq is available */ +#define HAVE_SYSTEM_PERCPU_WQ 1 + +/* timer_delete() is available */ +#define HAVE_TIMER_DELETE 1 + +/* topology_num_cores_per_package is availablea */ +#define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 + +/* totalram_pages() is available */ +#define HAVE_TOTALRAM_PAGES 1 + +/* usleep_range_state() is available */ +#define HAVE_USLEEP_RANGE_STATE 1 + +/* vfs_iocb_iter_read() is available */ +#define HAVE_VFS_IOCB_ITER_READ 1 + +/* vga_client_register() don't pass a cookie */ +#define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 + +/* vga_remove_vgacon() is available */ +#define HAVE_VGA_REMOVE_VGACON 1 + +/* vma_is_initial_{heap, stack} is available */ +#define HAVE_VMA_IS_INITIAL_HEAP 1 + +/* vma_lookup() is available */ +#define HAVE_VMA_LOOKUP 1 + +/* vmemdup_array_user() is available */ +#define HAVE_VMEMDUP_ARRAY_USER 1 + +/* vm_fault->{address/vma} is available */ +#define HAVE_VM_FAULT_ADDRESS_VMA 1 + +/* vm_flags_{set, clear} is available */ +#define HAVE_VM_FLAGS_SET 1 + +/* vm_operations_struct->fault() wants 1 arg */ +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 + +/* want_init_on_free() is available */ +#define HAVE_WANT_INIT_ON_FREE 1 + +/* ww_mutex_trylock() has context arg */ +#define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 + +/* zone_device_page_init() is available */ +/* #undef HAVE_ZONE_DEVICE_PAGE_INIT */ + +/* zone_device_page_init() takes 3 arguments */ +#define HAVE_ZONE_DEVICE_PAGE_INIT_3ARG 1 + +/* zone_managed_pages() is available */ +#define HAVE_ZONE_MANAGED_PAGES 1 + +/* __dma_fence_is_later() is available and has 2 args */ +/* #undef HAVE__DMA_FENCE_IS_LATER_2ARGS */ + +/* __dma_fence_is_later() is available and has fence args */ +#define HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG 1 + +/* __dma_fence_is_later() is available and has ops arg */ +/* #undef HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG */ + +/* __drm_atomic_helper_crtc_reset() is available */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 + +/* __sg_alloc_table_from_pages() has 9 args */ +/* #undef HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS */ + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "amdgpu-dkms" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "amdgpu-dkms 6.19.0" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "amdgpu-dkms" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "6.19.0" + +/* drm_file->debugfs_client is available */ +#define STRUCT_DRM_FILE_DEBUGFS_CLIENT 1 + +#include "config-amd-chips.h" + +#define AMDGPU_VERSION PACKAGE_VERSION diff --git a/drivers/gpu/drm/amd/dkms/config/install-sh b/drivers/gpu/drm/amd/dkms/config/install-sh new file mode 100755 index 0000000000000..ec298b5374027 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/install-sh @@ -0,0 +1,541 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2020-11-14.01; # UTC + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# 'make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +tab=' ' +nl=' +' +IFS=" $tab$nl" + +# Set DOITPROG to "echo" to test this script. + +doit=${DOITPROG-} +doit_exec=${doit:-exec} + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +# Create dirs (including intermediate dirs) using mode 755. +# This is like GNU 'install' as of coreutils 8.32 (2020). +mkdir_umask=22 + +backupsuffix= +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +is_target_a_directory=possibly + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -p pass -p to $cpprog. + -s $stripprog installed files. + -S SUFFIX attempt to back up existing files, with suffix SUFFIX. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG + +By default, rm is invoked with -f; when overridden with RMPROG, +it's up to you to specify -f if you want it. + +If -S is not specified, no backups are attempted. + +Email bug reports to bug-automake@gnu.org. +Automake home page: https://www.gnu.org/software/automake/ +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *"$tab"* | *"$nl"* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -p) cpprog="$cpprog -p";; + + -s) stripcmd=$stripprog;; + + -S) backupsuffix="$2" + shift;; + + -t) + is_target_a_directory=always + dst_arg=$2 + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + shift;; + + -T) is_target_a_directory=never;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +# We allow the use of options -d and -T together, by making -d +# take the precedence; this is for compatibility with GNU install. + +if test -n "$dir_arg"; then + if test -n "$dst_arg"; then + echo "$0: target directory not allowed when installing a directory." >&2 + exit 1 + fi +fi + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call 'install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + if test $# -gt 1 || test "$is_target_a_directory" = always; then + if test ! -d "$dst_arg"; then + echo "$0: $dst_arg: Is not a directory." >&2 + exit 1 + fi + fi +fi + +if test -z "$dir_arg"; then + do_exit='(exit $ret); exit $ret' + trap "ret=129; $do_exit" 1 + trap "ret=130; $do_exit" 2 + trap "ret=141; $do_exit" 13 + trap "ret=143; $do_exit" 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names problematic for 'test' and other utilities. + case $src in + -* | [=\(\)!]) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + # Don't chown directories that already exist. + if test $dstdir_status = 0; then + chowncmd="" + fi + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + dst=$dst_arg + + # If destination is a directory, append the input filename. + if test -d "$dst"; then + if test "$is_target_a_directory" = never; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dstbase=`basename "$src"` + case $dst in + */) dst=$dst$dstbase;; + *) dst=$dst/$dstbase;; + esac + dstdir_status=0 + else + dstdir=`dirname "$dst"` + test -d "$dstdir" + dstdir_status=$? + fi + fi + + case $dstdir in + */) dstdirslash=$dstdir;; + *) dstdirslash=$dstdir/;; + esac + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + # The $RANDOM variable is not portable (e.g., dash). Use it + # here however when possible just to lower collision chance. + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + + trap ' + ret=$? + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null + exit $ret + ' 0 + + # Because "mkdir -p" follows existing symlinks and we likely work + # directly in world-writeable /tmp, make sure that the '$tmpdir' + # directory is successfully created first before we actually test + # 'mkdir -p'. + if (umask $mkdir_umask && + $mkdirprog $mkdir_mode "$tmpdir" && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + test_tmpdir="$tmpdir/a" + ls_ld_tmpdir=`ls -ld "$test_tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null + fi + trap '' 0;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + [-=\(\)!]*) prefix='./';; + *) prefix='';; + esac + + oIFS=$IFS + IFS=/ + set -f + set fnord $dstdir + shift + set +f + IFS=$oIFS + + prefixes= + + for d + do + test X"$d" = X && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=${dstdirslash}_inst.$$_ + rmtmp=${dstdirslash}_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && + { test -z "$stripcmd" || { + # Create $dsttmp read-write so that cp doesn't create it read-only, + # which would cause strip to fail. + if test -z "$doit"; then + : >"$dsttmp" # No need to fork-exec 'touch'. + else + $doit touch "$dsttmp" + fi + } + } && + $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + set +f && + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # If $backupsuffix is set, and the file being installed + # already exists, attempt a backup. Don't worry if it fails, + # e.g., if mv doesn't support -f. + if test -n "$backupsuffix" && test -f "$dst"; then + $doit $mvcmd -f "$dst" "$dst$backupsuffix" 2>/dev/null + fi + + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'before-save-hook 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC0" +# time-stamp-end: "; # UTC" +# End: diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac new file mode 100644 index 0000000000000..42476e23441ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -0,0 +1,12 @@ +AC_INIT(amdgpu-dkms, 6.19.4) + +AC_LANG(C) +AC_CONFIG_AUX_DIR([config]) +AC_CONFIG_HEADERS([config/config.h]) +AC_PROG_INSTALL +AC_PROG_CC +AC_CONFIG_MACRO_DIR([m4]) + +AC_AMDGPU_CONFIG + +AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/dkms-config.sh b/drivers/gpu/drm/amd/dkms/dkms-config.sh new file mode 100755 index 0000000000000..efe7089df9c36 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms-config.sh @@ -0,0 +1,140 @@ +#!/bin/bash + +local_config=$1 +KERNELVER=$2 +CC=$3 +kernel_build_dir="/lib/modules/$KERNELVER/build" +kconfig_file="${kernel_build_dir}/include/config/auto.conf" +kcl_config_file="amd/dkms/config/config.h" +local_config_tmp=${local_config}.tmp +disabled_config_tmp=${local_config}.disabled.tmp + +echo "" > ${local_config_tmp} +echo "" > ${disabled_config_tmp} + +append_mk () { + echo $1 >> ${local_config_tmp} +} + +export_macro_mk() { + local config_name=$1 + local enable=${2:-1} + + if [ "$enable" -eq 1 ]; then + output=${local_config_tmp} + else + output=${disabled_config_tmp} + fi + + cat <<_DKMS_CONFIG >> ${output} +export ${config_name}=y +subdir-ccflags-y += -D${config_name} + +_DKMS_CONFIG +} + +get_config() { + grep "^$1=" "${kconfig_file}" | awk -F= '{print $2}' +} + +is_enabled() { + grep -q "^$1=" "${kconfig_file}" +} + +is_kcl_macro_defined() { + grep -q "define $1" "${kcl_config_file}" && echo "y" || echo "n" +} + +# Export OS variables +if [[ -f /etc/os-release ]]; then + OS_NAME=$(grep -oP '(?<=^ID=).+' /etc/os-release | tr -d '"') + OS_VERSION=$(grep -oP '(?<=^VERSION_ID=).+' /etc/os-release | tr -d '"') +else + OS_NAME="unknown" + OS_VERSION="0.0" +fi +append_mk "export OS_NAME=${OS_NAME}" +append_mk "export OS_VERSION=${OS_VERSION}" + +VERSION_MAJOR=$(echo ${OS_VERSION}.0 | cut -d. -f1) +VERSION_MINOR=$(echo ${OS_VERSION}.0 | cut -d. -f2) +OS_VERSION_STR=${OS_VERSION//./_} +OS_NAME_STR=$(echo ${OS_NAME} | tr a-z A-Z) + +# Generate macros related to the operating system to support compilation. +# The OS name is converted to uppercase and appended as a flag, e.g., -DOS_NAME_UBUNTU, -DOS_NAME_RHEL. +append_mk "subdir-ccflags-y += -DOS_NAME_${OS_NAME_STR}" + +# Add OS specific compile flags +append_mk "subdir-ccflags-y += -DOS_VERSION_MAJOR=${VERSION_MAJOR}" +append_mk "subdir-ccflags-y += -DOS_VERSION_MINOR=${VERSION_MINOR}" + +# Add additional OS specific configurations +case "${OS_NAME}" in + "opensuse-leap"|"sled"|"sles") + append_mk "subdir-ccflags-y += -DOS_NAME_SUSE_${OS_VERSION_STR}" + ;; + "ubuntu") + OS_BUILD_NUM=$(echo "${KERNELVER}" | cut -d '-' -f 2) + append_mk "subdir-ccflags-y += -DUBUNTU_BUILD_NUM=${OS_BUILD_NUM}" + OS_OEM=$(echo "${KERNELVER}" | cut -d '-' -f 3) + if [[ "${OS_OEM}" == "oem" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM" + fi + append_mk "subdir-ccflags-y += -DOS_NAME_UBUNTU_${OS_VERSION_STR}" + ;; + "rhel") + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_${OS_VERSION_STR}" + if [[ "${VERSION_MAJOR}" == "7" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_7_X" + append_mk "subdir-ccflags-y += -include /usr/src/kernels/${KERNELVER}/include/drm/drm_backport.h" + elif [[ "${VERSION_MAJOR}" == "8" ]]; then + append_mk "subdir-ccflags-y += -DOS_NAME_RHEL_8_X" + fi + ;; +esac + +# Extract DRM version and patch level from the main Makefile +DRM_VER=$(sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' ${kernel_build_dir}/Makefile) +DRM_PATCH=$(sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' ${kernel_build_dir}/Makefile) + +if [ -z "${DRM_VER}" ]; then + DRM_VER=$(echo ${KERNELVER} | cut -d. -f1) + DRM_PATCH=$(echo ${KERNELVER} | cut -d. -f2) +fi + +append_mk "subdir-ccflags-y += -DDRM_VER=${DRM_VER} -DDRM_PATCH=${DRM_PATCH} -DDRM_SUB=\"0\"" + +# Check for P2PDMA configuration +_enable=0 +if [[ "$(get_config CONFIG_PCI_P2PDMA)" == "y" ]]; then + if [[ "$(get_config CONFIG_DMABUF_MOVENOTIFY)" == "y" ]]; then + _enable=1 + fi +fi +export_macro_mk CONFIG_HSA_AMD_P2P ${_enable} + +# Check for HMM mirror configuration +_enable=0 +if [[ "$(is_kcl_macro_defined HAVE_AMDKCL_HMM_MIRROR_ENABLED)" == "y" ]]; then + if is_enabled CONFIG_DEVICE_PRIVATE; then + _enable=1 + fi +fi +export_macro_mk CONFIG_HSA_AMD_SVM ${_enable} + +export_macro_mk CONFIG_HSA_AMD +export_macro_mk CONFIG_DRM_AMDGPU_CIK +export_macro_mk CONFIG_DRM_AMDGPU_SI +export_macro_mk CONFIG_DRM_AMDGPU_USERPTR +export_macro_mk CONFIG_DRM_AMD_DC + +echo "Enabled configurations:" +cat ${local_config_tmp} +echo "****************" +echo "Disabled configurations:" +cat ${disabled_config_tmp} +echo "****************" + +rm -f ${disabled_config_tmp} +mv ${local_config_tmp} ${local_config} diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf new file mode 100644 index 0000000000000..15287e5222ac3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -0,0 +1,43 @@ +PACKAGE_NAME="amdgpu" +PACKAGE_VERSION="1.0" +AUTOINSTALL="yes" +# not all OS supports weak module updates +NO_WEAK_MODULES="yes" + +# not work with RHEL DKMS +#MODULES_CONF[0]="blacklist radeon" + +BUILT_MODULE_NAME[0]="amdgpu" +BUILT_MODULE_LOCATION[0]="amd/amdgpu" +DEST_MODULE_LOCATION[0]="/kernel/drivers/gpu/drm/amd/amdgpu" + +BUILT_MODULE_NAME[1]="amdttm" +BUILT_MODULE_LOCATION[1]="ttm" +DEST_MODULE_LOCATION[1]="/kernel/drivers/gpu/drm/ttm" + +BUILT_MODULE_NAME[2]="amdkcl" +BUILT_MODULE_LOCATION[2]="amd/amdkcl" +DEST_MODULE_LOCATION[2]="/kernel/drivers/gpu/drm/amd/amdkcl" + +BUILT_MODULE_NAME[3]="amd-sched" +BUILT_MODULE_LOCATION[3]="scheduler" +DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" + +BUILT_MODULE_NAME[4]="amddrm_ttm_helper" +BUILT_MODULE_LOCATION[4]="." +DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" + +BUILT_MODULE_NAME[5]="amddrm_buddy" +BUILT_MODULE_LOCATION[5]="." +DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" + +BUILT_MODULE_NAME[6]="amddrm_exec" +BUILT_MODULE_LOCATION[6]="." +DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm" + +BUILT_MODULE_NAME[7]="amdxcp" +BUILT_MODULE_LOCATION[7]="amd/amdxcp" +DEST_MODULE_LOCATION[7]="/kernel/drivers/gpu/drm/amd/amdxcp" + +MAKE[0]="'make' KERNELVER=$kernelver" + diff --git a/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script new file mode 100644 index 0000000000000..90b14faec6dbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script @@ -0,0 +1,74 @@ +## wattman-like functionality +# boot with amdgpu.ppfeaturemask=0xffffffff (make sure PP_OVERDRIVE_MASK bit is set see hwmgr.h) +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 917Mhz 1175 mV +#6: 949Mhz 1175 mV +#7: 973Mhz 1175 mV +#OD_MCLK: +#0: 150Mhz 900 mV +#1: 1375Mhz 975 mV +# change mclk dpm level 0 from 150 to 155Mhz, no change to voltage +# format is "m dpm_level clock_in_mhz voltage_in_mv" +echo "m 0 155 900" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 7 from 973 to 975Mhz, change voltage from 1175 to 1180 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 975 1180" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 5 from 917 to 910Mhz, change voltage from 1175 to 1160 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 910 1160" > /sys/class/drm/card0/device/pp_od_clk_voltage +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 910Mhz 1160 mV +#6: 949Mhz 1175 mV +#7: 975Mhz 1180 mV +#OD_MCLK: +#0: 155Mhz 900 mV +#1: 1375Mhz 975 mV +# commit the changes to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage +# reset to the default dpm states +echo "r" > /sys/class/drm/card0/device/pp_od_clk_voltage +# commit the reset state to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage + +## reading/adjusting hwmon values +# https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface +# see which hwmon device this is +cat /sys/class/hwmon/hwmon0/name +# readback current vddgfx/vddnb voltages +# see which one this is +cat /sys/class/hwmon/hwmon0/in0_label +# read the voltage (mV) +cat /sys/class/hwmon/hwmon0/in0_input +# see current power (microwatts) +cat /sys/class/hwmon/hwmon0/power1_average +# current temp (millidegrees C) +cat /sys/class/hwmon/hwmon0/temp1_input +# see fan speed (rpm) +cat /sys/class/hwmon/hwmon0/fan1_input +# see fan speed pwm (0-255) +cat /sys/class/hwmon/hwmon0/pwm1 +# see min/max pwm limits +cat /sys/class/hwmon/hwmon0/pwm1_min +cat /sys/class/hwmon/hwmon0/pwm1_max +# see current fan control mode (0 none, 1 manual fan control, 2 dynamic fan control) +cat /sys/class/hwmon/hwmon0/pwm1_enable +# enable manual fan control +echo 1 > /sys/class/hwmon/hwmon0/pwm1_enable +# manually set the fan speed (100/255 = 39%) +echo 100 > /sys/class/hwmon/hwmon0/pwm1 +# enable automatic fan control +echo 2 > /sys/class/hwmon/hwmon0/pwm1_enable diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 new file mode 100644 index 0000000000000..532031624b3a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.1-rc2-1163-g7d26097b4beb +dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. +dnl # +AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + __drm_atomic_helper_crtc_reset(NULL, NULL); + ],[__drm_atomic_helper_crtc_reset], [drivers/gpu/drm/drm_atomic_state_helper.c],[ + AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, + [__drm_atomic_helper_crtc_reset() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 new file mode 100644 index 0000000000000..70a1ec664ef7f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + access_ok(0, 0); + ],[ + AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, + [whether access_ok(x, x) is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 new file mode 100644 index 0000000000000..83a0b1e027b9b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit: v4.9-rc5-17-g174cc7187e6f +dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and +dnl # early_acpi_os_unmap_memory() from Linux kernel +AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + acpi_put_table(NULL); + ], [acpi_put_table], [drivers/acpi/acpica/tbxface.c], [ + AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, + [acpi_put_table() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 new file mode 100644 index 0000000000000..d2a957a3c28a7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -0,0 +1,41 @@ +dnl # +dnl # commit: v6.1-rc1-17-da11ef832972 +dnl # drm/amdgpu: Don't register backlight when another +dnl # backlight should be used (v3) + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_backlight_use_native(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE, 1, + [acpi_video_backlight_use_native() is available]) + ]) + ]) +]) + +dnl # +dnl # commit: v6.1-rc1-161-c0f50c5de93b +dnl # drm/amdgpu: Register ACPI video backlight when +dnl # skipping amdgpu backlight registration + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_register_backlight(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT, 1, + [acpi_video_register_backlight() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ + AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE + AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 new file mode 100644 index 0000000000000..5668a2d728b89 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit: v5.1-rc3-1-g817b4d64da03 +dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + acpi_dev_get_first_match_dev(NULL, NULL, 0); + ],[acpi_dev_get_first_match_dev],[drivers/acpi/utils.c], [ + AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, + [acpi_dev_get_first_match_dev() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 new file mode 100644 index 0000000000000..16493b5e8d995 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit aa475a59fff172ec858093fbc8471c0993081481 +dnl # ACPICA: ACPI 6.3: SRAT: add Generic Affinity Structure subtable +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct acpi_srat_generic_affinity *p = NULL; + p->reserved = 0; + ], [ + AC_DEFINE(HAVE_ACPI_SRAT_GENERIC_AFFINITY, 1, [struct acpi_srat_generic_affinity is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 new file mode 100644 index 0000000000000..c42fcb583b362 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -0,0 +1,44 @@ +dnl # +dnl # v5.12-rc3-5-gfc1b6620501f iommu/amd: Move a few prototypes to include/linux/amd-iommu.h +dnl # v5.12-rc3-4-gb29a1fc7595a iommu/amd: Remove a few unused exports +dnl # v4.11-rc4-171-gf5863a00e73c x86/events/amd/iommu.c: Modify functions to query max banks and counters +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + amd_iommu_pc_get_max_banks(0); + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, + [amd_iommu_pc_get_max_banks() declared]) + ], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + get_amd_iommu(0); + ],[get_amd_iommu],[drivers/iommu/amd/init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, + [amd_iommu_pc_get_max_banks() arg is unsigned int]) + ]) + ]) +]) + +dnl # +dnl # commit v3.10-rc3-89-g30861ddc9cca +dnl # perf/x86/amd: Add IOMMU Performance Counter resource management +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + #ifndef CONFIG_AMD_IOMMU + #error CONFIG_AMD_IOMMU not enabled + #endif + ], [amd_iommu_pc_supported], [drivers/iommu/amd/init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_SUPPORTED, 1, + [amd_iommu_pc_supported() is available]) + AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 new file mode 100644 index 0000000000000..3ddbe27c03284 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860 +dnl # drm, iommu: Change type of pasid to u32 +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void (*f)(struct pci_dev *pdev, u32 pasid) = NULL; + amd_iommu_invalidate_ctx callback; + + callback = f; + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, + [amd_iommu_invalidate_ctx take arg type of pasid as u32]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 new file mode 100644 index 0000000000000..defc80545265e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.1-2256-gbd100f492c7e +dnl # platform/x86: apple-gmux: Add apple_gmux_detect() helper +dnl # +AC_DEFUN([AC_AMDGPU_APPLE_GMUX_DETECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + apple_gmux_detect(NULL, NULL); + ],[ + AC_DEFINE(HAVE_APPLE_GMUX_DETECT, 1, + [apple_gmux_detect() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 new file mode 100644 index 0000000000000..8245a8d52ee43 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit v4.9-rc2-1-g8ef4227615e1 +dnl # x86/io: add interface to reserve io memtype for a resource range. (v1.1) +dnl # +AC_DEFUN([AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [arch_io_reserve_memtype_wc arch_io_free_memtype_wc], [arch/x86/mm/pat/memtype.c arch/x86/mm/pat.c], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_BACKPORT_H + #include + #endif + #include + ], [ + #ifdef CONFIG_X86 + #error stub arch_io_* functions found + #endif + + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 new file mode 100644 index 0000000000000..ec603c4bd1a9b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v6.8-rc4-70-gfd43b8ae76e9 +dnl # x86/cpu/topology: Provide __num_[cores|threads]_per_package +dnl # +AC_DEFUN([AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int a = 0; + a = topology_num_cores_per_package(); + ], [ + AC_DEFINE(HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE, 1, + [topology_num_cores_per_package is availablea]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 new file mode 100644 index 0000000000000..477d281b98373 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.9-11925-g2c92ca849fcc +dnl # tracing/treewide: Remove second parameter of __assign_str() +dnl # Due to trace system bases on runtime, so use script to handle specially +dnl # +AC_DEFUN([AC_AMDGPU_ASSIGN_STR], [ + AC_KERNEL_DO_BACKGROUND([ + header_file=stage6_event_callback.h + header_file_src=$LINUX/include/trace/stages/$header_file + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -q '^#define __assign_str(dst)' $header_file_src], [ + AC_DEFINE(HAVE_ASSIGN_STR_ONE_ARGUMENT, 1, + [__assign_str() wants 1 arguments]) + ]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 new file mode 100644 index 0000000000000..5d20db398bf97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v5.13-rc1-138-g67d1b0de258a locking/atomic: add arch_atomic_long*() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + long r = 0; + t = atomic_long_try_cmpxchg(NULL, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG, 1, + [atomic_long_try_cmpxchg() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.3-rc1-6-g8fc4fddaf9a1 +dnl # locking/generic: Wire up local{,64}_try_cmpxchg() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + s64 r = 0; + local_t *l = NULL; + t = local_try_cmpxchg(l, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_LOCAL_TRY_CMPXCHG, 1, + [local_try_cmpchg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 new file mode 100644 index 0000000000000..555b5b4729a0a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bin_attr_const_read.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v6.15-rc1-7-g97d06802d10a +dnl # sysfs: constify bin_attribute argument of bin_attribute::read/write() +dnl # +AC_DEFUN([AC_AMDGPU_BIN_ATTR_CONST_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ssize_t (*p)(struct file *, struct kobject *, const struct bin_attribute *, + char *, loff_t, size_t) = NULL; + + struct bin_attribute bin_attr; + bin_attr.read = p; + ], [ + AC_DEFINE(HAVE_BIN_ATTR_CONST_ARGS, 1, + [bin_attribute.read is const args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 new file mode 100644 index 0000000000000..233756077854c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc1-324-g63c15822b8dd +dnl # lib/bitmap: add bitmap_{read,write}() +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_read(NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_READ, 1, + [bitmap_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 new file mode 100644 index 0000000000000..3c981e3fa9518 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc1-22-525d6515604e +dnl # drm/amd/pm: use bitmap_{from,to}_arr32 where appropriate +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_TO_ARR32], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_to_arr32(NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_TO_ARR32, 1, + [bitmap_to_arr32() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 new file mode 100644 index 0000000000000..d6d3e21a7efea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/blk_types.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.10-rc4-97-g0d02129e76ed +dnl # block: merge struct block_device and struct hd_struct +dnl # +AC_DEFUN([AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct block_device *device = NULL; + struct device dev = {}; + device->bd_device = dev; + ], [ + AC_DEFINE(HAVE_BLOCK_DEVICE_BD_DEVICE, 1, + [struct block_device has member named 'bd_device']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 new file mode 100644 index 0000000000000..17faee9d17a88 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -0,0 +1,39 @@ +dnl # +dnl # v5.18-rc5-2003-g73b4b53276a1 +dnl # Revert "workqueue: remove unused cancel_work()" +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cancel_work(NULL); + ], [cancel_work], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_CANCEL_WORK, 1, + [cancel_work() is available]) + ]) + ]) +]) + +dnl # +dnl # commit id:v5.0-rc2-28-g8204e0c1113d +dnl # workqueue: Provide queue_work_node to queue work near a given NUMA node +dnl # +AC_DEFUN([AC_AMDGPU_QUEUE_WORK_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + queue_work_node(0,NULL, NULL); + ], [queue_work_node], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_QUEUE_WORK_NODE, 1, + [queue_work_node() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_WORKQUEUE], [ + AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_QUEUE_WORK_NODE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 b/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 new file mode 100644 index 0000000000000..112e9335801c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cec_connector_info.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # +dnl # v5.2-rc5-392-g32a847f9fa40 +dnl # media: cec: add struct cec_connector_info support +dnl # +dnl # v5.4-rc1-53-g9098c1c251ff +dnl # media: cec: expose the new connector info API +dnl # The structure cec_connector_info has been moved from the media/cec.h to the uapi/linux/cec.h +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct cec_connector_info conn_info; + memset(&conn_info, 0, sizeof(conn_info)); + ], [ + AC_DEFINE(HAVE_CEC_CONNECTOR_INFO, 1, + [struct cec_connector_info is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 b/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 new file mode 100644 index 0000000000000..b672c855b13f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cec_notifier_conn_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-393-gb48cb35c6a7b +dnl # media: cec-notifier: add new notifier functions +dnl # +AC_DEFUN([AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cec_notifier_conn_register(NULL, NULL, NULL); + ], [cec_notifier_conn_register], [drivers/media/cec/core/cec-notifier.c], [ + AC_DEFINE(HAVE_CEC_NOTIFIER_CONN_REGISTER, 1, + [cec_notifier_conn_register() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 new file mode 100644 index 0000000000000..c1075f2a16d7f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 @@ -0,0 +1,16 @@ +dnl # commit 67dd1a36334ffce82bebeb2d633e152aa436d370 +dnl # drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifndef AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + #error AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES not #defined + #endif + ], [ + AC_DEFINE(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES, 1, + [whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 new file mode 100644 index 0000000000000..1ae2aee78530f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 @@ -0,0 +1,17 @@ +dnl # commit 2624dd154bcc53ac2de16ecae9746ba867b6ca70 +dnl # drm/amdgpu: add timeline support in amdgpu CS v3 +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT) ||\ + !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL) + #error CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL not #defined + #endif + ], [ + AC_DEFINE(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, 1, + [whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 new file mode 100644 index 0000000000000..f9c4c12aa4b75 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc2-1-g2952db0fd51b +dnl # compat_ioctl: add compat_ptr_ioctl() +dnl # +AC_DEFUN([AC_AMDGPU_COMPAT_PTR_IOCTL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + compat_ptr_ioctl(NULL, 0, 0); + ],[compat_ptr_ioctl],[fs/ioctl.c],[ + AC_DEFINE(HAVE_COMPAT_PTR_IOCTL, + 1, + [compat_ptr_ioctl() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 new file mode 100644 index 0000000000000..d66b31b9b3536 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_CONFIG], [ + AC_ARG_ENABLE([linux-builtin], + [AS_HELP_STRING([--enable-linux-builtin], + [Configure for builtin kernel modules @<:@default=no@:>@])], + [], + [enable_linux_builtin=no]) + + AC_CONFIG_KERNEL +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/create_class.m4 b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 new file mode 100644 index 0000000000000..bb9bd7bd2d13d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_DEVICE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct class* class = NULL; + class = class_create(NULL); + ], [ + AC_DEFINE(HAVE_ONE_ARGUMENT_OF_CLASS_CREATE, 1, + [class_create has one argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 new file mode 100644 index 0000000000000..ad4b11459528a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 @@ -0,0 +1,40 @@ +dnl # +dnl # commit a4574f63edc6f76fb46dcd65d3eb4d5a8e23ba38 +dnl # mm/memremap_pages: convert to 'struct range' +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dev_pagemap *pm = NULL; + pm->range.start = 0; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_RANGE, 1, + [there is 'range' field within dev_pagemap structure]) + ]) + ]) +]) + +dnl # +dnl # Check for folio_free in dev_pagemap_ops +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_OPS_FOLIO_FREE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct dev_pagemap_ops *ops = NULL; + void (*func)(struct folio *) = ops->folio_free; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_OPS_FOLIO_FREE, 1, + [dev_pagemap_ops has folio_free member]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP], [ + AC_AMDGPU_DEV_PAGEMAP_RANGE + AC_AMDGPU_DEV_PAGEMAP_OPS_FOLIO_FREE +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 new file mode 100644 index 0000000000000..14ddb4989bbac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.13-rc2-70-g70f400d4d957 +dnl # driver core: Move the "removable" attribute from USB to core +dnl # +AC_DEFUN([AC_AMDGPU_DEV_IS_REMOVABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool res = 0; + res = dev_is_removable(NULL); + ], [ + AC_DEFINE(HAVE_DEV_IS_REMOVABLE, 1, + [dev_is_removable() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 new file mode 100644 index 0000000000000..0341249c5457b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.3-rc3-2427-g4b7d4d453fc4 +dnl # device_cgroup: Export devcgroup_check_permission +dnl # +AC_DEFUN([AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + devcgroup_check_permission(0, 0, 0, 0); + ], [devcgroup_check_permission], [security/device_cgroup.c], [ + AC_DEFINE(HAVE_DEVCGROUP_CHECK_PERMISSION, 1, [devcgroup_check_permission() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 b/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 new file mode 100644 index 0000000000000..372c0904e731a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devm_i2c_add_adapter.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc6-34-g07740c92ae57 +dnl # i2c: core: add managed function for adding i2c adapters +dnl # +AC_DEFUN([AC_AMDGPU_DEVM_I2C_ADD_ADAPTER], [ +AC_KERNEL_DO_BACKGROUND([ +AC_KERNEL_TRY_COMPILE_SYMBOL([ +#include + ], [ + devm_i2c_add_adapter(NULL, NULL); + ],[devm_i2c_add_adapter], [drivers/i2c/i2c-core-base.c],[ + AC_DEFINE(HAVE_DEVM_I2C_ADD_ADAPTER, 1, + [devm_i2c_add_adapter() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 new file mode 100644 index 0000000000000..86159c3f96200 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -0,0 +1,59 @@ +dnl # +dnl # v5.6-rc5-1663-g09606b5446c2 +dnl # dma-buf: add peer2peer flag +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_attach_ops *ptr = NULL; + ptr->allow_peer2peer = false; + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, + 1, + [struct dma_buf_attach_ops->allow_peer2peer is available]) + + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) + ],[ + dnl # + dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided + dnl # bd2275eeed5b dma-buf: drop dynamic_mapping flag + dnl # a448cb003edc drm/amdgpu: implement amdgpu_gem_prime_move_notify v2 + dnl # 2d4dad2734e2 drm/amdgpu: add amdgpu_dma_buf_pin/unpin v2 + dnl # 4993ba02635f drm/amdgpu: use allowed_domains for exported DMA-bufs + dnl # d2588d2ded0f drm/ttm: remove the backing store if no placement is given + dnl # bb42df4662a4 dma-buf: add dynamic DMA-buf handling v15 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->pin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) + ], [ + dnl # + dnl # commit v5.4-rc4-863-g15fd552d186c + dnl # dma-buf: change DMA-buf locking convention v3 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_buf_ops *dma_buf_ops = NULL; + dma_buf_ops->dynamic_mapping = true; + ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, + [dma_buf->dynamic_mapping is available]) + ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, + [dma_buf->dynamic_mapping is not available]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 new file mode 100644 index 0000000000000..f35b2f8d404ca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -0,0 +1,53 @@ +dnl # +dnl # v5.13-rc3-1424-g440d0f12b52a +dnl # dma-buf: add dma_fence_chain_alloc/free v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_chain *chain = NULL; + chain = dma_fence_chain_alloc(); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, + [dma_fence_chain_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # v5.0-1331-g7bf60c52e093 +dnl # dma-buf: add new dma_fence_chain container v7 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_chain *chain; + chain = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, + [struct dma_fence_chain is available]) + ]) + ]) +]) + +dnl # +dnl # v5.17-rc2-233-g18f5fad275ef +dnl # dma-buf: add dma_fence_chain_contained helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_contained(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_CONTAINED, 1, + [dma_fence_chain_contained() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 new file mode 100644 index 0000000000000..e82d65e149645 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc2-1312-ga25efb3863d0 +dnl # dma-buf: add dma_fence_describe and dma_resv_describe v2 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DESCRIBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_describe(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_DESCRIBE, 1, + [dma_fence_describe() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 new file mode 100644 index 0000000000000..7c07948aa5205 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.17-rc2-229-g976b6d97c623 +dnl # dma-buf: consolidate dma_fence subclass checking +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_CONTAINER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_container(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_CONTAINER, 1, [dma_fence_is_container() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 new file mode 100644 index 0000000000000..deb282b53858e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -0,0 +1,60 @@ +dnl # +dnl # v6.15-rc5-762-g549810e91815 +dnl # dma-fence: Change signature of __dma_fence_is_later +dnl # +AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence *fence = NULL; + __dma_fence_is_later(fence, 0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_FENCE_ARG, 1, + [__dma_fence_is_later() is available and has fence args]) + ],[ + dnl # + dnl # v5.1-rc2-1115-g5e498abf1485 + dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct dma_fence_ops *ops = NULL; + __dma_fence_is_later(0, 0, ops); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, + [__dma_fence_is_later() is available and has ops arg]) + ], [ + dnl # + dnl # v4.20-rc4-931-gb312d8ca3a7c + dnl # dma-buf: make fence sequence numbers 64 bit v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + __dma_fence_is_later(0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, + [__dma_fence_is_later() is available and has 2 args]) + ]) + ]) + ]) + ]) +]) + +dnl # +dnl # v6.7-rc1-17-g95ba893c9f4f +dnl # dma-buf: fix check in dma_resv_add_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_later_or_same(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_LATER_OR_SAME, 1, [dma_fence_is_later_or_same() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 new file mode 100644 index 0000000000000..5fd3aeec58e80 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -0,0 +1,38 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_ops *ops = NULL; + ops->use_64bit_seqno = false; + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO, 1, + [struct dma_fence_ops has use_64bit_seqno field]) + ]) + ]) +]) + + +dnl # +dnl # v6.3-rc2-1-gaec11c8d7cb3 +dnl # dma-buf/dma-fence: Add deadline awareness +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t deadline = 0; + struct dma_fence_ops *ops = NULL; + ops->set_deadline(NULL, deadline); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_SET_DEADLINE, 1, + [struct dma_fence_ops has callback set_deadline]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 new file mode 100644 index 0000000000000..d9e988cbc76d0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-signalling.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.8-rc2-471-g5fbff813a4a3 +dnl # dma-fence: basic lockdep annotations +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_SIGNALLING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_fence_begin_signalling(); + ],[ + AC_DEFINE(HAVE_DMA_FENCE_SIGNALLING, 1, + [test whether dma_fence_begin_signalling are available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 new file mode 100644 index 0000000000000..8054979dd1b6a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.6-rc1-33-gb83ce9cb4a46 +dnl # dma-buf: add dma_fence_timestamp helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t time; + time = dma_fence_timestamp(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_TIMESTAMP, 1, [dma_fence_TIMESTAMP() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 new file mode 100644 index 0000000000000..6f688ea3032f8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-unwrap-merge.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc2-285-g245a4a7b531c +dnl # dma-buf: generalize dma_fence unwrap & merging v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_UNWRAP_MERGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + __dma_fence_unwrap_merge(0, NULL, NULL); + ], [__dma_fence_unwrap_merge], [drivers/dma-buf/dma-fence-unwrap.c],[ + AC_DEFINE(HAVE_DMA_FENCE_UNWRAP_MERGE, 1, + [dma_fence_unwrap_merge() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 new file mode 100644 index 0000000000000..8f83620935f38 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -0,0 +1,71 @@ +dnl # +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_resv *resv = NULL; + resv->fences = NULL; + ], [ + dnl # this is the latest kernel + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1,[dma_resv->fences is available]) + ], [ + dnl # + dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex + dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, [dma_resv->seq is seqcount_ww_mutex_t]) + ], [ + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1,[dma_resv->seq is available]) + ],[ + dnl # + dnl # Trigger the bug for dma_resv->seq definition + dnl # + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, [Reporting dma_resv->seq bug]) + ]) + ]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([reservation_ww_class],[drivers/dma-buf/dma-resv.c], + [],[ + AC_DEFINE(HAVE_RESERVATION_WW_CLASS_BUG, 1, [Reporting reservation_ww_class missing]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DMA_RESV], [ + AC_AMDGPU_DMA_RESV_FENCES + AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 new file mode 100644 index 0000000000000..0b5844f8c43dc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.4-rc4-863-g15fd552d186c +dnl # dma-buf: change DMA-buf locking convention v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_IS_DYNAMIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_is_dynamic(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_IS_DYNAMIC, 1, + [dma_buf_is_dynamic() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 new file mode 100644 index 0000000000000..47bf06c5e0b65 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_array_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.17-rc6-1495-gcaaf2ae712b7 +dnl # dma-buf: Add dma_fence_array_for_each (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_ARRAY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_array_first(NULL); + ], [dma_fence_array_first], [drivers/dma-buf/dma-fence-array.c],[ + AC_DEFINE(HAVE_DMA_FENCE_ARRAY_FIRST, 1, + [dma_fence_array_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 new file mode 100644 index 0000000000000..b150200ac1f89 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_check_and_signal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.18-rc2-1390-gc891b99d25dd +dnl # dma-buf/dma-fence: Add dma_fence_check_and_signal() +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHECK_AND_SIGNAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + dma_fence_check_and_signal(NULL); + ], [dma_fence_check_and_signal], [drivers/dma-buf/dma-fence.c],[ + AC_DEFINE(HAVE_DMA_FENCE_CHECK_AND_SIGNAL, 1, + [dma_fence_check_and_signal() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 new file mode 100644 index 0000000000000..17b182f9f186a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_dedup_array.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.14-1919-g554f79d8cf32 +dnl # dma-buf: Add dma_fence_dedup_array +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + dma_fence_dedup_array(NULL, 0); + ], [dma_fence_dedup_array], [drivers/dma-buf/dma-fence-unwrap.c],[ + AC_DEFINE(HAVE_DMA_FENCE_DEDUP_ARRAY, 1, + [dma_fence_dedup_array() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 new file mode 100644 index 0000000000000..d39fec01539a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_fence_init64.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.15-rc5-1889-gbf33a0003d9e +dnl # dma-fence: Use a flag for 64-bit seqnos +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_INIT64], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_init64(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_INIT64, 1, + [dma_fence_init64() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 new file mode 100644 index 0000000000000..09d1275020880 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.7-rc5-32-gd9d200bcebc1 +dnl # dma-mapping: add generic helpers for mapping sgtable objects +dnl # +AC_DEFUN([AC_AMDGPU_DMA_MAP_SGTABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_map_sgtable(NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_MAP_SGTABLE, 1, + [dma_map_sgtable() is enabled]) + ] + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # leverage test for linux/dma-attrs.h + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 new file mode 100644 index 0000000000000..7a74bd4d25889 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -0,0 +1,17 @@ +#dnl +#dnl commit v4.14-rc4-65-g76f8507f7a64 +#dnl locking/rwsem: Add down_read_killable() +#dnl +AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + int ret; + ret = down_read_killable(NULL); + ],[down_read_killable], [kernel/locking/rwsem.c],[ + AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + [down_read_killable() is available])] + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..8596ee2770a7f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,41 @@ +dnl # +dnl # commit v5.13-rc3-1543-g97c9bfe3f660 +dnl # drm/aperture: Pass DRM driver structure instead of driver name +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + struct drm_driver; + ], [ + const struct drm_driver *drv = NULL; + drm_aperture_remove_conflicting_pci_framebuffers(NULL, drv); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG, 1, + [drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver*]) + ]) + ]) +]) + +dnl # +dnl # v5.19-rc2-317-g7283f862bd99 +dnl # drm: Implement DRM aperture helpers under video/ +dnl # +AC_DEFUN([AC_AMDGPU_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + aperture_remove_conflicting_pci_devices(NULL, NULL); + ], [ + AC_DEFINE(HAVE_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES, 1, + [aperture_remove_conflicting_pci_device() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 new file mode 100644 index 0000000000000..33ab26677d24f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.0-rc1-415-g022debad063e +dnl # drm/atomic: Add drm_atomic_state->duplicated +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_atomic_state *state = NULL; + state->duplicated = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED, 1, + [struct drm_connector_state->duplicated is available]) + ]) + ]) +]) + +dnl # +dnl # drm/atomic: Add drm_atomic_state->plane_color_pipeline +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_atomic_state *state = NULL; + state->plane_color_pipeline = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE, 1, + [struct drm_atomic_state->plane_color_pipeline is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 new file mode 100644 index 0000000000000..c5a71aac5af1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit c42b65e363ce introduce this change +dnl # v4.17-3-gc42b65e363ce +dnl # bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_free(NULL); + bitmap_alloc(0, 0); + bitmap_zalloc(0, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_FUNCS, + 1, + [bitmap_free(),bitmap_alloc(),bitmap_zalloc is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 new file mode 100644 index 0000000000000..42911c2cc2131 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 913b2cb727b7a47ccf8842d54c89f1b873c6deed +dnl # drm: change func to better detect wether swiotlb is needed +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CACHE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_need_swiotlb(0); + ], [ + AC_DEFINE(HAVE_DRM_NEED_SWIOTLB, 1, + [drm_need_swiotlb() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 new file mode 100644 index 0000000000000..c0d45ec249beb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-client.m4 @@ -0,0 +1,44 @@ +dnl # +dnl # commit v6.11-rc7-1514-gd07fdf922592 +dnl # drm: Add client-agnostic setup helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_CLIENT_SETUP_H + #include + #endif + #ifdef HAVE_DRM_CLIENTS_DRM_CLIENT_SETUP_H + #include + #endif + ], [ + drm_client_setup(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_CLIENT_SETUP, 1, + [drm_client_setup() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.12-rc2-587-gbf17766f1083 +dnl # drm/client: Move suspend/resume into DRM client callbacks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_DEV_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_client_dev_resume(NULL); + ], [ + AC_DEFINE(HAVE_DRM_CLIENT_DEV_RESUME, 1, + [drm_client_dev_resume() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CLIENT], [ + AC_AMDGPU_DRM_CLIENT_SETUP + AC_AMDGPU_DRM_CLIENT_DEV_RESUME +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 new file mode 100644 index 0000000000000..211e6fdd63702 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1582-g72921cdf8ac2 +dnl # drm/connector: Add helper to compare HDR metadata +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_atomic_hdr_metadata_equal(NULL, NULL); + ], [drm_connector_atomic_hdr_metadata_equal], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, + [drm_connector_atomic_hdr_metadata_equal() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 new file mode 100644 index 0000000000000..7ea380c7d60eb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1581-ge057b52c1d90 +dnl # drm/connector: Create a helper to attach the hdr_output_metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_attach_hdr_output_metadata_property(NULL); + ], [drm_connector_attach_hdr_output_metadata_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, + [drm_connector_attach_hdr_output_metadata_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 new file mode 100644 index 0000000000000..7c3454c843d50 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # dfbe9bf0 introduce this change +dnl # drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi +dnl # v5.13-3121-gdfbe9bf067a2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->is_hdmi = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_IS_HDMI, 1, + [display_info->is_hdmi is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 new file mode 100644 index 0000000000000..0f57128fcf1a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.3-rc1-656-g62afb4ad425a +dnl # drm/connector: Allow max possible encoders to attach to a connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + drm_connector_for_each_possible_encoder(connector, encoder) + return 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS, 1, + [drm_connector_for_each_possible_encoder() wants 2 arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 new file mode 100644 index 0000000000000..4495fbe5cb695 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -0,0 +1,63 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) + +dnl # +dnl # v5.10-rc3-1075-geca22edb37d2 +dnl # drm: Pass the full state to connectors atomic functions +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_best_encoder(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE, 1, + [atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state]) + ]) + ]) +]) + +dnl # +dnl # v6.13-rc2-288-g26d6fd81916e +dnl # drm/connector: make mode_valid take a const struct drm_display_mode +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum drm_mode_status (*p)(struct drm_connector *, const struct drm_display_mode *) = NULL; + + struct drm_connector_helper_funcs test_funcs; + test_funcs.mode_valid = p; + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_CONST_ARGUMENT, 1, + [.mode_valid need a const drm_display_mode argument]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_MODE_VALID_CONST_ARGUMENT +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 new file mode 100644 index 0000000000000..9af2f9f8226b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-330-g100163df4203 +dnl # drm: Add drm_connector_init() variant with ddc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_init_with_ddc(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_INIT_WITH_DDC, 1, + [drm_connector_init_with_ddc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 new file mode 100644 index 0000000000000..0ae5de382dec8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.5-rc2-1360-g69654c632d80 +dnl # drm/connector: Split out orientation quirk detection (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_panel_orientation_with_quirk(NULL, 0, 0, 0); + ],[drm_connector_set_panel_orientation_with_quirk], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, + [drm_connector_set_panel_orientation_with_quirk() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 new file mode 100644 index 0000000000000..6d852b75d9e05 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc1-377-g7672dbba85d3 +dnl # drm: Add Content protection type property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdcp_content_type = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE, 1, + [struct drm_connector_state has hdcp_content_type member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 new file mode 100644 index 0000000000000..d79d5c876e35b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.1-rc5-1688-gfbb5d0353c62 +dnl # drm: Add HDR source metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdr_output_metadata = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA, 1, + [struct drm_connector_state has hdr_output_metadata member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 new file mode 100644 index 0000000000000..69753da371891 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v4.20-rc3-425-g1398958cfd8d +dnl # drm: Add vrr_enabled property to drm CRTC +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [struct drm_connector_state->colorspace is available]) + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->self_refresh_aware = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE, 1, + [struct drm_connector_state->self_refresh_aware is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 new file mode 100644 index 0000000000000..01791b2a42e79 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # v6.1-rc1-146-g90b575f52c6a +dnl # drm/edid: detach debugfs EDID override from EDID property update +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector *connector = NULL; + connector->edid_override = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_EDID_OVERRIDE, 1, + [drm_connector->edid_override is available]) + ]) + ]) +]) + +dnl # +dnl # v6.13-rc2-179-gdf7c8e3dde37 +dnl # drm/connector: add mutex to protect ELD from concurrent access +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ELD_MUTEX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector connector; + void *ptr = &connector.eld_mutex; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_ELD_MUTEX, 1, + [drm_connector->eld_mutex is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STRUCT_MEMBER], [ + AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE + AC_AMDGPU_DRM_CONNECTOR_ELD_MUTEX +]) + +dnl # +dnl # v6.13-rc2-201-g1d985ddabbe0 +dnl # drm/connector: Add a way to init/add a connector in separate steps +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_dynamic_init(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_DYNAMIC_INIT, 1, + [drm_connector_dynamic_init is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 new file mode 100644 index 0000000000000..5bfb416a8ed5e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -0,0 +1,45 @@ +dnl # +dnl # v5.10-rc2-260-g29b77ad7b9ca +dnl # drm/atomic: Pass the full state to CRTC atomic_check +dnl +dnl # v5.10-rc2-261-gf6ebe9f9c923 +dnl # drm/atomic: Pass the full state to CRTC atomic begin and flush +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg]) + ]) + ]) +]) + +dnl # +dnl # v5.9-rc5-1161-g351f950db4ab +dnl # drm/atomic: Pass the full state to CRTC atomic enable/disable +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_enable(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct drm_atomic_state arg]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 new file mode 100644 index 0000000000000..cc6860f55c68e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc3-2032-g4d85f45c73a2 +dnl # drm/atomic: Rename crtc_state->pageflip_flags to async_flip +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_state *crtc_state = NULL; + crtc_state->async_flip = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP, 1, + [struct drm_crtc_state->async_flip is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 new file mode 100644 index 0000000000000..64e4926c74f1d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-wedged-event.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v6.16-rc1-333-g183bccafa176 +dnl # drm: Create a task info option for wedge events +dnl # +dnl # commit v6.14-rc1-238-gb7cf9f4ac1b8 +dnl # drm: Introduce device wedged event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_WEDGED_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dev_wedged_event(NULL, 0, NULL); + ], [drm_dev_wedged_event], [drivers/gpu/drm/drm_drv.c], [ + AC_DEFINE(HAVE_DRM_DEV_WEDGED_EVENT, 1, + [drm_dev_wedged_event() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 new file mode 100644 index 0000000000000..7bbbd70aab907 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit b347e04452ff6382ace8fba9c81f5bcb63be17a6 +dnl # drm: Remove pdev field from struct drm_device +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_device *pdd = NULL; + pdd->pdev = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_PDEV, 1, [struct drm_device has pdev member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 new file mode 100644 index 0000000000000..0ae82ec0ca780 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -0,0 +1,82 @@ +dnl # +dnl # commit v5.16-rc5-908-g4adc33f36d80 +dnl # drm/edid: Split deep color modes between RGB and YUV444 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->edid_hdmi_rgb444_dc_modes = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES, 1, + [display_info->edid_hdmi_rgb444_dc_modes is available]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.6-rc2-1062-ga1d11d1efe4d +dnl # drm/edid: Add function to parse EDID descriptors for monitor range +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->monitor_range.min_vfreq=0; + info->monitor_range.max_vfreq=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE, 1, + [struct drm_display_info has monitor_range member]) + ]) + ]) +]) + +dnl # +dnl # commit v5.18-3347-g721ed0ae5acf +dnl # drm/edid: add a quirk for two LG monitors to get them to work on 10bpc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->max_dsc_bpp=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP, 1, + [display_info->max_dsc_bpp is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1~27-a61bb3422e8d +dnl # drm/amdgpu_dm: Rely on split out luminance calculation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + struct drm_luminance_range_info *luminance_range; + luminance_range = &display_info->luminance_range; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, + [display_info->luminance_range is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES + AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE + AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP + AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 new file mode 100644 index 0000000000000..c0441f45a7861 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -0,0 +1,134 @@ +dnl # +dnl # commit edb1ed1ab7d314e114de84003f763da34c0f34c0 +dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.19-rc6-1758-gdf78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ],[ + dnl # + dnl # commit v4.20-rc4-1031-geceae1472467 + dnl # drm/dp_mst: Start tracking per-port VCPI allocations + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + struct drm_dp_mst_port *port = NULL; + ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + ]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.19-rc6-1758-gdf78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, + [drm_dp_atomic_find_time_slots() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_setup_commit(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_SETUP_COMMIT, 1, + [drm_dp_mst_atomic_setup_commit() is available]) + ]) + ]) +]) + +drm_dp_mst_atomic_wait_for_dependencies + +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_dp_mst_atomic_wait_for_dependencies(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, + [drm_dp_mst_atomic_wait_for_dependencies() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK, 1, + [drm_dp_mst_root_conn_atomic_check() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT + AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES + AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 new file mode 100644 index 0000000000000..cef22c56ee51c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.12-rc7-1495-g6cba3fe43341 +dnl # drm/dp: Add backpointer to drm_device in drm_dp_aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux dda; + dda.drm_dev = NULL; + ], [],[],[ + AC_DEFINE(HAVE_DRM_DP_AUX_DRM_DEV, 1, + [struct drm_dp_aux has member named 'drm_dev']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 new file mode 100644 index 0000000000000..7261c98f40b18 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v5.5-rc2-902-gdc48529fb14e +dnl # drm/dp_mst: Add PBN calculation for DSC modes +dnl # +dnl #v6.6-rc2-668-g7707dd602259 +dnl #drm/dp_mst: Fix fractional DSC bpp handling +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_calc_pbn_mode(0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, + [drm_dp_calc_pbn_mode() wants 3 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 new file mode 100644 index 0000000000000..3ded1ff2015a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-555-gae85b0df124f +dnl # drm_dp_cec: add connector info support. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_cec_register_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP, 1, + [drm_dp_cec_register_connector() wants p,p interface]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 new file mode 100644 index 0000000000000..75d4ab579bdb8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1498-g0c4fada608c1 +dnl # drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE] = {0}; + drm_dp_link_train_channel_eq_delay(aux, dpcd); + ], [drm_dp_link_train_channel_eq_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, + [drm_dp_link_train_channel_eq_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 new file mode 100644 index 0000000000000..a9aaff5a764a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1497-g9e9866664456 +dnl # drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE] = {0}; + drm_dp_link_train_clock_recovery_delay(aux, dpcd); + ], [drm_dp_link_train_clock_recovery_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, + [drm_dp_link_train_clock_recovery_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 new file mode 100644 index 0000000000000..c9127ca8d82c3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 971fb192aaeb4b5086ac3f21d00943a5e1431176 +dnl # drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, + [drm_dp_mst_add_affected_dsc_crtcs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 new file mode 100644 index 0000000000000..e56284f5a5a2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit eceae147246749c6dbaeefda802b30f804a3c54c +dnl # drm/dp_mst: Start tracking per-port VCPI allocations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_atomic_check(NULL); + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, + [drm_dp_mst_atomic_check() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 new file mode 100644 index 0000000000000..ad901210aeaba --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit 0529a1d385b9ce6cd7498d180f720eeb3f755980 +dnl # drm/dp_mst: Add DSC enablement helpers to DRM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); + ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_mst_atomic_enable_dsc() is available]) + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS, 1, + [drm_dp_mst_atomic_enable_dsc() wants 5args]) + ],[ + dnl # + dnl # commit 4d07b0bc403403438d9cf88450506240c5faf92f + dnl # drm/display/dp_mst: Move all payload info into the atomic state + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int vcpi; + vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 new file mode 100644 index 0000000000000..4198140ed6a0e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-752-g3f9b3f02dda5 +dnl # drm/dp_mst: Protect drm_dp_mst_port members with locking +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_DETECT_PORT_PPPP, 1, + [drm_dp_mst_detect_port() wants p,p,p,p args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 new file mode 100644 index 0000000000000..6d83fb019062d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit d251c02a2b78245bb32d7909a66b06285f7922a2 +dnl # drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_dsc_aux_for_port(NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, + [drm_dp_mst_dsc_aux_for_port() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 new file mode 100644 index 0000000000000..e45e020edc7fc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.6-rc5-4-gfcf463807596 +dnl # drm/dp_mst: Use full_pbn instead of available_pbn for bandwidth checks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_port *mst_port = NULL; + mst_port->full_pbn = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_FULL_PBN, 1, + [drm_dp_mst_port struct has full_pbn member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 new file mode 100644 index 0000000000000..c66ffa1496233 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.18-2579-g3af4b1f1d6e7 +dnl # "drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_port *dp_mst_port = NULL; + dp_mst_port->passthrough_aux = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX, 1, + [struct drm_dp_mst_port has passthrough_aux member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 new file mode 100644 index 0000000000000..4e54d919e6a3c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -0,0 +1,76 @@ +dnl # +dnl # commit v4.20-rc4-941-g16bff572cc66 +dnl # drm/dp-mst-helper: Remove hotplug callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->hotplug(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG, 1, + [struct drm_dp_mst_topology_cbs has hotplug member]) + ]) +]) + + +dnl # +dnl # commit v5.6-rc2-1065-ga5c4dc165957 +dnl # drm/dp_mst: Remove register_connector callback +dnl # +dnl # commit v4.3-rc3-39-gd9515c5ec1a2 +dnl # drm/dp/mst: split connector registration into two parts (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->register_connector(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->register_connector is available]) + ]) +]) + +dnl # +dnl # commit v5.6-rc5-1703-g72dc0f515913 +dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->destroy_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->destroy_connector is available]) + ]) +]) + +dnl # +dnl # commit v5.7-rc1-646-g471bdd0df0d5 +dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->poll_hpd_irq(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ, 1, + [struct drm_dp_mst_topology_cbs->poll_hpd_irq is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 new file mode 100644 index 0000000000000..3c491e182062e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-759-g6f85f73821f6 +dnl # drm/dp_mst: Add basic topology reprobing when resuming +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_topology_mgr_resume(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS, 1, + [drm_dp_mst_topology_mgr_resume() wants 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 new file mode 100644 index 0000000000000..1755debc25f59 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -0,0 +1,89 @@ +dnl # +dnl # commit v5.15-rc2-1075-gd6c6a76f80a1 +dnl # Update MST First Link Slot Information Based on Encoding Format +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + mst_state->total_avail_slots = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS, 1, + [struct drm_dp_mst_topology_state has member total_avail_slots]) + ]) + ]) +]) + + +dnl # +dnl # commit 8366f01fb15a54281c193658d1a916f6f2d5eb1e +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + struct list_head payloads; + payloads = mst_state->payloads; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS, 1, + [struct drm_dp_mst_topology_state has member payloads]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + mst_state->pbn_div = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT, 1, + [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + fixed20_12 pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION, 1, + [struct drm_dp_mst_topology_state has union member pbn_div]) + ]) + ]) +]) + +dnl # +dnl # commit v6.9-rc6-1554-g8a0a7b98d4b6 +dnl # drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int a = 0; + a = drm_dp_add_payload_part2(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS, 1, + [drm_dp_add_payload_part2 has three arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 new file mode 100644 index 0000000000000..6de9a34aa627d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -0,0 +1,45 @@ +dnl # +dnl # commit 1e797f556c616a42f1e039b1ff1d3c58f61b6104 +dnl # drm/dp: Split drm_dp_mst_allocate_vcpi +dnl # +dnl # Note: This autoconf only works with compiler flag -Werror +dnl # The interface types are specified in Hungarian notation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ + dnl # + dnl # commit d25689760b747287c6ca03cfe0729da63e0717f4 + dnl # drm/amdgpu/display: Keep malloc ref to MST port + dnl # + dnl # commit ebcc0e6b509108b4a67daa4c55809a05ab7f4b77 + dnl # drm/dp_mst: Introduce new refcounting scheme for mstbs and ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_get_port_malloc(NULL); + drm_dp_mst_put_port_malloc(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC, 1, [ + drm_dp_mst_{get,put}_port_malloc() is available]) + ]) + ]) + dnl # + dnl # commit aad0eab4e8dd76d1ba5248f9278633829cbcec38 + dnl # drm/dp_mst: Enable registration of AUX devices for MST ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_connector_early_unregister(NULL, NULL); + drm_dp_mst_connector_late_register(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + drm_dp_mst_connector_early_unregister() is available]) + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + drm_dp_mst_connector_late_register() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 new file mode 100644 index 0000000000000..10468731e64f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.3-5135-g7c5343f2a753 +dnl # "drm/mst: Refactor the flow for payload allocation/removement" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_remove_payload_part1(NULL, NULL, NULL); + ], [drm_dp_remove_payload_part1],[drivers/gpu/drm/display/drm_dp_mst_topology.c],[ + AC_DEFINE(HAVE_DRM_DP_REMOVE_RAYLOAD_PART, 1, + [drm_dp_remove_payload_part{1,2}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 new file mode 100644 index 0000000000000..44343cb753bbe --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit e11f5bd8228fc3760c221f940b9f6365dbf3e7ed +dnl # drm: Add support for DP 1.4 Compliance edid corruption test +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_send_real_edid_checksum(NULL, 0); + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, + [drm_dp_send_real_edid_checksum() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 new file mode 100644 index 0000000000000..b936fb17b95c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-date.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.13-rc1-117-gcb2e1c2136f7 +dnl # drm: remove driver date from struct drm_driver and all drivers +dnl # +dnl # v4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_DATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_driver *drm_driver = NULL; + drm_driver->date = NULL; + ],[ + AC_DEFINE(HAVE_DRM_DRIVER_DATE, 1, + [drm_driver->date is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 new file mode 100644 index 0000000000000..5ca66e8289bc1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d +dnl # drm: Switch DRIVER_ flags to an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ + dnl # + dnl # commit: v5.1-rc5-1467-g060cebb20cdb + dnl # drm: introduce a capability flag for syncobj timeline support + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + int flag; + flag = DRIVER_SYNCOBJ_TIMELINE; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ]) + + dnl # + dnl # commit: v5.0-rc1-390-g1ff494813baf + dnl # drm/irq: Ditch DRIVER_IRQ_SHARED + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + int flag; + flag = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) + ]) + ]) + + dnl # + dnl # commit: v5.2-rc5-867-g0424fdaf883a + dnl # drm/prime: Actually remove DRIVER_PRIME everywhere + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + int flag; + flag = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 new file mode 100644 index 0000000000000..0030f68fac152 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -0,0 +1,50 @@ +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # commit v5.10-rc2-329-g49a3f51dfeee + dnl # drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + funcs->vmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS, 1, [drm_gem_object_funcs->vmap() has 2 args]) + ],[ + dnl # commit v5.9-rc5-1077-gd693def4fd1c + dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.17-rc2-157-g7938f4218168 +dnl # dma-buf-map: Rename to iosys-map +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + struct iosys_map *map = NULL; + funcs->vmap(NULL, map); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG, 1, + [drm_gem_object_funcs.vmap hsa iosys_map arg]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 new file mode 100644 index 0000000000000..80cba3a5a1459 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -0,0 +1,38 @@ +dnl # +dnl # commit v5.3-rc1-325-g51c98747113e +dnl # drm/amdgpu: Fill out gem_object->resv +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_res_obj(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ, 1, + [drm_driver->gem_prime_res_obj() is available]) + ]) + ]) +]) +dnl # +dnl # commit 4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +dnl # commit v6.4-rc2-425-g0adec22702d4 +dnl # drm: Remove struct drm_driver.gem_prime_mmap +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_mmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_MMAP, 1, + [drm_driver->gem_prime_mmap() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 new file mode 100644 index 0000000000000..bac95ca04518c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-870-ge4fa8457b219 +dnl # drm/prime: Align gem_prime_export with obj_funcs.export +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_prime_export(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI, 1, + [drm_gem_prime_export() with p,i arg is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 new file mode 100644 index 0000000000000..e2a939c448834 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -0,0 +1,67 @@ +dnl # +dnl # 13d0add333afea7b2fef77473232b10dea3627dd +dnl # drm/edid: Pass connector to AVI infoframe functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + struct drm_connector *connector = NULL; + const struct drm_display_mode *mode = NULL; + drm_hdmi_avi_infoframe_from_display_mode(frame, connector, mode); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface]) + ], [ + dnl # + dnl # 10a8512008655d5ce62f8c56323a6b5bd221c920 + dnl # drm: Add HDMI infoframe helpers + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + const struct drm_display_mode *mode = NULL; + bool is_hdmi2_sink = false; + drm_hdmi_avi_infoframe_from_display_mode(frame, mode, is_hdmi2_sink); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface]) + ]) + ]) + ]) +]) + +dnl # +dnl # v6.1-rc1-143-g019b93874834 +dnl # drm/edid: rename drm_add_override_edid_modes() to drm_edid_override_connector_update() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_edid_override_connector_update(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE, 1, + [drm_edid_override_connector_update() is available]) + ],[ + dnl # + dnl # v5.2-rc2-25-g48eaeb7664c7 + dnl # drm: add fallback override/firmware EDID modes workaround + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_add_override_edid_modes(NULL); + ],[ + AC_DEFINE(HAVE_DRM_ADD_OVERRIDE_EDID_MODES, 1, + [drm_add_override_edid_modes() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 new file mode 100644 index 0000000000000..7eddabe7c8387 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit ec8bf1942567bf0736314da9723e93bcc73c131f +dnl # drm/fb-helper: Fixup fill_info cleanup +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 new file mode 100644 index 0000000000000..8e907a5616852 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-file.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit fd265d9e0c3358e6 +dnl # drm: add drm_memory_stats_is_zero +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMORY_STATS_IS_ZERO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memory_stats_is_zero(NULL); + ], [ + AC_DEFINE(HAVE_DRM_MEMORY_STATS_IS_ZERO, 1, + [drm_memory_stats_is_zero() is available]) + ]) + ]) +]) + +dnl # +dnl # commit fd265d9e0c3358e6 +dnl # drm: add drm_memory_stats_is_zero +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_memory_stats *stats; + stats = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_MEMORY_STATS, 1, + [struct drm_memory_stats is defined]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MEMORY_STATS], [ + AC_AMDGPU_DRM_MEMORY_STATS_IS_ZERO + AC_AMDGPU_STRUCT_DRM_MEMORY_STATS +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 new file mode 100644 index 0000000000000..8f42e769f8845 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlocked() +dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put +dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_gem_object_put(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, + [drm_gem_object_put() is available]) + + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_object_put(NULL); + ],[drm_gem_object_put],[drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) + ]) + ]) + ]) +]) + +dnl # +dnl # v6.8-rc3-286-gb31f5eba32ae drm: add drm_gem_object_is_shared_for_memory_stats() helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_gem_object_is_shared_for_memory_stats(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS, 1, + [drm_gem_object_is_shared_for_memory_stats() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 new file mode 100644 index 0000000000000..55570026acaff --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-380-gbb5a45d40d50 +dnl # drm/hdcp: update content protection property with uevent +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_hdcp_update_content_protection(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION, 1, + [drm_hdcp_update_content_protection is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 new file mode 100644 index 0000000000000..b2892203adf76 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -0,0 +1,154 @@ +AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ + dnl # + dnl # RHEL 7.x wrapper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_backport.h]) + + dnl # + dnl # Optional devices ID for amdgpu driver + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) + + dnl # + dnl # commit v5.0-rc1-342-gfcd70cd36b9b + dnl # drm: Split out drm_probe_helper.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_probe_helper.h]) + + dnl # + dnl # v5.4-rc1-214-g4e98f871bcff + dnl # drm: delete drmP.h + drm_os_linux.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drmP.h]) + + dnl # + dnl # commit v5.5-rc2-783-g368fd0aad1be + dnl # drm: Add Reusable task barrier. + dnl # + AC_KERNEL_CHECK_HEADERS([drm/task_barrier.h]) + + dnl # + dnl # v5.6-rc5-1258-gc6603c740e0e + dnl # drm: add managed resources tied to drm_device + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + + dnl # + dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amd_asic_type.h]) + + dnl # + dnl # v5.12-rc3-330-g2916059147ea + dnl # drm/aperture: Add infrastructure for aperture ownership + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + + dnl # + dnl # v5.15-rc1-290-ga1a98689301b + dnl # drm: Add privacy-screen class (v4) + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_privacy_screen_consumer.h]) + + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + + dnl # + dnl # v5.11-rc2-620-g6dd7b6ce43ac + dnl # drm: Add additional atomic helpers for shadow-buffered planes + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_atomic_helper.h]) + + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp.h]) + + dnl # + dnl # v5.7-13141-gca5999fde0a1 + dnl # mm: introduce include/linux/pgtable.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) + + dnl # + dnl # v6.1-rc2-542-g8ab59da26bc0 + dnl # drm/fb-helper: Move generic fbdev emulation into separate source file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + + dnl # + dnl # v6.2-rc6-1265-g849ee8a2f0df + dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) + + dnl # + dnl # v6.6-rc2-771-g8eb80946ab0c + dnl # drm/edid: split out drm_eld.h from drm_edid.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) + + dnl # + dnl # v6.9-rc2-212-ge2a1cda3e0c7 + dnl # drm/panic: Add drm panic locking + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_panic.h]) + + dnl # + dnl # v6.9-rc6-1436-gaae4682e5d66 + dnl # drm/fbdev-generic: Convert to fbdev-ttm + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_ttm.h]) + + dnl # + dnl # v6.12-rc1-3-g5f60d5f6bbc1 + dnl # move asm/unaligned.h to linux/unaligned.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/unaligned.h]) + + dnl # + dnl # v6.11-rc7-1514-gd07fdf922592 + dnl # drm: Add client-agnostic setup helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_client_setup.h]) + + dnl # + dnl # v6.12-rc6-1222-gb86711c6d6e2 + dnl # drm/client: Move public client header to clients/ subdirectory + dnl # + AC_KERNEL_CHECK_HEADERS([drm/clients/drm_client_setup.h]) + + dnl # + dnl # v6.12-rc2-586-gdf7e8b522a60 + dnl # drm/client: Move client event handlers to drm_client_event.c + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_client_event.h]) + + dnl # + dnl # drm: Add color operation + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_colorop.h]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 new file mode 100644 index 0000000000000..2bb2ec7fade6e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.15-rc2-1274-g710074bb8ab0 +dnl # drm/probe-helper: add drm_kms_helper_connector_hotplug_event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_kms_helper_connector_hotplug_event(NULL); + ], [ + AC_DEFINE(HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT, 1, + [drm_kms_helper_connector_hotplug_event() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 new file mode 100644 index 0000000000000..8ab4aaf2521dc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit b7e32bef4ae5f9149276203564b7911fac466588 +dnl # drm: Add a prefetching memcpy_from_wc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct iosys_map *dst = NULL, *src = NULL; + drm_memcpy_from_wc(dst, src, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG, 1, + [drm_memcpy_from_wc() is availablea and has struct iosys_map* arg]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 new file mode 100644 index 0000000000000..9a220e320f721 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.17-rc2-403-g2d3eec897033 +dnl # drm: Add drm_mode_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_init(NULL, NULL); + ], [drm_mode_init], [drivers/gpu/drm/drm_modes.c], [ + AC_DEFINE(HAVE_DRM_MODE_INIT, 1, + [drm_mode_init() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 new file mode 100644 index 0000000000000..e4a2a7d627810 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit: v6.1-rc1-27-30c637151cfa +dnl # drm/plane-helper: Export individual helpers +dnl # + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_DESTROY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_plane_helper_destroy(NULL); + ], [ + AC_DEFINE(HAVE_DRM_PLANE_HELPER_DESTROY, 1, + [drm_plane_helper_destroy() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_DRM_PLANE_HELPER_DESTROY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 new file mode 100644 index 0000000000000..cae3e54d7c7f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e +dnl # drm: allow limiting the scatter list size. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 new file mode 100644 index 0000000000000..a144bfa3967d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_show_fdinfo(NULL, NULL); + ],[drm_show_fdinfo], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_SHOW_FDINFO, 1, [drm_show_fdinfo() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_driver *drm_driver = NULL; + + drm_driver->show_fdinfo(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_SHOW_FDINFO, 1, + [drm_driver->show_fdinfo() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_SHOW_FDINFO], [ + AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO + AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 new file mode 100644 index 0000000000000..1b341003bb985 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-2803-gcf95d5c0c941 +dnl # drm: Update MST First Link Slot Information Based on Encoding Format +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_update_payload_part1(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG, 1, + [drm_dp_update_payload_part1() function has start_slot argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 new file mode 100644 index 0000000000000..d2f9038b46063 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc2-247-gd12e36494dc2 +dnl # drm/vblank: Introduce drm_crtc_vblank_crtc() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_VBLANK_CRTC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_crtc_vblank_crtc(NULL); + ],[ + AC_DEFINE(HAVE_CRTC_DRM_VBLANK_CRTC, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 new file mode 100644 index 0000000000000..06ca73cc0fe91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-rc3-1382-gf425821b9468 +dnl # drm/vma: Add a driver_private member to vma_node. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vma_offset_node *node = NULL; + node->readonly = false; + ], [ + AC_DEFINE(HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD, 1, [struct drm_vma_offset_node has readonly field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 new file mode 100644 index 0000000000000..f4c7be22ebded --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # v5.12-rc3-332-g603dc7ed917f drm/aperture: Inline fbdev conflict helpers into aperture helpers +dnl # v5.12-rc3-330-g2916059147ea drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_DRM_DRM_APERTURE_H = x ], [ + dnl # + dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers + dnl # + AC_KERNEL_TRY_COMPILE([ + struct task_struct; + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [remove_conflicting_pci_framebuffers() wants p,p args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 new file mode 100644 index 0000000000000..7b6d31518fe3c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.9-rc5-1595-ge1ad957d45f7 +dnl # Extract drm_atomic_helper_calc_timestamping_constants() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_atomic_helper_calc_timestamping_constants(NULL); + ],[drm_atomic_helper_calc_timestamping_constants], [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, + [drm_atomic_helper_calc_timestamping_constants() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 new file mode 100644 index 0000000000000..5fe466630d8dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc6-1230-g169b9182f192 +dnl # drm/atomic-helper: Add atomic_enable plane-helper callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_atomic_plane_enabling(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_ATOMIC_PLANE_ENABLING, 1, + [drm_atomic_plane_enabling() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 new file mode 100644 index 0000000000000..ef060260bee20 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.1-rc2-1103-ge33898a20744 +dnl # drm/client: Rename drm_client_add() to drm_client_register() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_client_register(NULL); + ],[ + AC_DEFINE(HAVE_DRM_CLIENT_REGISTER, 1, + [drm_client_register() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 new file mode 100644 index 0000000000000..11f356754b2c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc1-14-g9d2230dc1351 +dnl # drm: writeback: Add job prepare and cleanup operations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_helper_funcs *funcs = NULL; + funcs->prepare_writeback_job((struct drm_writeback_connector *)NULL, (struct drm_writeback_job *)NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, + [drm_connector_helper_funcs->prepare_writeback_job is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 new file mode 100644 index 0000000000000..88be95171ea7b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -0,0 +1,54 @@ +dnl # +dnl # commit v5.3-rc1-708-gf0a8f533adc2 +dnl # drm/print: add drm_debug_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.8-rc3-242-g9fd6f61a297e +dnl # drm/print: add drm_dbg_printer() for drm device specific printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_dbg_printer(NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DBG_PRINTER, + 1, + [drm_dbg_printer() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v5.4-rc4-974-g876905b8fe59 +dnl # drm/print: convert debug category macros into an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_CATEGORY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + enum drm_debug_category category; + category = DRM_UT_CORE; + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_CATEGORY, + 1, + [enum drm_debug_category is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 new file mode 100644 index 0000000000000..ab697ac5c5a3b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_aux_dpcd_probe_disabled.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc1-124-gb87ed522b364 +dnl # drm/dp: Add an EDID quirk for the DPCD register access probe +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + aux->dpcd_probe_disabled = false; + ], [ + AC_DEFINE(HAVE_DRM_DP_AUX_DPCD_PROBE_DISABLED, 1, + [drm_dp_aux->dpcd_probe_disabled is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 new file mode 100644 index 0000000000000..b17bff9ecd850 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_cec_attach.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.5-rc2-872-g113cdddcded6 +dnl # drm/cec: add drm_dp_cec_attach() as the non-edid version of set edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_ATTACH], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_cec_attach(NULL, 0); + ], [drm_dp_cec_attach], [drivers/gpu/drm/display/drm_dp_cec.c], [ + AC_DEFINE(HAVE_DRM_DP_CEC_ATTACH, 1, + [drm_dp_cec_attach() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 new file mode 100644 index 0000000000000..6d733484238af --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_edid_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.4-rc2-497-gc1c9042b2003 +dnl # drm/display/dp_mst: convert to struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_EDID_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_edid_read(NULL, NULL, NULL); + ], [drm_dp_mst_edid_read], [drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_EDID_READ, 1, + [drm_dp_mst_edid_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 new file mode 100644 index 0000000000000..a70fd97681104 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-4472-g55970ce50152 +dnl # drm/dp_mst: Clear MSG_RDY flag before sending new message +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_hpd_irq_handle_event(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT, 1, + [drm_dp_mst_hpd_irq_handle_event() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 new file mode 100644 index 0000000000000..b25b157e9d1e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.12-rc7-1527-g98025a62cb00 +dnl # drm/dp_mst: Use Extended Base Receiver Capability DPCD space +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT, 1, + [drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate]) + + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 new file mode 100644 index 0000000000000..1aace85d3c0f1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_queue_probe.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3523-gb1c1c23eae66 +dnl # drm/dp_mst: Add a helper to queue a topology probe +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_topology_queue_probe(NULL); + ], [drm_dp_mst_topology_queue_probe], [drivers/gpu/drm/display/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE, 1, + [drm_dp_mst_topology_queue_probe() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 new file mode 100644 index 0000000000000..8306568c2e0ca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.9-rc1-294-gb9936121d95b +dnl # drm/i915/dp: Extract drm_dp_read_dpcd_caps() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_read_dpcd_caps(NULL, NULL); + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c drivers/gpu/drm/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, + [drm_dp_read_dpcd_caps() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 new file mode 100644 index 0000000000000..527068f2403f8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.8-rc2-671-ge5b92773287c drm: report dp downstream port type as a subconnector property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SUBCONNECTOR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->dp_subconnector_property = NULL; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY, 1, + [drm_mode_config->dp_subconnector_property is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 new file mode 100644 index 0000000000000..a6f72c8fe6ba9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dsc_compute_rc_parameters(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS, 1, + [drm_dsc_compute_rc_parameters() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 new file mode 100644 index 0000000000000..e10e43c6dfe6c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.20-rc3-804-g19fd5adbb595 +dnl # drm/dsc: Define VESA Display Stream Compression Capabilities +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dsc_config *conf = NULL; + conf->simple_422 = true; + ], [ + AC_DEFINE(HAVE_DRM_DSC_CONFIG_SIMPLE_422, 1, + [struct drm_dsc_config has member simple_422]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 new file mode 100644 index 0000000000000..b85668160976c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dsc_pps_payload_pack(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_PPS_PAYLOAD_PACK, 1, + [drm_dsc_pps_payload_pack() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 new file mode 100644 index 0000000000000..86301a9a861f4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.18-rc5-1218-g6537f79a2aae +dnl # drm/edid: add new interfaces around struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_MALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_alloc(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_EDID_MALLOC, 1, + [drm_edid_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v5.19-rc2-380-g3d1ab66e043f +dnl # drm/edid: add drm_edid_raw() to access the raw EDID data +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_RAW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_raw(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_RAW, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1-145-g6c9b3db70aad +dnl # drm/edid: add function for checking drm_edid validity +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_VALID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_valid(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_VALID, 1, + [drm_edid_valid() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_EDID], [ + AC_AMDGPU_DRM_EDID_MALLOC + AC_AMDGPU_DRM_EDID_RAW + AC_AMDGPU_DRM_EDID_VALID +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 new file mode 100644 index 0000000000000..efad63d148bcc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_add_modes.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc2-707-gc533b5167c7e +dnl # drm/edid: add separate drm_edid_connector_add_modes() +dnl # +AC_DEFUN([AC_DRM_EDID_CONNECTOR_ADD_MODES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_connector_add_modes(NULL); + ], [drm_edid_connector_add_modes], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_CONNECTOR_ADD_MODES, 1, + [drm_edid_connector_add_modes is available]) + ]), + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 new file mode 100644 index 0000000000000..f88867def0c7e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_connector_update.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.19-rc2-378-gb71c0aaab9ef +dnl # drm/edid: add drm_edid_connector_update() +dnl # +AC_DEFUN([AC_DRM_EDID_CONNECTOR_UPDATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_connector_update(NULL, NULL); + ], [drm_edid_connector_update], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_CONNECTOR_UPDATE, 1, + [drm_edid_connector_update is available]) + ]), + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 new file mode 100644 index 0000000000000..38fb48bab685e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_is_digital.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.5-rc2-869-g7218779efc46 +dnl # drm/edid: add drm_edid_is_digital() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_IS_DIGITAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct drm_edid *drm_edid = NULL; + drm_edid_is_digital(drm_edid); + ], [ + AC_DEFINE(HAVE_DRM_EDID_IS_DIGITAL, 1, + [drm_edid_is_digital is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 new file mode 100644 index 0000000000000..25f464b720203 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_create_format_info.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit v6.16-rc2-1238-g81112eaac559 +dnl # drm: Pass the format info to .fb_create() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_framebuffer *test_fb_create_new( + struct drm_device *dev, + struct drm_file *file_priv, + const struct drm_format_info *info, + const struct drm_mode_fb_cmd2 *mode_cmd) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .fb_create = test_fb_create_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_FB_CREATE_FORMAT_INFO, 1, + [fb_create has const struct drm_format_info * parameter]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 new file mode 100644 index 0000000000000..7ce8c4a4c5c0d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_gem_is_fb.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit amd-staging-dkms-6.18.10-84-gdeca4d1c0b26 +dnl # drm/amdgpu: Move test for fbdev GEM object into generic helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_GEM_IS_FB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_fb_helper *fb_helper = NULL; + struct drm_gem_object *obj = NULL; + drm_fb_helper_gem_is_fb(fb_helper, obj); + ], [drm_fb_helper_gem_is_fb], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_GEM_IS_FB, 1, + [drm_fb_helper_gem_is_fb is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 new file mode 100644 index 0000000000000..5bbcaa354dfde --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.6-rc2-1021-g2dea2d118217 +dnl # drm: Remove unused arg from drm_fb_helper_init +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + drm_fb_helper_init(NULL, NULL); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_2ARGS, 1, + [drm_fb_helper_init() has 2 args]) + ], [ + dnl # + dnl # commit v4.10-rc5-1046-ge4563f6ba717 + dnl # drm: Rely on mode_config data for fb_helper initialization + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + drm_fb_helper_init(NULL, NULL, 0); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_3ARGS, 1, + [drm_fb_helper_init() has 3 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 new file mode 100644 index 0000000000000..c4144b607fbb7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.12-rc1-309-g56c594d8df64 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file *filp = NULL; + filp->client_name = NULL; + ], [ + AC_DEFINE(HAVE_DRM_FILE_CLIENT_NAME, 1, + [struct drm_file->client_name is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 new file mode 100644 index 0000000000000..5483d555b35eb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_file_err.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-1914-gec0a2cc40756 +dnl # dma-buf: Add drm_file_err (v1) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_ERR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_file_err(NULL, NULL); + ], [drm_file_err], [drivers/gpu/drm/drm_file.c],[ + AC_DEFINE(HAVE_DRM_FILE_ERR, 1, + [drm_file_err() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 new file mode 100644 index 0000000000000..3d95cd4406fe2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.16-rc1-268-g6a2d2ddf2c34 +dnl # drm: Move nomodeset kernel parameter to the DRM subsystem +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_firmware_drivers_only(); + ], [ + AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, + [drm_firmware_drivers_only() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 new file mode 100644 index 0000000000000..54d06ba68400f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v5.9-rc5-1367-g564b9f4c7cf9 +dnl # drm/amd/display: Add formats for DCC with 2/3 planes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_format_info format; + + format.format = DRM_FORMAT_XRGB16161616F; + format.block_w[0] = 0; + format.block_h[0] = 0; + ], [ + AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, + [drm_format_info.block_w and rm_format_info.block_h is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 new file mode 100644 index 0000000000000..a8110c2b201b0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-rc4-395-gb57aa47d39e9 +dnl # drm/gem: Test for imported GEM buffers with helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_IS_IMPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_is_imported(NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_IS_IMPORTED, 1, + [drm_gem_is_imported() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 new file mode 100644 index 0000000000000..e0311f6ebd145 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_plane_helper_prepare_fb(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB, 1, + [drm_gem_plane_helper_prepare_fb() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 new file mode 100644 index 0000000000000..cfdf6da657222 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3140-ge9b641807e5e +dnl # drm: new helper: drm_gem_prime_handle_to_dmabuf() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_dmabuf(NULL, NULL, 0, 0); + ],[drm_gem_prime_handle_to_dmabuf],[drivers/gpu/drm/drm_prime.c],[ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF, 1, + [drm_gem_prime_handle_to_dmabuf() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 new file mode 100644 index 0000000000000..71d0f4e7eb9d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_get_format_info_signature.m4 @@ -0,0 +1,24 @@ +dnl # +dnl # v6.16-rc2-1235-g0389e4256eb2 +dnl # drm: Pass pixel_format+modifier to .get_format_info() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + const struct drm_format_info *test_get_format_info_new( + u32 pixel_format, u64 modifier) { + return NULL; + } + + struct drm_mode_config_funcs funcs = { + .get_format_info = test_get_format_info_new, + }; + ], [ + AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO_TWO_ARGS, 1, + [get_format_info uses pixel_format and modifier parameters]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 new file mode 100644 index 0000000000000..69513e0cacc39 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef +dnl # DRM: add mode setting support +dnl # +dnl # commit v5.0-rc1-118-gc2d88e06bcb9 +dnl # drm: Move the legacy kms disable_all helper to crtc helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_helper_force_disable_all(NULL); + ],[drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ + AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, + [drm_helper_force_disable_all() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 new file mode 100644 index 0000000000000..e1e4dc10eb1ed --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc2-1239-ga34cc7bf1034 +dnl # drm: Allow the caller to pass in the format info to drm_helper_mode_fill_fb_struct() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + drm_helper_mode_fill_fb_struct(NULL, NULL, NULL, NULL); + ],[drm_helper_mode_fill_fb_struct], [drivers/gpu/drm/drm_modeset_helper.c],[ + AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_4_ARGS, 1, + [drm_helper_mode_fill_fb_struct() wants 4 arguments]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 new file mode 100644 index 0000000000000..4b809aec8cd50 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -0,0 +1,36 @@ +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_modifiers_not_supported = true; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED, 1, + [drm_mode_config->fb_modifiers_not_supported is available]) + ]) + ]) +]) + +dnl # +dnl # v6.1-rc1-103-g7c99616e3fe7 drm: Remove drm_mode_config::fb_base +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_base = 0; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_BASE, 1, + [drm_mode_config->fb_base is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ + AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED + AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 new file mode 100644 index 0000000000000..6d0309bc28be0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_panel_type_property.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.19-1925-g227b955a0144 +dnl # drm/connector: Add a new 'panel_type' property +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_MODE_CONFIG_HAS_PANEL_TYPE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config config; + config.panel_type_property = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_MODE_CONFIG_PANEL_TYPE_PROPERTY, 1, + [struct drm_mode_config has member panel_type_property]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 new file mode 100644 index 0000000000000..ecc33db72dcbd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -0,0 +1,53 @@ +dnl # +dnl # commit v5.3-rc1-675-g8806cd3aa025 +dnl # drm: Rename HDMI colorspace property creation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_colorspace_property(NULL); + ],[drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + [drm_connector_attach_colorspace_property() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_hdmi_colorspace_property(NULL, 0); + ], [drm_mode_create_hdmi_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_hdmi_colorspace_property() has 2 args]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_dp_colorspace_property(NULL, 0); + ], [drm_mode_create_dp_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_dp_colorspace_property() has 2 args]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS], [ + AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 new file mode 100644 index 0000000000000..4ff1d15d7f9a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_panel_backlight_quirk.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc1-123-g1234567890ab +dnl # drm/utils: add drm_get_panel_backlight_quirk +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PANEL_BACKLIGHT_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_get_panel_backlight_quirk(NULL); + ],[ + AC_DEFINE(HAVE_DRM_GET_PANEL_BACKLIGHT_QUIRK, 1, + [drm_get_panel_backlight_quirk() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 new file mode 100644 index 0000000000000..b3732d2b30714 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -0,0 +1,61 @@ +dnl # +dnl # commit v5.10-rc3-1140-gc67e62790f5c +dnl # drm/prime: split array import functions v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_prime_sg_to_dma_addr_array(NULL, NULL, 0); + ],[drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, + [drm_prime_sg_to_dma_addr_array() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v3.3-9296-g3248877ea179 +dnl # drm: base prime/dma-buf support (v5) +dnl # +dnl # commit v6.4-rc7-1904-g71a7974ac701 +dnl # drm/prime: Unexport helpers for fd/handle conversion +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_fd(NULL, NULL, 0, 0, NULL); + ],[drm_gem_prime_handle_to_fd], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_FD, 1, + [drm_gem_prime_handle_to_fd() is available]) + ]) + ]) +]) + +dnl # +dnl # commit 6619ccf1bb1d +dnl # dma-buf: Use struct dma_buf_map in dma_buf_vmap() interfaces +dnl # +dnl # commit 20e76f1a7059 +dnl # dma-buf: Use struct dma_buf_map in dma_buf_vunmap() interfaces +dnl # +dnl # commit c67e62790f5c +dnl # drm/prime: split array import functions v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + struct iosys_map map; + drm_gem_dmabuf_vmap(NULL, &map); + ],[drm_gem_dmabuf_vmap], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG, 1, + [drm_gem_dmabuf_vmap() has struct iosys_map arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 new file mode 100644 index 0000000000000..fb7266321075c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -0,0 +1,29 @@ +dnl # +dnl # v5.3-rc1-684-g141f6357f45c +dnl # drm: tweak drm_print_bits() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_print_bits(NULL, 0, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS_4ARGS, 1, + [drm_print_bits() has 4 args]) + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ], [ + dnl # v5.3-rc1-622-g2dc5d44ccc5e + dnl # drm: add drm_print_bits + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_print_bits(NULL, 0, NULL, 0, 0); + ],[drm_print_bits], [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 new file mode 100644 index 0000000000000..8636cef864a78 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_privacy_screen.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc1-293-g334f74ee85dc +dnl # drm/connector: Add a drm_connector privacy-screen helper functions (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_connector_state *drm_con_state = NULL; + drm_connector_update_privacy_screen(drm_con_state); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN, 1, + [drm_connector_update_privacy_screen() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 new file mode 100644 index 0000000000000..79e2de01aed3f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_private_obj_lock.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v4.20-rc4-945-gb962a12050a3 +dnl # drm/atomic: integrate modeset lock with private objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIVATE_OBJ_LOCK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_private_obj *obj = NULL; + struct drm_modeset_lock lock = {}; + obj->lock = lock; + ], [ + AC_DEFINE(HAVE_DRM_PRIVATE_OBJ_LOCK, 1, + [struct drm_private_obj.lock is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 new file mode 100644 index 0000000000000..12aea115000fb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_probe_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc6-1875-g216b9bbaeaea +dnl # drm/probe-helper: Add drm_crtc_helper_mode_valid_fixed() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_crtc_helper_mode_valid_fixed(NULL, NULL, NULL); + ], [drm_crtc_helper_mode_valid_fixed], [drivers/gpu/drm/drm_probe_helper.c],[ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_MODE_VALID_FIXED, 1, + [drm_crtc_helper_mode_valid_fixed() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 new file mode 100644 index 0000000000000..837e690cc9c32 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.6-rc2-359-g63170ac6f2e8 +dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 new file mode 100644 index 0000000000000..e735965113377 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.2-rc6-1265-g849ee8a2f0df +dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if IS_ENABLED(CONFIG_DRM_SUBALLOC_HELPER) + drm_suballoc_manager_init(NULL, 0, 0); + #else + #error CONFIG_DRM_SUBALLOC_HELPER is not enabled + #endif + ], [ + AC_DEFINE(HAVE_DRM_SUBALLOC_MANAGER_INIT, 1, + [Has function drm_suballoc_manager_init()]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 new file mode 100644 index 0000000000000..af363349cc643 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_syncobj_add_point.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.0-1332-g44f8a1396e83 +dnl # drm/syncobj: add new drm_syncobj_add_point interface v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_syncobj_add_point(NULL, NULL, NULL, 0); + ],[drm_syncobj_add_point], [drivers/gpu/drm/drm_syncobj.c], [ + AC_DEFINE(HAVE_DRM_SYNCOBJ_ADD_POINT, 1, + [drm_syncobj_add_point() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 new file mode 100644 index 0000000000000..78e8648f6b335 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v6.10-rc1-595-g0d5040e406d2 +dnl # drm/vblank: add dynamic per-crtc vblank configuration support +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc *vblank = NULL; + struct drm_vblank_crtc_config config = {}; + vblank->config = config; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_STRUCT_CONFIG, 1, + [struct vblank->config is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 new file mode 100644 index 0000000000000..90ef0ba2c3cc5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc_config config; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_CONFIG, 1, + [drm_vblank_crtc_config is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 new file mode 100644 index 0000000000000..7f2c208c36f96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.18-rc2-67-g57b8280a0a41 +dnl # drm: allow passing possible_crtcs to drm_writeback_connector_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_writeback_connector_init(NULL, NULL, NULL, NULL, NULL, 0, 0); + ],[drm_writeback_connector_init], [drivers/gpu/drm/drm_writeback.c],[ + AC_DEFINE(HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS, 1, + [drm_writeback_connector_init() has 7 args]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 b/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 new file mode 100644 index 0000000000000..37cc1db772586 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drmm_cgroup_register_region.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.13-rc6-2-g7b0af165e2d4 +dnl # drm/drv: Add drmm managed registration helper for dmem cgroups. +dnl # +AC_DEFUN([AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drmm_cgroup_register_region(NULL,NULL,0); + ],[drmm_cgroup_register_region], [drivers/gpu/drm/drm_drv.c],[ + AC_DEFINE(HAVE_DRMM_CGROUP_REGISTER_REGION, 1, + [drmm_cgroup_register_region() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 new file mode 100644 index 0000000000000..ce4b655254f91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.6-5709-g4064b9827063 +dnl # mm: allow VM_FAULT_RETRY for multiple times +dnl # +AC_DEFUN([AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + fault_flag_allow_retry_first(0); + ], [ + AC_DEFINE(HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST, 1, + [fault_flag_allow_retry_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 new file mode 100644 index 0000000000000..e702269ad9e9e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v6.9-rc4-152-gcb10c28ac82c +dnl # mm: remove follow_pfn +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfn(NULL, 0, NULL); + ],[follow_pfn], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFN, 1, + [follow_pfn() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.11-rc6-389-g6da8e9634bb7 +dnl # mm: new follow_pfnmap API +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFNMAP_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfnmap_start(NULL); + ],[follow_pfnmap_start], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFNMAP_START, 1, + [follow_pfnmap_start() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 new file mode 100644 index 0000000000000..be2f5c9928ae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v4.13-rc4-164-gd92a8cfcb37e +dnl # locking/lockdep: Rework FS_RECLAIM annotation +dnl # +AC_DEFUN([AC_AMDGPU_FS_RECLAIM_ACQUIRE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + fs_reclaim_acquire(0); + ],[ + AC_DEFINE(HAVE_FS_RECLAIM_ACQUIRE, 1, [fs_reclaim_acquire() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 new file mode 100644 index 0000000000000..782402a16e6a4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.7-rc2-1263-gc6af13d33475 +dnl # timer: add fsleep for flexible sleeping +dnl # +AC_DEFUN([AC_AMDGPU_FSLEEP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long usecs = 0; + fsleep(usecs); + ], [ + AC_DEFINE(HAVE_FSLEEP, 1, + [fsleep() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 new file mode 100644 index 0000000000000..01d095dd14cb8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-rc4-24-g8240ef50d486 +dnl # genirq: Add generic_handle_domain_irq() helper +dnl # +AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + generic_handle_domain_irq(NULL, 0); + ], [ + AC_DEFINE(HAVE_GENERIC_HANDLE_DOMAIN_IRQ, 1, + [generic_handle_domain_irq() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 new file mode 100644 index 0000000000000..d538ceb02d6b2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -0,0 +1,60 @@ +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ + dnl # + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ],[ + dnl # + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + dnl # + dnl # commit v6.4-rc4-55-gca5e863233e8 + dnl # mm/gup: remove vmas parameter from get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS, 1, + [get_user_pages_remote() remove argument vmas]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) + ]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 new file mode 100644 index 0000000000000..4350eefb61a2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.4-rc4-53-g54d020692b34 +dnl # mm/gup: remove unused vmas parameter from get_user_pages() +dnl # +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOVE_VMAS, 1, + [get_user_pages() remove vmas argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 new file mode 100644 index 0000000000000..4527ccd0a9659 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit f3ba3c710ac5a30cd058615a9eb62d2ad95bb782 +dnl # mm/highmem: Provide kmap_local* +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pgprot_t prot = {0}; + kmap_local_page_prot(NULL, prot); + ], [ + AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 new file mode 100644 index 0000000000000..72a1a8260873a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -0,0 +1,76 @@ +dnl # +dnl # v5.7-rc4-4-g2733ea144dcc mm/hmm: remove the customizable pfn format from hmm_range_fault +dnl # v5.7-rc4-3-g5c8f3c4cf18a mm/hmm: remove HMM_PFN_SPECIAL +dnl # v5.7-rc4-2-g4e2490843d55 drm/amdgpu: remove dead code after hmm_range_fault() +dnl # v5.7-rc4-1-gbe957c886d92 mm/hmm: make hmm_range_fault return 0 or -1 +dnl # +AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum hmm_pfn_flags flag; + flag = HMM_PFN_REQ_FAULT; + ], [ + AC_DEFINE(HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT, 1, + [hmm remove the customizable pfn format]) + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ], [ + dnl # + dnl # v5.6-rc3-21-g6bfef2f91945 + dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL);; + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) + ]) +]) + +dnl # +dnl # v5.1-10231-gbf198b2b34bf: mm/mmu_notifier: pass down vma and reasons why mmu notifier is happening +dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 +dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 +dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 +dnl # a22dd506400d - mm/hmm: remove hmm_mirror and related 2019-11-23 19:56:45 -0400 +dnl # 81fa1af31b5d - drm/amdgpu: Use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # 62914a99dee5 - drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # a9ae8731e6e5 - drm/amdgpu: Call find_vma under mmap_sem 2019-11-23 19:56:44 -0400 +dnl # 20fef4ef84bf - nouveau: use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # c625c274ee00 - nouveau: use mmu_notifier directly for invalidate_range_start 2019-11-23 19:56:44 -0400 +dnl # 3506ff69c3ec - drm/radeon: use mmu_interval_notifier_insert 2019-11-23 19:56:44 -0400 +dnl # 3889551db212 - RDMA/hfi1: Use mmu_interval_notifier_insert for user_exp_rcv 2019-11-23 19:56:44 -0400 +dnl # f25a546e6529 - RDMA/odp: Use mmu_interval_notifier_insert() 2019-11-23 19:56:44 -0400 +dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h even if disabled 2019-11-23 19:56:44 -0400 +dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 +dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # 7d4a8be0c4b2 - mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export +dnl # +AC_DEFUN([AC_AMDGPU_HMM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + #ifdef CONFIG_HMM_MIRROR + struct hmm_range *range = NULL; + struct mmu_notifier_range *mmu_range = NULL; + + range->notifier = NULL; + mmu_range->event = 0; + #else + #error CONFIG_HMM_MIRROR not enabled + #endif + ], [ + AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, + [hmm support is enabled]) + AC_AMDGPU_HMM_RANGE_FAULT + AC_AMDGPU_HSA_AMD_SVM + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 b/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 new file mode 100644 index 0000000000000..456d238010a25 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hrtimer_setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.12-rc1-119-g908a1d775422 +dnl # hrtimers: Introduce hrtimer_setup() to replace hrtimer_init() +dnl # +AC_DEFUN([AC_AMDGPU_HRTIMER_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + hrtimer_setup(NULL,NULL,0,0); + ],[hrtimer_setup], [kernel/time/hrtimer.c],[ + AC_DEFINE(HAVE_HRTIMER_SETUP, 1, + [hrtimer_setup() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 new file mode 100644 index 0000000000000..a4d3e37bfa38c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.1-12318-g7159dbdae3c5 +dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dummy +dnl # +AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + i2c_new_client_device(NULL, NULL); + ],[i2c_new_client_device], [drivers/i2c/i2c-core-base.c],[ + AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, + [i2c_new_client_device() is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 new file mode 100644 index 0000000000000..3f579b7ee7620 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -0,0 +1,41 @@ + +dnl # +dnl # commit v6.1-rc1~27-c4f306e31632 +dnl # drm/amdgpu: use idr_init_base() to initialize fpriv->bo_list_handles +dnl # +AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + idr_init_base(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_INIT_BASE, 1, + [idr_init_base() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v4.16-rc1~25-6ce711f27500 +dnl # idr: Make 1-based IDRs more efficient +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_IDE_IDR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct idr *idr = NULL; + idr->idr_base = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_IDE_IDR_BASE, 1, + [ide->idr_base is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_IDR], [ + AC_AMDGPU_IDR_INIT_BASE + AC_AMDGPU_STRUCT_IDE_IDR_BASE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 new file mode 100644 index 0000000000000..c96b4703e6cf9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_IMPORT_GUID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + import_guid(NULL, NULL); + ],[ + AC_DEFINE(HAVE_IMPORT_GUID, 1, + [import_guid() is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 new file mode 100644 index 0000000000000..d9edaefbebdcf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 @@ -0,0 +1,36 @@ +dnl # +dnl # commit 5d6527a784f7a6d247961e046e830de8d71b47d1 +dnl # Author: Jérôme Glisse +dnl # Date: Fri Dec 28 00:38:05 2018 -0800 +dnl # mm/mmu_notifier: use structure for invalidate_range_start/end callback +dnl # Patch series "mmu notifier contextual informations", v2. +dnl # +AC_DEFUN([AC_AMDGPU_INVALIDATE_RANGE_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL); + ], [ + AC_DEFINE(HAVE_2ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 2 args) + ], [ + dnl # + dnl # commit 93065ac753e4443840a057bfef4be71ec766fde9 + dnl # Author: Michal Hocko + dnl # Date: Tue Aug 21 21:52:33 2018 -0700 + dnl # mm, oom: distinguish blockable mode for mmu notifiers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL, 1, 1, 1); + ], [ + AC_DEFINE(HAVE_5ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 5 args) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 new file mode 100644 index 0000000000000..72ba661169b58 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_map_local_wc(NULL, 0); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_MAP_LOCAL_WC, 1, [io_mapping_map_local_wc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 new file mode 100644 index 0000000000000..282b77e11e1c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_unmap_local(NULL); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_UNMAP_LOCAL, 1, [io_mapping_unmap_local() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 new file mode 100644 index 0000000000000..116779b2674f0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.12-rc2-346-g97a7e4733b9b +dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow +dnl # +AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + is_cow_mapping(VM_SHARED); + ], [ + AC_DEFINE(HAVE_IS_COW_MAPPING, 1, [is_cow_mapping() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 new file mode 100644 index 0000000000000..29cc9b9271330 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v5.1-rc3-699-g3b15d09f7e6d +dnl # time: Introduce jiffies64_to_msecs() +dnl # +AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + jiffies64_to_msecs(0); + ],[jiffies64_to_msecs], [kernel/time/time.c], [ + AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 new file mode 100644 index 0000000000000..4e123cddf2838 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.6-11591-g0bd476e6c671 kallsyms: unexport kallsyms_lookup_name() and kallsyms_on_each_symbol() +dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sample module +dnl # +AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + kallsyms_lookup_name(NULL); + ],[kallsyms_lookup_name],[kernel/kallsyms.c],[ + AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, + [kallsyms_lookup_name is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 new file mode 100644 index 0000000000000..db9534eab47cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -0,0 +1,755 @@ +dnl # +dnl # Default kernel configuration +dnl # +AC_DEFUN([AC_CONFIG_KERNEL], [ + AC_KERNEL + AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_LINUX_HEADERS + AC_AMDGPU_STRUCT_DRM_MODE_CONFIG_HAS_PANEL_TYPE_PROPERTY + AC_AMDGPU_DRM_HEADERS + AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_KERNEL_SUPPORTED_AMD_CHIPS + AC_AMDGPU_IDR + AC_AMDGPU_DMA_MAP_SGTABLE + AC_AMDGPU_I2C_NEW_CLIENT_DEVICE + AC_AMDGPU_COMPAT_PTR_IOCTL + AC_AMDGPU_LIST_ROTATE_TO_FRONT + AC_AMDGPU_LIST_IS_FIRST + AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC + AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_KSYS_SYNC_HELPER + AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS + AC_AMDGPU_PCI + AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE + AC_AMDGPU_PCI_REBAR_GET_MAX_SIZE + AC_AMDGPU_PCI_RESIZE_RESOURCE + AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_ZONE_MANAGED_PAGES + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_FSLEEP + AC_AMDGPU_USLEEP_RANGE_STATE + AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT + AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE + AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU + AC_AMDGPU_DMA_RESV + AC_AMDGPU_TTM_BUFFER_OBJECT + AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_HMM + AC_AMDGPU_INVALIDATE_RANGE_START + AC_AMDGPU_GET_USER_PAGES_REMOTE + AC_AMDGPU_GET_USER_PAGES + AC_AMDGPU_DMA_BUF + AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX + AC_AMDGPU_DEV_PAGEMAP + AC_AMDGPU_DOWN_READ_KILLABLE + AC_AMDGPU_DRM_CACHE + AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_GEM_OBJECT_PUT + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_CALC_PBN_MODE + AC_AMDGPU_DRM_DP_ATOMIC_FUNCS + AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM + AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ + AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT + AC_AMDGPU_DRM_PRINT_BITS + AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL + AC_AMDGPU_STRUCT_DRM_DEVICE + AC_AMDGPU_DRM_DRIVER_FEATURE + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET + AC_AMDGPU_PCI_PR3_PRESENT + AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB + AC_AMDGPU_DRM_FB_HELPER_FILL_INFO + AC_AMDGPU_DRM_FB_HELPER_INIT + AC_AMDGPU_DRM_FB_HELPER_GEM_IS_FB + AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_EDID + AC_AMDGPU_DRM_EDID_IS_DIGITAL + AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE + AC_AMDGPU_DRM_PANEL_BACKLIGHT_QUIRK + AC_AMDGPU_DRM_MODE_INIT + AC_AMDGPU_DRM_DP_MST_TOPOLOGY + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_STRUCT_DRM_PLANE + AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS + AC_AMDGPU_DRM_CONNECTOR_STRUCT_MEMBER + AC_AMDGPU_DRM_DP_MST_DETECT_PORT + AC_AMDGPU_STRUCT_DRM_CRTC_STATE + AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT + AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_MODE_CONFIG + AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG + AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE + AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE + AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS + AC_AMDGPU_DRM_FORMAT_INFO + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + AC_AMDGPU_DRM_COLOR_LUT32 + AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_PLANE_COLOR_PIPELINE + AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY + AC_AMDGPU_DRM_PRIME_PAGES_TO_SG + AC_AMDGPU_DRM_GEM_DMABUF_VMAP_HAS_IOSYS_MAP_ARG + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS + AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT + AC_AMDGPU_FS_RECLAIM_ACQUIRE + AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE + AC_AMDGPU_SYSFS_EMIT + AC_AMDGPU_KTIME_IS_UNION + AC_AMDGPU_PXM_TO_NODE + AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY + AC_AMDGPU_STRUCT_XARRAY + AC_AMDGPU_MMPUT_ASYNC + AC_AMDGPU_DRM_MEMCPY_FROM_WC + AC_AMDGPU_IS_COW_MAPPING + AC_AMDGPU_VGA_REMOVE_VGACON + AC_AMDGPU_PCI_DRIVER_DEV_GROUPS + AC_AMDGPU_DRM_DISPLAY_INFO + AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL + AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC + AC_AMDGPU_KMAP_LOCAL + AC_AMDGPU_DRM_DP_AUX_DRM_DEV + AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY + AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY + AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + AC_AMDGPU_DRM_DEVICE_PDEV + AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK + AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DEV_IS_REMOVABLE + AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS + AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI + AC_AMDGPU_DRM_BITMAP_FUNCS + AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE + AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW + AC_AMDGPU_MIGRATE_DISABLE + AC_AMDGPU_CLOSE_FD + AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT + AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD + AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG + AC_AMDGPU_DRM_APERTURE + AC_AMDGPU_SYNCHRONIZE_SHRINKERS + AC_AMDGPU_KREALLOC_ARRAY + AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE + AC_AMDGPU_VMA_LOOKUP + AC_AMDGPU_DMA_FENCE_CHECK_AND_SIGNAL + AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC + AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO + AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ + AC_AMDGPU__DMA_FENCE_IS_LATER + AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY + AC_AMDGPU_DMA_FENCE_DESCRIBE + AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT + AC_AMDGPU_PCIE_ASPM_ENABLED + AC_AMDGPU_PM_SUSPEND_TARGET_STATE + AC_AMDGPU_SMCA_GET_BANK_TYPE + AC_AMDGPU_MCE_PRIO_UC + AC_AMDGPU_DMA_FENCE_IS_CONTAINER + AC_AMDGPU_STR_YES_NO + AC_AMDGPU_STR_READ_WRITE + AC_AMDGPU_TOTALRAM_PAGES + AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED + AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG + AC_AMDGPU_DRM_PRIVATE_OBJ_LOCK + AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DP_READ_DPCD_CAPS + AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART + AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK + AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS + AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB + AC_AMDGPU_BITMAP_TO_ARR32 + AC_AMDGPU_SHRINKER + AC_AMDGPU_STRUCT_DRM_EDID + AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX + AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN + AC_AMDGPU_ACPI_VIDEO_FUNCS + AC_AMDGPU_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_MEMORY_DEVICE_COHERENT + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE + AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_WANT_INIT_ON_FREE + AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP + AC_AMDGPU_ZONE_DEVICE_PAGE_INIT + AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT + AC_AMDGPU_VM_FLAGS_SET + AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF + AC_AMDGPU_PID_TYPE + AC_AMDGPU_FOLLOW_PFN + AC_AMDGPU_IMPORT_GUID + AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T + AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM + AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE + AC_AMDGPU_DRM_SHOW_FDINFO + AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG + AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG + AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_KVREALLOC + AC_AMDGPU_DMA_BUF_IS_DYNAMIC + AC_AMDGPU_KFIFO_OUT_LINEAR + AC_AMDGPU_DRM_CLIENT_REGISTER + AC_AMDGPU_DRM_COLOR_CTM_3X4 + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD + AC_AMDGPU_DMA_FENCE_TIMESTAMP + AC_AMDGPU_VMA_IS_INITIAL + AC_AMDGPU_CPUINFO_X86 + AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME + AC_AMDGPU_WORKQUEUE + AC_AMDGPU_DRM_DBG_PRINTER + AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS + AC_AMDGPU_DRM_DEBUG_CATEGORY + AC_AMDGPU_SMCA_UMC_V2 + AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE + AC_AMDGPU_DRM_CRTC_VBLANK_CRTC + AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET + AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE + AC_AMDGPU_PM_RUNTIME_PUT_AUTOSUSPEND + AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS + AC_AMDGPU_ASSIGN_STR + AC_AMDGPU_DRM_DP_MST_EDID_READ + AC_AMDGPU_DRM_DP_CEC_ATTACH + AC_AMDGPU_STRUCT_FILE_OPERATION + AC_AMDGPU_FOLLOW_PFNMAP_START + AC_AMDGPU_DRM_FILE + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_QUEUE_PROBE + AC_AMDGPU_DRM_CLIENT + AC_AMDGPU_DRM_SYNCOBJ_ADD_POINT + AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT + AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS + AC_AMDGPU_CEC_NOTIFIER_CONN_REGISTER + AC_AMDGPU_STRUCT_CEC_CONNECTOR_INFO + AC_AMDGPU_DRM_MEMORY_STATS + AC_AMDGPU_DRM_CONNECTOR_DYNAMIC_INIT + AC_AMDGPU_MODULE_IMPORT_NS + AC_AMDGPU_DRM_DEV_WEDGED_EVENT + AC_AMDGPU_SHMEM_READ_FOLIO + AC_AMDGPU_DRM_DRIVER_DATE + AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS + AC_AMDGPU_DMA_FENCE_ARRAY_FIRST + AC_AMDGPU_DMA_FENCE_DEDUP_ARRAY + AC_AMDGPU_DMA_FENCE_UNWRAP_MERGE + AC_AMDGPU_DRM_FILE_ERR + AC_AMDGPU_DRM_FILE_CLIENT_NAME + AC_AMDGPU_SIZE_MUL + AC_AMDGPU_RANGE_OVERFLOWS + AC_AMDGPU_DRM_CRTC_HELPER_MODE_VALID_FIXED + AC_AMDGPU_BIN_ATTR_CONST_ARGS + AC_AMDGPU_DRMM_CGROUP_REGISTER_REGION + AC_AMDGPU_HRTIMER_SETUP + AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL + AC_AMDGPU_TIMER_DELETE + AC_AMDGPU_SHMEM_WRITEOUT + AC_AMDGPU_SHMEM_FILE_SETUP_VMA_FLAGS + AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC + AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING + AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND + AC_AMDGPU_DRM_GEM_IS_IMPORTED + AC_AMDGPU_DMA_FENCE_INIT64 + AC_AMDGPU_DMA_FENCE_SIGNALLING + AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT + AC_AMDGPU_DRM_VBLANK_CRTC_STRUCT_CONFIG + AC_AMDGPU_DRM_CONNECTOR_UPDATE_PRIVACY_SCREEN + AC_AMDGPU_DRM_DP_AUX_DPCD_PROBE_DISABLED + AC_AMDGPU_BLOCK_DEVICE_BD_DEVICE + AC_AMDGPU_PAGE_PGMAP + AC_AMDGPU_VMEMDUP_ARRAY_USER + AC_AMDGPU_BITMAP_READ + AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_FB_CREATE_FORMAT_INFO + AC_AMDGPU_DRM_GET_FORMAT_INFO_2_ARGS + AC_AMDGPU_VFS_IOCB_ITER_READ + AC_AMDGPU_LIST_IS_HEAD + AC_AMDGPU_DEVM_I2C_ADD_ADAPTER + AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED + AC_AMDGPU_KFD_PEERDIRECT_SUPPORT + AC_AMDGPU_SYSTEM_PERCPU_WQ + AC_AMDGPU_PCI_DEV_IS_DISCONNECTED + AC_DRM_EDID_CONNECTOR_ADD_MODES + AC_DRM_EDID_CONNECTOR_UPDATE + + AC_KERNEL_WAIT + AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ + KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" + ]) + + AC_SUBST(KERNEL_MAKE) + AH_BOTTOM([#include "config-amd-chips.h"]) + AH_BOTTOM([#define AMDGPU_VERSION PACKAGE_VERSION]) +]) + +dnl # +dnl # Detect name used for Module.symvers file in kernel +dnl # +AC_DEFUN([AC_MODULE_SYMVERS], [ + modpost=$LINUX/scripts/Makefile.modpost + AC_MSG_CHECKING([kernel file name for module symbols]) + AS_IF([test -f "$modpost"], [ + AS_IF([grep -q Modules.symvers $modpost], [ + LINUX_SYMBOLS=Modules.symvers + ], [ + LINUX_SYMBOLS=Module.symvers + ]) + + AS_IF([test "x$enable_linux_builtin" != xyes -a ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed. If you are building with a custom kernel, make sure the + *** kernel is configured, built, and the '--with-linux=PATH' configure + *** option refers to the location of the kernel source.]) + ]) + ], [ + LINUX_SYMBOLS=NONE + ]) + AC_MSG_RESULT($LINUX_SYMBOLS) + AC_SUBST(LINUX_SYMBOLS) +]) + +dnl # +dnl # Detect the kernel to be built against +dnl # +AC_DEFUN([AC_KERNEL], [ + AC_ARG_WITH([linux], + AS_HELP_STRING([--with-linux=PATH], + [Path to kernel source]), + [kernelsrc="$withval"]) + + AC_ARG_WITH(linux-obj, + AS_HELP_STRING([--with-linux-obj=PATH], + [Path to kernel build objects]), + [kernelbuild="$withval"]) + + AC_MSG_CHECKING([kernel source directory]) + AS_IF([test -z "$kernelsrc"], [ + AS_IF([test -e "/lib/modules/$KERNELVER/source"], [ + headersdir="/lib/modules/$KERNELVER/source" + sourcelink=$(readlink -f "$headersdir") + ], [test -e "/lib/modules/$KERNELVER/build"], [ + headersdir="/lib/modules/$KERNELVER/build" + sourcelink=$(readlink -f "$headersdir") + ], [ + sourcelink=$(ls -1d /usr/src/kernels/* \ + /usr/src/linux-* \ + 2>/dev/null | grep -v obj | tail -1) + ]) + + AS_IF([test -n "$sourcelink" && test -e ${sourcelink}], [ + kernelsrc=`readlink -f ${sourcelink}` + ], [ + kernelsrc="[Not found]" + ]) + ], [ + AS_IF([test "$kernelsrc" = "NONE"], [ + kernsrcver=NONE + ]) + withlinux=yes + ]) + + AC_MSG_RESULT([$kernelsrc]) + AS_IF([test ! -d "$kernelsrc"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed and then try again. If that fails, you can specify the + *** location of the kernel source with the '--with-linux=PATH' option.]) + ]) + + AC_MSG_CHECKING([kernel build directory]) + AS_IF([test -z "$kernelbuild"], [ + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$KERNELVER/build"], [ + kernelbuild=`readlink -f /lib/modules/$KERNELVER/build` + ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} + ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/default + ], [test -d `dirname ${kernelsrc}`/build-${target_cpu}], [ + kernelbuild=`dirname ${kernelsrc}`/build-${target_cpu} + ], [ + kernelbuild=${kernelsrc} + ]) + ]) + AC_MSG_RESULT([$kernelbuild]) + + AC_MSG_CHECKING([kernel source version]) + utsrelease1=$kernelbuild/include/linux/version.h + utsrelease2=$kernelbuild/include/linux/utsrelease.h + utsrelease3=$kernelbuild/include/generated/utsrelease.h + AS_IF([test -r $utsrelease1 && fgrep -q UTS_RELEASE $utsrelease1], [ + utsrelease=linux/version.h + ], [test -r $utsrelease2 && fgrep -q UTS_RELEASE $utsrelease2], [ + utsrelease=linux/utsrelease.h + ], [test -r $utsrelease3 && fgrep -q UTS_RELEASE $utsrelease3], [ + utsrelease=generated/utsrelease.h + ]) + + AS_IF([test "$utsrelease"], [ + kernsrcver=`(echo "#include <$utsrelease>"; + echo "kernsrcver=UTS_RELEASE") | + cpp -I $kernelbuild/include | + grep "^kernsrcver=" | cut -d \" -f 2` + + AS_IF([test -z "$kernsrcver"], [ + AC_MSG_RESULT([Not found]) + AC_MSG_ERROR([*** Cannot determine kernel version.]) + ]) + ], [ + AC_MSG_RESULT([Not found]) + if test "x$enable_linux_builtin" != xyes; then + AC_MSG_ERROR([*** Cannot find UTS_RELEASE definition.]) + else + AC_MSG_ERROR([ + *** Cannot find UTS_RELEASE definition. + *** Please run 'make prepare' inside the kernel source tree.]) + fi + ]) + + AC_MSG_RESULT([$kernsrcver]) + + LINUX=${kernelsrc} + LINUX_OBJ=${kernelbuild} + LINUX_VERSION=${kernsrcver} + build_dir_root=$(cd "${0%/*}" && pwd) + + AC_SUBST(LINUX) + AC_SUBST(LINUX_OBJ) + AC_SUBST(LINUX_VERSION) + + AC_MODULE_SYMVERS +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_H +dnl # $1: contents to be filled in conftest.h +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_H], [ +cat - <<_ACEOF >conftest.h +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_C +dnl # fill in contents of conftest.h and $1 to conftest.c +dnl # $1: contents to be filled in conftest.c +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_C], [ +cat $build_dir_root/confdefs.h - <<_ACEOF >conftest.c +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_LANG_PROGRAM([PROLOGUE], [BODY]) +dnl # +AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ +$1 +int +main (void) +{ +dnl Do *not* indent the following line: there may be CPP directives. +dnl Don't move the `;' right after for the same reason. +$2 + ; + return 0; +} +]) + +dnl # +dnl # AC_KERNEL_COMPILE_MODULE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: make target. +dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $4: run it if make & $3 pass. +dnl # $5: run it if make & $3 fail. +dnl # $6: contents to be filled in conftest.h. Could be null. +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) + touch conftest.mod.c + if test "x$SINGLE_TARGET_BUILD_NO_TMP_VERSIONS" = x1; then + test -d $SINGLE_TARGET_BUILD_MODVERDIR || mkdir $SINGLE_TARGET_BUILD_MODVERDIR + rm -f $SINGLE_TARGET_BUILD_MODVERDIR/* + fi + echo "obj-m := conftest.o" >Makefile + kbuild_src_flag='' + kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' + kbuild_workaround_flag='' + kbuild_cc='' + if test -s ${LINUX_OBJ}/.config; then + if grep -q 'CONFIG_CC_IS_CLANG=y' "${LINUX_OBJ}/.config"; then + kbuild_cc='CC=clang LD=ld.lld LLVM=1' + fi + fi + test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC + test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done + AS_IF( + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], + [$4], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] + ) +]) + +dnl # +dnl # AC_KERNEL_TMP_BUILD_DIR +dnl # $1: contents to be executed in a temporary directory +dnl # +AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ + build_dir=$(mktemp -d -t build_XXXXXXXX -p $build_dir_root) + cd $build_dir + $1 + AS_IF([test -s confdefs.h], [ + cat confdefs.h >>$build_dir_root/confdefs.h + ]) + cd $build_dir_root + rm -rf $build_dir +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE_MODULE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_MODULE], + target='conftest.o' + [AC_KERNEL_COMPILE_MODULE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [$target], + [test -s conftest.o], + [$3], [$4]) +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $3: run it if make & $3 pass. +dnl # $4: run it if make & $3 fail. +dnl # $5: contents to be filled in conftest.h. Could be null. +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) + AS_IF( + [AC_TRY_COMMAND(eval $CC $CFLAGS) > /dev/null && AC_TRY_COMMAND([$2])], + [$3], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] + ) +]) +dnl # +dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE], + [AC_KERNEL_COMPILE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [test -s conftest.o || test -s .tmp_conftest.o], + [$3], [$4]) +]) + +dnl # +dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # check symbol exported or not +dnl # $1: symbol list to look for +dnl # $2: file list to look for $1 +dnl # $3: run it if pass. +dnl # $4: run it if fail. +dnl # +AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ + awk -v s="$1" ' + BEGIN { + n = 0; + num = split(s, symbols, " ") + } { + for (i in symbols) + if (symbols[[i]] == $[2]) + n++ + } END { + if (num == n) + exit 0; + else + exit 1 + }' $LINUX_OBJ/$LINUX_SYMBOLS 2>/dev/null + rc=$? + if test $rc -ne 0; then + n=0 + export=0 + for file in $2; do + n=$(awk -v s="$1" ' + BEGIN { + n = 0; + split(s, symbols, " ") + } { + for (i in symbols) { + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\)" + if ($[0] ~ s) + n++ + } + } END { + print n + }' $LINUX/$file 2>/dev/null) + rc=$? + if test $rc -eq 0; then + export=$(( $export+$n )) + fi + done + if test $(echo "$1" | wc -w) -eq $export; then : + $3 + else : + $4 + fi + else : + $3 + fi +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE_SYMBOL +dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # is called if not compiling for builtin +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: AC_KERNEL_CHECK_SYMBOL_EXPORT $1 +dnl # $4: AC_KERNEL_CHECK_SYMBOL_EXPORT $2 +dnl # $5: run it if checking pass +dnl # $6: run it if checking fail +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ + AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) + if test $rc -ne 0; then : + $6 + else + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) + if test $rc -ne 0; then : + $6 + else : + $5 + fi + fi +]) + +dnl # +dnl # AC_KERNEL_TEST_HEADER_FILE_EXIST +dnl # check header file exist +dnl # $1: header file to check +dnl # $2: run it if header file exist +dnl # $3: run it if header file nonexistent +dnl # +AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ + header_file=m4_normalize([$1]) + header_file_obj=$LINUX_OBJ/include/$header_file + header_file_src=$LINUX/include/$header_file + AS_IF([test -e $header_file_obj -o -e $header_file_src], [ + $2 + ], [ + $3 + ]) +]) + +dnl # +dnl # AC_KERNEL_CHECK_HEADERS +dnl # check whether header file(s) is(are) present +dnl # $1: header filei(s) to check +dnl # +AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ + AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) +]) + +dnl # +dnl # AC_KERNEL_DO_BACKGROUND +dnl # $1: contents to be executed +dnl # +AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ + do_background() { + AC_KERNEL_TMP_BUILD_DIR([$1]) + } + + AC_CHECK_PROG(NPROC, nproc, yes) + AS_IF([test x"$NPROC" != x"yes"], [ + ncpu=1 + ], [ + ncpu=$(nproc) + ]) + + while [[ $(jobs | wc -l) -gt $ncpu ]] + do + sleep 0.1 + done + + do_background & + procs="$! $procs" +]) + +dnl # +dnl # AC_KERNEL_WAIT +dnl # wait for all tests to be finished +dnl # +AC_DEFUN([AC_KERNEL_WAIT], [ + AC_MSG_CHECKING([for module configuration]) + wait $procs + AS_IF([[[ $? -eq 0 ]]], [ + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) + +dnl # +dnl # AC_KERNEL_SUPPORTED_AMD_CHIPS +dnl # get list of graphics chips supported by the amdgpu kernel driver +dnl # +AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ + AC_MSG_CHECKING([for supported chips]) + AS_IF([test $HAVE_DRM_AMD_ASIC_TYPE_H], [ + chips=$(awk 'BEGIN {enum = 0} { + if ($[0] ~ "^enum amd_asic_type") + enum = 1; + if (enum && $[1] ~ "CHIP_") { + gsub(",", ""); + if ($[1] == "CHIP_LAST") + exit; + print $[1]; + } + }' ../../include/drm/amd_asic_type.h) + + for i in $chips; do + $as_echo "#define HAVE_$i" >>config/config-amd-chips.h + done + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 new file mode 100644 index 0000000000000..97a050953c6d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -0,0 +1,68 @@ +dnl # +dnl # extract cc, cflags, cppflags +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ + AS_IF([test -s .conftest.o.cmd], [ + _conftest_cmd=$(head -1 .conftest.o.cmd | sed 's/.*:= //;s/;.*//;s/^[[[:space:]]]*//') + + CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[1]}') + CPP="$CC -E" + + CFLAGS=$(echo $_conftest_cmd | \ + cut -d ' ' -f 2- | \ + sed -e "s|\./\([[^/ ]]*\.o\.d\)|_OD_\1|g" \ + -e "s|\./|${LINUX_OBJ}/|g" \ + -e "s|_OD_|./|g" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ + -e "s|$PWD|\${PWD}|g") + CFLAGS=$(echo $CFLAGS | sed -E 's/-W(array-bounds|error=array-bounds|unused-variable|error=unused-variable|unused-[^ ]*-variable|error=unused-[^ ]*-variable)( |$)//g') + CFLAGS=$(echo $CFLAGS | sed -E "s/-Wunused/-Wno-unused/g") + CPPFLAGS=$(echo $CFLAGS | \ + sed 's| -|\n&|g' | \ + sed -n -e '/conftest/d' \ + -e '/KBUILD/d' \ + -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + xargs) + + CFLAGS=$(echo $CFLAGS | \ + sed -e "s|nostdinc|nostdinc -I../tiny_wrapper/include|") + + AC_SUBST(CC) + AC_SUBST(CPP) + AC_SUBST(CFLAGS) + AC_SUBST(CPPFLAGS) + ], [ + AC_MSG_ERROR([cannot detect CFLAGS...]) + ]) +]) + +dnl # +dnl # v5.3-rc4-54-g54b8ae66ae1a +dnl # kbuild: change *FLAGS_.o to take the path relative to $(obj) +dnl # +AC_DEFUN([AC_KERNEL_FLAGS_TAKE_PATH], [ + AS_IF([grep -qsm 1 "target-stem" ${LINUX}/scripts/Makefile.lib], [ + AC_DEFINE(HAVE_AMDKCL_FLAGS_TAKE_PATH, 1, + [*FLAGS_.o support to take the path relative to $(obj)]) + ]) +]) + +dnl # +dnl # v4.20-rc2-10-ge07db28eea38 +dnl # kbuild: fix single target build for external module +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ + AC_KERNEL_TMP_BUILD_DIR([ + AC_KERNEL_TRY_COMPILE_MODULE([], [], [], [ + SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions + AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ + SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 + ], [ + AC_MSG_WARN([compile single target fail expectedly]) + ]) + ]) + AC_KERNEL_SINGLE_TARGET_CFLAGS + AC_KERNEL_FLAGS_TAKE_PATH + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 new file mode 100644 index 0000000000000..82b1e366bd09a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # commit 8760c909f54a82aaa6e76da19afe798a0c77c3c3 +dnl # file: Rename __close_fd to close_fd and remove the files parameter +dnl # +AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + close_fd(0); + ], [ + AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ], [ + dnl # + dnl # commit 16a78543a1d3537645de737934b9387c42bfb53b + dnl # drm/amdkcl: fix for close_fd not defined + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_close(0); + ], [ + AC_DEFINE(HAVE_KSYS_CLOSE_FD, 1, [ksys_fd() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 b/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 new file mode 100644 index 0000000000000..ad65e8605f268 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfifo_out_linear.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v6.9-rc3-3-g4edd7e96a1f1 +dnl # kfifo: add kfifo_out_linear{,_ptr}() +dnl # +AC_DEFUN([AC_AMDGPU_KFIFO_OUT_LINEAR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + static DEFINE_KFIFO(fifo, int, 2); + unsigned int ret = kfifo_out_linear(&fifo, 0, 0); + ],[ + AC_DEFINE(HAVE_KFIFO_OUT_LINEAR, 1, + [kfifo_out_linear() available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 b/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 new file mode 100644 index 0000000000000..d5e1f0fe49cab --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kmap_local_page_try_from_panic.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.15-rc1-272-g8702048bb831 +dnl # mm/kmap: Add kmap_local_page_try_from_panic() +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL_PAGE_TRY_FROM_PANIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kmap_local_page_try_from_panic(NULL); + ], [ + AC_DEFINE(HAVE_KMAP_LOCAL_PAGE_TRY_FROM_PANIC, 1, + [kmap_local_page_try_from_panic() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 new file mode 100644 index 0000000000000..98fd7ba684a15 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -0,0 +1,53 @@ +dnl # +dnl # v5.10-13-gf0dbd2bd1c22 +dnl # mm: slab: provide krealloc_array() +dnl # +AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + void *p = krealloc_array(NULL, 0, 0, GFP_KERNEL); + (void)p; + ], [ + AC_DEFINE(HAVE_KREALLOC_ARRAY, 1, + [krealloc_array() is available]) + ]) + ]) +]) + +dnl # +dnl #v6.11-rc6-3-g590b9d576cae mm: kvmalloc: align kvrealloc() with krealloc() +dnl #v6.9-rc4-85-g7bd230a26648 mm/slab: enable slab allocation tagging for kmalloc and friends +dnl #v5.15-11-g8587ca6f3415 mm: move kvmalloc-related functions to slab.h +dnl #v5.14-rc4-23-gde2860f46362 mm: Add kvrealloc() +dnl # +AC_DEFUN([AC_AMDGPU_KVREALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC_3ARG, 1, [kvrealloc() has 3 arguments]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC_4ARG, 1, [kvrealloc() has 4 arguments]) + ],[ + AC_DEFINE(HAVE_NO_KVREALLOC, 1, [kvrealloc() isn't available]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 new file mode 100644 index 0000000000000..039aafc937e0c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b5dee3130bb4014511f5d0dd46855ed843e3fdc8 +dnl # PM / sleep: Refactor filesystems sync to reduce duplication +dnl # +AC_DEFUN([AC_AMDGPU_KSYS_SYNC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_sync_helper(); + ], [ + AC_DEFINE(HAVE_KSYS_SYNC_HELPER, 1, + [ksys_sync_helper() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 new file mode 100644 index 0000000000000..6177b3b6fa49e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract +dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c +dnl # +AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # sle sp2 server distro inlines kthread_use_mm/kthread_unuse_mm + dnl # in mmu_context.h + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + kthread_use_mm(NULL); + kthread_unuse_mm(NULL); + ], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 new file mode 100644 index 0000000000000..234ef7efa54b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v5.2-rc5-8-g9285ec4c8b61 +dnl # timekeeping: Use proper clock specifier names in functions +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_BOOTTIME_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_boottime_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_BOOTTIME_NS, 1, + [ktime_get_boottime_ns() is available]) + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ],[ + dnl # + dnl # commit v3.16-rc5-76-g897994e32b2b + dnl # timekeeping: Provide ktime_get[*]_ns() helpers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + ktime_get_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 new file mode 100644 index 0000000000000..0bd3f631e535f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.18-rc1-35-ga8802d97e733 +dnl # ktime: Get rid of the union +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_IS_UNION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t t; + t.tv64 = 0; + ], [ + AC_DEFINE(HAVE_KTIME_IS_UNION, 1, + [ktime_t is union]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 new file mode 100644 index 0000000000000..f025643ea5b56 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-fs.m4 @@ -0,0 +1,41 @@ +dnl # +dnl # commit v6.9-rc1-17-g210a03c9d51a +dnl # fs: claw back a few FMODE_* bits +dnl # +AC_DEFUN([AC_AMDGPU_FILE_OPERATION_FOP_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct file_operations file_operation; + file_operation.fop_flags = 0; + ],[ + AC_DEFINE(HAVE_FILE_OPERATION_FOP_FLAGS, 1, + [file_operation->fop_flags is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.11-rc1-2-g88a2f6468d01 +dnl # struct fd: representation change +dnl # +AC_DEFUN([AC_AMDGPU_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct fd f; + f.word = 0; + fd_empty(f); + ],[ + AC_DEFINE(HAVE_FD_EMPTY, 1, + [fd_empty is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_FILE_OPERATION], [ + AC_AMDGPU_FILE_OPERATION_FOP_FLAGS + AC_AMDGPU_FD +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 new file mode 100644 index 0000000000000..640ce25dcfd15 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -0,0 +1,187 @@ +AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ + + dnl # + dnl # commit 8bd9cb51daac89337295b6f037b0486911e1b408 + dnl # locking/atomics, asm-generic: Move some macros from + dnl # to a new file + dnl # + AC_KERNEL_CHECK_HEADERS([linux/bits.h]) + + dnl # + dnl # commit v4.3-rc4-1-g2f8e2c877784 + dnl # move io-64-nonatomic*.h out of asm-generic + dnl # + AC_KERNEL_CHECK_HEADERS([linux/io-64-nonatomic-lo-hi.h]) + + dnl # + dnl # commit 299878bac326c890699c696ebba26f56fe93fc75 + dnl # treewide: move set_memory_* functions away from cacheflush.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/set_memory.h]) + + dnl # + dnl # commit df6b35f409af0a8ff1ef62f552b8402f3fef8665 + dnl # x86/fpu: Rename i387.h to fpu/api.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/fpu/api.h]) + + dnl # + dnl # v4.19-rc6-7-ga3f8a30f3f00 + dnl # Compiler Attributes: use feature checks instead of version checks + dnl # + AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) + + dnl # + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) + + dnl # + dnl # v5.3-rc1-449-g52791eeec1d9 + dnl $ dma-buf: rename reservation_object to dma_resv + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-resv.h]) + + dnl # + dnl # v5.7-13149-g9740ca4e95b4 + dnl # mmap locking API: initial implementation as rwsem wrappers + dnl # + AC_KERNEL_CHECK_HEADERS([linux/mmap_lock.h]) + + dnl # + dnl # v4.19-rc4-1-g52916982af48 + dnl # PCI/P2PDMA: Support peer-to-peer memory + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pci-p2pdma.h]) + + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-attrs.h]) + + dnl # + dnl # 01fd30da0474 + dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + + dnl # + dnl # 7938f4218168 + dnl # dma-buf: dma-buf-map: Rename to iosys-map + dnl # + AC_KERNEL_CHECK_HEADERS([linux/iosys-map.h]) + + dnl # + dnl # v5.14-rc5-11-gc0891ac15f04 + dnl # isystem: ship and use stdarg.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) + + dnl # + dnl # v5.0-1331-g7bf60c52e093 + dnl # dma-buf: add new dma_fence_chain container v7 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) + + dnl # + dnl # v4.16-11455-gf6bb2a2c0b81 + dnl # xarray: add the xa_lock to the radix_tree_root + dnl # + AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) + + dnl # + dnl # v5.15-272-gd2a8ebbf8192 + dnl # kernel.h: split out container_of() and typeof_member() macros + dnl # + AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) + + dnl # + dnl # v5.15-rc4-2-g46b49b12f3fc + dnl # arch/cc: Introduce a function to check for confidential computing features + dnl # + AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) + + dnl # + dnl # v4.12-rc3-120-gfd851a3cdc19 + dnl # spin loop primitives for busy waiting + dnl # + AC_KERNEL_CHECK_HEADERS([linux/processor.h]) + + dnl # + dnl # v5.9-rc6-311-g0a0f0d8be76d + dnl # dma-mapping: split + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) + + dnl #v4.5-rc3-203-g2413306c2566 + dnl #apple-gmux: Add helper for presence detect + dnl + AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) + + dnl #v5.5-rc2-6-ga8ae608529ab + dnl #device.h: move 'struct class' stuff out to device/class.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) + + dnl #v4.12-10499-gbc6245e5efd7 + dnl #bug: split BUILD_BUG stuff out into + dnl + AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) + + dnl #v6.7-rc1-2-g58e82a62669d + dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature + dnl + AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) + + dnl #v5.5-5479-g23331e489361 + dnl #include/linux/units.h: add helpers for kelvin to/from Celsius conversion + dnl + AC_KERNEL_CHECK_HEADERS([linux/units.h]) + + dnl #v5.17-rc6-1496-g64a8f92fd783 + dnl #dma-buf: add dma_fence_unwrap v2 + dnl + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-unwrap.h]) + + dnl #5.19-rc2-317-g7283f862bd99 + dnl #drm: Implement DRM aperture helpers under video/ + dnl + AC_KERNEL_CHECK_HEADERS([linux/aperture.h]) + + dnl #v5.9-7812-gb296a6d53339 + dnl #kernel.h: split out min()/max() et al. helpers + dnl + AC_KERNEL_CHECK_HEADERS([linux/minmax.h]) + + dnl #v6.13-rc6-1-gb168ed458dde + dnl #kernel/cgroup: Add "dmem" memory accounting cgroup + dnl + AC_KERNEL_CHECK_HEADERS([linux/cgroup_dmem.h]) + + dnl #v6.5-rc3-2-g85be6d842447 + dnl #locking: Introduce __cleanup() based infrastructure + dnl + AC_KERNEL_CHECK_HEADERS([linux/cleanup.h]) + + dnl #v6.5-rc4-31-gb229baa374db + dnl #kernel.h: split out COUNT_ARGS() and CONCATENATE() to args.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/args.h]) + + dnl #v4.14-rc6-20-gd15155824c50 + dnl #linux/compiler.h: Split into compiler.h and compiler_types.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/compiler_types.h]) + + dnl #v5.12-rc2-4-g359a376081d4 + dnl #kunit: support failure from dynamic analysis tools + dnl + AC_KERNEL_CHECK_HEADERS([kunit/test-bug.h]) + + dnl #v5.5-rc2-4-gaf628aae8640 + dnl #device.h: move dev_printk()-like functions to dev_printk.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dev_printk.h]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 new file mode 100644 index 0000000000000..566de635a47da --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 70b44595eafe9c7c235f076d653a268ca1ab9fdb +dnl # Author: Mel Gorman +dnl # Date: Tue Mar 5 15:44:54 2019 -0800 +dnl # mm, compaction: use free lists to quickly locate a migration source +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_first(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_FIRST, 1, + [list_is_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 new file mode 100644 index 0000000000000..2e914f0314652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit a16b53849913e742d086bb2b6f5e069ea2850c56 +dnl # Author: Tobin C. Harding +dnl # Date: Mon May 13 17:15:59 2019 -0700 +dnl # list: add function list_rotate_to_front() +dnl # +AC_DEFUN([AC_AMDGPU_LIST_ROTATE_TO_FRONT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_rotate_to_front(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_ROTATE_TO_FRONT, 1, + [list_rotate_to_front() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 new file mode 100644 index 0000000000000..00495bfaa1f6b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc6-9-g4f0f586bf0c8 +dnl # treewide: Change list_sort to use const pointers +dnl # +AC_DEFUN([AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_cmp_func_t cmp = NULL; + struct list_head a = {0}, b = {0}; + cmp(NULL, &a, &b); + ], [ + AC_DEFINE(HAVE_LIST_CMP_FUNC_IS_CONST_PARAM, 1, + [list_cmp_func() is const param]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 b/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 new file mode 100644 index 0000000000000..81db7cc617a1d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list_is_head.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.16-23-g0425473037db +dnl # list: introduce list_is_head() helper and re-use it in list.h +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_HEAD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_head(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_HEAD, 1, + [list_is_head() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 new file mode 100644 index 0000000000000..de3f546345a28 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # +dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again +dnl # +AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) + ]) +]) +dnl # +dnl # v5.13-rc3-1-g94a311ce248e +dnl # x86/MCE/AMD, EDAC/mce_amd: Add new SMCA bank types +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum smca_bank_types bank_type; + bank_type = SMCA_UMC_V2; + ], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [enum SMCA_UMC_V2 is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 new file mode 100644 index 0000000000000..f9d0ba9a842cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + memalloc_noreclaim_save(); + ], [ + AC_DEFINE(HAVE_MEMALLOC_NORECLAIM_SAVE, 1, + [memalloc_noreclaim_save() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 b/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 new file mode 100644 index 0000000000000..8f11b7597c3a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mempool_alloc_preallocated.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.7-rc4-323-g37dcc69ad17a +dnl # mempool: introduce mempool_use_prealloc_only +dnl # +AC_DEFUN([AC_AMDGPU_MEMPOOL_ALLOC_PREALLOCATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + mempool_alloc_preallocated(NULL); + ],[mempool_alloc_preallocated], [mm/mempool.c],[ + AC_DEFINE(HAVE_MEMPOOL_ALLOC_PREALLOCATED, 1, + [mempool_alloc_preallocated() is available]) + ]) + ]) +]) + \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 new file mode 100644 index 0000000000000..53d34285e3b83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit f25cbb7a95a24ff9a2a3bebd308e303942ae6b2c +dnl # mm: add zone device coherent type memory support +dnl # +dnl # commit dd19e6d8ffaa1289d75d7833de97faf1b6b2c8e4 +dnl # mm: add device coherent vma selection for memory migration +dnl # +AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int v, w; + v = MEMORY_DEVICE_COHERENT; + w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + ], [ + AC_DEFINE(HAVE_DEVICE_COHERENT, 1, + [MEMORY_DEVICE_COHERENT is availablea]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 new file mode 100644 index 0000000000000..6de719a9bc6da --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.6-rc2-1-g66630058e56b +dnl # sched/rt: Provide migrate_disable/enable() inlines +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_DISABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + migrate_disable(); + ],[ + AC_DEFINE(HAVE_MIGRATE_DISABLE, 1, + [migrate_disable() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 new file mode 100644 index 0000000000000..f989b29503c45 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v6.0-rc3-595-g16ce101db85d +dnl # mm/memory.c: fix race when faulting a device private page +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma mig = {0}; + struct page *fault_page = NULL; + mig.fault_page = fault_page; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, + [struct migrate_vma has fault_page]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 new file mode 100644 index 0000000000000..108c7086638bd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.0-rc2-7-g05a940656e1e +dnl # slab: Introduce kmalloc_size_roundup() +dnl # +AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_t a, b = 0; + a = kmalloc_size_roundup(b); + ], [ + AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, + [kmalloc_size_roundup is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 new file mode 100644 index 0000000000000..f38fdf7f5d53c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.7-13157-g42fc541404f2 +dnl # mmap locking API: add mmap_assert_locked() and mmap_assert_write_locked() +dnl # +AC_DEFUN([AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmap_assert_write_locked(NULL); + ], [ + AC_DEFINE(HAVE_MMAP_ASSERT_WRITE_LOCKED, 1, + [mmap_assert_write_locked() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 new file mode 100644 index 0000000000000..cd095610a3c31 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.14-rc3-117-ga1b2289cef92 android: binder: drop lru lock in isolate callback +dnl # v4.13-4372-g212925802454 mm: oom: let oom_reap_task and exit_mmap run concurrently +dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from the oom reaper context +dnl # v6.0-rc1-16-g85eaeb5058f0 IB/core: Fix a nested dead lock as part of ODP flow (export symbol) +dnl # +AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + mmput_async(NULL); + ],[mmput_async], [kernel/fork.c], [ + AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 new file mode 100644 index 0000000000000..8b1aad73065f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 @@ -0,0 +1,18 @@ +dnl # commit b972216e27d1c853eced33f8638926636c606341 +dnl # mmu_notifier: add call_srcu and sync function +dnl # for listener to delay call and sync +dnl # +dnl # commit v5.3-rc5-63-gc96245148c1e +dnl # mm/mmu_notifiers: remove unregister_no_release +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_call_srcu(NULL, NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_CALL_SRCU, 1, [mmu_notifier_call_srcu() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 new file mode 100644 index 0000000000000..a5e8dcde897ff --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.3-rc1-29-g2c7933f53f6b +dnl # mm/mmu_notifiers: add a get/put scheme for the registration +dnl # +dnl # amdkcl: mmu_notifier_put() & mmu_notifier_synchronize() is +dnl # introduced in the same commit, yet rhel7.7 has different behavior +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_PUT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_put(NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_PUT, 1, + [mmu_notifier_put() is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_synchronize(); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_SYNCHRONIZE, 1, + [mmu_notifier_synchronize() is available]) + ]) + AC_AMDGPU_MMU_NOTIFIER_PUT + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 new file mode 100644 index 0000000000000..06742541fd0d9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4a83bfe916f3d2100df5bc8389bd182a537ced3e +dnl # mm/mmu_notifier: helper to test if a range invalidation is blockable +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmu_notifier_range_blockable(NULL); + ], [ + AC_DEFINE(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE, 1, + [mmu_notifier_range_blockable() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 b/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 new file mode 100644 index 0000000000000..bdc84e5d287c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/module_import_ns.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v6.13-rc1-2-gcdd30ebb1b9f +dnl # module: Convert symbol namespace to string literal +dnl # +AC_DEFUN([AC_AMDGPU_MODULE_IMPORT_NS], [ + AC_KERNEL_DO_BACKGROUND([ + header_file_src=$LINUX/include/linux/module.h + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -qE '^#define MODULE_IMPORT_NS\(ns\)\s+MODULE_INFO\(import_ns, ns\)$' $header_file_src ], [ + AC_DEFINE(HAVE_MODULE_IMPORT_NS_NEED_A_STRING, 1, + [MODULE_IMPORT_NS() wants a string arguments]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/overflow.m4 b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 new file mode 100644 index 0000000000000..e62b784d85e4c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/overflow.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # v5.17-rc3-2-ge1be43d9b5d0 +dnl # overflow: Implement size_t saturating arithmetic helpers +dnl # +AC_DEFUN([AC_AMDGPU_SIZE_MUL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_t offset; + offset = size_mul(0, 0); + ], [ + AC_DEFINE(HAVE_SIZE_MUL, 1, + [size_mul() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_RANGE_OVERFLOWS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool ret; + ret = range_overflows(0, 0, 0); + ], [ + AC_DEFINE(HAVE_RANGE_OVERFLOWS, 1, + [range_overflows() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 b/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 new file mode 100644 index 0000000000000..411f154c31e59 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/page_flag.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.14-rc6-302-g82ba975e4c43 +dnl # mm: allow compound zone device pages +dnl # +AC_DEFUN([AC_AMDGPU_PAGE_PGMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + page_pgmap(NULL); + ], [ + AC_DEFINE(HAVE_PAGE_PGMAP, 1, + [page_pgmap() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 new file mode 100644 index 0000000000000..c46dfedbf7a34 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 62ce94a7a5a54aac80975f5e6731707225d4077e +dnl # PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken +dnl # +AC_DEFUN([AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_host_bridge bridge; + bridge.no_ext_tags = 0; + ], [ + AC_DEFINE(HAVE_PCI_CONFIGURE_EXTENDED_TAGS, 1, + [PCI driver handles extended tags]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 new file mode 100644 index 0000000000000..0138c0b995d3c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -0,0 +1,38 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_dev_id(NULL); + ], [ + AC_DEFINE(HAVE_PCI_DEV_ID, 1, + [pci_dev_id() is available]) + ]) + ]) +]) + +dnl # +dnl # commit: v6.6-rc1-1-gd427da2323b0 +dnl # PCI: Add pci_get_base_class() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_GET_BASE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pci_get_base_class(0, NULL); + ], [pci_get_base_class], [drivers/pci/search.c], [ + AC_DEFINE(HAVE_PCI_GET_BASE_CLASS, 1, + [pci_get_base_class() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_PCI], [ + AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_GET_BASE_CLASS +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 new file mode 100644 index 0000000000000..dfb7bd92cade1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ded13b9cfd595adb478a1e371d2282048bba1df5 +dnl # PCI: Add support for dev_groups to struct pci_driver +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_driver *pd = NULL; + pd->dev_groups = NULL; + ], [ + AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 new file mode 100644 index 0000000000000..9201093cd8f20 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_dev_is_disconnected.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v6.8-rc3-9-g39714fd73c6b +dnl # PCI: Make pci_dev_is_disconnected() helper public for other drivers +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_IS_DISCONNECTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_dev_is_disconnected(NULL); + ], [ + AC_DEFINE(HAVE_PCI_DEV_IS_DISCONNECTED, 1, [pci_dev_is_disconnected is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 new file mode 100644 index 0000000000000..e0fbc073caf06 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v5.4-rc2-37-g52525b7a3cf8 +dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence +dnl # +AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pci_pr3_present(NULL); + ],[pci_pr3_present], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 new file mode 100644 index 0000000000000..01d066282244a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 192f1bf7559e895d51f81c3976c5892c8b1e0601 +dnl # PCI: Add pci_rebar_bytes_to_size() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_rebar_bytes_to_size(0); + ], [ + AC_DEFINE(HAVE_PCI_REBAR_BYTES_TO_SIZE, 1, + [pci_rebar_bytes_to_size() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 new file mode 100644 index 0000000000000..76b876c4b3ec3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_get_max_size.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.18-rc1-19-g1c680f2acdbb +dnl # PCI: Add pci_rebar_get_max_size() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_REBAR_GET_MAX_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_rebar_get_max_size(NULL, 0); + ], [ + AC_DEFINE(HAVE_PCI_REBAR_GET_MAX_SIZE, 1, + [pci_rebar_get_max_size() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 new file mode 100644 index 0000000000000..29a6f5dc91d1b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_resize_resource.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.18-rc1-12-g9f71938cd77f +dnl # PCI: Move Resizable BAR code to rebar.c +dnl # +AC_DEFUN([AC_AMDGPU_PCI_RESIZE_RESOURCE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret = 0; + ret = pci_resize_resource(NULL, 0, 0, 0); + ], [ + AC_DEFINE(HAVE_PCI_RESIZE_RESOURCE_ALIGN, 1, + [pci_resize_resource() has align parameter]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 new file mode 100644 index 0000000000000..32927a35d28f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.3-rc4-1-gaccd2dd72c8f +dnl # PCI/ASPM: Add pcie_aspm_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_ASPM_ENABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pcie_aspm_enabled(NULL); + ], [ + AC_DEFINE(HAVE_PCIE_ASPM_ENABLED, 1, + [pcie_aspm_enabled() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 new file mode 100644 index 0000000000000..6447b6c16afac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/peer_direct.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # +dnl # PEER DIRECT support +dnl # +dnl # Note that some kernels will have rdma/peer_mem.h and general P2P +dnl # support included. We should check for that case first. If so, we +dnl # set p2p support to 1. +dnl # If the system uses the ofa_kernel, which is present outside of the +dnl # base kernel, then check if it exists and has a p2p symbol present. +dnl # If so, we set p2p support to 1, but also require setting the path +dnl # to the ofa_kernel, which is checked in Kbuild. +dnl # This way we can support configs that have p2p integrated into the +dnl # base kernel, or configs using the ofa_kernel +AC_DEFUN([AC_AMDGPU_KFD_PEERDIRECT_SUPPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct peer_memory_client client; + ib_register_peer_memory_client(&client, NULL); + ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + ], [ + AS_IF([ grep -qw ib_register_peer_memory_client /usr/src/ofa_kernel/x86_64/${KERNELVER}/Module.symvers ], [ + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available]) + AC_DEFINE(HAVE_KFD_PEERDIRECT_SUPPORT_NEED_OFAPATH, 1, [HAVE_KFD_PEERDIRECT_SUPPORT is available and needs OFA path]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 new file mode 100644 index 0000000000000..da986da3833f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.18-rc1-6-g6883f81aac6f +dnl # pid: Implement PIDTYPE_TGID +dnl # +AC_DEFUN([AC_AMDGPU_PID_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum pid_type a; + a = PIDTYPE_TGID; + ], [ + AC_DEFINE(HAVE_PIDTYPE_TGID, 1, + [PIDTYPE is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 new file mode 100644 index 0000000000000..43400adb13498 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_hibernate_is_recovering.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.16-rc6-1339-g9b934e465aaf +dnl # PM: hibernate: add new api pm_hibernate_is_recovering() +dnl # +AC_DEFUN([AC_AMDGPU_PM_HIBERNATE_IS_RECOVERING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pm_hibernate_is_recovering(); + ], [ + AC_DEFINE(HAVE_PM_HIBERNATE_IS_RECOVERING, 1, + [pm_hibernate_is_recovering() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 new file mode 100644 index 0000000000000..c160029bddfd1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_hibernation_mode_is_suspend.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.16-2076-gbed9bcd014c2 +dnl # PM: hibernate: Add pm_hibernation_mode_is_suspend() +dnl # +AC_DEFUN([AC_AMDGPU_PM_HIBERNATION_MODE_IS_SUSPEND], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pm_hibernation_mode_is_suspend(); + ], [ + AC_DEFINE(HAVE_PM_HIBERNATION_MODE_IS_SUSPEND, 1, + [pm_hibernation_mode_is_suspend() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 new file mode 100644 index 0000000000000..f694f53991e2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_get_if_active.m4 @@ -0,0 +1,25 @@ +dnl # +dnl # commit v5.6-rc4-1-gc111566bea7c +dnl # PM: runtime: Add pm_runtime_get_if_active() +dnl # +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_GET_IF_ACTIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_runtime_get_if_active(NULL); + ],[ + AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_1ARGS, 1, + [pm_runtime_get_if_active() has one parameters]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_runtime_get_if_active(NULL, 0); + ],[ + AC_DEFINE(HAVE_PM_RUNTIME_GET_IF_ACTIVE_2ARGS, 1, + [pm_runtime_get_if_active() has two parameters]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 new file mode 100644 index 0000000000000..ac3809d47fbd8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_put_autosuspend.m4 @@ -0,0 +1,10 @@ +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_PUT_AUTOSUSPEND], [ + AC_MSG_CHECKING([if pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy]) + AS_IF([sed -n '/static inline int pm_runtime_put_autosuspend/,/^}/p' ${LINUX}/include/linux/pm_runtime.h | grep -q "pm_runtime_mark_last_busy"], [ + AC_MSG_RESULT([yes]) + AC_DEFINE(HAVE_PM_RUNTIME_PUT_AUTOSUSPEND_MARK_LAST_BUSY, 1, + [pm_runtime_put_autosuspend includes pm_runtime_mark_last_busy]) + ], [ + AC_MSG_RESULT([no]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 new file mode 100644 index 0000000000000..738b08a40004b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_runtime_resume_and_get.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.10-rc3-244-gdd8088d5a896 +dnl # PM: runtime: Add pm_runtime_resume_and_get to deal with usage counter +dnl # +AC_DEFUN([AC_AMDGPU_PM_RUNTIME_RESUME_AND_GET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_runtime_resume_and_get(NULL); + ],[ + AC_DEFINE(HAVE_PM_RUNTIME_RESUME_AND_GET, 1, + [pm_runtime_resume_and_get() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 new file mode 100644 index 0000000000000..7f4394902241d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit edf3ad32f18b0ea7d27ea9420f3bb9b2c850b48b +dnl # drm/amd: Warn users about potential s0ix problems +dnl # +AC_DEFUN([AC_AMDGPU_PM_SUSPEND_TARGET_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_suspend_target_state = PM_SUSPEND_TO_IDLE; + ],[ + AC_DEFINE(HAVE_PM_SUSPEND_TARGET_STATE, + 1, + [pm_suspend_target_state is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/processor.m4 b/drivers/gpu/drm/amd/dkms/m4/processor.m4 new file mode 100644 index 0000000000000..66dececcd8989 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/processor.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.6-rc1-4-gb9655e702dc5 +dnl # x86/cpu: Encapsulate topology information in cpuinfo_x86 +dnl # +AC_DEFUN([AC_AMDGPU_CPUINFO_X86], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct cpuinfo_x86* cpuinfo = NULL; + struct cpuinfo_topology topo; + topo = cpuinfo -> topo; + ],[ + AC_DEFINE(HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT, 1, + [ cpuinfo_x86.topo is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 new file mode 100644 index 0000000000000..a69d9f2264f6c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.7-20-gf2af6d3978d7 +dnl # virtio-mem: Allow to specify an ACPI PXM as nid +dnl # +AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pxm_to_node(0); + ],[pxm_to_node], [drivers/acpi/numa/srat.c], [ + AC_DEFINE(HAVE_PXM_TO_NODE, 1, + [pxm_to_node() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 b/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 new file mode 100644 index 0000000000000..bc80daac823ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ratelimit_state_reset_interval.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.15-rc1-1-g56a7b9f8b059 +dnl # ratelimit: Create functions to handle ratelimit_state internals +dnl # +AC_DEFUN([AC_AMDGPU_RATELIMIT_STATE_RESET_INTERVAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ratelimit_state_reset_interval(NULL,0); + ],[ + AC_DEFINE(HAVE_RATELIMIT_STATE_RESET_INTERVAL, 1, + [ratelimit_state_reset_interval() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 new file mode 100644 index 0000000000000..0a29c2b864323 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_RB_ADD_CACHED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + rb_add_cached(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_RB_ADD_CACHED, 1, + [rb_add_cached is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 new file mode 100644 index 0000000000000..98c49b53ddc6f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -0,0 +1,41 @@ +dnl # +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration +dnl # +AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ],[ + struct shrinker *a = NULL; + const char *b = NULL; + register_shrinker(a, b); + ],[ + AC_DEFINE(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS, 1, + [whether register_shrinker(x, x) is available]) + ]) + ]) +]) + +dnl # +dnl # commit: v6.6-rc4-53-gc42d50aefd17 +dnl # mm: shrinker: add infrastructure for dynamically allocating shrinker +dnl # +AC_DEFUN([AC_AMDGPU_SHRINKER_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shrinker_register(NULL); + ], [shrinker_register], [mm/shrinker.c], [ + AC_DEFINE(HAVE_SHRINKER_REGISTER, 1, + [shrinker_register() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_SHRINKER], [ + AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER_REGISTER +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 new file mode 100644 index 0000000000000..474a1baed1064 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sg_alloc_table_from_pages_segment.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit 90e7a6de62781c27d6a111fccfb19b807f9b6887 +dnl # v5.14-rc6-1-g90e7a6de6278 +dnl # lib/scatterlist: Provide a dedicated function to support table append +dnl # +AC_DEFUN([AC_AMDGPU_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + sg_alloc_table_from_pages_segment(NULL,NULL,0,0,0,0,GFP_KERNEL); + ], [sg_alloc_table_from_pages_segment],[lib/scatterlist.c], [ + AC_DEFINE(HAVE_SG_ALLOC_TABLE_FROM_PAGES_SEGMENT, 1, + [sg_alloc_table_from_pages_segment() is available]) + ],[ + dnl # + dnl # commit 07da1223ec939982497db3caccd6215b55acc35c + dnl # v5.9-rc8-3-g07da1223ec93 + dnl # lib/scatterlist: Add support in dynamic allocation of SG table from pages + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + __sg_alloc_table_from_pages(NULL,NULL,0,0,0,0,NULL,0,GFP_KERNEL); + ], [__sg_alloc_table_from_pages],[lib/scatterlist.c], [ + AC_DEFINE(HAVE___SG_ALLOC_TABLE_FROM_PAGES_9ARGS, 1, + [__sg_alloc_table_from_pages() has 9 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 new file mode 100644 index 0000000000000..619dd99b8d0d7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem-file-setup-vma-flags.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v7.0-rc4-590d356aa433 +dnl # mm: update shmem_[kernel]_file_*() functions to use vma_flags_t +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_FILE_SETUP_VMA_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + shmem_file_setup("test", 0, EMPTY_VMA_FLAGS); + ], [ + AC_DEFINE(HAVE_SHMEM_FILE_SETUP_VMA_FLAGS, 1, + [shmem_file_setup() takes vma_flags_t arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 new file mode 100644 index 0000000000000..fa41d75272979 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem-fs.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-rc4-463-gf01b2b3ed873 +dnl # shmem: add shmem_read_folio() and shmem_read_folio_gfp() +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_READ_FOLIO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + shmem_read_folio(NULL, 0); + ], [ + AC_DEFINE(HAVE_SHMEM_READ_FOLIO, 1, + [shmem_read_folio() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 new file mode 100644 index 0000000000000..1becbe3ee7c21 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/shmem_writeout.m4 @@ -0,0 +1,29 @@ +dnl # +dnl # commit v6.15-rc1-5-g7b73c12c6ebf +dnl # shmem: Add shmem_writeout() +dnl # +AC_DEFUN([AC_AMDGPU_SHMEM_WRITEOUT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT, 1, + [shmem_writeout() is available]) + ],[ + dnl # + dnl # commit v6.16-rc5-20-g44b1b073eb36 + dnl # mm: stop passing a writeback_control structure to shmem_writeout + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shmem_writeout(NULL, NULL,NULL); + ],[shmem_writeout], [mm/shmem.c],[ + AC_DEFINE(HAVE_SHMEM_WRITEOUT_WANT_3_ARGS, 1, + [shmem_writeout() wants 3 arguments]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 new file mode 100644 index 0000000000000..4dbfe78524f84 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -0,0 +1,49 @@ +dnl # +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + unsigned int a = 0, b = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a, b); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS, 1, + [whether smca_get_bank_type(x, x) is available]) + ],[ + dnl # + dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + unsigned int a = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT, 1, + [smca_get_bank_type(x) is available]) + ],[ + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + + ]) + ]) + + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 b/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 new file mode 100644 index 0000000000000..df1463125da0d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_read_write.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 1f5d7ea73c4b630dbb2c90818cb9fc0be54d2fe3 +dnl # lib/string_helpers: Add str_read_write() helper +dnl # v6.0-rc1-122-g1f5d7ea73c4b +dnl # +AC_DEFUN([AC_AMDGPU_STR_READ_WRITE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str; + str = str_read_write(true); + ], [ + AC_DEFINE(HAVE_STR_READ_WRITE, 1, + [str_read_write() is defined]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 new file mode 100644 index 0000000000000..5aefabf94021b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit ea4692c75e1c63926e4fb0728f5775ef0d733888 +dnl # lib/string_helpers: Consolidate string helpers implementation +dnl # +AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str; + str = str_yes_no(true); + ], [ + AC_DEFINE(HAVE_STR_YES_NO, 1, + [str_yes_no() is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 new file mode 100644 index 0000000000000..f3044c21f6b68 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.8-rc2-15-ge6584c3964f2 +dnl # string: Allow 2-argument strscpy() +dnl # +AC_DEFUN([AC_AMDGPU_STRSCPY_ALLOW_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + char name[8]; + strscpy(name, "foo"); + ],[ + AC_DEFINE(HAVE_STRSCPY_ALLOW_TWO_ARGUMENTS, 1, + [strscpy() allows two arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 new file mode 100644 index 0000000000000..1ad8e20e51b6c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 @@ -0,0 +1,48 @@ +dnl # +dnl # commit v6.12-rc6-16-gb626816fdd7f +dnl # sysfs: treewide: constify attribute callback of bin_is_visible() +dnl # +AC_DEFUN([AC_AMDGPU_BIN_FLASH_ATTR_IS_VISIBLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + static umode_t amdgpu_bin_attr_is_visible(struct kobject *kobj, + const struct bin_attribute *attr, + int idx) + { + return 0; + } + struct attribute_group amdgpu_attr_group = { + .is_bin_visible = amdgpu_bin_attr_is_visible, + }; + + ],[ + (void)amdgpu_attr_group; + ],[ + AC_DEFINE(HAVE_CONSTANT_ARGUMENT_IN_IS_BIN_VISIBLE, 1, + [need a const argument in member func .is_bin_visible]) + ]) + ]) +]) + +dnl # +dnl # commit v5.10-rc1 or later +dnl # sysfs: Make bin_attrs in struct attribute_group const +dnl # +AC_DEFUN([AC_AMDGPU_ATTRIBUTE_GROUP_BIN_ATTRS_NEW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + const struct bin_attribute *const test_bin_attrs[] = { NULL }; + struct attribute_group test_group = { + .bin_attrs = test_bin_attrs, + }; + (void)test_group; + ],[ + AC_DEFINE(HAVE_ATTRIBUTE_GROUP_BIN_ATTRS_NEW, 1, + [bin_attrs in struct attribute_group is const]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 new file mode 100644 index 0000000000000..cef143831f813 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.5-2548-g2d4457c2d03e +dnl # drm/amd/display: Add 3x4 CTM support for plane CTM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_CTM_3X4], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_color_ctm_3x4 *ctm = NULL; + ctm->matrix[0] = 0; + ],[ + AC_DEFINE(HAVE_DRM_COLOR_CTM_3X4, 1, + [struct drm_color_ctm_3x4 is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 new file mode 100644 index 0000000000000..156b6ff4ea7a8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_lut32.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # v6.18-rc2-1333-g621c45ca12ed +dnl # drm: Add Enhanced LUT precision structure +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_COLOR_LUT32], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_color_lut32 lut32; + lut32.red = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_COLOR_LUT32, 1, + [struct drm_color_lut32 is available]) + ]) + ]) +]) + +dnl # +dnl # v6.18-rc2-1333-g621c45ca12ed +dnl # drm: Add Enhanced LUT precision structure +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_LUT32_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_color_lut32_size(NULL); + ], [ + AC_DEFINE(HAVE_DRM_COLOR_LUT32_SIZE, 1, + [drm_color_lut32_size() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.18-rc2-1334-g94529775135c +dnl # drm: Add helper to extract lut from struct drm_color_lut32 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_LUT32_EXTRACT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_color_lut32_extract(0, 0); + ], [ + AC_DEFINE(HAVE_DRM_COLOR_LUT32_EXTRACT, 1, + [drm_color_lut32_extract() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_COLOR_LUT32], [ + AC_AMDGPU_STRUCT_DRM_COLOR_LUT32 + AC_AMDGPU_DRM_COLOR_LUT32_SIZE + AC_AMDGPU_DRM_COLOR_LUT32_EXTRACT +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 new file mode 100644 index 0000000000000..fbcca17fe167a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 @@ -0,0 +1,40 @@ +dnl # +dnl # commit v5.0-rc7-1020-gd2c6a405846c +dnl # drm: Add HDMI colorspace property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [drm_connector_state->colorspace is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.10-rc1-219-gab52af4ba7c7 +dnl # drm/connector: hdmi: Add Broadcast RGB property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->hdmi.broadcast_rgb = DRM_HDMI_BROADCAST_RGB_AUTO; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB, 1, + [drm_connector_state->hdmi.broadcast_rgb is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE], [ + AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE + AC_AMDGPU_DRM_CONNECTOR_STATE_HDMI_BROADCAST_RGB +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 new file mode 100644 index 0000000000000..6b53674fb88bc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -0,0 +1,39 @@ +dnl # +dnl # v5.5-rc2-1557-ge3eff4b5d91e drm/amdgpu: Convert to CRTC VBLANK callbacks +dnl # v5.5-rc2-1556-gea702333e567 drm/amdgpu: Convert to struct drm_crtc_helper_funcs.get_scanout_position() +dnl # v5.5-rc2-1555-g7fe3f0d15aac drm: Add get_vblank_timestamp() to struct drm_crtc_funcs +dnl # v5.5-rc2-1554-gf1e2b6371c12 drm: Add get_scanout_position() to struct drm_crtc_helper_funcs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_crtc_funcs *ptr = NULL; + ptr->get_vblank_timestamp(NULL, NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP, + 1, + [struct drm_crtc_funcs->get_vblank_timestamp() is available]) + ]) + ]) +]) + +dnl # +dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_atomic_helper_legacy_gamma_set(NULL, NULL, NULL, NULL, 0, NULL); + ], [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c],[],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, + [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 new file mode 100644 index 0000000000000..929e3edc5f603 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v5.5-rc2-1419-g7e13ad896484 +dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->open_count = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, + [drm_device->open_count is int]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 new file mode 100644 index 0000000000000..87a29c5cd5f4d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_display_info.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.5-rc2-871-g82b599ece3b8 +dnl # drm/edid: parse source physical address +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->source_physical_address = 0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_SOURCE_PHYSICAL_ADDRESS, 1, + [struct drm_display_info->source_physical_address is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 new file mode 100644 index 0000000000000..753914f3cc392 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_dp_mst_branch mst_primary; + const guid_t guid; + guid_copy(&mst_primary.guid, &guid); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_BRANCH_GUID_T, 1, + [the guid of struct drm_dp_mst_branch is guid_t]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 new file mode 100644 index 0000000000000..67e95bb8cf7a8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_file_debugfs_client.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.16-rc1-406-g1fd45bc21cec +dnl # drm: add debugfs support on per client-id basis +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DEBUGFS_CLIENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file file; + file.debugfs_client = NULL; + ], [ + AC_DEFINE(STRUCT_DRM_FILE_DEBUGFS_CLIENT, 1, + [drm_file->debugfs_client is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 new file mode 100644 index 0000000000000..62c60fa842710 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_memoty_status.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit v6.4-rc1-193-g686b21b5f6ca +dnl # drm: Add fdinfo memory stats +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + enum drm_gem_object_status res = 0; + res |= DRM_GEM_OBJECT_RESIDENT; + drm_print_memory_stats(NULL, NULL, res, NULL); + ],[drm_print_memory_stats], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_PRINT_MEMORY_STATS, 1, + [drm_print_memory_stats() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3 +dnl # drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_CLIENT_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_file *filp = NULL; + filp->client_id = 0; + ], [ + AC_DEFINE(HAVE_DRM_FILE_CLIENT_ID, 1, + [struct drm_file->client_id is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_FILE], [ + AC_AMDGPU_DRM_PRINT_MEMORY_STATS + AC_AMDGPU_DRM_FILE_CLIENT_ID +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 new file mode 100644 index 0000000000000..0260e0a4432b3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v6.8-rc1-123-gd35b4e13b8b8 +dnl # drm/plane: Add color pipeline property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PLANE_COLOR_PIPELINE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_plane *plane = NULL; + plane->color_pipeline_property = NULL; + ],[ + AC_DEFINE(HAVE_DRM_PLANE_COLOR_PIPELINE_PROPERTY, 1, + [drm_plane->color_pipeline_property is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE], [ + AC_AMDGPU_DRM_PLANE_COLOR_PIPELINE_PROPERTY +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 new file mode 100644 index 0000000000000..eb9f77f9d6b37 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -0,0 +1,55 @@ +dnl # commit v5.11-rc2-701-g7c11b99a8e58 +dnl # drm/atomic: Pass the full state to planes atomic_check +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs *funcs = NULL; + funcs->atomic_check(NULL, (struct drm_atomic_state *)NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, + [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) + ]) + ]) +]) + +dnl # +dnl # v6.9-rc2-213-gbf9fb17c6672 +dnl # drm/panic: Add a drm panic handler +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_plane_helper_funcs *ptr = NULL; + ptr->get_scanout_buffer(NULL, NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER, 1, + [struct drm_plane_helper_funcs->get_scanout_buffer is available]) + ]) + ]) +]) + +dnl # commit v6.14-rc1-243-gfd40a63c63a1 +dnl # drm/atomic: Let drivers decide which planes to async flip +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs* funcs = NULL; + funcs->atomic_async_check(NULL, NULL, true); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS, 1, + [drm_plane_helper_funcs->atomic_async_check() have three arguments]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_GET_SCANOUT_BUFFER + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK_THREE_ARGUMENTS +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 new file mode 100644 index 0000000000000..bd630c670c8c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_private_objs_state.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v6.18-rc1-214-g1226cd7c7686 +dnl # drm/atomic: Change state pointers to a more meaningful name +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct __drm_private_objs_state *obj_state = NULL; + obj_state->state_to_destroy = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY, 1, + [struct __drm_private_objs_state->state_to_destroy is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE], [ + AC_AMDGPU_STRUCT_DRM_PRIVATE_OBJS_STATE_STATE_TO_DESTROY +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 new file mode 100644 index 0000000000000..a698f80362f2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit aa30f47cf666111f6bbfd15f290a27e8a7b9d854 +dnl # kobject: Add support for default attribute groups to kobj_type +dnl # + +AC_DEFUN([AC_AMDGPU_STRUCT_KOBJ_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct kobj_type *k_type = NULL; + k_type->default_groups = NULL; + ],[ + AC_DEFINE(HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE, 1, + [kobj_type->default_groups is available]) + ],[ + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 new file mode 100644 index 0000000000000..17657770988f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -0,0 +1,36 @@ +dnl # +dnl # v5.8-rc4-7-g5143192cd410 mm/migrate: add a flags parameter to migrate_vma +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma *migrate = NULL; + migrate->pgmap_owner = NULL; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_PGMAP_OWNER, 1, + [migrate_vma->pgmap_owner is available]) + ]) +]) + +dnl # +dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma +dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap +dnl # +AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_OWNER, 1, + [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 new file mode 100644 index 0000000000000..9429112a66d2b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.14-rc3-760-g880121be1179 +dnl # mm/vmscan: add sync_shrinkers function v3 +dnl # +AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + synchronize_shrinkers(); + ], [synchronize_shrinkers], [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 new file mode 100644 index 0000000000000..7c355cae6ed01 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit: v5.9-rc5-23-g2efc459d06f1 +dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # to format sysfs output +AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + sysfs_emit(NULL, NULL); + sysfs_emit_at(NULL, 0, NULL); + ],[sysfs_emit sysfs_emit_at],[fs/sysfs/file.c], [ + AC_DEFINE(HAVE_SYSFS_EMIT, 1, + [sysfs_emit() and sysfs_emit_at() are available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 b/drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 new file mode 100644 index 0000000000000..ef97bed7949dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/system-percpu-wq.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit id: v6.15-1-g128ea9f6ccfb +dnl # workqueue: Add system_percpu_wq and system_dfl_wq +dnl # +AC_DEFUN([AC_AMDGPU_SYSTEM_PERCPU_WQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct workqueue_struct *wq = system_percpu_wq; + ], [system_percpu_wq], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_SYSTEM_PERCPU_WQ, 1, + [system_percpu_wq is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 b/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 new file mode 100644 index 0000000000000..9f9ba523b4a56 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/timer_delete.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.1-rc1-12-gbb663f0f3c39 +dnl # timers: Rename del_timer() to timer_delete() +dnl # +AC_DEFUN([AC_AMDGPU_TIMER_DELETE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + timer_delete(NULL); + ],[ + AC_DEFINE(HAVE_TIMER_DELETE, 1, + [timer_delete() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 new file mode 100644 index 0000000000000..f57daa513df71 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.20-6506-gca79b0c211af +dnl # mm: convert totalram_pages and totalhigh_pages variables to atomic +dnl # +AC_DEFUN([AC_AMDGPU_TOTALRAM_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long ret; + ret = totalram_pages(); + ], [ + AC_DEFINE(HAVE_TOTALRAM_PAGES, 1, + [totalram_pages() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 new file mode 100644 index 0000000000000..ed0b163902c11 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # v5.3-rc1-374-ge7f0141a217f drm/ttm: drop ttm_buffer_object->resv +dnl # v5.3-rc1-370-g5a5011a72489 drm/amdgpu: switch driver from bo->resv to bo->base.resv +dnl # v5.3-rc1-367-ge532a135d704 drm/ttm: switch ttm core from bo->resv to bo->base.resv +dnl # v5.3-rc1-365-gb96f3e7c8069 drm/ttm: use gem vma_node +dnl # v5.3-rc1-364-g1e053b10ba60 drm/ttm: use gem reservation object +dnl # v5.3-rc1-362-gc105de2828e1 drm/amdgpu: use embedded gem object +dnl # v5.3-rc1-358-g8eb8833e7ed3 drm/ttm: add gem base object +dnl # v5.0-rc1-1004-g1ba627148ef5 drm: Add reservation_object to drm_gem_object +dnl # +AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object *gem_obj = NULL; + gem_obj->resv = &gem_obj->_resv; + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, + [drm_gem_object->resv/_resv is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 new file mode 100644 index 0000000000000..cac1023aef491 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/usleep_range_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.16-rc4-168-ge4779015fd5d +dnl # timers: implement usleep_idle_range() +dnl # +AC_DEFUN([AC_AMDGPU_USLEEP_RANGE_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ], [ + usleep_range_state(0, 0, TASK_UNINTERRUPTIBLE); + ], [usleep_range_state], [kernel/time/timer.c kernel/time/sleep_timeout.c], [ + AC_DEFINE(HAVE_USLEEP_RANGE_STATE, 1, + [usleep_range_state() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 new file mode 100644 index 0000000000000..5c70d0482dc09 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vfs_iocb_iter_read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit: v5.5-rc7-11-g5dcdc43e24a1 +dnl # vfs: add vfs_iocb_iter_[read|write] helper functions +dnl # +AC_DEFUN([AC_AMDGPU_VFS_IOCB_ITER_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + vfs_iocb_iter_read(NULL, NULL, NULL); + ],[vfs_iocb_iter_read],[fs/read_write.c], [ + AC_DEFINE(HAVE_VFS_IOCB_ITER_READ, 1, + [vfs_iocb_iter_read() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 new file mode 100644 index 0000000000000..603da40bd05db --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.13-rc3-1630-gbf44e8cecc03 +dnl # vgaarb: don't pass a cookie to vga_client_register +dnl # +AC_DEFUN([AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct pci_dev; + ], [ + unsigned int (*callback)(struct pci_dev *, bool) = NULL; + vga_client_register(NULL, callback); + ], [ + AC_DEFINE(HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE, 1, + [vga_client_register() don't pass a cookie]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 new file mode 100644 index 0000000000000..f95a903f3143b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.0-rc1-998-gc6b38fbbde91 +dnl # drm: move i915_kick_out_vgacon to vgaarb +dnl # +AC_DEFUN([AC_AMDGPU_VGA_REMOVE_VGACON], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vga_remove_vgacon(NULL); + ], [ + AC_DEFINE(HAVE_VGA_REMOVE_VGACON, 1, + [vga_remove_vgacon() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 new file mode 100644 index 0000000000000..111d006f1ac28 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit v4.10-9602-g11bac8000449 +dnl # mm, fs: reduce fault, page_mkwrite, and pfn_mkwrite to take only vmf +dnl # +AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct vm_operations_struct *vm_ops = NULL; + vm_ops->fault(NULL); + ], [ + AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, + [vm_operations_struct->fault() wants 1 arg]) + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vma} is available]) + ], [ + dnl # + dnl # commit v4.9-7746-g82b0f8c39a38 + dnl # mm: join struct fault_env and vm_fault + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct vm_fault *ptest = NULL; + ptest->address = 0; + ptest->vma = NULL; + ], [ + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vma} is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 new file mode 100644 index 0000000000000..537ee8180393a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -0,0 +1,53 @@ +dnl # +dnl # v5.13-105-gce6d42f2e4a2 +dnl # mm: add vma_lookup(), update find_vma_intersection() comments +dnl # +AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_lookup(NULL, 0); + ], [ + AC_DEFINE(HAVE_VMA_LOOKUP, 1, + [vma_lookup() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.2-rc4-446-gbc292ab00f6c +dnl # mm: introduce vma->vm_flags wrapper functions +dnl # +AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vm_flags_set(NULL, 0); + vm_flags_clear(NULL, 0); + ], [ + AC_DEFINE(HAVE_VM_FLAGS_SET, 1, + [vm_flags_{set, clear} is available]) + ]) + ]) +]) + +dnl # +dnl # v6.5-rc4-265-g11250fd12eb8 +dnl # mm: factor out VMA stack and heap checks +dnl # +AC_DEFUN([AC_AMDGPU_VMA_IS_INITIAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_is_initial_heap(NULL); + vma_is_initial_stack(NULL); + ], [ + AC_DEFINE(HAVE_VMA_IS_INITIAL_HEAP, 1, + [vma_is_initial_{heap, stack} is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 b/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 new file mode 100644 index 0000000000000..90161018d5bac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmemdup_array_user.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.6-rc5-1-g313ebe47d755 +dnl # kernel: string.h: add array-wrappers for (v)memdup_user() +dnl # +AC_DEFUN([AC_AMDGPU_VMEMDUP_ARRAY_USER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vmemdup_array_user(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_VMEMDUP_ARRAY_USER, 1, + [vmemdup_array_user() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 new file mode 100644 index 0000000000000..47463793e94b1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.2-5754-g6471384af2a6 +dnl # mm: security: introduce init_on_alloc=1 and init_on_free=1 boot options +dnl # +AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool r; + r = want_init_on_free(); + ], [ + AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, + [want_init_on_free() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 new file mode 100644 index 0000000000000..9d87289b3bfc8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc1-1-g12235da8c80a +dnl # kernel/locking: Add context to ww_mutex_trylock() +dnl # +AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int r; + r = ww_mutex_trylock(NULL, NULL); + ], [ + AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, + [ww_mutex_trylock() has context arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/xarray.m4 b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 new file mode 100644 index 0000000000000..bfe64c548f1c1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.19-rc5-244-gf8d5d0cc145c +dnl # xarray: Add definition of struct xarray +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_XARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct xarray x; + xa_init(&x); + ], [ + AC_DEFINE(HAVE_STRUCT_XARRAY, 1, + [struct xarray is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 new file mode 100644 index 0000000000000..a1228bf4f67ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v4.20-6505-g9705bea5f833 +dnl # Author: Arun KS +dnl # Date: Fri Dec 28 00:34:24 2018 -0800 +dnl # mm: convert zone->managed_pages to atomic variable +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_MANAGED_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + zone_managed_pages(NULL); + ],[ + AC_DEFINE(HAVE_ZONE_MANAGED_PAGES, 1, + [zone_managed_pages() is available]) + ],[ + dnl # + dnl # commit v3.7-4152-g9feedc9d831e + dnl # mm: introduce new field "managed_pages" to struct zone + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct zone *z = NULL; + z->managed_pages = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_ZONE_MANAGED_PAGES, 1, + [zone->managed_pages is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 new file mode 100644 index 0000000000000..0e397f6383fc4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c: take a pgmap reference on page allocation +dnl # v6.0-rc3-596-gef233450898f mm: free device private pages have zero refcount +dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + zone_device_page_init(NULL); + ], [zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, + [zone_device_page_init() is available]) + ], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + zone_device_page_init(NULL,NULL, 0); + ], [zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT_3ARG, 1, + [zone_device_page_init() takes 3 arguments]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec new file mode 100644 index 0000000000000..b071bb677652a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -0,0 +1,101 @@ +%global pkg amdgpu +%global kernel kernel version +%define pkg_version 6.8.7 +%define osdb_version 1798298 +%define anolis_release 1 + +%global debug_package %{nil} + +Name: kmod-%{pkg} +Version: %(echo %{kernel} | sed -E 's/-/~/g; s/\.(an|al)[0-9]+$//g') +Release: %{pkg_version}_%{osdb_version}~%{anolis_release}%{?dist} +Summary: The amdgpu Linux kernel driver + +License: GPLv2 and Redistributable, no modification permitted +URL: http://www.amd.com/ +Source0: kmod-%{pkg}-%{pkg_version}.tar.gz + +BuildRequires: gcc +BuildRequires: make +Requires: kernel >= %{kernel} + +%description +The AMD display driver kernel module in DKMS format for AMD graphics S/W + +%prep +%autosetup -n kmod-%{pkg}-%{pkg_version} -p1 + +%build +pushd src +%{__make} KERNELVER=%(uname -r) +popd + +%install +mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko src/amddrm_exec.ko + +# Make .ko objects temporarily executable for automatic stripping +find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ + +# Generate depmod.conf +%{__install} -d %{buildroot}/%{_sysconfdir}/depmod.d/ +for kmod in $(find %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra -type f -name \*.ko -printf "%%P\n" | sort) +do + echo "override $(basename $kmod .ko) * weak-updates/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf + echo "override $(basename $kmod .ko) * extra/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf +done + +%clean +%{__rm} -rf %{buildroot} + +%post +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi +dracut -f --kver %{kernel}.%{_arch} + +%preun +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko" >> /var/run/rpm-%{pkg}-modules.list + +%postun +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{pkg}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{pkg}-modules.list +dracut -f --kver %{kernel}.%{_arch} + +%files +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_exec.ko +%defattr(644,root,root,755) +%license licenses +%config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf + +%changelog +* Thu Jul 18 2024 Bob Zhou - 6.8.7-1798298 +- diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh new file mode 100755 index 0000000000000..0c600db277937 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +MODULE_BUILD_DIR=$1 +rm -rf $MODULE_BUILD_DIR diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh new file mode 100755 index 0000000000000..3c70636d6d0eb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -0,0 +1,128 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +DKMS_TREE=$2 +MODULE_BUILD_DIR=$3 +CC=$4 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +if [ "$CC" == "gcc" ]; then + # Enable gcc-toolset for kernels that are built with non-default compiler + # perform this check only when permissions allow + if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + # CONFIG_GCC_VERSION is included in kernel v4.17-6936-ga4353898980c + if [ ! "$config_gcc_version" ]; then + config_gcc_version=$(strings /boot/vmlinuz-$KERNELVER | grep -F $KERNELVER | grep gcc | grep -oP 'gcc version \K[\d.]+') + fi + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done + fi + + gcc_version=$(($CC -dumpfullversion 2>/dev/null || $CC -dumpversion) | awk -F. '{printf "%d%02d%02d", $1, $2, $3}') + kernel_version=$(uname -r | awk -F. '{printf "%d%02d", $1, $2}') + # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. + if [ "$gcc_version" -lt 40805 ] && [ "$kernel_version" -ge 0504 ]; then + echo "Error: The GCC is too old for this kernel, please update the GCC to higher than 9.3" + exit 1 + fi +fi + +source $KCL/files + +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h + +# add amd prefix to exported symbols +for file in $FILES; do + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h +done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Kbuild +done + +# The upstream fix is commit c6031b1dbbbf ("kbuild: make *.mod rule robust against +# too long argument error"), merged in v5.19. Kernels < 6.0 may still lack this fix. +# Fix "Argument list too long" in recursive make for large modules (700+ .o files). +# Makefile.build recurses into subdirectories via sub-makes that don't inherit +# overrides. Inject the include into amd/amdgpu/Makefile; cmd_mod_fix.mk itself +# checks whether the fix is needed and is a no-op on newer kernels. +if version_lt 6.0; then + sed -i '1i\-include $(src)/../dkms/cmd_mod_fix.mk' amd/amdgpu/Makefile +fi + +export KERNELVER +ln -s $DKMS_TREE $MODULE_BUILD_DIR +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + +# unset TMPDIR in this shell +# otherwise conflicting package libpam-tmpdir incorrectly generates config +unset TMPDIR + +(cd $SRC && ./configure CC=${CC}) + +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file + done +fi + +# v6.11-rc6-3-g590b9d576cae mm: kvmalloc: align kvrealloc() with krealloc() +# Hardcoded modification for `drm_exec.c` to adapt `kvrealloc` function usage to four arguments. +# WARNING: Do NOT optimize this section. The change is essential to guarantee that if there are +# any semantic changes to 'size', it will trigger a DKMS installation failure. +# This ensures any changes to 'size' usage must be manually reviewed and addressed in this context. +if ! grep -q 'define HAVE_KVREALLOC_3ARG ' $SRC/config/config.h; then + sed -i -e 's/kvrealloc(exec->objects, size + PAGE_SIZE, GFP_KERNEL)/kvrealloc(exec->objects, size, size + PAGE_SIZE, GFP_KERNEL)/' \ + drm_exec.c +fi diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources new file mode 100644 index 0000000000000..34f51478f5472 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/sources @@ -0,0 +1,37 @@ +# +# The 'sources' file contains source/destination directives to be used +# by the build framework to construct the DKMS source tree +# +# File format: +# source destination +# ------ ----------- +# directory[/file] name directory/[file] name +# must exist at the directory: must have explicit directory name +# source path e.g. dir/ (with '/'). The name without +# slash is treated as a file if it does +# not exist +# the directory will be created if it +# does not exist +# file: optional file name at the destination +# +drivers/gpu/drm/amd . +drivers/gpu/drm/ttm . +include/drm/ttm include/drm/ +include/uapi/drm/amdgpu_drm.h include/uapi/drm/ +include/kcl include/ +drivers/gpu/drm/scheduler . +include/drm/gpu_scheduler.h include/drm/ +include/drm/amd_asic_type.h include/drm/ +include/drm/spsc_queue.h include/drm/ +include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +include/drm/amd_rdma.h include/drm/ +drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ +include/linux/dma-resv.h include/linux/ +include/kcl/reservation.h include/linux/ +include/uapi/linux/kfd_sysfs.h include/uapi/linux/ +drivers/gpu/drm/drm_gem_ttm_helper.c . +include/drm/drm_gem_ttm_helper.h include/drm/ +drivers/gpu/drm/drm_buddy.c . +include/drm/drm_buddy.h include/drm/ +drivers/gpu/drm/drm_exec.c . +include/drm/drm_exec.h include/drm/ diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h new file mode 100644 index 0000000000000..c616e0e2c1798 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +struct vm_area_struct; +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h new file mode 100644 index 0000000000000..820228761e24b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..8a1cf0f4f9e33 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h new file mode 100644 index 0000000000000..dfc77f48cef83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include +#endif + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h new file mode 100644 index 0000000000000..309ffe3820d70 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include +#include +#else +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/include/amd_acpi.h b/drivers/gpu/drm/amd/include/amd_acpi.h index 06badbf0c5b9e..84933c07f720d 100644 --- a/drivers/gpu/drm/amd/include/amd_acpi.h +++ b/drivers/gpu/drm/amd/include/amd_acpi.h @@ -24,6 +24,8 @@ #ifndef AMD_ACPI_H #define AMD_ACPI_H +#include + #define ACPI_AC_CLASS "ac_adapter" struct atif_verify_interface { @@ -112,6 +114,17 @@ struct atcs_pwr_shift_input { u8 drv_state; /* 0 = operational, 1 = not operational */ } __packed; +struct atcs_get_uma_size_output { + u16 size; /* structure size in bytes (includes size field) */ + u32 uma_size_mb; /* allocated UMA size in MB */ +} __packed; + +struct atcs_set_uma_allocation_size_input { + u16 size; /* structure size in bytes (includes size field) */ + u8 uma_size_index; /* UMA size index */ + u8 uma_size_type; /* UMA size type */ +} __packed; + /* AMD hw uses four ACPI control methods: * 1. ATIF * ARG0: (ACPI_INTEGER) function code @@ -427,7 +440,9 @@ struct atcs_pwr_shift_input { # define ATCS_PCIE_PERFORMANCE_REQUEST_SUPPORTED (1 << 1) # define ATCS_PCIE_DEVICE_READY_NOTIFICATION_SUPPORTED (1 << 2) # define ATCS_SET_PCIE_BUS_WIDTH_SUPPORTED (1 << 3) -# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7) +# define ACPI_ATCS_GET_UMA_SIZE_SUPPORTED (1 << 5) +# define ATCS_SET_POWER_SHIFT_CONTROL_SUPPORTED (1 << 7) +# define ACPI_ATCS_SET_UMA_ALLOCATION_SIZE_SUPPORTED (1 << 9) #define ATCS_FUNCTION_GET_EXTERNAL_STATE 0x1 /* ARG0: ATCS_FUNCTION_GET_EXTERNAL_STATE * ARG1: none @@ -492,4 +507,21 @@ struct atcs_pwr_shift_input { * OUTPUT: none */ +#define ATCS_FUNCTION_GET_UMA_SIZE 0x6 +/* ARG0: ATCS_FUNCTION_GET_UMA_SIZE + * ARG1: none + * OUTPUT: + * WORD - structure size in bytes (includes size field) + * DWORD - allocated UMA size in MB + */ + +#define ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE 0xA +/* ARG0: ATCS_FUNCTION_SET_UMA_ALLOCATION_SIZE + * ARG1: + * WORD - structure size in bytes (includes size field) + * BYTE - UMA size index + * BYTE - UMA size type + * OUTPUT: none + */ + #endif diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 17945094a1383..ac2d3701e2bdc 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -89,6 +89,7 @@ enum amd_apu_flags { * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine * @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia * @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor +* @AMD_IP_BLOCK_TYPE_RAS: Reliability, Availability, Serviceability * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types */ enum amd_ip_block_type { diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h new file mode 100644 index 0000000000000..aa3ef3a340134 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_offset.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _clk_15_0_0_OFFSET_HEADER +#define _clk_15_0_0_OFFSET_HEADER + +// addressBlock: clk_clk8_0_SmuClkDec +// base address: 0x6e000 +#define regCLK8_CLK0_DS_CNTL 0x4c14 +#define regCLK8_CLK0_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK1_DS_CNTL 0x4c1c +#define regCLK8_CLK1_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK2_DS_CNTL 0x4c24 +#define regCLK8_CLK2_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK3_DS_CNTL 0x4c2c +#define regCLK8_CLK3_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK4_DS_CNTL 0x4c34 +#define regCLK8_CLK4_DS_CNTL_BASE_IDX 0 +#define regCLK8_CLK0_BYPASS_CNTL 0x4c1a +#define regCLK8_CLK0_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK1_BYPASS_CNTL 0x4c22 +#define regCLK8_CLK1_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK2_BYPASS_CNTL 0x4c2a +#define regCLK8_CLK2_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK3_BYPASS_CNTL 0x4c32 +#define regCLK8_CLK3_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK4_BYPASS_CNTL 0x4c3a +#define regCLK8_CLK4_BYPASS_CNTL_BASE_IDX 0 +#define regCLK8_CLK_TICK_CNT_CONFIG_REG 0x4c51 +#define regCLK8_CLK_TICK_CNT_CONFIG_REG_BASE_IDX 0 +#define regCLK8_CLK_TICK_CNT_STATUS 0x4c52 +#define regCLK8_CLK_TICK_CNT_STATUS_BASE_IDX 0 +#define regCLK8_CLK0_CURRENT_CNT 0x4c53 +#define regCLK8_CLK0_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK1_CURRENT_CNT 0x4c54 +#define regCLK8_CLK1_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK2_CURRENT_CNT 0x4c55 +#define regCLK8_CLK2_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK3_CURRENT_CNT 0x4c56 +#define regCLK8_CLK3_CURRENT_CNT_BASE_IDX 0 +#define regCLK8_CLK4_CURRENT_CNT 0x4c57 +#define regCLK8_CLK4_CURRENT_CNT_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h new file mode 100644 index 0000000000000..c78622d06e1be --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_15_0_0_sh_mask.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _clk_15_0_0_SH_MASK_HEADER +#define _clk_15_0_0_SH_MASK_HEADER + +// addressBlock: clk_clk8_0_SmuClkDec +//CLK8_CLK_TICK_CNT_CONFIG_REG +#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD__SHIFT 0x0 +#define CLK8_CLK_TICK_CNT_CONFIG_REG__TIMER_THRESHOLD_MASK 0xFFFFL +//CLK8_CLK0_BYPASS_CNTL +#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK0_BYPASS_CNTL__CLK0_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK1_BYPASS_CNTL +#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK1_BYPASS_CNTL__CLK1_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK2_BYPASS_CNTL +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK3_BYPASS_CNTL +#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK3_BYPASS_CNTL__CLK3_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK4_BYPASS_CNTL +#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL__SHIFT 0x0 +#define CLK8_CLK4_BYPASS_CNTL__CLK4_BYPASS_SEL_MASK 0x00000007L +//CLK8_CLK0_DS_CNTL +#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK0_DS_CNTL__CLK0_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK0_DS_CNTL__CLK0_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK1_DS_CNTL +#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK1_DS_CNTL__CLK1_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK1_DS_CNTL__CLK1_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK2_DS_CNTL +#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK2_DS_CNTL__CLK2_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK2_DS_CNTL__CLK2_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK3_DS_CNTL +#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK3_DS_CNTL__CLK3_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK3_DS_CNTL__CLK3_ALLOW_DS_MASK 0x00000010L +//CLK8_CLK4_DS_CNTL +#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID__SHIFT 0x0 +#define CLK8_CLK4_DS_CNTL__CLK4_DS_DIV_ID_MASK 0x0000000FL +#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS__SHIFT 0x4 +#define CLK8_CLK4_DS_CNTL__CLK4_ALLOW_DS_MASK 0x00000010L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h new file mode 100644 index 0000000000000..3755a984681a5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_offset.h @@ -0,0 +1,17880 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dcn_4_2_0_OFFSET_HEADER +#define _dcn_4_2_0_OFFSET_HEADER + + + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x0 +#define regAZCONTROLLER0_CORB_WRITE_POINTER 0x0000 +#define regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_READ_POINTER 0x0000 +#define regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_CONTROL 0x0001 +#define regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_STATUS 0x0001 +#define regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0 +#define regAZCONTROLLER0_CORB_SIZE 0x0001 +#define regAZCONTROLLER0_CORB_SIZE_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS 0x0002 +#define regAZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS 0x0003 +#define regAZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_WRITE_POINTER 0x0004 +#define regAZCONTROLLER0_RIRB_WRITE_POINTER_BASE_IDX 0 +#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT 0x0004 +#define regAZCONTROLLER0_RESPONSE_INTERRUPT_COUNT_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_CONTROL 0x0005 +#define regAZCONTROLLER0_RIRB_CONTROL_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_STATUS 0x0005 +#define regAZCONTROLLER0_RIRB_STATUS_BASE_IDX 0 +#define regAZCONTROLLER0_RIRB_SIZE 0x0005 +#define regAZCONTROLLER0_RIRB_SIZE_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 +#define regAZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS 0x0008 +#define regAZCONTROLLER0_IMMEDIATE_COMMAND_STATUS_BASE_IDX 0 +#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS 0x000a +#define regAZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS 0x000b +#define regAZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS 0x074c +#define regAZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 + + +// addressBlock: dc_perfmon_dc_perfmondebugind +// base address: 0x0 +#define ixPERFMON_DEBUG_ID 0x0000 +#define ixPERFMON_DEBUG01 0x0001 +#define ixPERFMON_DEBUG02 0x0002 +#define ixPERFMON_DEBUG03 0x0003 +#define ixPERFMON_DEBUG04 0x0004 +#define ixPERFMON_DEBUG05 0x0005 +#define ixPERFMON_DEBUG06 0x0006 +#define ixPERFMON_DEBUG07 0x0007 +#define ixPERFMON_DEBUG08 0x0008 +#define ixPERFMON_DEBUG09 0x0009 +#define ixPERFMON_DEBUG0A 0x000a +#define ixPERFMON_DEBUG0B 0x000b +#define ixPERFMON_DEBUG0C 0x000c +#define ixPERFMON_DEBUG0D 0x000d +#define ixPERFMON_DEBUG0E 0x000e +#define ixPERFMON_DEBUG0F 0x000f +#define ixPERFMON_DEBUG10 0x0010 +#define ixPERFMON_DEBUG11 0x0011 +#define ixPERFMON_DEBUG12 0x0012 + + +// addressBlock: mcif_wb0_mcif_wbdebugind +// base address: 0x0 +#define ixMCIF_WB_DEBUG_ID 0x0000 +#define ixID01_WB_FMT_DBG 0x0001 +#define ixID02_WB_FMT_DBG 0x0002 +#define ixID03_WB_FMT_DBG 0x0003 +#define ixID04_WB_MGR_DBG 0x0004 +#define ixID05_WB_MGR_DBG 0x0005 +#define ixID06_WB_MGR_DBG 0x0006 +#define ixID07_WB_MGR_DBG 0x0007 +#define ixID08_WB_ARB_DBG 0x0008 +#define ixID09_WB_ARB_DBG 0x0009 +#define ixID0A_WB_ARB_DBG 0x000a +#define ixID0B_WB_ARB_DBG 0x000b +#define ixID0C_WB_ARB_DBG 0x000c +#define ixID0D_WB_ARB_DBG 0x000d +#define ixID0E_WB_ARB_DBG 0x000e +#define ixID0F_P010_WB_FMT_DBG_Y 0x000f +#define ixID10_P010_WB_FMT_DBG_C 0x0010 +#define ixID11_WB_ARB_P010_DBG 0x0011 +#define ixID12_WB_ARB_P010_DBG 0x0012 + + +// addressBlock: hubbub_dchubbubdebugind +// base address: 0x0 +#define ixDCHUBBUB_KEY_STATUS_DEBUG_1 0x005f +#define ixDCHUBBUB_KEY_STATUS_DEBUG_2 0x0060 + + +// addressBlock: odm0_odmdebugind +// base address: 0x0 +#define ixODM0_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM0_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM0_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM0_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: odm1_odmdebugind +// base address: 0x0 +#define ixODM1_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM1_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM1_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM1_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: odm2_odmdebugind +// base address: 0x0 +#define ixODM2_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM2_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM2_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM2_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: odm3_odmdebugind +// base address: 0x0 +#define ixODM3_OPTC_INPUT_DEBUG_ID 0x0000 +#define ixODM3_OPTC_INPUT_DEBUG0 0x0001 +#define ixODM3_OPTC_INPUT_DEBUG1 0x0002 +#define ixODM3_OPTC_INPUT_DEBUG2 0x0003 + + +// addressBlock: rbbmif_rbbmifdebugind +// base address: 0x0 +#define ixRBBMIF_DEBUG_ID 0x0000 +#define ixRBBMIF_DEBUG_0 0x0001 +#define ixRBBMIF_DEBUG_1 0x0002 +#define ixRBBMIF_DEBUG_2 0x0003 +#define ixRBBMIF_DEBUG_3 0x0004 +#define ixRBBMIF_DEBUG_4 0x0005 +#define ixRBBMIF_DEBUG_5 0x0006 +#define ixRBBMIF_DEBUG_6 0x0007 +#define ixRBBMIF_DEBUG_7 0x0008 +#define ixRBBMIF_DEBUG_8 0x0009 +#define ixRBBMIF_DEBUG_9 0x000a +#define ixRBBMIF_DEBUG_10 0x000b +#define ixRBBMIF_DEBUG_11 0x000c +#define ixRBBMIF_DEBUG_12 0x000d +#define ixRBBMIF_DEBUG_13 0x000e +#define ixRBBMIF_DEBUG_14 0x000f +#define ixRBBMIF_DEBUG_15 0x0010 +#define ixRBBMIF_DEBUG_16 0x0011 +#define ixRBBMIF_DEBUG_17 0x0012 +#define ixRBBMIF_DEBUG_18 0x0013 +#define ixRBBMIF_DEBUG_19 0x0014 +#define ixRBBMIF_DEBUG_20 0x0015 +#define ixRBBMIF_DEBUG_21 0x0016 +#define ixRBBMIF_DEBUG_22 0x0017 +#define ixRBBMIF_DEBUG_23 0x0018 +#define ixRBBMIF_DEBUG_24 0x0019 +#define ixRBBMIF_DEBUG_25 0x001a +#define ixRBBMIF_DEBUG_26 0x001b +#define ixRBBMIF_DEBUG_27 0x001c +#define ixRBBMIF_DEBUG_28 0x001d +#define ixRBBMIF_DEBUG_29 0x001e +#define ixRBBMIF_DEBUG_30 0x001f +#define ixRBBMIF_DEBUG_31 0x0020 +#define ixRBBMIF_DEBUG_32 0x0021 +#define ixRBBMIF_DEBUG_33 0x0022 +#define ixRBBMIF_DEBUG_34 0x0023 +#define ixRBBMIF_DEBUG_35 0x0024 +#define ixRBBMIF_DEBUG_36 0x0025 +#define ixRBBMIF_DEBUG_37 0x0026 +#define ixRBBMIF_DEBUG_38 0x0027 +#define ixRBBMIF_DEBUG_39 0x0028 +#define ixRBBMIF_DEBUG_40 0x0029 +#define ixRBBMIF_DEBUG_41 0x002a +#define ixRBBMIF_DEBUG_42 0x002b +#define ixRBBMIF_DEBUG_43 0x002c +#define ixRBBMIF_DEBUG_44 0x002d +#define ixRBBMIF_DEBUG_45 0x002e +#define ixRBBMIF_DEBUG_46 0x002f +#define ixRBBMIF_DEBUG_47 0x0030 +#define ixRBBMIF_DEBUG_48 0x0031 +#define ixRBBMIF_DEBUG_49 0x0032 +#define ixRBBMIF_DEBUG_50 0x0033 +#define ixRBBMIF_DEBUG_51 0x0034 +#define ixRBBMIF_DEBUG_52 0x0035 + + +// addressBlock: ihc_ihcdebugind +// base address: 0x0 +#define ixIHC_DEBUG_ID 0x0000 +#define ixIHC_CLIENT_DEBUG_A 0x0001 +#define ixIHC_CLIENT_DEBUG_B 0x0002 +#define ixIHC_CLIENT_DEBUG_C 0x0003 +#define ixIHC_CLIENT_DEBUG_D 0x0004 +#define ixIHC_CLIENT_DEBUG_E 0x0005 + + +// addressBlock: dmu_misc_dmumiscdebugind +// base address: 0x0 +#define ixDMU_MISC_DEBUG_ID 0x0000 +#define ixDMU_MISC_DEBUG_1 0x0001 +#define ixDMU_ZSC_TEST_DEBUG1_DATA 0x0002 +#define ixDMU_ZSC_TEST_DEBUG2_DATA 0x0003 + + +// addressBlock: dc_pg_dc_pgdebugind +// base address: 0x0 +#define ixDCPG_DEBUG_ID 0x0000 +#define ixDCPG_CONTROL_DEBUG_BUS0 0x0001 +#define ixDCPG_CONTROL_DEBUG_BUS1 0x0002 +#define ixDCPG_CONTROL_DEBUG_BUS2 0x0003 +#define ixDCPG_CONTROL_DEBUG_BUS3 0x0004 +#define ixDCPG_CONTROL_DEBUG_BUS16 0x0011 +#define ixDCPG_CONTROL_DEBUG_BUS17 0x0012 +#define ixDCPG_CONTROL_DEBUG_BUS18 0x0013 +#define ixDCPG_CONTROL_DEBUG_BUS19 0x0014 +#define ixDCPG_CONTROL_DEBUG_BUS22 0x0017 +#define ixDCPG_CONTROL_DEBUG_BUS23 0x0018 +#define ixDCPG_CONTROL_DEBUG_BUS24 0x0019 +#define ixDCPG_CONTROL_DEBUG_BUS25 0x001a +#define ixDCPG_CONTROL_DEBUG_BUS26 0x001b + + +// addressBlock: dp0_dpdebugind +// base address: 0x0 +#define ixDP0_DP_DEBUG_ID 0x0000 +#define ixDP0_DP_DEBUG_K 0x00a2 +#define ixDP0_DP_DEBUG_L 0x00a3 +#define ixDP0_DP_DEBUG_M 0x00a4 +#define ixDP0_DP_DEBUG_G 0x00b4 +#define ixDP0_DP_DEBUG_O 0x00fb +#define ixDP0_DP_DEBUG_P 0x00fc +#define ixDP0_DP_DEBUG_Q 0x00fd +#define ixDP0_DP_DEBUG_R 0x00fe +#define ixDP0_DP_DEBUG_S 0x00ff + + +// addressBlock: dp0_dpfedebugind +// base address: 0x0 +#define ixDP0_DP_FE_DEBUG_ID 0x0000 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP0_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP0_DP_DEBUG_T 0x0090 +#define ixDP0_DP_DEBUG_U 0x0091 +#define ixDP0_DP_DEBUG_V 0x0092 +#define ixDP0_DP_DEBUG_W 0x0093 +#define ixDP0_DP_DEBUG_X 0x0094 +#define ixDP0_DP_DEBUG_Y 0x0095 +#define ixDP0_DP_DEBUG_Z 0x0096 +#define ixDP0_DP_DEBUG_1A 0x0097 +#define ixDP0_DP_DEBUG_1B 0x0098 +#define ixDP0_DP_DEBUG_I 0x00a0 +#define ixDP0_DP_DEBUG_J 0x00a1 +#define ixDP0_DP_DEBUG_N 0x00a2 +#define ixDP0_DP_DEBUG_H 0x00ac +#define ixDP0_DP_DEBUG_A 0x00ad +#define ixDP0_DP_DEBUG_B 0x00ae +#define ixDP0_DP_DEBUG_C 0x00af +#define ixDP0_DP_DEBUG_D 0x00b0 +#define ixDP0_DP_DEBUG_E 0x00b2 +#define ixDP0_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp0_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP0_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig0_digdebugind +// base address: 0x0 +#define ixDIG0_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig0_digfedebugind +// base address: 0x0 +#define ixDIG0_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG0_DIG_VPG_DEBUG0 0x000b +#define ixDIG0_DIG_VPG_DEBUG1 0x000c +#define ixDIG0_DIG_VPG_DEBUG2 0x000d +#define ixDIG0_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp1_dpdebugind +// base address: 0x0 +#define ixDP1_DP_DEBUG_ID 0x0000 +#define ixDP1_DP_DEBUG_K 0x00a2 +#define ixDP1_DP_DEBUG_L 0x00a3 +#define ixDP1_DP_DEBUG_M 0x00a4 +#define ixDP1_DP_DEBUG_G 0x00b4 +#define ixDP1_DP_DEBUG_O 0x00fb +#define ixDP1_DP_DEBUG_P 0x00fc +#define ixDP1_DP_DEBUG_Q 0x00fd +#define ixDP1_DP_DEBUG_R 0x00fe +#define ixDP1_DP_DEBUG_S 0x00ff + + +// addressBlock: dp1_dpfedebugind +// base address: 0x0 +#define ixDP1_DP_FE_DEBUG_ID 0x0000 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP1_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP1_DP_DEBUG_T 0x0090 +#define ixDP1_DP_DEBUG_U 0x0091 +#define ixDP1_DP_DEBUG_V 0x0092 +#define ixDP1_DP_DEBUG_W 0x0093 +#define ixDP1_DP_DEBUG_X 0x0094 +#define ixDP1_DP_DEBUG_Y 0x0095 +#define ixDP1_DP_DEBUG_Z 0x0096 +#define ixDP1_DP_DEBUG_1A 0x0097 +#define ixDP1_DP_DEBUG_1B 0x0098 +#define ixDP1_DP_DEBUG_I 0x00a0 +#define ixDP1_DP_DEBUG_J 0x00a1 +#define ixDP1_DP_DEBUG_N 0x00a2 +#define ixDP1_DP_DEBUG_H 0x00ac +#define ixDP1_DP_DEBUG_A 0x00ad +#define ixDP1_DP_DEBUG_B 0x00ae +#define ixDP1_DP_DEBUG_C 0x00af +#define ixDP1_DP_DEBUG_D 0x00b0 +#define ixDP1_DP_DEBUG_E 0x00b2 +#define ixDP1_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp1_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP1_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig1_digdebugind +// base address: 0x0 +#define ixDIG1_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig1_digfedebugind +// base address: 0x0 +#define ixDIG1_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG1_DIG_VPG_DEBUG0 0x000b +#define ixDIG1_DIG_VPG_DEBUG1 0x000c +#define ixDIG1_DIG_VPG_DEBUG2 0x000d +#define ixDIG1_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp2_dpdebugind +// base address: 0x0 +#define ixDP2_DP_DEBUG_ID 0x0000 +#define ixDP2_DP_DEBUG_K 0x00a2 +#define ixDP2_DP_DEBUG_L 0x00a3 +#define ixDP2_DP_DEBUG_M 0x00a4 +#define ixDP2_DP_DEBUG_G 0x00b4 +#define ixDP2_DP_DEBUG_O 0x00fb +#define ixDP2_DP_DEBUG_P 0x00fc +#define ixDP2_DP_DEBUG_Q 0x00fd +#define ixDP2_DP_DEBUG_R 0x00fe +#define ixDP2_DP_DEBUG_S 0x00ff + + +// addressBlock: dp2_dpfedebugind +// base address: 0x0 +#define ixDP2_DP_FE_DEBUG_ID 0x0000 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP2_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP2_DP_DEBUG_T 0x0090 +#define ixDP2_DP_DEBUG_U 0x0091 +#define ixDP2_DP_DEBUG_V 0x0092 +#define ixDP2_DP_DEBUG_W 0x0093 +#define ixDP2_DP_DEBUG_X 0x0094 +#define ixDP2_DP_DEBUG_Y 0x0095 +#define ixDP2_DP_DEBUG_Z 0x0096 +#define ixDP2_DP_DEBUG_1A 0x0097 +#define ixDP2_DP_DEBUG_1B 0x0098 +#define ixDP2_DP_DEBUG_I 0x00a0 +#define ixDP2_DP_DEBUG_J 0x00a1 +#define ixDP2_DP_DEBUG_N 0x00a2 +#define ixDP2_DP_DEBUG_H 0x00ac +#define ixDP2_DP_DEBUG_A 0x00ad +#define ixDP2_DP_DEBUG_B 0x00ae +#define ixDP2_DP_DEBUG_C 0x00af +#define ixDP2_DP_DEBUG_D 0x00b0 +#define ixDP2_DP_DEBUG_E 0x00b2 +#define ixDP2_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp2_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP2_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig2_digdebugind +// base address: 0x0 +#define ixDIG2_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig2_digfedebugind +// base address: 0x0 +#define ixDIG2_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG2_DIG_VPG_DEBUG0 0x000b +#define ixDIG2_DIG_VPG_DEBUG1 0x000c +#define ixDIG2_DIG_VPG_DEBUG2 0x000d +#define ixDIG2_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp3_dpdebugind +// base address: 0x0 +#define ixDP3_DP_DEBUG_ID 0x0000 +#define ixDP3_DP_DEBUG_K 0x00a2 +#define ixDP3_DP_DEBUG_L 0x00a3 +#define ixDP3_DP_DEBUG_M 0x00a4 +#define ixDP3_DP_DEBUG_G 0x00b4 +#define ixDP3_DP_DEBUG_O 0x00fb +#define ixDP3_DP_DEBUG_P 0x00fc +#define ixDP3_DP_DEBUG_Q 0x00fd +#define ixDP3_DP_DEBUG_R 0x00fe +#define ixDP3_DP_DEBUG_S 0x00ff + + +// addressBlock: dp3_dpfedebugind +// base address: 0x0 +#define ixDP3_DP_FE_DEBUG_ID 0x0000 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP3_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP3_DP_DEBUG_T 0x0090 +#define ixDP3_DP_DEBUG_U 0x0091 +#define ixDP3_DP_DEBUG_V 0x0092 +#define ixDP3_DP_DEBUG_W 0x0093 +#define ixDP3_DP_DEBUG_X 0x0094 +#define ixDP3_DP_DEBUG_Y 0x0095 +#define ixDP3_DP_DEBUG_Z 0x0096 +#define ixDP3_DP_DEBUG_1A 0x0097 +#define ixDP3_DP_DEBUG_1B 0x0098 +#define ixDP3_DP_DEBUG_I 0x00a0 +#define ixDP3_DP_DEBUG_J 0x00a1 +#define ixDP3_DP_DEBUG_N 0x00a2 +#define ixDP3_DP_DEBUG_H 0x00ac +#define ixDP3_DP_DEBUG_A 0x00ad +#define ixDP3_DP_DEBUG_B 0x00ae +#define ixDP3_DP_DEBUG_C 0x00af +#define ixDP3_DP_DEBUG_D 0x00b0 +#define ixDP3_DP_DEBUG_E 0x00b2 +#define ixDP3_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp3_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP3_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig3_digdebugind +// base address: 0x0 +#define ixDIG3_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig3_digfedebugind +// base address: 0x0 +#define ixDIG3_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG3_DIG_VPG_DEBUG0 0x000b +#define ixDIG3_DIG_VPG_DEBUG1 0x000c +#define ixDIG3_DIG_VPG_DEBUG2 0x000d +#define ixDIG3_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dp4_dpdebugind +// base address: 0x0 +#define ixDP4_DP_DEBUG_ID 0x0000 +#define ixDP4_DP_DEBUG_K 0x00a2 +#define ixDP4_DP_DEBUG_L 0x00a3 +#define ixDP4_DP_DEBUG_M 0x00a4 +#define ixDP4_DP_DEBUG_G 0x00b4 +#define ixDP4_DP_DEBUG_O 0x00fb +#define ixDP4_DP_DEBUG_P 0x00fc +#define ixDP4_DP_DEBUG_Q 0x00fd +#define ixDP4_DP_DEBUG_R 0x00fe +#define ixDP4_DP_DEBUG_S 0x00ff + + +// addressBlock: dp4_dpfedebugind +// base address: 0x0 +#define ixDP4_DP_FE_DEBUG_ID 0x0000 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_0 0x0001 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_1 0x0002 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_2 0x0003 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_3 0x0004 +#define ixDP4_DP_FE_SYMCLK_DEBUG_DATA_4 0x0005 +#define ixDP4_DP_DEBUG_T 0x0090 +#define ixDP4_DP_DEBUG_U 0x0091 +#define ixDP4_DP_DEBUG_V 0x0092 +#define ixDP4_DP_DEBUG_W 0x0093 +#define ixDP4_DP_DEBUG_X 0x0094 +#define ixDP4_DP_DEBUG_Y 0x0095 +#define ixDP4_DP_DEBUG_Z 0x0096 +#define ixDP4_DP_DEBUG_1A 0x0097 +#define ixDP4_DP_DEBUG_1B 0x0098 +#define ixDP4_DP_DEBUG_I 0x00a0 +#define ixDP4_DP_DEBUG_J 0x00a1 +#define ixDP4_DP_DEBUG_N 0x00a2 +#define ixDP4_DP_DEBUG_H 0x00ac +#define ixDP4_DP_DEBUG_A 0x00ad +#define ixDP4_DP_DEBUG_B 0x00ae +#define ixDP4_DP_DEBUG_C 0x00af +#define ixDP4_DP_DEBUG_D 0x00b0 +#define ixDP4_DP_DEBUG_E 0x00b2 +#define ixDP4_DP_DEBUG_F 0x00b3 + + +// addressBlock: dp4_dpfe_dprefclk_debugind +// base address: 0x0 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_ID 0x0000 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_0 0x0001 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_1 0x0002 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_2 0x0003 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_3 0x0004 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_4 0x0005 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_5 0x0006 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_6 0x0007 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_7 0x0008 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_8 0x0009 +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_9 0x000a +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_10 0x000b +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_11 0x000c +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_12 0x000d +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_13 0x000e +#define ixDP4_DP_FE_DPREFCLK_DEBUG_DATA_14 0x000f + + +// addressBlock: dig4_digdebugind +// base address: 0x0 +#define ixDIG4_DIG_BE_CLKGEN_DEBUG0 0x0010 + + +// addressBlock: dig4_digfedebugind +// base address: 0x0 +#define ixDIG4_DIG_FE_DEBUG_ID 0x0000 +#define ixDIG4_DIG_VPG_DEBUG0 0x000b +#define ixDIG4_DIG_VPG_DEBUG1 0x000c +#define ixDIG4_DIG_VPG_DEBUG2 0x000d +#define ixDIG4_DIG_VPG_DEBUG3 0x000e + + +// addressBlock: dio_misc_dio_miscdebugind +// base address: 0x0 +#define ixI2C_DEBUG_BUS 0x0002 +#define ixDIO_RBBMIF_DEBUG_0 0x0007 +#define ixDIO_RBBMIF_DEBUG_1 0x0008 +#define ixDIO_RBBMIF_DEBUG_2 0x0009 +#define ixDIO_RBBMIF_DEBUG_3 0x000a +#define ixDIGA_RBBMIF_DEBUG_0 0x000b +#define ixDIGA_RBBMIF_DEBUG_1 0x000c +#define ixDIGA_RBBMIF_DEBUG_2 0x000d +#define ixDIGA_RBBMIF_DEBUG_3 0x000e +#define ixDIGB_RBBMIF_DEBUG_0 0x000f +#define ixDIGB_RBBMIF_DEBUG_1 0x0010 +#define ixDIGB_RBBMIF_DEBUG_2 0x0011 +#define ixDIGB_RBBMIF_DEBUG_3 0x0012 +#define ixDIGC_RBBMIF_DEBUG_0 0x0013 +#define ixDIGC_RBBMIF_DEBUG_1 0x0014 +#define ixDIGC_RBBMIF_DEBUG_2 0x0015 +#define ixDIGC_RBBMIF_DEBUG_3 0x0016 +#define ixDIGD_RBBMIF_DEBUG_0 0x0017 +#define ixDIGD_RBBMIF_DEBUG_1 0x0018 +#define ixDIGD_RBBMIF_DEBUG_2 0x0019 +#define ixDIGD_RBBMIF_DEBUG_3 0x001a +#define ixDIGE_RBBMIF_DEBUG_0 0x001b +#define ixDIGE_RBBMIF_DEBUG_1 0x001c +#define ixDIGE_RBBMIF_DEBUG_2 0x001d +#define ixDIGE_RBBMIF_DEBUG_3 0x001e +#define ixDIGA_DME_DEBUG 0x0027 +#define ixDIGB_DME_DEBUG 0x0028 +#define ixDIGC_DME_DEBUG 0x0029 +#define ixDIGD_DME_DEBUG 0x002a +#define ixDIGE_DME_DEBUG 0x002b +#define ixDIGA_RESYNC_FIFO_DEBUG 0x0033 +#define ixDIGB_RESYNC_FIFO_DEBUG 0x0034 +#define ixDIGC_RESYNC_FIFO_DEBUG 0x0035 +#define ixDIGD_RESYNC_FIFO_DEBUG 0x0036 +#define ixDIGE_RESYNC_FIFO_DEBUG 0x0037 + + +// addressBlock: apg_apg_socclk_debugind +// base address: 0x0 +#define ixAPG_SOCCLK_DEBUG_ID 0x0000 +#define ixAPG_SOCCLK_DEBUG0 0x0001 + + +// addressBlock: apg_apg_encclk_debugind +// base address: 0x0 +#define ixAPG_ENCCLK_DEBUG_ID 0x0000 +#define ixAPG_ENCCLK_DEBUG0 0x0001 +#define ixAPG_ENCCLK_DEBUG1 0x0002 +#define ixAPG_ENCCLK_DEBUG2 0x0003 +#define ixAPG_ENCCLK_DEBUG3 0x0004 + + +// addressBlock: dcoh_top_dcoh_topdebugind +// base address: 0x0 +#define ixDCOH_TOP_DEBUG_ID 0x0000 + + +// addressBlock: dp_aux0_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX0_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX0_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX0_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux0_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX0_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX0_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX0_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX0_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX0_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX0_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX0_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX0_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX0_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux1_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX1_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX1_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX1_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux1_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX1_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX1_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX1_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX1_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX1_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX1_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX1_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX1_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX1_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux2_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX2_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX2_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX2_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux2_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX2_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX2_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX2_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX2_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX2_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX2_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX2_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX2_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX2_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux3_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX3_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX3_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX3_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux3_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX3_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX3_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX3_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX3_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX3_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX3_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX3_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX3_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX3_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: dp_aux4_auxdebugdispclkind +// base address: 0x0 +#define ixDP_AUX4_AUX_DEBUG_DISPCLK_ID 0x0000 +#define ixDP_AUX4_DP_AUX_DEBUG_H 0x0001 +#define ixDP_AUX4_DP_AUX_DEBUG_I 0x0002 + + +// addressBlock: dp_aux4_auxdebugrefclkind +// base address: 0x0 +#define ixDP_AUX4_AUX_DEBUG_REFCLK_ID 0x0000 +#define ixDP_AUX4_DP_AUX_DEBUG_A 0x0001 +#define ixDP_AUX4_DP_AUX_DEBUG_B 0x0002 +#define ixDP_AUX4_DP_AUX_DEBUG_C 0x0003 +#define ixDP_AUX4_DP_AUX_DEBUG_D 0x0004 +#define ixDP_AUX4_DP_AUX_DEBUG_E 0x0005 +#define ixDP_AUX4_DP_AUX_DEBUG_F 0x0006 +#define ixDP_AUX4_DP_AUX_DEBUG_G 0x0007 +#define ixDP_AUX4_DP_AUX_DEBUG_J 0x0008 + + +// addressBlock: hpd0_hpddebugind +// base address: 0x0 +#define ixHPD0_HPD_DEBUG_ID 0x0000 +#define ixHPD0_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd1_hpddebugind +// base address: 0x0 +#define ixHPD1_HPD_DEBUG_ID 0x0000 +#define ixHPD1_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd2_hpddebugind +// base address: 0x0 +#define ixHPD2_HPD_DEBUG_ID 0x0000 +#define ixHPD2_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd3_hpddebugind +// base address: 0x0 +#define ixHPD3_HPD_DEBUG_ID 0x0000 +#define ixHPD3_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpd4_hpddebugind +// base address: 0x0 +#define ixHPD4_HPD_DEBUG_ID 0x0000 +#define ixHPD4_HPD_DEBUG_0 0x0001 + + +// addressBlock: hpo_top_hpo_topdebugind +// base address: 0x0 +#define ixHPO_TOP_DEBUG_ID 0x0000 + + +// addressBlock: hdmi_link_enc0_linkencdebugind +// base address: 0x0 +#define ixHDMI_LINK_ENC_DEBUG_ID 0x0000 + + +// addressBlock: hdmi_frl_enc0_frldebugind +// base address: 0x0 +#define ixHDMI_FRL_ENC_DEBUG_ID 0x0000 + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_hdmistreamclk_debugind +// base address: 0x0 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID 0x0000 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0 0x0001 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1 0x0002 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2 0x0003 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3 0x0004 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4 0x0005 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5 0x0006 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6 0x0007 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7 0x0008 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8 0x0009 +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9 0x000a +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10 0x000b +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11 0x000c +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12 0x000d +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13 0x000e +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14 0x000f +#define ixHDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15 0x0010 + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_0 0x0001 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_1 0x0002 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_2 0x0003 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_3 0x0004 +#define ixHDMI_STREAM_ENC_DISPCLK_DEBUG_4 0x0005 + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc0_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc1_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc2_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dispclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_stream_enc3_dp_stream_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_symclk32_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID 0x0000 + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_dpstreamclk_debugind +// base address: 0x0 +#define ixDP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID 0x0000 + + +// addressBlock: dp_link_enc0_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym320_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: dp_link_enc1_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym321_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: dp_link_enc2_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym322_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: dp_link_enc3_dplinkencdebugind +// base address: 0x0 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID 0x0000 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0 0x0001 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1 0x0002 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2 0x0003 +#define ixDP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3 0x0004 + + +// addressBlock: dp_dphy_sym323_dpdphysym32debugind +// base address: 0x0 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID 0x0000 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0 0x0001 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1 0x0002 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2 0x0003 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3 0x0004 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4 0x0005 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5 0x0006 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6 0x0007 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7 0x0008 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8 0x0009 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9 0x000a +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10 0x000b +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11 0x000c +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12 0x000d +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13 0x000e +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14 0x000f +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15 0x0010 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16 0x0011 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17 0x0012 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18 0x0013 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19 0x0014 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20 0x0015 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21 0x0016 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22 0x0017 +#define ixDP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23 0x0018 + + +// addressBlock: azendpoint_sinkinfoind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 +#define ixSINK_DESCRIPTION0 0x0005 +#define ixSINK_DESCRIPTION1 0x0006 +#define ixSINK_DESCRIPTION2 0x0007 +#define ixSINK_DESCRIPTION3 0x0008 +#define ixSINK_DESCRIPTION4 0x0009 +#define ixSINK_DESCRIPTION5 0x000a +#define ixSINK_DESCRIPTION6 0x000b +#define ixSINK_DESCRIPTION7 0x000c +#define ixSINK_DESCRIPTION8 0x000d +#define ixSINK_DESCRIPTION9 0x000e +#define ixSINK_DESCRIPTION10 0x000f +#define ixSINK_DESCRIPTION11 0x0010 +#define ixSINK_DESCRIPTION12 0x0011 +#define ixSINK_DESCRIPTION13 0x0012 +#define ixSINK_DESCRIPTION14 0x0013 +#define ixSINK_DESCRIPTION15 0x0014 +#define ixSINK_DESCRIPTION16 0x0015 +#define ixSINK_DESCRIPTION17 0x0016 + + +// addressBlock: azf0controller_azinputcrc0resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azinputcrc1resultind +// base address: 0x0 +#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc0resultind +// base address: 0x0 +#define ixAZALIA_CRC0_CHANNEL0 0x0000 +#define ixAZALIA_CRC0_CHANNEL1 0x0001 +#define ixAZALIA_CRC0_CHANNEL2 0x0002 +#define ixAZALIA_CRC0_CHANNEL3 0x0003 +#define ixAZALIA_CRC0_CHANNEL4 0x0004 +#define ixAZALIA_CRC0_CHANNEL5 0x0005 +#define ixAZALIA_CRC0_CHANNEL6 0x0006 +#define ixAZALIA_CRC0_CHANNEL7 0x0007 + + +// addressBlock: azf0controller_azcrc1resultind +// base address: 0x0 +#define ixAZALIA_CRC1_CHANNEL0 0x0000 +#define ixAZALIA_CRC1_CHANNEL1 0x0001 +#define ixAZALIA_CRC1_CHANNEL2 0x0002 +#define ixAZALIA_CRC1_CHANNEL3 0x0003 +#define ixAZALIA_CRC1_CHANNEL4 0x0004 +#define ixAZALIA_CRC1_CHANNEL5 0x0005 +#define ixAZALIA_CRC1_CHANNEL6 0x0006 +#define ixAZALIA_CRC1_CHANNEL7 0x0007 + + +// addressBlock: azf0stream0_streamind +// base address: 0x0 +#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM0_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream1_streamind +// base address: 0x0 +#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM1_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream2_streamind +// base address: 0x0 +#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM2_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream3_streamind +// base address: 0x0 +#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM3_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream4_streamind +// base address: 0x0 +#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM4_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream5_streamind +// base address: 0x0 +#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM5_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream6_streamind +// base address: 0x0 +#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM6_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream7_streamind +// base address: 0x0 +#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM7_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream8_streamind +// base address: 0x0 +#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM8_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream9_streamind +// base address: 0x0 +#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM9_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream10_streamind +// base address: 0x0 +#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM10_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream11_streamind +// base address: 0x0 +#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM11_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream12_streamind +// base address: 0x0 +#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM12_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream13_streamind +// base address: 0x0 +#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM13_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream14_streamind +// base address: 0x0 +#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM14_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0stream15_streamind +// base address: 0x0 +#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 +#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 +#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 +#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 +#define ixAZF0STREAM15_AZALIA_STREAM_DEBUG 0x0005 + + +// addressBlock: azf0endpoint0_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint1_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint2_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint3_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint4_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint5_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint6_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0endpoint7_endpointind +// base address: 0x0 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA 0x0027 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 +#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 +#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d +#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e +#define ixAZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS 0x0070 + + +// addressBlock: azf0inputendpoint0_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint1_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint2_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint3_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint4_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint5_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint6_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: azf0inputendpoint7_inputendpointind +// base address: 0x0 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG 0x0000 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 +#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 + + +// addressBlock: dscc_dsccdebugind0 +// base address: 0x0 +#define ixDSCC_DEBUG_ID 0x0000 +#define ixDSCC_DEBUG_0 0x0001 +#define ixDSCC_DEBUG_1 0x0002 +#define ixDSCC_DEBUG_2 0x0003 +#define ixDSCC_DEBUG_3 0x0004 +#define ixDSCC_DEBUG_4 0x0005 +#define ixDSCC_DEBUG_5 0x0006 +#define ixDSCC_DEBUG_6 0x0007 +#define ixDSCC_DEBUG_7 0x0008 +#define ixDSCC_DEBUG_8 0x0009 +#define ixDSCC_DEBUG_9 0x000a +#define ixDSCC_DEBUG_10 0x000b +#define ixDSCC_DEBUG_11 0x000c +#define ixDSCC_DEBUG_12 0x000d +#define ixDSCC_DEBUG_13 0x000e +#define ixDSCC_DEBUG_14 0x000f +#define ixDSCC_DEBUG_15 0x0010 +#define ixDSCC_DEBUG_16 0x0011 +#define ixDSCC_DEBUG_17 0x0012 +#define ixDSCC_DEBUG_18 0x0013 +#define ixDSCC_DEBUG_19 0x0014 +#define ixDSCC_DEBUG_20 0x0015 +#define ixDSCC_DEBUG_21 0x0016 +#define ixDSCC_DEBUG_22 0x0017 +#define ixDSCC_DEBUG_23 0x0018 +#define ixDSCC_DEBUG_24 0x0019 +#define ixDSCC_DEBUG_25 0x001a +#define ixDSCC_DEBUG_26 0x001b +#define ixDSCC_DEBUG_27 0x001c +#define ixDSCC_DEBUG_28 0x001d + + +// addressBlock: dscc_dscc_dispclk_debugind0 +// base address: 0x0 +#define ixDSCC_DISPCLK_DEBUG_ID 0x0000 +#define ixDSCC_DISPCLK_DEBUG_0 0x0001 +#define ixDSCC_DISPCLK_DEBUG_1 0x0002 +#define ixDSCC_DISPCLK_DEBUG_2 0x0003 +#define ixDSCC_DISPCLK_DEBUG_3 0x0004 +#define ixDSCC_DISPCLK_DEBUG_4 0x0005 +#define ixDSCC_DISPCLK_DEBUG_5 0x0006 +#define ixDSCC_DISPCLK_DEBUG_6 0x0007 +#define ixDSCC_DISPCLK_DEBUG_7 0x0008 +#define ixDSCC_DISPCLK_DEBUG_8 0x0009 +#define ixDSCC_DISPCLK_DEBUG_9 0x000a +#define ixDSCC_DISPCLK_DEBUG_10 0x000b +#define ixDSCC_DISPCLK_DEBUG_11 0x000c +#define ixDSCC_DISPCLK_DEBUG_12 0x000d +#define ixDSCC_DISPCLK_DEBUG_13 0x000e +#define ixDSCC_DISPCLK_DEBUG_14 0x000f +#define ixDSCC_DISPCLK_DEBUG_15 0x0010 +#define ixDSCC_DISPCLK_DEBUG_16 0x0011 +#define ixDSCC_DISPCLK_DEBUG_17 0x0012 +#define ixDSCC_DISPCLK_DEBUG_18 0x0013 +#define ixDSCC_DISPCLK_DEBUG_19 0x0014 +#define ixDSCC_DISPCLK_DEBUG_20 0x0015 +#define ixDSCC_DISPCLK_DEBUG_21 0x0016 +#define ixDSCC_DISPCLK_DEBUG_22 0x0017 +#define ixDSCC_DISPCLK_DEBUG_23 0x0018 +#define ixDSCC_DISPCLK_DEBUG_24 0x0019 +#define ixDSCC_DISPCLK_DEBUG_25 0x001a +#define ixDSCC_DISPCLK_DEBUG_26 0x001b +#define ixDSCC_DISPCLK_DEBUG_27 0x001c +#define ixDSCC_DISPCLK_DEBUG_28 0x001d +#define ixDSCC_DISPCLK_DEBUG_29 0x001e +#define ixDSCC_DISPCLK_DEBUG_30 0x001f +#define ixDSCC_DISPCLK_DEBUG_31 0x0020 +#define ixDSCC_DISPCLK_DEBUG_32 0x0021 +#define ixDSCC_DISPCLK_DEBUG_33 0x0022 + + +// addressBlock: dsccif_dsccifdebugind +// base address: 0x0 +#define ixDSCCIF_DEBUG_ID 0x0000 +#define ixDSCCIF_DEBUG_0 0x0001 +#define ixDSCCIF_DEBUG_1 0x0002 + + +// addressBlock: dsc_top_dsc_topdebugind +// base address: 0x0 +#define ixDSC_TOP_DEBUG_ID 0x0000 +#define ixDSC_TOP_DEBUG_0 0x0001 +#define ixDSC_TOP_DEBUG_1 0x0002 +#define ixDSC_TOP_DEBUG_2 0x0003 + + +// addressBlock: dpia_port0_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT0_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT0_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port1_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT1_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT1_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port2_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT2_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT2_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port3_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT3_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT3_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port4_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT4_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT4_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port5_dpiaportdebugind +// base address: 0x0 +#define ixDPIA_PORT5_DPIA_PORT_DEBUG_ID 0x0000 +#define ixDPIA_PORT5_DPIA_PORT_DEBUG_BUS0 0x0001 + + +// addressBlock: dpia_port_ml0_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml1_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml2_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml3_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml4_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_ml5_dpiaportmldebugind +// base address: 0x0 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0 0x0001 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1 0x0002 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2 0x0003 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3 0x0004 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4 0x0005 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5 0x0006 +#define ixDPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6 0x0007 + + +// addressBlock: dpia_port_aux0_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux1_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux2_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux3_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux4_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_port_aux5_dpiaportauxdebugind +// base address: 0x0 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID 0x0000 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1 0x0001 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2 0x0002 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3 0x0003 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4 0x0004 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5 0x0005 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6 0x0006 +#define ixDPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7 0x0007 + + +// addressBlock: dpia_mu0_dpia_mu_debugind +// base address: 0x0 +#define ixDPIA_MU_DEBUG_ID 0x0000 + + +// addressBlock: azendpoint_descriptorind +// base address: 0x0 +#define ixAUDIO_DESCRIPTOR0 0x0001 +#define ixAUDIO_DESCRIPTOR1 0x0002 +#define ixAUDIO_DESCRIPTOR2 0x0003 +#define ixAUDIO_DESCRIPTOR3 0x0004 +#define ixAUDIO_DESCRIPTOR4 0x0005 +#define ixAUDIO_DESCRIPTOR5 0x0006 +#define ixAUDIO_DESCRIPTOR6 0x0007 +#define ixAUDIO_DESCRIPTOR7 0x0008 +#define ixAUDIO_DESCRIPTOR8 0x0009 +#define ixAUDIO_DESCRIPTOR9 0x000a +#define ixAUDIO_DESCRIPTOR10 0x000b +#define ixAUDIO_DESCRIPTOR11 0x000c +#define ixAUDIO_DESCRIPTOR12 0x000d +#define ixAUDIO_DESCRIPTOR13 0x000e + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x0 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x0 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 +#define regAZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x0 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 +#define regAZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 +#define regAZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x20 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 +#define regAZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x40 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 +#define regAZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x60 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 +#define regAZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x80 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 +#define regAZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0xa0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 +#define regAZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0xc0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 +#define regAZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0xe0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 +#define regAZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 + + +// addressBlock: dce_dc_dccg_dccg_dispdec +// base address: 0x0 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 +#define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 +#define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 +#define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 +#define regPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDP_DTO_DBUF_EN 0x0044 +#define regDP_DTO_DBUF_EN_BASE_IDX 1 +#define regDSCCLK3_DTO_PARAM 0x0045 +#define regDSCCLK3_DTO_PARAM_BASE_IDX 1 +#define regDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 +#define regDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL4 0x0049 +#define regDCCG_GATE_DISABLE_CNTL4_BASE_IDX 1 +#define regDPSTREAMCLK_CNTL 0x004a +#define regDPSTREAMCLK_CNTL_BASE_IDX 1 +#define regREFCLK_CGTT_BLK_CTRL_REG 0x004b +#define regREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c +#define regPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 +#define regDCCG_PERFMON_CNTL2 0x004e +#define regDCCG_PERFMON_CNTL2_BASE_IDX 1 +#define regDPIASYMCLK_CNTL 0x004f +#define regDPIASYMCLK_CNTL_BASE_IDX 1 +#define regDCCG_GLOBAL_FGCG_REP_CNTL 0x0050 +#define regDCCG_GLOBAL_FGCG_REP_CNTL_BASE_IDX 1 +#define regOTG_ADD_DROP_PIXEL_CNTL 0x0056 +#define regOTG_ADD_DROP_PIXEL_CNTL_BASE_IDX 1 +#define regDPREFCLK_CNTL 0x0058 +#define regDPREFCLK_CNTL_BASE_IDX 1 +#define regDCE_VERSION 0x005e +#define regDCE_VERSION_BASE_IDX 1 +#define regSYMCLK32_SE_CNTL 0x0065 +#define regSYMCLK32_SE_CNTL_BASE_IDX 1 +#define regSYMCLK32_LE_CNTL 0x0066 +#define regSYMCLK32_LE_CNTL_BASE_IDX 1 +#define regDTBCLK_P_CNTL 0x0068 +#define regDTBCLK_P_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL5 0x0069 +#define regDCCG_GATE_DISABLE_CNTL5_BASE_IDX 1 +#define regDSCCLK0_DTO_PARAM 0x006c +#define regDSCCLK0_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK1_DTO_PARAM 0x006d +#define regDSCCLK1_DTO_PARAM_BASE_IDX 1 +#define regDSCCLK2_DTO_PARAM 0x006e +#define regDSCCLK2_DTO_PARAM_BASE_IDX 1 +#define regOTG_PIXEL_RATE_DIV 0x006f +#define regOTG_PIXEL_RATE_DIV_BASE_IDX 1 +#define regMILLISECOND_TIME_BASE_DIV 0x0070 +#define regMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDISPCLK_FREQ_CHANGE_CNTL 0x0071 +#define regDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 +#define regDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 +#define regDCCG_PERFMON_CNTL 0x0073 +#define regDCCG_PERFMON_CNTL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL 0x0074 +#define regDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 +#define regDISPCLK_CGTT_BLK_CTRL_REG 0x0075 +#define regDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regSOCCLK_CGTT_BLK_CTRL_REG 0x0076 +#define regSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_CAC_STATUS 0x0077 +#define regDCCG_CAC_STATUS_BASE_IDX 1 +#define regMICROSECOND_TIME_BASE_DIV 0x007b +#define regMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL2 0x007c +#define regDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 +#define regSYMCLK_CGTT_BLK_CTRL_REG 0x007d +#define regSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDCCG_DISP_CNTL_REG 0x007f +#define regDCCG_DISP_CNTL_REG_BASE_IDX 1 +#define regOTG0_PIXEL_RATE_CNTL 0x0080 +#define regOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO0_PHASE 0x0081 +#define regDP_DTO0_PHASE_BASE_IDX 1 +#define regDP_DTO0_MODULO 0x0082 +#define regDP_DTO0_MODULO_BASE_IDX 1 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 +#define regOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG1_PIXEL_RATE_CNTL 0x0084 +#define regOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO1_PHASE 0x0085 +#define regDP_DTO1_PHASE_BASE_IDX 1 +#define regDP_DTO1_MODULO 0x0086 +#define regDP_DTO1_MODULO_BASE_IDX 1 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 +#define regOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG2_PIXEL_RATE_CNTL 0x0088 +#define regOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO2_PHASE 0x0089 +#define regDP_DTO2_PHASE_BASE_IDX 1 +#define regDP_DTO2_MODULO 0x008a +#define regDP_DTO2_MODULO_BASE_IDX 1 +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b +#define regOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regOTG3_PIXEL_RATE_CNTL 0x008c +#define regOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDP_DTO3_PHASE 0x008d +#define regDP_DTO3_PHASE_BASE_IDX 1 +#define regDP_DTO3_MODULO 0x008e +#define regDP_DTO3_MODULO_BASE_IDX 1 +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f +#define regOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 +#define regDPPCLK_CGTT_BLK_CTRL_REG 0x0098 +#define regDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 +#define regDPPCLK0_DTO_PARAM 0x0099 +#define regDPPCLK0_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK1_DTO_PARAM 0x009a +#define regDPPCLK1_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK2_DTO_PARAM 0x009b +#define regDPPCLK2_DTO_PARAM_BASE_IDX 1 +#define regDPPCLK3_DTO_PARAM 0x009c +#define regDPPCLK3_DTO_PARAM_BASE_IDX 1 +#define regDCCG_CAC_STATUS2 0x009f +#define regDCCG_CAC_STATUS2_BASE_IDX 1 +#define regSYMCLKA_CLOCK_ENABLE 0x00a0 +#define regSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKB_CLOCK_ENABLE 0x00a1 +#define regSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKC_CLOCK_ENABLE 0x00a2 +#define regSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKD_CLOCK_ENABLE 0x00a3 +#define regSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 +#define regSYMCLKE_CLOCK_ENABLE 0x00a4 +#define regSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 +#define regDCCG_SOFT_RESET 0x00a6 +#define regDCCG_SOFT_RESET_BASE_IDX 1 +#define regDSCCLK_DTO_CTRL 0x00a7 +#define regDSCCLK_DTO_CTRL_BASE_IDX 1 +#define regDPPCLK_CTRL 0x00a8 +#define regDPPCLK_CTRL_BASE_IDX 1 +#define regDCCG_GATE_DISABLE_CNTL6 0x00a9 +#define regDCCG_GATE_DISABLE_CNTL6_BASE_IDX 1 +#define regSYMCLK_PSP_CNTL 0x00aa +#define regSYMCLK_PSP_CNTL_BASE_IDX 1 +#define regDCCG_AUDIO_DTO_SOURCE 0x00ab +#define regDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_PHASE 0x00ac +#define regDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO0_MODULE 0x00ad +#define regDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_PHASE 0x00ae +#define regDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 +#define regDCCG_AUDIO_DTO1_MODULE 0x00af +#define regDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 +#define regDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 +#define regDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 +#define regDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 +#define regDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 +#define regDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 +#define regDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 +#define regDPPCLK_DTO_CTRL 0x00b6 +#define regDPPCLK_DTO_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_CTRL 0x00b8 +#define regDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 +#define regDCCG_VSYNC_CNT_INT_CTRL 0x00b9 +#define regDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 +#define regFORCE_SYMCLK_DISABLE 0x00ba +#define regFORCE_SYMCLK_DISABLE_BASE_IDX 1 +#define regDCCG_TEST_CLK_SEL 0x00be +#define regDCCG_TEST_CLK_SEL_BASE_IDX 1 +#define regHDMICHARCLK0_CLOCK_CNTL 0x004a +#define regHDMICHARCLK0_CLOCK_CNTL_BASE_IDX 2 +#define regPHYASYMCLK_CLOCK_CNTL 0x0052 +#define regPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYBSYMCLK_CLOCK_CNTL 0x0053 +#define regPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYCSYMCLK_CLOCK_CNTL 0x0054 +#define regPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYDSYMCLK_CLOCK_CNTL 0x0055 +#define regPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regPHYESYMCLK_CLOCK_CNTL 0x0056 +#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2 +#define regHDMISTREAMCLK_CNTL 0x0059 +#define regHDMISTREAMCLK_CNTL_BASE_IDX 2 +#define regDCCG_GATE_DISABLE_CNTL3 0x005a +#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX 2 +#define regHDMISTREAMCLK0_DTO_PARAM 0x005b +#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX 2 +#define regDPIACLK_810M_DTO_PHASE 0x0064 +#define regDPIACLK_810M_DTO_PHASE_BASE_IDX 2 +#define regDPIACLK_540M_DTO_PHASE 0x0065 +#define regDPIACLK_540M_DTO_PHASE_BASE_IDX 2 +#define regDPIACLK_DTO_CNTL 0x0066 +#define regDPIACLK_DTO_CNTL_BASE_IDX 2 +#define regDPIACLK_810M_DTO_MODULO 0x0068 +#define regDPIACLK_810M_DTO_MODULO_BASE_IDX 2 +#define regDPIACLK_540M_DTO_MODULO 0x0069 +#define regDPIACLK_540M_DTO_MODULO_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +// base address: 0x0 +#define regDENTIST_DISPCLK_CNTL 0x0064 +#define regDENTIST_DISPCLK_CNTL_BASE_IDX 1 + + +// addressBlock: azroot_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 +#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 +#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b +#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f + + +// addressBlock: azendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e +#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e +#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a +#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f +#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX 0x3774 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA 0x3775 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 +#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 +#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 +#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a +#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b +#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c +#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d +#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c +#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e + + +// addressBlock: azinputendpoint_f2codecind +// base address: 0x0 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a +#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d +#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 +#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +// base address: 0x0 +#define regDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 +#define regDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 +#define regDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON0_PERFCOUNTER_STATE 0x0002 +#define regDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CNTL 0x0003 +#define regDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CNTL2 0x0004 +#define regDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 +#define regDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 +#define regDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_HI 0x0007 +#define regDC_PERFMON0_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON0_PERFMON_LOW 0x0008 +#define regDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +// base address: 0x30 +#define regDC_PERFMON1_PERFCOUNTER_CNTL 0x000c +#define regDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d +#define regDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON1_PERFCOUNTER_STATE 0x000e +#define regDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CNTL 0x000f +#define regDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CNTL2 0x0010 +#define regDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 +#define regDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 +#define regDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_HI 0x0013 +#define regDC_PERFMON1_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON1_PERFMON_LOW 0x0014 +#define regDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +// base address: 0x0 +#define regDOMAIN0_PG_CONFIG 0x0080 +#define regDOMAIN0_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN0_PG_STATUS 0x0081 +#define regDOMAIN0_PG_STATUS_BASE_IDX 2 +#define regDOMAIN1_PG_CONFIG 0x0082 +#define regDOMAIN1_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN1_PG_STATUS 0x0083 +#define regDOMAIN1_PG_STATUS_BASE_IDX 2 +#define regDOMAIN2_PG_CONFIG 0x0084 +#define regDOMAIN2_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN2_PG_STATUS 0x0085 +#define regDOMAIN2_PG_STATUS_BASE_IDX 2 +#define regDOMAIN3_PG_CONFIG 0x0086 +#define regDOMAIN3_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN3_PG_STATUS 0x0087 +#define regDOMAIN3_PG_STATUS_BASE_IDX 2 +#define regDOMAIN16_PG_CONFIG 0x0089 +#define regDOMAIN16_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN16_PG_STATUS 0x008a +#define regDOMAIN16_PG_STATUS_BASE_IDX 2 +#define regDOMAIN17_PG_CONFIG 0x008b +#define regDOMAIN17_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN17_PG_STATUS 0x008c +#define regDOMAIN17_PG_STATUS_BASE_IDX 2 +#define regDOMAIN18_PG_CONFIG 0x008d +#define regDOMAIN18_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN18_PG_STATUS 0x008e +#define regDOMAIN18_PG_STATUS_BASE_IDX 2 +#define regDOMAIN19_PG_CONFIG 0x008f +#define regDOMAIN19_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN19_PG_STATUS 0x0090 +#define regDOMAIN19_PG_STATUS_BASE_IDX 2 +#define regDOMAIN22_PG_CONFIG 0x0092 +#define regDOMAIN22_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN22_PG_STATUS 0x0093 +#define regDOMAIN22_PG_STATUS_BASE_IDX 2 +#define regDOMAIN23_PG_CONFIG 0x0094 +#define regDOMAIN23_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN23_PG_STATUS 0x0095 +#define regDOMAIN23_PG_STATUS_BASE_IDX 2 +#define regDOMAIN24_PG_CONFIG 0x0096 +#define regDOMAIN24_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN24_PG_STATUS 0x0097 +#define regDOMAIN24_PG_STATUS_BASE_IDX 2 +#define regDOMAIN25_PG_CONFIG 0x0098 +#define regDOMAIN25_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN25_PG_STATUS 0x0099 +#define regDOMAIN25_PG_STATUS_BASE_IDX 2 +#define regDOMAIN26_PG_CONFIG 0x009a +#define regDOMAIN26_PG_CONFIG_BASE_IDX 2 +#define regDOMAIN26_PG_STATUS 0x009b +#define regDOMAIN26_PG_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS 0x009c +#define regDCPG_INTERRUPT_STATUS_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_2 0x009d +#define regDCPG_INTERRUPT_STATUS_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_STATUS_3 0x009e +#define regDCPG_INTERRUPT_STATUS_3_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_1 0x009f +#define regDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_2 0x00a0 +#define regDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 +#define regDCPG_INTERRUPT_CONTROL_3 0x00a1 +#define regDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2 +#define regDC_IP_REQUEST_CNTL 0x00a2 +#define regDC_IP_REQUEST_CNTL_BASE_IDX 2 +#define regLONO_MEM_PWR_REQ_CNTL 0x00a6 +#define regLONO_MEM_PWR_REQ_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +// base address: 0x2f8 +#define regDC_PERFMON2_PERFCOUNTER_CNTL 0x00be +#define regDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf +#define regDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 +#define regDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CNTL 0x00c1 +#define regDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CNTL2 0x00c2 +#define regDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 +#define regDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 +#define regDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_HI 0x00c5 +#define regDC_PERFMON2_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON2_PERFMON_LOW 0x00c6 +#define regDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +// base address: 0x0 +#define regCC_DC_PIPE_DIS 0x00ca +#define regCC_DC_PIPE_DIS_BASE_IDX 2 +#define regDMU_CLK_CNTL 0x00cb +#define regDMU_CLK_CNTL_BASE_IDX 2 +#define regDMCUB_SMU_INTERRUPT_CNTL 0x00cd +#define regDMCUB_SMU_INTERRUPT_CNTL_BASE_IDX 2 +#define regSMU_INTERRUPT_CONTROL 0x00ce +#define regSMU_INTERRUPT_CONTROL_BASE_IDX 2 +#define regZSC_CNTL 0x00cf +#define regZSC_CNTL_BASE_IDX 2 +#define regZSC_CNTL2 0x00d0 +#define regZSC_CNTL2_BASE_IDX 2 +#define regDMU_MISC_ALLOW_DS_FORCE 0x00d6 +#define regDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2 +#define regZSC_STATUS 0x00d7 +#define regZSC_STATUS_BASE_IDX 2 +#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG 0x00d8 +#define regDMU_DISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 +#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG 0x00d9 +#define regDMU_SOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 2 +#define regZPR_CLK_UNGATE_DELAY 0x00da +#define regZPR_CLK_UNGATE_DELAY_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_ihc_dispdec +// base address: 0x0 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 +#define regDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 +#define regDC_GPU_TIMER_READ 0x0128 +#define regDC_GPU_TIMER_READ_BASE_IDX 2 +#define regDC_GPU_TIMER_READ_CNTL 0x0129 +#define regDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS 0x012a +#define regDISP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE 0x012b +#define regDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE2 0x012c +#define regDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE3 0x012d +#define regDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE4 0x012e +#define regDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE5 0x012f +#define regDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 +#define regDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 +#define regDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 +#define regDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 +#define regDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 +#define regDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 +#define regDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 +#define regDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 +#define regDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 +#define regDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 +#define regDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE16 0x013a +#define regDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE17 0x013b +#define regDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE18 0x013c +#define regDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE19 0x013d +#define regDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE20 0x013e +#define regDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE21 0x013f +#define regDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 +#define regDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_VREADY 0x0141 +#define regDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP 0x0142 +#define regDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 +#define regDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 +#define regDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE23 0x0145 +#define regDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE24 0x0146 +#define regDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2 +#define regDISP_INTERRUPT_STATUS_CONTINUE25 0x0147 +#define regDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2 +#define regDCCG_INTERRUPT_DEST 0x0148 +#define regDCCG_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST 0x0149 +#define regDMU_INTERRUPT_DEST_BASE_IDX 2 +#define regDMU_INTERRUPT_DEST2 0x014a +#define regDMU_INTERRUPT_DEST2_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST 0x014b +#define regDCPG_INTERRUPT_DEST_BASE_IDX 2 +#define regDCPG_INTERRUPT_DEST2 0x014c +#define regDCPG_INTERRUPT_DEST2_BASE_IDX 2 +#define regMMHUBBUB_INTERRUPT_DEST 0x014d +#define regMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2 +#define regWB_INTERRUPT_DEST 0x014e +#define regWB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST 0x014f +#define regDCHUB_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150 +#define regDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regDCHUB_INTERRUPT_DEST2 0x0151 +#define regDCHUB_INTERRUPT_DEST2_BASE_IDX 2 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152 +#define regDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2 +#define regMPC_INTERRUPT_DEST 0x0153 +#define regMPC_INTERRUPT_DEST_BASE_IDX 2 +#define regOPP_INTERRUPT_DEST 0x0154 +#define regOPP_INTERRUPT_DEST_BASE_IDX 2 +#define regOPTC_INTERRUPT_DEST 0x0155 +#define regOPTC_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG0_INTERRUPT_DEST 0x0156 +#define regOTG0_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG1_INTERRUPT_DEST 0x0157 +#define regOTG1_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG2_INTERRUPT_DEST 0x0158 +#define regOTG2_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG3_INTERRUPT_DEST 0x0159 +#define regOTG3_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG4_INTERRUPT_DEST 0x015a +#define regOTG4_INTERRUPT_DEST_BASE_IDX 2 +#define regOTG5_INTERRUPT_DEST 0x015b +#define regOTG5_INTERRUPT_DEST_BASE_IDX 2 +#define regDIG_INTERRUPT_DEST 0x015c +#define regDIG_INTERRUPT_DEST_BASE_IDX 2 +#define regI2C_DDC_HPD_INTERRUPT_DEST 0x015d +#define regI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2 +#define regDIO_INTERRUPT_DEST 0x015f +#define regDIO_INTERRUPT_DEST_BASE_IDX 2 +#define regDCIO_INTERRUPT_DEST 0x0160 +#define regDCIO_INTERRUPT_DEST_BASE_IDX 2 +#define regHPD_INTERRUPT_DEST 0x0161 +#define regHPD_INTERRUPT_DEST_BASE_IDX 2 +#define regAZ_INTERRUPT_DEST 0x0162 +#define regAZ_INTERRUPT_DEST_BASE_IDX 2 +#define regAUX_INTERRUPT_DEST 0x0163 +#define regAUX_INTERRUPT_DEST_BASE_IDX 2 +#define regDSC_INTERRUPT_DEST 0x0164 +#define regDSC_INTERRUPT_DEST_BASE_IDX 2 +#define regHPO_INTERRUPT_DEST 0x0165 +#define regHPO_INTERRUPT_DEST_BASE_IDX 2 +#define regDPP_INTERRUPT_DEST 0x0166 +#define regDPP_INTERRUPT_DEST_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +// base address: 0x0 +#define regDMCUB_RBBMIF_SEC_CNTL 0x017a +#define regDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +// base address: 0x0 +#define regRBBMIF_TIMEOUT 0x017f +#define regRBBMIF_TIMEOUT_BASE_IDX 2 +#define regRBBMIF_STATUS 0x0180 +#define regRBBMIF_STATUS_BASE_IDX 2 +#define regRBBMIF_STATUS_2 0x0181 +#define regRBBMIF_STATUS_2_BASE_IDX 2 +#define regRBBMIF_INT_STATUS 0x0182 +#define regRBBMIF_INT_STATUS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS 0x0183 +#define regRBBMIF_TIMEOUT_DIS_BASE_IDX 2 +#define regRBBMIF_TIMEOUT_DIS_2 0x0184 +#define regRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2 +#define regRBBMIF_STATUS_FLAG 0x0185 +#define regRBBMIF_STATUS_FLAG_BASE_IDX 2 + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +// base address: 0x0 +#define regDMCUB_REGION0_OFFSET 0x018e +#define regDMCUB_REGION0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION0_OFFSET_HIGH 0x018f +#define regDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET 0x0190 +#define regDMCUB_REGION1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION1_OFFSET_HIGH 0x0191 +#define regDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET 0x0192 +#define regDMCUB_REGION2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION2_OFFSET_HIGH 0x0193 +#define regDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET 0x0196 +#define regDMCUB_REGION4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION4_OFFSET_HIGH 0x0197 +#define regDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET 0x0198 +#define regDMCUB_REGION5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION5_OFFSET_HIGH 0x0199 +#define regDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET 0x019a +#define regDMCUB_REGION6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION6_OFFSET_HIGH 0x019b +#define regDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET 0x019c +#define regDMCUB_REGION7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION7_OFFSET_HIGH 0x019d +#define regDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION0_TOP_ADDRESS 0x019e +#define regDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION1_TOP_ADDRESS 0x019f +#define regDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION2_TOP_ADDRESS 0x01a0 +#define regDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION4_TOP_ADDRESS 0x01a1 +#define regDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION5_TOP_ADDRESS 0x01a2 +#define regDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION6_TOP_ADDRESS 0x01a3 +#define regDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION7_TOP_ADDRESS 0x01a4 +#define regDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5 +#define regDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6 +#define regDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7 +#define regDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8 +#define regDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9 +#define regDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa +#define regDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab +#define regDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac +#define regDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad +#define regDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae +#define regDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af +#define regDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0 +#define regDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1 +#define regDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2 +#define regDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3 +#define regDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4 +#define regDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET 0x01b5 +#define regDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6 +#define regDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET 0x01b7 +#define regDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8 +#define regDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET 0x01b9 +#define regDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba +#define regDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET 0x01bb +#define regDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc +#define regDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET 0x01bd +#define regDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be +#define regDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET 0x01bf +#define regDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0 +#define regDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET 0x01c1 +#define regDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2 +#define regDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET 0x01c3 +#define regDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4 +#define regDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ENABLE 0x01c5 +#define regDMCUB_INTERRUPT_ENABLE_BASE_IDX 2 +#define regDMCUB_INTERRUPT_ACK 0x01c6 +#define regDMCUB_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INTERRUPT_STATUS 0x01c7 +#define regDMCUB_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_INTERRUPT_TYPE 0x01c8 +#define regDMCUB_INTERRUPT_TYPE_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_STATUS 0x01c9 +#define regDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_CTXID 0x01ca +#define regDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2 +#define regDMCUB_EXT_INTERRUPT_ACK 0x01cb +#define regDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2 +#define regDMCUB_INST_FETCH_FAULT_ADDR 0x01cc +#define regDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd +#define regDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_SEC_CNTL 0x01ce +#define regDMCUB_SEC_CNTL_BASE_IDX 2 +#define regDMCUB_MEM_CNTL 0x01cf +#define regDMCUB_MEM_CNTL_BASE_IDX 2 +#define regDMCUB_INBOX0_BASE_ADDRESS 0x01d0 +#define regDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX0_SIZE 0x01d1 +#define regDMCUB_INBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX0_WPTR 0x01d2 +#define regDMCUB_INBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX0_RPTR 0x01d3 +#define regDMCUB_INBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_BASE_ADDRESS 0x01d4 +#define regDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_INBOX1_SIZE 0x01d5 +#define regDMCUB_INBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_INBOX1_WPTR 0x01d6 +#define regDMCUB_INBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_INBOX1_RPTR 0x01d7 +#define regDMCUB_INBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8 +#define regDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX0_SIZE 0x01d9 +#define regDMCUB_OUTBOX0_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX0_WPTR 0x01da +#define regDMCUB_OUTBOX0_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX0_RPTR 0x01db +#define regDMCUB_OUTBOX0_RPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc +#define regDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2 +#define regDMCUB_OUTBOX1_SIZE 0x01dd +#define regDMCUB_OUTBOX1_SIZE_BASE_IDX 2 +#define regDMCUB_OUTBOX1_WPTR 0x01de +#define regDMCUB_OUTBOX1_WPTR_BASE_IDX 2 +#define regDMCUB_OUTBOX1_RPTR 0x01df +#define regDMCUB_OUTBOX1_RPTR_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER0 0x01e0 +#define regDMCUB_TIMER_TRIGGER0_BASE_IDX 2 +#define regDMCUB_TIMER_TRIGGER1 0x01e1 +#define regDMCUB_TIMER_TRIGGER1_BASE_IDX 2 +#define regDMCUB_TIMER_WINDOW 0x01e2 +#define regDMCUB_TIMER_WINDOW_BASE_IDX 2 +#define regDMCUB_SCRATCH0 0x01e3 +#define regDMCUB_SCRATCH0_BASE_IDX 2 +#define regDMCUB_SCRATCH1 0x01e4 +#define regDMCUB_SCRATCH1_BASE_IDX 2 +#define regDMCUB_SCRATCH2 0x01e5 +#define regDMCUB_SCRATCH2_BASE_IDX 2 +#define regDMCUB_SCRATCH3 0x01e6 +#define regDMCUB_SCRATCH3_BASE_IDX 2 +#define regDMCUB_SCRATCH4 0x01e7 +#define regDMCUB_SCRATCH4_BASE_IDX 2 +#define regDMCUB_SCRATCH5 0x01e8 +#define regDMCUB_SCRATCH5_BASE_IDX 2 +#define regDMCUB_SCRATCH6 0x01e9 +#define regDMCUB_SCRATCH6_BASE_IDX 2 +#define regDMCUB_SCRATCH7 0x01ea +#define regDMCUB_SCRATCH7_BASE_IDX 2 +#define regDMCUB_SCRATCH8 0x01eb +#define regDMCUB_SCRATCH8_BASE_IDX 2 +#define regDMCUB_SCRATCH9 0x01ec +#define regDMCUB_SCRATCH9_BASE_IDX 2 +#define regDMCUB_SCRATCH10 0x01ed +#define regDMCUB_SCRATCH10_BASE_IDX 2 +#define regDMCUB_SCRATCH11 0x01ee +#define regDMCUB_SCRATCH11_BASE_IDX 2 +#define regDMCUB_SCRATCH12 0x01ef +#define regDMCUB_SCRATCH12_BASE_IDX 2 +#define regDMCUB_SCRATCH13 0x01f0 +#define regDMCUB_SCRATCH13_BASE_IDX 2 +#define regDMCUB_SCRATCH14 0x01f1 +#define regDMCUB_SCRATCH14_BASE_IDX 2 +#define regDMCUB_SCRATCH15 0x01f2 +#define regDMCUB_SCRATCH15_BASE_IDX 2 +#define regDMCUB_SCRATCH16 0x01f3 +#define regDMCUB_SCRATCH16_BASE_IDX 2 +#define regDMCUB_SCRATCH17 0x01f4 +#define regDMCUB_SCRATCH17_BASE_IDX 2 +#define regDMCUB_SCRATCH18 0x01f5 +#define regDMCUB_SCRATCH18_BASE_IDX 2 +#define regDMCUB_CNTL 0x01f6 +#define regDMCUB_CNTL_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN0 0x01f7 +#define regDMCUB_GPINT_DATAIN0_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN1 0x01f8 +#define regDMCUB_GPINT_DATAIN1_BASE_IDX 2 +#define regDMCUB_GPINT_DATAOUT 0x01f9 +#define regDMCUB_GPINT_DATAOUT_BASE_IDX 2 +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa +#define regDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2 +#define regDMCUB_LS_WAKE_INT_ENABLE 0x01fb +#define regDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2 +#define regDMCUB_MEM_PWR_CNTL 0x01fc +#define regDMCUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regDMCUB_TIMER_CURRENT 0x01fd +#define regDMCUB_TIMER_CURRENT_BASE_IDX 2 +#define regDMCUB_PROC_ID 0x01ff +#define regDMCUB_PROC_ID_BASE_IDX 2 +#define regDMCUB_CNTL2 0x0200 +#define regDMCUB_CNTL2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN2 0x0215 +#define regDMCUB_GPINT_DATAIN2_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN3 0x0216 +#define regDMCUB_GPINT_DATAIN3_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN4 0x0217 +#define regDMCUB_GPINT_DATAIN4_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN5 0x0218 +#define regDMCUB_GPINT_DATAIN5_BASE_IDX 2 +#define regDMCUB_GPINT_DATAIN6 0x0219 +#define regDMCUB_GPINT_DATAIN6_BASE_IDX 2 +#define regDMCUB_REGION3_TMR_AXI_SPACE 0x021a +#define regDMCUB_REGION3_TMR_AXI_SPACE_BASE_IDX 2 +#define regDMCUB_SCRATCH19 0x021b +#define regDMCUB_SCRATCH19_BASE_IDX 2 +#define regDMCUB_SCRATCH20 0x021c +#define regDMCUB_SCRATCH20_BASE_IDX 2 +#define regDMCUB_SCRATCH21 0x021d +#define regDMCUB_SCRATCH21_BASE_IDX 2 +#define regDMCUB_SCRATCH22 0x021e +#define regDMCUB_SCRATCH22_BASE_IDX 2 +#define regDMCUB_SCRATCH23 0x021f +#define regDMCUB_SCRATCH23_BASE_IDX 2 +#define regHOST_INTERRUPT_CSR 0x0222 +#define regHOST_INTERRUPT_CSR_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_RDY 0x0223 +#define regDMCUB_REG_INBOX0_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG0 0x0224 +#define regDMCUB_REG_INBOX0_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG1 0x0225 +#define regDMCUB_REG_INBOX0_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG2 0x0226 +#define regDMCUB_REG_INBOX0_MSG2_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG3 0x0227 +#define regDMCUB_REG_INBOX0_MSG3_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG4 0x0228 +#define regDMCUB_REG_INBOX0_MSG4_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG5 0x0229 +#define regDMCUB_REG_INBOX0_MSG5_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG6 0x022a +#define regDMCUB_REG_INBOX0_MSG6_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG7 0x022b +#define regDMCUB_REG_INBOX0_MSG7_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG8 0x022c +#define regDMCUB_REG_INBOX0_MSG8_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG9 0x022d +#define regDMCUB_REG_INBOX0_MSG9_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG10 0x022e +#define regDMCUB_REG_INBOX0_MSG10_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG11 0x022f +#define regDMCUB_REG_INBOX0_MSG11_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG12 0x0230 +#define regDMCUB_REG_INBOX0_MSG12_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG13 0x0231 +#define regDMCUB_REG_INBOX0_MSG13_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_MSG14 0x0232 +#define regDMCUB_REG_INBOX0_MSG14_BASE_IDX 2 +#define regDMCUB_REG_INBOX0_RSP 0x0233 +#define regDMCUB_REG_INBOX0_RSP_BASE_IDX 2 +#define regDMCUB_REG_OUTBOX0_RDY 0x0234 +#define regDMCUB_REG_OUTBOX0_RDY_BASE_IDX 2 +#define regDMCUB_REG_OUTBOX0_MSG0 0x0235 +#define regDMCUB_REG_OUTBOX0_MSG0_BASE_IDX 2 +#define regDMCUB_REG_OUTBOX0_RSP 0x0236 +#define regDMCUB_REG_OUTBOX0_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_RDY 0x0237 +#define regDMCUB_REG_INBOX1_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_MSG0 0x0238 +#define regDMCUB_REG_INBOX1_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_MSG1 0x0239 +#define regDMCUB_REG_INBOX1_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_RSP 0x023a +#define regDMCUB_REG_INBOX1_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX1_INTERRUPT_CSR 0x023b +#define regDMCUB_REG_INBOX1_INTERRUPT_CSR_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_RDY 0x023c +#define regDMCUB_REG_INBOX2_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_MSG0 0x023d +#define regDMCUB_REG_INBOX2_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_MSG1 0x023e +#define regDMCUB_REG_INBOX2_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX2_RSP 0x023f +#define regDMCUB_REG_INBOX2_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_RDY 0x0240 +#define regDMCUB_REG_INBOX3_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_MSG0 0x0241 +#define regDMCUB_REG_INBOX3_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_MSG1 0x0242 +#define regDMCUB_REG_INBOX3_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX3_RSP 0x0243 +#define regDMCUB_REG_INBOX3_RSP_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_RDY 0x0244 +#define regDMCUB_REG_INBOX4_RDY_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_MSG0 0x0245 +#define regDMCUB_REG_INBOX4_MSG0_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_MSG1 0x0246 +#define regDMCUB_REG_INBOX4_MSG1_BASE_IDX 2 +#define regDMCUB_REG_INBOX4_RSP 0x0247 +#define regDMCUB_REG_INBOX4_RSP_BASE_IDX 2 +#define regDMCUB_IDLE_HYSTERESIS_CSR 0x0249 +#define regDMCUB_IDLE_HYSTERESIS_CSR_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +// base address: 0x0 +#define regMCIF_WB_BUFMGR_SW_CONTROL 0x0272 +#define regMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_STATUS 0x0274 +#define regMCIF_WB_BUFMGR_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_PITCH 0x0275 +#define regMCIF_WB_BUF_PITCH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS 0x0276 +#define regMCIF_WB_BUF_1_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_1_STATUS2 0x0277 +#define regMCIF_WB_BUF_1_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS 0x0278 +#define regMCIF_WB_BUF_2_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_2_STATUS2 0x0279 +#define regMCIF_WB_BUF_2_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS 0x027a +#define regMCIF_WB_BUF_3_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_3_STATUS2 0x027b +#define regMCIF_WB_BUF_3_STATUS2_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS 0x027c +#define regMCIF_WB_BUF_4_STATUS_BASE_IDX 2 +#define regMCIF_WB_BUF_4_STATUS2 0x027d +#define regMCIF_WB_BUF_4_STATUS2_BASE_IDX 2 +#define regMCIF_WB_ARBITRATION_CONTROL 0x027e +#define regMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SCLK_CHANGE 0x027f +#define regMCIF_WB_SCLK_CHANGE_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_INDEX 0x0280 +#define regMCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regMCIF_WB_TEST_DEBUG_DATA 0x0281 +#define regMCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y 0x0282 +#define regMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C 0x0284 +#define regMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y 0x0286 +#define regMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C 0x0288 +#define regMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y 0x028a +#define regMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C 0x028c +#define regMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y 0x028e +#define regMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C 0x0290 +#define regMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 +#define regMCIF_WB_BUFMGR_VCE_CONTROL 0x0292 +#define regMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_NB_PSTATE_CONTROL 0x0293 +#define regMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 +#define regMCIF_WB_CLOCK_GATER_CONTROL 0x0294 +#define regMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 +#define regMCIF_WB_SELF_REFRESH_CONTROL 0x0296 +#define regMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 +#define regMULTI_LEVEL_QOS_CTRL 0x0297 +#define regMULTI_LEVEL_QOS_CTRL_BASE_IDX 2 +#define regMCIF_WB_SECURITY_LEVEL 0x0298 +#define regMCIF_WB_SECURITY_LEVEL_BASE_IDX 2 +#define regMCIF_WB_BUF_LUMA_SIZE 0x0299 +#define regMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_CHROMA_SIZE 0x029a +#define regMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b +#define regMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c +#define regMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d +#define regMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e +#define regMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f +#define regMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0 +#define regMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1 +#define regMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2 +#define regMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2 +#define regMCIF_WB_BUF_1_RESOLUTION 0x02a3 +#define regMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_2_RESOLUTION 0x02a4 +#define regMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_3_RESOLUTION 0x02a5 +#define regMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_BUF_4_RESOLUTION 0x02a6 +#define regMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI 0x02a7 +#define regMCIF_WB_PSTATE_CHANGE_DURATION_VBI_BASE_IDX 2 +#define regMCIF_WB_VMID_CONTROL 0x02a8 +#define regMCIF_WB_VMID_CONTROL_BASE_IDX 2 +#define regMCIF_WB_MIN_TTO 0x02a9 +#define regMCIF_WB_MIN_TTO_BASE_IDX 2 +#define regMCIF_WB_TMZ 0x02b2 +#define regMCIF_WB_TMZ_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +// base address: 0x0 +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa +#define regMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 +#define regMCIF_WB_WATERMARK 0x02ab +#define regMCIF_WB_WATERMARK_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONFIG 0x02ac +#define regMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad +#define regMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae +#define regMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af +#define regMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_ADDR_REGION 0x02b0 +#define regMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2 +#define regMMHUBBUB_MIN_TTO 0x02b1 +#define regMMHUBBUB_MIN_TTO_BASE_IDX 2 +#define regMMHUBBUB_CTRL 0x0333 +#define regMMHUBBUB_CTRL_BASE_IDX 2 +#define regWBIF_SMU_WM_CONTROL 0x0334 +#define regWBIF_SMU_WM_CONTROL_BASE_IDX 2 +#define regWBIF0_MISC_CTRL 0x0335 +#define regWBIF0_MISC_CTRL_BASE_IDX 2 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0336 +#define regWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0337 +#define regWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_STATUS 0x033e +#define regMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_MEM_PWR_CNTL 0x033f +#define regMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 +#define regMMHUBBUB_CLOCK_CNTL 0x0340 +#define regMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regMMHUBBUB_SOFT_RESET 0x0341 +#define regMMHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDMU_IF_ERR_STATUS 0x0345 +#define regDMU_IF_ERR_STATUS_BASE_IDX 2 +#define regMMHUBBUB_CLIENT_UNIT_ID 0x0346 +#define regMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_SECURITY_CFG 0x0347 +#define regMMHUBBUB_WARMUP_SECURITY_CFG_BASE_IDX 2 +#define regMMHUBBUB_WARMUP_VMID_CONTROL 0x0348 +#define regMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0xd48 +#define regDC_PERFMON3_PERFCOUNTER_CNTL 0x0352 +#define regDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353 +#define regDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON3_PERFCOUNTER_STATE 0x0354 +#define regDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CNTL 0x0355 +#define regDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CNTL2 0x0356 +#define regDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357 +#define regDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358 +#define regDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_HI 0x0359 +#define regDC_PERFMON3_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON3_PERFMON_LOW 0x035a +#define regDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +// base address: 0x0 +#define regAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e +#define regAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM0_AZALIA_STREAM_DATA 0x035f +#define regAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +// base address: 0x8 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 +#define regAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 +#define regAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +// base address: 0x10 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 +#define regAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 +#define regAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +// base address: 0x18 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 +#define regAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 +#define regAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +// base address: 0x20 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 +#define regAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 +#define regAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +// base address: 0x28 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 +#define regAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 +#define regAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +// base address: 0x30 +#define regAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a +#define regAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM6_AZALIA_STREAM_DATA 0x036b +#define regAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +// base address: 0x38 +#define regAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c +#define regAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM7_AZALIA_STREAM_DATA 0x036d +#define regAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_misc_dispdec +// base address: 0x0 +#define regAZ_CLOCK_CNTL 0x0372 +#define regAZ_CLOCK_CNTL_BASE_IDX 2 +#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL 0x0373 +#define regAZ_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 2 +#define regAZ_STRAPS 0x0374 +#define regAZ_STRAPS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +// base address: 0xde8 +#define regDC_PERFMON4_PERFCOUNTER_CNTL 0x037a +#define regDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b +#define regDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON4_PERFCOUNTER_STATE 0x037c +#define regDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CNTL 0x037d +#define regDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CNTL2 0x037e +#define regDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f +#define regDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380 +#define regDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_HI 0x0381 +#define regDC_PERFMON4_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON4_PERFMON_LOW 0x0382 +#define regDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +// base address: 0x0 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 +#define regAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +// base address: 0x18 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d +#define regAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +// base address: 0x30 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 +#define regAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +// base address: 0x48 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 +#define regAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +// base address: 0x60 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f +#define regAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +// base address: 0x78 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 +#define regAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +// base address: 0x90 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab +#define regAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +// base address: 0xa8 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 +#define regAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +// base address: 0x0 +#define regAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 +#define regAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO 0x03c3 +#define regAZALIA_AUDIO_DTO_BASE_IDX 2 +#define regAZALIA_AUDIO_DTO_CONTROL 0x03c4 +#define regAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 +#define regAZALIA_SOCCLK_CONTROL 0x03c5 +#define regAZALIA_SOCCLK_CONTROL_BASE_IDX 2 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 +#define regAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 +#define regAZALIA_DATA_DMA_CONTROL 0x03c7 +#define regAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_BDL_DMA_CONTROL 0x03c8 +#define regAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_RIRB_AND_DP_CONTROL 0x03c9 +#define regAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 +#define regAZALIA_CORB_DMA_CONTROL 0x03ca +#define regAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 +#define regAZALIA_GLOBAL_CAPABILITIES 0x03d3 +#define regAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 +#define regAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 +#define regAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 +#define regAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL0 0x03d9 +#define regAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL1 0x03da +#define regAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL2 0x03db +#define regAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_CONTROL3 0x03dc +#define regAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC0_RESULT 0x03dd +#define regAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL0 0x03de +#define regAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL1 0x03df +#define regAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL2 0x03e0 +#define regAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_CONTROL3 0x03e1 +#define regAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_INPUT_CRC1_RESULT 0x03e2 +#define regAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL0 0x03e3 +#define regAZALIA_CRC0_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL1 0x03e4 +#define regAZALIA_CRC0_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL2 0x03e5 +#define regAZALIA_CRC0_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC0_CONTROL3 0x03e6 +#define regAZALIA_CRC0_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC0_RESULT 0x03e7 +#define regAZALIA_CRC0_RESULT_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL0 0x03e8 +#define regAZALIA_CRC1_CONTROL0_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL1 0x03e9 +#define regAZALIA_CRC1_CONTROL1_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL2 0x03ea +#define regAZALIA_CRC1_CONTROL2_BASE_IDX 2 +#define regAZALIA_CRC1_CONTROL3 0x03eb +#define regAZALIA_CRC1_CONTROL3_BASE_IDX 2 +#define regAZALIA_CRC1_RESULT 0x03ec +#define regAZALIA_CRC1_RESULT_BASE_IDX 2 +#define regAZALIA_MEM_PWR_CTRL 0x03ee +#define regAZALIA_MEM_PWR_CTRL_BASE_IDX 2 +#define regAZALIA_MEM_PWR_STATUS 0x03ef +#define regAZALIA_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0root_dispdec +// base address: 0x0 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 +#define regAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 +#define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 +#define regAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d +#define regAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 +#define regAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 +#define regCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 +#define regCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c +#define regREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d +#define regREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +// base address: 0x320 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 +#define regAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 +#define regAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +// base address: 0x328 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 +#define regAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 +#define regAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +// base address: 0x330 +#define regAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a +#define regAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM10_AZALIA_STREAM_DATA 0x042b +#define regAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +// base address: 0x338 +#define regAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c +#define regAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM11_AZALIA_STREAM_DATA 0x042d +#define regAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +// base address: 0x340 +#define regAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e +#define regAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM12_AZALIA_STREAM_DATA 0x042f +#define regAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +// base address: 0x348 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 +#define regAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 +#define regAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +// base address: 0x350 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 +#define regAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 +#define regAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +// base address: 0x358 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 +#define regAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 +#define regAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 +#define regAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +// base address: 0x0 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b +#define regAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +// base address: 0x10 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f +#define regAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +// base address: 0x20 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 +#define regAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +// base address: 0x30 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 +#define regAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +// base address: 0x40 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b +#define regAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +// base address: 0x50 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f +#define regAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +// base address: 0x60 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 +#define regAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +// base address: 0x70 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 +#define regAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +// base address: 0x0 +#define regDCHUBBUB_SDPIF_CFG0 0x046f +#define regDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG1 0x0470 +#define regDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_CFG2 0x0471 +#define regDCHUBBUB_SDPIF_CFG2_BASE_IDX 2 +#define regVM_REQUEST_PHYSICAL 0x0472 +#define regVM_REQUEST_PHYSICAL_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_0 0x0473 +#define regDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 +#define regDCHUBBUB_FORCE_IO_STATUS_1 0x0474 +#define regDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_BASE 0x0475 +#define regDCN_VM_FB_LOCATION_BASE_BASE_IDX 2 +#define regDCN_VM_FB_LOCATION_TOP 0x0476 +#define regDCN_VM_FB_LOCATION_TOP_BASE_IDX 2 +#define regDCN_VM_FB_OFFSET 0x0477 +#define regDCN_VM_FB_OFFSET_BASE_IDX 2 +#define regDCN_VM_AGP_BOT 0x0478 +#define regDCN_VM_AGP_BOT_BASE_IDX 2 +#define regDCN_VM_AGP_TOP 0x0479 +#define regDCN_VM_AGP_TOP_BASE_IDX 2 +#define regDCN_VM_AGP_BASE 0x047a +#define regDCN_VM_AGP_BASE_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_START 0x047b +#define regDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_END 0x047c +#define regDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2 +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x047d +#define regDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x047e +#define regDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC 0x047f +#define regDCHUBBUB_SDPIF_PIPE_NOALLOC_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x0480 +#define regDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL 0x0481 +#define regDCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL 0x0482 +#define regDCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL 0x0483 +#define regDCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL 0x0484 +#define regDCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL_BASE_IDX 2 +#define regSDPIF_REQUEST_RATE_LIMIT 0x0485 +#define regSDPIF_REQUEST_RATE_LIMIT_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x0486 +#define regDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x0487 +#define regDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +// base address: 0x0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04af +#define regDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04b0 +#define regDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 +#define regDCHUBBUB_CRC_CTRL 0x04b1 +#define regDCHUBBUB_CRC_CTRL_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_R 0x04b2 +#define regDCHUBBUB_CRC0_VAL_R_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_G 0x04b3 +#define regDCHUBBUB_CRC0_VAL_G_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_B 0x04b4 +#define regDCHUBBUB_CRC0_VAL_B_BASE_IDX 2 +#define regDCHUBBUB_CRC0_VAL_A 0x04b5 +#define regDCHUBBUB_CRC0_VAL_A_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_R 0x04b6 +#define regDCHUBBUB_CRC1_VAL_R_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_G 0x04b7 +#define regDCHUBBUB_CRC1_VAL_G_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_B 0x04b8 +#define regDCHUBBUB_CRC1_VAL_B_BASE_IDX 2 +#define regDCHUBBUB_CRC1_VAL_A 0x04b9 +#define regDCHUBBUB_CRC1_VAL_A_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT_CNTL 0x04ba +#define regDCHUBBUB_DCC_STAT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT0 0x04bb +#define regDCHUBBUB_DCC_STAT0_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT1 0x04bc +#define regDCHUBBUB_DCC_STAT1_BASE_IDX 2 +#define regDCHUBBUB_DCC_STAT2 0x04bd +#define regDCHUBBUB_DCC_STAT2_BASE_IDX 2 +#define regDCHUBBUB_COMPBUF_CTRL 0x04be +#define regDCHUBBUB_COMPBUF_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET0_CTRL 0x04bf +#define regDCHUBBUB_DET0_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET1_CTRL 0x04c0 +#define regDCHUBBUB_DET1_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET2_CTRL 0x04c1 +#define regDCHUBBUB_DET2_CTRL_BASE_IDX 2 +#define regDCHUBBUB_DET3_CTRL 0x04c2 +#define regDCHUBBUB_DET3_CTRL_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL 0x04c4 +#define regDCHUBBUB_MEM_PWR_MODE_CTRL_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_1 0x04c5 +#define regCOMPBUF_MEM_PWR_CTRL_1_BASE_IDX 2 +#define regCOMPBUF_MEM_PWR_CTRL_2 0x04c6 +#define regCOMPBUF_MEM_PWR_CTRL_2_BASE_IDX 2 +#define regDCHUBBUB_MEM_PWR_STATUS 0x04c7 +#define regDCHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 +#define regCOMPBUF_RESERVED_SPACE 0x04c8 +#define regCOMPBUF_RESERVED_SPACE_BASE_IDX 2 +#define regDCHUBBUB_DEBUG_CTRL_0 0x04c9 +#define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX 0x04cc +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA 0x04cd +#define regDCHUBBUB_RET_PATH_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +// base address: 0x0 +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x04ef +#define regDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 +#define regDCHUBBUB_ARB_SAT_LEVEL 0x04f0 +#define regDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 +#define regDCHUBBUB_ARB_QOS_FORCE 0x04f1 +#define regDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL 0x04f2 +#define regDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DRAM_HVM_STATE_CNTL 0x04f3 +#define regDCHUBBUB_ARB_DRAM_HVM_STATE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL 0x04f4 +#define regDCHUBBUB_ARB_USR_RETRAINING_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x04f5 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A 0x04f6 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x04f7 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x04f8 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A 0x04f9 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x04fa +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A 0x04fb +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A 0x04fc +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A 0x04fd +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x04fe +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x04ff +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x0500 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B 0x0501 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x0502 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0503 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B 0x0504 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0505 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B 0x0506 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B 0x0507 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B 0x0508 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0509 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x050a +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x050b +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C 0x050c +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x050d +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x050e +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C 0x050f +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0510 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C 0x0511 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C 0x0512 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C 0x0513 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0514 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0515 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0516 +#define regDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D 0x0517 +#define regDCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0518 +#define regDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x0519 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D 0x051a +#define regDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D 0x051c +#define regDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D 0x051d +#define regDCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D 0x051e +#define regDCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x051f +#define regDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0520 +#define regDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2 +#define regDCHUBBUB_ARB_HOSTVM_CNTL 0x0521 +#define regDCHUBBUB_ARB_HOSTVM_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x0522 +#define regDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_MALL_CNTL 0x0523 +#define regDCHUBBUB_ARB_MALL_CNTL_BASE_IDX 2 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE 0x0524 +#define regDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL 0x0525 +#define regDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_LSB 0x0526 +#define regSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK0_ADDRESS_MSB 0x0527 +#define regSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_LSB 0x0528 +#define regSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK1_ADDRESS_MSB 0x0529 +#define regSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_LSB 0x052a +#define regSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK2_ADDRESS_MSB 0x052b +#define regSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_LSB 0x052c +#define regSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 +#define regSURFACE_CHECK3_ADDRESS_MSB 0x052d +#define regSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 +#define regVTG0_CONTROL 0x052e +#define regVTG0_CONTROL_BASE_IDX 2 +#define regVTG1_CONTROL 0x052f +#define regVTG1_CONTROL_BASE_IDX 2 +#define regVTG2_CONTROL 0x0530 +#define regVTG2_CONTROL_BASE_IDX 2 +#define regVTG3_CONTROL 0x0531 +#define regVTG3_CONTROL_BASE_IDX 2 +#define regDCHUBBUB_SOFT_RESET 0x0532 +#define regDCHUBBUB_SOFT_RESET_BASE_IDX 2 +#define regDCHUBBUB_CLOCK_CNTL 0x0533 +#define regDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 +#define regDCFCLK_CNTL 0x0534 +#define regDCFCLK_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0535 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0536 +#define regDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 +#define regDCHUBBUB_VLINE_SNAPSHOT 0x0537 +#define regDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 +#define regDCHUBBUB_CTRL_STATUS 0x0538 +#define regDCHUBBUB_CTRL_STATUS_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053e +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053f +#define regDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x0540 +#define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2 +#define regFMON_CTRL 0x0541 +#define regFMON_CTRL_BASE_IDX 2 +#define regDCHUBBUB_TEST_DEBUG_INDEX 0x0542 +#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCHUBBUB_TEST_DEBUG_DATA 0x0543 +#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec +// base address: 0x1534 +#define regDC_PERFMON5_PERFCOUNTER_CNTL 0x054d +#define regDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e +#define regDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON5_PERFCOUNTER_STATE 0x054f +#define regDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CNTL 0x0550 +#define regDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CNTL2 0x0551 +#define regDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552 +#define regDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553 +#define regDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_HI 0x0554 +#define regDC_PERFMON5_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON5_PERFMON_LOW 0x0555 +#define regDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +// base address: 0x0 +#define regDCN_VM_CONTEXT0_CNTL 0x0559 +#define regDCN_VM_CONTEXT0_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b +#define regDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d +#define regDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f +#define regDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_CNTL 0x0560 +#define regDCN_VM_CONTEXT1_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566 +#define regDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_CNTL 0x0567 +#define regDCN_VM_CONTEXT2_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b +#define regDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d +#define regDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_CNTL 0x056e +#define regDCN_VM_CONTEXT3_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574 +#define regDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_CNTL 0x0575 +#define regDCN_VM_CONTEXT4_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b +#define regDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_CNTL 0x057c +#define regDCN_VM_CONTEXT5_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e +#define regDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582 +#define regDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_CNTL 0x0583 +#define regDCN_VM_CONTEXT6_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589 +#define regDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_CNTL 0x058a +#define regDCN_VM_CONTEXT7_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c +#define regDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e +#define regDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590 +#define regDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_CNTL 0x0591 +#define regDCN_VM_CONTEXT8_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597 +#define regDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_CNTL 0x0598 +#define regDCN_VM_CONTEXT9_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a +#define regDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c +#define regDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e +#define regDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_CNTL 0x059f +#define regDCN_VM_CONTEXT10_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5 +#define regDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_CNTL 0x05a6 +#define regDCN_VM_CONTEXT11_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa +#define regDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac +#define regDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_CNTL 0x05ad +#define regDCN_VM_CONTEXT12_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af +#define regDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3 +#define regDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_CNTL 0x05b4 +#define regDCN_VM_CONTEXT13_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba +#define regDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_CNTL 0x05bb +#define regDCN_VM_CONTEXT14_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd +#define regDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf +#define regDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1 +#define regDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_CNTL 0x05c2 +#define regDCN_VM_CONTEXT15_CNTL_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8 +#define regDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_MSB 0x05c9 +#define regDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_DEFAULT_ADDR_LSB 0x05ca +#define regDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define regDCN_VM_FAULT_CNTL 0x05cb +#define regDCN_VM_FAULT_CNTL_BASE_IDX 2 +#define regDCN_VM_FAULT_STATUS 0x05cc +#define regDCN_VM_FAULT_STATUS_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_MSB 0x05cd +#define regDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2 +#define regDCN_VM_FAULT_ADDR_LSB 0x05ce +#define regDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +// base address: 0x0 +#define regHUBP0_DCSURF_SURFACE_CONFIG 0x05e5 +#define regHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_ADDR_CONFIG 0x05e6 +#define regHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_TILING_CONFIG 0x05e7 +#define regHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb +#define regHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec +#define regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef +#define regHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0 +#define regHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2 +#define regHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP0_DCHUBP_CNTL 0x05f3 +#define regHUBP0_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP0_HUBP_CLK_CNTL 0x05f4 +#define regHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP0_DCHUBP_VMPG_CONFIG 0x05f5 +#define regHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_CONFIG 0x05f6 +#define regHUBP0_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP0_DCHUBP_MALL_SUB_VP 0x05f7 +#define regHUBP0_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG_DB 0x05f8 +#define regHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP0_HUBPREQ_DEBUG 0x05f9 +#define regHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP0_HUBP_DEBUG_CTRL 0x05fa +#define regHUBP0_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK 0x05fb +#define regHUBP0_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK 0x05fc +#define regHUBP0_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fd +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fe +#define regHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP0_HUBP_MALL_STATUS 0x05ff +#define regHUBP0_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +// base address: 0x0 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608 +#define regHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ0_VMID_SETTINGS_0 0x0609 +#define regHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d +#define regHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611 +#define regHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615 +#define regHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619 +#define regHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a +#define regHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b +#define regHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c +#define regHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x061f +#define regHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE 0x0620 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0621 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0622 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0623 +#define regHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0624 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0625 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0626 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0627 +#define regHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ0_DCN_EXPANSION_MODE 0x0628 +#define regHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ0_DCN_TTU_QOS_WM 0x0629 +#define regHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062a +#define regHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062b +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062c +#define regHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062d +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062e +#define regHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x062f +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0630 +#define regHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0631 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0632 +#define regHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0633 +#define regHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0634 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0635 +#define regHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0642 +#define regHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_0 0x0643 +#define regHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ0_BLANK_OFFSET_1 0x0644 +#define regHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ0_DST_DIMENSIONS 0x0645 +#define regHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ0_DST_AFTER_SCALER 0x0646 +#define regHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS 0x0647 +#define regHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_PREFETCH_SETTINGS_C 0x0648 +#define regHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_0 0x0649 +#define regHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_1 0x064a +#define regHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_2 0x064b +#define regHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_3 0x064c +#define regHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_4 0x064d +#define regHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_0 0x064e +#define regHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_1 0x064f +#define regHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_2 0x0650 +#define regHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_0 0x0651 +#define regHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_1 0x0652 +#define regHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_2 0x0653 +#define regHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_3 0x0654 +#define regHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_4 0x0655 +#define regHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_5 0x0656 +#define regHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_6 0x0657 +#define regHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_NOM_PARAMETERS_7 0x0658 +#define regHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE 0x0659 +#define regHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ0_PER_LINE_DELIVERY 0x065a +#define regHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ0_CURSOR_SETTINGS 0x065b +#define regHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065c +#define regHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065d +#define regHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065e +#define regHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x065f +#define regHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_5 0x0662 +#define regHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_VBLANK_PARAMETERS_6 0x0663 +#define regHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_3 0x0664 +#define regHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_4 0x0665 +#define regHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_5 0x0666 +#define regHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ0_FLIP_PARAMETERS_6 0x0667 +#define regHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ0_UCLK_PSTATE_FORCE 0x0668 +#define regHUBPREQ0_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0 0x0669 +#define regHUBPREQ0_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG1 0x066a +#define regHUBPREQ0_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ0_HUBPREQ_STATUS_REG2 0x066b +#define regHUBPREQ0_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +// base address: 0x0 +#define regHUBPRET0_HUBPRET_CONTROL 0x066c +#define regHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d +#define regHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e +#define regHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670 +#define regHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE0 0x0671 +#define regHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE1 0x0672 +#define regHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_INTERRUPT 0x0673 +#define regHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674 +#define regHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675 +#define regHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +// base address: 0x0 +#define regCURSOR0_0_CURSOR_CONTROL 0x0678 +#define regCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a +#define regCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_SIZE 0x067b +#define regCURSOR0_0_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_POSITION 0x067c +#define regCURSOR0_0_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_HOT_SPOT 0x067d +#define regCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e +#define regCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_DST_OFFSET 0x067f +#define regCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680 +#define regCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681 +#define regCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682 +#define regCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683 +#define regCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_CNTL 0x0684 +#define regCURSOR0_0_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_QOS_CNTL 0x0685 +#define regCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_STATUS 0x0686 +#define regCURSOR0_0_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_CNTL 0x0687 +#define regCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_0_DMDATA_SW_DATA 0x0688 +#define regCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_CONTROL 0x0689 +#define regCURSOR0_0_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW 0x068a +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH 0x068b +#define regCURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM 0x068c +#define regCURSOR0_0_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a74 +#define regDC_PERFMON6_PERFCOUNTER_CNTL 0x069d +#define regDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e +#define regDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON6_PERFCOUNTER_STATE 0x069f +#define regDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CNTL 0x06a0 +#define regDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CNTL2 0x06a1 +#define regDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2 +#define regDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3 +#define regDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_HI 0x06a4 +#define regDC_PERFMON6_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON6_PERFMON_LOW 0x06a5 +#define regDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +// base address: 0x370 +#define regHUBP1_DCSURF_SURFACE_CONFIG 0x06c1 +#define regHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_ADDR_CONFIG 0x06c2 +#define regHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_TILING_CONFIG 0x06c3 +#define regHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7 +#define regHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8 +#define regHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb +#define regHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc +#define regHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce +#define regHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP1_DCHUBP_CNTL 0x06cf +#define regHUBP1_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP1_HUBP_CLK_CNTL 0x06d0 +#define regHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP1_DCHUBP_VMPG_CONFIG 0x06d1 +#define regHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_CONFIG 0x06d2 +#define regHUBP1_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP1_DCHUBP_MALL_SUB_VP 0x06d3 +#define regHUBP1_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG_DB 0x06d4 +#define regHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP1_HUBPREQ_DEBUG 0x06d5 +#define regHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP1_HUBP_DEBUG_CTRL 0x06d6 +#define regHUBP1_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK 0x06d7 +#define regHUBP1_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK 0x06d8 +#define regHUBP1_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d9 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06da +#define regHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP1_HUBP_MALL_STATUS 0x06db +#define regHUBP1_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +// base address: 0x370 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4 +#define regHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ1_VMID_SETTINGS_0 0x06e5 +#define regHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9 +#define regHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed +#define regHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1 +#define regHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5 +#define regHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6 +#define regHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8 +#define regHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fb +#define regHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fc +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fd +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06fe +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x06ff +#define regHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0700 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0701 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0702 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0703 +#define regHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ1_DCN_EXPANSION_MODE 0x0704 +#define regHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ1_DCN_TTU_QOS_WM 0x0705 +#define regHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0706 +#define regHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0707 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0708 +#define regHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0709 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070a +#define regHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070b +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070c +#define regHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070d +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070e +#define regHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL 0x070f +#define regHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0710 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0711 +#define regHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071e +#define regHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_0 0x071f +#define regHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ1_BLANK_OFFSET_1 0x0720 +#define regHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ1_DST_DIMENSIONS 0x0721 +#define regHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ1_DST_AFTER_SCALER 0x0722 +#define regHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS 0x0723 +#define regHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_PREFETCH_SETTINGS_C 0x0724 +#define regHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_0 0x0725 +#define regHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_1 0x0726 +#define regHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_2 0x0727 +#define regHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_3 0x0728 +#define regHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_4 0x0729 +#define regHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_0 0x072a +#define regHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_1 0x072b +#define regHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_2 0x072c +#define regHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_0 0x072d +#define regHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_1 0x072e +#define regHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_2 0x072f +#define regHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_3 0x0730 +#define regHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_4 0x0731 +#define regHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_5 0x0732 +#define regHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_6 0x0733 +#define regHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_NOM_PARAMETERS_7 0x0734 +#define regHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0735 +#define regHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ1_PER_LINE_DELIVERY 0x0736 +#define regHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ1_CURSOR_SETTINGS 0x0737 +#define regHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0738 +#define regHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x0739 +#define regHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073a +#define regHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073b +#define regHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_5 0x073e +#define regHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_VBLANK_PARAMETERS_6 0x073f +#define regHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_3 0x0740 +#define regHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_4 0x0741 +#define regHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_5 0x0742 +#define regHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ1_FLIP_PARAMETERS_6 0x0743 +#define regHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ1_UCLK_PSTATE_FORCE 0x0744 +#define regHUBPREQ1_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0 0x0745 +#define regHUBPREQ1_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1 0x0746 +#define regHUBPREQ1_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2 0x0747 +#define regHUBPREQ1_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +// base address: 0x370 +#define regHUBPRET1_HUBPRET_CONTROL 0x0748 +#define regHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749 +#define regHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a +#define regHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c +#define regHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE0 0x074d +#define regHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE1 0x074e +#define regHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_INTERRUPT 0x074f +#define regHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750 +#define regHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751 +#define regHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +// base address: 0x370 +#define regCURSOR0_1_CURSOR_CONTROL 0x0754 +#define regCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756 +#define regCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_SIZE 0x0757 +#define regCURSOR0_1_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_POSITION 0x0758 +#define regCURSOR0_1_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_HOT_SPOT 0x0759 +#define regCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a +#define regCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_DST_OFFSET 0x075b +#define regCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c +#define regCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d +#define regCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e +#define regCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f +#define regCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_CNTL 0x0760 +#define regCURSOR0_1_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_QOS_CNTL 0x0761 +#define regCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_STATUS 0x0762 +#define regCURSOR0_1_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_CNTL 0x0763 +#define regCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_1_DMDATA_SW_DATA 0x0764 +#define regCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_CONTROL 0x0765 +#define regCURSOR0_1_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW 0x0766 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH 0x0767 +#define regCURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM 0x0768 +#define regCURSOR0_1_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x1de4 +#define regDC_PERFMON7_PERFCOUNTER_CNTL 0x0779 +#define regDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a +#define regDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON7_PERFCOUNTER_STATE 0x077b +#define regDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CNTL 0x077c +#define regDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CNTL2 0x077d +#define regDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e +#define regDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f +#define regDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_HI 0x0780 +#define regDC_PERFMON7_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON7_PERFMON_LOW 0x0781 +#define regDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +// base address: 0x6e0 +#define regHUBP2_DCSURF_SURFACE_CONFIG 0x079d +#define regHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_ADDR_CONFIG 0x079e +#define regHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_TILING_CONFIG 0x079f +#define regHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3 +#define regHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4 +#define regHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7 +#define regHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8 +#define regHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa +#define regHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP2_DCHUBP_CNTL 0x07ab +#define regHUBP2_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP2_HUBP_CLK_CNTL 0x07ac +#define regHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP2_DCHUBP_VMPG_CONFIG 0x07ad +#define regHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_CONFIG 0x07ae +#define regHUBP2_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP2_DCHUBP_MALL_SUB_VP 0x07af +#define regHUBP2_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG_DB 0x07b0 +#define regHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP2_HUBPREQ_DEBUG 0x07b1 +#define regHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP2_HUBP_DEBUG_CTRL 0x07b2 +#define regHUBP2_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK 0x07b3 +#define regHUBP2_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK 0x07b4 +#define regHUBP2_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b5 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b6 +#define regHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP2_HUBP_MALL_STATUS 0x07b7 +#define regHUBP2_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +// base address: 0x6e0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0 +#define regHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ2_VMID_SETTINGS_0 0x07c1 +#define regHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5 +#define regHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9 +#define regHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd +#define regHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1 +#define regHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2 +#define regHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4 +#define regHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d7 +#define regHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d8 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07d9 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07da +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07db +#define regHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dc +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07dd +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07de +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07df +#define regHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ2_DCN_EXPANSION_MODE 0x07e0 +#define regHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ2_DCN_TTU_QOS_WM 0x07e1 +#define regHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e2 +#define regHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e3 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e4 +#define regHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e5 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e6 +#define regHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e7 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e8 +#define regHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07e9 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ea +#define regHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07eb +#define regHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ec +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ed +#define regHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fa +#define regHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_0 0x07fb +#define regHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ2_BLANK_OFFSET_1 0x07fc +#define regHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ2_DST_DIMENSIONS 0x07fd +#define regHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ2_DST_AFTER_SCALER 0x07fe +#define regHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS 0x07ff +#define regHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_PREFETCH_SETTINGS_C 0x0800 +#define regHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_0 0x0801 +#define regHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_1 0x0802 +#define regHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_2 0x0803 +#define regHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_3 0x0804 +#define regHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_4 0x0805 +#define regHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_0 0x0806 +#define regHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_1 0x0807 +#define regHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_2 0x0808 +#define regHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_0 0x0809 +#define regHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_1 0x080a +#define regHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_2 0x080b +#define regHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_3 0x080c +#define regHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_4 0x080d +#define regHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_5 0x080e +#define regHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_6 0x080f +#define regHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_NOM_PARAMETERS_7 0x0810 +#define regHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0811 +#define regHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ2_PER_LINE_DELIVERY 0x0812 +#define regHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ2_CURSOR_SETTINGS 0x0813 +#define regHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0814 +#define regHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0815 +#define regHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0816 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0817 +#define regHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_5 0x081a +#define regHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_VBLANK_PARAMETERS_6 0x081b +#define regHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_3 0x081c +#define regHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_4 0x081d +#define regHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_5 0x081e +#define regHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ2_FLIP_PARAMETERS_6 0x081f +#define regHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ2_UCLK_PSTATE_FORCE 0x0820 +#define regHUBPREQ2_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0 0x0821 +#define regHUBPREQ2_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1 0x0822 +#define regHUBPREQ2_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2 0x0823 +#define regHUBPREQ2_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +// base address: 0x6e0 +#define regHUBPRET2_HUBPRET_CONTROL 0x0824 +#define regHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825 +#define regHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826 +#define regHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828 +#define regHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE0 0x0829 +#define regHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE1 0x082a +#define regHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_INTERRUPT 0x082b +#define regHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c +#define regHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d +#define regHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +// base address: 0x6e0 +#define regCURSOR0_2_CURSOR_CONTROL 0x0830 +#define regCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832 +#define regCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_SIZE 0x0833 +#define regCURSOR0_2_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_POSITION 0x0834 +#define regCURSOR0_2_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_HOT_SPOT 0x0835 +#define regCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836 +#define regCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_DST_OFFSET 0x0837 +#define regCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838 +#define regCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839 +#define regCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a +#define regCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b +#define regCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_CNTL 0x083c +#define regCURSOR0_2_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_QOS_CNTL 0x083d +#define regCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_STATUS 0x083e +#define regCURSOR0_2_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_CNTL 0x083f +#define regCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_2_DMDATA_SW_DATA 0x0840 +#define regCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_CONTROL 0x0841 +#define regCURSOR0_2_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW 0x0842 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH 0x0843 +#define regCURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM 0x0844 +#define regCURSOR0_2_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x2154 +#define regDC_PERFMON8_PERFCOUNTER_CNTL 0x0855 +#define regDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856 +#define regDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON8_PERFCOUNTER_STATE 0x0857 +#define regDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CNTL 0x0858 +#define regDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CNTL2 0x0859 +#define regDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a +#define regDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b +#define regDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_HI 0x085c +#define regDC_PERFMON8_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON8_PERFMON_LOW 0x085d +#define regDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +// base address: 0xa50 +#define regHUBP3_DCSURF_SURFACE_CONFIG 0x0879 +#define regHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_ADDR_CONFIG 0x087a +#define regHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_TILING_CONFIG 0x087b +#define regHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f +#define regHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880 +#define regHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883 +#define regHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884 +#define regHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886 +#define regHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 +#define regHUBP3_DCHUBP_CNTL 0x0887 +#define regHUBP3_DCHUBP_CNTL_BASE_IDX 2 +#define regHUBP3_HUBP_CLK_CNTL 0x0888 +#define regHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 +#define regHUBP3_DCHUBP_VMPG_CONFIG 0x0889 +#define regHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_CONFIG 0x088a +#define regHUBP3_DCHUBP_MALL_CONFIG_BASE_IDX 2 +#define regHUBP3_DCHUBP_MALL_SUB_VP 0x088b +#define regHUBP3_DCHUBP_MALL_SUB_VP_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG_DB 0x088c +#define regHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 +#define regHUBP3_HUBPREQ_DEBUG 0x088d +#define regHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 +#define regHUBP3_HUBP_DEBUG_CTRL 0x088e +#define regHUBP3_HUBP_DEBUG_CTRL_BASE_IDX 2 +#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK 0x088f +#define regHUBP3_HUBP_DEBUG_MUX_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK 0x0890 +#define regHUBP3_HUBP_DEBUG_MUX_DPPCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0891 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0892 +#define regHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 +#define regHUBP3_HUBP_MALL_STATUS 0x0893 +#define regHUBP3_HUBP_MALL_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +// base address: 0xa50 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c +#define regHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 +#define regHUBPREQ3_VMID_SETTINGS_0 0x089d +#define regHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1 +#define regHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5 +#define regHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9 +#define regHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad +#define regHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae +#define regHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af +#define regHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0 +#define regHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b3 +#define regHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b4 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b5 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b6 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b7 +#define regHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b8 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08b9 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08ba +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bb +#define regHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 +#define regHUBPREQ3_DCN_EXPANSION_MODE 0x08bc +#define regHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 +#define regHUBPREQ3_DCN_TTU_QOS_WM 0x08bd +#define regHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08be +#define regHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08bf +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c0 +#define regHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c1 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c2 +#define regHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c3 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c4 +#define regHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c5 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c6 +#define regHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c7 +#define regHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c8 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08c9 +#define regHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d6 +#define regHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_0 0x08d7 +#define regHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 +#define regHUBPREQ3_BLANK_OFFSET_1 0x08d8 +#define regHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 +#define regHUBPREQ3_DST_DIMENSIONS 0x08d9 +#define regHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 +#define regHUBPREQ3_DST_AFTER_SCALER 0x08da +#define regHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS 0x08db +#define regHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_PREFETCH_SETTINGS_C 0x08dc +#define regHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_0 0x08dd +#define regHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_1 0x08de +#define regHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_2 0x08df +#define regHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_3 0x08e0 +#define regHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_4 0x08e1 +#define regHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_0 0x08e2 +#define regHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_1 0x08e3 +#define regHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_2 0x08e4 +#define regHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_0 0x08e5 +#define regHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_1 0x08e6 +#define regHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_2 0x08e7 +#define regHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_3 0x08e8 +#define regHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_4 0x08e9 +#define regHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_5 0x08ea +#define regHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_6 0x08eb +#define regHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_NOM_PARAMETERS_7 0x08ec +#define regHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ed +#define regHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 +#define regHUBPREQ3_PER_LINE_DELIVERY 0x08ee +#define regHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 +#define regHUBPREQ3_CURSOR_SETTINGS 0x08ef +#define regHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f0 +#define regHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f1 +#define regHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f3 +#define regHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_5 0x08f6 +#define regHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_VBLANK_PARAMETERS_6 0x08f7 +#define regHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_3 0x08f8 +#define regHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_4 0x08f9 +#define regHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_5 0x08fa +#define regHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2 +#define regHUBPREQ3_FLIP_PARAMETERS_6 0x08fb +#define regHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2 +#define regHUBPREQ3_UCLK_PSTATE_FORCE 0x08fc +#define regHUBPREQ3_UCLK_PSTATE_FORCE_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG0 0x08fd +#define regHUBPREQ3_HUBPREQ_STATUS_REG0_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG1 0x08fe +#define regHUBPREQ3_HUBPREQ_STATUS_REG1_BASE_IDX 2 +#define regHUBPREQ3_HUBPREQ_STATUS_REG2 0x08ff +#define regHUBPREQ3_HUBPREQ_STATUS_REG2_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +// base address: 0xa50 +#define regHUBPRET3_HUBPRET_CONTROL 0x0900 +#define regHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901 +#define regHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902 +#define regHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904 +#define regHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE0 0x0905 +#define regHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE1 0x0906 +#define regHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_INTERRUPT 0x0907 +#define regHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908 +#define regHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909 +#define regHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +// base address: 0xa50 +#define regCURSOR0_3_CURSOR_CONTROL 0x090c +#define regCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e +#define regCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_SIZE 0x090f +#define regCURSOR0_3_CURSOR_SIZE_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_POSITION 0x0910 +#define regCURSOR0_3_CURSOR_POSITION_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_HOT_SPOT 0x0911 +#define regCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912 +#define regCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_DST_OFFSET 0x0913 +#define regCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914 +#define regCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915 +#define regCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916 +#define regCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917 +#define regCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_CNTL 0x0918 +#define regCURSOR0_3_DMDATA_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_QOS_CNTL 0x0919 +#define regCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_STATUS 0x091a +#define regCURSOR0_3_DMDATA_STATUS_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_CNTL 0x091b +#define regCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2 +#define regCURSOR0_3_DMDATA_SW_DATA 0x091c +#define regCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_CONTROL 0x091d +#define regCURSOR0_3_HUBP_3DLUT_CONTROL_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW 0x091e +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_LOW_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH 0x091f +#define regCURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH_BASE_IDX 2 +#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM 0x0920 +#define regCURSOR0_3_HUBP_3DLUT_DLG_PARAM_BASE_IDX 2 + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +// base address: 0x24c4 +#define regDC_PERFMON9_PERFCOUNTER_CNTL 0x0931 +#define regDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932 +#define regDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON9_PERFCOUNTER_STATE 0x0933 +#define regDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CNTL 0x0934 +#define regDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CNTL2 0x0935 +#define regDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936 +#define regDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937 +#define regDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_HI 0x0938 +#define regDC_PERFMON9_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON9_PERFMON_LOW 0x0939 +#define regDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +// base address: 0x0 +#define regDPP_TOP0_DPP_CONTROL 0x0cc5 +#define regDPP_TOP0_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP0_DPP_SOFT_RESET 0x0cc6 +#define regDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_R 0x0cc7 +#define regDPP_TOP0_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_G 0x0cc8 +#define regDPP_TOP0_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_B 0x0cc9 +#define regDPP_TOP0_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_VAL_A 0x0cca +#define regDPP_TOP0_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP0_DPP_CRC_CTRL 0x0ccb +#define regDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP0_HOST_READ_CONTROL 0x0ccc +#define regDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +// base address: 0x0 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0cd1 +#define regCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_FORMAT_CONTROL 0x0cd2 +#define regCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd3 +#define regCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd4 +#define regCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd5 +#define regCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd6 +#define regCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd7 +#define regCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd8 +#define regCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd9 +#define regCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cda +#define regCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_RED 0x0cdb +#define regCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_GREEN 0x0cdc +#define regCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdd +#define regCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT01 0x0cdf +#define regCNVC_CFG0_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG0_ALPHA_2BIT_LUT23 0x0ce0 +#define regCNVC_CFG0_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEALPHA 0x0ce1 +#define regCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_MODE 0x0ce2 +#define regCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C11_C12 0x0ce3 +#define regCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C13_C14 0x0ce4 +#define regCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C21_C22 0x0ce5 +#define regCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C23_C24 0x0ce6 +#define regCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C31_C32 0x0ce7 +#define regCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_C33_C34 0x0ce8 +#define regCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce9 +#define regCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C13_C14 0x0cea +#define regCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ceb +#define regCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C23_C24 0x0cec +#define regCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C31_C32 0x0ced +#define regCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG0_PRE_CSC_B_C33_C34 0x0cee +#define regCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG0_CNVC_COEF_FORMAT 0x0cef +#define regCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG0_PRE_DEGAM 0x0cf0 +#define regCNVC_CFG0_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG0_PRE_REALPHA 0x0cf1 +#define regCNVC_CFG0_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_cur_dispdec +// base address: 0x0 +#define regCM_CUR0_CURSOR0_CONTROL 0x0cf4 +#define regCM_CUR0_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_COLOR0 0x0cf5 +#define regCM_CUR0_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_COLOR1 0x0cf6 +#define regCM_CUR0_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y 0x0cf7 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0cf8 +#define regCM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_MODE 0x0cf9 +#define regCM_CUR0_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C11_C12_A 0x0cfa +#define regCM_CUR0_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C13_C14_A 0x0cfb +#define regCM_CUR0_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C21_C22_A 0x0cfc +#define regCM_CUR0_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C23_C24_A 0x0cfd +#define regCM_CUR0_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C31_C32_A 0x0cfe +#define regCM_CUR0_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C33_C34_A 0x0cff +#define regCM_CUR0_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C11_C12_B 0x0d00 +#define regCM_CUR0_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C13_C14_B 0x0d01 +#define regCM_CUR0_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C21_C22_B 0x0d02 +#define regCM_CUR0_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C23_C24_B 0x0d03 +#define regCM_CUR0_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C31_C32_B 0x0d04 +#define regCM_CUR0_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR0_CUR0_MATRIX_C33_C34_B 0x0d05 +#define regCM_CUR0_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +// base address: 0x0 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0d08 +#define regDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA 0x0d09 +#define regDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL0_SCL_MODE 0x0d0a +#define regDSCL0_SCL_MODE_BASE_IDX 2 +#define regDSCL0_SCL_TAP_CONTROL 0x0d0b +#define regDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_CONTROL 0x0d0c +#define regDSCL0_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL0_DSCL_2TAP_CONTROL 0x0d0d +#define regDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0d0e +#define regDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d0f +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT 0x0d10 +#define regDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d11 +#define regDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d12 +#define regDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d13 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT 0x0d14 +#define regDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d15 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d16 +#define regDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_C 0x0d17 +#define regDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d18 +#define regDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL0_SCL_BLACK_COLOR 0x0d19 +#define regDSCL0_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL0_DSCL_UPDATE 0x0d1a +#define regDSCL0_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL0_DSCL_AUTOCAL 0x0d1b +#define regDSCL0_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d1c +#define regDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d1d +#define regDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL0_OTG_H_BLANK 0x0d1e +#define regDSCL0_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL0_OTG_V_BLANK 0x0d1f +#define regDSCL0_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL0_RECOUT_START 0x0d20 +#define regDSCL0_RECOUT_START_BASE_IDX 2 +#define regDSCL0_RECOUT_SIZE 0x0d21 +#define regDSCL0_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL0_MPC_SIZE 0x0d22 +#define regDSCL0_MPC_SIZE_BASE_IDX 2 +#define regDSCL0_LB_DATA_FORMAT 0x0d23 +#define regDSCL0_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL0_LB_MEMORY_CTRL 0x0d24 +#define regDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL0_LB_V_COUNTER 0x0d25 +#define regDSCL0_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_CTRL 0x0d26 +#define regDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_MEM_PWR_STATUS 0x0d27 +#define regDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL0_OBUF_CONTROL 0x0d28 +#define regDSCL0_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL0_OBUF_MEM_PWR_CTRL 0x0d29 +#define regDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_MODE 0x0d2a +#define regDSCL0_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_MODE 0x0d2b +#define regDSCL0_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL0_DSCL_SC_MODE 0x0d2c +#define regDSCL0_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL0_DSCL_SC_MATRIX_C0C1 0x0d2d +#define regDSCL0_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL0_DSCL_SC_MATRIX_C2C3 0x0d2e +#define regDSCL0_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0d2f +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0d30 +#define regDSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0d31 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0d32 +#define regDSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0d33 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0d34 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0d35 +#define regDSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_RINGEST_FORCE 0x0d36 +#define regDSCL0_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF_CNTL 0x0d37 +#define regDSCL0_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0d38 +#define regDSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF_CNTL 0x0d39 +#define regDSCL0_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0d3a +#define regDSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0 0x0d3b +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1 0x0d3c +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2 0x0d3d +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3 0x0d3e +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4 0x0d3f +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5 0x0d40 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6 0x0d41 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7 0x0d42 +#define regDSCL0_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0 0x0d43 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1 0x0d44 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2 0x0d45 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3 0x0d46 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4 0x0d47 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5 0x0d48 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6 0x0d49 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7 0x0d4a +#define regDSCL0_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0 0x0d4b +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1 0x0d4c +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2 0x0d4d +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3 0x0d4e +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4 0x0d4f +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5 0x0d50 +#define regDSCL0_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0 0x0d51 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1 0x0d52 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2 0x0d53 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3 0x0d54 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4 0x0d55 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5 0x0d56 +#define regDSCL0_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_ISHARP_MODE 0x0d57 +#define regDSCL0_ISHARP_MODE_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_CTRL 0x0d58 +#define regDSCL0_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_INDEX 0x0d59 +#define regDSCL0_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_DATA 0x0d5a +#define regDSCL0_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP 0x0d5b +#define regDSCL0_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL0_ISHARP_NOISEDET_THRESHOLD 0x0d5c +#define regDSCL0_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL0_ISHARP_NOISE_GAIN_PWL 0x0d5d +#define regDSCL0_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG0 0x0d5e +#define regDSCL0_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG1 0x0d5f +#define regDSCL0_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG2 0x0d60 +#define regDSCL0_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG3 0x0d61 +#define regDSCL0_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG4 0x0d62 +#define regDSCL0_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL0_ISHARP_LBA_PWL_SEG5 0x0d63 +#define regDSCL0_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0d64 +#define regDSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +// base address: 0x0 +#define regCM0_CM_CONTROL 0x0d69 +#define regCM0_CM_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_CONTROL 0x0d6a +#define regCM0_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C11_C12 0x0d6b +#define regCM0_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C13_C14 0x0d6c +#define regCM0_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C21_C22 0x0d6d +#define regCM0_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C23_C24 0x0d6e +#define regCM0_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C31_C32 0x0d6f +#define regCM0_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_C33_C34 0x0d70 +#define regCM0_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C11_C12 0x0d71 +#define regCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C13_C14 0x0d72 +#define regCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C21_C22 0x0d73 +#define regCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C23_C24 0x0d74 +#define regCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C31_C32 0x0d75 +#define regCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM0_CM_POST_CSC_B_C33_C34 0x0d76 +#define regCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM0_CM_BIAS_CR_R 0x0d77 +#define regCM0_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM0_CM_BIAS_Y_G_CB_B 0x0d78 +#define regCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_CONTROL 0x0d79 +#define regCM0_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_INDEX 0x0d7a +#define regCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_DATA 0x0d7b +#define regCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM0_CM_GAMCOR_LUT_CONTROL 0x0d7c +#define regCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d7d +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d7e +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d7f +#define regCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d80 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d81 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d82 +#define regCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d83 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d84 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d85 +#define regCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d86 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d87 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d88 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d89 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d8a +#define regCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d8b +#define regCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d8c +#define regCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d8d +#define regCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d8e +#define regCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d8f +#define regCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d90 +#define regCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d91 +#define regCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d92 +#define regCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d93 +#define regCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d94 +#define regCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d95 +#define regCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d96 +#define regCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d97 +#define regCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d98 +#define regCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d99 +#define regCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d9a +#define regCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d9b +#define regCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d9c +#define regCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d9d +#define regCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d9e +#define regCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d9f +#define regCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0da0 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0da1 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0da2 +#define regCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0da3 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0da4 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0da5 +#define regCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0da6 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0da7 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0da8 +#define regCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0da9 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0daa +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0dab +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0dac +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0dad +#define regCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0dae +#define regCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0daf +#define regCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0db0 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0db1 +#define regCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0db2 +#define regCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0db3 +#define regCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0db4 +#define regCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0db5 +#define regCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0db6 +#define regCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0db7 +#define regCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0db8 +#define regCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0db9 +#define regCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0dba +#define regCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0dbb +#define regCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0dbc +#define regCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0dbd +#define regCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0dbe +#define regCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0dbf +#define regCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0dc0 +#define regCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0dc1 +#define regCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0dc2 +#define regCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM0_CM_HDR_MULT_COEF 0x0dc3 +#define regCM0_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_CTRL 0x0dc4 +#define regCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM0_CM_MEM_PWR_STATUS 0x0dc5 +#define regCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM0_CM_DEALPHA 0x0dc7 +#define regCM0_CM_DEALPHA_BASE_IDX 2 +#define regCM0_CM_COEF_FORMAT 0x0dc8 +#define regCM0_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM0_CM_TEST_DEBUG_INDEX 0x0dc9 +#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM0_CM_TEST_DEBUG_DATA 0x0dca +#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM0_CM_HIST_CNTL 0x0dcb +#define regCM0_CM_HIST_CNTL_BASE_IDX 2 +#define regCM0_CM_HIST_SCALE_SRC1 0x0dcc +#define regCM0_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM0_CM_HIST_COEFA_SRC2 0x0dcd +#define regCM0_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_COEFB_SRC2 0x0dce +#define regCM0_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_COEFC_SRC2 0x0dcf +#define regCM0_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_SCALE_SRC3 0x0dd0 +#define regCM0_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM0_CM_HIST_BIAS_SRC1 0x0dd1 +#define regCM0_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM0_CM_HIST_BIAS_SRC2 0x0dd2 +#define regCM0_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM0_CM_HIST_BIAS_SRC3 0x0dd3 +#define regCM0_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM0_CM_HIST_LOCK 0x0dd4 +#define regCM0_CM_HIST_LOCK_BASE_IDX 2 +#define regCM0_CM_HIST_INDEX 0x0dd5 +#define regCM0_CM_HIST_INDEX_BASE_IDX 2 +#define regCM0_CM_HIST_DATA 0x0dd6 +#define regCM0_CM_HIST_DATA_BASE_IDX 2 +#define regCM0_CM_HIST_STATUS 0x0dd7 +#define regCM0_CM_HIST_STATUS_BASE_IDX 2 +#define regCM0_CM_HIST_INT_CONTROL 0x0dd8 +#define regCM0_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3890 +#define regDC_PERFMON10_PERFCOUNTER_CNTL 0x0e24 +#define regDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON10_PERFCOUNTER_CNTL2 0x0e25 +#define regDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON10_PERFCOUNTER_STATE 0x0e26 +#define regDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CNTL 0x0e27 +#define regDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CNTL2 0x0e28 +#define regDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0e29 +#define regDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_CVALUE_LOW 0x0e2a +#define regDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_HI 0x0e2b +#define regDC_PERFMON10_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON10_PERFMON_LOW 0x0e2c +#define regDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +// base address: 0x5ac +#define regDPP_TOP1_DPP_CONTROL 0x0e30 +#define regDPP_TOP1_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP1_DPP_SOFT_RESET 0x0e31 +#define regDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_R 0x0e32 +#define regDPP_TOP1_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_G 0x0e33 +#define regDPP_TOP1_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_B 0x0e34 +#define regDPP_TOP1_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_VAL_A 0x0e35 +#define regDPP_TOP1_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP1_DPP_CRC_CTRL 0x0e36 +#define regDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP1_HOST_READ_CONTROL 0x0e37 +#define regDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +// base address: 0x5ac +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3c +#define regCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_FORMAT_CONTROL 0x0e3d +#define regCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3e +#define regCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3f +#define regCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_BIAS_B 0x0e40 +#define regCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_R 0x0e41 +#define regCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_G 0x0e42 +#define regCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG1_FCNV_FP_SCALE_B 0x0e43 +#define regCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e44 +#define regCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e45 +#define regCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_RED 0x0e46 +#define regCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_GREEN 0x0e47 +#define regCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG1_COLOR_KEYER_BLUE 0x0e48 +#define regCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT01 0x0e4a +#define regCNVC_CFG1_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG1_ALPHA_2BIT_LUT23 0x0e4b +#define regCNVC_CFG1_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEALPHA 0x0e4c +#define regCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_MODE 0x0e4d +#define regCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C11_C12 0x0e4e +#define regCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C13_C14 0x0e4f +#define regCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C21_C22 0x0e50 +#define regCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C23_C24 0x0e51 +#define regCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C31_C32 0x0e52 +#define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_C33_C34 0x0e53 +#define regCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e54 +#define regCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e55 +#define regCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e56 +#define regCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e57 +#define regCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e58 +#define regCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e59 +#define regCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG1_CNVC_COEF_FORMAT 0x0e5a +#define regCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG1_PRE_DEGAM 0x0e5b +#define regCNVC_CFG1_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG1_PRE_REALPHA 0x0e5c +#define regCNVC_CFG1_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_cur_dispdec +// base address: 0x5ac +#define regCM_CUR1_CURSOR0_CONTROL 0x0e5f +#define regCM_CUR1_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_COLOR0 0x0e60 +#define regCM_CUR1_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_COLOR1 0x0e61 +#define regCM_CUR1_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y 0x0e62 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0e63 +#define regCM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_MODE 0x0e64 +#define regCM_CUR1_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C11_C12_A 0x0e65 +#define regCM_CUR1_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C13_C14_A 0x0e66 +#define regCM_CUR1_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C21_C22_A 0x0e67 +#define regCM_CUR1_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C23_C24_A 0x0e68 +#define regCM_CUR1_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C31_C32_A 0x0e69 +#define regCM_CUR1_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C33_C34_A 0x0e6a +#define regCM_CUR1_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C11_C12_B 0x0e6b +#define regCM_CUR1_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C13_C14_B 0x0e6c +#define regCM_CUR1_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C21_C22_B 0x0e6d +#define regCM_CUR1_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C23_C24_B 0x0e6e +#define regCM_CUR1_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C31_C32_B 0x0e6f +#define regCM_CUR1_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR1_CUR0_MATRIX_C33_C34_B 0x0e70 +#define regCM_CUR1_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +// base address: 0x5ac +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e73 +#define regDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e74 +#define regDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL1_SCL_MODE 0x0e75 +#define regDSCL1_SCL_MODE_BASE_IDX 2 +#define regDSCL1_SCL_TAP_CONTROL 0x0e76 +#define regDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_CONTROL 0x0e77 +#define regDSCL1_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL1_DSCL_2TAP_CONTROL 0x0e78 +#define regDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e79 +#define regDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e7a +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT 0x0e7b +#define regDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e7c +#define regDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e7d +#define regDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e7e +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT 0x0e7f +#define regDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e80 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e81 +#define regDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_C 0x0e82 +#define regDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e83 +#define regDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL1_SCL_BLACK_COLOR 0x0e84 +#define regDSCL1_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL1_DSCL_UPDATE 0x0e85 +#define regDSCL1_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL1_DSCL_AUTOCAL 0x0e86 +#define regDSCL1_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e87 +#define regDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e88 +#define regDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL1_OTG_H_BLANK 0x0e89 +#define regDSCL1_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL1_OTG_V_BLANK 0x0e8a +#define regDSCL1_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL1_RECOUT_START 0x0e8b +#define regDSCL1_RECOUT_START_BASE_IDX 2 +#define regDSCL1_RECOUT_SIZE 0x0e8c +#define regDSCL1_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL1_MPC_SIZE 0x0e8d +#define regDSCL1_MPC_SIZE_BASE_IDX 2 +#define regDSCL1_LB_DATA_FORMAT 0x0e8e +#define regDSCL1_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL1_LB_MEMORY_CTRL 0x0e8f +#define regDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL1_LB_V_COUNTER 0x0e90 +#define regDSCL1_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_CTRL 0x0e91 +#define regDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_MEM_PWR_STATUS 0x0e92 +#define regDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL1_OBUF_CONTROL 0x0e93 +#define regDSCL1_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL1_OBUF_MEM_PWR_CTRL 0x0e94 +#define regDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_MODE 0x0e95 +#define regDSCL1_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_MODE 0x0e96 +#define regDSCL1_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL1_DSCL_SC_MODE 0x0e97 +#define regDSCL1_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL1_DSCL_SC_MATRIX_C0C1 0x0e98 +#define regDSCL1_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL1_DSCL_SC_MATRIX_C2C3 0x0e99 +#define regDSCL1_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x0e9a +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x0e9b +#define regDSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x0e9c +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x0e9d +#define regDSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x0e9e +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x0e9f +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x0ea0 +#define regDSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_RINGEST_FORCE 0x0ea1 +#define regDSCL1_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF_CNTL 0x0ea2 +#define regDSCL1_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x0ea3 +#define regDSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF_CNTL 0x0ea4 +#define regDSCL1_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x0ea5 +#define regDSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0 0x0ea6 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1 0x0ea7 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2 0x0ea8 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3 0x0ea9 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4 0x0eaa +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5 0x0eab +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6 0x0eac +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7 0x0ead +#define regDSCL1_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0 0x0eae +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1 0x0eaf +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2 0x0eb0 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3 0x0eb1 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4 0x0eb2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5 0x0eb3 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6 0x0eb4 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7 0x0eb5 +#define regDSCL1_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0 0x0eb6 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1 0x0eb7 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2 0x0eb8 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3 0x0eb9 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4 0x0eba +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5 0x0ebb +#define regDSCL1_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0 0x0ebc +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1 0x0ebd +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2 0x0ebe +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3 0x0ebf +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4 0x0ec0 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5 0x0ec1 +#define regDSCL1_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_ISHARP_MODE 0x0ec2 +#define regDSCL1_ISHARP_MODE_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_CTRL 0x0ec3 +#define regDSCL1_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_INDEX 0x0ec4 +#define regDSCL1_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_DATA 0x0ec5 +#define regDSCL1_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP 0x0ec6 +#define regDSCL1_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL1_ISHARP_NOISEDET_THRESHOLD 0x0ec7 +#define regDSCL1_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL1_ISHARP_NOISE_GAIN_PWL 0x0ec8 +#define regDSCL1_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG0 0x0ec9 +#define regDSCL1_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG1 0x0eca +#define regDSCL1_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG2 0x0ecb +#define regDSCL1_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG3 0x0ecc +#define regDSCL1_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG4 0x0ecd +#define regDSCL1_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL1_ISHARP_LBA_PWL_SEG5 0x0ece +#define regDSCL1_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x0ecf +#define regDSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +// base address: 0x5ac +#define regCM1_CM_CONTROL 0x0ed4 +#define regCM1_CM_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_CONTROL 0x0ed5 +#define regCM1_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C11_C12 0x0ed6 +#define regCM1_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C13_C14 0x0ed7 +#define regCM1_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C21_C22 0x0ed8 +#define regCM1_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C23_C24 0x0ed9 +#define regCM1_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C31_C32 0x0eda +#define regCM1_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_C33_C34 0x0edb +#define regCM1_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C11_C12 0x0edc +#define regCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C13_C14 0x0edd +#define regCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C21_C22 0x0ede +#define regCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C23_C24 0x0edf +#define regCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C31_C32 0x0ee0 +#define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM1_CM_POST_CSC_B_C33_C34 0x0ee1 +#define regCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM1_CM_BIAS_CR_R 0x0ee2 +#define regCM1_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM1_CM_BIAS_Y_G_CB_B 0x0ee3 +#define regCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_CONTROL 0x0ee4 +#define regCM1_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_INDEX 0x0ee5 +#define regCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_DATA 0x0ee6 +#define regCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM1_CM_GAMCOR_LUT_CONTROL 0x0ee7 +#define regCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0ee8 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ee9 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eea +#define regCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eeb +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eec +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eed +#define regCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eee +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eef +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0ef0 +#define regCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0ef1 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0ef2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0ef3 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0ef4 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0ef5 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0ef6 +#define regCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ef7 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ef8 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ef9 +#define regCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0efa +#define regCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0efb +#define regCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0efc +#define regCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0efd +#define regCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0efe +#define regCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0eff +#define regCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0f00 +#define regCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0f01 +#define regCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0f02 +#define regCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0f03 +#define regCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0f04 +#define regCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0f05 +#define regCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0f06 +#define regCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0f07 +#define regCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0f08 +#define regCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0f09 +#define regCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0f0a +#define regCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0f0b +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0f0c +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0f0d +#define regCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0f0e +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0f0f +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0f10 +#define regCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0f11 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0f12 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0f13 +#define regCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0f14 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0f15 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0f16 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0f17 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0f18 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0f19 +#define regCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0f1a +#define regCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0f1b +#define regCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0f1c +#define regCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0f1d +#define regCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0f1e +#define regCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0f1f +#define regCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0f20 +#define regCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0f21 +#define regCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0f22 +#define regCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0f23 +#define regCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0f24 +#define regCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0f25 +#define regCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0f26 +#define regCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0f27 +#define regCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0f28 +#define regCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0f29 +#define regCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0f2a +#define regCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0f2b +#define regCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0f2c +#define regCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0f2d +#define regCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM1_CM_HDR_MULT_COEF 0x0f2e +#define regCM1_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_CTRL 0x0f2f +#define regCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM1_CM_MEM_PWR_STATUS 0x0f30 +#define regCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM1_CM_DEALPHA 0x0f32 +#define regCM1_CM_DEALPHA_BASE_IDX 2 +#define regCM1_CM_COEF_FORMAT 0x0f33 +#define regCM1_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM1_CM_TEST_DEBUG_INDEX 0x0f34 +#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM1_CM_TEST_DEBUG_DATA 0x0f35 +#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM1_CM_HIST_CNTL 0x0f36 +#define regCM1_CM_HIST_CNTL_BASE_IDX 2 +#define regCM1_CM_HIST_SCALE_SRC1 0x0f37 +#define regCM1_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM1_CM_HIST_COEFA_SRC2 0x0f38 +#define regCM1_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_COEFB_SRC2 0x0f39 +#define regCM1_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_COEFC_SRC2 0x0f3a +#define regCM1_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_SCALE_SRC3 0x0f3b +#define regCM1_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM1_CM_HIST_BIAS_SRC1 0x0f3c +#define regCM1_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM1_CM_HIST_BIAS_SRC2 0x0f3d +#define regCM1_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM1_CM_HIST_BIAS_SRC3 0x0f3e +#define regCM1_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM1_CM_HIST_LOCK 0x0f3f +#define regCM1_CM_HIST_LOCK_BASE_IDX 2 +#define regCM1_CM_HIST_INDEX 0x0f40 +#define regCM1_CM_HIST_INDEX_BASE_IDX 2 +#define regCM1_CM_HIST_DATA 0x0f41 +#define regCM1_CM_HIST_DATA_BASE_IDX 2 +#define regCM1_CM_HIST_STATUS 0x0f42 +#define regCM1_CM_HIST_STATUS_BASE_IDX 2 +#define regCM1_CM_HIST_INT_CONTROL 0x0f43 +#define regCM1_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x3e3c +#define regDC_PERFMON11_PERFCOUNTER_CNTL 0x0f8f +#define regDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON11_PERFCOUNTER_CNTL2 0x0f90 +#define regDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON11_PERFCOUNTER_STATE 0x0f91 +#define regDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CNTL 0x0f92 +#define regDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CNTL2 0x0f93 +#define regDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0f94 +#define regDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_CVALUE_LOW 0x0f95 +#define regDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_HI 0x0f96 +#define regDC_PERFMON11_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON11_PERFMON_LOW 0x0f97 +#define regDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +// base address: 0xb58 +#define regDPP_TOP2_DPP_CONTROL 0x0f9b +#define regDPP_TOP2_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP2_DPP_SOFT_RESET 0x0f9c +#define regDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_R 0x0f9d +#define regDPP_TOP2_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_G 0x0f9e +#define regDPP_TOP2_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_B 0x0f9f +#define regDPP_TOP2_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_VAL_A 0x0fa0 +#define regDPP_TOP2_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP2_DPP_CRC_CTRL 0x0fa1 +#define regDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP2_HOST_READ_CONTROL 0x0fa2 +#define regDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +// base address: 0xb58 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa7 +#define regCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_FORMAT_CONTROL 0x0fa8 +#define regCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa9 +#define regCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_G 0x0faa +#define regCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_BIAS_B 0x0fab +#define regCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_R 0x0fac +#define regCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_G 0x0fad +#define regCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG2_FCNV_FP_SCALE_B 0x0fae +#define regCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_CONTROL 0x0faf +#define regCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fb0 +#define regCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_RED 0x0fb1 +#define regCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb2 +#define regCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb3 +#define regCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT01 0x0fb5 +#define regCNVC_CFG2_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG2_ALPHA_2BIT_LUT23 0x0fb6 +#define regCNVC_CFG2_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEALPHA 0x0fb7 +#define regCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_MODE 0x0fb8 +#define regCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C11_C12 0x0fb9 +#define regCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C13_C14 0x0fba +#define regCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C21_C22 0x0fbb +#define regCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C23_C24 0x0fbc +#define regCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C31_C32 0x0fbd +#define regCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_C33_C34 0x0fbe +#define regCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbf +#define regCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fc0 +#define regCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fc1 +#define regCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fc2 +#define regCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc3 +#define regCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc4 +#define regCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc5 +#define regCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG2_PRE_DEGAM 0x0fc6 +#define regCNVC_CFG2_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG2_PRE_REALPHA 0x0fc7 +#define regCNVC_CFG2_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_cur_dispdec +// base address: 0xb58 +#define regCM_CUR2_CURSOR0_CONTROL 0x0fca +#define regCM_CUR2_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_COLOR0 0x0fcb +#define regCM_CUR2_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_COLOR1 0x0fcc +#define regCM_CUR2_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y 0x0fcd +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x0fce +#define regCM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_MODE 0x0fcf +#define regCM_CUR2_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_A 0x0fd0 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_A 0x0fd1 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_A 0x0fd2 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_A 0x0fd3 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C31_C32_A 0x0fd4 +#define regCM_CUR2_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C33_C34_A 0x0fd5 +#define regCM_CUR2_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_B 0x0fd6 +#define regCM_CUR2_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_B 0x0fd7 +#define regCM_CUR2_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_B 0x0fd8 +#define regCM_CUR2_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_B 0x0fd9 +#define regCM_CUR2_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C31_C32_B 0x0fda +#define regCM_CUR2_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR2_CUR0_MATRIX_C33_C34_B 0x0fdb +#define regCM_CUR2_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +// base address: 0xb58 +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fde +#define regDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fdf +#define regDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL2_SCL_MODE 0x0fe0 +#define regDSCL2_SCL_MODE_BASE_IDX 2 +#define regDSCL2_SCL_TAP_CONTROL 0x0fe1 +#define regDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_CONTROL 0x0fe2 +#define regDSCL2_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL2_DSCL_2TAP_CONTROL 0x0fe3 +#define regDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fe4 +#define regDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fe5 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT 0x0fe6 +#define regDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fe7 +#define regDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fe8 +#define regDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fe9 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT 0x0fea +#define regDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0feb +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fec +#define regDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_C 0x0fed +#define regDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fee +#define regDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL2_SCL_BLACK_COLOR 0x0fef +#define regDSCL2_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL2_DSCL_UPDATE 0x0ff0 +#define regDSCL2_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL2_DSCL_AUTOCAL 0x0ff1 +#define regDSCL2_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0ff2 +#define regDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ff3 +#define regDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL2_OTG_H_BLANK 0x0ff4 +#define regDSCL2_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL2_OTG_V_BLANK 0x0ff5 +#define regDSCL2_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL2_RECOUT_START 0x0ff6 +#define regDSCL2_RECOUT_START_BASE_IDX 2 +#define regDSCL2_RECOUT_SIZE 0x0ff7 +#define regDSCL2_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL2_MPC_SIZE 0x0ff8 +#define regDSCL2_MPC_SIZE_BASE_IDX 2 +#define regDSCL2_LB_DATA_FORMAT 0x0ff9 +#define regDSCL2_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL2_LB_MEMORY_CTRL 0x0ffa +#define regDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL2_LB_V_COUNTER 0x0ffb +#define regDSCL2_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_CTRL 0x0ffc +#define regDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_MEM_PWR_STATUS 0x0ffd +#define regDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL2_OBUF_CONTROL 0x0ffe +#define regDSCL2_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL2_OBUF_MEM_PWR_CTRL 0x0fff +#define regDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_MODE 0x1000 +#define regDSCL2_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_MODE 0x1001 +#define regDSCL2_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL2_DSCL_SC_MODE 0x1002 +#define regDSCL2_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL2_DSCL_SC_MATRIX_C0C1 0x1003 +#define regDSCL2_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL2_DSCL_SC_MATRIX_C2C3 0x1004 +#define regDSCL2_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x1005 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1006 +#define regDSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1007 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1008 +#define regDSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1009 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x100a +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x100b +#define regDSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_RINGEST_FORCE 0x100c +#define regDSCL2_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF_CNTL 0x100d +#define regDSCL2_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x100e +#define regDSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF_CNTL 0x100f +#define regDSCL2_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x1010 +#define regDSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0 0x1011 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1 0x1012 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2 0x1013 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3 0x1014 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4 0x1015 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5 0x1016 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6 0x1017 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7 0x1018 +#define regDSCL2_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0 0x1019 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1 0x101a +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2 0x101b +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3 0x101c +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4 0x101d +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5 0x101e +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6 0x101f +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7 0x1020 +#define regDSCL2_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0 0x1021 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1 0x1022 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2 0x1023 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3 0x1024 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4 0x1025 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5 0x1026 +#define regDSCL2_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0 0x1027 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1 0x1028 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2 0x1029 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3 0x102a +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4 0x102b +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5 0x102c +#define regDSCL2_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_ISHARP_MODE 0x102d +#define regDSCL2_ISHARP_MODE_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_CTRL 0x102e +#define regDSCL2_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_INDEX 0x102f +#define regDSCL2_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_DATA 0x1030 +#define regDSCL2_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP 0x1031 +#define regDSCL2_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL2_ISHARP_NOISEDET_THRESHOLD 0x1032 +#define regDSCL2_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL2_ISHARP_NOISE_GAIN_PWL 0x1033 +#define regDSCL2_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG0 0x1034 +#define regDSCL2_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG1 0x1035 +#define regDSCL2_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG2 0x1036 +#define regDSCL2_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG3 0x1037 +#define regDSCL2_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG4 0x1038 +#define regDSCL2_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL2_ISHARP_LBA_PWL_SEG5 0x1039 +#define regDSCL2_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x103a +#define regDSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +// base address: 0xb58 +#define regCM2_CM_CONTROL 0x103f +#define regCM2_CM_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_CONTROL 0x1040 +#define regCM2_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C11_C12 0x1041 +#define regCM2_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C13_C14 0x1042 +#define regCM2_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C21_C22 0x1043 +#define regCM2_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C23_C24 0x1044 +#define regCM2_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C31_C32 0x1045 +#define regCM2_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_C33_C34 0x1046 +#define regCM2_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C11_C12 0x1047 +#define regCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C13_C14 0x1048 +#define regCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C21_C22 0x1049 +#define regCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C23_C24 0x104a +#define regCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C31_C32 0x104b +#define regCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM2_CM_POST_CSC_B_C33_C34 0x104c +#define regCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM2_CM_BIAS_CR_R 0x104d +#define regCM2_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM2_CM_BIAS_Y_G_CB_B 0x104e +#define regCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_CONTROL 0x104f +#define regCM2_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_INDEX 0x1050 +#define regCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_DATA 0x1051 +#define regCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM2_CM_GAMCOR_LUT_CONTROL 0x1052 +#define regCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1053 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1054 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1055 +#define regCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1056 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1057 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1058 +#define regCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1059 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x105a +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x105b +#define regCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x105c +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x105d +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x105e +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x105f +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1060 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1061 +#define regCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1062 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1063 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1064 +#define regCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1065 +#define regCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3 0x1066 +#define regCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5 0x1067 +#define regCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7 0x1068 +#define regCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9 0x1069 +#define regCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11 0x106a +#define regCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13 0x106b +#define regCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15 0x106c +#define regCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17 0x106d +#define regCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19 0x106e +#define regCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21 0x106f +#define regCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1070 +#define regCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1071 +#define regCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1072 +#define regCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1073 +#define regCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1074 +#define regCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1075 +#define regCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x1076 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x1077 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x1078 +#define regCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1079 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x107a +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x107b +#define regCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x107c +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x107d +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x107e +#define regCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x107f +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1080 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1081 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1082 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1083 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1084 +#define regCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1085 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G 0x1086 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R 0x1087 +#define regCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1 0x1088 +#define regCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3 0x1089 +#define regCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5 0x108a +#define regCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7 0x108b +#define regCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9 0x108c +#define regCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11 0x108d +#define regCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13 0x108e +#define regCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15 0x108f +#define regCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1090 +#define regCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1091 +#define regCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1092 +#define regCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1093 +#define regCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1094 +#define regCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1095 +#define regCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29 0x1096 +#define regCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31 0x1097 +#define regCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33 0x1098 +#define regCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM2_CM_HDR_MULT_COEF 0x1099 +#define regCM2_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_CTRL 0x109a +#define regCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM2_CM_MEM_PWR_STATUS 0x109b +#define regCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM2_CM_DEALPHA 0x109d +#define regCM2_CM_DEALPHA_BASE_IDX 2 +#define regCM2_CM_COEF_FORMAT 0x109e +#define regCM2_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM2_CM_TEST_DEBUG_INDEX 0x109f +#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM2_CM_TEST_DEBUG_DATA 0x10a0 +#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM2_CM_HIST_CNTL 0x10a1 +#define regCM2_CM_HIST_CNTL_BASE_IDX 2 +#define regCM2_CM_HIST_SCALE_SRC1 0x10a2 +#define regCM2_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM2_CM_HIST_COEFA_SRC2 0x10a3 +#define regCM2_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_COEFB_SRC2 0x10a4 +#define regCM2_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_COEFC_SRC2 0x10a5 +#define regCM2_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_SCALE_SRC3 0x10a6 +#define regCM2_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM2_CM_HIST_BIAS_SRC1 0x10a7 +#define regCM2_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM2_CM_HIST_BIAS_SRC2 0x10a8 +#define regCM2_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM2_CM_HIST_BIAS_SRC3 0x10a9 +#define regCM2_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM2_CM_HIST_LOCK 0x10aa +#define regCM2_CM_HIST_LOCK_BASE_IDX 2 +#define regCM2_CM_HIST_INDEX 0x10ab +#define regCM2_CM_HIST_INDEX_BASE_IDX 2 +#define regCM2_CM_HIST_DATA 0x10ac +#define regCM2_CM_HIST_DATA_BASE_IDX 2 +#define regCM2_CM_HIST_STATUS 0x10ad +#define regCM2_CM_HIST_STATUS_BASE_IDX 2 +#define regCM2_CM_HIST_INT_CONTROL 0x10ae +#define regCM2_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x43e8 +#define regDC_PERFMON12_PERFCOUNTER_CNTL 0x10fa +#define regDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON12_PERFCOUNTER_CNTL2 0x10fb +#define regDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON12_PERFCOUNTER_STATE 0x10fc +#define regDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CNTL 0x10fd +#define regDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CNTL2 0x10fe +#define regDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x10ff +#define regDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_CVALUE_LOW 0x1100 +#define regDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_HI 0x1101 +#define regDC_PERFMON12_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON12_PERFMON_LOW 0x1102 +#define regDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +// base address: 0x1104 +#define regDPP_TOP3_DPP_CONTROL 0x1106 +#define regDPP_TOP3_DPP_CONTROL_BASE_IDX 2 +#define regDPP_TOP3_DPP_SOFT_RESET 0x1107 +#define regDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_R 0x1108 +#define regDPP_TOP3_DPP_CRC_VAL_R_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_G 0x1109 +#define regDPP_TOP3_DPP_CRC_VAL_G_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_B 0x110a +#define regDPP_TOP3_DPP_CRC_VAL_B_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_VAL_A 0x110b +#define regDPP_TOP3_DPP_CRC_VAL_A_BASE_IDX 2 +#define regDPP_TOP3_DPP_CRC_CTRL 0x110c +#define regDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 +#define regDPP_TOP3_HOST_READ_CONTROL 0x110d +#define regDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +// base address: 0x1104 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1112 +#define regCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_FORMAT_CONTROL 0x1113 +#define regCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_R 0x1114 +#define regCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_G 0x1115 +#define regCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_BIAS_B 0x1116 +#define regCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_R 0x1117 +#define regCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_G 0x1118 +#define regCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2 +#define regCNVC_CFG3_FCNV_FP_SCALE_B 0x1119 +#define regCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_CONTROL 0x111a +#define regCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_ALPHA 0x111b +#define regCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_RED 0x111c +#define regCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_GREEN 0x111d +#define regCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 +#define regCNVC_CFG3_COLOR_KEYER_BLUE 0x111e +#define regCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT01 0x1120 +#define regCNVC_CFG3_ALPHA_2BIT_LUT01_BASE_IDX 2 +#define regCNVC_CFG3_ALPHA_2BIT_LUT23 0x1121 +#define regCNVC_CFG3_ALPHA_2BIT_LUT23_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEALPHA 0x1122 +#define regCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_MODE 0x1123 +#define regCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C11_C12 0x1124 +#define regCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C13_C14 0x1125 +#define regCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C21_C22 0x1126 +#define regCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C23_C24 0x1127 +#define regCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C31_C32 0x1128 +#define regCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_C33_C34 0x1129 +#define regCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C11_C12 0x112a +#define regCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C13_C14 0x112b +#define regCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C21_C22 0x112c +#define regCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C23_C24 0x112d +#define regCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C31_C32 0x112e +#define regCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2 +#define regCNVC_CFG3_PRE_CSC_B_C33_C34 0x112f +#define regCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2 +#define regCNVC_CFG3_CNVC_COEF_FORMAT 0x1130 +#define regCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2 +#define regCNVC_CFG3_PRE_DEGAM 0x1131 +#define regCNVC_CFG3_PRE_DEGAM_BASE_IDX 2 +#define regCNVC_CFG3_PRE_REALPHA 0x1132 +#define regCNVC_CFG3_PRE_REALPHA_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_cur_dispdec +// base address: 0x1104 +#define regCM_CUR3_CURSOR0_CONTROL 0x1135 +#define regCM_CUR3_CURSOR0_CONTROL_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_COLOR0 0x1136 +#define regCM_CUR3_CURSOR0_COLOR0_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_COLOR1 0x1137 +#define regCM_CUR3_CURSOR0_COLOR1_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y 0x1138 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y_BASE_IDX 2 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB 0x1139 +#define regCM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_MODE 0x113a +#define regCM_CUR3_CUR0_MATRIX_MODE_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C11_C12_A 0x113b +#define regCM_CUR3_CUR0_MATRIX_C11_C12_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C13_C14_A 0x113c +#define regCM_CUR3_CUR0_MATRIX_C13_C14_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C21_C22_A 0x113d +#define regCM_CUR3_CUR0_MATRIX_C21_C22_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C23_C24_A 0x113e +#define regCM_CUR3_CUR0_MATRIX_C23_C24_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C31_C32_A 0x113f +#define regCM_CUR3_CUR0_MATRIX_C31_C32_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_A 0x1140 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_A_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C11_C12_B 0x1141 +#define regCM_CUR3_CUR0_MATRIX_C11_C12_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C13_C14_B 0x1142 +#define regCM_CUR3_CUR0_MATRIX_C13_C14_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C21_C22_B 0x1143 +#define regCM_CUR3_CUR0_MATRIX_C21_C22_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C23_C24_B 0x1144 +#define regCM_CUR3_CUR0_MATRIX_C23_C24_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C31_C32_B 0x1145 +#define regCM_CUR3_CUR0_MATRIX_C31_C32_B_BASE_IDX 2 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_B 0x1146 +#define regCM_CUR3_CUR0_MATRIX_C33_C34_B_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +// base address: 0x1104 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT 0x1149 +#define regDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 +#define regDSCL3_SCL_COEF_RAM_TAP_DATA 0x114a +#define regDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 +#define regDSCL3_SCL_MODE 0x114b +#define regDSCL3_SCL_MODE_BASE_IDX 2 +#define regDSCL3_SCL_TAP_CONTROL 0x114c +#define regDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_CONTROL 0x114d +#define regDSCL3_DSCL_CONTROL_BASE_IDX 2 +#define regDSCL3_DSCL_2TAP_CONTROL 0x114e +#define regDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x114f +#define regDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1150 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT 0x1151 +#define regDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1152 +#define regDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C 0x1153 +#define regDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1154 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT 0x1155 +#define regDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1156 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1157 +#define regDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_C 0x1158 +#define regDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x1159 +#define regDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 +#define regDSCL3_SCL_BLACK_COLOR 0x115a +#define regDSCL3_SCL_BLACK_COLOR_BASE_IDX 2 +#define regDSCL3_DSCL_UPDATE 0x115b +#define regDSCL3_DSCL_UPDATE_BASE_IDX 2 +#define regDSCL3_DSCL_AUTOCAL 0x115c +#define regDSCL3_DSCL_AUTOCAL_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x115d +#define regDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x115e +#define regDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 +#define regDSCL3_OTG_H_BLANK 0x115f +#define regDSCL3_OTG_H_BLANK_BASE_IDX 2 +#define regDSCL3_OTG_V_BLANK 0x1160 +#define regDSCL3_OTG_V_BLANK_BASE_IDX 2 +#define regDSCL3_RECOUT_START 0x1161 +#define regDSCL3_RECOUT_START_BASE_IDX 2 +#define regDSCL3_RECOUT_SIZE 0x1162 +#define regDSCL3_RECOUT_SIZE_BASE_IDX 2 +#define regDSCL3_MPC_SIZE 0x1163 +#define regDSCL3_MPC_SIZE_BASE_IDX 2 +#define regDSCL3_LB_DATA_FORMAT 0x1164 +#define regDSCL3_LB_DATA_FORMAT_BASE_IDX 2 +#define regDSCL3_LB_MEMORY_CTRL 0x1165 +#define regDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 +#define regDSCL3_LB_V_COUNTER 0x1166 +#define regDSCL3_LB_V_COUNTER_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_CTRL 0x1167 +#define regDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_MEM_PWR_STATUS 0x1168 +#define regDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 +#define regDSCL3_OBUF_CONTROL 0x1169 +#define regDSCL3_OBUF_CONTROL_BASE_IDX 2 +#define regDSCL3_OBUF_MEM_PWR_CTRL 0x116a +#define regDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_MODE 0x116b +#define regDSCL3_DSCL_EASF_H_MODE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_MODE 0x116c +#define regDSCL3_DSCL_EASF_V_MODE_BASE_IDX 2 +#define regDSCL3_DSCL_SC_MODE 0x116d +#define regDSCL3_DSCL_SC_MODE_BASE_IDX 2 +#define regDSCL3_DSCL_SC_MATRIX_C0C1 0x116e +#define regDSCL3_DSCL_SC_MATRIX_C0C1_BASE_IDX 2 +#define regDSCL3_DSCL_SC_MATRIX_C2C3 0x116f +#define regDSCL3_DSCL_SC_MATRIX_C2C3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x1170 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1171 +#define regDSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1172 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1173 +#define regDSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1174 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1175 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1176 +#define regDSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_RINGEST_FORCE 0x1177 +#define regDSCL3_DSCL_EASF_RINGEST_FORCE_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF_CNTL 0x1178 +#define regDSCL3_DSCL_EASF_H_BF_CNTL_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN 0x1179 +#define regDSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF_CNTL 0x117a +#define regDSCL3_DSCL_EASF_V_BF_CNTL_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN 0x117b +#define regDSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0 0x117c +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1 0x117d +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2 0x117e +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3 0x117f +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4 0x1180 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5 0x1181 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6 0x1182 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7 0x1183 +#define regDSCL3_DSCL_EASF_H_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0 0x1184 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1 0x1185 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2 0x1186 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3 0x1187 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4 0x1188 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5 0x1189 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6 0x118a +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG6_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7 0x118b +#define regDSCL3_DSCL_EASF_V_BF1_PWL_SEG7_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0 0x118c +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1 0x118d +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2 0x118e +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3 0x118f +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4 0x1190 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5 0x1191 +#define regDSCL3_DSCL_EASF_H_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0 0x1192 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1 0x1193 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2 0x1194 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3 0x1195 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4 0x1196 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5 0x1197 +#define regDSCL3_DSCL_EASF_V_BF3_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_ISHARP_MODE 0x1198 +#define regDSCL3_ISHARP_MODE_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_CTRL 0x1199 +#define regDSCL3_ISHARP_DELTA_CTRL_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_INDEX 0x119a +#define regDSCL3_ISHARP_DELTA_INDEX_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_DATA 0x119b +#define regDSCL3_ISHARP_DELTA_DATA_BASE_IDX 2 +#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP 0x119c +#define regDSCL3_ISHARP_NLDELTA_SOFT_CLIP_BASE_IDX 2 +#define regDSCL3_ISHARP_NOISEDET_THRESHOLD 0x119d +#define regDSCL3_ISHARP_NOISEDET_THRESHOLD_BASE_IDX 2 +#define regDSCL3_ISHARP_NOISE_GAIN_PWL 0x119e +#define regDSCL3_ISHARP_NOISE_GAIN_PWL_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG0 0x119f +#define regDSCL3_ISHARP_LBA_PWL_SEG0_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG1 0x11a0 +#define regDSCL3_ISHARP_LBA_PWL_SEG1_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG2 0x11a1 +#define regDSCL3_ISHARP_LBA_PWL_SEG2_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG3 0x11a2 +#define regDSCL3_ISHARP_LBA_PWL_SEG3_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG4 0x11a3 +#define regDSCL3_ISHARP_LBA_PWL_SEG4_BASE_IDX 2 +#define regDSCL3_ISHARP_LBA_PWL_SEG5 0x11a4 +#define regDSCL3_ISHARP_LBA_PWL_SEG5_BASE_IDX 2 +#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11a5 +#define regDSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +// base address: 0x1104 +#define regCM3_CM_CONTROL 0x11aa +#define regCM3_CM_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_CONTROL 0x11ab +#define regCM3_CM_POST_CSC_CONTROL_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C11_C12 0x11ac +#define regCM3_CM_POST_CSC_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C13_C14 0x11ad +#define regCM3_CM_POST_CSC_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C21_C22 0x11ae +#define regCM3_CM_POST_CSC_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C23_C24 0x11af +#define regCM3_CM_POST_CSC_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C31_C32 0x11b0 +#define regCM3_CM_POST_CSC_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_C33_C34 0x11b1 +#define regCM3_CM_POST_CSC_C33_C34_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C11_C12 0x11b2 +#define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C13_C14 0x11b3 +#define regCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C21_C22 0x11b4 +#define regCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C23_C24 0x11b5 +#define regCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C31_C32 0x11b6 +#define regCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2 +#define regCM3_CM_POST_CSC_B_C33_C34 0x11b7 +#define regCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2 +#define regCM3_CM_BIAS_CR_R 0x11b8 +#define regCM3_CM_BIAS_CR_R_BASE_IDX 2 +#define regCM3_CM_BIAS_Y_G_CB_B 0x11b9 +#define regCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_CONTROL 0x11ba +#define regCM3_CM_GAMCOR_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_INDEX 0x11bb +#define regCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_DATA 0x11bc +#define regCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2 +#define regCM3_CM_GAMCOR_LUT_CONTROL 0x11bd +#define regCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x11be +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x11bf +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x11c0 +#define regCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x11c1 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x11c2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x11c3 +#define regCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x11c4 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x11c5 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x11c6 +#define regCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x11c7 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x11c8 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x11c9 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x11ca +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x11cb +#define regCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x11cc +#define regCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B 0x11cd +#define regCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G 0x11ce +#define regCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R 0x11cf +#define regCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1 0x11d0 +#define regCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3 0x11d1 +#define regCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5 0x11d2 +#define regCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7 0x11d3 +#define regCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9 0x11d4 +#define regCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11 0x11d5 +#define regCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13 0x11d6 +#define regCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15 0x11d7 +#define regCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17 0x11d8 +#define regCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19 0x11d9 +#define regCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21 0x11da +#define regCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23 0x11db +#define regCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11dc +#define regCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11dd +#define regCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11de +#define regCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11df +#define regCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11e0 +#define regCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11e1 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11e2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11e3 +#define regCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11e4 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11e5 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11e6 +#define regCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11e7 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11e8 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11e9 +#define regCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ea +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11eb +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11ec +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11ed +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11ee +#define regCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11ef +#define regCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11f0 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11f1 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11f2 +#define regCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11f3 +#define regCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11f4 +#define regCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11f5 +#define regCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11f6 +#define regCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11f7 +#define regCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11f8 +#define regCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11f9 +#define regCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11fa +#define regCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11fb +#define regCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11fc +#define regCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11fd +#define regCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11fe +#define regCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11ff +#define regCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27 0x1200 +#define regCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29 0x1201 +#define regCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31 0x1202 +#define regCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33 0x1203 +#define regCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2 +#define regCM3_CM_HDR_MULT_COEF 0x1204 +#define regCM3_CM_HDR_MULT_COEF_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_CTRL 0x1205 +#define regCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 +#define regCM3_CM_MEM_PWR_STATUS 0x1206 +#define regCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 +#define regCM3_CM_DEALPHA 0x1208 +#define regCM3_CM_DEALPHA_BASE_IDX 2 +#define regCM3_CM_COEF_FORMAT 0x1209 +#define regCM3_CM_COEF_FORMAT_BASE_IDX 2 +#define regCM3_CM_TEST_DEBUG_INDEX 0x120a +#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regCM3_CM_TEST_DEBUG_DATA 0x120b +#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 +#define regCM3_CM_HIST_CNTL 0x120c +#define regCM3_CM_HIST_CNTL_BASE_IDX 2 +#define regCM3_CM_HIST_SCALE_SRC1 0x120d +#define regCM3_CM_HIST_SCALE_SRC1_BASE_IDX 2 +#define regCM3_CM_HIST_COEFA_SRC2 0x120e +#define regCM3_CM_HIST_COEFA_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_COEFB_SRC2 0x120f +#define regCM3_CM_HIST_COEFB_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_COEFC_SRC2 0x1210 +#define regCM3_CM_HIST_COEFC_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_SCALE_SRC3 0x1211 +#define regCM3_CM_HIST_SCALE_SRC3_BASE_IDX 2 +#define regCM3_CM_HIST_BIAS_SRC1 0x1212 +#define regCM3_CM_HIST_BIAS_SRC1_BASE_IDX 2 +#define regCM3_CM_HIST_BIAS_SRC2 0x1213 +#define regCM3_CM_HIST_BIAS_SRC2_BASE_IDX 2 +#define regCM3_CM_HIST_BIAS_SRC3 0x1214 +#define regCM3_CM_HIST_BIAS_SRC3_BASE_IDX 2 +#define regCM3_CM_HIST_LOCK 0x1215 +#define regCM3_CM_HIST_LOCK_BASE_IDX 2 +#define regCM3_CM_HIST_INDEX 0x1216 +#define regCM3_CM_HIST_INDEX_BASE_IDX 2 +#define regCM3_CM_HIST_DATA 0x1217 +#define regCM3_CM_HIST_DATA_BASE_IDX 2 +#define regCM3_CM_HIST_STATUS 0x1218 +#define regCM3_CM_HIST_STATUS_BASE_IDX 2 +#define regCM3_CM_HIST_INT_CONTROL 0x1219 +#define regCM3_CM_HIST_INT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +// base address: 0x4994 +#define regDC_PERFMON13_PERFCOUNTER_CNTL 0x1265 +#define regDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON13_PERFCOUNTER_CNTL2 0x1266 +#define regDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON13_PERFCOUNTER_STATE 0x1267 +#define regDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CNTL 0x1268 +#define regDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CNTL2 0x1269 +#define regDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x126a +#define regDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_CVALUE_LOW 0x126b +#define regDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_HI 0x126c +#define regDC_PERFMON13_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON13_PERFMON_LOW 0x126d +#define regDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux0_dispdec +// base address: 0x0 +#define regDP_AUX0_AUX_CONTROL 0x16b2 +#define regDP_AUX0_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_CONTROL 0x16b3 +#define regDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_ARB_CONTROL 0x16b4 +#define regDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL 0x16b5 +#define regDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_STATUS 0x16b6 +#define regDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_STATUS 0x16b7 +#define regDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_SW_DATA 0x16b8 +#define regDP_AUX0_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_LS_DATA 0x16b9 +#define regDP_AUX0_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x16ba +#define regDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_CONTROL 0x16bb +#define regDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0 0x16bc +#define regDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1 0x16bd +#define regDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_TX_STATUS 0x16be +#define regDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_DPHY_RX_STATUS 0x16bf +#define regDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL 0x16c1 +#define regDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX0_AUX_PHY_WAKE_STATUS 0x16c2 +#define regDP_AUX0_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux1_dispdec +// base address: 0x70 +#define regDP_AUX1_AUX_CONTROL 0x16ce +#define regDP_AUX1_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_CONTROL 0x16cf +#define regDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_ARB_CONTROL 0x16d0 +#define regDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL 0x16d1 +#define regDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_STATUS 0x16d2 +#define regDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_STATUS 0x16d3 +#define regDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_SW_DATA 0x16d4 +#define regDP_AUX1_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_LS_DATA 0x16d5 +#define regDP_AUX1_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x16d6 +#define regDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL 0x16d7 +#define regDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0 0x16d8 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1 0x16d9 +#define regDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_TX_STATUS 0x16da +#define regDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_DPHY_RX_STATUS 0x16db +#define regDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_CNTL 0x16dd +#define regDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX1_AUX_PHY_WAKE_STATUS 0x16de +#define regDP_AUX1_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux2_dispdec +// base address: 0xe0 +#define regDP_AUX2_AUX_CONTROL 0x16ea +#define regDP_AUX2_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_CONTROL 0x16eb +#define regDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_ARB_CONTROL 0x16ec +#define regDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_INTERRUPT_CONTROL 0x16ed +#define regDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_STATUS 0x16ee +#define regDP_AUX2_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_STATUS 0x16ef +#define regDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_SW_DATA 0x16f0 +#define regDP_AUX2_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_LS_DATA 0x16f1 +#define regDP_AUX2_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x16f2 +#define regDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL 0x16f3 +#define regDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0 0x16f4 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1 0x16f5 +#define regDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_TX_STATUS 0x16f6 +#define regDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_DPHY_RX_STATUS 0x16f7 +#define regDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL 0x16f9 +#define regDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX2_AUX_PHY_WAKE_STATUS 0x16fa +#define regDP_AUX2_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux3_dispdec +// base address: 0x150 +#define regDP_AUX3_AUX_CONTROL 0x1706 +#define regDP_AUX3_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_CONTROL 0x1707 +#define regDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_ARB_CONTROL 0x1708 +#define regDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL 0x1709 +#define regDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_STATUS 0x170a +#define regDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_STATUS 0x170b +#define regDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_SW_DATA 0x170c +#define regDP_AUX3_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_LS_DATA 0x170d +#define regDP_AUX3_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x170e +#define regDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_CONTROL 0x170f +#define regDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1710 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1711 +#define regDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_TX_STATUS 0x1712 +#define regDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_DPHY_RX_STATUS 0x1713 +#define regDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL 0x1715 +#define regDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX3_AUX_PHY_WAKE_STATUS 0x1716 +#define regDP_AUX3_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dp_aux4_dispdec +// base address: 0x1c0 +#define regDP_AUX4_AUX_CONTROL 0x1722 +#define regDP_AUX4_AUX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_CONTROL 0x1723 +#define regDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_ARB_CONTROL 0x1724 +#define regDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL 0x1725 +#define regDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_STATUS 0x1726 +#define regDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_STATUS 0x1727 +#define regDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_SW_DATA 0x1728 +#define regDP_AUX4_AUX_SW_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_LS_DATA 0x1729 +#define regDP_AUX4_AUX_LS_DATA_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x172a +#define regDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_CONTROL 0x172b +#define regDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0 0x172c +#define regDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1 0x172d +#define regDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_TX_STATUS 0x172e +#define regDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_DPHY_RX_STATUS 0x172f +#define regDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL 0x1731 +#define regDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2 +#define regDP_AUX4_AUX_PHY_WAKE_STATUS 0x1732 +#define regDP_AUX4_AUX_PHY_WAKE_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd0_dispdec +// base address: 0x0 +#define regHPD0_DC_HPD_INT_STATUS 0x175a +#define regHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD0_DC_HPD_INT_CONTROL 0x175b +#define regHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_CONTROL 0x175c +#define regHPD0_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL 0x175d +#define regHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x175e +#define regHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd1_dispdec +// base address: 0x20 +#define regHPD1_DC_HPD_INT_STATUS 0x1762 +#define regHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD1_DC_HPD_INT_CONTROL 0x1763 +#define regHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_CONTROL 0x1764 +#define regHPD1_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1765 +#define regHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1766 +#define regHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd2_dispdec +// base address: 0x40 +#define regHPD2_DC_HPD_INT_STATUS 0x176a +#define regHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD2_DC_HPD_INT_CONTROL 0x176b +#define regHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_CONTROL 0x176c +#define regHPD2_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL 0x176d +#define regHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x176e +#define regHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd3_dispdec +// base address: 0x60 +#define regHPD3_DC_HPD_INT_STATUS 0x1772 +#define regHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD3_DC_HPD_INT_CONTROL 0x1773 +#define regHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_CONTROL 0x1774 +#define regHPD3_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1775 +#define regHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1776 +#define regHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_hpd4_dispdec +// base address: 0x80 +#define regHPD4_DC_HPD_INT_STATUS 0x177a +#define regHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 +#define regHPD4_DC_HPD_INT_CONTROL 0x177b +#define regHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_CONTROL 0x177c +#define regHPD4_DC_HPD_CONTROL_BASE_IDX 2 +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL 0x177d +#define regHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x177e +#define regHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux0_dispdec +// base address: 0x13128 +#define regDPIA_MUX0_DPIA_MUX_CONTROL 0x178a +#define regDPIA_MUX0_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux1_dispdec +// base address: 0x13130 +#define regDPIA_MUX1_DPIA_MUX_CONTROL 0x178c +#define regDPIA_MUX1_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux2_dispdec +// base address: 0x13138 +#define regDPIA_MUX2_DPIA_MUX_CONTROL 0x178e +#define regDPIA_MUX2_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux3_dispdec +// base address: 0x13140 +#define regDPIA_MUX3_DPIA_MUX_CONTROL 0x1790 +#define regDPIA_MUX3_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux4_dispdec +// base address: 0x13148 +#define regDPIA_MUX4_DPIA_MUX_CONTROL 0x1792 +#define regDPIA_MUX4_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dpia_mux5_dispdec +// base address: 0x13150 +#define regDPIA_MUX5_DPIA_MUX_CONTROL 0x1794 +#define regDPIA_MUX5_DPIA_MUX_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux0_dispdec +// base address: 0x13168 +#define regPHY_MUX0_PHY_MUX_CONTROL 0x179a +#define regPHY_MUX0_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX0_PORT_TYPE 0x179b +#define regPHY_MUX0_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux1_dispdec +// base address: 0x13174 +#define regPHY_MUX1_PHY_MUX_CONTROL 0x179d +#define regPHY_MUX1_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX1_PORT_TYPE 0x179e +#define regPHY_MUX1_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux2_dispdec +// base address: 0x13180 +#define regPHY_MUX2_PHY_MUX_CONTROL 0x17a0 +#define regPHY_MUX2_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX2_PORT_TYPE 0x17a1 +#define regPHY_MUX2_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux3_dispdec +// base address: 0x1318c +#define regPHY_MUX3_PHY_MUX_CONTROL 0x17a3 +#define regPHY_MUX3_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX3_PORT_TYPE 0x17a4 +#define regPHY_MUX3_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_phy_mux4_dispdec +// base address: 0x13198 +#define regPHY_MUX4_PHY_MUX_CONTROL 0x17a6 +#define regPHY_MUX4_PHY_MUX_CONTROL_BASE_IDX 2 +#define regPHY_MUX4_PORT_TYPE 0x17a7 +#define regPHY_MUX4_PORT_TYPE_BASE_IDX 2 + + +// addressBlock: dce_dc_dcoh_dcoh_top_dispdec +// base address: 0x0 +#define regDCOH_TOP_CLOCK_CONTROL 0x17af +#define regDCOH_TOP_CLOCK_CONTROL_BASE_IDX 2 +#define regDCOH_DCN_STATUS 0x17b0 +#define regDCOH_DCN_STATUS_BASE_IDX 2 +#define regDCOH_TOP_SPARE 0x17b4 +#define regDCOH_TOP_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt0_dispdec +// base address: 0x0 +#define regFMT0_FMT_CLAMP_COMPONENT_R 0x183c +#define regFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_G 0x183d +#define regFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_COMPONENT_B 0x183e +#define regFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f +#define regFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_CONTROL 0x1840 +#define regFMT0_FMT_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 +#define regFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_R_SEED 0x1842 +#define regFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_G_SEED 0x1843 +#define regFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT0_FMT_DITHER_RAND_B_SEED 0x1844 +#define regFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT0_FMT_CLAMP_CNTL 0x1845 +#define regFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846 +#define regFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847 +#define regFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT0_FMT_422_CONTROL 0x1849 +#define regFMT0_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg0_dispdec +// base address: 0x0 +#define regDPG0_DPG_CONTROL 0x1854 +#define regDPG0_DPG_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_RAMP_CONTROL 0x1855 +#define regDPG0_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG0_DPG_DIMENSIONS 0x1856 +#define regDPG0_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_R_CR 0x1857 +#define regDPG0_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_G_Y 0x1858 +#define regDPG0_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG0_DPG_COLOUR_B_CB 0x1859 +#define regDPG0_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG0_DPG_OFFSET_SEGMENT 0x185a +#define regDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG0_DPG_STATUS 0x185b +#define regDPG0_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +// base address: 0x0 +#define regOPPBUF0_OPPBUF_CONTROL 0x1884 +#define regOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 +#define regOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF0_OPPBUF_CONTROL1 0x1889 +#define regOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +// base address: 0x0 +#define regOPP_PIPE0_OPP_PIPE_CONTROL 0x188b +#define regOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +// base address: 0x0 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x188f +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1890 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA 0x1891 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR 0x1892 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG 0x1893 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB 0x1894 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC 0x1895 +#define regOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt1_dispdec +// base address: 0x168 +#define regFMT1_FMT_CLAMP_COMPONENT_R 0x1896 +#define regFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_G 0x1897 +#define regFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_COMPONENT_B 0x1898 +#define regFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 +#define regFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_CONTROL 0x189a +#define regFMT1_FMT_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_BIT_DEPTH_CONTROL 0x189b +#define regFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_R_SEED 0x189c +#define regFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_G_SEED 0x189d +#define regFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT1_FMT_DITHER_RAND_B_SEED 0x189e +#define regFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT1_FMT_CLAMP_CNTL 0x189f +#define regFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0 +#define regFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1 +#define regFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT1_FMT_422_CONTROL 0x18a3 +#define regFMT1_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg1_dispdec +// base address: 0x168 +#define regDPG1_DPG_CONTROL 0x18ae +#define regDPG1_DPG_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_RAMP_CONTROL 0x18af +#define regDPG1_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG1_DPG_DIMENSIONS 0x18b0 +#define regDPG1_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_R_CR 0x18b1 +#define regDPG1_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_G_Y 0x18b2 +#define regDPG1_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG1_DPG_COLOUR_B_CB 0x18b3 +#define regDPG1_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG1_DPG_OFFSET_SEGMENT 0x18b4 +#define regDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG1_DPG_STATUS 0x18b5 +#define regDPG1_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +// base address: 0x168 +#define regOPPBUF1_OPPBUF_CONTROL 0x18de +#define regOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 +#define regOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF1_OPPBUF_CONTROL1 0x18e3 +#define regOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +// base address: 0x168 +#define regOPP_PIPE1_OPP_PIPE_CONTROL 0x18e5 +#define regOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +// base address: 0x168 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18e9 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ea +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA 0x18eb +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR 0x18ec +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG 0x18ed +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB 0x18ee +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC 0x18ef +#define regOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt2_dispdec +// base address: 0x2d0 +#define regFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 +#define regFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 +#define regFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 +#define regFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 +#define regFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_CONTROL 0x18f4 +#define regFMT2_FMT_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 +#define regFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 +#define regFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 +#define regFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 +#define regFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT2_FMT_CLAMP_CNTL 0x18f9 +#define regFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa +#define regFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb +#define regFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT2_FMT_422_CONTROL 0x18fd +#define regFMT2_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg2_dispdec +// base address: 0x2d0 +#define regDPG2_DPG_CONTROL 0x1908 +#define regDPG2_DPG_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_RAMP_CONTROL 0x1909 +#define regDPG2_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG2_DPG_DIMENSIONS 0x190a +#define regDPG2_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_R_CR 0x190b +#define regDPG2_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_G_Y 0x190c +#define regDPG2_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG2_DPG_COLOUR_B_CB 0x190d +#define regDPG2_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG2_DPG_OFFSET_SEGMENT 0x190e +#define regDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG2_DPG_STATUS 0x190f +#define regDPG2_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +// base address: 0x2d0 +#define regOPPBUF2_OPPBUF_CONTROL 0x1938 +#define regOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a +#define regOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF2_OPPBUF_CONTROL1 0x193d +#define regOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE2_OPP_PIPE_CONTROL 0x193f +#define regOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +// base address: 0x2d0 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1943 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1944 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA 0x1945 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR 0x1946 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG 0x1947 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB 0x1948 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC 0x1949 +#define regOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_fmt3_dispdec +// base address: 0x438 +#define regFMT3_FMT_CLAMP_COMPONENT_R 0x194a +#define regFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_G 0x194b +#define regFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_COMPONENT_B 0x194c +#define regFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 +#define regFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d +#define regFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_CONTROL 0x194e +#define regFMT3_FMT_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_BIT_DEPTH_CONTROL 0x194f +#define regFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_R_SEED 0x1950 +#define regFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_G_SEED 0x1951 +#define regFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 +#define regFMT3_FMT_DITHER_RAND_B_SEED 0x1952 +#define regFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 +#define regFMT3_FMT_CLAMP_CNTL 0x1953 +#define regFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954 +#define regFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955 +#define regFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 +#define regFMT3_FMT_422_CONTROL 0x1957 +#define regFMT3_FMT_422_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dpg3_dispdec +// base address: 0x438 +#define regDPG3_DPG_CONTROL 0x1962 +#define regDPG3_DPG_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_RAMP_CONTROL 0x1963 +#define regDPG3_DPG_RAMP_CONTROL_BASE_IDX 2 +#define regDPG3_DPG_DIMENSIONS 0x1964 +#define regDPG3_DPG_DIMENSIONS_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_R_CR 0x1965 +#define regDPG3_DPG_COLOUR_R_CR_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_G_Y 0x1966 +#define regDPG3_DPG_COLOUR_G_Y_BASE_IDX 2 +#define regDPG3_DPG_COLOUR_B_CB 0x1967 +#define regDPG3_DPG_COLOUR_B_CB_BASE_IDX 2 +#define regDPG3_DPG_OFFSET_SEGMENT 0x1968 +#define regDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2 +#define regDPG3_DPG_STATUS 0x1969 +#define regDPG3_DPG_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +// base address: 0x438 +#define regOPPBUF3_OPPBUF_CONTROL 0x1992 +#define regOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 +#define regOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 +#define regOPPBUF3_OPPBUF_CONTROL1 0x1997 +#define regOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +// base address: 0x438 +#define regOPP_PIPE3_OPP_PIPE_CONTROL 0x1999 +#define regOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +// base address: 0x438 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199d +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x199e +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA 0x199f +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR 0x19a0 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG 0x19a1 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB 0x19a2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB_BASE_IDX 2 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC 0x19a3 +#define regOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_top_dispdec +// base address: 0x0 +#define regOPP_TOP_CLK_CONTROL 0x1a5e +#define regOPP_TOP_CLK_CONTROL_BASE_IDX 2 +#define regOPP_ABM_CONTROL 0x1a60 +#define regOPP_ABM_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +// base address: 0x0 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64 +#define regDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +// base address: 0x4 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65 +#define regDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +// base address: 0x8 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66 +#define regDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +// base address: 0xc +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67 +#define regDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2 + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +// base address: 0x6af8 +#define regDC_PERFMON14_PERFCOUNTER_CNTL 0x1abe +#define regDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON14_PERFCOUNTER_CNTL2 0x1abf +#define regDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON14_PERFCOUNTER_STATE 0x1ac0 +#define regDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CNTL 0x1ac1 +#define regDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CNTL2 0x1ac2 +#define regDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x1ac3 +#define regDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_CVALUE_LOW 0x1ac4 +#define regDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_HI 0x1ac5 +#define regDC_PERFMON14_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON14_PERFMON_LOW 0x1ac6 +#define regDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm0_dispdec +// base address: 0x0 +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca +#define regODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_RSMU_UNDERFLOW 0x1acb +#define regODM0_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 +#define regODM0_OPTC_UNDERFLOW_THRESHOLD 0x1acc +#define regODM0_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM0_OPTC_DATA_SOURCE_SELECT 0x1acd +#define regODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM0_OPTC_DATA_FORMAT_CONTROL 0x1ace +#define regODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_BYTES_PER_PIXEL 0x1acf +#define regODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL 0x1ad0 +#define regODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_WIDTH_CONTROL2 0x1ad1 +#define regODM0_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL 0x1ad2 +#define regODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM0_OPTC_MEMORY_CONFIG 0x1ad3 +#define regODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad4 +#define regODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm1_dispdec +// base address: 0x40 +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada +#define regODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_RSMU_UNDERFLOW 0x1adb +#define regODM1_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 +#define regODM1_OPTC_UNDERFLOW_THRESHOLD 0x1adc +#define regODM1_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM1_OPTC_DATA_SOURCE_SELECT 0x1add +#define regODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM1_OPTC_DATA_FORMAT_CONTROL 0x1ade +#define regODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_BYTES_PER_PIXEL 0x1adf +#define regODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL 0x1ae0 +#define regODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_WIDTH_CONTROL2 0x1ae1 +#define regODM1_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL 0x1ae2 +#define regODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM1_OPTC_MEMORY_CONFIG 0x1ae3 +#define regODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae4 +#define regODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm2_dispdec +// base address: 0x80 +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea +#define regODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_RSMU_UNDERFLOW 0x1aeb +#define regODM2_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 +#define regODM2_OPTC_UNDERFLOW_THRESHOLD 0x1aec +#define regODM2_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM2_OPTC_DATA_SOURCE_SELECT 0x1aed +#define regODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM2_OPTC_DATA_FORMAT_CONTROL 0x1aee +#define regODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_BYTES_PER_PIXEL 0x1aef +#define regODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL 0x1af0 +#define regODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_WIDTH_CONTROL2 0x1af1 +#define regODM2_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL 0x1af2 +#define regODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM2_OPTC_MEMORY_CONFIG 0x1af3 +#define regODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM2_OPTC_INPUT_SPARE_REGISTER 0x1af4 +#define regODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_odm3_dispdec +// base address: 0xc0 +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa +#define regODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_RSMU_UNDERFLOW 0x1afb +#define regODM3_OPTC_RSMU_UNDERFLOW_BASE_IDX 2 +#define regODM3_OPTC_UNDERFLOW_THRESHOLD 0x1afc +#define regODM3_OPTC_UNDERFLOW_THRESHOLD_BASE_IDX 2 +#define regODM3_OPTC_DATA_SOURCE_SELECT 0x1afd +#define regODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 +#define regODM3_OPTC_DATA_FORMAT_CONTROL 0x1afe +#define regODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_BYTES_PER_PIXEL 0x1aff +#define regODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL 0x1b00 +#define regODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_WIDTH_CONTROL2 0x1b01 +#define regODM3_OPTC_WIDTH_CONTROL2_BASE_IDX 2 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL 0x1b02 +#define regODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 +#define regODM3_OPTC_MEMORY_CONFIG 0x1b03 +#define regODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2 +#define regODM3_OPTC_INPUT_SPARE_REGISTER 0x1b04 +#define regODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg0_dispdec +// base address: 0x0 +#define regOTG0_OTG_H_TOTAL 0x1b2a +#define regOTG0_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_H_BLANK_START_END 0x1b2b +#define regOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A 0x1b2c +#define regOTG0_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_H_SYNC_A_CNTL 0x1b2d +#define regOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_H_TIMING_CNTL 0x1b2e +#define regOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL 0x1b2f +#define regOTG0_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MIN 0x1b30 +#define regOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MAX 0x1b31 +#define regOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_MID 0x1b32 +#define regOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_CONTROL 0x1b33 +#define regOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL 0x1b34 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL2 0x1b35 +#define regOTG0_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_V_TOTAL_INT_STATUS 0x1b36 +#define regOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b37 +#define regOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_V_BLANK_START_END 0x1b38 +#define regOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A 0x1b39 +#define regOTG0_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG0_OTG_V_SYNC_A_CNTL 0x1b3a +#define regOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_CNTL 0x1b3b +#define regOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3c +#define regOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_CNTL 0x1b3d +#define regOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3e +#define regOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3f +#define regOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b41 +#define regOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG0_OTG_CONTROL 0x1b43 +#define regOTG0_OTG_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DLPC_CONTROL 0x1b44 +#define regOTG0_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_PWA_FRAME_SYNC_CONTROL 0x1b45 +#define regOTG0_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_CONTROL 0x1b46 +#define regOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_INTERLACE_STATUS 0x1b47 +#define regOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK0 0x1b48 +#define regOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG0_OTG_PIXEL_DATA_READBACK1 0x1b49 +#define regOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG0_OTG_STATUS 0x1b4a +#define regOTG0_OTG_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STATUS_POSITION 0x1b4b +#define regOTG0_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG0_OTG_LONG_VBLANK_STATUS 0x1b4c +#define regOTG0_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG0_OTG_NOM_VERT_POSITION 0x1b4d +#define regOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_STATUS_FRAME_COUNT 0x1b4e +#define regOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_VF_COUNT 0x1b4f +#define regOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG0_OTG_STATUS_HV_COUNT 0x1b50 +#define regOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG0_OTG_COUNT_CONTROL 0x1b51 +#define regOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_COUNT_RESET 0x1b52 +#define regOTG0_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b53 +#define regOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG0_OTG_VERT_SYNC_CONTROL 0x1b54 +#define regOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_STEREO_STATUS 0x1b55 +#define regOTG0_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG0_OTG_STEREO_CONTROL 0x1b56 +#define regOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_STATUS 0x1b57 +#define regOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_CONTROL 0x1b58 +#define regOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_POSITION 0x1b59 +#define regOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG0_OTG_SNAPSHOT_FRAME 0x1b5a +#define regOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG0_OTG_INTERRUPT_CONTROL 0x1b5b +#define regOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_UPDATE_LOCK 0x1b5c +#define regOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5d +#define regOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_MASTER_EN 0x1b5e +#define regOTG0_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b60 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b61 +#define regOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b62 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b63 +#define regOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b64 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b65 +#define regOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC_CNTL 0x1b66 +#define regOTG0_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b67 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b68 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b69 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6a +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_R 0x1b6b +#define regOTG0_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_G 0x1b6c +#define regOTG0_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_B 0x1b6d +#define regOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_C 0x1b6e +#define regOTG0_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b6f +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b70 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b71 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b72 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_R 0x1b73 +#define regOTG0_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_G 0x1b74 +#define regOTG0_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_B 0x1b75 +#define regOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC1_DATA_C 0x1b76 +#define regOTG0_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_R 0x1b77 +#define regOTG0_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_G 0x1b78 +#define regOTG0_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_B 0x1b79 +#define regOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC2_DATA_C 0x1b7a +#define regOTG0_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_R 0x1b7b +#define regOTG0_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_G 0x1b7c +#define regOTG0_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_B 0x1b7d +#define regOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG0_OTG_CRC3_DATA_C 0x1b7e +#define regOTG0_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG0_OTG_CRC0_DATA_AES 0x1b7f +#define regOTG0_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b80 +#define regOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b81 +#define regOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1b82 +#define regOTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1b83 +#define regOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1b84 +#define regOTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1b85 +#define regOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1b86 +#define regOTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1b87 +#define regOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1b88 +#define regOTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1b89 +#define regOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b8a +#define regOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b8b +#define regOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_VSYNC_GAP 0x1b8c +#define regOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_MODE 0x1b8d +#define regOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG0_OTG_CLOCK_CONTROL 0x1b8e +#define regOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_VSTARTUP_PARAM 0x1b8f +#define regOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_PARAM 0x1b90 +#define regOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG0_OTG_VREADY_PARAM 0x1b91 +#define regOTG0_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b92 +#define regOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG0_OTG_MASTER_UPDATE_LOCK 0x1b93 +#define regOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG0_OTG_GSL_CONTROL 0x1b94 +#define regOTG0_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_X 0x1b95 +#define regOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG0_OTG_GSL_WINDOW_Y 0x1b96 +#define regOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG0_OTG_VUPDATE_KEEPOUT 0x1b97 +#define regOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL0 0x1b98 +#define regOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL1 0x1b99 +#define regOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL2 0x1b9a +#define regOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL3 0x1b9b +#define regOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG0_OTG_GLOBAL_CONTROL4 0x1b9c +#define regOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b9d +#define regOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b9f +#define regOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1ba0 +#define regOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1ba1 +#define regOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW 0x1ba2 +#define regOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTROL 0x1ba3 +#define regOTG0_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_DRR_CONTOL2 0x1ba4 +#define regOTG0_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO0 0x1ba5 +#define regOTG0_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG0_OTG_M_CONST_DTO1 0x1ba6 +#define regOTG0_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG0_OTG_REQUEST_CONTROL 0x1ba7 +#define regOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba8 +#define regOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG0_OTG_PSTATE_REGISTER 0x1ba9 +#define regOTG0_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG0_OTG_ENCRYPTION 0x1baa +#define regOTG0_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG0_OTG_SPARE_REGISTER 0x1bab +#define regOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg1_dispdec +// base address: 0x220 +#define regOTG1_OTG_H_TOTAL 0x1bb2 +#define regOTG1_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_H_BLANK_START_END 0x1bb3 +#define regOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A 0x1bb4 +#define regOTG1_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_H_SYNC_A_CNTL 0x1bb5 +#define regOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_H_TIMING_CNTL 0x1bb6 +#define regOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL 0x1bb7 +#define regOTG1_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MIN 0x1bb8 +#define regOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MAX 0x1bb9 +#define regOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_MID 0x1bba +#define regOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_CONTROL 0x1bbb +#define regOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_COUNT_STOP_CONTROL 0x1bbc +#define regOTG1_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_V_COUNT_STOP_CONTROL2 0x1bbd +#define regOTG1_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_V_TOTAL_INT_STATUS 0x1bbe +#define regOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bbf +#define regOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_V_BLANK_START_END 0x1bc0 +#define regOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A 0x1bc1 +#define regOTG1_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG1_OTG_V_SYNC_A_CNTL 0x1bc2 +#define regOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_CNTL 0x1bc3 +#define regOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bc4 +#define regOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_CNTL 0x1bc5 +#define regOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bc6 +#define regOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bc7 +#define regOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bc9 +#define regOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG1_OTG_CONTROL 0x1bcb +#define regOTG1_OTG_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DLPC_CONTROL 0x1bcc +#define regOTG1_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_PWA_FRAME_SYNC_CONTROL 0x1bcd +#define regOTG1_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_CONTROL 0x1bce +#define regOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_INTERLACE_STATUS 0x1bcf +#define regOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK0 0x1bd0 +#define regOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG1_OTG_PIXEL_DATA_READBACK1 0x1bd1 +#define regOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG1_OTG_STATUS 0x1bd2 +#define regOTG1_OTG_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STATUS_POSITION 0x1bd3 +#define regOTG1_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG1_OTG_LONG_VBLANK_STATUS 0x1bd4 +#define regOTG1_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG1_OTG_NOM_VERT_POSITION 0x1bd5 +#define regOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_STATUS_FRAME_COUNT 0x1bd6 +#define regOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_VF_COUNT 0x1bd7 +#define regOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG1_OTG_STATUS_HV_COUNT 0x1bd8 +#define regOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG1_OTG_COUNT_CONTROL 0x1bd9 +#define regOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_COUNT_RESET 0x1bda +#define regOTG1_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bdb +#define regOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG1_OTG_VERT_SYNC_CONTROL 0x1bdc +#define regOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_STEREO_STATUS 0x1bdd +#define regOTG1_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG1_OTG_STEREO_CONTROL 0x1bde +#define regOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_STATUS 0x1bdf +#define regOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_CONTROL 0x1be0 +#define regOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_POSITION 0x1be1 +#define regOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG1_OTG_SNAPSHOT_FRAME 0x1be2 +#define regOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG1_OTG_INTERRUPT_CONTROL 0x1be3 +#define regOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_UPDATE_LOCK 0x1be4 +#define regOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1be5 +#define regOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_MASTER_EN 0x1be6 +#define regOTG1_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be8 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be9 +#define regOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1bea +#define regOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1beb +#define regOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1bec +#define regOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bed +#define regOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC_CNTL 0x1bee +#define regOTG1_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bef +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bf0 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bf1 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bf2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_R 0x1bf3 +#define regOTG1_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_G 0x1bf4 +#define regOTG1_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_B 0x1bf5 +#define regOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_C 0x1bf6 +#define regOTG1_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf7 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf8 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf9 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bfa +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_R 0x1bfb +#define regOTG1_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_G 0x1bfc +#define regOTG1_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_B 0x1bfd +#define regOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC1_DATA_C 0x1bfe +#define regOTG1_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_R 0x1bff +#define regOTG1_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_G 0x1c00 +#define regOTG1_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_B 0x1c01 +#define regOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC2_DATA_C 0x1c02 +#define regOTG1_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_R 0x1c03 +#define regOTG1_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_G 0x1c04 +#define regOTG1_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_B 0x1c05 +#define regOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG1_OTG_CRC3_DATA_C 0x1c06 +#define regOTG1_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG1_OTG_CRC0_DATA_AES 0x1c07 +#define regOTG1_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1c08 +#define regOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c09 +#define regOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c0a +#define regOTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c0b +#define regOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c0c +#define regOTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c0d +#define regOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c0e +#define regOTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c0f +#define regOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c10 +#define regOTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c11 +#define regOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c12 +#define regOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c13 +#define regOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_VSYNC_GAP 0x1c14 +#define regOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_MODE 0x1c15 +#define regOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG1_OTG_CLOCK_CONTROL 0x1c16 +#define regOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_VSTARTUP_PARAM 0x1c17 +#define regOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_PARAM 0x1c18 +#define regOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG1_OTG_VREADY_PARAM 0x1c19 +#define regOTG1_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c1a +#define regOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG1_OTG_MASTER_UPDATE_LOCK 0x1c1b +#define regOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG1_OTG_GSL_CONTROL 0x1c1c +#define regOTG1_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_X 0x1c1d +#define regOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG1_OTG_GSL_WINDOW_Y 0x1c1e +#define regOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG1_OTG_VUPDATE_KEEPOUT 0x1c1f +#define regOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL0 0x1c20 +#define regOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL1 0x1c21 +#define regOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL2 0x1c22 +#define regOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL3 0x1c23 +#define regOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG1_OTG_GLOBAL_CONTROL4 0x1c24 +#define regOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c25 +#define regOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c27 +#define regOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c28 +#define regOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c29 +#define regOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c2a +#define regOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTROL 0x1c2b +#define regOTG1_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_DRR_CONTOL2 0x1c2c +#define regOTG1_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO0 0x1c2d +#define regOTG1_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG1_OTG_M_CONST_DTO1 0x1c2e +#define regOTG1_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG1_OTG_REQUEST_CONTROL 0x1c2f +#define regOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG1_OTG_PIPE_UPDATE_STATUS 0x1c30 +#define regOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG1_OTG_PSTATE_REGISTER 0x1c31 +#define regOTG1_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG1_OTG_ENCRYPTION 0x1c32 +#define regOTG1_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG1_OTG_SPARE_REGISTER 0x1c33 +#define regOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg2_dispdec +// base address: 0x440 +#define regOTG2_OTG_H_TOTAL 0x1c3a +#define regOTG2_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_H_BLANK_START_END 0x1c3b +#define regOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A 0x1c3c +#define regOTG2_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_H_SYNC_A_CNTL 0x1c3d +#define regOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_H_TIMING_CNTL 0x1c3e +#define regOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL 0x1c3f +#define regOTG2_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MIN 0x1c40 +#define regOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MAX 0x1c41 +#define regOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_MID 0x1c42 +#define regOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_CONTROL 0x1c43 +#define regOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL 0x1c44 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL2 0x1c45 +#define regOTG2_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_V_TOTAL_INT_STATUS 0x1c46 +#define regOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c47 +#define regOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_V_BLANK_START_END 0x1c48 +#define regOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A 0x1c49 +#define regOTG2_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG2_OTG_V_SYNC_A_CNTL 0x1c4a +#define regOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_CNTL 0x1c4b +#define regOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c4c +#define regOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_CNTL 0x1c4d +#define regOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c4e +#define regOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c4f +#define regOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c51 +#define regOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG2_OTG_CONTROL 0x1c53 +#define regOTG2_OTG_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DLPC_CONTROL 0x1c54 +#define regOTG2_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_PWA_FRAME_SYNC_CONTROL 0x1c55 +#define regOTG2_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_CONTROL 0x1c56 +#define regOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_INTERLACE_STATUS 0x1c57 +#define regOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK0 0x1c58 +#define regOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG2_OTG_PIXEL_DATA_READBACK1 0x1c59 +#define regOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG2_OTG_STATUS 0x1c5a +#define regOTG2_OTG_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STATUS_POSITION 0x1c5b +#define regOTG2_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG2_OTG_LONG_VBLANK_STATUS 0x1c5c +#define regOTG2_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG2_OTG_NOM_VERT_POSITION 0x1c5d +#define regOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_STATUS_FRAME_COUNT 0x1c5e +#define regOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_VF_COUNT 0x1c5f +#define regOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG2_OTG_STATUS_HV_COUNT 0x1c60 +#define regOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG2_OTG_COUNT_CONTROL 0x1c61 +#define regOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_COUNT_RESET 0x1c62 +#define regOTG2_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c63 +#define regOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG2_OTG_VERT_SYNC_CONTROL 0x1c64 +#define regOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_STEREO_STATUS 0x1c65 +#define regOTG2_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG2_OTG_STEREO_CONTROL 0x1c66 +#define regOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_STATUS 0x1c67 +#define regOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_CONTROL 0x1c68 +#define regOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_POSITION 0x1c69 +#define regOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG2_OTG_SNAPSHOT_FRAME 0x1c6a +#define regOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG2_OTG_INTERRUPT_CONTROL 0x1c6b +#define regOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_UPDATE_LOCK 0x1c6c +#define regOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c6d +#define regOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_MASTER_EN 0x1c6e +#define regOTG2_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c70 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c71 +#define regOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c72 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c73 +#define regOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c74 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c75 +#define regOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC_CNTL 0x1c76 +#define regOTG2_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c77 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c78 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c79 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c7a +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_R 0x1c7b +#define regOTG2_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_G 0x1c7c +#define regOTG2_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_B 0x1c7d +#define regOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_C 0x1c7e +#define regOTG2_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c7f +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c80 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c81 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c82 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_R 0x1c83 +#define regOTG2_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_G 0x1c84 +#define regOTG2_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_B 0x1c85 +#define regOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC1_DATA_C 0x1c86 +#define regOTG2_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_R 0x1c87 +#define regOTG2_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_G 0x1c88 +#define regOTG2_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_B 0x1c89 +#define regOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC2_DATA_C 0x1c8a +#define regOTG2_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_R 0x1c8b +#define regOTG2_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_G 0x1c8c +#define regOTG2_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_B 0x1c8d +#define regOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG2_OTG_CRC3_DATA_C 0x1c8e +#define regOTG2_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG2_OTG_CRC0_DATA_AES 0x1c8f +#define regOTG2_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c90 +#define regOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c91 +#define regOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1c92 +#define regOTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1c93 +#define regOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1c94 +#define regOTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1c95 +#define regOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1c96 +#define regOTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1c97 +#define regOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1c98 +#define regOTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1c99 +#define regOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c9a +#define regOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c9b +#define regOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_VSYNC_GAP 0x1c9c +#define regOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_MODE 0x1c9d +#define regOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG2_OTG_CLOCK_CONTROL 0x1c9e +#define regOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_VSTARTUP_PARAM 0x1c9f +#define regOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_PARAM 0x1ca0 +#define regOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG2_OTG_VREADY_PARAM 0x1ca1 +#define regOTG2_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS 0x1ca2 +#define regOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG2_OTG_MASTER_UPDATE_LOCK 0x1ca3 +#define regOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG2_OTG_GSL_CONTROL 0x1ca4 +#define regOTG2_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_X 0x1ca5 +#define regOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG2_OTG_GSL_WINDOW_Y 0x1ca6 +#define regOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG2_OTG_VUPDATE_KEEPOUT 0x1ca7 +#define regOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL0 0x1ca8 +#define regOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL1 0x1ca9 +#define regOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL2 0x1caa +#define regOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL3 0x1cab +#define regOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG2_OTG_GLOBAL_CONTROL4 0x1cac +#define regOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG2_OTG_TRIG_MANUAL_CONTROL 0x1cad +#define regOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_TIMING_INT_STATUS 0x1caf +#define regOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1cb0 +#define regOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1cb1 +#define regOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW 0x1cb2 +#define regOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTROL 0x1cb3 +#define regOTG2_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_DRR_CONTOL2 0x1cb4 +#define regOTG2_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO0 0x1cb5 +#define regOTG2_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG2_OTG_M_CONST_DTO1 0x1cb6 +#define regOTG2_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG2_OTG_REQUEST_CONTROL 0x1cb7 +#define regOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG2_OTG_PIPE_UPDATE_STATUS 0x1cb8 +#define regOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG2_OTG_PSTATE_REGISTER 0x1cb9 +#define regOTG2_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG2_OTG_ENCRYPTION 0x1cba +#define regOTG2_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG2_OTG_SPARE_REGISTER 0x1cbb +#define regOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_otg3_dispdec +// base address: 0x660 +#define regOTG3_OTG_H_TOTAL 0x1cc2 +#define regOTG3_OTG_H_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_H_BLANK_START_END 0x1cc3 +#define regOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A 0x1cc4 +#define regOTG3_OTG_H_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_H_SYNC_A_CNTL 0x1cc5 +#define regOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_H_TIMING_CNTL 0x1cc6 +#define regOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL 0x1cc7 +#define regOTG3_OTG_V_TOTAL_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MIN 0x1cc8 +#define regOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MAX 0x1cc9 +#define regOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_MID 0x1cca +#define regOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_CONTROL 0x1ccb +#define regOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_COUNT_STOP_CONTROL 0x1ccc +#define regOTG3_OTG_V_COUNT_STOP_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_V_COUNT_STOP_CONTROL2 0x1ccd +#define regOTG3_OTG_V_COUNT_STOP_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_V_TOTAL_INT_STATUS 0x1cce +#define regOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1ccf +#define regOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_V_BLANK_START_END 0x1cd0 +#define regOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A 0x1cd1 +#define regOTG3_OTG_V_SYNC_A_BASE_IDX 2 +#define regOTG3_OTG_V_SYNC_A_CNTL 0x1cd2 +#define regOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_CNTL 0x1cd3 +#define regOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cd4 +#define regOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_CNTL 0x1cd5 +#define regOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cd6 +#define regOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cd7 +#define regOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cd9 +#define regOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 +#define regOTG3_OTG_CONTROL 0x1cdb +#define regOTG3_OTG_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DLPC_CONTROL 0x1cdc +#define regOTG3_OTG_DLPC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_PWA_FRAME_SYNC_CONTROL 0x1cdd +#define regOTG3_OTG_PWA_FRAME_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_CONTROL 0x1cde +#define regOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_INTERLACE_STATUS 0x1cdf +#define regOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK0 0x1ce0 +#define regOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 +#define regOTG3_OTG_PIXEL_DATA_READBACK1 0x1ce1 +#define regOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 +#define regOTG3_OTG_STATUS 0x1ce2 +#define regOTG3_OTG_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STATUS_POSITION 0x1ce3 +#define regOTG3_OTG_STATUS_POSITION_BASE_IDX 2 +#define regOTG3_OTG_LONG_VBLANK_STATUS 0x1ce4 +#define regOTG3_OTG_LONG_VBLANK_STATUS_BASE_IDX 2 +#define regOTG3_OTG_NOM_VERT_POSITION 0x1ce5 +#define regOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_STATUS_FRAME_COUNT 0x1ce6 +#define regOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_VF_COUNT 0x1ce7 +#define regOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 +#define regOTG3_OTG_STATUS_HV_COUNT 0x1ce8 +#define regOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2 +#define regOTG3_OTG_COUNT_CONTROL 0x1ce9 +#define regOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_COUNT_RESET 0x1cea +#define regOTG3_OTG_COUNT_RESET_BASE_IDX 2 +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1ceb +#define regOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 +#define regOTG3_OTG_VERT_SYNC_CONTROL 0x1cec +#define regOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_STEREO_STATUS 0x1ced +#define regOTG3_OTG_STEREO_STATUS_BASE_IDX 2 +#define regOTG3_OTG_STEREO_CONTROL 0x1cee +#define regOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_STATUS 0x1cef +#define regOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_CONTROL 0x1cf0 +#define regOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_POSITION 0x1cf1 +#define regOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 +#define regOTG3_OTG_SNAPSHOT_FRAME 0x1cf2 +#define regOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 +#define regOTG3_OTG_INTERRUPT_CONTROL 0x1cf3 +#define regOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_UPDATE_LOCK 0x1cf4 +#define regOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cf5 +#define regOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_MASTER_EN 0x1cf6 +#define regOTG3_OTG_MASTER_EN_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1cf8 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1cf9 +#define regOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1cfa +#define regOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1cfb +#define regOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1cfc +#define regOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cfd +#define regOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC_CNTL 0x1cfe +#define regOTG3_OTG_CRC_CNTL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cff +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d00 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1d01 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d02 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_R 0x1d03 +#define regOTG3_OTG_CRC0_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_G 0x1d04 +#define regOTG3_OTG_CRC0_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_B 0x1d05 +#define regOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_C 0x1d06 +#define regOTG3_OTG_CRC0_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1d07 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d08 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1d09 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d0a +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_R 0x1d0b +#define regOTG3_OTG_CRC1_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_G 0x1d0c +#define regOTG3_OTG_CRC1_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_B 0x1d0d +#define regOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC1_DATA_C 0x1d0e +#define regOTG3_OTG_CRC1_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_R 0x1d0f +#define regOTG3_OTG_CRC2_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_G 0x1d10 +#define regOTG3_OTG_CRC2_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_B 0x1d11 +#define regOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC2_DATA_C 0x1d12 +#define regOTG3_OTG_CRC2_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_R 0x1d13 +#define regOTG3_OTG_CRC3_DATA_R_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_G 0x1d14 +#define regOTG3_OTG_CRC3_DATA_G_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_B 0x1d15 +#define regOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 +#define regOTG3_OTG_CRC3_DATA_C 0x1d16 +#define regOTG3_OTG_CRC3_DATA_C_BASE_IDX 2 +#define regOTG3_OTG_CRC0_DATA_AES 0x1d17 +#define regOTG3_OTG_CRC0_DATA_AES_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1d18 +#define regOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d19 +#define regOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK 0x1d1a +#define regOTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK 0x1d1b +#define regOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK 0x1d1c +#define regOTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK 0x1d1d +#define regOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK 0x1d1e +#define regOTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK 0x1d1f +#define regOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK 0x1d20 +#define regOTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK 0x1d21 +#define regOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK_BASE_IDX 2 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d22 +#define regOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d23 +#define regOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_VSYNC_GAP 0x1d24 +#define regOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_MODE 0x1d25 +#define regOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 +#define regOTG3_OTG_CLOCK_CONTROL 0x1d26 +#define regOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_VSTARTUP_PARAM 0x1d27 +#define regOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_PARAM 0x1d28 +#define regOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 +#define regOTG3_OTG_VREADY_PARAM 0x1d29 +#define regOTG3_OTG_VREADY_PARAM_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d2a +#define regOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 +#define regOTG3_OTG_MASTER_UPDATE_LOCK 0x1d2b +#define regOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 +#define regOTG3_OTG_GSL_CONTROL 0x1d2c +#define regOTG3_OTG_GSL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_X 0x1d2d +#define regOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 +#define regOTG3_OTG_GSL_WINDOW_Y 0x1d2e +#define regOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 +#define regOTG3_OTG_VUPDATE_KEEPOUT 0x1d2f +#define regOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL0 0x1d30 +#define regOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL1 0x1d31 +#define regOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL2 0x1d32 +#define regOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL3 0x1d33 +#define regOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 +#define regOTG3_OTG_GLOBAL_CONTROL4 0x1d34 +#define regOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d35 +#define regOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d37 +#define regOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d38 +#define regOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d39 +#define regOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2 +#define regOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d3a +#define regOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTROL 0x1d3b +#define regOTG3_OTG_DRR_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_DRR_CONTOL2 0x1d3c +#define regOTG3_OTG_DRR_CONTOL2_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO0 0x1d3d +#define regOTG3_OTG_M_CONST_DTO0_BASE_IDX 2 +#define regOTG3_OTG_M_CONST_DTO1 0x1d3e +#define regOTG3_OTG_M_CONST_DTO1_BASE_IDX 2 +#define regOTG3_OTG_REQUEST_CONTROL 0x1d3f +#define regOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 +#define regOTG3_OTG_PIPE_UPDATE_STATUS 0x1d40 +#define regOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2 +#define regOTG3_OTG_PSTATE_REGISTER 0x1d41 +#define regOTG3_OTG_PSTATE_REGISTER_BASE_IDX 2 +#define regOTG3_OTG_ENCRYPTION 0x1d42 +#define regOTG3_OTG_ENCRYPTION_BASE_IDX 2 +#define regOTG3_OTG_SPARE_REGISTER 0x1d43 +#define regOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +// base address: 0x0 +#define regGSL_SOURCE_SELECT 0x1e2b +#define regGSL_SOURCE_SELECT_BASE_IDX 2 +#define regOPTC_DLPC_CONTROL 0x1e2c +#define regOPTC_DLPC_CONTROL_BASE_IDX 2 +#define regOPTC_CLOCK_CONTROL 0x1e2d +#define regOPTC_CLOCK_CONTROL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL 0x1e2e +#define regODM_MEM_PWR_CTRL_BASE_IDX 2 +#define regODM_MEM_PWR_CTRL3 0x1e30 +#define regODM_MEM_PWR_CTRL3_BASE_IDX 2 +#define regODM_MEM_PWR_STATUS 0x1e31 +#define regODM_MEM_PWR_STATUS_BASE_IDX 2 +#define regOPTC_MISC_SPARE_REGISTER 0x1e32 +#define regOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +// base address: 0x79a8 +#define regDC_PERFMON15_PERFCOUNTER_CNTL 0x1e6a +#define regDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON15_PERFCOUNTER_CNTL2 0x1e6b +#define regDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON15_PERFCOUNTER_STATE 0x1e6c +#define regDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CNTL 0x1e6d +#define regDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CNTL2 0x1e6e +#define regDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x1e6f +#define regDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_CVALUE_LOW 0x1e70 +#define regDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_HI 0x1e71 +#define regDC_PERFMON15_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON15_PERFMON_LOW 0x1e72 +#define regDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +// base address: 0x0 +#define regDC_I2C_CONTROL 0x1e98 +#define regDC_I2C_CONTROL_BASE_IDX 2 +#define regDC_I2C_ARBITRATION 0x1e99 +#define regDC_I2C_ARBITRATION_BASE_IDX 2 +#define regDC_I2C_INTERRUPT_CONTROL 0x1e9a +#define regDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDC_I2C_SW_STATUS 0x1e9b +#define regDC_I2C_SW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_HW_STATUS 0x1e9c +#define regDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC2_HW_STATUS 0x1e9d +#define regDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC3_HW_STATUS 0x1e9e +#define regDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC4_HW_STATUS 0x1e9f +#define regDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC5_HW_STATUS 0x1ea0 +#define regDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 +#define regDC_I2C_DDC1_SPEED 0x1ea2 +#define regDC_I2C_DDC1_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC1_SETUP 0x1ea3 +#define regDC_I2C_DDC1_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC2_SPEED 0x1ea4 +#define regDC_I2C_DDC2_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC2_SETUP 0x1ea5 +#define regDC_I2C_DDC2_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC3_SPEED 0x1ea6 +#define regDC_I2C_DDC3_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC3_SETUP 0x1ea7 +#define regDC_I2C_DDC3_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC4_SPEED 0x1ea8 +#define regDC_I2C_DDC4_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC4_SETUP 0x1ea9 +#define regDC_I2C_DDC4_SETUP_BASE_IDX 2 +#define regDC_I2C_DDC5_SPEED 0x1eaa +#define regDC_I2C_DDC5_SPEED_BASE_IDX 2 +#define regDC_I2C_DDC5_SETUP 0x1eab +#define regDC_I2C_DDC5_SETUP_BASE_IDX 2 +#define regDC_I2C_TRANSACTION0 0x1eae +#define regDC_I2C_TRANSACTION0_BASE_IDX 2 +#define regDC_I2C_TRANSACTION1 0x1eaf +#define regDC_I2C_TRANSACTION1_BASE_IDX 2 +#define regDC_I2C_TRANSACTION2 0x1eb0 +#define regDC_I2C_TRANSACTION2_BASE_IDX 2 +#define regDC_I2C_TRANSACTION3 0x1eb1 +#define regDC_I2C_TRANSACTION3_BASE_IDX 2 +#define regDC_I2C_DATA 0x1eb2 +#define regDC_I2C_DATA_BASE_IDX 2 +#define regDC_I2C_EDID_DETECT_CTRL 0x1eb6 +#define regDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 +#define regDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 +#define regDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +// base address: 0x0 +#define regDIO_SCRATCH0 0x1eca +#define regDIO_SCRATCH0_BASE_IDX 2 +#define regDIO_SCRATCH1 0x1ecb +#define regDIO_SCRATCH1_BASE_IDX 2 +#define regDIO_SCRATCH2 0x1ecc +#define regDIO_SCRATCH2_BASE_IDX 2 +#define regDIO_SCRATCH3 0x1ecd +#define regDIO_SCRATCH3_BASE_IDX 2 +#define regDIO_SCRATCH4 0x1ece +#define regDIO_SCRATCH4_BASE_IDX 2 +#define regDIO_SCRATCH5 0x1ecf +#define regDIO_SCRATCH5_BASE_IDX 2 +#define regDIO_SCRATCH6 0x1ed0 +#define regDIO_SCRATCH6_BASE_IDX 2 +#define regDIO_SCRATCH7 0x1ed1 +#define regDIO_SCRATCH7_BASE_IDX 2 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS 0x1ed3 +#define regDIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_STATUS 0x1edd +#define regDIO_MEM_PWR_STATUS_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL 0x1ede +#define regDIO_MEM_PWR_CTRL_BASE_IDX 2 +#define regDIO_MEM_PWR_CTRL2 0x1edf +#define regDIO_MEM_PWR_CTRL2_BASE_IDX 2 +#define regDIO_CLK_CNTL 0x1ee0 +#define regDIO_CLK_CNTL_BASE_IDX 2 +#define regDIO_POWER_MANAGEMENT_CNTL 0x1ee4 +#define regDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff +#define regDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 +#define regDIO_PSP_INTERRUPT_STATUS 0x1f00 +#define regDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 +#define regDIO_PSP_INTERRUPT_CLEAR 0x1f01 +#define regDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 +#define regDIO_STATUS 0x1f02 +#define regDIO_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec +// base address: 0x0 +#define regDIG0_STREAM_MAPPER_CONTROL 0x1f0d +#define regDIG0_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG1_STREAM_MAPPER_CONTROL 0x1f0e +#define regDIG1_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG2_STREAM_MAPPER_CONTROL 0x1f0f +#define regDIG2_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG3_STREAM_MAPPER_CONTROL 0x1f10 +#define regDIG3_STREAM_MAPPER_CONTROL_BASE_IDX 2 +#define regDIG4_STREAM_MAPPER_CONTROL 0x1f11 +#define regDIG4_STREAM_MAPPER_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +// base address: 0x7d10 +#define regDC_PERFMON16_PERFCOUNTER_CNTL 0x1f44 +#define regDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON16_PERFCOUNTER_CNTL2 0x1f45 +#define regDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON16_PERFCOUNTER_STATE 0x1f46 +#define regDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CNTL 0x1f47 +#define regDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CNTL2 0x1f48 +#define regDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1f49 +#define regDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_CVALUE_LOW 0x1f4a +#define regDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_HI 0x1f4b +#define regDC_PERFMON16_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON16_PERFMON_LOW 0x1f4c +#define regDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +// base address: 0x154a0 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068 +#define regVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_PACKET_DATA 0x2069 +#define regVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a +#define regVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b +#define regVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG0_VPG_GENERIC_STATUS 0x206c +#define regVPG0_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG0_VPG_MEM_PWR 0x206d +#define regVPG0_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e +#define regVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG0_VPG_ISRC1_2_DATA 0x206f +#define regVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_apg_apg_dispdec +// base address: 0x154cc +#define regAPG0_APG_CONTROL 0x2073 +#define regAPG0_APG_CONTROL_BASE_IDX 2 +#define regAPG0_APG_CONTROL2 0x2074 +#define regAPG0_APG_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_GEN_CONTROL 0x2075 +#define regAPG0_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG0_APG_PACKET_CONTROL 0x2076 +#define regAPG0_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG0_APG_DBG_ACP 0x2077 +#define regAPG0_APG_DBG_ACP_BASE_IDX 2 +#define regAPG0_APG_DBG_AUDIO_INFO 0x2079 +#define regAPG0_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG0_APG_DBG_60958_0 0x207a +#define regAPG0_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG0_APG_DBG_60958_1 0x207b +#define regAPG0_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG0_APG_DBG_60958_2 0x207c +#define regAPG0_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL 0x207d +#define regAPG0_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_CONTROL2 0x207e +#define regAPG0_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_AUDIO_CRC_RESULT 0x207f +#define regAPG0_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL0 0x2080 +#define regAPG0_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL1 0x2081 +#define regAPG0_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL2 0x2082 +#define regAPG0_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG0_APG_DBG_RAMP_CONTROL3 0x2083 +#define regAPG0_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG0_APG_STATUS 0x2084 +#define regAPG0_APG_STATUS_BASE_IDX 2 +#define regAPG0_APG_STATUS2 0x2085 +#define regAPG0_APG_STATUS2_BASE_IDX 2 +#define regAPG0_APG_DBG_AUDIO_DTO_CNTL 0x2086 +#define regAPG0_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG0_APG_MEM_PWR 0x2087 +#define regAPG0_APG_MEM_PWR_BASE_IDX 2 +#define regAPG0_APG_SPARE 0x2089 +#define regAPG0_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +// base address: 0x15544 +#define regDME0_DME_CONTROL 0x2091 +#define regDME0_DME_CONTROL_BASE_IDX 2 +#define regDME0_DME_MEMORY_CONTROL 0x2092 +#define regDME0_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig0_dispdec +// base address: 0x0 +#define regDIG0_DIG_FE_CNTL 0x2093 +#define regDIG0_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_FE_CLK_CNTL 0x2094 +#define regDIG0_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG0_DIG_FE_EN_CNTL 0x2095 +#define regDIG0_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_CNTL 0x2096 +#define regDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG0_DIG_OUTPUT_CRC_RESULT 0x2097 +#define regDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG0_DIG_CLOCK_PATTERN 0x2098 +#define regDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_TEST_PATTERN 0x2099 +#define regDIG0_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG0_DIG_RANDOM_PATTERN_SEED 0x209a +#define regDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL0 0x209b +#define regDIG0_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG0_DIG_FIFO_CTRL1 0x209c +#define regDIG0_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG0_HDMI_METADATA_PACKET_CONTROL 0x209d +#define regDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_CONTROL 0x209e +#define regDIG0_HDMI_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_STATUS 0x209f +#define regDIG0_HDMI_STATUS_BASE_IDX 2 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL 0x20a0 +#define regDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_PACKET_CONTROL 0x20a1 +#define regDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL 0x20a2 +#define regDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_INFOFRAME_CONTROL0 0x20a3 +#define regDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x20a4 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x20a5 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20a6 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG0_HDMI_GC 0x20a7 +#define regDIG0_HDMI_GC_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x20a8 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x20a9 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20aa +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20ab +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20ac +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20ad +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20ae +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20af +#define regDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG0_HDMI_DB_CONTROL 0x20b0 +#define regDIG0_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_0 0x20b1 +#define regDIG0_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_32_1 0x20b2 +#define regDIG0_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_0 0x20b3 +#define regDIG0_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_44_1 0x20b4 +#define regDIG0_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_0 0x20b5 +#define regDIG0_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_48_1 0x20b6 +#define regDIG0_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_0 0x20b7 +#define regDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG0_HDMI_ACR_STATUS_1 0x20b8 +#define regDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG0_DIG_FE_AUDIO_CNTL 0x20b9 +#define regDIG0_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CLK_CNTL 0x20ba +#define regDIG0_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_CNTL 0x20bb +#define regDIG0_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG0_DIG_BE_EN_CNTL 0x20bc +#define regDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CNTL 0x20e3 +#define regDIG0_TMDS_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL_CHAR 0x20e4 +#define regDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CONTROL0_FEEDBACK 0x20e5 +#define regDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20e6 +#define regDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20e7 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20e8 +#define regDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG0_TMDS_CTL_BITS 0x20ea +#define regDIG0_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG0_TMDS_DCBALANCER_CONTROL 0x20eb +#define regDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20ec +#define regDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG0_TMDS_CTL0_1_GEN_CNTL 0x20ed +#define regDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG0_TMDS_CTL2_3_GEN_CNTL 0x20ee +#define regDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG0_DIG_VERSION 0x20f0 +#define regDIG0_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp0_dispdec +// base address: 0x0 +#define regDP0_DP_LINK_CNTL 0x211e +#define regDP0_DP_LINK_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT 0x211f +#define regDP0_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP0_DP_MSA_COLORIMETRY 0x2120 +#define regDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP0_DP_CONFIG 0x2121 +#define regDP0_DP_CONFIG_BASE_IDX 2 +#define regDP0_DP_VID_STREAM_CNTL 0x2122 +#define regDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO 0x2123 +#define regDP0_DP_STEER_FIFO_BASE_IDX 2 +#define regDP0_DP_MSA_MISC 0x2124 +#define regDP0_DP_MSA_MISC_BASE_IDX 2 +#define regDP0_DP_DPHY_INTERNAL_CTRL 0x2125 +#define regDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP0_DP_VID_TIMING 0x2126 +#define regDP0_DP_VID_TIMING_BASE_IDX 2 +#define regDP0_DP_VID_N 0x2127 +#define regDP0_DP_VID_N_BASE_IDX 2 +#define regDP0_DP_VID_M 0x2128 +#define regDP0_DP_VID_M_BASE_IDX 2 +#define regDP0_DP_LINK_FRAMING_CNTL 0x2129 +#define regDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP0_DP_HBR2_EYE_PATTERN 0x212a +#define regDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP0_DP_VID_MSA_VBID 0x212b +#define regDP0_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP0_DP_VID_INTERRUPT_CNTL 0x212c +#define regDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CNTL 0x212d +#define regDP0_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x212e +#define regDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM0 0x212f +#define regDP0_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM1 0x2130 +#define regDP0_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP0_DP_DPHY_SYM2 0x2131 +#define regDP0_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP0_DP_DPHY_8B10B_CNTL 0x2132 +#define regDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_PRBS_CNTL 0x2133 +#define regDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_SCRAM_CNTL 0x2134 +#define regDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CONTROL0 0x2135 +#define regDP0_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_CONTROL1 0x2136 +#define regDP0_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT0 0x2137 +#define regDP0_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT1 0x2138 +#define regDP0_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT2 0x2139 +#define regDP0_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_RESULT3 0x213a +#define regDP0_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP0_DP_DPHY_CRC_STATUS 0x213b +#define regDP0_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP0_DP_TU_CNTL 0x213c +#define regDP0_DP_TU_CNTL_BASE_IDX 2 +#define regDP0_DP_PIXEL_FORMAT_DB_CNTL 0x213d +#define regDP0_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL 0x2141 +#define regDP0_DP_SEC_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL1 0x2142 +#define regDP0_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING1 0x2143 +#define regDP0_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING2 0x2144 +#define regDP0_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING3 0x2145 +#define regDP0_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP0_DP_SEC_FRAMING4 0x2146 +#define regDP0_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N 0x2147 +#define regDP0_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_N_READBACK 0x2148 +#define regDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M 0x2149 +#define regDP0_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP0_DP_SEC_AUD_M_READBACK 0x214a +#define regDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP0_DP_SEC_TIMESTAMP 0x214b +#define regDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP0_DP_SEC_PACKET_CNTL 0x214c +#define regDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_CNTL 0x214d +#define regDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP0_DP_MSE_RATE_UPDATE 0x214f +#define regDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0 0x2150 +#define regDP0_DP_MSE_SAT0_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1 0x2151 +#define regDP0_DP_MSE_SAT1_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2 0x2152 +#define regDP0_DP_MSE_SAT2_BASE_IDX 2 +#define regDP0_DP_MSE_SAT_UPDATE 0x2153 +#define regDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP0_DP_MSE_LINK_TIMING 0x2154 +#define regDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP0_DP_MSE_MISC_CNTL 0x2155 +#define regDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x215a +#define regDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x215b +#define regDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSE_SAT0_STATUS 0x215d +#define regDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT1_STATUS 0x215e +#define regDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP0_DP_MSE_SAT2_STATUS 0x215f +#define regDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP0_DP_HBLANK_CONTROL 0x2161 +#define regDP0_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM1 0x2162 +#define regDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM2 0x2163 +#define regDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM3 0x2164 +#define regDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP0_DP_MSA_TIMING_PARAM4 0x2165 +#define regDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL 0x2166 +#define regDP0_DP_MSO_CNTL_BASE_IDX 2 +#define regDP0_DP_MSO_CNTL1 0x2167 +#define regDP0_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP0_DP_STEER_FIFO_CNTL 0x2168 +#define regDP0_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL2 0x2169 +#define regDP0_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL3 0x216a +#define regDP0_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL4 0x216b +#define regDP0_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL5 0x216c +#define regDP0_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL6 0x216d +#define regDP0_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP0_DP_SEC_CNTL7 0x216e +#define regDP0_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP0_DP_DB_CNTL 0x216f +#define regDP0_DP_DB_CNTL_BASE_IDX 2 +#define regDP0_DP_MSA_VBID_MISC 0x2170 +#define regDP0_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP0_DP_SEC_METADATA_TRANSMISSION 0x2171 +#define regDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP0_DP_ALPM_CNTL 0x2173 +#define regDP0_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP8_CNTL 0x2174 +#define regDP0_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP9_CNTL 0x2175 +#define regDP0_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP10_CNTL 0x2176 +#define regDP0_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP11_CNTL 0x2177 +#define regDP0_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP0_DP_GSP_EN_DB_STATUS 0x2178 +#define regDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL1 0x2179 +#define regDP0_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL2 0x217a +#define regDP0_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL3 0x217b +#define regDP0_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL4 0x217c +#define regDP0_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP0_DP_AUXLESS_ALPM_CNTL5 0x217d +#define regDP0_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS 0x217e +#define regDP0_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL 0x217f +#define regDP0_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0 0x2180 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1 0x2181 +#define regDP0_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL 0x2182 +#define regDP0_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x2183 +#define regDP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING 0x2186 +#define regDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2187 +#define regDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +// base address: 0x15930 +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x218c +#define regVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_PACKET_DATA 0x218d +#define regVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x218e +#define regVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x218f +#define regVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG1_VPG_GENERIC_STATUS 0x2190 +#define regVPG1_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG1_VPG_MEM_PWR 0x2191 +#define regVPG1_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x2192 +#define regVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG1_VPG_ISRC1_2_DATA 0x2193 +#define regVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_apg_apg_dispdec +// base address: 0x1595c +#define regAPG1_APG_CONTROL 0x2197 +#define regAPG1_APG_CONTROL_BASE_IDX 2 +#define regAPG1_APG_CONTROL2 0x2198 +#define regAPG1_APG_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_GEN_CONTROL 0x2199 +#define regAPG1_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG1_APG_PACKET_CONTROL 0x219a +#define regAPG1_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG1_APG_DBG_ACP 0x219b +#define regAPG1_APG_DBG_ACP_BASE_IDX 2 +#define regAPG1_APG_DBG_AUDIO_INFO 0x219d +#define regAPG1_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG1_APG_DBG_60958_0 0x219e +#define regAPG1_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG1_APG_DBG_60958_1 0x219f +#define regAPG1_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG1_APG_DBG_60958_2 0x21a0 +#define regAPG1_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL 0x21a1 +#define regAPG1_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2 0x21a2 +#define regAPG1_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_AUDIO_CRC_RESULT 0x21a3 +#define regAPG1_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL0 0x21a4 +#define regAPG1_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL1 0x21a5 +#define regAPG1_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL2 0x21a6 +#define regAPG1_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG1_APG_DBG_RAMP_CONTROL3 0x21a7 +#define regAPG1_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG1_APG_STATUS 0x21a8 +#define regAPG1_APG_STATUS_BASE_IDX 2 +#define regAPG1_APG_STATUS2 0x21a9 +#define regAPG1_APG_STATUS2_BASE_IDX 2 +#define regAPG1_APG_DBG_AUDIO_DTO_CNTL 0x21aa +#define regAPG1_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG1_APG_MEM_PWR 0x21ab +#define regAPG1_APG_MEM_PWR_BASE_IDX 2 +#define regAPG1_APG_SPARE 0x21ad +#define regAPG1_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +// base address: 0x159d4 +#define regDME1_DME_CONTROL 0x21b5 +#define regDME1_DME_CONTROL_BASE_IDX 2 +#define regDME1_DME_MEMORY_CONTROL 0x21b6 +#define regDME1_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig1_dispdec +// base address: 0x490 +#define regDIG1_DIG_FE_CNTL 0x21b7 +#define regDIG1_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_FE_CLK_CNTL 0x21b8 +#define regDIG1_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG1_DIG_FE_EN_CNTL 0x21b9 +#define regDIG1_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_CNTL 0x21ba +#define regDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG1_DIG_OUTPUT_CRC_RESULT 0x21bb +#define regDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG1_DIG_CLOCK_PATTERN 0x21bc +#define regDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_TEST_PATTERN 0x21bd +#define regDIG1_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG1_DIG_RANDOM_PATTERN_SEED 0x21be +#define regDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL0 0x21bf +#define regDIG1_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG1_DIG_FIFO_CTRL1 0x21c0 +#define regDIG1_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL 0x21c1 +#define regDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_CONTROL 0x21c2 +#define regDIG1_HDMI_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_STATUS 0x21c3 +#define regDIG1_HDMI_STATUS_BASE_IDX 2 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL 0x21c4 +#define regDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_PACKET_CONTROL 0x21c5 +#define regDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_VBI_PACKET_CONTROL 0x21c6 +#define regDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_INFOFRAME_CONTROL0 0x21c7 +#define regDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x21c8 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x21c9 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21ca +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG1_HDMI_GC 0x21cb +#define regDIG1_HDMI_GC_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x21cc +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x21cd +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21ce +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21cf +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21d0 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21d1 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21d2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21d3 +#define regDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG1_HDMI_DB_CONTROL 0x21d4 +#define regDIG1_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_0 0x21d5 +#define regDIG1_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_32_1 0x21d6 +#define regDIG1_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_0 0x21d7 +#define regDIG1_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_44_1 0x21d8 +#define regDIG1_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_0 0x21d9 +#define regDIG1_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_48_1 0x21da +#define regDIG1_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_0 0x21db +#define regDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG1_HDMI_ACR_STATUS_1 0x21dc +#define regDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG1_DIG_FE_AUDIO_CNTL 0x21dd +#define regDIG1_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CLK_CNTL 0x21de +#define regDIG1_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_CNTL 0x21df +#define regDIG1_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG1_DIG_BE_EN_CNTL 0x21e0 +#define regDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CNTL 0x2207 +#define regDIG1_TMDS_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL_CHAR 0x2208 +#define regDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CONTROL0_FEEDBACK 0x2209 +#define regDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL 0x220a +#define regDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x220b +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x220c +#define regDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG1_TMDS_CTL_BITS 0x220e +#define regDIG1_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG1_TMDS_DCBALANCER_CONTROL 0x220f +#define regDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x2210 +#define regDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL 0x2211 +#define regDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL 0x2212 +#define regDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG1_DIG_VERSION 0x2214 +#define regDIG1_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp1_dispdec +// base address: 0x490 +#define regDP1_DP_LINK_CNTL 0x2242 +#define regDP1_DP_LINK_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT 0x2243 +#define regDP1_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP1_DP_MSA_COLORIMETRY 0x2244 +#define regDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP1_DP_CONFIG 0x2245 +#define regDP1_DP_CONFIG_BASE_IDX 2 +#define regDP1_DP_VID_STREAM_CNTL 0x2246 +#define regDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO 0x2247 +#define regDP1_DP_STEER_FIFO_BASE_IDX 2 +#define regDP1_DP_MSA_MISC 0x2248 +#define regDP1_DP_MSA_MISC_BASE_IDX 2 +#define regDP1_DP_DPHY_INTERNAL_CTRL 0x2249 +#define regDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP1_DP_VID_TIMING 0x224a +#define regDP1_DP_VID_TIMING_BASE_IDX 2 +#define regDP1_DP_VID_N 0x224b +#define regDP1_DP_VID_N_BASE_IDX 2 +#define regDP1_DP_VID_M 0x224c +#define regDP1_DP_VID_M_BASE_IDX 2 +#define regDP1_DP_LINK_FRAMING_CNTL 0x224d +#define regDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP1_DP_HBR2_EYE_PATTERN 0x224e +#define regDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP1_DP_VID_MSA_VBID 0x224f +#define regDP1_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP1_DP_VID_INTERRUPT_CNTL 0x2250 +#define regDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CNTL 0x2251 +#define regDP1_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2252 +#define regDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM0 0x2253 +#define regDP1_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM1 0x2254 +#define regDP1_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP1_DP_DPHY_SYM2 0x2255 +#define regDP1_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP1_DP_DPHY_8B10B_CNTL 0x2256 +#define regDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_PRBS_CNTL 0x2257 +#define regDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_SCRAM_CNTL 0x2258 +#define regDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CONTROL0 0x2259 +#define regDP1_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_CONTROL1 0x225a +#define regDP1_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT0 0x225b +#define regDP1_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT1 0x225c +#define regDP1_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT2 0x225d +#define regDP1_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_RESULT3 0x225e +#define regDP1_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP1_DP_DPHY_CRC_STATUS 0x225f +#define regDP1_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP1_DP_TU_CNTL 0x2260 +#define regDP1_DP_TU_CNTL_BASE_IDX 2 +#define regDP1_DP_PIXEL_FORMAT_DB_CNTL 0x2261 +#define regDP1_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL 0x2265 +#define regDP1_DP_SEC_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL1 0x2266 +#define regDP1_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING1 0x2267 +#define regDP1_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING2 0x2268 +#define regDP1_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING3 0x2269 +#define regDP1_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP1_DP_SEC_FRAMING4 0x226a +#define regDP1_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N 0x226b +#define regDP1_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_N_READBACK 0x226c +#define regDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M 0x226d +#define regDP1_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP1_DP_SEC_AUD_M_READBACK 0x226e +#define regDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP1_DP_SEC_TIMESTAMP 0x226f +#define regDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP1_DP_SEC_PACKET_CNTL 0x2270 +#define regDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_CNTL 0x2271 +#define regDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP1_DP_MSE_RATE_UPDATE 0x2273 +#define regDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0 0x2274 +#define regDP1_DP_MSE_SAT0_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1 0x2275 +#define regDP1_DP_MSE_SAT1_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2 0x2276 +#define regDP1_DP_MSE_SAT2_BASE_IDX 2 +#define regDP1_DP_MSE_SAT_UPDATE 0x2277 +#define regDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP1_DP_MSE_LINK_TIMING 0x2278 +#define regDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP1_DP_MSE_MISC_CNTL 0x2279 +#define regDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x227e +#define regDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x227f +#define regDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSE_SAT0_STATUS 0x2281 +#define regDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT1_STATUS 0x2282 +#define regDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP1_DP_MSE_SAT2_STATUS 0x2283 +#define regDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP1_DP_HBLANK_CONTROL 0x2285 +#define regDP1_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM1 0x2286 +#define regDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM2 0x2287 +#define regDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM3 0x2288 +#define regDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP1_DP_MSA_TIMING_PARAM4 0x2289 +#define regDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL 0x228a +#define regDP1_DP_MSO_CNTL_BASE_IDX 2 +#define regDP1_DP_MSO_CNTL1 0x228b +#define regDP1_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP1_DP_STEER_FIFO_CNTL 0x228c +#define regDP1_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL2 0x228d +#define regDP1_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL3 0x228e +#define regDP1_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL4 0x228f +#define regDP1_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL5 0x2290 +#define regDP1_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL6 0x2291 +#define regDP1_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP1_DP_SEC_CNTL7 0x2292 +#define regDP1_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP1_DP_DB_CNTL 0x2293 +#define regDP1_DP_DB_CNTL_BASE_IDX 2 +#define regDP1_DP_MSA_VBID_MISC 0x2294 +#define regDP1_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP1_DP_SEC_METADATA_TRANSMISSION 0x2295 +#define regDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP1_DP_ALPM_CNTL 0x2297 +#define regDP1_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP8_CNTL 0x2298 +#define regDP1_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP9_CNTL 0x2299 +#define regDP1_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP10_CNTL 0x229a +#define regDP1_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP11_CNTL 0x229b +#define regDP1_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP1_DP_GSP_EN_DB_STATUS 0x229c +#define regDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL1 0x229d +#define regDP1_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL2 0x229e +#define regDP1_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL3 0x229f +#define regDP1_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL4 0x22a0 +#define regDP1_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP1_DP_AUXLESS_ALPM_CNTL5 0x22a1 +#define regDP1_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS 0x22a2 +#define regDP1_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL 0x22a3 +#define regDP1_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0 0x22a4 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1 0x22a5 +#define regDP1_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL 0x22a6 +#define regDP1_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x22a7 +#define regDP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING 0x22aa +#define regDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS 0x22ab +#define regDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +// base address: 0x15dc0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x22b0 +#define regVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_PACKET_DATA 0x22b1 +#define regVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x22b2 +#define regVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x22b3 +#define regVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG2_VPG_GENERIC_STATUS 0x22b4 +#define regVPG2_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG2_VPG_MEM_PWR 0x22b5 +#define regVPG2_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x22b6 +#define regVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG2_VPG_ISRC1_2_DATA 0x22b7 +#define regVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_apg_apg_dispdec +// base address: 0x15dec +#define regAPG2_APG_CONTROL 0x22bb +#define regAPG2_APG_CONTROL_BASE_IDX 2 +#define regAPG2_APG_CONTROL2 0x22bc +#define regAPG2_APG_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_GEN_CONTROL 0x22bd +#define regAPG2_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG2_APG_PACKET_CONTROL 0x22be +#define regAPG2_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG2_APG_DBG_ACP 0x22bf +#define regAPG2_APG_DBG_ACP_BASE_IDX 2 +#define regAPG2_APG_DBG_AUDIO_INFO 0x22c1 +#define regAPG2_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG2_APG_DBG_60958_0 0x22c2 +#define regAPG2_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG2_APG_DBG_60958_1 0x22c3 +#define regAPG2_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG2_APG_DBG_60958_2 0x22c4 +#define regAPG2_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL 0x22c5 +#define regAPG2_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_CONTROL2 0x22c6 +#define regAPG2_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_AUDIO_CRC_RESULT 0x22c7 +#define regAPG2_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL0 0x22c8 +#define regAPG2_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL1 0x22c9 +#define regAPG2_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL2 0x22ca +#define regAPG2_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG2_APG_DBG_RAMP_CONTROL3 0x22cb +#define regAPG2_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG2_APG_STATUS 0x22cc +#define regAPG2_APG_STATUS_BASE_IDX 2 +#define regAPG2_APG_STATUS2 0x22cd +#define regAPG2_APG_STATUS2_BASE_IDX 2 +#define regAPG2_APG_DBG_AUDIO_DTO_CNTL 0x22ce +#define regAPG2_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG2_APG_MEM_PWR 0x22cf +#define regAPG2_APG_MEM_PWR_BASE_IDX 2 +#define regAPG2_APG_SPARE 0x22d1 +#define regAPG2_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +// base address: 0x15e64 +#define regDME2_DME_CONTROL 0x22d9 +#define regDME2_DME_CONTROL_BASE_IDX 2 +#define regDME2_DME_MEMORY_CONTROL 0x22da +#define regDME2_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig2_dispdec +// base address: 0x920 +#define regDIG2_DIG_FE_CNTL 0x22db +#define regDIG2_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_FE_CLK_CNTL 0x22dc +#define regDIG2_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG2_DIG_FE_EN_CNTL 0x22dd +#define regDIG2_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_CNTL 0x22de +#define regDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG2_DIG_OUTPUT_CRC_RESULT 0x22df +#define regDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG2_DIG_CLOCK_PATTERN 0x22e0 +#define regDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_TEST_PATTERN 0x22e1 +#define regDIG2_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED 0x22e2 +#define regDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL0 0x22e3 +#define regDIG2_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG2_DIG_FIFO_CTRL1 0x22e4 +#define regDIG2_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL 0x22e5 +#define regDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_CONTROL 0x22e6 +#define regDIG2_HDMI_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_STATUS 0x22e7 +#define regDIG2_HDMI_STATUS_BASE_IDX 2 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL 0x22e8 +#define regDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_PACKET_CONTROL 0x22e9 +#define regDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_VBI_PACKET_CONTROL 0x22ea +#define regDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_INFOFRAME_CONTROL0 0x22eb +#define regDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x22ec +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x22ed +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22ee +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG2_HDMI_GC 0x22ef +#define regDIG2_HDMI_GC_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x22f0 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x22f1 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22f2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22f3 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22f4 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22f5 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22f6 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22f7 +#define regDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG2_HDMI_DB_CONTROL 0x22f8 +#define regDIG2_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_0 0x22f9 +#define regDIG2_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_32_1 0x22fa +#define regDIG2_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_0 0x22fb +#define regDIG2_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_44_1 0x22fc +#define regDIG2_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_0 0x22fd +#define regDIG2_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_48_1 0x22fe +#define regDIG2_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_0 0x22ff +#define regDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG2_HDMI_ACR_STATUS_1 0x2300 +#define regDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG2_DIG_FE_AUDIO_CNTL 0x2301 +#define regDIG2_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CLK_CNTL 0x2302 +#define regDIG2_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_CNTL 0x2303 +#define regDIG2_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG2_DIG_BE_EN_CNTL 0x2304 +#define regDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CNTL 0x232b +#define regDIG2_TMDS_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL_CHAR 0x232c +#define regDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CONTROL0_FEEDBACK 0x232d +#define regDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL 0x232e +#define regDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x232f +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x2330 +#define regDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG2_TMDS_CTL_BITS 0x2332 +#define regDIG2_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG2_TMDS_DCBALANCER_CONTROL 0x2333 +#define regDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x2334 +#define regDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL 0x2335 +#define regDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL 0x2336 +#define regDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG2_DIG_VERSION 0x2338 +#define regDIG2_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp2_dispdec +// base address: 0x920 +#define regDP2_DP_LINK_CNTL 0x2366 +#define regDP2_DP_LINK_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT 0x2367 +#define regDP2_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP2_DP_MSA_COLORIMETRY 0x2368 +#define regDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP2_DP_CONFIG 0x2369 +#define regDP2_DP_CONFIG_BASE_IDX 2 +#define regDP2_DP_VID_STREAM_CNTL 0x236a +#define regDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO 0x236b +#define regDP2_DP_STEER_FIFO_BASE_IDX 2 +#define regDP2_DP_MSA_MISC 0x236c +#define regDP2_DP_MSA_MISC_BASE_IDX 2 +#define regDP2_DP_DPHY_INTERNAL_CTRL 0x236d +#define regDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP2_DP_VID_TIMING 0x236e +#define regDP2_DP_VID_TIMING_BASE_IDX 2 +#define regDP2_DP_VID_N 0x236f +#define regDP2_DP_VID_N_BASE_IDX 2 +#define regDP2_DP_VID_M 0x2370 +#define regDP2_DP_VID_M_BASE_IDX 2 +#define regDP2_DP_LINK_FRAMING_CNTL 0x2371 +#define regDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP2_DP_HBR2_EYE_PATTERN 0x2372 +#define regDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP2_DP_VID_MSA_VBID 0x2373 +#define regDP2_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP2_DP_VID_INTERRUPT_CNTL 0x2374 +#define regDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CNTL 0x2375 +#define regDP2_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2376 +#define regDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM0 0x2377 +#define regDP2_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM1 0x2378 +#define regDP2_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP2_DP_DPHY_SYM2 0x2379 +#define regDP2_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP2_DP_DPHY_8B10B_CNTL 0x237a +#define regDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_PRBS_CNTL 0x237b +#define regDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_SCRAM_CNTL 0x237c +#define regDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CONTROL0 0x237d +#define regDP2_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_CONTROL1 0x237e +#define regDP2_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT0 0x237f +#define regDP2_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT1 0x2380 +#define regDP2_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT2 0x2381 +#define regDP2_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_RESULT3 0x2382 +#define regDP2_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP2_DP_DPHY_CRC_STATUS 0x2383 +#define regDP2_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP2_DP_TU_CNTL 0x2384 +#define regDP2_DP_TU_CNTL_BASE_IDX 2 +#define regDP2_DP_PIXEL_FORMAT_DB_CNTL 0x2385 +#define regDP2_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL 0x2389 +#define regDP2_DP_SEC_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL1 0x238a +#define regDP2_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING1 0x238b +#define regDP2_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING2 0x238c +#define regDP2_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING3 0x238d +#define regDP2_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP2_DP_SEC_FRAMING4 0x238e +#define regDP2_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N 0x238f +#define regDP2_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_N_READBACK 0x2390 +#define regDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M 0x2391 +#define regDP2_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP2_DP_SEC_AUD_M_READBACK 0x2392 +#define regDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP2_DP_SEC_TIMESTAMP 0x2393 +#define regDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP2_DP_SEC_PACKET_CNTL 0x2394 +#define regDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_CNTL 0x2395 +#define regDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP2_DP_MSE_RATE_UPDATE 0x2397 +#define regDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0 0x2398 +#define regDP2_DP_MSE_SAT0_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1 0x2399 +#define regDP2_DP_MSE_SAT1_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2 0x239a +#define regDP2_DP_MSE_SAT2_BASE_IDX 2 +#define regDP2_DP_MSE_SAT_UPDATE 0x239b +#define regDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP2_DP_MSE_LINK_TIMING 0x239c +#define regDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP2_DP_MSE_MISC_CNTL 0x239d +#define regDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x23a2 +#define regDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x23a3 +#define regDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSE_SAT0_STATUS 0x23a5 +#define regDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT1_STATUS 0x23a6 +#define regDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP2_DP_MSE_SAT2_STATUS 0x23a7 +#define regDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP2_DP_HBLANK_CONTROL 0x23a9 +#define regDP2_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM1 0x23aa +#define regDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM2 0x23ab +#define regDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM3 0x23ac +#define regDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP2_DP_MSA_TIMING_PARAM4 0x23ad +#define regDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL 0x23ae +#define regDP2_DP_MSO_CNTL_BASE_IDX 2 +#define regDP2_DP_MSO_CNTL1 0x23af +#define regDP2_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP2_DP_STEER_FIFO_CNTL 0x23b0 +#define regDP2_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL2 0x23b1 +#define regDP2_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL3 0x23b2 +#define regDP2_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL4 0x23b3 +#define regDP2_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL5 0x23b4 +#define regDP2_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL6 0x23b5 +#define regDP2_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP2_DP_SEC_CNTL7 0x23b6 +#define regDP2_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP2_DP_DB_CNTL 0x23b7 +#define regDP2_DP_DB_CNTL_BASE_IDX 2 +#define regDP2_DP_MSA_VBID_MISC 0x23b8 +#define regDP2_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP2_DP_SEC_METADATA_TRANSMISSION 0x23b9 +#define regDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP2_DP_ALPM_CNTL 0x23bb +#define regDP2_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP8_CNTL 0x23bc +#define regDP2_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP9_CNTL 0x23bd +#define regDP2_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP10_CNTL 0x23be +#define regDP2_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP11_CNTL 0x23bf +#define regDP2_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP2_DP_GSP_EN_DB_STATUS 0x23c0 +#define regDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL1 0x23c1 +#define regDP2_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL2 0x23c2 +#define regDP2_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL3 0x23c3 +#define regDP2_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL4 0x23c4 +#define regDP2_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP2_DP_AUXLESS_ALPM_CNTL5 0x23c5 +#define regDP2_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS 0x23c6 +#define regDP2_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL 0x23c7 +#define regDP2_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0 0x23c8 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1 0x23c9 +#define regDP2_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL 0x23ca +#define regDP2_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x23cb +#define regDP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING 0x23ce +#define regDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS 0x23cf +#define regDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +// base address: 0x16250 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x23d4 +#define regVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_PACKET_DATA 0x23d5 +#define regVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x23d6 +#define regVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x23d7 +#define regVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG3_VPG_GENERIC_STATUS 0x23d8 +#define regVPG3_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG3_VPG_MEM_PWR 0x23d9 +#define regVPG3_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x23da +#define regVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG3_VPG_ISRC1_2_DATA 0x23db +#define regVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_apg_apg_dispdec +// base address: 0x1627c +#define regAPG3_APG_CONTROL 0x23df +#define regAPG3_APG_CONTROL_BASE_IDX 2 +#define regAPG3_APG_CONTROL2 0x23e0 +#define regAPG3_APG_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_GEN_CONTROL 0x23e1 +#define regAPG3_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG3_APG_PACKET_CONTROL 0x23e2 +#define regAPG3_APG_PACKET_CONTROL_BASE_IDX 2 +#define regAPG3_APG_DBG_ACP 0x23e3 +#define regAPG3_APG_DBG_ACP_BASE_IDX 2 +#define regAPG3_APG_DBG_AUDIO_INFO 0x23e5 +#define regAPG3_APG_DBG_AUDIO_INFO_BASE_IDX 2 +#define regAPG3_APG_DBG_60958_0 0x23e6 +#define regAPG3_APG_DBG_60958_0_BASE_IDX 2 +#define regAPG3_APG_DBG_60958_1 0x23e7 +#define regAPG3_APG_DBG_60958_1_BASE_IDX 2 +#define regAPG3_APG_DBG_60958_2 0x23e8 +#define regAPG3_APG_DBG_60958_2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL 0x23e9 +#define regAPG3_APG_AUDIO_CRC_CONTROL_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_CONTROL2 0x23ea +#define regAPG3_APG_AUDIO_CRC_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_AUDIO_CRC_RESULT 0x23eb +#define regAPG3_APG_AUDIO_CRC_RESULT_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL0 0x23ec +#define regAPG3_APG_DBG_RAMP_CONTROL0_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL1 0x23ed +#define regAPG3_APG_DBG_RAMP_CONTROL1_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL2 0x23ee +#define regAPG3_APG_DBG_RAMP_CONTROL2_BASE_IDX 2 +#define regAPG3_APG_DBG_RAMP_CONTROL3 0x23ef +#define regAPG3_APG_DBG_RAMP_CONTROL3_BASE_IDX 2 +#define regAPG3_APG_STATUS 0x23f0 +#define regAPG3_APG_STATUS_BASE_IDX 2 +#define regAPG3_APG_STATUS2 0x23f1 +#define regAPG3_APG_STATUS2_BASE_IDX 2 +#define regAPG3_APG_DBG_AUDIO_DTO_CNTL 0x23f2 +#define regAPG3_APG_DBG_AUDIO_DTO_CNTL_BASE_IDX 2 +#define regAPG3_APG_MEM_PWR 0x23f3 +#define regAPG3_APG_MEM_PWR_BASE_IDX 2 +#define regAPG3_APG_SPARE 0x23f5 +#define regAPG3_APG_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +// base address: 0x162f4 +#define regDME3_DME_CONTROL 0x23fd +#define regDME3_DME_CONTROL_BASE_IDX 2 +#define regDME3_DME_MEMORY_CONTROL 0x23fe +#define regDME3_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig3_dispdec +// base address: 0xdb0 +#define regDIG3_DIG_FE_CNTL 0x23ff +#define regDIG3_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_FE_CLK_CNTL 0x2400 +#define regDIG3_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG3_DIG_FE_EN_CNTL 0x2401 +#define regDIG3_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_CNTL 0x2402 +#define regDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG3_DIG_OUTPUT_CRC_RESULT 0x2403 +#define regDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG3_DIG_CLOCK_PATTERN 0x2404 +#define regDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_TEST_PATTERN 0x2405 +#define regDIG3_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG3_DIG_RANDOM_PATTERN_SEED 0x2406 +#define regDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL0 0x2407 +#define regDIG3_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG3_DIG_FIFO_CTRL1 0x2408 +#define regDIG3_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL 0x2409 +#define regDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_CONTROL 0x240a +#define regDIG3_HDMI_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_STATUS 0x240b +#define regDIG3_HDMI_STATUS_BASE_IDX 2 +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL 0x240c +#define regDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_PACKET_CONTROL 0x240d +#define regDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_VBI_PACKET_CONTROL 0x240e +#define regDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_INFOFRAME_CONTROL0 0x240f +#define regDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2410 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x2411 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x2412 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG3_HDMI_GC 0x2413 +#define regDIG3_HDMI_GC_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2414 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2415 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2416 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2417 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x2418 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x2419 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x241a +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x241b +#define regDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG3_HDMI_DB_CONTROL 0x241c +#define regDIG3_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_0 0x241d +#define regDIG3_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_32_1 0x241e +#define regDIG3_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_0 0x241f +#define regDIG3_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_44_1 0x2420 +#define regDIG3_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_0 0x2421 +#define regDIG3_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_48_1 0x2422 +#define regDIG3_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_0 0x2423 +#define regDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG3_HDMI_ACR_STATUS_1 0x2424 +#define regDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG3_DIG_FE_AUDIO_CNTL 0x2425 +#define regDIG3_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CLK_CNTL 0x2426 +#define regDIG3_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_CNTL 0x2427 +#define regDIG3_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG3_DIG_BE_EN_CNTL 0x2428 +#define regDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CNTL 0x244f +#define regDIG3_TMDS_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL_CHAR 0x2450 +#define regDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CONTROL0_FEEDBACK 0x2451 +#define regDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL 0x2452 +#define regDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x2453 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x2454 +#define regDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG3_TMDS_CTL_BITS 0x2456 +#define regDIG3_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG3_TMDS_DCBALANCER_CONTROL 0x2457 +#define regDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x2458 +#define regDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL 0x2459 +#define regDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG3_TMDS_CTL2_3_GEN_CNTL 0x245a +#define regDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG3_DIG_VERSION 0x245c +#define regDIG3_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp3_dispdec +// base address: 0xdb0 +#define regDP3_DP_LINK_CNTL 0x248a +#define regDP3_DP_LINK_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT 0x248b +#define regDP3_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP3_DP_MSA_COLORIMETRY 0x248c +#define regDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP3_DP_CONFIG 0x248d +#define regDP3_DP_CONFIG_BASE_IDX 2 +#define regDP3_DP_VID_STREAM_CNTL 0x248e +#define regDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO 0x248f +#define regDP3_DP_STEER_FIFO_BASE_IDX 2 +#define regDP3_DP_MSA_MISC 0x2490 +#define regDP3_DP_MSA_MISC_BASE_IDX 2 +#define regDP3_DP_DPHY_INTERNAL_CTRL 0x2491 +#define regDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP3_DP_VID_TIMING 0x2492 +#define regDP3_DP_VID_TIMING_BASE_IDX 2 +#define regDP3_DP_VID_N 0x2493 +#define regDP3_DP_VID_N_BASE_IDX 2 +#define regDP3_DP_VID_M 0x2494 +#define regDP3_DP_VID_M_BASE_IDX 2 +#define regDP3_DP_LINK_FRAMING_CNTL 0x2495 +#define regDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP3_DP_HBR2_EYE_PATTERN 0x2496 +#define regDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP3_DP_VID_MSA_VBID 0x2497 +#define regDP3_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP3_DP_VID_INTERRUPT_CNTL 0x2498 +#define regDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CNTL 0x2499 +#define regDP3_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x249a +#define regDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM0 0x249b +#define regDP3_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM1 0x249c +#define regDP3_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP3_DP_DPHY_SYM2 0x249d +#define regDP3_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP3_DP_DPHY_8B10B_CNTL 0x249e +#define regDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_PRBS_CNTL 0x249f +#define regDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_SCRAM_CNTL 0x24a0 +#define regDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CONTROL0 0x24a1 +#define regDP3_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_CONTROL1 0x24a2 +#define regDP3_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT0 0x24a3 +#define regDP3_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT1 0x24a4 +#define regDP3_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT2 0x24a5 +#define regDP3_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_RESULT3 0x24a6 +#define regDP3_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP3_DP_DPHY_CRC_STATUS 0x24a7 +#define regDP3_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP3_DP_TU_CNTL 0x24a8 +#define regDP3_DP_TU_CNTL_BASE_IDX 2 +#define regDP3_DP_PIXEL_FORMAT_DB_CNTL 0x24a9 +#define regDP3_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL 0x24ad +#define regDP3_DP_SEC_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL1 0x24ae +#define regDP3_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING1 0x24af +#define regDP3_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING2 0x24b0 +#define regDP3_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING3 0x24b1 +#define regDP3_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP3_DP_SEC_FRAMING4 0x24b2 +#define regDP3_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N 0x24b3 +#define regDP3_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_N_READBACK 0x24b4 +#define regDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M 0x24b5 +#define regDP3_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP3_DP_SEC_AUD_M_READBACK 0x24b6 +#define regDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP3_DP_SEC_TIMESTAMP 0x24b7 +#define regDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP3_DP_SEC_PACKET_CNTL 0x24b8 +#define regDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_CNTL 0x24b9 +#define regDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP3_DP_MSE_RATE_UPDATE 0x24bb +#define regDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0 0x24bc +#define regDP3_DP_MSE_SAT0_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1 0x24bd +#define regDP3_DP_MSE_SAT1_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2 0x24be +#define regDP3_DP_MSE_SAT2_BASE_IDX 2 +#define regDP3_DP_MSE_SAT_UPDATE 0x24bf +#define regDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP3_DP_MSE_LINK_TIMING 0x24c0 +#define regDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP3_DP_MSE_MISC_CNTL 0x24c1 +#define regDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x24c6 +#define regDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x24c7 +#define regDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSE_SAT0_STATUS 0x24c9 +#define regDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT1_STATUS 0x24ca +#define regDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP3_DP_MSE_SAT2_STATUS 0x24cb +#define regDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP3_DP_HBLANK_CONTROL 0x24cd +#define regDP3_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM1 0x24ce +#define regDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM2 0x24cf +#define regDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM3 0x24d0 +#define regDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP3_DP_MSA_TIMING_PARAM4 0x24d1 +#define regDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL 0x24d2 +#define regDP3_DP_MSO_CNTL_BASE_IDX 2 +#define regDP3_DP_MSO_CNTL1 0x24d3 +#define regDP3_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP3_DP_STEER_FIFO_CNTL 0x24d4 +#define regDP3_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL2 0x24d5 +#define regDP3_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL3 0x24d6 +#define regDP3_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL4 0x24d7 +#define regDP3_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL5 0x24d8 +#define regDP3_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL6 0x24d9 +#define regDP3_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP3_DP_SEC_CNTL7 0x24da +#define regDP3_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP3_DP_DB_CNTL 0x24db +#define regDP3_DP_DB_CNTL_BASE_IDX 2 +#define regDP3_DP_MSA_VBID_MISC 0x24dc +#define regDP3_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP3_DP_SEC_METADATA_TRANSMISSION 0x24dd +#define regDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP3_DP_ALPM_CNTL 0x24df +#define regDP3_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP8_CNTL 0x24e0 +#define regDP3_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP9_CNTL 0x24e1 +#define regDP3_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP10_CNTL 0x24e2 +#define regDP3_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP11_CNTL 0x24e3 +#define regDP3_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP3_DP_GSP_EN_DB_STATUS 0x24e4 +#define regDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL1 0x24e5 +#define regDP3_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL2 0x24e6 +#define regDP3_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL3 0x24e7 +#define regDP3_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL4 0x24e8 +#define regDP3_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP3_DP_AUXLESS_ALPM_CNTL5 0x24e9 +#define regDP3_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS 0x24ea +#define regDP3_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL 0x24eb +#define regDP3_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0 0x24ec +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1 0x24ed +#define regDP3_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL 0x24ee +#define regDP3_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x24ef +#define regDP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING 0x24f2 +#define regDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS 0x24f3 +#define regDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +// base address: 0x166e0 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x24f8 +#define regVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_PACKET_DATA 0x24f9 +#define regVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x24fa +#define regVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x24fb +#define regVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG4_VPG_GENERIC_STATUS 0x24fc +#define regVPG4_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG4_VPG_MEM_PWR 0x24fd +#define regVPG4_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x24fe +#define regVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG4_VPG_ISRC1_2_DATA 0x24ff +#define regVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_apg_apg_dispdec +// base address: 0x1670c +#define regAPG4_APG_CONTROL 0x2503 +#define regAPG4_APG_CONTROL_BASE_IDX 2 +#define regAPG4_APG_CONTROL2 0x2504 +#define regAPG4_APG_CONTROL2_BASE_IDX 2 +#define regAPG4_APG_DBG_GEN_CONTROL 0x2505 +#define regAPG4_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG4_APG_MEM_PWR 0x2517 +#define regAPG4_APG_MEM_PWR_BASE_IDX 2 + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +// base address: 0x16784 +#define regDME4_DME_CONTROL 0x2521 +#define regDME4_DME_CONTROL_BASE_IDX 2 +#define regDME4_DME_MEMORY_CONTROL 0x2522 +#define regDME4_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dig4_dispdec +// base address: 0x1240 +#define regDIG4_DIG_FE_CNTL 0x2523 +#define regDIG4_DIG_FE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_FE_CLK_CNTL 0x2524 +#define regDIG4_DIG_FE_CLK_CNTL_BASE_IDX 2 +#define regDIG4_DIG_FE_EN_CNTL 0x2525 +#define regDIG4_DIG_FE_EN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_CNTL 0x2526 +#define regDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 +#define regDIG4_DIG_OUTPUT_CRC_RESULT 0x2527 +#define regDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 +#define regDIG4_DIG_CLOCK_PATTERN 0x2528 +#define regDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_TEST_PATTERN 0x2529 +#define regDIG4_DIG_TEST_PATTERN_BASE_IDX 2 +#define regDIG4_DIG_RANDOM_PATTERN_SEED 0x252a +#define regDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL0 0x252b +#define regDIG4_DIG_FIFO_CTRL0_BASE_IDX 2 +#define regDIG4_DIG_FIFO_CTRL1 0x252c +#define regDIG4_DIG_FIFO_CTRL1_BASE_IDX 2 +#define regDIG4_HDMI_METADATA_PACKET_CONTROL 0x252d +#define regDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_CONTROL 0x252e +#define regDIG4_HDMI_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_STATUS 0x252f +#define regDIG4_HDMI_STATUS_BASE_IDX 2 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2530 +#define regDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_PACKET_CONTROL 0x2531 +#define regDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_VBI_PACKET_CONTROL 0x2532 +#define regDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_INFOFRAME_CONTROL0 0x2533 +#define regDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2534 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x2535 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x2536 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2 +#define regDIG4_HDMI_GC 0x2537 +#define regDIG4_HDMI_GC_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2538 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2539 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x253a +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x253b +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x253c +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x253d +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x253e +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2 +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x253f +#define regDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2 +#define regDIG4_HDMI_DB_CONTROL 0x2540 +#define regDIG4_HDMI_DB_CONTROL_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_0 0x2541 +#define regDIG4_HDMI_ACR_32_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_32_1 0x2542 +#define regDIG4_HDMI_ACR_32_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_0 0x2543 +#define regDIG4_HDMI_ACR_44_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_44_1 0x2544 +#define regDIG4_HDMI_ACR_44_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_0 0x2545 +#define regDIG4_HDMI_ACR_48_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_48_1 0x2546 +#define regDIG4_HDMI_ACR_48_1_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_0 0x2547 +#define regDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 +#define regDIG4_HDMI_ACR_STATUS_1 0x2548 +#define regDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 +#define regDIG4_DIG_FE_AUDIO_CNTL 0x2549 +#define regDIG4_DIG_FE_AUDIO_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CLK_CNTL 0x254a +#define regDIG4_DIG_BE_CLK_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_CNTL 0x254b +#define regDIG4_DIG_BE_CNTL_BASE_IDX 2 +#define regDIG4_DIG_BE_EN_CNTL 0x254c +#define regDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CNTL 0x2573 +#define regDIG4_TMDS_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL_CHAR 0x2574 +#define regDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CONTROL0_FEEDBACK 0x2575 +#define regDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL 0x2576 +#define regDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x2577 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x2578 +#define regDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 +#define regDIG4_TMDS_CTL_BITS 0x257a +#define regDIG4_TMDS_CTL_BITS_BASE_IDX 2 +#define regDIG4_TMDS_DCBALANCER_CONTROL 0x257b +#define regDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x257c +#define regDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2 +#define regDIG4_TMDS_CTL0_1_GEN_CNTL 0x257d +#define regDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 +#define regDIG4_TMDS_CTL2_3_GEN_CNTL 0x257e +#define regDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 +#define regDIG4_DIG_VERSION 0x2580 +#define regDIG4_DIG_VERSION_BASE_IDX 2 + + +// addressBlock: dce_dc_dio_dp4_dispdec +// base address: 0x1240 +#define regDP4_DP_LINK_CNTL 0x25ae +#define regDP4_DP_LINK_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT 0x25af +#define regDP4_DP_PIXEL_FORMAT_BASE_IDX 2 +#define regDP4_DP_MSA_COLORIMETRY 0x25b0 +#define regDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 +#define regDP4_DP_CONFIG 0x25b1 +#define regDP4_DP_CONFIG_BASE_IDX 2 +#define regDP4_DP_VID_STREAM_CNTL 0x25b2 +#define regDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO 0x25b3 +#define regDP4_DP_STEER_FIFO_BASE_IDX 2 +#define regDP4_DP_MSA_MISC 0x25b4 +#define regDP4_DP_MSA_MISC_BASE_IDX 2 +#define regDP4_DP_DPHY_INTERNAL_CTRL 0x25b5 +#define regDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 +#define regDP4_DP_VID_TIMING 0x25b6 +#define regDP4_DP_VID_TIMING_BASE_IDX 2 +#define regDP4_DP_VID_N 0x25b7 +#define regDP4_DP_VID_N_BASE_IDX 2 +#define regDP4_DP_VID_M 0x25b8 +#define regDP4_DP_VID_M_BASE_IDX 2 +#define regDP4_DP_LINK_FRAMING_CNTL 0x25b9 +#define regDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 +#define regDP4_DP_HBR2_EYE_PATTERN 0x25ba +#define regDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 +#define regDP4_DP_VID_MSA_VBID 0x25bb +#define regDP4_DP_VID_MSA_VBID_BASE_IDX 2 +#define regDP4_DP_VID_INTERRUPT_CNTL 0x25bc +#define regDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CNTL 0x25bd +#define regDP4_DP_DPHY_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x25be +#define regDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM0 0x25bf +#define regDP4_DP_DPHY_SYM0_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM1 0x25c0 +#define regDP4_DP_DPHY_SYM1_BASE_IDX 2 +#define regDP4_DP_DPHY_SYM2 0x25c1 +#define regDP4_DP_DPHY_SYM2_BASE_IDX 2 +#define regDP4_DP_DPHY_8B10B_CNTL 0x25c2 +#define regDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_PRBS_CNTL 0x25c3 +#define regDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_SCRAM_CNTL 0x25c4 +#define regDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CONTROL0 0x25c5 +#define regDP4_DP_DPHY_CRC_CONTROL0_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_CONTROL1 0x25c6 +#define regDP4_DP_DPHY_CRC_CONTROL1_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT0 0x25c7 +#define regDP4_DP_DPHY_CRC_RESULT0_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT1 0x25c8 +#define regDP4_DP_DPHY_CRC_RESULT1_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT2 0x25c9 +#define regDP4_DP_DPHY_CRC_RESULT2_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_RESULT3 0x25ca +#define regDP4_DP_DPHY_CRC_RESULT3_BASE_IDX 2 +#define regDP4_DP_DPHY_CRC_STATUS 0x25cb +#define regDP4_DP_DPHY_CRC_STATUS_BASE_IDX 2 +#define regDP4_DP_TU_CNTL 0x25cc +#define regDP4_DP_TU_CNTL_BASE_IDX 2 +#define regDP4_DP_PIXEL_FORMAT_DB_CNTL 0x25cd +#define regDP4_DP_PIXEL_FORMAT_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL 0x25d1 +#define regDP4_DP_SEC_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL1 0x25d2 +#define regDP4_DP_SEC_CNTL1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING1 0x25d3 +#define regDP4_DP_SEC_FRAMING1_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING2 0x25d4 +#define regDP4_DP_SEC_FRAMING2_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING3 0x25d5 +#define regDP4_DP_SEC_FRAMING3_BASE_IDX 2 +#define regDP4_DP_SEC_FRAMING4 0x25d6 +#define regDP4_DP_SEC_FRAMING4_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N 0x25d7 +#define regDP4_DP_SEC_AUD_N_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_N_READBACK 0x25d8 +#define regDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M 0x25d9 +#define regDP4_DP_SEC_AUD_M_BASE_IDX 2 +#define regDP4_DP_SEC_AUD_M_READBACK 0x25da +#define regDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 +#define regDP4_DP_SEC_TIMESTAMP 0x25db +#define regDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 +#define regDP4_DP_SEC_PACKET_CNTL 0x25dc +#define regDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_CNTL 0x25dd +#define regDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 +#define regDP4_DP_MSE_RATE_UPDATE 0x25df +#define regDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0 0x25e0 +#define regDP4_DP_MSE_SAT0_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1 0x25e1 +#define regDP4_DP_MSE_SAT1_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2 0x25e2 +#define regDP4_DP_MSE_SAT2_BASE_IDX 2 +#define regDP4_DP_MSE_SAT_UPDATE 0x25e3 +#define regDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 +#define regDP4_DP_MSE_LINK_TIMING 0x25e4 +#define regDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 +#define regDP4_DP_MSE_MISC_CNTL 0x25e5 +#define regDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x25ea +#define regDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x25eb +#define regDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSE_SAT0_STATUS 0x25ed +#define regDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT1_STATUS 0x25ee +#define regDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 +#define regDP4_DP_MSE_SAT2_STATUS 0x25ef +#define regDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 +#define regDP4_DP_HBLANK_CONTROL 0x25f1 +#define regDP4_DP_HBLANK_CONTROL_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM1 0x25f2 +#define regDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM2 0x25f3 +#define regDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM3 0x25f4 +#define regDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 +#define regDP4_DP_MSA_TIMING_PARAM4 0x25f5 +#define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL 0x25f6 +#define regDP4_DP_MSO_CNTL_BASE_IDX 2 +#define regDP4_DP_MSO_CNTL1 0x25f7 +#define regDP4_DP_MSO_CNTL1_BASE_IDX 2 +#define regDP4_DP_STEER_FIFO_CNTL 0x25f8 +#define regDP4_DP_STEER_FIFO_CNTL_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL2 0x25f9 +#define regDP4_DP_SEC_CNTL2_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL3 0x25fa +#define regDP4_DP_SEC_CNTL3_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL4 0x25fb +#define regDP4_DP_SEC_CNTL4_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL5 0x25fc +#define regDP4_DP_SEC_CNTL5_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL6 0x25fd +#define regDP4_DP_SEC_CNTL6_BASE_IDX 2 +#define regDP4_DP_SEC_CNTL7 0x25fe +#define regDP4_DP_SEC_CNTL7_BASE_IDX 2 +#define regDP4_DP_DB_CNTL 0x25ff +#define regDP4_DP_DB_CNTL_BASE_IDX 2 +#define regDP4_DP_MSA_VBID_MISC 0x2600 +#define regDP4_DP_MSA_VBID_MISC_BASE_IDX 2 +#define regDP4_DP_SEC_METADATA_TRANSMISSION 0x2601 +#define regDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2 +#define regDP4_DP_ALPM_CNTL 0x2603 +#define regDP4_DP_ALPM_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP8_CNTL 0x2604 +#define regDP4_DP_GSP8_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP9_CNTL 0x2605 +#define regDP4_DP_GSP9_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP10_CNTL 0x2606 +#define regDP4_DP_GSP10_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP11_CNTL 0x2607 +#define regDP4_DP_GSP11_CNTL_BASE_IDX 2 +#define regDP4_DP_GSP_EN_DB_STATUS 0x2608 +#define regDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL1 0x2609 +#define regDP4_DP_AUXLESS_ALPM_CNTL1_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL2 0x260a +#define regDP4_DP_AUXLESS_ALPM_CNTL2_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL3 0x260b +#define regDP4_DP_AUXLESS_ALPM_CNTL3_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL4 0x260c +#define regDP4_DP_AUXLESS_ALPM_CNTL4_BASE_IDX 2 +#define regDP4_DP_AUXLESS_ALPM_CNTL5 0x260d +#define regDP4_DP_AUXLESS_ALPM_CNTL5_BASE_IDX 2 +#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS 0x260e +#define regDP4_DP_STREAM_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL 0x260f +#define regDP4_DP_STREAM_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0 0x2610 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1 0x2611 +#define regDP4_DP_LINK_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL 0x2612 +#define regDP4_DP_LINK_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL 0x2613 +#define regDP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING 0x2616 +#define regDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2617 +#define regDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +// base address: 0x0 +#define regDSC_TOP0_DSC_TOP_CONTROL 0x3000 +#define regDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_DEBUG_CONTROL 0x3001 +#define regDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP0_DSC_SPARE_DEBUG 0x3002 +#define regDSC_TOP0_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX 0x3003 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA 0x3004 +#define regDSC_TOP0_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +// base address: 0x0 +#define regDSCCIF0_DSCCIF_CONFIG0 0x3005 +#define regDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +// base address: 0x0 +#define regDSCC0_DSCC_CONFIG0 0x300a +#define regDSCC0_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG1 0x300b +#define regDSCC0_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_CONFIG2 0x300c +#define regDSCC0_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_STATUS 0x300d +#define regDSCC0_DSCC_STATUS_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL0 0x300e +#define regDSCC0_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_CONTROL1 0x300f +#define regDSCC0_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_STATUS0 0x3010 +#define regDSCC0_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC0_DSCC_INTERRUPT_STATUS1 0x3011 +#define regDSCC0_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG0 0x3012 +#define regDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG1 0x3013 +#define regDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG2 0x3014 +#define regDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG3 0x3015 +#define regDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG4 0x3016 +#define regDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG5 0x3017 +#define regDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG6 0x3018 +#define regDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG7 0x3019 +#define regDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG8 0x301a +#define regDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG9 0x301b +#define regDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG10 0x301c +#define regDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG11 0x301d +#define regDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG12 0x301e +#define regDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG13 0x301f +#define regDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG14 0x3020 +#define regDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG15 0x3021 +#define regDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG16 0x3022 +#define regDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG17 0x3023 +#define regDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG18 0x3024 +#define regDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG19 0x3025 +#define regDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG20 0x3026 +#define regDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG21 0x3027 +#define regDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC0_DSCC_PPS_CONFIG22 0x3028 +#define regDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL0 0x3029 +#define regDSCC0_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC0_DSCC_MEM_POWER_CONTROL1 0x302a +#define regDSCC0_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x302b +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x302c +#define regDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x302d +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x302e +#define regDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302f +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3030 +#define regDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR0 0x3031 +#define regDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC0_DSCC_MAX_ABS_ERROR1 0x3032 +#define regDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3033 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3034 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3035 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3036 +#define regDSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3037 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3038 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3039 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x303a +#define regDSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX0 0x303b +#define regDSCC0_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX1 0x303c +#define regDSCC0_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX2 0x303d +#define regDSCC0_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_INDEX3 0x303e +#define regDSCC0_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303f +#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA0 0x3040 +#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA1 0x3041 +#define regDSCC0_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA2 0x3042 +#define regDSCC0_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC0_DSCC_TEST_DEBUG_DATA3 0x3043 +#define regDSCC0_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3044 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3045 +#define regDSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc140 +#define regDC_PERFMON17_PERFCOUNTER_CNTL 0x3050 +#define regDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON17_PERFCOUNTER_CNTL2 0x3051 +#define regDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON17_PERFCOUNTER_STATE 0x3052 +#define regDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CNTL 0x3053 +#define regDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CNTL2 0x3054 +#define regDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x3055 +#define regDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_CVALUE_LOW 0x3056 +#define regDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_HI 0x3057 +#define regDC_PERFMON17_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON17_PERFMON_LOW 0x3058 +#define regDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +// base address: 0x170 +#define regDSC_TOP1_DSC_TOP_CONTROL 0x305c +#define regDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_DEBUG_CONTROL 0x305d +#define regDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP1_DSC_SPARE_DEBUG 0x305e +#define regDSC_TOP1_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX 0x305f +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA 0x3060 +#define regDSC_TOP1_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +// base address: 0x170 +#define regDSCCIF1_DSCCIF_CONFIG0 0x3061 +#define regDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +// base address: 0x170 +#define regDSCC1_DSCC_CONFIG0 0x3066 +#define regDSCC1_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG1 0x3067 +#define regDSCC1_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_CONFIG2 0x3068 +#define regDSCC1_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_STATUS 0x3069 +#define regDSCC1_DSCC_STATUS_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL0 0x306a +#define regDSCC1_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_CONTROL1 0x306b +#define regDSCC1_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_STATUS0 0x306c +#define regDSCC1_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC1_DSCC_INTERRUPT_STATUS1 0x306d +#define regDSCC1_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG0 0x306e +#define regDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG1 0x306f +#define regDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG2 0x3070 +#define regDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG3 0x3071 +#define regDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG4 0x3072 +#define regDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG5 0x3073 +#define regDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG6 0x3074 +#define regDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG7 0x3075 +#define regDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG8 0x3076 +#define regDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG9 0x3077 +#define regDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG10 0x3078 +#define regDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG11 0x3079 +#define regDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG12 0x307a +#define regDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG13 0x307b +#define regDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG14 0x307c +#define regDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG15 0x307d +#define regDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG16 0x307e +#define regDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG17 0x307f +#define regDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG18 0x3080 +#define regDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG19 0x3081 +#define regDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG20 0x3082 +#define regDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG21 0x3083 +#define regDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC1_DSCC_PPS_CONFIG22 0x3084 +#define regDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL0 0x3085 +#define regDSCC1_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC1_DSCC_MEM_POWER_CONTROL1 0x3086 +#define regDSCC1_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3087 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3088 +#define regDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3089 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x308a +#define regDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x308b +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x308c +#define regDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR0 0x308d +#define regDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC1_DSCC_MAX_ABS_ERROR1 0x308e +#define regDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x308f +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3090 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3091 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x3092 +#define regDSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x3093 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x3094 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x3095 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x3096 +#define regDSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX0 0x3097 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX1 0x3098 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX2 0x3099 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_INDEX3 0x309a +#define regDSCC1_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x309b +#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA0 0x309c +#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA1 0x309d +#define regDSCC1_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA2 0x309e +#define regDSCC1_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC1_DSCC_TEST_DEBUG_DATA3 0x309f +#define regDSCC1_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30a0 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30a1 +#define regDSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc2b0 +#define regDC_PERFMON18_PERFCOUNTER_CNTL 0x30ac +#define regDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON18_PERFCOUNTER_CNTL2 0x30ad +#define regDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON18_PERFCOUNTER_STATE 0x30ae +#define regDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CNTL 0x30af +#define regDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CNTL2 0x30b0 +#define regDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x30b1 +#define regDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_CVALUE_LOW 0x30b2 +#define regDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_HI 0x30b3 +#define regDC_PERFMON18_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON18_PERFMON_LOW 0x30b4 +#define regDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +// base address: 0x2e0 +#define regDSC_TOP2_DSC_TOP_CONTROL 0x30b8 +#define regDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9 +#define regDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP2_DSC_SPARE_DEBUG 0x30ba +#define regDSC_TOP2_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX 0x30bb +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA 0x30bc +#define regDSC_TOP2_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +// base address: 0x2e0 +#define regDSCCIF2_DSCCIF_CONFIG0 0x30bd +#define regDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +// base address: 0x2e0 +#define regDSCC2_DSCC_CONFIG0 0x30c2 +#define regDSCC2_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG1 0x30c3 +#define regDSCC2_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_CONFIG2 0x30c4 +#define regDSCC2_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_STATUS 0x30c5 +#define regDSCC2_DSCC_STATUS_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL0 0x30c6 +#define regDSCC2_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_CONTROL1 0x30c7 +#define regDSCC2_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_STATUS0 0x30c8 +#define regDSCC2_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC2_DSCC_INTERRUPT_STATUS1 0x30c9 +#define regDSCC2_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG0 0x30ca +#define regDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG1 0x30cb +#define regDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG2 0x30cc +#define regDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG3 0x30cd +#define regDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG4 0x30ce +#define regDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG5 0x30cf +#define regDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG6 0x30d0 +#define regDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG7 0x30d1 +#define regDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG8 0x30d2 +#define regDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG9 0x30d3 +#define regDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG10 0x30d4 +#define regDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG11 0x30d5 +#define regDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG12 0x30d6 +#define regDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG13 0x30d7 +#define regDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG14 0x30d8 +#define regDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG15 0x30d9 +#define regDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG16 0x30da +#define regDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG17 0x30db +#define regDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG18 0x30dc +#define regDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG19 0x30dd +#define regDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG20 0x30de +#define regDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG21 0x30df +#define regDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC2_DSCC_PPS_CONFIG22 0x30e0 +#define regDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL0 0x30e1 +#define regDSCC2_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL1 0x30e2 +#define regDSCC2_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30e3 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30e4 +#define regDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e5 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e6 +#define regDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e7 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e8 +#define regDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR0 0x30e9 +#define regDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC2_DSCC_MAX_ABS_ERROR1 0x30ea +#define regDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x30eb +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x30ec +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x30ed +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x30ee +#define regDSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x30ef +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x30f0 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x30f1 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x30f2 +#define regDSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX0 0x30f3 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX1 0x30f4 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX2 0x30f5 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX3 0x30f6 +#define regDSCC2_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f7 +#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA0 0x30f8 +#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA1 0x30f9 +#define regDSCC2_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA2 0x30fa +#define regDSCC2_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC2_DSCC_TEST_DEBUG_DATA3 0x30fb +#define regDSCC2_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x30fc +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x30fd +#define regDSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc420 +#define regDC_PERFMON19_PERFCOUNTER_CNTL 0x3108 +#define regDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON19_PERFCOUNTER_CNTL2 0x3109 +#define regDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON19_PERFCOUNTER_STATE 0x310a +#define regDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CNTL 0x310b +#define regDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CNTL2 0x310c +#define regDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x310d +#define regDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_CVALUE_LOW 0x310e +#define regDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_HI 0x310f +#define regDC_PERFMON19_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON19_PERFMON_LOW 0x3110 +#define regDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +// base address: 0x450 +#define regDSC_TOP3_DSC_TOP_CONTROL 0x3114 +#define regDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2 +#define regDSC_TOP3_DSC_DEBUG_CONTROL 0x3115 +#define regDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2 +#define regDSC_TOP3_DSC_SPARE_DEBUG 0x3116 +#define regDSC_TOP3_DSC_SPARE_DEBUG_BASE_IDX 2 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX 0x3117 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA 0x3118 +#define regDSC_TOP3_DSC_TOP_TEST_DEBUG_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +// base address: 0x450 +#define regDSCCIF3_DSCCIF_CONFIG0 0x3119 +#define regDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +// base address: 0x450 +#define regDSCC3_DSCC_CONFIG0 0x311e +#define regDSCC3_DSCC_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_CONFIG1 0x311f +#define regDSCC3_DSCC_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_CONFIG2 0x3120 +#define regDSCC3_DSCC_CONFIG2_BASE_IDX 2 +#define regDSCC3_DSCC_STATUS 0x3121 +#define regDSCC3_DSCC_STATUS_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_CONTROL0 0x3122 +#define regDSCC3_DSCC_INTERRUPT_CONTROL0_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_CONTROL1 0x3123 +#define regDSCC3_DSCC_INTERRUPT_CONTROL1_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_STATUS0 0x3124 +#define regDSCC3_DSCC_INTERRUPT_STATUS0_BASE_IDX 2 +#define regDSCC3_DSCC_INTERRUPT_STATUS1 0x3125 +#define regDSCC3_DSCC_INTERRUPT_STATUS1_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG0 0x3126 +#define regDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG1 0x3127 +#define regDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG2 0x3128 +#define regDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG3 0x3129 +#define regDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG4 0x312a +#define regDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG5 0x312b +#define regDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG6 0x312c +#define regDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG7 0x312d +#define regDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG8 0x312e +#define regDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG9 0x312f +#define regDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG10 0x3130 +#define regDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG11 0x3131 +#define regDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG12 0x3132 +#define regDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG13 0x3133 +#define regDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG14 0x3134 +#define regDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG15 0x3135 +#define regDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG16 0x3136 +#define regDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG17 0x3137 +#define regDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG18 0x3138 +#define regDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG19 0x3139 +#define regDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG20 0x313a +#define regDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG21 0x313b +#define regDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2 +#define regDSCC3_DSCC_PPS_CONFIG22 0x313c +#define regDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2 +#define regDSCC3_DSCC_MEM_POWER_CONTROL0 0x313d +#define regDSCC3_DSCC_MEM_POWER_CONTROL0_BASE_IDX 2 +#define regDSCC3_DSCC_MEM_POWER_CONTROL1 0x313e +#define regDSCC3_DSCC_MEM_POWER_CONTROL1_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313f +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3140 +#define regDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3141 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3142 +#define regDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3143 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3144 +#define regDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR0 0x3145 +#define regDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2 +#define regDSCC3_DSCC_MAX_ABS_ERROR1 0x3146 +#define regDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 0x3147 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 0x3148 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 0x3149 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 0x314a +#define regDSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 0x314b +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 0x314c +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 0x314d +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_BASE_IDX 2 +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 0x314e +#define regDSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX0 0x314f +#define regDSCC3_DSCC_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX1 0x3150 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX1_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX2 0x3151 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX2_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX3 0x3152 +#define regDSCC3_DSCC_TEST_DEBUG_INDEX3_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x3153 +#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA0 0x3154 +#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA1 0x3155 +#define regDSCC3_DSCC_TEST_DEBUG_DATA1_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA2 0x3156 +#define regDSCC3_DSCC_TEST_DEBUG_DATA2_BASE_IDX 2 +#define regDSCC3_DSCC_TEST_DEBUG_DATA3 0x3157 +#define regDSCC3_DSCC_TEST_DEBUG_DATA3_BASE_IDX 2 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 0x3158 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0_BASE_IDX 2 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 0x3159 +#define regDSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0_BASE_IDX 2 + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +// base address: 0xc590 +#define regDC_PERFMON20_PERFCOUNTER_CNTL 0x3164 +#define regDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON20_PERFCOUNTER_CNTL2 0x3165 +#define regDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON20_PERFCOUNTER_STATE 0x3166 +#define regDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CNTL 0x3167 +#define regDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CNTL2 0x3168 +#define regDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x3169 +#define regDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_CVALUE_LOW 0x316a +#define regDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_HI 0x316b +#define regDC_PERFMON20_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON20_PERFMON_LOW 0x316c +#define regDC_PERFMON20_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +// base address: 0x0 +#define regDWB_ENABLE_CLK_CTRL 0x3228 +#define regDWB_ENABLE_CLK_CTRL_BASE_IDX 2 +#define regDWB_MEM_PWR_CTRL 0x3229 +#define regDWB_MEM_PWR_CTRL_BASE_IDX 2 +#define regFC_MODE_CTRL 0x322a +#define regFC_MODE_CTRL_BASE_IDX 2 +#define regFC_FLOW_CTRL 0x322b +#define regFC_FLOW_CTRL_BASE_IDX 2 +#define regFC_WINDOW_START 0x322c +#define regFC_WINDOW_START_BASE_IDX 2 +#define regFC_WINDOW_SIZE 0x322d +#define regFC_WINDOW_SIZE_BASE_IDX 2 +#define regFC_SOURCE_SIZE 0x322e +#define regFC_SOURCE_SIZE_BASE_IDX 2 +#define regDWB_UPDATE_CTRL 0x322f +#define regDWB_UPDATE_CTRL_BASE_IDX 2 +#define regDWB_CRC_CTRL 0x3230 +#define regDWB_CRC_CTRL_BASE_IDX 2 +#define regDWB_CRC_MASK_R_G 0x3231 +#define regDWB_CRC_MASK_R_G_BASE_IDX 2 +#define regDWB_CRC_MASK_B_A 0x3232 +#define regDWB_CRC_MASK_B_A_BASE_IDX 2 +#define regDWB_CRC_VAL_R_G 0x3233 +#define regDWB_CRC_VAL_R_G_BASE_IDX 2 +#define regDWB_CRC_VAL_B_A 0x3234 +#define regDWB_CRC_VAL_B_A_BASE_IDX 2 +#define regDWB_OUT_CTRL 0x3235 +#define regDWB_OUT_CTRL_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237 +#define regDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2 +#define regDWB_HOST_READ_CONTROL 0x3238 +#define regDWB_HOST_READ_CONTROL_BASE_IDX 2 +#define regDWB_OVERFLOW_STATUS 0x3239 +#define regDWB_OVERFLOW_STATUS_BASE_IDX 2 +#define regDWB_OVERFLOW_COUNTER 0x323a +#define regDWB_OVERFLOW_COUNTER_BASE_IDX 2 +#define regDWB_SOFT_RESET 0x323b +#define regDWB_SOFT_RESET_BASE_IDX 2 +#define regDWB_DEBUG_CTRL 0x323c +#define regDWB_DEBUG_CTRL_BASE_IDX 2 +#define regDWB_DEBUG 0x323d +#define regDWB_DEBUG_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +// base address: 0xca20 +#define regDC_PERFMON21_PERFCOUNTER_CNTL 0x3288 +#define regDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2 +#define regDC_PERFMON21_PERFCOUNTER_CNTL2 0x3289 +#define regDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2 +#define regDC_PERFMON21_PERFCOUNTER_STATE 0x328a +#define regDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CNTL 0x328b +#define regDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CNTL2 0x328c +#define regDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x328d +#define regDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_CVALUE_LOW 0x328e +#define regDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_HI 0x328f +#define regDC_PERFMON21_PERFMON_HI_BASE_IDX 2 +#define regDC_PERFMON21_PERFMON_LOW 0x3290 +#define regDC_PERFMON21_PERFMON_LOW_BASE_IDX 2 + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +// base address: 0x0 +#define regDWB_HDR_MULT_COEF 0x3294 +#define regDWB_HDR_MULT_COEF_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_MODE 0x3295 +#define regDWB_GAMUT_REMAP_MODE_BASE_IDX 2 +#define regDWB_GAMUT_REMAP_COEF_FORMAT 0x3296 +#define regDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C11_C12 0x3297 +#define regDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C13_C14 0x3298 +#define regDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C21_C22 0x3299 +#define regDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C23_C24 0x329a +#define regDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C31_C32 0x329b +#define regDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPA_C33_C34 0x329c +#define regDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C11_C12 0x329d +#define regDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C13_C14 0x329e +#define regDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C21_C22 0x329f +#define regDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C23_C24 0x32a0 +#define regDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C31_C32 0x32a1 +#define regDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2 +#define regDWB_GAMUT_REMAPB_C33_C34 0x32a2 +#define regDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2 +#define regDWB_OGAM_CONTROL 0x32a3 +#define regDWB_OGAM_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_LUT_INDEX 0x32a4 +#define regDWB_OGAM_LUT_INDEX_BASE_IDX 2 +#define regDWB_OGAM_LUT_DATA 0x32a5 +#define regDWB_OGAM_LUT_DATA_BASE_IDX 2 +#define regDWB_OGAM_LUT_CONTROL 0x32a6 +#define regDWB_OGAM_LUT_CONTROL_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_B 0x32a7 +#define regDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_G 0x32a8 +#define regDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_CNTL_R 0x32a9 +#define regDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa +#define regDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac +#define regDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae +#define regDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af +#define regDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_B 0x32b0 +#define regDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_B 0x32b1 +#define regDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_G 0x32b2 +#define regDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_G 0x32b3 +#define regDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL1_R 0x32b4 +#define regDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_END_CNTL2_R 0x32b5 +#define regDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_B 0x32b6 +#define regDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_G 0x32b7 +#define regDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMA_OFFSET_R 0x32b8 +#define regDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_0_1 0x32b9 +#define regDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_2_3 0x32ba +#define regDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_4_5 0x32bb +#define regDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_6_7 0x32bc +#define regDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_8_9 0x32bd +#define regDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_10_11 0x32be +#define regDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_12_13 0x32bf +#define regDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_14_15 0x32c0 +#define regDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_16_17 0x32c1 +#define regDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_18_19 0x32c2 +#define regDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_20_21 0x32c3 +#define regDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_22_23 0x32c4 +#define regDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_24_25 0x32c5 +#define regDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_26_27 0x32c6 +#define regDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_28_29 0x32c7 +#define regDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_30_31 0x32c8 +#define regDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMA_REGION_32_33 0x32c9 +#define regDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_B 0x32ca +#define regDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_G 0x32cb +#define regDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_CNTL_R 0x32cc +#define regDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd +#define regDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf +#define regDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1 +#define regDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2 +#define regDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_B 0x32d3 +#define regDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_B 0x32d4 +#define regDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_G 0x32d5 +#define regDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_G 0x32d6 +#define regDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL1_R 0x32d7 +#define regDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_END_CNTL2_R 0x32d8 +#define regDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_B 0x32d9 +#define regDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_G 0x32da +#define regDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2 +#define regDWB_OGAM_RAMB_OFFSET_R 0x32db +#define regDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_0_1 0x32dc +#define regDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_2_3 0x32dd +#define regDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_4_5 0x32de +#define regDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_6_7 0x32df +#define regDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_8_9 0x32e0 +#define regDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_10_11 0x32e1 +#define regDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_12_13 0x32e2 +#define regDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_14_15 0x32e3 +#define regDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_16_17 0x32e4 +#define regDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_18_19 0x32e5 +#define regDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_20_21 0x32e6 +#define regDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_22_23 0x32e7 +#define regDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_24_25 0x32e8 +#define regDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_26_27 0x32e9 +#define regDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_28_29 0x32ea +#define regDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_30_31 0x32eb +#define regDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2 +#define regDWB_OGAM_RAMB_REGION_32_33 0x32ec +#define regDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2 + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +// base address: 0x0 +#define regDCHVM_CTRL0 0x3603 +#define regDCHVM_CTRL0_BASE_IDX 2 +#define regDCHVM_CTRL1 0x3604 +#define regDCHVM_CTRL1_BASE_IDX 2 +#define regDCHVM_CLK_CTRL 0x3605 +#define regDCHVM_CLK_CTRL_BASE_IDX 2 +#define regDCHVM_MEM_CTRL 0x3606 +#define regDCHVM_MEM_CTRL_BASE_IDX 2 +#define regDCHVM_RIOMMU_CTRL0 0x3607 +#define regDCHVM_RIOMMU_CTRL0_BASE_IDX 2 +#define regDCHVM_RIOMMU_STAT0 0x3608 +#define regDCHVM_RIOMMU_STAT0_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +// base address: 0x1ab8c +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL 0x3623 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x3624 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL 0x3625 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x3626 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x3627 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE 0x3628 +#define regDP_STREAM_ENC0_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +// base address: 0x1abc0 +#define regAPG5_APG_CONTROL 0x3630 +#define regAPG5_APG_CONTROL_BASE_IDX 2 +#define regAPG5_APG_CONTROL2 0x3631 +#define regAPG5_APG_CONTROL2_BASE_IDX 2 +#define regAPG5_APG_DBG_GEN_CONTROL 0x3632 +#define regAPG5_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG5_APG_MEM_PWR 0x3644 +#define regAPG5_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +// base address: 0x1ac38 +#define regDME5_DME_CONTROL 0x364e +#define regDME5_DME_CONTROL_BASE_IDX 2 +#define regDME5_DME_MEMORY_CONTROL 0x364f +#define regDME5_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +// base address: 0x1ac44 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3651 +#define regVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG5_VPG_GENERIC_PACKET_DATA 0x3652 +#define regVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x3653 +#define regVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3654 +#define regVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG5_VPG_GENERIC_STATUS 0x3655 +#define regVPG5_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG5_VPG_MEM_PWR 0x3656 +#define regVPG5_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x3657 +#define regVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG5_VPG_ISRC1_2_DATA 0x3658 +#define regVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +// base address: 0x1ac74 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL 0x365d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL 0x365e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x365f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3660 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3661 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 0x3662 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 0x3663 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 0x3664 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 0x3665 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 0x3666 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 0x3667 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 0x3668 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 0x3669 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 0x366a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL 0x366b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x366c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x366d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x366e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x366f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3670 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3671 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3672 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3673 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3674 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3675 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x3676 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x3677 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3678 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3679 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x367a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL 0x367b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x367c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x367d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x367e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL 0x3683 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL 0x3684 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3685 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3686 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL 0x3687 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 0x3688 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 0x3689 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2 0x368a +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3 0x368b +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS 0x368c +#define regDP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x368d +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x368e +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x368f +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3690 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3691 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3692 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3693 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS 0x3694 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL 0x3695 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3696 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3697 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3698 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE 0x3699 +#define regDP_SYM32_ENC0_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +// base address: 0x1ad7c +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL 0x369f +#define regDP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE 0x36a0 +#define regDP_LINK_ENC0_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +// base address: 0x1add0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL 0x36b4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS 0x36b5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE 0x36b8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 0x36b9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 0x36ba +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 0x36bb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 0x36bc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 0x36bf +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 0x36c0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 0x36c1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 0x36c2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 0x36c5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 0x36c6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 0x36c7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 0x36c8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 0x36cb +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 0x36cc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 0x36cd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 0x36ce +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 0x36cf +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x36d0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x36d1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL 0x36d3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG 0x36d4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 0x36d5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 0x36d6 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 0x36d7 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 0x36d8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE 0x36d9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 0x36da +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 0x36db +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 0x36dc +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 0x36dd +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 0x36de +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 0x36df +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 0x36e0 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 0x36e1 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 0x36e2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 0x36e3 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 0x36e4 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS 0x36e5 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x36e8 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x36e9 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x36ea +#define regDP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +// base address: 0x1aedc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL 0x36f7 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x36f8 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL 0x36f9 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x36fa +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x36fb +#define regDP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE 0x36fc +#define regDP_STREAM_ENC1_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +// base address: 0x1af10 +#define regAPG6_APG_CONTROL 0x3704 +#define regAPG6_APG_CONTROL_BASE_IDX 2 +#define regAPG6_APG_CONTROL2 0x3705 +#define regAPG6_APG_CONTROL2_BASE_IDX 2 +#define regAPG6_APG_DBG_GEN_CONTROL 0x3706 +#define regAPG6_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG6_APG_MEM_PWR 0x3718 +#define regAPG6_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +// base address: 0x1af88 +#define regDME6_DME_CONTROL 0x3722 +#define regDME6_DME_CONTROL_BASE_IDX 2 +#define regDME6_DME_MEMORY_CONTROL 0x3723 +#define regDME6_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +// base address: 0x1af94 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x3725 +#define regVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_PACKET_DATA 0x3726 +#define regVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x3727 +#define regVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x3728 +#define regVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG6_VPG_GENERIC_STATUS 0x3729 +#define regVPG6_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG6_VPG_MEM_PWR 0x372a +#define regVPG6_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x372b +#define regVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG6_VPG_ISRC1_2_DATA 0x372c +#define regVPG6_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +// base address: 0x1afc4 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL 0x3731 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3732 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3733 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3734 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3735 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 0x3736 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 0x3737 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 0x3738 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 0x3739 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 0x373a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 0x373b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 0x373c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 0x373d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 0x373e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL 0x373f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3740 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3741 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3742 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3743 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3744 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3745 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x3746 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x3747 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x3748 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x3749 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x374a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x374b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x374c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x374d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x374e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL 0x374f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3750 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3751 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3752 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL 0x3757 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL 0x3758 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3759 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x375a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL 0x375b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 0x375c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 0x375d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2 0x375e +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3 0x375f +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS 0x3760 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3761 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3762 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3763 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3764 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3765 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL 0x3766 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x3767 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS 0x3768 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL 0x3769 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x376a +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x376b +#define regDP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL 0x376c +#define regDP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE 0x376d +#define regDP_SYM32_ENC1_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +// base address: 0x1b0cc +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL 0x3773 +#define regDP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE 0x3774 +#define regDP_LINK_ENC1_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +// base address: 0x1b120 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL 0x3788 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS 0x3789 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE 0x378c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 0x378d +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 0x378e +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 0x378f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3790 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 0x3793 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 0x3794 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 0x3795 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 0x3796 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3799 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 0x379a +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 0x379b +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 0x379c +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 0x379f +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 0x37a0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 0x37a1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 0x37a2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 0x37a3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x37a4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x37a5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL 0x37a7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG 0x37a8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 0x37a9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 0x37aa +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 0x37ab +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 0x37ac +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE 0x37ad +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 0x37ae +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 0x37af +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 0x37b0 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 0x37b1 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 0x37b2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 0x37b3 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 0x37b4 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 0x37b5 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 0x37b6 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 0x37b7 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 0x37b8 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS 0x37b9 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x37bc +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x37bd +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x37be +#define regDP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +// base address: 0x1b22c +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL 0x37cb +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x37cc +#define regDP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL 0x37cd +#define regDP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x37ce +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x37cf +#define regDP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE 0x37d0 +#define regDP_STREAM_ENC2_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +// base address: 0x1b260 +#define regAPG7_APG_CONTROL 0x37d8 +#define regAPG7_APG_CONTROL_BASE_IDX 2 +#define regAPG7_APG_CONTROL2 0x37d9 +#define regAPG7_APG_CONTROL2_BASE_IDX 2 +#define regAPG7_APG_DBG_GEN_CONTROL 0x37da +#define regAPG7_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG7_APG_MEM_PWR 0x37ec +#define regAPG7_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +// base address: 0x1b2d8 +#define regDME7_DME_CONTROL 0x37f6 +#define regDME7_DME_CONTROL_BASE_IDX 2 +#define regDME7_DME_MEMORY_CONTROL 0x37f7 +#define regDME7_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +// base address: 0x1b2e4 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL 0x37f9 +#define regVPG7_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_PACKET_DATA 0x37fa +#define regVPG7_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL 0x37fb +#define regVPG7_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x37fc +#define regVPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG7_VPG_GENERIC_STATUS 0x37fd +#define regVPG7_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG7_VPG_MEM_PWR 0x37fe +#define regVPG7_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL 0x37ff +#define regVPG7_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG7_VPG_ISRC1_2_DATA 0x3800 +#define regVPG7_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +// base address: 0x1b314 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL 0x3805 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL 0x3806 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x3807 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x3808 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x3809 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 0x380a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 0x380b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 0x380c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 0x380d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 0x380e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 0x380f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 0x3810 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 0x3811 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 0x3812 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL 0x3813 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x3814 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x3815 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x3816 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x3817 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x3818 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x3819 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x381a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x381b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x381c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x381d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x381e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x381f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x3820 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x3821 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x3822 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL 0x3823 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x3824 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x3825 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x3826 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL 0x382b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL 0x382c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL 0x382d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x382e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL 0x382f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 0x3830 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 0x3831 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2 0x3832 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3 0x3833 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS 0x3834 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3835 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x3836 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x3837 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x3838 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x3839 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL 0x383a +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x383b +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS 0x383c +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL 0x383d +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x383e +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x383f +#define regDP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3840 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE 0x3841 +#define regDP_SYM32_ENC2_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc2_dispdec +// base address: 0x1b41c +#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL 0x3847 +#define regDP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE 0x3848 +#define regDP_LINK_ENC2_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym322_dispdec +// base address: 0x1b470 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL 0x385c +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS 0x385d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE 0x3860 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3861 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3862 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3863 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3864 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 0x3867 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 0x3868 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 0x3869 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 0x386a +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 0x386d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 0x386e +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 0x386f +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3870 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 0x3873 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 0x3874 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 0x3875 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 0x3876 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 0x3877 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x3878 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x3879 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL 0x387b +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG 0x387c +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 0x387d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 0x387e +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 0x387f +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3880 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE 0x3881 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 0x3882 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 0x3883 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 0x3884 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 0x3885 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 0x3886 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 0x3887 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 0x3888 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 0x3889 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 0x388a +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 0x388b +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 0x388c +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS 0x388d +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3890 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3891 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3892 +#define regDP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +// base address: 0x1b57c +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL 0x389f +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL 0x38a0 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL 0x38a1 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x38a2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x38a3 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 2 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE 0x38a4 +#define regDP_STREAM_ENC3_DP_STREAM_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +// base address: 0x1b5b0 +#define regAPG8_APG_CONTROL 0x38ac +#define regAPG8_APG_CONTROL_BASE_IDX 2 +#define regAPG8_APG_CONTROL2 0x38ad +#define regAPG8_APG_CONTROL2_BASE_IDX 2 +#define regAPG8_APG_DBG_GEN_CONTROL 0x38ae +#define regAPG8_APG_DBG_GEN_CONTROL_BASE_IDX 2 +#define regAPG8_APG_MEM_PWR 0x38c0 +#define regAPG8_APG_MEM_PWR_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +// base address: 0x1b628 +#define regDME8_DME_CONTROL 0x38ca +#define regDME8_DME_CONTROL_BASE_IDX 2 +#define regDME8_DME_MEMORY_CONTROL 0x38cb +#define regDME8_DME_MEMORY_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +// base address: 0x1b634 +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL 0x38cd +#define regVPG8_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_PACKET_DATA 0x38ce +#define regVPG8_VPG_GENERIC_PACKET_DATA_BASE_IDX 2 +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL 0x38cf +#define regVPG8_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x38d0 +#define regVPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2 +#define regVPG8_VPG_GENERIC_STATUS 0x38d1 +#define regVPG8_VPG_GENERIC_STATUS_BASE_IDX 2 +#define regVPG8_VPG_MEM_PWR 0x38d2 +#define regVPG8_VPG_MEM_PWR_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL 0x38d3 +#define regVPG8_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2 +#define regVPG8_VPG_ISRC1_2_DATA 0x38d4 +#define regVPG8_VPG_ISRC1_2_DATA_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +// base address: 0x1b664 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL 0x38d9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL 0x38da +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL 0x38db +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL 0x38dc +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT 0x38dd +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 0x38de +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 0x38df +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 0x38e0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 0x38e1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 0x38e2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 0x38e3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 0x38e4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 0x38e5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 0x38e6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL 0x38e7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 0x38e8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 0x38e9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 0x38ea +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 0x38eb +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 0x38ec +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 0x38ed +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 0x38ee +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 0x38ef +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 0x38f0 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 0x38f1 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 0x38f2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 0x38f3 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 0x38f4 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 0x38f5 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 0x38f6 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL 0x38f7 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 0x38f8 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 0x38f9 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL 0x38fa +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL 0x38ff +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL 0x3900 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL 0x3901 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL 0x3902 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL 0x3903 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 0x3904 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 0x3905 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2 0x3906 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3 0x3907 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS 0x3908 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS 0x3909 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL 0x390a +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL 0x390b +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL 0x390c +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET 0x390d +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL 0x390e +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL 0x390f +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS 0x3910 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL 0x3911 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL 0x3912 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS 0x3913 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL 0x3914 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL_BASE_IDX 2 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE 0x3915 +#define regDP_SYM32_ENC3_DP_SYM32_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_link_enc3_dispdec +// base address: 0x1b76c +#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL 0x391b +#define regDP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL_BASE_IDX 2 +#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE 0x391c +#define regDP_LINK_ENC3_DP_LINK_ENC_SPARE_BASE_IDX 2 + + +// addressBlock: dce_dc_hpo_dp_dphy_sym323_dispdec +// base address: 0x1b7c0 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL 0x3930 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS 0x3931 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE 0x3934 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 0x3935 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 0x3936 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 0x3937 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 0x3938 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 0x393b +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 0x393c +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 0x393d +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 0x393e +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 0x3941 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 0x3942 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 0x3943 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 0x3944 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 0x3947 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 0x3948 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 0x3949 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 0x394a +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 0x394b +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 0x394c +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 0x394d +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL 0x394f +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG 0x3950 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 0x3951 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 0x3952 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 0x3953 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 0x3954 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE 0x3955 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 0x3956 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 0x3957 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 0x3958 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 0x3959 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 0x395a +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 0x395b +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 0x395c +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 0x395d +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 0x395e +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 0x395f +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 0x3960 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS 0x3961 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 0x3964 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 0x3965 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1_BASE_IDX 2 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL 0x3966 +#define regDP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL_BASE_IDX 2 + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +// base address: 0x0 +#define regMPCC0_MPCC_TOP_SEL 0x0000 +#define regMPCC0_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_SEL 0x0001 +#define regMPCC0_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_OPP_ID 0x0002 +#define regMPCC0_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL 0x0003 +#define regMPCC0_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_CONTROL2 0x0004 +#define regMPCC0_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC0_MPCC_SM_CONTROL 0x0005 +#define regMPCC0_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL 0x0006 +#define regMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC0_MPCC_TOP_GAIN 0x0007 +#define regMPCC0_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE 0x0008 +#define regMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0009 +#define regMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x000a +#define regMPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC0_MPCC_BG_R_CR 0x000b +#define regMPCC0_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC0_MPCC_BG_G_Y 0x000c +#define regMPCC0_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC0_MPCC_BG_B_CB 0x000d +#define regMPCC0_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC0_MPCC_MEM_PWR_CTRL 0x000e +#define regMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC0_MPCC_STATUS 0x000f +#define regMPCC0_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +// base address: 0x54 +#define regMPCC1_MPCC_TOP_SEL 0x0015 +#define regMPCC1_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_SEL 0x0016 +#define regMPCC1_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_OPP_ID 0x0017 +#define regMPCC1_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL 0x0018 +#define regMPCC1_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_CONTROL2 0x0019 +#define regMPCC1_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC1_MPCC_SM_CONTROL 0x001a +#define regMPCC1_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_UPDATE_LOCK_SEL 0x001b +#define regMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC1_MPCC_TOP_GAIN 0x001c +#define regMPCC1_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_INSIDE 0x001d +#define regMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x001e +#define regMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x001f +#define regMPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC1_MPCC_BG_R_CR 0x0020 +#define regMPCC1_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC1_MPCC_BG_G_Y 0x0021 +#define regMPCC1_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC1_MPCC_BG_B_CB 0x0022 +#define regMPCC1_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC1_MPCC_MEM_PWR_CTRL 0x0023 +#define regMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC1_MPCC_STATUS 0x0024 +#define regMPCC1_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +// base address: 0xa8 +#define regMPCC2_MPCC_TOP_SEL 0x002a +#define regMPCC2_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_SEL 0x002b +#define regMPCC2_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_OPP_ID 0x002c +#define regMPCC2_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL 0x002d +#define regMPCC2_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_CONTROL2 0x002e +#define regMPCC2_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC2_MPCC_SM_CONTROL 0x002f +#define regMPCC2_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL 0x0030 +#define regMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC2_MPCC_TOP_GAIN 0x0031 +#define regMPCC2_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE 0x0032 +#define regMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0033 +#define regMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0034 +#define regMPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC2_MPCC_BG_R_CR 0x0035 +#define regMPCC2_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC2_MPCC_BG_G_Y 0x0036 +#define regMPCC2_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC2_MPCC_BG_B_CB 0x0037 +#define regMPCC2_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC2_MPCC_MEM_PWR_CTRL 0x0038 +#define regMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC2_MPCC_STATUS 0x0039 +#define regMPCC2_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +// base address: 0xfc +#define regMPCC3_MPCC_TOP_SEL 0x003f +#define regMPCC3_MPCC_TOP_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_SEL 0x0040 +#define regMPCC3_MPCC_BOT_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_OPP_ID 0x0041 +#define regMPCC3_MPCC_OPP_ID_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL 0x0042 +#define regMPCC3_MPCC_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_CONTROL2 0x0043 +#define regMPCC3_MPCC_CONTROL2_BASE_IDX 3 +#define regMPCC3_MPCC_SM_CONTROL 0x0044 +#define regMPCC3_MPCC_SM_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL 0x0045 +#define regMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3 +#define regMPCC3_MPCC_TOP_GAIN 0x0046 +#define regMPCC3_MPCC_TOP_GAIN_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE 0x0047 +#define regMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0048 +#define regMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL 0x0049 +#define regMPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL_BASE_IDX 3 +#define regMPCC3_MPCC_BG_R_CR 0x004a +#define regMPCC3_MPCC_BG_R_CR_BASE_IDX 3 +#define regMPCC3_MPCC_BG_G_Y 0x004b +#define regMPCC3_MPCC_BG_G_Y_BASE_IDX 3 +#define regMPCC3_MPCC_BG_B_CB 0x004c +#define regMPCC3_MPCC_BG_B_CB_BASE_IDX 3 +#define regMPCC3_MPCC_MEM_PWR_CTRL 0x004d +#define regMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC3_MPCC_STATUS 0x004e +#define regMPCC3_MPCC_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +// base address: 0x0 +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL 0x007e +#define regMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x007f +#define regMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0080 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0081 +#define regMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0082 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0083 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0084 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0085 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0086 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0087 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0088 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0089 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x008a +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x008b +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x008c +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x008d +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x008e +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x008f +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0090 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0091 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0092 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0093 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0094 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0095 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0096 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0097 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x0098 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x0099 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x009a +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x009b +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x009c +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x009d +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x009e +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x009f +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x00a0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x00a1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x00a2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x00a3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x00a4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x00a5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x00a6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x00a7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x00a8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x00a9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x00aa +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x00ab +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x00ac +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x00ad +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x00ae +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x00af +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x00b0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x00b1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x00b2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x00b3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x00b4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x00b5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x00b6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x00b7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x00b8 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x00b9 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x00ba +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x00bb +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x00bc +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x00bd +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x00be +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x00bf +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x00c0 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x00c1 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x00c2 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x00c3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x00c4 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x00c5 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x00c6 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x00c7 +#define regMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x00c8 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x00c9 +#define regMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x00ca +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x00cb +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x00cc +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x00cd +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x00ce +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x00cf +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x00d0 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x00d1 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x00d2 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x00d3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x00d4 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x00d5 +#define regMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +// base address: 0x178 +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL 0x00dc +#define regMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x00dd +#define regMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x00de +#define regMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x00df +#define regMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x00e0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x00e1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x00e2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x00e3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x00e4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x00e5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x00e6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x00e7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x00e8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x00e9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x00ea +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x00eb +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x00ec +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x00ed +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x00ee +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x00ef +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x00f0 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x00f1 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x00f2 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x00f3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x00f4 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x00f5 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x00f6 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x00f7 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x00f8 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x00f9 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x00fa +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x00fb +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x00fc +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x00fd +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x00fe +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x00ff +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x0100 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x0101 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x0102 +#define regMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x0103 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x0104 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x0105 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0106 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0107 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0108 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0109 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x010a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x010b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x010c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x010d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x010e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x010f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x0110 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x0111 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x0112 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x0113 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x0114 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x0115 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x0116 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x0117 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x0118 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x0119 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x011a +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x011b +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x011c +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x011d +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x011e +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x011f +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x0120 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x0121 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x0122 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x0123 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x0124 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x0125 +#define regMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0126 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x0127 +#define regMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x0128 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x0129 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x012a +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x012b +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x012c +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x012d +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x012e +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x012f +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x0130 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x0131 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x0132 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x0133 +#define regMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +// base address: 0x2f0 +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL 0x013a +#define regMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x013b +#define regMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x013c +#define regMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x013d +#define regMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x013e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x013f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0140 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0141 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0142 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0143 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x0144 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x0145 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x0146 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x0147 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x0148 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x0149 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x014a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x014b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x014c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x014d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x014e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x014f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0150 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0151 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0152 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0153 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x0154 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x0155 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x0156 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x0157 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x0158 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x0159 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x015a +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x015b +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x015c +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x015d +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x015e +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x015f +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0160 +#define regMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0161 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0162 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0163 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x0164 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x0165 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x0166 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x0167 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x0168 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x0169 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x016a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x016b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x016c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x016d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x016e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x016f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0170 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0171 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0172 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0173 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x0174 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x0175 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x0176 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x0177 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x0178 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x0179 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x017a +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x017b +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x017c +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x017d +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x017e +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x017f +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0180 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0181 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0182 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0183 +#define regMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x0184 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x0185 +#define regMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x0186 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x0187 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x0188 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x0189 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x018a +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x018b +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x018c +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x018d +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x018e +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x018f +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0190 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0191 +#define regMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +// base address: 0x468 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0198 +#define regMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0199 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x019a +#define regMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x019b +#define regMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x019c +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x019d +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x019e +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x019f +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x01a0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x01a1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x01a2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x01a3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x01a4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x01a5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x01a6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x01a7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x01a8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x01a9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x01aa +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x01ab +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x01ac +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x01ad +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x01ae +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x01af +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x01b0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x01b1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x01b2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x01b3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x01b4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x01b5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x01b6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x01b7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x01b8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x01b9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x01ba +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x01bb +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x01bc +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x01bd +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x01be +#define regMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x01bf +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x01c0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x01c1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01c2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01c3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01c4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01c5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01c6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01c7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x01c8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x01c9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x01ca +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x01cb +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x01cc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x01cd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x01ce +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x01cf +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x01d0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x01d1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x01d2 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x01d3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x01d4 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x01d5 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x01d6 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x01d7 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x01d8 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x01d9 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x01da +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x01db +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x01dc +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x01dd +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x01de +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x01df +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x01e0 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x01e1 +#define regMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01e2 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x01e3 +#define regMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x01e4 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x01e5 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x01e6 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x01e7 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x01e8 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x01e9 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x01ea +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x01eb +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x01ec +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x01ed +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x01ee +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x01ef +#define regMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +// base address: 0x0 +#define regMPC_OUT0_MUX 0x02b2 +#define regMPC_OUT0_MUX_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CONTROL 0x02b3 +#define regMPC_OUT0_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_G_Y 0x02b4 +#define regMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT0_DENORM_CLAMP_B_CB 0x02b5 +#define regMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT1_MUX 0x02b6 +#define regMPC_OUT1_MUX_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CONTROL 0x02b7 +#define regMPC_OUT1_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_G_Y 0x02b8 +#define regMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT1_DENORM_CLAMP_B_CB 0x02b9 +#define regMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT2_MUX 0x02ba +#define regMPC_OUT2_MUX_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CONTROL 0x02bb +#define regMPC_OUT2_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_G_Y 0x02bc +#define regMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT2_DENORM_CLAMP_B_CB 0x02bd +#define regMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT3_MUX 0x02be +#define regMPC_OUT3_MUX_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CONTROL 0x02bf +#define regMPC_OUT3_DENORM_CONTROL_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_G_Y 0x02c0 +#define regMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3 +#define regMPC_OUT3_DENORM_CLAMP_B_CB 0x02c1 +#define regMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3 +#define regMPC_OUT_CSC_COEF_FORMAT 0x02ca +#define regMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3 +#define regMPC_OUT0_CSC_MODE 0x02cb +#define regMPC_OUT0_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_A 0x02cc +#define regMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_A 0x02cd +#define regMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_A 0x02ce +#define regMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_A 0x02cf +#define regMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_A 0x02d0 +#define regMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_A 0x02d1 +#define regMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT0_CSC_C11_C12_B 0x02d2 +#define regMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C13_C14_B 0x02d3 +#define regMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C21_C22_B 0x02d4 +#define regMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C23_C24_B 0x02d5 +#define regMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C31_C32_B 0x02d6 +#define regMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT0_CSC_C33_C34_B 0x02d7 +#define regMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_MODE 0x02d8 +#define regMPC_OUT1_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_A 0x02d9 +#define regMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_A 0x02da +#define regMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_A 0x02db +#define regMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_A 0x02dc +#define regMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_A 0x02dd +#define regMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_A 0x02de +#define regMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT1_CSC_C11_C12_B 0x02df +#define regMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C13_C14_B 0x02e0 +#define regMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C21_C22_B 0x02e1 +#define regMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C23_C24_B 0x02e2 +#define regMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C31_C32_B 0x02e3 +#define regMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT1_CSC_C33_C34_B 0x02e4 +#define regMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_MODE 0x02e5 +#define regMPC_OUT2_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_A 0x02e6 +#define regMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_A 0x02e7 +#define regMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_A 0x02e8 +#define regMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_A 0x02e9 +#define regMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_A 0x02ea +#define regMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_A 0x02eb +#define regMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT2_CSC_C11_C12_B 0x02ec +#define regMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C13_C14_B 0x02ed +#define regMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C21_C22_B 0x02ee +#define regMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C23_C24_B 0x02ef +#define regMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C31_C32_B 0x02f0 +#define regMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT2_CSC_C33_C34_B 0x02f1 +#define regMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_MODE 0x02f2 +#define regMPC_OUT3_CSC_MODE_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_A 0x02f3 +#define regMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_A 0x02f4 +#define regMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_A 0x02f5 +#define regMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_A 0x02f6 +#define regMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_A 0x02f7 +#define regMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_A 0x02f8 +#define regMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3 +#define regMPC_OUT3_CSC_C11_C12_B 0x02f9 +#define regMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C13_C14_B 0x02fa +#define regMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C21_C22_B 0x02fb +#define regMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C23_C24_B 0x02fc +#define regMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C31_C32_B 0x02fd +#define regMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3 +#define regMPC_OUT3_CSC_C33_C34_B 0x02fe +#define regMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3 +#define regMPC_OCSC_TEST_DEBUG_INDEX 0x031b +#define regMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_OCSC_TEST_DEBUG_DATA 0x031c +#define regMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_rmcm0_dispdec +// base address: 0x0 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_CONTROL 0x031f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R 0x0320 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G 0x0321 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B 0x0322 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R 0x0323 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B 0x0324 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX 0x0325 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA 0x0326 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x0327 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x0328 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x0329 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x032a +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x032b +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x032c +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x032d +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1 0x032e +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3 0x032f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5 0x0330 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7 0x0331 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9 0x0332 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11 0x0333 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13 0x0334 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15 0x0335 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17 0x0336 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19 0x0337 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21 0x0338 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23 0x0339 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25 0x033a +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27 0x033b +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29 0x033c +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31 0x033d +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33 0x033e +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B 0x033f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G 0x0340 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R 0x0341 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B 0x0342 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G 0x0343 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R 0x0344 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1 0x0345 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3 0x0346 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5 0x0347 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7 0x0348 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9 0x0349 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11 0x034a +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13 0x034b +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15 0x034c +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17 0x034d +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19 0x034e +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21 0x034f +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23 0x0350 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25 0x0351 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27 0x0352 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29 0x0353 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31 0x0354 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33 0x0355 +#define regMPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_MODE 0x0356 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_MODE_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_INDEX 0x0357 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA 0x0358 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT 0x0359 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x035a +#define regMPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x035b +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R 0x035c +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G 0x035d +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B 0x035e +#define regMPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x035f +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE 0x0360 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A 0x0361 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A 0x0362 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A 0x0363 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A 0x0364 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A 0x0365 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A 0x0366 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B 0x0367 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B 0x0368 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B 0x0369 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B 0x036a +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B 0x036b +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B 0x036c +#define regMPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL 0x036d +#define regMPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x036e +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS 0x036f +#define regMPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_CNTL 0x0370 +#define regMPC_RMCM0_MPC_RMCM_CNTL_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX 0x0372 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA 0x0373 +#define regMPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_rmcm1_dispdec +// base address: 0x168 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_CONTROL 0x0379 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R 0x037a +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G 0x037b +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B 0x037c +#define regMPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R 0x037d +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B 0x037e +#define regMPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX 0x037f +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA 0x0380 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x0381 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x0382 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x0383 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x0384 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x0385 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x0386 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x0387 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1 0x0388 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3 0x0389 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5 0x038a +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7 0x038b +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9 0x038c +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11 0x038d +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13 0x038e +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15 0x038f +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17 0x0390 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19 0x0391 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21 0x0392 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23 0x0393 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25 0x0394 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27 0x0395 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29 0x0396 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31 0x0397 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33 0x0398 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B 0x0399 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G 0x039a +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R 0x039b +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B 0x039c +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G 0x039d +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R 0x039e +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1 0x039f +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3 0x03a0 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5 0x03a1 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7 0x03a2 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9 0x03a3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11 0x03a4 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13 0x03a5 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15 0x03a6 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17 0x03a7 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19 0x03a8 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21 0x03a9 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23 0x03aa +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25 0x03ab +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27 0x03ac +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29 0x03ad +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31 0x03ae +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33 0x03af +#define regMPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_MODE 0x03b0 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_MODE_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_INDEX 0x03b1 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA 0x03b2 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT 0x03b3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x03b4 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x03b5 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R 0x03b6 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G 0x03b7 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B 0x03b8 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x03b9 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE 0x03ba +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A 0x03bb +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A 0x03bc +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A 0x03bd +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A 0x03be +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A 0x03bf +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A 0x03c0 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B 0x03c1 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B 0x03c2 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B 0x03c3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B 0x03c4 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B 0x03c5 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B 0x03c6 +#define regMPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL 0x03c7 +#define regMPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x03c8 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS 0x03c9 +#define regMPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_CNTL 0x03ca +#define regMPC_RMCM1_MPC_RMCM_CNTL_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_INDEX 0x03cc +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_INDEX_BASE_IDX 3 +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_DATA 0x03cd +#define regMPC_RMCM1_MPC_RMCM_TEST_DEBUG_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +// base address: 0x17e1c +#define regDC_PERFMON22_PERFCOUNTER_CNTL 0x0447 +#define regDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 3 +#define regDC_PERFMON22_PERFCOUNTER_CNTL2 0x0448 +#define regDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define regDC_PERFMON22_PERFCOUNTER_STATE 0x0449 +#define regDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CNTL 0x044a +#define regDC_PERFMON22_PERFMON_CNTL_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CNTL2 0x044b +#define regDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x044c +#define regDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_CVALUE_LOW 0x044d +#define regDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_HI 0x044e +#define regDC_PERFMON22_PERFMON_HI_BASE_IDX 3 +#define regDC_PERFMON22_PERFMON_LOW 0x044f +#define regDC_PERFMON22_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec +// base address: 0x0 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL 0x0453 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R 0x0454 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G 0x0455 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B 0x0456 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R 0x0457 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B 0x0458 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX 0x0459 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA 0x045a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x045b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x045c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x045d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x045e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x045f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0460 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0461 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0462 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0463 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0464 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0465 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0466 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0467 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0468 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0469 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x046a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x046b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x046c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x046d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x046e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x046f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0470 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0471 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0472 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0473 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0474 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0475 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0476 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0477 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0478 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0479 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x047a +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x047b +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x047c +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x047d +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x047e +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x047f +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0480 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0481 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0482 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0483 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0484 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0485 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0486 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0487 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0488 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0489 +#define regMPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE 0x048a +#define regMPCC_MCM0_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX 0x048b +#define regMPCC_MCM0_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA 0x048c +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT 0x048d +#define regMPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x048e +#define regMPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x048f +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0490 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0491 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0492 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL 0x0493 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX 0x0494 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA 0x0495 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL 0x0496 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0497 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0498 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0499 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x049a +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x049b +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x049c +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x049d +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x049e +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x049f +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x04a0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x04a1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x04a2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x04a3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x04a4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x04a5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x04a6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x04a7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x04a8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x04a9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x04aa +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x04ab +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x04ac +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x04ad +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x04ae +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x04af +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x04b0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x04b1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x04b2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x04b3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x04b4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x04b5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x04b6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x04b7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x04b8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x04b9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x04ba +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x04bb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x04bc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x04bd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x04be +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x04bf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x04c0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x04c1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x04c2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x04c3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x04c4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x04c5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x04c6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x04c7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x04c8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x04c9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x04ca +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x04cb +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x04cc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x04cd +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x04ce +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x04cf +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x04d0 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x04d1 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x04d2 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x04d3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x04d4 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x04d5 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x04d6 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x04d7 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x04d8 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x04d9 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x04da +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x04db +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x04dc +#define regMPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x04dd +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x04de +#define regMPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x04df +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x04e0 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x04e1 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x04e2 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x04e3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x04e4 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x04e5 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x04e6 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x04e7 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x04e8 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x04e9 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x04ea +#define regMPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x04eb +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x04ec +#define regMPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x04ed +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x04ee +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x04ef +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x04f0 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x04f1 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x04f2 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x04f3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x04f4 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x04f5 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x04f6 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x04f7 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x04f8 +#define regMPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL 0x04f9 +#define regMPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x04fa +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x04fb +#define regMPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec +// base address: 0x2c0 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL 0x0503 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R 0x0504 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G 0x0505 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B 0x0506 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R 0x0507 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B 0x0508 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX 0x0509 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA 0x050a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x050b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x050c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x050d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x050e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x050f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0510 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0511 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0512 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0513 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0514 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0515 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0516 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0517 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0518 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0519 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x051a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x051b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x051c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x051d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x051e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x051f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0520 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0521 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0522 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0523 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0524 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0525 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0526 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0527 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0528 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0529 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x052a +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x052b +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x052c +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x052d +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x052e +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x052f +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0530 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0531 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0532 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0533 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0534 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0535 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0536 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0537 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0538 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0539 +#define regMPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE 0x053a +#define regMPCC_MCM1_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX 0x053b +#define regMPCC_MCM1_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA 0x053c +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT 0x053d +#define regMPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x053e +#define regMPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x053f +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x0540 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x0541 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x0542 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL 0x0543 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX 0x0544 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA 0x0545 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL 0x0546 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x0547 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x0548 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x0549 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x054a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x054b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x054c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x054d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x054e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x054f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0550 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0551 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0552 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0553 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0554 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0555 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0556 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0557 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0558 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0559 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x055a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x055b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x055c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x055d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x055e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x055f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0560 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0561 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0562 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0563 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0564 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0565 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0566 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0567 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0568 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0569 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x056a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x056b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x056c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x056d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x056e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x056f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0570 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0571 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0572 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0573 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0574 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0575 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0576 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0577 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0578 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0579 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x057a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x057b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x057c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x057d +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x057e +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x057f +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0580 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0581 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0582 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0583 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0584 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0585 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0586 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0587 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0588 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0589 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x058a +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x058b +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x058c +#define regMPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x058d +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x058e +#define regMPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x058f +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0590 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0591 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0592 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0593 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0594 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0595 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0596 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0597 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0598 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0599 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x059a +#define regMPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x059b +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x059c +#define regMPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x059d +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x059e +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x059f +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x05a0 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x05a1 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x05a2 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x05a3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x05a4 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x05a5 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x05a6 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x05a7 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x05a8 +#define regMPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL 0x05a9 +#define regMPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x05aa +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x05ab +#define regMPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec +// base address: 0x580 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL 0x05b3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R 0x05b4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G 0x05b5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B 0x05b6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R 0x05b7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B 0x05b8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX 0x05b9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA 0x05ba +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x05bb +#define regMPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x05bc +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x05bd +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x05be +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x05bf +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x05c0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x05c1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x05c2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x05c3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x05c4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x05c5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x05c6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x05c7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x05c8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x05c9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x05ca +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x05cb +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x05cc +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x05cd +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x05ce +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x05cf +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x05d0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x05d1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x05d2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x05d3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x05d4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x05d5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x05d6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x05d7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x05d8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x05d9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x05da +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x05db +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x05dc +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x05dd +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x05de +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x05df +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x05e0 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x05e1 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x05e2 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x05e3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x05e4 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x05e5 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x05e6 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x05e7 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x05e8 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x05e9 +#define regMPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE 0x05ea +#define regMPCC_MCM2_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX 0x05eb +#define regMPCC_MCM2_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA 0x05ec +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT 0x05ed +#define regMPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x05ee +#define regMPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x05ef +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x05f0 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x05f1 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x05f2 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL 0x05f3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX 0x05f4 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA 0x05f5 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL 0x05f6 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x05f7 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x05f8 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x05f9 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x05fa +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x05fb +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x05fc +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x05fd +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x05fe +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x05ff +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x0600 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x0601 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x0602 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x0603 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x0604 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x0605 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x0606 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x0607 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x0608 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x0609 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x060a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x060b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x060c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x060d +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x060e +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x060f +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x0610 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x0611 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x0612 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x0613 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x0614 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x0615 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x0616 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x0617 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x0618 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x0619 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x061a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x061b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x061c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x061d +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x061e +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x061f +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x0620 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x0621 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x0622 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x0623 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x0624 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x0625 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x0626 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x0627 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x0628 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x0629 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x062a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x062b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x062c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x062d +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x062e +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x062f +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x0630 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x0631 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x0632 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x0633 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x0634 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x0635 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x0636 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x0637 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x0638 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x0639 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x063a +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x063b +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x063c +#define regMPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x063d +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x063e +#define regMPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x063f +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x0640 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x0641 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x0642 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x0643 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x0644 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x0645 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x0646 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x0647 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x0648 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x0649 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x064a +#define regMPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x064b +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x064c +#define regMPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x064d +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x064e +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x064f +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0650 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0651 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0652 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0653 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0654 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0655 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0656 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0657 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0658 +#define regMPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL 0x0659 +#define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x065a +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x065b +#define regMPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec +// base address: 0x840 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL 0x0663 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R 0x0664 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G 0x0665 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B 0x0666 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R 0x0667 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B 0x0668 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX 0x0669 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA 0x066a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK 0x066b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B 0x066c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G 0x066d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R 0x066e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B 0x066f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G 0x0670 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R 0x0671 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 0x0672 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 0x0673 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 0x0674 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 0x0675 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 0x0676 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 0x0677 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 0x0678 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 0x0679 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 0x067a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 0x067b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 0x067c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 0x067d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 0x067e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 0x067f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 0x0680 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 0x0681 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 0x0682 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B 0x0683 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G 0x0684 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R 0x0685 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B 0x0686 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G 0x0687 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R 0x0688 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 0x0689 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 0x068a +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 0x068b +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 0x068c +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 0x068d +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 0x068e +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 0x068f +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 0x0690 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 0x0691 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 0x0692 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 0x0693 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 0x0694 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 0x0695 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 0x0696 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 0x0697 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 0x0698 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 0x0699 +#define regMPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE 0x069a +#define regMPCC_MCM3_MPCC_MCM_3DLUT_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX 0x069b +#define regMPCC_MCM3_MPCC_MCM_3DLUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA 0x069c +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT 0x069d +#define regMPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL 0x069e +#define regMPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR 0x069f +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R 0x06a0 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G 0x06a1 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B 0x06a2 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL 0x06a3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX 0x06a4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA 0x06a5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL 0x06a6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x06a7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x06a8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x06a9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x06aa +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x06ab +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x06ac +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x06ad +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x06ae +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x06af +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x06b0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x06b1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x06b2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x06b3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x06b4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x06b5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B 0x06b6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G 0x06b7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R 0x06b8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 0x06b9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 0x06ba +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 0x06bb +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 0x06bc +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 0x06bd +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 0x06be +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 0x06bf +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 0x06c0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 0x06c1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 0x06c2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 0x06c3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 0x06c4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 0x06c5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 0x06c6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 0x06c7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 0x06c8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 0x06c9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B 0x06ca +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G 0x06cb +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R 0x06cc +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B 0x06cd +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G 0x06ce +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R 0x06cf +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B 0x06d0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G 0x06d1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R 0x06d2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B 0x06d3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B 0x06d4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G 0x06d5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G 0x06d6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R 0x06d7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R 0x06d8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B 0x06d9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G 0x06da +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R 0x06db +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 0x06dc +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 0x06dd +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 0x06de +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 0x06df +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 0x06e0 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 0x06e1 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 0x06e2 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 0x06e3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 0x06e4 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 0x06e5 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 0x06e6 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 0x06e7 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 0x06e8 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 0x06e9 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 0x06ea +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 0x06eb +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 0x06ec +#define regMPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x06ed +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x06ee +#define regMPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A 0x06ef +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A 0x06f0 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A 0x06f1 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A 0x06f2 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A 0x06f3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A 0x06f4 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B 0x06f5 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B 0x06f6 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B 0x06f7 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B 0x06f8 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B 0x06f9 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B 0x06fa +#define regMPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x06fb +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x06fc +#define regMPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A 0x06fd +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A 0x06fe +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A 0x06ff +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A 0x0700 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A 0x0701 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A 0x0702 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B 0x0703 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B 0x0704 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B 0x0705 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B 0x0706 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B 0x0707 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B_BASE_IDX 3 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B 0x0708 +#define regMPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL 0x0709 +#define regMPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT 0x070a +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT_BASE_IDX 3 +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS 0x070b +#define regMPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS_BASE_IDX 3 + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +// base address: 0x0 +#define regMPC_CLOCK_CONTROL 0x0873 +#define regMPC_CLOCK_CONTROL_BASE_IDX 3 +#define regMPC_SOFT_RESET 0x0874 +#define regMPC_SOFT_RESET_BASE_IDX 3 +#define regMPC_CRC_CTRL 0x0875 +#define regMPC_CRC_CTRL_BASE_IDX 3 +#define regMPC_CRC_SEL_CONTROL 0x0876 +#define regMPC_CRC_SEL_CONTROL_BASE_IDX 3 +#define regMPC_CRC_RESULT_A 0x0877 +#define regMPC_CRC_RESULT_A_BASE_IDX 3 +#define regMPC_CRC_RESULT_R 0x0878 +#define regMPC_CRC_RESULT_R_BASE_IDX 3 +#define regMPC_CRC_RESULT_G 0x0879 +#define regMPC_CRC_RESULT_G_BASE_IDX 3 +#define regMPC_CRC_RESULT_B 0x087a +#define regMPC_CRC_RESULT_B_BASE_IDX 3 +#define regMPC_PERFMON_EVENT_CTRL 0x087d +#define regMPC_PERFMON_EVENT_CTRL_BASE_IDX 3 +#define regMPC_BYPASS_BG_AR 0x087e +#define regMPC_BYPASS_BG_AR_BASE_IDX 3 +#define regMPC_BYPASS_BG_GB 0x087f +#define regMPC_BYPASS_BG_GB_BASE_IDX 3 +#define regMPC_HOST_READ_CONTROL 0x0880 +#define regMPC_HOST_READ_CONTROL_BASE_IDX 3 +#define regMPC_DPP_PENDING_STATUS 0x0881 +#define regMPC_DPP_PENDING_STATUS_BASE_IDX 3 +#define regMPC_PENDING_STATUS_MISC 0x0882 +#define regMPC_PENDING_STATUS_MISC_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0 0x0883 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET0 0x0884 +#define regADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET0 0x0885 +#define regADR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET0 0x0886 +#define regCFG_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET0 0x0887 +#define regCUR_VUPDATE_LOCK_SET0_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0888 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET1 0x0889 +#define regADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET1 0x088a +#define regADR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET1 0x088b +#define regCFG_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET1 0x088c +#define regCUR_VUPDATE_LOCK_SET1_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2 0x088d +#define regADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET2 0x088e +#define regADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET2 0x088f +#define regADR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET2 0x0890 +#define regCFG_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET2 0x0891 +#define regCUR_VUPDATE_LOCK_SET2_BASE_IDX 3 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3 0x0892 +#define regADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_CFG_VUPDATE_LOCK_SET3 0x0893 +#define regADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regADR_VUPDATE_LOCK_SET3 0x0894 +#define regADR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCFG_VUPDATE_LOCK_SET3 0x0895 +#define regCFG_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regCUR_VUPDATE_LOCK_SET3 0x0896 +#define regCUR_VUPDATE_LOCK_SET3_BASE_IDX 3 +#define regHUBP0_3DLUT_FL_CONFIG 0x0897 +#define regHUBP0_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP0_3DLUT_FL_BIAS_SCALE 0x0898 +#define regHUBP0_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regHUBP1_3DLUT_FL_CONFIG 0x0899 +#define regHUBP1_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP1_3DLUT_FL_BIAS_SCALE 0x089a +#define regHUBP1_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regHUBP2_3DLUT_FL_CONFIG 0x089b +#define regHUBP2_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP2_3DLUT_FL_BIAS_SCALE 0x089c +#define regHUBP2_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regHUBP3_3DLUT_FL_CONFIG 0x089d +#define regHUBP3_3DLUT_FL_CONFIG_BASE_IDX 3 +#define regHUBP3_3DLUT_FL_BIAS_SCALE 0x089e +#define regHUBP3_3DLUT_FL_BIAS_SCALE_BASE_IDX 3 +#define regMPC_DWB0_MUX 0x08ad +#define regMPC_DWB0_MUX_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +// base address: 0x2634c +#define regHDMI_STREAM_ENC_CLOCK_CONTROL 0x08d3 +#define regHDMI_STREAM_ENC_CLOCK_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL 0x08d4 +#define regHDMI_STREAM_ENC_INPUT_MUX_CONTROL_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 0x08d5 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 0x08d6 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1_BASE_IDX 3 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 0x08d7 +#define regHDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2_BASE_IDX 3 +#define regHDMI_STREAM_ENC_AUDIO_CONTROL 0x08d8 +#define regHDMI_STREAM_ENC_AUDIO_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +// base address: 0x2637c +#define regHDMI_TB_ENC_CONTROL 0x08df +#define regHDMI_TB_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_PIXEL_FORMAT 0x08e0 +#define regHDMI_TB_ENC_PIXEL_FORMAT_BASE_IDX 3 +#define regHDMI_TB_ENC_PACKET_CONTROL 0x08e1 +#define regHDMI_TB_ENC_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL 0x08e2 +#define regHDMI_TB_ENC_ACR_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1 0x08e3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2 0x08e4 +#define regHDMI_TB_ENC_VBI_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GC_CONTROL 0x08e5 +#define regHDMI_TB_ENC_GC_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0 0x08e6 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL0_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1 0x08e7 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL1_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2 0x08e8 +#define regHDMI_TB_ENC_GENERIC_PACKET_CONTROL2_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE 0x08e9 +#define regHDMI_TB_ENC_GENERIC_PACKET0_1_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE 0x08ea +#define regHDMI_TB_ENC_GENERIC_PACKET2_3_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE 0x08eb +#define regHDMI_TB_ENC_GENERIC_PACKET4_5_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE 0x08ec +#define regHDMI_TB_ENC_GENERIC_PACKET6_7_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE 0x08ed +#define regHDMI_TB_ENC_GENERIC_PACKET8_9_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE 0x08ee +#define regHDMI_TB_ENC_GENERIC_PACKET10_11_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE 0x08ef +#define regHDMI_TB_ENC_GENERIC_PACKET12_13_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE 0x08f0 +#define regHDMI_TB_ENC_GENERIC_PACKET14_LINE_BASE_IDX 3 +#define regHDMI_TB_ENC_DB_CONTROL 0x08f1 +#define regHDMI_TB_ENC_DB_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_0 0x08f2 +#define regHDMI_TB_ENC_ACR_32_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_32_1 0x08f3 +#define regHDMI_TB_ENC_ACR_32_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_0 0x08f4 +#define regHDMI_TB_ENC_ACR_44_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_44_1 0x08f5 +#define regHDMI_TB_ENC_ACR_44_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_0 0x08f6 +#define regHDMI_TB_ENC_ACR_48_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_48_1 0x08f7 +#define regHDMI_TB_ENC_ACR_48_1_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_0 0x08f8 +#define regHDMI_TB_ENC_ACR_STATUS_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ACR_STATUS_1 0x08f9 +#define regHDMI_TB_ENC_ACR_STATUS_1_BASE_IDX 3 +#define regHDMI_TB_ENC_BUFFER_CONTROL 0x08fb +#define regHDMI_TB_ENC_BUFFER_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MEM_CTRL 0x08fe +#define regHDMI_TB_ENC_MEM_CTRL_BASE_IDX 3 +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL 0x08ff +#define regHDMI_TB_ENC_METADATA_PACKET_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK 0x0900 +#define regHDMI_TB_ENC_H_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK 0x0901 +#define regHDMI_TB_ENC_HC_ACTIVE_BLANK_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_CNTL 0x0903 +#define regHDMI_TB_ENC_CRC_CNTL_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_0 0x0904 +#define regHDMI_TB_ENC_CRC_RESULT_0_BASE_IDX 3 +#define regHDMI_TB_ENC_ENCRYPTION_CONTROL 0x0907 +#define regHDMI_TB_ENC_ENCRYPTION_CONTROL_BASE_IDX 3 +#define regHDMI_TB_ENC_MODE 0x0908 +#define regHDMI_TB_ENC_MODE_BASE_IDX 3 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS 0x0909 +#define regHDMI_TB_ENC_INPUT_FIFO_STATUS_BASE_IDX 3 +#define regHDMI_TB_ENC_CRC_RESULT_1 0x090a +#define regHDMI_TB_ENC_CRC_RESULT_1_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_apg_apg_dispdec +// base address: 0x2644c +#define regAPG9_APG_CONTROL 0x0913 +#define regAPG9_APG_CONTROL_BASE_IDX 3 +#define regAPG9_APG_CONTROL2 0x0914 +#define regAPG9_APG_CONTROL2_BASE_IDX 3 +#define regAPG9_APG_DBG_GEN_CONTROL 0x0915 +#define regAPG9_APG_DBG_GEN_CONTROL_BASE_IDX 3 +#define regAPG9_APG_MEM_PWR 0x0927 +#define regAPG9_APG_MEM_PWR_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +// base address: 0x264c4 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931 +#define regVPG9_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3 +#define regVPG9_VPG_GENERIC_PACKET_DATA 0x0932 +#define regVPG9_VPG_GENERIC_PACKET_DATA_BASE_IDX 3 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL 0x0933 +#define regVPG9_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934 +#define regVPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3 +#define regVPG9_VPG_GENERIC_STATUS 0x0935 +#define regVPG9_VPG_GENERIC_STATUS_BASE_IDX 3 +#define regVPG9_VPG_MEM_PWR 0x0936 +#define regVPG9_VPG_MEM_PWR_BASE_IDX 3 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL 0x0937 +#define regVPG9_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3 +#define regVPG9_VPG_ISRC1_2_DATA 0x0938 +#define regVPG9_VPG_ISRC1_2_DATA_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +// base address: 0x264f0 +#define regDME9_DME_CONTROL 0x093c +#define regDME9_DME_CONTROL_BASE_IDX 3 +#define regDME9_DME_MEMORY_CONTROL 0x093d +#define regDME9_DME_MEMORY_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +// base address: 0x2656c +#define regHDMI_LINK_ENC_CONTROL 0x095b +#define regHDMI_LINK_ENC_CONTROL_BASE_IDX 3 +#define regHDMI_LINK_ENC_CLK_CTRL 0x095c +#define regHDMI_LINK_ENC_CLK_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +// base address: 0x26594 +#define regHDMI_FRL_ENC_CONFIG 0x0965 +#define regHDMI_FRL_ENC_CONFIG_BASE_IDX 3 +#define regHDMI_FRL_ENC_CONFIG2 0x0966 +#define regHDMI_FRL_ENC_CONFIG2_BASE_IDX 3 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS 0x0967 +#define regHDMI_FRL_ENC_METER_BUFFER_STATUS_BASE_IDX 3 +#define regHDMI_FRL_ENC_MEM_CTRL 0x0968 +#define regHDMI_FRL_ENC_MEM_CTRL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +// base address: 0x2790c +#define regHPO_TOP_CLOCK_CONTROL 0x0e43 +#define regHPO_TOP_CLOCK_CONTROL_BASE_IDX 3 +#define regHPO_TOP_HW_CONTROL 0x0e44 +#define regHPO_TOP_HW_CONTROL_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +// base address: 0x27958 +#define regDP_STREAM_MAPPER_CONTROL0 0x0e56 +#define regDP_STREAM_MAPPER_CONTROL0_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL1 0x0e57 +#define regDP_STREAM_MAPPER_CONTROL1_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL2 0x0e58 +#define regDP_STREAM_MAPPER_CONTROL2_BASE_IDX 3 +#define regDP_STREAM_MAPPER_CONTROL3 0x0e59 +#define regDP_STREAM_MAPPER_CONTROL3_BASE_IDX 3 + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +// base address: 0x1a698 +#define regDC_PERFMON23_PERFCOUNTER_CNTL 0x0e66 +#define regDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 3 +#define regDC_PERFMON23_PERFCOUNTER_CNTL2 0x0e67 +#define regDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 3 +#define regDC_PERFMON23_PERFCOUNTER_STATE 0x0e68 +#define regDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CNTL 0x0e69 +#define regDC_PERFMON23_PERFMON_CNTL_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CNTL2 0x0e6a +#define regDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x0e6b +#define regDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_CVALUE_LOW 0x0e6c +#define regDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_HI 0x0e6d +#define regDC_PERFMON23_PERFMON_HI_BASE_IDX 3 +#define regDC_PERFMON23_PERFMON_LOW 0x0e6e +#define regDC_PERFMON23_PERFMON_LOW_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm0_dispdec +// base address: 0x0 +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a +#define regABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_USER_LEVEL 0x0e7b +#define regABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c +#define regABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d +#define regABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e +#define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f +#define regABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM0_BL1_PWM_ABM_CNTL 0x0e80 +#define regABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81 +#define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_CNTL 0x0e82 +#define regABM0_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e83 +#define regABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_PWL_CNTL 0x0e84 +#define regABM0_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0e85 +#define regABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM0_DC_ABM1_ACE_CNTL_MISC 0x0e86 +#define regABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e88 +#define regABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_MISC_CTRL 0x0e89 +#define regABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e8a +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0e8b +#define regABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e8c +#define regABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e8d +#define regABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e8e +#define regABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e8f +#define regABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e90 +#define regABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e91 +#define regABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e92 +#define regABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e93 +#define regABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e94 +#define regABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0e95 +#define regABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e96 +#define regABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e97 +#define regABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e98 +#define regABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e99 +#define regABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0e9a +#define regABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0e9b +#define regABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0e9c +#define regABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0e9d +#define regABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_INDEX 0x0e9e +#define regABM0_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM0_DC_ABM1_HG_RESULT_DATA 0x0e9f +#define regABM0_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM0_DC_ABM1_BL_MASTER_LOCK 0x0ea0 +#define regABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm1_dispdec +// base address: 0x104 +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb +#define regABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_USER_LEVEL 0x0ebc +#define regABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd +#define regABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe +#define regABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf +#define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0 +#define regABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM1_BL1_PWM_ABM_CNTL 0x0ec1 +#define regABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2 +#define regABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_CNTL 0x0ec3 +#define regABM1_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec4 +#define regABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_PWL_CNTL 0x0ec5 +#define regABM1_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0ec6 +#define regABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM1_DC_ABM1_ACE_CNTL_MISC 0x0ec7 +#define regABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ec9 +#define regABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_MISC_CTRL 0x0eca +#define regABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ecb +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0ecc +#define regABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ecd +#define regABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ece +#define regABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ecf +#define regABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed0 +#define regABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed1 +#define regABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed2 +#define regABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed3 +#define regABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed4 +#define regABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0ed5 +#define regABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0ed6 +#define regABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0ed7 +#define regABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0ed8 +#define regABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0ed9 +#define regABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0eda +#define regABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0edb +#define regABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0edc +#define regABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0edd +#define regABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0ede +#define regABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_INDEX 0x0edf +#define regABM1_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM1_DC_ABM1_HG_RESULT_DATA 0x0ee0 +#define regABM1_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM1_DC_ABM1_BL_MASTER_LOCK 0x0ee1 +#define regABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm2_dispdec +// base address: 0x208 +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc +#define regABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_USER_LEVEL 0x0efd +#define regABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe +#define regABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff +#define regABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00 +#define regABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01 +#define regABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM2_BL1_PWM_ABM_CNTL 0x0f02 +#define regABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03 +#define regABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_CNTL 0x0f04 +#define regABM2_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f05 +#define regABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_PWL_CNTL 0x0f06 +#define regABM2_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f07 +#define regABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM2_DC_ABM1_ACE_CNTL_MISC 0x0f08 +#define regABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f0a +#define regABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_MISC_CTRL 0x0f0b +#define regABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f0c +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0f0d +#define regABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f0e +#define regABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f0f +#define regABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f10 +#define regABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f11 +#define regABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f12 +#define regABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f13 +#define regABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f14 +#define regABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f15 +#define regABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f16 +#define regABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f17 +#define regABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f18 +#define regABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f19 +#define regABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1a +#define regABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1b +#define regABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f1c +#define regABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f1d +#define regABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f1e +#define regABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f1f +#define regABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_INDEX 0x0f20 +#define regABM2_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM2_DC_ABM1_HG_RESULT_DATA 0x0f21 +#define regABM2_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM2_DC_ABM1_BL_MASTER_LOCK 0x0f22 +#define regABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dc_opp_abm3_dispdec +// base address: 0x30c +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d +#define regABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_USER_LEVEL 0x0f3e +#define regABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f +#define regABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40 +#define regABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41 +#define regABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42 +#define regABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3 +#define regABM3_BL1_PWM_ABM_CNTL 0x0f43 +#define regABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44 +#define regABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_CNTL 0x0f45 +#define regABM3_DC_ABM1_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f46 +#define regABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_PWL_CNTL 0x0f47 +#define regABM3_DC_ABM1_ACE_PWL_CNTL_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA 0x0f48 +#define regABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA_BASE_IDX 3 +#define regABM3_DC_ABM1_ACE_CNTL_MISC 0x0f49 +#define regABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3 +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f4b +#define regABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_MISC_CTRL 0x0f4c +#define regABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f4d +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB 0x0f4e +#define regABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f4f +#define regABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f50 +#define regABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f51 +#define regABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f52 +#define regABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f53 +#define regABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f54 +#define regABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f55 +#define regABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f56 +#define regABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f57 +#define regABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG 0x0f58 +#define regABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f59 +#define regABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5a +#define regABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5b +#define regABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f5c +#define regABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX 0x0f5d +#define regABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX 0x0f5e +#define regABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX 0x0f5f +#define regABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX 0x0f60 +#define regABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_INDEX 0x0f61 +#define regABM3_DC_ABM1_HG_RESULT_INDEX_BASE_IDX 3 +#define regABM3_DC_ABM1_HG_RESULT_DATA 0x0f62 +#define regABM3_DC_ABM1_HG_RESULT_DATA_BASE_IDX 3 +#define regABM3_DC_ABM1_BL_MASTER_LOCK 0x0f63 +#define regABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3 + + +// addressBlock: dce_dpia_dpia_mu0_dpiadec +// base address: 0x72000 +#define regDPIA_MU_CLOCK_CTRL 0x13800 +#define regDPIA_MU_CLOCK_CTRL_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0 0x13801 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT0_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT0 0x13802 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT0_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1 0x13803 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT1_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT1 0x13804 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT1_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2 0x13805 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT2_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT2 0x13806 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT2_BASE_IDX 3 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3 0x13807 +#define regDPIA_MU_CLOCK_CTRL_DPIA_PORT3_BASE_IDX 3 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT3 0x13808 +#define regDPIA_MU_RESET_CTRL_DPIA_PORT3_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT0 0x13811 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT0_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT1 0x13812 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT1_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT2 0x13813 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT2_BASE_IDX 3 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT3 0x13814 +#define regDPIA_MU_TPI_STATUS_DPIA_PORT3_BASE_IDX 3 +#define regDPIA_MU_TPI_MAX_CREDIT_COUNT 0x13819 +#define regDPIA_MU_TPI_MAX_CREDIT_COUNT_BASE_IDX 3 +#define regDPIA_MU_INTERRUPT_STATUS 0x1381a +#define regDPIA_MU_INTERRUPT_STATUS_BASE_IDX 3 +#define regDPIA_MU_INTERRUPT_CTRL 0x1381b +#define regDPIA_MU_INTERRUPT_CTRL_BASE_IDX 3 +#define regDPIA_MU_LOCAL_INTERRUPT_CTRL 0x1381c +#define regDPIA_MU_LOCAL_INTERRUPT_CTRL_BASE_IDX 3 +#define regDPIA_MU_LOCAL_INTERRUPT_ACK 0x1381d +#define regDPIA_MU_LOCAL_INTERRUPT_ACK_BASE_IDX 3 +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL 0x1381e +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL_BASE_IDX 3 +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2 0x1381f +#define regDPIA_MU_RBBMIF_TIMEOUT_CTRL2_BASE_IDX 3 +#define regDPIA_MU_RBBMIF_STATUS 0x13820 +#define regDPIA_MU_RBBMIF_STATUS_BASE_IDX 3 +#define regDPIA_MU_MICROSECOND_REF_CTRL 0x13821 +#define regDPIA_MU_MICROSECOND_REF_CTRL_BASE_IDX 3 +#define regDPIA_MU_PORT_ADP_STATUS 0x13822 +#define regDPIA_MU_PORT_ADP_STATUS_BASE_IDX 3 +#define regDPIA_GLUE_CTRL 0x13823 +#define regDPIA_GLUE_CTRL_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL0 0x13825 +#define regDPIA_PERF_COUNT_CONTROL0_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL1 0x13826 +#define regDPIA_PERF_COUNT_CONTROL1_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL2 0x13827 +#define regDPIA_PERF_COUNT_CONTROL2_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL3 0x13828 +#define regDPIA_PERF_COUNT_CONTROL3_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL4 0x13829 +#define regDPIA_PERF_COUNT_CONTROL4_BASE_IDX 3 +#define regDPIA_PERF_COUNT_CONTROL5 0x1382a +#define regDPIA_PERF_COUNT_CONTROL5_BASE_IDX 3 +#define regDPIA_PERF_COUNT_INDEX 0x1382b +#define regDPIA_PERF_COUNT_INDEX_BASE_IDX 3 +#define regDPIA_PERF_COUNT_DATA_LO 0x1382c +#define regDPIA_PERF_COUNT_DATA_LO_BASE_IDX 3 +#define regDPIA_MU_SPARE 0x1382d +#define regDPIA_MU_SPARE_BASE_IDX 3 + +// addressBlock: dce_dc_hda_azcontroller_azdec +// base address: 0x1300000 +#define regGLOBAL_CAPABILITIES 0x4b7000 +#define regGLOBAL_CAPABILITIES_BASE_IDX 3 +#define regMINOR_VERSION 0x4b7000 +#define regMINOR_VERSION_BASE_IDX 3 +#define regMAJOR_VERSION 0x4b7000 +#define regMAJOR_VERSION_BASE_IDX 3 +#define regOUTPUT_PAYLOAD_CAPABILITY 0x4b7001 +#define regOUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regINPUT_PAYLOAD_CAPABILITY 0x4b7001 +#define regINPUT_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regGLOBAL_CONTROL 0x4b7002 +#define regGLOBAL_CONTROL_BASE_IDX 3 +#define regWAKE_ENABLE 0x4b7003 +#define regWAKE_ENABLE_BASE_IDX 3 +#define regSTATE_CHANGE_STATUS 0x4b7003 +#define regSTATE_CHANGE_STATUS_BASE_IDX 3 +#define regGLOBAL_STATUS 0x4b7004 +#define regGLOBAL_STATUS_BASE_IDX 3 +#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 +#define regOUTPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regINPUT_STREAM_PAYLOAD_CAPABILITY 0x4b7006 +#define regINPUT_STREAM_PAYLOAD_CAPABILITY_BASE_IDX 3 +#define regINTERRUPT_CONTROL 0x4b7008 +#define regINTERRUPT_CONTROL_BASE_IDX 3 +#define regINTERRUPT_STATUS 0x4b7009 +#define regINTERRUPT_STATUS_BASE_IDX 3 +#define regWALL_CLOCK_COUNTER 0x4b700c +#define regWALL_CLOCK_COUNTER_BASE_IDX 3 +#define regSTREAM_SYNCHRONIZATION 0x4b700e +#define regSTREAM_SYNCHRONIZATION_BASE_IDX 3 +#define regCORB_LOWER_BASE_ADDRESS 0x4b7010 +#define regCORB_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regCORB_UPPER_BASE_ADDRESS 0x4b7011 +#define regCORB_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_WRITE_POINTER 0x4b7012 +#define regAZCONTROLLER1_CORB_WRITE_POINTER_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_READ_POINTER 0x4b7012 +#define regAZCONTROLLER1_CORB_READ_POINTER_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_CONTROL 0x4b7013 +#define regAZCONTROLLER1_CORB_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_STATUS 0x4b7013 +#define regAZCONTROLLER1_CORB_STATUS_BASE_IDX 3 +#define regAZCONTROLLER1_CORB_SIZE 0x4b7013 +#define regAZCONTROLLER1_CORB_SIZE_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS 0x4b7014 +#define regAZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS 0x4b7015 +#define regAZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_WRITE_POINTER 0x4b7016 +#define regAZCONTROLLER1_RIRB_WRITE_POINTER_BASE_IDX 3 +#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT 0x4b7016 +#define regAZCONTROLLER1_RESPONSE_INTERRUPT_COUNT_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_CONTROL 0x4b7017 +#define regAZCONTROLLER1_RIRB_CONTROL_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_STATUS 0x4b7017 +#define regAZCONTROLLER1_RIRB_STATUS_BASE_IDX 3 +#define regAZCONTROLLER1_RIRB_SIZE 0x4b7017 +#define regAZCONTROLLER1_RIRB_SIZE_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x4b7018 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE 0x4b7019 +#define regAZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 3 +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS 0x4b701a +#define regAZCONTROLLER1_IMMEDIATE_COMMAND_STATUS_BASE_IDX 3 +#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS 0x4b701c +#define regAZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS 0x4b701d +#define regAZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS 0x4b780c +#define regAZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azendpoint_azdec +// base address: 0x1300000 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +// base address: 0x1300000 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x4b7018 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x4b7018 +#define regAZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azroot_azdec +// base address: 0x1300000 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x4b7018 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 3 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x4b7018 +#define regAZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream0_azdec +// base address: 0x1300000 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7020 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7021 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7022 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7023 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7024 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7024 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7026 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7027 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7821 +#define regAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream1_azdec +// base address: 0x1300020 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7028 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7029 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b702a +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b702b +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b702c +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b702c +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b702e +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b702f +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7829 +#define regAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream2_azdec +// base address: 0x1300040 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7030 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7031 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7032 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7033 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7034 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7034 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7036 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7037 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7831 +#define regAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream3_azdec +// base address: 0x1300060 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7038 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7039 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b703a +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b703b +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b703c +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b703c +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b703e +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b703f +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7839 +#define regAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream4_azdec +// base address: 0x1300080 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7040 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7041 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7042 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7043 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7044 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7044 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7046 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7047 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7841 +#define regAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream5_azdec +// base address: 0x13000a0 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7048 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7049 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b704a +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b704b +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b704c +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b704c +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b704e +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b704f +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7849 +#define regAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream6_azdec +// base address: 0x13000c0 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7050 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7051 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b7052 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b7053 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b7054 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b7054 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b7056 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b7057 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7851 +#define regAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + + +// addressBlock: dce_dc_hda_azstream7_azdec +// base address: 0x13000e0 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x4b7058 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x4b7059 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x4b705a +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x4b705b +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x4b705c +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x4b705c +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x4b705e +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x4b705f +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 3 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x4b7859 +#define regAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 3 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h new file mode 100644 index 0000000000000..01fb530933698 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_2_0_sh_mask.h @@ -0,0 +1,67286 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dcn_4_2_0_SH_MASK_HEADER +#define _dcn_4_2_0_SH_MASK_HEADER + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//AZCONTROLLER0_CORB_WRITE_POINTER +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER0_CORB_READ_POINTER +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_CORB_CONTROL +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER0_CORB_STATUS +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER0_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER0_CORB_SIZE +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER0_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_RIRB_WRITE_POINTER +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER0_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER0_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER0_RIRB_CONTROL +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER0_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER0_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER0_RIRB_STATUS +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER0_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER0_RIRB_SIZE +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER0_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER0_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER0_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER0_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER0_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dc_perfmon_dc_perfmondebugind +//PERFMON_DEBUG_ID +#define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID__SHIFT 0x0 +#define PERFMON_DEBUG_ID__PERFMON_DEBUG_ID_MASK 0xFFFFFFFFL +//PERFMON_DEBUG01 +#define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG01__CLK0_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG02 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG02__CLK0_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG03 +#define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG03__CLK1_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG04 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG04__CLK1_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG05 +#define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG05__CLK2_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG06 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG06__CLK2_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG07 +#define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG07__CLK3_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG08 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG08__CLK3_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG09 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_START__SHIFT 0x0 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP__SHIFT 0x1 +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_START_MASK 0x00000001L +#define PERFMON_DEBUG09__PERFMON_EN_EVENT_STOP_MASK 0x00000002L +//PERFMON_DEBUG0A +#define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0A__CLK4_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0B +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0B__CLK4_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG0C +#define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0C__CLK5_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0D +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0D__CLK5_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG0E +#define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG0E__CLK6_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG0F +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG0F__CLK6_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG10 +#define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW__SHIFT 0x0 +#define PERFMON_DEBUG10__CLK7_PERFCOUNTER_LOW_MASK 0xFFFFFFFFL +//PERFMON_DEBUG11 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI__SHIFT 0x0 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT__SHIFT 0x10 +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_HI_MASK 0x0000FFFFL +#define PERFMON_DEBUG11__CLK7_PERFCOUNTER_EVENT_MASK 0x001F0000L +//PERFMON_DEBUG12 +#define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF__SHIFT 0x0 +#define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF__SHIFT 0x1 +#define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF__SHIFT 0x2 +#define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF__SHIFT 0x3 +#define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF__SHIFT 0x4 +#define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF__SHIFT 0x5 +#define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF__SHIFT 0x6 +#define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF__SHIFT 0x7 +#define PERFMON_DEBUG12__PERFCOUNTER_OFF__SHIFT 0x8 +#define PERFMON_DEBUG12__CLK0_PERFCOUNTER_OFF_MASK 0x00000001L +#define PERFMON_DEBUG12__CLK1_PERFCOUNTER_OFF_MASK 0x00000002L +#define PERFMON_DEBUG12__CLK2_PERFCOUNTER_OFF_MASK 0x00000004L +#define PERFMON_DEBUG12__CLK3_PERFCOUNTER_OFF_MASK 0x00000008L +#define PERFMON_DEBUG12__CLK4_PERFCOUNTER_OFF_MASK 0x00000010L +#define PERFMON_DEBUG12__CLK5_PERFCOUNTER_OFF_MASK 0x00000020L +#define PERFMON_DEBUG12__CLK6_PERFCOUNTER_OFF_MASK 0x00000040L +#define PERFMON_DEBUG12__CLK7_PERFCOUNTER_OFF_MASK 0x00000080L +#define PERFMON_DEBUG12__PERFCOUNTER_OFF_MASK 0x00000100L + + +// addressBlock: mcif_wb0_mcif_wbdebugind +//MCIF_WB_DEBUG_ID +#define MCIF_WB_DEBUG_ID__MCIF_WB_DEBUG_ID__SHIFT 0x0 +#define MCIF_WB_DEBUG_ID__MCIF_WB_DEBUG_ID_MASK 0xFFFFFFFFL +//ID01_WB_FMT_DBG +#define ID01_WB_FMT_DBG__ID01_WB_FMT_DBG__SHIFT 0x0 +#define ID01_WB_FMT_DBG__ID01_WB_FMT_DBG_MASK 0xFFFFFFFFL +//ID02_WB_FMT_DBG +#define ID02_WB_FMT_DBG__ID02_WB_FMT_DBG__SHIFT 0x0 +#define ID02_WB_FMT_DBG__ID02_WB_FMT_DBG_MASK 0xFFFFFFFFL +//ID03_WB_FMT_DBG +#define ID03_WB_FMT_DBG__ID03_WB_FMT_DBG__SHIFT 0x0 +#define ID03_WB_FMT_DBG__ID03_WB_FMT_DBG_MASK 0xFFFFFFFFL +//ID04_WB_MGR_DBG +#define ID04_WB_MGR_DBG__ID04_WB_MGR_DBG__SHIFT 0x0 +#define ID04_WB_MGR_DBG__ID04_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID05_WB_MGR_DBG +#define ID05_WB_MGR_DBG__ID05_WB_MGR_DBG__SHIFT 0x0 +#define ID05_WB_MGR_DBG__ID05_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID06_WB_MGR_DBG +#define ID06_WB_MGR_DBG__ID06_WB_MGR_DBG__SHIFT 0x0 +#define ID06_WB_MGR_DBG__ID06_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID07_WB_MGR_DBG +#define ID07_WB_MGR_DBG__ID07_WB_MGR_DBG__SHIFT 0x0 +#define ID07_WB_MGR_DBG__ID07_WB_MGR_DBG_MASK 0xFFFFFFFFL +//ID08_WB_ARB_DBG +#define ID08_WB_ARB_DBG__ID08_WB_ARB_DBG__SHIFT 0x0 +#define ID08_WB_ARB_DBG__ID08_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID09_WB_ARB_DBG +#define ID09_WB_ARB_DBG__ID09_WB_ARB_DBG__SHIFT 0x0 +#define ID09_WB_ARB_DBG__ID09_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0A_WB_ARB_DBG +#define ID0A_WB_ARB_DBG__ID0A_WB_ARB_DBG__SHIFT 0x0 +#define ID0A_WB_ARB_DBG__ID0A_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0B_WB_ARB_DBG +#define ID0B_WB_ARB_DBG__ID0B_WB_ARB_DBG__SHIFT 0x0 +#define ID0B_WB_ARB_DBG__ID0B_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0C_WB_ARB_DBG +#define ID0C_WB_ARB_DBG__ID0C_WB_ARB_DBG__SHIFT 0x0 +#define ID0C_WB_ARB_DBG__ID0C_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0D_WB_ARB_DBG +#define ID0D_WB_ARB_DBG__ID0D_WB_ARB_DBG__SHIFT 0x0 +#define ID0D_WB_ARB_DBG__ID0D_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0E_WB_ARB_DBG +#define ID0E_WB_ARB_DBG__ID0E_WB_ARB_DBG__SHIFT 0x0 +#define ID0E_WB_ARB_DBG__ID0E_WB_ARB_DBG_MASK 0xFFFFFFFFL +//ID0F_P010_WB_FMT_DBG_Y +#define ID0F_P010_WB_FMT_DBG_Y__ID0F_P010_WB_FMT_DBG_Y__SHIFT 0x0 +#define ID0F_P010_WB_FMT_DBG_Y__ID0F_P010_WB_FMT_DBG_Y_MASK 0xFFFFFFFFL +//ID10_P010_WB_FMT_DBG_C +#define ID10_P010_WB_FMT_DBG_C__ID10_P010_WB_FMT_DBG_C__SHIFT 0x0 +#define ID10_P010_WB_FMT_DBG_C__ID10_P010_WB_FMT_DBG_C_MASK 0xFFFFFFFFL +//ID11_WB_ARB_P010_DBG +#define ID11_WB_ARB_P010_DBG__ID11_WB_ARB_P010_DBG__SHIFT 0x0 +#define ID11_WB_ARB_P010_DBG__ID11_WB_ARB_P010_DBG_MASK 0xFFFFFFFFL +//ID12_WB_ARB_P010_DBG +#define ID12_WB_ARB_P010_DBG__ID12_WB_ARB_P010_DBG__SHIFT 0x0 +#define ID12_WB_ARB_P010_DBG__ID12_WB_ARB_P010_DBG_MASK 0xFFFFFFFFL + + +// addressBlock: hubbub_dchubbubdebugind +//DCHUBBUB_KEY_STATUS_DEBUG_1 +#define DCHUBBUB_KEY_STATUS_DEBUG_1__DCHUBBUB_KEY_STATUS_DEBUG_1__SHIFT 0x0 +#define DCHUBBUB_KEY_STATUS_DEBUG_1__DCHUBBUB_KEY_STATUS_DEBUG_1_MASK 0xFFFFFFFFL +//DCHUBBUB_KEY_STATUS_DEBUG_2 +#define DCHUBBUB_KEY_STATUS_DEBUG_2__DCHUBBUB_KEY_STATUS_DEBUG_2__SHIFT 0x0 +#define DCHUBBUB_KEY_STATUS_DEBUG_2__DCHUBBUB_KEY_STATUS_DEBUG_2_MASK 0xFFFFFFFFL + + +// addressBlock: odm0_odmdebugind +//ODM0_OPTC_INPUT_DEBUG_ID +#define ODM0_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM0_OPTC_INPUT_DEBUG0 +#define ODM0_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM0_OPTC_INPUT_DEBUG1 +#define ODM0_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM0_OPTC_INPUT_DEBUG2 +#define ODM0_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM0_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: odm1_odmdebugind +//ODM1_OPTC_INPUT_DEBUG_ID +#define ODM1_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM1_OPTC_INPUT_DEBUG0 +#define ODM1_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM1_OPTC_INPUT_DEBUG1 +#define ODM1_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM1_OPTC_INPUT_DEBUG2 +#define ODM1_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM1_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: odm2_odmdebugind +//ODM2_OPTC_INPUT_DEBUG_ID +#define ODM2_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM2_OPTC_INPUT_DEBUG0 +#define ODM2_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM2_OPTC_INPUT_DEBUG1 +#define ODM2_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM2_OPTC_INPUT_DEBUG2 +#define ODM2_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM2_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: odm3_odmdebugind +//ODM3_OPTC_INPUT_DEBUG_ID +#define ODM3_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG_ID__OPTC_INPUT_DEBUG_ID_MASK 0xFFFFFFFFL +//ODM3_OPTC_INPUT_DEBUG0 +#define ODM3_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG0__OPTC_INPUT_DEBUG0_MASK 0xFFFFFFFFL +//ODM3_OPTC_INPUT_DEBUG1 +#define ODM3_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG1__OPTC_INPUT_DEBUG1_MASK 0xFFFFFFFFL +//ODM3_OPTC_INPUT_DEBUG2 +#define ODM3_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2__SHIFT 0x0 +#define ODM3_OPTC_INPUT_DEBUG2__OPTC_INPUT_DEBUG2_MASK 0xFFFFFFFFL + + +// addressBlock: rbbmif_rbbmifdebugind +//RBBMIF_DEBUG_ID +#define RBBMIF_DEBUG_ID__RBBMIF_DEBUG_ID__SHIFT 0x0 +#define RBBMIF_DEBUG_ID__RBBMIF_DEBUG_ID_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_0 +#define RBBMIF_DEBUG_0__RBBMIF_DEBUG_0__SHIFT 0x0 +#define RBBMIF_DEBUG_0__RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_1 +#define RBBMIF_DEBUG_1__RBBMIF_DEBUG_1__SHIFT 0x0 +#define RBBMIF_DEBUG_1__RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_2 +#define RBBMIF_DEBUG_2__RBBMIF_DEBUG_2__SHIFT 0x0 +#define RBBMIF_DEBUG_2__RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_3 +#define RBBMIF_DEBUG_3__RBBMIF_DEBUG_3__SHIFT 0x0 +#define RBBMIF_DEBUG_3__RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_4 +#define RBBMIF_DEBUG_4__RBBMIF_DEBUG_4__SHIFT 0x0 +#define RBBMIF_DEBUG_4__RBBMIF_DEBUG_4_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_5 +#define RBBMIF_DEBUG_5__DBG_RBBMIF_DC_0__SHIFT 0x0 +#define RBBMIF_DEBUG_5__DBG_RBBMIF_DC_0_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_6 +#define RBBMIF_DEBUG_6__DBG_RBBMIF_DC_1__SHIFT 0x0 +#define RBBMIF_DEBUG_6__DBG_RBBMIF_DC_1_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_7 +#define RBBMIF_DEBUG_7__DBG_RBBMIF_DC_2__SHIFT 0x0 +#define RBBMIF_DEBUG_7__DBG_RBBMIF_DC_2_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_8 +#define RBBMIF_DEBUG_8__DBG_RBBMIF_DC_3__SHIFT 0x0 +#define RBBMIF_DEBUG_8__DBG_RBBMIF_DC_3_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_9 +#define RBBMIF_DEBUG_9__DBG_RBBMIF_DC_4__SHIFT 0x0 +#define RBBMIF_DEBUG_9__DBG_RBBMIF_DC_4_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_10 +#define RBBMIF_DEBUG_10__DBG_RBBMIF_DC_5__SHIFT 0x0 +#define RBBMIF_DEBUG_10__DBG_RBBMIF_DC_5_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_11 +#define RBBMIF_DEBUG_11__DBG_RBBMIF_DC_6__SHIFT 0x0 +#define RBBMIF_DEBUG_11__DBG_RBBMIF_DC_6_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_12 +#define RBBMIF_DEBUG_12__DBG_RBBMIF_DC_7__SHIFT 0x0 +#define RBBMIF_DEBUG_12__DBG_RBBMIF_DC_7_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_13 +#define RBBMIF_DEBUG_13__DBG_RBBMIF_DC_8__SHIFT 0x0 +#define RBBMIF_DEBUG_13__DBG_RBBMIF_DC_8_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_14 +#define RBBMIF_DEBUG_14__DBG_RBBMIF_DC_9__SHIFT 0x0 +#define RBBMIF_DEBUG_14__DBG_RBBMIF_DC_9_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_15 +#define RBBMIF_DEBUG_15__DBG_RBBMIF_DC_10__SHIFT 0x0 +#define RBBMIF_DEBUG_15__DBG_RBBMIF_DC_10_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_16 +#define RBBMIF_DEBUG_16__DBG_RBBMIF_DC_11__SHIFT 0x0 +#define RBBMIF_DEBUG_16__DBG_RBBMIF_DC_11_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_17 +#define RBBMIF_DEBUG_17__DBG_RBBMIF_DC_12__SHIFT 0x0 +#define RBBMIF_DEBUG_17__DBG_RBBMIF_DC_12_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_18 +#define RBBMIF_DEBUG_18__DBG_RBBMIF_DC_13__SHIFT 0x0 +#define RBBMIF_DEBUG_18__DBG_RBBMIF_DC_13_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_19 +#define RBBMIF_DEBUG_19__DBG_RBBMIF_DC_14__SHIFT 0x0 +#define RBBMIF_DEBUG_19__DBG_RBBMIF_DC_14_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_20 +#define RBBMIF_DEBUG_20__DBG_RBBMIF_DC_15__SHIFT 0x0 +#define RBBMIF_DEBUG_20__DBG_RBBMIF_DC_15_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_21 +#define RBBMIF_DEBUG_21__DBG_RBBMIF_DC_16__SHIFT 0x0 +#define RBBMIF_DEBUG_21__DBG_RBBMIF_DC_16_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_22 +#define RBBMIF_DEBUG_22__DBG_RBBMIF_DC_17__SHIFT 0x0 +#define RBBMIF_DEBUG_22__DBG_RBBMIF_DC_17_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_23 +#define RBBMIF_DEBUG_23__DBG_RBBMIF_DC_18__SHIFT 0x0 +#define RBBMIF_DEBUG_23__DBG_RBBMIF_DC_18_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_24 +#define RBBMIF_DEBUG_24__DBG_RBBMIF_DC_19__SHIFT 0x0 +#define RBBMIF_DEBUG_24__DBG_RBBMIF_DC_19_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_25 +#define RBBMIF_DEBUG_25__DBG_RBBMIF_DC_20__SHIFT 0x0 +#define RBBMIF_DEBUG_25__DBG_RBBMIF_DC_20_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_26 +#define RBBMIF_DEBUG_26__DBG_RBBMIF_DC_21__SHIFT 0x0 +#define RBBMIF_DEBUG_26__DBG_RBBMIF_DC_21_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_27 +#define RBBMIF_DEBUG_27__DBG_RBBMIF_DC_22__SHIFT 0x0 +#define RBBMIF_DEBUG_27__DBG_RBBMIF_DC_22_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_28 +#define RBBMIF_DEBUG_28__DBG_RBBMIF_DC_23__SHIFT 0x0 +#define RBBMIF_DEBUG_28__DBG_RBBMIF_DC_23_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_29 +#define RBBMIF_DEBUG_29__DBG_RBBMIF_DC_24__SHIFT 0x0 +#define RBBMIF_DEBUG_29__DBG_RBBMIF_DC_24_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_30 +#define RBBMIF_DEBUG_30__DBG_RBBMIF_DC_25__SHIFT 0x0 +#define RBBMIF_DEBUG_30__DBG_RBBMIF_DC_25_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_31 +#define RBBMIF_DEBUG_31__DBG_RBBMIF_DC_26__SHIFT 0x0 +#define RBBMIF_DEBUG_31__DBG_RBBMIF_DC_26_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_32 +#define RBBMIF_DEBUG_32__DBG_RBBMIF_DC_27__SHIFT 0x0 +#define RBBMIF_DEBUG_32__DBG_RBBMIF_DC_27_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_33 +#define RBBMIF_DEBUG_33__DBG_RBBMIF_DC_28__SHIFT 0x0 +#define RBBMIF_DEBUG_33__DBG_RBBMIF_DC_28_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_34 +#define RBBMIF_DEBUG_34__DBG_RBBMIF_DC_29__SHIFT 0x0 +#define RBBMIF_DEBUG_34__DBG_RBBMIF_DC_29_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_35 +#define RBBMIF_DEBUG_35__DBG_RBBMIF_DC_30__SHIFT 0x0 +#define RBBMIF_DEBUG_35__DBG_RBBMIF_DC_30_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_36 +#define RBBMIF_DEBUG_36__DBG_RBBMIF_DC_31__SHIFT 0x0 +#define RBBMIF_DEBUG_36__DBG_RBBMIF_DC_31_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_37 +#define RBBMIF_DEBUG_37__DBG_RBBMIF_DC_32__SHIFT 0x0 +#define RBBMIF_DEBUG_37__DBG_RBBMIF_DC_32_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_38 +#define RBBMIF_DEBUG_38__DBG_RBBMIF_DC_33__SHIFT 0x0 +#define RBBMIF_DEBUG_38__DBG_RBBMIF_DC_33_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_39 +#define RBBMIF_DEBUG_39__DBG_RBBMIF_DC_34__SHIFT 0x0 +#define RBBMIF_DEBUG_39__DBG_RBBMIF_DC_34_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_40 +#define RBBMIF_DEBUG_40__DBG_RBBMIF_DC_35__SHIFT 0x0 +#define RBBMIF_DEBUG_40__DBG_RBBMIF_DC_35_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_41 +#define RBBMIF_DEBUG_41__DBG_RBBMIF_DC_36__SHIFT 0x0 +#define RBBMIF_DEBUG_41__DBG_RBBMIF_DC_36_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_42 +#define RBBMIF_DEBUG_42__DBG_RBBMIF_DC_37__SHIFT 0x0 +#define RBBMIF_DEBUG_42__DBG_RBBMIF_DC_37_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_43 +#define RBBMIF_DEBUG_43__DBG_RBBMIF_DC_38__SHIFT 0x0 +#define RBBMIF_DEBUG_43__DBG_RBBMIF_DC_38_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_44 +#define RBBMIF_DEBUG_44__DBG_RBBMIF_DC_39__SHIFT 0x0 +#define RBBMIF_DEBUG_44__DBG_RBBMIF_DC_39_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_45 +#define RBBMIF_DEBUG_45__DBG_RBBMIF_DC_40__SHIFT 0x0 +#define RBBMIF_DEBUG_45__DBG_RBBMIF_DC_40_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_46 +#define RBBMIF_DEBUG_46__DBG_RBBMIF_DC_41__SHIFT 0x0 +#define RBBMIF_DEBUG_46__DBG_RBBMIF_DC_41_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_47 +#define RBBMIF_DEBUG_47__DBG_RBBMIF_DC_42__SHIFT 0x0 +#define RBBMIF_DEBUG_47__DBG_RBBMIF_DC_42_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_48 +#define RBBMIF_DEBUG_48__DBG_RBBMIF_DC_43__SHIFT 0x0 +#define RBBMIF_DEBUG_48__DBG_RBBMIF_DC_43_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_49 +#define RBBMIF_DEBUG_49__DBG_RBBMIF_DC_44__SHIFT 0x0 +#define RBBMIF_DEBUG_49__DBG_RBBMIF_DC_44_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_50 +#define RBBMIF_DEBUG_50__DBG_RBBMIF_DC_45__SHIFT 0x0 +#define RBBMIF_DEBUG_50__DBG_RBBMIF_DC_45_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_51 +#define RBBMIF_DEBUG_51__DBG_RBBMIF_DC_46__SHIFT 0x0 +#define RBBMIF_DEBUG_51__DBG_RBBMIF_DC_46_MASK 0xFFFFFFFFL +//RBBMIF_DEBUG_52 +#define RBBMIF_DEBUG_52__DBG_RBBMIF_DC_47__SHIFT 0x0 +#define RBBMIF_DEBUG_52__DBG_RBBMIF_DC_47_MASK 0xFFFFFFFFL + + +// addressBlock: ihc_ihcdebugind +//IHC_DEBUG_ID +#define IHC_DEBUG_ID__IHC_DEBUG_ID__SHIFT 0x0 +#define IHC_DEBUG_ID__IHC_DEBUG_ID_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_A +#define IHC_CLIENT_DEBUG_A__IHC_TEST_DEBUG_A__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_A__IHC_TEST_DEBUG_A_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_B +#define IHC_CLIENT_DEBUG_B__IHC_TEST_DEBUG_B__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_B__IHC_TEST_DEBUG_B_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_C +#define IHC_CLIENT_DEBUG_C__IHC_TEST_DEBUG_C__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_C__IHC_TEST_DEBUG_C_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_D +#define IHC_CLIENT_DEBUG_D__IHC_TEST_DEBUG_D__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_D__IHC_TEST_DEBUG_D_MASK 0xFFFFFFFFL +//IHC_CLIENT_DEBUG_E +#define IHC_CLIENT_DEBUG_E__IHC_TEST_DEBUG_E__SHIFT 0x0 +#define IHC_CLIENT_DEBUG_E__IHC_TEST_DEBUG_E_MASK 0xFFFFFFFFL + + +// addressBlock: dmu_misc_dmumiscdebugind +//DMU_MISC_DEBUG_ID +#define DMU_MISC_DEBUG_ID__DMU_MISC_DEBUG_ID__SHIFT 0x0 +#define DMU_MISC_DEBUG_ID__DMU_MISC_DEBUG_ID_MASK 0xFFFFFFFFL +//DMU_MISC_DEBUG_1 +#define DMU_MISC_DEBUG_1__DMU_MISC_DEBUG_1__SHIFT 0x0 +#define DMU_MISC_DEBUG_1__DMU_MISC_DEBUG_1_MASK 0xFFFFFFFFL +//DMU_ZSC_TEST_DEBUG1_DATA +#define DMU_ZSC_TEST_DEBUG1_DATA__DMU_ZSC_TEST_DEBUG1_DATA__SHIFT 0x0 +#define DMU_ZSC_TEST_DEBUG1_DATA__DMU_ZSC_TEST_DEBUG1_DATA_MASK 0xFFFFFFFFL +//DMU_ZSC_TEST_DEBUG2_DATA +#define DMU_ZSC_TEST_DEBUG2_DATA__DMU_ZSC_TEST_DEBUG2_DATA__SHIFT 0x0 +#define DMU_ZSC_TEST_DEBUG2_DATA__DMU_ZSC_TEST_DEBUG2_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dc_pg_dc_pgdebugind +//DCPG_DEBUG_ID +#define DCPG_DEBUG_ID__DCPG_DEBUG_ID__SHIFT 0x0 +#define DCPG_DEBUG_ID__DCPG_DEBUG_ID_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS0 +#define DCPG_CONTROL_DEBUG_BUS0__DCPG_CONTROL_DEBUG_BUS0__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS0__DCPG_CONTROL_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS1 +#define DCPG_CONTROL_DEBUG_BUS1__DCPG_CONTROL_DEBUG_BUS1__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS1__DCPG_CONTROL_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS2 +#define DCPG_CONTROL_DEBUG_BUS2__DCPG_CONTROL_DEBUG_BUS2__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS2__DCPG_CONTROL_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS3 +#define DCPG_CONTROL_DEBUG_BUS3__DCPG_CONTROL_DEBUG_BUS3__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS3__DCPG_CONTROL_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS16 +#define DCPG_CONTROL_DEBUG_BUS16__DCPG_CONTROL_DEBUG_BUS16__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS16__DCPG_CONTROL_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS17 +#define DCPG_CONTROL_DEBUG_BUS17__DCPG_CONTROL_DEBUG_BUS17__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS17__DCPG_CONTROL_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS18 +#define DCPG_CONTROL_DEBUG_BUS18__DCPG_CONTROL_DEBUG_BUS18__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS18__DCPG_CONTROL_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS19 +#define DCPG_CONTROL_DEBUG_BUS19__DCPG_CONTROL_DEBUG_BUS19__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS19__DCPG_CONTROL_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS22 +#define DCPG_CONTROL_DEBUG_BUS22__DCPG_CONTROL_DEBUG_BUS22__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS22__DCPG_CONTROL_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS23 +#define DCPG_CONTROL_DEBUG_BUS23__DCPG_CONTROL_DEBUG_BUS23__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS23__DCPG_CONTROL_DEBUG_BUS23_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS24 +#define DCPG_CONTROL_DEBUG_BUS24__DCPG_CONTROL_DEBUG_BUS24__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS24__DCPG_CONTROL_DEBUG_BUS24_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS25 +#define DCPG_CONTROL_DEBUG_BUS25__DCPG_CONTROL_DEBUG_BUS25__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS25__DCPG_CONTROL_DEBUG_BUS25_MASK 0xFFFFFFFFL +//DCPG_CONTROL_DEBUG_BUS26 +#define DCPG_CONTROL_DEBUG_BUS26__DCPG_CONTROL_DEBUG_BUS26__SHIFT 0x0 +#define DCPG_CONTROL_DEBUG_BUS26__DCPG_CONTROL_DEBUG_BUS26_MASK 0xFFFFFFFFL + + +// addressBlock: dp0_dpdebugind +//DP0_DP_DEBUG_ID +#define DP0_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP0_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_K +#define DP0_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP0_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_L +#define DP0_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP0_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_M +#define DP0_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP0_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_G +#define DP0_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP0_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_O +#define DP0_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP0_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_P +#define DP0_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP0_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_Q +#define DP0_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP0_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_R +#define DP0_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP0_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_S +#define DP0_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP0_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp0_dpfedebugind +//DP0_DP_FE_DEBUG_ID +#define DP0_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP0_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP0_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP0_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_T +#define DP0_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP0_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_U +#define DP0_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP0_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_V +#define DP0_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP0_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_W +#define DP0_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP0_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_X +#define DP0_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP0_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_Y +#define DP0_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP0_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_Z +#define DP0_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP0_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_1A +#define DP0_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP0_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_1B +#define DP0_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP0_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_I +#define DP0_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP0_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_J +#define DP0_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP0_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_N +#define DP0_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP0_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_H +#define DP0_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP0_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_A +#define DP0_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP0_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_B +#define DP0_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP0_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_C +#define DP0_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP0_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_D +#define DP0_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP0_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_E +#define DP0_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP0_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP0_DP_DEBUG_F +#define DP0_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP0_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp0_dpfe_dprefclk_debugind +//DP0_DP_FE_DPREFCLK_DEBUG_ID +#define DP0_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP0_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP0_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig0_digdebugind +//DIG0_DIG_BE_CLKGEN_DEBUG0 +#define DIG0_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG0_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig0_digfedebugind +//DIG0_DIG_FE_DEBUG_ID +#define DIG0_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG0_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG0 +#define DIG0_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG1 +#define DIG0_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG2 +#define DIG0_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG0_DIG_VPG_DEBUG3 +#define DIG0_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG0_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp1_dpdebugind +//DP1_DP_DEBUG_ID +#define DP1_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP1_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_K +#define DP1_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP1_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_L +#define DP1_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP1_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_M +#define DP1_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP1_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_G +#define DP1_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP1_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_O +#define DP1_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP1_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_P +#define DP1_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP1_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_Q +#define DP1_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP1_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_R +#define DP1_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP1_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_S +#define DP1_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP1_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp1_dpfedebugind +//DP1_DP_FE_DEBUG_ID +#define DP1_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP1_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP1_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP1_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_T +#define DP1_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP1_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_U +#define DP1_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP1_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_V +#define DP1_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP1_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_W +#define DP1_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP1_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_X +#define DP1_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP1_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_Y +#define DP1_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP1_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_Z +#define DP1_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP1_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_1A +#define DP1_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP1_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_1B +#define DP1_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP1_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_I +#define DP1_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP1_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_J +#define DP1_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP1_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_N +#define DP1_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP1_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_H +#define DP1_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP1_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_A +#define DP1_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP1_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_B +#define DP1_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP1_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_C +#define DP1_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP1_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_D +#define DP1_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP1_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_E +#define DP1_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP1_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP1_DP_DEBUG_F +#define DP1_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP1_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp1_dpfe_dprefclk_debugind +//DP1_DP_FE_DPREFCLK_DEBUG_ID +#define DP1_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP1_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP1_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig1_digdebugind +//DIG1_DIG_BE_CLKGEN_DEBUG0 +#define DIG1_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG1_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig1_digfedebugind +//DIG1_DIG_FE_DEBUG_ID +#define DIG1_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG1_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG0 +#define DIG1_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG1 +#define DIG1_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG2 +#define DIG1_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG1_DIG_VPG_DEBUG3 +#define DIG1_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG1_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp2_dpdebugind +//DP2_DP_DEBUG_ID +#define DP2_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP2_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_K +#define DP2_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP2_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_L +#define DP2_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP2_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_M +#define DP2_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP2_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_G +#define DP2_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP2_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_O +#define DP2_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP2_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_P +#define DP2_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP2_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_Q +#define DP2_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP2_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_R +#define DP2_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP2_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_S +#define DP2_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP2_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp2_dpfedebugind +//DP2_DP_FE_DEBUG_ID +#define DP2_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP2_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP2_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP2_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_T +#define DP2_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP2_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_U +#define DP2_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP2_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_V +#define DP2_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP2_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_W +#define DP2_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP2_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_X +#define DP2_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP2_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_Y +#define DP2_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP2_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_Z +#define DP2_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP2_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_1A +#define DP2_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP2_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_1B +#define DP2_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP2_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_I +#define DP2_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP2_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_J +#define DP2_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP2_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_N +#define DP2_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP2_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_H +#define DP2_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP2_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_A +#define DP2_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP2_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_B +#define DP2_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP2_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_C +#define DP2_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP2_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_D +#define DP2_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP2_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_E +#define DP2_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP2_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP2_DP_DEBUG_F +#define DP2_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP2_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp2_dpfe_dprefclk_debugind +//DP2_DP_FE_DPREFCLK_DEBUG_ID +#define DP2_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP2_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP2_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig2_digdebugind +//DIG2_DIG_BE_CLKGEN_DEBUG0 +#define DIG2_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG2_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig2_digfedebugind +//DIG2_DIG_FE_DEBUG_ID +#define DIG2_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG2_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG0 +#define DIG2_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG1 +#define DIG2_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG2 +#define DIG2_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG2_DIG_VPG_DEBUG3 +#define DIG2_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG2_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp3_dpdebugind +//DP3_DP_DEBUG_ID +#define DP3_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP3_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_K +#define DP3_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP3_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_L +#define DP3_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP3_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_M +#define DP3_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP3_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_G +#define DP3_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP3_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_O +#define DP3_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP3_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_P +#define DP3_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP3_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_Q +#define DP3_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP3_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_R +#define DP3_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP3_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_S +#define DP3_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP3_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp3_dpfedebugind +//DP3_DP_FE_DEBUG_ID +#define DP3_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP3_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP3_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP3_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_T +#define DP3_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP3_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_U +#define DP3_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP3_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_V +#define DP3_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP3_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_W +#define DP3_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP3_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_X +#define DP3_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP3_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_Y +#define DP3_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP3_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_Z +#define DP3_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP3_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_1A +#define DP3_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP3_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_1B +#define DP3_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP3_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_I +#define DP3_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP3_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_J +#define DP3_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP3_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_N +#define DP3_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP3_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_H +#define DP3_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP3_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_A +#define DP3_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP3_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_B +#define DP3_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP3_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_C +#define DP3_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP3_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_D +#define DP3_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP3_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_E +#define DP3_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP3_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP3_DP_DEBUG_F +#define DP3_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP3_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp3_dpfe_dprefclk_debugind +//DP3_DP_FE_DPREFCLK_DEBUG_ID +#define DP3_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP3_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP3_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig3_digdebugind +//DIG3_DIG_BE_CLKGEN_DEBUG0 +#define DIG3_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG3_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig3_digfedebugind +//DIG3_DIG_FE_DEBUG_ID +#define DIG3_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG3_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG0 +#define DIG3_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG1 +#define DIG3_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG2 +#define DIG3_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG3_DIG_VPG_DEBUG3 +#define DIG3_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG3_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dp4_dpdebugind +//DP4_DP_DEBUG_ID +#define DP4_DP_DEBUG_ID__DP_DEBUG_ID__SHIFT 0x0 +#define DP4_DP_DEBUG_ID__DP_DEBUG_ID_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_K +#define DP4_DP_DEBUG_K__DP_DEBUG_K__SHIFT 0x0 +#define DP4_DP_DEBUG_K__DP_DEBUG_K_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_L +#define DP4_DP_DEBUG_L__DP_DEBUG_L__SHIFT 0x0 +#define DP4_DP_DEBUG_L__DP_DEBUG_L_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_M +#define DP4_DP_DEBUG_M__DP_DEBUG_M__SHIFT 0x0 +#define DP4_DP_DEBUG_M__DP_DEBUG_M_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_G +#define DP4_DP_DEBUG_G__DP_DEBUG_G__SHIFT 0x0 +#define DP4_DP_DEBUG_G__DP_DEBUG_G_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_O +#define DP4_DP_DEBUG_O__DP_DEBUG_O__SHIFT 0x0 +#define DP4_DP_DEBUG_O__DP_DEBUG_O_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_P +#define DP4_DP_DEBUG_P__DP_DEBUG_P__SHIFT 0x0 +#define DP4_DP_DEBUG_P__DP_DEBUG_P_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_Q +#define DP4_DP_DEBUG_Q__DP_DEBUG_Q__SHIFT 0x0 +#define DP4_DP_DEBUG_Q__DP_DEBUG_Q_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_R +#define DP4_DP_DEBUG_R__DP_DEBUG_R__SHIFT 0x0 +#define DP4_DP_DEBUG_R__DP_DEBUG_R_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_S +#define DP4_DP_DEBUG_S__DP_DEBUG_S__SHIFT 0x0 +#define DP4_DP_DEBUG_S__DP_DEBUG_S_MASK 0xFFFFFFFFL + + +// addressBlock: dp4_dpfedebugind +//DP4_DP_FE_DEBUG_ID +#define DP4_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID__SHIFT 0x0 +#define DP4_DP_FE_DEBUG_ID__DP_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_0__DP_FE_SYMCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_1 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_1__DP_FE_SYMCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_2 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_2__DP_FE_SYMCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_3 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_3__DP_FE_SYMCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP4_DP_FE_SYMCLK_DEBUG_DATA_4 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP4_DP_FE_SYMCLK_DEBUG_DATA_4__DP_FE_SYMCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_T +#define DP4_DP_DEBUG_T__DP_DEBUG_T__SHIFT 0x0 +#define DP4_DP_DEBUG_T__DP_DEBUG_T_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_U +#define DP4_DP_DEBUG_U__DP_DEBUG_U__SHIFT 0x0 +#define DP4_DP_DEBUG_U__DP_DEBUG_U_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_V +#define DP4_DP_DEBUG_V__DP_DEBUG_V__SHIFT 0x0 +#define DP4_DP_DEBUG_V__DP_DEBUG_V_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_W +#define DP4_DP_DEBUG_W__DP_DEBUG_W__SHIFT 0x0 +#define DP4_DP_DEBUG_W__DP_DEBUG_W_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_X +#define DP4_DP_DEBUG_X__DP_DEBUG_X__SHIFT 0x0 +#define DP4_DP_DEBUG_X__DP_DEBUG_X_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_Y +#define DP4_DP_DEBUG_Y__DP_DEBUG_Y__SHIFT 0x0 +#define DP4_DP_DEBUG_Y__DP_DEBUG_Y_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_Z +#define DP4_DP_DEBUG_Z__DP_DEBUG_Z__SHIFT 0x0 +#define DP4_DP_DEBUG_Z__DP_DEBUG_Z_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_1A +#define DP4_DP_DEBUG_1A__DP_DEBUG_1A__SHIFT 0x0 +#define DP4_DP_DEBUG_1A__DP_DEBUG_1A_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_1B +#define DP4_DP_DEBUG_1B__DP_DEBUG_1B__SHIFT 0x0 +#define DP4_DP_DEBUG_1B__DP_DEBUG_1B_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_I +#define DP4_DP_DEBUG_I__DP_DEBUG_I__SHIFT 0x0 +#define DP4_DP_DEBUG_I__DP_DEBUG_I_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_J +#define DP4_DP_DEBUG_J__DP_DEBUG_J__SHIFT 0x0 +#define DP4_DP_DEBUG_J__DP_DEBUG_J_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_N +#define DP4_DP_DEBUG_N__DP_DEBUG_N__SHIFT 0x0 +#define DP4_DP_DEBUG_N__DP_DEBUG_N_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_H +#define DP4_DP_DEBUG_H__DP_DEBUG_H__SHIFT 0x0 +#define DP4_DP_DEBUG_H__DP_DEBUG_H_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_A +#define DP4_DP_DEBUG_A__DP_DEBUG_A__SHIFT 0x0 +#define DP4_DP_DEBUG_A__DP_DEBUG_A_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_B +#define DP4_DP_DEBUG_B__DP_DEBUG_B__SHIFT 0x0 +#define DP4_DP_DEBUG_B__DP_DEBUG_B_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_C +#define DP4_DP_DEBUG_C__DP_DEBUG_C__SHIFT 0x0 +#define DP4_DP_DEBUG_C__DP_DEBUG_C_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_D +#define DP4_DP_DEBUG_D__DP_DEBUG_D__SHIFT 0x0 +#define DP4_DP_DEBUG_D__DP_DEBUG_D_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_E +#define DP4_DP_DEBUG_E__DP_DEBUG_E__SHIFT 0x0 +#define DP4_DP_DEBUG_E__DP_DEBUG_E_MASK 0xFFFFFFFFL +//DP4_DP_DEBUG_F +#define DP4_DP_DEBUG_F__DP_DEBUG_F__SHIFT 0x0 +#define DP4_DP_DEBUG_F__DP_DEBUG_F_MASK 0xFFFFFFFFL + + +// addressBlock: dp4_dpfe_dprefclk_debugind +//DP4_DP_FE_DPREFCLK_DEBUG_ID +#define DP4_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_ID__DP_FE_DPREFCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_0__DP_FE_DPREFCLK_DEBUG_DATA_0_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_1 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_1__DP_FE_DPREFCLK_DEBUG_DATA_1_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_2 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_2__DP_FE_DPREFCLK_DEBUG_DATA_2_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_3 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_3__DP_FE_DPREFCLK_DEBUG_DATA_3_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_4 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_4__DP_FE_DPREFCLK_DEBUG_DATA_4_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_5 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_5__DP_FE_DPREFCLK_DEBUG_DATA_5_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_6 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_6__DP_FE_DPREFCLK_DEBUG_DATA_6_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_7 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_7__DP_FE_DPREFCLK_DEBUG_DATA_7_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_8 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_8__DP_FE_DPREFCLK_DEBUG_DATA_8_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_9 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_9__DP_FE_DPREFCLK_DEBUG_DATA_9_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_10 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_10__DP_FE_DPREFCLK_DEBUG_DATA_10_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_11 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_11__DP_FE_DPREFCLK_DEBUG_DATA_11_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_12 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_12__DP_FE_DPREFCLK_DEBUG_DATA_12_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_13 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_13__DP_FE_DPREFCLK_DEBUG_DATA_13_MASK 0xFFFFFFFFL +//DP4_DP_FE_DPREFCLK_DEBUG_DATA_14 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14__SHIFT 0x0 +#define DP4_DP_FE_DPREFCLK_DEBUG_DATA_14__DP_FE_DPREFCLK_DEBUG_DATA_14_MASK 0xFFFFFFFFL + + +// addressBlock: dig4_digdebugind +//DIG4_DIG_BE_CLKGEN_DEBUG0 +#define DIG4_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0__SHIFT 0x0 +#define DIG4_DIG_BE_CLKGEN_DEBUG0__DIG_BE_CLKGEN_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: dig4_digfedebugind +//DIG4_DIG_FE_DEBUG_ID +#define DIG4_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID__SHIFT 0x0 +#define DIG4_DIG_FE_DEBUG_ID__DIG_FE_DEBUG_ID_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG0 +#define DIG4_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG0__DIG_VPG_DEBUG0_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG1 +#define DIG4_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG1__DIG_VPG_DEBUG1_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG2 +#define DIG4_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG2__DIG_VPG_DEBUG2_MASK 0xFFFFFFFFL +//DIG4_DIG_VPG_DEBUG3 +#define DIG4_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3__SHIFT 0x0 +#define DIG4_DIG_VPG_DEBUG3__DIG_VPG_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dio_misc_dio_miscdebugind +//I2C_DEBUG_BUS +#define I2C_DEBUG_BUS__I2C_DEBUG_BUS__SHIFT 0x12 +#define I2C_DEBUG_BUS__I2C_DEBUG_BUS_MASK 0xFFFC0000L +//DIO_RBBMIF_DEBUG_0 +#define DIO_RBBMIF_DEBUG_0__DIO_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_0__DIO_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIO_RBBMIF_DEBUG_1 +#define DIO_RBBMIF_DEBUG_1__DIO_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_1__DIO_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIO_RBBMIF_DEBUG_2 +#define DIO_RBBMIF_DEBUG_2__DIO_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_2__DIO_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIO_RBBMIF_DEBUG_3 +#define DIO_RBBMIF_DEBUG_3__DIO_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIO_RBBMIF_DEBUG_3__DIO_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_0 +#define DIGA_RBBMIF_DEBUG_0__DIGA_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_0__DIGA_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_1 +#define DIGA_RBBMIF_DEBUG_1__DIGA_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_1__DIGA_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_2 +#define DIGA_RBBMIF_DEBUG_2__DIGA_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_2__DIGA_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGA_RBBMIF_DEBUG_3 +#define DIGA_RBBMIF_DEBUG_3__DIGA_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGA_RBBMIF_DEBUG_3__DIGA_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_0 +#define DIGB_RBBMIF_DEBUG_0__DIGB_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_0__DIGB_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_1 +#define DIGB_RBBMIF_DEBUG_1__DIGB_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_1__DIGB_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_2 +#define DIGB_RBBMIF_DEBUG_2__DIGB_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_2__DIGB_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGB_RBBMIF_DEBUG_3 +#define DIGB_RBBMIF_DEBUG_3__DIGB_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGB_RBBMIF_DEBUG_3__DIGB_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_0 +#define DIGC_RBBMIF_DEBUG_0__DIGC_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_0__DIGC_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_1 +#define DIGC_RBBMIF_DEBUG_1__DIGC_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_1__DIGC_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_2 +#define DIGC_RBBMIF_DEBUG_2__DIGC_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_2__DIGC_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGC_RBBMIF_DEBUG_3 +#define DIGC_RBBMIF_DEBUG_3__DIGC_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGC_RBBMIF_DEBUG_3__DIGC_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_0 +#define DIGD_RBBMIF_DEBUG_0__DIGD_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_0__DIGD_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_1 +#define DIGD_RBBMIF_DEBUG_1__DIGD_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_1__DIGD_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_2 +#define DIGD_RBBMIF_DEBUG_2__DIGD_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_2__DIGD_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGD_RBBMIF_DEBUG_3 +#define DIGD_RBBMIF_DEBUG_3__DIGD_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGD_RBBMIF_DEBUG_3__DIGD_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_0 +#define DIGE_RBBMIF_DEBUG_0__DIGE_RBBMIF_DEBUG_0__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_0__DIGE_RBBMIF_DEBUG_0_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_1 +#define DIGE_RBBMIF_DEBUG_1__DIGE_RBBMIF_DEBUG_1__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_1__DIGE_RBBMIF_DEBUG_1_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_2 +#define DIGE_RBBMIF_DEBUG_2__DIGE_RBBMIF_DEBUG_2__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_2__DIGE_RBBMIF_DEBUG_2_MASK 0xFFFFFFFFL +//DIGE_RBBMIF_DEBUG_3 +#define DIGE_RBBMIF_DEBUG_3__DIGE_RBBMIF_DEBUG_3__SHIFT 0x0 +#define DIGE_RBBMIF_DEBUG_3__DIGE_RBBMIF_DEBUG_3_MASK 0xFFFFFFFFL +//DIGA_DME_DEBUG +#define DIGA_DME_DEBUG__DIGA_DME_DEBUG__SHIFT 0x0 +#define DIGA_DME_DEBUG__DIGA_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGB_DME_DEBUG +#define DIGB_DME_DEBUG__DIGB_DME_DEBUG__SHIFT 0x0 +#define DIGB_DME_DEBUG__DIGB_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGC_DME_DEBUG +#define DIGC_DME_DEBUG__DIGC_DME_DEBUG__SHIFT 0x0 +#define DIGC_DME_DEBUG__DIGC_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGD_DME_DEBUG +#define DIGD_DME_DEBUG__DIGD_DME_DEBUG__SHIFT 0x0 +#define DIGD_DME_DEBUG__DIGD_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGE_DME_DEBUG +#define DIGE_DME_DEBUG__DIGE_DME_DEBUG__SHIFT 0x0 +#define DIGE_DME_DEBUG__DIGE_DME_DEBUG_MASK 0xFFFFFFFFL +//DIGA_RESYNC_FIFO_DEBUG +#define DIGA_RESYNC_FIFO_DEBUG__DIGA_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGA_RESYNC_FIFO_DEBUG__DIGA_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGB_RESYNC_FIFO_DEBUG +#define DIGB_RESYNC_FIFO_DEBUG__DIGB_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGB_RESYNC_FIFO_DEBUG__DIGB_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGC_RESYNC_FIFO_DEBUG +#define DIGC_RESYNC_FIFO_DEBUG__DIGC_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGC_RESYNC_FIFO_DEBUG__DIGC_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGD_RESYNC_FIFO_DEBUG +#define DIGD_RESYNC_FIFO_DEBUG__DIGD_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGD_RESYNC_FIFO_DEBUG__DIGD_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL +//DIGE_RESYNC_FIFO_DEBUG +#define DIGE_RESYNC_FIFO_DEBUG__DIGE_RESYNC_FIFO_DEBUG__SHIFT 0x0 +#define DIGE_RESYNC_FIFO_DEBUG__DIGE_RESYNC_FIFO_DEBUG_MASK 0xFFFFFFFFL + + +// addressBlock: apg_apg_socclk_debugind +//APG_SOCCLK_DEBUG_ID +#define APG_SOCCLK_DEBUG_ID__APG_SOCCLK_DEBUG_ID__SHIFT 0x0 +#define APG_SOCCLK_DEBUG_ID__APG_SOCCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//APG_SOCCLK_DEBUG0 +#define APG_SOCCLK_DEBUG0__APG_SOCCLK_DEBUG0__SHIFT 0x0 +#define APG_SOCCLK_DEBUG0__APG_SOCCLK_DEBUG0_MASK 0xFFFFFFFFL + + +// addressBlock: apg_apg_encclk_debugind +//APG_ENCCLK_DEBUG_ID +#define APG_ENCCLK_DEBUG_ID__APG_ENCCLK_DEBUG_ID__SHIFT 0x0 +#define APG_ENCCLK_DEBUG_ID__APG_ENCCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG0 +#define APG_ENCCLK_DEBUG0__APG_ENCCLK_DEBUG0__SHIFT 0x0 +#define APG_ENCCLK_DEBUG0__APG_ENCCLK_DEBUG0_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG1 +#define APG_ENCCLK_DEBUG1__APG_ENCCLK_DEBUG1__SHIFT 0x0 +#define APG_ENCCLK_DEBUG1__APG_ENCCLK_DEBUG1_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG2 +#define APG_ENCCLK_DEBUG2__APG_ENCCLK_DEBUG2__SHIFT 0x0 +#define APG_ENCCLK_DEBUG2__APG_ENCCLK_DEBUG2_MASK 0xFFFFFFFFL +//APG_ENCCLK_DEBUG3 +#define APG_ENCCLK_DEBUG3__APG_ENCCLK_DEBUG3__SHIFT 0x0 +#define APG_ENCCLK_DEBUG3__APG_ENCCLK_DEBUG3_MASK 0xFFFFFFFFL + + +// addressBlock: dcoh_top_dcoh_topdebugind +//DCOH_TOP_DEBUG_ID +#define DCOH_TOP_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define DCOH_TOP_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux0_auxdebugdispclkind +//DP_AUX0_AUX_DEBUG_DISPCLK_ID +#define DP_AUX0_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX0_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_H +#define DP_AUX0_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_I +#define DP_AUX0_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux0_auxdebugrefclkind +//DP_AUX0_AUX_DEBUG_REFCLK_ID +#define DP_AUX0_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX0_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_A +#define DP_AUX0_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_B +#define DP_AUX0_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_C +#define DP_AUX0_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_D +#define DP_AUX0_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_E +#define DP_AUX0_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_F +#define DP_AUX0_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_G +#define DP_AUX0_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX0_DP_AUX_DEBUG_J +#define DP_AUX0_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX0_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux1_auxdebugdispclkind +//DP_AUX1_AUX_DEBUG_DISPCLK_ID +#define DP_AUX1_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX1_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_H +#define DP_AUX1_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_I +#define DP_AUX1_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux1_auxdebugrefclkind +//DP_AUX1_AUX_DEBUG_REFCLK_ID +#define DP_AUX1_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX1_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_A +#define DP_AUX1_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_B +#define DP_AUX1_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_C +#define DP_AUX1_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_D +#define DP_AUX1_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_E +#define DP_AUX1_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_F +#define DP_AUX1_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_G +#define DP_AUX1_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX1_DP_AUX_DEBUG_J +#define DP_AUX1_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX1_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux2_auxdebugdispclkind +//DP_AUX2_AUX_DEBUG_DISPCLK_ID +#define DP_AUX2_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX2_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_H +#define DP_AUX2_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_I +#define DP_AUX2_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux2_auxdebugrefclkind +//DP_AUX2_AUX_DEBUG_REFCLK_ID +#define DP_AUX2_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX2_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_A +#define DP_AUX2_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_B +#define DP_AUX2_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_C +#define DP_AUX2_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_D +#define DP_AUX2_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_E +#define DP_AUX2_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_F +#define DP_AUX2_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_G +#define DP_AUX2_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX2_DP_AUX_DEBUG_J +#define DP_AUX2_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX2_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux3_auxdebugdispclkind +//DP_AUX3_AUX_DEBUG_DISPCLK_ID +#define DP_AUX3_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX3_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_H +#define DP_AUX3_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_I +#define DP_AUX3_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux3_auxdebugrefclkind +//DP_AUX3_AUX_DEBUG_REFCLK_ID +#define DP_AUX3_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX3_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_A +#define DP_AUX3_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_B +#define DP_AUX3_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_C +#define DP_AUX3_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_D +#define DP_AUX3_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_E +#define DP_AUX3_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_F +#define DP_AUX3_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_G +#define DP_AUX3_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX3_DP_AUX_DEBUG_J +#define DP_AUX3_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX3_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux4_auxdebugdispclkind +//DP_AUX4_AUX_DEBUG_DISPCLK_ID +#define DP_AUX4_AUX_DEBUG_DISPCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX4_AUX_DEBUG_DISPCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_H +#define DP_AUX4_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_H__DP_AUX_DEBUG_H_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_I +#define DP_AUX4_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_I__DP_AUX_DEBUG_I_MASK 0xFFFFFFFFL + + +// addressBlock: dp_aux4_auxdebugrefclkind +//DP_AUX4_AUX_DEBUG_REFCLK_ID +#define DP_AUX4_AUX_DEBUG_REFCLK_ID__DEBUG_ID__SHIFT 0x0 +#define DP_AUX4_AUX_DEBUG_REFCLK_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_A +#define DP_AUX4_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_A__DP_AUX_DEBUG_A_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_B +#define DP_AUX4_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_B__DP_AUX_DEBUG_B_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_C +#define DP_AUX4_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_C__DP_AUX_DEBUG_C_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_D +#define DP_AUX4_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_D__DP_AUX_DEBUG_D_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_E +#define DP_AUX4_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_E__DP_AUX_DEBUG_E_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_F +#define DP_AUX4_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_F__DP_AUX_DEBUG_F_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_G +#define DP_AUX4_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_G__DP_AUX_DEBUG_G_MASK 0xFFFFFFFFL +//DP_AUX4_DP_AUX_DEBUG_J +#define DP_AUX4_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J__SHIFT 0x0 +#define DP_AUX4_DP_AUX_DEBUG_J__DP_AUX_DEBUG_J_MASK 0xFFFFFFFFL + + +// addressBlock: hpd0_hpddebugind +//HPD0_HPD_DEBUG_ID +#define HPD0_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD0_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD0_HPD_DEBUG_0 +#define HPD0_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD0_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd1_hpddebugind +//HPD1_HPD_DEBUG_ID +#define HPD1_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD1_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD1_HPD_DEBUG_0 +#define HPD1_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD1_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd2_hpddebugind +//HPD2_HPD_DEBUG_ID +#define HPD2_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD2_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD2_HPD_DEBUG_0 +#define HPD2_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD2_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd3_hpddebugind +//HPD3_HPD_DEBUG_ID +#define HPD3_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD3_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD3_HPD_DEBUG_0 +#define HPD3_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD3_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpd4_hpddebugind +//HPD4_HPD_DEBUG_ID +#define HPD4_HPD_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPD4_HPD_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL +//HPD4_HPD_DEBUG_0 +#define HPD4_HPD_DEBUG_0__HPD_DEBUG_0__SHIFT 0x0 +#define HPD4_HPD_DEBUG_0__HPD_DEBUG_0_MASK 0xFFFFFFFFL + + +// addressBlock: hpo_top_hpo_topdebugind +//HPO_TOP_DEBUG_ID +#define HPO_TOP_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define HPO_TOP_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_link_enc0_linkencdebugind +//HDMI_LINK_ENC_DEBUG_ID +#define HDMI_LINK_ENC_DEBUG_ID__HDMI_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define HDMI_LINK_ENC_DEBUG_ID__HDMI_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_frl_enc0_frldebugind +//HDMI_FRL_ENC_DEBUG_ID +#define HDMI_FRL_ENC_DEBUG_ID__HDMI_FRL_ENC_DEBUG_ID__SHIFT 0x0 +#define HDMI_FRL_ENC_DEBUG_ID__HDMI_FRL_ENC_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_hdmistreamclk_debugind +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_0_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_1_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_2_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_3_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_4_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_5_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_6_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_7_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_8_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_9_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_10_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_11_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_12_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_13_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_14_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15__SHIFT 0x0 +#define HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15__HDMI_STREAM_ENC_HDMISTREAMCLK_DEBUG_15_MASK 0xFFFFFFFFL + + +// addressBlock: hdmi_stream_enc0_hdmi_stream_enc_dispclk_debugind +//HDMI_STREAM_ENC_DISPCLK_DEBUG_ID +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_ID__HDMI_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_ID__HDMI_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_0__HDMI_STREAM_ENC_DISPCLK_DEBUG_0__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_0__HDMI_STREAM_ENC_DISPCLK_DEBUG_0_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_1 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_1__HDMI_STREAM_ENC_DISPCLK_DEBUG_1__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_1__HDMI_STREAM_ENC_DISPCLK_DEBUG_1_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_2 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_2__HDMI_STREAM_ENC_DISPCLK_DEBUG_2__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_2__HDMI_STREAM_ENC_DISPCLK_DEBUG_2_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_3 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_3__HDMI_STREAM_ENC_DISPCLK_DEBUG_3__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_3__HDMI_STREAM_ENC_DISPCLK_DEBUG_3_MASK 0xFFFFFFFFL +//HDMI_STREAM_ENC_DISPCLK_DEBUG_4 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_4__HDMI_STREAM_ENC_DISPCLK_DEBUG_4__SHIFT 0x0 +#define HDMI_STREAM_ENC_DISPCLK_DEBUG_4__HDMI_STREAM_ENC_DISPCLK_DEBUG_4_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc0_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc0_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc0_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc1_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc1_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc1_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc2_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc2_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc2_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dispclk_debugind +//DP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID +#define DP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_DISPCLK_DEBUG_ID__DP_STREAM_ENC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc3_dp_stream_enc_dpstreamclk_debugind +//DP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID__DP_STREAM_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_stream_enc3_dp_stream_enc_symclk32_debugind +//DP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID +#define DP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SYMCLK32_DEBUG_ID__DP_STREAM_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_symclk32_debugind +//DP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMCLK32_DEBUG_ID__DP_SYM32_ENC_SYMCLK32_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_sym32_enc3_dp_sym32_enc_dpstreamclk_debugind +//DP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID +#define DP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID__DP_SYM32_ENC_DPSTREAMCLK_DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc0_dplinkencdebugind +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym320_dpdphysym32debugind +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc1_dplinkencdebugind +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym321_dpdphysym32debugind +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc2_dplinkencdebugind +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym322_dpdphysym32debugind +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: dp_link_enc3_dplinkencdebugind +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_ID__DP_LINK_ENC_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS0__DP_LINK_ENC_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS1__DP_LINK_ENC_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS2__DP_LINK_ENC_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_DEBUG_BUS3__DP_LINK_ENC_DEBUG_BUS3_MASK 0xFFFFFFFFL + + +// addressBlock: dp_dphy_sym323_dpdphysym32debugind +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_ID__DP_DPHY_SYM32_DEBUG_ID_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS0__DP_DPHY_SYM32_DEBUG_BUS0_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS1__DP_DPHY_SYM32_DEBUG_BUS1_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS2__DP_DPHY_SYM32_DEBUG_BUS2_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS3__DP_DPHY_SYM32_DEBUG_BUS3_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS4__DP_DPHY_SYM32_DEBUG_BUS4_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS5__DP_DPHY_SYM32_DEBUG_BUS5_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS6__DP_DPHY_SYM32_DEBUG_BUS6_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS7__DP_DPHY_SYM32_DEBUG_BUS7_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS8__DP_DPHY_SYM32_DEBUG_BUS8_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS9__DP_DPHY_SYM32_DEBUG_BUS9_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS10__DP_DPHY_SYM32_DEBUG_BUS10_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS11__DP_DPHY_SYM32_DEBUG_BUS11_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS12__DP_DPHY_SYM32_DEBUG_BUS12_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS13__DP_DPHY_SYM32_DEBUG_BUS13_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS14__DP_DPHY_SYM32_DEBUG_BUS14_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS15__DP_DPHY_SYM32_DEBUG_BUS15_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS16__DP_DPHY_SYM32_DEBUG_BUS16_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS17__DP_DPHY_SYM32_DEBUG_BUS17_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS18__DP_DPHY_SYM32_DEBUG_BUS18_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS19__DP_DPHY_SYM32_DEBUG_BUS19_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS20__DP_DPHY_SYM32_DEBUG_BUS20_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS21__DP_DPHY_SYM32_DEBUG_BUS21_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS22__DP_DPHY_SYM32_DEBUG_BUS22_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_DEBUG_BUS23__DP_DPHY_SYM32_DEBUG_BUS23_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_sinkinfoind +//AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000FFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_PORTID1 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xFFFFFFFFL +//SINK_DESCRIPTION0 +#define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION1 +#define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION2 +#define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION3 +#define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION4 +#define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION5 +#define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION6 +#define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION7 +#define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION8 +#define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION9 +#define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION10 +#define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION11 +#define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION12 +#define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION13 +#define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION14 +#define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION15 +#define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION16 +#define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000FFL +//SINK_DESCRIPTION17 +#define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x0 +#define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000FFL + + +// addressBlock: azf0controller_azinputcrc0resultind +//AZALIA_INPUT_CRC0_CHANNEL0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL1 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL2 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL3 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL4 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL5 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL6 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CHANNEL7 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azinputcrc1resultind +//AZALIA_INPUT_CRC1_CHANNEL0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL0__INPUT_CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL1 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL1__INPUT_CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL2 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL2__INPUT_CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL3 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL3__INPUT_CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL4 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL4__INPUT_CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL5 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL5__INPUT_CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL6 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL6__INPUT_CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CHANNEL7 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CHANNEL7__INPUT_CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc0resultind +//AZALIA_CRC0_CHANNEL0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL1 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL2 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL3 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL4 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL5 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL6 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CHANNEL7 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC0_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0controller_azcrc1resultind +//AZALIA_CRC1_CHANNEL0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL0__CRC_CHANNEL0_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL1 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL1__CRC_CHANNEL1_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL2 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL2__CRC_CHANNEL2_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL3 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL3__CRC_CHANNEL3_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL4 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL4__CRC_CHANNEL4_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL5 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL5__CRC_CHANNEL5_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL6 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL6__CRC_CHANNEL6_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CHANNEL7 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7__SHIFT 0x0 +#define AZALIA_CRC1_CHANNEL7__CRC_CHANNEL7_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream0_streamind +//AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM0_AZALIA_STREAM_DEBUG +#define AZF0STREAM0_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream1_streamind +//AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM1_AZALIA_STREAM_DEBUG +#define AZF0STREAM1_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream2_streamind +//AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM2_AZALIA_STREAM_DEBUG +#define AZF0STREAM2_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream3_streamind +//AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM3_AZALIA_STREAM_DEBUG +#define AZF0STREAM3_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream4_streamind +//AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM4_AZALIA_STREAM_DEBUG +#define AZF0STREAM4_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream5_streamind +//AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM5_AZALIA_STREAM_DEBUG +#define AZF0STREAM5_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream6_streamind +//AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM6_AZALIA_STREAM_DEBUG +#define AZF0STREAM6_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream7_streamind +//AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM7_AZALIA_STREAM_DEBUG +#define AZF0STREAM7_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream8_streamind +//AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM8_AZALIA_STREAM_DEBUG +#define AZF0STREAM8_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream9_streamind +//AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM9_AZALIA_STREAM_DEBUG +#define AZF0STREAM9_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream10_streamind +//AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM10_AZALIA_STREAM_DEBUG +#define AZF0STREAM10_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream11_streamind +//AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM11_AZALIA_STREAM_DEBUG +#define AZF0STREAM11_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream12_streamind +//AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM12_AZALIA_STREAM_DEBUG +#define AZF0STREAM12_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream13_streamind +//AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM13_AZALIA_STREAM_DEBUG +#define AZF0STREAM13_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream14_streamind +//AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM14_AZALIA_STREAM_DEBUG +#define AZF0STREAM14_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0stream15_streamind +//AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x10 +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007FL +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007F00L +#define AZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00FF0000L +//AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L +//AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xFFFFFFFFL +//AZF0STREAM15_AZALIA_STREAM_DEBUG +#define AZF0STREAM15_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: azf0endpoint0_endpointind +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint1_endpointind +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint2_endpointind +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint3_endpointind +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint4_endpointind +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint5_endpointind +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint6_endpointind +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0endpoint7_endpointind +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x1b +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00FC0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LFE_PLAYBACK_LEVEL_MASK 0x03000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_INDEX_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__SUPPORTS_AI_MASK 0x00000040L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_PACKET_ENABLE_MASK 0x00000080L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_MASK 0x00000300L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE0_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_ACP_DATA__ACP_TYPE_DEPENDENT_BYTE1_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000FFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xFFFF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00FF0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xFF000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000FFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x9 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0xc +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x11 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x14 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000F000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00F00000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS__AUDIO_ENABLE_STATUS_MASK 0x00000001L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS__AUDIO_ENABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS__AUDIO_DISABLED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK__SHIFT 0x4 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE__SHIFT 0x8 +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_FLAG_MASK 0x00000001L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_MASK_MASK 0x00000010L +#define AZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS__AUDIO_FORMAT_CHANGED_TYPE_MASK 0x00000100L +//AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS +#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_ENDPOINT_FGCG_REP_DIS__ENDPOINT_FGCG_REP_DIS_MASK 0x00000001L + + +// addressBlock: azf0inputendpoint0_inputendpointind +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint1_inputendpointind +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint2_inputendpointind +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint3_inputendpointind +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint4_inputendpointind +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint5_inputendpointind +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint6_inputendpointind +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: azf0inputendpoint7_inputendpointind +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG__AZALIA_INPUT_DEBUG_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x9 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE__SHIFT 0x11 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x19 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00000100L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00000200L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_ENABLE_MASK 0x00010000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_MUTE_MASK 0x00020000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL6_CHANNEL_ID_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xF0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_GATING_DISABLE_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__CLOCK_ON_STATE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x1c +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03FFFFFFL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L + + +// addressBlock: dscc_dsccdebugind0 +//DSCC_DEBUG_ID +#define DSCC_DEBUG_ID__DSCC_DEBUG_ID__SHIFT 0x0 +#define DSCC_DEBUG_ID__DSCC_DEBUG_ID_MASK 0xFFFFFFFFL +//DSCC_DEBUG_0 +#define DSCC_DEBUG_0__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC_DEBUG_0__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC_DEBUG_1 +#define DSCC_DEBUG_1__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC_DEBUG_1__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC_DEBUG_2 +#define DSCC_DEBUG_2__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC_DEBUG_2__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC_DEBUG_3 +#define DSCC_DEBUG_3__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC_DEBUG_3__DSCC_RATE_BUFFER_MODEL_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC_DEBUG_4 +#define DSCC_DEBUG_4__DSCC_DEBUG_4__SHIFT 0x0 +#define DSCC_DEBUG_4__DSCC_DEBUG_4_MASK 0xFFFFFFFFL +//DSCC_DEBUG_5 +#define DSCC_DEBUG_5__DSCC_DEBUG_5__SHIFT 0x0 +#define DSCC_DEBUG_5__DSCC_DEBUG_5_MASK 0xFFFFFFFFL +//DSCC_DEBUG_6 +#define DSCC_DEBUG_6__DSCC_DEBUG_6__SHIFT 0x0 +#define DSCC_DEBUG_6__DSCC_DEBUG_6_MASK 0xFFFFFFFFL +//DSCC_DEBUG_7 +#define DSCC_DEBUG_7__DSCC_DEBUG_7__SHIFT 0x0 +#define DSCC_DEBUG_7__DSCC_DEBUG_7_MASK 0xFFFFFFFFL +//DSCC_DEBUG_8 +#define DSCC_DEBUG_8__DSCC_DEBUG_8__SHIFT 0x0 +#define DSCC_DEBUG_8__DSCC_DEBUG_8_MASK 0xFFFFFFFFL +//DSCC_DEBUG_9 +#define DSCC_DEBUG_9__DSCC_DEBUG_9__SHIFT 0x0 +#define DSCC_DEBUG_9__DSCC_DEBUG_9_MASK 0xFFFFFFFFL +//DSCC_DEBUG_10 +#define DSCC_DEBUG_10__DSCC_DEBUG_10__SHIFT 0x0 +#define DSCC_DEBUG_10__DSCC_DEBUG_10_MASK 0xFFFFFFFFL +//DSCC_DEBUG_11 +#define DSCC_DEBUG_11__DSCC_DEBUG_11__SHIFT 0x0 +#define DSCC_DEBUG_11__DSCC_DEBUG_11_MASK 0xFFFFFFFFL +//DSCC_DEBUG_12 +#define DSCC_DEBUG_12__DSCC_DEBUG_12__SHIFT 0x0 +#define DSCC_DEBUG_12__DSCC_DEBUG_12_MASK 0xFFFFFFFFL +//DSCC_DEBUG_13 +#define DSCC_DEBUG_13__DSCC_DEBUG_13__SHIFT 0x0 +#define DSCC_DEBUG_13__DSCC_DEBUG_13_MASK 0xFFFFFFFFL +//DSCC_DEBUG_14 +#define DSCC_DEBUG_14__DSCC_DEBUG_14__SHIFT 0x0 +#define DSCC_DEBUG_14__DSCC_DEBUG_14_MASK 0xFFFFFFFFL +//DSCC_DEBUG_15 +#define DSCC_DEBUG_15__DSCC_DEBUG_15__SHIFT 0x0 +#define DSCC_DEBUG_15__DSCC_DEBUG_15_MASK 0xFFFFFFFFL +//DSCC_DEBUG_16 +#define DSCC_DEBUG_16__DSCC_DEBUG_16__SHIFT 0x0 +#define DSCC_DEBUG_16__DSCC_DEBUG_16_MASK 0xFFFFFFFFL +//DSCC_DEBUG_17 +#define DSCC_DEBUG_17__DSCC_DEBUG_17__SHIFT 0x0 +#define DSCC_DEBUG_17__DSCC_DEBUG_17_MASK 0xFFFFFFFFL +//DSCC_DEBUG_18 +#define DSCC_DEBUG_18__DSCC_DEBUG_18__SHIFT 0x0 +#define DSCC_DEBUG_18__DSCC_DEBUG_18_MASK 0xFFFFFFFFL +//DSCC_DEBUG_19 +#define DSCC_DEBUG_19__DSCC_DEBUG_19__SHIFT 0x0 +#define DSCC_DEBUG_19__DSCC_DEBUG_19_MASK 0xFFFFFFFFL +//DSCC_DEBUG_20 +#define DSCC_DEBUG_20__DSCC_DEBUG_20__SHIFT 0x0 +#define DSCC_DEBUG_20__DSCC_DEBUG_20_MASK 0xFFFFFFFFL +//DSCC_DEBUG_21 +#define DSCC_DEBUG_21__DSCC_DEBUG_21__SHIFT 0x0 +#define DSCC_DEBUG_21__DSCC_DEBUG_21_MASK 0xFFFFFFFFL +//DSCC_DEBUG_22 +#define DSCC_DEBUG_22__DSCC_DEBUG_22__SHIFT 0x0 +#define DSCC_DEBUG_22__DSCC_DEBUG_22_MASK 0xFFFFFFFFL +//DSCC_DEBUG_23 +#define DSCC_DEBUG_23__DSCC_DEBUG_23__SHIFT 0x0 +#define DSCC_DEBUG_23__DSCC_DEBUG_23_MASK 0xFFFFFFFFL +//DSCC_DEBUG_24 +#define DSCC_DEBUG_24__DSCC_DEBUG_24__SHIFT 0x0 +#define DSCC_DEBUG_24__DSCC_DEBUG_24_MASK 0xFFFFFFFFL +//DSCC_DEBUG_25 +#define DSCC_DEBUG_25__DSCC_DEBUG_25__SHIFT 0x0 +#define DSCC_DEBUG_25__DSCC_DEBUG_25_MASK 0xFFFFFFFFL +//DSCC_DEBUG_26 +#define DSCC_DEBUG_26__DSCC_DEBUG_26__SHIFT 0x0 +#define DSCC_DEBUG_26__DSCC_DEBUG_26_MASK 0xFFFFFFFFL +//DSCC_DEBUG_27 +#define DSCC_DEBUG_27__DSCC_DEBUG_27__SHIFT 0x0 +#define DSCC_DEBUG_27__DSCC_DEBUG_27_MASK 0xFFFFFFFFL +//DSCC_DEBUG_28 +#define DSCC_DEBUG_28__DSCC_DEBUG_28__SHIFT 0x0 +#define DSCC_DEBUG_28__DSCC_DEBUG_28_MASK 0xFFFFFFFFL + + +// addressBlock: dscc_dscc_dispclk_debugind0 +//DSCC_DISPCLK_DEBUG_ID +#define DSCC_DISPCLK_DEBUG_ID__DSCC_DISPCLK_DEBUG_ID__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_ID__DSCC_DISPCLK_DEBUG_ID_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_0 +#define DSCC_DISPCLK_DEBUG_0__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_0__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_1 +#define DSCC_DISPCLK_DEBUG_1__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_1__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_2 +#define DSCC_DISPCLK_DEBUG_2__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_2__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_3 +#define DSCC_DISPCLK_DEBUG_3__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_3__DSCC_OUTPUT_BUFFER_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC_DISPCLK_DEBUG_4 +#define DSCC_DISPCLK_DEBUG_4__DSCC_INITIAL_XMIT_DELAY_REACHED__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_4__DSCC_LAST_SLICE_PIXEL_COUNT_AT_INITIAL_XMIT_DELAY__SHIFT 0x4 +#define DSCC_DISPCLK_DEBUG_4__DSCC_OUTPUT_BUFFER_PIXEL_THRESHOLD_AT_INITIAL_XMIT_DELAY__SHIFT 0x10 +#define DSCC_DISPCLK_DEBUG_4__DSCC_INITIAL_XMIT_DELAY_REACHED_MASK 0x00000001L +#define DSCC_DISPCLK_DEBUG_4__DSCC_LAST_SLICE_PIXEL_COUNT_AT_INITIAL_XMIT_DELAY_MASK 0x00007FF0L +#define DSCC_DISPCLK_DEBUG_4__DSCC_OUTPUT_BUFFER_PIXEL_THRESHOLD_AT_INITIAL_XMIT_DELAY_MASK 0xFFFF0000L +//DSCC_DISPCLK_DEBUG_5 +#define DSCC_DISPCLK_DEBUG_5__DSCC_TOTAL_PIXEL_COUNT_IN_OUTPUT_BUFFER__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_5__DSCC_TOTAL_PIXEL_COUNT_IN_OUTPUT_BUFFER_MASK 0x0000FFFFL +//DSCC_DISPCLK_DEBUG_6 +#define DSCC_DISPCLK_DEBUG_6__DSCC_DISPCLK_DEBUG_6__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_6__DSCC_DISPCLK_DEBUG_6_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_7 +#define DSCC_DISPCLK_DEBUG_7__DSCC_DISPCLK_DEBUG_7__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_7__DSCC_DISPCLK_DEBUG_7_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_8 +#define DSCC_DISPCLK_DEBUG_8__DSCC_DISPCLK_DEBUG_8__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_8__DSCC_DISPCLK_DEBUG_8_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_9 +#define DSCC_DISPCLK_DEBUG_9__DSCC_DISPCLK_DEBUG_9__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_9__DSCC_DISPCLK_DEBUG_9_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_10 +#define DSCC_DISPCLK_DEBUG_10__DSCC_DISPCLK_DEBUG_10__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_10__DSCC_DISPCLK_DEBUG_10_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_11 +#define DSCC_DISPCLK_DEBUG_11__DSCC_DISPCLK_DEBUG_11__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_11__DSCC_DISPCLK_DEBUG_11_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_12 +#define DSCC_DISPCLK_DEBUG_12__DSCC_DISPCLK_DEBUG_12__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_12__DSCC_DISPCLK_DEBUG_12_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_13 +#define DSCC_DISPCLK_DEBUG_13__DSCC_DISPCLK_DEBUG_13__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_13__DSCC_DISPCLK_DEBUG_13_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_14 +#define DSCC_DISPCLK_DEBUG_14__DSCC_DISPCLK_DEBUG_14__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_14__DSCC_DISPCLK_DEBUG_14_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_15 +#define DSCC_DISPCLK_DEBUG_15__DSCC_DISPCLK_DEBUG_15__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_15__DSCC_DISPCLK_DEBUG_15_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_16 +#define DSCC_DISPCLK_DEBUG_16__DSCC_DISPCLK_DEBUG_16__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_16__DSCC_DISPCLK_DEBUG_16_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_17 +#define DSCC_DISPCLK_DEBUG_17__DSCC_DISPCLK_DEBUG_17__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_17__DSCC_DISPCLK_DEBUG_17_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_18 +#define DSCC_DISPCLK_DEBUG_18__DSCC_DISPCLK_DEBUG_18__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_18__DSCC_DISPCLK_DEBUG_18_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_19 +#define DSCC_DISPCLK_DEBUG_19__DSCC_DISPCLK_DEBUG_19__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_19__DSCC_DISPCLK_DEBUG_19_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_20 +#define DSCC_DISPCLK_DEBUG_20__DSCC_DISPCLK_DEBUG_20__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_20__DSCC_DISPCLK_DEBUG_20_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_21 +#define DSCC_DISPCLK_DEBUG_21__DSCC_DISPCLK_DEBUG_21__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_21__DSCC_DISPCLK_DEBUG_21_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_22 +#define DSCC_DISPCLK_DEBUG_22__DSCC_DISPCLK_DEBUG_22__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_22__DSCC_DISPCLK_DEBUG_22_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_23 +#define DSCC_DISPCLK_DEBUG_23__DSCC_DISPCLK_DEBUG_23__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_23__DSCC_DISPCLK_DEBUG_23_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_24 +#define DSCC_DISPCLK_DEBUG_24__DSCC_DISPCLK_DEBUG_24__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_24__DSCC_DISPCLK_DEBUG_24_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_25 +#define DSCC_DISPCLK_DEBUG_25__DSCC_DISPCLK_DEBUG_25__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_25__DSCC_DISPCLK_DEBUG_25_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_26 +#define DSCC_DISPCLK_DEBUG_26__DSCC_DISPCLK_DEBUG_26__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_26__DSCC_DISPCLK_DEBUG_26_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_27 +#define DSCC_DISPCLK_DEBUG_27__DSCC_DISPCLK_DEBUG_27__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_27__DSCC_DISPCLK_DEBUG_27_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_28 +#define DSCC_DISPCLK_DEBUG_28__DSCC_DISPCLK_DEBUG_28__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_28__DSCC_DISPCLK_DEBUG_28_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_29 +#define DSCC_DISPCLK_DEBUG_29__DSCC_DISPCLK_DEBUG_29__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_29__DSCC_DISPCLK_DEBUG_29_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_30 +#define DSCC_DISPCLK_DEBUG_30__DSCC_DISPCLK_DEBUG_30__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_30__DSCC_DISPCLK_DEBUG_30_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_31 +#define DSCC_DISPCLK_DEBUG_31__DSCC_DISPCLK_DEBUG_31__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_31__DSCC_DISPCLK_DEBUG_31_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_32 +#define DSCC_DISPCLK_DEBUG_32__DSCC_DISPCLK_DEBUG_32__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_32__DSCC_DISPCLK_DEBUG_32_MASK 0xFFFFFFFFL +//DSCC_DISPCLK_DEBUG_33 +#define DSCC_DISPCLK_DEBUG_33__DSCC_DISPCLK_DEBUG_33__SHIFT 0x0 +#define DSCC_DISPCLK_DEBUG_33__DSCC_DISPCLK_DEBUG_33_MASK 0xFFFFFFFFL + + +// addressBlock: dsccif_dsccifdebugind +//DSCCIF_DEBUG_ID +#define DSCCIF_DEBUG_ID__DSCCIF_DEBUG_ID__SHIFT 0x0 +#define DSCCIF_DEBUG_ID__DSCCIF_DEBUG_ID_MASK 0xFFFFFFFFL +//DSCCIF_DEBUG_0 +#define DSCCIF_DEBUG_0__DSCCIF_DEBUG_0__SHIFT 0x0 +#define DSCCIF_DEBUG_0__DSCCIF_DEBUG_0_MASK 0xFFFFFFFFL +//DSCCIF_DEBUG_1 +#define DSCCIF_DEBUG_1__DSCCIF_DEBUG_1__SHIFT 0x0 +#define DSCCIF_DEBUG_1__DSCCIF_DEBUG_1_MASK 0xFFFFFFFFL + + +// addressBlock: dsc_top_dsc_topdebugind +//DSC_TOP_DEBUG_ID +#define DSC_TOP_DEBUG_ID__DSC_TOP_DEBUG_ID__SHIFT 0x0 +#define DSC_TOP_DEBUG_ID__DSC_TOP_DEBUG_ID_MASK 0xFFFFFFFFL +//DSC_TOP_DEBUG_0 +#define DSC_TOP_DEBUG_0__DSC_TOP_DEBUG_0__SHIFT 0x0 +#define DSC_TOP_DEBUG_0__DSC_TOP_DEBUG_0_MASK 0xFFFFFFFFL +//DSC_TOP_DEBUG_1 +#define DSC_TOP_DEBUG_1__DSC_TOP_DEBUG_1__SHIFT 0x0 +#define DSC_TOP_DEBUG_1__DSC_TOP_DEBUG_1_MASK 0xFFFFFFFFL +//DSC_TOP_DEBUG_2 +#define DSC_TOP_DEBUG_2__DSC_TOP_DEBUG_2__SHIFT 0x0 +#define DSC_TOP_DEBUG_2__DSC_TOP_DEBUG_2_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port0_dpiaportdebugind +//DPIA_PORT0_DPIA_PORT_DEBUG_ID +#define DPIA_PORT0_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT0_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT0_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT0_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT0_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port1_dpiaportdebugind +//DPIA_PORT1_DPIA_PORT_DEBUG_ID +#define DPIA_PORT1_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT1_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT1_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT1_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT1_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port2_dpiaportdebugind +//DPIA_PORT2_DPIA_PORT_DEBUG_ID +#define DPIA_PORT2_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT2_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT2_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT2_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT2_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port3_dpiaportdebugind +//DPIA_PORT3_DPIA_PORT_DEBUG_ID +#define DPIA_PORT3_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT3_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT3_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT3_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT3_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port4_dpiaportdebugind +//DPIA_PORT4_DPIA_PORT_DEBUG_ID +#define DPIA_PORT4_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT4_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT4_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT4_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT4_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port5_dpiaportdebugind +//DPIA_PORT5_DPIA_PORT_DEBUG_ID +#define DPIA_PORT5_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT5_DPIA_PORT_DEBUG_ID__DPIA_PORT_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT5_DPIA_PORT_DEBUG_BUS0 +#define DPIA_PORT5_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0__SHIFT 0x0 +#define DPIA_PORT5_DPIA_PORT_DEBUG_BUS0__DPIA_PORT_DEBUG_BUS0_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml0_dpiaportmldebugind +//DPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML0_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml1_dpiaportmldebugind +//DPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML1_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml2_dpiaportmldebugind +//DPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML2_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml3_dpiaportmldebugind +//DPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML3_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml4_dpiaportmldebugind +//DPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML4_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_ml5_dpiaportmldebugind +//DPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID +#define DPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_TEST_DEBUG_ID__DPIA_PORT_ML_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA0__DPIA_PORT_ML_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA1__DPIA_PORT_ML_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA2__DPIA_PORT_ML_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA3__DPIA_PORT_ML_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA4__DPIA_PORT_ML_DEBUG_DATA4_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA5__DPIA_PORT_ML_DEBUG_DATA5_MASK 0xFFFFFFFFL +//DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6__SHIFT 0x0 +#define DPIA_PORT_ML5_DPIA_PORT_ML_DEBUG_DATA6__DPIA_PORT_ML_DEBUG_DATA6_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux0_dpiaportauxdebugind +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX0_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux1_dpiaportauxdebugind +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX1_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux2_dpiaportauxdebugind +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX2_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux3_dpiaportauxdebugind +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX3_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux4_dpiaportauxdebugind +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX4_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_port_aux5_dpiaportauxdebugind +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG_ID__DPIA_PORT_AUX_TEST_DEBUG_ID_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG1__DPIA_PORT_AUX_TEST_DEBUG1_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG2__DPIA_PORT_AUX_TEST_DEBUG2_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG3__DPIA_PORT_AUX_TEST_DEBUG3_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG4__DPIA_PORT_AUX_TEST_DEBUG4_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG5__DPIA_PORT_AUX_TEST_DEBUG5_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG6__DPIA_PORT_AUX_TEST_DEBUG6_MASK 0xFFFFFFFFL +//DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7__SHIFT 0x0 +#define DPIA_PORT_AUX5_DPIA_PORT_AUX_TEST_DEBUG7__DPIA_PORT_AUX_TEST_DEBUG7_MASK 0xFFFFFFFFL + + +// addressBlock: dpia_mu0_dpia_mu_debugind +//DPIA_MU_DEBUG_ID +#define DPIA_MU_DEBUG_ID__DEBUG_ID__SHIFT 0x0 +#define DPIA_MU_DEBUG_ID__DEBUG_ID_MASK 0xFFFFFFFFL + + +// addressBlock: azendpoint_descriptorind +//AUDIO_DESCRIPTOR0 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR1 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR2 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR3 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR4 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR5 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR6 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR7 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR8 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR9 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR10 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR11 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR12 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AUDIO_DESCRIPTOR13 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x0 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT0_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT0_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dispdec +//PHYPLLA_PIXCLK_RESYNC_CNTL +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLA_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLB_PIXCLK_RESYNC_CNTL +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLB_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLC_PIXCLK_RESYNC_CNTL +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLC_PIXCLK_RESYNC_CNTL__PHYPLLC_PIXCLK_ENABLE_MASK 0x00000100L +//PHYPLLD_PIXCLK_RESYNC_CNTL +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLD_PIXCLK_RESYNC_CNTL__PHYPLLD_PIXCLK_ENABLE_MASK 0x00000100L +//DP_DTO_DBUF_EN +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN__SHIFT 0x0 +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN__SHIFT 0x1 +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN__SHIFT 0x2 +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN__SHIFT 0x3 +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN__SHIFT 0x4 +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN__SHIFT 0x5 +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN__SHIFT 0x6 +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN__SHIFT 0x7 +#define DP_DTO_DBUF_EN__DP_DTO0_DBUF_EN_MASK 0x00000001L +#define DP_DTO_DBUF_EN__DP_DTO1_DBUF_EN_MASK 0x00000002L +#define DP_DTO_DBUF_EN__DP_DTO2_DBUF_EN_MASK 0x00000004L +#define DP_DTO_DBUF_EN__DP_DTO3_DBUF_EN_MASK 0x00000008L +#define DP_DTO_DBUF_EN__DP_DTO4_DBUF_EN_MASK 0x00000010L +#define DP_DTO_DBUF_EN__DP_DTO5_DBUF_EN_MASK 0x00000020L +#define DP_DTO_DBUF_EN__DP_DTO6_DBUF_EN_MASK 0x00000040L +#define DP_DTO_DBUF_EN__DP_DTO7_DBUF_EN_MASK 0x00000080L +//DSCCLK3_DTO_PARAM +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE__SHIFT 0x0 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO__SHIFT 0x10 +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK3_DTO_PARAM__DSCCLK3_DTO_MODULO_MASK 0x00FF0000L +//DPREFCLK_CGTT_BLK_CTRL_REG +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPREFCLK_CGTT_BLK_CTRL_REG__DPREFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_GATE_DISABLE_CNTL4 +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_ROOT_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_ROOT_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_ROOT_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_ROOT_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_ROOT_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_ROOT_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_ROOT_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_ROOT_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE_MASK 0x00800000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK4_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK5_GATE_DISABLE_MASK 0x10000000L +//DPSTREAMCLK_CNTL +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT 0x3 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT 0x4 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN__SHIFT 0x7 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL__SHIFT 0x8 +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN__SHIFT 0xb +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL__SHIFT 0xc +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN__SHIFT 0xf +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN_MASK 0x00000008L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL_MASK 0x00000070L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK1_EN_MASK 0x00000080L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_SRC_SEL_MASK 0x00000700L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK2_EN_MASK 0x00000800L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_SRC_SEL_MASK 0x00007000L +#define DPSTREAMCLK_CNTL__DPSTREAMCLK3_EN_MASK 0x00008000L +//REFCLK_CGTT_BLK_CTRL_REG +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//PHYPLLE_PIXCLK_RESYNC_CNTL +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE__SHIFT 0x0 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE__SHIFT 0x8 +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L +#define PHYPLLE_PIXCLK_RESYNC_CNTL__PHYPLLE_PIXCLK_ENABLE_MASK 0x00000100L +//DCCG_PERFMON_CNTL2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE__SHIFT 0x5 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE__SHIFT 0x6 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE__SHIFT 0x7 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE__SHIFT 0x8 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE__SHIFT 0x9 +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DSICLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_REFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYC_PIXCLK_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYD_PIXCLK_ENABLE_MASK 0x00000020L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYE_PIXCLK_ENABLE_MASK 0x00000040L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYF_PIXCLK_ENABLE_MASK 0x00000080L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_UNIPHYG_PIXCLK_ENABLE_MASK 0x00000100L +#define DCCG_PERFMON_CNTL2__DCCG_PERF_DTBCLK0_ENABLE_MASK 0x00000200L +//DPIASYMCLK_CNTL +#define DPIASYMCLK_CNTL__DPIASYMCLK0_SRC_SEL__SHIFT 0x0 +#define DPIASYMCLK_CNTL__DPIASYMCLK0_EN__SHIFT 0x3 +#define DPIASYMCLK_CNTL__DPIASYMCLK1_SRC_SEL__SHIFT 0x4 +#define DPIASYMCLK_CNTL__DPIASYMCLK1_EN__SHIFT 0x7 +#define DPIASYMCLK_CNTL__DPIASYMCLK2_SRC_SEL__SHIFT 0x8 +#define DPIASYMCLK_CNTL__DPIASYMCLK2_EN__SHIFT 0xb +#define DPIASYMCLK_CNTL__DPIASYMCLK3_SRC_SEL__SHIFT 0xc +#define DPIASYMCLK_CNTL__DPIASYMCLK3_EN__SHIFT 0xf +#define DPIASYMCLK_CNTL__DPIASYMCLK4_SRC_SEL__SHIFT 0x10 +#define DPIASYMCLK_CNTL__DPIASYMCLK4_EN__SHIFT 0x13 +#define DPIASYMCLK_CNTL__DPIASYMCLK5_SRC_SEL__SHIFT 0x14 +#define DPIASYMCLK_CNTL__DPIASYMCLK5_EN__SHIFT 0x17 +#define DPIASYMCLK_CNTL__DPIASYMCLK0_SRC_SEL_MASK 0x00000007L +#define DPIASYMCLK_CNTL__DPIASYMCLK0_EN_MASK 0x00000008L +#define DPIASYMCLK_CNTL__DPIASYMCLK1_SRC_SEL_MASK 0x00000070L +#define DPIASYMCLK_CNTL__DPIASYMCLK1_EN_MASK 0x00000080L +#define DPIASYMCLK_CNTL__DPIASYMCLK2_SRC_SEL_MASK 0x00000700L +#define DPIASYMCLK_CNTL__DPIASYMCLK2_EN_MASK 0x00000800L +#define DPIASYMCLK_CNTL__DPIASYMCLK3_SRC_SEL_MASK 0x00007000L +#define DPIASYMCLK_CNTL__DPIASYMCLK3_EN_MASK 0x00008000L +#define DPIASYMCLK_CNTL__DPIASYMCLK4_SRC_SEL_MASK 0x00070000L +#define DPIASYMCLK_CNTL__DPIASYMCLK4_EN_MASK 0x00080000L +#define DPIASYMCLK_CNTL__DPIASYMCLK5_SRC_SEL_MASK 0x00700000L +#define DPIASYMCLK_CNTL__DPIASYMCLK5_EN_MASK 0x00800000L +//DCCG_GLOBAL_FGCG_REP_CNTL +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS__SHIFT 0x0 +#define DCCG_GLOBAL_FGCG_REP_CNTL__DCCG_GLOBAL_FGCG_REP_DIS_MASK 0x00000001L +//OTG_ADD_DROP_PIXEL_CNTL +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_ADD_PIXEL__SHIFT 0x0 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_ADD_PIXEL__SHIFT 0x1 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_ADD_PIXEL__SHIFT 0x2 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_ADD_PIXEL__SHIFT 0x3 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_DROP_PIXEL__SHIFT 0x8 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_DROP_PIXEL__SHIFT 0x9 +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_DROP_PIXEL__SHIFT 0xa +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_DROP_PIXEL__SHIFT 0xb +#define OTG_ADD_DROP_PIXEL_CNTL__OTG_ADD_DROP_PIXEL_DONE__SHIFT 0x1f +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_ADD_PIXEL_MASK 0x00000001L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_ADD_PIXEL_MASK 0x00000002L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_ADD_PIXEL_MASK 0x00000004L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_ADD_PIXEL_MASK 0x00000008L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG0_DROP_PIXEL_MASK 0x00000100L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG1_DROP_PIXEL_MASK 0x00000200L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG2_DROP_PIXEL_MASK 0x00000400L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG3_DROP_PIXEL_MASK 0x00000800L +#define OTG_ADD_DROP_PIXEL_CNTL__OTG_ADD_DROP_PIXEL_DONE_MASK 0x80000000L +//DPREFCLK_CNTL +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL__SHIFT 0x0 +#define DPREFCLK_CNTL__DPREFCLK_SRC_SEL_MASK 0x00000007L +//DCE_VERSION +#define DCE_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define DCE_VERSION__MINOR_VERSION__SHIFT 0x8 +#define DCE_VERSION__MAJOR_VERSION_MASK 0x000000FFL +#define DCE_VERSION__MINOR_VERSION_MASK 0x0000FF00L +//SYMCLK32_SE_CNTL +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN__SHIFT 0x3 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN__SHIFT 0x7 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN__SHIFT 0xb +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN__SHIFT 0xf +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE0_EN_MASK 0x00000008L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE1_EN_MASK 0x00000080L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE2_EN_MASK 0x00000800L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_SE_CNTL__SYMCLK32_SE3_EN_MASK 0x00008000L +//SYMCLK32_LE_CNTL +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL__SHIFT 0x0 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN__SHIFT 0x3 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL__SHIFT 0x4 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN__SHIFT 0x7 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_SRC_SEL__SHIFT 0x8 +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_EN__SHIFT 0xb +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_SRC_SEL__SHIFT 0xc +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_EN__SHIFT 0xf +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_SRC_SEL_MASK 0x00000007L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE0_EN_MASK 0x00000008L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_SRC_SEL_MASK 0x00000070L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE1_EN_MASK 0x00000080L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_SRC_SEL_MASK 0x00000700L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE2_EN_MASK 0x00000800L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_SRC_SEL_MASK 0x00007000L +#define SYMCLK32_LE_CNTL__SYMCLK32_LE3_EN_MASK 0x00008000L +//DTBCLK_P_CNTL +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL__SHIFT 0x0 +#define DTBCLK_P_CNTL__DTBCLK_P0_EN__SHIFT 0x2 +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL__SHIFT 0x3 +#define DTBCLK_P_CNTL__DTBCLK_P1_EN__SHIFT 0x5 +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL__SHIFT 0x6 +#define DTBCLK_P_CNTL__DTBCLK_P2_EN__SHIFT 0x8 +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL__SHIFT 0x9 +#define DTBCLK_P_CNTL__DTBCLK_P3_EN__SHIFT 0xb +#define DTBCLK_P_CNTL__DTBCLK_P0_SRC_SEL_MASK 0x00000003L +#define DTBCLK_P_CNTL__DTBCLK_P0_EN_MASK 0x00000004L +#define DTBCLK_P_CNTL__DTBCLK_P1_SRC_SEL_MASK 0x00000018L +#define DTBCLK_P_CNTL__DTBCLK_P1_EN_MASK 0x00000020L +#define DTBCLK_P_CNTL__DTBCLK_P2_SRC_SEL_MASK 0x000000C0L +#define DTBCLK_P_CNTL__DTBCLK_P2_EN_MASK 0x00000100L +#define DTBCLK_P_CNTL__DTBCLK_P3_SRC_SEL_MASK 0x00000600L +#define DTBCLK_P_CNTL__DTBCLK_P3_EN_MASK 0x00000800L +//DCCG_GATE_DISABLE_CNTL5 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE__SHIFT 0x7 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL5__DTBCLK_P3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_ROOT_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK0_GATE_DISABLE_MASK 0x00000080L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK2_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_ROOT_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL5__DPSTREAMCLK3_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_ROOT_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_ROOT_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_ROOT_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_ROOT_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_ROOT_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKA_FE_ROOT_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKB_FE_ROOT_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKC_FE_ROOT_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKD_FE_ROOT_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL5__SYMCLKE_FE_ROOT_GATE_DISABLE_MASK 0x10000000L +//DSCCLK0_DTO_PARAM +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE__SHIFT 0x0 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO__SHIFT 0x10 +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK0_DTO_PARAM__DSCCLK0_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK1_DTO_PARAM +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE__SHIFT 0x0 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO__SHIFT 0x10 +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK1_DTO_PARAM__DSCCLK1_DTO_MODULO_MASK 0x00FF0000L +//DSCCLK2_DTO_PARAM +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE__SHIFT 0x0 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO__SHIFT 0x10 +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_PHASE_MASK 0x000000FFL +#define DSCCLK2_DTO_PARAM__DSCCLK2_DTO_MODULO_MASK 0x00FF0000L +//OTG_PIXEL_RATE_DIV +#define OTG_PIXEL_RATE_DIV__OTG0_TMDS_PIXEL_RATE_DIV__SHIFT 0x0 +#define OTG_PIXEL_RATE_DIV__DPDTO0_INT__SHIFT 0x1 +#define OTG_PIXEL_RATE_DIV__OTG1_TMDS_PIXEL_RATE_DIV__SHIFT 0x5 +#define OTG_PIXEL_RATE_DIV__DPDTO1_INT__SHIFT 0x6 +#define OTG_PIXEL_RATE_DIV__OTG2_TMDS_PIXEL_RATE_DIV__SHIFT 0xa +#define OTG_PIXEL_RATE_DIV__DPDTO2_INT__SHIFT 0xb +#define OTG_PIXEL_RATE_DIV__OTG3_TMDS_PIXEL_RATE_DIV__SHIFT 0xf +#define OTG_PIXEL_RATE_DIV__DPDTO3_INT__SHIFT 0x10 +#define OTG_PIXEL_RATE_DIV__OTG0_TMDS_PIXEL_RATE_DIV_MASK 0x00000001L +#define OTG_PIXEL_RATE_DIV__DPDTO0_INT_MASK 0x0000001EL +#define OTG_PIXEL_RATE_DIV__OTG1_TMDS_PIXEL_RATE_DIV_MASK 0x00000020L +#define OTG_PIXEL_RATE_DIV__DPDTO1_INT_MASK 0x000003C0L +#define OTG_PIXEL_RATE_DIV__OTG2_TMDS_PIXEL_RATE_DIV_MASK 0x00000400L +#define OTG_PIXEL_RATE_DIV__DPDTO2_INT_MASK 0x00007800L +#define OTG_PIXEL_RATE_DIV__OTG3_TMDS_PIXEL_RATE_DIV_MASK 0x00008000L +#define OTG_PIXEL_RATE_DIV__DPDTO3_INT_MASK 0x000F0000L +//MILLISECOND_TIME_BASE_DIV +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001FFFFL +#define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DISPCLK_FREQ_CHANGE_CNTL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x0 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x10 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x14 +#define DISPCLK_FREQ_CHANGE_CNTL__RESYNC_FIFO_LEVEL_ADJUST_EN__SHIFT 0x15 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x16 +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x18 +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x1d +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x1e +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x1f +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003FFFL +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000F0000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L +#define DISPCLK_FREQ_CHANGE_CNTL__RESYNC_FIFO_LEVEL_ADJUST_EN_MASK 0x00200000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x00400000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x1F000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L +#define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L +//DC_MEM_GLOBAL_PWR_REQ_CNTL +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define DC_MEM_GLOBAL_PWR_REQ_CNTL__DC_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//DCCG_PERFMON_CNTL +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x0 +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x1 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE__SHIFT 0x2 +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE__SHIFT 0x3 +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x4 +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x5 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x6 +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x7 +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL__SHIFT 0x8 +#define DCCG_PERFMON_CNTL__DCCG_PERF_TEST_CLK_ENABLE__SHIFT 0xb +#define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L +#define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYA_PIXCLK_ENABLE_MASK 0x00000004L +#define DCCG_PERFMON_CNTL__DCCG_PERF_UNIPHYB_PIXCLK_ENABLE_MASK 0x00000008L +#define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L +#define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L +#define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L +#define DCCG_PERFMON_CNTL__DCCG_PERF_OTG_SEL_MASK 0x00000700L +#define DCCG_PERFMON_CNTL__DCCG_PERF_TEST_CLK_ENABLE_MASK 0x00000800L +//DCCG_GATE_DISABLE_CNTL +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE__SHIFT 0x1d +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE__SHIFT 0x1e +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL__SOCCLK_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL__DPREFCLK_R_DCCG_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL__DSCCLK_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK0_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK1_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL__AOMCLK2_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL__REFCLK_R_DIG_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL__DSICLK_GATE_DISABLE_MASK 0x10000000L +#define DCCG_GATE_DISABLE_CNTL__BYTECLK_GATE_DISABLE_MASK 0x20000000L +#define DCCG_GATE_DISABLE_CNTL__ESCCLK_GATE_DISABLE_MASK 0x40000000L +//DISPCLK_CGTT_BLK_CTRL_REG +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//SOCCLK_CGTT_BLK_CTRL_REG +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SOCCLK_CGTT_BLK_CTRL_REG__SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_CAC_STATUS +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x0 +#define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xFFFFFFFFL +//MICROSECOND_TIME_BASE_DIV +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x8 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x10 +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x11 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x14 +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007F00L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L +#define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L +#define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L +//DCCG_GATE_DISABLE_CNTL2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE__SHIFT 0x6 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE__SHIFT 0x10 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE__SHIFT 0x11 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE__SHIFT 0x12 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE__SHIFT 0x13 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE__SHIFT 0x1c +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_FE_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_FE_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_FE_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_FE_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_FE_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_FE_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_FE_GATE_DISABLE_MASK 0x00000040L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK1_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK3_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK4_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK5_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKA_GATE_DISABLE_MASK 0x00010000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKB_GATE_DISABLE_MASK 0x00020000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKC_GATE_DISABLE_MASK 0x00040000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKD_GATE_DISABLE_MASK 0x00080000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKE_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKF_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL2__SYMCLKG_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL2__PHYASYMCLK_ROOT_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYBSYMCLK_ROOT_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYCSYMCLK_ROOT_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYDSYMCLK_ROOT_GATE_DISABLE_MASK 0x08000000L +#define DCCG_GATE_DISABLE_CNTL2__PHYESYMCLK_ROOT_GATE_DISABLE_MASK 0x10000000L +//SYMCLK_CGTT_BLK_CTRL_REG +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY__SHIFT 0x0 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define SYMCLK_CGTT_BLK_CTRL_REG__SYMCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DCCG_DISP_CNTL_REG +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ__SHIFT 0x8 +#define DCCG_DISP_CNTL_REG__ALLOW_SR_ON_TRANS_REQ_MASK 0x00000100L +//OTG0_PIXEL_RATE_CNTL +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x4 +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE__SHIFT 0x5 +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS__SHIFT 0x7 +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL__SHIFT 0xc +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG0_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L +#define OTG0_PIXEL_RATE_CNTL__DP_DTO0_DS_DISABLE_MASK 0x00000020L +#define OTG0_PIXEL_RATE_CNTL__DPDTO0_ENABLE_STATUS_MASK 0x00000080L +#define OTG0_PIXEL_RATE_CNTL__PIPE0_DTO_SRC_SEL_MASK 0x00001000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG0_PIXEL_RATE_CNTL__OTG0_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO0_PHASE +#define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x0 +#define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xFFFFFFFFL +//DP_DTO0_MODULO +#define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x0 +#define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xFFFFFFFFL +//OTG0_PHYPLL_PIXEL_RATE_CNTL +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG0_PHYPLL_PIXEL_RATE_CNTL__OTG0_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG1_PIXEL_RATE_CNTL +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x4 +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE__SHIFT 0x5 +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS__SHIFT 0x7 +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL__SHIFT 0xc +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG1_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L +#define OTG1_PIXEL_RATE_CNTL__DP_DTO1_DS_DISABLE_MASK 0x00000020L +#define OTG1_PIXEL_RATE_CNTL__DPDTO1_ENABLE_STATUS_MASK 0x00000080L +#define OTG1_PIXEL_RATE_CNTL__PIPE1_DTO_SRC_SEL_MASK 0x00001000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG1_PIXEL_RATE_CNTL__OTG1_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO1_PHASE +#define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x0 +#define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xFFFFFFFFL +//DP_DTO1_MODULO +#define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x0 +#define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xFFFFFFFFL +//OTG1_PHYPLL_PIXEL_RATE_CNTL +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG1_PHYPLL_PIXEL_RATE_CNTL__OTG1_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG2_PIXEL_RATE_CNTL +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x4 +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE__SHIFT 0x5 +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS__SHIFT 0x7 +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL__SHIFT 0xc +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG2_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L +#define OTG2_PIXEL_RATE_CNTL__DP_DTO2_DS_DISABLE_MASK 0x00000020L +#define OTG2_PIXEL_RATE_CNTL__DPDTO2_ENABLE_STATUS_MASK 0x00000080L +#define OTG2_PIXEL_RATE_CNTL__PIPE2_DTO_SRC_SEL_MASK 0x00001000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG2_PIXEL_RATE_CNTL__OTG2_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO2_PHASE +#define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x0 +#define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xFFFFFFFFL +//DP_DTO2_MODULO +#define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x0 +#define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xFFFFFFFFL +//OTG2_PHYPLL_PIXEL_RATE_CNTL +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG2_PHYPLL_PIXEL_RATE_CNTL__OTG2_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//OTG3_PIXEL_RATE_CNTL +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x4 +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE__SHIFT 0x5 +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS__SHIFT 0x7 +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL__SHIFT 0xc +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR__SHIFT 0xe +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT__SHIFT 0x10 +#define OTG3_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_SOURCE_MASK 0x00000003L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L +#define OTG3_PIXEL_RATE_CNTL__DP_DTO3_DS_DISABLE_MASK 0x00000020L +#define OTG3_PIXEL_RATE_CNTL__DPDTO3_ENABLE_STATUS_MASK 0x00000080L +#define OTG3_PIXEL_RATE_CNTL__PIPE3_DTO_SRC_SEL_MASK 0x00001000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_FIFO_ERROR_MASK 0x0000C000L +#define OTG3_PIXEL_RATE_CNTL__OTG3_DIO_ERROR_COUNT_MASK 0x0FFF0000L +//DP_DTO3_PHASE +#define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x0 +#define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xFFFFFFFFL +//DP_DTO3_MODULO +#define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x0 +#define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xFFFFFFFFL +//OTG3_PHYPLL_PIXEL_RATE_CNTL +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE__SHIFT 0x0 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE__SHIFT 0x4 +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PHYPLL_PIXEL_RATE_SOURCE_MASK 0x00000007L +#define OTG3_PHYPLL_PIXEL_RATE_CNTL__OTG3_PIXEL_RATE_PLL_SOURCE_MASK 0x00000010L +//DPPCLK_CGTT_BLK_CTRL_REG +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DPPCLK_CGTT_BLK_CTRL_REG__DPPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DPPCLK0_DTO_PARAM +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE__SHIFT 0x0 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO__SHIFT 0x10 +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK0_DTO_PARAM__DPPCLK0_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK1_DTO_PARAM +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE__SHIFT 0x0 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO__SHIFT 0x10 +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK1_DTO_PARAM__DPPCLK1_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK2_DTO_PARAM +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE__SHIFT 0x0 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO__SHIFT 0x10 +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK2_DTO_PARAM__DPPCLK2_DTO_MODULO_MASK 0x00FF0000L +//DPPCLK3_DTO_PARAM +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE__SHIFT 0x0 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO__SHIFT 0x10 +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_PHASE_MASK 0x000000FFL +#define DPPCLK3_DTO_PARAM__DPPCLK3_DTO_MODULO_MASK 0x00FF0000L +//DCCG_CAC_STATUS2 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2__SHIFT 0x0 +#define DCCG_CAC_STATUS2__CAC_STATUS_RDDATA2_MASK 0x0007FFFFL +//SYMCLKA_CLOCK_ENABLE +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN__SHIFT 0x4 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL__SHIFT 0x5 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_EN_MASK 0x00000010L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_SRC_SEL_MASK 0x000000E0L +#define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKB_CLOCK_ENABLE +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN__SHIFT 0x4 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL__SHIFT 0x5 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_EN_MASK 0x00000010L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_SRC_SEL_MASK 0x000000E0L +#define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKC_CLOCK_ENABLE +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN__SHIFT 0x4 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL__SHIFT 0x5 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_EN_MASK 0x00000010L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_SRC_SEL_MASK 0x000000E0L +#define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKD_CLOCK_ENABLE +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN__SHIFT 0x4 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL__SHIFT 0x5 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_EN_MASK 0x00000010L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_SRC_SEL_MASK 0x000000E0L +#define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_SRC_SEL_MASK 0x00000700L +//SYMCLKE_CLOCK_ENABLE +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x0 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN__SHIFT 0x4 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL__SHIFT 0x5 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL__SHIFT 0x8 +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_EN_MASK 0x00000010L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_SRC_SEL_MASK 0x000000E0L +#define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_SRC_SEL_MASK 0x00000700L +//DCCG_SOFT_RESET +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x0 +#define DCCG_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x2 +#define DCCG_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x3 +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET__SHIFT 0x4 +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET__SHIFT 0x8 +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET__SHIFT 0xc +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET__SHIFT 0xd +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET__SHIFT 0xe +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET__SHIFT 0xf +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET__SHIFT 0x10 +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET__SHIFT 0x11 +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET__SHIFT 0x12 +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET__SHIFT 0x13 +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET__SHIFT 0x14 +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET__SHIFT 0x15 +#define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L +#define DCCG_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L +#define DCCG_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L +#define DCCG_SOFT_RESET__AUDIO_DTO2_CLK_SOFT_RESET_MASK 0x00000010L +#define DCCG_SOFT_RESET__DPREFCLK_SOFT_RESET_MASK 0x00000100L +#define DCCG_SOFT_RESET__AMCLK0_SOFT_RESET_MASK 0x00001000L +#define DCCG_SOFT_RESET__AMCLK1_SOFT_RESET_MASK 0x00002000L +#define DCCG_SOFT_RESET__P0PLL_CFG_IF_SOFT_RESET_MASK 0x00004000L +#define DCCG_SOFT_RESET__P1PLL_CFG_IF_SOFT_RESET_MASK 0x00008000L +#define DCCG_SOFT_RESET__P2PLL_CFG_IF_SOFT_RESET_MASK 0x00010000L +#define DCCG_SOFT_RESET__A0PLL_CFG_IF_SOFT_RESET_MASK 0x00020000L +#define DCCG_SOFT_RESET__A1PLL_CFG_IF_SOFT_RESET_MASK 0x00040000L +#define DCCG_SOFT_RESET__C0PLL_CFG_IF_SOFT_RESET_MASK 0x00080000L +#define DCCG_SOFT_RESET__C1PLL_CFG_IF_SOFT_RESET_MASK 0x00100000L +#define DCCG_SOFT_RESET__C2PLL_CFG_IF_SOFT_RESET_MASK 0x00200000L +//DSCCLK_DTO_CTRL +#define DSCCLK_DTO_CTRL__DSCCLK0_EN__SHIFT 0x0 +#define DSCCLK_DTO_CTRL__DSCCLK1_EN__SHIFT 0x1 +#define DSCCLK_DTO_CTRL__DSCCLK2_EN__SHIFT 0x2 +#define DSCCLK_DTO_CTRL__DSCCLK3_EN__SHIFT 0x3 +#define DSCCLK_DTO_CTRL__DSCCLK4_EN__SHIFT 0x4 +#define DSCCLK_DTO_CTRL__DSCCLK5_EN__SHIFT 0x5 +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN__SHIFT 0x8 +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN__SHIFT 0x9 +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN__SHIFT 0xb +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN__SHIFT 0xc +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN__SHIFT 0xd +#define DSCCLK_DTO_CTRL__DSCCLK0_EN_MASK 0x00000001L +#define DSCCLK_DTO_CTRL__DSCCLK1_EN_MASK 0x00000002L +#define DSCCLK_DTO_CTRL__DSCCLK2_EN_MASK 0x00000004L +#define DSCCLK_DTO_CTRL__DSCCLK3_EN_MASK 0x00000008L +#define DSCCLK_DTO_CTRL__DSCCLK4_EN_MASK 0x00000010L +#define DSCCLK_DTO_CTRL__DSCCLK5_EN_MASK 0x00000020L +#define DSCCLK_DTO_CTRL__DSCCLK0_DTO_DB_EN_MASK 0x00000100L +#define DSCCLK_DTO_CTRL__DSCCLK1_DTO_DB_EN_MASK 0x00000200L +#define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN_MASK 0x00000400L +#define DSCCLK_DTO_CTRL__DSCCLK3_DTO_DB_EN_MASK 0x00000800L +#define DSCCLK_DTO_CTRL__DSCCLK4_DTO_DB_EN_MASK 0x00001000L +#define DSCCLK_DTO_CTRL__DSCCLK5_DTO_DB_EN_MASK 0x00002000L +//DPPCLK_CTRL +#define DPPCLK_CTRL__DPPCLK0_EN__SHIFT 0x0 +#define DPPCLK_CTRL__DPPCLK1_EN__SHIFT 0x3 +#define DPPCLK_CTRL__DPPCLK2_EN__SHIFT 0x6 +#define DPPCLK_CTRL__DPPCLK3_EN__SHIFT 0x9 +#define DPPCLK_CTRL__DPPCLK0_EN_MASK 0x00000001L +#define DPPCLK_CTRL__DPPCLK1_EN_MASK 0x00000008L +#define DPPCLK_CTRL__DPPCLK2_EN_MASK 0x00000040L +#define DPPCLK_CTRL__DPPCLK3_EN_MASK 0x00000200L +//DCCG_GATE_DISABLE_CNTL6 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL6__DPREFCLK_DIO_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK0_ROOT_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK1_ROOT_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK2_ROOT_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL6__DPPCLK3_ROOT_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK0_ROOT_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK1_ROOT_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK2_ROOT_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL6__DSCCLK3_ROOT_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL6__HDMISTREAMCLK0_ROOT_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL6__DPREFCLK_DIO_GATE_DISABLE_MASK 0x01000000L +//SYMCLK_PSP_CNTL +#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON__SHIFT 0x0 +#define SYMCLK_PSP_CNTL__SYMCLK_PSP_FORCE_ON_MASK 0x00000001L +//DCCG_AUDIO_DTO_SOURCE +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x0 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x4 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO__SHIFT 0x14 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO__SHIFT 0x18 +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO__SHIFT 0x1c +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000030L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO2_USE_512FBR_DTO_MASK 0x00100000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_USE_512FBR_DTO_MASK 0x01000000L +#define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO1_USE_512FBR_DTO_MASK 0x10000000L +//DCCG_AUDIO_DTO0_PHASE +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO0_MODULE +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_PHASE +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xFFFFFFFFL +//DCCG_AUDIO_DTO1_MODULE +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x0 +#define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG0_LATCH_VALUE +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG0_LATCH_VALUE__DCCG_VSYNC_CNT_OTG0_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG1_LATCH_VALUE +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG1_LATCH_VALUE__DCCG_VSYNC_CNT_OTG1_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG2_LATCH_VALUE +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG2_LATCH_VALUE__DCCG_VSYNC_CNT_OTG2_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG3_LATCH_VALUE +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG3_LATCH_VALUE__DCCG_VSYNC_CNT_OTG3_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG4_LATCH_VALUE +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG4_LATCH_VALUE__DCCG_VSYNC_CNT_OTG4_LATCH_VALUE_MASK 0xFFFFFFFFL +//DCCG_VSYNC_OTG5_LATCH_VALUE +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE__SHIFT 0x0 +#define DCCG_VSYNC_OTG5_LATCH_VALUE__DCCG_VSYNC_CNT_OTG5_LATCH_VALUE_MASK 0xFFFFFFFFL +//DPPCLK_DTO_CTRL +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN__SHIFT 0x1 +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN__SHIFT 0x5 +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN__SHIFT 0x9 +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN__SHIFT 0xd +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN__SHIFT 0x11 +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN__SHIFT 0x15 +#define DPPCLK_DTO_CTRL__DPPCLK0_DTO_DB_EN_MASK 0x00000002L +#define DPPCLK_DTO_CTRL__DPPCLK1_DTO_DB_EN_MASK 0x00000020L +#define DPPCLK_DTO_CTRL__DPPCLK2_DTO_DB_EN_MASK 0x00000200L +#define DPPCLK_DTO_CTRL__DPPCLK3_DTO_DB_EN_MASK 0x00002000L +#define DPPCLK_DTO_CTRL__DPPCLK4_DTO_DB_EN_MASK 0x00020000L +#define DPPCLK_DTO_CTRL__DPPCLK5_DTO_DB_EN_MASK 0x00200000L +//DCCG_VSYNC_CNT_CTRL +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE__SHIFT 0x0 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET__SHIFT 0x2 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL__SHIFT 0x3 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL__SHIFT 0x4 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT__SHIFT 0x8 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN__SHIFT 0x10 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN__SHIFT 0x11 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN__SHIFT 0x12 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN__SHIFT 0x13 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN__SHIFT 0x14 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN__SHIFT 0x15 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL__SHIFT 0x18 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL__SHIFT 0x19 +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL__SHIFT 0x1a +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL__SHIFT 0x1b +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL__SHIFT 0x1c +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL__SHIFT 0x1d +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_ENABLE_MASK 0x00000001L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_SW_RESET_MASK 0x00000004L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_RESET_SEL_MASK 0x00000008L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_EXT_TRIG_SEL_MASK 0x000000F0L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_CNT_FRAME_CNT_MASK 0x00000F00L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_LATCH_EN_MASK 0x00010000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_LATCH_EN_MASK 0x00020000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_LATCH_EN_MASK 0x00040000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_LATCH_EN_MASK 0x00080000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_LATCH_EN_MASK 0x00100000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_LATCH_EN_MASK 0x00200000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG0_VSYNC_TRIG_SEL_MASK 0x01000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG1_VSYNC_TRIG_SEL_MASK 0x02000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG2_VSYNC_TRIG_SEL_MASK 0x04000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG3_VSYNC_TRIG_SEL_MASK 0x08000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG4_VSYNC_TRIG_SEL_MASK 0x10000000L +#define DCCG_VSYNC_CNT_CTRL__DCCG_VSYNC_OTG5_VSYNC_TRIG_SEL_MASK 0x20000000L +//DCCG_VSYNC_CNT_INT_CTRL +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT__SHIFT 0x0 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT__SHIFT 0x1 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT__SHIFT 0x2 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT__SHIFT 0x3 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT__SHIFT 0x4 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT__SHIFT 0x5 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR__SHIFT 0x8 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR__SHIFT 0x9 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR__SHIFT 0xa +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR__SHIFT 0xb +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR__SHIFT 0xc +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR__SHIFT 0xd +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK__SHIFT 0x10 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK__SHIFT 0x11 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0x12 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK__SHIFT 0x13 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK__SHIFT 0x14 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK__SHIFT 0x15 +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_MASK 0x00000001L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_MASK 0x00000002L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_MASK 0x00000004L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_MASK 0x00000008L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_MASK 0x00000010L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_MASK 0x00000020L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_INTERRUPT_CLEAR_MASK 0x00000100L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_INTERRUPT_CLEAR_MASK 0x00000200L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_INTERRUPT_CLEAR_MASK 0x00000400L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_INTERRUPT_CLEAR_MASK 0x00000800L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_INTERRUPT_CLEAR_MASK 0x00001000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_INTERRUPT_CLEAR_MASK 0x00002000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG0_LATCH_MASK_MASK 0x00010000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG1_LATCH_MASK_MASK 0x00020000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK_MASK 0x00040000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG3_LATCH_MASK_MASK 0x00080000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG4_LATCH_MASK_MASK 0x00100000L +#define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG5_LATCH_MASK_MASK 0x00200000L +//FORCE_SYMCLK_DISABLE +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE__SHIFT 0x0 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE__SHIFT 0x1 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE__SHIFT 0x2 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE__SHIFT 0x3 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE__SHIFT 0x4 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE__SHIFT 0x5 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE__SHIFT 0x6 +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKA_DISABLE_MASK 0x00000001L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKB_DISABLE_MASK 0x00000002L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKC_DISABLE_MASK 0x00000004L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKD_DISABLE_MASK 0x00000008L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKE_DISABLE_MASK 0x00000010L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKF_DISABLE_MASK 0x00000020L +#define FORCE_SYMCLK_DISABLE__FORCE_SYMCLKG_DISABLE_MASK 0x00000040L +//DCCG_TEST_CLK_SEL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x0 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_OR_DATA_GENERICA__SHIFT 0x9 +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0xc +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL__SHIFT 0xe +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000001FFL +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_OR_DATA_GENERICA_MASK 0x00000200L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00001000L +#define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_DIV_SEL_MASK 0x0000C000L +//HDMICHARCLK0_CLOCK_CNTL +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN__SHIFT 0x0 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL__SHIFT 0x4 +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_EN_MASK 0x00000001L +#define HDMICHARCLK0_CLOCK_CNTL__HDMICHARCLK0_SRC_SEL_MASK 0x00000070L +//PHYASYMCLK_CLOCK_CNTL +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN__SHIFT 0x0 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_EN_MASK 0x00000001L +#define PHYASYMCLK_CLOCK_CNTL__PHYASYMCLK_SRC_SEL_MASK 0x00000030L +//PHYBSYMCLK_CLOCK_CNTL +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN__SHIFT 0x0 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_EN_MASK 0x00000001L +#define PHYBSYMCLK_CLOCK_CNTL__PHYBSYMCLK_SRC_SEL_MASK 0x00000030L +//PHYCSYMCLK_CLOCK_CNTL +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN__SHIFT 0x0 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_EN_MASK 0x00000001L +#define PHYCSYMCLK_CLOCK_CNTL__PHYCSYMCLK_SRC_SEL_MASK 0x00000030L +//PHYDSYMCLK_CLOCK_CNTL +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN__SHIFT 0x0 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_EN_MASK 0x00000001L +#define PHYDSYMCLK_CLOCK_CNTL__PHYDSYMCLK_SRC_SEL_MASK 0x00000030L +//PHYESYMCLK_CLOCK_CNTL +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN__SHIFT 0x0 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL__SHIFT 0x4 +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_EN_MASK 0x00000001L +#define PHYESYMCLK_CLOCK_CNTL__PHYESYMCLK_SRC_SEL_MASK 0x00000030L +//HDMISTREAMCLK_CNTL +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL__SHIFT 0x0 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN__SHIFT 0x3 +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_SRC_SEL_MASK 0x00000007L +#define HDMISTREAMCLK_CNTL__HDMISTREAMCLK0_EN_MASK 0x00000008L +//DCCG_GATE_DISABLE_CNTL3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE__SHIFT 0x0 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE__SHIFT 0x1 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE__SHIFT 0x2 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE__SHIFT 0x3 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE__SHIFT 0x4 +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE__SHIFT 0x5 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE__SHIFT 0x8 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE__SHIFT 0x9 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE__SHIFT 0xb +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE__SHIFT 0xc +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE__SHIFT 0xd +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE__SHIFT 0xe +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE__SHIFT 0xf +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE__SHIFT 0x14 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE__SHIFT 0x15 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE__SHIFT 0x16 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE__SHIFT 0x17 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE2_GATE_DISABLE__SHIFT 0x18 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE2_GATE_DISABLE__SHIFT 0x19 +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE3_GATE_DISABLE__SHIFT 0x1a +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE3_GATE_DISABLE__SHIFT 0x1b +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK0_GATE_DISABLE_MASK 0x00000001L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK1_GATE_DISABLE_MASK 0x00000002L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK2_GATE_DISABLE_MASK 0x00000004L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK3_GATE_DISABLE_MASK 0x00000008L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK4_GATE_DISABLE_MASK 0x00000010L +#define DCCG_GATE_DISABLE_CNTL3__HDMISTREAMCLK5_GATE_DISABLE_MASK 0x00000020L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE0_GATE_DISABLE_MASK 0x00000100L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE0_GATE_DISABLE_MASK 0x00000200L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE_MASK 0x00000400L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE1_GATE_DISABLE_MASK 0x00000800L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE2_GATE_DISABLE_MASK 0x00001000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE2_GATE_DISABLE_MASK 0x00002000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE3_GATE_DISABLE_MASK 0x00004000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_SE3_GATE_DISABLE_MASK 0x00008000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE0_GATE_DISABLE_MASK 0x00100000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK 0x00200000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK 0x00400000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK 0x00800000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE2_GATE_DISABLE_MASK 0x01000000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE2_GATE_DISABLE_MASK 0x02000000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE3_GATE_DISABLE_MASK 0x04000000L +#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE3_GATE_DISABLE_MASK 0x08000000L +//HDMISTREAMCLK0_DTO_PARAM +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT 0x0 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT 0x8 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT 0x10 +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK 0x000000FFL +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK 0x0000FF00L +#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK 0x00010000L +//DPIACLK_810M_DTO_PHASE +#define DPIACLK_810M_DTO_PHASE__DPIACLK_810M_DTO_PHASE__SHIFT 0x0 +#define DPIACLK_810M_DTO_PHASE__DPIACLK_810M_DTO_PHASE_MASK 0xFFFFFFFFL +//DPIACLK_540M_DTO_PHASE +#define DPIACLK_540M_DTO_PHASE__DPIACLK_540M_DTO_PHASE__SHIFT 0x0 +#define DPIACLK_540M_DTO_PHASE__DPIACLK_540M_DTO_PHASE_MASK 0xFFFFFFFFL +//DPIACLK_DTO_CNTL +#define DPIACLK_DTO_CNTL__DPIACLK_810M_DTO_ENABLE__SHIFT 0x0 +#define DPIACLK_DTO_CNTL__DPIACLK_540M_DTO_ENABLE__SHIFT 0x1 +#define DPIACLK_DTO_CNTL__DPIACLK_810M_DTO_ENABLE_MASK 0x00000001L +#define DPIACLK_DTO_CNTL__DPIACLK_540M_DTO_ENABLE_MASK 0x00000002L +//DPIACLK_810M_DTO_MODULO +#define DPIACLK_810M_DTO_MODULO__DPIACLK_810M_DTO_MODULO__SHIFT 0x0 +#define DPIACLK_810M_DTO_MODULO__DPIACLK_810M_DTO_MODULO_MASK 0xFFFFFFFFL +//DPIACLK_540M_DTO_MODULO +#define DPIACLK_540M_DTO_MODULO__DPIACLK_540M_DTO_MODULO__SHIFT 0x0 +#define DPIACLK_540M_DTO_MODULO__DPIACLK_540M_DTO_MODULO_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dfs_dispdec +//DENTIST_DISPCLK_CNTL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG_MASK 0x00200000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG_MASK 0x00400000L +#define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L + + +// addressBlock: azroot_f2codecind +//AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L + + +// addressBlock: azendpoint_f2codecind +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0xf +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007FL +//AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L +#define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L +//AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000FFL +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L +//AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007FL +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000FC00L +//AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LFE_PLAYBACK_LEVEL_MASK 0x00000003L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_INDEX_MASK 0x0000003FL +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__SUPPORTS_AI_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_INDEX__ACP_PACKET_ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_ACP_DATA__ACP_DATA_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xFF000000L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000FFL +#define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003CL +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000F0L +//AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x0 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x4 +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000FL +#define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000F0L +//AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS__OUTPUT_ACTIVE_MASK 0x00000001L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE__CODING_TYPE_MASK 0x000000FFL +//AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGED_ACK_UR_ENABLE_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_REASON_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED__FORMAT_CHANGE_RESPONSE_MASK 0x00FF0000L +//AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION__WIRELESS_DISPLAY_IDENTIFICATION_MASK 0x00000003L +//AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE__REMOTE_KEEP_ALIVE_CAPABILITY_MASK 0x00000010L +//AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L +//AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x0 +#define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xFFFFFFFFL + + +// addressBlock: azinputendpoint_f2codecind +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0xf +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x17 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007F00L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL__IN_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7FFFFFFFL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0xc +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x1e +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000F0L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000F00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000F000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00F00000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3F000000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xC0000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003FL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000C0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000FFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE__MULTICHANNEL0_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE__MULTICHANNEL2_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE__MULTICHANNEL4_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE__MULTICHANNEL6_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000F0L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__LPIB_SNAPSHOT_LOCK_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL__CYCLIC_BUFFER_WRAP_COUNT_MASK 0x0000FF00L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB__LPIB_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT__LPIB_TIMER_SNAPSHOT_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__CHANNEL_LAYOUT_MASK 0x00000006L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_ACTIVITY_UR_ENABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL__INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE_MASK 0x00000020L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID__SHIFT 0x1f +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__CHANNEL_ALLOCATION_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_BYTE_5_MASK 0x00FF0000L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME__INFOFRAME_VALID_MASK 0x80000000L +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L__CHANNEL_STATUS_L_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H__CHANNEL_STATUS_H_MASK 0xFFFFFFFFL +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x9 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0xb +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x14 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000F0000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00F00000L +//AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x0 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x1 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x2 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x3 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x4 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x5 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x6 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x7 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x8 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x10 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x18 +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000FF00L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L +#define AZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec +//DC_PERFMON0_PERFCOUNTER_CNTL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_CNTL2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON0_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFCOUNTER_STATE +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON0_PERFMON_CNTL +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON0_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON0_PERFMON_CNTL2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON0_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON0_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON0_PERFMON_CVALUE_LOW +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON0_PERFMON_HI +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON0_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON0_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON0_PERFMON_LOW +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON0_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec +//DC_PERFMON1_PERFCOUNTER_CNTL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_CNTL2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON1_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFCOUNTER_STATE +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON1_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON1_PERFMON_CNTL +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON1_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON1_PERFMON_CNTL2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON1_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON1_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON1_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON1_PERFMON_CVALUE_LOW +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON1_PERFMON_HI +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON1_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON1_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON1_PERFMON_LOW +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON1_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dc_pg_dispdec +//DOMAIN0_PG_CONFIG +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN0_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN0_PG_STATUS +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN0_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN0_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN1_PG_CONFIG +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN1_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN1_PG_STATUS +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN1_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN1_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN2_PG_CONFIG +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN2_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN2_PG_STATUS +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN2_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN2_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN3_PG_CONFIG +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN3_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN3_PG_STATUS +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN3_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN3_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN16_PG_CONFIG +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN16_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN16_PG_STATUS +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN16_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN16_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN17_PG_CONFIG +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN17_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN17_PG_STATUS +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN17_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN17_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN18_PG_CONFIG +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN18_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN18_PG_STATUS +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN18_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN18_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN19_PG_CONFIG +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN19_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN19_PG_STATUS +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN19_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN19_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN22_PG_CONFIG +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN22_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN22_PG_STATUS +#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN22_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN22_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN23_PG_CONFIG +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN23_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN23_PG_STATUS +#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN23_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN23_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN24_PG_CONFIG +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN24_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN24_PG_STATUS +#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN24_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN24_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN25_PG_CONFIG +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN25_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN25_PG_STATUS +#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN25_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN25_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DOMAIN26_PG_CONFIG +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_FORCEON__SHIFT 0x0 +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_GATE__SHIFT 0x8 +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_FORCEON_MASK 0x00000001L +#define DOMAIN26_PG_CONFIG__DOMAIN_POWER_GATE_MASK 0x00000100L +//DOMAIN26_PG_STATUS +#define DOMAIN26_PG_STATUS__DOMAIN_DESIRED_PWR_STATE__SHIFT 0x1c +#define DOMAIN26_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS__SHIFT 0x1e +#define DOMAIN26_PG_STATUS__DOMAIN_DESIRED_PWR_STATE_MASK 0x10000000L +#define DOMAIN26_PG_STATUS__DOMAIN_PGFSM_PWR_STATUS_MASK 0xC0000000L +//DCPG_INTERRUPT_STATUS +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS__DOMAIN0_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS__DOMAIN1_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS__DOMAIN2_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS__DOMAIN3_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN16_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN17_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN18_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_2__DOMAIN19_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +//DCPG_INTERRUPT_STATUS_3 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED__SHIFT 0x0 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED__SHIFT 0x1 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED__SHIFT 0x2 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED__SHIFT 0x3 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED__SHIFT 0x4 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED__SHIFT 0x5 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED__SHIFT 0x6 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED__SHIFT 0x7 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_UP_INT_OCCURRED__SHIFT 0x8 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_DOWN_INT_OCCURRED__SHIFT 0x9 +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_UP_INT_OCCURRED_MASK 0x00000001L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN22_POWER_DOWN_INT_OCCURRED_MASK 0x00000002L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_UP_INT_OCCURRED_MASK 0x00000004L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN23_POWER_DOWN_INT_OCCURRED_MASK 0x00000008L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_UP_INT_OCCURRED_MASK 0x00000010L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN24_POWER_DOWN_INT_OCCURRED_MASK 0x00000020L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_UP_INT_OCCURRED_MASK 0x00000040L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN25_POWER_DOWN_INT_OCCURRED_MASK 0x00000080L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_UP_INT_OCCURRED_MASK 0x00000100L +#define DCPG_INTERRUPT_STATUS_3__DOMAIN26_POWER_DOWN_INT_OCCURRED_MASK 0x00000200L +//DCPG_INTERRUPT_CONTROL_1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN0_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN1_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN2_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_1__DOMAIN3_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN16_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN17_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN18_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_2__DOMAIN19_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +//DCPG_INTERRUPT_CONTROL_3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK__SHIFT 0x0 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR__SHIFT 0x1 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK__SHIFT 0x2 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR__SHIFT 0x3 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK__SHIFT 0x4 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR__SHIFT 0x5 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK__SHIFT 0x6 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR__SHIFT 0x7 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK__SHIFT 0x8 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR__SHIFT 0x9 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK__SHIFT 0xa +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR__SHIFT 0xb +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK__SHIFT 0xc +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR__SHIFT 0xd +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK__SHIFT 0xe +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR__SHIFT 0xf +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_MASK__SHIFT 0x10 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_CLEAR__SHIFT 0x11 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_MASK__SHIFT 0x12 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_CLEAR__SHIFT 0x13 +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_MASK_MASK 0x00000001L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_UP_INT_CLEAR_MASK 0x00000002L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_MASK_MASK 0x00000004L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN22_POWER_DOWN_INT_CLEAR_MASK 0x00000008L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_MASK_MASK 0x00000010L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_UP_INT_CLEAR_MASK 0x00000020L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_MASK_MASK 0x00000040L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN23_POWER_DOWN_INT_CLEAR_MASK 0x00000080L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_MASK_MASK 0x00000100L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_UP_INT_CLEAR_MASK 0x00000200L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_MASK_MASK 0x00000400L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN24_POWER_DOWN_INT_CLEAR_MASK 0x00000800L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_MASK_MASK 0x00001000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_UP_INT_CLEAR_MASK 0x00002000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_MASK_MASK 0x00004000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN25_POWER_DOWN_INT_CLEAR_MASK 0x00008000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_MASK_MASK 0x00010000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_UP_INT_CLEAR_MASK 0x00020000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_MASK_MASK 0x00040000L +#define DCPG_INTERRUPT_CONTROL_3__DOMAIN26_POWER_DOWN_INT_CLEAR_MASK 0x00080000L +//DC_IP_REQUEST_CNTL +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN__SHIFT 0x0 +#define DC_IP_REQUEST_CNTL__IP_REQUEST_EN_MASK 0x00000001L +//LONO_MEM_PWR_REQ_CNTL +#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS__SHIFT 0x0 +#define LONO_MEM_PWR_REQ_CNTL__LONO_MEM_PWR_REQ_DIS_MASK 0x00000001L + + +// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON2_PERFCOUNTER_CNTL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_CNTL2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON2_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFCOUNTER_STATE +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON2_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON2_PERFMON_CNTL +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON2_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON2_PERFMON_CNTL2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON2_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON2_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON2_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON2_PERFMON_CVALUE_LOW +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON2_PERFMON_HI +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON2_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON2_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON2_PERFMON_LOW +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON2_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dmu_dmu_misc_dispdec +//CC_DC_PIPE_DIS +#define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x0 +#define CC_DC_PIPE_DIS__DC_FULL_DIS__SHIFT 0xc +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE__SHIFT 0x10 +#define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x000000FFL +#define CC_DC_PIPE_DIS__DC_FULL_DIS_MASK 0x00001000L +#define CC_DC_PIPE_DIS__DC_DMCUB_ENABLE_MASK 0x00010000L +//DMU_CLK_CNTL +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL__SHIFT 0x0 +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS__SHIFT 0x4 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS__SHIFT 0x5 +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON__SHIFT 0x6 +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON__SHIFT 0x7 +#define DMU_CLK_CNTL__RIOMMU_CLK_SEL__SHIFT 0x8 +#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS__SHIFT 0xc +#define DMU_CLK_CNTL__IHC_FGCG_REP_DIS__SHIFT 0xd +#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL__SHIFT 0xe +#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP__SHIFT 0x10 +#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP__SHIFT 0x12 +#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP__SHIFT 0x14 +#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP__SHIFT 0x16 +#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP__SHIFT 0x18 +#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP__SHIFT 0x1a +#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS__SHIFT 0x1c +#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE__SHIFT 0x1d +#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE__SHIFT 0x1e +#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE__SHIFT 0x1f +#define DMU_CLK_CNTL__DMU_TEST_CLK_SEL_MASK 0x0000000FL +#define DMU_CLK_CNTL__DISPCLK_R_DMU_GATE_DIS_MASK 0x00000010L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_GATE_DIS_MASK 0x00000020L +#define DMU_CLK_CNTL__DISPCLK_R_CLOCK_ON_MASK 0x00000040L +#define DMU_CLK_CNTL__DISPCLK_G_RBBMIF_CLOCK_ON_MASK 0x00000080L +#define DMU_CLK_CNTL__RIOMMU_CLK_SEL_MASK 0x00000100L +#define DMU_CLK_CNTL__RBBMIF_FGCG_REP_DIS_MASK 0x00001000L +#define DMU_CLK_CNTL__IHC_FGCG_REP_DIS_MASK 0x00002000L +#define DMU_CLK_CNTL__DMCUB_DMCUBCLK_SRC_SEL_MASK 0x0000C000L +#define DMU_CLK_CNTL__DPREFCLK_ALLOW_DS_CLKSTOP_MASK 0x00030000L +#define DMU_CLK_CNTL__DISPCLK_ALLOW_DS_CLKSTOP_MASK 0x000C0000L +#define DMU_CLK_CNTL__DPPCLK_ALLOW_DS_CLKSTOP_MASK 0x00300000L +#define DMU_CLK_CNTL__DTBCLK_ALLOW_DS_CLKSTOP_MASK 0x00C00000L +#define DMU_CLK_CNTL__DCFCLK_ALLOW_DS_CLKSTOP_MASK 0x03000000L +#define DMU_CLK_CNTL__DPIACLK_ALLOW_DS_CLKSTOP_MASK 0x0C000000L +#define DMU_CLK_CNTL__LONO_FGCG_REP_DIS_MASK 0x10000000L +#define DMU_CLK_CNTL__LONO_DISPCLK_GATE_DISABLE_MASK 0x20000000L +#define DMU_CLK_CNTL__LONO_SOCCLK_GATE_DISABLE_MASK 0x40000000L +#define DMU_CLK_CNTL__LONO_DMCUBCLK_GATE_DISABLE_MASK 0x80000000L +//DMCUB_SMU_INTERRUPT_CNTL +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT__SHIFT 0x0 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG__SHIFT 0x10 +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_INT_MASK 0x00000001L +#define DMCUB_SMU_INTERRUPT_CNTL__DMCUB_SMU_MSG_MASK 0xFFFF0000L +//SMU_INTERRUPT_CONTROL +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE__SHIFT 0x0 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS__SHIFT 0x4 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT__SHIFT 0x10 +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_ENABLE_MASK 0x00000001L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_STATUS_MASK 0x00000010L +#define SMU_INTERRUPT_CONTROL__DC_SMU_INT_EVENT_MASK 0xFFFF0000L +//ZSC_CNTL +#define ZSC_CNTL__FORCE_SOC_ACCESS__SHIFT 0x0 +#define ZSC_CNTL__LONO_PWR_DN__SHIFT 0x8 +#define ZSC_CNTL__FORCE_SOC_ACCESS_MASK 0x00000003L +#define ZSC_CNTL__LONO_PWR_DN_MASK 0x00000100L +//ZSC_CNTL2 +#define ZSC_CNTL2__ALLOW_Z10__SHIFT 0x0 +#define ZSC_CNTL2__ALLOW_Z10_MASK 0x00000001L +//DMU_MISC_ALLOW_DS_FORCE +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN__SHIFT 0x0 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE__SHIFT 0x4 +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_EN_MASK 0x00000001L +#define DMU_MISC_ALLOW_DS_FORCE__DMU_MISC_ALLOW_DS_FORCE_VALUE_MASK 0x00000010L +//ZSC_STATUS +#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS__SHIFT 0x0 +#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS__SHIFT 0x4 +#define ZSC_STATUS__FENCE_REQ_STATUS__SHIFT 0x8 +#define ZSC_STATUS__FENCE_ACK_STATUS__SHIFT 0x9 +#define ZSC_STATUS__FENCE_STATUS__SHIFT 0xa +#define ZSC_STATUS__SOC_ACCESS_TRIGGER_STATUS_MASK 0x00000007L +#define ZSC_STATUS__SOC_ACCESS_STICKY_TRIGGER_STATUS_MASK 0x00000070L +#define ZSC_STATUS__FENCE_REQ_STATUS_MASK 0x00000100L +#define ZSC_STATUS__FENCE_ACK_STATUS_MASK 0x00000200L +#define ZSC_STATUS__FENCE_STATUS_MASK 0x00000C00L +//DMU_DISPCLK_CGTT_BLK_CTRL_REG +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DMU_DISPCLK_CGTT_BLK_CTRL_REG__LONO_DISPCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//DMU_SOCCLK_CGTT_BLK_CTRL_REG +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DMU_SOCCLK_CGTT_BLK_CTRL_REG__LONO_SOCCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +//ZPR_CLK_UNGATE_DELAY +#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY__SHIFT 0x0 +#define ZPR_CLK_UNGATE_DELAY__ZPR_CLK_UNGATE_DELAY_MASK 0x000000FFL + + +// addressBlock: dce_dc_dmu_ihc_dispdec +//DC_GPU_TIMER_START_POSITION_V_UPDATE +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_VSTARTUP +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D1_VSTARTUP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D2_VSTARTUP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D3_VSTARTUP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D4_VSTARTUP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D5_VSTARTUP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VSTARTUP__DC_GPU_TIMER_START_POSITION_D6_VSTARTUP_MASK 0x00700000L +//DC_GPU_TIMER_READ +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x0 +#define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xFFFFFFFFL +//DC_GPU_TIMER_READ_CNTL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x0 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x8 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0xb +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0xe +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x11 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x14 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x17 +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000007FL +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001C000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000E0000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L +#define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L +//DISP_INTERRUPT_STATUS +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS__OPTC1_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS__DIO_ALPM_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS__RBBMIF_IHC_TIMEOUT_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE__OPTC2_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__OTG1_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE2 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE2__OPTC3_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__OTG2_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE3 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE3__OPTC4_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__WBSCL0_DATA_OVERFLOW_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__OTG3_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC5_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OPTC6_DATA_UNDERFLOW_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__OTG4_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SNAPSHOT_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGA_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_TRIGB_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VSYNC_NOM_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT0_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT1_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG5_IHC_VERTICAL_INTERRUPT2_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT0_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT1_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__OTG6_IHC_VERTICAL_INTERRUPT2_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE5__DISP_INTERRUPT_STATUS_CONTINUE6_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE6 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE6__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB0_IHIF_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_CWB1_IHIF_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB0_IHIF_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB1_IHIF_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__MCIF_DWB2_IHIF_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE6__DISP_INTERRUPT_STATUS_CONTINUE7_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE7 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DCCG_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DMU_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DIO_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER0_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__WB0_PERFMON_COUNTER1_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE7__DISP_INTERRUPT_STATUS_CONTINUE8_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE8 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DPP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE8__DISP_INTERRUPT_STATUS_CONTINUE9_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP0_HIST_RDY_IHC_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP1_HIST_RDY_IHC_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP2_HIST_RDY_IHC_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_HIST_RDY_IHC_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_HIST_RDY_IHC_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_HIST_RDY_IHC_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP6_HIST_RDY_IHC_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP7_HIST_RDY_IHC_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP0_HIST_RDY_IHC_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP1_HIST_RDY_IHC_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP2_HIST_RDY_IHC_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP3_HIST_RDY_IHC_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP4_HIST_RDY_IHC_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP5_HIST_RDY_IHC_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP6_HIST_RDY_IHC_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DPP7_HIST_RDY_IHC_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL1_DATA_OVERFLOW_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__WBSCL2_DATA_OVERFLOW_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE9__DISP_INTERRUPT_STATUS_CONTINUE10_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE10 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG0_LATCH_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG1_LATCH_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG2_LATCH_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG3_LATCH_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG4_LATCH_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_IHC_VSYNC_OTG5_LATCH_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER0_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DCCG_PERFMON2_COUNTER1_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG1_IHC_DRR_TIMING_UPDATE_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG2_IHC_DRR_TIMING_UPDATE_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG3_IHC_DRR_TIMING_UPDATE_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG4_IHC_DRR_TIMING_UPDATE_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG5_IHC_DRR_TIMING_UPDATE_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__OTG6_IHC_DRR_TIMING_UPDATE_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE10__DISP_INTERRUPT_STATUS_CONTINUE11_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE11__WB2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC0_STALL_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC1_STALL_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC2_STALL_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC3_STALL_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC4_STALL_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC5_STALL_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC6_STALL_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__MPCC7_STALL_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE11__DISP_INTERRUPT_STATUS_CONTINUE12_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE12__MPC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DPP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE12__DISP_INTERRUPT_STATUS_CONTINUE13_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_VM_FAULT_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_TIMEOUT_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__HUBP0_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE13__DISP_INTERRUPT_STATUS_CONTINUE14_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE14 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__HUBP1_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE14__DISP_INTERRUPT_STATUS_CONTINUE15_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE15 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP6_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VBLANK_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_VLINE2_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__HUBP2_IHC_TIMEOUT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE15__DISP_INTERRUPT_STATUS_CONTINUE16_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VBLANK_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_VLINE2_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VBLANK_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_VLINE2_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VBLANK_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_VLINE2_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VBLANK_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_VLINE2_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VBLANK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_VLINE2_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP3_IHC_TIMEOUT_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP4_IHC_TIMEOUT_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP5_IHC_TIMEOUT_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP6_IHC_TIMEOUT_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__HUBP7_IHC_TIMEOUT_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE16__DISP_INTERRUPT_STATUS_CONTINUE17_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPP_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE17__OPTC_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER0_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__MMHUBBUB_PERFMON_COUNTER1_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP0_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP1_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP2_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP3_IHC_FLIP_AWAY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP4_IHC_FLIP_AWAY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP5_IHC_FLIP_AWAY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP6_IHC_FLIP_AWAY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__HUBP7_IHC_FLIP_AWAY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE17__DISP_INTERRUPT_STATUS_CONTINUE18_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE18__AZ_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE18__DISP_INTERRUPT_STATUS_CONTINUE19_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE19 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DIGG_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE19__DISP_INTERRUPT_STATUS_CONTINUE20_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE20 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_CPU_SS_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_CPU_SS_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_CPU_SS_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_CPU_SS_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_CPU_SS_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_CPU_SS_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_V_UPDATE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_V_UPDATE_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_V_UPDATE_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_V_UPDATE_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_V_UPDATE_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_V_UPDATE_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VSTARTUP_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VSTARTUP_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VSTARTUP_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VSTARTUP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VSTARTUP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VSTARTUP_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG1_IHC_VREADY_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG2_IHC_VREADY_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG3_IHC_VREADY_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG4_IHC_VREADY_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG5_IHC_VREADY_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__OTG6_IHC_VREADY_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE20__DISP_INTERRUPT_STATUS_CONTINUE21_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE21 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DC_I2C_VGA_READ_REQUEST_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DIGH_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE21__DISP_INTERRUPT_STATUS_CONTINUE22_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE22 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE22__DISP_INTERRUPT_STATUS_CONTINUE23_MASK 0x80000000L +//DC_GPU_TIMER_START_POSITION_VREADY +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D1_VREADY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D2_VREADY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D3_VREADY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D4_VREADY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D5_VREADY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_VREADY__DC_GPU_TIMER_START_POSITION_D6_VREADY_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D1_FLIP_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D2_FLIP_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D3_FLIP_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D4_FLIP_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D5_FLIP_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D6_FLIP_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D7_FLIP_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP__DC_GPU_TIMER_START_POSITION_D8_FLIP_MASK 0x70000000L +//DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_NO_LOCK_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_NO_LOCK_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_NO_LOCK_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_NO_LOCK_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_NO_LOCK_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_NO_LOCK_MASK 0x00700000L +//DC_GPU_TIMER_START_POSITION_FLIP_AWAY +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY__SHIFT 0x0 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY__SHIFT 0x4 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY__SHIFT 0x8 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY__SHIFT 0xc +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY__SHIFT 0x10 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY__SHIFT 0x14 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY__SHIFT 0x18 +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY__SHIFT 0x1c +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D1_FLIP_AWAY_MASK 0x00000007L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D2_FLIP_AWAY_MASK 0x00000070L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D3_FLIP_AWAY_MASK 0x00000700L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D4_FLIP_AWAY_MASK 0x00007000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D5_FLIP_AWAY_MASK 0x00070000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D6_FLIP_AWAY_MASK 0x00700000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D7_FLIP_AWAY_MASK 0x07000000L +#define DC_GPU_TIMER_START_POSITION_FLIP_AWAY__DC_GPU_TIMER_START_POSITION_D8_FLIP_AWAY_MASK 0x70000000L +//DISP_INTERRUPT_STATUS_CONTINUE23 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE23__DISP_INTERRUPT_STATUS_CONTINUE24_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE24 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x0 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x2 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x3 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x4 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x5 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0xe +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0xf +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT__SHIFT 0x18 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT__SHIFT 0x19 +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT__SHIFT 0x1a +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT__SHIFT 0x1b +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25__SHIFT 0x1f +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000001L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC0_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000002L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000004L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC1_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000008L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000010L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC2_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000020L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC3_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC4_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER0_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DSC5_PERFMON_COUNTER1_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_HIGH_PRIORITY_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_TIMER_LOW_PRIORITY_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00004000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00008000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_INBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_HIGH_PRIORITY_DONE_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_READY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_OUTBOX_LOW_PRIORITY_DONE_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN0_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN1_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN2_INTERRUPT_MASK 0x01000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN3_INTERRUPT_MASK 0x02000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN4_INTERRUPT_MASK 0x04000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN5_INTERRUPT_MASK 0x08000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAIN6_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_GENERAL_DATAOUT_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DMCUB_UNDEFINED_ADDRESS_FAULT_INTERRUPT_MASK 0x40000000L +#define DISP_INTERRUPT_STATUS_CONTINUE24__DISP_INTERRUPT_STATUS_CONTINUE25_MASK 0x80000000L +//DISP_INTERRUPT_STATUS_CONTINUE25 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x6 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x7 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x8 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT__SHIFT 0x9 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT__SHIFT 0xa +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT__SHIFT 0xb +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT__SHIFT 0xc +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT__SHIFT 0xd +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX0_RDY_INTERRUPT__SHIFT 0x10 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX1_RDY_INTERRUPT__SHIFT 0x11 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX2_RDY_INTERRUPT__SHIFT 0x12 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX3_RDY_INTERRUPT__SHIFT 0x13 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX4_RDY_INTERRUPT__SHIFT 0x14 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_OUTBOX0_RSP_INTERRUPT__SHIFT 0x15 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_INBOX0_RSP_INTERRUPT__SHIFT 0x16 +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_OUTBOX0_RDY_INTERRUPT__SHIFT 0x17 +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT__SHIFT 0x1c +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT__SHIFT 0x1d +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT__SHIFT 0x1e +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC0_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000040L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC1_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000080L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC2_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000100L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC3_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000200L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC4_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000400L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DSC5_IHC_CORE_ERROR_INTERRUPT_MASK 0x00000800L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DPIA_INTERRUPT_MASK 0x00001000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_WHITELIST_INVALID_ACCESS_INTERRUPT_MASK 0x00002000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX0_RDY_INTERRUPT_MASK 0x00010000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX1_RDY_INTERRUPT_MASK 0x00020000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX2_RDY_INTERRUPT_MASK 0x00040000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX3_RDY_INTERRUPT_MASK 0x00080000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_INBOX4_RDY_INTERRUPT_MASK 0x00100000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_REG_OUTBOX0_RSP_INTERRUPT_MASK 0x00200000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_INBOX0_RSP_INTERRUPT_MASK 0x00400000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__DMCUB_HOST_REG_OUTBOX0_RDY_INTERRUPT_MASK 0x00800000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER0_INTERRUPT_MASK 0x10000000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__HPO_PERFMON_COUNTER1_INTERRUPT_MASK 0x20000000L +#define DISP_INTERRUPT_STATUS_CONTINUE25__MMHUBBUB_WARMUP_INTERRUPT_MASK 0x40000000L +//DCCG_INTERRUPT_DEST +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST__SHIFT 0x0 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST__SHIFT 0x1 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST__SHIFT 0x2 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST__SHIFT 0x3 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST__SHIFT 0x4 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST__SHIFT 0x5 +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG0_LATCH_INT_DEST_MASK 0x00000001L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG1_LATCH_INT_DEST_MASK 0x00000002L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG2_LATCH_INT_DEST_MASK 0x00000004L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG3_LATCH_INT_DEST_MASK 0x00000008L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG4_LATCH_INT_DEST_MASK 0x00000010L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_VSYNC_OTG5_LATCH_INT_DEST_MASK 0x00000020L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCCG_INTERRUPT_DEST__DCCG_IHC_PERFMON2_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +//DMU_INTERRUPT_DEST +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST__SHIFT 0x8 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST__SHIFT 0x9 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST__SHIFT 0xa +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST__SHIFT 0xb +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST__SHIFT 0xe +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST__SHIFT 0xf +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST__SHIFT 0x10 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST__SHIFT 0x11 +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST__SHIFT 0x1a +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER0_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_TIMER1_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT0_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT1_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT2_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT3_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT4_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT5_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT6_INT_DEST_MASK 0x00000100L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_GPINT_IH_INT_DEST_MASK 0x00000200L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_READY_INT_DEST_MASK 0x00000400L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX0_DONE_INT_DEST_MASK 0x00000800L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_READY_INT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_INBOX1_DONE_INT_DEST_MASK 0x00002000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_READY_INT_DEST_MASK 0x00004000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX0_DONE_INT_DEST_MASK 0x00008000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_READY_INT_DEST_MASK 0x00010000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_OUTBOX1_DONE_INT_DEST_MASK 0x00020000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DMU_INTERRUPT_DEST__DMU_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DMU_INTERRUPT_DEST__DMCUB_IHC_UNDEFINED_ADDRESS_FAULT_INT_DEST_MASK 0x04000000L +#define DMU_INTERRUPT_DEST__RBBMIF_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +//DMU_INTERRUPT_DEST2 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX0_RDY_INT_DEST__SHIFT 0x0 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX1_RDY_INT_DEST__SHIFT 0x1 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX2_RDY_INT_DEST__SHIFT 0x2 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX3_RDY_INT_DEST__SHIFT 0x3 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX4_RDY_INT_DEST__SHIFT 0x4 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_OUTBOX0_RSP_INT_DEST__SHIFT 0x5 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_INBOX0_RSP_INT_DEST__SHIFT 0x6 +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_OUTBOX0_RDY_INT_DEST__SHIFT 0x7 +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST__SHIFT 0xc +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST__SHIFT 0xd +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX0_RDY_INT_DEST_MASK 0x00000001L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX1_RDY_INT_DEST_MASK 0x00000002L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX2_RDY_INT_DEST_MASK 0x00000004L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX3_RDY_INT_DEST_MASK 0x00000008L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_INBOX4_RDY_INT_DEST_MASK 0x00000010L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_REG_OUTBOX0_RSP_INT_DEST_MASK 0x00000020L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_INBOX0_RSP_INT_DEST_MASK 0x00000040L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_HOST_REG_OUTBOX0_RDY_INT_DEST_MASK 0x00000080L +#define DMU_INTERRUPT_DEST2__DPIA_IHC_INTERRUPT_DEST_MASK 0x00001000L +#define DMU_INTERRUPT_DEST2__DMCUB_IHC_WHITELIST_INVALID_ACCESS_INTERRUPT_DEST_MASK 0x00002000L +//DCPG_INTERRUPT_DEST +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST__DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +//DCPG_INTERRUPT_DEST2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST__SHIFT 0x0 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST__SHIFT 0x1 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST__SHIFT 0x2 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST__SHIFT 0x3 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST__SHIFT 0x4 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST__SHIFT 0x5 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST__SHIFT 0x6 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST__SHIFT 0x7 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST__SHIFT 0x8 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST__SHIFT 0x9 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT_DEST__SHIFT 0xa +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x10 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x11 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x12 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x13 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x14 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x15 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x16 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x17 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x18 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x19 +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT_DEST__SHIFT 0x1a +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_UP_INTERRUPT_DEST_MASK 0x00000001L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_UP_INTERRUPT_DEST_MASK 0x00000002L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_UP_INTERRUPT_DEST_MASK 0x00000004L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_UP_INTERRUPT_DEST_MASK 0x00000008L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_UP_INTERRUPT_DEST_MASK 0x00000010L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_UP_INTERRUPT_DEST_MASK 0x00000020L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_UP_INTERRUPT_DEST_MASK 0x00000040L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_UP_INTERRUPT_DEST_MASK 0x00000080L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_UP_INTERRUPT_DEST_MASK 0x00000100L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_UP_INTERRUPT_DEST_MASK 0x00000200L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_UP_INTERRUPT_DEST_MASK 0x00000400L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN16_POWER_DOWN_INTERRUPT_DEST_MASK 0x00010000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN17_POWER_DOWN_INTERRUPT_DEST_MASK 0x00020000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN18_POWER_DOWN_INTERRUPT_DEST_MASK 0x00040000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN19_POWER_DOWN_INTERRUPT_DEST_MASK 0x00080000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN20_POWER_DOWN_INTERRUPT_DEST_MASK 0x00100000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN21_POWER_DOWN_INTERRUPT_DEST_MASK 0x00200000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN22_POWER_DOWN_INTERRUPT_DEST_MASK 0x00400000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN23_POWER_DOWN_INTERRUPT_DEST_MASK 0x00800000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN24_POWER_DOWN_INTERRUPT_DEST_MASK 0x01000000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN25_POWER_DOWN_INTERRUPT_DEST_MASK 0x02000000L +#define DCPG_INTERRUPT_DEST2__DCPG_IHC_DOMAIN26_POWER_DOWN_INTERRUPT_DEST_MASK 0x04000000L +//MMHUBBUB_INTERRUPT_DEST +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST__SHIFT 0x1 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST__SHIFT 0x2 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST__SHIFT 0x3 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST__SHIFT 0x4 +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST__SHIFT 0x5 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST__SHIFT 0x8 +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB0_IHIF_INTERRUPT_DEST_MASK 0x00000002L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_CWB1_IHIF_INTERRUPT_DEST_MASK 0x00000004L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB0_IHIF_INTERRUPT_DEST_MASK 0x00000008L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB1_IHIF_INTERRUPT_DEST_MASK 0x00000010L +#define MMHUBBUB_INTERRUPT_DEST__BUFMGR_DWB2_IHIF_INTERRUPT_DEST_MASK 0x00000020L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_WARMUP_INTERRUPT_DEST_MASK 0x00000100L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MMHUBBUB_INTERRUPT_DEST__MMHUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//WB_INTERRUPT_DEST +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x1 +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0x9 +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST__SHIFT 0xb +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define WB_INTERRUPT_DEST__WBSCL0_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000002L +#define WB_INTERRUPT_DEST__WBSCL1_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000200L +#define WB_INTERRUPT_DEST__WBSCL2_IHIF_DATA_OVERFLOW_INTERRUPT_DEST_MASK 0x00000800L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define WB_INTERRUPT_DEST__WB0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define WB_INTERRUPT_DEST__WB1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define WB_INTERRUPT_DEST__WB2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +//DCHUB_INTERRUPT_DEST +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST__SHIFT 0x1e +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x1f +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST__HUBP0_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST__HUBP1_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST__HUBP2_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST__HUBP3_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_INTERRUPT_DEST__HUBP4_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VBLANK_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_VLINE2_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_INTERRUPT_DEST__HUBP5_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VBLANK_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_VLINE2_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_INTERRUPT_DEST__HUBP6_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VBLANK_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE_INTERRUPT_DEST_MASK 0x20000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_VLINE2_INTERRUPT_DEST_MASK 0x40000000L +#define DCHUB_INTERRUPT_DEST__HUBP7_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x80000000L +//DCHUB_PERFCOUNTER_INTERRUPT_DEST +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1c +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1d +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBBUB_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x10000000L +#define DCHUB_PERFCOUNTER_INTERRUPT_DEST__HUBP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x20000000L +//DCHUB_INTERRUPT_DEST2 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x0 +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x1 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x2 +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x3 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x4 +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x5 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x6 +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x7 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST__SHIFT 0x8 +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0x9 +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xa +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xb +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xc +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xd +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST__SHIFT 0xe +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST__SHIFT 0xf +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST__SHIFT 0x18 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST__SHIFT 0x19 +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST__SHIFT 0x1a +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000001L +#define DCHUB_INTERRUPT_DEST2__HUBP0_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000002L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000004L +#define DCHUB_INTERRUPT_DEST2__HUBP1_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000008L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000010L +#define DCHUB_INTERRUPT_DEST2__HUBP2_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000020L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000040L +#define DCHUB_INTERRUPT_DEST2__HUBP3_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000080L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000100L +#define DCHUB_INTERRUPT_DEST2__HUBP4_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000200L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_INTERRUPT_DEST_MASK 0x00000400L +#define DCHUB_INTERRUPT_DEST2__HUBP5_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00000800L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_INTERRUPT_DEST_MASK 0x00001000L +#define DCHUB_INTERRUPT_DEST2__HUBP6_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00002000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_INTERRUPT_DEST_MASK 0x00004000L +#define DCHUB_INTERRUPT_DEST2__HUBP7_IHC_FLIP_AWAY_INTERRUPT_DEST_MASK 0x00008000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_VM_FAULT_INTERRUPT_DEST_MASK 0x01000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_TIMEOUT_INTERRUPT_DEST_MASK 0x02000000L +#define DCHUB_INTERRUPT_DEST2__HUBBUB_IHC_COMPBUF_SIZE_CHANGE_INTERRUPT_DEST_MASK 0x04000000L +//DPP_PERFCOUNTER_INTERRUPT_DEST +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x10 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x11 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x14 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x15 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x18 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x19 +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1a +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1b +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00010000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00020000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00100000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00200000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x01000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP6_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x02000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x04000000L +#define DPP_PERFCOUNTER_INTERRUPT_DEST__DPP7_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x08000000L +//MPC_INTERRUPT_DEST +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST__SHIFT 0x0 +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST__SHIFT 0x1 +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST__SHIFT 0x2 +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST__SHIFT 0x3 +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST__SHIFT 0x4 +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST__SHIFT 0x5 +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST__SHIFT 0x6 +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST__SHIFT 0x7 +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define MPC_INTERRUPT_DEST__MPCC0_STALL_INTERRUPT_DEST_MASK 0x00000001L +#define MPC_INTERRUPT_DEST__MPCC1_STALL_INTERRUPT_DEST_MASK 0x00000002L +#define MPC_INTERRUPT_DEST__MPCC2_STALL_INTERRUPT_DEST_MASK 0x00000004L +#define MPC_INTERRUPT_DEST__MPCC3_STALL_INTERRUPT_DEST_MASK 0x00000008L +#define MPC_INTERRUPT_DEST__MPCC4_STALL_INTERRUPT_DEST_MASK 0x00000010L +#define MPC_INTERRUPT_DEST__MPCC5_STALL_INTERRUPT_DEST_MASK 0x00000020L +#define MPC_INTERRUPT_DEST__MPCC6_STALL_INTERRUPT_DEST_MASK 0x00000040L +#define MPC_INTERRUPT_DEST__MPCC7_STALL_INTERRUPT_DEST_MASK 0x00000080L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define MPC_INTERRUPT_DEST__MPC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPP_INTERRUPT_DEST +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPP_INTERRUPT_DEST__OPP_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//OPTC_INTERRUPT_DEST +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x18 +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x19 +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1a +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1b +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1c +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST__SHIFT 0x1d +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define OPTC_INTERRUPT_DEST__OPTC_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +#define OPTC_INTERRUPT_DEST__OPTC0_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x01000000L +#define OPTC_INTERRUPT_DEST__OPTC1_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x02000000L +#define OPTC_INTERRUPT_DEST__OPTC2_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x04000000L +#define OPTC_INTERRUPT_DEST__OPTC3_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x08000000L +#define OPTC_INTERRUPT_DEST__OPTC4_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x10000000L +#define OPTC_INTERRUPT_DEST__OPTC5_IHC_DATA_UNDERFLOW_INTERRUPT_DEST_MASK 0x20000000L +//OTG0_INTERRUPT_DEST +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG0_INTERRUPT_DEST__OTG0_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG0_INTERRUPT_DEST__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG0_INTERRUPT_DEST__OTG0_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG1_INTERRUPT_DEST +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG1_INTERRUPT_DEST__OTG1_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG1_INTERRUPT_DEST__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG1_INTERRUPT_DEST__OTG1_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG2_INTERRUPT_DEST +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG2_INTERRUPT_DEST__OTG2_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG2_INTERRUPT_DEST__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG2_INTERRUPT_DEST__OTG2_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG3_INTERRUPT_DEST +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG3_INTERRUPT_DEST__OTG3_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG3_INTERRUPT_DEST__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG3_INTERRUPT_DEST__OTG3_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG4_INTERRUPT_DEST +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG4_INTERRUPT_DEST__OTG4_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG4_INTERRUPT_DEST__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG4_INTERRUPT_DEST__OTG4_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//OTG5_INTERRUPT_DEST +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST__SHIFT 0x0 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST__SHIFT 0x1 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST__SHIFT 0x2 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST__SHIFT 0x3 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST__SHIFT 0x4 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST__SHIFT 0x5 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST__SHIFT 0x6 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST__SHIFT 0x7 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST__SHIFT 0x8 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST__SHIFT 0x9 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST__SHIFT 0xa +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST__SHIFT 0xb +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST__SHIFT 0xf +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST__SHIFT 0x10 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST__SHIFT 0x11 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST__SHIFT 0x12 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST__SHIFT 0x13 +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST__SHIFT 0x14 +#define OTG5_INTERRUPT_DEST__OTG5_IHC_CPU_SS_INTERRUPT_DEST_MASK 0x00000001L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_DRR_TIMING_INTERRUPT_DEST_MASK 0x00000002L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_INTERRUPT_DEST_MASK 0x00000004L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SNAPSHOT_INTERRUPT_DEST_MASK 0x00000008L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_FORCE_COUNT_NOW_INTERRUPT_DEST_MASK 0x00000010L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT_DEST_MASK 0x00000020L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGA_INTERRUPT_DEST_MASK 0x00000040L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_TRIGB_INTERRUPT_DEST_MASK 0x00000080L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT_DEST_MASK 0x00000100L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT0_DEST_MASK 0x00000200L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT1_DEST_MASK 0x00000400L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_OTG_VERTICAL_INTERRUPT2_DEST_MASK 0x00000800L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INTERRUPT_DEST_MASK 0x00008000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSTARTUP_INTERRUPT_DEST_MASK 0x00010000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VREADY_INTERRUPT_DEST_MASK 0x00020000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_VSYNC_NOM_INTERRUPT_DEST_MASK 0x00040000L +#define OTG5_INTERRUPT_DEST__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT_DEST_MASK 0x00080000L +#define OTG5_INTERRUPT_DEST__OTG5_DRR_V_TOTAL_REACH_INTERRUPT_DEST_MASK 0x00100000L +//DIG_INTERRUPT_DEST +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x0 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x1 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x2 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x3 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x4 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x5 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x6 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST__SHIFT 0x7 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x8 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0x9 +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xa +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xb +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xc +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xd +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xe +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST__SHIFT 0xf +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000001L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000002L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000004L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000008L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000010L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000020L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000040L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_VID_STREAM_DISABLE_INTERRUPT_DEST_MASK 0x00000080L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGA_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000100L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGB_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000200L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGC_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000400L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGD_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00000800L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGE_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00001000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGF_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00002000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGG_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00004000L +#define DIG_INTERRUPT_DEST__DOUT_IHC_DIGH_FAST_TRAINING_COMPLETE_INTERRUPT_DEST_MASK 0x00008000L +//I2C_DDC_HPD_INTERRUPT_DEST +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x10 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x11 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x12 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x13 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x14 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST__SHIFT 0x15 +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST__SHIFT 0x16 +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define I2C_DDC_HPD_INTERRUPT_DEST__DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC1_READ_REQUEST_INTERRUPT_DEST_MASK 0x00010000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC2_READ_REQUEST_INTERRUPT_DEST_MASK 0x00020000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC3_READ_REQUEST_INTERRUPT_DEST_MASK 0x00040000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC4_READ_REQUEST_INTERRUPT_DEST_MASK 0x00080000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC5_READ_REQUEST_INTERRUPT_DEST_MASK 0x00100000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDC6_READ_REQUEST_INTERRUPT_DEST_MASK 0x00200000L +#define I2C_DDC_HPD_INTERRUPT_DEST__DC_I2C_DDCVGA_READ_REQUEST_INTERRPUT_DEST_MASK 0x00400000L +//DIO_INTERRUPT_DEST +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST__SHIFT 0x4 +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xc +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xd +#define DIO_INTERRUPT_DEST__DIO_ALPM_INTERRUPT_DEST_MASK 0x00000010L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00001000L +#define DIO_INTERRUPT_DEST__DIO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00002000L +//DCIO_INTERRUPT_DEST +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x0 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x2 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x3 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x4 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x6 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST__SHIFT 0x10 +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000001L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000004L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000008L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000010L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT_DEST_MASK 0x00000040L +#define DCIO_INTERRUPT_DEST__DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT_DEST_MASK 0x00010000L +//HPD_INTERRUPT_DEST +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST__SHIFT 0x0 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST__SHIFT 0x1 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST__SHIFT 0x2 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST__SHIFT 0x3 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST__SHIFT 0x4 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST__SHIFT 0x5 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST__SHIFT 0x8 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST__SHIFT 0x9 +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST__SHIFT 0xa +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST__SHIFT 0xb +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST__SHIFT 0xc +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST__SHIFT 0xd +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_INTERRUPT_DEST_MASK 0x00000001L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_INTERRUPT_DEST_MASK 0x00000002L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_INTERRUPT_DEST_MASK 0x00000004L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_INTERRUPT_DEST_MASK 0x00000008L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_INTERRUPT_DEST_MASK 0x00000010L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_INTERRUPT_DEST_MASK 0x00000020L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD1_RX_INTERRUPT_DEST_MASK 0x00000100L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD2_RX_INTERRUPT_DEST_MASK 0x00000200L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD3_RX_INTERRUPT_DEST_MASK 0x00000400L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD4_RX_INTERRUPT_DEST_MASK 0x00000800L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD5_RX_INTERRUPT_DEST_MASK 0x00001000L +#define HPD_INTERRUPT_DEST__DOUT_IHC_HPD6_RX_INTERRUPT_DEST_MASK 0x00002000L +//AZ_INTERRUPT_DEST +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x0 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x1 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x2 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x3 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x4 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x5 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x6 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST__SHIFT 0x7 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST__SHIFT 0x8 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST__SHIFT 0x9 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST__SHIFT 0xa +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST__SHIFT 0xb +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST__SHIFT 0xc +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST__SHIFT 0xd +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST__SHIFT 0xe +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST__SHIFT 0xf +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST__SHIFT 0x10 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST__SHIFT 0x11 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST__SHIFT 0x12 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST__SHIFT 0x13 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST__SHIFT 0x14 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST__SHIFT 0x15 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST__SHIFT 0x16 +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST__SHIFT 0x17 +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x1e +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x1f +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000001L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000002L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000004L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000008L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000010L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000020L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000040L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT_DEST_MASK 0x00000080L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT_DEST_MASK 0x00000100L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT_DEST_MASK 0x00000200L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT_DEST_MASK 0x00000400L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT_DEST_MASK 0x00000800L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT_DEST_MASK 0x00001000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT_DEST_MASK 0x00002000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT_DEST_MASK 0x00004000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT_DEST_MASK 0x00008000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT_DEST_MASK 0x00010000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT_DEST_MASK 0x00020000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT_DEST_MASK 0x00040000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT_DEST_MASK 0x00080000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT_DEST_MASK 0x00100000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT_DEST_MASK 0x00200000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT_DEST_MASK 0x00400000L +#define AZ_INTERRUPT_DEST__AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT_DEST_MASK 0x00800000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x40000000L +#define AZ_INTERRUPT_DEST__AZ_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x80000000L +//AUX_INTERRUPT_DEST +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST__SHIFT 0x0 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST__SHIFT 0x1 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST__SHIFT 0x2 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST__SHIFT 0x3 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST__SHIFT 0x4 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST__SHIFT 0x5 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST__SHIFT 0x6 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST__SHIFT 0x7 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST__SHIFT 0x8 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST__SHIFT 0x9 +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST__SHIFT 0xa +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST__SHIFT 0xb +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_SW_DONE_INTERRUPT_DEST_MASK 0x00000001L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX1_LS_DONE_INTERRUPT_DEST_MASK 0x00000002L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_SW_DONE_INTERRUPT_DEST_MASK 0x00000004L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX2_LS_DONE_INTERRUPT_DEST_MASK 0x00000008L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_SW_DONE_INTERRUPT_DEST_MASK 0x00000010L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX3_LS_DONE_INTERRUPT_DEST_MASK 0x00000020L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_SW_DONE_INTERRUPT_DEST_MASK 0x00000040L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX4_LS_DONE_INTERRUPT_DEST_MASK 0x00000080L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_SW_DONE_INTERRUPT_DEST_MASK 0x00000100L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX5_LS_DONE_INTERRUPT_DEST_MASK 0x00000200L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_SW_DONE_INTERRUPT_DEST_MASK 0x00000400L +#define AUX_INTERRUPT_DEST__DOUT_IHC_AUX6_LS_DONE_INTERRUPT_DEST_MASK 0x00000800L +//DSC_INTERRUPT_DEST +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x1 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x5 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x6 +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x7 +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x9 +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xa +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xb +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0xd +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0xe +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0xf +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x11 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x12 +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x13 +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST__SHIFT 0x15 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x16 +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x17 +#define DSC_INTERRUPT_DEST__DSC0_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000002L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define DSC_INTERRUPT_DEST__DSC0_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define DSC_INTERRUPT_DEST__DSC1_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000020L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000040L +#define DSC_INTERRUPT_DEST__DSC1_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000080L +#define DSC_INTERRUPT_DEST__DSC2_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00000200L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000400L +#define DSC_INTERRUPT_DEST__DSC2_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000800L +#define DSC_INTERRUPT_DEST__DSC3_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00002000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00004000L +#define DSC_INTERRUPT_DEST__DSC3_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00008000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00020000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00040000L +#define DSC_INTERRUPT_DEST__DSC4_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00080000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_CORE_ERROR_INTERRUPT_DEST_MASK 0x00200000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00400000L +#define DSC_INTERRUPT_DEST__DSC5_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00800000L +//HPO_INTERRUPT_DEST +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST__SHIFT 0x2 +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST__SHIFT 0x3 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x4 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x5 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x6 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x7 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x8 +#define HPO_INTERRUPT_DEST__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_DEST__SHIFT 0x9 +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER0_INTERRUPT_DEST_MASK 0x00000004L +#define HPO_INTERRUPT_DEST__HPO_IHC_PERFMON_COUNTER1_INTERRUPT_DEST_MASK 0x00000008L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE0_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000010L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE1_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000020L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE2_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000040L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE3_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000080L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE4_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000100L +#define HPO_INTERRUPT_DEST__HPO_IHC_SE5_ALPM_WAKE_INTERRUPT_DEST_MASK 0x00000200L +//DPP_INTERRUPT_DEST +#define DPP_INTERRUPT_DEST__DPP0_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x0 +#define DPP_INTERRUPT_DEST__DPP1_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x1 +#define DPP_INTERRUPT_DEST__DPP2_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x2 +#define DPP_INTERRUPT_DEST__DPP3_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x3 +#define DPP_INTERRUPT_DEST__DPP4_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x4 +#define DPP_INTERRUPT_DEST__DPP5_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x5 +#define DPP_INTERRUPT_DEST__DPP6_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x6 +#define DPP_INTERRUPT_DEST__DPP7_HIST_RDY_IHC_INTERRUPT_DEST__SHIFT 0x7 +#define DPP_INTERRUPT_DEST__DPP0_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000001L +#define DPP_INTERRUPT_DEST__DPP1_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000002L +#define DPP_INTERRUPT_DEST__DPP2_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000004L +#define DPP_INTERRUPT_DEST__DPP3_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000008L +#define DPP_INTERRUPT_DEST__DPP4_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000010L +#define DPP_INTERRUPT_DEST__DPP5_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000020L +#define DPP_INTERRUPT_DEST__DPP6_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000040L +#define DPP_INTERRUPT_DEST__DPP7_HIST_RDY_IHC_INTERRUPT_DEST_MASK 0x00000080L + + +// addressBlock: dce_dc_dmu_fgsec_dispdec +//DMCUB_RBBMIF_SEC_CNTL +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL__SHIFT 0x0 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL__SHIFT 0x4 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID__SHIFT 0x8 +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SEC_LVL_MASK 0x00000007L +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_TRUST_LVL_MASK 0x000000F0L +#define DMCUB_RBBMIF_SEC_CNTL__DMCUB_RBBMIF_SOURCE_ID_MASK 0x01FFFF00L + + +// addressBlock: dce_dc_dmu_rbbmif_dispdec +//RBBMIF_TIMEOUT +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT 0x14 +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK 0xFFF00000L +//RBBMIF_STATUS +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT 0x0 +#define RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK 0xFFFFFFFFL +//RBBMIF_STATUS_2 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT 0x0 +#define RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK 0x000000FFL +//RBBMIF_INT_STATUS +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT 0x1c +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT 0x1d +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT 0x1e +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT 0x1f +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK 0x0003FFFCL +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK 0x10000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK 0x20000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK 0x40000000L +#define RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT 0x8 +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT 0x9 +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT 0xa +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT 0xb +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT 0xc +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT 0xd +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT 0xe +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT 0xf +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT 0x10 +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT 0x11 +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT 0x12 +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT 0x13 +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT 0x14 +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT 0x15 +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT 0x16 +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT 0x17 +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT 0x18 +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT 0x19 +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT 0x1a +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT 0x1b +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT 0x1c +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT 0x1d +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT 0x1e +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT 0x1f +#define RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK 0x00000080L +#define RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK 0x00000100L +#define RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK 0x00000200L +#define RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK 0x00000400L +#define RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK 0x00000800L +#define RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK 0x00001000L +#define RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK 0x00002000L +#define RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK 0x00004000L +#define RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK 0x00008000L +#define RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK 0x00010000L +#define RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK 0x00020000L +#define RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK 0x00040000L +#define RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK 0x00080000L +#define RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK 0x00100000L +#define RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK 0x00200000L +#define RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK 0x00400000L +#define RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK 0x00800000L +#define RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK 0x01000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK 0x02000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK 0x04000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK 0x08000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK 0x10000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK 0x20000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK 0x40000000L +#define RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK 0x80000000L +//RBBMIF_TIMEOUT_DIS_2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT 0x0 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT 0x1 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT 0x2 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT 0x3 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT 0x4 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT 0x5 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS__SHIFT 0x6 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT39_TIMEOUT_DIS__SHIFT 0x7 +#define RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK 0x00000001L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK 0x00000002L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK 0x00000004L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK 0x00000008L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK 0x00000010L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK 0x00000020L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT38_TIMEOUT_DIS_MASK 0x00000040L +#define RBBMIF_TIMEOUT_DIS_2__CLIENT39_TIMEOUT_DIS_MASK 0x00000080L +//RBBMIF_STATUS_FLAG +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT 0x0 +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT 0x4 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT 0x5 +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT 0x6 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x8 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x9 +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x10 +#define RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK 0x00000003L +#define RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK 0x00000010L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK 0x00000020L +#define RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK 0x00000040L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000100L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000E00L +#define RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dmu_dmcub_dispdec +//DMCUB_REGION0_OFFSET +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION0_OFFSET__DMCUB_REGION0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION0_OFFSET_HIGH +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION0_OFFSET_HIGH__DMCUB_REGION0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION1_OFFSET +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION1_OFFSET__DMCUB_REGION1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION1_OFFSET_HIGH +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION1_OFFSET_HIGH__DMCUB_REGION1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION2_OFFSET +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION2_OFFSET__DMCUB_REGION2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION2_OFFSET_HIGH +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION2_OFFSET_HIGH__DMCUB_REGION2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION4_OFFSET +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION4_OFFSET__DMCUB_REGION4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION4_OFFSET_HIGH +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION4_OFFSET_HIGH__DMCUB_REGION4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION5_OFFSET +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION5_OFFSET__DMCUB_REGION5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION5_OFFSET_HIGH +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION5_OFFSET_HIGH__DMCUB_REGION5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION6_OFFSET +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION6_OFFSET__DMCUB_REGION6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION6_OFFSET_HIGH +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION6_OFFSET_HIGH__DMCUB_REGION6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION7_OFFSET +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION7_OFFSET__DMCUB_REGION7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION7_OFFSET_HIGH +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION7_OFFSET_HIGH__DMCUB_REGION7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION0_TOP_ADDRESS +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION0_TOP_ADDRESS__DMCUB_REGION0_ENABLE_MASK 0x80000000L +//DMCUB_REGION1_TOP_ADDRESS +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION1_TOP_ADDRESS__DMCUB_REGION1_ENABLE_MASK 0x80000000L +//DMCUB_REGION2_TOP_ADDRESS +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION2_TOP_ADDRESS__DMCUB_REGION2_ENABLE_MASK 0x80000000L +//DMCUB_REGION4_TOP_ADDRESS +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION4_TOP_ADDRESS__DMCUB_REGION4_ENABLE_MASK 0x80000000L +//DMCUB_REGION5_TOP_ADDRESS +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION5_TOP_ADDRESS__DMCUB_REGION5_ENABLE_MASK 0x80000000L +//DMCUB_REGION6_TOP_ADDRESS +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION6_TOP_ADDRESS__DMCUB_REGION6_ENABLE_MASK 0x80000000L +//DMCUB_REGION7_TOP_ADDRESS +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION7_TOP_ADDRESS__DMCUB_REGION7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_BASE_ADDRESS +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_BASE_ADDRESS__DMCUB_REGION3_CW0_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW1_BASE_ADDRESS +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_BASE_ADDRESS__DMCUB_REGION3_CW1_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW2_BASE_ADDRESS +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_BASE_ADDRESS__DMCUB_REGION3_CW2_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW3_BASE_ADDRESS +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_BASE_ADDRESS__DMCUB_REGION3_CW3_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW4_BASE_ADDRESS +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_BASE_ADDRESS__DMCUB_REGION3_CW4_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW5_BASE_ADDRESS +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_BASE_ADDRESS__DMCUB_REGION3_CW5_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW6_BASE_ADDRESS +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_BASE_ADDRESS__DMCUB_REGION3_CW6_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW7_BASE_ADDRESS +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_BASE_ADDRESS__DMCUB_REGION3_CW7_BASE_ADDRESS_MASK 0x1FFFFFFFL +//DMCUB_REGION3_CW0_TOP_ADDRESS +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW0_TOP_ADDRESS__DMCUB_REGION3_CW0_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW1_TOP_ADDRESS +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW1_TOP_ADDRESS__DMCUB_REGION3_CW1_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW2_TOP_ADDRESS +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW2_TOP_ADDRESS__DMCUB_REGION3_CW2_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW3_TOP_ADDRESS +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW3_TOP_ADDRESS__DMCUB_REGION3_CW3_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW4_TOP_ADDRESS +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW4_TOP_ADDRESS__DMCUB_REGION3_CW4_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW5_TOP_ADDRESS +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW5_TOP_ADDRESS__DMCUB_REGION3_CW5_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW6_TOP_ADDRESS +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW6_TOP_ADDRESS__DMCUB_REGION3_CW6_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW7_TOP_ADDRESS +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS__SHIFT 0x0 +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE__SHIFT 0x1f +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_TOP_ADDRESS_MASK 0x1FFFFFFFL +#define DMCUB_REGION3_CW7_TOP_ADDRESS__DMCUB_REGION3_CW7_ENABLE_MASK 0x80000000L +//DMCUB_REGION3_CW0_OFFSET +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW0_OFFSET__DMCUB_REGION3_CW0_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW0_OFFSET_HIGH +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW0_OFFSET_HIGH__DMCUB_REGION3_CW0_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW1_OFFSET +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW1_OFFSET__DMCUB_REGION3_CW1_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW1_OFFSET_HIGH +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW1_OFFSET_HIGH__DMCUB_REGION3_CW1_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW2_OFFSET +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW2_OFFSET__DMCUB_REGION3_CW2_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW2_OFFSET_HIGH +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW2_OFFSET_HIGH__DMCUB_REGION3_CW2_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW3_OFFSET +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW3_OFFSET__DMCUB_REGION3_CW3_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW3_OFFSET_HIGH +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW3_OFFSET_HIGH__DMCUB_REGION3_CW3_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW4_OFFSET +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW4_OFFSET__DMCUB_REGION3_CW4_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW4_OFFSET_HIGH +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW4_OFFSET_HIGH__DMCUB_REGION3_CW4_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW5_OFFSET +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW5_OFFSET__DMCUB_REGION3_CW5_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW5_OFFSET_HIGH +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW5_OFFSET_HIGH__DMCUB_REGION3_CW5_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW6_OFFSET +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW6_OFFSET__DMCUB_REGION3_CW6_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW6_OFFSET_HIGH +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW6_OFFSET_HIGH__DMCUB_REGION3_CW6_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_REGION3_CW7_OFFSET +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET__SHIFT 0x8 +#define DMCUB_REGION3_CW7_OFFSET__DMCUB_REGION3_CW7_OFFSET_MASK 0xFFFFFF00L +//DMCUB_REGION3_CW7_OFFSET_HIGH +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH__SHIFT 0x0 +#define DMCUB_REGION3_CW7_OFFSET_HIGH__DMCUB_REGION3_CW7_OFFSET_HIGH_MASK 0x0000FFFFL +//DMCUB_INTERRUPT_ENABLE +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN__SHIFT 0x0 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN__SHIFT 0x1 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN__SHIFT 0x2 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN__SHIFT 0x3 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN__SHIFT 0x4 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN__SHIFT 0x5 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN__SHIFT 0x6 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN__SHIFT 0x7 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN__SHIFT 0x8 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN__SHIFT 0x9 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN__SHIFT 0xa +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN__SHIFT 0xb +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN__SHIFT 0xc +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN__SHIFT 0xd +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN__SHIFT 0xe +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN__SHIFT 0xf +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN__SHIFT 0x10 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN__SHIFT 0x11 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN__SHIFT 0x12 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX0_RDY_INT_EN__SHIFT 0x13 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX2_RDY_INT_EN__SHIFT 0x15 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX3_RDY_INT_EN__SHIFT 0x16 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX4_RDY_INT_EN__SHIFT 0x17 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_OUTBOX0_RSP_INT_EN__SHIFT 0x18 +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER0_INT_EN_MASK 0x00000001L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_TIMER1_INT_EN_MASK 0x00000002L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_READY_INT_EN_MASK 0x00000004L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX0_DONE_INT_EN_MASK 0x00000008L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_READY_INT_EN_MASK 0x00000010L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_INBOX1_DONE_INT_EN_MASK 0x00000020L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_READY_INT_EN_MASK 0x00000040L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX0_DONE_INT_EN_MASK 0x00000080L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_READY_INT_EN_MASK 0x00000100L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_OUTBOX1_DONE_INT_EN_MASK 0x00000200L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT0_INT_EN_MASK 0x00000400L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT1_INT_EN_MASK 0x00000800L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT2_INT_EN_MASK 0x00001000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT3_INT_EN_MASK 0x00002000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT4_INT_EN_MASK 0x00004000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT5_INT_EN_MASK 0x00008000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT6_INT_EN_MASK 0x00010000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_GPINT_IH_INT_EN_MASK 0x00020000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_EN_MASK 0x00040000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX0_RDY_INT_EN_MASK 0x00080000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX2_RDY_INT_EN_MASK 0x00200000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX3_RDY_INT_EN_MASK 0x00400000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_INBOX4_RDY_INT_EN_MASK 0x00800000L +#define DMCUB_INTERRUPT_ENABLE__DMCUB_REG_OUTBOX0_RSP_INT_EN_MASK 0x01000000L +//DMCUB_INTERRUPT_ACK +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK__SHIFT 0x0 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK__SHIFT 0x1 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK__SHIFT 0x2 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK__SHIFT 0x3 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK__SHIFT 0x4 +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK__SHIFT 0x5 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK__SHIFT 0x6 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK__SHIFT 0x7 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK__SHIFT 0x8 +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK__SHIFT 0x9 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK__SHIFT 0xa +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK__SHIFT 0xb +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK__SHIFT 0xc +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK__SHIFT 0xd +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK__SHIFT 0xe +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK__SHIFT 0xf +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK__SHIFT 0x10 +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK__SHIFT 0x11 +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK__SHIFT 0x12 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX0_RDY_INT_ACK__SHIFT 0x13 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX2_RDY_INT_ACK__SHIFT 0x15 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX3_RDY_INT_ACK__SHIFT 0x16 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX4_RDY_INT_ACK__SHIFT 0x17 +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_OUTBOX0_RSP_INT_ACK__SHIFT 0x18 +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER0_INT_ACK_MASK 0x00000001L +#define DMCUB_INTERRUPT_ACK__DMCUB_TIMER1_INT_ACK_MASK 0x00000002L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_READY_INT_ACK_MASK 0x00000004L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX0_DONE_INT_ACK_MASK 0x00000008L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_READY_INT_ACK_MASK 0x00000010L +#define DMCUB_INTERRUPT_ACK__DMCUB_INBOX1_DONE_INT_ACK_MASK 0x00000020L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_READY_INT_ACK_MASK 0x00000040L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX0_DONE_INT_ACK_MASK 0x00000080L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_READY_INT_ACK_MASK 0x00000100L +#define DMCUB_INTERRUPT_ACK__DMCUB_OUTBOX1_DONE_INT_ACK_MASK 0x00000200L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT0_INT_ACK_MASK 0x00000400L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT1_INT_ACK_MASK 0x00000800L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT2_INT_ACK_MASK 0x00001000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT3_INT_ACK_MASK 0x00002000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT4_INT_ACK_MASK 0x00004000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT5_INT_ACK_MASK 0x00008000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT6_INT_ACK_MASK 0x00010000L +#define DMCUB_INTERRUPT_ACK__DMCUB_GPINT_IH_INT_ACK_MASK 0x00020000L +#define DMCUB_INTERRUPT_ACK__DMCUB_UNDEFINED_ADDRESS_FAULT_ACK_MASK 0x00040000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX0_RDY_INT_ACK_MASK 0x00080000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX2_RDY_INT_ACK_MASK 0x00200000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX3_RDY_INT_ACK_MASK 0x00400000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_INBOX4_RDY_INT_ACK_MASK 0x00800000L +#define DMCUB_INTERRUPT_ACK__DMCUB_REG_OUTBOX0_RSP_INT_ACK_MASK 0x01000000L +//DMCUB_INTERRUPT_STATUS +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT__SHIFT 0x0 +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT__SHIFT 0x1 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT__SHIFT 0x2 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT__SHIFT 0x3 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT__SHIFT 0x4 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT__SHIFT 0x5 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT__SHIFT 0x6 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT__SHIFT 0x7 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT__SHIFT 0x8 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT__SHIFT 0x9 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT__SHIFT 0xa +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT__SHIFT 0xb +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT__SHIFT 0xc +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT__SHIFT 0xd +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT__SHIFT 0xe +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT__SHIFT 0xf +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT__SHIFT 0x10 +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT__SHIFT 0x11 +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT__SHIFT 0x12 +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT__SHIFT 0x13 +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT__SHIFT 0x14 +#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT__SHIFT 0x15 +#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT__SHIFT 0x16 +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX0_RDY_INT_STAT__SHIFT 0x17 +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX2_RDY_INT_STAT__SHIFT 0x19 +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX3_RDY_INT_STAT__SHIFT 0x1a +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX4_RDY_INT_STAT__SHIFT 0x1b +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_OUTBOX0_RSP_INT_STAT__SHIFT 0x1c +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER0_INT_STAT_MASK 0x00000001L +#define DMCUB_INTERRUPT_STATUS__DMCUB_TIMER1_INT_STAT_MASK 0x00000002L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_READY_INT_STAT_MASK 0x00000004L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX0_DONE_INT_STAT_MASK 0x00000008L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_READY_INT_STAT_MASK 0x00000010L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INBOX1_DONE_INT_STAT_MASK 0x00000020L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_READY_INT_STAT_MASK 0x00000040L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX0_DONE_INT_STAT_MASK 0x00000080L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_READY_INT_STAT_MASK 0x00000100L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OUTBOX1_DONE_INT_STAT_MASK 0x00000200L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT0_INT_STAT_MASK 0x00000400L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT1_INT_STAT_MASK 0x00000800L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT2_INT_STAT_MASK 0x00001000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT3_INT_STAT_MASK 0x00002000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT4_INT_STAT_MASK 0x00004000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT5_INT_STAT_MASK 0x00008000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT6_INT_STAT_MASK 0x00010000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_GPINT_IH_INT_STAT_MASK 0x00020000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_UNDEFINED_ADDRESS_FAULT_MASK 0x00040000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_INST_FETCH_FAULT_MASK 0x00080000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_DATA_WRITE_FAULT_MASK 0x00100000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_PWR_UP_TRIG_INT_STAT_MASK 0x00200000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_OTG_RESYNC_TRIG_INT_STAT_MASK 0x00400000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX0_RDY_INT_STAT_MASK 0x00800000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX2_RDY_INT_STAT_MASK 0x02000000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX3_RDY_INT_STAT_MASK 0x04000000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_INBOX4_RDY_INT_STAT_MASK 0x08000000L +#define DMCUB_INTERRUPT_STATUS__DMCUB_REG_OUTBOX0_RSP_INT_STAT_MASK 0x10000000L +//DMCUB_INTERRUPT_TYPE +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE__SHIFT 0x0 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE__SHIFT 0x1 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE__SHIFT 0x2 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE__SHIFT 0x3 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE__SHIFT 0x4 +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE__SHIFT 0x5 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE__SHIFT 0x6 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE__SHIFT 0x7 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE__SHIFT 0x8 +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE__SHIFT 0x9 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE__SHIFT 0xa +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE__SHIFT 0xb +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE__SHIFT 0xc +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE__SHIFT 0xd +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE__SHIFT 0xe +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE__SHIFT 0xf +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE__SHIFT 0x10 +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE__SHIFT 0x11 +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE__SHIFT 0x12 +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER0_INT_TYPE_MASK 0x00000001L +#define DMCUB_INTERRUPT_TYPE__DMCUB_TIMER1_INT_TYPE_MASK 0x00000002L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_READY_INT_TYPE_MASK 0x00000004L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX0_DONE_INT_TYPE_MASK 0x00000008L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_READY_INT_TYPE_MASK 0x00000010L +#define DMCUB_INTERRUPT_TYPE__DMCUB_INBOX1_DONE_INT_TYPE_MASK 0x00000020L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_READY_INT_TYPE_MASK 0x00000040L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX0_DONE_INT_TYPE_MASK 0x00000080L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_READY_INT_TYPE_MASK 0x00000100L +#define DMCUB_INTERRUPT_TYPE__DMCUB_OUTBOX1_DONE_INT_TYPE_MASK 0x00000200L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT0_INT_TYPE_MASK 0x00000400L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT1_INT_TYPE_MASK 0x00000800L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT2_INT_TYPE_MASK 0x00001000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT3_INT_TYPE_MASK 0x00002000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT4_INT_TYPE_MASK 0x00004000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT5_INT_TYPE_MASK 0x00008000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT6_INT_TYPE_MASK 0x00010000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_GPINT_IH_INT_TYPE_MASK 0x00020000L +#define DMCUB_INTERRUPT_TYPE__DMCUB_UNDEFINED_ADDRESS_FAULT_INT_TYPE_MASK 0x00040000L +//DMCUB_EXT_INTERRUPT_STATUS +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID__SHIFT 0x8 +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_COUNT_MASK 0x000000FFL +#define DMCUB_EXT_INTERRUPT_STATUS__DMCUB_EXT_INTERRUPT_ID_MASK 0x0000FF00L +//DMCUB_EXT_INTERRUPT_CTXID +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_CTXID__DMCUB_EXT_INTERRUPT_CTXID_MASK 0x0FFFFFFFL +//DMCUB_EXT_INTERRUPT_ACK +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK__SHIFT 0x0 +#define DMCUB_EXT_INTERRUPT_ACK__DMCUB_EXT_INTERRUPT_ACK_MASK 0x00000001L +//DMCUB_INST_FETCH_FAULT_ADDR +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_INST_FETCH_FAULT_ADDR__DMCUB_INST_FETCH_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_DATA_WRITE_FAULT_ADDR +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_DATA_WRITE_FAULT_ADDR__DMCUB_DATA_WRITE_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_SEC_CNTL +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL__SHIFT 0x0 +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID__SHIFT 0x8 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET__SHIFT 0x10 +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE__SHIFT 0x11 +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS__SHIFT 0x14 +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS__SHIFT 0x15 +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR__SHIFT 0x18 +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR__SHIFT 0x19 +#define DMCUB_SEC_CNTL__DMCUB_MEM_SEC_LVL_MASK 0x00000007L +#define DMCUB_SEC_CNTL__DMCUB_MEM_UNIT_ID_MASK 0x00003F00L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_MASK 0x00010000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_FAULT_INT_DISABLE_MASK 0x00020000L +#define DMCUB_SEC_CNTL__DMCUB_AUTO_RESET_STATUS_MASK 0x00100000L +#define DMCUB_SEC_CNTL__DMCUB_SEC_RESET_STATUS_MASK 0x00200000L +#define DMCUB_SEC_CNTL__DMCUB_INST_FETCH_FAULT_CLEAR_MASK 0x01000000L +#define DMCUB_SEC_CNTL__DMCUB_DATA_WRITE_FAULT_CLEAR_MASK 0x02000000L +//DMCUB_MEM_CNTL +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS__SHIFT 0x0 +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS__SHIFT 0x4 +#define DMCUB_MEM_CNTL__DMCUB_MEM_WRITE_QOS_MASK 0x0000000FL +#define DMCUB_MEM_CNTL__DMCUB_MEM_READ_QOS_MASK 0x000000F0L +//DMCUB_INBOX0_BASE_ADDRESS +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX0_BASE_ADDRESS__DMCUB_INBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_SIZE +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE__SHIFT 0x0 +#define DMCUB_INBOX0_SIZE__DMCUB_INBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_WPTR +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR__SHIFT 0x0 +#define DMCUB_INBOX0_WPTR__DMCUB_INBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX0_RPTR +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR__SHIFT 0x0 +#define DMCUB_INBOX0_RPTR__DMCUB_INBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_BASE_ADDRESS +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_INBOX1_BASE_ADDRESS__DMCUB_INBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_SIZE +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE__SHIFT 0x0 +#define DMCUB_INBOX1_SIZE__DMCUB_INBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_WPTR +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR__SHIFT 0x0 +#define DMCUB_INBOX1_WPTR__DMCUB_INBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_INBOX1_RPTR +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR__SHIFT 0x0 +#define DMCUB_INBOX1_RPTR__DMCUB_INBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_BASE_ADDRESS +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX0_BASE_ADDRESS__DMCUB_OUTBOX0_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_SIZE +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX0_SIZE__DMCUB_OUTBOX0_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_WPTR +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_WPTR__DMCUB_OUTBOX0_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX0_RPTR +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX0_RPTR__DMCUB_OUTBOX0_RPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_BASE_ADDRESS +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS__SHIFT 0x0 +#define DMCUB_OUTBOX1_BASE_ADDRESS__DMCUB_OUTBOX1_BASE_ADDRESS_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_SIZE +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE__SHIFT 0x0 +#define DMCUB_OUTBOX1_SIZE__DMCUB_OUTBOX1_SIZE_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_WPTR +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_WPTR__DMCUB_OUTBOX1_WPTR_MASK 0xFFFFFFFFL +//DMCUB_OUTBOX1_RPTR +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR__SHIFT 0x0 +#define DMCUB_OUTBOX1_RPTR__DMCUB_OUTBOX1_RPTR_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER0__DMCUB_TIMER_TRIGGER0_MASK 0xFFFFFFFFL +//DMCUB_TIMER_TRIGGER1 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1__SHIFT 0x0 +#define DMCUB_TIMER_TRIGGER1__DMCUB_TIMER_TRIGGER1_MASK 0xFFFFFFFFL +//DMCUB_TIMER_WINDOW +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW__SHIFT 0x0 +#define DMCUB_TIMER_WINDOW__DMCUB_TIMER_WINDOW_MASK 0x00000007L +//DMCUB_SCRATCH0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0__SHIFT 0x0 +#define DMCUB_SCRATCH0__DMCUB_SCRATCH0_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH1 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1__SHIFT 0x0 +#define DMCUB_SCRATCH1__DMCUB_SCRATCH1_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH2 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2__SHIFT 0x0 +#define DMCUB_SCRATCH2__DMCUB_SCRATCH2_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH3 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3__SHIFT 0x0 +#define DMCUB_SCRATCH3__DMCUB_SCRATCH3_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH4 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4__SHIFT 0x0 +#define DMCUB_SCRATCH4__DMCUB_SCRATCH4_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH5 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5__SHIFT 0x0 +#define DMCUB_SCRATCH5__DMCUB_SCRATCH5_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH6 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6__SHIFT 0x0 +#define DMCUB_SCRATCH6__DMCUB_SCRATCH6_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH7 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7__SHIFT 0x0 +#define DMCUB_SCRATCH7__DMCUB_SCRATCH7_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH8 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8__SHIFT 0x0 +#define DMCUB_SCRATCH8__DMCUB_SCRATCH8_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH9 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9__SHIFT 0x0 +#define DMCUB_SCRATCH9__DMCUB_SCRATCH9_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH10 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10__SHIFT 0x0 +#define DMCUB_SCRATCH10__DMCUB_SCRATCH10_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH11 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11__SHIFT 0x0 +#define DMCUB_SCRATCH11__DMCUB_SCRATCH11_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH12 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12__SHIFT 0x0 +#define DMCUB_SCRATCH12__DMCUB_SCRATCH12_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH13 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13__SHIFT 0x0 +#define DMCUB_SCRATCH13__DMCUB_SCRATCH13_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH14 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14__SHIFT 0x0 +#define DMCUB_SCRATCH14__DMCUB_SCRATCH14_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH15 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15__SHIFT 0x0 +#define DMCUB_SCRATCH15__DMCUB_SCRATCH15_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH16 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16__SHIFT 0x0 +#define DMCUB_SCRATCH16__DMCUB_SCRATCH16_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH17 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17__SHIFT 0x0 +#define DMCUB_SCRATCH17__DMCUB_SCRATCH17_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH18 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18__SHIFT 0x0 +#define DMCUB_SCRATCH18__DMCUB_SCRATCH18_MASK 0xFFFFFFFFL +//DMCUB_CNTL +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY__SHIFT 0x0 +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS__SHIFT 0x8 +#define DMCUB_CNTL__DMCUB_ENABLE__SHIFT 0x10 +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE__SHIFT 0x12 +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN__SHIFT 0x13 +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS__SHIFT 0x14 +#define DMCUB_CNTL__DMCUB_LS_WAKE_DELAY_MASK 0x000000FFL +#define DMCUB_CNTL__DMCUB_DMCUBCLK_R_GATE_DIS_MASK 0x00000100L +#define DMCUB_CNTL__DMCUB_ENABLE_MASK 0x00010000L +#define DMCUB_CNTL__DMCUB_MEM_LIGHT_SLEEP_DISABLE_MASK 0x00040000L +#define DMCUB_CNTL__DMCUB_TRACEPORT_EN_MASK 0x00080000L +#define DMCUB_CNTL__DMCUB_PWAIT_MODE_STATUS_MASK 0x00100000L +//DMCUB_GPINT_DATAIN0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN0__DMCUB_GPINT_DATAIN0_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN1 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN1__DMCUB_GPINT_DATAIN1_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAOUT +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT__SHIFT 0x0 +#define DMCUB_GPINT_DATAOUT__DMCUB_GPINT_DATAOUT_MASK 0xFFFFFFFFL +//DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__SHIFT 0x0 +#define DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR__DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_MASK 0xFFFFFFFFL +//DMCUB_LS_WAKE_INT_ENABLE +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE__SHIFT 0x0 +#define DMCUB_LS_WAKE_INT_ENABLE__DMCUB_LS_WAKE_INT_ENABLE_MASK 0xFFFFFFFFL +//DMCUB_MEM_PWR_CNTL +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE__SHIFT 0x1 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS__SHIFT 0x3 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE__SHIFT 0x4 +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_FORCE_MASK 0x00000006L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_DIS_MASK 0x00000008L +#define DMCUB_MEM_PWR_CNTL__DMCUB_MEM_PWR_STATE_MASK 0x00000030L +//DMCUB_TIMER_CURRENT +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT__SHIFT 0x0 +#define DMCUB_TIMER_CURRENT__DMCUB_TIMER_CURRENT_MASK 0xFFFFFFFFL +//DMCUB_PROC_ID +#define DMCUB_PROC_ID__DMCUB_PROC_ID__SHIFT 0x0 +#define DMCUB_PROC_ID__DMCUB_PROC_ID_MASK 0x0000FFFFL +//DMCUB_CNTL2 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET__SHIFT 0x0 +#define DMCUB_CNTL2__DMCUB_SOFT_RESET_MASK 0x00000001L +//DMCUB_GPINT_DATAIN2 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN2__DMCUB_GPINT_DATAIN2_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN3 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN3__DMCUB_GPINT_DATAIN3_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN4 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN4__DMCUB_GPINT_DATAIN4_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN5 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN5__DMCUB_GPINT_DATAIN5_MASK 0xFFFFFFFFL +//DMCUB_GPINT_DATAIN6 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6__SHIFT 0x0 +#define DMCUB_GPINT_DATAIN6__DMCUB_GPINT_DATAIN6_MASK 0xFFFFFFFFL +//DMCUB_REGION3_TMR_AXI_SPACE +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE__SHIFT 0x0 +#define DMCUB_REGION3_TMR_AXI_SPACE__DMCUB_REGION3_TMR_AXI_SPACE_MASK 0x07L +//DMCUB_SCRATCH19 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19__SHIFT 0x0 +#define DMCUB_SCRATCH19__DMCUB_SCRATCH19_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH20 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20__SHIFT 0x0 +#define DMCUB_SCRATCH20__DMCUB_SCRATCH20_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH21 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21__SHIFT 0x0 +#define DMCUB_SCRATCH21__DMCUB_SCRATCH21_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH22 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22__SHIFT 0x0 +#define DMCUB_SCRATCH22__DMCUB_SCRATCH22_MASK 0xFFFFFFFFL +//DMCUB_SCRATCH23 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23__SHIFT 0x0 +#define DMCUB_SCRATCH23__DMCUB_SCRATCH23_MASK 0xFFFFFFFFL +//HOST_INTERRUPT_CSR +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_EN__SHIFT 0x0 +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_EN__SHIFT 0x1 +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_ACK__SHIFT 0x8 +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_ACK__SHIFT 0x9 +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_STAT__SHIFT 0xc +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_STAT__SHIFT 0xd +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_EN_MASK 0x00000001L +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_EN_MASK 0x00000002L +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_ACK_MASK 0x00000100L +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_ACK_MASK 0x00000200L +#define HOST_INTERRUPT_CSR__HOST_REG_INBOX0_RSP_INT_STAT_MASK 0x00001000L +#define HOST_INTERRUPT_CSR__HOST_REG_OUTBOX0_RDY_INT_STAT_MASK 0x00002000L +//DMCUB_REG_INBOX0_RDY +#define DMCUB_REG_INBOX0_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG0 +#define DMCUB_REG_INBOX0_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG1 +#define DMCUB_REG_INBOX0_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG2 +#define DMCUB_REG_INBOX0_MSG2__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG2__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG3 +#define DMCUB_REG_INBOX0_MSG3__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG3__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG4 +#define DMCUB_REG_INBOX0_MSG4__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG4__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG5 +#define DMCUB_REG_INBOX0_MSG5__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG5__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG6 +#define DMCUB_REG_INBOX0_MSG6__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG6__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG7 +#define DMCUB_REG_INBOX0_MSG7__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG7__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG8 +#define DMCUB_REG_INBOX0_MSG8__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG8__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG9 +#define DMCUB_REG_INBOX0_MSG9__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG9__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG10 +#define DMCUB_REG_INBOX0_MSG10__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG10__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG11 +#define DMCUB_REG_INBOX0_MSG11__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG11__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG12 +#define DMCUB_REG_INBOX0_MSG12__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG12__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG13 +#define DMCUB_REG_INBOX0_MSG13__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG13__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_MSG14 +#define DMCUB_REG_INBOX0_MSG14__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_MSG14__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX0_RSP +#define DMCUB_REG_INBOX0_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX0_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_OUTBOX0_RDY +#define DMCUB_REG_OUTBOX0_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_OUTBOX0_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_OUTBOX0_MSG0 +#define DMCUB_REG_OUTBOX0_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_OUTBOX0_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_OUTBOX0_RSP +#define DMCUB_REG_OUTBOX0_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_OUTBOX0_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_RDY +#define DMCUB_REG_INBOX1_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_MSG0 +#define DMCUB_REG_INBOX1_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_MSG1 +#define DMCUB_REG_INBOX1_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_RSP +#define DMCUB_REG_INBOX1_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX1_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX1_INTERRUPT_CSR +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_EN__SHIFT 0x0 +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_ACK__SHIFT 0x1 +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_STAT__SHIFT 0x2 +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_EN_MASK 0x00000001L +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_ACK_MASK 0x00000002L +#define DMCUB_REG_INBOX1_INTERRUPT_CSR__DMCUB_REG_INBOX1_RDY_INT_STAT_MASK 0x00000004L +//DMCUB_REG_INBOX2_RDY +#define DMCUB_REG_INBOX2_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX2_MSG0 +#define DMCUB_REG_INBOX2_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX2_MSG1 +#define DMCUB_REG_INBOX2_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX2_RSP +#define DMCUB_REG_INBOX2_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX2_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_RDY +#define DMCUB_REG_INBOX3_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_MSG0 +#define DMCUB_REG_INBOX3_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_MSG1 +#define DMCUB_REG_INBOX3_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX3_RSP +#define DMCUB_REG_INBOX3_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX3_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_RDY +#define DMCUB_REG_INBOX4_RDY__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_RDY__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_MSG0 +#define DMCUB_REG_INBOX4_MSG0__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_MSG0__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_MSG1 +#define DMCUB_REG_INBOX4_MSG1__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_MSG1__DATA_MASK 0xFFFFFFFFL +//DMCUB_REG_INBOX4_RSP +#define DMCUB_REG_INBOX4_RSP__DATA__SHIFT 0x0 +#define DMCUB_REG_INBOX4_RSP__DATA_MASK 0xFFFFFFFFL +//DMCUB_IDLE_HYSTERESIS_CSR +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_ENABLE__SHIFT 0x0 +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_STATE__SHIFT 0x1 +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_THRESHOLD__SHIFT 0x10 +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_ENABLE_MASK 0x00000001L +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_STATE_MASK 0x00000002L +#define DMCUB_IDLE_HYSTERESIS_CSR__IDLE_HYSTERESIS_THRESHOLD_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec +//MCIF_WB_BUFMGR_SW_CONTROL +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN__SHIFT 0x7 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN__SHIFT 0x18 +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x00000010L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x00000020L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x00000040L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN_MASK 0x00000080L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_ADDR_FENCE_EN_MASK 0x01000000L +//MCIF_WB_BUFMGR_STATUS +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x0 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS__SHIFT 0x1 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x00000001L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS_MASK 0x00000002L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x00000070L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x00000080L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x01FFF000L +#define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000L +//MCIF_WB_BUF_PITCH +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18 +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0x0000FF00L +#define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xFF000000L +//MCIF_WB_BUF_1_STATUS +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_1_STATUS2 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_BUF_2_STATUS +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_STATUS2 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_BUF_3_STATUS +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_STATUS2 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_BUF_4_STATUS +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x00000001L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x00000002L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x00000004L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x00000008L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x00000010L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0x000000E0L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0x00000F00L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x00007000L +#define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_STATUS2 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL__SHIFT 0xf +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ__SHIFT 0x10 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN__SHIFT 0x14 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN__SHIFT 0x15 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG__SHIFT 0x16 +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x00002000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x00004000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_BLACK_PIXEL_MASK 0x00008000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_TMZ_MASK 0x000F0000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_Y_OVERRUN_MASK 0x00100000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_C_OVERRUN_MASK 0x00200000L +#define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_EYE_FLAG_MASK 0x00400000L +//MCIF_WB_ARBITRATION_CONTROL +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x14 +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x00000003L +#define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xFFF00000L +//MCIF_WB_SCLK_CHANGE +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON__SHIFT 0x0 +#define MCIF_WB_SCLK_CHANGE__WM_CHANGE_ACK_FORCE_ON_MASK 0x00000001L +//MCIF_WB_TEST_DEBUG_INDEX +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MCIF_WB_TEST_DEBUG_DATA +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0 +#define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_Y +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_1_ADDR_C +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_Y +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_2_ADDR_C +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_Y +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_3_ADDR_C +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_Y +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xFFFFFFFFL +//MCIF_WB_BUF_4_ADDR_C +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xFFFFFFFFL +//MCIF_WB_BUFMGR_VCE_CONTROL +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10 +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x00000001L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0x00000F00L +#define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1FFF0000L +//MCIF_WB_NB_PSTATE_CONTROL +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x1 +#define MCIF_WB_NB_PSTATE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000002L +//MCIF_WB_CLOCK_GATER_CONTROL +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE__SHIFT 0x0 +#define MCIF_WB_CLOCK_GATER_CONTROL__MCIF_WB_CLI_CLOCK_GATER_OVERRIDE_MASK 0x00000001L +//MCIF_WB_SELF_REFRESH_CONTROL +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH__SHIFT 0x1 +#define MCIF_WB_SELF_REFRESH_CONTROL__PERFRAME_SELF_REFRESH_MASK 0x00000002L +//MULTI_LEVEL_QOS_CTRL +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0 +#define MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL +//MCIF_WB_SECURITY_LEVEL +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE__SHIFT 0x4 +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L +#define MCIF_WB_SECURITY_LEVEL__MCIF_WB_SPACE_MASK 0x00000070L +//MCIF_WB_BUF_LUMA_SIZE +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_CHROMA_SIZE +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE__SHIFT 0x0 +#define MCIF_WB_BUF_CHROMA_SIZE__MCIF_WB_BUF_CHROMA_SIZE_MASK 0x000FFFFFL +//MCIF_WB_BUF_1_ADDR_Y_HIGH +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_Y_HIGH__MCIF_WB_BUF_1_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_ADDR_C_HIGH +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_1_ADDR_C_HIGH__MCIF_WB_BUF_1_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_Y_HIGH +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_Y_HIGH__MCIF_WB_BUF_2_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_2_ADDR_C_HIGH +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_2_ADDR_C_HIGH__MCIF_WB_BUF_2_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_Y_HIGH +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_Y_HIGH__MCIF_WB_BUF_3_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_3_ADDR_C_HIGH +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_3_ADDR_C_HIGH__MCIF_WB_BUF_3_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_Y_HIGH +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_Y_HIGH__MCIF_WB_BUF_4_ADDR_Y_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_4_ADDR_C_HIGH +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH__SHIFT 0x0 +#define MCIF_WB_BUF_4_ADDR_C_HIGH__MCIF_WB_BUF_4_ADDR_C_HIGH_MASK 0x000000FFL +//MCIF_WB_BUF_1_RESOLUTION +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_1_RESOLUTION__MCIF_WB_BUF_1_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_2_RESOLUTION +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_2_RESOLUTION__MCIF_WB_BUF_2_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_3_RESOLUTION +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_3_RESOLUTION__MCIF_WB_BUF_3_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_BUF_4_RESOLUTION +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH__SHIFT 0x0 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT__SHIFT 0x10 +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_WIDTH_MASK 0x00001FFFL +#define MCIF_WB_BUF_4_RESOLUTION__MCIF_WB_BUF_4_RESOLUTION_HEIGHT_MASK 0x1FFF0000L +//MCIF_WB_PSTATE_CHANGE_DURATION_VBI +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x0 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI__SHIFT 0x10 +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_UCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0x0000FFFFL +#define MCIF_WB_PSTATE_CHANGE_DURATION_VBI__MCIF_WB_FCLK_PSTATE_CHANGE_DURATION_VBI_MASK 0xFFFF0000L +//MCIF_WB_VMID_CONTROL +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID__SHIFT 0x0 +#define MCIF_WB_VMID_CONTROL__MCIF_WB_P_VMID_MASK 0x0000000FL +//MCIF_WB_MIN_TTO +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO__SHIFT 0x0 +#define MCIF_WB_MIN_TTO__MCIF_WB_MIN_TTO_MASK 0x0007FFFFL +//MCIF_WB_TMZ +#define MCIF_WB_TMZ__MCIF_WB_TMZ__SHIFT 0x0 +#define MCIF_WB_TMZ__MCIF_WB_TMZ_MASK 0x0000000FL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec +//MCIF_WB_NB_PSTATE_LATENCY_WATERMARK +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK__SHIFT 0x0 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE__SHIFT 0x1f +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_REFRESH_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_MASK_MASK 0x07000000L +#define MCIF_WB_NB_PSTATE_LATENCY_WATERMARK__NB_PSTATE_CHANGE_WATERMARK_TYPE_MASK 0x80000000L +//MCIF_WB_WATERMARK +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK__SHIFT 0x0 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK__SHIFT 0x18 +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK 0x001FFFFFL +#define MCIF_WB_WATERMARK__MCIF_WB_CLI_WATERMARK_MASK_MASK 0x07000000L +//MMHUBBUB_WARMUP_CONFIG +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS__SHIFT 0x10 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID__SHIFT 0x14 +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_QOS_MASK 0x000F0000L +#define MMHUBBUB_WARMUP_CONFIG__MMHUBBUB_WARMUP_AWID_MASK 0x00F00000L +//MMHUBBUB_WARMUP_CONTROL_STATUS +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN__SHIFT 0x0 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN__SHIFT 0x4 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS__SHIFT 0x5 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK__SHIFT 0x6 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR__SHIFT 0x8 +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_EN_MASK 0x00000001L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_EN_MASK 0x00000010L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_STATUS_MASK 0x00000020L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_SW_INT_ACK_MASK 0x00000040L +#define MMHUBBUB_WARMUP_CONTROL_STATUS__MMHUBBUB_WARMUP_INC_ADDR_MASK 0x03FFFF00L +//MMHUBBUB_WARMUP_BASE_ADDR_LOW +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_LOW__MMHUBBUB_WARMUP_BASE_ADDR_LOW_MASK 0xFFFFFFFFL +//MMHUBBUB_WARMUP_BASE_ADDR_HIGH +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH__SHIFT 0x0 +#define MMHUBBUB_WARMUP_BASE_ADDR_HIGH__MMHUBBUB_WARMUP_BASE_ADDR_HIGH_MASK 0x000007FFL +//MMHUBBUB_WARMUP_ADDR_REGION +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION__SHIFT 0x0 +#define MMHUBBUB_WARMUP_ADDR_REGION__MMHUBBUB_WARMUP_ADDR_REGION_MASK 0x07FFFFFFL +//MMHUBBUB_MIN_TTO +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO__SHIFT 0x0 +#define MMHUBBUB_MIN_TTO__MMHUBBUB_MIN_TTO_MASK 0x0007FFFFL +//MMHUBBUB_CTRL +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE__SHIFT 0x0 +#define MMHUBBUB_CTRL__MMHUB_SOCCLK_DS_MODE_MASK 0x00000003L +//WBIF_SMU_WM_CONTROL +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL__SHIFT 0x14 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ__SHIFT 0x16 +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_SEL_MASK 0x00300000L +#define WBIF_SMU_WM_CONTROL__MCIF_WB_WM_CHG_REQ_MASK 0x00400000L +//WBIF0_MISC_CTRL +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH__SHIFT 0x0 +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE__SHIFT 0x10 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS__SHIFT 0x18 +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS__SHIFT 0x19 +#define WBIF0_MISC_CTRL__MCIFWB0_WR_COMBINE_TIMEOUT_THRESH_MASK 0x000003FFL +#define WBIF0_MISC_CTRL__MCIF_WB0_SOCCLK_DS_ENABLE_MASK 0x00010000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_DIS_MASK 0x01000000L +#define WBIF0_MISC_CTRL__MCIF_WB0_WM_CHG_ACK_INT_STATUS_MASK 0x02000000L +//WBIF0_PHASE0_OUTSTANDING_COUNTER +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE0_OUTSTANDING_COUNTER__MCIF_WB0_PHASE0_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//WBIF0_PHASE1_OUTSTANDING_COUNTER +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER__SHIFT 0x0 +#define WBIF0_PHASE1_OUTSTANDING_COUNTER__MCIF_WB0_PHASE1_OUTSTANDING_COUNTER_MASK 0x07FFFFFFL +//MMHUBBUB_MEM_PWR_STATUS +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE__SHIFT 0x0 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE__SHIFT 0x6 +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM0_PWR_STATE_MASK 0x00000003L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_LUMA_MEM1_PWR_STATE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM0_PWR_STATE_MASK 0x00000030L +#define MMHUBBUB_MEM_PWR_STATUS__MCIF_DWB0_CHROMA_MEM1_PWR_STATE_MASK 0x000000C0L +//MMHUBBUB_MEM_PWR_CNTL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE__SHIFT 0x2 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS__SHIFT 0x4 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL__SHIFT 0x5 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM__SHIFT 0x7 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM__SHIFT 0x8 +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_FORCE_MASK 0x0000000CL +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_DIS_MASK 0x00000010L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_MEM_PWR_MODE_SEL_MASK 0x00000060L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_LUMA_MEM_EN_NUM_MASK 0x00000080L +#define MMHUBBUB_MEM_PWR_CNTL__MCIF_DWB0_CHROMA_MEM_EN_NUM_MASK 0x00000100L +//MMHUBBUB_CLOCK_CNTL +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS__SHIFT 0x5 +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS__SHIFT 0x9 +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS__SHIFT 0xa +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS__SHIFT 0x11 +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_R_MMHUBBUB_GATE_DIS_MASK 0x00000020L +#define MMHUBBUB_CLOCK_CNTL__DISPCLK_G_WBIF0_GATE_DIS_MASK 0x00000200L +#define MMHUBBUB_CLOCK_CNTL__SOCCLK_G_WBIF0_GATE_DIS_MASK 0x00000400L +#define MMHUBBUB_CLOCK_CNTL__MMHUBBUB_FGCG_REP_DIS_MASK 0x00020000L +//MMHUBBUB_SOFT_RESET +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET__SHIFT 0x2 +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET__SHIFT 0x8 +#define MMHUBBUB_SOFT_RESET__WBIF0_SOFT_RESET_MASK 0x00000004L +#define MMHUBBUB_SOFT_RESET__DMUIF_SOFT_RESET_MASK 0x00000100L +//DMU_IF_ERR_STATUS +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR__SHIFT 0x0 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR__SHIFT 0x4 +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_MASK 0x00000001L +#define DMU_IF_ERR_STATUS__DMU_RD_OUTSTANDING_ERR_CLR_MASK 0x00000010L +//MMHUBBUB_CLIENT_UNIT_ID +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID__SHIFT 0x8 +#define MMHUBBUB_CLIENT_UNIT_ID__WBIF0_UNIT_ID_MASK 0x00003F00L +//MMHUBBUB_WARMUP_SECURITY_CFG +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_UNITID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SECURE_LVL__SHIFT 0x8 +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SPACE__SHIFT 0x10 +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_UNITID_MASK 0x0000003FL +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SECURE_LVL_MASK 0x00000700L +#define MMHUBBUB_WARMUP_SECURITY_CFG__MMHUBBUB_WARMUP_SPACE_MASK 0x00070000L +//MMHUBBUB_WARMUP_VMID_CONTROL +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID__SHIFT 0x0 +#define MMHUBBUB_WARMUP_VMID_CONTROL__MMHUBBUB_WARMUP_P_VMID_MASK 0x0000000FL + + +// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON3_PERFCOUNTER_CNTL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_CNTL2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON3_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFCOUNTER_STATE +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON3_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON3_PERFMON_CNTL +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON3_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON3_PERFMON_CNTL2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON3_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON3_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON3_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON3_PERFMON_CVALUE_LOW +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON3_PERFMON_HI +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON3_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON3_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON3_PERFMON_LOW +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON3_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream0_dispdec +//AZF0STREAM0_AZALIA_STREAM_INDEX +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM0_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM0_AZALIA_STREAM_DATA +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM0_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream1_dispdec +//AZF0STREAM1_AZALIA_STREAM_INDEX +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM1_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM1_AZALIA_STREAM_DATA +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM1_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream2_dispdec +//AZF0STREAM2_AZALIA_STREAM_INDEX +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM2_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM2_AZALIA_STREAM_DATA +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM2_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream3_dispdec +//AZF0STREAM3_AZALIA_STREAM_INDEX +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM3_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM3_AZALIA_STREAM_DATA +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM3_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream4_dispdec +//AZF0STREAM4_AZALIA_STREAM_INDEX +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM4_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM4_AZALIA_STREAM_DATA +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM4_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream5_dispdec +//AZF0STREAM5_AZALIA_STREAM_INDEX +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM5_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM5_AZALIA_STREAM_DATA +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM5_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream6_dispdec +//AZF0STREAM6_AZALIA_STREAM_INDEX +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM6_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM6_AZALIA_STREAM_DATA +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM6_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream7_dispdec +//AZF0STREAM7_AZALIA_STREAM_INDEX +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM7_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM7_AZALIA_STREAM_DATA +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM7_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_az_misc_dispdec +//AZ_CLOCK_CNTL +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS__SHIFT 0x0 +#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS__SHIFT 0x1 +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x4 +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS__SHIFT 0x8 +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL__SHIFT 0xc +#define AZ_CLOCK_CNTL__SCLK_GATE_DIS__SHIFT 0x10 +#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY__SHIFT 0x14 +#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY__SHIFT 0x18 +#define AZ_CLOCK_CNTL__SCLK_G_STREAM_AZ_GATE_DIS_MASK 0x00000001L +#define AZ_CLOCK_CNTL__AZ_GLOBAL_FGCG_REP_DIS_MASK 0x00000002L +#define AZ_CLOCK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000010L +#define AZ_CLOCK_CNTL__SCLK_G_CNTL_AZ_GATE_DIS_MASK 0x00000100L +#define AZ_CLOCK_CNTL__DCIPG_TEST_CLK_SEL_MASK 0x0000F000L +#define AZ_CLOCK_CNTL__SCLK_GATE_DIS_MASK 0x00010000L +#define AZ_CLOCK_CNTL__SCLK_TURN_ON_DELAY_MASK 0x00F00000L +#define AZ_CLOCK_CNTL__SCLK_TURN_OFF_DELAY_MASK 0xFF000000L +//AZ_MEM_GLOBAL_PWR_REQ_CNTL +#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x0 +#define AZ_MEM_GLOBAL_PWR_REQ_CNTL__AZ_MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001L +//AZ_STRAPS +#define AZ_STRAPS__AUDIO_PORT_CONNECTIVITY__SHIFT 0x0 +#define AZ_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x4 +#define AZ_STRAPS__AUDIO_PORT_CONNECTIVITY_MASK 0x00000007L +#define AZ_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x00000070L + + +// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON4_PERFCOUNTER_CNTL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_CNTL2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON4_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFCOUNTER_STATE +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON4_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON4_PERFMON_CNTL +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON4_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON4_PERFMON_CNTL2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON4_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON4_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON4_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON4_PERFMON_CVALUE_LOW +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON4_PERFMON_HI +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON4_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON4_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON4_PERFMON_LOW +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON4_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint0_dispdec +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint1_dispdec +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint2_dispdec +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint3_dispdec +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint4_dispdec +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint5_dispdec +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint6_dispdec +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0endpoint7_dispdec +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0controller_dispdec +//AZALIA_CONTROLLER_CLOCK_GATING +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING__SHIFT 0x0 +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE__SHIFT 0x4 +#define AZALIA_CONTROLLER_CLOCK_GATING__ENABLE_CLOCK_GATING_MASK 0x00000001L +#define AZALIA_CONTROLLER_CLOCK_GATING__CLOCK_ON_STATE_MASK 0x00000010L +//AZALIA_AUDIO_DTO +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x0 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x10 +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000FFFFL +#define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xFFFF0000L +//AZALIA_AUDIO_DTO_CONTROL +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x8 +#define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L +//AZALIA_SOCCLK_CONTROL +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN__SHIFT 0x1 +#define AZALIA_SOCCLK_CONTROL__AUDIO_STREAM_SOCCLK_DEEP_SLEEP_EXIT_EN_MASK 0x00000002L +//AZALIA_UNDERFLOW_FILLER_SAMPLE +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x0 +#define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xFFFFFFFFL +//AZALIA_DATA_DMA_CONTROL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x10 +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x11 +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_DATA_DMA_CONTROL__INPUT_DATA_DMA_ISOCHRONOUS_MASK 0x000000C0L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L +#define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L +//AZALIA_BDL_DMA_CONTROL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP__SHIFT 0x2 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS__SHIFT 0x6 +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_NON_SNOOP_MASK 0x0000000CL +#define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L +#define AZALIA_BDL_DMA_CONTROL__INPUT_BDL_DMA_ISOCHRONOUS_MASK 0x000000C0L +//AZALIA_RIRB_AND_DP_CONTROL +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x0 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x4 +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER__SHIFT 0x5 +#define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L +#define AZALIA_RIRB_AND_DP_CONTROL__DP_UPDATE_FREQ_DIVIDER_MASK 0x000001E0L +//AZALIA_CORB_DMA_CONTROL +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x0 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x4 +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L +#define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L +//AZALIA_GLOBAL_CAPABILITIES +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L +//AZALIA_OUTPUT_PAYLOAD_CAPABILITY +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x10 +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFF0000L +//AZALIA_OUTPUT_STREAM_ARBITER_CONTROL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x0 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x8 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL__SHIFT 0x10 +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000FFL +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L +#define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__INPUT_LATENCY_HIDING_LEVEL_MASK 0x00FF0000L +//AZALIA_INPUT_PAYLOAD_CAPABILITY +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x10 +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0x0000FFFFL +#define AZALIA_INPUT_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFF0000L +//AZALIA_INPUT_CRC0_CONTROL0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_CONTROL1 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC0_CONTROL2 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC0_CONTROL3 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC0_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC0_RESULT +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC0_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_EN_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL0__INPUT_CRC_INSTANCE_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_CONTROL1 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL1__INPUT_CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_INPUT_CRC1_CONTROL2 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL2__INPUT_CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_INPUT_CRC1_CONTROL3 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_INPUT_CRC1_CONTROL3__INPUT_CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_INPUT_CRC1_RESULT +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT__SHIFT 0x0 +#define AZALIA_INPUT_CRC1_RESULT__INPUT_CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL0 +#define AZALIA_CRC0_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC0_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC0_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC0_CONTROL1 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC0_CONTROL2 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC0_CONTROL3 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC0_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC0_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC0_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC0_RESULT +#define AZALIA_CRC0_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC0_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL0 +#define AZALIA_CRC1_CONTROL0__CRC_EN__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL__SHIFT 0xc +#define AZALIA_CRC1_CONTROL0__CRC_EN_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL0__CRC_BLOCK_MODE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL0__CRC_INSTANCE_SEL_MASK 0x00000700L +#define AZALIA_CRC1_CONTROL0__CRC_SOURCE_SEL_MASK 0x00001000L +//AZALIA_CRC1_CONTROL1 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL1__CRC_BLOCK_SIZE_MASK 0xFFFFFFFFL +//AZALIA_CRC1_CONTROL2 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL2__CRC_BLOCK_ITERATION_MASK 0x0000FFFFL +//AZALIA_CRC1_CONTROL3 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE__SHIFT 0x0 +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE__SHIFT 0x4 +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL__SHIFT 0x8 +#define AZALIA_CRC1_CONTROL3__CRC_COMPLETE_MASK 0x00000001L +#define AZALIA_CRC1_CONTROL3__CRC_BLOCK_COMPLETE_PHASE_MASK 0x00000010L +#define AZALIA_CRC1_CONTROL3__CRC_CHANNEL_RESULT_SEL_MASK 0x00000700L +//AZALIA_CRC1_RESULT +#define AZALIA_CRC1_RESULT__CRC_RESULT__SHIFT 0x0 +#define AZALIA_CRC1_RESULT__CRC_RESULT_MASK 0xFFFFFFFFL +//AZALIA_MEM_PWR_CTRL +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE__SHIFT 0x0 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS__SHIFT 0x2 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE__SHIFT 0x3 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS__SHIFT 0x5 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE__SHIFT 0x6 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS__SHIFT 0x8 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE__SHIFT 0x9 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS__SHIFT 0xb +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE__SHIFT 0xc +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS__SHIFT 0xe +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE__SHIFT 0xf +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS__SHIFT 0x11 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE__SHIFT 0x12 +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS__SHIFT 0x14 +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL__SHIFT 0x1c +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_FORCE_MASK 0x00000003L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_DIS_MASK 0x00000004L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_FORCE_MASK 0x00000018L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM0_MEM_PWR_DIS_MASK 0x00000020L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_FORCE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM1_MEM_PWR_DIS_MASK 0x00000100L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_FORCE_MASK 0x00000600L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM2_MEM_PWR_DIS_MASK 0x00000800L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_FORCE_MASK 0x00003000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM3_MEM_PWR_DIS_MASK 0x00004000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_FORCE_MASK 0x00018000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM4_MEM_PWR_DIS_MASK 0x00020000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_FORCE_MASK 0x000C0000L +#define AZALIA_MEM_PWR_CTRL__AZ_INPUT_STREAM5_MEM_PWR_DIS_MASK 0x00100000L +#define AZALIA_MEM_PWR_CTRL__AZ_MEM_PWR_MODE_SEL_MASK 0x30000000L +//AZALIA_MEM_PWR_STATUS +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE__SHIFT 0x0 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE__SHIFT 0x2 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE__SHIFT 0x4 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE__SHIFT 0x6 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE__SHIFT 0x8 +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE__SHIFT 0xa +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE__SHIFT 0xc +#define AZALIA_MEM_PWR_STATUS__AZ_MEM_PWR_STATE_MASK 0x00000003L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM0_MEM_PWR_STATE_MASK 0x0000000CL +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM1_MEM_PWR_STATE_MASK 0x00000030L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM2_MEM_PWR_STATE_MASK 0x000000C0L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM3_MEM_PWR_STATE_MASK 0x00000300L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM4_MEM_PWR_STATE_MASK 0x00000C00L +#define AZALIA_MEM_PWR_STATUS__AZ_INPUT_STREAM5_MEM_PWR_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hda_azf0root_dispdec +//AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x0 +#define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x0 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x4 +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L +#define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L +//AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x0 +#define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003FL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000FFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001F0000L +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xFFFFFFFFL +//AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x1e +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x1f +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3FFFFFFFL +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L +#define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x4 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x9 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0xa +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000FL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000F0L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x8 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x10 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x18 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000FFL +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000FF00L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00FF0000L +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xFF000000L +//AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x0 +#define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x000000FFL +//CC_RCU_DC_AUDIO_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY__INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_PORT_CONNECTIVITY +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L +//REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT 0x0 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x4 +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK 0x00000007L +#define REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L + + +// addressBlock: dce_dc_hda_azf0stream8_dispdec +//AZF0STREAM8_AZALIA_STREAM_INDEX +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM8_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM8_AZALIA_STREAM_DATA +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM8_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream9_dispdec +//AZF0STREAM9_AZALIA_STREAM_INDEX +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM9_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM9_AZALIA_STREAM_DATA +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM9_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream10_dispdec +//AZF0STREAM10_AZALIA_STREAM_INDEX +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM10_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM10_AZALIA_STREAM_DATA +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM10_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream11_dispdec +//AZF0STREAM11_AZALIA_STREAM_INDEX +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM11_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM11_AZALIA_STREAM_DATA +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM11_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream12_dispdec +//AZF0STREAM12_AZALIA_STREAM_INDEX +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM12_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM12_AZALIA_STREAM_DATA +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM12_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream13_dispdec +//AZF0STREAM13_AZALIA_STREAM_INDEX +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM13_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM13_AZALIA_STREAM_DATA +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM13_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream14_dispdec +//AZF0STREAM14_AZALIA_STREAM_INDEX +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM14_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM14_AZALIA_STREAM_DATA +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM14_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0stream15_dispdec +//AZF0STREAM15_AZALIA_STREAM_INDEX +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x8 +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000FFL +#define AZF0STREAM15_AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L +//AZF0STREAM15_AZALIA_STREAM_DATA +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x0 +#define AZF0STREAM15_AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX__AZALIA_INPUT_ENDPOINT_REG_INDEX_MASK 0x00003FFFL +//AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA__SHIFT 0x0 +#define AZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA__AZALIA_INPUT_ENDPOINT_REG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec +//DCHUBBUB_SDPIF_CFG0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS__SHIFT 0x3 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS__SHIFT 0x6 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR__SHIFT 0xa +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR__SHIFT 0xb +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR__SHIFT 0xc +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN__SHIFT 0xd +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN__SHIFT 0xe +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL__SHIFT 0xf +#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY__SHIFT 0x19 +#define DCHUBBUB_SDPIF_CFG0__SDPIF_NO_OUTSTANDING_REQ_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_STATUS_MASK 0x00000006L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_DATA_RESPONSE_STATUS_MASK 0x00000038L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_MASK 0x000003C0L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_MASK 0x00000400L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_RESPONSE_STATUS_CLEAR_MASK 0x00000800L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_ERROR_CLEAR_MASK 0x00001000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_FLUSH_REQ_CREDIT_EN_MASK 0x00002000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_REQ_CREDIT_EN_MASK 0x00004000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_PORT_CONTROL_MASK 0x00008000L +#define DCHUBBUB_SDPIF_CFG0__DF_CSTATE_DISALLOW_MASK 0x00010000L +#define DCHUBBUB_SDPIF_CFG0__SDPIF_CREDIT_DISCONNECT_DELAY_MASK 0x7E000000L +//DCHUBBUB_SDPIF_CFG1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS__SHIFT 0x1 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING__SHIFT 0x9 +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_DETECT_EN_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_MASK 0x00000002L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_PRQ_ERROR_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_FORCE_SNOOP_MASK 0x00000100L +#define DCHUBBUB_SDPIF_CFG1__SDPIF_MAX_NUM_OUTSTANDING_MASK 0x00000200L +//DCHUBBUB_SDPIF_CFG2 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT__SHIFT 0x0 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK__SHIFT 0x10 +#define DCHUBBUB_SDPIF_CFG2__dGPU_ADDR_PRESENT_MASK 0x00000001L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_HOSTVM_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_CFG2__SDPIF_UNIT_ID_BITMASK_MASK 0x01FF0000L +//VM_REQUEST_PHYSICAL +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT 0x0 +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT 0x3 +#define VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK 0x00000001L +#define VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK 0x00000008L +//DCHUBBUB_FORCE_IO_STATUS_0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY__SHIFT 0x1 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR__SHIFT 0x2 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID__SHIFT 0x3 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE__SHIFT 0x7 +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO__SHIFT 0xa +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_MASK 0x00000001L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_STICKY_MASK 0x00000002L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_CLEAR_MASK 0x00000004L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_PIPE_ID_MASK 0x00000078L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_REQUEST_TYPE_MASK 0x00000380L +#define DCHUBBUB_FORCE_IO_STATUS_0__SDPIF_FORCE_IO_STATUS_ADDR_LO_MASK 0xFFFFFC00L +//DCHUBBUB_FORCE_IO_STATUS_1 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI__SHIFT 0x0 +#define DCHUBBUB_FORCE_IO_STATUS_1__SDPIF_FORCE_IO_STATUS_ADDR_HI_MASK 0x001FFFFFL +//DCN_VM_FB_LOCATION_BASE +#define DCN_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL +//DCN_VM_FB_LOCATION_TOP +#define DCN_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 +#define DCN_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL +//DCN_VM_FB_OFFSET +#define DCN_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define DCN_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL +//DCN_VM_AGP_BOT +#define DCN_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 +#define DCN_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL +//DCN_VM_AGP_TOP +#define DCN_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 +#define DCN_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL +//DCN_VM_AGP_BASE +#define DCN_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 +#define DCN_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_START +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_START_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_END +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_END_MASK 0x000FFFFFL +//DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define DCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//DCHUBBUB_SDPIF_PIPE_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE0_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE1_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE2_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_SEC_LVL__SDPIF_PIPE3_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_NOALLOC +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC__SHIFT 0x1 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC__SHIFT 0x2 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC__SHIFT 0x3 +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE0_NOALLOC_MASK 0x00000001L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE1_NOALLOC_MASK 0x00000002L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE2_NOALLOC_MASK 0x00000004L +#define DCHUBBUB_SDPIF_PIPE_NOALLOC__SDPIF_PIPE3_NOALLOC_MASK 0x00000008L +//DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE0_DMDATA_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE1_DMDATA_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE2_DMDATA_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL__SDPIF_PIPE3_DMDATA_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE0_DCCMETA_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE1_DCCMETA_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE2_DCCMETA_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_DCCMETA_SEC_LVL__SDPIF_PIPE3_DCCMETA_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE0_CURSOR0_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE1_CURSOR0_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE2_CURSOR0_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_CURSOR0_SEC_LVL__SDPIF_PIPE3_CURSOR0_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE0_3DLUT_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE1_3DLUT_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE2_3DLUT_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE3_3DLUT_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE0_3DLUT_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE1_3DLUT_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE2_3DLUT_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_3DLUT_SEC_LVL__SDPIF_PIPE3_3DLUT_SEC_LVL_MASK 0x0000F000L +//DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL__SHIFT 0x0 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL__SHIFT 0x4 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL__SHIFT 0x8 +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL__SHIFT 0xc +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE0_GPUVM_SEC_LVL_MASK 0x0000000FL +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE1_GPUVM_SEC_LVL_MASK 0x000000F0L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE2_GPUVM_SEC_LVL_MASK 0x00000F00L +#define DCHUBBUB_SDPIF_PIPE_GPUVM_SEC_LVL__SDPIF_PIPE3_GPUVM_SEC_LVL_MASK 0x0000F000L +//SDPIF_REQUEST_RATE_LIMIT +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT__SHIFT 0x0 +#define SDPIF_REQUEST_RATE_LIMIT__SDPIF_REQUEST_RATE_LIMIT_MASK 0x00000FFFL +//DCHUBBUB_SDPIF_MEM_PWR_CTRL +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_SDPIF_MEM_PWR_CTRL__DCHUBBUB_SDPIF_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_SDPIF_MEM_PWR_STATUS +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_SDPIF_MEM_PWR_STATUS__DCHUBBUB_SDPIF_MEM_PWR_STATE_MASK 0x00000003L + + +// addressBlock: dce_dc_dchubbubl_hubbub_ret_path_dispdec +//DCHUBBUB_RET_PATH_MEM_PWR_CTRL +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS__SHIFT 0x2 +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_FORCE_MASK 0x00000003L +#define DCHUBBUB_RET_PATH_MEM_PWR_CTRL__DCHUBBUB_RET_PATH_MEM_PWR_DIS_MASK 0x00000004L +//DCHUBBUB_RET_PATH_MEM_PWR_STATUS +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_MEM_PWR_STATUS__DCHUBBUB_RET_PATH_MEM_PWR_STATE_MASK 0x00000003L +//DCHUBBUB_CRC_CTRL +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN__SHIFT 0x0 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN__SHIFT 0x1 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING__SHIFT 0x2 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING__SHIFT 0x3 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL__SHIFT 0x4 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL__SHIFT 0x6 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL__SHIFT 0x8 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL__SHIFT 0xc +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL__SHIFT 0x14 +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_EN_MASK 0x00000001L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_CONT_EN_MASK 0x00000002L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_ONE_SHOT_PENDING_MASK 0x00000004L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_ONE_SHOT_PENDING_MASK 0x00000008L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC0_SRC_SEL_MASK 0x00000030L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC1_SRC_SEL_MASK 0x000000C0L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_PIPE_SEL_MASK 0x00000F00L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_SURF_SEL_MASK 0x00001000L +#define DCHUBBUB_CRC_CTRL__DCHUBBUB_CRC_DATA_SRC_SEL_MASK 0x00100000L +//DCHUBBUB_CRC0_VAL_R +#define DCHUBBUB_CRC0_VAL_R__DCHUBBUB_CRC0_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_R__DCHUBBUB_CRC0_R_CR_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC0_VAL_G +#define DCHUBBUB_CRC0_VAL_G__DCHUBBUB_CRC0_G_Y__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_G__DCHUBBUB_CRC0_G_Y_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC0_VAL_B +#define DCHUBBUB_CRC0_VAL_B__DCHUBBUB_CRC0_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_B__DCHUBBUB_CRC0_B_CB_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC0_VAL_A +#define DCHUBBUB_CRC0_VAL_A__DCHUBBUB_CRC0_ALPHA__SHIFT 0x0 +#define DCHUBBUB_CRC0_VAL_A__DCHUBBUB_CRC0_ALPHA_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_R +#define DCHUBBUB_CRC1_VAL_R__DCHUBBUB_CRC1_R_CR__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_R__DCHUBBUB_CRC1_R_CR_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_G +#define DCHUBBUB_CRC1_VAL_G__DCHUBBUB_CRC1_G_Y__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_G__DCHUBBUB_CRC1_G_Y_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_B +#define DCHUBBUB_CRC1_VAL_B__DCHUBBUB_CRC1_B_CB__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_B__DCHUBBUB_CRC1_B_CB_MASK 0xFFFFFFFFL +//DCHUBBUB_CRC1_VAL_A +#define DCHUBBUB_CRC1_VAL_A__DCHUBBUB_CRC1_ALPHA__SHIFT 0x0 +#define DCHUBBUB_CRC1_VAL_A__DCHUBBUB_CRC1_ALPHA_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT_CNTL +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN__SHIFT 0x1 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE__SHIFT 0x2 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL__SHIFT 0x4 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT__SHIFT 0x10 +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_MODE_MASK 0x00000001L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_EN_MASK 0x00000002L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_DONE_MASK 0x00000004L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_PIPE_SEL_MASK 0x000000F0L +#define DCHUBBUB_DCC_STAT_CNTL__DCHUBBUB_DCC_STAT_FRAME_CNT_MASK 0xFFFF0000L +//DCHUBBUB_DCC_STAT0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT0__DCHUBBUB_DCC_STAT_TOTAL_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT1 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT1__DCHUBBUB_DCC_STAT_ZS_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_DCC_STAT2 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ__SHIFT 0x0 +#define DCHUBBUB_DCC_STAT2__DCHUBBUB_DCC_STAT_DCC_REQ_MASK 0xFFFFFFFFL +//DCHUBBUB_COMPBUF_CTRL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE__SHIFT 0x0 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE__SHIFT 0x10 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS__SHIFT 0x12 +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR__SHIFT 0x13 +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR__SHIFT 0x1f +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_MASK 0x0000001FL +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CURRENT_MASK 0x00001F00L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_ENABLE_MASK 0x00010000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_STATUS_MASK 0x00040000L +#define DCHUBBUB_COMPBUF_CTRL__COMPBUF_SIZE_CHANGE_DONE_INT_CLEAR_MASK 0x00080000L +#define DCHUBBUB_COMPBUF_CTRL__CONFIG_ERROR_MASK 0x80000000L +//DCHUBBUB_DET0_CTRL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET0_CTRL__DET0_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET1_CTRL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET1_CTRL__DET1_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET2_CTRL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET2_CTRL__DET2_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_DET3_CTRL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE__SHIFT 0x0 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT__SHIFT 0x8 +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_MASK 0x0000001FL +#define DCHUBBUB_DET3_CTRL__DET3_SIZE_CURRENT_MASK 0x00001F00L +//DCHUBBUB_MEM_PWR_MODE_CTRL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE__SHIFT 0x10 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE__SHIFT 0x12 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE__SHIFT 0x14 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS__SHIFT 0x18 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS__SHIFT 0x19 +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS__SHIFT 0x1a +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACCESS_MEM_PWR_MODE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_ACTIVE_MEM_PWR_MODE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_MODE_CTRL__COMPBUF_IDLE_MEM_PWR_MODE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_FORCE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_FORCE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__UNALLOCATED_MEM_PWR_MODE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_FORCE_MASK 0x00030000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_IDLE_MEM_PWR_MODE_MASK 0x000C0000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DET_MEM_PWR_LS_MODE_MASK 0x00300000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__SEGMENT_MEM_PWR_DIS_MASK 0x01000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__METAFIFO_MEM_PWR_DIS_MASK 0x02000000L +#define DCHUBBUB_MEM_PWR_MODE_CTRL__DCC_SKID_MEM_PWR_DIS_MASK 0x04000000L +//COMPBUF_MEM_PWR_CTRL_1 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY__SHIFT 0x10 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY__SHIFT 0x18 +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_ACTIVE_SLEEP_LATENCY_MASK 0x0000FF00L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_WAKE_LATENCY_MASK 0x00FF0000L +#define COMPBUF_MEM_PWR_CTRL_1__COMPBUF_IDLE_SLEEP_LATENCY_MASK 0xFF000000L +//COMPBUF_MEM_PWR_CTRL_2 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY__SHIFT 0x0 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY__SHIFT 0x8 +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY__SHIFT 0xc +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_UNALLOCATED_WAKE_LATENCY_MASK 0x000000FFL +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_ACTIVE_ENTER_LATENCY_MASK 0x00000F00L +#define COMPBUF_MEM_PWR_CTRL_2__COMPBUF_IDLE_ENTER_LATENCY_MASK 0x0000F000L +//DCHUBBUB_MEM_PWR_STATUS +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE__SHIFT 0x0 +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE__SHIFT 0x2 +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE__SHIFT 0x4 +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE__SHIFT 0x6 +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE__SHIFT 0x8 +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE__SHIFT 0xa +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE__SHIFT 0xc +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE__SHIFT 0xe +#define DCHUBBUB_MEM_PWR_STATUS__COMPBUF_MEM_PWR_STATE_MASK 0x00000003L +#define DCHUBBUB_MEM_PWR_STATUS__METAFIFO_MEM_PWR_STATE_MASK 0x0000000CL +#define DCHUBBUB_MEM_PWR_STATUS__UNALLOCATED_MEM_PWR_STATE_MASK 0x00000030L +#define DCHUBBUB_MEM_PWR_STATUS__DCC_SKID_MEM_PWR_STATE_MASK 0x000000C0L +#define DCHUBBUB_MEM_PWR_STATUS__DET0_MEM_PWR_STATE_MASK 0x00000300L +#define DCHUBBUB_MEM_PWR_STATUS__DET1_MEM_PWR_STATE_MASK 0x00000C00L +#define DCHUBBUB_MEM_PWR_STATUS__DET2_MEM_PWR_STATE_MASK 0x00003000L +#define DCHUBBUB_MEM_PWR_STATUS__DET3_MEM_PWR_STATE_MASK 0x0000C000L +//COMPBUF_RESERVED_SPACE +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B__SHIFT 0x0 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS__SHIFT 0x10 +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_64B_MASK 0x00000FFFL +#define COMPBUF_RESERVED_SPACE__COMPBUF_RESERVED_SPACE_ZS_MASK 0x0FFF0000L +//DCHUBBUB_DEBUG_CTRL_0 +#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH__SHIFT 0x0 +#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH__SHIFT 0x8 +#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH__SHIFT 0xc +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10 +#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE__SHIFT 0x1b +#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE__SHIFT 0x1c +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE__SHIFT 0x1d +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE__SHIFT 0x1e +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE__SHIFT 0x1f +#define DCHUBBUB_DEBUG_CTRL_0__METAFIFO_DEPTH_MASK 0x000000FFL +#define DCHUBBUB_DEBUG_CTRL_0__COMPBUF_SEG_DEPTH_MASK 0x00000F00L +#define DCHUBBUB_DEBUG_CTRL_0__DET_SEG_DEPTH_MASK 0x0000F000L +#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x07FF0000L +#define DCHUBBUB_DEBUG_CTRL_0__DELAY_COMPBUF_DEALLOC_ON_DRQ_STOP_DISABLE_MASK 0x08000000L +#define DCHUBBUB_DEBUG_CTRL_0__SEG_ALLOC_ERR_PIPE_BLANK_ENABLE_MASK 0x10000000L +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_RESET_OPTIMIZATION_DISABLE_MASK 0x20000000L +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_ALLOC_ENABLE_MASK 0x40000000L +#define DCHUBBUB_DEBUG_CTRL_0__DATAFIFO_STALL_FOR_DEALLOC_ENABLE_MASK 0x80000000L +//DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX +#define DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX__DCHUBBUB_RET_PATH_TEST_DEBUG_INDEX_MASK 0x000000FFL +//DCHUBBUB_RET_PATH_TEST_DEBUG_DATA +#define DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCHUBBUB_RET_PATH_TEST_DEBUG_DATA__DCHUBBUB_RET_PATH_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_dispdec +//DCHUBBUB_ARB_DF_REQ_OUTSTAND +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND__SHIFT 0x0 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND__SHIFT 0xa +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD__SHIFT 0x16 +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MAX_REQ_OUTSTAND_MASK 0x000001FFL +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_MASK 0x0007FC00L +#define DCHUBBUB_ARB_DF_REQ_OUTSTAND__DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD_MASK 0x7FC00000L +//DCHUBBUB_ARB_SAT_LEVEL +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL__SHIFT 0x0 +#define DCHUBBUB_ARB_SAT_LEVEL__DCHUBBUB_ARB_SAT_LEVEL_MASK 0xFFFFFFFFL +//DCHUBBUB_ARB_QOS_FORCE +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE__SHIFT 0x8 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x9 +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS__SHIFT 0xc +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_VALUE_MASK 0x0000000FL +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_QOS_FORCE_ENABLE_MASK 0x00000100L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_DO_NOT_FORCE_URGENCY_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000200L +#define DCHUBBUB_ARB_QOS_FORCE__DCHUBBUB_ARB_HOSTVM_STALL_QOS_MASK 0x0000F000L +//DCHUBBUB_ARB_DRAM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE__SHIFT 0x1 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0x2 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE__SHIFT 0x4 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE__SHIFT 0x5 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE__SHIFT 0x7 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE__SHIFT 0xc +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE__SHIFT 0xd +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DISABL_EXIT_DEEPSLEEP_WHEN_PREFETCH_START_PENDING__SHIFT 0xe +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP__SHIFT 0xf +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE__SHIFT 0x10 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE__SHIFT 0x11 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY__SHIFT 0x12 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS__SHIFT 0x18 +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE_MASK 0x00000001L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE_MASK 0x00000002L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_CSTATE_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000004L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE_MASK 0x00000010L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE_MASK 0x00000020L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__ENABLE_QOS_FORCE_PSTATE_MASK 0x00000080L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE_MASK 0x00001000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE_MASK 0x00002000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DISABL_EXIT_DEEPSLEEP_WHEN_PREFETCH_START_PENDING_MASK 0x00004000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DISABLE_HOSTVM_FORCE_DCFCLK_DEEP_SLEEP_MASK 0x00008000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_VALUE_MASK 0x00010000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_ENABLE_MASK 0x00020000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_ALLOW_DCFCLK_DEEP_SLEEP_FORCE_LEGACY_MASK 0x00040000L +#define DCHUBBUB_ARB_DRAM_STATE_CNTL__DCHUBBUB_ARB_DCFCLK_DEEP_SLEEP_HYSTERESIS_MASK 0xFF000000L +//DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_NO_PENDING_HVM_REQ_BEFORE_ENTER_CSTATE_HYSTERESIS__SHIFT 0x0 +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL_RESERVED__SHIFT 0x10 +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_NO_PENDING_HVM_REQ_BEFORE_ENTER_CSTATE_HYSTERESIS_MASK 0x0000FFFFL +#define DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL__DCHUBBUB_ARB_DRAM_HVM_STATE_CNTL_RESERVED_MASK 0xFFFF0000L +//DCHUBBUB_ARB_USR_RETRAINING_CNTL +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING__SHIFT 0x1 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE__SHIFT 0x8 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE__SHIFT 0x9 +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST__SHIFT 0xa +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE__SHIFT 0xb +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__USR_RETRAINING_REQUEST_MASK 0x00000001L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__ALLOW_USR_RETRAINING_MASK 0x00000002L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_VALUE_MASK 0x00000100L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_ALLOW_USR_RETRAINING_FORCE_ENABLE_MASK 0x00000200L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PSTATE_CHANGE_REQUEST_MASK 0x00000400L +#define DCHUBBUB_ARB_USR_RETRAINING_CNTL__DCHUBBUB_ARB_DO_NOT_FORCE_ALLOW_USR_RETRAINING_DURING_PRE_CSTATE_MASK 0x00000800L +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_A +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_A__DCHUBBUB_ARB_FRAC_URG_BW_NOM_A_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_B +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_B__DCHUBBUB_ARB_FRAC_URG_BW_NOM_B_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_C +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_C__DCHUBBUB_ARB_FRAC_URG_BW_NOM_C_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_MASK 0x000003FFL +//DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D__DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D__DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__SHIFT 0x0 +#define DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D__DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_MASK 0x00003FFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D_MASK 0x000FFFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__SHIFT 0x0 +#define DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D__DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D_MASK 0x000FFFFFL +//DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D__DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D_MASK 0x0000FFFFL +//DCHUBBUB_ARB_FRAC_URG_BW_NOM_D +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_NOM_D__DCHUBBUB_ARB_FRAC_URG_BW_NOM_D_MASK 0x000003FFL +//DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__SHIFT 0x0 +#define DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D__DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_MASK 0x000003FFL +//DCHUBBUB_ARB_HOSTVM_CNTL +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE__SHIFT 0x0 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE__SHIFT 0x1 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING__SHIFT 0x2 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK__SHIFT 0x3 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS__SHIFT 0x4 +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS__SHIFT 0x6 +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS__SHIFT 0x7 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS__SHIFT 0x8 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES__SHIFT 0x10 +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS__SHIFT 0x18 +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD__SHIFT 0x1c +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_CSTATE_MASK 0x00000001L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_PSTATE_MASK 0x00000002L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DISABLE_HOSTVM_FORCE_ALLOW_USR_RETRAINING_MASK 0x00000004L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SLACK_MASK_MASK 0x00000008L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_SPACE_OK_STATUS_MASK 0x00000010L +#define DCHUBBUB_ARB_HOSTVM_CNTL__PRQ_GID_FREE_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHVM_RET_FIFO_FREE_STATUS_MASK 0x00000040L +#define DCHUBBUB_ARB_HOSTVM_CNTL__NON_PRQ_CLIENT_WINNER_STATUS_MASK 0x00000080L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_ALLOCATED_GROUPS_MASK 0x00003F00L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_MAX_RD_FIFO_ENTRIES_MASK 0x00FF0000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__HOSTVM_QOS_MASK 0x0F000000L +#define DCHUBBUB_ARB_HOSTVM_CNTL__DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD_MASK 0xF0000000L +//DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT__SHIFT 0x0 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE__SHIFT 0x4 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS__SHIFT 0x5 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST__SHIFT 0x8 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8__SHIFT 0x10 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE__SHIFT 0x18 +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_MASK 0x00000003L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE_MASK 0x00000010L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_STATUS_MASK 0x00000020L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST_MASK 0x00000100L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__DCHUBBUB_ARB_WATERMARK_CHANGE_SELECT_Z8_MASK 0x00010000L +#define DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL__PSTATE_CHANGE_TYPE_MASK 0x01000000L +//DCHUBBUB_ARB_MALL_CNTL +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS__SHIFT 0x0 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE__SHIFT 0x4 +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define DCHUBBUB_ARB_MALL_CNTL__GLOBAL_USE_MALL_FOR_SS_MASK 0x00000001L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_IN_USE_MASK 0x00000010L +#define DCHUBBUB_ARB_MALL_CNTL__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +//DCHUBBUB_ARB_TIMEOUT_ENABLE +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_ARB_TIMEOUT_ENABLE__DCHUBBUB_ARB_TIMEOUT_ENABLE_MASK 0x00000001L +//DCHUBBUB_GLOBAL_TIMER_CNTL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV__SHIFT 0x0 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE__SHIFT 0xc +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT__SHIFT 0x10 +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_REFDIV_MASK 0x0000000FL +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_ENABLE_MASK 0x00001000L +#define DCHUBBUB_GLOBAL_TIMER_CNTL__DCHUBBUB_GLOBAL_TIMER_INIT_MASK 0xFFFF0000L +//SURFACE_CHECK0_ADDRESS_LSB +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_LSB__SURFACE_CHECK0_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK0_ADDRESS_MSB +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK0_ADDRESS_MSB__SURFACE_CHECK0_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK0_ADDRESS_MSB__CHECKER0_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK1_ADDRESS_LSB +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_LSB__SURFACE_CHECK1_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK1_ADDRESS_MSB +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK1_ADDRESS_MSB__SURFACE_CHECK1_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK1_ADDRESS_MSB__CHECKER1_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK2_ADDRESS_LSB +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_LSB__SURFACE_CHECK2_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK2_ADDRESS_MSB +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK2_ADDRESS_MSB__SURFACE_CHECK2_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK2_ADDRESS_MSB__CHECKER2_SURFACE_INUSE_MASK 0x80000000L +//SURFACE_CHECK3_ADDRESS_LSB +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_LSB__SURFACE_CHECK3_ADDRESS_LSB_MASK 0xFFFFFFFFL +//SURFACE_CHECK3_ADDRESS_MSB +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB__SHIFT 0x0 +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE__SHIFT 0x1f +#define SURFACE_CHECK3_ADDRESS_MSB__SURFACE_CHECK3_ADDRESS_MSB_MASK 0x0000FFFFL +#define SURFACE_CHECK3_ADDRESS_MSB__CHECKER3_SURFACE_INUSE_MASK 0x80000000L +//VTG0_CONTROL +#define VTG0_CONTROL__VTG0_FP2__SHIFT 0x0 +#define VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT 0x10 +#define VTG0_CONTROL__VTG0_ENABLE__SHIFT 0x1f +#define VTG0_CONTROL__VTG0_FP2_MASK 0x00007FFFL +#define VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG0_CONTROL__VTG0_ENABLE_MASK 0x80000000L +//VTG1_CONTROL +#define VTG1_CONTROL__VTG1_FP2__SHIFT 0x0 +#define VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT 0x10 +#define VTG1_CONTROL__VTG1_ENABLE__SHIFT 0x1f +#define VTG1_CONTROL__VTG1_FP2_MASK 0x00007FFFL +#define VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG1_CONTROL__VTG1_ENABLE_MASK 0x80000000L +//VTG2_CONTROL +#define VTG2_CONTROL__VTG2_FP2__SHIFT 0x0 +#define VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT 0x10 +#define VTG2_CONTROL__VTG2_ENABLE__SHIFT 0x1f +#define VTG2_CONTROL__VTG2_FP2_MASK 0x00007FFFL +#define VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG2_CONTROL__VTG2_ENABLE_MASK 0x80000000L +//VTG3_CONTROL +#define VTG3_CONTROL__VTG3_FP2__SHIFT 0x0 +#define VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT 0x10 +#define VTG3_CONTROL__VTG3_ENABLE__SHIFT 0x1f +#define VTG3_CONTROL__VTG3_FP2_MASK 0x00007FFFL +#define VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK 0x7FFF0000L +#define VTG3_CONTROL__VTG3_ENABLE_MASK 0x80000000L +//DCHUBBUB_SOFT_RESET +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET__SHIFT 0x0 +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET__SHIFT 0x1 +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET__SHIFT 0x4 +#define DCHUBBUB_SOFT_RESET__DCHUBBUB_GLOBAL_SOFT_RESET_MASK 0x00000001L +#define DCHUBBUB_SOFT_RESET__ALLOW_CSTATE_SOFT_RESET_MASK 0x00000002L +#define DCHUBBUB_SOFT_RESET__GLBFLIP_SOFT_RESET_MASK 0x00000010L +//DCHUBBUB_CLOCK_CNTL +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL__SHIFT 0x0 +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x5 +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS__SHIFT 0x6 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS__SHIFT 0x7 +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_TEST_CLK_SEL_MASK 0x0000001FL +#define DCHUBBUB_CLOCK_CNTL__DISPCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000020L +#define DCHUBBUB_CLOCK_CNTL__DCFCLK_R_DCHUBBUB_GATE_DIS_MASK 0x00000040L +#define DCHUBBUB_CLOCK_CNTL__DCHUBBUB_FGCG_REP_DIS_MASK 0x00000080L +//DCFCLK_CNTL +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY__SHIFT 0x0 +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY__SHIFT 0x4 +#define DCFCLK_CNTL__DCFCLK_GATE_DIS__SHIFT 0x1f +#define DCFCLK_CNTL__DCFCLK_TURN_ON_DELAY_MASK 0x0000000FL +#define DCFCLK_CNTL__DCFCLK_TURN_OFF_DELAY_MASK 0x00000FF0L +#define DCFCLK_CNTL__DCFCLK_GATE_DIS_MASK 0x80000000L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL__SHIFT 0x2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL__SHIFT 0x3 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL__SHIFT 0x7 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY__SHIFT 0xa +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL__SHIFT 0xb +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_CNT_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_LATENCY_EVENT_SHORT_PULSE_FILTER_EN_MASK 0x00000002L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DCHUBBUB_DF_REQ_CMD_LATENCY_SEL_MASK 0x00000004L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_PIPE_SEL_MASK 0x00000078L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ARB_LATENCY_REQ_TYPE_SEL_MASK 0x00000380L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__DF_LATENCY_URGENT_ONLY_MASK 0x00000400L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL__ROB_FIFO_LEVEL_MASK 0x003FF800L +//DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN__SHIFT 0x0 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL__SHIFT 0x1 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR__SHIFT 0x4 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL__SHIFT 0xc +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_DEBUG_SEL__SHIFT 0xf +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL__SHIFT 0x14 +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET__SHIFT 0x1f +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_EN_MASK 0x00000001L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_SRC_SEL_MASK 0x0000000EL +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__DCHUBBUB_LATENCY_FRAME_WIN_DUR_MASK 0x00000FF0L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_SOURCE_SEL_MASK 0x00007000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__LATENCY_DEBUG_SEL_MASK 0x00008000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_MASK 0x7FF00000L +#define DCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2__ROB_MAX_FIFO_LEVEL_RESET_MASK 0x80000000L +//DCHUBBUB_VLINE_SNAPSHOT +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT__SHIFT 0x0 +#define DCHUBBUB_VLINE_SNAPSHOT__DCHUBBUB_VLINE_SNAPSHOT_MASK 0x00000001L +//DCHUBBUB_CTRL_STATUS +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN__SHIFT 0x0 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 +#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG__SHIFT 0x4 +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f +#define DCHUBBUB_CTRL_STATUS__URGENT_ZERO_SIZE_REQ_EN_MASK 0x00000001L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L +#define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L +#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG_MASK 0x3FFFFFF0L +#define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL1 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD__SHIFT 0x6 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS_MASK 0x0000003FL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD_MASK 0xFFFFFFC0L +//DCHUBBUB_TIMEOUT_DETECTION_CTRL2 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN__SHIFT 0x1b +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET__SHIFT 0x1c +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD_MASK 0x07FFFFFFL +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_DETECTION_EN_MASK 0x08000000L +#define DCHUBBUB_TIMEOUT_DETECTION_CTRL2__DCHUBBUB_TIMEOUT_TIMER_RESET_MASK 0x10000000L +//DCHUBBUB_TIMEOUT_INTERRUPT_STATUS +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE__SHIFT 0x0 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS__SHIFT 0x1 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR__SHIFT 0x2 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK__SHIFT 0x3 +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_ENABLE_MASK 0x00000001L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_STATUS_MASK 0x00000002L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_CLEAR_MASK 0x00000004L +#define DCHUBBUB_TIMEOUT_INTERRUPT_STATUS__DCHUBBUB_TIMEOUT_INT_MASK_MASK 0x000000F8L +//FMON_CTRL +#define FMON_CTRL__FMON_START__SHIFT 0x0 +#define FMON_CTRL__FMON_MODE__SHIFT 0x1 +#define FMON_CTRL__FMON_PSTATE_IGNORE__SHIFT 0x4 +#define FMON_CTRL__FMON_STATUS_IGNORE__SHIFT 0x5 +#define FMON_CTRL__FMON_URG_MODE_GREATER__SHIFT 0x6 +#define FMON_CTRL__FMON_FILTER_UID_EN__SHIFT 0x7 +#define FMON_CTRL__FMON_STATE__SHIFT 0x9 +#define FMON_CTRL__FMON_URG_FILTER__SHIFT 0xc +#define FMON_CTRL__FMON_URG_THRESHOLD__SHIFT 0xd +#define FMON_CTRL__FMON_FILTER_UID_1__SHIFT 0x11 +#define FMON_CTRL__FMON_FILTER_UID_2__SHIFT 0x16 +#define FMON_CTRL__FMON_SOF_SEL__SHIFT 0x1b +#define FMON_CTRL__FMON_START_MASK 0x00000001L +#define FMON_CTRL__FMON_MODE_MASK 0x00000006L +#define FMON_CTRL__FMON_PSTATE_IGNORE_MASK 0x00000010L +#define FMON_CTRL__FMON_STATUS_IGNORE_MASK 0x00000020L +#define FMON_CTRL__FMON_URG_MODE_GREATER_MASK 0x00000040L +#define FMON_CTRL__FMON_FILTER_UID_EN_MASK 0x00000180L +#define FMON_CTRL__FMON_STATE_MASK 0x00000600L +#define FMON_CTRL__FMON_URG_FILTER_MASK 0x00001000L +#define FMON_CTRL__FMON_URG_THRESHOLD_MASK 0x0001E000L +#define FMON_CTRL__FMON_FILTER_UID_1_MASK 0x003E0000L +#define FMON_CTRL__FMON_FILTER_UID_2_MASK 0x07C00000L +#define FMON_CTRL__FMON_SOF_SEL_MASK 0x38000000L +//DCHUBBUB_TEST_DEBUG_INDEX +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_INDEX__DCHUBBUB_TEST_DEBUG_INDEX_MASK 0x000000FFL +//DCHUBBUB_TEST_DEBUG_DATA +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCHUBBUB_TEST_DEBUG_DATA__DCHUBBUB_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_dchubbub_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON5_PERFCOUNTER_CNTL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_CNTL2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON5_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFCOUNTER_STATE +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON5_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON5_PERFMON_CNTL +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON5_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON5_PERFMON_CNTL2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON5_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON5_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON5_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON5_PERFMON_CVALUE_LOW +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON5_PERFMON_HI +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON5_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON5_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON5_PERFMON_LOW +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON5_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dchubbubl_hubbub_vmrq_if_dispdec +//DCN_VM_CONTEXT0_CNTL +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT0_CNTL__VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_CNTL +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT1_CNTL__VM_CONTEXT1_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT1_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT1_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT1_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_CNTL +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT2_CNTL__VM_CONTEXT2_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT2_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT2_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT2_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_CNTL +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT3_CNTL__VM_CONTEXT3_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT3_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT3_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT3_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_CNTL +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT4_CNTL__VM_CONTEXT4_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT4_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT4_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT4_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_CNTL +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT5_CNTL__VM_CONTEXT5_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT5_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT5_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT5_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_CNTL +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT6_CNTL__VM_CONTEXT6_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT6_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT6_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT6_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_CNTL +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT7_CNTL__VM_CONTEXT7_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT7_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT7_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT7_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_CNTL +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT8_CNTL__VM_CONTEXT8_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT8_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT8_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT8_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_CNTL +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT9_CNTL__VM_CONTEXT9_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT9_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT9_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT9_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_CNTL +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT10_CNTL__VM_CONTEXT10_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT10_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT10_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT10_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_CNTL +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT11_CNTL__VM_CONTEXT11_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT11_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT11_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT11_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_CNTL +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT12_CNTL__VM_CONTEXT12_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT12_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT12_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT12_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_CNTL +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT13_CNTL__VM_CONTEXT13_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT13_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT13_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT13_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_CNTL +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT14_CNTL__VM_CONTEXT14_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT14_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT14_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT14_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_CNTL +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH__SHIFT 0x1 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_DEPTH_MASK 0x00000006L +#define DCN_VM_CONTEXT15_CNTL__VM_CONTEXT15_PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__VM_CONTEXT15_PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__VM_CONTEXT15_START_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL +//DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define DCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__VM_CONTEXT15_END_LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//DCN_VM_DEFAULT_ADDR_MSB +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA__SHIFT 0x1c +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP__SHIFT 0x1d +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_ADDR_MSB_MASK 0x0000000FL +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SPA_MASK 0x10000000L +#define DCN_VM_DEFAULT_ADDR_MSB__DCN_VM_DEFAULT_SNOOP_MASK 0x20000000L +//DCN_VM_DEFAULT_ADDR_LSB +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_DEFAULT_ADDR_LSB__DCN_VM_DEFAULT_ADDR_LSB_MASK 0xFFFFFFFFL +//DCN_VM_FAULT_CNTL +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR__SHIFT 0x0 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE__SHIFT 0x1 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE__SHIFT 0x2 +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE__SHIFT 0x8 +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE__SHIFT 0x9 +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_CLEAR_MASK 0x00000001L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_STATUS_MODE_MASK 0x00000002L +#define DCN_VM_FAULT_CNTL__DCN_VM_ERROR_INTERRUPT_ENABLE_MASK 0x00000004L +#define DCN_VM_FAULT_CNTL__DCN_VM_RANGE_FAULT_DISABLE_MASK 0x00000100L +#define DCN_VM_FAULT_CNTL__DCN_VM_PRQ_FAULT_DISABLE_MASK 0x00000200L +//DCN_VM_FAULT_STATUS +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS__SHIFT 0x0 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID__SHIFT 0x10 +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID__SHIFT 0x14 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL__SHIFT 0x18 +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE__SHIFT 0x1a +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS__SHIFT 0x1f +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_STATUS_MASK 0x0000FFFFL +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_VMID_MASK 0x000F0000L +#define DCN_VM_FAULT_STATUS__DCN_VM_TR_RESP_ERROR_VMID_MASK 0x00F00000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_TABLE_LEVEL_MASK 0x03000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_PIPE_MASK 0x3C000000L +#define DCN_VM_FAULT_STATUS__DCN_VM_ERROR_INTERRUPT_STATUS_MASK 0x80000000L +//DCN_VM_FAULT_ADDR_MSB +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_MSB__DCN_VM_FAULT_ADDR_MSB_MASK 0x0000000FL +//DCN_VM_FAULT_ADDR_LSB +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB__SHIFT 0x0 +#define DCN_VM_FAULT_ADDR_LSB__DCN_VM_FAULT_ADDR_LSB_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec +//HUBP0_DCSURF_SURFACE_CONFIG +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP0_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP0_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP0_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP0_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP0_DCSURF_ADDR_CONFIG +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP0_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP0_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP0_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP0_DCSURF_TILING_CONFIG +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP0_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP0_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP0_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP0_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP0_DCSURF_PRI_VIEWPORT_START +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_START_C +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_START_C +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP0_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP0_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP0_DCHUBP_CNTL +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP0_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP0_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP0_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP0_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP0_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP0_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP0_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP0_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP0_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP0_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP0_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP0_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP0_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP0_HUBP_CLK_CNTL +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP0_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP0_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP0_DCHUBP_VMPG_CONFIG +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP0_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP0_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP0_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP0_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP0_DCHUBP_MALL_CONFIG +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP0_DCHUBP_MALL_SUB_VP +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP0_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP0_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP0_HUBPREQ_DEBUG_DB +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP0_HUBPREQ_DEBUG +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP0_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP0_HUBP_DEBUG_CTRL +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP0_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP0_HUBP_DEBUG_MUX_DCFCLK +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP0_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP0_HUBP_DEBUG_MUX_DPPCLK +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP0_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP0_HUBP_MALL_STATUS +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP0_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP0_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP0_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP0_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP0_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP0_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP0_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP0_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP0_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP0_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP0_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP0_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP0_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec +//HUBPREQ0_DCSURF_SURFACE_PITCH +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ0_DCSURF_SURFACE_PITCH_C +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ0_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ0_VMID_SETTINGS_0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ0_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ0_DCSURF_SURFACE_CONTROL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ0_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ0_DCSURF_FLIP_CONTROL +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ0_DCSURF_FLIP_CONTROL2 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ0_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ0_DCSURF_SURFACE_INUSE +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ0_DCN_EXPANSION_MODE +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ0_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ0_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ0_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ0_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ0_DCN_TTU_QOS_WM +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ0_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ0_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ0_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ0_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ0_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ0_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ0_DCN_DMDATA_VM_CNTL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ0_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ0_BLANK_OFFSET_0 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ0_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ0_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ0_BLANK_OFFSET_1 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ0_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ0_DST_DIMENSIONS +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ0_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ0_DST_AFTER_SCALER +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ0_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ0_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ0_PREFETCH_SETTINGS +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ0_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ0_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ0_PREFETCH_SETTINGS_C +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ0_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ0_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ0_VBLANK_PARAMETERS_1 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_2 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_3 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_4 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ0_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ0_FLIP_PARAMETERS_1 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_2 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_1 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_2 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_3 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_4 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_5 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ0_NOM_PARAMETERS_6 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ0_NOM_PARAMETERS_7 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ0_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ0_PER_LINE_DELIVERY_PRE +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ0_PER_LINE_DELIVERY +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ0_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ0_CURSOR_SETTINGS +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ0_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ0_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ0_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ0_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ0_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ0_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ0_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ0_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ0_VBLANK_PARAMETERS_5 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_VBLANK_PARAMETERS_6 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ0_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_3 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_4 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_5 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_FLIP_PARAMETERS_6 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ0_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ0_UCLK_PSTATE_FORCE +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ0_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ0_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ0_HUBPREQ_STATUS_REG0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ0_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG1 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ0_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ0_HUBPREQ_STATUS_REG2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ0_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec +//HUBPRET0_HUBPRET_CONTROL +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET0_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET0_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET0_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET0_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET0_HUBPRET_MEM_PWR_CTRL +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET0_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET0_HUBPRET_MEM_PWR_STATUS +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET0_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET0_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET0_HUBPRET_READ_LINE0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE1 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_INTERRUPT +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET0_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET0_HUBPRET_READ_LINE_VALUE +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET0_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET0_HUBPRET_READ_LINE_STATUS +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET0_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec +//CURSOR0_0_CURSOR_CONTROL +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_0_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_0_CURSOR_SURFACE_ADDRESS +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_CURSOR_SIZE +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_0_CURSOR_POSITION +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_0_CURSOR_HOT_SPOT +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_0_CURSOR_STEREO_CONTROL +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_0_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_0_CURSOR_DST_OFFSET +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_0_CURSOR_MEM_PWR_CTRL +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_0_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_0_CURSOR_MEM_PWR_STATUS +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_0_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_0_DMDATA_ADDRESS_HIGH +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_0_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_0_DMDATA_ADDRESS_LOW +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_DMDATA_CNTL +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_0_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_QOS_CNTL +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_0_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_0_DMDATA_STATUS +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_0_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_0_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_0_DMDATA_SW_CNTL +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_0_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_0_DMDATA_SW_DATA +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_0_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_0_HUBP_3DLUT_CONTROL +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_0_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_0_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_0_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_0_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON6_PERFCOUNTER_CNTL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_CNTL2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON6_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFCOUNTER_STATE +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON6_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON6_PERFMON_CNTL +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON6_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON6_PERFMON_CNTL2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON6_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON6_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON6_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON6_PERFMON_CVALUE_LOW +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON6_PERFMON_HI +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON6_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON6_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON6_PERFMON_LOW +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON6_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec +//HUBP1_DCSURF_SURFACE_CONFIG +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP1_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP1_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP1_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP1_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP1_DCSURF_ADDR_CONFIG +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP1_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP1_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP1_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP1_DCSURF_TILING_CONFIG +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP1_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP1_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP1_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP1_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP1_DCSURF_PRI_VIEWPORT_START +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_START_C +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_START_C +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP1_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP1_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP1_DCHUBP_CNTL +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP1_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP1_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP1_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP1_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP1_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP1_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP1_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP1_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP1_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP1_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP1_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP1_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP1_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP1_HUBP_CLK_CNTL +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP1_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP1_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP1_DCHUBP_VMPG_CONFIG +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP1_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP1_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP1_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP1_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP1_DCHUBP_MALL_CONFIG +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP1_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP1_DCHUBP_MALL_SUB_VP +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP1_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP1_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP1_HUBPREQ_DEBUG_DB +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP1_HUBPREQ_DEBUG +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP1_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP1_HUBP_DEBUG_CTRL +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP1_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP1_HUBP_DEBUG_MUX_DCFCLK +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP1_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP1_HUBP_DEBUG_MUX_DPPCLK +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP1_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP1_HUBP_MALL_STATUS +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP1_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP1_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP1_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP1_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP1_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP1_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP1_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP1_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP1_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP1_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP1_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP1_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP1_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec +//HUBPREQ1_DCSURF_SURFACE_PITCH +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ1_DCSURF_SURFACE_PITCH_C +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ1_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ1_VMID_SETTINGS_0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ1_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ1_DCSURF_SURFACE_CONTROL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ1_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ1_DCSURF_FLIP_CONTROL +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ1_DCSURF_FLIP_CONTROL2 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ1_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ1_DCSURF_SURFACE_INUSE +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ1_DCN_EXPANSION_MODE +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ1_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ1_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ1_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ1_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ1_DCN_TTU_QOS_WM +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ1_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ1_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ1_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ1_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ1_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ1_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ1_DCN_DMDATA_VM_CNTL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ1_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ1_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ1_BLANK_OFFSET_0 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ1_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ1_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ1_BLANK_OFFSET_1 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ1_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ1_DST_DIMENSIONS +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ1_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ1_DST_AFTER_SCALER +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ1_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ1_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ1_PREFETCH_SETTINGS +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ1_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ1_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ1_PREFETCH_SETTINGS_C +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ1_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ1_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ1_VBLANK_PARAMETERS_1 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_2 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_3 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_4 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ1_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ1_FLIP_PARAMETERS_1 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_2 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_1 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_2 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_3 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_4 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_5 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ1_NOM_PARAMETERS_6 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ1_NOM_PARAMETERS_7 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ1_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ1_PER_LINE_DELIVERY_PRE +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ1_PER_LINE_DELIVERY +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ1_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ1_CURSOR_SETTINGS +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ1_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ1_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ1_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ1_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ1_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ1_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ1_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ1_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ1_VBLANK_PARAMETERS_5 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_VBLANK_PARAMETERS_6 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ1_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_3 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_4 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_5 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_FLIP_PARAMETERS_6 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ1_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ1_UCLK_PSTATE_FORCE +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ1_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ1_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ1_HUBPREQ_STATUS_REG0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ1_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG1 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ1_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ1_HUBPREQ_STATUS_REG2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ1_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec +//HUBPRET1_HUBPRET_CONTROL +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET1_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET1_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET1_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET1_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET1_HUBPRET_MEM_PWR_CTRL +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET1_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET1_HUBPRET_MEM_PWR_STATUS +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET1_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET1_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET1_HUBPRET_READ_LINE0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE1 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_INTERRUPT +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET1_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET1_HUBPRET_READ_LINE_VALUE +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET1_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET1_HUBPRET_READ_LINE_STATUS +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET1_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec +//CURSOR0_1_CURSOR_CONTROL +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_1_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_1_CURSOR_SURFACE_ADDRESS +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_CURSOR_SIZE +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_1_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_1_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_1_CURSOR_POSITION +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_1_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_1_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_1_CURSOR_HOT_SPOT +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_1_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_1_CURSOR_STEREO_CONTROL +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_1_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_1_CURSOR_DST_OFFSET +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_1_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_1_CURSOR_MEM_PWR_CTRL +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_1_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_1_CURSOR_MEM_PWR_STATUS +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_1_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_1_DMDATA_ADDRESS_HIGH +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_1_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_1_DMDATA_ADDRESS_LOW +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_DMDATA_CNTL +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_1_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_QOS_CNTL +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_1_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_1_DMDATA_STATUS +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_1_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_1_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_1_DMDATA_SW_CNTL +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_1_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_1_DMDATA_SW_DATA +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_1_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_1_HUBP_3DLUT_CONTROL +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_1_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_1_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_1_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_1_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON7_PERFCOUNTER_CNTL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_CNTL2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON7_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFCOUNTER_STATE +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON7_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON7_PERFMON_CNTL +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON7_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON7_PERFMON_CNTL2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON7_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON7_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON7_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON7_PERFMON_CVALUE_LOW +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON7_PERFMON_HI +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON7_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON7_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON7_PERFMON_LOW +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON7_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec +//HUBP2_DCSURF_SURFACE_CONFIG +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP2_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP2_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP2_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP2_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP2_DCSURF_ADDR_CONFIG +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP2_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP2_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP2_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP2_DCSURF_TILING_CONFIG +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP2_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP2_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP2_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP2_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP2_DCSURF_PRI_VIEWPORT_START +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_START_C +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_START_C +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP2_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP2_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP2_DCHUBP_CNTL +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP2_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP2_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP2_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP2_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP2_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP2_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP2_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP2_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP2_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP2_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP2_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP2_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP2_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP2_HUBP_CLK_CNTL +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP2_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP2_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP2_DCHUBP_VMPG_CONFIG +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP2_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP2_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP2_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP2_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP2_DCHUBP_MALL_CONFIG +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP2_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP2_DCHUBP_MALL_SUB_VP +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP2_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP2_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP2_HUBPREQ_DEBUG_DB +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP2_HUBPREQ_DEBUG +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP2_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP2_HUBP_DEBUG_CTRL +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP2_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP2_HUBP_DEBUG_MUX_DCFCLK +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP2_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP2_HUBP_DEBUG_MUX_DPPCLK +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP2_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP2_HUBP_MALL_STATUS +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP2_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP2_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP2_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP2_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP2_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP2_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP2_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP2_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP2_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP2_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP2_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP2_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP2_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec +//HUBPREQ2_DCSURF_SURFACE_PITCH +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ2_DCSURF_SURFACE_PITCH_C +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ2_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ2_VMID_SETTINGS_0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ2_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ2_DCSURF_SURFACE_CONTROL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ2_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ2_DCSURF_FLIP_CONTROL +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ2_DCSURF_FLIP_CONTROL2 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ2_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ2_DCSURF_SURFACE_INUSE +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ2_DCN_EXPANSION_MODE +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ2_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ2_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ2_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ2_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ2_DCN_TTU_QOS_WM +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ2_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ2_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ2_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ2_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ2_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ2_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ2_DCN_DMDATA_VM_CNTL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ2_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ2_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ2_BLANK_OFFSET_0 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ2_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ2_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ2_BLANK_OFFSET_1 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ2_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ2_DST_DIMENSIONS +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ2_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ2_DST_AFTER_SCALER +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ2_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ2_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ2_PREFETCH_SETTINGS +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ2_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ2_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ2_PREFETCH_SETTINGS_C +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ2_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ2_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ2_VBLANK_PARAMETERS_1 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_2 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_3 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_4 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ2_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ2_FLIP_PARAMETERS_1 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_2 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_1 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_2 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_3 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_4 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_5 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ2_NOM_PARAMETERS_6 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ2_NOM_PARAMETERS_7 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ2_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ2_PER_LINE_DELIVERY_PRE +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ2_PER_LINE_DELIVERY +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ2_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ2_CURSOR_SETTINGS +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ2_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ2_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ2_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ2_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ2_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ2_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ2_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ2_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ2_VBLANK_PARAMETERS_5 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_VBLANK_PARAMETERS_6 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ2_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_3 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_4 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_5 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_FLIP_PARAMETERS_6 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ2_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ2_UCLK_PSTATE_FORCE +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ2_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ2_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ2_HUBPREQ_STATUS_REG0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ2_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG1 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ2_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ2_HUBPREQ_STATUS_REG2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ2_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec +//HUBPRET2_HUBPRET_CONTROL +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET2_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET2_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET2_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET2_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET2_HUBPRET_MEM_PWR_CTRL +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET2_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET2_HUBPRET_MEM_PWR_STATUS +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET2_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET2_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET2_HUBPRET_READ_LINE0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE1 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_INTERRUPT +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET2_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET2_HUBPRET_READ_LINE_VALUE +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET2_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET2_HUBPRET_READ_LINE_STATUS +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET2_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec +//CURSOR0_2_CURSOR_CONTROL +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_2_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_2_CURSOR_SURFACE_ADDRESS +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_CURSOR_SIZE +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_2_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_2_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_2_CURSOR_POSITION +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_2_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_2_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_2_CURSOR_HOT_SPOT +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_2_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_2_CURSOR_STEREO_CONTROL +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_2_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_2_CURSOR_DST_OFFSET +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_2_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_2_CURSOR_MEM_PWR_CTRL +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_2_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_2_CURSOR_MEM_PWR_STATUS +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_2_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_2_DMDATA_ADDRESS_HIGH +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_2_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_2_DMDATA_ADDRESS_LOW +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_DMDATA_CNTL +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_2_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_QOS_CNTL +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_2_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_2_DMDATA_STATUS +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_2_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_2_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_2_DMDATA_SW_CNTL +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_2_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_2_DMDATA_SW_DATA +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_2_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_2_HUBP_3DLUT_CONTROL +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_2_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_2_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_2_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_2_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON8_PERFCOUNTER_CNTL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_CNTL2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON8_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFCOUNTER_STATE +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON8_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON8_PERFMON_CNTL +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON8_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON8_PERFMON_CNTL2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON8_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON8_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON8_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON8_PERFMON_CVALUE_LOW +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON8_PERFMON_HI +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON8_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON8_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON8_PERFMON_LOW +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON8_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec +//HUBP3_DCSURF_SURFACE_CONFIG +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE__SHIFT 0x8 +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN__SHIFT 0xa +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN__SHIFT 0xb +#define HUBP3_DCSURF_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define HUBP3_DCSURF_SURFACE_CONFIG__ROTATION_ANGLE_MASK 0x00000300L +#define HUBP3_DCSURF_SURFACE_CONFIG__H_MIRROR_EN_MASK 0x00000400L +#define HUBP3_DCSURF_SURFACE_CONFIG__ALPHA_PLANE_EN_MASK 0x00000800L +//HUBP3_DCSURF_ADDR_CONFIG +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE__SHIFT 0x6 +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0xc +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS__SHIFT 0x10 +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define HUBP3_DCSURF_ADDR_CONFIG__PIPE_INTERLEAVE_MASK 0x000000C0L +#define HUBP3_DCSURF_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x00003000L +#define HUBP3_DCSURF_ADDR_CONFIG__NUM_PKRS_MASK 0x00070000L +//HUBP3_DCSURF_TILING_CONFIG +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE__SHIFT 0x0 +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE__SHIFT 0x7 +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR__SHIFT 0x9 +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED__SHIFT 0xb +#define HUBP3_DCSURF_TILING_CONFIG__SW_MODE_MASK 0x0000001FL +#define HUBP3_DCSURF_TILING_CONFIG__DIM_TYPE_MASK 0x00000180L +#define HUBP3_DCSURF_TILING_CONFIG__META_LINEAR_MASK 0x00000200L +#define HUBP3_DCSURF_TILING_CONFIG__PIPE_ALIGNED_MASK 0x00000800L +//HUBP3_DCSURF_PRI_VIEWPORT_START +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START__PRI_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_START_C +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_START_C__PRI_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C__PRI_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_X_START_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START__SEC_VIEWPORT_Y_START_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_WIDTH_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION__SEC_VIEWPORT_HEIGHT_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_START_C +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_X_START_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_START_C__SEC_VIEWPORT_Y_START_C_MASK 0x3FFF0000L +//HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C__SHIFT 0x0 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C__SHIFT 0x10 +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_WIDTH_C_MASK 0x00003FFFL +#define HUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C__SEC_VIEWPORT_HEIGHT_C_MASK 0x3FFF0000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE__SHIFT 0x18 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__SWATH_HEIGHT_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__PTE_ROW_HEIGHT_LINEAR_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__CHUNK_SIZE_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_CHUNK_SIZE_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__META_CHUNK_SIZE_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__MIN_META_CHUNK_SIZE_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__DPTE_GROUP_SIZE_MASK 0x00700000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG__VM_GROUP_SIZE_MASK 0x07000000L +//HUBP3_DCHUBP_REQ_SIZE_CONFIG_C +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C__SHIFT 0x0 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C__SHIFT 0x4 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C__SHIFT 0x8 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C__SHIFT 0xb +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C__SHIFT 0x10 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C__SHIFT 0x12 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C__SHIFT 0x14 +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__SWATH_HEIGHT_C_MASK 0x00000007L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__PTE_ROW_HEIGHT_LINEAR_C_MASK 0x00000070L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__CHUNK_SIZE_C_MASK 0x00000700L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_CHUNK_SIZE_C_MASK 0x00001800L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__META_CHUNK_SIZE_C_MASK 0x00030000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__MIN_META_CHUNK_SIZE_C_MASK 0x000C0000L +#define HUBP3_DCHUBP_REQ_SIZE_CONFIG_C__DPTE_GROUP_SIZE_C_MASK 0x00700000L +//HUBP3_DCHUBP_CNTL +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN__SHIFT 0x0 +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ__SHIFT 0x1 +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET__SHIFT 0x2 +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK__SHIFT 0x3 +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL__SHIFT 0x4 +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC__SHIFT 0x8 +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM__SHIFT 0x9 +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE__SHIFT 0xa +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS__SHIFT 0xb +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE__SHIFT 0xc +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE__SHIFT 0xd +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ__SHIFT 0x10 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS__SHIFT 0x14 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD__SHIFT 0x18 +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR__SHIFT 0x1a +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN__SHIFT 0x1b +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS__SHIFT 0x1c +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR__SHIFT 0x1f +#define HUBP3_DCHUBP_CNTL__HUBP_BLANK_EN_MASK 0x00000001L +#define HUBP3_DCHUBP_CNTL__HUBP_NO_OUTSTANDING_REQ_MASK 0x00000002L +#define HUBP3_DCHUBP_CNTL__HUBP_SOFT_RESET_MASK 0x00000004L +#define HUBP3_DCHUBP_CNTL__HUBP_IN_BLANK_MASK 0x00000008L +#define HUBP3_DCHUBP_CNTL__HUBP_VTG_SEL_MASK 0x000000F0L +#define HUBP3_DCHUBP_CNTL__HUBP_VREADY_AT_OR_AFTER_VSYNC_MASK 0x00000100L +#define HUBP3_DCHUBP_CNTL__HUBP_DISABLE_STOP_DATA_DURING_VM_MASK 0x00000200L +#define HUBP3_DCHUBP_CNTL__HUBP_UNBOUNDED_REQ_MODE_MASK 0x00000400L +#define HUBP3_DCHUBP_CNTL__HUBP_SEG_ALLOC_ERR_STATUS_MASK 0x00000800L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_DISABLE_MASK 0x00001000L +#define HUBP3_DCHUBP_CNTL__HUBP_TTU_MODE_MASK 0x0000E000L +#define HUBP3_DCHUBP_CNTL__HUBP_XRQ_NO_OUTSTANDING_REQ_MASK 0x000F0000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_MASK 0x00F00000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_THRESHOLD_MASK 0x03000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_STATUS_CLEAR_MASK 0x04000000L +#define HUBP3_DCHUBP_CNTL__HUBP_TIMEOUT_INTERRUPT_EN_MASK 0x08000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_STATUS_MASK 0x70000000L +#define HUBP3_DCHUBP_CNTL__HUBP_UNDERFLOW_CLEAR_MASK 0x80000000L +//HUBP3_HUBP_CLK_CNTL +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE__SHIFT 0x0 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS__SHIFT 0x5 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS__SHIFT 0x8 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS__SHIFT 0xc +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS__SHIFT 0x10 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON__SHIFT 0x14 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON__SHIFT 0x15 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON__SHIFT 0x16 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON__SHIFT 0x17 +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS__SHIFT 0x18 +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON__SHIFT 0x19 +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL__SHIFT 0x1c +#define HUBP3_HUBP_CLK_CNTL__HUBP_CLOCK_ENABLE_MASK 0x00000001L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_GATE_DIS_MASK 0x00000020L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_GATE_DIS_MASK 0x00000100L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_GATE_DIS_MASK 0x00001000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_GATE_DIS_MASK 0x00010000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_R_CLOCK_ON_MASK 0x00100000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DPPCLK_G_CLOCK_ON_MASK 0x00200000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_R_CLOCK_ON_MASK 0x00400000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DCFCLK_G_CLOCK_ON_MASK 0x00800000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_FGCG_REP_DIS_MASK 0x01000000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_DISPCLK_G_CLOCK_ON_MASK 0x02000000L +#define HUBP3_HUBP_CLK_CNTL__HUBP_TEST_CLK_SEL_MASK 0xF0000000L +//HUBP3_DCHUBP_VMPG_CONFIG +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE__SHIFT 0x0 +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE__SHIFT 0x1 +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE__SHIFT 0x2 +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME__SHIFT 0x7 +#define HUBP3_DCHUBP_VMPG_CONFIG__VMPG_SIZE_MASK 0x00000001L +#define HUBP3_DCHUBP_VMPG_CONFIG__PTE_BUFFER_MODE_MASK 0x00000002L +#define HUBP3_DCHUBP_VMPG_CONFIG__BIGK_FRAGMENT_SIZE_MASK 0x0000007CL +#define HUBP3_DCHUBP_VMPG_CONFIG__FORCE_ONE_ROW_FOR_FRAME_MASK 0x00000080L +//HUBP3_DCHUBP_MALL_CONFIG +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR__SHIFT 0x2 +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_SEL_MASK 0x00000003L +#define HUBP3_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR_MASK 0x00000004L +//HUBP3_DCHUBP_MALL_SUB_VP +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE__SHIFT 0x0 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0__SHIFT 0x1 +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1__SHIFT 0xf +#define HUBP3_DCHUBP_MALL_SUB_VP__USE_MALL_AT_START_LINE_MASK 0x00000001L +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S0_MASK 0x00007FFEL +#define HUBP3_DCHUBP_MALL_SUB_VP__SUB_VP_START_LINE_S1_MASK 0x1FFF8000L +//HUBP3_HUBPREQ_DEBUG_DB +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG_DB__HUBPREQ_DEBUG_MASK 0xFFFFFFFFL +//HUBP3_HUBPREQ_DEBUG +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG__SHIFT 0x0 +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS__SHIFT 0x1f +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_MASK 0x7FFFFFFFL +#define HUBP3_HUBPREQ_DEBUG__HUBPREQ_DEBUG_FLIP_REQ_DURING_MALL_STATUS_MASK 0x80000000L +//HUBP3_HUBP_DEBUG_CTRL +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_EN__SHIFT 0x0 +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS__SHIFT 0x4 +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_EN_MASK 0x00000001L +#define HUBP3_HUBP_DEBUG_CTRL__HUBP_DBG_HUBP_DCFCLK_G_DIS_MASK 0x00000010L +//HUBP3_HUBP_DEBUG_MUX_DCFCLK +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK__SHIFT 0x8 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK__SHIFT 0x10 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK__SHIFT 0x18 +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL0_DCFCLK_MASK 0x000000FFL +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL1_DCFCLK_MASK 0x0000FF00L +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL2_DCFCLK_MASK 0x00FF0000L +#define HUBP3_HUBP_DEBUG_MUX_DCFCLK__HUBP_DBG_DATA_SEL3_DCFCLK_MASK 0xFF000000L +//HUBP3_HUBP_DEBUG_MUX_DPPCLK +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK__SHIFT 0x8 +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DPPCLK_MASK 0x00000007L +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL1_DPPCLK_MASK 0x00000070L +#define HUBP3_HUBP_DEBUG_MUX_DPPCLK__HUBP_DBG_DATA_SEL0_DISPCLK_MASK 0x00000700L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK__SHIFT 0x1c +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_EN_DCFCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_PERIOD_M1_DCFCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_START_SEL_DCFCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_PERFMON_STOP_SEL_DCFCLK_MASK 0x01F00000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK__HUBP_MEASURE_WIN_MODE_DCFCLK_MASK 0x30000000L +//HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK__SHIFT 0x0 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK__SHIFT 0x1 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK__SHIFT 0x4 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK__SHIFT 0xc +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK__SHIFT 0x14 +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_EN_DPPCLK_MASK 0x00000001L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_SRC_SEL_DPPCLK_MASK 0x00000002L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_MEASURE_WIN_PERIOD_M1_DPPCLK_MASK 0x00000FF0L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_START_SEL_DPPCLK_MASK 0x0001F000L +#define HUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK__HUBP_PERFMON_STOP_SEL_DPPCLK_MASK 0x01F00000L +//HUBP3_HUBP_MALL_STATUS +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN__SHIFT 0x0 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE__SHIFT 0x1 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST__SHIFT 0x2 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE__SHIFT 0x3 +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE__SHIFT 0x4 +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE__SHIFT 0x5 +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE__SHIFT 0x6 +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE__SHIFT 0x7 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE__SHIFT 0x8 +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH__SHIFT 0x9 +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME__SHIFT 0xa +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME__SHIFT 0xb +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL__SHIFT 0xc +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL__SHIFT 0xd +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL__SHIFT 0xe +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME__SHIFT 0xf +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS__SHIFT 0x10 +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING__SHIFT 0x11 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING__SHIFT 0x12 +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO__SHIFT 0x13 +#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP__SHIFT 0x14 +#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP__SHIFT 0x15 +#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING__SHIFT 0x16 +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP__SHIFT 0x17 +#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING__SHIFT 0x18 +#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING__SHIFT 0x19 +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_STATIC_SCREEN_MASK 0x00000001L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQ_FOR_PSTATE_CHANGE_MASK 0x00000002L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_REQUEST_MASK 0x00000004L +#define HUBP3_HUBP_MALL_STATUS__MALL_USE_RESPONSE_MASK 0x00000008L +#define HUBP3_HUBP_MALL_STATUS__MALL_IN_USE_MASK 0x00000010L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_COMPLETE_MASK 0x00000020L +#define HUBP3_HUBP_MALL_STATUS__SUB_VP_MALL_RETRIEVE_MASK 0x00000040L +#define HUBP3_HUBP_MALL_STATUS__MCB_MALL_USE_RESPONSE_MASK 0x00000080L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_RETRIEVE_MASK 0x00000100L +#define HUBP3_HUBP_MALL_STATUS__CURSOR_LOCAL_PREFETCH_MASK 0x00000200L +#define HUBP3_HUBP_MALL_STATUS__MALL_RETRIEVE_FRAME_MASK 0x00000400L +#define HUBP3_HUBP_MALL_STATUS__MALL_PREFETCH_FRAME_MASK 0x00000800L +#define HUBP3_HUBP_MALL_STATUS__CRQ_BUSY_WITH_MALL_MASK 0x00001000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_MASK 0x00002000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_BUSY_WITH_MALL_MASK 0x00004000L +#define HUBP3_HUBP_MALL_STATUS__USE_ONE_ROW_FOR_FRAME_MASK 0x00008000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_RETRIEVE_IN_PROGRESS_MASK 0x00010000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_SUB_VP_MALL_OUTSTANDING_MASK 0x00020000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_OUTSTANDING_MASK 0x00040000L +#define HUBP3_HUBP_MALL_STATUS__DRQ_MALL_CNT_ZERO_MASK 0x00080000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_S1_MALL_RETRIEVE_SUB_VP_MASK 0x00100000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_S0_MALL_RETRIEVE_SUB_VP_MASK 0x00200000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_MALL_OUTSTANDING_MASK 0x00400000L +#define HUBP3_HUBP_MALL_STATUS__MRQ_BUSY_WITH_MALL_SUB_VP_MASK 0x00800000L +#define HUBP3_HUBP_MALL_STATUS__CRQ_MALL_OUTSTANDING_MASK 0x01000000L +#define HUBP3_HUBP_MALL_STATUS__CRQ_LOCAL_OUTSTANDING_MASK 0x02000000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec +//HUBPREQ3_DCSURF_SURFACE_PITCH +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH__PITCH_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH__META_PITCH_MASK 0x3FFF0000L +//HUBPREQ3_DCSURF_SURFACE_PITCH_C +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__PITCH_C_MASK 0x00003FFFL +#define HUBPREQ3_DCSURF_SURFACE_PITCH_C__META_PITCH_C_MASK 0x3FFF0000L +//HUBPREQ3_VMID_SETTINGS_0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID__SHIFT 0x0 +#define HUBPREQ3_VMID_SETTINGS_0__VMID_MASK 0x0000000FL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS__PRIMARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH__PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C__PRIMARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C__PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS__SECONDARY_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH__SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C__SECONDARY_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C__SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS__PRIMARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH__PRIMARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C__PRIMARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C__PRIMARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS__SECONDARY_META_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH__SECONDARY_META_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C__SECONDARY_META_SURFACE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C__SECONDARY_META_SURFACE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +//HUBPREQ3_DCSURF_SURFACE_CONTROL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN__SHIFT 0x4 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK__SHIFT 0x5 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C__SHIFT 0x7 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C__SHIFT 0xb +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ__SHIFT 0xd +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C__SHIFT 0x14 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C__SHIFT 0x18 +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ__SHIFT 0x1a +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C__SHIFT 0x1b +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C__SHIFT 0x1d +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_MASK 0x0000000FL +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_EN_MASK 0x00000010L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_MASK 0x00000060L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_TMZ_C_MASK 0x00000780L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_SURFACE_DCC_IND_BLK_C_MASK 0x00001800L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_MASK 0x0001E000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_EN_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_MASK 0x000C0000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_TMZ_C_MASK 0x00F00000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_SURFACE_DCC_IND_BLK_C_MASK 0x03000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_MASK 0x04000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__PRIMARY_META_SURFACE_TMZ_C_MASK 0x08000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_MASK 0x10000000L +#define HUBPREQ3_DCSURF_SURFACE_CONTROL__SECONDARY_META_SURFACE_TMZ_C_MASK 0x20000000L +//HUBPREQ3_DCSURF_FLIP_CONTROL +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM__SHIFT 0x4 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC__SHIFT 0x10 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE__SHIFT 0x11 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY__SHIFT 0x12 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY__SHIFT 0x14 +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_UPDATE_LOCK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_VUPDATE_SKIP_NUM_MASK 0x000000F0L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__HUBPREQ_MASTER_UPDATE_LOCK_STATUS_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_MODE_FOR_STEREOSYNC_MASK 0x00003000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_IN_STEREOSYNC_MASK 0x00010000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_DISABLE_MASK 0x00020000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_STEREO_SELECT_POLARITY_MASK 0x00040000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL__SURFACE_FLIP_PENDING_DELAY_MASK 0x3FF00000L +//HUBPREQ3_DCSURF_FLIP_CONTROL2 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME__SHIFT 0x0 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE__SHIFT 0x8 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK__SHIFT 0x9 +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE__SHIFT 0xa +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH__SHIFT 0xc +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE__SHIFT 0x1c +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE__SHIFT 0x1f +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_PENDING_MIN_TIME_MASK 0x000000FFL +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_ENABLE_MASK 0x00000100L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_GSL_MASK_MASK 0x00000200L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_TRIPLE_BUFFER_ENABLE_MASK 0x00000400L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_INUSE_RAED_NO_LATCH_MASK 0x00001000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__IMME_FLIP_BUF_TRACK_MODE_MASK 0x10000000L +#define HUBPREQ3_DCSURF_FLIP_CONTROL2__SURFACE_FLIP_EXEC_DEBUG_MODE_MASK 0x80000000L +//HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE__SHIFT 0x1 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK__SHIFT 0x2 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE__SHIFT 0x3 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR__SHIFT 0x8 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR__SHIFT 0x9 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED__SHIFT 0x10 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS__SHIFT 0x11 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED__SHIFT 0x12 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS__SHIFT 0x13 +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_MASK_MASK 0x00000001L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_TYPE_MASK 0x00000002L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_MASK_MASK 0x00000004L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_TYPE_MASK 0x00000008L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_CLEAR_MASK 0x00000100L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_CLEAR_MASK 0x00000200L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_OCCURRED_MASK 0x00010000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_INT_STATUS_MASK 0x00020000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_OCCURRED_MASK 0x00040000L +#define HUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT__SURFACE_FLIP_AWAY_INT_STATUS_MASK 0x00080000L +//HUBPREQ3_DCSURF_SURFACE_INUSE +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE__SURFACE_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH__SURFACE_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_C__SURFACE_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C__SURFACE_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE__SURFACE_EARLIEST_INUSE_ADDRESS_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH__SURFACE_EARLIEST_INUSE_VMID_MASK 0xF0000000L +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C__SURFACE_EARLIEST_INUSE_ADDRESS_C_MASK 0xFFFFFFFFL +//HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C__SHIFT 0x0 +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C__SHIFT 0x1c +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C_MASK 0x0000FFFFL +#define HUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C__SURFACE_EARLIEST_INUSE_VMID_C_MASK 0xF0000000L +//HUBPREQ3_DCN_EXPANSION_MODE +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE__SHIFT 0x0 +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE__SHIFT 0x2 +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE__SHIFT 0x4 +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE__SHIFT 0x6 +#define HUBPREQ3_DCN_EXPANSION_MODE__DRQ_EXPANSION_MODE_MASK 0x00000003L +#define HUBPREQ3_DCN_EXPANSION_MODE__CRQ_EXPANSION_MODE_MASK 0x0000000CL +#define HUBPREQ3_DCN_EXPANSION_MODE__MRQ_EXPANSION_MODE_MASK 0x00000030L +#define HUBPREQ3_DCN_EXPANSION_MODE__PRQ_EXPANSION_MODE_MASK 0x000000C0L +//HUBPREQ3_DCN_TTU_QOS_WM +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM__SHIFT 0x0 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM__SHIFT 0x10 +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_LOW_WM_MASK 0x00003FFFL +#define HUBPREQ3_DCN_TTU_QOS_WM__QoS_LEVEL_HIGH_WM_MASK 0x3FFF0000L +//HUBPREQ3_DCN_GLOBAL_TTU_CNTL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK__SHIFT 0x0 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT__SHIFT 0x18 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT__SHIFT 0x19 +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE__SHIFT 0x1b +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP__SHIFT 0x1c +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__MIN_TTU_VBLANK_MASK 0x00FFFFFFL +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PIPE_IN_FLUSH_URGENT_MASK 0x01000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__PRQ_MRQ_FLUSH_URGENT_MASK 0x02000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__ROW_TTU_MODE_MASK 0x08000000L +#define HUBPREQ3_DCN_GLOBAL_TTU_CNTL__QoS_LEVEL_FLIP_MASK 0xF0000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF0_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_SURF1_TTU_CNTL0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_SURF1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_SURF1_TTU_CNTL1 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_SURF1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR0_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR0_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR0_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR0_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_CUR1_TTU_CNTL0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED__SHIFT 0x18 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE__SHIFT 0x1c +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__REFCYC_PER_REQ_DELIVERY_MASK 0x007FFFFFL +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_LEVEL_FIXED_MASK 0x0F000000L +#define HUBPREQ3_DCN_CUR1_TTU_CNTL0__QoS_RAMP_DISABLE_MASK 0x10000000L +//HUBPREQ3_DCN_CUR1_TTU_CNTL1 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE__SHIFT 0x0 +#define HUBPREQ3_DCN_CUR1_TTU_CNTL1__REFCYC_PER_REQ_DELIVERY_PRE_MASK 0x007FFFFFL +//HUBPREQ3_DCN_DMDATA_VM_CNTL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA__SHIFT 0x0 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS__SHIFT 0x10 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR__SHIFT 0x14 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS__SHIFT 0x18 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS__SHIFT 0x19 +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR__SHIFT 0x1a +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE__SHIFT 0x1f +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__REFCYC_PER_VM_DMDATA_MASK 0x0000FFFFL +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_MASK 0x000F0000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_FAULT_STATUS_CLEAR_MASK 0x00100000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_MASK 0x01000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_LATE_STATUS_MASK 0x02000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_UNDERFLOW_STATUS_CLEAR_MASK 0x04000000L +#define HUBPREQ3_DCN_DMDATA_VM_CNTL__DMDATA_VM_DONE_MASK 0x80000000L +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR__MC_VM_SYSTEM_APERTURE_LOW_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR__MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MASK 0x3FFFFFFFL +//HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define HUBPREQ3_DCN_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +//HUBPREQ3_BLANK_OFFSET_0 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END__SHIFT 0x10 +#define HUBPREQ3_BLANK_OFFSET_0__REFCYC_H_BLANK_END_MASK 0x00001FFFL +#define HUBPREQ3_BLANK_OFFSET_0__DLG_V_BLANK_END_MASK 0x7FFF0000L +//HUBPREQ3_BLANK_OFFSET_1 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START__SHIFT 0x0 +#define HUBPREQ3_BLANK_OFFSET_1__MIN_DST_Y_NEXT_START_MASK 0x0003FFFFL +//HUBPREQ3_DST_DIMENSIONS +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL__SHIFT 0x0 +#define HUBPREQ3_DST_DIMENSIONS__REFCYC_PER_HTOTAL_MASK 0x001FFFFFL +//HUBPREQ3_DST_AFTER_SCALER +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER__SHIFT 0x0 +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER__SHIFT 0x10 +#define HUBPREQ3_DST_AFTER_SCALER__REFCYC_X_AFTER_SCALER_MASK 0x00001FFFL +#define HUBPREQ3_DST_AFTER_SCALER__DST_Y_AFTER_SCALER_MASK 0x00070000L +//HUBPREQ3_PREFETCH_SETTINGS +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH__SHIFT 0x18 +#define HUBPREQ3_PREFETCH_SETTINGS__VRATIO_PREFETCH_MASK 0x003FFFFFL +#define HUBPREQ3_PREFETCH_SETTINGS__DST_Y_PREFETCH_MASK 0xFF000000L +//HUBPREQ3_PREFETCH_SETTINGS_C +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C__SHIFT 0x0 +#define HUBPREQ3_PREFETCH_SETTINGS_C__VRATIO_PREFETCH_C_MASK 0x003FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK__SHIFT 0x8 +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_VM_VBLANK_MASK 0x0000007FL +#define HUBPREQ3_VBLANK_PARAMETERS_0__DST_Y_PER_ROW_VBLANK_MASK 0x00003F00L +//HUBPREQ3_VBLANK_PARAMETERS_1 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_1__REFCYC_PER_PTE_GROUP_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_2 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_2__REFCYC_PER_PTE_GROUP_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_3 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_3__REFCYC_PER_META_CHUNK_VBLANK_L_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_4 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_4__REFCYC_PER_META_CHUNK_VBLANK_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP__SHIFT 0x8 +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_VM_FLIP_MASK 0x0000007FL +#define HUBPREQ3_FLIP_PARAMETERS_0__DST_Y_PER_ROW_FLIP_MASK 0x00003F00L +//HUBPREQ3_FLIP_PARAMETERS_1 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_1__REFCYC_PER_PTE_GROUP_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_2 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_2__REFCYC_PER_META_CHUNK_FLIP_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_0__DST_Y_PER_PTE_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_1 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_1__REFCYC_PER_PTE_GROUP_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_2 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_2__DST_Y_PER_PTE_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_3 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_3__REFCYC_PER_PTE_GROUP_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_4 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_4__DST_Y_PER_META_ROW_NOM_L_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_5 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_5__REFCYC_PER_META_CHUNK_NOM_L_MASK 0x007FFFFFL +//HUBPREQ3_NOM_PARAMETERS_6 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_6__DST_Y_PER_META_ROW_NOM_C_MASK 0x0001FFFFL +//HUBPREQ3_NOM_PARAMETERS_7 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C__SHIFT 0x0 +#define HUBPREQ3_NOM_PARAMETERS_7__REFCYC_PER_META_CHUNK_NOM_C_MASK 0x007FFFFFL +//HUBPREQ3_PER_LINE_DELIVERY_PRE +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY_PRE__REFCYC_PER_LINE_DELIVERY_PRE_C_MASK 0x1FFF0000L +//HUBPREQ3_PER_LINE_DELIVERY +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L__SHIFT 0x0 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C__SHIFT 0x10 +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_L_MASK 0x00001FFFL +#define HUBPREQ3_PER_LINE_DELIVERY__REFCYC_PER_LINE_DELIVERY_C_MASK 0x1FFF0000L +//HUBPREQ3_CURSOR_SETTINGS +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET__SHIFT 0x0 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST__SHIFT 0x8 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET__SHIFT 0x10 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST__SHIFT 0x18 +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET_MASK 0x000000FFL +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST_MASK 0x00000300L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_DST_Y_OFFSET_MASK 0x00FF0000L +#define HUBPREQ3_CURSOR_SETTINGS__CURSOR1_CHUNK_HDL_ADJUST_MASK 0x03000000L +//HUBPREQ3_REF_FREQ_TO_PIX_FREQ +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ__SHIFT 0x0 +#define HUBPREQ3_REF_FREQ_TO_PIX_FREQ__REF_FREQ_TO_PIX_FREQ_MASK 0x001FFFFFL +//HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT__SHIFT 0x0 +#define HUBPREQ3_DST_Y_DELTA_DRQ_LIMIT__DST_Y_DELTA_DRQ_LIMIT_MASK 0x00007FFFL +//HUBPREQ3_HUBPREQ_MEM_PWR_CTRL +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS__SHIFT 0xe +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE__SHIFT 0xf +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_FORCE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_DPTE_MEM_PWR_DIS_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_FORCE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_MPTE_MEM_PWR_DIS_MASK 0x00000040L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_META_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_FORCE_MASK 0x00003000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_PDE_MEM_PWR_DIS_MASK 0x00004000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_FORCE_MASK 0x00018000L +#define HUBPREQ3_HUBPREQ_MEM_PWR_CTRL__REQ_TPTE_MEM_PWR_DIS_MASK 0x00020000L +//HUBPREQ3_HUBPREQ_MEM_PWR_STATUS +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE__SHIFT 0x6 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_DPTE_MEM_PWR_STATE_MASK 0x00000003L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_MPTE_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_META_MEM_PWR_STATE_MASK 0x00000030L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_PDE_MEM_PWR_STATE_MASK 0x000000C0L +#define HUBPREQ3_HUBPREQ_MEM_PWR_STATUS__REQ_TPTE_MEM_PWR_STATE_MASK 0x00000300L +//HUBPREQ3_VBLANK_PARAMETERS_5 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_5__REFCYC_PER_VM_GROUP_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_VBLANK_PARAMETERS_6 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK__SHIFT 0x0 +#define HUBPREQ3_VBLANK_PARAMETERS_6__REFCYC_PER_VM_REQ_VBLANK_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_3 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_3__REFCYC_PER_VM_GROUP_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_4 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_4__REFCYC_PER_VM_REQ_FLIP_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_5 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_5__REFCYC_PER_PTE_GROUP_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_FLIP_PARAMETERS_6 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C__SHIFT 0x0 +#define HUBPREQ3_FLIP_PARAMETERS_6__REFCYC_PER_META_CHUNK_FLIP_C_MASK 0x007FFFFFL +//HUBPREQ3_UCLK_PSTATE_FORCE +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN__SHIFT 0x0 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x1 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN__SHIFT 0x2 +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE__SHIFT 0x3 +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_EN_MASK 0x00000001L +#define HUBPREQ3_UCLK_PSTATE_FORCE__DATA_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000002L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_EN_MASK 0x00000004L +#define HUBPREQ3_UCLK_PSTATE_FORCE__CURSOR_UCLK_PSTATE_FORCE_VALUE_MASK 0x00000008L +//HUBPREQ3_HUBPREQ_STATUS_REG0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S0_MASK 0x0000001FL +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_MPTE_ROW_READY_S1_MASK 0x00001F00L +#define HUBPREQ3_HUBPREQ_STATUS_REG0__STATUS_VTG_COUNT_MASK 0x7FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG1 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S0_MASK 0x00003FFFL +#define HUBPREQ3_HUBPREQ_STATUS_REG1__STATUS_CHUNK_REQ_X_OR_Y_S1_MASK 0x3FFF0000L +//HUBPREQ3_HUBPREQ_STATUS_REG2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0__SHIFT 0x0 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0__SHIFT 0x1 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0__SHIFT 0x2 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0__SHIFT 0x3 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0__SHIFT 0x4 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0__SHIFT 0x5 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1__SHIFT 0x8 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1__SHIFT 0x9 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1__SHIFT 0xa +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1__SHIFT 0xb +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1__SHIFT 0xc +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1__SHIFT 0xd +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR__SHIFT 0x10 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR__SHIFT 0x11 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR__SHIFT 0x12 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR__SHIFT 0x13 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR__SHIFT 0x14 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR__SHIFT 0x15 +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK__SHIFT 0x1a +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN__SHIFT 0x1b +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY__SHIFT 0x1c +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH__SHIFT 0x1d +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0__SHIFT 0x1e +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1__SHIFT 0x1f +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S0_MASK 0x00000001L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S0_MASK 0x00000002L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S0_MASK 0x00000004L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S0_MASK 0x00000008L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S0_MASK 0x00000010L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S0_MASK 0x00000020L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_S1_MASK 0x00000100L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_S1_MASK 0x00000200L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_S1_MASK 0x00000400L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_S1_MASK 0x00000800L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_S1_MASK 0x00001000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_S1_MASK 0x00002000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_EXIT_SELF_REFRESH_CUR_MASK 0x00010000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ENTER_SELF_REFRESH_CUR_MASK 0x00020000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_UCLK_PSTATE_CHANGE_CUR_MASK 0x00040000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_FCLK_PSTATE_CHANGE_CUR_MASK 0x00080000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_ALLOW_USR_RETRAINING_CUR_MASK 0x00100000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_QOS_URGENT_CUR_MASK 0x00200000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_VBLANK_MASK 0x04000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_HUBP_EN_MASK 0x08000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_RECOVERY_MASK 0x10000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_PIPE_IN_FLUSH_MASK 0x20000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S0_MASK 0x40000000L +#define HUBPREQ3_HUBPREQ_STATUS_REG2__STATUS_FLIP_ACTIVE_S1_MASK 0x80000000L + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec +//HUBPRET3_HUBPRET_CONTROL +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS__SHIFT 0x4 +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE__SHIFT 0xf +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA__SHIFT 0x10 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G__SHIFT 0x12 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B__SHIFT 0x14 +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R__SHIFT 0x16 +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE__SHIFT 0x18 +#define HUBPRET3_HUBPRET_CONTROL__DET_BUF_PLANE1_BASE_ADDRESS_MASK 0x00007FF0L +#define HUBPRET3_HUBPRET_CONTROL__PACK_3TO2_ELEMENT_DISABLE_MASK 0x00008000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_ALPHA_MASK 0x00030000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_Y_G_MASK 0x000C0000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CB_B_MASK 0x00300000L +#define HUBPRET3_HUBPRET_CONTROL__CROSSBAR_SRC_CR_R_MASK 0x00C00000L +#define HUBPRET3_HUBPRET_CONTROL__HUBPRET_CONTROL_SPARE_MASK 0xFF000000L +//HUBPRET3_HUBPRET_MEM_PWR_CTRL +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS__SHIFT 0xa +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE__SHIFT 0x14 +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_FORCE_MASK 0x00000300L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__DMROB_MEM_PWR_DIS_MASK 0x00000400L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_FORCE_MASK 0x00030000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_DIS_MASK 0x00040000L +#define HUBPRET3_HUBPRET_MEM_PWR_CTRL__PIXCDC_MEM_PWR_LS_MODE_MASK 0x00300000L +//HUBPRET3_HUBPRET_MEM_PWR_STATUS +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE__SHIFT 0x2 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__DMROB_MEM_PWR_STATE_MASK 0x0000000CL +#define HUBPRET3_HUBPRET_MEM_PWR_STATUS__PIXCDC_MEM_PWR_STATE_MASK 0x00000030L +//HUBPRET3_HUBPRET_READ_LINE_CTRL0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_INTERVAL_IN_NONACTIVE_MASK 0x0000FFFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL0__PIPE_READ_LINE_VBLANK_MAXIMUM_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_CTRL1 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__PIPE_READ_LINE_REPORTED_WHEN_REQ_DISABLED_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_CTRL1__HUBPRET_READ_LINE_CTRL1_SPARE_MASK 0xFFFF0000L +//HUBPRET3_HUBPRET_READ_LINE0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE0__PIPE_READ_LINE0_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE1 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_START_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE1__PIPE_READ_LINE1_END_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_INTERRUPT +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK__SHIFT 0x1 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK__SHIFT 0x2 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE__SHIFT 0x6 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR__SHIFT 0x8 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR__SHIFT 0x9 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR__SHIFT 0xa +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS__SHIFT 0xc +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS__SHIFT 0xd +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS__SHIFT 0xe +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS__SHIFT 0x10 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS__SHIFT 0x11 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS__SHIFT 0x12 +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_MASK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_MASK_MASK 0x00000002L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_MASK_MASK 0x00000004L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_TYPE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_TYPE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_TYPE_MASK 0x00000040L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_CLEAR_MASK 0x00000100L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_CLEAR_MASK 0x00000200L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_CLEAR_MASK 0x00000400L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_STATUS_MASK 0x00001000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_STATUS_MASK 0x00002000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_STATUS_MASK 0x00004000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_VBLANK_INT_STATUS_MASK 0x00010000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE0_INT_STATUS_MASK 0x00020000L +#define HUBPRET3_HUBPRET_INTERRUPT__PIPE_READ_LINE1_INT_STATUS_MASK 0x00040000L +//HUBPRET3_HUBPRET_READ_LINE_VALUE +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT__SHIFT 0x10 +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_MASK 0x00003FFFL +#define HUBPRET3_HUBPRET_READ_LINE_VALUE__PIPE_READ_LINE_SNAPSHOT_MASK 0x3FFF0000L +//HUBPRET3_HUBPRET_READ_LINE_STATUS +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK__SHIFT 0x0 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE__SHIFT 0x4 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE__SHIFT 0x5 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE__SHIFT 0x8 +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE__SHIFT 0xa +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_VBLANK_MASK 0x00000001L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_INSIDE_MASK 0x00000010L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE0_OUTSIDE_MASK 0x00000020L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_INSIDE_MASK 0x00000100L +#define HUBPRET3_HUBPRET_READ_LINE_STATUS__PIPE_READ_LINE1_OUTSIDE_MASK 0x00000400L + + +// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec +//CURSOR0_3_CURSOR_CONTROL +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE__SHIFT 0x2 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE__SHIFT 0x8 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ__SHIFT 0xc +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS__SHIFT 0x14 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK__SHIFT 0x18 +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN__SHIFT 0x1e +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL__SHIFT 0x1f +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_ENABLE_MASK 0x00000001L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_REQ_MODE_MASK 0x00000004L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00000010L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_MODE_MASK 0x00000700L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_TMZ_MASK 0x00001000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PITCH_MASK 0x00030000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_MASK 0x00100000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK_MASK 0x1F000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_EN_MASK 0x40000000L +#define CURSOR0_3_CURSOR_CONTROL__CURSOR_PERFMON_LATENCY_MEASURE_SEL_MASK 0x80000000L +//CURSOR0_3_CURSOR_SURFACE_ADDRESS +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xFFFFFFFFL +//CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_CURSOR_SIZE +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT__SHIFT 0x0 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH__SHIFT 0x10 +#define CURSOR0_3_CURSOR_SIZE__CURSOR_HEIGHT_MASK 0x000001FFL +#define CURSOR0_3_CURSOR_SIZE__CURSOR_WIDTH_MASK 0x01FF0000L +//CURSOR0_3_CURSOR_POSITION +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION__SHIFT 0x0 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION__SHIFT 0x10 +#define CURSOR0_3_CURSOR_POSITION__CURSOR_Y_POSITION_MASK 0x00003FFFL +#define CURSOR0_3_CURSOR_POSITION__CURSOR_X_POSITION_MASK 0x3FFF0000L +//CURSOR0_3_CURSOR_HOT_SPOT +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x0 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x10 +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x000000FFL +#define CURSOR0_3_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x00FF0000L +//CURSOR0_3_CURSOR_STEREO_CONTROL +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN__SHIFT 0x0 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET__SHIFT 0x4 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET__SHIFT 0x12 +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_STEREO_EN_MASK 0x00000001L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_PRIMARY_OFFSET_MASK 0x0003FFF0L +#define CURSOR0_3_CURSOR_STEREO_CONTROL__CURSOR_SECONDARY_OFFSET_MASK 0xFFFC0000L +//CURSOR0_3_CURSOR_DST_OFFSET +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET__SHIFT 0x0 +#define CURSOR0_3_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET_MASK 0x00001FFFL +//CURSOR0_3_CURSOR_MEM_PWR_CTRL +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS__SHIFT 0x2 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE__SHIFT 0x4 +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_FORCE_MASK 0x00000003L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_DIS_MASK 0x00000004L +#define CURSOR0_3_CURSOR_MEM_PWR_CTRL__CROB_MEM_PWR_LS_MODE_MASK 0x00000030L +//CURSOR0_3_CURSOR_MEM_PWR_STATUS +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE__SHIFT 0x0 +#define CURSOR0_3_CURSOR_MEM_PWR_STATUS__CROB_MEM_PWR_STATE_MASK 0x00000003L +//CURSOR0_3_DMDATA_ADDRESS_HIGH +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ__SHIFT 0x1e +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_ADDRESS_HIGH_MASK 0x0000FFFFL +#define CURSOR0_3_DMDATA_ADDRESS_HIGH__DMDATA_TMZ_MASK 0x40000000L +//CURSOR0_3_DMDATA_ADDRESS_LOW +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_DMDATA_ADDRESS_LOW__DMDATA_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_DMDATA_CNTL +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE__SHIFT 0x2 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_CNTL__DMDATA_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_MODE_MASK 0x00000004L +#define CURSOR0_3_DMDATA_CNTL__DMDATA_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_QOS_CNTL +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL__SHIFT 0x4 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA__SHIFT 0x10 +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_MODE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_QOS_LEVEL_MASK 0x000000F0L +#define CURSOR0_3_DMDATA_QOS_CNTL__DMDATA_DL_DELTA_MASK 0xFFFF0000L +//CURSOR0_3_DMDATA_STATUS +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE__SHIFT 0x0 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW__SHIFT 0x2 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR__SHIFT 0x4 +#define CURSOR0_3_DMDATA_STATUS__DMDATA_DONE_MASK 0x00000001L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_MASK 0x00000004L +#define CURSOR0_3_DMDATA_STATUS__DMDATA_UNDERFLOW_CLEAR_MASK 0x00000010L +//CURSOR0_3_DMDATA_SW_CNTL +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT__SHIFT 0x1 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE__SHIFT 0x10 +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_UPDATED_MASK 0x00000001L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_REPEAT_MASK 0x00000002L +#define CURSOR0_3_DMDATA_SW_CNTL__DMDATA_SW_SIZE_MASK 0x0FFF0000L +//CURSOR0_3_DMDATA_SW_DATA +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA__SHIFT 0x0 +#define CURSOR0_3_DMDATA_SW_DATA__DMDATA_SW_DATA_MASK 0xFFFFFFFFL +//CURSOR0_3_HUBP_3DLUT_CONTROL +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE__SHIFT 0x1 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH__SHIFT 0x2 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ__SHIFT 0x12 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B__SHIFT 0x16 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G__SHIFT 0x18 +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R__SHIFT 0x1a +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS__SHIFT 0x1d +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH__SHIFT 0x1e +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE__SHIFT 0x1f +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ENABLE_MASK 0x00000001L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_ADDRESSING_MODE_MASK 0x00000002L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WIDTH_MASK 0x0003FFFCL +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_TMZ_MASK 0x003C0000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_B_MASK 0x00C00000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_G_MASK 0x03000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_CROSSBAR_SEL_R_MASK 0x0C000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_WTRIG_FIX_DIS_MASK 0x20000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_MPC_WIDTH_MASK 0x40000000L +#define CURSOR0_3_HUBP_3DLUT_CONTROL__HUBP_3DLUT_DONE_MASK 0x80000000L +//CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_LOW__HUBP_3DLUT_ADDRESS_LOW_MASK 0xFFFFFFFFL +//CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_ADDRESS_HIGH__HUBP_3DLUT_ADDRESS_HIGH_MASK 0x0000FFFFL +//CURSOR0_3_HUBP_3DLUT_DLG_PARAM +#define CURSOR0_3_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP__SHIFT 0x0 +#define CURSOR0_3_HUBP_3DLUT_DLG_PARAM__REFCYC_PER_3DLUT_GROUP_MASK 0x007FFFFFL + + +// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON9_PERFCOUNTER_CNTL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_CNTL2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON9_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFCOUNTER_STATE +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON9_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON9_PERFMON_CNTL +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON9_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON9_PERFMON_CNTL2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON9_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON9_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON9_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON9_PERFMON_CVALUE_LOW +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON9_PERFMON_HI +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON9_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON9_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON9_PERFMON_LOW +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON9_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec +//DPP_TOP0_DPP_CONTROL +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP0_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP0_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP0_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP0_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP0_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP0_DPP_SOFT_RESET +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP0_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP0_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP0_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP0_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP0_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP0_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP0_DPP_CRC_VAL_R +#define DPP_TOP0_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_VAL_G +#define DPP_TOP0_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_VAL_B +#define DPP_TOP0_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_VAL_A +#define DPP_TOP0_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP0_DPP_CRC_CTRL +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP0_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP0_HOST_READ_CONTROL +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP0_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec +//CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG0_FORMAT_CONTROL +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG0_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG0_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG0_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG0_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG0_FCNV_FP_BIAS_R +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_G +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_BIAS_B +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_R +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_G +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG0_FCNV_FP_SCALE_B +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG0_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG0_COLOR_KEYER_CONTROL +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG0_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG0_COLOR_KEYER_ALPHA +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_RED +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_GREEN +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_COLOR_KEYER_BLUE +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG0_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT01 +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG0_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG0_ALPHA_2BIT_LUT23 +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG0_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG0_PRE_DEALPHA +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG0_PRE_CSC_MODE +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG0_PRE_CSC_C11_C12 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C13_C14 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C21_C22 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C23_C24 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C31_C32 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_C33_C34 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C11_C12 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C13_C14 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C21_C22 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C23_C24 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C31_C32 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG0_PRE_CSC_B_C33_C34 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG0_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG0_CNVC_COEF_FORMAT +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG0_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG0_PRE_DEGAM +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG0_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG0_PRE_REALPHA +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG0_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_cur_dispdec +//CM_CUR0_CURSOR0_CONTROL +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR0_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR0_CURSOR0_COLOR0 +#define CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR0_CURSOR0_COLOR1 +#define CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_MODE +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR0_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR0_CUR0_MATRIX_C11_C12_A +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C13_C14_A +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C21_C22_A +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C23_C24_A +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C31_C32_A +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C33_C34_A +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C11_C12_B +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C13_C14_B +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C21_C22_B +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C23_C24_B +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C31_C32_B +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR0_CUR0_MATRIX_C33_C34_B +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR0_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec +//DSCL0_SCL_COEF_RAM_TAP_SELECT +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL0_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL0_SCL_COEF_RAM_TAP_DATA +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL0_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL0_SCL_MODE +#define DSCL0_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL0_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL0_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL0_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL0_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL0_SCL_TAP_CONTROL +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL0_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL0_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL0_DSCL_CONTROL +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL0_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL0_DSCL_2TAP_CONTROL +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL0_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL0_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL0_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_HORZ_FILTER_INIT_C +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL0_SCL_VERT_FILTER_INIT_C +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL0_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL0_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL0_SCL_BLACK_COLOR +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL0_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL0_DSCL_UPDATE +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL0_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL0_DSCL_AUTOCAL +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL0_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL0_OTG_H_BLANK +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL0_OTG_V_BLANK +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL0_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL0_RECOUT_START +#define DSCL0_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL0_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL0_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL0_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL0_RECOUT_SIZE +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL0_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL0_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL0_MPC_SIZE +#define DSCL0_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL0_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL0_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL0_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL0_LB_DATA_FORMAT +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL0_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL0_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL0_LB_MEMORY_CTRL +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL0_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL0_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL0_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL0_LB_V_COUNTER +#define DSCL0_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL0_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL0_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL0_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL0_DSCL_MEM_PWR_CTRL +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL0_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL0_DSCL_MEM_PWR_STATUS +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL0_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL0_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL0_OBUF_CONTROL +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL0_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL0_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL0_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL0_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL0_OBUF_MEM_PWR_CTRL +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL0_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL0_DSCL_EASF_H_MODE +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL0_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL0_DSCL_EASF_V_MODE +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL0_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL0_DSCL_SC_MODE +#define DSCL0_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL0_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL0_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL0_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL0_DSCL_SC_MATRIX_C0C1 +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL0_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL0_DSCL_SC_MATRIX_C2C3 +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL0_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_RINGEST_FORCE +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL0_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL0_DSCL_EASF_H_BF_CNTL +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL0_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL0_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL0_DSCL_EASF_V_BF_CNTL +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL0_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL0_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL0_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL0_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL0_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL0_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL0_ISHARP_MODE +#define DSCL0_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL0_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL0_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL0_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL0_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL0_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL0_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL0_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL0_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL0_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL0_ISHARP_DELTA_CTRL +#define DSCL0_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL0_ISHARP_DELTA_INDEX +#define DSCL0_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL0_ISHARP_DELTA_DATA +#define DSCL0_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL0_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL0_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL0_ISHARP_NOISEDET_THRESHOLD +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL0_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL0_ISHARP_NOISE_GAIN_PWL +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL0_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL0_ISHARP_LBA_PWL_SEG0 +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG1 +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG2 +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG3 +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG4 +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL0_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL0_ISHARP_LBA_PWL_SEG5 +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL0_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL0_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec +//CM0_CM_CONTROL +#define CM0_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM0_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM0_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM0_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM0_CM_POST_CSC_CONTROL +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM0_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM0_CM_POST_CSC_C11_C12 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C13_C14 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C21_C22 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C23_C24 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C31_C32 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_C33_C34 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C11_C12 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C13_C14 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C21_C22 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C23_C24 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C31_C32 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM0_CM_POST_CSC_B_C33_C34 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM0_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM0_CM_BIAS_CR_R +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM0_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM0_CM_BIAS_Y_G_CB_B +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM0_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_CONTROL +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM0_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM0_CM_GAMCOR_LUT_INDEX +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM0_CM_GAMCOR_LUT_DATA +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_LUT_CONTROL +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM0_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM0_CM_GAMCOR_RAMA_START_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMA_OFFSET_B +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_G +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_OFFSET_R +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMA_REGION_0_1 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_2_3 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_4_5 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_6_7 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_8_9 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_10_11 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_12_13 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_14_15 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_16_17 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_18_19 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_20_21 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_22_23 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_24_25 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_26_27 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_28_29 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_30_31 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMA_REGION_32_33 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM0_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM0_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM0_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM0_CM_GAMCOR_RAMB_OFFSET_B +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_G +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_OFFSET_R +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM0_CM_GAMCOR_RAMB_REGION_0_1 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_2_3 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_4_5 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_6_7 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_8_9 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_10_11 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_12_13 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_14_15 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_16_17 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_18_19 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_20_21 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_22_23 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_24_25 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_26_27 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_28_29 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_30_31 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_GAMCOR_RAMB_REGION_32_33 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM0_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM0_CM_HDR_MULT_COEF +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM0_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM0_CM_MEM_PWR_CTRL +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM0_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM0_CM_MEM_PWR_STATUS +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM0_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM0_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM0_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM0_CM_DEALPHA +#define CM0_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM0_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM0_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM0_CM_COEF_FORMAT +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM0_CM_TEST_DEBUG_INDEX +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM0_CM_TEST_DEBUG_DATA +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM0_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM0_CM_HIST_CNTL +#define CM0_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM0_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM0_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM0_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM0_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM0_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM0_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM0_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM0_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM0_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM0_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM0_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM0_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM0_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM0_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM0_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM0_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM0_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM0_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM0_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM0_CM_HIST_SCALE_SRC1 +#define CM0_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM0_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM0_CM_HIST_COEFA_SRC2 +#define CM0_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_COEFB_SRC2 +#define CM0_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_COEFC_SRC2 +#define CM0_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_SCALE_SRC3 +#define CM0_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM0_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM0_CM_HIST_BIAS_SRC1 +#define CM0_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM0_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM0_CM_HIST_BIAS_SRC2 +#define CM0_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM0_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM0_CM_HIST_BIAS_SRC3 +#define CM0_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM0_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM0_CM_HIST_LOCK +#define CM0_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM0_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM0_CM_HIST_INDEX +#define CM0_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM0_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM0_CM_HIST_DATA +#define CM0_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM0_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM0_CM_HIST_STATUS +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM0_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM0_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM0_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM0_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM0_CM_HIST_INT_CONTROL +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM0_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON10_PERFCOUNTER_CNTL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_CNTL2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON10_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFCOUNTER_STATE +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON10_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON10_PERFMON_CNTL +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON10_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON10_PERFMON_CNTL2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON10_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON10_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON10_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON10_PERFMON_CVALUE_LOW +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON10_PERFMON_HI +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON10_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON10_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON10_PERFMON_LOW +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON10_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec +//DPP_TOP1_DPP_CONTROL +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP1_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP1_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP1_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP1_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP1_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP1_DPP_SOFT_RESET +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP1_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP1_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP1_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP1_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP1_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP1_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP1_DPP_CRC_VAL_R +#define DPP_TOP1_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_VAL_G +#define DPP_TOP1_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_VAL_B +#define DPP_TOP1_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_VAL_A +#define DPP_TOP1_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP1_DPP_CRC_CTRL +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP1_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP1_HOST_READ_CONTROL +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP1_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec +//CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG1_FORMAT_CONTROL +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG1_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG1_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG1_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG1_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG1_FCNV_FP_BIAS_R +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_G +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_BIAS_B +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_R +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_G +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG1_FCNV_FP_SCALE_B +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG1_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG1_COLOR_KEYER_CONTROL +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG1_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG1_COLOR_KEYER_ALPHA +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_RED +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_GREEN +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_COLOR_KEYER_BLUE +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG1_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT01 +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG1_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG1_ALPHA_2BIT_LUT23 +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG1_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG1_PRE_DEALPHA +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG1_PRE_CSC_MODE +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG1_PRE_CSC_C11_C12 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C13_C14 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C21_C22 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C23_C24 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C31_C32 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_C33_C34 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C11_C12 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C13_C14 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C21_C22 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C23_C24 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C31_C32 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG1_PRE_CSC_B_C33_C34 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG1_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG1_CNVC_COEF_FORMAT +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG1_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG1_PRE_DEGAM +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG1_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG1_PRE_REALPHA +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG1_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_cur_dispdec +//CM_CUR1_CURSOR0_CONTROL +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR1_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR1_CURSOR0_COLOR0 +#define CM_CUR1_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR1_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR1_CURSOR0_COLOR1 +#define CM_CUR1_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR1_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR1_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_MODE +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR1_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR1_CUR0_MATRIX_C11_C12_A +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C13_C14_A +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C21_C22_A +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C23_C24_A +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C31_C32_A +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C33_C34_A +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C11_C12_B +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C13_C14_B +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C21_C22_B +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C23_C24_B +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C31_C32_B +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR1_CUR0_MATRIX_C33_C34_B +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR1_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec +//DSCL1_SCL_COEF_RAM_TAP_SELECT +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL1_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL1_SCL_COEF_RAM_TAP_DATA +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL1_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL1_SCL_MODE +#define DSCL1_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL1_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL1_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL1_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL1_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL1_SCL_TAP_CONTROL +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL1_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL1_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL1_DSCL_CONTROL +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL1_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL1_DSCL_2TAP_CONTROL +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL1_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL1_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL1_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_HORZ_FILTER_INIT_C +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL1_SCL_VERT_FILTER_INIT_C +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL1_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL1_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL1_SCL_BLACK_COLOR +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL1_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL1_DSCL_UPDATE +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL1_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL1_DSCL_AUTOCAL +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL1_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL1_OTG_H_BLANK +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL1_OTG_V_BLANK +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL1_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL1_RECOUT_START +#define DSCL1_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL1_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL1_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL1_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL1_RECOUT_SIZE +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL1_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL1_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL1_MPC_SIZE +#define DSCL1_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL1_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL1_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL1_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL1_LB_DATA_FORMAT +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL1_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL1_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL1_LB_MEMORY_CTRL +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL1_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL1_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL1_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL1_LB_V_COUNTER +#define DSCL1_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL1_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL1_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL1_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL1_DSCL_MEM_PWR_CTRL +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL1_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL1_DSCL_MEM_PWR_STATUS +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL1_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL1_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL1_OBUF_CONTROL +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL1_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL1_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL1_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL1_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL1_OBUF_MEM_PWR_CTRL +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL1_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL1_DSCL_EASF_H_MODE +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL1_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL1_DSCL_EASF_V_MODE +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL1_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL1_DSCL_SC_MODE +#define DSCL1_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL1_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL1_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL1_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL1_DSCL_SC_MATRIX_C0C1 +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL1_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL1_DSCL_SC_MATRIX_C2C3 +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL1_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_RINGEST_FORCE +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL1_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL1_DSCL_EASF_H_BF_CNTL +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL1_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL1_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL1_DSCL_EASF_V_BF_CNTL +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL1_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL1_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL1_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL1_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL1_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL1_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL1_ISHARP_MODE +#define DSCL1_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL1_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL1_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL1_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL1_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL1_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL1_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL1_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL1_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL1_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL1_ISHARP_DELTA_CTRL +#define DSCL1_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL1_ISHARP_DELTA_INDEX +#define DSCL1_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL1_ISHARP_DELTA_DATA +#define DSCL1_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL1_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL1_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL1_ISHARP_NOISEDET_THRESHOLD +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL1_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL1_ISHARP_NOISE_GAIN_PWL +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL1_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL1_ISHARP_LBA_PWL_SEG0 +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG1 +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG2 +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG3 +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG4 +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL1_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL1_ISHARP_LBA_PWL_SEG5 +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL1_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL1_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec +//CM1_CM_CONTROL +#define CM1_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM1_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM1_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM1_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM1_CM_POST_CSC_CONTROL +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM1_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM1_CM_POST_CSC_C11_C12 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C13_C14 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C21_C22 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C23_C24 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C31_C32 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_C33_C34 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C11_C12 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C13_C14 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C21_C22 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C23_C24 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C31_C32 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM1_CM_POST_CSC_B_C33_C34 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM1_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM1_CM_BIAS_CR_R +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM1_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM1_CM_BIAS_Y_G_CB_B +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM1_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_CONTROL +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM1_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM1_CM_GAMCOR_LUT_INDEX +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM1_CM_GAMCOR_LUT_DATA +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_LUT_CONTROL +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM1_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM1_CM_GAMCOR_RAMA_START_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMA_OFFSET_B +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_G +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_OFFSET_R +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMA_REGION_0_1 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_2_3 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_4_5 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_6_7 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_8_9 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_10_11 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_12_13 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_14_15 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_16_17 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_18_19 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_20_21 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_22_23 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_24_25 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_26_27 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_28_29 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_30_31 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMA_REGION_32_33 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM1_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM1_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM1_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM1_CM_GAMCOR_RAMB_OFFSET_B +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_G +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_OFFSET_R +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM1_CM_GAMCOR_RAMB_REGION_0_1 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_2_3 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_4_5 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_6_7 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_8_9 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_10_11 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_12_13 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_14_15 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_16_17 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_18_19 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_20_21 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_22_23 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_24_25 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_26_27 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_28_29 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_30_31 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_GAMCOR_RAMB_REGION_32_33 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM1_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM1_CM_HDR_MULT_COEF +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM1_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM1_CM_MEM_PWR_CTRL +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM1_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM1_CM_MEM_PWR_STATUS +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM1_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM1_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM1_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM1_CM_DEALPHA +#define CM1_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM1_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM1_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM1_CM_COEF_FORMAT +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM1_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM1_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM1_CM_TEST_DEBUG_INDEX +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM1_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM1_CM_TEST_DEBUG_DATA +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM1_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM1_CM_HIST_CNTL +#define CM1_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM1_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM1_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM1_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM1_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM1_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM1_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM1_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM1_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM1_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM1_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM1_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM1_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM1_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM1_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM1_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM1_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM1_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM1_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM1_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM1_CM_HIST_SCALE_SRC1 +#define CM1_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM1_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM1_CM_HIST_COEFA_SRC2 +#define CM1_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_COEFB_SRC2 +#define CM1_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_COEFC_SRC2 +#define CM1_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_SCALE_SRC3 +#define CM1_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM1_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM1_CM_HIST_BIAS_SRC1 +#define CM1_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM1_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM1_CM_HIST_BIAS_SRC2 +#define CM1_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM1_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM1_CM_HIST_BIAS_SRC3 +#define CM1_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM1_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM1_CM_HIST_LOCK +#define CM1_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM1_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM1_CM_HIST_INDEX +#define CM1_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM1_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM1_CM_HIST_DATA +#define CM1_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM1_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM1_CM_HIST_STATUS +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM1_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM1_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM1_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM1_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM1_CM_HIST_INT_CONTROL +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM1_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON11_PERFCOUNTER_CNTL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_CNTL2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON11_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFCOUNTER_STATE +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON11_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON11_PERFMON_CNTL +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON11_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON11_PERFMON_CNTL2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON11_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON11_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON11_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON11_PERFMON_CVALUE_LOW +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON11_PERFMON_HI +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON11_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON11_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON11_PERFMON_LOW +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON11_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec +//DPP_TOP2_DPP_CONTROL +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP2_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP2_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP2_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP2_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP2_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP2_DPP_SOFT_RESET +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP2_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP2_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP2_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP2_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP2_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP2_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP2_DPP_CRC_VAL_R +#define DPP_TOP2_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_VAL_G +#define DPP_TOP2_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_VAL_B +#define DPP_TOP2_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_VAL_A +#define DPP_TOP2_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP2_DPP_CRC_CTRL +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP2_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP2_HOST_READ_CONTROL +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP2_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec +//CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG2_FORMAT_CONTROL +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG2_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG2_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG2_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG2_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG2_FCNV_FP_BIAS_R +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_G +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_BIAS_B +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_R +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_G +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG2_FCNV_FP_SCALE_B +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG2_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG2_COLOR_KEYER_CONTROL +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG2_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG2_COLOR_KEYER_ALPHA +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_RED +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_GREEN +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_COLOR_KEYER_BLUE +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG2_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT01 +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG2_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG2_ALPHA_2BIT_LUT23 +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG2_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG2_PRE_DEALPHA +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG2_PRE_CSC_MODE +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG2_PRE_CSC_C11_C12 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C13_C14 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C21_C22 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C23_C24 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C31_C32 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_C33_C34 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C11_C12 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C13_C14 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C21_C22 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C23_C24 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C31_C32 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG2_PRE_CSC_B_C33_C34 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG2_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG2_CNVC_COEF_FORMAT +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG2_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG2_PRE_DEGAM +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG2_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG2_PRE_REALPHA +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG2_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_cur_dispdec +//CM_CUR2_CURSOR0_CONTROL +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR2_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR2_CURSOR0_COLOR0 +#define CM_CUR2_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR2_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR2_CURSOR0_COLOR1 +#define CM_CUR2_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR2_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR2_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_MODE +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR2_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR2_CUR0_MATRIX_C11_C12_A +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C13_C14_A +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C21_C22_A +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C23_C24_A +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C31_C32_A +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C33_C34_A +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C11_C12_B +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C13_C14_B +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C21_C22_B +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C23_C24_B +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C31_C32_B +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR2_CUR0_MATRIX_C33_C34_B +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR2_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec +//DSCL2_SCL_COEF_RAM_TAP_SELECT +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL2_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL2_SCL_COEF_RAM_TAP_DATA +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL2_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL2_SCL_MODE +#define DSCL2_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL2_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL2_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL2_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL2_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL2_SCL_TAP_CONTROL +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL2_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL2_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL2_DSCL_CONTROL +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL2_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL2_DSCL_2TAP_CONTROL +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL2_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL2_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL2_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_HORZ_FILTER_INIT_C +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL2_SCL_VERT_FILTER_INIT_C +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL2_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL2_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL2_SCL_BLACK_COLOR +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL2_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL2_DSCL_UPDATE +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL2_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL2_DSCL_AUTOCAL +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL2_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL2_OTG_H_BLANK +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL2_OTG_V_BLANK +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL2_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL2_RECOUT_START +#define DSCL2_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL2_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL2_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL2_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL2_RECOUT_SIZE +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL2_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL2_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL2_MPC_SIZE +#define DSCL2_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL2_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL2_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL2_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL2_LB_DATA_FORMAT +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL2_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL2_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL2_LB_MEMORY_CTRL +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL2_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL2_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL2_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL2_LB_V_COUNTER +#define DSCL2_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL2_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL2_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL2_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL2_DSCL_MEM_PWR_CTRL +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL2_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL2_DSCL_MEM_PWR_STATUS +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL2_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL2_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL2_OBUF_CONTROL +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL2_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL2_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL2_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL2_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL2_OBUF_MEM_PWR_CTRL +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL2_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL2_DSCL_EASF_H_MODE +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL2_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL2_DSCL_EASF_V_MODE +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL2_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL2_DSCL_SC_MODE +#define DSCL2_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL2_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL2_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL2_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL2_DSCL_SC_MATRIX_C0C1 +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL2_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL2_DSCL_SC_MATRIX_C2C3 +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL2_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_RINGEST_FORCE +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL2_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL2_DSCL_EASF_H_BF_CNTL +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL2_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL2_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL2_DSCL_EASF_V_BF_CNTL +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL2_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL2_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL2_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL2_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL2_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL2_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL2_ISHARP_MODE +#define DSCL2_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL2_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL2_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL2_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL2_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL2_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL2_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL2_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL2_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL2_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL2_ISHARP_DELTA_CTRL +#define DSCL2_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL2_ISHARP_DELTA_INDEX +#define DSCL2_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL2_ISHARP_DELTA_DATA +#define DSCL2_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL2_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL2_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL2_ISHARP_NOISEDET_THRESHOLD +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL2_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL2_ISHARP_NOISE_GAIN_PWL +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL2_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL2_ISHARP_LBA_PWL_SEG0 +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG1 +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG2 +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG3 +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG4 +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL2_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL2_ISHARP_LBA_PWL_SEG5 +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL2_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL2_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec +//CM2_CM_CONTROL +#define CM2_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM2_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM2_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM2_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM2_CM_POST_CSC_CONTROL +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM2_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM2_CM_POST_CSC_C11_C12 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C13_C14 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C21_C22 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C23_C24 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C31_C32 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_C33_C34 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C11_C12 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C13_C14 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C21_C22 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C23_C24 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C31_C32 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM2_CM_POST_CSC_B_C33_C34 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM2_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM2_CM_BIAS_CR_R +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM2_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM2_CM_BIAS_Y_G_CB_B +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM2_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_CONTROL +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM2_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM2_CM_GAMCOR_LUT_INDEX +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM2_CM_GAMCOR_LUT_DATA +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_LUT_CONTROL +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM2_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM2_CM_GAMCOR_RAMA_START_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMA_OFFSET_B +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_G +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_OFFSET_R +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMA_REGION_0_1 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_2_3 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_4_5 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_6_7 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_8_9 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_10_11 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_12_13 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_14_15 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_16_17 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_18_19 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_20_21 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_22_23 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_24_25 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_26_27 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_28_29 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_30_31 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMA_REGION_32_33 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM2_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM2_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM2_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM2_CM_GAMCOR_RAMB_OFFSET_B +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_G +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_OFFSET_R +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM2_CM_GAMCOR_RAMB_REGION_0_1 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_2_3 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_4_5 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_6_7 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_8_9 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_10_11 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_12_13 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_14_15 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_16_17 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_18_19 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_20_21 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_22_23 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_24_25 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_26_27 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_28_29 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_30_31 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_GAMCOR_RAMB_REGION_32_33 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM2_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM2_CM_HDR_MULT_COEF +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM2_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM2_CM_MEM_PWR_CTRL +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM2_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM2_CM_MEM_PWR_STATUS +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM2_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM2_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM2_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM2_CM_DEALPHA +#define CM2_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM2_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM2_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM2_CM_COEF_FORMAT +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM2_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM2_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM2_CM_TEST_DEBUG_INDEX +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM2_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM2_CM_TEST_DEBUG_DATA +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM2_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM2_CM_HIST_CNTL +#define CM2_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM2_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM2_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM2_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM2_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM2_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM2_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM2_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM2_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM2_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM2_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM2_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM2_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM2_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM2_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM2_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM2_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM2_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM2_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM2_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM2_CM_HIST_SCALE_SRC1 +#define CM2_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM2_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM2_CM_HIST_COEFA_SRC2 +#define CM2_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_COEFB_SRC2 +#define CM2_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_COEFC_SRC2 +#define CM2_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_SCALE_SRC3 +#define CM2_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM2_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM2_CM_HIST_BIAS_SRC1 +#define CM2_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM2_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM2_CM_HIST_BIAS_SRC2 +#define CM2_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM2_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM2_CM_HIST_BIAS_SRC3 +#define CM2_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM2_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM2_CM_HIST_LOCK +#define CM2_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM2_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM2_CM_HIST_INDEX +#define CM2_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM2_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM2_CM_HIST_DATA +#define CM2_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM2_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM2_CM_HIST_STATUS +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM2_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM2_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM2_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM2_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM2_CM_HIST_INT_CONTROL +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM2_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON12_PERFCOUNTER_CNTL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_CNTL2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON12_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFCOUNTER_STATE +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON12_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON12_PERFMON_CNTL +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON12_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON12_PERFMON_CNTL2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON12_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON12_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON12_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON12_PERFMON_CVALUE_LOW +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON12_PERFMON_HI +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON12_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON12_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON12_PERFMON_LOW +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON12_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec +//DPP_TOP3_DPP_CONTROL +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE__SHIFT 0x4 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE__SHIFT 0x8 +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE__SHIFT 0xa +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE__SHIFT 0xc +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE__SHIFT 0xe +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x10 +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE__SHIFT 0x12 +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS__SHIFT 0x18 +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL__SHIFT 0x1c +#define DPP_TOP3_DPP_CONTROL__DPP_CLOCK_ENABLE_MASK 0x00000010L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_GATE_DISABLE_MASK 0x00000100L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DYN_GATE_DISABLE_MASK 0x00000400L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_G_DSCL_GATE_DISABLE_MASK 0x00001000L +#define DPP_TOP3_DPP_CONTROL__DPPCLK_R_GATE_DISABLE_MASK 0x00004000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00010000L +#define DPP_TOP3_DPP_CONTROL__DISPCLK_G_GATE_DISABLE_MASK 0x00040000L +#define DPP_TOP3_DPP_CONTROL__DPP_FGCG_REP_DIS_MASK 0x01000000L +#define DPP_TOP3_DPP_CONTROL__DPP_TEST_CLK_SEL_MASK 0x70000000L +//DPP_TOP3_DPP_SOFT_RESET +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET__SHIFT 0x0 +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET__SHIFT 0x4 +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET__SHIFT 0x8 +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET__SHIFT 0xc +#define DPP_TOP3_DPP_SOFT_RESET__HIST_SOFT_RESET__SHIFT 0x10 +#define DPP_TOP3_DPP_SOFT_RESET__CNVC_SOFT_RESET_MASK 0x00000001L +#define DPP_TOP3_DPP_SOFT_RESET__DSCL_SOFT_RESET_MASK 0x00000010L +#define DPP_TOP3_DPP_SOFT_RESET__CM_SOFT_RESET_MASK 0x00000100L +#define DPP_TOP3_DPP_SOFT_RESET__OBUF_SOFT_RESET_MASK 0x00001000L +#define DPP_TOP3_DPP_SOFT_RESET__HIST_SOFT_RESET_MASK 0x00010000L +//DPP_TOP3_DPP_CRC_VAL_R +#define DPP_TOP3_DPP_CRC_VAL_R__DPP_CRC_R_CR__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_R__DPP_CRC_R_CR_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_VAL_G +#define DPP_TOP3_DPP_CRC_VAL_G__DPP_CRC_G_Y__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_G__DPP_CRC_G_Y_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_VAL_B +#define DPP_TOP3_DPP_CRC_VAL_B__DPP_CRC_B_CB__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_B__DPP_CRC_B_CB_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_VAL_A +#define DPP_TOP3_DPP_CRC_VAL_A__DPP_CRC_ALPHA__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_VAL_A__DPP_CRC_ALPHA_MASK 0xFFFFFFFFL +//DPP_TOP3_DPP_CRC_CTRL +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN__SHIFT 0x0 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN__SHIFT 0x1 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING__SHIFT 0x2 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL__SHIFT 0x3 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL__SHIFT 0x4 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN__SHIFT 0x6 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE__SHIFT 0x7 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE__SHIFT 0x9 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL__SHIFT 0xb +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK__SHIFT 0x10 +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_EN_MASK 0x00000001L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_CONT_EN_MASK 0x00000002L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_ONE_SHOT_PENDING_MASK 0x00000004L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_420_COMP_SEL_MASK 0x00000008L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_SRC_SEL_MASK 0x00000030L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_EN_MASK 0x00000040L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_STEREO_MODE_MASK 0x00000180L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_INTERLACE_MODE_MASK 0x00000600L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800L +#define DPP_TOP3_DPP_CRC_CTRL__DPP_CRC_MASK_MASK 0xFFFF0000L +//DPP_TOP3_HOST_READ_CONTROL +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DPP_TOP3_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL + + +// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec +//CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE__SHIFT 0x8 +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007FL +#define CNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT__CNVC_ALPHA_PLANE_ENABLE_MASK 0x00000100L +//CNVC_CFG3_FORMAT_CONTROL +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x0 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x4 +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x8 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS__SHIFT 0xc +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN__SHIFT 0xd +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x10 +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x11 +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING__SHIFT 0x14 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R__SHIFT 0x18 +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G__SHIFT 0x1a +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B__SHIFT 0x1c +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010L +#define CNVC_CFG3_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MASK 0x00001000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_BYPASS_MSB_ALIGN_MASK 0x00002000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000L +#define CNVC_CFG3_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000L +#define CNVC_CFG3_FORMAT_CONTROL__CNVC_UPDATE_PENDING_MASK 0x00100000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_R_MASK 0x03000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_G_MASK 0x0C000000L +#define CNVC_CFG3_FORMAT_CONTROL__FORMAT_CROSSBAR_B_MASK 0x30000000L +//CNVC_CFG3_FCNV_FP_BIAS_R +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_G +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_BIAS_B +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_R +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_G +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007FFFFL +//CNVC_CFG3_FCNV_FP_SCALE_B +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x0 +#define CNVC_CFG3_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007FFFFL +//CNVC_CFG3_COLOR_KEYER_CONTROL +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x1 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x4 +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002L +#define CNVC_CFG3_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030L +//CNVC_CFG3_COLOR_KEYER_ALPHA +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_RED +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_GREEN +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_COLOR_KEYER_BLUE +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x0 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x10 +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000FFFFL +#define CNVC_CFG3_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xFFFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT01 +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000FFFL +#define CNVC_CFG3_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0FFF0000L +//CNVC_CFG3_ALPHA_2BIT_LUT23 +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x0 +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x10 +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000FFFL +#define CNVC_CFG3_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0FFF0000L +//CNVC_CFG3_PRE_DEALPHA +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010L +//CNVC_CFG3_PRE_CSC_MODE +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x2 +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x0000000CL +//CNVC_CFG3_PRE_CSC_C11_C12 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C13_C14 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C21_C22 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C23_C24 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C31_C32 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_C33_C34 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C11_C12 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C11_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C11_C12__PRE_CSC_B_C12_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C13_C14 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C13_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C13_C14__PRE_CSC_B_C14_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C21_C22 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C21_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C21_C22__PRE_CSC_B_C22_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C23_C24 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C23_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C23_C24__PRE_CSC_B_C24_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C31_C32 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C31_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C31_C32__PRE_CSC_B_C32_MASK 0xFFFF0000L +//CNVC_CFG3_PRE_CSC_B_C33_C34 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33__SHIFT 0x0 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34__SHIFT 0x10 +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C33_MASK 0x0000FFFFL +#define CNVC_CFG3_PRE_CSC_B_C33_C34__PRE_CSC_B_C34_MASK 0xFFFF0000L +//CNVC_CFG3_CNVC_COEF_FORMAT +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x0 +#define CNVC_CFG3_CNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001L +//CNVC_CFG3_PRE_DEGAM +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x0 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x4 +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003L +#define CNVC_CFG3_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070L +//CNVC_CFG3_PRE_REALPHA +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x0 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x4 +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001L +#define CNVC_CFG3_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_cur_dispdec +//CM_CUR3_CURSOR0_CONTROL +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ENABLE__SHIFT 0x0 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE__SHIFT 0x1 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE__SHIFT 0x2 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN__SHIFT 0x3 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_MODE__SHIFT 0x4 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN__SHIFT 0x7 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING__SHIFT 0x10 +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ENABLE_MASK 0x00000001L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_EXPANSION_MODE_MASK 0x00000002L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIX_INV_MODE_MASK 0x00000004L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_ROM_EN_MASK 0x00000008L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_MODE_MASK 0x00000070L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_PIXEL_ALPHA_MOD_EN_MASK 0x00000080L +#define CM_CUR3_CURSOR0_CONTROL__CUR0_UPDATE_PENDING_MASK 0x00010000L +//CM_CUR3_CURSOR0_COLOR0 +#define CM_CUR3_CURSOR0_COLOR0__CUR0_COLOR0__SHIFT 0x0 +#define CM_CUR3_CURSOR0_COLOR0__CUR0_COLOR0_MASK 0x00FFFFFFL +//CM_CUR3_CURSOR0_COLOR1 +#define CM_CUR3_CURSOR0_COLOR1__CUR0_COLOR1__SHIFT 0x0 +#define CM_CUR3_CURSOR0_COLOR1__CUR0_COLOR1_MASK 0x00FFFFFFL +//CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y__SHIFT 0x0 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y__SHIFT 0x10 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y_MASK 0x0000FFFFL +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y_MASK 0xFFFF0000L +//CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB__SHIFT 0x0 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB__SHIFT 0x10 +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB_MASK 0x0000FFFFL +#define CM_CUR3_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_MODE +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT__SHIFT 0x2 +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT__SHIFT 0x4 +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_MASK 0x00000003L +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_MODE_CURRENT_MASK 0x0000000CL +#define CM_CUR3_CUR0_MATRIX_MODE__CUR0_MATRIX_COEF_FORMAT_MASK 0x00000010L +//CM_CUR3_CUR0_MATRIX_C11_C12_A +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C11_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C11_C12_A__CUR0_MATRIX_C12_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C13_C14_A +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C13_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C13_C14_A__CUR0_MATRIX_C14_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C21_C22_A +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C21_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C21_C22_A__CUR0_MATRIX_C22_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C23_C24_A +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C23_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C23_C24_A__CUR0_MATRIX_C24_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C31_C32_A +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C31_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C31_C32_A__CUR0_MATRIX_C32_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C33_C34_A +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C33_A_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C33_C34_A__CUR0_MATRIX_C34_A_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C11_C12_B +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C11_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C11_C12_B__CUR0_MATRIX_C12_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C13_C14_B +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C13_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C13_C14_B__CUR0_MATRIX_C14_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C21_C22_B +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C21_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C21_C22_B__CUR0_MATRIX_C22_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C23_C24_B +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C23_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C23_C24_B__CUR0_MATRIX_C24_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C31_C32_B +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C31_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C31_C32_B__CUR0_MATRIX_C32_B_MASK 0xFFFF0000L +//CM_CUR3_CUR0_MATRIX_C33_C34_B +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B__SHIFT 0x0 +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B__SHIFT 0x10 +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C33_B_MASK 0x0000FFFFL +#define CM_CUR3_CUR0_MATRIX_C33_C34_B__CUR0_MATRIX_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec +//DSCL3_SCL_COEF_RAM_TAP_SELECT +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x8 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003F00L +#define DSCL3_SCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000L +//DSCL3_SCL_COEF_RAM_TAP_DATA +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x0 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0xf +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x10 +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x1f +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003FFFL +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3FFF0000L +#define DSCL3_SCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L +//DSCL3_SCL_MODE +#define DSCL3_SCL_MODE__DSCL_MODE__SHIFT 0x0 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT__SHIFT 0x8 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0xc +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x10 +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x14 +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x18 +#define DSCL3_SCL_MODE__DSCL_MODE_MASK 0x00000007L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_MASK 0x00000100L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000L +#define DSCL3_SCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000L +#define DSCL3_SCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000L +#define DSCL3_SCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000L +//DSCL3_SCL_TAP_CONTROL +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x0 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x4 +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x8 +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0xc +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070L +#define DSCL3_SCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700L +#define DSCL3_SCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000L +//DSCL3_DSCL_CONTROL +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x0 +#define DSCL3_DSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001L +//DSCL3_DSCL_2TAP_CONTROL +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x0 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x4 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x10 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x14 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x18 +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000L +#define DSCL3_DSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000L +//DSCL3_SCL_MANUAL_REPLICATE_CONTROL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x0 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x8 +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000FL +#define DSCL3_SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000F00L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_HORZ_FILTER_INIT_C +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07FFFFFFL +//DSCL3_SCL_VERT_FILTER_INIT_C +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0F000000L +//DSCL3_SCL_VERT_FILTER_INIT_BOT_C +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x0 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x18 +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00FFFFFFL +#define DSCL3_SCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0F000000L +//DSCL3_SCL_BLACK_COLOR +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x0 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x10 +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000FFFFL +#define DSCL3_SCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xFFFF0000L +//DSCL3_DSCL_UPDATE +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x0 +#define DSCL3_DSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L +//DSCL3_DSCL_AUTOCAL +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x0 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE__SHIFT 0x8 +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID__SHIFT 0xc +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_NUM_PIPE_MASK 0x00000300L +#define DSCL3_DSCL_AUTOCAL__AUTOCAL_PIPE_ID_MASK 0x00003000L +//DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00003FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x3FFF0000L +//DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x0 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x10 +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00003FFFL +#define DSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x3FFF0000L +//DSCL3_OTG_H_BLANK +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3FFF0000L +//DSCL3_OTG_V_BLANK +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x0 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x10 +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003FFFL +#define DSCL3_OTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3FFF0000L +//DSCL3_RECOUT_START +#define DSCL3_RECOUT_START__RECOUT_START_X__SHIFT 0x0 +#define DSCL3_RECOUT_START__RECOUT_START_Y__SHIFT 0x10 +#define DSCL3_RECOUT_START__RECOUT_START_X_MASK 0x00003FFFL +#define DSCL3_RECOUT_START__RECOUT_START_Y_MASK 0x3FFF0000L +//DSCL3_RECOUT_SIZE +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x0 +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x10 +#define DSCL3_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003FFFL +#define DSCL3_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3FFF0000L +//DSCL3_MPC_SIZE +#define DSCL3_MPC_SIZE__MPC_WIDTH__SHIFT 0x0 +#define DSCL3_MPC_SIZE__MPC_HEIGHT__SHIFT 0x10 +#define DSCL3_MPC_SIZE__MPC_WIDTH_MASK 0x00003FFFL +#define DSCL3_MPC_SIZE__MPC_HEIGHT_MASK 0x3FFF0000L +//DSCL3_LB_DATA_FORMAT +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT 0x0 +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN__SHIFT 0x4 +#define DSCL3_LB_DATA_FORMAT__INTERLEAVE_EN_MASK 0x00000001L +#define DSCL3_LB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010L +//DSCL3_LB_MEMORY_CTRL +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG__SHIFT 0x0 +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x8 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x10 +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x18 +#define DSCL3_LB_MEMORY_CTRL__MEMORY_CONFIG_MASK 0x00000003L +#define DSCL3_LB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003F00L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007F0000L +#define DSCL3_LB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7F000000L +//DSCL3_LB_V_COUNTER +#define DSCL3_LB_V_COUNTER__V_COUNTER__SHIFT 0x0 +#define DSCL3_LB_V_COUNTER__V_COUNTER_C__SHIFT 0x10 +#define DSCL3_LB_V_COUNTER__V_COUNTER_MASK 0x00001FFFL +#define DSCL3_LB_V_COUNTER__V_COUNTER_C_MASK 0x1FFF0000L +//DSCL3_DSCL_MEM_PWR_CTRL +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS__SHIFT 0xe +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS__SHIFT 0x12 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE__SHIFT 0x14 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS__SHIFT 0x16 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE__SHIFT 0x18 +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS__SHIFT 0x1a +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x1c +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_FORCE_MASK 0x00003000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G3_MEM_PWR_DIS_MASK 0x00004000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_FORCE_MASK 0x00030000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G4_MEM_PWR_DIS_MASK 0x00040000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_FORCE_MASK 0x00300000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G5_MEM_PWR_DIS_MASK 0x00400000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_FORCE_MASK 0x03000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_G6_MEM_PWR_DIS_MASK 0x04000000L +#define DSCL3_DSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000L +//DSCL3_DSCL_MEM_PWR_STATUS +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x0 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x2 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE__SHIFT 0x6 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE__SHIFT 0x8 +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE__SHIFT 0xa +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE__SHIFT 0xc +#define DSCL3_DSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000CL +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G3_MEM_PWR_STATE_MASK 0x000000C0L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G4_MEM_PWR_STATE_MASK 0x00000300L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G5_MEM_PWR_STATE_MASK 0x00000C00L +#define DSCL3_DSCL_MEM_PWR_STATUS__LB_G6_MEM_PWR_STATE_MASK 0x00003000L +//DSCL3_OBUF_CONTROL +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS__SHIFT 0x0 +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER__SHIFT 0x1 +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH__SHIFT 0x2 +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT__SHIFT 0x4 +#define DSCL3_OBUF_CONTROL__OBUF_BYPASS_MASK 0x00000001L +#define DSCL3_OBUF_CONTROL__OBUF_USE_FULL_BUFFER_MASK 0x00000002L +#define DSCL3_OBUF_CONTROL__OBUF_IS_HALF_RECOUT_WIDTH_MASK 0x00000004L +#define DSCL3_OBUF_CONTROL__OBUF_OUT_HOLD_CNT_MASK 0x000000F0L +//DSCL3_OBUF_MEM_PWR_CTRL +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE__SHIFT 0x8 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE__SHIFT 0x10 +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_MODE_MASK 0x00000100L +#define DSCL3_OBUF_MEM_PWR_CTRL__OBUF_MEM_PWR_STATE_MASK 0x00030000L +//DSCL3_DSCL_EASF_H_MODE +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL3_DSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL3_DSCL_EASF_V_MODE +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x4 +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x8 +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010L +#define DSCL3_DSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003F00L +//DSCL3_DSCL_SC_MODE +#define DSCL3_DSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x0 +#define DSCL3_DSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x8 +#define DSCL3_DSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001L +#define DSCL3_DSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100L +//DSCL3_DSCL_SC_MATRIX_C0C1 +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x0 +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x10 +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000FFFFL +#define DSCL3_DSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xFFFF0000L +//DSCL3_DSCL_SC_MATRIX_C2C3 +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x0 +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x10 +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000FFFFL +#define DSCL3_DSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_RINGEST_FORCE +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x0 +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000FFFFL +#define DSCL3_DSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xFFFF0000L +//DSCL3_DSCL_EASF_H_BF_CNTL +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x8 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000F00L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL3_DSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x8 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x10 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x18 +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003FL +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003F00L +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003F0000L +#define DSCL3_DSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3F000000L +//DSCL3_DSCL_EASF_V_BF_CNTL +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x8 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x18 +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x1c +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000F00L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00F00000L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0F000000L +#define DSCL3_DSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xF0000000L +//DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB__SHIFT 0x8 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA__SHIFT 0x10 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB__SHIFT 0x18 +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXA_MASK 0x0000003FL +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MAXB_MASK 0x00003F00L +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINA_MASK 0x003F0000L +#define DSCL3_DSCL_EASF_V_BF_FINAL_MAX_MIN__SCL_EASF_V_BF_MINB_MASK 0x3F000000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG1 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG2 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG3 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG4 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG5 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG6 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_H_BF1_PWL_SEG7 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG1 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG2 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG3 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG4 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG5 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG6 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x14 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003F000L +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7FF00000L +//DSCL3_DSCL_EASF_V_BF1_PWL_SEG7 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007FFL +#define DSCL3_DSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003F000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG1 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG2 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG3 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG4 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_H_BF3_PWL_SEG5 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG1 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG2 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG3 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG4 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x13 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007F000L +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xFFF80000L +//DSCL3_DSCL_EASF_V_BF3_PWL_SEG5 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000FFFL +#define DSCL3_DSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007F000L +//DSCL3_ISHARP_MODE +#define DSCL3_ISHARP_MODE__ISHARP_EN__SHIFT 0x0 +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x4 +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x5 +#define DSCL3_ISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x9 +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT__SHIFT 0xa +#define DSCL3_ISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0xb +#define DSCL3_ISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0xc +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x1c +#define DSCL3_ISHARP_MODE__ISHARP_EN_MASK 0x00000001L +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010L +#define DSCL3_ISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060L +#define DSCL3_ISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200L +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_MASK 0x00000400L +#define DSCL3_ISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800L +#define DSCL3_ISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0FFFF000L +#define DSCL3_ISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000L +//DSCL3_ISHARP_DELTA_CTRL +#define DSCL3_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001L +//DSCL3_ISHARP_DELTA_INDEX +#define DSCL3_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001FL +//DSCL3_ISHARP_DELTA_DATA +#define DSCL3_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xFFFFFFFFL +//DSCL3_ISHARP_NLDELTA_SOFT_CLIP +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x0 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x1 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x8 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x10 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x11 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x18 +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000FEL +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000FF00L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00FE0000L +#define DSCL3_ISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xFF000000L +//DSCL3_ISHARP_NOISEDET_THRESHOLD +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x0 +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x10 +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003FFL +#define DSCL3_ISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03FF0000L +//DSCL3_ISHARP_NOISE_GAIN_PWL +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x0 +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x8 +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x10 +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001FL +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001F00L +#define DSCL3_ISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3FFF0000L +//DSCL3_ISHARP_LBA_PWL_SEG0 +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG1 +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG2 +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG3 +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG4 +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x14 +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003F000L +#define DSCL3_ISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1FF00000L +//DSCL3_ISHARP_LBA_PWL_SEG5 +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x0 +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0xc +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003FFL +#define DSCL3_ISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003F000L +//DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x0 +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x2 +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x4 +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003L +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004L +#define DSCL3_ISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030L + + +// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec +//CM3_CM_CONTROL +#define CM3_CM_CONTROL__CM_BYPASS__SHIFT 0x0 +#define CM3_CM_CONTROL__CM_UPDATE_PENDING__SHIFT 0x8 +#define CM3_CM_CONTROL__CM_BYPASS_MASK 0x00000001L +#define CM3_CM_CONTROL__CM_UPDATE_PENDING_MASK 0x00000100L +//CM3_CM_POST_CSC_CONTROL +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE__SHIFT 0x0 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT__SHIFT 0x2 +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_MASK 0x00000003L +#define CM3_CM_POST_CSC_CONTROL__CM_POST_CSC_MODE_CURRENT_MASK 0x0000000CL +//CM3_CM_POST_CSC_C11_C12 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C11_C12__CM_POST_CSC_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C13_C14 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C13_C14__CM_POST_CSC_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C21_C22 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C21_C22__CM_POST_CSC_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C23_C24 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C23_C24__CM_POST_CSC_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C31_C32 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C31_C32__CM_POST_CSC_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_C33_C34 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_C33_C34__CM_POST_CSC_C34_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C11_C12 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C11_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C11_C12__CM_POST_CSC_B_C12_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C13_C14 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C13_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C13_C14__CM_POST_CSC_B_C14_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C21_C22 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C21_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C21_C22__CM_POST_CSC_B_C22_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C23_C24 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C23_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C23_C24__CM_POST_CSC_B_C24_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C31_C32 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C31_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C31_C32__CM_POST_CSC_B_C32_MASK 0xFFFF0000L +//CM3_CM_POST_CSC_B_C33_C34 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33__SHIFT 0x0 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34__SHIFT 0x10 +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C33_MASK 0x0000FFFFL +#define CM3_CM_POST_CSC_B_C33_C34__CM_POST_CSC_B_C34_MASK 0xFFFF0000L +//CM3_CM_BIAS_CR_R +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R__SHIFT 0x0 +#define CM3_CM_BIAS_CR_R__CM_BIAS_CR_R_MASK 0x0000FFFFL +//CM3_CM_BIAS_Y_G_CB_B +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G__SHIFT 0x0 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B__SHIFT 0x10 +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_Y_G_MASK 0x0000FFFFL +#define CM3_CM_BIAS_Y_G_CB_B__CM_BIAS_CB_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_CONTROL +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE__SHIFT 0x0 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT__SHIFT 0x2 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE__SHIFT 0x3 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT__SHIFT 0x4 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT__SHIFT 0x6 +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_MASK 0x00000003L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_MASK 0x00000004L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_PWL_DISABLE_MASK 0x00000008L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_MODE_CURRENT_MASK 0x00000030L +#define CM3_CM_GAMCOR_CONTROL__CM_GAMCOR_SELECT_CURRENT_MASK 0x00000040L +//CM3_CM_GAMCOR_LUT_INDEX +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_INDEX__CM_GAMCOR_LUT_INDEX_MASK 0x000001FFL +//CM3_CM_GAMCOR_LUT_DATA +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_DATA__CM_GAMCOR_LUT_DATA_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_LUT_CONTROL +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG__SHIFT 0x5 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL__SHIFT 0x6 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x7 +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_READ_DBG_MASK 0x00000020L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040L +#define CM3_CM_GAMCOR_LUT_CONTROL__CM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080L +//CM3_CM_GAMCOR_RAMA_START_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMA_START_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R__CM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_B__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_B__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_G__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_G__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL1_R__CM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMA_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMA_END_CNTL2_R__CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMA_OFFSET_B +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_B__CM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_G +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_G__CM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_OFFSET_R +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_OFFSET_R__CM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMA_REGION_0_1 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_0_1__CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_2_3 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_2_3__CM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_4_5 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_4_5__CM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_6_7 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_6_7__CM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_8_9 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_8_9__CM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_10_11 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_10_11__CM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_12_13 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_12_13__CM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_14_15 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_14_15__CM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_16_17 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_16_17__CM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_18_19 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_18_19__CM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_20_21 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_20_21__CM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_22_23 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_22_23__CM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_24_25 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_24_25__CM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_26_27 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_26_27__CM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_28_29 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_28_29__CM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_30_31 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_30_31__CM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMA_REGION_32_33 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMA_REGION_32_33__CM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define CM3_CM_GAMCOR_RAMB_START_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R__CM_GAMCOR_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL1_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_B__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_B +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_B__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_G__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_G +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_G__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_END_CNTL1_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL1_R__CM_GAMCOR_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//CM3_CM_GAMCOR_RAMB_END_CNTL2_R +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define CM3_CM_GAMCOR_RAMB_END_CNTL2_R__CM_GAMCOR_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//CM3_CM_GAMCOR_RAMB_OFFSET_B +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_B__CM_GAMCOR_RAMB_OFFSET_B_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_G +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_G__CM_GAMCOR_RAMB_OFFSET_G_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_OFFSET_R +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_OFFSET_R__CM_GAMCOR_RAMB_OFFSET_R_MASK 0x0007FFFFL +//CM3_CM_GAMCOR_RAMB_REGION_0_1 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_0_1__CM_GAMCOR_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_2_3 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_2_3__CM_GAMCOR_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_4_5 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_4_5__CM_GAMCOR_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_6_7 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_6_7__CM_GAMCOR_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_8_9 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_8_9__CM_GAMCOR_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_10_11 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_10_11__CM_GAMCOR_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_12_13 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_12_13__CM_GAMCOR_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_14_15 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_14_15__CM_GAMCOR_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_16_17 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_16_17__CM_GAMCOR_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_18_19 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_18_19__CM_GAMCOR_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_20_21 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_20_21__CM_GAMCOR_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_22_23 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_22_23__CM_GAMCOR_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_24_25 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_24_25__CM_GAMCOR_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_26_27 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_26_27__CM_GAMCOR_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_28_29 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_28_29__CM_GAMCOR_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_30_31 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_30_31__CM_GAMCOR_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_GAMCOR_RAMB_REGION_32_33 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define CM3_CM_GAMCOR_RAMB_REGION_32_33__CM_GAMCOR_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//CM3_CM_HDR_MULT_COEF +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF__SHIFT 0x0 +#define CM3_CM_HDR_MULT_COEF__CM_HDR_MULT_COEF_MASK 0x0007FFFFL +//CM3_CM_MEM_PWR_CTRL +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x2 +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE__SHIFT 0x8 +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS__SHIFT 0x9 +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004L +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_FORCE_MASK 0x00000100L +#define CM3_CM_MEM_PWR_CTRL__HIST_MEM_PWR_DIS_MASK 0x00000200L +//CM3_CM_MEM_PWR_STATUS +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x0 +#define CM3_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE__SHIFT 0x8 +#define CM3_CM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003L +#define CM3_CM_MEM_PWR_STATUS__HIST_MEM_PWR_STATE_MASK 0x00000100L +//CM3_CM_DEALPHA +#define CM3_CM_DEALPHA__CM_DEALPHA_EN__SHIFT 0x0 +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND__SHIFT 0x1 +#define CM3_CM_DEALPHA__CM_DEALPHA_EN_MASK 0x00000001L +#define CM3_CM_DEALPHA__CM_DEALPHA_ABLND_MASK 0x00000002L +//CM3_CM_COEF_FORMAT +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT__SHIFT 0x0 +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT__SHIFT 0x4 +#define CM3_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK 0x00000001L +#define CM3_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK 0x00000010L +//CM3_CM_TEST_DEBUG_INDEX +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define CM3_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//CM3_CM_TEST_DEBUG_DATA +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA__SHIFT 0x0 +#define CM3_CM_TEST_DEBUG_DATA__CM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//CM3_CM_HIST_CNTL +#define CM3_CM_HIST_CNTL__CM_HIST_SEL__SHIFT 0x0 +#define CM3_CM_HIST_CNTL__CM_HIST_CH_EN__SHIFT 0x2 +#define CM3_CM_HIST_CNTL__CM_HIST_SRC1_SEL__SHIFT 0x4 +#define CM3_CM_HIST_CNTL__CM_HIST_SRC2_SEL__SHIFT 0x5 +#define CM3_CM_HIST_CNTL__CM_HIST_SRC3_SEL__SHIFT 0x6 +#define CM3_CM_HIST_CNTL__CM_HIST_CH1_XBAR__SHIFT 0x7 +#define CM3_CM_HIST_CNTL__CM_HIST_CH2_XBAR__SHIFT 0x9 +#define CM3_CM_HIST_CNTL__CM_HIST_CH3_XBAR__SHIFT 0xb +#define CM3_CM_HIST_CNTL__CM_HIST_FORMAT__SHIFT 0xd +#define CM3_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK__SHIFT 0xf +#define CM3_CM_HIST_CNTL__CM_HIST_SEL_MASK 0x00000003L +#define CM3_CM_HIST_CNTL__CM_HIST_CH_EN_MASK 0x0000000CL +#define CM3_CM_HIST_CNTL__CM_HIST_SRC1_SEL_MASK 0x00000010L +#define CM3_CM_HIST_CNTL__CM_HIST_SRC2_SEL_MASK 0x00000020L +#define CM3_CM_HIST_CNTL__CM_HIST_SRC3_SEL_MASK 0x00000040L +#define CM3_CM_HIST_CNTL__CM_HIST_CH1_XBAR_MASK 0x00000180L +#define CM3_CM_HIST_CNTL__CM_HIST_CH2_XBAR_MASK 0x00000600L +#define CM3_CM_HIST_CNTL__CM_HIST_CH3_XBAR_MASK 0x00001800L +#define CM3_CM_HIST_CNTL__CM_HIST_FORMAT_MASK 0x00006000L +#define CM3_CM_HIST_CNTL__CM_HIST_READ_CHANNEL_MASK_MASK 0x00038000L +//CM3_CM_HIST_SCALE_SRC1 +#define CM3_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1__SHIFT 0x0 +#define CM3_CM_HIST_SCALE_SRC1__CM_HIST_SCALE_SRC1_MASK 0x0007FFFFL +//CM3_CM_HIST_COEFA_SRC2 +#define CM3_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_COEFA_SRC2__CM_HIST_COEFA_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_COEFB_SRC2 +#define CM3_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_COEFB_SRC2__CM_HIST_COEFB_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_COEFC_SRC2 +#define CM3_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_COEFC_SRC2__CM_HIST_COEFC_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_SCALE_SRC3 +#define CM3_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3__SHIFT 0x0 +#define CM3_CM_HIST_SCALE_SRC3__CM_HIST_SCALE_SRC3_MASK 0x0007FFFFL +//CM3_CM_HIST_BIAS_SRC1 +#define CM3_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1__SHIFT 0x0 +#define CM3_CM_HIST_BIAS_SRC1__CM_HIST_BIAS_SRC1_MASK 0x0007FFFFL +//CM3_CM_HIST_BIAS_SRC2 +#define CM3_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2__SHIFT 0x0 +#define CM3_CM_HIST_BIAS_SRC2__CM_HIST_BIAS_SRC2_MASK 0x0007FFFFL +//CM3_CM_HIST_BIAS_SRC3 +#define CM3_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3__SHIFT 0x0 +#define CM3_CM_HIST_BIAS_SRC3__CM_HIST_BIAS_SRC3_MASK 0x0007FFFFL +//CM3_CM_HIST_LOCK +#define CM3_CM_HIST_LOCK__CM_HIST_LOCK__SHIFT 0x0 +#define CM3_CM_HIST_LOCK__CM_HIST_LOCK_MASK 0x00000001L +//CM3_CM_HIST_INDEX +#define CM3_CM_HIST_INDEX__CM_HIST_INDEX__SHIFT 0x0 +#define CM3_CM_HIST_INDEX__CM_HIST_INDEX_MASK 0x000000FFL +//CM3_CM_HIST_DATA +#define CM3_CM_HIST_DATA__CM_HIST_DATA__SHIFT 0x0 +#define CM3_CM_HIST_DATA__CM_HIST_DATA_MASK 0x01FFFFFFL +//CM3_CM_HIST_STATUS +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS__SHIFT 0x0 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS__SHIFT 0x1 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT__SHIFT 0x2 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ__SHIFT 0x3 +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED__SHIFT 0x4 +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT__SHIFT 0x5 +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT__SHIFT 0x6 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED__SHIFT 0xc +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT__SHIFT 0xd +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED__SHIFT 0x10 +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT__SHIFT 0x11 +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW__SHIFT 0x18 +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT__SHIFT 0x19 +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE__SHIFT 0x1a +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT__SHIFT 0x1b +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_RDY_STATUS_MASK 0x00000001L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_RDY_STATUS_MASK 0x00000002L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_COLLECT_MASK 0x00000004L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFF_INUSE_READ_MASK 0x00000008L +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_MASK 0x00000010L +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CURRENT_MASK 0x00000020L +#define CM3_CM_HIST_STATUS__CM_HIST_FRAME_COLLECT_SKIPPED_CNT_MASK 0x000001C0L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_MASK 0x00001000L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFA_FRAME_READ_SKIPPED_CURRENT_MASK 0x00002000L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_MASK 0x00010000L +#define CM3_CM_HIST_STATUS__CM_HIST_BUFB_FRAME_READ_SKIPPED_CURRENT_MASK 0x00020000L +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_MASK 0x01000000L +#define CM3_CM_HIST_STATUS__CM_HIST_COUNT_OVERFLOW_CURRENT_MASK 0x02000000L +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_MASK 0x04000000L +#define CM3_CM_HIST_STATUS__CM_HIST_COLLECT_INCOMPLETE_CURRENT_MASK 0x08000000L +//CM3_CM_HIST_INT_CONTROL +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT__SHIFT 0x0 +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN__SHIFT 0x4 +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_MASK 0x00000001L +#define CM3_CM_HIST_INT_CONTROL__CM_HIST_RDY_INT_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON13_PERFCOUNTER_CNTL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_CNTL2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON13_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFCOUNTER_STATE +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON13_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON13_PERFMON_CNTL +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON13_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON13_PERFMON_CNTL2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON13_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON13_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON13_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON13_PERFMON_CVALUE_LOW +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON13_PERFMON_HI +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON13_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON13_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON13_PERFMON_LOW +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON13_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dcoh_dp_aux0_dispdec +//DP_AUX0_AUX_CONTROL +#define DP_AUX0_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX0_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX0_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX0_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX0_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX0_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX0_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX0_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX0_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX0_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX0_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX0_AUX_SW_CONTROL +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX0_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX0_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX0_AUX_ARB_CONTROL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX0_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX0_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX0_AUX_INTERRUPT_CONTROL +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX0_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX0_AUX_SW_STATUS +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX0_AUX_LS_STATUS +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX0_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX0_AUX_SW_DATA +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX0_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX0_AUX_LS_DATA +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX0_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX0_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX0_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_TX_CONTROL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX0_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX0_AUX_DPHY_RX_CONTROL0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX0_AUX_DPHY_RX_CONTROL1 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX0_AUX_DPHY_TX_STATUS +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX0_AUX_DPHY_RX_STATUS +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX0_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX0_AUX_PHY_WAKE_CNTL +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX0_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX0_AUX_PHY_WAKE_STATUS +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX0_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux1_dispdec +//DP_AUX1_AUX_CONTROL +#define DP_AUX1_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX1_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX1_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX1_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX1_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX1_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX1_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX1_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX1_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX1_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX1_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX1_AUX_SW_CONTROL +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX1_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX1_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX1_AUX_ARB_CONTROL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX1_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX1_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX1_AUX_INTERRUPT_CONTROL +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX1_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX1_AUX_SW_STATUS +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX1_AUX_LS_STATUS +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX1_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX1_AUX_SW_DATA +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX1_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX1_AUX_LS_DATA +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX1_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX1_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX1_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_TX_CONTROL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX1_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX1_AUX_DPHY_RX_CONTROL0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX1_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX1_AUX_DPHY_RX_CONTROL1 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX1_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX1_AUX_DPHY_TX_STATUS +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX1_AUX_DPHY_RX_STATUS +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX1_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX1_AUX_PHY_WAKE_CNTL +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX1_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX1_AUX_PHY_WAKE_STATUS +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX1_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux2_dispdec +//DP_AUX2_AUX_CONTROL +#define DP_AUX2_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX2_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX2_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX2_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX2_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX2_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX2_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX2_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX2_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX2_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX2_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX2_AUX_SW_CONTROL +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX2_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX2_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX2_AUX_ARB_CONTROL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX2_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX2_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX2_AUX_INTERRUPT_CONTROL +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX2_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX2_AUX_SW_STATUS +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX2_AUX_LS_STATUS +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX2_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX2_AUX_SW_DATA +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX2_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX2_AUX_LS_DATA +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX2_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX2_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX2_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_TX_CONTROL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX2_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX2_AUX_DPHY_RX_CONTROL0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX2_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX2_AUX_DPHY_RX_CONTROL1 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX2_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX2_AUX_DPHY_TX_STATUS +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX2_AUX_DPHY_RX_STATUS +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX2_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX2_AUX_PHY_WAKE_CNTL +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX2_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX2_AUX_PHY_WAKE_STATUS +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX2_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux3_dispdec +//DP_AUX3_AUX_CONTROL +#define DP_AUX3_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX3_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX3_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX3_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX3_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX3_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX3_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX3_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX3_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX3_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX3_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX3_AUX_SW_CONTROL +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX3_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX3_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX3_AUX_ARB_CONTROL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX3_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX3_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX3_AUX_INTERRUPT_CONTROL +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX3_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX3_AUX_SW_STATUS +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX3_AUX_LS_STATUS +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX3_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX3_AUX_SW_DATA +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX3_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX3_AUX_LS_DATA +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX3_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX3_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX3_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_TX_CONTROL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX3_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX3_AUX_DPHY_RX_CONTROL0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX3_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX3_AUX_DPHY_RX_CONTROL1 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX3_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX3_AUX_DPHY_TX_STATUS +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX3_AUX_DPHY_RX_STATUS +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX3_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX3_AUX_PHY_WAKE_CNTL +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX3_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX3_AUX_PHY_WAKE_STATUS +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX3_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_dp_aux4_dispdec +//DP_AUX4_AUX_CONTROL +#define DP_AUX4_AUX_CONTROL__AUX_EN__SHIFT 0x0 +#define DP_AUX4_AUX_CONTROL__AUX_RESET__SHIFT 0x4 +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE__SHIFT 0x5 +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x8 +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0xc +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x10 +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x12 +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x14 +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x18 +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x1c +#define DP_AUX4_AUX_CONTROL__AUX_EN_MASK 0x00000001L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_MASK 0x00000010L +#define DP_AUX4_AUX_CONTROL__AUX_RESET_DONE_MASK 0x00000020L +#define DP_AUX4_AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L +#define DP_AUX4_AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L +#define DP_AUX4_AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L +#define DP_AUX4_AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L +#define DP_AUX4_AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L +#define DP_AUX4_AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L +#define DP_AUX4_AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L +//DP_AUX4_AUX_SW_CONTROL +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x0 +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x2 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x4 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x10 +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L +#define DP_AUX4_AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000F0L +#define DP_AUX4_AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001F0000L +//DP_AUX4_AUX_ARB_CONTROL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x0 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x8 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0xa +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x10 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x11 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x18 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x19 +#define DP_AUX4_AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000001L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L +#define DP_AUX4_AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L +//DP_AUX4_AUX_INTERRUPT_CONTROL +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x0 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x1 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x2 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x4 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x5 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x6 +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L +#define DP_AUX4_AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L +//DP_AUX4_AUX_SW_STATUS +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x1d +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0x60000000L +//DP_AUX4_AUX_LS_STATUS +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x0 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x1 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x8 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0xa +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x13 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x18 +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x1d +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x1e +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x1f +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1F000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L +#define DP_AUX4_AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L +//DP_AUX4_AUX_SW_DATA +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x0 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x1f +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001F0000L +#define DP_AUX4_AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L +//DP_AUX4_AUX_LS_DATA +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x8 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x10 +#define DP_AUX4_AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000FF00L +#define DP_AUX4_AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001F0000L +//DP_AUX4_AUX_DPHY_TX_REF_CONTROL +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_TX_CONTROL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME__SHIFT 0x6 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x0000000FL +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MUL_MASK 0x00000030L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_OE_ASSERT_TIME_MASK 0x00000040L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003F00L +#define DP_AUX4_AUX_DPHY_TX_CONTROL__AUX_MODE_DET_CHECK_DELAY_MASK 0x00070000L +//DP_AUX4_AUX_DPHY_RX_CONTROL0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0xc +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x11 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x12 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x13 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x14 +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x1c +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L +#define DP_AUX4_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L +//DP_AUX4_AUX_DPHY_RX_CONTROL1 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT 0xf +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000FFL +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK 0x00007F00L +#define DP_AUX4_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK 0x00018000L +//DP_AUX4_AUX_DPHY_TX_STATUS +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01FF0000L +//DP_AUX4_AUX_DPHY_RX_STATUS +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x0 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x8 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x10 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x15 +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001F00L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001F0000L +#define DP_AUX4_AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3FE00000L +//DP_AUX4_AUX_PHY_WAKE_CNTL +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO__SHIFT 0x0 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING__SHIFT 0x1 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY__SHIFT 0x2 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK__SHIFT 0x3 +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_GO_MASK 0x00000001L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PENDING_MASK 0x00000002L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_PRIORITY_MASK 0x00000004L +#define DP_AUX4_AUX_PHY_WAKE_CNTL__DP_AUX_PHY_WAKE_ACK_MASK 0x00000008L +//DP_AUX4_AUX_PHY_WAKE_STATUS +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE__SHIFT 0x4 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT__SHIFT 0x7 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON__SHIFT 0x9 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE__SHIFT 0xb +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL__SHIFT 0xc +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP__SHIFT 0xe +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L__SHIFT 0x11 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H__SHIFT 0x12 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET__SHIFT 0x14 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H__SHIFT 0x16 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L__SHIFT 0x17 +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_STATE_MASK 0x00000070L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_TIMEOUT_MASK 0x00000080L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_HPD_DISCON_MASK 0x00000200L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_NON_AUX_MODE_MASK 0x00000800L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_MIN_COUNT_VIOL_MASK 0x00001000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_INVALID_STOP_MASK 0x00004000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_L_MASK 0x00020000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_SYNC_INVALID_H_MASK 0x00040000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_NO_DET_MASK 0x00100000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_H_MASK 0x00400000L +#define DP_AUX4_AUX_PHY_WAKE_STATUS__AUX_PHY_WAKE_ACK_RECV_INVALID_L_MASK 0x00800000L + + +// addressBlock: dce_dc_dcoh_hpd0_dispdec +//HPD0_DC_HPD_INT_STATUS +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD0_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD0_DC_HPD_INT_CONTROL +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD0_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD0_DC_HPD_CONTROL +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD0_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD0_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD0_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD0_DC_HPD_FAST_TRAIN_CNTL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD0_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD0_DC_HPD_TOGGLE_FILT_CNTL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD0_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd1_dispdec +//HPD1_DC_HPD_INT_STATUS +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD1_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD1_DC_HPD_INT_CONTROL +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD1_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD1_DC_HPD_CONTROL +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD1_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD1_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD1_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD1_DC_HPD_FAST_TRAIN_CNTL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD1_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD1_DC_HPD_TOGGLE_FILT_CNTL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD1_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd2_dispdec +//HPD2_DC_HPD_INT_STATUS +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD2_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD2_DC_HPD_INT_CONTROL +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD2_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD2_DC_HPD_CONTROL +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD2_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD2_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD2_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD2_DC_HPD_FAST_TRAIN_CNTL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD2_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD2_DC_HPD_TOGGLE_FILT_CNTL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD2_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd3_dispdec +//HPD3_DC_HPD_INT_STATUS +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD3_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD3_DC_HPD_INT_CONTROL +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD3_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD3_DC_HPD_CONTROL +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD3_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD3_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD3_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD3_DC_HPD_FAST_TRAIN_CNTL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD3_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD3_DC_HPD_TOGGLE_FILT_CNTL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD3_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_hpd4_dispdec +//HPD4_DC_HPD_INT_STATUS +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS__SHIFT 0x0 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE__SHIFT 0x1 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED__SHIFT 0x4 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS__SHIFT 0x8 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0xc +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x18 +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_INT_STATUS_MASK 0x00000001L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK 0x00000002L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_SENSE_DELAYED_MASK 0x00000010L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_RX_INT_STATUS_MASK 0x00000100L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000FF000L +#define HPD4_DC_HPD_INT_STATUS__DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xFF000000L +//HPD4_DC_HPD_INT_CONTROL +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK__SHIFT 0x0 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY__SHIFT 0x8 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN__SHIFT 0x10 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK__SHIFT 0x14 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN__SHIFT 0x18 +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_ACK_MASK 0x00000001L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_POLARITY_MASK 0x00000100L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_INT_EN_MASK 0x00010000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_ACK_MASK 0x00100000L +#define HPD4_DC_HPD_INT_CONTROL__DC_HPD_RX_INT_EN_MASK 0x01000000L +//HPD4_DC_HPD_CONTROL +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER__SHIFT 0x0 +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER__SHIFT 0x10 +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN__SHIFT 0x1c +#define HPD4_DC_HPD_CONTROL__DC_HPD_CONNECTION_TIMER_MASK 0x00001FFFL +#define HPD4_DC_HPD_CONTROL__DC_HPD_RX_INT_TIMER_MASK 0x03FF0000L +#define HPD4_DC_HPD_CONTROL__DC_HPD_EN_MASK 0x10000000L +//HPD4_DC_HPD_FAST_TRAIN_CNTL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY__SHIFT 0xc +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN__SHIFT 0x18 +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN__SHIFT 0x1c +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_DELAY_MASK 0x000FF000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_AUX_TX_EN_MASK 0x01000000L +#define HPD4_DC_HPD_FAST_TRAIN_CNTL__DC_HPD_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L +//HPD4_DC_HPD_TOGGLE_FILT_CNTL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY__SHIFT 0x0 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY__SHIFT 0x14 +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_CONNECT_INT_DELAY_MASK 0x000000FFL +#define HPD4_DC_HPD_TOGGLE_FILT_CNTL__DC_HPD_DISCONNECT_INT_DELAY_MASK 0x0FF00000L + + +// addressBlock: dce_dc_dcoh_dpia_mux0_dispdec +//DPIA_MUX0_DPIA_MUX_CONTROL +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX0_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX0_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX0_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX0_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX0_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX0_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux1_dispdec +//DPIA_MUX1_DPIA_MUX_CONTROL +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX1_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX1_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX1_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX1_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX1_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX1_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux2_dispdec +//DPIA_MUX2_DPIA_MUX_CONTROL +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX2_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX2_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX2_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX2_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX2_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX2_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux3_dispdec +//DPIA_MUX3_DPIA_MUX_CONTROL +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX3_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX3_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX3_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX3_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX3_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX3_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux4_dispdec +//DPIA_MUX4_DPIA_MUX_CONTROL +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX4_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX4_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX4_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX4_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX4_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX4_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_dpia_mux5_dispdec +//DPIA_MUX5_DPIA_MUX_CONTROL +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENABLE__SHIFT 0x0 +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET__SHIFT 0x4 +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET_DONE__SHIFT 0x5 +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x6 +#define DPIA_MUX5_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT__SHIFT 0x8 +#define DPIA_MUX5_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT__SHIFT 0x10 +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENABLE_MASK 0x00000001L +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET_MASK 0x00000010L +#define DPIA_MUX5_DPIA_MUX_CONTROL__RESET_DONE_MASK 0x00000020L +#define DPIA_MUX5_DPIA_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000040L +#define DPIA_MUX5_DPIA_MUX_CONTROL__DIG_DP_SOURCE_SELECT_MASK 0x00000F00L +#define DPIA_MUX5_DPIA_MUX_CONTROL__HPO_DP_SOURCE_SELECT_MASK 0x00070000L + + +// addressBlock: dce_dc_dcoh_phy_mux0_dispdec +//PHY_MUX0_PHY_MUX_CONTROL +#define PHY_MUX0_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX0_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX0_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX0_PORT_TYPE +#define PHY_MUX0_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX0_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux1_dispdec +//PHY_MUX1_PHY_MUX_CONTROL +#define PHY_MUX1_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX1_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX1_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX1_PORT_TYPE +#define PHY_MUX1_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX1_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux2_dispdec +//PHY_MUX2_PHY_MUX_CONTROL +#define PHY_MUX2_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX2_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX2_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX2_PORT_TYPE +#define PHY_MUX2_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX2_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux3_dispdec +//PHY_MUX3_PHY_MUX_CONTROL +#define PHY_MUX3_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX3_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX3_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX3_PORT_TYPE +#define PHY_MUX3_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX3_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_phy_mux4_dispdec +//PHY_MUX4_PHY_MUX_CONTROL +#define PHY_MUX4_PHY_MUX_CONTROL__ENC_TYPE_SEL__SHIFT 0x0 +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL__SHIFT 0x4 +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_DP_ENC_SEL__SHIFT 0x8 +#define PHY_MUX4_PHY_MUX_CONTROL__ENC_TYPE_SEL_MASK 0x00000003L +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_HDMI_ENC_SEL_MASK 0x00000070L +#define PHY_MUX4_PHY_MUX_CONTROL__HPO_DP_ENC_SEL_MASK 0x00000700L +//PHY_MUX4_PORT_TYPE +#define PHY_MUX4_PORT_TYPE__PORT_TYPE__SHIFT 0x0 +#define PHY_MUX4_PORT_TYPE__PORT_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dcoh_dcoh_top_dispdec +//DCOH_TOP_CLOCK_CONTROL +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_G_GATE_DIS__SHIFT 0x0 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_G_GATE_DIS__SHIFT 0x8 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_R_GATE_DIS__SHIFT 0xc +#define DCOH_TOP_CLOCK_CONTROL__DCOH_FGCG_REP_DIS__SHIFT 0x10 +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_G_GATE_DIS_MASK 0x00000001L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_G_GATE_DIS_MASK 0x00000100L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_REFCLK_R_GATE_DIS_MASK 0x00001000L +#define DCOH_TOP_CLOCK_CONTROL__DCOH_FGCG_REP_DIS_MASK 0x00010000L +//DCOH_DCN_STATUS +#define DCOH_DCN_STATUS__DCN_ACTIVE__SHIFT 0x0 +#define DCOH_DCN_STATUS__DCN_ACTIVE_MASK 0x00000001L +//DCOH_TOP_SPARE +#define DCOH_TOP_SPARE__DCOH_TOP_SPARE__SHIFT 0x0 +#define DCOH_TOP_SPARE__DCOH_TOP_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt0_dispdec +//FMT0_FMT_CLAMP_COMPONENT_R +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_G +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_COMPONENT_B +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT0_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT0_FMT_DYNAMIC_EXP_CNTL +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT0_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT0_FMT_CONTROL +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT0_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT0_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT0_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT0_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT0_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT0_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT0_FMT_BIT_DEPTH_CONTROL +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT0_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT0_FMT_DITHER_RAND_R_SEED +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_G_SEED +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT0_FMT_DITHER_RAND_B_SEED +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT0_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT0_FMT_CLAMP_CNTL +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT0_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT0_FMT_MAP420_MEMORY_CONTROL +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT0_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT0_FMT_422_CONTROL +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT0_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg0_dispdec +//DPG0_DPG_CONTROL +#define DPG0_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG0_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG0_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG0_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG0_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG0_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG0_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG0_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG0_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG0_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG0_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG0_DPG_RAMP_CONTROL +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG0_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG0_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG0_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG0_DPG_DIMENSIONS +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG0_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_COLOUR_R_CR +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_G_Y +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG0_DPG_COLOUR_B_CB +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG0_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG0_DPG_OFFSET_SEGMENT +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG0_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG0_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG0_DPG_STATUS +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG0_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf0_dispdec +//OPPBUF0_OPPBUF_CONTROL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF0_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF0_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF0_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF0_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF0_OPPBUF_CONTROL1 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF0_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe0_dispdec +//OPP_PIPE0_OPP_PIPE_CONTROL +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE0_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec +//OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC0_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt1_dispdec +//FMT1_FMT_CLAMP_COMPONENT_R +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_G +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_COMPONENT_B +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT1_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT1_FMT_DYNAMIC_EXP_CNTL +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT1_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT1_FMT_CONTROL +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT1_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT1_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT1_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT1_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT1_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT1_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT1_FMT_BIT_DEPTH_CONTROL +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT1_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT1_FMT_DITHER_RAND_R_SEED +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_G_SEED +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT1_FMT_DITHER_RAND_B_SEED +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT1_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT1_FMT_CLAMP_CNTL +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT1_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT1_FMT_MAP420_MEMORY_CONTROL +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT1_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT1_FMT_422_CONTROL +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT1_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg1_dispdec +//DPG1_DPG_CONTROL +#define DPG1_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG1_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG1_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG1_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG1_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG1_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG1_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG1_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG1_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG1_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG1_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG1_DPG_RAMP_CONTROL +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG1_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG1_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG1_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG1_DPG_DIMENSIONS +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG1_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_COLOUR_R_CR +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_G_Y +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG1_DPG_COLOUR_B_CB +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG1_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG1_DPG_OFFSET_SEGMENT +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG1_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG1_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG1_DPG_STATUS +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG1_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf1_dispdec +//OPPBUF1_OPPBUF_CONTROL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF1_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF1_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF1_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF1_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF1_OPPBUF_CONTROL1 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF1_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe1_dispdec +//OPP_PIPE1_OPP_PIPE_CONTROL +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE1_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec +//OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC1_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt2_dispdec +//FMT2_FMT_CLAMP_COMPONENT_R +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_G +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_COMPONENT_B +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT2_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT2_FMT_DYNAMIC_EXP_CNTL +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT2_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT2_FMT_CONTROL +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT2_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT2_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT2_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT2_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT2_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT2_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT2_FMT_BIT_DEPTH_CONTROL +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT2_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT2_FMT_DITHER_RAND_R_SEED +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_G_SEED +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT2_FMT_DITHER_RAND_B_SEED +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT2_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT2_FMT_CLAMP_CNTL +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT2_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT2_FMT_MAP420_MEMORY_CONTROL +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT2_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT2_FMT_422_CONTROL +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT2_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg2_dispdec +//DPG2_DPG_CONTROL +#define DPG2_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG2_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG2_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG2_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG2_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG2_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG2_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG2_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG2_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG2_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG2_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG2_DPG_RAMP_CONTROL +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG2_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG2_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG2_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG2_DPG_DIMENSIONS +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG2_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_COLOUR_R_CR +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_G_Y +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG2_DPG_COLOUR_B_CB +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG2_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG2_DPG_OFFSET_SEGMENT +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG2_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG2_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG2_DPG_STATUS +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG2_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf2_dispdec +//OPPBUF2_OPPBUF_CONTROL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF2_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF2_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF2_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF2_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF2_OPPBUF_CONTROL1 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF2_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe2_dispdec +//OPP_PIPE2_OPP_PIPE_CONTROL +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE2_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec +//OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC2_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_fmt3_dispdec +//FMT3_FMT_CLAMP_COMPONENT_R +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_LOWER_R_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_R__FMT_CLAMP_UPPER_R_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_G +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_LOWER_G_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_G__FMT_CLAMP_UPPER_G_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_COMPONENT_B +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B__SHIFT 0x0 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B__SHIFT 0x10 +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_LOWER_B_MASK 0x0000FFFFL +#define FMT3_FMT_CLAMP_COMPONENT_B__FMT_CLAMP_UPPER_B_MASK 0xFFFF0000L +//FMT3_FMT_DYNAMIC_EXP_CNTL +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x0 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x4 +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L +#define FMT3_FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L +//FMT3_FMT_CONTROL +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x8 +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0xc +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x10 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE__SHIFT 0x12 +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER__SHIFT 0x14 +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x15 +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define FMT3_FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000F00L +#define FMT3_FMT_CONTROL__FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000L +#define FMT3_FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00030000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_MODE_MASK 0x000C0000L +#define FMT3_FMT_CONTROL__FMT_SUBSAMPLING_ORDER_MASK 0x00100000L +#define FMT3_FMT_CONTROL__FMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00200000L +#define FMT3_FMT_CONTROL__FMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L +//FMT3_FMT_BIT_DEPTH_CONTROL +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x0 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE__SHIFT 0x1 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x4 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x8 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x9 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0xb +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0xd +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0xe +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0xf +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x10 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x11 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x15 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x18 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x19 +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x1a +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x1c +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x1e +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_MODE_MASK 0x00000002L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000030L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00060000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0C000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L +#define FMT3_FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xC0000000L +//FMT3_FMT_DITHER_RAND_R_SEED +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_R_SEED__FMT_OFFSET_R_CR_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_G_SEED +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_G_SEED__FMT_OFFSET_G_Y_MASK 0xFFFF0000L +//FMT3_FMT_DITHER_RAND_B_SEED +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x0 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB__SHIFT 0x10 +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000FFL +#define FMT3_FMT_DITHER_RAND_B_SEED__FMT_OFFSET_B_CB_MASK 0xFFFF0000L +//FMT3_FMT_CLAMP_CNTL +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x0 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x10 +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L +#define FMT3_FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L +//FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH__SHIFT 0x0 +#define FMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL__FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH_MASK 0x00001FFFL +//FMT3_FMT_MAP420_MEMORY_CONTROL +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE__SHIFT 0x0 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS__SHIFT 0x4 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE__SHIFT 0x8 +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_FORCE_MASK 0x00000003L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_DIS_MASK 0x00000010L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_MAP420MEM_PWR_STATE_MASK 0x00000300L +#define FMT3_FMT_MAP420_MEMORY_CONTROL__FMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L +//FMT3_FMT_422_CONTROL +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT__SHIFT 0x0 +#define FMT3_FMT_422_CONTROL__FMT_LEFT_EDGE_EXTRA_PIXEL_COUNT_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_dpg3_dispdec +//DPG3_DPG_CONTROL +#define DPG3_DPG_CONTROL__DPG_EN__SHIFT 0x0 +#define DPG3_DPG_CONTROL__DPG_MODE__SHIFT 0x4 +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE__SHIFT 0x8 +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH__SHIFT 0xc +#define DPG3_DPG_CONTROL__DPG_VRES__SHIFT 0x10 +#define DPG3_DPG_CONTROL__DPG_HRES__SHIFT 0x14 +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY__SHIFT 0x18 +#define DPG3_DPG_CONTROL__DPG_EN_MASK 0x00000001L +#define DPG3_DPG_CONTROL__DPG_MODE_MASK 0x00000070L +#define DPG3_DPG_CONTROL__DPG_DYNAMIC_RANGE_MASK 0x00000100L +#define DPG3_DPG_CONTROL__DPG_BIT_DEPTH_MASK 0x00003000L +#define DPG3_DPG_CONTROL__DPG_VRES_MASK 0x000F0000L +#define DPG3_DPG_CONTROL__DPG_HRES_MASK 0x00F00000L +#define DPG3_DPG_CONTROL__DPG_FIELD_POLARITY_MASK 0x01000000L +//DPG3_DPG_RAMP_CONTROL +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET__SHIFT 0x0 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0__SHIFT 0x18 +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1__SHIFT 0x1c +#define DPG3_DPG_RAMP_CONTROL__DPG_RAMP0_OFFSET_MASK 0x0000FFFFL +#define DPG3_DPG_RAMP_CONTROL__DPG_INC0_MASK 0x0F000000L +#define DPG3_DPG_RAMP_CONTROL__DPG_INC1_MASK 0xF0000000L +//DPG3_DPG_DIMENSIONS +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT__SHIFT 0x0 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH__SHIFT 0x10 +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_HEIGHT_MASK 0x00003FFFL +#define DPG3_DPG_DIMENSIONS__DPG_ACTIVE_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_COLOUR_R_CR +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR__SHIFT 0x0 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR__SHIFT 0x10 +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR0_R_CR_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_R_CR__DPG_COLOUR1_R_CR_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_G_Y +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y__SHIFT 0x0 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y__SHIFT 0x10 +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR0_G_Y_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_G_Y__DPG_COLOUR1_G_Y_MASK 0xFFFF0000L +//DPG3_DPG_COLOUR_B_CB +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB__SHIFT 0x0 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB__SHIFT 0x10 +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR0_B_CB_MASK 0x0000FFFFL +#define DPG3_DPG_COLOUR_B_CB__DPG_COLOUR1_B_CB_MASK 0xFFFF0000L +//DPG3_DPG_OFFSET_SEGMENT +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET__SHIFT 0x0 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH__SHIFT 0x10 +#define DPG3_DPG_OFFSET_SEGMENT__DPG_X_OFFSET_MASK 0x00003FFFL +#define DPG3_DPG_OFFSET_SEGMENT__DPG_SEGMENT_WIDTH_MASK 0x3FFF0000L +//DPG3_DPG_STATUS +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING__SHIFT 0x0 +#define DPG3_DPG_STATUS__DPG_DOUBLE_BUFFER_PENDING_MASK 0x00000001L + + +// addressBlock: dce_dc_opp_oppbuf3_dispdec +//OPPBUF3_OPPBUF_CONTROL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION__SHIFT 0x10 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM__SHIFT 0x14 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION__SHIFT 0x18 +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING__SHIFT 0x1c +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_ACTIVE_WIDTH_MASK 0x00003FFFL +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DISPLAY_SEGMENTATION_MASK 0x00070000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_OVERLAP_PIXEL_NUM_MASK 0x00F00000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_PIXEL_REPETITION_MASK 0x0F000000L +#define OPPBUF3_OPPBUF_CONTROL__OPPBUF_DOUBLE_BUFFER_PENDING_MASK 0x10000000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE__SHIFT 0xa +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R__SHIFT 0x14 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE1_SIZE_MASK 0x000003FFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_3D_VACT_SPACE2_SIZE_MASK 0x000FFC00L +#define OPPBUF3_OPPBUF_3D_PARAMETERS_0__OPPBUF_DUMMY_DATA_R_MASK 0xFFF00000L +//OPPBUF3_OPPBUF_3D_PARAMETERS_1 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G__SHIFT 0x0 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B__SHIFT 0x10 +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_G_MASK 0x00000FFFL +#define OPPBUF3_OPPBUF_3D_PARAMETERS_1__OPPBUF_DUMMY_DATA_B_MASK 0x0FFF0000L +//OPPBUF3_OPPBUF_CONTROL1 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS__SHIFT 0x0 +#define OPPBUF3_OPPBUF_CONTROL1__OPPBUF_NUM_SEGMENT_PADDED_PIXELS_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_opp_pipe3_dispdec +//OPP_PIPE3_OPP_PIPE_CONTROL +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN__SHIFT 0x0 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON__SHIFT 0x1 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x4 +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_EN_MASK 0x00000001L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_CLOCK_ON_MASK 0x00000002L +#define OPP_PIPE3_OPP_PIPE_CONTROL__OPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010L + + +// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec +//OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN__SHIFT 0x4 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE__SHIFT 0x8 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN__SHIFT 0xa +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE__SHIFT 0xc +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN__SHIFT 0xe +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT__SHIFT 0x14 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT__SHIFT 0x18 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_EN_MASK 0x00000001L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_CONT_EN_MASK 0x00000010L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_MODE_MASK 0x00000300L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_STEREO_EN_MASK 0x00000400L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_INTERLACE_EN_MASK 0x00004000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_PIXEL_SELECT_MASK 0x00300000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_SOURCE_SELECT_MASK 0x01000000L +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL__OPP_PIPE_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +//OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_MASK__OPP_PIPE_CRC_MASK_MASK 0x0000FFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTA__OPP_PIPE_CRC_RESULT_A_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTR__OPP_PIPE_CRC_RESULT_R_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTG__OPP_PIPE_CRC_RESULT_G_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTB__OPP_PIPE_CRC_RESULT_B_MASK 0xFFFFFFFFL +//OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C__SHIFT 0x0 +#define OPP_PIPE_CRC3_OPP_PIPE_CRC_RESULTC__OPP_PIPE_CRC_RESULT_C_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_opp_top_dispdec +//OPP_TOP_CLK_CONTROL +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS__SHIFT 0x4 +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL__SHIFT 0x8 +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON__SHIFT 0xc +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON__SHIFT 0xd +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON__SHIFT 0xe +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON__SHIFT 0xf +#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS__SHIFT 0x18 +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPP_TOP_CLK_CONTROL__OPP_DISPCLK_G_ABM_GATE_DIS_MASK 0x00000010L +#define OPP_TOP_CLK_CONTROL__OPP_TEST_CLK_SEL_MASK 0x00000F00L +#define OPP_TOP_CLK_CONTROL__OPP_ABM0_CLOCK_ON_MASK 0x00001000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM1_CLOCK_ON_MASK 0x00002000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM2_CLOCK_ON_MASK 0x00004000L +#define OPP_TOP_CLK_CONTROL__OPP_ABM3_CLOCK_ON_MASK 0x00008000L +#define OPP_TOP_CLK_CONTROL__OPP_FGCG_REP_DIS_MASK 0x01000000L +//OPP_ABM_CONTROL +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL__SHIFT 0x0 +#define OPP_ABM_CONTROL__OPP_ABM_BLPWM_SEL_MASK 0x00000007L + + +// addressBlock: dce_dc_opp_dscrm0_dispdec +//DSCRM0_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM0_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm1_dispdec +//DSCRM1_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM1_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm2_dispdec +//DSCRM2_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM2_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_dscrm3_dispdec +//DSCRM3_DSCRM_DSC_FORWARD_CONFIG +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN__SHIFT 0x0 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE__SHIFT 0x4 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x8 +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS__SHIFT 0xc +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_MASK 0x00000001L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_OPP_PIPE_SOURCE_MASK 0x00000070L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000100L +#define DSCRM3_DSCRM_DSC_FORWARD_CONFIG__DSCRM_DSC_FORWARD_EN_STATUS_MASK 0x00001000L + + +// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON14_PERFCOUNTER_CNTL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_CNTL2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON14_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFCOUNTER_STATE +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON14_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON14_PERFMON_CNTL +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON14_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON14_PERFMON_CNTL2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON14_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON14_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON14_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON14_PERFMON_CVALUE_LOW +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON14_PERFMON_HI +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON14_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON14_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON14_PERFMON_LOW +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON14_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm0_dispdec +//ODM0_OPTC_INPUT_GLOBAL_CONTROL +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM0_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM0_OPTC_RSMU_UNDERFLOW +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN__SHIFT 0x0 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS__SHIFT 0x1 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS__SHIFT 0x2 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR__SHIFT 0x3 +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_EN_MASK 0x00000001L +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000002L +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_INT_STATUS_MASK 0x00000004L +#define ODM0_OPTC_RSMU_UNDERFLOW__OPTC_RSMU_UNDERFLOW_CLEAR_MASK 0x00000008L +//ODM0_OPTC_UNDERFLOW_THRESHOLD +#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM0_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM0_OPTC_DATA_SOURCE_SELECT +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM0_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM0_OPTC_DATA_FORMAT_CONTROL +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM0_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM0_OPTC_BYTES_PER_PIXEL +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM0_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM0_OPTC_WIDTH_CONTROL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM0_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM0_OPTC_WIDTH_CONTROL2 +#define ODM0_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM0_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM0_OPTC_INPUT_CLOCK_CONTROL +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM0_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM0_OPTC_MEMORY_CONFIG +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM0_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM0_OPTC_INPUT_SPARE_REGISTER +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM0_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm1_dispdec +//ODM1_OPTC_INPUT_GLOBAL_CONTROL +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM1_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM1_OPTC_UNDERFLOW_THRESHOLD +#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM1_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM1_OPTC_DATA_SOURCE_SELECT +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM1_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM1_OPTC_DATA_FORMAT_CONTROL +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM1_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM1_OPTC_BYTES_PER_PIXEL +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM1_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM1_OPTC_WIDTH_CONTROL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM1_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM1_OPTC_WIDTH_CONTROL2 +#define ODM1_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM1_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM1_OPTC_INPUT_CLOCK_CONTROL +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM1_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM1_OPTC_MEMORY_CONFIG +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM1_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM1_OPTC_INPUT_SPARE_REGISTER +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM1_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm2_dispdec +//ODM2_OPTC_INPUT_GLOBAL_CONTROL +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM2_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM2_OPTC_UNDERFLOW_THRESHOLD +#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM2_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM2_OPTC_DATA_SOURCE_SELECT +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM2_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM2_OPTC_DATA_FORMAT_CONTROL +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM2_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM2_OPTC_BYTES_PER_PIXEL +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM2_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM2_OPTC_WIDTH_CONTROL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM2_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM2_OPTC_WIDTH_CONTROL2 +#define ODM2_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM2_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM2_OPTC_INPUT_CLOCK_CONTROL +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM2_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM2_OPTC_MEMORY_CONFIG +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM2_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM2_OPTC_INPUT_SPARE_REGISTER +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM2_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_odm3_dispdec +//ODM3_OPTC_INPUT_GLOBAL_CONTROL +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET__SHIFT 0x0 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN__SHIFT 0x8 +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS__SHIFT 0xa +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS__SHIFT 0xb +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR__SHIFT 0xc +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT__SHIFT 0xd +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING__SHIFT 0x1f +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_INPUT_SOFT_RESET_MASK 0x00000001L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_EN_MASK 0x00000100L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_STATUS_MASK 0x00000400L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_INT_STATUS_MASK 0x00000800L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_CLEAR_MASK 0x00001000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_UNDERFLOW_OCCURRED_CURRENT_MASK 0x00002000L +#define ODM3_OPTC_INPUT_GLOBAL_CONTROL__OPTC_DOUBLE_BUFFER_PENDING_MASK 0x80000000L +//ODM3_OPTC_UNDERFLOW_THRESHOLD +#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD__SHIFT 0x0 +#define ODM3_OPTC_UNDERFLOW_THRESHOLD__OPTC_UNDERFLOW_THRESHOLD_MASK 0x01FFFFFFL +//ODM3_OPTC_DATA_SOURCE_SELECT +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT__SHIFT 0x0 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT__SHIFT 0x8 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL__SHIFT 0x10 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL__SHIFT 0x14 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL__SHIFT 0x18 +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL__SHIFT 0x1c +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_INPUT_SEGMENT_MASK 0x00000003L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_NUM_OF_OUTPUT_SEGMENT_MASK 0x00000300L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG0_SRC_SEL_MASK 0x000F0000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG1_SRC_SEL_MASK 0x00F00000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG2_SRC_SEL_MASK 0x0F000000L +#define ODM3_OPTC_DATA_SOURCE_SELECT__OPTC_SEG3_SRC_SEL_MASK 0xF0000000L +//ODM3_OPTC_DATA_FORMAT_CONTROL +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT__SHIFT 0x0 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE__SHIFT 0x4 +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DATA_FORMAT_MASK 0x00000003L +#define ODM3_OPTC_DATA_FORMAT_CONTROL__OPTC_DSC_MODE_MASK 0x00000030L +//ODM3_OPTC_BYTES_PER_PIXEL +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL__SHIFT 0x0 +#define ODM3_OPTC_BYTES_PER_PIXEL__OPTC_DSC_BYTES_PER_PIXEL_MASK 0x7FFFFFFFL +//ODM3_OPTC_WIDTH_CONTROL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH__SHIFT 0x10 +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_SEGMENT_WIDTH_MASK 0x00001FFFL +#define ODM3_OPTC_WIDTH_CONTROL__OPTC_DSC_SLICE_WIDTH_MASK 0x1FFF0000L +//ODM3_OPTC_WIDTH_CONTROL2 +#define ODM3_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST__SHIFT 0x0 +#define ODM3_OPTC_WIDTH_CONTROL2__OPTC_SEGMENT_WIDTH_LAST_MASK 0x00001FFFL +//ODM3_OPTC_INPUT_CLOCK_CONTROL +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS__SHIFT 0x0 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN__SHIFT 0x1 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON__SHIFT 0x2 +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_GATE_DIS_MASK 0x00000001L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_EN_MASK 0x00000002L +#define ODM3_OPTC_INPUT_CLOCK_CONTROL__OPTC_INPUT_CLK_ON_MASK 0x00000004L +//ODM3_OPTC_MEMORY_CONFIG +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL__SHIFT 0x0 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS__SHIFT 0x10 +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_MASK 0x0000FFFFL +#define ODM3_OPTC_MEMORY_CONFIG__OPTC_MEM_SEL_STATUS_MASK 0xFFFF0000L +//ODM3_OPTC_INPUT_SPARE_REGISTER +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG__SHIFT 0x0 +#define ODM3_OPTC_INPUT_SPARE_REGISTER__OPTC_INPUT_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg0_dispdec +//OTG0_OTG_H_TOTAL +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG0_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_H_BLANK_START_END +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_H_SYNC_A_CNTL +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG0_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG0_OTG_H_TIMING_CNTL +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG0_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG0_OTG_V_TOTAL +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MIN +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MAX +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_MID +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG0_OTG_V_TOTAL_CONTROL +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG0_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_V_COUNT_STOP_CONTROL +#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG0_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG0_OTG_V_COUNT_STOP_CONTROL2 +#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG0_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG0_OTG_V_TOTAL_INT_STATUS +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG0_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG0_OTG_VSYNC_NOM_INT_STATUS +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG0_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG0_OTG_V_BLANK_START_END +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG0_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG0_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG0_OTG_V_SYNC_A_CNTL +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG0_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG0_OTG_TRIGA_CNTL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGA_MANUAL_TRIG +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_TRIGB_CNTL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG0_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG0_OTG_TRIGB_MANUAL_TRIG +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG0_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG0_OTG_FORCE_COUNT_NOW_CNTL +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG0_OTG_STEREO_FORCE_NEXT_EYE +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG0_OTG_CONTROL +#define OTG0_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG0_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG0_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG0_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG0_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG0_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG0_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG0_OTG_DLPC_CONTROL +#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG0_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG0_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG0_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG0_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG0_OTG_INTERLACE_CONTROL +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG0_OTG_INTERLACE_STATUS +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG0_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG0_OTG_PIXEL_DATA_READBACK0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG0_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG0_OTG_PIXEL_DATA_READBACK1 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG0_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG0_OTG_STATUS +#define OTG0_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG0_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG0_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG0_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG0_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG0_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG0_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG0_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG0_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG0_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG0_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG0_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG0_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG0_OTG_STATUS_POSITION +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG0_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_LONG_VBLANK_STATUS +#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG0_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG0_OTG_NOM_VERT_POSITION +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG0_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG0_OTG_STATUS_FRAME_COUNT +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_STATUS_VF_COUNT +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_STATUS_HV_COUNT +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG0_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG0_OTG_COUNT_CONTROL +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG0_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG0_OTG_COUNT_RESET +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG0_OTG_VERT_SYNC_CONTROL +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG0_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG0_OTG_STEREO_STATUS +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG0_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG0_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG0_OTG_STEREO_CONTROL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG0_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG0_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG0_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG0_OTG_SNAPSHOT_STATUS +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG0_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG0_OTG_SNAPSHOT_CONTROL +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG0_OTG_SNAPSHOT_POSITION +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG0_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG0_OTG_SNAPSHOT_FRAME +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG0_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG0_OTG_INTERRUPT_CONTROL +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG0_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG0_OTG_UPDATE_LOCK +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG0_OTG_DOUBLE_BUFFER_CONTROL +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG0_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG0_OTG_MASTER_EN +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG0_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG0_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG0_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG0_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG0_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG0_OTG_CRC_CNTL +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG0_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG0_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG0_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG0_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_DATA_R +#define OTG0_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_G +#define OTG0_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_B +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_C +#define OTG0_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_DATA_R +#define OTG0_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_DATA_G +#define OTG0_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_DATA_B +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC1_DATA_C +#define OTG0_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG0_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_R +#define OTG0_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_G +#define OTG0_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_B +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC2_DATA_C +#define OTG0_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG0_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_R +#define OTG0_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_G +#define OTG0_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_B +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC3_DATA_C +#define OTG0_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG0_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC0_DATA_AES +#define OTG0_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG0_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG0_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG0_OTG_STATIC_SCREEN_CONTROL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG0_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG0_OTG_3D_STRUCTURE_CONTROL +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG0_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG0_OTG_GSL_VSYNC_GAP +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG0_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG0_OTG_MASTER_UPDATE_MODE +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG0_OTG_CLOCK_CONTROL +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG0_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG0_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG0_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG0_OTG_VSTARTUP_PARAM +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG0_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG0_OTG_VUPDATE_PARAM +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG0_OTG_VREADY_PARAM +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG0_OTG_GLOBAL_SYNC_STATUS +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG0_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG0_OTG_MASTER_UPDATE_LOCK +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG0_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG0_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG0_OTG_GSL_CONTROL +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG0_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG0_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG0_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG0_OTG_GSL_WINDOW_X +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_GSL_WINDOW_Y +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG0_OTG_VUPDATE_KEEPOUT +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG0_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG0_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL1 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL2 +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG0_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG0_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG0_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG0_OTG_GLOBAL_CONTROL3 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG0_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG0_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG0_OTG_GLOBAL_CONTROL4 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG0_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG0_OTG_TRIG_MANUAL_CONTROL +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG0_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG0_OTG_DRR_TIMING_INT_STATUS +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG0_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG0_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG0_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG0_OTG_DRR_V_TOTAL_CHANGE +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG0_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG0_OTG_DRR_TRIGGER_WINDOW +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG0_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTROL +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG0_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG0_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG0_OTG_DRR_CONTOL2 +#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG0_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG0_OTG_M_CONST_DTO1 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG0_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG0_OTG_REQUEST_CONTROL +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG0_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG0_OTG_PIPE_UPDATE_STATUS +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG0_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG0_OTG_PSTATE_REGISTER +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG0_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG0_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG0_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG0_OTG_ENCRYPTION +#define OTG0_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG0_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG0_OTG_SPARE_REGISTER +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG0_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg1_dispdec +//OTG1_OTG_H_TOTAL +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG1_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_H_BLANK_START_END +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_H_SYNC_A_CNTL +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG1_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG1_OTG_H_TIMING_CNTL +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG1_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG1_OTG_V_TOTAL +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MIN +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MAX +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_MID +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG1_OTG_V_TOTAL_CONTROL +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG1_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_V_COUNT_STOP_CONTROL +#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG1_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG1_OTG_V_COUNT_STOP_CONTROL2 +#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG1_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG1_OTG_V_TOTAL_INT_STATUS +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG1_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG1_OTG_VSYNC_NOM_INT_STATUS +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG1_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG1_OTG_V_BLANK_START_END +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG1_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG1_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG1_OTG_V_SYNC_A_CNTL +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG1_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG1_OTG_TRIGA_CNTL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGA_MANUAL_TRIG +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_TRIGB_CNTL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG1_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG1_OTG_TRIGB_MANUAL_TRIG +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG1_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG1_OTG_FORCE_COUNT_NOW_CNTL +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG1_OTG_STEREO_FORCE_NEXT_EYE +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG1_OTG_CONTROL +#define OTG1_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG1_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG1_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG1_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG1_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG1_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG1_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG1_OTG_DLPC_CONTROL +#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG1_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG1_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG1_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG1_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG1_OTG_INTERLACE_CONTROL +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG1_OTG_INTERLACE_STATUS +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG1_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG1_OTG_PIXEL_DATA_READBACK0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG1_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG1_OTG_PIXEL_DATA_READBACK1 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG1_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG1_OTG_STATUS +#define OTG1_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG1_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG1_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG1_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG1_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG1_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG1_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG1_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG1_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG1_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG1_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG1_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG1_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG1_OTG_STATUS_POSITION +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG1_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_LONG_VBLANK_STATUS +#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG1_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG1_OTG_NOM_VERT_POSITION +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG1_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG1_OTG_STATUS_FRAME_COUNT +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_STATUS_VF_COUNT +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_STATUS_HV_COUNT +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG1_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG1_OTG_COUNT_CONTROL +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG1_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG1_OTG_COUNT_RESET +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG1_OTG_VERT_SYNC_CONTROL +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG1_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG1_OTG_STEREO_STATUS +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG1_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG1_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG1_OTG_STEREO_CONTROL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG1_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG1_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG1_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG1_OTG_SNAPSHOT_STATUS +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG1_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG1_OTG_SNAPSHOT_CONTROL +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG1_OTG_SNAPSHOT_POSITION +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG1_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG1_OTG_SNAPSHOT_FRAME +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG1_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG1_OTG_INTERRUPT_CONTROL +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG1_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG1_OTG_UPDATE_LOCK +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG1_OTG_DOUBLE_BUFFER_CONTROL +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG1_OTG_MASTER_EN +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG1_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG1_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG1_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG1_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG1_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG1_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG1_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG1_OTG_CRC_CNTL +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG1_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG1_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG1_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG1_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_DATA_R +#define OTG1_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_G +#define OTG1_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_B +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_C +#define OTG1_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_DATA_R +#define OTG1_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_DATA_G +#define OTG1_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_DATA_B +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC1_DATA_C +#define OTG1_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG1_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_R +#define OTG1_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_G +#define OTG1_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_B +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC2_DATA_C +#define OTG1_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG1_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_R +#define OTG1_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_G +#define OTG1_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_B +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC3_DATA_C +#define OTG1_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG1_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC0_DATA_AES +#define OTG1_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG1_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG1_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG1_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG1_OTG_STATIC_SCREEN_CONTROL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG1_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG1_OTG_3D_STRUCTURE_CONTROL +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG1_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG1_OTG_GSL_VSYNC_GAP +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG1_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG1_OTG_MASTER_UPDATE_MODE +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG1_OTG_CLOCK_CONTROL +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG1_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG1_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG1_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG1_OTG_VSTARTUP_PARAM +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG1_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG1_OTG_VUPDATE_PARAM +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG1_OTG_VREADY_PARAM +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG1_OTG_GLOBAL_SYNC_STATUS +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG1_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG1_OTG_MASTER_UPDATE_LOCK +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG1_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG1_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG1_OTG_GSL_CONTROL +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG1_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG1_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG1_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG1_OTG_GSL_WINDOW_X +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_GSL_WINDOW_Y +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG1_OTG_VUPDATE_KEEPOUT +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG1_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG1_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL1 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL2 +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG1_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG1_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG1_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG1_OTG_GLOBAL_CONTROL3 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG1_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG1_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG1_OTG_GLOBAL_CONTROL4 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG1_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG1_OTG_TRIG_MANUAL_CONTROL +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG1_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG1_OTG_DRR_TIMING_INT_STATUS +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG1_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG1_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG1_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG1_OTG_DRR_V_TOTAL_CHANGE +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG1_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG1_OTG_DRR_TRIGGER_WINDOW +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG1_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTROL +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG1_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG1_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG1_OTG_DRR_CONTOL2 +#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG1_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG1_OTG_M_CONST_DTO1 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG1_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG1_OTG_REQUEST_CONTROL +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG1_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG1_OTG_PIPE_UPDATE_STATUS +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG1_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG1_OTG_PSTATE_REGISTER +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG1_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG1_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG1_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG1_OTG_ENCRYPTION +#define OTG1_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG1_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG1_OTG_SPARE_REGISTER +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG1_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg2_dispdec +//OTG2_OTG_H_TOTAL +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG2_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_H_BLANK_START_END +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_H_SYNC_A_CNTL +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG2_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG2_OTG_H_TIMING_CNTL +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG2_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG2_OTG_V_TOTAL +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MIN +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MAX +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_MID +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG2_OTG_V_TOTAL_CONTROL +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG2_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_V_COUNT_STOP_CONTROL +#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG2_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG2_OTG_V_COUNT_STOP_CONTROL2 +#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG2_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG2_OTG_V_TOTAL_INT_STATUS +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG2_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG2_OTG_VSYNC_NOM_INT_STATUS +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG2_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG2_OTG_V_BLANK_START_END +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG2_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG2_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG2_OTG_V_SYNC_A_CNTL +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG2_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG2_OTG_TRIGA_CNTL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGA_MANUAL_TRIG +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_TRIGB_CNTL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG2_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG2_OTG_TRIGB_MANUAL_TRIG +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG2_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG2_OTG_FORCE_COUNT_NOW_CNTL +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG2_OTG_STEREO_FORCE_NEXT_EYE +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG2_OTG_CONTROL +#define OTG2_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG2_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG2_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG2_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG2_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG2_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG2_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG2_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG2_OTG_DLPC_CONTROL +#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG2_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG2_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG2_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG2_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG2_OTG_INTERLACE_CONTROL +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG2_OTG_INTERLACE_STATUS +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG2_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG2_OTG_PIXEL_DATA_READBACK0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG2_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG2_OTG_PIXEL_DATA_READBACK1 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG2_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG2_OTG_STATUS +#define OTG2_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG2_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG2_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG2_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG2_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG2_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG2_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG2_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG2_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG2_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG2_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG2_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG2_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG2_OTG_STATUS_POSITION +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG2_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_LONG_VBLANK_STATUS +#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG2_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG2_OTG_NOM_VERT_POSITION +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG2_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG2_OTG_STATUS_FRAME_COUNT +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_STATUS_VF_COUNT +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_STATUS_HV_COUNT +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG2_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG2_OTG_COUNT_CONTROL +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG2_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG2_OTG_COUNT_RESET +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG2_OTG_VERT_SYNC_CONTROL +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG2_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG2_OTG_STEREO_STATUS +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG2_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG2_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG2_OTG_STEREO_CONTROL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG2_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG2_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG2_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG2_OTG_SNAPSHOT_STATUS +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG2_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG2_OTG_SNAPSHOT_CONTROL +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG2_OTG_SNAPSHOT_POSITION +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG2_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG2_OTG_SNAPSHOT_FRAME +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG2_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG2_OTG_INTERRUPT_CONTROL +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG2_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG2_OTG_UPDATE_LOCK +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG2_OTG_DOUBLE_BUFFER_CONTROL +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG2_OTG_MASTER_EN +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG2_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG2_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG2_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG2_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG2_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG2_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG2_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG2_OTG_CRC_CNTL +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG2_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG2_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG2_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG2_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_DATA_R +#define OTG2_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_G +#define OTG2_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_B +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_C +#define OTG2_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_DATA_R +#define OTG2_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_DATA_G +#define OTG2_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_DATA_B +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC1_DATA_C +#define OTG2_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG2_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_R +#define OTG2_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_G +#define OTG2_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_B +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC2_DATA_C +#define OTG2_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG2_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_R +#define OTG2_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_G +#define OTG2_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_B +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC3_DATA_C +#define OTG2_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG2_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC0_DATA_AES +#define OTG2_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG2_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG2_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG2_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG2_OTG_STATIC_SCREEN_CONTROL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG2_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG2_OTG_3D_STRUCTURE_CONTROL +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG2_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG2_OTG_GSL_VSYNC_GAP +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG2_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG2_OTG_MASTER_UPDATE_MODE +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG2_OTG_CLOCK_CONTROL +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG2_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG2_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG2_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG2_OTG_VSTARTUP_PARAM +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG2_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG2_OTG_VUPDATE_PARAM +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG2_OTG_VREADY_PARAM +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG2_OTG_GLOBAL_SYNC_STATUS +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG2_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG2_OTG_MASTER_UPDATE_LOCK +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG2_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG2_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG2_OTG_GSL_CONTROL +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG2_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG2_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG2_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG2_OTG_GSL_WINDOW_X +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_GSL_WINDOW_Y +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG2_OTG_VUPDATE_KEEPOUT +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG2_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG2_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL1 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL2 +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG2_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG2_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG2_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG2_OTG_GLOBAL_CONTROL3 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG2_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG2_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG2_OTG_GLOBAL_CONTROL4 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG2_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG2_OTG_TRIG_MANUAL_CONTROL +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG2_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG2_OTG_DRR_TIMING_INT_STATUS +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG2_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG2_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG2_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG2_OTG_DRR_V_TOTAL_CHANGE +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG2_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG2_OTG_DRR_TRIGGER_WINDOW +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG2_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTROL +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG2_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG2_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG2_OTG_DRR_CONTOL2 +#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG2_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG2_OTG_M_CONST_DTO1 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG2_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG2_OTG_REQUEST_CONTROL +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG2_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG2_OTG_PIPE_UPDATE_STATUS +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG2_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG2_OTG_PSTATE_REGISTER +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG2_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG2_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG2_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG2_OTG_ENCRYPTION +#define OTG2_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG2_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG2_OTG_SPARE_REGISTER +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG2_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_otg3_dispdec +//OTG3_OTG_H_TOTAL +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL__SHIFT 0x0 +#define OTG3_OTG_H_TOTAL__OTG_H_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_H_BLANK_START_END +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_H_BLANK_START_END__OTG_H_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_H_SYNC_A__OTG_H_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_H_SYNC_A_CNTL +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN__SHIFT 0x10 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF__SHIFT 0x11 +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_COMP_SYNC_A_EN_MASK 0x00010000L +#define OTG3_OTG_H_SYNC_A_CNTL__OTG_H_SYNC_A_CUTOFF_MASK 0x00020000L +//OTG3_OTG_H_TIMING_CNTL +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE__SHIFT 0x0 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL__SHIFT 0x8 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR__SHIFT 0x10 +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MASK 0x00000003L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_MANUAL_MASK 0x00000100L +#define OTG3_OTG_H_TIMING_CNTL__OTG_H_TIMING_DIV_MODE_CURR_MASK 0x00030000L +//OTG3_OTG_V_TOTAL +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL__OTG_V_TOTAL_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MIN +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MIN__OTG_V_TOTAL_MIN_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MAX +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MAX__OTG_V_TOTAL_MAX_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_MID +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_MID__OTG_V_TOTAL_MID_MASK 0x00007FFFL +//OTG3_OTG_V_TOTAL_CONTROL +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL__SHIFT 0x1 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN__SHIFT 0x2 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN__SHIFT 0x3 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD__SHIFT 0x5 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK__SHIFT 0x10 +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MIN_SEL_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_V_TOTAL_MAX_SEL_MASK 0x00000002L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MAX_EN_MASK 0x00000004L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_REPLACING_MIN_EN_MASK 0x00000008L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_FORCE_LOCK_ON_EVENT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_DRR_EVENT_ACTIVE_PERIOD_MASK 0x00000020L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_VTOTAL_MID_FRAME_NUM_MASK 0x0000FF00L +#define OTG3_OTG_V_TOTAL_CONTROL__OTG_SET_V_TOTAL_MIN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_V_COUNT_STOP_CONTROL +#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP__SHIFT 0x0 +#define OTG3_OTG_V_COUNT_STOP_CONTROL__OTG_V_COUNT_STOP_MASK 0x00007FFFL +//OTG3_OTG_V_COUNT_STOP_CONTROL2 +#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER__SHIFT 0x0 +#define OTG3_OTG_V_COUNT_STOP_CONTROL2__OTG_V_COUNT_STOP_TIMER_MASK 0xFFFFFFFFL +//OTG3_OTG_V_TOTAL_INT_STATUS +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK__SHIFT 0x8 +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK__SHIFT 0xc +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_MASK 0x00000100L +#define OTG3_OTG_V_TOTAL_INT_STATUS__OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_MSK_MASK 0x00001000L +//OTG3_OTG_VSYNC_NOM_INT_STATUS +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM__SHIFT 0x0 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_MASK 0x00000001L +#define OTG3_OTG_VSYNC_NOM_INT_STATUS__OTG_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L +//OTG3_OTG_V_BLANK_START_END +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START__SHIFT 0x0 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END__SHIFT 0x10 +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_START_MASK 0x00007FFFL +#define OTG3_OTG_V_BLANK_START_END__OTG_V_BLANK_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END__SHIFT 0x10 +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_START_MASK 0x00007FFFL +#define OTG3_OTG_V_SYNC_A__OTG_V_SYNC_A_END_MASK 0x7FFF0000L +//OTG3_OTG_V_SYNC_A_CNTL +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL__SHIFT 0x0 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE__SHIFT 0x8 +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_A_POL_MASK 0x00000001L +#define OTG3_OTG_V_SYNC_A_CNTL__OTG_V_SYNC_MODE_MASK 0x00000100L +//OTG3_OTG_TRIGA_CNTL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGA_CNTL__OTG_TRIGA_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGA_MANUAL_TRIG +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGA_MANUAL_TRIG__OTG_TRIGA_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_TRIGB_CNTL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT__SHIFT 0x0 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT__SHIFT 0x5 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT__SHIFT 0x8 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN__SHIFT 0xb +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS__SHIFT 0xc +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS__SHIFT 0xd +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED__SHIFT 0xe +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x10 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x12 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT__SHIFT 0x14 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY__SHIFT 0x18 +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR__SHIFT 0x1f +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_SELECT_MASK 0x0000001FL +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_SOURCE_PIPE_SELECT_MASK 0x000000E0L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_SELECT_MASK 0x00000700L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000800L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_INPUT_STATUS_MASK 0x00001000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_POLARITY_STATUS_MASK 0x00002000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00030000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x000C0000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_DELAY_MASK 0x1F000000L +#define OTG3_OTG_TRIGB_CNTL__OTG_TRIGB_CLEAR_MASK 0x80000000L +//OTG3_OTG_TRIGB_MANUAL_TRIG +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG__SHIFT 0x0 +#define OTG3_OTG_TRIGB_MANUAL_TRIG__OTG_TRIGB_MANUAL_TRIG_MASK 0x00000001L +//OTG3_OTG_FORCE_COUNT_NOW_CNTL +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE__SHIFT 0x0 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK__SHIFT 0x4 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x8 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR__SHIFT 0x18 +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_MODE_MASK 0x00000003L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_FORCE_COUNT_NOW_CNTL__OTG_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L +//OTG3_OTG_STEREO_FORCE_NEXT_EYE +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_FORCE_NEXT_EYE__OTG_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L +//OTG3_OTG_CONTROL +#define OTG3_OTG_CONTROL__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL__SHIFT 0x8 +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL__SHIFT 0xc +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT 0xd +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY__SHIFT 0xe +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE__SHIFT 0x10 +#define OTG3_OTG_CONTROL__OTG_OUT_MUX__SHIFT 0x14 +#define OTG3_OTG_CONTROL__OTG_MASTER_EN_MASK 0x00000001L +#define OTG3_OTG_CONTROL__OTG_DISABLE_POINT_CNTL_MASK 0x00000300L +#define OTG3_OTG_CONTROL__OTG_START_POINT_CNTL_MASK 0x00001000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL_MASK 0x00002000L +#define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_POLARITY_MASK 0x00004000L +#define OTG3_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK 0x00010000L +#define OTG3_OTG_CONTROL__OTG_OUT_MUX_MASK 0x00300000L +//OTG3_OTG_DLPC_CONTROL +#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE__SHIFT 0x0 +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION__SHIFT 0x10 +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT__SHIFT 0x1f +#define OTG3_OTG_DLPC_CONTROL__OTG_RESYNC_MODE_MASK 0x00000001L +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_LOCATION_MASK 0x7FFF0000L +#define OTG3_OTG_DLPC_CONTROL__OTG_DLPC_SNAPSHOT_CURRENT_MASK 0x80000000L +//OTG3_OTG_PWA_FRAME_SYNC_CONTROL +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN__SHIFT 0x0 +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE__SHIFT 0x1 +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE__SHIFT 0x10 +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_EN_MASK 0x00000001L +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_VCOUNT_MODE_MASK 0x00000002L +#define OTG3_OTG_PWA_FRAME_SYNC_CONTROL__OTG_PWA_FRAME_SYNC_LINE_MASK 0x03FF0000L +//OTG3_OTG_INTERLACE_CONTROL +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x10 +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_ENABLE_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_CONTROL__OTG_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L +//OTG3_OTG_INTERLACE_STATUS +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD__SHIFT 0x0 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD__SHIFT 0x1 +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_CURRENT_FIELD_MASK 0x00000001L +#define OTG3_OTG_INTERLACE_STATUS__OTG_INTERLACE_NEXT_FIELD_MASK 0x00000002L +//OTG3_OTG_PIXEL_DATA_READBACK0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y__SHIFT 0x10 +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_BLUE_CB_MASK 0x0000FFFFL +#define OTG3_OTG_PIXEL_DATA_READBACK0__OTG_PIXEL_DATA_GREEN_Y_MASK 0xFFFF0000L +//OTG3_OTG_PIXEL_DATA_READBACK1 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR__SHIFT 0x0 +#define OTG3_OTG_PIXEL_DATA_READBACK1__OTG_PIXEL_DATA_RED_CR_MASK 0x0000FFFFL +//OTG3_OTG_STATUS +#define OTG3_OTG_STATUS__OTG_V_BLANK__SHIFT 0x0 +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP__SHIFT 0x1 +#define OTG3_OTG_STATUS__OTG_V_SYNC_A__SHIFT 0x2 +#define OTG3_OTG_STATUS__OTG_V_UPDATE__SHIFT 0x3 +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE__SHIFT 0x5 +#define OTG3_OTG_STATUS__OTG_H_BLANK__SHIFT 0x10 +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP__SHIFT 0x11 +#define OTG3_OTG_STATUS__OTG_H_SYNC_A__SHIFT 0x12 +#define OTG3_OTG_STATUS__OTG_V_BLANK_MASK 0x00000001L +#define OTG3_OTG_STATUS__OTG_V_ACTIVE_DISP_MASK 0x00000002L +#define OTG3_OTG_STATUS__OTG_V_SYNC_A_MASK 0x00000004L +#define OTG3_OTG_STATUS__OTG_V_UPDATE_MASK 0x00000008L +#define OTG3_OTG_STATUS__OTG_V_BLANK_3D_STRUCTURE_MASK 0x00000020L +#define OTG3_OTG_STATUS__OTG_H_BLANK_MASK 0x00010000L +#define OTG3_OTG_STATUS__OTG_H_ACTIVE_DISP_MASK 0x00020000L +#define OTG3_OTG_STATUS__OTG_H_SYNC_A_MASK 0x00040000L +//OTG3_OTG_STATUS_POSITION +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK__SHIFT 0xf +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_STATUS_POSITION__OTG_VERT_LONG_VBLANK_MASK 0x00008000L +#define OTG3_OTG_STATUS_POSITION__OTG_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_LONG_VBLANK_STATUS +#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT__SHIFT 0x0 +#define OTG3_OTG_LONG_VBLANK_STATUS__OTG_V_COUNT_STOP_COUNT_MASK 0xFFFFFFFFL +//OTG3_OTG_NOM_VERT_POSITION +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM__SHIFT 0x0 +#define OTG3_OTG_NOM_VERT_POSITION__OTG_VERT_COUNT_NOM_MASK 0x00007FFFL +//OTG3_OTG_STATUS_FRAME_COUNT +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_FRAME_COUNT__OTG_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_STATUS_VF_COUNT +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_VF_COUNT__OTG_VF_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_STATUS_HV_COUNT +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT__SHIFT 0x0 +#define OTG3_OTG_STATUS_HV_COUNT__OTG_HV_COUNT_MASK 0x7FFFFFFFL +//OTG3_OTG_COUNT_CONTROL +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN__SHIFT 0x0 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT 0x1 +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_COUNT_BY2_EN_MASK 0x00000001L +#define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT_MASK 0x0000001EL +//OTG3_OTG_COUNT_RESET +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_COUNT_RESET__OTG_RESET_FRAME_COUNT_MASK 0x00000001L +//OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x0 +#define OTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE__OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L +//OTG3_OTG_VERT_SYNC_CONTROL +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x8 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE__SHIFT 0x10 +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L +#define OTG3_OTG_VERT_SYNC_CONTROL__OTG_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L +//OTG3_OTG_STEREO_STATUS +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE__SHIFT 0x0 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT__SHIFT 0x8 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT__SHIFT 0x10 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG__SHIFT 0x14 +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x18 +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE__SHIFT 0x1e +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE__SHIFT 0x1f +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_CURRENT_EYE_MASK 0x00000001L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_OUTPUT_MASK 0x00000100L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_SYNC_SELECT_MASK 0x00010000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_EYE_FLAG_MASK 0x00100000L +#define OTG3_OTG_STEREO_STATUS__OTG_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_3D_STRUCTURE_STATE_MASK 0x40000000L +#define OTG3_OTG_STEREO_STATUS__OTG_CURRENT_STEREOSYNC_EN_STATE_MASK 0x80000000L +//OTG3_OTG_STEREO_CONTROL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x0 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0xf +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY__SHIFT 0x11 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP__SHIFT 0x12 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM__SHIFT 0x13 +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX__SHIFT 0x14 +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL__SHIFT 0x15 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN__SHIFT 0x18 +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00007FFFL +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EYE_FLAG_POLARITY_MASK 0x00020000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP_MASK 0x00040000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_FIELD_NUM_MASK 0x00080000L +#define OTG3_OTG_STEREO_CONTROL__OTG_DISABLE_V_BLANK_FOR_DP_FIX_MASK 0x00100000L +#define OTG3_OTG_STEREO_CONTROL__OTG_FIELD_NUM_SEL_MASK 0x00200000L +#define OTG3_OTG_STEREO_CONTROL__OTG_STEREO_EN_MASK 0x01000000L +//OTG3_OTG_SNAPSHOT_STATUS +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR__SHIFT 0x1 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x2 +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_CLEAR_MASK 0x00000002L +#define OTG3_OTG_SNAPSHOT_STATUS__OTG_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L +//OTG3_OTG_SNAPSHOT_CONTROL +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_CONTROL__OTG_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L +//OTG3_OTG_SNAPSHOT_POSITION +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT__SHIFT 0x10 +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_VERT_COUNT_MASK 0x00007FFFL +#define OTG3_OTG_SNAPSHOT_POSITION__OTG_SNAPSHOT_HORZ_COUNT_MASK 0x7FFF0000L +//OTG3_OTG_SNAPSHOT_FRAME +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT__SHIFT 0x0 +#define OTG3_OTG_SNAPSHOT_FRAME__OTG_SNAPSHOT_FRAME_COUNT_MASK 0x00FFFFFFL +//OTG3_OTG_INTERRUPT_CONTROL +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK__SHIFT 0x0 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x8 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x9 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x10 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x11 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK__SHIFT 0x18 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK__SHIFT 0x19 +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE__SHIFT 0x1a +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE__SHIFT 0x1b +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x1e +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x1f +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_MSK_MASK 0x00000001L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_SNAPSHOT_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_MSK_MASK 0x01000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_MSK_MASK 0x02000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGA_INT_TYPE_MASK 0x04000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_TRIGB_INT_TYPE_MASK 0x08000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_VSYNC_NOM_INT_TYPE_MASK 0x20000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L +#define OTG3_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L +//OTG3_OTG_UPDATE_LOCK +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_UPDATE_LOCK__OTG_UPDATE_LOCK_MASK 0x00000001L +//OTG3_OTG_DOUBLE_BUFFER_CONTROL +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT 0x0 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING__SHIFT 0x5 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING__SHIFT 0x6 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING__SHIFT 0x7 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY__SHIFT 0x8 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING__SHIFT 0x9 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE__SHIFT 0x18 +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK 0x00000001L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_TIMING_DB_UPDATE_PENDING_MASK 0x00000020L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_CTRL_DB_UPDATE_PENDING_MASK 0x00000040L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_3D_STRUCTURE_EN_DB_UPDATE_PENDING_MASK 0x00000080L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_INSTANTLY_MASK 0x00000100L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_VSTARTUP_DB_UPDATE_PENDING_MASK 0x00000200L +#define OTG3_OTG_DOUBLE_BUFFER_CONTROL__OTG_DRR_TIMING_DBUF_UPDATE_MODE_MASK 0x03000000L +//OTG3_OTG_MASTER_EN +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN__SHIFT 0x0 +#define OTG3_OTG_MASTER_EN__OTG_MASTER_EN_MASK 0x00000001L +//OTG3_OTG_VERTICAL_INTERRUPT0_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_START_MASK 0x00007FFFL +#define OTG3_OTG_VERTICAL_INTERRUPT0_POSITION__OTG_VERTICAL_INTERRUPT0_LINE_END_MASK 0x7FFF0000L +//OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY__SHIFT 0x4 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS__SHIFT 0x1c +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_MASK 0x00000010L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VERTICAL_INTERRUPT0_INT_TYPE_MASK 0x01000000L +#define OTG3_OTG_VERTICAL_INTERRUPT0_CONTROL__OTG_VINTE_STATUS_MASK 0x10000000L +//OTG3_OTG_VERTICAL_INTERRUPT1_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT1_POSITION__OTG_VERTICAL_INTERRUPT1_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT1_CONTROL__OTG_VERTICAL_INTERRUPT1_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_VERTICAL_INTERRUPT2_POSITION +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START__SHIFT 0x0 +#define OTG3_OTG_VERTICAL_INTERRUPT2_POSITION__OTG_VERTICAL_INTERRUPT2_LINE_START_MASK 0x00007FFFL +//OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE__SHIFT 0x8 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS__SHIFT 0xc +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS__SHIFT 0x10 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR__SHIFT 0x14 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE__SHIFT 0x18 +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_ENABLE_MASK 0x00000100L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_STATUS_MASK 0x00001000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_STATUS_MASK 0x00010000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_CLEAR_MASK 0x00100000L +#define OTG3_OTG_VERTICAL_INTERRUPT2_CONTROL__OTG_VERTICAL_INTERRUPT2_INT_TYPE_MASK 0x01000000L +//OTG3_OTG_CRC_CNTL +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN__SHIFT 0x0 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN__SHIFT 0x1 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_POLY_SEL__SHIFT 0x2 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY__SHIFT 0x3 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN__SHIFT 0x4 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL__SHIFT 0x5 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN__SHIFT 0x7 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE__SHIFT 0x8 +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE__SHIFT 0xa +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE__SHIFT 0xc +#define OTG3_OTG_CRC_CNTL__OTG_CRC_AES_EN__SHIFT 0xe +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x13 +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT__SHIFT 0x14 +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT__SHIFT 0x18 +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING__SHIFT 0x1c +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING__SHIFT 0x1d +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING__SHIFT 0x1e +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING__SHIFT 0x1f +#define OTG3_OTG_CRC_CNTL__OTG_CRC_EN_MASK 0x00000001L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_WINDOW_DB_EN_MASK 0x00000002L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_POLY_SEL_MASK 0x00000004L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_BLANK_ONLY_MASK 0x00000008L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_EN_MASK 0x00000010L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CAPTURE_START_SEL_MASK 0x00000060L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_EN_MASK 0x00000080L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_STEREO_MODE_MASK 0x00000300L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_CONT_MODE_MASK 0x00000400L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_INTERLACE_MODE_MASK 0x00003000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_AES_EN_MASK 0x00004000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00080000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC0_SELECT_MASK 0x00700000L +#define OTG3_OTG_CRC_CNTL__OTG_CRC1_SELECT_MASK 0x07000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC0_PENDING_MASK 0x10000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC1_PENDING_MASK 0x20000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC2_PENDING_MASK 0x40000000L +#define OTG3_OTG_CRC_CNTL__OTG_ONE_SHOT_CRC3_PENDING_MASK 0x80000000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL__OTG_CRC0_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL__OTG_CRC0_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL__OTG_CRC0_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL__OTG_CRC0_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_DATA_R +#define OTG3_OTG_CRC0_DATA_R__CRC0_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_R__CRC0_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_G +#define OTG3_OTG_CRC0_DATA_G__CRC0_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_G__CRC0_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_B +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_B__CRC0_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_C +#define OTG3_OTG_CRC0_DATA_C__CRC0_C__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_C__CRC0_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL__OTG_CRC1_WINDOWA_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL__OTG_CRC1_WINDOWA_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL__OTG_CRC1_WINDOWB_X_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_START_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL__OTG_CRC1_WINDOWB_Y_END_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_DATA_R +#define OTG3_OTG_CRC1_DATA_R__CRC1_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_R__CRC1_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_DATA_G +#define OTG3_OTG_CRC1_DATA_G__CRC1_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_G__CRC1_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_DATA_B +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_B__CRC1_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC1_DATA_C +#define OTG3_OTG_CRC1_DATA_C__CRC1_C__SHIFT 0x0 +#define OTG3_OTG_CRC1_DATA_C__CRC1_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_R +#define OTG3_OTG_CRC2_DATA_R__CRC2_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_R__CRC2_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_G +#define OTG3_OTG_CRC2_DATA_G__CRC2_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_G__CRC2_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_B +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_B__CRC2_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC2_DATA_C +#define OTG3_OTG_CRC2_DATA_C__CRC2_C__SHIFT 0x0 +#define OTG3_OTG_CRC2_DATA_C__CRC2_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_R +#define OTG3_OTG_CRC3_DATA_R__CRC3_R_CR__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_R__CRC3_R_CR_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_G +#define OTG3_OTG_CRC3_DATA_G__CRC3_G_Y__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_G__CRC3_G_Y_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_B +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_B__CRC3_B_CB_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC3_DATA_C +#define OTG3_OTG_CRC3_DATA_C__CRC3_C__SHIFT 0x0 +#define OTG3_OTG_CRC3_DATA_C__CRC3_C_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC0_DATA_AES +#define OTG3_OTG_CRC0_DATA_AES__CRC0_AES__SHIFT 0x0 +#define OTG3_OTG_CRC0_DATA_AES__CRC0_AES_MASK 0xFFFFFFFFL +//OTG3_OTG_CRC_SIG_RED_GREEN_MASK +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_RED_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_RED_GREEN_MASK__OTG_CRC_SIG_GREEN_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK__SHIFT 0x0 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK__SHIFT 0x10 +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_BLUE_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK__OTG_CRC_SIG_CONTROL_MASK_MASK 0xFFFF0000L +//OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_X_CONTROL_READBACK__OTG_CRC0_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWA_Y_CONTROL_READBACK__OTG_CRC0_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_X_CONTROL_READBACK__OTG_CRC0_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC0_WINDOWB_Y_CONTROL_READBACK__OTG_CRC0_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_X_CONTROL_READBACK__OTG_CRC1_WINDOWA_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWA_Y_CONTROL_READBACK__OTG_CRC1_WINDOWA_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_X_CONTROL_READBACK__OTG_CRC1_WINDOWB_X_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK__SHIFT 0x0 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK__SHIFT 0x10 +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_START_READBACK_MASK 0x00007FFFL +#define OTG3_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK__OTG_CRC1_WINDOWB_Y_END_READBACK_MASK 0x7FFF0000L +//OTG3_OTG_STATIC_SCREEN_CONTROL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK__SHIFT 0x0 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT__SHIFT 0x10 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE__SHIFT 0x18 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS__SHIFT 0x19 +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS__SHIFT 0x1a +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR__SHIFT 0x1b +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE__SHIFT 0x1c +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE__SHIFT 0x1e +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE__SHIFT 0x1f +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_EVENT_MASK_MASK 0x0000FFFFL +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_FRAME_COUNT_MASK 0x00FF0000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_ENABLE_MASK 0x01000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_SS_STATUS_MASK 0x02000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_STATUS_MASK 0x04000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_CLEAR_MASK 0x08000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_CPU_SS_INT_TYPE_MASK 0x10000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_MASK 0x40000000L +#define OTG3_OTG_STATIC_SCREEN_CONTROL__OTG_STATIC_SCREEN_OVERRIDE_VALUE_MASK 0x80000000L +//OTG3_OTG_3D_STRUCTURE_CONTROL +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN__SHIFT 0x0 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x8 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0xc +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x10 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x11 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT__SHIFT 0x12 +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_EN_MASK 0x00000001L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L +#define OTG3_OTG_3D_STRUCTURE_CONTROL__OTG_3D_STRUCTURE_F_COUNT_MASK 0x000C0000L +//OTG3_OTG_GSL_VSYNC_GAP +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT__SHIFT 0x0 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x10 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE__SHIFT 0x11 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR__SHIFT 0x13 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x17 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP__SHIFT 0x18 +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_LIMIT_MASK 0x000000FFL +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_DELAY_MASK 0x0000FF00L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MODE_MASK 0x00060000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L +#define OTG3_OTG_GSL_VSYNC_GAP__OTG_GSL_VSYNC_GAP_MASK 0xFF000000L +//OTG3_OTG_MASTER_UPDATE_MODE +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00000003L +//OTG3_OTG_CLOCK_CONTROL +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN__SHIFT 0x0 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS__SHIFT 0x1 +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET__SHIFT 0x4 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON__SHIFT 0x8 +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY__SHIFT 0x10 +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_EN_MASK 0x00000001L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_GATE_DIS_MASK 0x00000002L +#define OTG3_OTG_CLOCK_CONTROL__OTG_SOFT_RESET_MASK 0x00000010L +#define OTG3_OTG_CLOCK_CONTROL__OTG_CLOCK_ON_MASK 0x00000100L +#define OTG3_OTG_CLOCK_CONTROL__OTG_BUSY_MASK 0x00010000L +//OTG3_OTG_VSTARTUP_PARAM +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START__SHIFT 0x0 +#define OTG3_OTG_VSTARTUP_PARAM__VSTARTUP_START_MASK 0x000003FFL +//OTG3_OTG_VUPDATE_PARAM +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_PARAM__VUPDATE_WIDTH_MASK 0x03FF0000L +//OTG3_OTG_VREADY_PARAM +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VREADY_PARAM__VREADY_OFFSET_MASK 0x0000FFFFL +//OTG3_OTG_GLOBAL_SYNC_STATUS +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE__SHIFT 0x1 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED__SHIFT 0x2 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS__SHIFT 0x3 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN__SHIFT 0x5 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE__SHIFT 0x6 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL__SHIFT 0x7 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED__SHIFT 0x8 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS__SHIFT 0x9 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR__SHIFT 0xa +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS__SHIFT 0xb +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN__SHIFT 0xc +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED__SHIFT 0xe +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS__SHIFT 0xf +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS__SHIFT 0x11 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN__SHIFT 0x12 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE__SHIFT 0x13 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS__SHIFT 0x15 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR__SHIFT 0x16 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS__SHIFT 0x18 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_EN_MASK 0x00000001L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_TYPE_MASK 0x00000002L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_OCCURRED_MASK 0x00000004L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_INT_STATUS_MASK 0x00000008L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VSTARTUP_EVENT_CLEAR_MASK 0x00000010L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_EN_MASK 0x00000020L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_TYPE_MASK 0x00000040L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_POSITION_SEL_MASK 0x00000080L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_OCCURRED_MASK 0x00000100L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_INT_STATUS_MASK 0x00000200L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_EVENT_CLEAR_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_STATUS_MASK 0x00000800L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_EN_MASK 0x00001000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_OCCURRED_MASK 0x00004000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_INT_STATUS_MASK 0x00008000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_EVENT_CLEAR_MASK 0x00010000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VUPDATE_NO_LOCK_STATUS_MASK 0x00020000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_EN_MASK 0x00040000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_TYPE_MASK 0x00080000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_OCCURRED_MASK 0x00100000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_INT_STATUS_MASK 0x00200000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__VREADY_EVENT_CLEAR_MASK 0x00400000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__STEREO_SELECT_STATUS_MASK 0x01000000L +#define OTG3_OTG_GLOBAL_SYNC_STATUS__FIELD_NUMBER_STATUS_MASK 0x02000000L +//OTG3_OTG_MASTER_UPDATE_LOCK +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK__SHIFT 0x0 +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS__SHIFT 0x8 +#define OTG3_OTG_MASTER_UPDATE_LOCK__OTG_MASTER_UPDATE_LOCK_MASK 0x00000001L +#define OTG3_OTG_MASTER_UPDATE_LOCK__UPDATE_LOCK_STATUS_MASK 0x00000100L +//OTG3_OTG_GSL_CONTROL +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN__SHIFT 0x0 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN__SHIFT 0x1 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN__SHIFT 0x2 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN__SHIFT 0x3 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE__SHIFT 0x4 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY__SHIFT 0x8 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY__SHIFT 0x10 +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS__SHIFT 0x1c +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN__SHIFT 0x1f +#define OTG3_OTG_GSL_CONTROL__OTG_GSL0_EN_MASK 0x00000001L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL1_EN_MASK 0x00000002L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL2_EN_MASK 0x00000004L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_EN_MASK 0x00000008L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_MASTER_MODE_MASK 0x00000030L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_DELAY_MASK 0x00000F00L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_FORCE_DELAY_MASK 0x001F0000L +#define OTG3_OTG_GSL_CONTROL__OTG_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L +#define OTG3_OTG_GSL_CONTROL__OTG_MASTER_UPDATE_LOCK_GSL_EN_MASK 0x80000000L +//OTG3_OTG_GSL_WINDOW_X +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_X__OTG_GSL_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_GSL_WINDOW_Y +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y__SHIFT 0x0 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y__SHIFT 0x10 +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GSL_WINDOW_Y__OTG_GSL_WINDOW_END_Y_MASK 0x7FFF0000L +//OTG3_OTG_VUPDATE_KEEPOUT +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET__SHIFT 0x0 +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET__SHIFT 0x10 +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN__SHIFT 0x1f +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET_MASK 0x0000FFFFL +#define OTG3_OTG_VUPDATE_KEEPOUT__MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET_MASK 0x03FF0000L +#define OTG3_OTG_VUPDATE_KEEPOUT__OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_START_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_END_X_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL0__MASTER_UPDATE_LOCK_DB_EN_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL1 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_START_Y_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_DB_END_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL1__MASTER_UPDATE_LOCK_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL2 +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN__SHIFT 0xa +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL__SHIFT 0x19 +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE__SHIFT 0x1e +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL2__GLOBAL_UPDATE_LOCK_EN_MASK 0x00000400L +#define OTG3_OTG_GLOBAL_CONTROL2__MANUAL_FLOW_CONTROL_SEL_MASK 0x00070000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_MASTER_UPDATE_LOCK_SEL_MASK 0x0E000000L +#define OTG3_OTG_GLOBAL_CONTROL2__OTG_VUPDATE_BLOCK_DISABLE_MASK 0x40000000L +#define OTG3_OTG_GLOBAL_CONTROL2__DCCG_VUPDATE_MODE_MASK 0x80000000L +//OTG3_OTG_GLOBAL_CONTROL3 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL__SHIFT 0x4 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL__SHIFT 0x14 +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_FIELD_MASK 0x00000003L +#define OTG3_OTG_GLOBAL_CONTROL3__MASTER_UPDATE_LOCK_DB_STEREO_SEL_MASK 0x00000030L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_FIELD_SEL_MASK 0x00030000L +#define OTG3_OTG_GLOBAL_CONTROL3__DIG_UPDATE_EYE_SEL_MASK 0x00300000L +//OTG3_OTG_GLOBAL_CONTROL4 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X__SHIFT 0x0 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y__SHIFT 0x10 +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE__SHIFT 0x1f +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_X_MASK 0x00007FFFL +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_POSITION_Y_MASK 0x7FFF0000L +#define OTG3_OTG_GLOBAL_CONTROL4__DIG_UPDATE_VCOUNT_MODE_MASK 0x80000000L +//OTG3_OTG_TRIG_MANUAL_CONTROL +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL__SHIFT 0x0 +#define OTG3_OTG_TRIG_MANUAL_CONTROL__TRIG_MANUAL_CONTROL_MASK 0x00000001L +//OTG3_OTG_DRR_TIMING_INT_STATUS +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED__SHIFT 0x0 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT__SHIFT 0x4 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR__SHIFT 0x8 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK__SHIFT 0xc +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE__SHIFT 0xd +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED__SHIFT 0x10 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT__SHIFT 0x14 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR__SHIFT 0x18 +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK__SHIFT 0x1c +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE__SHIFT 0x1d +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_MASK 0x00000001L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MASK 0x00000010L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_CLEAR_MASK 0x00000100L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_MSK_MASK 0x00001000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_TIMING_UPDATE_OCCURRED_INT_TYPE_MASK 0x00002000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_MASK 0x00010000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MASK 0x00100000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_CLEAR_MASK 0x01000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_MSK_MASK 0x10000000L +#define OTG3_OTG_DRR_TIMING_INT_STATUS__OTG_DRR_V_TOTAL_REACH_OCCURRED_INT_TYPE_MASK 0x20000000L +//OTG3_OTG_DRR_V_TOTAL_REACH_RANGE +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE__SHIFT 0x10 +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_LOWER_RANGE_MASK 0x00007FFFL +#define OTG3_OTG_DRR_V_TOTAL_REACH_RANGE__OTG_DRR_V_TOTAL_REACH_UPPER_RANGE_MASK 0x7FFF0000L +//OTG3_OTG_DRR_V_TOTAL_CHANGE +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT__SHIFT 0x0 +#define OTG3_OTG_DRR_V_TOTAL_CHANGE__OTG_DRR_V_TOTAL_CHANGE_LIMIT_MASK 0x00007FFFL +//OTG3_OTG_DRR_TRIGGER_WINDOW +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X__SHIFT 0x0 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X__SHIFT 0x10 +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_START_X_MASK 0x00007FFFL +#define OTG3_OTG_DRR_TRIGGER_WINDOW__OTG_DRR_TRIGGER_WINDOW_END_X_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTROL +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR__SHIFT 0x10 +#define OTG3_OTG_DRR_CONTROL__OTG_DRR_AVERAGE_FRAME_MASK 0x00000003L +#define OTG3_OTG_DRR_CONTROL__OTG_V_TOTAL_LAST_USED_BY_DRR_MASK 0x7FFF0000L +//OTG3_OTG_DRR_CONTOL2 +#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR__SHIFT 0x0 +#define OTG3_OTG_DRR_CONTOL2__OTG_VCOUNT2_LAST_USED_BY_DRR_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO0__OTG_M_CONST_DTO_PHASE_MASK 0xFFFFFFFFL +//OTG3_OTG_M_CONST_DTO1 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO__SHIFT 0x0 +#define OTG3_OTG_M_CONST_DTO1__OTG_M_CONST_DTO_MODULO_MASK 0xFFFFFFFFL +//OTG3_OTG_REQUEST_CONTROL +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE__SHIFT 0x0 +#define OTG3_OTG_REQUEST_CONTROL__OTG_REQUEST_MODE_FOR_H_DUPLICATE_MASK 0x00000001L +//OTG3_OTG_PIPE_UPDATE_STATUS +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING__SHIFT 0x0 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING__SHIFT 0x4 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING__SHIFT 0x8 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS__SHIFT 0x10 +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_FLIP_PENDING_MASK 0x00000001L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_DC_REG_UPDATE_PENDING_MASK 0x00000010L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_CURSOR_UPDATE_PENDING_MASK 0x00000100L +#define OTG3_OTG_PIPE_UPDATE_STATUS__OTG_VUPDATE_KEEPOUT_STATUS_MASK 0x00010000L +//OTG3_OTG_PSTATE_REGISTER +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START__SHIFT 0x0 +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND__SHIFT 0x10 +#define OTG3_OTG_PSTATE_REGISTER__OTG_UNBLANK__SHIFT 0x14 +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN__SHIFT 0x18 +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_KEEPOUT_START_MASK 0x00007FFFL +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_EXTEND_MASK 0x00010000L +#define OTG3_OTG_PSTATE_REGISTER__OTG_UNBLANK_MASK 0x00100000L +#define OTG3_OTG_PSTATE_REGISTER__OTG_PSTATE_ALLOW_WIDTH_MIN_MASK 0xFF000000L +//OTG3_OTG_ENCRYPTION +#define OTG3_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL__SHIFT 0x0 +#define OTG3_OTG_ENCRYPTION__OTG_ENCRYPTION_REQUIRED_LEVEL_MASK 0x00000003L +//OTG3_OTG_SPARE_REGISTER +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG__SHIFT 0x0 +#define OTG3_OTG_SPARE_REGISTER__OTG_SPARE_REG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_optc_optc_misc_dispdec +//GSL_SOURCE_SELECT +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL__SHIFT 0x0 +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL__SHIFT 0x4 +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL__SHIFT 0x8 +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL__SHIFT 0x10 +#define GSL_SOURCE_SELECT__GSL0_READY_SOURCE_SEL_MASK 0x00000007L +#define GSL_SOURCE_SELECT__GSL1_READY_SOURCE_SEL_MASK 0x00000070L +#define GSL_SOURCE_SELECT__GSL2_READY_SOURCE_SEL_MASK 0x00000700L +#define GSL_SOURCE_SELECT__GSL_TIMING_SYNC_SEL_MASK 0x00070000L +//OPTC_DLPC_CONTROL +#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX__SHIFT 0x0 +#define OPTC_DLPC_CONTROL__OPTC_DLPC_SNAPSHOT_MUX_MASK 0x00000007L +//OPTC_CLOCK_CONTROL +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON__SHIFT 0x1 +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL__SHIFT 0x8 +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS__SHIFT 0xf +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define OPTC_CLOCK_CONTROL__OPTC_DISPCLK_R_CLOCK_ON_MASK 0x00000002L +#define OPTC_CLOCK_CONTROL__OPTC_TEST_CLK_SEL_MASK 0x00000F00L +#define OPTC_CLOCK_CONTROL__OPTC_FGCG_REP_DIS_MASK 0x00008000L +//ODM_MEM_PWR_CTRL +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE__SHIFT 0x4 +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS__SHIFT 0x6 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE__SHIFT 0x8 +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS__SHIFT 0xa +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE__SHIFT 0xc +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS__SHIFT 0xe +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE__SHIFT 0x10 +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS__SHIFT 0x12 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE__SHIFT 0x14 +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS__SHIFT 0x16 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE__SHIFT 0x18 +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS__SHIFT 0x1a +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE__SHIFT 0x1c +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS__SHIFT 0x1e +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_FORCE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL__ODM_MEM0_PWR_DIS_MASK 0x00000004L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_FORCE_MASK 0x00000030L +#define ODM_MEM_PWR_CTRL__ODM_MEM1_PWR_DIS_MASK 0x00000040L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_FORCE_MASK 0x00000300L +#define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK 0x00000400L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_FORCE_MASK 0x00003000L +#define ODM_MEM_PWR_CTRL__ODM_MEM3_PWR_DIS_MASK 0x00004000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_FORCE_MASK 0x00030000L +#define ODM_MEM_PWR_CTRL__ODM_MEM4_PWR_DIS_MASK 0x00040000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_FORCE_MASK 0x00300000L +#define ODM_MEM_PWR_CTRL__ODM_MEM5_PWR_DIS_MASK 0x00400000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_FORCE_MASK 0x03000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM6_PWR_DIS_MASK 0x04000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_FORCE_MASK 0x30000000L +#define ODM_MEM_PWR_CTRL__ODM_MEM7_PWR_DIS_MASK 0x40000000L +//ODM_MEM_PWR_CTRL3 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE__SHIFT 0x0 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE__SHIFT 0x2 +#define ODM_MEM_PWR_CTRL3__ODM_MEM_UNASSIGNED_PWR_MODE_MASK 0x00000003L +#define ODM_MEM_PWR_CTRL3__ODM_MEM_VBLANK_PWR_MODE_MASK 0x0000000CL +//ODM_MEM_PWR_STATUS +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE__SHIFT 0x0 +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE__SHIFT 0x2 +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE__SHIFT 0x4 +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE__SHIFT 0x6 +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE__SHIFT 0x8 +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE__SHIFT 0xa +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE__SHIFT 0xc +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE__SHIFT 0xe +#define ODM_MEM_PWR_STATUS__ODM_MEM0_PWR_STATE_MASK 0x00000003L +#define ODM_MEM_PWR_STATUS__ODM_MEM1_PWR_STATE_MASK 0x0000000CL +#define ODM_MEM_PWR_STATUS__ODM_MEM2_PWR_STATE_MASK 0x00000030L +#define ODM_MEM_PWR_STATUS__ODM_MEM3_PWR_STATE_MASK 0x000000C0L +#define ODM_MEM_PWR_STATUS__ODM_MEM4_PWR_STATE_MASK 0x00000300L +#define ODM_MEM_PWR_STATUS__ODM_MEM5_PWR_STATE_MASK 0x00000C00L +#define ODM_MEM_PWR_STATUS__ODM_MEM6_PWR_STATE_MASK 0x00003000L +#define ODM_MEM_PWR_STATUS__ODM_MEM7_PWR_STATE_MASK 0x0000C000L +//OPTC_MISC_SPARE_REGISTER +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG__SHIFT 0x0 +#define OPTC_MISC_SPARE_REGISTER__OPTC_MISC_SPARE_REG_MASK 0x000000FFL + + +// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON15_PERFCOUNTER_CNTL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_CNTL2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON15_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFCOUNTER_STATE +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON15_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON15_PERFMON_CNTL +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON15_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON15_PERFMON_CNTL2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON15_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON15_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON15_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON15_PERFMON_CVALUE_LOW +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON15_PERFMON_HI +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON15_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON15_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON15_PERFMON_LOW +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON15_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dout_i2c_dispdec +//DC_I2C_CONTROL +#define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x0 +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x1 +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x2 +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x3 +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x8 +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x14 +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x1f +#define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L +#define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L +#define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L +#define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L +#define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L +#define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L +#define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L +//DC_I2C_ARBITRATION +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x0 +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x2 +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x4 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x8 +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0xc +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x14 +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x15 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x18 +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x19 +#define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L +#define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000CL +#define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L +#define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L +#define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L +#define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L +//DC_I2C_INTERRUPT_CONTROL +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x0 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x1 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x2 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x4 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x5 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x6 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x8 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x9 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0xa +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0xc +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0xd +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0xe +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x10 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x11 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x12 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x14 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x15 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x16 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x18 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x19 +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x1a +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x1b +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x1c +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x1d +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L +#define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L +//DC_I2C_SW_STATUS +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x0 +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x2 +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x4 +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x5 +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x6 +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x7 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x8 +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0xc +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0xd +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0xe +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0xf +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x12 +#define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L +#define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L +#define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L +#define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L +#define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L +#define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L +#define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L +#define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L +//DC_I2C_DDC1_HW_STATUS +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC2_HW_STATUS +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC3_HW_STATUS +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC4_HW_STATUS +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC5_HW_STATUS +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x0 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x3 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x10 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x11 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x14 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x18 +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x1c +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0F000000L +#define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L +//DC_I2C_DDC1_SPEED +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC1_SETUP +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC2_SPEED +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC2_SETUP +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC3_SPEED +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC3_SETUP +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC4_SPEED +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC4_SETUP +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_DDC5_SPEED +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x0 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x4 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL__SHIFT 0x8 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x10 +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_START_STOP_TIMING_CNTL_MASK 0x00000300L +#define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xFFFF0000L +//DC_I2C_DDC5_SETUP +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x0 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x1 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH__SHIFT 0x2 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN__SHIFT 0x3 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x4 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x5 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x6 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x7 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x8 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x10 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x18 +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_SEND_RESET_LENGTH_MASK 0x00000004L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_EN_MASK 0x00000008L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000FF00L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00FF0000L +#define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xFF000000L +//DC_I2C_TRANSACTION0 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x0 +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x8 +#define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0xc +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0xd +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x10 +#define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L +#define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L +#define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L +#define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x03FF0000L +//DC_I2C_TRANSACTION1 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x0 +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x8 +#define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0xc +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0xd +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x10 +#define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L +#define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L +#define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L +#define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x03FF0000L +//DC_I2C_TRANSACTION2 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x0 +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x8 +#define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0xc +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0xd +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x10 +#define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L +#define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L +#define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L +#define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x03FF0000L +//DC_I2C_TRANSACTION3 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x0 +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x8 +#define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0xc +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0xd +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x10 +#define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L +#define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L +#define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L +#define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x03FF0000L +//DC_I2C_DATA +#define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x0 +#define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x8 +#define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x10 +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x1f +#define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L +#define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000FF00L +#define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x03FF0000L +#define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L +//DC_I2C_EDID_DETECT_CTRL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x0 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x14 +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x1c +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000FFFFL +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00F00000L +#define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L +//DC_I2C_READ_REQUEST_INTERRUPT +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED__SHIFT 0x0 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT__SHIFT 0x1 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK__SHIFT 0x2 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK__SHIFT 0x3 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED__SHIFT 0x4 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT__SHIFT 0x5 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK__SHIFT 0x6 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK__SHIFT 0x7 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED__SHIFT 0x8 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT__SHIFT 0x9 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK__SHIFT 0xa +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK__SHIFT 0xb +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED__SHIFT 0xc +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT__SHIFT 0xd +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK__SHIFT 0xe +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK__SHIFT 0xf +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED__SHIFT 0x10 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT__SHIFT 0x11 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK__SHIFT 0x12 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK__SHIFT 0x13 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED__SHIFT 0x14 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT__SHIFT 0x15 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK__SHIFT 0x16 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK__SHIFT 0x17 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED__SHIFT 0x18 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT__SHIFT 0x19 +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK__SHIFT 0x1a +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK__SHIFT 0x1b +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE__SHIFT 0x1e +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE__SHIFT 0x1f +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_OCCURRED_MASK 0x00000001L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_INT_MASK 0x00000002L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_ACK_MASK 0x00000004L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC1_READ_REQUEST_MASK_MASK 0x00000008L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_OCCURRED_MASK 0x00000010L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_INT_MASK 0x00000020L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_ACK_MASK 0x00000040L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC2_READ_REQUEST_MASK_MASK 0x00000080L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_OCCURRED_MASK 0x00000100L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_INT_MASK 0x00000200L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_ACK_MASK 0x00000400L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC3_READ_REQUEST_MASK_MASK 0x00000800L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_OCCURRED_MASK 0x00001000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_INT_MASK 0x00002000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_ACK_MASK 0x00004000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC4_READ_REQUEST_MASK_MASK 0x00008000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_OCCURRED_MASK 0x00010000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_INT_MASK 0x00020000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_ACK_MASK 0x00040000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC5_READ_REQUEST_MASK_MASK 0x00080000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_OCCURRED_MASK 0x00100000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_INT_MASK 0x00200000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_ACK_MASK 0x00400000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC6_READ_REQUEST_MASK_MASK 0x00800000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_OCCURRED_MASK 0x01000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_INT_MASK 0x02000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_ACK_MASK 0x04000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDCVGA_READ_REQUEST_MASK_MASK 0x08000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_ACK_ENABLE_MASK 0x40000000L +#define DC_I2C_READ_REQUEST_INTERRUPT__DC_I2C_DDC_READ_REQUEST_INT_TYPE_MASK 0x80000000L + + +// addressBlock: dce_dc_dio_dio_misc_dispdec +//DIO_SCRATCH0 +#define DIO_SCRATCH0__DIO_SCRATCH0__SHIFT 0x0 +#define DIO_SCRATCH0__DIO_SCRATCH0_MASK 0xFFFFFFFFL +//DIO_SCRATCH1 +#define DIO_SCRATCH1__DIO_SCRATCH1__SHIFT 0x0 +#define DIO_SCRATCH1__DIO_SCRATCH1_MASK 0xFFFFFFFFL +//DIO_SCRATCH2 +#define DIO_SCRATCH2__DIO_SCRATCH2__SHIFT 0x0 +#define DIO_SCRATCH2__DIO_SCRATCH2_MASK 0xFFFFFFFFL +//DIO_SCRATCH3 +#define DIO_SCRATCH3__DIO_SCRATCH3__SHIFT 0x0 +#define DIO_SCRATCH3__DIO_SCRATCH3_MASK 0xFFFFFFFFL +//DIO_SCRATCH4 +#define DIO_SCRATCH4__DIO_SCRATCH4__SHIFT 0x0 +#define DIO_SCRATCH4__DIO_SCRATCH4_MASK 0xFFFFFFFFL +//DIO_SCRATCH5 +#define DIO_SCRATCH5__DIO_SCRATCH5__SHIFT 0x0 +#define DIO_SCRATCH5__DIO_SCRATCH5_MASK 0xFFFFFFFFL +//DIO_SCRATCH6 +#define DIO_SCRATCH6__DIO_SCRATCH6__SHIFT 0x0 +#define DIO_SCRATCH6__DIO_SCRATCH6_MASK 0xFFFFFFFFL +//DIO_SCRATCH7 +#define DIO_SCRATCH7__DIO_SCRATCH7__SHIFT 0x0 +#define DIO_SCRATCH7__DIO_SCRATCH7_MASK 0xFFFFFFFFL +//DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x1 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x3 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x4 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x5 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x6 +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGA_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGB_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000002L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGC_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGD_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000008L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGE_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000010L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGF_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000020L +#define DIO_DP_ALPM_WAKEUP_INTERRUPT_STATUS__DIGG_DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000040L +//DIO_MEM_PWR_STATUS +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE__SHIFT 0x0 +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE__SHIFT 0x3 +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE__SHIFT 0x4 +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE__SHIFT 0x5 +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE__SHIFT 0x6 +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE__SHIFT 0x7 +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE__SHIFT 0x8 +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE__SHIFT 0x9 +#define DIO_MEM_PWR_STATUS__I2C_MEM_PWR_STATE_MASK 0x00000001L +#define DIO_MEM_PWR_STATUS__DPA_MEM_PWR_STATE_MASK 0x00000008L +#define DIO_MEM_PWR_STATUS__DPB_MEM_PWR_STATE_MASK 0x00000010L +#define DIO_MEM_PWR_STATUS__DPC_MEM_PWR_STATE_MASK 0x00000020L +#define DIO_MEM_PWR_STATUS__DPD_MEM_PWR_STATE_MASK 0x00000040L +#define DIO_MEM_PWR_STATUS__DPE_MEM_PWR_STATE_MASK 0x00000080L +#define DIO_MEM_PWR_STATUS__DPF_MEM_PWR_STATE_MASK 0x00000100L +#define DIO_MEM_PWR_STATUS__DPG_MEM_PWR_STATE_MASK 0x00000200L +//DIO_MEM_PWR_CTRL +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x0 +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS__SHIFT 0x1 +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS__SHIFT 0x4 +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS__SHIFT 0x5 +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS__SHIFT 0x6 +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS__SHIFT 0x7 +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS__SHIFT 0x8 +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS__SHIFT 0x9 +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS__SHIFT 0xa +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000001L +#define DIO_MEM_PWR_CTRL__I2C_LIGHT_SLEEP_DIS_MASK 0x00000002L +#define DIO_MEM_PWR_CTRL__DPA_LIGHT_SLEEP_DIS_MASK 0x00000010L +#define DIO_MEM_PWR_CTRL__DPB_LIGHT_SLEEP_DIS_MASK 0x00000020L +#define DIO_MEM_PWR_CTRL__DPC_LIGHT_SLEEP_DIS_MASK 0x00000040L +#define DIO_MEM_PWR_CTRL__DPD_LIGHT_SLEEP_DIS_MASK 0x00000080L +#define DIO_MEM_PWR_CTRL__DPE_LIGHT_SLEEP_DIS_MASK 0x00000100L +#define DIO_MEM_PWR_CTRL__DPF_LIGHT_SLEEP_DIS_MASK 0x00000200L +#define DIO_MEM_PWR_CTRL__DPG_LIGHT_SLEEP_DIS_MASK 0x00000400L +//DIO_MEM_PWR_CTRL2 +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE__SHIFT 0x18 +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE__SHIFT 0x19 +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE__SHIFT 0x1a +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE__SHIFT 0x1b +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE__SHIFT 0x1c +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE__SHIFT 0x1d +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE__SHIFT 0x1e +#define DIO_MEM_PWR_CTRL2__DPA_LIGHT_SLEEP_FORCE_MASK 0x01000000L +#define DIO_MEM_PWR_CTRL2__DPB_LIGHT_SLEEP_FORCE_MASK 0x02000000L +#define DIO_MEM_PWR_CTRL2__DPC_LIGHT_SLEEP_FORCE_MASK 0x04000000L +#define DIO_MEM_PWR_CTRL2__DPD_LIGHT_SLEEP_FORCE_MASK 0x08000000L +#define DIO_MEM_PWR_CTRL2__DPE_LIGHT_SLEEP_FORCE_MASK 0x10000000L +#define DIO_MEM_PWR_CTRL2__DPF_LIGHT_SLEEP_FORCE_MASK 0x20000000L +#define DIO_MEM_PWR_CTRL2__DPG_LIGHT_SLEEP_FORCE_MASK 0x40000000L +//DIO_CLK_CNTL +#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL__SHIFT 0x0 +#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS__SHIFT 0x9 +#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS__SHIFT 0xa +#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS__SHIFT 0xb +#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS__SHIFT 0xc +#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS__SHIFT 0xd +#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS__SHIFT 0xe +#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS__SHIFT 0xf +#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS__SHIFT 0x10 +#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS__SHIFT 0x11 +#define DIO_CLK_CNTL__DPREFCLK_R_GATE_DIS__SHIFT 0x12 +#define DIO_CLK_CNTL__DPREFCLK_G_GATE_DIS__SHIFT 0x13 +#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS__SHIFT 0x14 +#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS__SHIFT 0x15 +#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS__SHIFT 0x16 +#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS__SHIFT 0x17 +#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS__SHIFT 0x18 +#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS__SHIFT 0x19 +#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS__SHIFT 0x1a +#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS__SHIFT 0x1b +#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS__SHIFT 0x1c +#define DIO_CLK_CNTL__SOCCLK_R_GATE_DIS__SHIFT 0x1d +#define DIO_CLK_CNTL__DIO_TEST_CLK_SEL_MASK 0x0000007FL +#define DIO_CLK_CNTL__DISPCLK_R_GATE_DIS_MASK 0x00000200L +#define DIO_CLK_CNTL__DISPCLK_G_GATE_DIS_MASK 0x00000400L +#define DIO_CLK_CNTL__REFCLK_R_GATE_DIS_MASK 0x00000800L +#define DIO_CLK_CNTL__REFCLK_G_GATE_DIS_MASK 0x00001000L +#define DIO_CLK_CNTL__SOCCLK_G_GATE_DIS_MASK 0x00002000L +#define DIO_CLK_CNTL__SYMCLK_FE_R_GATE_DIS_MASK 0x00004000L +#define DIO_CLK_CNTL__SYMCLK_FE_G_GATE_DIS_MASK 0x00008000L +#define DIO_CLK_CNTL__SYMCLK_R_GATE_DIS_MASK 0x00010000L +#define DIO_CLK_CNTL__SYMCLK_G_GATE_DIS_MASK 0x00020000L +#define DIO_CLK_CNTL__DPREFCLK_R_GATE_DIS_MASK 0x00040000L +#define DIO_CLK_CNTL__DPREFCLK_G_GATE_DIS_MASK 0x00080000L +#define DIO_CLK_CNTL__DIO_FGCG_REP_DIS_MASK 0x00100000L +#define DIO_CLK_CNTL__DISPCLK_G_HDCP_GATE_DIS_MASK 0x00200000L +#define DIO_CLK_CNTL__SYMCLKA_G_HDCP_GATE_DIS_MASK 0x00400000L +#define DIO_CLK_CNTL__SYMCLKB_G_HDCP_GATE_DIS_MASK 0x00800000L +#define DIO_CLK_CNTL__SYMCLKC_G_HDCP_GATE_DIS_MASK 0x01000000L +#define DIO_CLK_CNTL__SYMCLKD_G_HDCP_GATE_DIS_MASK 0x02000000L +#define DIO_CLK_CNTL__SYMCLKE_G_HDCP_GATE_DIS_MASK 0x04000000L +#define DIO_CLK_CNTL__SYMCLKF_G_HDCP_GATE_DIS_MASK 0x08000000L +#define DIO_CLK_CNTL__SYMCLKG_G_HDCP_GATE_DIS_MASK 0x10000000L +#define DIO_CLK_CNTL__SOCCLK_R_GATE_DIS_MASK 0x20000000L +//DIO_POWER_MANAGEMENT_CNTL +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x0 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x8 +#define DIO_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L +#define DIO_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L +//DIO_HDMI_RXSTATUS_TIMER_CONTROL +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE__SHIFT 0x0 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE__SHIFT 0x4 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS__SHIFT 0x8 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK__SHIFT 0xc +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL__SHIFT 0x10 +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_ENABLE_MASK 0x00000001L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_TYPE_MASK 0x00000010L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_STATUS_MASK 0x00000100L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_MASK_MASK 0x00001000L +#define DIO_HDMI_RXSTATUS_TIMER_CONTROL__DIO_HDMI_RXSTATUS_TIMER_INTERVAL_MASK 0x0FFF0000L +//DIO_PSP_INTERRUPT_STATUS +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE__SHIFT 0x1 +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_STATUS_MASK 0x00000001L +#define DIO_PSP_INTERRUPT_STATUS__DIO_PSP_INTERRUPT_MESSAGE_MASK 0xFFFFFFFEL +//DIO_PSP_INTERRUPT_CLEAR +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR__SHIFT 0x0 +#define DIO_PSP_INTERRUPT_CLEAR__DIO_PSP_INTERRUPT_CLEAR_MASK 0x00000001L +//DIO_STATUS +#define DIO_STATUS__DIO_EN__SHIFT 0x0 +#define DIO_STATUS__DIO_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dig_stream_mapper_dispdec +//DIG0_STREAM_MAPPER_CONTROL +#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG0_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG1_STREAM_MAPPER_CONTROL +#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG1_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG2_STREAM_MAPPER_CONTROL +#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG2_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG3_STREAM_MAPPER_CONTROL +#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG3_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L +//DIG4_STREAM_MAPPER_CONTROL +#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET__SHIFT 0x0 +#define DIG4_STREAM_MAPPER_CONTROL__DIG_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON16_PERFCOUNTER_CNTL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_CNTL2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON16_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFCOUNTER_STATE +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON16_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON16_PERFMON_CNTL +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON16_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON16_PERFMON_CNTL2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON16_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON16_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON16_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON16_PERFMON_CVALUE_LOW +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON16_PERFMON_HI +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON16_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON16_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON16_PERFMON_LOW +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON16_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec +//VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG0_VPG_GENERIC_PACKET_DATA +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG0_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG0_VPG_GENERIC_STATUS +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG0_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG0_VPG_MEM_PWR +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG0_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG0_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG0_VPG_ISRC1_2_ACCESS_CTRL +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG0_VPG_ISRC1_2_DATA +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG0_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig0_apg_apg_dispdec +//APG0_APG_CONTROL +#define APG0_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG0_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG0_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG0_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG0_APG_CONTROL2 +#define APG0_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG0_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG0_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG0_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG0_APG_DBG_GEN_CONTROL +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG0_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG0_APG_PACKET_CONTROL +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG0_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG0_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG0_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG0_APG_DBG_ACP +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG0_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG0_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG0_APG_DBG_AUDIO_INFO +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG0_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG0_APG_DBG_60958_0 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG0_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG0_APG_DBG_60958_1 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG0_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG0_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG0_APG_DBG_60958_2 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG0_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG0_APG_AUDIO_CRC_CONTROL +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG0_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG0_APG_AUDIO_CRC_CONTROL2 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG0_APG_AUDIO_CRC_RESULT +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG0_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG0_APG_DBG_RAMP_CONTROL0 +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG0_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG0_APG_DBG_RAMP_CONTROL1 +#define APG0_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG0_APG_DBG_RAMP_CONTROL2 +#define APG0_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG0_APG_DBG_RAMP_CONTROL3 +#define APG0_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG0_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG0_APG_STATUS +#define APG0_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG0_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG0_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG0_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG0_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG0_APG_STATUS2 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG0_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG0_APG_DBG_AUDIO_DTO_CNTL +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG0_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG0_APG_MEM_PWR +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG0_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG0_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG0_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG0_APG_SPARE +#define APG0_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG0_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec +//DME0_DME_CONTROL +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME0_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME0_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME0_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME0_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME0_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME0_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME0_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME0_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME0_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME0_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME0_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME0_DME_MEMORY_CONTROL +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME0_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig0_dispdec +//DIG0_DIG_FE_CNTL +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG0_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG0_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG0_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG0_DIG_FE_CLK_CNTL +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG0_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG0_DIG_FE_EN_CNTL +#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG0_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG0_DIG_OUTPUT_CRC_CNTL +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG0_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG0_DIG_OUTPUT_CRC_RESULT +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG0_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG0_DIG_CLOCK_PATTERN +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG0_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG0_DIG_TEST_PATTERN +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG0_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG0_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG0_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG0_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG0_DIG_RANDOM_PATTERN_SEED +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG0_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG0_DIG_FIFO_CTRL0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG0_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG0_DIG_FIFO_CTRL1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG0_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG0_HDMI_METADATA_PACKET_CONTROL +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG0_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_CONTROL +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG0_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG0_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG0_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG0_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG0_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG0_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG0_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG0_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG0_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG0_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG0_HDMI_STATUS +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG0_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG0_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG0_HDMI_AUDIO_PACKET_CONTROL +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG0_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG0_HDMI_ACR_PACKET_CONTROL +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG0_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG0_HDMI_VBI_PACKET_CONTROL +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG0_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG0_HDMI_INFOFRAME_CONTROL0 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG0_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG0_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG0_HDMI_GC +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG0_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG0_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG0_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG0_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG0_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG0_HDMI_DB_CONTROL +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG0_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG0_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG0_HDMI_ACR_32_0 +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG0_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_32_1 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG0_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_44_0 +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG0_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_44_1 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG0_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_48_0 +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG0_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_48_1 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG0_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG0_HDMI_ACR_STATUS_0 +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG0_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG0_HDMI_ACR_STATUS_1 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG0_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG0_DIG_FE_AUDIO_CNTL +#define DIG0_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG0_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG0_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG0_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG0_DIG_BE_CLK_CNTL +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET__SHIFT 0x6 +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON__SHIFT 0xc +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG0_DIG_BE_CLK_CNTL__HDCP_SOFT_RESET_MASK 0x00000040L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_HDCP_CLOCK_ON_MASK 0x00001000L +#define DIG0_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG0_DIG_BE_CNTL +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG0_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG0_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG0_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG0_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG0_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG0_DIG_BE_EN_CNTL +#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG0_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG0_TMDS_CNTL +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG0_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG0_TMDS_CONTROL_CHAR +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG0_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG0_TMDS_CONTROL0_FEEDBACK +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG0_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG0_TMDS_STEREOSYNC_CTL_SEL +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG0_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG0_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG0_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG0_TMDS_CTL_BITS +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG0_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG0_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG0_TMDS_DCBALANCER_CONTROL +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG0_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG0_TMDS_SYNC_DCBALANCE_CHAR +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG0_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG0_TMDS_CTL0_1_GEN_CNTL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG0_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG0_TMDS_CTL2_3_GEN_CNTL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG0_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG0_DIG_VERSION +#define DIG0_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG0_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp0_dispdec +//DP0_DP_LINK_CNTL +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP0_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP0_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP0_DP_PIXEL_FORMAT +#define DP0_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP0_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP0_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP0_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP0_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP0_DP_MSA_COLORIMETRY +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP0_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP0_DP_CONFIG +#define DP0_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP0_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP0_DP_VID_STREAM_CNTL +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP0_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP0_DP_STEER_FIFO +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP0_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP0_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP0_DP_MSA_MISC +#define DP0_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP0_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP0_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP0_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP0_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP0_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP0_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP0_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP0_DP_DPHY_INTERNAL_CTRL +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP0_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP0_DP_VID_TIMING +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP0_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP0_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP0_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP0_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP0_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP0_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP0_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP0_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP0_DP_VID_N +#define DP0_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP0_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP0_DP_VID_M +#define DP0_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP0_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP0_DP_LINK_FRAMING_CNTL +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP0_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP0_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP0_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP0_DP_HBR2_EYE_PATTERN +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP0_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP0_DP_VID_MSA_VBID +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP0_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP0_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP0_DP_VID_INTERRUPT_CNTL +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP0_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP0_DP_DPHY_CNTL +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP0_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP0_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP0_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP0_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP0_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP0_DP_DPHY_TRAINING_PATTERN_SEL +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP0_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP0_DP_DPHY_SYM0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP0_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP0_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP0_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM1 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP0_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP0_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP0_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP0_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP0_DP_DPHY_SYM2 +#define DP0_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP0_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP0_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP0_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP0_DP_DPHY_8B10B_CNTL +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP0_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP0_DP_DPHY_PRBS_CNTL +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP0_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP0_DP_DPHY_SCRAM_CNTL +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP0_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP0_DP_DPHY_CRC_CONTROL0 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP0_DP_DPHY_CRC_CONTROL1 +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP0_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP0_DP_DPHY_CRC_RESULT0 +#define DP0_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_RESULT1 +#define DP0_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_RESULT2 +#define DP0_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_RESULT3 +#define DP0_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP0_DP_DPHY_CRC_STATUS +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP0_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP0_DP_TU_CNTL +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP0_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP0_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP0_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP0_DP_PIXEL_FORMAT_DB_CNTL +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP0_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP0_DP_SEC_CNTL +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL1 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING1 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP0_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING2 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP0_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING3 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP0_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP0_DP_SEC_FRAMING4 +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP0_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP0_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP0_DP_SEC_AUD_N +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_N_READBACK +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP0_DP_SEC_AUD_M_READBACK +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP0_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP0_DP_SEC_TIMESTAMP +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP0_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP0_DP_SEC_PACKET_CNTL +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP0_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP0_DP_MSE_RATE_CNTL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP0_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP0_DP_MSE_RATE_UPDATE +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP0_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP0_DP_MSE_SAT0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP0_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP0_DP_MSE_SAT1 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP0_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP0_DP_MSE_SAT2 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP0_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP0_DP_MSE_SAT_UPDATE +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP0_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP0_DP_MSE_LINK_TIMING +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP0_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP0_DP_MSE_MISC_CNTL +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP0_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP0_DP_DPHY_BS_SR_SWAP_CNTL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP0_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP0_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP0_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP0_DP_MSE_SAT0_STATUS +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP0_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT1_STATUS +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP0_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP0_DP_MSE_SAT2_STATUS +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP0_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP0_DP_HBLANK_CONTROL +#define DP0_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP0_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP0_DP_MSA_TIMING_PARAM1 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM2 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP0_DP_MSA_TIMING_PARAM3 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP0_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP0_DP_MSA_TIMING_PARAM4 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP0_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP0_DP_MSO_CNTL +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP0_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP0_DP_MSO_CNTL1 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP0_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP0_DP_STEER_FIFO_CNTL +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP0_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP0_DP_SEC_CNTL2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP0_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP0_DP_SEC_CNTL3 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL4 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL5 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_CNTL6 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP0_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP0_DP_SEC_CNTL7 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP0_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP0_DP_DB_CNTL +#define DP0_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP0_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP0_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP0_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP0_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP0_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP0_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP0_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP0_DP_MSA_VBID_MISC +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP0_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP0_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_SEC_METADATA_TRANSMISSION +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP0_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP0_DP_ALPM_CNTL +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP0_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP0_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP0_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP0_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP0_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP0_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP8_CNTL +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP9_CNTL +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP10_CNTL +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP11_CNTL +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP0_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP0_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_GSP_EN_DB_STATUS +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP0_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP0_DP_AUXLESS_ALPM_CNTL1 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP0_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP0_DP_AUXLESS_ALPM_CNTL2 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP0_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP0_DP_AUXLESS_ALPM_CNTL3 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP0_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_AUXLESS_ALPM_CNTL4 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP0_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP0_DP_AUXLESS_ALPM_CNTL5 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP0_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP0_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP0_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP0_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP0_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP0_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP0_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP0_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP0_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP0_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP0_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP0_DP_DPHY_FAST_TRAINING +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP0_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP0_DP_DPHY_FAST_TRAINING_STATUS +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP0_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec +//VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG1_VPG_GENERIC_PACKET_DATA +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG1_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG1_VPG_GENERIC_STATUS +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG1_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG1_VPG_MEM_PWR +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG1_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG1_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG1_VPG_ISRC1_2_ACCESS_CTRL +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG1_VPG_ISRC1_2_DATA +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG1_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig1_apg_apg_dispdec +//APG1_APG_CONTROL +#define APG1_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG1_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG1_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG1_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG1_APG_CONTROL2 +#define APG1_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG1_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG1_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG1_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG1_APG_DBG_GEN_CONTROL +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG1_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG1_APG_PACKET_CONTROL +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG1_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG1_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG1_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG1_APG_DBG_ACP +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG1_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG1_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG1_APG_DBG_AUDIO_INFO +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG1_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG1_APG_DBG_60958_0 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG1_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG1_APG_DBG_60958_1 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG1_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG1_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG1_APG_DBG_60958_2 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG1_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG1_APG_AUDIO_CRC_CONTROL +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG1_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG1_APG_AUDIO_CRC_CONTROL2 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG1_APG_AUDIO_CRC_RESULT +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG1_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG1_APG_DBG_RAMP_CONTROL0 +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG1_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG1_APG_DBG_RAMP_CONTROL1 +#define APG1_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG1_APG_DBG_RAMP_CONTROL2 +#define APG1_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG1_APG_DBG_RAMP_CONTROL3 +#define APG1_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG1_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG1_APG_STATUS +#define APG1_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG1_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG1_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG1_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG1_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG1_APG_STATUS2 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG1_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG1_APG_DBG_AUDIO_DTO_CNTL +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG1_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG1_APG_MEM_PWR +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG1_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG1_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG1_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG1_APG_SPARE +#define APG1_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG1_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec +//DME1_DME_CONTROL +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME1_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME1_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME1_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME1_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME1_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME1_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME1_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME1_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME1_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME1_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME1_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME1_DME_MEMORY_CONTROL +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME1_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig1_dispdec +//DIG1_DIG_FE_CNTL +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG1_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG1_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG1_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG1_DIG_FE_CLK_CNTL +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG1_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG1_DIG_FE_EN_CNTL +#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG1_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG1_DIG_OUTPUT_CRC_CNTL +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG1_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG1_DIG_OUTPUT_CRC_RESULT +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG1_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG1_DIG_CLOCK_PATTERN +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG1_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG1_DIG_TEST_PATTERN +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG1_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG1_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG1_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG1_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG1_DIG_RANDOM_PATTERN_SEED +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG1_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG1_DIG_FIFO_CTRL0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG1_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG1_DIG_FIFO_CTRL1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG1_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG1_HDMI_METADATA_PACKET_CONTROL +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG1_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_CONTROL +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG1_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG1_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG1_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG1_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG1_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG1_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG1_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG1_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG1_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG1_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG1_HDMI_STATUS +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG1_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG1_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG1_HDMI_AUDIO_PACKET_CONTROL +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG1_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG1_HDMI_ACR_PACKET_CONTROL +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG1_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG1_HDMI_VBI_PACKET_CONTROL +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG1_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG1_HDMI_INFOFRAME_CONTROL0 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG1_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG1_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG1_HDMI_GC +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG1_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG1_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG1_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG1_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG1_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG1_HDMI_DB_CONTROL +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG1_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG1_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG1_HDMI_ACR_32_0 +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG1_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_32_1 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG1_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_44_0 +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG1_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_44_1 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG1_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_48_0 +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG1_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_48_1 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG1_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG1_HDMI_ACR_STATUS_0 +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG1_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG1_HDMI_ACR_STATUS_1 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG1_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG1_DIG_FE_AUDIO_CNTL +#define DIG1_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG1_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG1_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG1_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG1_DIG_BE_CLK_CNTL +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG1_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG1_DIG_BE_CNTL +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG1_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG1_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG1_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG1_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG1_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG1_DIG_BE_EN_CNTL +#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG1_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG1_TMDS_CNTL +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG1_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG1_TMDS_CONTROL_CHAR +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG1_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG1_TMDS_CONTROL0_FEEDBACK +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG1_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG1_TMDS_STEREOSYNC_CTL_SEL +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG1_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG1_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG1_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG1_TMDS_CTL_BITS +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG1_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG1_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG1_TMDS_DCBALANCER_CONTROL +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG1_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG1_TMDS_SYNC_DCBALANCE_CHAR +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG1_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG1_TMDS_CTL0_1_GEN_CNTL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG1_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG1_TMDS_CTL2_3_GEN_CNTL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG1_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG1_DIG_VERSION +#define DIG1_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG1_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp1_dispdec +//DP1_DP_LINK_CNTL +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP1_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP1_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP1_DP_PIXEL_FORMAT +#define DP1_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP1_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP1_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP1_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP1_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP1_DP_MSA_COLORIMETRY +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP1_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP1_DP_CONFIG +#define DP1_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP1_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP1_DP_VID_STREAM_CNTL +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP1_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP1_DP_STEER_FIFO +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP1_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP1_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP1_DP_MSA_MISC +#define DP1_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP1_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP1_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP1_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP1_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP1_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP1_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP1_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP1_DP_DPHY_INTERNAL_CTRL +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP1_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP1_DP_VID_TIMING +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP1_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP1_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP1_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP1_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP1_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP1_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP1_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP1_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP1_DP_VID_N +#define DP1_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP1_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP1_DP_VID_M +#define DP1_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP1_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP1_DP_LINK_FRAMING_CNTL +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP1_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP1_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP1_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP1_DP_HBR2_EYE_PATTERN +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP1_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP1_DP_VID_MSA_VBID +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP1_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP1_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP1_DP_VID_INTERRUPT_CNTL +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP1_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP1_DP_DPHY_CNTL +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP1_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP1_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP1_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP1_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP1_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP1_DP_DPHY_TRAINING_PATTERN_SEL +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP1_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP1_DP_DPHY_SYM0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP1_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP1_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP1_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM1 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP1_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP1_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP1_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP1_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP1_DP_DPHY_SYM2 +#define DP1_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP1_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP1_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP1_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP1_DP_DPHY_8B10B_CNTL +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP1_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP1_DP_DPHY_PRBS_CNTL +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP1_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP1_DP_DPHY_SCRAM_CNTL +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP1_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP1_DP_DPHY_CRC_CONTROL0 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP1_DP_DPHY_CRC_CONTROL1 +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP1_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP1_DP_DPHY_CRC_RESULT0 +#define DP1_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_RESULT1 +#define DP1_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_RESULT2 +#define DP1_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_RESULT3 +#define DP1_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP1_DP_DPHY_CRC_STATUS +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP1_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP1_DP_TU_CNTL +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP1_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP1_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP1_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP1_DP_PIXEL_FORMAT_DB_CNTL +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP1_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP1_DP_SEC_CNTL +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL1 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING1 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP1_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING2 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP1_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING3 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP1_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP1_DP_SEC_FRAMING4 +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP1_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP1_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP1_DP_SEC_AUD_N +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_N_READBACK +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP1_DP_SEC_AUD_M_READBACK +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP1_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP1_DP_SEC_TIMESTAMP +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP1_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP1_DP_SEC_PACKET_CNTL +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP1_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP1_DP_MSE_RATE_CNTL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP1_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP1_DP_MSE_RATE_UPDATE +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP1_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP1_DP_MSE_SAT0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP1_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP1_DP_MSE_SAT1 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP1_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP1_DP_MSE_SAT2 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP1_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP1_DP_MSE_SAT_UPDATE +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP1_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP1_DP_MSE_LINK_TIMING +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP1_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP1_DP_MSE_MISC_CNTL +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP1_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP1_DP_DPHY_BS_SR_SWAP_CNTL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP1_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP1_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP1_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP1_DP_MSE_SAT0_STATUS +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP1_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT1_STATUS +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP1_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP1_DP_MSE_SAT2_STATUS +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP1_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP1_DP_HBLANK_CONTROL +#define DP1_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP1_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP1_DP_MSA_TIMING_PARAM1 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM2 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP1_DP_MSA_TIMING_PARAM3 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP1_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP1_DP_MSA_TIMING_PARAM4 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP1_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP1_DP_MSO_CNTL +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP1_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP1_DP_MSO_CNTL1 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP1_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP1_DP_STEER_FIFO_CNTL +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP1_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP1_DP_SEC_CNTL2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP1_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP1_DP_SEC_CNTL3 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL4 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL5 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_CNTL6 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP1_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP1_DP_SEC_CNTL7 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP1_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP1_DP_DB_CNTL +#define DP1_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP1_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP1_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP1_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP1_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP1_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP1_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP1_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP1_DP_MSA_VBID_MISC +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP1_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP1_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_SEC_METADATA_TRANSMISSION +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP1_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP1_DP_ALPM_CNTL +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP1_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP1_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP1_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP1_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP1_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP1_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP8_CNTL +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP9_CNTL +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP10_CNTL +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP11_CNTL +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP1_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP1_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_GSP_EN_DB_STATUS +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP1_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP1_DP_AUXLESS_ALPM_CNTL1 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP1_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP1_DP_AUXLESS_ALPM_CNTL2 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP1_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP1_DP_AUXLESS_ALPM_CNTL3 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP1_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_AUXLESS_ALPM_CNTL4 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP1_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP1_DP_AUXLESS_ALPM_CNTL5 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP1_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP1_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP1_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP1_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP1_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP1_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP1_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP1_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP1_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP1_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP1_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP1_DP_DPHY_FAST_TRAINING +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP1_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP1_DP_DPHY_FAST_TRAINING_STATUS +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP1_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec +//VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG2_VPG_GENERIC_PACKET_DATA +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG2_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG2_VPG_GENERIC_STATUS +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG2_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG2_VPG_MEM_PWR +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG2_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG2_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG2_VPG_ISRC1_2_ACCESS_CTRL +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG2_VPG_ISRC1_2_DATA +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG2_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig2_apg_apg_dispdec +//APG2_APG_CONTROL +#define APG2_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG2_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG2_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG2_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG2_APG_CONTROL2 +#define APG2_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG2_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG2_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG2_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG2_APG_DBG_GEN_CONTROL +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG2_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG2_APG_PACKET_CONTROL +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG2_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG2_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG2_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG2_APG_DBG_ACP +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG2_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG2_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG2_APG_DBG_AUDIO_INFO +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG2_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG2_APG_DBG_60958_0 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG2_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG2_APG_DBG_60958_1 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG2_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG2_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG2_APG_DBG_60958_2 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG2_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG2_APG_AUDIO_CRC_CONTROL +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG2_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG2_APG_AUDIO_CRC_CONTROL2 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG2_APG_AUDIO_CRC_RESULT +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG2_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG2_APG_DBG_RAMP_CONTROL0 +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG2_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG2_APG_DBG_RAMP_CONTROL1 +#define APG2_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG2_APG_DBG_RAMP_CONTROL2 +#define APG2_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG2_APG_DBG_RAMP_CONTROL3 +#define APG2_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG2_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG2_APG_STATUS +#define APG2_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG2_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG2_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG2_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG2_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG2_APG_STATUS2 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG2_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG2_APG_DBG_AUDIO_DTO_CNTL +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG2_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG2_APG_MEM_PWR +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG2_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG2_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG2_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG2_APG_SPARE +#define APG2_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG2_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec +//DME2_DME_CONTROL +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME2_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME2_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME2_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME2_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME2_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME2_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME2_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME2_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME2_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME2_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME2_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME2_DME_MEMORY_CONTROL +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME2_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig2_dispdec +//DIG2_DIG_FE_CNTL +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG2_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG2_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG2_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG2_DIG_FE_CLK_CNTL +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG2_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG2_DIG_FE_EN_CNTL +#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG2_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG2_DIG_OUTPUT_CRC_CNTL +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG2_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG2_DIG_OUTPUT_CRC_RESULT +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG2_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG2_DIG_CLOCK_PATTERN +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG2_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG2_DIG_TEST_PATTERN +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG2_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG2_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG2_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG2_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG2_DIG_RANDOM_PATTERN_SEED +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG2_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG2_DIG_FIFO_CTRL0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG2_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG2_DIG_FIFO_CTRL1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG2_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG2_HDMI_METADATA_PACKET_CONTROL +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG2_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_CONTROL +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG2_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG2_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG2_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG2_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG2_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG2_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG2_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG2_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG2_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG2_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG2_HDMI_STATUS +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG2_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG2_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG2_HDMI_AUDIO_PACKET_CONTROL +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG2_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG2_HDMI_ACR_PACKET_CONTROL +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG2_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG2_HDMI_VBI_PACKET_CONTROL +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG2_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG2_HDMI_INFOFRAME_CONTROL0 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG2_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG2_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG2_HDMI_GC +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG2_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG2_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG2_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG2_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG2_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG2_HDMI_DB_CONTROL +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG2_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG2_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG2_HDMI_ACR_32_0 +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG2_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_32_1 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG2_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_44_0 +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG2_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_44_1 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG2_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_48_0 +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG2_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_48_1 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG2_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG2_HDMI_ACR_STATUS_0 +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG2_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG2_HDMI_ACR_STATUS_1 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG2_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG2_DIG_FE_AUDIO_CNTL +#define DIG2_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG2_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG2_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG2_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG2_DIG_BE_CLK_CNTL +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG2_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG2_DIG_BE_CNTL +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG2_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG2_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG2_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG2_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG2_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG2_DIG_BE_EN_CNTL +#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG2_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG2_TMDS_CNTL +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG2_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG2_TMDS_CONTROL_CHAR +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG2_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG2_TMDS_CONTROL0_FEEDBACK +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG2_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG2_TMDS_STEREOSYNC_CTL_SEL +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG2_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG2_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG2_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG2_TMDS_CTL_BITS +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG2_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG2_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG2_TMDS_DCBALANCER_CONTROL +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG2_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG2_TMDS_SYNC_DCBALANCE_CHAR +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG2_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG2_TMDS_CTL0_1_GEN_CNTL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG2_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG2_TMDS_CTL2_3_GEN_CNTL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG2_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG2_DIG_VERSION +#define DIG2_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG2_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp2_dispdec +//DP2_DP_LINK_CNTL +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP2_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP2_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP2_DP_PIXEL_FORMAT +#define DP2_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP2_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP2_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP2_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP2_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP2_DP_MSA_COLORIMETRY +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP2_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP2_DP_CONFIG +#define DP2_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP2_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP2_DP_VID_STREAM_CNTL +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP2_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP2_DP_STEER_FIFO +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP2_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP2_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP2_DP_MSA_MISC +#define DP2_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP2_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP2_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP2_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP2_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP2_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP2_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP2_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP2_DP_DPHY_INTERNAL_CTRL +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP2_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP2_DP_VID_TIMING +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP2_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP2_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP2_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP2_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP2_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP2_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP2_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP2_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP2_DP_VID_N +#define DP2_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP2_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP2_DP_VID_M +#define DP2_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP2_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP2_DP_LINK_FRAMING_CNTL +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP2_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP2_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP2_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP2_DP_HBR2_EYE_PATTERN +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP2_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP2_DP_VID_MSA_VBID +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP2_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP2_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP2_DP_VID_INTERRUPT_CNTL +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP2_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP2_DP_DPHY_CNTL +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP2_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP2_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP2_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP2_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP2_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP2_DP_DPHY_TRAINING_PATTERN_SEL +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP2_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP2_DP_DPHY_SYM0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP2_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP2_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP2_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM1 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP2_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP2_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP2_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP2_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP2_DP_DPHY_SYM2 +#define DP2_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP2_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP2_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP2_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP2_DP_DPHY_8B10B_CNTL +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP2_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP2_DP_DPHY_PRBS_CNTL +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP2_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP2_DP_DPHY_SCRAM_CNTL +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP2_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP2_DP_DPHY_CRC_CONTROL0 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP2_DP_DPHY_CRC_CONTROL1 +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP2_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP2_DP_DPHY_CRC_RESULT0 +#define DP2_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_RESULT1 +#define DP2_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_RESULT2 +#define DP2_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_RESULT3 +#define DP2_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP2_DP_DPHY_CRC_STATUS +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP2_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP2_DP_TU_CNTL +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP2_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP2_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP2_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP2_DP_PIXEL_FORMAT_DB_CNTL +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP2_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP2_DP_SEC_CNTL +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL1 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING1 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP2_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING2 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP2_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING3 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP2_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP2_DP_SEC_FRAMING4 +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP2_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP2_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP2_DP_SEC_AUD_N +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_N_READBACK +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP2_DP_SEC_AUD_M_READBACK +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP2_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP2_DP_SEC_TIMESTAMP +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP2_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP2_DP_SEC_PACKET_CNTL +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP2_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP2_DP_MSE_RATE_CNTL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP2_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP2_DP_MSE_RATE_UPDATE +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP2_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP2_DP_MSE_SAT0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP2_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP2_DP_MSE_SAT1 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP2_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP2_DP_MSE_SAT2 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP2_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP2_DP_MSE_SAT_UPDATE +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP2_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP2_DP_MSE_LINK_TIMING +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP2_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP2_DP_MSE_MISC_CNTL +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP2_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP2_DP_DPHY_BS_SR_SWAP_CNTL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP2_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP2_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP2_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP2_DP_MSE_SAT0_STATUS +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP2_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT1_STATUS +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP2_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP2_DP_MSE_SAT2_STATUS +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP2_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP2_DP_HBLANK_CONTROL +#define DP2_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP2_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP2_DP_MSA_TIMING_PARAM1 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM2 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP2_DP_MSA_TIMING_PARAM3 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP2_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP2_DP_MSA_TIMING_PARAM4 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP2_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP2_DP_MSO_CNTL +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP2_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP2_DP_MSO_CNTL1 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP2_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP2_DP_STEER_FIFO_CNTL +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP2_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP2_DP_SEC_CNTL2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP2_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP2_DP_SEC_CNTL3 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL4 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL5 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_CNTL6 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP2_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP2_DP_SEC_CNTL7 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP2_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP2_DP_DB_CNTL +#define DP2_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP2_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP2_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP2_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP2_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP2_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP2_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP2_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP2_DP_MSA_VBID_MISC +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP2_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP2_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_SEC_METADATA_TRANSMISSION +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP2_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP2_DP_ALPM_CNTL +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP2_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP2_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP2_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP2_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP2_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP2_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP8_CNTL +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP9_CNTL +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP10_CNTL +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP11_CNTL +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP2_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP2_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_GSP_EN_DB_STATUS +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP2_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP2_DP_AUXLESS_ALPM_CNTL1 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP2_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP2_DP_AUXLESS_ALPM_CNTL2 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP2_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP2_DP_AUXLESS_ALPM_CNTL3 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP2_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_AUXLESS_ALPM_CNTL4 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP2_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP2_DP_AUXLESS_ALPM_CNTL5 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP2_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP2_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP2_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP2_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP2_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP2_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP2_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP2_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP2_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP2_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP2_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP2_DP_DPHY_FAST_TRAINING +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP2_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP2_DP_DPHY_FAST_TRAINING_STATUS +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP2_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec +//VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG3_VPG_GENERIC_PACKET_DATA +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG3_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG3_VPG_GENERIC_STATUS +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG3_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG3_VPG_MEM_PWR +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG3_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG3_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG3_VPG_ISRC1_2_ACCESS_CTRL +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG3_VPG_ISRC1_2_DATA +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG3_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig3_apg_apg_dispdec +//APG3_APG_CONTROL +#define APG3_APG_CONTROL__APG_RESET__SHIFT 0x1 +#define APG3_APG_CONTROL__APG_RESET_DONE__SHIFT 0x2 +#define APG3_APG_CONTROL__APG_RESET_MASK 0x00000002L +#define APG3_APG_CONTROL__APG_RESET_DONE_MASK 0x00000004L +//APG3_APG_CONTROL2 +#define APG3_APG_CONTROL2__APG_ENABLE__SHIFT 0x0 +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID__SHIFT 0x8 +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x18 +#define APG3_APG_CONTROL2__APG_ENABLE_MASK 0x00000001L +#define APG3_APG_CONTROL2__APG_DP_AUDIO_STREAM_ID_MASK 0x0000FF00L +#define APG3_APG_CONTROL2__APG_DP_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x01000000L +//APG3_APG_DBG_GEN_CONTROL +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG3_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG3_APG_PACKET_CONTROL +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL__SHIFT 0x0 +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE__SHIFT 0x1 +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE__SHIFT 0x2 +#define APG3_APG_PACKET_CONTROL__APG_DBG_MUX_SEL_MASK 0x00000001L +#define APG3_APG_PACKET_CONTROL__APG_ACP_SOURCE_MASK 0x00000002L +#define APG3_APG_PACKET_CONTROL__APG_AUDIO_INFO_SOURCE_MASK 0x00000004L +//APG3_APG_DBG_ACP +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE__SHIFT 0x0 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0__SHIFT 0x8 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1__SHIFT 0x10 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_REQUIRED__SHIFT 0x18 +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_MASK 0x00000003L +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE0_MASK 0x0000FF00L +#define APG3_APG_DBG_ACP__APG_DBG_ACP_TYPE_DEPENDENT_BYTE1_MASK 0x00FF0000L +#define APG3_APG_DBG_ACP__APG_DBG_ACP_REQUIRED_MASK 0x01000000L +//APG3_APG_DBG_AUDIO_INFO +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA__SHIFT 0x0 +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC__SHIFT 0x8 +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV__SHIFT 0xb +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH__SHIFT 0xf +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL__SHIFT 0x10 +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CA_MASK 0x000000FFL +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_CC_MASK 0x00000700L +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LSV_MASK 0x00007800L +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_DM_INH_MASK 0x00008000L +#define APG3_APG_DBG_AUDIO_INFO__APG_DBG_AUDIO_INFO_LFEPBL_MASK 0x00030000L +//APG3_APG_DBG_60958_0 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_A__SHIFT 0x0 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_B__SHIFT 0x1 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_C__SHIFT 0x2 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_D__SHIFT 0x3 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_MODE__SHIFT 0x6 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE__SHIFT 0x8 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER__SHIFT 0x10 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x14 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x18 +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY__SHIFT 0x1c +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_A_MASK 0x00000001L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_B_MASK 0x00000002L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_C_MASK 0x00000004L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_D_MASK 0x00000038L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_MODE_MASK 0x000000C0L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CATEGORY_CODE_MASK 0x0000FF00L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SOURCE_NUMBER_MASK 0x000F0000L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CHANNEL_NUMBER_L_MASK 0x00F00000L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_SAMPLING_FREQUENCY_MASK 0x0F000000L +#define APG3_APG_DBG_60958_0__APG_DBG_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L +//APG3_APG_DBG_60958_1 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH__SHIFT 0x0 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x4 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_VALID__SHIFT 0x10 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x14 +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_WORD_LENGTH_MASK 0x0000000FL +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000F0L +#define APG3_APG_DBG_60958_1__APG_DBG_60958_VALID_MASK 0x00010000L +#define APG3_APG_DBG_60958_1__APG_DBG_60958_CS_CHANNEL_NUMBER_R_MASK 0x00F00000L +//APG3_APG_DBG_60958_2 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x0 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x4 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x8 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5__SHIFT 0xc +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x10 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x14 +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000FL +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000F0L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000F00L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000F000L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_6_MASK 0x000F0000L +#define APG3_APG_DBG_60958_2__APG_DBG_60958_CS_CHANNEL_NUMBER_7_MASK 0x00F00000L +//APG3_APG_AUDIO_CRC_CONTROL +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT__SHIFT 0x4 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL__SHIFT 0xd +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_EN_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CONT_MASK 0x00000010L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_CH_SEL_MASK 0x0000E000L +#define APG3_APG_AUDIO_CRC_CONTROL__APG_AUDIO_CRC_COUNT_MASK 0xFFFF0000L +//APG3_APG_AUDIO_CRC_CONTROL2 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_CONTROL2__APG_AUDIO_CRC_COUNT_FORCE_DEFAULT_MASK 0x0000FFFFL +//APG3_APG_AUDIO_CRC_RESULT +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE__SHIFT 0x0 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR__SHIFT 0x8 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC__SHIFT 0x10 +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_MASK 0x00000001L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_DONE_CLEAR_MASK 0x00000100L +#define APG3_APG_AUDIO_CRC_RESULT__APG_AUDIO_CRC_MASK 0xFFFF0000L +//APG3_APG_DBG_RAMP_CONTROL0 +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN__SHIFT 0x1f +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_MAX_COUNT_MASK 0x00FFFFFFL +#define APG3_APG_DBG_RAMP_CONTROL0__APG_DBG_RAMP_DATA_SIGN_MASK 0x80000000L +//APG3_APG_DBG_RAMP_CONTROL1 +#define APG3_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL1__APG_DBG_RAMP_MIN_COUNT_MASK 0x00FFFFFFL +//APG3_APG_DBG_RAMP_CONTROL2 +#define APG3_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL2__APG_DBG_RAMP_INC_COUNT_MASK 0x00FFFFFFL +//APG3_APG_DBG_RAMP_CONTROL3 +#define APG3_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT__SHIFT 0x0 +#define APG3_APG_DBG_RAMP_CONTROL3__APG_DBG_RAMP_DEC_COUNT_MASK 0x00FFFFFFL +//APG3_APG_STATUS +#define APG3_APG_STATUS__APG_AUDIO_ENABLE__SHIFT 0x4 +#define APG3_APG_STATUS__APG_HBR_ENABLE__SHIFT 0x8 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS__SHIFT 0x18 +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR__SHIFT 0x19 +#define APG3_APG_STATUS__APG_AUDIO_ENABLE_MASK 0x00000010L +#define APG3_APG_STATUS__APG_HBR_ENABLE_MASK 0x00000100L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_MASK 0x01000000L +#define APG3_APG_STATUS__APG_AUDIO_FIFO_OVERFLOW_STATUS_CLEAR_MASK 0x02000000L +//APG3_APG_STATUS2 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE__SHIFT 0x0 +#define APG3_APG_STATUS2__APG_OUTPUT_ACTIVE_MASK 0x00000001L +//APG3_APG_DBG_AUDIO_DTO_CNTL +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE__SHIFT 0x8 +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI__SHIFT 0xc +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV__SHIFT 0x10 +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_BASE_MASK 0x00000100L +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_MULTI_MASK 0x00007000L +#define APG3_APG_DBG_AUDIO_DTO_CNTL__APG_DBG_AUDIO_DTO_DIV_MASK 0x00070000L +//APG3_APG_MEM_PWR +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG3_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG3_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG3_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L +//APG3_APG_SPARE +#define APG3_APG_SPARE__APG_SPARE__SHIFT 0x0 +#define APG3_APG_SPARE__APG_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec +//DME3_DME_CONTROL +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME3_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME3_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME3_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME3_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME3_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME3_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME3_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME3_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME3_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME3_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME3_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME3_DME_MEMORY_CONTROL +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME3_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig3_dispdec +//DIG3_DIG_FE_CNTL +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG3_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG3_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG3_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG3_DIG_FE_CLK_CNTL +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG3_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG3_DIG_FE_EN_CNTL +#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG3_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG3_DIG_OUTPUT_CRC_CNTL +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG3_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG3_DIG_OUTPUT_CRC_RESULT +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG3_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG3_DIG_CLOCK_PATTERN +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG3_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG3_DIG_TEST_PATTERN +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG3_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG3_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG3_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG3_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG3_DIG_RANDOM_PATTERN_SEED +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG3_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG3_DIG_FIFO_CTRL0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG3_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG3_DIG_FIFO_CTRL1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG3_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG3_HDMI_METADATA_PACKET_CONTROL +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG3_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_CONTROL +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG3_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG3_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG3_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG3_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG3_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG3_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG3_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG3_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG3_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG3_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG3_HDMI_STATUS +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG3_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG3_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG3_HDMI_AUDIO_PACKET_CONTROL +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG3_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG3_HDMI_ACR_PACKET_CONTROL +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG3_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG3_HDMI_VBI_PACKET_CONTROL +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG3_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG3_HDMI_INFOFRAME_CONTROL0 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG3_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG3_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG3_HDMI_GC +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG3_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG3_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG3_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG3_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG3_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG3_HDMI_DB_CONTROL +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG3_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG3_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG3_HDMI_ACR_32_0 +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG3_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_32_1 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG3_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_44_0 +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG3_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_44_1 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG3_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_48_0 +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG3_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_48_1 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG3_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG3_HDMI_ACR_STATUS_0 +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG3_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG3_HDMI_ACR_STATUS_1 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG3_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG3_DIG_FE_AUDIO_CNTL +#define DIG3_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG3_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG3_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG3_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG3_DIG_BE_CLK_CNTL +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG3_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG3_DIG_BE_CNTL +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG3_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG3_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG3_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG3_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG3_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG3_DIG_BE_EN_CNTL +#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG3_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG3_TMDS_CNTL +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG3_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG3_TMDS_CONTROL_CHAR +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG3_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG3_TMDS_CONTROL0_FEEDBACK +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG3_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG3_TMDS_STEREOSYNC_CTL_SEL +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG3_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG3_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG3_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG3_TMDS_CTL_BITS +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG3_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG3_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG3_TMDS_DCBALANCER_CONTROL +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG3_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG3_TMDS_SYNC_DCBALANCE_CHAR +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG3_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG3_TMDS_CTL0_1_GEN_CNTL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG3_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG3_TMDS_CTL2_3_GEN_CNTL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG3_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG3_DIG_VERSION +#define DIG3_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG3_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp3_dispdec +//DP3_DP_LINK_CNTL +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP3_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP3_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP3_DP_PIXEL_FORMAT +#define DP3_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP3_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP3_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP3_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP3_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP3_DP_MSA_COLORIMETRY +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP3_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP3_DP_CONFIG +#define DP3_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP3_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP3_DP_VID_STREAM_CNTL +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP3_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP3_DP_STEER_FIFO +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP3_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP3_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP3_DP_MSA_MISC +#define DP3_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP3_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP3_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP3_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP3_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP3_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP3_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP3_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP3_DP_DPHY_INTERNAL_CTRL +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP3_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP3_DP_VID_TIMING +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP3_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP3_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP3_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP3_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP3_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP3_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP3_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP3_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP3_DP_VID_N +#define DP3_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP3_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP3_DP_VID_M +#define DP3_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP3_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP3_DP_LINK_FRAMING_CNTL +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP3_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP3_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP3_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP3_DP_HBR2_EYE_PATTERN +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP3_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP3_DP_VID_MSA_VBID +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP3_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP3_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP3_DP_VID_INTERRUPT_CNTL +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP3_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP3_DP_DPHY_CNTL +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP3_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP3_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP3_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP3_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP3_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP3_DP_DPHY_TRAINING_PATTERN_SEL +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP3_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP3_DP_DPHY_SYM0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP3_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP3_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP3_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM1 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP3_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP3_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP3_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP3_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP3_DP_DPHY_SYM2 +#define DP3_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP3_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP3_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP3_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP3_DP_DPHY_8B10B_CNTL +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP3_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP3_DP_DPHY_PRBS_CNTL +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP3_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP3_DP_DPHY_SCRAM_CNTL +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP3_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP3_DP_DPHY_CRC_CONTROL0 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP3_DP_DPHY_CRC_CONTROL1 +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP3_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP3_DP_DPHY_CRC_RESULT0 +#define DP3_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_RESULT1 +#define DP3_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_RESULT2 +#define DP3_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_RESULT3 +#define DP3_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP3_DP_DPHY_CRC_STATUS +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP3_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP3_DP_TU_CNTL +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP3_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP3_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP3_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP3_DP_PIXEL_FORMAT_DB_CNTL +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP3_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP3_DP_SEC_CNTL +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL1 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING1 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP3_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING2 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP3_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING3 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP3_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP3_DP_SEC_FRAMING4 +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP3_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP3_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP3_DP_SEC_AUD_N +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_N_READBACK +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP3_DP_SEC_AUD_M_READBACK +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP3_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP3_DP_SEC_TIMESTAMP +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP3_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP3_DP_SEC_PACKET_CNTL +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP3_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP3_DP_MSE_RATE_CNTL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP3_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP3_DP_MSE_RATE_UPDATE +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP3_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP3_DP_MSE_SAT0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP3_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP3_DP_MSE_SAT1 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP3_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP3_DP_MSE_SAT2 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP3_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP3_DP_MSE_SAT_UPDATE +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP3_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP3_DP_MSE_LINK_TIMING +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP3_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP3_DP_MSE_MISC_CNTL +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP3_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP3_DP_DPHY_BS_SR_SWAP_CNTL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP3_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP3_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP3_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP3_DP_MSE_SAT0_STATUS +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP3_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT1_STATUS +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP3_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP3_DP_MSE_SAT2_STATUS +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP3_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP3_DP_HBLANK_CONTROL +#define DP3_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP3_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP3_DP_MSA_TIMING_PARAM1 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM2 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP3_DP_MSA_TIMING_PARAM3 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP3_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP3_DP_MSA_TIMING_PARAM4 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP3_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP3_DP_MSO_CNTL +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP3_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP3_DP_MSO_CNTL1 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP3_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP3_DP_STEER_FIFO_CNTL +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP3_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP3_DP_SEC_CNTL2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP3_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP3_DP_SEC_CNTL3 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL4 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL5 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_CNTL6 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP3_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP3_DP_SEC_CNTL7 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP3_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP3_DP_DB_CNTL +#define DP3_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP3_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP3_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP3_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP3_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP3_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP3_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP3_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP3_DP_MSA_VBID_MISC +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP3_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP3_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_SEC_METADATA_TRANSMISSION +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP3_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP3_DP_ALPM_CNTL +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP3_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP3_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP3_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP3_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP3_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP3_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP8_CNTL +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP9_CNTL +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP10_CNTL +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP11_CNTL +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP3_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP3_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_GSP_EN_DB_STATUS +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP3_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP3_DP_AUXLESS_ALPM_CNTL1 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP3_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP3_DP_AUXLESS_ALPM_CNTL2 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP3_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP3_DP_AUXLESS_ALPM_CNTL3 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP3_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_AUXLESS_ALPM_CNTL4 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP3_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP3_DP_AUXLESS_ALPM_CNTL5 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP3_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP3_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP3_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP3_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP3_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP3_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP3_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP3_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP3_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP3_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP3_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP3_DP_DPHY_FAST_TRAINING +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP3_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP3_DP_DPHY_FAST_TRAINING_STATUS +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP3_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec +//VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG4_VPG_GENERIC_PACKET_DATA +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG4_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG4_VPG_GENERIC_STATUS +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG4_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG4_VPG_MEM_PWR +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG4_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG4_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG4_VPG_ISRC1_2_ACCESS_CTRL +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG4_VPG_ISRC1_2_DATA +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG4_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_dio_dig4_apg_apg_dispdec +//APG4_APG_DBG_GEN_CONTROL +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG4_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG4_APG_MEM_PWR +#define APG4_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG4_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG4_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG4_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG4_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG4_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG4_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG4_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec +//DME4_DME_CONTROL +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME4_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME4_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME4_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME4_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME4_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME4_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME4_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME4_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME4_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME4_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME4_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME4_DME_MEMORY_CONTROL +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME4_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_dio_dig4_dispdec +//DIG4_DIG_FE_CNTL +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x0 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x4 +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x8 +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT__SHIFT 0xc +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN__SHIFT 0x14 +#define DIG4_DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L +#define DIG4_DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_SELECT_MASK 0x00007000L +#define DIG4_DIG_FE_CNTL__DIG_DIGITAL_BYPASS_EN_MASK 0x00100000L +//DIG4_DIG_FE_CLK_CNTL +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE__SHIFT 0x0 +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN__SHIFT 0x4 +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET__SHIFT 0x5 +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON__SHIFT 0xa +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON__SHIFT 0xb +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON__SHIFT 0xc +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON__SHIFT 0xe +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_MODE_MASK 0x00000007L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_CLK_EN_MASK 0x00000010L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOFT_RESET_MASK 0x00000020L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_DISPCLK_G_CLOCK_ON_MASK 0x00000400L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_CLOCK_ON_MASK 0x00000800L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_APG_CLOCK_ON_MASK 0x00001000L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON_MASK 0x00002000L +#define DIG4_DIG_FE_CLK_CNTL__DIG_FE_SOCCLK_G_APG_CLOCK_ON_MASK 0x00004000L +//DIG4_DIG_FE_EN_CNTL +#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE__SHIFT 0x0 +#define DIG4_DIG_FE_EN_CNTL__DIG_FE_ENABLE_MASK 0x00000001L +//DIG4_DIG_OUTPUT_CRC_CNTL +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x4 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x8 +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L +#define DIG4_DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L +//DIG4_DIG_OUTPUT_CRC_RESULT +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x0 +#define DIG4_DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3FFFFFFFL +//DIG4_DIG_CLOCK_PATTERN +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x0 +#define DIG4_DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003FFL +//DIG4_DIG_TEST_PATTERN +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x0 +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x1 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x4 +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x5 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x6 +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x10 +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L +#define DIG4_DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L +#define DIG4_DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L +#define DIG4_DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L +#define DIG4_DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03FF0000L +//DIG4_DIG_RANDOM_PATTERN_SEED +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x0 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x18 +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00FFFFFFL +#define DIG4_DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L +//DIG4_DIG_FIFO_CTRL0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE__SHIFT 0x0 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC__SHIFT 0x8 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x9 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE__SHIFT 0x14 +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR__SHIFT 0x1c +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ENABLE_MASK 0x00000001L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_START_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_READ_CLOCK_SRC_MASK 0x00000100L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00000600L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_RESET_DONE_MASK 0x00100000L +#define DIG4_DIG_FIFO_CTRL0__DIG_FIFO_ERROR_MASK 0x30000000L +//DIG4_DIG_FIFO_CTRL1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x1 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x2 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY__SHIFT 0x8 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0xa +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x16 +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED__SHIFT 0x1d +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1e +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x1f +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000FCL +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_LEVEL_DET_DELAY_MASK 0x00000300L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000FC00L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03C00000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_CALIBRATED_MASK 0x20000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L +#define DIG4_DIG_FIFO_CTRL1__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L +//DIG4_HDMI_METADATA_PACKET_CONTROL +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define DIG4_HDMI_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_CONTROL +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN__SHIFT 0x1 +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE__SHIFT 0x2 +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED__SHIFT 0x3 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x8 +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x9 +#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN__SHIFT 0xa +#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED__SHIFT 0xb +#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING__SHIFT 0xc +#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT__SHIFT 0xd +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM__SHIFT 0x10 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x18 +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x1c +#define DIG4_HDMI_CONTROL__HDMI_DATA_SCRAMBLE_EN_MASK 0x00000002L +#define DIG4_HDMI_CONTROL__HDMI_CLOCK_CHANNEL_RATE_MASK 0x00000004L +#define DIG4_HDMI_CONTROL__HDMI_NO_EXTRA_NULL_PACKET_FILLED_MASK 0x00000008L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L +#define DIG4_HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L +#define DIG4_HDMI_CONTROL__DOLBY_VISION_EN_MASK 0x00000400L +#define DIG4_HDMI_CONTROL__DOLBY_VISION_METADATA_PACKET_MISSED_MASK 0x00000800L +#define DIG4_HDMI_CONTROL__TMDS_PIXEL_ENCODING_MASK 0x00001000L +#define DIG4_HDMI_CONTROL__TMDS_COLOR_FORMAT_MASK 0x00006000L +#define DIG4_HDMI_CONTROL__HDMI_UNSCRAMBLED_CONTROL_LINE_NUM_MASK 0x003F0000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L +#define DIG4_HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L +//DIG4_HDMI_STATUS +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x10 +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x1b +#define DIG4_HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L +#define DIG4_HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L +//DIG4_HDMI_AUDIO_PACKET_CONTROL +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x4 +#define DIG4_HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L +//DIG4_HDMI_ACR_PACKET_CONTROL +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define DIG4_HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +//DIG4_HDMI_VBI_PACKET_CONTROL +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x0 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x4 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x5 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x8 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x9 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND__SHIFT 0xc +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x10 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE__SHIFT 0x18 +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_SEND_MASK 0x00001000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003F0000L +#define DIG4_HDMI_VBI_PACKET_CONTROL__HDMI_ACP_LINE_MASK 0x3F000000L +//DIG4_HDMI_INFOFRAME_CONTROL0 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x4 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE__SHIFT 0x8 +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L +#define DIG4_HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_LINE_MASK 0x00003F00L +//DIG4_HDMI_GENERIC_PACKET_CONTROL0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE__SHIFT 0x1f +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_UPDATE_LOCK_DISABLE_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x40000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_UPDATE_LOCK_DISABLE_MASK 0x80000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC8_UPDATE_LOCK_DISABLE_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC9_UPDATE_LOCK_DISABLE_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC10_UPDATE_LOCK_DISABLE_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC11_UPDATE_LOCK_DISABLE_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC12_UPDATE_LOCK_DISABLE_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC13_UPDATE_LOCK_DISABLE_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL6__HDMI_GENERIC14_UPDATE_LOCK_DISABLE_MASK 0x08000000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL5__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//DIG4_HDMI_GC +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x0 +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x8 +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0xc +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L +#define DIG4_HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define DIG4_HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000F00L +#define DIG4_HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL1 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC0_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC1_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL2 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL3 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC4_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL3__HDMI_GENERIC5_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL4 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC6_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL4__HDMI_GENERIC7_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL7 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC8_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL7__HDMI_GENERIC9_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL8 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC10_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL8__HDMI_GENERIC11_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL9 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC12_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL9__HDMI_GENERIC13_LINE_MASK 0xFFFF0000L +//DIG4_HDMI_GENERIC_PACKET_CONTROL10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING__SHIFT 0x10 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING__SHIFT 0x11 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING__SHIFT 0x12 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING__SHIFT 0x13 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING__SHIFT 0x14 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING__SHIFT 0x15 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING__SHIFT 0x16 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING__SHIFT 0x17 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING__SHIFT 0x18 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING__SHIFT 0x19 +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING__SHIFT 0x1a +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING__SHIFT 0x1b +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING__SHIFT 0x1c +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING__SHIFT 0x1d +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING__SHIFT 0x1e +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_LINE_MASK 0x0000FFFFL +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC0_EN_DB_PENDING_MASK 0x00010000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC1_EN_DB_PENDING_MASK 0x00020000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC2_EN_DB_PENDING_MASK 0x00040000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC3_EN_DB_PENDING_MASK 0x00080000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC4_EN_DB_PENDING_MASK 0x00100000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC5_EN_DB_PENDING_MASK 0x00200000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC6_EN_DB_PENDING_MASK 0x00400000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC7_EN_DB_PENDING_MASK 0x00800000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC8_EN_DB_PENDING_MASK 0x01000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC9_EN_DB_PENDING_MASK 0x02000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC10_EN_DB_PENDING_MASK 0x04000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC11_EN_DB_PENDING_MASK 0x08000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC12_EN_DB_PENDING_MASK 0x10000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC13_EN_DB_PENDING_MASK 0x20000000L +#define DIG4_HDMI_GENERIC_PACKET_CONTROL10__HDMI_GENERIC14_EN_DB_PENDING_MASK 0x40000000L +//DIG4_HDMI_DB_CONTROL +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN__SHIFT 0x4 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR__SHIFT 0x5 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK__SHIFT 0x8 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_MASK 0x00000010L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_TAKEN_CLR_MASK 0x00000020L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_LOCK_MASK 0x00000100L +#define DIG4_HDMI_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DIG4_HDMI_DB_CONTROL__VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DIG4_HDMI_ACR_32_0 +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define DIG4_HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_32_1 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define DIG4_HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_44_0 +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define DIG4_HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_44_1 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define DIG4_HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_48_0 +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define DIG4_HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_48_1 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define DIG4_HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//DIG4_HDMI_ACR_STATUS_0 +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define DIG4_HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//DIG4_HDMI_ACR_STATUS_1 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define DIG4_HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//DIG4_DIG_FE_AUDIO_CNTL +#define DIG4_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DIG4_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE__SHIFT 0x8 +#define DIG4_DIG_FE_AUDIO_CNTL__DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DIG4_DIG_FE_AUDIO_CNTL__APG_CLOCK_ENABLE_MASK 0x00000100L +//DIG4_DIG_BE_CLK_CNTL +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE__SHIFT 0x0 +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN__SHIFT 0x4 +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET__SHIFT 0x5 +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON__SHIFT 0xb +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON__SHIFT 0xd +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_MODE_MASK 0x00000007L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_CLK_EN_MASK 0x00000010L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SOFT_RESET_MASK 0x00000020L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_CLOCK_ON_MASK 0x00000800L +#define DIG4_DIG_BE_CLK_CNTL__DIG_BE_SYMCLK_G_TMDS_CLOCK_ON_MASK 0x00002000L +//DIG4_DIG_BE_CNTL +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_CNTL__DIG_SWAP__SHIFT 0x1 +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x2 +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x8 +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x1c +#define DIG4_DIG_BE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00000001L +#define DIG4_DIG_BE_CNTL__DIG_SWAP_MASK 0x00000002L +#define DIG4_DIG_BE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00000004L +#define DIG4_DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00007F00L +#define DIG4_DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L +//DIG4_DIG_BE_EN_CNTL +#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE__SHIFT 0x0 +#define DIG4_DIG_BE_EN_CNTL__DIG_BE_ENABLE_MASK 0x00000001L +//DIG4_TMDS_CNTL +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x0 +#define DIG4_TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L +//DIG4_TMDS_CONTROL_CHAR +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x0 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x1 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x2 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x3 +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L +#define DIG4_TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L +//DIG4_TMDS_CONTROL0_FEEDBACK +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x0 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x8 +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L +#define DIG4_TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L +//DIG4_TMDS_STEREOSYNC_CTL_SEL +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x0 +#define DIG4_TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L +//DIG4_TMDS_SYNC_CHAR_PATTERN_0_1 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03FF0000L +//DIG4_TMDS_SYNC_CHAR_PATTERN_2_3 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x0 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x10 +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03FF0000L +//DIG4_TMDS_CTL_BITS +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x0 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x8 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x10 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x18 +#define DIG4_TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L +#define DIG4_TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L +//DIG4_TMDS_DCBALANCER_CONTROL +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x0 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x4 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x8 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x10 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x18 +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000F0000L +#define DIG4_TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L +//DIG4_TMDS_SYNC_DCBALANCE_CHAR +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01__SHIFT 0x0 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11__SHIFT 0x10 +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR01_MASK 0x000003FFL +#define DIG4_TMDS_SYNC_DCBALANCE_CHAR__TMDS_SYNC_DCBAL_CHAR11_MASK 0x03FF0000L +//DIG4_TMDS_CTL0_1_GEN_CNTL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x1f +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L +#define DIG4_TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L +//DIG4_TMDS_CTL2_3_GEN_CNTL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x0 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x4 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x7 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x8 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0xa +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0xb +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0xc +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x10 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x14 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x17 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x18 +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x1a +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x1b +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x1c +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000FL +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000F0000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L +#define DIG4_TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L +//DIG4_DIG_VERSION +#define DIG4_DIG_VERSION__DIG_TYPE__SHIFT 0x0 +#define DIG4_DIG_VERSION__DIG_TYPE_MASK 0x00000001L + + +// addressBlock: dce_dc_dio_dp4_dispdec +//DP4_DP_LINK_CNTL +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x4 +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x8 +#define DP4_DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L +#define DP4_DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L +//DP4_DP_PIXEL_FORMAT +#define DP4_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0x4 +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP4_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define DP4_DP_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00000030L +#define DP4_DP_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000700L +#define DP4_DP_PIXEL_FORMAT__COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +//DP4_DP_MSA_COLORIMETRY +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0__SHIFT 0x18 +#define DP4_DP_MSA_COLORIMETRY__DP_MSA_MISC0_MASK 0xFF000000L +//DP4_DP_CONFIG +#define DP4_DP_CONFIG__DP_UDI_LANES__SHIFT 0x0 +#define DP4_DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L +//DP4_DP_VID_STREAM_CNTL +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x8 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x10 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x14 +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L +#define DP4_DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L +//DP4_DP_STEER_FIFO +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE__SHIFT 0x0 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x1 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE__SHIFT 0x2 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x4 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x5 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x6 +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x7 +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_ENABLE_MASK 0x00000001L +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000002L +#define DP4_DP_STEER_FIFO__DP_STEER_FIFO_RESET_DONE_MASK 0x00000004L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L +#define DP4_DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L +//DP4_DP_MSA_MISC +#define DP4_DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x0 +#define DP4_DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x8 +#define DP4_DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x10 +#define DP4_DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x18 +#define DP4_DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000FFL +#define DP4_DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000FF00L +#define DP4_DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00FF0000L +#define DP4_DP_MSA_MISC__DP_MSA_MISC4_MASK 0xFF000000L +//DP4_DP_DPHY_INTERNAL_CTRL +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN__SHIFT 0x0 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_EN_MASK 0x00000001L +#define DP4_DP_DPHY_INTERNAL_CTRL__DPHY_ALT_SCRAMBLER_RESET_SEL_MASK 0x00000010L +//DP4_DP_VID_TIMING +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE__SHIFT 0x4 +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x8 +#define DP4_DP_VID_TIMING__DP_VID_M_DIV__SHIFT 0xc +#define DP4_DP_VID_TIMING__DP_VID_N_INTERVAL__SHIFT 0xe +#define DP4_DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x18 +#define DP4_DP_VID_TIMING__DP_VID_M_N_DOUBLE_BUFFER_MODE_MASK 0x00000010L +#define DP4_DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L +#define DP4_DP_VID_TIMING__DP_VID_M_DIV_MASK 0x00003000L +#define DP4_DP_VID_TIMING__DP_VID_N_INTERVAL_MASK 0x0000C000L +#define DP4_DP_VID_TIMING__DP_VID_N_DIV_MASK 0xFF000000L +//DP4_DP_VID_N +#define DP4_DP_VID_N__DP_VID_N__SHIFT 0x0 +#define DP4_DP_VID_N__DP_VID_N_MASK 0x00FFFFFFL +//DP4_DP_VID_M +#define DP4_DP_VID_M__DP_VID_M__SHIFT 0x0 +#define DP4_DP_VID_M__DP_VID_M_MASK 0x00FFFFFFL +//DP4_DP_LINK_FRAMING_CNTL +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x0 +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE__SHIFT 0x14 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x18 +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x1c +#define DP4_DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003FFFFL +#define DP4_DP_LINK_FRAMING_CNTL__DP_BACK_TO_BACK_BS_AVOIDANCE_ENABLE_MASK 0x00100000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L +#define DP4_DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L +//DP4_DP_HBR2_EYE_PATTERN +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x0 +#define DP4_DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L +//DP4_DP_VID_MSA_VBID +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x0 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE__SHIFT 0xc +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x18 +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000FFFL +#define DP4_DP_VID_MSA_VBID__DP_VID_MSA_TRANSMISSION_ENABLE_MASK 0x00001000L +#define DP4_DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L +//DP4_DP_VID_INTERRUPT_CNTL +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x0 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x1 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x2 +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L +#define DP4_DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L +//DP4_DP_DPHY_CNTL +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x0 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x1 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x2 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x3 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW__SHIFT 0x5 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS__SHIFT 0x6 +#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM__SHIFT 0x7 +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL__SHIFT 0x8 +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x10 +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x18 +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L +#define DP4_DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_READY_SHADOW_MASK 0x00000020L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_ACTIVE_STATUS_MASK 0x00000040L +#define DP4_DP_DPHY_CNTL__DPHY_FEC_DISABLE_MODE_FOR_ALPM_MASK 0x00000080L +#define DP4_DP_DPHY_CNTL__DPHY_SCRAMBLER_SEL_MASK 0x00000100L +#define DP4_DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L +#define DP4_DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L +//DP4_DP_DPHY_TRAINING_PATTERN_SEL +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x0 +#define DP4_DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L +//DP4_DP_DPHY_SYM0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x0 +#define DP4_DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0xa +#define DP4_DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x14 +#define DP4_DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM1 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x0 +#define DP4_DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0xa +#define DP4_DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x14 +#define DP4_DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000FFC00L +#define DP4_DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3FF00000L +//DP4_DP_DPHY_SYM2 +#define DP4_DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x0 +#define DP4_DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0xa +#define DP4_DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003FFL +#define DP4_DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000FFC00L +//DP4_DP_DPHY_8B10B_CNTL +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x8 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x10 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x18 +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L +#define DP4_DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L +//DP4_DP_DPHY_PRBS_CNTL +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x0 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x4 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x8 +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L +#define DP4_DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7FFFFF00L +//DP4_DP_DPHY_SCRAM_CNTL +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS__SHIFT 0x0 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE__SHIFT 0x4 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT__SHIFT 0x8 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE__SHIFT 0x18 +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_DIS_MASK 0x00000001L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_ADVANCE_MASK 0x00000010L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_BS_COUNT_MASK 0x0003FF00L +#define DP4_DP_DPHY_SCRAM_CNTL__DPHY_SCRAMBLER_KCODE_MASK 0x01000000L +//DP4_DP_DPHY_CRC_CONTROL0 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_EN_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_CONT_EN_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_CONTROL0__DPHY_CRC_FIELD_MASK 0x00000100L +//DP4_DP_DPHY_CRC_CONTROL1 +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003FL +#define DP4_DP_DPHY_CRC_CONTROL1__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003F00L +//DP4_DP_DPHY_CRC_RESULT0 +#define DP4_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT0__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_RESULT1 +#define DP4_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT1__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_RESULT2 +#define DP4_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT2__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_RESULT3 +#define DP4_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_RESULT3__DPHY_CRC_RESULT_MASK 0xFFFFFFFFL +//DP4_DP_DPHY_CRC_STATUS +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID__SHIFT 0x0 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK__SHIFT 0x4 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x8 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0xc +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x10 +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_MASK 0x00000001L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_RESULT_VALID_ACK_MASK 0x00000010L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000100L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00001000L +#define DP4_DP_DPHY_CRC_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L +//DP4_DP_TU_CNTL +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG__SHIFT 0x8 +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_ACK__SHIFT 0xc +#define DP4_DP_TU_CNTL__DP_TU_SIZE__SHIFT 0x18 +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L +#define DP4_DP_TU_CNTL__DP_TU_OVERFLOW_ACK_MASK 0x00001000L +#define DP4_DP_TU_CNTL__DP_TU_SIZE_MASK 0x3F000000L +//DP4_DP_PIXEL_FORMAT_DB_CNTL +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE__SHIFT 0x0 +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING__SHIFT 0x4 +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_ENABLE_MASK 0x00000001L +#define DP4_DP_PIXEL_FORMAT_DB_CNTL__PIXEL_FORMAT_DB_PENDING_MASK 0x00000010L +//DP4_DP_SEC_CNTL +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0xc +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP4_ENABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP5_ENABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP6_ENABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL__DP_SEC_GSP7_ENABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL1 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND__SHIFT 0x5 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING__SHIFT 0x6 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED__SHIFT 0x7 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE__SHIFT 0xa +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE__SHIFT 0xb +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE__SHIFT 0xc +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE__SHIFT 0xd +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE__SHIFT 0xe +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_MASK 0x00000020L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_PENDING_MASK 0x00000040L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_DEADLINE_MISSED_MASK 0x00000080L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP1_LINE_REFERENCE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP2_LINE_REFERENCE_MASK 0x00000400L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP3_LINE_REFERENCE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP4_LINE_REFERENCE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP5_LINE_REFERENCE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP6_LINE_REFERENCE_MASK 0x00004000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP7_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL1__DP_SEC_GSP0_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING1 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000FFFL +#define DP4_DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING2 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000FFFFL +#define DP4_DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING3 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x10 +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003FFFL +#define DP4_DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xFFFF0000L +//DP4_DP_SEC_FRAMING4 +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING__SHIFT 0x0 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x14 +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x18 +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x1c +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP4_DP_SEC_FRAMING4__DP_SST_SDP_SPLITTING_MASK 0x00000001L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L +#define DP4_DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP4_DP_SEC_AUD_N +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_N_READBACK +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00FFFFFFL +//DP4_DP_SEC_AUD_M_READBACK +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x0 +#define DP4_DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00FFFFFFL +//DP4_DP_SEC_TIMESTAMP +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x0 +#define DP4_DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L +//DP4_DP_SEC_PACKET_CNTL +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x4 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER__SHIFT 0x18 +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L +#define DP4_DP_SEC_PACKET_CNTL__DP_SEC_ATP_VERSION_NUMBER_MASK 0x3F000000L +//DP4_DP_MSE_RATE_CNTL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x0 +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x1a +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03FFFFFFL +#define DP4_DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xFC000000L +//DP4_DP_MSE_RATE_UPDATE +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x0 +#define DP4_DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L +//DP4_DP_MSE_SAT0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x0 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0__SHIFT 0x4 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0__SHIFT 0x5 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x8 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x10 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1__SHIFT 0x14 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1__SHIFT 0x15 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x18 +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT0_MASK 0x00000010L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE0_MASK 0x00000020L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPT1_MASK 0x00100000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_ENCRYPTION_TYPE1_MASK 0x00200000L +#define DP4_DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3F000000L +//DP4_DP_MSE_SAT1 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x0 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2__SHIFT 0x4 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2__SHIFT 0x5 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x8 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x10 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3__SHIFT 0x14 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3__SHIFT 0x15 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x18 +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT2_MASK 0x00000010L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE2_MASK 0x00000020L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPT3_MASK 0x00100000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_ENCRYPTION_TYPE3_MASK 0x00200000L +#define DP4_DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3F000000L +//DP4_DP_MSE_SAT2 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x0 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4__SHIFT 0x4 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4__SHIFT 0x5 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x8 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x10 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5__SHIFT 0x14 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5__SHIFT 0x15 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x18 +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT4_MASK 0x00000010L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE4_MASK 0x00000020L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPT5_MASK 0x00100000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_ENCRYPTION_TYPE5_MASK 0x00200000L +#define DP4_DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3F000000L +//DP4_DP_MSE_SAT_UPDATE +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x0 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x8 +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L +#define DP4_DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L +//DP4_DP_MSE_LINK_TIMING +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x0 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x10 +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003FFL +#define DP4_DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L +//DP4_DP_MSE_MISC_CNTL +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x0 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x4 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x8 +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L +#define DP4_DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L +//DP4_DP_DPHY_BS_SR_SWAP_CNTL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT__SHIFT 0x0 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE__SHIFT 0xf +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START__SHIFT 0x10 +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_MASK 0x000003FFL +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_BS_SR_SWAP_DONE_MASK 0x00008000L +#define DP4_DP_DPHY_BS_SR_SWAP_CNTL__DPHY_LOAD_BS_COUNT_START_MASK 0x00010000L +//DP4_DP_DPHY_HBR2_PATTERN_CONTROL +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL__SHIFT 0x0 +#define DP4_DP_DPHY_HBR2_PATTERN_CONTROL__DP_DPHY_HBR2_PATTERN_CONTROL_MASK 0x00000007L +//DP4_DP_MSE_SAT0_STATUS +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS__SHIFT 0x5 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS__SHIFT 0x15 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC0_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT0_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE0_STATUS_MASK 0x00000020L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT0_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SRC1_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPT1_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE1_STATUS_MASK 0x00200000L +#define DP4_DP_MSE_SAT0_STATUS__DP_MSE_SAT_SLOT_COUNT1_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT1_STATUS +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS__SHIFT 0x5 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS__SHIFT 0x15 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC2_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT2_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE2_STATUS_MASK 0x00000020L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT2_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SRC3_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPT3_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE3_STATUS_MASK 0x00200000L +#define DP4_DP_MSE_SAT1_STATUS__DP_MSE_SAT_SLOT_COUNT3_STATUS_MASK 0x3F000000L +//DP4_DP_MSE_SAT2_STATUS +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS__SHIFT 0x0 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS__SHIFT 0x4 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS__SHIFT 0x5 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS__SHIFT 0x8 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS__SHIFT 0x10 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS__SHIFT 0x14 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS__SHIFT 0x15 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS__SHIFT 0x18 +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC4_STATUS_MASK 0x00000007L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT4_STATUS_MASK 0x00000010L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE4_STATUS_MASK 0x00000020L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT4_STATUS_MASK 0x00003F00L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SRC5_STATUS_MASK 0x00070000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPT5_STATUS_MASK 0x00100000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_ENCRYPTION_TYPE5_STATUS_MASK 0x00200000L +#define DP4_DP_MSE_SAT2_STATUS__DP_MSE_SAT_SLOT_COUNT5_STATUS_MASK 0x3F000000L +//DP4_DP_HBLANK_CONTROL +#define DP4_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP4_DP_HBLANK_CONTROL__DP_HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP4_DP_MSA_TIMING_PARAM1 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_VTOTAL_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM1__DP_MSA_HTOTAL_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM2 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_VSTART_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM2__DP_MSA_HSTART_MASK 0xFFFF0000L +//DP4_DP_MSA_TIMING_PARAM3 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY__SHIFT 0xf +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY__SHIFT 0x1f +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCWIDTH_MASK 0x00007FFFL +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_VSYNCPOLARITY_MASK 0x00008000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCWIDTH_MASK 0x7FFF0000L +#define DP4_DP_MSA_TIMING_PARAM3__DP_MSA_HSYNCPOLARITY_MASK 0x80000000L +//DP4_DP_MSA_TIMING_PARAM4 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT__SHIFT 0x0 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH__SHIFT 0x10 +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_VHEIGHT_MASK 0x0000FFFFL +#define DP4_DP_MSA_TIMING_PARAM4__DP_MSA_HWIDTH_MASK 0xFFFF0000L +//DP4_DP_MSO_CNTL +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK__SHIFT 0x0 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE__SHIFT 0x18 +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL__DP_MSO_NUM_OF_SSTLINK_MASK 0x00000003L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_STREAM_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ASP_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ATP_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_AIP_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_ACM_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP0_ENABLE_MASK 0x0F000000L +#define DP4_DP_MSO_CNTL__DP_MSO_SEC_GSP1_ENABLE_MASK 0xF0000000L +//DP4_DP_MSO_CNTL1 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE__SHIFT 0x0 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE__SHIFT 0x4 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE__SHIFT 0x8 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE__SHIFT 0xc +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE__SHIFT 0x10 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE__SHIFT 0x14 +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE__SHIFT 0x1c +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP2_ENABLE_MASK 0x0000000FL +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP3_ENABLE_MASK 0x000000F0L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP4_ENABLE_MASK 0x00000F00L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP5_ENABLE_MASK 0x0000F000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP6_ENABLE_MASK 0x000F0000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_GSP7_ENABLE_MASK 0x00F00000L +#define DP4_DP_MSO_CNTL1__DP_MSO_SEC_ISRC_ENABLE_MASK 0xF0000000L +//DP4_DP_STEER_FIFO_CNTL +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN__SHIFT 0x8 +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE__SHIFT 0x10 +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_FIFO_COMPRESSED_LOW_GRANULARITY_MODE_EN_MASK 0x00000100L +#define DP4_DP_STEER_FIFO_CNTL__DP_STEER_OUTPUT_PIXEL_PER_CYCLE_MASK 0x00030000L +//DP4_DP_SEC_CNTL2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND__SHIFT 0x0 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING__SHIFT 0x1 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED__SHIFT 0x2 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE__SHIFT 0x3 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND__SHIFT 0x4 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING__SHIFT 0x5 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED__SHIFT 0x6 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE__SHIFT 0x7 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND__SHIFT 0x8 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING__SHIFT 0x9 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED__SHIFT 0xa +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE__SHIFT 0xb +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND__SHIFT 0xc +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING__SHIFT 0xd +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE__SHIFT 0xf +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND__SHIFT 0x10 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING__SHIFT 0x11 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED__SHIFT 0x12 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND__SHIFT 0x14 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING__SHIFT 0x15 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED__SHIFT 0x16 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND__SHIFT 0x18 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING__SHIFT 0x19 +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED__SHIFT 0x1a +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS__SHIFT 0x1c +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_MASK 0x00000001L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_PENDING_MASK 0x00000002L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_DEADLINE_MISSED_MASK 0x00000004L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP1_SEND_ANY_LINE_MASK 0x00000008L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_MASK 0x00000010L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_PENDING_MASK 0x00000020L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_DEADLINE_MISSED_MASK 0x00000040L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP2_SEND_ANY_LINE_MASK 0x00000080L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_MASK 0x00000100L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_PENDING_MASK 0x00000200L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_DEADLINE_MISSED_MASK 0x00000400L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP3_SEND_ANY_LINE_MASK 0x00000800L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_MASK 0x00001000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_PENDING_MASK 0x00002000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP4_SEND_ANY_LINE_MASK 0x00008000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_MASK 0x00010000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_PENDING_MASK 0x00020000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_DEADLINE_MISSED_MASK 0x00040000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP5_SEND_ANY_LINE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_MASK 0x00100000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_PENDING_MASK 0x00200000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_DEADLINE_MISSED_MASK 0x00400000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP6_SEND_ANY_LINE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_MASK 0x01000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_PENDING_MASK 0x02000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_DEADLINE_MISSED_MASK 0x04000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP7_SEND_ANY_LINE_MASK 0x08000000L +#define DP4_DP_SEC_CNTL2__DP_SEC_GSP11_PPS_MASK 0x10000000L +//DP4_DP_SEC_CNTL3 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP1_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL3__DP_SEC_GSP2_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL4 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP3_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL4__DP_SEC_GSP4_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL5 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP5_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL5__DP_SEC_GSP6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_CNTL6 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM__SHIFT 0x0 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE__SHIFT 0x12 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE__SHIFT 0x13 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE__SHIFT 0x16 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE__SHIFT 0x17 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE__SHIFT 0x1a +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE__SHIFT 0x1b +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP0_EN_DB_DISABLE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP1_EN_DB_DISABLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP2_EN_DB_DISABLE_MASK 0x00040000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP3_EN_DB_DISABLE_MASK 0x00080000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP4_EN_DB_DISABLE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP5_EN_DB_DISABLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP6_EN_DB_DISABLE_MASK 0x00400000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP7_EN_DB_DISABLE_MASK 0x00800000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP8_EN_DB_DISABLE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP9_EN_DB_DISABLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP10_EN_DB_DISABLE_MASK 0x04000000L +#define DP4_DP_SEC_CNTL6__DP_SEC_GSP11_EN_DB_DISABLE_MASK 0x08000000L +//DP4_DP_SEC_CNTL7 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE__SHIFT 0x0 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE__SHIFT 0x1 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE__SHIFT 0x4 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE__SHIFT 0x5 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE__SHIFT 0x8 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE__SHIFT 0x9 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE__SHIFT 0xc +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE__SHIFT 0xd +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE__SHIFT 0x10 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE__SHIFT 0x11 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE__SHIFT 0x14 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE__SHIFT 0x15 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE__SHIFT 0x18 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE__SHIFT 0x19 +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE__SHIFT 0x1c +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE__SHIFT 0x1d +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_ACTIVE_MASK 0x00000001L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP0_SEND_IN_IDLE_MASK 0x00000002L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_ACTIVE_MASK 0x00000010L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP1_SEND_IN_IDLE_MASK 0x00000020L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_ACTIVE_MASK 0x00000100L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP2_SEND_IN_IDLE_MASK 0x00000200L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_ACTIVE_MASK 0x00001000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP3_SEND_IN_IDLE_MASK 0x00002000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_ACTIVE_MASK 0x00010000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP4_SEND_IN_IDLE_MASK 0x00020000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_ACTIVE_MASK 0x00100000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP5_SEND_IN_IDLE_MASK 0x00200000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_ACTIVE_MASK 0x01000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP6_SEND_IN_IDLE_MASK 0x02000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_ACTIVE_MASK 0x10000000L +#define DP4_DP_SEC_CNTL7__DP_SEC_GSP7_SEND_IN_IDLE_MASK 0x20000000L +//DP4_DP_DB_CNTL +#define DP4_DP_DB_CNTL__DP_DB_PENDING__SHIFT 0x0 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN__SHIFT 0x4 +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR__SHIFT 0x5 +#define DP4_DP_DB_CNTL__DP_DB_LOCK__SHIFT 0x8 +#define DP4_DP_DB_CNTL__DP_DB_DISABLE__SHIFT 0xc +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING__SHIFT 0xf +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN__SHIFT 0x10 +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR__SHIFT 0x11 +#define DP4_DP_DB_CNTL__DP_DB_PENDING_MASK 0x00000001L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_MASK 0x00000010L +#define DP4_DP_DB_CNTL__DP_DB_TAKEN_CLR_MASK 0x00000020L +#define DP4_DP_DB_CNTL__DP_DB_LOCK_MASK 0x00000100L +#define DP4_DP_DB_CNTL__DP_DB_DISABLE_MASK 0x00001000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_PENDING_MASK 0x00008000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_MASK 0x00010000L +#define DP4_DP_DB_CNTL__DP_VUPDATE_DB_TAKEN_CLR_MASK 0x00020000L +//DP4_DP_MSA_VBID_MISC +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE__SHIFT 0x0 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x4 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE__SHIFT 0x8 +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE__SHIFT 0x9 +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN__SHIFT 0xc +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN__SHIFT 0xd +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM__SHIFT 0x10 +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_MASK 0x00000003L +#define DP4_DP_MSA_VBID_MISC__DP_MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000010L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_MASK 0x00000100L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_MASK 0x00000200L +#define DP4_DP_MSA_VBID_MISC__DP_VBID1_OVERRIDE_EN_MASK 0x00001000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID2_OVERRIDE_EN_MASK 0x00002000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_MSA_VBID_MISC__DP_VBID6_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_SEC_METADATA_TRANSMISSION +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x1 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE__SHIFT 0x4 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE__SHIFT 0x10 +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000002L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_MSO_METADATA_PACKET_ENABLE_MASK 0x000000F0L +#define DP4_DP_SEC_METADATA_TRANSMISSION__DP_SEC_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//DP4_DP_ALPM_CNTL +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND__SHIFT 0x0 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING__SHIFT 0x1 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND__SHIFT 0x2 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING__SHIFT 0x3 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO__SHIFT 0x5 +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE__SHIFT 0x6 +#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP__SHIFT 0x7 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM__SHIFT 0x8 +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS__SHIFT 0xb +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN__SHIFT 0xc +#define DP4_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE__SHIFT 0xf +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM__SHIFT 0x10 +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_SEND_MASK 0x00000001L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PENDING_MASK 0x00000002L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_SEND_MASK 0x00000004L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_STANDBY_PENDING_MASK 0x00000008L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_ALPM_CNTL__DP_LINK_TRAINING_SWITCH_BETWEEN_VIDEO_MASK 0x00000020L +#define DP4_DP_ALPM_CNTL__DP_ALPM_SLEEP_SEQUENCE_MODE_MASK 0x00000040L +#define DP4_DP_ALPM_CNTL__DP_STOP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_MASK 0x00000080L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_PATTERN_NUM_MASK 0x00000300L +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_STATUS_MASK 0x00000800L +#define DP4_DP_ALPM_CNTL__DP_FORCE_SCRAMBLED_ZERO_AFTER_SLEEP_EN_MASK 0x00001000L +#define DP4_DP_ALPM_CNTL__DP_ALPM_LINE_REFERENCE_MASK 0x00008000L +#define DP4_DP_ALPM_CNTL__DP_ML_PHY_SLEEP_STANDBY_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP8_CNTL +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND__SHIFT 0x7 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP8_CNTL__DP_MSO_SEC_GSP8_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_MASK 0x00000080L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP8_CNTL__DP_SEC_GSP8_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP9_CNTL +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND__SHIFT 0x7 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP9_CNTL__DP_MSO_SEC_GSP9_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_MASK 0x00000080L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP9_CNTL__DP_SEC_GSP9_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP10_CNTL +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND__SHIFT 0x7 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP10_CNTL__DP_MSO_SEC_GSP10_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_MASK 0x00000080L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP10_CNTL__DP_SEC_GSP10_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP11_CNTL +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE__SHIFT 0x0 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE__SHIFT 0x4 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE__SHIFT 0x5 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE__SHIFT 0x6 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND__SHIFT 0x7 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE__SHIFT 0x8 +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING__SHIFT 0xc +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE__SHIFT 0xd +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED__SHIFT 0xe +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM__SHIFT 0x10 +#define DP4_DP_GSP11_CNTL__DP_MSO_SEC_GSP11_ENABLE_MASK 0x0000000FL +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_ENABLE_MASK 0x00000010L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_REFERENCE_MASK 0x00000020L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_IN_IDLE_MASK 0x00000040L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_MASK 0x00000080L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ANY_LINE_MASK 0x00000100L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_PENDING_MASK 0x00001000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_ACTIVE_MASK 0x00002000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_SEND_DEADLINE_MISSED_MASK 0x00004000L +#define DP4_DP_GSP11_CNTL__DP_SEC_GSP11_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_GSP_EN_DB_STATUS +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING__SHIFT 0x0 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING__SHIFT 0x1 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING__SHIFT 0x2 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING__SHIFT 0x3 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING__SHIFT 0x4 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING__SHIFT 0x5 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING__SHIFT 0x6 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING__SHIFT 0x7 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING__SHIFT 0x8 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING__SHIFT 0x9 +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING__SHIFT 0xa +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING__SHIFT 0xb +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP0_EN_DB_PENDING_MASK 0x00000001L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP1_EN_DB_PENDING_MASK 0x00000002L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP2_EN_DB_PENDING_MASK 0x00000004L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP3_EN_DB_PENDING_MASK 0x00000008L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP4_EN_DB_PENDING_MASK 0x00000010L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP5_EN_DB_PENDING_MASK 0x00000020L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP6_EN_DB_PENDING_MASK 0x00000040L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP7_EN_DB_PENDING_MASK 0x00000080L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP8_EN_DB_PENDING_MASK 0x00000100L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP9_EN_DB_PENDING_MASK 0x00000200L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP10_EN_DB_PENDING_MASK 0x00000400L +#define DP4_DP_GSP_EN_DB_STATUS__DP_SEC_GSP11_EN_DB_PENDING_MASK 0x00000800L +//DP4_DP_AUXLESS_ALPM_CNTL1 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT__SHIFT 0x4 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL__SHIFT 0x14 +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE__SHIFT 0x1f +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_REPEAT_MASK 0x000000F0L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_DELAY_MASK 0x0007FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_ML_PHY_SLEEP_INTERVAL_MASK 0x1FF00000L +#define DP4_DP_AUXLESS_ALPM_CNTL1__DP_SET_AUXLESS_ALPM_SLEEP_STATE_MASK 0x80000000L +//DP4_DP_AUXLESS_ALPM_CNTL2 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND__SHIFT 0x7 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING__SHIFT 0x11 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE__SHIFT 0x12 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING__SHIFT 0x13 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD__SHIFT 0x14 +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ML_PHY_SLEEP_HOLD_TIME_MASK 0x0000007FL +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_SEND_MASK 0x00000080L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_IMMEDIATE_MASK 0x00010000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_WAKEUP_PENDING_MASK 0x00020000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_IMMEDIATE_MASK 0x00040000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_FEC_EN_PENDING_MASK 0x00080000L +#define DP4_DP_AUXLESS_ALPM_CNTL2__DP_ALPM_ML_PHY_LOCK_PERIOD_MASK 0x3FF00000L +//DP4_DP_AUXLESS_ALPM_CNTL3 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_WAKEUP_LINE_NUM_MASK 0x0000FFFFL +#define DP4_DP_AUXLESS_ALPM_CNTL3__DP_ALPM_FEC_EN_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_AUXLESS_ALPM_CNTL4 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN__SHIFT 0x1 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL__SHIFT 0x2 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME__SHIFT 0x3 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE__SHIFT 0x4 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS__SHIFT 0x5 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE__SHIFT 0x6 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM__SHIFT 0x18 +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_MASK 0x00000002L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_SLEEP_PATTERN_SEL_MASK 0x00000004L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FORCE_WAKEUP_NEXT_FRAME_MASK 0x00000008L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_DIS_IMMEDIATE_MASK 0x00000010L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_HW_MODE_EN_STATUS_MASK 0x00000020L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_CURRENT_STATE_MASK 0x00000040L +#define DP4_DP_AUXLESS_ALPM_CNTL4__DP_ALPM_FRAME_NUM_MASK 0xFF000000L +//DP4_DP_AUXLESS_ALPM_CNTL5 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK__SHIFT 0x0 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED__SHIFT 0x1 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS__SHIFT 0x2 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR__SHIFT 0x3 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM__SHIFT 0x8 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM__SHIFT 0x10 +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_MASK_MASK 0x00000001L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_OCCURRED_MASK 0x00000002L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_STATUS_MASK 0x00000004L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_CLEAR_MASK 0x00000008L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_FRAME_NUM_MASK 0x0000FF00L +#define DP4_DP_AUXLESS_ALPM_CNTL5__DP_ALPM_WAKEUP_INTERRUPT_LINE_NUM_MASK 0xFFFF0000L +//DP4_DP_STREAM_SYMBOL_COUNT_STATUS +#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT__SHIFT 0x0 +#define DP4_DP_STREAM_SYMBOL_COUNT_STATUS__DP_STREAM_BS_COUNT_MASK 0x0000FFFFL +//DP4_DP_STREAM_SYMBOL_COUNT_CONTROL +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE__SHIFT 0x0 +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET__SHIFT 0x4 +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_ENABLE_MASK 0x00000001L +#define DP4_DP_STREAM_SYMBOL_COUNT_CONTROL__DP_STREAM_BS_COUNT_RESET_MASK 0x00000010L +//DP4_DP_LINK_SYMBOL_COUNT_STATUS0 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT__SHIFT 0x0 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS0__DP_LINK_SR_COUNT_MASK 0x0000FFFFL +//DP4_DP_LINK_SYMBOL_COUNT_STATUS1 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT__SHIFT 0x0 +#define DP4_DP_LINK_SYMBOL_COUNT_STATUS1__DP_LINK_CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP4_DP_LINK_SYMBOL_COUNT_CONTROL +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE__SHIFT 0x0 +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET__SHIFT 0x4 +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE__SHIFT 0x8 +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET__SHIFT 0xc +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_ENABLE_MASK 0x00000001L +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_SR_COUNT_RESET_MASK 0x00000010L +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_ENABLE_MASK 0x00000100L +#define DP4_DP_LINK_SYMBOL_COUNT_CONTROL__DP_LINK_CYCLE_COUNT_RESET_MASK 0x00001000L +//DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING__SHIFT 0x8 +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP4_DP_SYM8_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_PENDING_MASK 0x00000100L +//DP4_DP_DPHY_FAST_TRAINING +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x1 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x2 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x14 +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_STREAM_RESET_DURING_FAST_TRAINING_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000FFF00L +#define DP4_DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xFFF00000L +//DP4_DP_DPHY_FAST_TRAINING_STATUS +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x0 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x4 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x8 +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0xc +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L +#define DP4_DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec +//DSC_TOP0_DSC_TOP_CONTROL +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP0_DSC_DEBUG_CONTROL +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP0_DSC_SPARE_DEBUG +#define DSC_TOP0_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP0_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP0_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec +//DSCCIF0_DSCCIF_CONFIG0 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF0_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF0_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF0_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec +//DSCC0_DSCC_CONFIG0 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC0_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC0_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC0_DSCC_CONFIG1 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC0_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC0_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC0_DSCC_CONFIG2 +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC0_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC0_DSCC_STATUS +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC0_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC0_DSCC_INTERRUPT_CONTROL0 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC0_DSCC_INTERRUPT_CONTROL1 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC0_DSCC_INTERRUPT_STATUS0 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC0_DSCC_INTERRUPT_STATUS1 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC0_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC0_DSCC_PPS_CONFIG0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC0_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG1 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC0_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC0_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC0_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC0_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC0_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG2 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG3 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG4 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC0_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG5 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC0_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG6 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC0_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC0_DSCC_PPS_CONFIG7 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG8 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG9 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC0_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC0_DSCC_PPS_CONFIG11 +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC0_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC0_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC0_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC0_DSCC_PPS_CONFIG12 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG13 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG14 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC0_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC0_DSCC_PPS_CONFIG15 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC0_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG16 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG17 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG18 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG19 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG20 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG21 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC0_DSCC_PPS_CONFIG22 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC0_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC0_DSCC_MEM_POWER_CONTROL0 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC0_DSCC_MEM_POWER_CONTROL1 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC0_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC0_DSCC_MAX_ABS_ERROR0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC0_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC0_DSCC_MAX_ABS_ERROR1 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC0_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC0_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC0_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC0_DSCC_TEST_DEBUG_INDEX0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_INDEX1 +#define DSCC0_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_INDEX2 +#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_INDEX3 +#define DSCC0_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC0_DSCC_TEST_DEBUG_DATA0 +#define DSCC0_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC0_DSCC_TEST_DEBUG_DATA1 +#define DSCC0_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC0_DSCC_TEST_DEBUG_DATA2 +#define DSCC0_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC0_DSCC_TEST_DEBUG_DATA3 +#define DSCC0_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC0_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC0_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON17_PERFCOUNTER_CNTL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_CNTL2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON17_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFCOUNTER_STATE +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON17_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON17_PERFMON_CNTL +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON17_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON17_PERFMON_CNTL2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON17_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON17_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON17_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON17_PERFMON_CVALUE_LOW +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON17_PERFMON_HI +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON17_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON17_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON17_PERFMON_LOW +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON17_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec +//DSC_TOP1_DSC_TOP_CONTROL +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP1_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP1_DSC_DEBUG_CONTROL +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP1_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP1_DSC_SPARE_DEBUG +#define DSC_TOP1_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP1_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP1_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP1_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec +//DSCCIF1_DSCCIF_CONFIG0 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF1_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF1_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF1_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec +//DSCC1_DSCC_CONFIG0 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC1_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC1_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC1_DSCC_CONFIG1 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC1_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC1_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC1_DSCC_CONFIG2 +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC1_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC1_DSCC_STATUS +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC1_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC1_DSCC_INTERRUPT_CONTROL0 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC1_DSCC_INTERRUPT_CONTROL1 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC1_DSCC_INTERRUPT_STATUS0 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC1_DSCC_INTERRUPT_STATUS1 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC1_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC1_DSCC_PPS_CONFIG0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC1_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG1 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC1_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC1_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC1_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC1_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC1_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG2 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG3 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG4 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC1_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG5 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC1_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG6 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC1_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC1_DSCC_PPS_CONFIG7 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG8 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG9 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC1_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC1_DSCC_PPS_CONFIG11 +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC1_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC1_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC1_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC1_DSCC_PPS_CONFIG12 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG13 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG14 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC1_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC1_DSCC_PPS_CONFIG15 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC1_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG16 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG17 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG18 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG19 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG20 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG21 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC1_DSCC_PPS_CONFIG22 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC1_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC1_DSCC_MEM_POWER_CONTROL0 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC1_DSCC_MEM_POWER_CONTROL1 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC1_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC1_DSCC_MAX_ABS_ERROR0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC1_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC1_DSCC_MAX_ABS_ERROR1 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC1_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC1_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC1_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC1_DSCC_TEST_DEBUG_INDEX0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_INDEX1 +#define DSCC1_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_INDEX2 +#define DSCC1_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_INDEX3 +#define DSCC1_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC1_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC1_DSCC_TEST_DEBUG_DATA0 +#define DSCC1_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC1_DSCC_TEST_DEBUG_DATA1 +#define DSCC1_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC1_DSCC_TEST_DEBUG_DATA2 +#define DSCC1_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC1_DSCC_TEST_DEBUG_DATA3 +#define DSCC1_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC1_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC1_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON18_PERFCOUNTER_CNTL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_CNTL2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON18_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFCOUNTER_STATE +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON18_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON18_PERFMON_CNTL +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON18_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON18_PERFMON_CNTL2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON18_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON18_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON18_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON18_PERFMON_CVALUE_LOW +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON18_PERFMON_HI +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON18_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON18_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON18_PERFMON_LOW +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON18_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec +//DSC_TOP2_DSC_TOP_CONTROL +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP2_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP2_DSC_DEBUG_CONTROL +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP2_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP2_DSC_SPARE_DEBUG +#define DSC_TOP2_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP2_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP2_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP2_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec +//DSCCIF2_DSCCIF_CONFIG0 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF2_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF2_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF2_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec +//DSCC2_DSCC_CONFIG0 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC2_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC2_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC2_DSCC_CONFIG1 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC2_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC2_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC2_DSCC_CONFIG2 +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC2_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC2_DSCC_STATUS +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC2_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC2_DSCC_INTERRUPT_CONTROL0 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC2_DSCC_INTERRUPT_CONTROL1 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC2_DSCC_INTERRUPT_STATUS0 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC2_DSCC_INTERRUPT_STATUS1 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC2_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC2_DSCC_PPS_CONFIG0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC2_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG1 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC2_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC2_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC2_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC2_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC2_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG2 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG3 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG4 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC2_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG5 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC2_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG6 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC2_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC2_DSCC_PPS_CONFIG7 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG8 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG9 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC2_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC2_DSCC_PPS_CONFIG11 +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC2_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC2_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC2_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC2_DSCC_PPS_CONFIG12 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG13 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG14 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC2_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC2_DSCC_PPS_CONFIG15 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC2_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG16 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG17 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG18 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG19 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG20 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG21 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC2_DSCC_PPS_CONFIG22 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC2_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC2_DSCC_MEM_POWER_CONTROL0 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC2_DSCC_MEM_POWER_CONTROL1 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC2_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC2_DSCC_MAX_ABS_ERROR0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC2_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC2_DSCC_MAX_ABS_ERROR1 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC2_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC2_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC2_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC2_DSCC_TEST_DEBUG_INDEX0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_INDEX1 +#define DSCC2_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_INDEX2 +#define DSCC2_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_INDEX3 +#define DSCC2_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC2_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC2_DSCC_TEST_DEBUG_DATA0 +#define DSCC2_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC2_DSCC_TEST_DEBUG_DATA1 +#define DSCC2_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC2_DSCC_TEST_DEBUG_DATA2 +#define DSCC2_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC2_DSCC_TEST_DEBUG_DATA3 +#define DSCC2_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC2_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC2_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON19_PERFCOUNTER_CNTL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_CNTL2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON19_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFCOUNTER_STATE +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON19_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON19_PERFMON_CNTL +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON19_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON19_PERFMON_CNTL2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON19_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON19_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON19_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON19_PERFMON_CVALUE_LOW +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON19_PERFMON_HI +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON19_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON19_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON19_PERFMON_LOW +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON19_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec +//DSC_TOP3_DSC_TOP_CONTROL +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS__SHIFT 0x4 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS__SHIFT 0xc +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN__SHIFT 0x10 +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_CLOCK_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DISPCLK_R_GATE_DIS_MASK 0x00000010L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK 0x00000100L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_FGCG_REP_DIS_MASK 0x00001000L +#define DSC_TOP3_DSC_TOP_CONTROL__DSC_DSCCLK_DYNAMIC_CLOCK_GATE_EN_MASK 0x00010000L +//DSC_TOP3_DSC_DEBUG_CONTROL +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT 0x0 +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT 0x4 +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK 0x00000001L +#define DSC_TOP3_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK 0x00000070L +//DSC_TOP3_DSC_SPARE_DEBUG +#define DSC_TOP3_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG__SHIFT 0x0 +#define DSC_TOP3_DSC_SPARE_DEBUG__DSC_SPARE_DEBUG_MASK 0xFFFFFFFFL +//DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE__SHIFT 0x8 +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_INDEX__DSC_TOP_TEST_DEBUG_BUS_ROTATE_MASK 0x00001F00L +//DSC_TOP3_DSC_TOP_TEST_DEBUG_DATA +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA__SHIFT 0x0 +#define DSC_TOP3_DSC_TOP_TEST_DEBUG_DATA__DSC_TOP_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec +//DSCCIF3_DSCCIF_CONFIG0 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT__SHIFT 0xc +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x10 +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x18 +#define DSCCIF3_DSCCIF_CONFIG0__INPUT_PIXEL_FORMAT_MASK 0x00007000L +#define DSCCIF3_DSCCIF_CONFIG0__BITS_PER_COMPONENT_MASK 0x000F0000L +#define DSCCIF3_DSCCIF_CONFIG0__DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000L + + +// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec +//DSCC3_DSCC_CONFIG0 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE__SHIFT 0x4 +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN__SHIFT 0x8 +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_PER_LINE_MASK 0x00000030L +#define DSCC3_DSCC_CONFIG0__ALTERNATE_ICH_ENCODING_EN_MASK 0x00000100L +#define DSCC3_DSCC_CONFIG0__NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION_MASK 0xFFFF0000L +//DSCC3_DSCC_CONFIG1 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH__SHIFT 0x18 +#define DSCC3_DSCC_CONFIG1__DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE_MASK 0x0003FFFFL +#define DSCC3_DSCC_CONFIG1__DSCC_DISABLE_ICH_MASK 0x01000000L +//DSCC3_DSCC_CONFIG2 +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD__SHIFT 0x0 +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD__SHIFT 0x10 +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_ELASTICITY_THRESHOLD_MASK 0x0000FFFFL +#define DSCC3_DSCC_CONFIG2__OUTPUT_BUFFER_TOTAL_PIXEL_COUNT_THRESHOLD_MASK 0xFFFF0000L +//DSCC3_DSCC_STATUS +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x0 +#define DSCC3_DSCC_STATUS__DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x00000001L +//DSCC3_DSCC_INTERRUPT_CONTROL0 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +//DSCC3_DSCC_INTERRUPT_CONTROL1 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED_INT_EN3_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN0_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN1_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN2_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED_INT_EN3_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_CONTROL1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_INT_EN_MASK 0x00000100L +//DSCC3_DSCC_INTERRUPT_STATUS0 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_STATUS0__DSCC_RATE_CONTROL_BUFFER_MODEL_OVERFLOW_CLEAR3_MASK 0x00080000L +//DSCC3_DSCC_INTERRUPT_STATUS1 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0__SHIFT 0x0 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1__SHIFT 0x1 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2__SHIFT 0x2 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3__SHIFT 0x3 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0__SHIFT 0x4 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1__SHIFT 0x5 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2__SHIFT 0x6 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3__SHIFT 0x7 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED__SHIFT 0x8 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0__SHIFT 0x10 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1__SHIFT 0x11 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2__SHIFT 0x12 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3__SHIFT 0x13 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0__SHIFT 0x14 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1__SHIFT 0x15 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2__SHIFT 0x16 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3__SHIFT 0x17 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR__SHIFT 0x18 +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED0_MASK 0x00000001L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED1_MASK 0x00000002L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED2_MASK 0x00000004L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_OCCURRED3_MASK 0x00000008L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED0_MASK 0x00000010L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED1_MASK 0x00000020L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED2_MASK 0x00000040L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_OCCURRED3_MASK 0x00000080L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_OCCURRED_MASK 0x00000100L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR0_MASK 0x00010000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR1_MASK 0x00020000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR2_MASK 0x00040000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_OVERFLOW_CLEAR3_MASK 0x00080000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR0_MASK 0x00100000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR1_MASK 0x00200000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR2_MASK 0x00400000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_OUTPUT_BUFFER_UNDERFLOW_CLEAR3_MASK 0x00800000L +#define DSCC3_DSCC_INTERRUPT_STATUS1__DSCC_END_OF_FRAME_NOT_REACHED_CLEAR_MASK 0x01000000L +//DSCC3_DSCC_PPS_CONFIG0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR__SHIFT 0x4 +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MINOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG0__DSC_VERSION_MAJOR_MASK 0x000000F0L +#define DSCC3_DSCC_PPS_CONFIG0__PPS_IDENTIFIER_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG0__LINEBUF_DEPTH_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG0__BITS_PER_COMPONENT_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG1 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422__SHIFT 0xb +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB__SHIFT 0xc +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE__SHIFT 0xd +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422__SHIFT 0xe +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420__SHIFT 0xf +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG1__BITS_PER_PIXEL_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG1__VBR_ENABLE_MASK 0x00000400L +#define DSCC3_DSCC_PPS_CONFIG1__SIMPLE_422_MASK 0x00000800L +#define DSCC3_DSCC_PPS_CONFIG1__CONVERT_RGB_MASK 0x00001000L +#define DSCC3_DSCC_PPS_CONFIG1__BLOCK_PRED_ENABLE_MASK 0x00002000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_422_MASK 0x00004000L +#define DSCC3_DSCC_PPS_CONFIG1__NATIVE_420_MASK 0x00008000L +#define DSCC3_DSCC_PPS_CONFIG1__CHUNK_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG2 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG2__PIC_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG2__PIC_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG3 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_WIDTH_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG3__SLICE_HEIGHT_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG4 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_XMIT_DELAY_MASK 0x000003FFL +#define DSCC3_DSCC_PPS_CONFIG4__INITIAL_DEC_DELAY_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG5 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG5__INITIAL_SCALE_VALUE_MASK 0x0000003FL +#define DSCC3_DSCC_PPS_CONFIG5__SCALE_INCREMENT_INTERVAL_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG6 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG6__SCALE_DECREMENT_INTERVAL_MASK 0x00000FFFL +#define DSCC3_DSCC_PPS_CONFIG6__FIRST_LINE_BPG_OFFSET_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG6__SECOND_LINE_BPG_OFFSET_MASK 0x1F000000L +//DSCC3_DSCC_PPS_CONFIG7 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG7__NFL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG7__SLICE_BPG_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG8 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG8__NSL_BPG_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG8__SECOND_LINE_OFFSET_ADJ_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG9 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG9__INITIAL_OFFSET_MASK 0x0000FFFFL +#define DSCC3_DSCC_PPS_CONFIG9__FINAL_OFFSET_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MIN_QP_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG10__FLATNESS_MAX_QP_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG10__RC_MODEL_SIZE_MASK 0xFFFF0000L +//DSCC3_DSCC_PPS_CONFIG11 +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI__SHIFT 0x1c +#define DSCC3_DSCC_PPS_CONFIG11__RC_EDGE_FACTOR_MASK 0x0000000FL +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00L +#define DSCC3_DSCC_PPS_CONFIG11__RC_QUANT_INCR_LIMIT1_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_LO_MASK 0x0F000000L +#define DSCC3_DSCC_PPS_CONFIG11__RC_TGT_OFFSET_HI_MASK 0xF0000000L +//DSCC3_DSCC_PPS_CONFIG12 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH0_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH1_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH2_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG12__RC_BUF_THRESH3_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG13 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH4_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH5_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH6_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG13__RC_BUF_THRESH7_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG14 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11__SHIFT 0x18 +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH8_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH9_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH10_MASK 0x00FF0000L +#define DSCC3_DSCC_PPS_CONFIG14__RC_BUF_THRESH11_MASK 0xFF000000L +//DSCC3_DSCC_PPS_CONFIG15 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13__SHIFT 0x8 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH12_MASK 0x000000FFL +#define DSCC3_DSCC_PPS_CONFIG15__RC_BUF_THRESH13_MASK 0x0000FF00L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MIN_QP0_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_MAX_QP0_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG15__RANGE_BPG_OFFSET0_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG16 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP1_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP1_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET1_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MIN_QP2_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_MAX_QP2_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG16__RANGE_BPG_OFFSET2_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG17 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP3_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP3_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET3_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MIN_QP4_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_MAX_QP4_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG17__RANGE_BPG_OFFSET4_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG18 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP5_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP5_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET5_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MIN_QP6_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_MAX_QP6_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG18__RANGE_BPG_OFFSET6_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG19 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP7_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP7_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET7_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MIN_QP8_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_MAX_QP8_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG19__RANGE_BPG_OFFSET8_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG20 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP9_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP9_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET9_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MIN_QP10_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_MAX_QP10_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG20__RANGE_BPG_OFFSET10_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG21 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP11_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP11_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET11_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MIN_QP12_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_MAX_QP12_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG21__RANGE_BPG_OFFSET12_MASK 0xFC000000L +//DSCC3_DSCC_PPS_CONFIG22 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13__SHIFT 0x0 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13__SHIFT 0x5 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13__SHIFT 0xa +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14__SHIFT 0x10 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14__SHIFT 0x15 +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14__SHIFT 0x1a +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP13_MASK 0x0000001FL +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP13_MASK 0x000003E0L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET13_MASK 0x0000FC00L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MIN_QP14_MASK 0x001F0000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_MAX_QP14_MASK 0x03E00000L +#define DSCC3_DSCC_PPS_CONFIG22__RANGE_BPG_OFFSET14_MASK 0xFC000000L +//DSCC3_DSCC_MEM_POWER_CONTROL0 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL0__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC3_DSCC_MEM_POWER_CONTROL1 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE__SHIFT 0x4 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS__SHIFT 0x8 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE__SHIFT 0x10 +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000003L +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_FORCE_MASK 0x00000030L +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_DIS_MASK 0x00000100L +#define DSCC3_DSCC_MEM_POWER_CONTROL1__DSCC_MEM_PWR_STATE_MASK 0x00030000L +//DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER__DSCC_R_Y_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER__DSCC_R_Y_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER__DSCC_G_CB_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER__DSCC_G_CB_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER__DSCC_B_CR_SQUARED_ERROR_LOWER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER__SHIFT 0x0 +#define DSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER__DSCC_B_CR_SQUARED_ERROR_UPPER_MASK 0xFFFFFFFFL +//DSCC3_DSCC_MAX_ABS_ERROR0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR__SHIFT 0x10 +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_R_Y_MAX_ABS_ERROR_MASK 0x0000FFFFL +#define DSCC3_DSCC_MAX_ABS_ERROR0__DSCC_G_CB_MAX_ABS_ERROR_MASK 0xFFFF0000L +//DSCC3_DSCC_MAX_ABS_ERROR1 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR__SHIFT 0x0 +#define DSCC3_DSCC_MAX_ABS_ERROR1__DSCC_B_CR_MAX_ABS_ERROR_MASK 0x0000FFFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL0_MASK 0x00007FFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL1_MASK 0x00007FFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL2_MASK 0x00007FFFL +//DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC3_DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3__DSCC_OUTPUT_BUFFER_MAX_FULLNESS_LEVEL3_MASK 0x00007FFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL0_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL1_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL2_MASK 0x0003FFFFL +//DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__SHIFT 0x0 +#define DSCC3_DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3__DSCC_RATE_BUFFER_MODEL_MAX_FULLNESS_LEVEL3_MASK 0x0003FFFFL +//DSCC3_DSCC_TEST_DEBUG_INDEX0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX0__DSCC_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_INDEX1 +#define DSCC3_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX1__DSCC_TEST_DEBUG_INDEX1_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_INDEX2 +#define DSCC3_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX2__DSCC_TEST_DEBUG_INDEX2_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_INDEX3 +#define DSCC3_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_INDEX3__DSCC_TEST_DEBUG_INDEX3_MASK 0x000000FFL +//DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT 0x8 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT 0x10 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT 0x18 +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK 0x0000001FL +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK 0x00001F00L +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK 0x001F0000L +#define DSCC3_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK 0x1F000000L +//DSCC3_DSCC_TEST_DEBUG_DATA0 +#define DSCC3_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA0__DSCC_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL +//DSCC3_DSCC_TEST_DEBUG_DATA1 +#define DSCC3_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA1__DSCC_TEST_DEBUG_DATA1_MASK 0xFFFFFFFFL +//DSCC3_DSCC_TEST_DEBUG_DATA2 +#define DSCC3_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA2__DSCC_TEST_DEBUG_DATA2_MASK 0xFFFFFFFFL +//DSCC3_DSCC_TEST_DEBUG_DATA3 +#define DSCC3_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3__SHIFT 0x0 +#define DSCC3_DSCC_TEST_DEBUG_DATA3__DSCC_TEST_DEBUG_DATA3_MASK 0xFFFFFFFFL +//DSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0__SHIFT 0x0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_INDEX0__DSCC_DISPCLK_TEST_DEBUG_INDEX0_MASK 0x000000FFL +//DSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0__SHIFT 0x0 +#define DSCC3_DSCC_DISPCLK_TEST_DEBUG_DATA0__DSCC_DISPCLK_TEST_DEBUG_DATA0_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON20_PERFCOUNTER_CNTL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_CNTL2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON20_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFCOUNTER_STATE +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON20_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON20_PERFMON_CNTL +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON20_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON20_PERFMON_CNTL2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON20_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON20_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON20_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON20_PERFMON_CVALUE_LOW +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON20_PERFMON_HI +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON20_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON20_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON20_PERFMON_LOW +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON20_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec +//DWB_ENABLE_CLK_CTRL +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE__SHIFT 0x0 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS__SHIFT 0x4 +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS__SHIFT 0x8 +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL__SHIFT 0xc +#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS__SHIFT 0x18 +#define DWB_ENABLE_CLK_CTRL__DWB_ENABLE_MASK 0x00000001L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_R_DWB_GATE_DIS_MASK 0x00000010L +#define DWB_ENABLE_CLK_CTRL__DISPCLK_G_DWB_GATE_DIS_MASK 0x00000100L +#define DWB_ENABLE_CLK_CTRL__DWB_TEST_CLK_SEL_MASK 0x00003000L +#define DWB_ENABLE_CLK_CTRL__DWB_FGCG_REP_DIS_MASK 0x01000000L +//DWB_MEM_PWR_CTRL +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE__SHIFT 0x8 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS__SHIFT 0xa +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE__SHIFT 0xc +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE__SHIFT 0x10 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS__SHIFT 0x12 +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE__SHIFT 0x14 +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_FORCE_MASK 0x00000300L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_DIS_MASK 0x00000400L +#define DWB_MEM_PWR_CTRL__DWB_OUT_FIFO_MEM_PWR_STATE_MASK 0x00003000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_FORCE_MASK 0x00030000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_DIS_MASK 0x00040000L +#define DWB_MEM_PWR_CTRL__DWB_OGAM_LUT_MEM_PWR_STATE_MASK 0x00300000L +//FC_MODE_CTRL +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN__SHIFT 0x0 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE__SHIFT 0x4 +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN__SHIFT 0x8 +#define FC_MODE_CTRL__FC_EYE_SELECTION__SHIFT 0xc +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY__SHIFT 0x10 +#define FC_MODE_CTRL__FC_NEW_CONTENT__SHIFT 0x14 +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT__SHIFT 0x1f +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_MASK 0x00000001L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_RATE_MASK 0x00000030L +#define FC_MODE_CTRL__FC_WINDOW_CROP_EN_MASK 0x00000100L +#define FC_MODE_CTRL__FC_EYE_SELECTION_MASK 0x00003000L +#define FC_MODE_CTRL__FC_STEREO_EYE_POLARITY_MASK 0x00010000L +#define FC_MODE_CTRL__FC_NEW_CONTENT_MASK 0x00100000L +#define FC_MODE_CTRL__FC_FRAME_CAPTURE_EN_CURRENT_MASK 0x80000000L +//FC_FLOW_CTRL +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT__SHIFT 0x0 +#define FC_FLOW_CTRL__FC_FIRST_PIXEL_DELAY_COUNT_MASK 0x00000FFFL +//FC_WINDOW_START +#define FC_WINDOW_START__FC_WINDOW_START_X__SHIFT 0x0 +#define FC_WINDOW_START__FC_WINDOW_START_Y__SHIFT 0x10 +#define FC_WINDOW_START__FC_WINDOW_START_X_MASK 0x00001FFFL +#define FC_WINDOW_START__FC_WINDOW_START_Y_MASK 0x1FFF0000L +//FC_WINDOW_SIZE +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH__SHIFT 0x0 +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT__SHIFT 0x10 +#define FC_WINDOW_SIZE__FC_WINDOW_WIDTH_MASK 0x00000FFFL +#define FC_WINDOW_SIZE__FC_WINDOW_HEIGHT_MASK 0x0FFF0000L +//FC_SOURCE_SIZE +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH__SHIFT 0x0 +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT__SHIFT 0x10 +#define FC_SOURCE_SIZE__FC_SOURCE_WIDTH_MASK 0x00007FFFL +#define FC_SOURCE_SIZE__FC_SOURCE_HEIGHT_MASK 0x7FFF0000L +//DWB_UPDATE_CTRL +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK__SHIFT 0x0 +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING__SHIFT 0x4 +#define DWB_UPDATE_CTRL__DWB_UPDATE_LOCK_MASK 0x00000001L +#define DWB_UPDATE_CTRL__DWB_UPDATE_PENDING_MASK 0x00000010L +//DWB_CRC_CTRL +#define DWB_CRC_CTRL__DWB_CRC_EN__SHIFT 0x0 +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN__SHIFT 0x4 +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL__SHIFT 0x8 +#define DWB_CRC_CTRL__DWB_CRC_EN_MASK 0x00000001L +#define DWB_CRC_CTRL__DWB_CRC_CONT_EN_MASK 0x00000010L +#define DWB_CRC_CTRL__DWB_CRC_SRC_SEL_MASK 0x00000300L +//DWB_CRC_MASK_R_G +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_R_G__DWB_CRC_RED_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_R_G__DWB_CRC_GREEN_MASK_MASK 0xFFFF0000L +//DWB_CRC_MASK_B_A +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK__SHIFT 0x0 +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK__SHIFT 0x10 +#define DWB_CRC_MASK_B_A__DWB_CRC_BLUE_MASK_MASK 0x0000FFFFL +#define DWB_CRC_MASK_B_A__DWB_CRC_A_MASK_MASK 0xFFFF0000L +//DWB_CRC_VAL_R_G +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED__SHIFT 0x0 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN__SHIFT 0x10 +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_RED_MASK 0x0000FFFFL +#define DWB_CRC_VAL_R_G__DWB_CRC_SIG_GREEN_MASK 0xFFFF0000L +//DWB_CRC_VAL_B_A +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE__SHIFT 0x0 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A__SHIFT 0x10 +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_BLUE_MASK 0x0000FFFFL +#define DWB_CRC_VAL_B_A__DWB_CRC_SIG_A_MASK 0xFFFF0000L +//DWB_OUT_CTRL +#define DWB_OUT_CTRL__OUT_FORMAT__SHIFT 0x0 +#define DWB_OUT_CTRL__OUT_DENORM__SHIFT 0x4 +#define DWB_OUT_CTRL__OUT_MAX__SHIFT 0x8 +#define DWB_OUT_CTRL__OUT_MIN__SHIFT 0x14 +#define DWB_OUT_CTRL__OUT_FORMAT_MASK 0x00000003L +#define DWB_OUT_CTRL__OUT_DENORM_MASK 0x00000030L +#define DWB_OUT_CTRL__OUT_MAX_MASK 0x0003FF00L +#define DWB_OUT_CTRL__OUT_MIN_MASK 0x3FF00000L +//DWB_MMHUBBUB_BACKPRESSURE_CNT_EN +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT_EN__DWB_MMHUBBUB_BACKPRESSURE_CNT_EN_MASK 0x00000001L +//DWB_MMHUBBUB_BACKPRESSURE_CNT +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE__SHIFT 0x0 +#define DWB_MMHUBBUB_BACKPRESSURE_CNT__DWB_MMHUBBUB_MAX_BACKPRESSURE_MASK 0x0000FFFFL +//DWB_HOST_READ_CONTROL +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define DWB_HOST_READ_CONTROL__DWB_HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//DWB_OVERFLOW_STATUS +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG__SHIFT 0x0 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK__SHIFT 0x8 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK__SHIFT 0xc +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS__SHIFT 0x10 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE__SHIFT 0x14 +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_FLAG_MASK 0x00000001L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_ACK_MASK 0x00000100L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_MASK_MASK 0x00001000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_STATUS_MASK 0x00010000L +#define DWB_OVERFLOW_STATUS__DWB_DATA_OVERFLOW_INT_TYPE_MASK 0x00100000L +//DWB_OVERFLOW_COUNTER +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE__SHIFT 0x0 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT__SHIFT 0x4 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT__SHIFT 0x10 +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_TYPE_MASK 0x00000003L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_X_CNT_MASK 0x0000FFF0L +#define DWB_OVERFLOW_COUNTER__DWB_DATA_OVERFLOW_OUT_Y_CNT_MASK 0x0FFF0000L +//DWB_SOFT_RESET +#define DWB_SOFT_RESET__DWB_SOFT_RESET__SHIFT 0x0 +#define DWB_SOFT_RESET__DWB_SOFT_RESET_MASK 0x00000001L +//DWB_DEBUG_CTRL +#define DWB_DEBUG_CTRL__DWB_DEBUG_EN__SHIFT 0x0 +#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL__SHIFT 0x6 +#define DWB_DEBUG_CTRL__DWB_DEBUG_EN_MASK 0x00000001L +#define DWB_DEBUG_CTRL__DWB_DEBUG_SEL_MASK 0x000000C0L +//DWB_DEBUG +#define DWB_DEBUG__DWB_DEBUG__SHIFT 0x0 +#define DWB_DEBUG__DWB_DEBUG_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON21_PERFCOUNTER_CNTL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_CNTL2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON21_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFCOUNTER_STATE +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON21_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON21_PERFMON_CNTL +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON21_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON21_PERFMON_CNTL2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON21_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON21_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON21_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON21_PERFMON_CVALUE_LOW +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON21_PERFMON_HI +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON21_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON21_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON21_PERFMON_LOW +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON21_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec +//DWB_HDR_MULT_COEF +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF__SHIFT 0x0 +#define DWB_HDR_MULT_COEF__DWB_HDR_MULT_COEF_MASK 0x0007FFFFL +//DWB_GAMUT_REMAP_MODE +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE__SHIFT 0x0 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x18 +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_MASK 0x00000003L +#define DWB_GAMUT_REMAP_MODE__DWB_GAMUT_REMAP_MODE_CURRENT_MASK 0x03000000L +//DWB_GAMUT_REMAP_COEF_FORMAT +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define DWB_GAMUT_REMAP_COEF_FORMAT__DWB_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//DWB_GAMUT_REMAPA_C11_C12 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C11_C12__DWB_GAMUT_REMAPA_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C13_C14 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C13_C14__DWB_GAMUT_REMAPA_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C21_C22 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C21_C22__DWB_GAMUT_REMAPA_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C23_C24 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C23_C24__DWB_GAMUT_REMAPA_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C31_C32 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C31_C32__DWB_GAMUT_REMAPA_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPA_C33_C34 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPA_C33_C34__DWB_GAMUT_REMAPA_C34_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C11_C12 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C11_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C11_C12__DWB_GAMUT_REMAPB_C12_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C13_C14 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C13_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C13_C14__DWB_GAMUT_REMAPB_C14_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C21_C22 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C21_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C21_C22__DWB_GAMUT_REMAPB_C22_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C23_C24 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C23_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C23_C24__DWB_GAMUT_REMAPB_C24_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C31_C32 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C31_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C31_C32__DWB_GAMUT_REMAPB_C32_MASK 0xFFFF0000L +//DWB_GAMUT_REMAPB_C33_C34 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33__SHIFT 0x0 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34__SHIFT 0x10 +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C33_MASK 0x0000FFFFL +#define DWB_GAMUT_REMAPB_C33_C34__DWB_GAMUT_REMAPB_C34_MASK 0xFFFF0000L +//DWB_OGAM_CONTROL +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE__SHIFT 0x0 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT__SHIFT 0x4 +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE__SHIFT 0x8 +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT__SHIFT 0x18 +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT__SHIFT 0x1c +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_MASK 0x00000003L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_MASK 0x00000010L +#define DWB_OGAM_CONTROL__DWB_OGAM_PWL_DISABLE_MASK 0x00000100L +#define DWB_OGAM_CONTROL__DWB_OGAM_MODE_CURRENT_MASK 0x03000000L +#define DWB_OGAM_CONTROL__DWB_OGAM_SELECT_CURRENT_MASK 0x10000000L +//DWB_OGAM_LUT_INDEX +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX__SHIFT 0x0 +#define DWB_OGAM_LUT_INDEX__DWB_OGAM_LUT_INDEX_MASK 0x000001FFL +//DWB_OGAM_LUT_DATA +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA__SHIFT 0x0 +#define DWB_OGAM_LUT_DATA__DWB_OGAM_LUT_DATA_MASK 0x0003FFFFL +//DWB_OGAM_LUT_CONTROL +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x4 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG__SHIFT 0x8 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL__SHIFT 0xc +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE__SHIFT 0x10 +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000030L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_READ_DBG_MASK 0x00000100L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_HOST_SEL_MASK 0x00001000L +#define DWB_OGAM_LUT_CONTROL__DWB_OGAM_LUT_CONFIG_MODE_MASK 0x00010000L +//DWB_OGAM_RAMA_START_CNTL_B +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_G +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_CNTL_R +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMA_START_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMA_START_BASE_CNTL_B +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_B__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_G +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_G__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_BASE_CNTL_R +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_BASE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_START_SLOPE_CNTL_R__DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL1_B +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_B__DWB_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_B +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_B__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_G +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_G__DWB_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_G +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_G__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_END_CNTL1_R +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL1_R__DWB_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMA_END_CNTL2_R +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMA_END_CNTL2_R__DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMA_OFFSET_B +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_B__DWB_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_G +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_G__DWB_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_OFFSET_R +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMA_OFFSET_R__DWB_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMA_REGION_0_1 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_0_1__DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_2_3 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_2_3__DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_4_5 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_4_5__DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_6_7 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_6_7__DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_8_9 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_8_9__DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_10_11 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_10_11__DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_12_13 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_12_13__DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_14_15 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_14_15__DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_16_17 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_16_17__DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_18_19 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_18_19__DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_20_21 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_20_21__DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_22_23 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_22_23__DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_24_25 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_24_25__DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_26_27 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_26_27__DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_28_29 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_28_29__DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_30_31 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_30_31__DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMA_REGION_32_33 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMA_REGION_32_33__DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_START_CNTL_B +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_G +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_CNTL_R +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define DWB_OGAM_RAMB_START_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//DWB_OGAM_RAMB_START_BASE_CNTL_B +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_B +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_B__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_G +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_G +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_G__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_BASE_CNTL_R +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_BASE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_START_SLOPE_CNTL_R +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_START_SLOPE_CNTL_R__DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL1_B +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_B__DWB_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_B +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_B__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_G +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_G__DWB_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_G +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_G__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_END_CNTL1_R +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL1_R__DWB_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//DWB_OGAM_RAMB_END_CNTL2_R +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define DWB_OGAM_RAMB_END_CNTL2_R__DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//DWB_OGAM_RAMB_OFFSET_B +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_B__DWB_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_G +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_G__DWB_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_OFFSET_R +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define DWB_OGAM_RAMB_OFFSET_R__DWB_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//DWB_OGAM_RAMB_REGION_0_1 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_0_1__DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_2_3 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_2_3__DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_4_5 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_4_5__DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_6_7 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_6_7__DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_8_9 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_8_9__DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_10_11 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_10_11__DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_12_13 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_12_13__DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_14_15 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_14_15__DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_16_17 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_16_17__DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_18_19 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_18_19__DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_20_21 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_20_21__DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_22_23 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_22_23__DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_24_25 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_24_25__DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_26_27 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_26_27__DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_28_29 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_28_29__DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_30_31 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_30_31__DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//DWB_OGAM_RAMB_REGION_32_33 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define DWB_OGAM_RAMB_REGION_32_33__DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L + + +// addressBlock: dce_dc_dchvm_hvm_dispdec +//DCHVM_CTRL0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ__SHIFT 0x0 +#define DCHVM_CTRL0__HOSTVM_INIT_REQ_MASK 0x00000001L +//DCHVM_CTRL1 +#define DCHVM_CTRL1__DUMMY1__SHIFT 0x0 +#define DCHVM_CTRL1__DUMMY1_MASK 0xFFFFFFFFL +//DCHVM_CLK_CTRL +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS__SHIFT 0x1 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS__SHIFT 0x4 +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS__SHIFT 0x5 +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE__SHIFT 0x8 +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE__SHIFT 0xa +#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS__SHIFT 0xc +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKCTL_MODE__SHIFT 0xf +#define DCHVM_CLK_CTRL__HVM_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define DCHVM_CLK_CTRL__HVM_DISPCLK_G_GATE_DIS_MASK 0x00000002L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_R_GATE_DIS_MASK 0x00000010L +#define DCHVM_CLK_CTRL__HVM_DCFCLK_G_GATE_DIS_MASK 0x00000020L +#define DCHVM_CLK_CTRL__TR_REQ_REQCLKREQ_MODE_MASK 0x00000300L +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKREQ_MODE_MASK 0x00000C00L +#define DCHVM_CLK_CTRL__HVM_FGCG_REP_DIS_MASK 0x00001000L +#define DCHVM_CLK_CTRL__TW_RSP_COMPCLKCTL_MODE_MASK 0x00008000L +//DCHVM_MEM_CTRL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS__SHIFT 0x0 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ__SHIFT 0x2 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS__SHIFT 0x4 +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_PWR_REQ_DIS_MASK 0x00000001L +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_FORCE_REQ_MASK 0x0000000CL +#define DCHVM_MEM_CTRL__HVM_GPUVMRET_POWER_STATUS_MASK 0x00000030L +//DCHVM_RIOMMU_CTRL0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ__SHIFT 0x0 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS__SHIFT 0x1 +#define DCHVM_RIOMMU_CTRL0__HOSTVM_PREFETCH_REQ_MASK 0x00000001L +#define DCHVM_RIOMMU_CTRL0__HOSTVM_POWERSTATUS_MASK 0x00000002L +//DCHVM_RIOMMU_STAT0 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE__SHIFT 0x0 +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE__SHIFT 0x1 +#define DCHVM_RIOMMU_STAT0__RIOMMU_ACTIVE_MASK 0x00000001L +#define DCHVM_RIOMMU_STAT0__HOSTVM_PREFETCH_DONE_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dispdec +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC0_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC0_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_apg_apg_dispdec +//APG5_APG_DBG_GEN_CONTROL +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG5_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG5_APG_MEM_PWR +#define APG5_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG5_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG5_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG5_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG5_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG5_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG5_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG5_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_dme_dme_dispdec +//DME5_DME_CONTROL +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME5_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME5_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME5_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME5_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME5_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME5_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME5_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME5_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME5_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME5_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME5_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME5_DME_MEMORY_CONTROL +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME5_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc0_vpg_vpg_dispdec +//VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG5_VPG_GENERIC_PACKET_DATA +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG5_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG5_VPG_GENERIC_STATUS +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG5_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG5_VPG_MEM_PWR +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG5_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG5_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG5_VPG_ISRC1_2_ACCESS_CTRL +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG5_VPG_ISRC1_2_DATA +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG5_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc0_dispdec +//DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC0_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC0_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC0_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC0_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc0_dispdec +//DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC0_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC0_DP_LINK_ENC_SPARE +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC0_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym320_dispdec +//DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM320_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dispdec +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC1_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC1_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC1_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC1_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_apg_apg_dispdec +//APG6_APG_DBG_GEN_CONTROL +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG6_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG6_APG_MEM_PWR +#define APG6_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG6_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG6_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG6_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG6_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG6_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG6_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG6_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_dme_dme_dispdec +//DME6_DME_CONTROL +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME6_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME6_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME6_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME6_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME6_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME6_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME6_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME6_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME6_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME6_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME6_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME6_DME_MEMORY_CONTROL +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME6_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc1_vpg_vpg_dispdec +//VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG6_VPG_GENERIC_PACKET_DATA +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG6_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG6_VPG_GENERIC_STATUS +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG6_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG6_VPG_MEM_PWR +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG6_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG6_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG6_VPG_ISRC1_2_ACCESS_CTRL +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG6_VPG_ISRC1_2_DATA +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG6_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc1_dispdec +//DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC1_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC1_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC1_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC1_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc1_dispdec +//DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC1_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC1_DP_LINK_ENC_SPARE +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC1_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym321_dispdec +//DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM321_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dispdec +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC2_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC2_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC2_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC2_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_apg_apg_dispdec +//APG7_APG_DBG_GEN_CONTROL +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG7_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG7_APG_MEM_PWR +#define APG7_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG7_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG7_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG7_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG7_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG7_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG7_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG7_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_dme_dme_dispdec +//DME7_DME_CONTROL +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME7_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME7_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME7_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME7_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME7_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME7_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME7_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME7_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME7_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME7_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME7_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME7_DME_MEMORY_CONTROL +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME7_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc2_vpg_vpg_dispdec +//VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG7_VPG_GENERIC_PACKET_DATA +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG7_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG7_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG7_VPG_GENERIC_STATUS +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG7_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG7_VPG_MEM_PWR +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG7_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG7_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG7_VPG_ISRC1_2_ACCESS_CTRL +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG7_VPG_ISRC1_2_DATA +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG7_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc2_dispdec +//DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC2_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC2_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC2_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC2_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc2_dispdec +//DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC2_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC2_DP_LINK_ENC_SPARE +#define DP_LINK_ENC2_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC2_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym322_dispdec +//DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM322_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dispdec +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32__SHIFT 0x11 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_DPSTREAMCLK_MASK 0x00001000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_CLOCK_ON_SYMCLK32_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_CONTROL__DP_STREAM_ENC_APG_CLOCK_ON_SYMCLK32_MASK 0x00020000L +//DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_INPUT_MUX_CONTROL__DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL_MASK 0x00000007L +//DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define DP_STREAM_ENC3_DP_STREAM_ENC_AUDIO_CONTROL__DP_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL__SHIFT 0x8 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_START_LEVEL_MASK 0x00003F00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_READ_CLOCK_SRC_MASK 0x00010000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define DP_STREAM_ENC3_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//DP_STREAM_ENC3_DP_STREAM_ENC_SPARE +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE__SHIFT 0x0 +#define DP_STREAM_ENC3_DP_STREAM_ENC_SPARE__DP_STREAM_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_apg_apg_dispdec +//APG8_APG_DBG_GEN_CONTROL +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG8_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG8_APG_MEM_PWR +#define APG8_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG8_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG8_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG8_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG8_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG8_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG8_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG8_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_dme_dme_dispdec +//DME8_DME_CONTROL +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME8_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME8_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME8_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME8_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME8_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME8_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME8_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME8_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME8_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME8_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME8_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME8_DME_MEMORY_CONTROL +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME8_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_dp_stream_enc3_vpg_vpg_dispdec +//VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG8_VPG_GENERIC_PACKET_DATA +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG8_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG8_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG8_VPG_GENERIC_STATUS +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG8_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG8_VPG_MEM_PWR +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG8_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG8_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG8_VPG_ISRC1_2_ACCESS_CTRL +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG8_VPG_ISRC1_2_DATA +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG8_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_dp_sym32_enc3_dispdec +//DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_CONTROL__DP_SYM32_ENC_RESET_DONE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_RESET_DONE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_FIFO_CONTROL__PIXEL_TO_SYMBOL_FIFO_OVERFLOW_STATUS_MASK 0x00001000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL__MSA_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL__PIXEL_FORMAT_DOUBLE_BUFFER_PENDING_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__PIXEL_ENCODING_TYPE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_PIXEL_ENCODING_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PIXEL_FORMAT__UNCOMPRESSED_COMPONENT_DEPTH_MASK 0x00000300L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA0__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA1__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA2__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA3__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA4__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA5__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA6__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA7__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA8__MSA_DATA_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_HBLANK_CONTROL__HBLANK_MINIMUM_SYMBOL_WIDTH_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL0__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL1__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL2__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL3__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL4__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL5__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL6__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL7__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL8__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL9__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL10__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL11__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL12__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL13__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE__SHIFT 0x7 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING__SHIFT 0x9 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING__SHIFT 0xa +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_IDLE_CONTINUOUS_TRANSMISSION_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_SEND_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_ONE_SHOT_POSITION_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_PAYLOAD_SIZE_MASK 0x00000060L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_SOF_REFERENCE_MASK 0x00000080L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_DEADLINE_MISSED_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRIGGER_TRANSMISSION_PENDING_MASK 0x00000200L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_DOUBLE_BUFFER_PENDING_MASK 0x00000400L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_GSP_CONTROL14__GSP_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__GSP0_PRIORITY_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_CONTROL__SDP_CRC16_ENABLE_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE__SHIFT 0x1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE__SHIFT 0x2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE__SHIFT 0x3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY__SHIFT 0x5 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS__SHIFT 0x1d +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_ENABLE_MASK 0x00000002L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AIP_ENABLE_MASK 0x00000004L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ACM_ENABLE_MASK 0x00000008L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ISRC_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ASP_PRIORITY_MASK 0x00000020L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__ATP_VERSION_NUMBER_MASK 0x00003F00L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_MASK 0x10000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL0__AUDIO_MUTE_STATUS_MASK 0x20000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_2_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x000003F0L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_8_CHANNEL_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x0003F000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_AUDIO_CONTROL1__ASP_CONCATENATION_HBR_LAYOUT_MAX_SAMPLE_COUNT_MASK 0x03F00000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_SOF_REFERENCE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_DOUBLE_BUFFER_PENDING_MASK 0x00001000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL__METADATA_PACKET_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_MISC1_STEREOSYNC_OVERRIDE_EN_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_ENABLE_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_MSA_CONTROL__MSA_TRANSMISSION_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_VBID_CONTROL__VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_DISABLE_DEFER_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_STREAM_CONTROL__VID_STREAM_STATUS_MASK 0x00000100L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_PANEL_REPLAY_CONTROL__PANEL_REPLAY_TUNNELING_OPTIMIZATION_DOUBLE_BUFFER_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_CONTROL__CRC_CONT_MODE_ENABLE_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT0__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT1__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT2__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_RESULT3__CRC_RESULT_MASK 0xFFFFFFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_VID_CRC_STATUS__CRC_VALID_ACK_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_STATUS__BS_COUNT_MASK 0x0000FFFFL +//DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_SYMBOL_COUNT_CONTROL__BS_COUNT_RESET_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_SLEEP_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE__SHIFT 0x18 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__REQUEST_MASK 0x00100000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__MODE_MASK 0x01000000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_CONTROL__PENDING_MASK 0x10000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__SLEEP_OFFSET_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_REQUEST_OFFSET__WAKE_OFFSET_MASK 0xFFFF0000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_READY_CONTROL__SDP_PENDING_MODE_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__ENABLE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__DISABLE_MODE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_HARDWARE_MODE_CONTROL__FRAME_NUMBER_MASK 0x0000FF00L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_SLEEP_STATE_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_HARDWARE_MODE_STATE_MASK 0x00000010L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_STATUS__CURRENT_FRAME_MASK 0x0000FF00L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_START_CONTROL__START_STATE_MASK 0x00000001L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE__SHIFT 0x10 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER__SHIFT 0x14 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE__SHIFT 0x1c +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_NUMBER_MASK 0x0000FFFFL +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__LINE_REFERENCE_MASK 0x00010000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__FRAME_NUMBER_MASK 0x0FF00000L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_CONTROL__ENABLE_MASK 0x10000000L +//DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__OCCURRED_MASK 0x00000001L +#define DP_SYM32_ENC3_DP_SYM32_ENC_ALPM_WAKE_INTERRUPT_STATUS__CLEAR_MASK 0x00000010L +//DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE__SHIFT 0x4 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS__SHIFT 0x8 +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE__SHIFT 0xc +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00000003L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_FORCE_MASK 0x00000030L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_DIS_MASK 0x00000100L +#define DP_SYM32_ENC3_DP_SYM32_ENC_MEM_POWER_CONTROL__MEM_PWR_STATE_MASK 0x00003000L +//DP_SYM32_ENC3_DP_SYM32_ENC_SPARE +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE__SHIFT 0x0 +#define DP_SYM32_ENC3_DP_SYM32_ENC_SPARE__DP_SYM32_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_link_enc3_dispdec +//DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32__SHIFT 0x4 +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define DP_LINK_ENC3_DP_LINK_ENC_CLOCK_CONTROL__DP_LINK_ENC_CLOCK_ON_SYMCLK32_MASK 0x00000010L +//DP_LINK_ENC3_DP_LINK_ENC_SPARE +#define DP_LINK_ENC3_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE__SHIFT 0x0 +#define DP_LINK_ENC3_DP_LINK_ENC_SPARE__DP_LINK_ENC_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hpo_dp_dphy_sym323_dispdec +//DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_RESET__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__MODE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__NUM_LANES__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE__SHIFT 0xa +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP__SHIFT 0xd +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__DPHY_RESET_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__PRECODER_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__MODE_MASK 0x00000030L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__NUM_LANES_MASK 0x00000300L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__OUTPUT_MODE_MASK 0x00000400L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__SHORT_LAST_TPS2_PERIOD_MASK 0x00001000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_CONTROL__START_FROM_SLEEP_MASK 0x00002000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__STATUS__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RESET_STATUS__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CURRENT_MODE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING__SHIFT 0x10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS__SHIFT 0x12 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CM_MODE_EN__SHIFT 0x14 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__STATUS_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RESET_STATUS_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CURRENT_MODE_MASK 0x00000030L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__ENCRYPTION_ENABLED_MASK 0x00000100L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__RATE_UPDATE_PENDING_MASK 0x00001000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SAT_UPDATE_PENDING_MASK 0x00030000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__SCHEDULER_STATUS_MASK 0x000C0000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_STATUS__CM_MODE_EN_MASK 0x00100000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_UPDATE__SAT_UPDATE_MASK 0x00000003L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL0__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL1__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL2__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X__SHIFT 0x19 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_Y_MASK 0x01FFFFFFL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_VC_RATE_CNTL3__STREAM_VC_RATE_X_MASK 0xFE000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS0__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS1__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS2__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_STREAM_SOURCE_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_ENABLE_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_ENCRYPTION_TYPE_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SAT_VC_STATUS3__SAT_SLOT_COUNT_MASK 0x00007F00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_MODE_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_CONFIG0__EDP_LINK_SECURITY_STRENGTH_MASK 0x00000030L +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR0__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR1__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR2__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3__SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_EDP_ASSR3__SEED_MASK 0x007FFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME__SHIFT 0x10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_PATTERNS_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__PATTERN_INTERVAL_MASK 0x00000FF0L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__NUM_REPEAT_MASK 0x0000F000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_SLEEP_CONFIG0__HOLD_TIME_MASK 0x00FF0000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_WAKE_CONFIG0__LOCK_PERIOD_MASK 0x0003FFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__SLEEP_DELAY_MASK 0x0000007FL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ALPM_CONTROL__MIN_SLEEP_CYCLES_MASK 0x000FFF00L +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1__SHIFT 0xc +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2__SHIFT 0x10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2__SHIFT 0x14 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3__SHIFT 0x18 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3__SHIFT 0x1c +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT0_MASK 0x00000007L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL0_MASK 0x00000070L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT1_MASK 0x00000700L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL1_MASK 0x00007000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT2_MASK 0x00070000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL2_MASK 0x00700000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_SELECT3_MASK 0x07000000L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CONFIG__TP_PRBS_SEL3_MASK 0x70000000L +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED0__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED1__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED2__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_PRBS_SEED3__TP_PRBS_SEED_MASK 0x7FFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_SQ_PULSE__TP_SQ_PULSE_WIDTH_MASK 0x000000FFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM0__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM1__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM2__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM3__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM4__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM5__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM6__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM7__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM8__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM9__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_TP_CUSTOM10__TP_CUSTOM_MASK 0x00FFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE__SHIFT 0x2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR__SHIFT 0x3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION__SHIFT 0x4 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL__SHIFT 0x5 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION__SHIFT 0x6 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW__SHIFT 0x7 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR__SHIFT 0x8 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY__SHIFT 0x9 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__TOTAL_SLOT_COUNT_ERROR_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_ERROR_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__VC_SAME_STREAM_SOURCE_MASK 0x00000004L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__NO_ACT_ERROR_MASK 0x00000008L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__UNEXPECT_MODE_TRANSITION_MASK 0x00000010L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ILLEGAL_STREAM_SYMBOL_MASK 0x00000020L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__RATE_COUNTER_SATURATION_MASK 0x00000040L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__COUNTER_OVERFLOW_MASK 0x00000080L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__CIPHER_ERROR_MASK 0x00000100L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_ERROR_STATUS__ALPM_WAKE_REQ_EARLY_MASK 0x00000200L +//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS0__LLCP_COUNT_MASK 0x0000FFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_STATUS1__CYCLE_COUNT_MASK 0xFFFFFFFFL +//DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE__SHIFT 0x0 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET__SHIFT 0x1 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE__SHIFT 0x2 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET__SHIFT 0x3 +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_ENABLE_MASK 0x00000001L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__LLCP_COUNT_RESET_MASK 0x00000002L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_ENABLE_MASK 0x00000004L +#define DP_DPHY_SYM323_DP_DPHY_SYM32_SYMBOL_COUNT_CONTROL__CYCLE_COUNT_RESET_MASK 0x00000008L + + +// addressBlock: dce_dc_mpc_mpcc0_dispdec +//MPCC0_MPCC_TOP_SEL +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC0_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC0_MPCC_BOT_SEL +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC0_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC0_MPCC_OPP_ID +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC0_MPCC_CONTROL +#define MPCC0_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC0_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC0_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC0_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC0_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC0_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC0_MPCC_CONTROL2 +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC0_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC0_MPCC_SM_CONTROL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC0_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC0_MPCC_UPDATE_LOCK_SEL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC0_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC0_MPCC_TOP_GAIN +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC0_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_INSIDE +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_BOT_GAIN_OUTSIDE +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC0_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC0_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC0_MPCC_BG_R_CR +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC0_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC0_MPCC_BG_G_Y +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC0_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC0_MPCC_BG_B_CB +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC0_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC0_MPCC_MEM_PWR_CTRL +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC0_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC0_MPCC_STATUS +#define MPCC0_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC0_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC0_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC0_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC0_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC0_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc1_dispdec +//MPCC1_MPCC_TOP_SEL +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC1_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC1_MPCC_BOT_SEL +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC1_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC1_MPCC_OPP_ID +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC1_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC1_MPCC_CONTROL +#define MPCC1_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC1_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC1_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC1_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC1_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC1_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC1_MPCC_CONTROL2 +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC1_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC1_MPCC_SM_CONTROL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC1_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC1_MPCC_UPDATE_LOCK_SEL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC1_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC1_MPCC_TOP_GAIN +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC1_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_INSIDE +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_BOT_GAIN_OUTSIDE +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC1_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC1_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC1_MPCC_BG_R_CR +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC1_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC1_MPCC_BG_G_Y +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC1_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC1_MPCC_BG_B_CB +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC1_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC1_MPCC_MEM_PWR_CTRL +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC1_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC1_MPCC_STATUS +#define MPCC1_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC1_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC1_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC1_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC1_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC1_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc2_dispdec +//MPCC2_MPCC_TOP_SEL +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC2_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC2_MPCC_BOT_SEL +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC2_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC2_MPCC_OPP_ID +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC2_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC2_MPCC_CONTROL +#define MPCC2_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC2_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC2_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC2_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC2_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC2_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC2_MPCC_CONTROL2 +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC2_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC2_MPCC_SM_CONTROL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC2_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC2_MPCC_UPDATE_LOCK_SEL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC2_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC2_MPCC_TOP_GAIN +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC2_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_INSIDE +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_BOT_GAIN_OUTSIDE +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC2_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC2_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC2_MPCC_BG_R_CR +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC2_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC2_MPCC_BG_G_Y +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC2_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC2_MPCC_BG_B_CB +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC2_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC2_MPCC_MEM_PWR_CTRL +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC2_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC2_MPCC_STATUS +#define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC2_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC2_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC2_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC2_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC2_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc3_dispdec +//MPCC3_MPCC_TOP_SEL +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL__SHIFT 0x0 +#define MPCC3_MPCC_TOP_SEL__MPCC_TOP_SEL_MASK 0x0000000FL +//MPCC3_MPCC_BOT_SEL +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL__SHIFT 0x0 +#define MPCC3_MPCC_BOT_SEL__MPCC_BOT_SEL_MASK 0x0000000FL +//MPCC3_MPCC_OPP_ID +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT 0x0 +#define MPCC3_MPCC_OPP_ID__MPCC_OPP_ID_MASK 0x0000000FL +//MPCC3_MPCC_CONTROL +#define MPCC3_MPCC_CONTROL__MPCC_MODE__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE__SHIFT 0x4 +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x6 +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x7 +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC__SHIFT 0x8 +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE__SHIFT 0xb +#define MPCC3_MPCC_CONTROL__MPCC_MODE_MASK 0x00000003L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_BLND_MODE_MASK 0x00000030L +#define MPCC3_MPCC_CONTROL__MPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040L +#define MPCC3_MPCC_CONTROL__MPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080L +#define MPCC3_MPCC_CONTROL__MPCC_BG_BPC_MASK 0x00000700L +#define MPCC3_MPCC_CONTROL__MPCC_BOT_GAIN_MODE_MASK 0x00000800L +//MPCC3_MPCC_CONTROL2 +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA__SHIFT 0x0 +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_GAIN__SHIFT 0x10 +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_ALPHA_MASK 0x00000FFFL +#define MPCC3_MPCC_CONTROL2__MPCC_GLOBAL_GAIN_MASK 0x0FFF0000L +//MPCC3_MPCC_SM_CONTROL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN__SHIFT 0x0 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE__SHIFT 0x1 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT__SHIFT 0x4 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT__SHIFT 0x5 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL__SHIFT 0x8 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL__SHIFT 0x10 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL__SHIFT 0x18 +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_EN_MASK 0x00000001L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_MODE_MASK 0x0000000EL +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FRAME_ALT_MASK 0x00000010L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FIELD_ALT_MASK 0x00000020L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_FRAME_POL_MASK 0x00000300L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_FORCE_NEXT_TOP_POL_MASK 0x00030000L +#define MPCC3_MPCC_SM_CONTROL__MPCC_SM_CURRENT_FRAME_POL_MASK 0x01000000L +//MPCC3_MPCC_UPDATE_LOCK_SEL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL__SHIFT 0x0 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS__SHIFT 0x4 +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCK_SEL_MASK 0x0000000FL +#define MPCC3_MPCC_UPDATE_LOCK_SEL__MPCC_UPDATE_LOCKED_STATUS_MASK 0x00000070L +//MPCC3_MPCC_TOP_GAIN +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN__SHIFT 0x0 +#define MPCC3_MPCC_TOP_GAIN__MPCC_TOP_GAIN_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_INSIDE +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_INSIDE__MPCC_BOT_GAIN_INSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_BOT_GAIN_OUTSIDE +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE__SHIFT 0x0 +#define MPCC3_MPCC_BOT_GAIN_OUTSIDE__MPCC_BOT_GAIN_OUTSIDE_MASK 0x0007FFFFL +//MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x0 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x4 +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001L +#define MPCC3_MPCC_MOVABLE_CM_LOCATION_CONTROL__MPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010L +//MPCC3_MPCC_BG_R_CR +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR__SHIFT 0x0 +#define MPCC3_MPCC_BG_R_CR__MPCC_BG_R_CR_MASK 0x00000FFFL +//MPCC3_MPCC_BG_G_Y +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y__SHIFT 0x0 +#define MPCC3_MPCC_BG_G_Y__MPCC_BG_G_Y_MASK 0x00000FFFL +//MPCC3_MPCC_BG_B_CB +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB__SHIFT 0x0 +#define MPCC3_MPCC_BG_B_CB__MPCC_BG_B_CB_MASK 0x00000FFFL +//MPCC3_MPCC_MEM_PWR_CTRL +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE__SHIFT 0x8 +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC3_MPCC_MEM_PWR_CTRL__MPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300L +//MPCC3_MPCC_STATUS +#define MPCC3_MPCC_STATUS__MPCC_IDLE__SHIFT 0x0 +#define MPCC3_MPCC_STATUS__MPCC_BUSY__SHIFT 0x1 +#define MPCC3_MPCC_STATUS__MPCC_DISABLED__SHIFT 0x2 +#define MPCC3_MPCC_STATUS__MPCC_IDLE_MASK 0x00000001L +#define MPCC3_MPCC_STATUS__MPCC_BUSY_MASK 0x00000002L +#define MPCC3_MPCC_STATUS__MPCC_DISABLED_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec +//MPCC_OGAM0_MPCC_OGAM_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM0_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM0_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM0_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM0_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec +//MPCC_OGAM1_MPCC_OGAM_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM1_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM1_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM1_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM1_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec +//MPCC_OGAM2_MPCC_OGAM_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM2_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM2_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM2_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM2_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM2_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec +//MPCC_OGAM3_MPCC_OGAM_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT__SHIFT 0x2 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT__SHIFT 0x9 +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_MASK 0x00000004L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_PWL_DISABLE_MASK 0x00000008L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_CURRENT_MASK 0x00000180L +#define MPCC_OGAM3_MPCC_OGAM_CONTROL__MPCC_OGAM_SELECT_CURRENT_MASK 0x00000200L +//MPCC_OGAM3_MPCC_OGAM_LUT_INDEX +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_INDEX__MPCC_OGAM_LUT_INDEX_MASK 0x000001FFL +//MPCC_OGAM3_MPCC_OGAM_LUT_DATA +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_DATA__MPCC_OGAM_LUT_DATA_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_OGAM3_MPCC_OGAM_LUT_CONTROL__MPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R__MPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R__MPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R__MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B__MPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G__MPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R__MPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1__MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3__MPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5__MPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7__MPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9__MPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11__MPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13__MPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15__MPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17__MPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19__MPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21__MPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23__MPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25__MPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27__MPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29__MPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31__MPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33__MPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R__MPCC_OGAM_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R__MPCC_OGAM_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R__MPCC_OGAM_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B__MPCC_OGAM_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G__MPCC_OGAM_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R__MPCC_OGAM_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1__MPCC_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3__MPCC_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5__MPCC_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7__MPCC_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9__MPCC_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11__MPCC_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13__MPCC_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15__MPCC_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17__MPCC_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19__MPCC_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21__MPCC_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23__MPCC_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25__MPCC_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27__MPCC_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29__MPCC_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31__MPCC_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33__MPCC_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT__MPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_OGAM3_MPCC_GAMUT_REMAP_MODE__MPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A__MPCC_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A__MPCC_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A__MPCC_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A__MPCC_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A__MPCC_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A__MPCC_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B__MPCC_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B__MPCC_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B__MPCC_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B__MPCC_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B__MPCC_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B__MPCC_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L + + +// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec +//MPC_OUT0_MUX +#define MPC_OUT0_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT0_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT0_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT0_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT0_DENORM_CONTROL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT0_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT0_DENORM_CLAMP_G_Y +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT0_DENORM_CLAMP_B_CB +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT0_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT1_MUX +#define MPC_OUT1_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT1_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT1_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT1_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT1_DENORM_CONTROL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT1_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT1_DENORM_CLAMP_G_Y +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT1_DENORM_CLAMP_B_CB +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT1_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT2_MUX +#define MPC_OUT2_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT2_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT2_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT2_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT2_DENORM_CONTROL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT2_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT2_DENORM_CLAMP_G_Y +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT2_DENORM_CLAMP_B_CB +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT2_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT3_MUX +#define MPC_OUT3_MUX__MPC_OUT_MUX__SHIFT 0x0 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR__SHIFT 0x5 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK__SHIFT 0x7 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE__SHIFT 0x8 +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL__SHIFT 0x9 +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE__SHIFT 0xa +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT__SHIFT 0xb +#define MPC_OUT3_MUX__MPC_OUT_MUX_MASK 0x0000000FL +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_OVFL_ERROR_MASK 0x00000020L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_ERROR_ACK_MASK 0x00000080L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_DISABLE_MASK 0x00000100L +#define MPC_OUT3_MUX__MPC_OUT_RATE_CONTROL_MASK 0x00000200L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_MODE_MASK 0x00000400L +#define MPC_OUT3_MUX__MPC_OUT_FLOW_CONTROL_COUNT_MASK 0x007FF800L +//MPC_OUT3_DENORM_CONTROL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x0 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0xc +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE__SHIFT 0x18 +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00FFF000L +#define MPC_OUT3_DENORM_CONTROL__MPC_OUT_DENORM_MODE_MASK 0x07000000L +//MPC_OUT3_DENORM_CLAMP_G_Y +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_G_Y__MPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00FFF000L +//MPC_OUT3_DENORM_CLAMP_B_CB +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x0 +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0xc +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000FFFL +#define MPC_OUT3_DENORM_CLAMP_B_CB__MPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00FFF000L +//MPC_OUT_CSC_COEF_FORMAT +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT__SHIFT 0x0 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT__SHIFT 0x1 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT__SHIFT 0x2 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT__SHIFT 0x3 +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC0_COEF_FORMAT_MASK 0x00000001L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC1_COEF_FORMAT_MASK 0x00000002L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC2_COEF_FORMAT_MASK 0x00000004L +#define MPC_OUT_CSC_COEF_FORMAT__MPC_OCSC3_COEF_FORMAT_MASK 0x00000008L +//MPC_OUT0_CSC_MODE +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT0_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT0_CSC_C11_C12_A +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_A +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_A +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_A +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_A +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_A +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C11_C12_B +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C13_C14_B +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C21_C22_B +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C23_C24_B +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C31_C32_B +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT0_CSC_C33_C34_B +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT0_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_MODE +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT1_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT1_CSC_C11_C12_A +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_A +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_A +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_A +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_A +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_A +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C11_C12_B +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C13_C14_B +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C21_C22_B +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C23_C24_B +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C31_C32_B +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT1_CSC_C33_C34_B +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT1_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_MODE +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT2_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT2_CSC_C11_C12_A +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_A +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_A +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_A +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_A +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_A +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C11_C12_B +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C13_C14_B +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C21_C22_B +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C23_C24_B +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C31_C32_B +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT2_CSC_C33_C34_B +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT2_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_MODE +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE__SHIFT 0x0 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT__SHIFT 0x7 +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_MASK 0x00000003L +#define MPC_OUT3_CSC_MODE__MPC_OCSC_MODE_CURRENT_MASK 0x00000180L +//MPC_OUT3_CSC_C11_C12_A +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C11_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_A__MPC_OCSC_C12_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_A +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C13_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_A__MPC_OCSC_C14_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_A +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C21_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_A__MPC_OCSC_C22_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_A +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C23_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_A__MPC_OCSC_C24_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_A +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C31_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_A__MPC_OCSC_C32_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_A +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C33_A_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_A__MPC_OCSC_C34_A_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C11_C12_B +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C11_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C11_C12_B__MPC_OCSC_C12_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C13_C14_B +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C13_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C13_C14_B__MPC_OCSC_C14_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C21_C22_B +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C21_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C21_C22_B__MPC_OCSC_C22_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C23_C24_B +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C23_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C23_C24_B__MPC_OCSC_C24_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C31_C32_B +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C31_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C31_C32_B__MPC_OCSC_C32_B_MASK 0xFFFF0000L +//MPC_OUT3_CSC_C33_C34_B +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B__SHIFT 0x0 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B__SHIFT 0x10 +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C33_B_MASK 0x0000FFFFL +#define MPC_OUT3_CSC_C33_C34_B__MPC_OCSC_C34_B_MASK 0xFFFF0000L +//MPC_OCSC_TEST_DEBUG_INDEX +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MPC_OCSC_TEST_DEBUG_INDEX__MPC_OCSC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MPC_OCSC_TEST_DEBUG_DATA +#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA__SHIFT 0x0 +#define MPC_OCSC_TEST_DEBUG_DATA__MPC_OCSC_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpc_rmcm0_dispdec +//MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMCM0_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM0_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM0_MPC_RMCM_3DLUT_MODE +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE_MASK 0x00000030L +#define MPC_RMCM0_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMCM0_MPC_RMCM_3DLUT_INDEX +#define MPC_RMCM0_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX_MASK 0x00003FFFL +//MPC_RMCM0_MPC_RMCM_3DLUT_DATA +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMCM0_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPC_RMCM0_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPC_RMCM0_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +//MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPC_RMCM0_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L +//MPC_RMCM0_MPC_RMCM_CNTL +#define MPC_RMCM0_MPC_RMCM_CNTL__MPC_RMCM_CNTL__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_CNTL__MPC_RMCM_CNTL_MASK 0x0000000FL +//MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_INDEX__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_INDEX__MPC_RMCM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA__MPC_RMCM_TEST_DEBUG_DATA__SHIFT 0x0 +#define MPC_RMCM0_MPC_RMCM_TEST_DEBUG_DATA__MPC_RMCM_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpc_rmcm1_dispdec +//MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_SHAPER_CONTROL__MPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_R__MPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_G__MPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_OFFSET_B__MPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_R__MPC_RMCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_SCALE_G_B__MPC_RMCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_INDEX__MPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_DATA__MPC_RMCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPC_RMCM1_MPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__MPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_START_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_B__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_G__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_END_CNTL_R__MPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_0_1__MPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_2_3__MPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_4_5__MPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_6_7__MPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_8_9__MPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_10_11__MPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_12_13__MPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_14_15__MPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_16_17__MPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_18_19__MPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_20_21__MPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_22_23__MPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_24_25__MPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_26_27__MPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_28_29__MPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_30_31__MPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMA_REGION_32_33__MPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_START_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_B__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_G__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_END_CNTL_R__MPC_RMCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_0_1__MPC_RMCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_2_3__MPC_RMCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_4_5__MPC_RMCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_6_7__MPC_RMCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_8_9__MPC_RMCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_10_11__MPC_RMCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_12_13__MPC_RMCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_14_15__MPC_RMCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_16_17__MPC_RMCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_18_19__MPC_RMCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_20_21__MPC_RMCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_22_23__MPC_RMCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_24_25__MPC_RMCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_26_27__MPC_RMCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_28_29__MPC_RMCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_30_31__MPC_RMCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPC_RMCM1_MPC_RMCM_SHAPER_RAMB_REGION_32_33__MPC_RMCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPC_RMCM1_MPC_RMCM_3DLUT_MODE +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_SIZE_MASK 0x00000030L +#define MPC_RMCM1_MPC_RMCM_3DLUT_MODE__MPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPC_RMCM1_MPC_RMCM_3DLUT_INDEX +#define MPC_RMCM1_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_INDEX__MPC_RMCM_3DLUT_INDEX_MASK 0x00003FFFL +//MPC_RMCM1_MPC_RMCM_3DLUT_DATA +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA__MPC_RMCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_3DLUT_DATA_30BIT__MPC_RMCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPC_RMCM1_MPC_RMCM_3DLUT_READ_WRITE_CONTROL__MPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_NORM_FACTOR__MPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_R__MPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_G__MPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_3DLUT_OUT_OFFSET_B__MPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_COEF_FORMAT__MPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_MODE__MPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_A__MPC_RMCM_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_A__MPC_RMCM_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_A__MPC_RMCM_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_A__MPC_RMCM_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_A__MPC_RMCM_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_A__MPC_RMCM_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C11_C12_B__MPC_RMCM_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C13_C14_B__MPC_RMCM_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C21_C22_B__MPC_RMCM_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C23_C24_B__MPC_RMCM_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C31_C32_B__MPC_RMCM_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPC_RMCM1_MPC_RMCM_GAMUT_REMAP_C33_C34_B__MPC_RMCM_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPC_RMCM1_MPC_RMCM_MEM_PWR_CTRL__MPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +//MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_SELECT__MPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPC_RMCM1_MPC_RMCM_3DLUT_FAST_LOAD_STATUS__MPC_RMCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L +//MPC_RMCM1_MPC_RMCM_CNTL +#define MPC_RMCM1_MPC_RMCM_CNTL__MPC_RMCM_CNTL__SHIFT 0x0 +#define MPC_RMCM1_MPC_RMCM_CNTL__MPC_RMCM_CNTL_MASK 0x0000000FL + + +// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON22_PERFCOUNTER_CNTL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_CNTL2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON22_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFCOUNTER_STATE +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON22_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON22_PERFMON_CNTL +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON22_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON22_PERFMON_CNTL2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON22_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON22_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON22_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON22_PERFMON_CVALUE_LOW +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON22_PERFMON_HI +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON22_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON22_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON22_PERFMON_LOW +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON22_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_mpc_mpcc_mcm0_dispdec +//MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM0_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM0_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM0_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM0_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM0_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM0_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_mcm1_dispdec +//MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM1_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM1_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM1_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM1_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM1_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM1_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM1_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_mcm2_dispdec +//MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM2_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM2_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM2_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM2_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM2_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM2_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpcc_mcm3_dispdec +//MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_LUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_SHAPER_CONTROL__MPCC_MCM_SHAPER_MODE_CURRENT_MASK 0x0000000CL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_R__MPCC_MCM_SHAPER_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_G__MPCC_MCM_SHAPER_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_OFFSET_B__MPCC_MCM_SHAPER_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_R__MPCC_MCM_SHAPER_SCALE_R_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_SCALE_G_B__MPCC_MCM_SHAPER_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_INDEX__MPCC_MCM_SHAPER_LUT_INDEX_MASK 0x000000FFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_DATA__MPCC_MCM_SHAPER_LUT_DATA_MASK 0x00FFFFFFL +//MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_SHAPER_LUT_WRITE_EN_MASK__MPCC_MCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_START_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_B__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_G__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_END_CNTL_R__MPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_0_1__MPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_2_3__MPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_4_5__MPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_6_7__MPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_8_9__MPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_10_11__MPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_12_13__MPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_14_15__MPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_16_17__MPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_18_19__MPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_20_21__MPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_22_23__MPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_24_25__MPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_26_27__MPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_28_29__MPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_30_31__MPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMA_REGION_32_33__MPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_START_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_B__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_B_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_G__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_G_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_END_CNTL_R__MPCC_MCM_SHAPER_RAMB_EXP_REGION_END_BASE_R_MASK 0x3FFF0000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_0_1__MPCC_MCM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_2_3__MPCC_MCM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_4_5__MPCC_MCM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_6_7__MPCC_MCM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_8_9__MPCC_MCM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_10_11__MPCC_MCM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_12_13__MPCC_MCM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_14_15__MPCC_MCM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_16_17__MPCC_MCM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_18_19__MPCC_MCM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_20_21__MPCC_MCM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_22_23__MPCC_MCM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_24_25__MPCC_MCM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_26_27__MPCC_MCM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_28_29__MPCC_MCM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_30_31__MPCC_MCM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_SHAPER_RAMB_REGION_32_33__MPCC_MCM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_3DLUT_MODE +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_SIZE_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_3DLUT_MODE__MPCC_MCM_3DLUT_MODE_CURRENT_MASK 0x00000300L +//MPCC_MCM3_MPCC_MCM_3DLUT_INDEX +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_INDEX__MPCC_MCM_3DLUT_INDEX_MASK 0x000007FFL +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA0_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA__MPCC_MCM_3DLUT_DATA1_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_3DLUT_DATA_30BIT__MPCC_MCM_3DLUT_DATA_30BIT_MASK 0xFFFFFFFCL +//MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000FL +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_RAM_SEL_MASK 0x00000010L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_30BIT_EN_MASK 0x00000100L +#define MPCC_MCM3_MPCC_MCM_3DLUT_READ_WRITE_CONTROL__MPCC_MCM_3DLUT_READ_SEL_MASK 0x00030000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_NORM_FACTOR__MPCC_MCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000FFFFL +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_OFFSET_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_R__MPCC_MCM_3DLUT_OUT_SCALE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_OFFSET_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_G__MPCC_MCM_3DLUT_OUT_SCALE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_OFFSET_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_3DLUT_OUT_OFFSET_B__MPCC_MCM_3DLUT_OUT_SCALE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_1DLUT_CONTROL__MPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040L +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_INDEX__MPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001FFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_DATA__MPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x6 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040L +#define MPCC_MCM3_MPCC_MCM_1DLUT_LUT_CONTROL__MPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_B__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_G__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL1_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_END_CNTL2_R__MPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_B__MPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_G__MPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_OFFSET_R__MPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_0_1__MPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_2_3__MPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_4_5__MPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_6_7__MPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_8_9__MPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_10_11__MPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_12_13__MPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_14_15__MPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_16_17__MPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_18_19__MPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_20_21__MPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_22_23__MPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_24_25__MPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_26_27__MPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_28_29__MPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_30_31__MPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMA_REGION_32_33__MPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_B_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_B_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_G_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_G_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_R_MASK 0x0003FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SEGMENT_R_MASK 0x07F00000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_SLOPE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_SLOPE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_START_BASE_CNTL_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_START_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_B_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_B__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_G_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_G_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_G__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_G_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL1_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_BASE_R_MASK 0x0003FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_R_MASK 0x0000FFFFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_END_CNTL2_R__MPCC_MCM_1DLUT_RAMB_EXP_REGION_END_SLOPE_R_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_B__MPCC_MCM_1DLUT_RAMB_OFFSET_B_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_G__MPCC_MCM_1DLUT_RAMB_OFFSET_G_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_OFFSET_R__MPCC_MCM_1DLUT_RAMB_OFFSET_R_MASK 0x0007FFFFL +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_0_1__MPCC_MCM_1DLUT_RAMB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_2_3__MPCC_MCM_1DLUT_RAMB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_4_5__MPCC_MCM_1DLUT_RAMB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_6_7__MPCC_MCM_1DLUT_RAMB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_8_9__MPCC_MCM_1DLUT_RAMB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_10_11__MPCC_MCM_1DLUT_RAMB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_12_13__MPCC_MCM_1DLUT_RAMB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_14_15__MPCC_MCM_1DLUT_RAMB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_16_17__MPCC_MCM_1DLUT_RAMB_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_18_19__MPCC_MCM_1DLUT_RAMB_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_20_21__MPCC_MCM_1DLUT_RAMB_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_22_23__MPCC_MCM_1DLUT_RAMB_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_24_25__MPCC_MCM_1DLUT_RAMB_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_26_27__MPCC_MCM_1DLUT_RAMB_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_28_29__MPCC_MCM_1DLUT_RAMB_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_30_31__MPCC_MCM_1DLUT_RAMB_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_LUT_OFFSET_MASK 0x000001FFL +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_LUT_OFFSET_MASK 0x01FF0000L +#define MPCC_MCM3_MPCC_MCM_1DLUT_RAMB_REGION_32_33__MPCC_MCM_1DLUT_RAMB_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000L +//MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_FIRST_GAMUT_REMAP_MODE__MPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_A__MPCC_MCM_FIRST_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_A__MPCC_MCM_FIRST_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_A__MPCC_MCM_FIRST_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_A__MPCC_MCM_FIRST_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_A__MPCC_MCM_FIRST_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_A__MPCC_MCM_FIRST_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C11_C12_B__MPCC_MCM_FIRST_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C13_C14_B__MPCC_MCM_FIRST_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C21_C22_B__MPCC_MCM_FIRST_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C23_C24_B__MPCC_MCM_FIRST_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C31_C32_B__MPCC_MCM_FIRST_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_FIRST_GAMUT_REMAP_C33_C34_B__MPCC_MCM_FIRST_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__MPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001L +//MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x7 +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_SECOND_GAMUT_REMAP_MODE__MPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C11_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_A__MPCC_MCM_SECOND_GAMUT_REMAP_C12_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C13_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_A__MPCC_MCM_SECOND_GAMUT_REMAP_C14_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C21_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_A__MPCC_MCM_SECOND_GAMUT_REMAP_C22_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C23_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_A__MPCC_MCM_SECOND_GAMUT_REMAP_C24_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C31_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_A__MPCC_MCM_SECOND_GAMUT_REMAP_C32_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C33_A_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_A__MPCC_MCM_SECOND_GAMUT_REMAP_C34_A_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C11_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C11_C12_B__MPCC_MCM_SECOND_GAMUT_REMAP_C12_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C13_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C13_C14_B__MPCC_MCM_SECOND_GAMUT_REMAP_C14_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C21_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C21_C22_B__MPCC_MCM_SECOND_GAMUT_REMAP_C22_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C23_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C23_C24_B__MPCC_MCM_SECOND_GAMUT_REMAP_C24_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C31_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C31_C32_B__MPCC_MCM_SECOND_GAMUT_REMAP_C32_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B__SHIFT 0x0 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B__SHIFT 0x10 +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C33_B_MASK 0x0000FFFFL +#define MPCC_MCM3_MPC_MCM_SECOND_GAMUT_REMAP_C33_C34_B__MPCC_MCM_SECOND_GAMUT_REMAP_C34_B_MASK 0xFFFF0000L +//MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x4 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x8 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS__SHIFT 0xa +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0xc +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x10 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x12 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x14 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE__SHIFT 0x18 +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE__SHIFT 0x1a +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x1c +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_3DLUT_MEM_PWR_STATE_MASK 0x0C000000L +#define MPCC_MCM3_MPCC_MCM_MEM_PWR_CTRL__MPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000L +//MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_SELECT__MPCC_MCM_3DLUT_FL_SEL_MASK 0x0000000FL +//MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE__SHIFT 0x0 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW__SHIFT 0x1 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW__SHIFT 0x2 +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_DONE_MASK 0x00000001L +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_SOFT_UNDERFLOW_MASK 0x00000002L +#define MPCC_MCM3_MPCC_MCM_3DLUT_FAST_LOAD_STATUS__MPCC_MCM_3DLUT_FL_HARD_UNDERFLOW_MASK 0x00000004L + + +// addressBlock: dce_dc_mpc_mpc_cfg_dispdec +//MPC_CLOCK_CONTROL +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE0_GATE_DISABLE__SHIFT 0x0 +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE1_GATE_DISABLE__SHIFT 0x1 +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE2_GATE_DISABLE__SHIFT 0x2 +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE3_GATE_DISABLE__SHIFT 0x3 +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE__SHIFT 0x8 +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL__SHIFT 0xc +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE0_GATE_DISABLE_MASK 0x00000001L +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE1_GATE_DISABLE_MASK 0x00000002L +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE2_GATE_DISABLE_MASK 0x00000004L +#define MPC_CLOCK_CONTROL__DISPCLK_G_PIPE3_GATE_DISABLE_MASK 0x00000008L +#define MPC_CLOCK_CONTROL__DISPCLK_R_GATE_DISABLE_MASK 0x00000100L +#define MPC_CLOCK_CONTROL__MPC_TEST_CLK_SEL_MASK 0x0000F000L +//MPC_SOFT_RESET +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET__SHIFT 0x0 +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET__SHIFT 0x1 +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET__SHIFT 0x2 +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET__SHIFT 0x3 +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET__SHIFT 0xa +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET__SHIFT 0xb +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET__SHIFT 0xc +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET__SHIFT 0xd +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET__SHIFT 0x14 +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET__SHIFT 0x15 +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET__SHIFT 0x16 +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET__SHIFT 0x17 +#define MPC_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x1f +#define MPC_SOFT_RESET__MPCC0_SOFT_RESET_MASK 0x00000001L +#define MPC_SOFT_RESET__MPCC1_SOFT_RESET_MASK 0x00000002L +#define MPC_SOFT_RESET__MPCC2_SOFT_RESET_MASK 0x00000004L +#define MPC_SOFT_RESET__MPCC3_SOFT_RESET_MASK 0x00000008L +#define MPC_SOFT_RESET__MPC_SFR0_SOFT_RESET_MASK 0x00000400L +#define MPC_SOFT_RESET__MPC_SFR1_SOFT_RESET_MASK 0x00000800L +#define MPC_SOFT_RESET__MPC_SFR2_SOFT_RESET_MASK 0x00001000L +#define MPC_SOFT_RESET__MPC_SFR3_SOFT_RESET_MASK 0x00002000L +#define MPC_SOFT_RESET__MPC_SFT0_SOFT_RESET_MASK 0x00100000L +#define MPC_SOFT_RESET__MPC_SFT1_SOFT_RESET_MASK 0x00200000L +#define MPC_SOFT_RESET__MPC_SFT2_SOFT_RESET_MASK 0x00400000L +#define MPC_SOFT_RESET__MPC_SFT3_SOFT_RESET_MASK 0x00800000L +#define MPC_SOFT_RESET__MPC_SOFT_RESET_MASK 0x80000000L +//MPC_CRC_CTRL +#define MPC_CRC_CTRL__MPC_CRC_EN__SHIFT 0x0 +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN__SHIFT 0x4 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE__SHIFT 0x8 +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN__SHIFT 0xa +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE__SHIFT 0xc +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL__SHIFT 0x18 +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING__SHIFT 0x1c +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED__SHIFT 0x1e +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK__SHIFT 0x1f +#define MPC_CRC_CTRL__MPC_CRC_EN_MASK 0x00000001L +#define MPC_CRC_CTRL__MPC_CRC_CONT_EN_MASK 0x00000010L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_MODE_MASK 0x00000300L +#define MPC_CRC_CTRL__MPC_CRC_STEREO_EN_MASK 0x00000400L +#define MPC_CRC_CTRL__MPC_CRC_INTERLACE_MODE_MASK 0x00003000L +#define MPC_CRC_CTRL__MPC_CRC_SRC_SEL_MASK 0x03000000L +#define MPC_CRC_CTRL__MPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_ENABLED_MASK 0x40000000L +#define MPC_CRC_CTRL__MPC_CRC_UPDATE_LOCK_MASK 0x80000000L +//MPC_CRC_SEL_CONTROL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL__SHIFT 0x0 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL__SHIFT 0x4 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL__SHIFT 0x8 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK__SHIFT 0x10 +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DPP_SEL_MASK 0x0000000FL +#define MPC_CRC_SEL_CONTROL__MPC_CRC_OPP_SEL_MASK 0x000000F0L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_DWB_SEL_MASK 0x00000300L +#define MPC_CRC_SEL_CONTROL__MPC_CRC_MASK_MASK 0xFFFF0000L +//MPC_CRC_RESULT_A +#define MPC_CRC_RESULT_A__MPC_CRC_RESULT_A__SHIFT 0x0 +#define MPC_CRC_RESULT_A__MPC_CRC_RESULT_A_MASK 0xFFFFFFFFL +//MPC_CRC_RESULT_R +#define MPC_CRC_RESULT_R__MPC_CRC_RESULT_R__SHIFT 0x0 +#define MPC_CRC_RESULT_R__MPC_CRC_RESULT_R_MASK 0xFFFFFFFFL +//MPC_CRC_RESULT_G +#define MPC_CRC_RESULT_G__MPC_CRC_RESULT_G__SHIFT 0x0 +#define MPC_CRC_RESULT_G__MPC_CRC_RESULT_G_MASK 0xFFFFFFFFL +//MPC_CRC_RESULT_B +#define MPC_CRC_RESULT_B__MPC_CRC_RESULT_B__SHIFT 0x0 +#define MPC_CRC_RESULT_B__MPC_CRC_RESULT_B_MASK 0xFFFFFFFFL +//MPC_PERFMON_EVENT_CTRL +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN__SHIFT 0x0 +#define MPC_PERFMON_EVENT_CTRL__MPC_PERFMON_EVENT_EN_MASK 0x00000001L +//MPC_BYPASS_BG_AR +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA__SHIFT 0x0 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR__SHIFT 0x10 +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_ALPHA_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_AR__MPC_BYPASS_BG_R_CR_MASK 0xFFFF0000L +//MPC_BYPASS_BG_GB +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y__SHIFT 0x0 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB__SHIFT 0x10 +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_G_Y_MASK 0x0000FFFFL +#define MPC_BYPASS_BG_GB__MPC_BYPASS_BG_B_CB_MASK 0xFFFF0000L +//MPC_HOST_READ_CONTROL +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x0 +#define MPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000FFL +//MPC_DPP_PENDING_STATUS +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING__SHIFT 0x0 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING__SHIFT 0x2 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING__SHIFT 0x4 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING__SHIFT 0x5 +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING__SHIFT 0x6 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING__SHIFT 0x8 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING__SHIFT 0xa +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING__SHIFT 0xc +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING__SHIFT 0xd +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING__SHIFT 0xe +#define MPC_DPP_PENDING_STATUS__IN_DPP0_SURFACE_UPDATE_PENDING_MASK 0x00000001L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_DPP_PENDING_STATUS__IN_DPP0_CURSOR_UPDATE_PENDING_MASK 0x00000004L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_SURFACE_UPDATE_PENDING_MASK 0x00000010L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CONFIG_UPDATE_PENDING_MASK 0x00000020L +#define MPC_DPP_PENDING_STATUS__IN_DPP1_CURSOR_UPDATE_PENDING_MASK 0x00000040L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_SURFACE_UPDATE_PENDING_MASK 0x00000100L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_DPP_PENDING_STATUS__IN_DPP2_CURSOR_UPDATE_PENDING_MASK 0x00000400L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_SURFACE_UPDATE_PENDING_MASK 0x00001000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CONFIG_UPDATE_PENDING_MASK 0x00002000L +#define MPC_DPP_PENDING_STATUS__IN_DPP3_CURSOR_UPDATE_PENDING_MASK 0x00004000L +//MPC_PENDING_STATUS_MISC +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING__SHIFT 0x0 +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING__SHIFT 0x1 +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING__SHIFT 0x2 +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING__SHIFT 0x3 +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x8 +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING__SHIFT 0x9 +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING__SHIFT 0xa +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING__SHIFT 0xb +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING__SHIFT 0x10 +#define MPC_PENDING_STATUS_MISC__OUT_OPP0_CONFIG_UPDATE_PENDING_MASK 0x00000001L +#define MPC_PENDING_STATUS_MISC__OUT_OPP1_CONFIG_UPDATE_PENDING_MASK 0x00000002L +#define MPC_PENDING_STATUS_MISC__OUT_OPP2_CONFIG_UPDATE_PENDING_MASK 0x00000004L +#define MPC_PENDING_STATUS_MISC__OUT_OPP3_CONFIG_UPDATE_PENDING_MASK 0x00000008L +#define MPC_PENDING_STATUS_MISC__MPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100L +#define MPC_PENDING_STATUS_MISC__MPCC1_CONFIG_UPDATE_PENDING_MASK 0x00000200L +#define MPC_PENDING_STATUS_MISC__MPCC2_CONFIG_UPDATE_PENDING_MASK 0x00000400L +#define MPC_PENDING_STATUS_MISC__MPCC3_CONFIG_UPDATE_PENDING_MASK 0x00000800L +#define MPC_PENDING_STATUS_MISC__IN_DWB0_CONFIG_UPDATE_PENDING_MASK 0x00010000L +//ADR_CFG_CUR_VUPDATE_LOCK_SET0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET0__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET0__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET0__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET0__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET0__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET1 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET1__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET1 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET1__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET1 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET1__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET1 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET1__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET1 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET1__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET2 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET2__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET2 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET2__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET2 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET2__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET2 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET2__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET2 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET2__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_CUR_VUPDATE_LOCK_SET3 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_CUR_VUPDATE_LOCK_SET3__ADR_CFG_CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_CFG_VUPDATE_LOCK_SET3 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_CFG_VUPDATE_LOCK_SET3__ADR_CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//ADR_VUPDATE_LOCK_SET3 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define ADR_VUPDATE_LOCK_SET3__ADR_VUPDATE_LOCK_SET_MASK 0x00000001L +//CFG_VUPDATE_LOCK_SET3 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CFG_VUPDATE_LOCK_SET3__CFG_VUPDATE_LOCK_SET_MASK 0x00000001L +//CUR_VUPDATE_LOCK_SET3 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET__SHIFT 0x0 +#define CUR_VUPDATE_LOCK_SET3__CUR_VUPDATE_LOCK_SET_MASK 0x00000001L +//HUBP0_3DLUT_FL_CONFIG +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP0_3DLUT_FL_CONFIG__HUBP0_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP0_3DLUT_FL_BIAS_SCALE +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP0_3DLUT_FL_BIAS_SCALE__HUBP0_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//HUBP1_3DLUT_FL_CONFIG +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP1_3DLUT_FL_CONFIG__HUBP1_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP1_3DLUT_FL_BIAS_SCALE +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP1_3DLUT_FL_BIAS_SCALE__HUBP1_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//HUBP2_3DLUT_FL_CONFIG +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP2_3DLUT_FL_CONFIG__HUBP2_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP2_3DLUT_FL_BIAS_SCALE +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP2_3DLUT_FL_BIAS_SCALE__HUBP2_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//HUBP3_3DLUT_FL_CONFIG +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_MODE__SHIFT 0x0 +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_FORMAT__SHIFT 0x4 +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_MODE_MASK 0x00000003L +#define HUBP3_3DLUT_FL_CONFIG__HUBP3_3DLUT_FL_FORMAT_MASK 0x00000030L +//HUBP3_3DLUT_FL_BIAS_SCALE +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_BIAS__SHIFT 0x0 +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_SCALE__SHIFT 0x10 +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_BIAS_MASK 0x0000FFFFL +#define HUBP3_3DLUT_FL_BIAS_SCALE__HUBP3_3DLUT_FL_SCALE_MASK 0xFFFF0000L +//MPC_DWB0_MUX +#define MPC_DWB0_MUX__MPC_DWB0_MUX__SHIFT 0x0 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS__SHIFT 0x4 +#define MPC_DWB0_MUX__MPC_DWB0_MUX_MASK 0x0000000FL +#define MPC_DWB0_MUX__MPC_DWB0_MUX_STATUS_MASK 0x000000F0L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dispdec +//HDMI_STREAM_ENC_CLOCK_CONTROL +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_SOCCLK__SHIFT 0x9 +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_HDMISTREAMCLK__SHIFT 0xd +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_DISPCLK_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_SOCCLK_MASK 0x00000200L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_CLOCK_ON_HDMISTREAMCLK_MASK 0x00001000L +#define HDMI_STREAM_ENC_CLOCK_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_ON_HDMISTREAMCLK_MASK 0x00002000L +//HDMI_STREAM_ENC_INPUT_MUX_CONTROL +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_INPUT_MUX_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_SOURCE_SEL_MASK 0x00000007L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE__SHIFT 0x8 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_UNCOMPRESSED_PIXEL_FORMAT__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_COMPRESSED_PIXEL_FORMAT__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE__SHIFT 0x14 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR__SHIFT 0x1c +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ENABLE_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_MASK 0x00000010L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_PIXEL_ENCODING_TYPE_MASK 0x00000100L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_UNCOMPRESSED_PIXEL_FORMAT_MASK 0x00001000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_COMPRESSED_PIXEL_FORMAT_MASK 0x00010000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_RESET_DONE_MASK 0x00100000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_VIDEO_STREAM_ACTIVE_MASK 0x01000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0__FIFO_ERROR_MASK 0x30000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x1 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL__SHIFT 0x4 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY__SHIFT 0xa +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL__SHIFT 0xc +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL__SHIFT 0x10 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x18 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED__SHIFT 0x1f +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000001L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECAL_AVERAGE_MASK 0x00000002L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_FORCE_RECOMP_MINMAX_MASK 0x00000004L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_OVERWRITE_LEVEL_MASK 0x000003F0L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_LEVEL_DET_DELAY_MASK 0x00000C00L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MINIMUM_LEVEL_MASK 0x0000F000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_MAXIMUM_LEVEL_MASK 0x001F0000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CAL_AVERAGE_LEVEL_MASK 0x3F000000L +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL1__FIFO_CALIBRATED_MASK 0x80000000L +//HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC__SHIFT 0x6 +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_START_LEVEL_MASK 0x0000003FL +#define HDMI_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL2__FIFO_READ_CLOCK_SRC_MASK 0x00000040L +//HDMI_STREAM_ENC_AUDIO_CONTROL +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL__SHIFT 0x0 +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_EN__SHIFT 0x8 +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL_MASK 0x00000007L +#define HDMI_STREAM_ENC_AUDIO_CONTROL__HDMI_STREAM_ENC_APG_CLOCK_EN_MASK 0x00000100L + + +// addressBlock: dce_dc_hpo_hdmi_tb_enc0_dispdec +//HDMI_TB_ENC_CONTROL +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE__SHIFT 0x8 +#define HDMI_TB_ENC_CONTROL__HDMI_TB_ENC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_CONTROL__HDMI_RESET_DONE_MASK 0x00000100L +//HDMI_TB_ENC_PIXEL_FORMAT +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x8 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING__SHIFT 0x10 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE__SHIFT 0x18 +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DEEP_COLOR_DEPTH_MASK 0x00000300L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_PIXEL_ENCODING_MASK 0x00030000L +#define HDMI_TB_ENC_PIXEL_FORMAT__HDMI_DSC_MODE_MASK 0x03000000L +//HDMI_TB_ENC_PACKET_CONTROL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE__SHIFT 0x8 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW__SHIFT 0xc +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR__SHIFT 0x10 +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_PACKETS_PER_LINE_MASK 0x0000001FL +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_MAX_ISLANDS_PER_LINE_MASK 0x00000300L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_OVERFLOW_MASK 0x00001000L +#define HDMI_TB_ENC_PACKET_CONTROL__HDMI_TB_ENC_PACKET_ERROR_CLEAR_MASK 0x00010000L +//HDMI_TB_ENC_ACR_PACKET_CONTROL +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x4 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x8 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x10 +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x1f +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L +#define HDMI_TB_ENC_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE__SHIFT 0x6 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE__SHIFT 0x9 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND__SHIFT 0xc +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE__SHIFT 0xe +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_GC_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ISRC_LINE_REFERENCE_MASK 0x00000040L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_ACP_LINE_REFERENCE_MASK 0x00000200L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_REFERENCE_MASK 0x00004000L +#define HDMI_TB_ENC_VBI_PACKET_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_VBI_PACKET_CONTROL2 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ISRC_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_VBI_PACKET_CONTROL2__HDMI_ACP_LINE_MASK 0x7FFF0000L +//HDMI_TB_ENC_GC_CONTROL +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE__SHIFT 0x0 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT__SHIFT 0x2 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE__SHIFT 0x4 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_ACTIVE_AVMUTE__SHIFT 0x8 +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_MASK 0x00000001L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_DEFAULT_PHASE_MASK 0x00000010L +#define HDMI_TB_ENC_GC_CONTROL__HDMI_ACTIVE_AVMUTE_MASK 0x00000100L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN__SHIFT 0x1e +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC2_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC3_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC4_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC5_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC6_LINE_REFERENCE_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_CONT_MASK 0x20000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LOCK_EN_MASK 0x40000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL0__HDMI_GENERIC7_LINE_REFERENCE_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_CONT_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LOCK_EN_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC8_LINE_REFERENCE_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_CONT_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LOCK_EN_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC9_LINE_REFERENCE_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_CONT_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LOCK_EN_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC10_LINE_REFERENCE_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_CONT_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LOCK_EN_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC11_LINE_REFERENCE_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_CONT_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LOCK_EN_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC12_LINE_REFERENCE_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_CONT_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LOCK_EN_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC13_LINE_REFERENCE_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_CONT_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LOCK_EN_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL1__HDMI_GENERIC14_LINE_REFERENCE_MASK 0x08000000L +//HDMI_TB_ENC_GENERIC_PACKET_CONTROL2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING__SHIFT 0x1 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND__SHIFT 0x2 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING__SHIFT 0x3 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND__SHIFT 0x4 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING__SHIFT 0x5 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND__SHIFT 0x6 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING__SHIFT 0x7 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND__SHIFT 0x8 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING__SHIFT 0x9 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND__SHIFT 0xa +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING__SHIFT 0xb +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND__SHIFT 0xc +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING__SHIFT 0xd +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND__SHIFT 0xe +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING__SHIFT 0x11 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND__SHIFT 0x12 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING__SHIFT 0x13 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND__SHIFT 0x14 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING__SHIFT 0x15 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND__SHIFT 0x16 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING__SHIFT 0x17 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND__SHIFT 0x18 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING__SHIFT 0x19 +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND__SHIFT 0x1a +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING__SHIFT 0x1b +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND__SHIFT 0x1c +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING__SHIFT 0x1d +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_MASK 0x00000001L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC0_IMMEDIATE_SEND_PENDING_MASK 0x00000002L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_MASK 0x00000004L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC1_IMMEDIATE_SEND_PENDING_MASK 0x00000008L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_MASK 0x00000010L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC2_IMMEDIATE_SEND_PENDING_MASK 0x00000020L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_MASK 0x00000040L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC3_IMMEDIATE_SEND_PENDING_MASK 0x00000080L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_MASK 0x00000100L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC4_IMMEDIATE_SEND_PENDING_MASK 0x00000200L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_MASK 0x00000400L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC5_IMMEDIATE_SEND_PENDING_MASK 0x00000800L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_MASK 0x00001000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC6_IMMEDIATE_SEND_PENDING_MASK 0x00002000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_MASK 0x00004000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC7_IMMEDIATE_SEND_PENDING_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_MASK 0x00010000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC8_IMMEDIATE_SEND_PENDING_MASK 0x00020000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_MASK 0x00040000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC9_IMMEDIATE_SEND_PENDING_MASK 0x00080000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_MASK 0x00100000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC10_IMMEDIATE_SEND_PENDING_MASK 0x00200000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_MASK 0x00400000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC11_IMMEDIATE_SEND_PENDING_MASK 0x00800000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_MASK 0x01000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC12_IMMEDIATE_SEND_PENDING_MASK 0x02000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_MASK 0x04000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC13_IMMEDIATE_SEND_PENDING_MASK 0x08000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_MASK 0x10000000L +#define HDMI_TB_ENC_GENERIC_PACKET_CONTROL2__HDMI_GENERIC14_IMMEDIATE_SEND_PENDING_MASK 0x20000000L +//HDMI_TB_ENC_GENERIC_PACKET0_1_LINE +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC0_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET0_1_LINE__HDMI_GENERIC1_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET2_3_LINE +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC2_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET2_3_LINE__HDMI_GENERIC3_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET4_5_LINE +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC4_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET4_5_LINE__HDMI_GENERIC5_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET6_7_LINE +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC6_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET6_7_LINE__HDMI_GENERIC7_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET8_9_LINE +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC8_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET8_9_LINE__HDMI_GENERIC9_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET10_11_LINE +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC10_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET10_11_LINE__HDMI_GENERIC11_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET12_13_LINE +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP__SHIFT 0x1f +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC12_EMP_MASK 0x00008000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_LINE_MASK 0x7FFF0000L +#define HDMI_TB_ENC_GENERIC_PACKET12_13_LINE__HDMI_GENERIC13_EMP_MASK 0x80000000L +//HDMI_TB_ENC_GENERIC_PACKET14_LINE +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE__SHIFT 0x0 +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP__SHIFT 0xf +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_LINE_MASK 0x00007FFFL +#define HDMI_TB_ENC_GENERIC_PACKET14_LINE__HDMI_GENERIC14_EMP_MASK 0x00008000L +//HDMI_TB_ENC_DB_CONTROL +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING__SHIFT 0x0 +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE__SHIFT 0xc +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING__SHIFT 0xf +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_PENDING_MASK 0x00000001L +#define HDMI_TB_ENC_DB_CONTROL__HDMI_DB_DISABLE_MASK 0x00001000L +#define HDMI_TB_ENC_DB_CONTROL__VUPDATE_DB_PENDING_MASK 0x00008000L +//HDMI_TB_ENC_ACR_32_0 +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0xc +#define HDMI_TB_ENC_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_32_1 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_32_1__HDMI_ACR_N_32_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_44_0 +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0xc +#define HDMI_TB_ENC_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_44_1 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_44_1__HDMI_ACR_N_44_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_48_0 +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0xc +#define HDMI_TB_ENC_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_48_1 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_48_1__HDMI_ACR_N_48_MASK 0x000FFFFFL +//HDMI_TB_ENC_ACR_STATUS_0 +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0xc +#define HDMI_TB_ENC_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xFFFFF000L +//HDMI_TB_ENC_ACR_STATUS_1 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x0 +#define HDMI_TB_ENC_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000FFFFFL +//HDMI_TB_ENC_BUFFER_CONTROL +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x0 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN__SHIFT 0x1 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET__SHIFT 0x4 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x8 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL__SHIFT 0x18 +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000001L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_EN_MASK 0x00000002L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_MAX_MIN_LEVEL_RESET_MASK 0x00000010L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_BORROWBUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x0000FF00L +#define HDMI_TB_ENC_BUFFER_CONTROL__HDMI_RATE_BUFFER_PREFILL_OVERRIDE_LEVEL_MASK 0x1F000000L +//HDMI_TB_ENC_MEM_CTRL +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_TB_ENC_MEM_CTRL__BORROWBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L +//HDMI_TB_ENC_METADATA_PACKET_CONTROL +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE__SHIFT 0x4 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED__SHIFT 0x8 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE__SHIFT 0x10 +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_REFERENCE_MASK 0x00000010L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_MISSED_MASK 0x00000100L +#define HDMI_TB_ENC_METADATA_PACKET_CONTROL__HDMI_METADATA_PACKET_LINE_MASK 0xFFFF0000L +//HDMI_TB_ENC_H_ACTIVE_BLANK +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_H_ACTIVE_BLANK__HDMI_H_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_HC_ACTIVE_BLANK +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE__SHIFT 0x0 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK__SHIFT 0x10 +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_ACTIVE_MASK 0x00007FFFL +#define HDMI_TB_ENC_HC_ACTIVE_BLANK__HDMI_HC_BLANK_MASK 0x7FFF0000L +//HDMI_TB_ENC_CRC_CNTL +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN__SHIFT 0x1 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE__SHIFT 0x8 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL__SHIFT 0xa +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE__SHIFT 0x11 +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_EN_MASK 0x00000001L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_CONT_EN_MASK 0x00000002L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_TYPE_MASK 0x00000300L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_SRC_SEL_MASK 0x00000C00L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_EN_MASK 0x00010000L +#define HDMI_TB_ENC_CRC_CNTL__HDMI_CRC_INTERLACE_MODE_MASK 0x00060000L +//HDMI_TB_ENC_CRC_RESULT_0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1__SHIFT 0x10 +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE0_MASK 0x0000FFFFL +#define HDMI_TB_ENC_CRC_RESULT_0__CRC_TRIBYTE1_MASK 0xFFFF0000L +//HDMI_TB_ENC_ENCRYPTION_CONTROL +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE__SHIFT 0x0 +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE__SHIFT 0x4 +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_ENABLE_MASK 0x00000001L +#define HDMI_TB_ENC_ENCRYPTION_CONTROL__HDMI_EESS_WHEN_AVMUTE_MASK 0x00000010L +//HDMI_TB_ENC_MODE +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE__SHIFT 0x0 +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK__SHIFT 0x8 +#define HDMI_TB_ENC_MODE__HDMI_BORROW_MODE_MASK 0x00000003L +#define HDMI_TB_ENC_MODE__HDMI_SKIP_FIRST_HBLANK_MASK 0x00000100L +//HDMI_TB_ENC_INPUT_FIFO_STATUS +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR__SHIFT 0x0 +#define HDMI_TB_ENC_INPUT_FIFO_STATUS__INPUT_FIFO_ERROR_MASK 0x00000001L +//HDMI_TB_ENC_CRC_RESULT_1 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2__SHIFT 0x0 +#define HDMI_TB_ENC_CRC_RESULT_1__CRC_TRIBYTE2_MASK 0x0000FFFFL + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_apg_apg_dispdec +//APG9_APG_DBG_GEN_CONTROL +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE__SHIFT 0x0 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET__SHIFT 0x1 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE__SHIFT 0x8 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE__SHIFT 0x18 +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_ENABLE_MASK 0x00000001L +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_GEN_RESET_MASK 0x00000002L +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_CHANNEL_ENABLE_MASK 0x0000FF00L +#define APG9_APG_DBG_GEN_CONTROL__APG_DBG_AUDIO_TEST_CH_DISABLE_MASK 0xFF000000L +//APG9_APG_MEM_PWR +#define APG9_APG_MEM_PWR__APG_MEM_PWR_DIS__SHIFT 0x0 +#define APG9_APG_MEM_PWR__APG_MEM_PWR_FORCE__SHIFT 0x4 +#define APG9_APG_MEM_PWR__APG_MEM_PWR_STATE__SHIFT 0x8 +#define APG9_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE__SHIFT 0xc +#define APG9_APG_MEM_PWR__APG_MEM_PWR_DIS_MASK 0x00000001L +#define APG9_APG_MEM_PWR__APG_MEM_PWR_FORCE_MASK 0x00000030L +#define APG9_APG_MEM_PWR__APG_MEM_PWR_STATE_MASK 0x00000300L +#define APG9_APG_MEM_PWR__APG_MEM_DEFAULT_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_vpg_vpg_dispdec +//VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_ACCESS_CTRL__VPG_GENERIC_DATA_INDEX_MASK 0x000000FFL +//VPG9_VPG_GENERIC_PACKET_DATA +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_GENERIC_PACKET_DATA__VPG_GENERIC_DATA_BYTE3_MASK 0xFF000000L +//VPG9_VPG_GSP_FRAME_UPDATE_CTRL +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC0_FRAME_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC1_FRAME_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC2_FRAME_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC3_FRAME_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC4_FRAME_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC5_FRAME_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC6_FRAME_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC7_FRAME_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC8_FRAME_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC9_FRAME_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC10_FRAME_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC11_FRAME_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC12_FRAME_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC13_FRAME_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_FRAME_UPDATE_CTRL__VPG_GENERIC14_FRAME_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE__SHIFT 0x0 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE__SHIFT 0x1 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE__SHIFT 0x2 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE__SHIFT 0x3 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE__SHIFT 0x4 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE__SHIFT 0x5 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE__SHIFT 0x6 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE__SHIFT 0x7 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE__SHIFT 0x8 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE__SHIFT 0x9 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE__SHIFT 0xa +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE__SHIFT 0xb +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE__SHIFT 0xc +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE__SHIFT 0xd +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE__SHIFT 0xe +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING__SHIFT 0x10 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING__SHIFT 0x11 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING__SHIFT 0x12 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING__SHIFT 0x13 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING__SHIFT 0x14 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING__SHIFT 0x15 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING__SHIFT 0x16 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING__SHIFT 0x17 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING__SHIFT 0x18 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING__SHIFT 0x19 +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1a +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1b +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1c +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1d +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING__SHIFT 0x1e +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_MASK 0x00000001L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_MASK 0x00000002L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_MASK 0x00000004L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_MASK 0x00000008L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_MASK 0x00000010L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_MASK 0x00000020L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_MASK 0x00000040L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_MASK 0x00000080L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_MASK 0x00000100L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_MASK 0x00000200L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_MASK 0x00000400L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_MASK 0x00000800L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_MASK 0x00001000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_MASK 0x00002000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_MASK 0x00004000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC0_IMMEDIATE_UPDATE_PENDING_MASK 0x00010000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC1_IMMEDIATE_UPDATE_PENDING_MASK 0x00020000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC2_IMMEDIATE_UPDATE_PENDING_MASK 0x00040000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC3_IMMEDIATE_UPDATE_PENDING_MASK 0x00080000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC4_IMMEDIATE_UPDATE_PENDING_MASK 0x00100000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC5_IMMEDIATE_UPDATE_PENDING_MASK 0x00200000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC6_IMMEDIATE_UPDATE_PENDING_MASK 0x00400000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC7_IMMEDIATE_UPDATE_PENDING_MASK 0x00800000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC8_IMMEDIATE_UPDATE_PENDING_MASK 0x01000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC9_IMMEDIATE_UPDATE_PENDING_MASK 0x02000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC10_IMMEDIATE_UPDATE_PENDING_MASK 0x04000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC11_IMMEDIATE_UPDATE_PENDING_MASK 0x08000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC12_IMMEDIATE_UPDATE_PENDING_MASK 0x10000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC13_IMMEDIATE_UPDATE_PENDING_MASK 0x20000000L +#define VPG9_VPG_GSP_IMMEDIATE_UPDATE_CTRL__VPG_GENERIC14_IMMEDIATE_UPDATE_PENDING_MASK 0x40000000L +//VPG9_VPG_GENERIC_STATUS +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS__SHIFT 0x0 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED__SHIFT 0x1 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR__SHIFT 0x4 +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_LOCK_STATUS_MASK 0x00000001L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_OCCURED_MASK 0x00000002L +#define VPG9_VPG_GENERIC_STATUS__VPG_GENERIC_CONFLICT_CLR_MASK 0x00000010L +//VPG9_VPG_MEM_PWR +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS__SHIFT 0x0 +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE__SHIFT 0x4 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE__SHIFT 0x8 +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L +#define VPG9_VPG_MEM_PWR__VPG_GSP_LIGHT_SLEEP_FORCE_MASK 0x00000010L +#define VPG9_VPG_MEM_PWR__VPG_GSP_MEM_PWR_STATE_MASK 0x00000100L +//VPG9_VPG_ISRC1_2_ACCESS_CTRL +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_ACCESS_CTRL__VPG_ISRC1_2_DATA_INDEX_MASK 0x0000000FL +//VPG9_VPG_ISRC1_2_DATA +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0__SHIFT 0x0 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1__SHIFT 0x8 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2__SHIFT 0x10 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3__SHIFT 0x18 +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE0_MASK 0x000000FFL +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE1_MASK 0x0000FF00L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE2_MASK 0x00FF0000L +#define VPG9_VPG_ISRC1_2_DATA__VPG_ISRC_DATA_BYTE3_MASK 0xFF000000L + + +// addressBlock: dce_dc_hpo_hdmi_stream_enc0_dme_dme_dispdec +//DME9_DME_CONTROL +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID__SHIFT 0x0 +#define DME9_DME_CONTROL__METADATA_ENGINE_EN__SHIFT 0x4 +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE__SHIFT 0x8 +#define DME9_DME_CONTROL__METADATA_DB_PENDING__SHIFT 0xc +#define DME9_DME_CONTROL__METADATA_DB_TAKEN__SHIFT 0xd +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR__SHIFT 0x10 +#define DME9_DME_CONTROL__METADATA_DB_DISABLE__SHIFT 0x14 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED__SHIFT 0x18 +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR__SHIFT 0x19 +#define DME9_DME_CONTROL__METADATA_HUBP_REQUESTOR_ID_MASK 0x00000007L +#define DME9_DME_CONTROL__METADATA_ENGINE_EN_MASK 0x00000010L +#define DME9_DME_CONTROL__METADATA_STREAM_TYPE_MASK 0x00000100L +#define DME9_DME_CONTROL__METADATA_DB_PENDING_MASK 0x00001000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_MASK 0x00002000L +#define DME9_DME_CONTROL__METADATA_DB_TAKEN_CLR_MASK 0x00010000L +#define DME9_DME_CONTROL__METADATA_DB_DISABLE_MASK 0x00100000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_MASK 0x01000000L +#define DME9_DME_CONTROL__METADATA_TRANSMISSION_MISSED_CLR_MASK 0x02000000L +//DME9_DME_MEMORY_CONTROL +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE__SHIFT 0x0 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS__SHIFT 0x4 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE__SHIFT 0x8 +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0xc +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_FORCE_MASK 0x00000003L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_DIS_MASK 0x00000010L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_PWR_STATE_MASK 0x00000300L +#define DME9_DME_MEMORY_CONTROL__DME_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000L + + +// addressBlock: dce_dc_hpo_hdmi_link_enc0_dispdec +//HDMI_LINK_ENC_CONTROL +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE__SHIFT 0x0 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET__SHIFT 0x4 +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_ENABLE_MASK 0x00000001L +#define HDMI_LINK_ENC_CONTROL__HDMI_LINK_ENC_SOFT_RESET_MASK 0x00000010L +//HDMI_LINK_ENC_CLK_CTRL +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN__SHIFT 0x0 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK__SHIFT 0x1 +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_EN_MASK 0x00000001L +#define HDMI_LINK_ENC_CLK_CTRL__HDMI_LINK_ENC_CLOCK_ON_HDMICHARCLK_MASK 0x00000002L + + +// addressBlock: dce_dc_hpo_hdmi_frl_enc0_dispdec +//HDMI_FRL_ENC_CONFIG +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE__SHIFT 0x1 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE__SHIFT 0x2 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN__SHIFT 0x10 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN__SHIFT 0x14 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE_COUNT_MASK 0x00000001L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_TRAINING_ENABLE_MASK 0x00000002L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_SCRAMBLER_DISABLE_MASK 0x00000004L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE0_TRAINING_PATTERN_MASK 0x000F0000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE1_TRAINING_PATTERN_MASK 0x00F00000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE2_TRAINING_PATTERN_MASK 0x0F000000L +#define HDMI_FRL_ENC_CONFIG__HDMI_LINK_LANE3_TRAINING_PATTERN_MASK 0xF0000000L +//HDMI_FRL_ENC_CONFIG2 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE__SHIFT 0x0 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD__SHIFT 0xc +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN__SHIFT 0x18 +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE__SHIFT 0x19 +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL__SHIFT 0x1a +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET__SHIFT 0x1c +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS__SHIFT 0x1d +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS__SHIFT 0x1e +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_MASK 0x000001FFL +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_THRESHOLD_MASK 0x001FF000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_CAL_EN_MASK 0x01000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_RC_COMPRESS_DISABLE_MASK 0x02000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_FRL_HDMISTREAMCLK_DB_SEL_MASK 0x0C000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_MAX_JITTER_VALUE_RESET_MASK 0x10000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_JITTER_EXCEED_STATUS_MASK 0x20000000L +#define HDMI_FRL_ENC_CONFIG2__HDMI_LINK_METER_BUFFER_OVERFLOW_STATUS_MASK 0x40000000L +//HDMI_FRL_ENC_METER_BUFFER_STATUS +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL__SHIFT 0x0 +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET__SHIFT 0x1f +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_MAX_METER_BUFFER_LEVEL_MASK 0x0000007FL +#define HDMI_FRL_ENC_METER_BUFFER_STATUS__HDMI_LINK_METER_BUFFER_MAX_LEVEL_RESET_MASK 0x80000000L +//HDMI_FRL_ENC_MEM_CTRL +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS__SHIFT 0x0 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE__SHIFT 0x1 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE__SHIFT 0x4 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x8 +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_DIS_MASK 0x00000001L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_FORCE_MASK 0x00000006L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_PWR_STATE_MASK 0x00000030L +#define HDMI_FRL_ENC_MEM_CTRL__METERBUFFER_MEM_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00000300L + + +// addressBlock: dce_dc_hpo_hpo_top_dispdec +//HPO_TOP_CLOCK_CONTROL +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS__SHIFT 0x0 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS__SHIFT 0x1 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS__SHIFT 0x4 +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS__SHIFT 0x5 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS__SHIFT 0x8 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS__SHIFT 0x9 +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS__SHIFT 0xc +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS__SHIFT 0xd +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS__SHIFT 0x10 +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS__SHIFT 0x11 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS__SHIFT 0x12 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS__SHIFT 0x13 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS__SHIFT 0x14 +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS__SHIFT 0x15 +#define HPO_TOP_CLOCK_CONTROL__HPO_FGCG_REP_DIS__SHIFT 0x17 +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL__SHIFT 0x18 +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_R_GATE_DIS_MASK 0x00000001L +#define HPO_TOP_CLOCK_CONTROL__HPO_DISPCLK_GATE_DIS_MASK 0x00000002L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_R_GATE_DIS_MASK 0x00000010L +#define HPO_TOP_CLOCK_CONTROL__HPO_SOCCLK_GATE_DIS_MASK 0x00000020L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_R_GATE_DIS_MASK 0x00000100L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMISTREAMCLK_G_GATE_DIS_MASK 0x00000200L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_R_GATE_DIS_MASK 0x00001000L +#define HPO_TOP_CLOCK_CONTROL__HPO_HDMICHARCLK_G_GATE_DIS_MASK 0x00002000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_R_GATE_DIS_MASK 0x00010000L +#define HPO_TOP_CLOCK_CONTROL__HPO_DPSTREAMCLK_G_GATE_DIS_MASK 0x00020000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_R_GATE_DIS_MASK 0x00040000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_SE_G_GATE_DIS_MASK 0x00080000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_R_GATE_DIS_MASK 0x00100000L +#define HPO_TOP_CLOCK_CONTROL__HPO_SYMCLK32_LE_G_GATE_DIS_MASK 0x00200000L +#define HPO_TOP_CLOCK_CONTROL__HPO_FGCG_REP_DIS_MASK 0x00800000L +#define HPO_TOP_CLOCK_CONTROL__HPO_TEST_CLK_SEL_MASK 0xFF000000L +//HPO_TOP_HW_CONTROL +#define HPO_TOP_HW_CONTROL__HPO_IO_EN__SHIFT 0x0 +#define HPO_TOP_HW_CONTROL__HPO_IO_EN_MASK 0x00000001L + + +// addressBlock: dce_dc_hpo_dp_stream_mapper_dispdec +//DP_STREAM_MAPPER_CONTROL0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL0__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL1 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL1__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL2 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL2__DP_STREAM_LINK_TARGET_MASK 0x00000007L +//DP_STREAM_MAPPER_CONTROL3 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET__SHIFT 0x0 +#define DP_STREAM_MAPPER_CONTROL3__DP_STREAM_LINK_TARGET_MASK 0x00000007L + + +// addressBlock: dce_dc_hpo_hpo_dcperfmon_dc_perfmon_dispdec +//DC_PERFMON23_PERFCOUNTER_CNTL +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL__SHIFT 0x9 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE__SHIFT 0xc +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL__SHIFT 0xf +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE__SHIFT 0x10 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS__SHIFT 0x16 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN__SHIFT 0x17 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN__SHIFT 0x18 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK__SHIFT 0x19 +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE__SHIFT 0x1a +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_EVENT_SEL_MASK 0x000001FFL +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CVALUE_SEL_MASK 0x00000E00L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INC_MODE_MASK 0x00007000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_HW_CNTL_SEL_MASK 0x00008000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RUNEN_MODE_MASK 0x00010000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTOFF_START_DIS_MASK 0x00400000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_RESTART_EN_MASK 0x00800000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_INT_EN_MASK 0x01000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_OFF_MASK_MASK 0x02000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_ACTIVE_MASK 0x04000000L +#define DC_PERFMON23_PERFCOUNTER_CNTL__PERFCOUNTER_CNTL_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFCOUNTER_CNTL2 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL__SHIFT 0x2 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL__SHIFT 0x3 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL__SHIFT 0x8 +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_COUNTED_VALUE_TYPE_MASK 0x00000003L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP1_SEL_MASK 0x00000004L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_HW_STOP2_SEL_MASK 0x00000008L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTOFF_SEL_MASK 0x00003F00L +#define DC_PERFMON23_PERFCOUNTER_CNTL2__PERFCOUNTER_CNTL2_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFCOUNTER_STATE +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE__SHIFT 0x0 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0__SHIFT 0x2 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE__SHIFT 0x4 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1__SHIFT 0x6 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE__SHIFT 0x8 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE__SHIFT 0xc +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3__SHIFT 0xe +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE__SHIFT 0x10 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4__SHIFT 0x12 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE__SHIFT 0x14 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5__SHIFT 0x16 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE__SHIFT 0x18 +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6__SHIFT 0x1a +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE__SHIFT 0x1c +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7__SHIFT 0x1e +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT0_STATE_MASK 0x00000003L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL0_MASK 0x00000004L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT1_STATE_MASK 0x00000030L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL1_MASK 0x00000040L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT2_STATE_MASK 0x00000300L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2_MASK 0x00000400L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT3_STATE_MASK 0x00003000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL3_MASK 0x00004000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT4_STATE_MASK 0x00030000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL4_MASK 0x00040000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT5_STATE_MASK 0x00300000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL5_MASK 0x00400000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT6_STATE_MASK 0x03000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL6_MASK 0x04000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_CNT7_STATE_MASK 0x30000000L +#define DC_PERFMON23_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL7_MASK 0x40000000L +//DC_PERFMON23_PERFMON_CNTL +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT__SHIFT 0x8 +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR__SHIFT 0x1c +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN__SHIFT 0x1d +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS__SHIFT 0x1e +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK__SHIFT 0x1f +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000003L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_RPT_COUNT_MASK 0x0FFFFF00L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_AND_OR_MASK 0x10000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_EN_MASK 0x20000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_STATUS_MASK 0x40000000L +#define DC_PERFMON23_PERFMON_CNTL__PERFMON_CNTOFF_INT_ACK_MASK 0x80000000L +//DC_PERFMON23_PERFMON_CNTL2 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE__SHIFT 0x1 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL__SHIFT 0x2 +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CNTOFF_INT_TYPE_MASK 0x00000001L +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_CLK_ENABLE_MASK 0x00000002L +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_START_SEL_MASK 0x000003FCL +#define DC_PERFMON23_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL_MASK 0x0003FC00L +//DC_PERFMON23_PERFMON_CVALUE_INT_MISC +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS__SHIFT 0x1 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS__SHIFT 0x2 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS__SHIFT 0x3 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS__SHIFT 0x4 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS__SHIFT 0x5 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS__SHIFT 0x6 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS__SHIFT 0x7 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK__SHIFT 0x8 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK__SHIFT 0x9 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK__SHIFT 0xa +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK__SHIFT 0xb +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK__SHIFT 0xc +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK__SHIFT 0xd +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK__SHIFT 0xe +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK__SHIFT 0xf +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI__SHIFT 0x10 +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_STATUS_MASK 0x00000001L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_STATUS_MASK 0x00000002L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_STATUS_MASK 0x00000004L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_STATUS_MASK 0x00000008L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_STATUS_MASK 0x00000010L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_STATUS_MASK 0x00000020L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_STATUS_MASK 0x00000040L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_STATUS_MASK 0x00000080L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT0_ACK_MASK 0x00000100L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT1_ACK_MASK 0x00000200L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT2_ACK_MASK 0x00000400L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT3_ACK_MASK 0x00000800L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT4_ACK_MASK 0x00001000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT5_ACK_MASK 0x00002000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT6_ACK_MASK 0x00004000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFCOUNTER_INT7_ACK_MASK 0x00008000L +#define DC_PERFMON23_PERFMON_CVALUE_INT_MISC__PERFMON_CVALUE_HI_MASK 0xFFFF0000L +//DC_PERFMON23_PERFMON_CVALUE_LOW +#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_CVALUE_LOW__PERFMON_CVALUE_LOW_MASK 0xFFFFFFFFL +//DC_PERFMON23_PERFMON_HI +#define DC_PERFMON23_PERFMON_HI__PERFMON_HI__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL__SHIFT 0x1d +#define DC_PERFMON23_PERFMON_HI__PERFMON_HI_MASK 0x0000FFFFL +#define DC_PERFMON23_PERFMON_HI__PERFMON_READ_SEL_MASK 0xE0000000L +//DC_PERFMON23_PERFMON_LOW +#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW__SHIFT 0x0 +#define DC_PERFMON23_PERFMON_LOW__PERFMON_LOW_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_opp_abm0_dispdec +//ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_USER_LEVEL +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_TARGET_ABM_LEVEL +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM0_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM0_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM0_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM0_BL1_PWM_ABM_CNTL +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM0_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM0_DC_ABM1_CNTL +#define ABM0_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM0_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM0_DC_ABM1_IPCSC_COEFF_SEL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM0_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM0_DC_ABM1_ACE_PWL_CNTL +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM0_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM0_DC_ABM1_ACE_CNTL_MISC +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM0_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM0_DC_ABM1_HG_MISC_CTRL +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM0_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM0_DC_ABM1_LS_SUM_OF_LUMA +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM0_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM0_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM0_DC_ABM1_LS_PIXEL_COUNT +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM0_DC_ABM1_HG_SAMPLE_RATE +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM0_DC_ABM1_LS_SAMPLE_RATE +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM0_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_HG_RESULT_INDEX +#define ABM0_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM0_DC_ABM1_HG_RESULT_DATA +#define ABM0_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM0_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM0_DC_ABM1_BL_MASTER_LOCK +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM0_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm1_dispdec +//ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_USER_LEVEL +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_TARGET_ABM_LEVEL +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM1_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM1_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM1_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM1_BL1_PWM_ABM_CNTL +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM1_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM1_DC_ABM1_CNTL +#define ABM1_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM1_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM1_DC_ABM1_IPCSC_COEFF_SEL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM1_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM1_DC_ABM1_ACE_PWL_CNTL +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM1_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM1_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM1_DC_ABM1_ACE_CNTL_MISC +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM1_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM1_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM1_DC_ABM1_HG_MISC_CTRL +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM1_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM1_DC_ABM1_LS_SUM_OF_LUMA +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM1_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM1_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM1_DC_ABM1_LS_PIXEL_COUNT +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM1_DC_ABM1_HG_SAMPLE_RATE +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM1_DC_ABM1_LS_SAMPLE_RATE +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM1_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_HG_RESULT_INDEX +#define ABM1_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM1_DC_ABM1_HG_RESULT_DATA +#define ABM1_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM1_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM1_DC_ABM1_BL_MASTER_LOCK +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM1_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm2_dispdec +//ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_USER_LEVEL +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_TARGET_ABM_LEVEL +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM2_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM2_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM2_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM2_BL1_PWM_ABM_CNTL +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM2_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM2_DC_ABM1_CNTL +#define ABM2_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM2_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM2_DC_ABM1_IPCSC_COEFF_SEL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM2_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM2_DC_ABM1_ACE_PWL_CNTL +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM2_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM2_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM2_DC_ABM1_ACE_CNTL_MISC +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM2_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM2_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM2_DC_ABM1_HG_MISC_CTRL +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM2_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM2_DC_ABM1_LS_SUM_OF_LUMA +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM2_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM2_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM2_DC_ABM1_LS_PIXEL_COUNT +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM2_DC_ABM1_HG_SAMPLE_RATE +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM2_DC_ABM1_LS_SAMPLE_RATE +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM2_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_HG_RESULT_INDEX +#define ABM2_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM2_DC_ABM1_HG_RESULT_DATA +#define ABM2_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM2_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM2_DC_ABM1_BL_MASTER_LOCK +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM2_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dc_opp_abm3_dispdec +//ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_USER_LEVEL +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_TARGET_ABM_LEVEL +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_CURRENT_ABM_LEVEL +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x0 +#define ABM3_BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001FFFFL +//ABM3_BL1_PWM_FINAL_DUTY_CYCLE +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x0 +#define ABM3_BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001FFFFL +//ABM3_BL1_PWM_ABM_CNTL +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x1 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x2 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x3 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x10 +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L +#define ABM3_BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xFFFF0000L +//ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM3_DC_ABM1_CNTL +#define ABM3_DC_ABM1_CNTL__ABM1_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS__SHIFT 0x4 +#define ABM3_DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_CNTL__ABM1_PROCESSING_BYPASS_MASK 0x00000010L +//ABM3_DC_ABM1_IPCSC_COEFF_SEL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x0 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0xa +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x14 +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x000001FFL +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x0007FC00L +#define ABM3_DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x1FF00000L +//ABM3_DC_ABM1_ACE_PWL_CNTL +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x1c +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x1d +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x1e +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_OFFSET_SLOPE_INDEX_MASK 0x0000003FL +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L +#define ABM3_DC_ABM1_ACE_PWL_CNTL__ABM1_ACE_LOCK_MASK 0x80000000L +//ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA__SHIFT 0x10 +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_SLOPE_DATA_MASK 0x00000FFFL +#define ABM3_DC_ABM1_ACE_OFFSET_SLOPE_DATA__ABM1_ACE_OFFSET_DATA_MASK 0x0FFF0000L +//ABM3_DC_ABM1_ACE_CNTL_MISC +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x0 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x8 +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L +#define ABM3_DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L +//ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x0 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x1 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x2 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x8 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x9 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0xa +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x10 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x18 +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x1f +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L +#define ABM3_DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L +//ABM3_DC_ABM1_HG_MISC_CTRL +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION__SHIFT 0xe +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x10 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x14 +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_LATCH_POSITION_MASK 0x00004000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L +#define ABM3_DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L +//ABM3_DC_ABM1_LS_SUM_OF_LUMA +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SUM_OF_LUMA_MSB__ABM1_LS_SUM_OF_LUMA_MSB_MASK 0x000003FFL +//ABM3_DC_ABM1_LS_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x00000FFFL +#define ABM3_DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x0FFF0000L +//ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x00000FFFL +#define ABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x0FFF0000L +//ABM3_DC_ABM1_LS_PIXEL_COUNT +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x10 +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x00000FFFL +#define ABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x0FFF0000L +//ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00FFFFFFL +//ABM3_DC_ABM1_HG_SAMPLE_RATE +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM3_DC_ABM1_LS_SAMPLE_RATE +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x0 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x8 +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L +#define ABM3_DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000FF00L +//ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG +#define ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG__ABM1_HG_BIN_33_64_SHIFT_FLAG_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX__ABM1_HG_BIN_33_40_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX__ABM1_HG_BIN_41_48_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX__ABM1_HG_BIN_49_56_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX +#define ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX__ABM1_HG_BIN_57_64_SHIFT_INDEX_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_HG_RESULT_INDEX +#define ABM3_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_INDEX__ABM1_HG_RESULT_INDEX_MASK 0x0000003FL +//ABM3_DC_ABM1_HG_RESULT_DATA +#define ABM3_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA__SHIFT 0x0 +#define ABM3_DC_ABM1_HG_RESULT_DATA__ABM1_HG_RESULT_DATA_MASK 0xFFFFFFFFL +//ABM3_DC_ABM1_BL_MASTER_LOCK +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x1f +#define ABM3_DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L + + +// addressBlock: dce_dpia_dpia_mu0_dpiadec +//DPIA_MU_CLOCK_CTRL +#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL__DPIA_DPIASYMCLK_GATE_DIS__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_G_GATE_DIS__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_R_GATE_DIS__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS__SHIFT 0xb +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS__SHIFT 0xc +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS__SHIFT 0xd +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS__SHIFT 0xe +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL__SHIFT 0x18 +#define DPIA_MU_CLOCK_CTRL__DPIA_REFCLK_GATE_DIS_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL__DPIA_DPIASYMCLK_GATE_DIS_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL__DPIA_CIO_CLKS_GATE_DIS_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_REFCLK_R_GATE_DIS_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_G_GATE_DIS_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_DPIASYMCLK_R_GATE_DIS_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_ML_SSCLK_G_GATE_DIS_MASK 0x00000800L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXIN_SSCLK_G_GATE_DIS_MASK 0x00001000L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_AUXOUT_SSCLK_G_GATE_DIS_MASK 0x00002000L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TMUCLK_G_GATE_DIS_MASK 0x00004000L +#define DPIA_MU_CLOCK_CTRL__DPIA_MU_TEST_CLK_SEL_MASK 0xFF000000L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT0__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT0__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT1__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT1__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT2__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT2__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_CLOCK_CTRL_DPIA_PORT3 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC__SHIFT 0x0 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN__SHIFT 0x1 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN__SHIFT 0x2 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_ML_CLOCK_ON__SHIFT 0x8 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON__SHIFT 0x9 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON__SHIFT 0xa +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_AUX_CLOCK_ON__SHIFT 0x10 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON__SHIFT 0x11 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON__SHIFT 0x12 +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__CLK_SRC_MASK 0x00000001L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_CLK_EN_MASK 0x00000002L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUX_CLK_EN_MASK 0x00000004L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_ML_CLOCK_ON_MASK 0x00000100L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__ML_SSCLK_CLOCK_ON_MASK 0x00000200L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__TMUCLK_CLOCK_ON_MASK 0x00000400L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__DPIASYMCLK_AUX_CLOCK_ON_MASK 0x00010000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXIN_SSCLK_CLOCK_ON_MASK 0x00020000L +#define DPIA_MU_CLOCK_CTRL_DPIA_PORT3__AUXOUT_SSCLK_CLOCK_ON_MASK 0x00040000L +//DPIA_MU_RESET_CTRL_DPIA_PORT3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST__SHIFT 0x0 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST__SHIFT 0x1 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST__SHIFT 0x2 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST__SHIFT 0x3 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE__SHIFT 0x8 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE__SHIFT 0x9 +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_SW_RST_MASK 0x00000001L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_SW_RST_MASK 0x00000002L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__AUX_TPI_SW_RST_MASK 0x00000004L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__ML_TPI_SW_RST_MASK 0x00000008L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CAPREG_RESET_DONE_MASK 0x00000100L +#define DPIA_MU_RESET_CTRL_DPIA_PORT3__CORE_RESET_DONE_MASK 0x00000200L +//DPIA_MU_TPI_STATUS_DPIA_PORT0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT0__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_STATUS_DPIA_PORT1 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT1__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_STATUS_DPIA_PORT2 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT2__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_STATUS_DPIA_PORT3 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT__SHIFT 0x8 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT__SHIFT 0x10 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED__SHIFT 0x18 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED__SHIFT 0x19 +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED__SHIFT 0x1a +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_CREDIT_COUNT_MASK 0x0000007FL +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_CREDIT_COUNT_MASK 0x00000F00L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_CREDIT_COUNT_MASK 0x000F0000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__MAIN_LINK_EXTRA_CREDIT_RECEIVED_MASK 0x01000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXOUT_EXTRA_CREDIT_RECEIVED_MASK 0x02000000L +#define DPIA_MU_TPI_STATUS_DPIA_PORT3__AUXIN_EXTRA_PAYLOAD_RECEIVED_MASK 0x04000000L +//DPIA_MU_TPI_MAX_CREDIT_COUNT +#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT__SHIFT 0x0 +#define DPIA_MU_TPI_MAX_CREDIT_COUNT__DPIA_TPI_MAX_CREDIT_COUNT_MASK 0x0000003FL +//DPIA_MU_INTERRUPT_STATUS +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS__SHIFT 0x0 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS__SHIFT 0x3 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS__SHIFT 0x6 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS__SHIFT 0x9 +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT4_INT_STATUS__SHIFT 0xc +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT5_INT_STATUS__SHIFT 0xf +#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS__SHIFT 0x1f +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT0_INT_STATUS_MASK 0x00000007L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT1_INT_STATUS_MASK 0x00000038L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT2_INT_STATUS_MASK 0x000001C0L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT3_INT_STATUS_MASK 0x00000E00L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT4_INT_STATUS_MASK 0x00007000L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_PORT5_INT_STATUS_MASK 0x00038000L +#define DPIA_MU_INTERRUPT_STATUS__DPIA_MU_LOCAL_INT_STATUS_MASK 0x80000000L +//DPIA_MU_INTERRUPT_CTRL +#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN__SHIFT 0x0 +#define DPIA_MU_INTERRUPT_CTRL__DPIA_PORT_INT_MASK__SHIFT 0x8 +#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK__SHIFT 0x18 +#define DPIA_MU_INTERRUPT_CTRL__DPIA_DCN_INT_EN_MASK 0x00000001L +#define DPIA_MU_INTERRUPT_CTRL__DPIA_PORT_INT_MASK_MASK 0x0000FF00L +#define DPIA_MU_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_MASK_MASK 0x01000000L +//DPIA_MU_LOCAL_INTERRUPT_CTRL +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS__SHIFT 0x0 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR__SHIFT 0x2 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP__SHIFT 0x14 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS__SHIFT 0x18 +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_INT_STATUS_MASK 0x00000001L +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_ADDR_MASK 0x000FFFFCL +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__RBBMIF_TIMEOUT_OP_MASK 0x00100000L +#define DPIA_MU_LOCAL_INTERRUPT_CTRL__DPIA_RST_DONE_INT_STATUS_MASK 0x01000000L +//DPIA_MU_LOCAL_INTERRUPT_ACK +#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK__SHIFT 0x0 +#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK__SHIFT 0x1 +#define DPIA_MU_LOCAL_INTERRUPT_ACK__RBBMIF_TIMEOUT_INT_ACK_MASK 0x00000001L +#define DPIA_MU_LOCAL_INTERRUPT_ACK__DPIA_RST_DONE_INT_ACK_MASK 0x00000002L +//DPIA_MU_RBBMIF_TIMEOUT_CTRL +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY__SHIFT 0x0 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD__SHIFT 0x14 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_DELAY_MASK 0x000FFFFFL +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL__RBBMIF_TIMEOUT_HOLD_MASK 0xFFF00000L +//DPIA_MU_RBBMIF_TIMEOUT_CTRL2 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS__SHIFT 0x0 +#define DPIA_MU_RBBMIF_TIMEOUT_CTRL2__RBBMIF_TIMEOUT_DIS_MASK 0x00000001L +//DPIA_MU_RBBMIF_STATUS +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG__SHIFT 0x0 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE__SHIFT 0x1 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR__SHIFT 0x5 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK__SHIFT 0x18 +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR__SHIFT 0x1f +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_FLAG_MASK 0x00000001L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_TYPE_MASK 0x00000006L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_ADDR_MASK 0x007FFFE0L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_TIMEOUT_STATUS_READBACK_MASK 0x01000000L +#define DPIA_MU_RBBMIF_STATUS__RBBMIF_INVALID_ACCESS_STATUS_CLEAR_MASK 0x80000000L +//DPIA_MU_MICROSECOND_REF_CTRL +#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV__SHIFT 0x0 +#define DPIA_MU_MICROSECOND_REF_CTRL__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007FL +//DPIA_MU_PORT_ADP_STATUS +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS__SHIFT 0x0 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS__SHIFT 0x1 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS__SHIFT 0x2 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS__SHIFT 0x3 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT4_HIDDEN_STATUS__SHIFT 0x4 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT5_HIDDEN_STATUS__SHIFT 0x5 +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT0_HIDDEN_STATUS_MASK 0x00000001L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT1_HIDDEN_STATUS_MASK 0x00000002L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT2_HIDDEN_STATUS_MASK 0x00000004L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT3_HIDDEN_STATUS_MASK 0x00000008L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT4_HIDDEN_STATUS_MASK 0x00000010L +#define DPIA_MU_PORT_ADP_STATUS__DPIA_PORT5_HIDDEN_STATUS_MASK 0x00000020L +//DPIA_GLUE_CTRL +#define DPIA_GLUE_CTRL__DPIA_IO_EN__SHIFT 0x0 +#define DPIA_GLUE_CTRL__DPIA_GLUE_ML_SSCLK_DBG_BUS_SEL__SHIFT 0x4 +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXOUT_SSCLK_DBG_BUS_SEL__SHIFT 0x8 +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXIN_SSCLK_DBG_BUS_SEL__SHIFT 0xa +#define DPIA_GLUE_CTRL__DPIA_IO_EN_MASK 0x00000001L +#define DPIA_GLUE_CTRL__DPIA_GLUE_ML_SSCLK_DBG_BUS_SEL_MASK 0x00000030L +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXOUT_SSCLK_DBG_BUS_SEL_MASK 0x00000300L +#define DPIA_GLUE_CTRL__DPIA_GLUE_AUXIN_SSCLK_DBG_BUS_SEL_MASK 0x00000C00L +//DPIA_PERF_COUNT_CONTROL0 +#define DPIA_PERF_COUNT_CONTROL0__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL0__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL0__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL0__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL0__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL0__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL0__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL0__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL0__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL1 +#define DPIA_PERF_COUNT_CONTROL1__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL1__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL1__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL1__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL1__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL1__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL1__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL1__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL1__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL2 +#define DPIA_PERF_COUNT_CONTROL2__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL2__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL2__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL2__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL2__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL2__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL2__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL2__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL2__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL3 +#define DPIA_PERF_COUNT_CONTROL3__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL3__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL3__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL3__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL3__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL3__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL3__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL3__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL3__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL4 +#define DPIA_PERF_COUNT_CONTROL4__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL4__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL4__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL4__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL4__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL4__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL4__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL4__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL4__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_CONTROL5 +#define DPIA_PERF_COUNT_CONTROL5__ENABLE__SHIFT 0x0 +#define DPIA_PERF_COUNT_CONTROL5__MODE__SHIFT 0x1 +#define DPIA_PERF_COUNT_CONTROL5__STATUS__SHIFT 0x4 +#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT__SHIFT 0x5 +#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT__SHIFT 0x8 +#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT__SHIFT 0xc +#define DPIA_PERF_COUNT_CONTROL5__ENABLE_MASK 0x00000001L +#define DPIA_PERF_COUNT_CONTROL5__MODE_MASK 0x0000000EL +#define DPIA_PERF_COUNT_CONTROL5__STATUS_MASK 0x00000010L +#define DPIA_PERF_COUNT_CONTROL5__PORT_SELECT_MASK 0x000000E0L +#define DPIA_PERF_COUNT_CONTROL5__STAT_SELECT_MASK 0x00000300L +#define DPIA_PERF_COUNT_CONTROL5__COUNT_LIMIT_MASK 0xFFFFF000L +//DPIA_PERF_COUNT_INDEX +#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT__SHIFT 0x0 +#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT__SHIFT 0x4 +#define DPIA_PERF_COUNT_INDEX__COUNTER_SELECT_MASK 0x00000007L +#define DPIA_PERF_COUNT_INDEX__MEAS_SELECT_MASK 0x00000070L +//DPIA_PERF_COUNT_DATA_LO +#define DPIA_PERF_COUNT_DATA_LO__VALUE__SHIFT 0x0 +#define DPIA_PERF_COUNT_DATA_LO__VALUE_MASK 0xFFFFFFFFL +//DPIA_MU_SPARE +#define DPIA_MU_SPARE__DPIA_MU_SPARE__SHIFT 0x0 +#define DPIA_MU_SPARE__DPIA_MU_SPARE_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azcontroller_azdec +//GLOBAL_CAPABILITIES +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0 +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1 +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3 +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8 +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc +#define GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L +#define GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L +#define GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L +#define GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L +#define GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L +//MINOR_VERSION +#define MINOR_VERSION__MINOR_VERSION__SHIFT 0x0 +#define MINOR_VERSION__MINOR_VERSION_MASK 0xFFL +//MAJOR_VERSION +#define MAJOR_VERSION__MAJOR_VERSION__SHIFT 0x0 +#define MAJOR_VERSION__MAJOR_VERSION_MASK 0xFFL +//OUTPUT_PAYLOAD_CAPABILITY +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//INPUT_PAYLOAD_CAPABILITY +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY__SHIFT 0x0 +#define INPUT_PAYLOAD_CAPABILITY__INPUT_PAYLOAD_CAPABILITY_MASK 0xFFFFL +//GLOBAL_CONTROL +#define GLOBAL_CONTROL__CONTROLLER_RESET__SHIFT 0x0 +#define GLOBAL_CONTROL__FLUSH_CONTROL__SHIFT 0x1 +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE__SHIFT 0x8 +#define GLOBAL_CONTROL__CONTROLLER_RESET_MASK 0x00000001L +#define GLOBAL_CONTROL__FLUSH_CONTROL_MASK 0x00000002L +#define GLOBAL_CONTROL__ACCEPT_UNSOLICITED_RESPONSE_ENABLE_MASK 0x00000100L +//WAKE_ENABLE +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG__SHIFT 0x0 +#define WAKE_ENABLE__SDIN_WAKE_ENABLE_FLAG_MASK 0x0001L +//STATE_CHANGE_STATUS +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS__SHIFT 0x0 +#define STATE_CHANGE_STATUS__STATE_CHANGE_STATUS_MASK 0x0001L +//GLOBAL_STATUS +#define GLOBAL_STATUS__FLUSH_STATUS__SHIFT 0x1 +#define GLOBAL_STATUS__FLUSH_STATUS_MASK 0x00000002L +//OUTPUT_STREAM_PAYLOAD_CAPABILITY +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x0 +#define OUTPUT_STREAM_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xFFFFL +//INPUT_STREAM_PAYLOAD_CAPABILITY +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY__SHIFT 0x0 +#define INPUT_STREAM_PAYLOAD_CAPABILITY__INSTRMPAY_MASK 0xFFFFL +//INTERRUPT_CONTROL +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE__SHIFT 0x0 +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE__SHIFT 0x1 +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE__SHIFT 0x2 +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE__SHIFT 0x3 +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE__SHIFT 0x4 +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE__SHIFT 0x5 +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE__SHIFT 0x6 +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE__SHIFT 0x7 +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE__SHIFT 0x8 +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE__SHIFT 0x9 +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE__SHIFT 0xb +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE__SHIFT 0xc +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE__SHIFT 0xd +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE__SHIFT 0xe +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE__SHIFT 0xf +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE__SHIFT 0x1e +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE__SHIFT 0x1f +#define INTERRUPT_CONTROL__STREAM_0_INTERRUPT_ENABLE_MASK 0x00000001L +#define INTERRUPT_CONTROL__STREAM_1_INTERRUPT_ENABLE_MASK 0x00000002L +#define INTERRUPT_CONTROL__STREAM_2_INTERRUPT_ENABLE_MASK 0x00000004L +#define INTERRUPT_CONTROL__STREAM_3_INTERRUPT_ENABLE_MASK 0x00000008L +#define INTERRUPT_CONTROL__STREAM_4_INTERRUPT_ENABLE_MASK 0x00000010L +#define INTERRUPT_CONTROL__STREAM_5_INTERRUPT_ENABLE_MASK 0x00000020L +#define INTERRUPT_CONTROL__STREAM_6_INTERRUPT_ENABLE_MASK 0x00000040L +#define INTERRUPT_CONTROL__STREAM_7_INTERRUPT_ENABLE_MASK 0x00000080L +#define INTERRUPT_CONTROL__STREAM_8_INTERRUPT_ENABLE_MASK 0x00000100L +#define INTERRUPT_CONTROL__STREAM_9_INTERRUPT_ENABLE_MASK 0x00000200L +#define INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE_MASK 0x00000400L +#define INTERRUPT_CONTROL__STREAM_11_INTERRUPT_ENABLE_MASK 0x00000800L +#define INTERRUPT_CONTROL__STREAM_12_INTERRUPT_ENABLE_MASK 0x00001000L +#define INTERRUPT_CONTROL__STREAM_13_INTERRUPT_ENABLE_MASK 0x00002000L +#define INTERRUPT_CONTROL__STREAM_14_INTERRUPT_ENABLE_MASK 0x00004000L +#define INTERRUPT_CONTROL__STREAM_15_INTERRUPT_ENABLE_MASK 0x00008000L +#define INTERRUPT_CONTROL__CONTROLLER_INTERRUPT_ENABLE_MASK 0x40000000L +#define INTERRUPT_CONTROL__GLOBAL_INTERRUPT_ENABLE_MASK 0x80000000L +//INTERRUPT_STATUS +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS__SHIFT 0x0 +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS__SHIFT 0x1 +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS__SHIFT 0x2 +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS__SHIFT 0x3 +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS__SHIFT 0x4 +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS__SHIFT 0x5 +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS__SHIFT 0x6 +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS__SHIFT 0x7 +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS__SHIFT 0x8 +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS__SHIFT 0x9 +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS__SHIFT 0xb +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS__SHIFT 0xc +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS__SHIFT 0xd +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS__SHIFT 0xe +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS__SHIFT 0xf +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS__SHIFT 0x1e +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS__SHIFT 0x1f +#define INTERRUPT_STATUS__STREAM_0_INTERRUPT_STATUS_MASK 0x00000001L +#define INTERRUPT_STATUS__STREAM_1_INTERRUPT_STATUS_MASK 0x00000002L +#define INTERRUPT_STATUS__STREAM_2_INTERRUPT_STATUS_MASK 0x00000004L +#define INTERRUPT_STATUS__STREAM_3_INTERRUPT_STATUS_MASK 0x00000008L +#define INTERRUPT_STATUS__STREAM_4_INTERRUPT_STATUS_MASK 0x00000010L +#define INTERRUPT_STATUS__STREAM_5_INTERRUPT_STATUS_MASK 0x00000020L +#define INTERRUPT_STATUS__STREAM_6_INTERRUPT_STATUS_MASK 0x00000040L +#define INTERRUPT_STATUS__STREAM_7_INTERRUPT_STATUS_MASK 0x00000080L +#define INTERRUPT_STATUS__STREAM_8_INTERRUPT_STATUS_MASK 0x00000100L +#define INTERRUPT_STATUS__STREAM_9_INTERRUPT_STATUS_MASK 0x00000200L +#define INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS_MASK 0x00000400L +#define INTERRUPT_STATUS__STREAM_11_INTERRUPT_STATUS_MASK 0x00000800L +#define INTERRUPT_STATUS__STREAM_12_INTERRUPT_STATUS_MASK 0x00001000L +#define INTERRUPT_STATUS__STREAM_13_INTERRUPT_STATUS_MASK 0x00002000L +#define INTERRUPT_STATUS__STREAM_14_INTERRUPT_STATUS_MASK 0x00004000L +#define INTERRUPT_STATUS__STREAM_15_INTERRUPT_STATUS_MASK 0x00008000L +#define INTERRUPT_STATUS__CONTROLLER_INTERRUPT_STATUS_MASK 0x40000000L +#define INTERRUPT_STATUS__GLOBAL_INTERRUPT_STATUS_MASK 0x80000000L +//WALL_CLOCK_COUNTER +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER__SHIFT 0x0 +#define WALL_CLOCK_COUNTER__WALL_CLOCK_COUNTER_MASK 0xFFFFFFFFL +//STREAM_SYNCHRONIZATION +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION__SHIFT 0x0 +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION__SHIFT 0x1 +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION__SHIFT 0x2 +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION__SHIFT 0x3 +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION__SHIFT 0x4 +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION__SHIFT 0x5 +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION__SHIFT 0x6 +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION__SHIFT 0x7 +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION__SHIFT 0x8 +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION__SHIFT 0x9 +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION__SHIFT 0xb +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION__SHIFT 0xc +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION__SHIFT 0xd +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION__SHIFT 0xe +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION__SHIFT 0xf +#define STREAM_SYNCHRONIZATION__STREAM_0_SYNCHRONIZATION_MASK 0x00000001L +#define STREAM_SYNCHRONIZATION__STREAM_1_SYNCHRONIZATION_MASK 0x00000002L +#define STREAM_SYNCHRONIZATION__STREAM_2_SYNCHRONIZATION_MASK 0x00000004L +#define STREAM_SYNCHRONIZATION__STREAM_3_SYNCHRONIZATION_MASK 0x00000008L +#define STREAM_SYNCHRONIZATION__STREAM_4_SYNCHRONIZATION_MASK 0x00000010L +#define STREAM_SYNCHRONIZATION__STREAM_5_SYNCHRONIZATION_MASK 0x00000020L +#define STREAM_SYNCHRONIZATION__STREAM_6_SYNCHRONIZATION_MASK 0x00000040L +#define STREAM_SYNCHRONIZATION__STREAM_7_SYNCHRONIZATION_MASK 0x00000080L +#define STREAM_SYNCHRONIZATION__STREAM_8_SYNCHRONIZATION_MASK 0x00000100L +#define STREAM_SYNCHRONIZATION__STREAM_9_SYNCHRONIZATION_MASK 0x00000200L +#define STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION_MASK 0x00000400L +#define STREAM_SYNCHRONIZATION__STREAM_11_SYNCHRONIZATION_MASK 0x00000800L +#define STREAM_SYNCHRONIZATION__STREAM_12_SYNCHRONIZATION_MASK 0x00001000L +#define STREAM_SYNCHRONIZATION__STREAM_13_SYNCHRONIZATION_MASK 0x00002000L +#define STREAM_SYNCHRONIZATION__STREAM_14_SYNCHRONIZATION_MASK 0x00004000L +#define STREAM_SYNCHRONIZATION__STREAM_15_SYNCHRONIZATION_MASK 0x00008000L +//CORB_LOWER_BASE_ADDRESS +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define CORB_LOWER_BASE_ADDRESS__CORB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//CORB_UPPER_BASE_ADDRESS +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define CORB_UPPER_BASE_ADDRESS__CORB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_CORB_WRITE_POINTER +#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL +//AZCONTROLLER1_CORB_READ_POINTER +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL +#define AZCONTROLLER1_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER1_CORB_CONTROL +#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0 +#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1 +#define AZCONTROLLER1_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L +#define AZCONTROLLER1_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L +//AZCONTROLLER1_CORB_STATUS +#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION__SHIFT 0x0 +#define AZCONTROLLER1_CORB_STATUS__CORB_MEMORY_ERROR_INDICATION_MASK 0x01L +//AZCONTROLLER1_CORB_SIZE +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE__SHIFT 0x0 +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_MASK 0x0003L +#define AZCONTROLLER1_CORB_SIZE__CORB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZCONTROLLER1_RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS +#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_RIRB_WRITE_POINTER +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT 0xf +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK 0x00FFL +#define AZCONTROLLER1_RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK 0x8000L +//AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT +#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT 0x0 +#define AZCONTROLLER1_RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK 0x00FFL +//AZCONTROLLER1_RIRB_CONTROL +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1 +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT 0x2 +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK 0x01L +#define AZCONTROLLER1_RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x02L +#define AZCONTROLLER1_RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK 0x04L +//AZCONTROLLER1_RIRB_STATUS +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT 0x2 +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_INTERRUPT_MASK 0x01L +#define AZCONTROLLER1_RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK 0x04L +//AZCONTROLLER1_RIRB_SIZE +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE__SHIFT 0x0 +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4 +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_MASK 0x0003L +#define AZCONTROLLER1_RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0x00F0L +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS__SHIFT 0x1c +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD_MASK 0x0FFFFFFFL +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE__IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS_MASK 0xF0000000L +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0000FFFFL +//AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE +#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_RESPONSE_INPUT_INTERFACE__IMMEDIATE_RESPONSE_READ_MASK 0xFFFFFFFFL +//AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY__SHIFT 0x0 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID__SHIFT 0x1 +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_COMMAND_BUSY_MASK 0x00000001L +#define AZCONTROLLER1_IMMEDIATE_COMMAND_STATUS__IMMEDIATE_RESULT_VALID_MASK 0x00000002L +//AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE__SHIFT 0x0 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT 0x1 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_BUFFER_ENABLE_MASK 0x00000001L +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS_MASK 0x0000007EL +#define AZCONTROLLER1_DMA_POSITION_LOWER_BASE_ADDRESS__DMA_POSITION_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS +#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZCONTROLLER1_DMA_POSITION_UPPER_BASE_ADDRESS__DMA_POSITION_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS +#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS__SHIFT 0x0 +#define AZCONTROLLER1_WALL_CLOCK_COUNTER_ALIAS__WALL_CLOCK_COUNTER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azendpoint_azdec +//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azinputendpoint_azdec +//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZINPUTENDPOINT1_AZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azroot_azdec +//AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA__IMMEDIATE_COMMAND_WRITE_MASK 0xFFFFFFFFL +//AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE__SHIFT 0x0 +#define AZROOT1_AZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX__IMMEDIATE_COMMAND_WRITE_MASK 0x0001FFFFL + + +// addressBlock: dce_dc_hda_azstream0_azdec +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream1_azdec +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream2_azdec +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream3_azdec +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream4_azdec +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream5_azdec +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream6_azdec +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + + +// addressBlock: dce_dc_hda_azstream7_azdec +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN__SHIFT 0x1 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE__SHIFT 0x2 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE__SHIFT 0x3 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE__SHIFT 0x4 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL__SHIFT 0x10 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY__SHIFT 0x12 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER__SHIFT 0x14 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS__SHIFT 0x1a +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR__SHIFT 0x1b +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR__SHIFT 0x1c +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY__SHIFT 0x1d +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RESET_MASK 0x00000001L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_RUN_MASK 0x00000002L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__INTERRUPT_ON_COMPLETION_ENABLE_MASK 0x00000004L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_INTERRUPT_ENABLE_MASK 0x00000008L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_INTERRUPT_ENABLE_MASK 0x00000010L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STRIPE_CONTROL_MASK 0x00030000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__TRAFFIC_PRIORITY_MASK 0x00040000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__STREAM_NUMBER_MASK 0x00F00000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__BUFFER_COMPLETION_INTERRUPT_STATUS_MASK 0x04000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_ERROR_MASK 0x08000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__DESCRIPTOR_ERROR_MASK 0x10000000L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS__FIFO_READY_MASK 0x20000000L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER__LINK_POSITION_IN_BUFFER_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH__CYCLIC_BUFFER_LENGTH_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX__LAST_VALID_INDEX_MASK 0x000000FFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE__FIFO_SIZE_MASK 0xFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE__SHIFT 0x4 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x8 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0xb +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE__SHIFT 0xe +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__NUMBER_OF_CHANNELS_MASK 0x000FL +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__BITS_PER_SAMPLE_MASK 0x0070L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x0700L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x3800L +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT__SAMPLE_BASE_RATE_MASK 0x4000L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS__SHIFT 0x7 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS_MASK 0x0000007FL +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_MASK 0xFFFFFF80L +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS__BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS_MASK 0xFFFFFFFFL +//AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS__SHIFT 0x0 +#define AZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS__LINK_POSITION_IN_BUFFER_ALIAS_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h new file mode 100644 index 0000000000000..5e99515fbf64a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_offset.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dpcs_4_0_0_OFFSET_HEADER +#define _dpcs_4_0_0_OFFSET_HEADER + +// addressBlock: dpcssys_dcio_dcio_dispdec +// base address: 0x0 +#define regDC_GENERICA 0x2868 +#define regDC_GENERICA_BASE_IDX 2 +#define regDC_GENERICB 0x2869 +#define regDC_GENERICB_BASE_IDX 2 +#define regDCIO_CLOCK_CNTL 0x286a +#define regDCIO_CLOCK_CNTL_BASE_IDX 2 +#define regDC_REF_CLK_CNTL 0x286b +#define regDC_REF_CLK_CNTL_BASE_IDX 2 +#define regUNIPHYA_LINK_CNTL 0x286d +#define regUNIPHYA_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYA_CHANNEL_XBAR_CNTL 0x286e +#define regUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYB_LINK_CNTL 0x286f +#define regUNIPHYB_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 +#define regUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYC_LINK_CNTL 0x2871 +#define regUNIPHYC_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 +#define regUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYD_LINK_CNTL 0x2873 +#define regUNIPHYD_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 +#define regUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regUNIPHYE_LINK_CNTL 0x2875 +#define regUNIPHYE_LINK_CNTL_BASE_IDX 2 +#define regUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 +#define regUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 +#define regDCIO_WRCMD_DELAY 0x287e +#define regDCIO_WRCMD_DELAY_BASE_IDX 2 +#define regDC_PINSTRAPS 0x2880 +#define regDC_PINSTRAPS_BASE_IDX 2 +#define regDCIO_SPARE 0x2882 +#define regDCIO_SPARE_BASE_IDX 2 +#define regINTERCEPT_STATE 0x2884 +#define regINTERCEPT_STATE_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_PAT 0x2886 +#define regDCIO_PATTERN_GEN_PAT_BASE_IDX 2 +#define regDCIO_PATTERN_GEN_EN 0x2887 +#define regDCIO_PATTERN_GEN_EN_BASE_IDX 2 +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL 0x288b +#define regDCIO_BL_PWM_FRAME_START_DISP_SEL_BASE_IDX 2 +#define regDCIO_GSL_GENLK_PAD_CNTL 0x288c +#define regDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d +#define regDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 +#define regDPCS_DCIO_TEST_CLK_SRC 0x2890 +#define regDPCS_DCIO_TEST_CLK_SRC_BASE_IDX 2 +#define regDCIO_DEBUG 0x2897 +#define regDCIO_DEBUG_BASE_IDX 2 +#define regDCIO_TEST_DEBUG_INDEX 0x2899 +#define regDCIO_TEST_DEBUG_INDEX_BASE_IDX 2 +#define regDCIO_TEST_DEBUG_DATA 0x289a +#define regDCIO_TEST_DEBUG_DATA_BASE_IDX 2 +#define regDBG_OUT_CNTL 0x289c +#define regDBG_OUT_CNTL_BASE_IDX 2 +#define regDCIO_DEBUG_CONFIG 0x289d +#define regDCIO_DEBUG_CONFIG_BASE_IDX 2 +#define regDCIO_SOFT_RESET 0x289e +#define regDCIO_SOFT_RESET_BASE_IDX 2 + + +// addressBlock: dpcssys_dcio_dcio_chip_dispdec +// base address: 0x0 +#define regDC_GPIO_DDC1_MASK 0x28d0 +#define regDC_GPIO_DDC1_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC1_A 0x28d1 +#define regDC_GPIO_DDC1_A_BASE_IDX 2 +#define regDC_GPIO_DDC1_EN 0x28d2 +#define regDC_GPIO_DDC1_EN_BASE_IDX 2 +#define regDC_GPIO_DDC1_Y 0x28d3 +#define regDC_GPIO_DDC1_Y_BASE_IDX 2 +#define regDC_GPIO_DDC2_MASK 0x28d4 +#define regDC_GPIO_DDC2_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC2_A 0x28d5 +#define regDC_GPIO_DDC2_A_BASE_IDX 2 +#define regDC_GPIO_DDC2_EN 0x28d6 +#define regDC_GPIO_DDC2_EN_BASE_IDX 2 +#define regDC_GPIO_DDC2_Y 0x28d7 +#define regDC_GPIO_DDC2_Y_BASE_IDX 2 +#define regDC_GPIO_DDC3_MASK 0x28d8 +#define regDC_GPIO_DDC3_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC3_A 0x28d9 +#define regDC_GPIO_DDC3_A_BASE_IDX 2 +#define regDC_GPIO_DDC3_EN 0x28da +#define regDC_GPIO_DDC3_EN_BASE_IDX 2 +#define regDC_GPIO_DDC3_Y 0x28db +#define regDC_GPIO_DDC3_Y_BASE_IDX 2 +#define regDC_GPIO_DDC4_MASK 0x28dc +#define regDC_GPIO_DDC4_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC4_A 0x28dd +#define regDC_GPIO_DDC4_A_BASE_IDX 2 +#define regDC_GPIO_DDC4_EN 0x28de +#define regDC_GPIO_DDC4_EN_BASE_IDX 2 +#define regDC_GPIO_DDC4_Y 0x28df +#define regDC_GPIO_DDC4_Y_BASE_IDX 2 +#define regDC_GPIO_DDC5_MASK 0x28e0 +#define regDC_GPIO_DDC5_MASK_BASE_IDX 2 +#define regDC_GPIO_DDC5_A 0x28e1 +#define regDC_GPIO_DDC5_A_BASE_IDX 2 +#define regDC_GPIO_DDC5_EN 0x28e2 +#define regDC_GPIO_DDC5_EN_BASE_IDX 2 +#define regDC_GPIO_DDC5_Y 0x28e3 +#define regDC_GPIO_DDC5_Y_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_MASK 0x28e8 +#define regDC_GPIO_DDCVGA_MASK_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_A 0x28e9 +#define regDC_GPIO_DDCVGA_A_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_EN 0x28ea +#define regDC_GPIO_DDCVGA_EN_BASE_IDX 2 +#define regDC_GPIO_DDCVGA_Y 0x28eb +#define regDC_GPIO_DDCVGA_Y_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ0_EN 0x28fa +#define regDC_GPIO_PWRSEQ0_EN_BASE_IDX 2 +#define regDC_GPIO_PAD_STRENGTH_1 0x28fc +#define regDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 +#define regPHY_AUX_CNTL 0x28ff +#define regPHY_AUX_CNTL_BASE_IDX 2 +#define regDC_GPIO_PWRSEQ1_EN 0x2902 +#define regDC_GPIO_PWRSEQ1_EN_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_0 0x2916 +#define regDC_GPIO_AUX_CTRL_0_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_1 0x2917 +#define regDC_GPIO_AUX_CTRL_1_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_3 0x291b +#define regDC_GPIO_AUX_CTRL_3_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_4 0x291c +#define regDC_GPIO_AUX_CTRL_4_BASE_IDX 2 +#define regDC_GPIO_AUX_CTRL_5 0x291d +#define regDC_GPIO_AUX_CTRL_5_BASE_IDX 2 +#define regAUXI2C_PAD_ALL_PWR_OK 0x291e +#define regAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h new file mode 100644 index 0000000000000..e124cc13bfa64 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_0_0_sh_mask.h @@ -0,0 +1,688 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright 2026 Advanced Micro Devices, Inc. */ + +#ifndef _dpcs_4_0_0_SH_MASK_HEADER +#define _dpcs_4_0_0_SH_MASK_HEADER + +// addressBlock: dpcssys_dcio_dcio_dispdec +//DC_GENERICA +#define DC_GENERICA__GENERICA_SEL__SHIFT 0x7 +#define DC_GENERICA__GENERICA_SEL_MASK 0x00000F80L +//DC_GENERICB +#define DC_GENERICB__GENERICB_SEL__SHIFT 0x8 +#define DC_GENERICB__GENERICB_SEL_MASK 0x00000F00L +//DCIO_CLOCK_CNTL +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT 0x0 +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT 0x5 +#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK 0x0000001FL +#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK 0x00000020L +//DC_REF_CLK_CNTL +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x8 +#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L +//UNIPHYA_LINK_CNTL +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYA_CHANNEL_XBAR_CNTL +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYA_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYB_LINK_CNTL +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYB_CHANNEL_XBAR_CNTL +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYB_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYC_LINK_CNTL +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYC_CHANNEL_XBAR_CNTL +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYC_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYD_LINK_CNTL +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYD_CHANNEL_XBAR_CNTL +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYD_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//UNIPHYE_LINK_CNTL +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0xc +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0xd +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0xe +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0xf +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L +#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L +//UNIPHYE_CHANNEL_XBAR_CNTL +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x0 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x8 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x10 +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x18 +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN__SHIFT 0x1c +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN__SHIFT 0x1d +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN__SHIFT 0x1e +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN__SHIFT 0x1f +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL0_EN_MASK 0x10000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL1_EN_MASK 0x20000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL2_EN_MASK 0x40000000L +#define UNIPHYE_CHANNEL_XBAR_CNTL__DOUT_PHY_CHANNEL3_EN_MASK 0x80000000L +//DCIO_WRCMD_DELAY +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT 0x18 +#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK 0xFF000000L +//DC_PINSTRAPS +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0xd +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0xe +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x10 +#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L +#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000C000L +#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L +//DCIO_SPARE +#define DCIO_SPARE__DCIO_SPARE__SHIFT 0x0 +#define DCIO_SPARE__DCIO_SPARE_MASK 0xFFFFFFFFL +//INTERCEPT_STATE +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT 0x0 +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT 0x1 +#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE__SHIFT 0x2 +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT 0x4 +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT 0x5 +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT 0x6 +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT 0x7 +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT 0x8 +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT 0x9 +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT 0xa +#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE__SHIFT 0x10 +#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE__SHIFT 0x11 +#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE__SHIFT 0x12 +#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE__SHIFT 0x13 +#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE__SHIFT 0x14 +#define INTERCEPT_STATE__DPCS5_DC_INTERCEPTB_STATE__SHIFT 0x15 +#define INTERCEPT_STATE__DPCS6_DC_INTERCEPTB_STATE__SHIFT 0x16 +#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK 0x00000001L +#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK 0x00000002L +#define INTERCEPT_STATE__DLPC_INTERCEPTB_STATE_MASK 0x00000004L +#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK 0x00000010L +#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK 0x00000020L +#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK 0x00000040L +#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK 0x00000080L +#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK 0x00000100L +#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK 0x00000200L +#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK 0x00000400L +#define INTERCEPT_STATE__DPCS0_DC_INTERCEPTB_STATE_MASK 0x00010000L +#define INTERCEPT_STATE__DPCS1_DC_INTERCEPTB_STATE_MASK 0x00020000L +#define INTERCEPT_STATE__DPCS2_DC_INTERCEPTB_STATE_MASK 0x00040000L +#define INTERCEPT_STATE__DPCS3_DC_INTERCEPTB_STATE_MASK 0x00080000L +#define INTERCEPT_STATE__DPCS4_DC_INTERCEPTB_STATE_MASK 0x00100000L +#define INTERCEPT_STATE__DPCS5_DC_INTERCEPTB_STATE_MASK 0x00200000L +#define INTERCEPT_STATE__DPCS6_DC_INTERCEPTB_STATE_MASK 0x00400000L +//DCIO_PATTERN_GEN_PAT +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT__SHIFT 0x0 +#define DCIO_PATTERN_GEN_PAT__DCIO_PATTERN_GEN_PAT_MASK 0xFFFFFFFFL +//DCIO_PATTERN_GEN_EN +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN__SHIFT 0x0 +#define DCIO_PATTERN_GEN_EN__DCIO_PATTERN_GEN_EN_MASK 0x00000001L +//DCIO_BL_PWM_FRAME_START_DISP_SEL +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT 0x0 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT 0x4 +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK 0x00000007L +#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK 0x00000070L +//DCIO_GSL_GENLK_PAD_CNTL +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L +//DCIO_GSL_SWAPLOCK_PAD_CNTL +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT 0x4 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x8 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT 0x14 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x18 +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK 0x00000030L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK 0x00300000L +#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L +//DPCS_DCIO_TEST_CLK_SRC +#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL__SHIFT 0x0 +#define DPCS_DCIO_TEST_CLK_SRC__DPCS_TEST_CLK_SRC_SEL_MASK 0x00000007L +//DCIO_DEBUG +#define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x0 +#define DCIO_DEBUG__DCIO_DEBUG_MASK 0xFFFFFFFFL +//DCIO_TEST_DEBUG_INDEX +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x0 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x8 +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000FFL +#define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L +//DCIO_TEST_DEBUG_DATA +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x0 +#define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xFFFFFFFFL +//DBG_OUT_CNTL +#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL__SHIFT 0x0 +#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL__SHIFT 0x5 +#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA__SHIFT 0xc +#define DBG_OUT_CNTL__DBG_OUT_BLK_SEL_MASK 0x00000003L +#define DBG_OUT_CNTL__DBG_OUT_4BIT_SEL_MASK 0x000000E0L +#define DBG_OUT_CNTL__DBG_OUT_12BIT_TEST_DATA_MASK 0x00FFF000L +//DCIO_DEBUG_CONFIG +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN__SHIFT 0x0 +#define DCIO_DEBUG_CONFIG__DCIO_DBG_EN_MASK 0x00000001L +//DCIO_SOFT_RESET +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT 0x0 +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT 0x1 +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT 0x2 +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT 0x3 +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT 0x4 +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT 0x5 +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT 0x6 +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT 0x10 +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT 0x11 +#define DCIO_SOFT_RESET__DLPC_SOFT_RESET__SHIFT 0x14 +#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK 0x00000001L +#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK 0x00000002L +#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK 0x00000004L +#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK 0x00000008L +#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK 0x00000010L +#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK 0x00000020L +#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK 0x00000040L +#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK 0x00010000L +#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK 0x00020000L +#define DCIO_SOFT_RESET__DLPC_SOFT_RESET_MASK 0x00100000L + + +// addressBlock: dpcssys_dcio_dcio_chip_dispdec +//DC_GPIO_DDC1_MASK +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x10 +#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x14 +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC1_MASK__DC_GPIO_AUX1_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L +#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L +#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC1_MASK__DC_GPIO_AUX1_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC1_A +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L +//DC_GPIO_DDC1_EN +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC1_Y +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC2_MASK +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x10 +#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x14 +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC2_MASK__DC_GPIO_AUX2_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L +#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L +#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC2_MASK__DC_GPIO_AUX2_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC2_A +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L +//DC_GPIO_DDC2_EN +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC2_Y +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC3_MASK +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x10 +#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x14 +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC3_MASK__DC_GPIO_AUX3_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L +#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L +#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC3_MASK__DC_GPIO_AUX3_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC3_A +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L +//DC_GPIO_DDC3_EN +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC3_Y +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC4_MASK +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x10 +#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x14 +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC4_MASK__DC_GPIO_AUX4_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L +#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L +#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC4_MASK__DC_GPIO_AUX4_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC4_A +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L +//DC_GPIO_DDC4_EN +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC4_Y +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L +//DC_GPIO_DDC5_MASK +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x4 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0xe +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x10 +#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x14 +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDC5_MASK__DC_GPIO_AUX5_PD_HP_EN__SHIFT 0x18 +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L +#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L +#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDC5_MASK__DC_GPIO_AUX5_PD_HP_EN_MASK 0x01000000L +//DC_GPIO_DDC5_A +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x0 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x8 +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L +#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L +//DC_GPIO_DDC5_EN +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x0 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x8 +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L +#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L +//DC_GPIO_DDC5_Y +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x0 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x8 +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L +#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L +//DC_GPIO_DDCVGA_MASK +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x0 +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY__SHIFT 0x4 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x6 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x8 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0xc +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0xe +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x16 +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x1c +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L +#define DC_GPIO_DDCVGA_MASK__DDCVGA_INVERT_INPUT_POLARITY_MASK 0x00000010L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L +#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L +#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xF0000000L +//DC_GPIO_DDCVGA_A +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x0 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x8 +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L +#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L +//DC_GPIO_DDCVGA_EN +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x0 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x8 +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L +#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L +//DC_GPIO_DDCVGA_Y +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x0 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x8 +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L +#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L +//DC_GPIO_PWRSEQ0_EN +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_PAD_STRENGTH_1 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x0 +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x4 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x18 +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x1c +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000FL +#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000F0L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0F000000L +#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xF0000000L +//PHY_AUX_CNTL +#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x9 +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT 0xa +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT 0xc +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT 0xe +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT 0x10 +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT 0x12 +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT 0x14 +#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00000200L +#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK 0x00000C00L +#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK 0x00003000L +#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK 0x0000C000L +#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK 0x00030000L +#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK 0x000C0000L +#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK 0x00300000L +//DC_GPIO_PWRSEQ1_EN +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT 0x14 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT 0x15 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT 0x19 +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT 0x1a +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x1d +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK 0x00100000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK 0x00E00000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK 0x02000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK 0x1C000000L +#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x20000000L +//DC_GPIO_AUX_CTRL_0 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK 0x00003000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_1 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT 0x7 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT 0x1e +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK 0x00000040L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK 0x00000080L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK 0x00001800L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK 0x0000C000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK 0x20000000L +#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK 0xC0000000L +//DC_GPIO_AUX_CTRL_3 +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT 0x1 +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT 0x3 +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT 0x5 +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT 0x9 +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT 0xb +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK 0x00000001L +#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK 0x00000002L +#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK 0x00000004L +#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK 0x00000008L +#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK 0x00000010L +#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK 0x00000020L +#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK 0x00000100L +#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK 0x00000200L +#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK 0x00000400L +#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK 0x00000800L +#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK 0x00030000L +#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK 0x000C0000L +#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK 0x00300000L +#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK 0x00C00000L +#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK 0x03000000L +#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK 0x0C000000L +//DC_GPIO_AUX_CTRL_4 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK 0x0000000FL +#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK 0x000000F0L +#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK 0x00000F00L +#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK 0x0000F000L +#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK 0x000F0000L +#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK 0x00F00000L +//DC_GPIO_AUX_CTRL_5 +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT 0x0 +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT 0x2 +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT 0x4 +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT 0x6 +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT 0x8 +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT 0xa +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT 0xc +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT 0xd +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT 0xe +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT 0xf +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT 0x10 +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT 0x11 +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT 0x12 +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT 0x13 +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT 0x14 +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT 0x15 +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT 0x16 +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT 0x17 +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT 0x18 +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT 0x19 +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT 0x1a +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT 0x1b +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT 0x1c +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT 0x1d +#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK 0x00000003L +#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK 0x0000000CL +#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK 0x00000030L +#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK 0x000000C0L +#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK 0x00000300L +#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK 0x00000C00L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK 0x00001000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK 0x00002000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK 0x00004000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK 0x00008000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK 0x00010000L +#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK 0x00020000L +#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK 0x00040000L +#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK 0x00080000L +#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK 0x00100000L +#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK 0x00200000L +#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK 0x00400000L +#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK 0x00800000L +#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK 0x01000000L +#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK 0x02000000L +#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK 0x04000000L +#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK 0x08000000L +#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK 0x10000000L +#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK 0x20000000L +//AUXI2C_PAD_ALL_PWR_OK +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT 0x0 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT 0x1 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT 0x2 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT 0x3 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT 0x4 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT 0x5 +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK 0x00000001L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK 0x00000002L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK 0x00000004L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK 0x00000008L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK 0x00000010L +#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK 0x00000020L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h index 320e1ee5df1a9..2050888f7ec6d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h @@ -2616,6 +2616,13 @@ #define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f +#define mmSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_MASK_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA0_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA1_DEFAULT 0x00000000 #define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h index 5e15ac14b63c8..3645266a2bcb4 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h @@ -4493,6 +4493,8 @@ #define mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX 0 #define mmGB_EDC_MODE 0x1e1e #define mmGB_EDC_MODE_BASE_IDX 0 +#define mmCP_DEBUG 0x1e1f +#define mmCP_DEBUG_BASE_IDX 0 #define mmCP_PQ_WPTR_POLL_CNTL 0x1e23 #define mmCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 #define mmCP_PQ_WPTR_POLL_CNTL1 0x1e24 @@ -5155,6 +5157,8 @@ #define mmTCP_WATCH3_ADDR_L_BASE_IDX 0 #define mmTCP_WATCH3_CNTL 0x204b #define mmTCP_WATCH3_CNTL_BASE_IDX 0 +#define mmTCP_UTCL0_STATUS 0x2057 +#define mmTCP_UTCL0_STATUS_BASE_IDX 0 #define mmTCP_PERFCOUNTER_FILTER 0x2059 #define mmTCP_PERFCOUNTER_FILTER_BASE_IDX 0 #define mmTCP_PERFCOUNTER_FILTER_EN 0x205a @@ -6951,6 +6955,8 @@ #define mmCP_CE_IB1_CMD_BUFSZ_BASE_IDX 1 #define mmCP_CE_IB2_CMD_BUFSZ 0x20bf #define mmCP_CE_IB2_CMD_BUFSZ_BASE_IDX 1 +#define mmCP_IB1_CMD_BUFSZ 0x20c0 +#define mmCP_IB1_CMD_BUFSZ_BASE_IDX 1 #define mmCP_IB2_CMD_BUFSZ 0x20c1 #define mmCP_IB2_CMD_BUFSZ_BASE_IDX 1 #define mmCP_ST_CMD_BUFSZ 0x20c2 @@ -7413,6 +7419,8 @@ #define mmCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 #define mmCP_MES_DOORBELL_CONTROL6 0x2841 #define mmCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR 0x2842 +#define mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX 1 #define mmCP_MES_GP0_LO 0x2843 #define mmCP_MES_GP0_LO_BASE_IDX 1 #define mmCP_MES_GP0_HI 0x2844 @@ -9140,10 +9148,16 @@ #define mmRLC_LB_CNTR_INIT_1_BASE_IDX 1 #define mmRLC_LB_CNTR_1 0x4c1c #define mmRLC_LB_CNTR_1_BASE_IDX 1 +#define mmRLC_GPM_DEBUG_INST_ADDR 0x4c1d +#define mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX 1 #define mmRLC_JUMP_TABLE_RESTORE 0x4c1e #define mmRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 #define mmRLC_PG_DELAY_2 0x4c1f #define mmRLC_PG_DELAY_2_BASE_IDX 1 +#define mmRLC_GPM_DEBUG_INST_A 0x4c22 +#define mmRLC_GPM_DEBUG_INST_A_BASE_IDX 1 +#define mmRLC_GPM_DEBUG_INST_B 0x4c23 +#define mmRLC_GPM_DEBUG_INST_B_BASE_IDX 1 #define mmRLC_GPU_CLOCK_COUNT_LSB 0x4c24 #define mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 #define mmRLC_GPU_CLOCK_COUNT_MSB 0x4c25 @@ -9608,6 +9622,8 @@ #define mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 #define mmRLC_LB_CNTR_2 0x4de7 #define mmRLC_LB_CNTR_2_BASE_IDX 1 +#define mmRLC_LX6_CORE_PDEBUG_INST 0x4deb +#define mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX 1 #define mmRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1 #define mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1 #define mmRLC_CPAXI_DOORBELL_MON_STAT 0x4df2 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h index e4ecd6c2d20e2..dde32271fb860 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h @@ -18054,6 +18054,23 @@ #define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L #define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x0001FFFEL +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x00000003L +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0x0000000CL +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x00000070L +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x00000080L +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x00000100L +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x00000200L +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x00008000L +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xFFFF0000L //SPI_GDBG_TRAP_MASK #define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 #define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 @@ -19076,6 +19093,13 @@ #define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L +//TCP_UTCL0_STATUS +#define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L //TCP_PERFCOUNTER_FILTER #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 @@ -25836,6 +25860,9 @@ //CP_CE_IB1_CMD_BUFSZ #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 #define CP_CE_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB1_CMD_BUFSZ +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL //CP_CE_IB2_CMD_BUFSZ #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 #define CP_CE_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h new file mode 100644 index 0000000000000..d6a2839b4682a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -0,0 +1,12418 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_0_OFFSET_HEADER +#define _gc_12_1_0_OFFSET_HEADER + + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec +// base address: 0x4980 +#define regSDMA0_SDMA_DEC_START 0x0000 +#define regSDMA0_SDMA_DEC_START_BASE_IDX 0 +#define regSDMA0_SDMA_MCU_MISC_CNTL 0x0001 +#define regSDMA0_SDMA_MCU_MISC_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UCODE_REV 0x0003 +#define regSDMA0_SDMA_UCODE_REV_BASE_IDX 0 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_LO 0x0005 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_HI 0x0006 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA0_SDMA_POWER_CNTL 0x000c +#define regSDMA0_SDMA_POWER_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_CNTL 0x000d +#define regSDMA0_SDMA_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_CHICKEN_BITS 0x000e +#define regSDMA0_SDMA_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA0_SDMA_CACHE_CNTL 0x000f +#define regSDMA0_SDMA_CACHE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_RB_RPTR_FETCH 0x0020 +#define regSDMA0_SDMA_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA0_SDMA_RB_RPTR_FETCH_HI 0x0021 +#define regSDMA0_SDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA0_SDMA_IB_OFFSET_FETCH 0x0022 +#define regSDMA0_SDMA_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA0_SDMA_PROGRAM 0x0023 +#define regSDMA0_SDMA_PROGRAM_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS_REG 0x0024 +#define regSDMA0_SDMA_STATUS_REG_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS1_REG 0x0025 +#define regSDMA0_SDMA_STATUS1_REG_BASE_IDX 0 +#define regSDMA0_SDMA_CNTL1 0x0026 +#define regSDMA0_SDMA_CNTL1_BASE_IDX 0 +#define regSDMA0_SDMA_HBM_PAGE_CONFIG 0x0027 +#define regSDMA0_SDMA_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA0_SDMA_FREEZE 0x0028 +#define regSDMA0_SDMA_FREEZE_BASE_IDX 0 +#define regSDMA0_SDMA_PROCESS_QUANTUM0 0x0029 +#define regSDMA0_SDMA_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA0_SDMA_PROCESS_QUANTUM1 0x002a +#define regSDMA0_SDMA_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA0_SDMA_WATCHDOG_CNTL 0x002b +#define regSDMA0_SDMA_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_STATUS0 0x002c +#define regSDMA0_SDMA_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_STATUS1 0x002d +#define regSDMA0_SDMA_QUEUE_STATUS1_BASE_IDX 0 +#define regSDMA0_SDMA_ID 0x002e +#define regSDMA0_SDMA_ID_BASE_IDX 0 +#define regSDMA0_SDMA_VERSION 0x002f +#define regSDMA0_SDMA_VERSION_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS2_REG 0x0030 +#define regSDMA0_SDMA_STATUS2_REG_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_CNTL 0x0031 +#define regSDMA0_SDMA_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_PERMS_CNTL 0x0032 +#define regSDMA0_SDMA_ATOMIC_PERMS_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_PREOP_LO 0x0033 +#define regSDMA0_SDMA_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_PREOP_HI 0x0034 +#define regSDMA0_SDMA_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA0_SDMA_DCC_CNTL 0x0035 +#define regSDMA0_SDMA_DCC_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WARMUPL2_CNTL 0x0036 +#define regSDMA0_SDMA_UTCL1_WARMUPL2_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_CNTL 0x0037 +#define regSDMA0_SDMA_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WATERMK 0x0038 +#define regSDMA0_SDMA_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_TIMEOUT 0x0039 +#define regSDMA0_SDMA_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_PAGE 0x003a +#define regSDMA0_SDMA_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA0_SDMA_EXTERNAL_FROZEN 0x003b +#define regSDMA0_SDMA_EXTERNAL_FROZEN_BASE_IDX 0 +#define regSDMA0_SDMA_FREEZE_TRIGGER 0x003c +#define regSDMA0_SDMA_FREEZE_TRIGGER_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_CACHE_CNTL 0x0040 +#define regSDMA0_SDMA_UTCL1_CACHE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_RD_STATUS 0x0041 +#define regSDMA0_SDMA_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WR_STATUS 0x0042 +#define regSDMA0_SDMA_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_INV0 0x0043 +#define regSDMA0_SDMA_UTCL1_INV0_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_INV1 0x0044 +#define regSDMA0_SDMA_UTCL1_INV1_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_INV2 0x0045 +#define regSDMA0_SDMA_UTCL1_INV2_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_RD_XNACK0 0x0046 +#define regSDMA0_SDMA_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_RD_XNACK1 0x0047 +#define regSDMA0_SDMA_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WR_XNACK0 0x0048 +#define regSDMA0_SDMA_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WR_XNACK1 0x0049 +#define regSDMA0_SDMA_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA0_SDMA_CHICKEN_BITS_2 0x004a +#define regSDMA0_SDMA_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS3_REG 0x004b +#define regSDMA0_SDMA_STATUS3_REG_BASE_IDX 0 +#define regSDMA0_SDMA_GLOBAL_QUANTUM 0x004c +#define regSDMA0_SDMA_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA0_SDMA_ERROR_LOG 0x004d +#define regSDMA0_SDMA_ERROR_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG0 0x004e +#define regSDMA0_SDMA_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG1 0x004f +#define regSDMA0_SDMA_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG2 0x0050 +#define regSDMA0_SDMA_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG3 0x0051 +#define regSDMA0_SDMA_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA0_SDMA_MCU_COUNTER 0x0052 +#define regSDMA0_SDMA_MCU_COUNTER_BASE_IDX 0 +#define regSDMA0_SDMA_CRD_CNTL 0x0053 +#define regSDMA0_SDMA_CRD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_RLC_CGCG_CTRL 0x0054 +#define regSDMA0_SDMA_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG 0x0055 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_AQL_STATUS 0x0057 +#define regSDMA0_SDMA_AQL_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_TLBI_GCR_CNTL 0x0060 +#define regSDMA0_SDMA_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_INT_STATUS 0x0061 +#define regSDMA0_SDMA_INT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG2 0x0062 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define regSDMA0_SDMA_INVALID_ADDR_LO 0x0063 +#define regSDMA0_SDMA_INVALID_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_INVALID_ADDR_HI 0x0064 +#define regSDMA0_SDMA_INVALID_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_INVALID_ADDR_SOURCE 0x0065 +#define regSDMA0_SDMA_INVALID_ADDR_SOURCE_BASE_IDX 0 +#define regSDMA0_SDMA_CLOCK_GATING_STATUS 0x0066 +#define regSDMA0_SDMA_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS4_REG 0x0067 +#define regSDMA0_SDMA_STATUS4_REG_BASE_IDX 0 +#define regSDMA0_SDMA_SCRATCH_RAM_DATA 0x0068 +#define regSDMA0_SDMA_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA0_SDMA_SCRATCH_RAM_ADDR 0x0069 +#define regSDMA0_SDMA_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA0_SDMA_TIMESTAMP_CNTL 0x006a +#define regSDMA0_SDMA_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS5_REG 0x006b +#define regSDMA0_SDMA_STATUS5_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_RESET_REQ 0x006c +#define regSDMA0_SDMA_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_DEQUEUE_REQUEST 0x006d +#define regSDMA0_SDMA_QUEUE_DEQUEUE_REQUEST_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS6_REG 0x006e +#define regSDMA0_SDMA_STATUS6_REG_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS7_REG 0x006f +#define regSDMA0_SDMA_STATUS7_REG_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS8_REG 0x0070 +#define regSDMA0_SDMA_STATUS8_REG_BASE_IDX 0 +#define regSDMA0_SDMA_CE_CTRL 0x0071 +#define regSDMA0_SDMA_CE_CTRL_BASE_IDX 0 +#define regSDMA0_SDMA_RAS_STATUS 0x0072 +#define regSDMA0_SDMA_RAS_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_POISON_INFO 0x0073 +#define regSDMA0_SDMA_POISON_INFO_BASE_IDX 0 +#define regSDMA0_SDMA_MEMHUB_CNTL 0x0074 +#define regSDMA0_SDMA_MEMHUB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_CNTL 0x0200 +#define regSDMA0_SDMA_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_BASE 0x0201 +#define regSDMA0_SDMA_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_BASE_HI 0x0202 +#define regSDMA0_SDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR 0x0203 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_HI 0x0204 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR 0x0205 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_HI 0x0206 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO 0x0207 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI 0x0208 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_CNTL 0x0209 +#define regSDMA0_SDMA_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_RPTR 0x020a +#define regSDMA0_SDMA_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_OFFSET 0x020b +#define regSDMA0_SDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_BASE_LO 0x020c +#define regSDMA0_SDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_BASE_HI 0x020d +#define regSDMA0_SDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_SIZE 0x020e +#define regSDMA0_SDMA_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DOORBELL 0x020f +#define regSDMA0_SDMA_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_LOG 0x0210 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET 0x0211 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_LO 0x0212 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_HI 0x0213 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_SCHEDULE_CNTL 0x0214 +#define regSDMA0_SDMA_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_SUB_REMAIN 0x0215 +#define regSDMA0_SDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_PREEMPT 0x0216 +#define regSDMA0_SDMA_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG 0x0217 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x0218 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x0219 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_AQL_CNTL 0x021a +#define regSDMA0_SDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE 0x021b +#define regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS 0x021e +#define regSDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_CNTL 0x021f +#define regSDMA0_SDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA0 0x0220 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA1 0x0221 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA2 0x0222 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA3 0x0223 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA4 0x0224 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA5 0x0225 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA6 0x0226 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA7 0x0227 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA8 0x0228 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA9 0x0229 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA10 0x022a +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_LO 0x022b +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_HI 0x022c +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD 0x022d +#define regSDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO 0x022e +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI 0x022f +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MQD_CONTROL 0x0230 +#define regSDMA0_SDMA_QUEUE0_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CONTEXT_STATUS 0x0231 +#define regSDMA0_SDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG1 0x0232 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG2 0x0233 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_CNTL 0x023c +#define regSDMA0_SDMA_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_BASE 0x023d +#define regSDMA0_SDMA_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_BASE_HI 0x023e +#define regSDMA0_SDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR 0x023f +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_HI 0x0240 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR 0x0241 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_HI 0x0242 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO 0x0243 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI 0x0244 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_CNTL 0x0245 +#define regSDMA0_SDMA_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_RPTR 0x0246 +#define regSDMA0_SDMA_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_OFFSET 0x0247 +#define regSDMA0_SDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_LO 0x0248 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_HI 0x0249 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_SIZE 0x024a +#define regSDMA0_SDMA_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DOORBELL 0x024b +#define regSDMA0_SDMA_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DOORBELL_LOG 0x024c +#define regSDMA0_SDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DOORBELL_OFFSET 0x024d +#define regSDMA0_SDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_LO 0x024e +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_HI 0x024f +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_SCHEDULE_CNTL 0x0250 +#define regSDMA0_SDMA_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_SUB_REMAIN 0x0251 +#define regSDMA0_SDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_PREEMPT 0x0252 +#define regSDMA0_SDMA_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG 0x0253 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x0254 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x0255 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_AQL_CNTL 0x0256 +#define regSDMA0_SDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE 0x0257 +#define regSDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS 0x025a +#define regSDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_CNTL 0x025b +#define regSDMA0_SDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA0 0x025c +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA1 0x025d +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA2 0x025e +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA3 0x025f +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA4 0x0260 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA5 0x0261 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA6 0x0262 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA7 0x0263 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA8 0x0264 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA9 0x0265 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA10 0x0266 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_LO 0x0267 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_HI 0x0268 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD 0x0269 +#define regSDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO 0x026a +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI 0x026b +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MQD_CONTROL 0x026c +#define regSDMA0_SDMA_QUEUE1_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CONTEXT_STATUS 0x026d +#define regSDMA0_SDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG1 0x026e +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG2 0x026f +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_CNTL 0x0278 +#define regSDMA0_SDMA_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_BASE 0x0279 +#define regSDMA0_SDMA_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_BASE_HI 0x027a +#define regSDMA0_SDMA_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR 0x027b +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_HI 0x027c +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR 0x027d +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_HI 0x027e +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO 0x027f +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI 0x0280 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_CNTL 0x0281 +#define regSDMA0_SDMA_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_RPTR 0x0282 +#define regSDMA0_SDMA_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_OFFSET 0x0283 +#define regSDMA0_SDMA_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_LO 0x0284 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_HI 0x0285 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_SIZE 0x0286 +#define regSDMA0_SDMA_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DOORBELL 0x0287 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_LOG 0x0288 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_OFFSET 0x0289 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_LO 0x028a +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_HI 0x028b +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_SCHEDULE_CNTL 0x028c +#define regSDMA0_SDMA_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_SUB_REMAIN 0x028d +#define regSDMA0_SDMA_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_PREEMPT 0x028e +#define regSDMA0_SDMA_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG 0x028f +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0290 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0291 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_AQL_CNTL 0x0292 +#define regSDMA0_SDMA_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE 0x0293 +#define regSDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS 0x0296 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_CNTL 0x0297 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA0 0x0298 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA1 0x0299 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA2 0x029a +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA3 0x029b +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA4 0x029c +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA5 0x029d +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA6 0x029e +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA7 0x029f +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA8 0x02a0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA9 0x02a1 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA10 0x02a2 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_LO 0x02a3 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_HI 0x02a4 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD 0x02a5 +#define regSDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO 0x02a6 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI 0x02a7 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MQD_CONTROL 0x02a8 +#define regSDMA0_SDMA_QUEUE2_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_STATUS 0x02a9 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG1 0x02aa +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG2 0x02ab +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_CNTL 0x02b4 +#define regSDMA0_SDMA_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_BASE 0x02b5 +#define regSDMA0_SDMA_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_BASE_HI 0x02b6 +#define regSDMA0_SDMA_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR 0x02b7 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_HI 0x02b8 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR 0x02b9 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_HI 0x02ba +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO 0x02bb +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI 0x02bc +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_CNTL 0x02bd +#define regSDMA0_SDMA_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_RPTR 0x02be +#define regSDMA0_SDMA_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_OFFSET 0x02bf +#define regSDMA0_SDMA_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_LO 0x02c0 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_HI 0x02c1 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_SIZE 0x02c2 +#define regSDMA0_SDMA_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DOORBELL 0x02c3 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_LOG 0x02c4 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_OFFSET 0x02c5 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_LO 0x02c6 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_HI 0x02c7 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_SCHEDULE_CNTL 0x02c8 +#define regSDMA0_SDMA_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_SUB_REMAIN 0x02c9 +#define regSDMA0_SDMA_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_PREEMPT 0x02ca +#define regSDMA0_SDMA_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG 0x02cb +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x02cc +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x02cd +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_AQL_CNTL 0x02ce +#define regSDMA0_SDMA_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE 0x02cf +#define regSDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS 0x02d2 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_CNTL 0x02d3 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA0 0x02d4 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA1 0x02d5 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA2 0x02d6 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA3 0x02d7 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA4 0x02d8 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA5 0x02d9 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA6 0x02da +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA7 0x02db +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA8 0x02dc +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA9 0x02dd +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA10 0x02de +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_LO 0x02df +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_HI 0x02e0 +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD 0x02e1 +#define regSDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO 0x02e2 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI 0x02e3 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MQD_CONTROL 0x02e4 +#define regSDMA0_SDMA_QUEUE3_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_STATUS 0x02e5 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG1 0x02e6 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG2 0x02e7 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_CNTL 0x02f0 +#define regSDMA0_SDMA_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_BASE 0x02f1 +#define regSDMA0_SDMA_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_BASE_HI 0x02f2 +#define regSDMA0_SDMA_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR 0x02f3 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_HI 0x02f4 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR 0x02f5 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_HI 0x02f6 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO 0x02f7 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI 0x02f8 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_CNTL 0x02f9 +#define regSDMA0_SDMA_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_RPTR 0x02fa +#define regSDMA0_SDMA_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_OFFSET 0x02fb +#define regSDMA0_SDMA_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_BASE_LO 0x02fc +#define regSDMA0_SDMA_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_BASE_HI 0x02fd +#define regSDMA0_SDMA_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_SIZE 0x02fe +#define regSDMA0_SDMA_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DOORBELL 0x02ff +#define regSDMA0_SDMA_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_LOG 0x0300 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_OFFSET 0x0301 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_LO 0x0302 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_HI 0x0303 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_SCHEDULE_CNTL 0x0304 +#define regSDMA0_SDMA_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_SUB_REMAIN 0x0305 +#define regSDMA0_SDMA_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_PREEMPT 0x0306 +#define regSDMA0_SDMA_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG 0x0307 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0308 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0309 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_AQL_CNTL 0x030a +#define regSDMA0_SDMA_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE 0x030b +#define regSDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS 0x030e +#define regSDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_CNTL 0x030f +#define regSDMA0_SDMA_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA0 0x0310 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA1 0x0311 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA2 0x0312 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA3 0x0313 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA4 0x0314 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA5 0x0315 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA6 0x0316 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA7 0x0317 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA8 0x0318 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA9 0x0319 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA10 0x031a +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_LO 0x031b +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_HI 0x031c +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD 0x031d +#define regSDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO 0x031e +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI 0x031f +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MQD_CONTROL 0x0320 +#define regSDMA0_SDMA_QUEUE4_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CONTEXT_STATUS 0x0321 +#define regSDMA0_SDMA_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG1 0x0322 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG2 0x0323 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_CNTL 0x032c +#define regSDMA0_SDMA_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_BASE 0x032d +#define regSDMA0_SDMA_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_BASE_HI 0x032e +#define regSDMA0_SDMA_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR 0x032f +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_HI 0x0330 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR 0x0331 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_HI 0x0332 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO 0x0333 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI 0x0334 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_CNTL 0x0335 +#define regSDMA0_SDMA_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_RPTR 0x0336 +#define regSDMA0_SDMA_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_OFFSET 0x0337 +#define regSDMA0_SDMA_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_LO 0x0338 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_HI 0x0339 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_SIZE 0x033a +#define regSDMA0_SDMA_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DOORBELL 0x033b +#define regSDMA0_SDMA_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DOORBELL_LOG 0x033c +#define regSDMA0_SDMA_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DOORBELL_OFFSET 0x033d +#define regSDMA0_SDMA_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_LO 0x033e +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_HI 0x033f +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_SCHEDULE_CNTL 0x0340 +#define regSDMA0_SDMA_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_SUB_REMAIN 0x0341 +#define regSDMA0_SDMA_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_PREEMPT 0x0342 +#define regSDMA0_SDMA_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG 0x0343 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x0344 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x0345 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_AQL_CNTL 0x0346 +#define regSDMA0_SDMA_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE 0x0347 +#define regSDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS 0x034a +#define regSDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_CNTL 0x034b +#define regSDMA0_SDMA_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA0 0x034c +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA1 0x034d +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA2 0x034e +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA3 0x034f +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA4 0x0350 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA5 0x0351 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA6 0x0352 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA7 0x0353 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA8 0x0354 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA9 0x0355 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA10 0x0356 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_LO 0x0357 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_HI 0x0358 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD 0x0359 +#define regSDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO 0x035a +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI 0x035b +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MQD_CONTROL 0x035c +#define regSDMA0_SDMA_QUEUE5_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CONTEXT_STATUS 0x035d +#define regSDMA0_SDMA_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG1 0x035e +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG2 0x035f +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_CNTL 0x0368 +#define regSDMA0_SDMA_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_BASE 0x0369 +#define regSDMA0_SDMA_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_BASE_HI 0x036a +#define regSDMA0_SDMA_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR 0x036b +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_HI 0x036c +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR 0x036d +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_HI 0x036e +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO 0x036f +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI 0x0370 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_CNTL 0x0371 +#define regSDMA0_SDMA_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_RPTR 0x0372 +#define regSDMA0_SDMA_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_OFFSET 0x0373 +#define regSDMA0_SDMA_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_LO 0x0374 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_HI 0x0375 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_SIZE 0x0376 +#define regSDMA0_SDMA_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DOORBELL 0x0377 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_LOG 0x0378 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_OFFSET 0x0379 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_LO 0x037a +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_HI 0x037b +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_SCHEDULE_CNTL 0x037c +#define regSDMA0_SDMA_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_SUB_REMAIN 0x037d +#define regSDMA0_SDMA_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_PREEMPT 0x037e +#define regSDMA0_SDMA_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG 0x037f +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x0380 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x0381 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_AQL_CNTL 0x0382 +#define regSDMA0_SDMA_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE 0x0383 +#define regSDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS 0x0386 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_CNTL 0x0387 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA0 0x0388 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA1 0x0389 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA2 0x038a +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA3 0x038b +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA4 0x038c +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA5 0x038d +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA6 0x038e +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA7 0x038f +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA8 0x0390 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA9 0x0391 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA10 0x0392 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_LO 0x0393 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_HI 0x0394 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD 0x0395 +#define regSDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO 0x0396 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI 0x0397 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MQD_CONTROL 0x0398 +#define regSDMA0_SDMA_QUEUE6_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_STATUS 0x0399 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG1 0x039a +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG2 0x039b +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_CNTL 0x03a4 +#define regSDMA0_SDMA_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_BASE 0x03a5 +#define regSDMA0_SDMA_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_BASE_HI 0x03a6 +#define regSDMA0_SDMA_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR 0x03a7 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_HI 0x03a8 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR 0x03a9 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_HI 0x03aa +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO 0x03ab +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI 0x03ac +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_CNTL 0x03ad +#define regSDMA0_SDMA_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_RPTR 0x03ae +#define regSDMA0_SDMA_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_OFFSET 0x03af +#define regSDMA0_SDMA_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_LO 0x03b0 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_HI 0x03b1 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_SIZE 0x03b2 +#define regSDMA0_SDMA_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DOORBELL 0x03b3 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_LOG 0x03b4 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_OFFSET 0x03b5 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_LO 0x03b6 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_HI 0x03b7 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_SCHEDULE_CNTL 0x03b8 +#define regSDMA0_SDMA_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_SUB_REMAIN 0x03b9 +#define regSDMA0_SDMA_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_PREEMPT 0x03ba +#define regSDMA0_SDMA_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG 0x03bb +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x03bc +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x03bd +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_AQL_CNTL 0x03be +#define regSDMA0_SDMA_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE 0x03bf +#define regSDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS 0x03c2 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_CNTL 0x03c3 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA0 0x03c4 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA1 0x03c5 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA2 0x03c6 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA3 0x03c7 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA4 0x03c8 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA5 0x03c9 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA6 0x03ca +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA7 0x03cb +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA8 0x03cc +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA9 0x03cd +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA10 0x03ce +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_LO 0x03cf +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_HI 0x03d0 +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD 0x03d1 +#define regSDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO 0x03d2 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI 0x03d3 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MQD_CONTROL 0x03d4 +#define regSDMA0_SDMA_QUEUE7_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_STATUS 0x03d5 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG1 0x03d6 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG2 0x03d7 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_CNTL 0x03e0 +#define regSDMA0_SDMA_QUEUE8_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_BASE 0x03e1 +#define regSDMA0_SDMA_QUEUE8_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_BASE_HI 0x03e2 +#define regSDMA0_SDMA_QUEUE8_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR 0x03e3 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_HI 0x03e4 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR 0x03e5 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_HI 0x03e6 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO 0x03e7 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI 0x03e8 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_CNTL 0x03e9 +#define regSDMA0_SDMA_QUEUE8_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_RPTR 0x03ea +#define regSDMA0_SDMA_QUEUE8_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_OFFSET 0x03eb +#define regSDMA0_SDMA_QUEUE8_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_BASE_LO 0x03ec +#define regSDMA0_SDMA_QUEUE8_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_BASE_HI 0x03ed +#define regSDMA0_SDMA_QUEUE8_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_SIZE 0x03ee +#define regSDMA0_SDMA_QUEUE8_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL 0x03ef +#define regSDMA0_SDMA_QUEUE8_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_LOG 0x03f0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_OFFSET 0x03f1 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_LO 0x03f2 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_HI 0x03f3 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_SCHEDULE_CNTL 0x03f4 +#define regSDMA0_SDMA_QUEUE8_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_SUB_REMAIN 0x03f5 +#define regSDMA0_SDMA_QUEUE8_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_PREEMPT 0x03f6 +#define regSDMA0_SDMA_QUEUE8_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG 0x03f7 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO 0x03f8 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI 0x03f9 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_AQL_CNTL 0x03fa +#define regSDMA0_SDMA_QUEUE8_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE 0x03fb +#define regSDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS 0x03fe +#define regSDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_CNTL 0x03ff +#define regSDMA0_SDMA_QUEUE8_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA0 0x0400 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA1 0x0401 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA2 0x0402 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA3 0x0403 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA4 0x0404 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA5 0x0405 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA6 0x0406 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA7 0x0407 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA8 0x0408 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA9 0x0409 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA10 0x040a +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_LO 0x040b +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_HI 0x040c +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD 0x040d +#define regSDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO 0x040e +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI 0x040f +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MQD_CONTROL 0x0410 +#define regSDMA0_SDMA_QUEUE8_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CONTEXT_STATUS 0x0411 +#define regSDMA0_SDMA_QUEUE8_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG1 0x0412 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG2 0x0413 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_CNTL 0x041c +#define regSDMA0_SDMA_QUEUE9_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_BASE 0x041d +#define regSDMA0_SDMA_QUEUE9_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_BASE_HI 0x041e +#define regSDMA0_SDMA_QUEUE9_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR 0x041f +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_HI 0x0420 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR 0x0421 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_HI 0x0422 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO 0x0423 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI 0x0424 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_CNTL 0x0425 +#define regSDMA0_SDMA_QUEUE9_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_RPTR 0x0426 +#define regSDMA0_SDMA_QUEUE9_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_OFFSET 0x0427 +#define regSDMA0_SDMA_QUEUE9_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_LO 0x0428 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_HI 0x0429 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_SIZE 0x042a +#define regSDMA0_SDMA_QUEUE9_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DOORBELL 0x042b +#define regSDMA0_SDMA_QUEUE9_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DOORBELL_LOG 0x042c +#define regSDMA0_SDMA_QUEUE9_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DOORBELL_OFFSET 0x042d +#define regSDMA0_SDMA_QUEUE9_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_LO 0x042e +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_HI 0x042f +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_SCHEDULE_CNTL 0x0430 +#define regSDMA0_SDMA_QUEUE9_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_SUB_REMAIN 0x0431 +#define regSDMA0_SDMA_QUEUE9_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_PREEMPT 0x0432 +#define regSDMA0_SDMA_QUEUE9_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG 0x0433 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO 0x0434 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI 0x0435 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_AQL_CNTL 0x0436 +#define regSDMA0_SDMA_QUEUE9_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE 0x0437 +#define regSDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS 0x043a +#define regSDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_CNTL 0x043b +#define regSDMA0_SDMA_QUEUE9_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA0 0x043c +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA1 0x043d +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA2 0x043e +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA3 0x043f +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA4 0x0440 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA5 0x0441 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA6 0x0442 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA7 0x0443 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA8 0x0444 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA9 0x0445 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA10 0x0446 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_LO 0x0447 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_HI 0x0448 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD 0x0449 +#define regSDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO 0x044a +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI 0x044b +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MQD_CONTROL 0x044c +#define regSDMA0_SDMA_QUEUE9_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CONTEXT_STATUS 0x044d +#define regSDMA0_SDMA_QUEUE9_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG1 0x044e +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG2 0x044f +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG2_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec +// base address: 0x3e200 +#define regSDMA0_SDMA_VM_CTX_LO 0x5880 +#define regSDMA0_SDMA_VM_CTX_LO_BASE_IDX 1 +#define regSDMA0_SDMA_VM_CTX_HI 0x5881 +#define regSDMA0_SDMA_VM_CTX_HI_BASE_IDX 1 +#define regSDMA0_SDMA_ACTIVE_FCN_ID 0x5882 +#define regSDMA0_SDMA_ACTIVE_FCN_ID_BASE_IDX 1 +#define regSDMA0_SDMA_VM_CTX_CNTL 0x5883 +#define regSDMA0_SDMA_VM_CTX_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_VIRT_RESET_REQ 0x5884 +#define regSDMA0_SDMA_VIRT_RESET_REQ_BASE_IDX 1 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE0 0x5885 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE1 0x5886 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE2 0x5887 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE0 0x5888 +#define regSDMA0_SDMA_PUB_REG_TYPE0_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE1 0x5889 +#define regSDMA0_SDMA_PUB_REG_TYPE1_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE2 0x588a +#define regSDMA0_SDMA_PUB_REG_TYPE2_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE3 0x588b +#define regSDMA0_SDMA_PUB_REG_TYPE3_BASE_IDX 1 +#define regSDMA0_SDMA_VM_CNTL 0x588d +#define regSDMA0_SDMA_VM_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_MCU_CNTL 0x588e +#define regSDMA0_SDMA_MCU_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_IC_BASE_LO 0x589a +#define regSDMA0_SDMA_IC_BASE_LO_BASE_IDX 1 +#define regSDMA0_SDMA_IC_BASE_HI 0x589b +#define regSDMA0_SDMA_IC_BASE_HI_BASE_IDX 1 +#define regSDMA0_SDMA_IC_BASE_CNTL 0x589c +#define regSDMA0_SDMA_IC_BASE_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_IC_OP_CNTL 0x589d +#define regSDMA0_SDMA_IC_OP_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_IC_CNTL 0x589f +#define regSDMA0_SDMA_IC_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec +// base address: 0x3f200 +#define regSDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET 0x5cc4 +#define regSDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec +// base address: 0x37880 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG 0x3e20 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG 0x3e21 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG 0x3e22 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e23 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_MISC_CNTL 0x3e24 +#define regSDMA0_SDMA_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT 0x3e25 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT1 0x3e26 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT 0x3e27 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT1 0x3e28 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT 0x3e29 +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT1 0x3e2a +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT 0x3e2b +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT1 0x3e2c +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT 0x3e2d +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT1 0x3e2e +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT 0x3e2f +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT1 0x3e30 +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec +// base address: 0x35980 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_LO 0x3660 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_HI 0x3661 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_LO 0x3662 +#define regSDMA0_SDMA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_HI 0x3663 +#define regSDMA0_SDMA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_LO 0x3664 +#define regSDMA0_SDMA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_HI 0x3665 +#define regSDMA0_SDMA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_LO 0x3666 +#define regSDMA0_SDMA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_HI 0x3667 +#define regSDMA0_SDMA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_LO 0x3668 +#define regSDMA0_SDMA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_HI 0x3669 +#define regSDMA0_SDMA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_LO 0x366a +#define regSDMA0_SDMA_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_HI 0x366b +#define regSDMA0_SDMA_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_LO 0x366c +#define regSDMA0_SDMA_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_HI 0x366d +#define regSDMA0_SDMA_PERFCOUNTER5_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec +// base address: 0x3c430 +#define regSDMA0_GFX_ICG_SDMA_CTRL 0x510c +#define regSDMA0_GFX_ICG_SDMA_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec:1 +// base address: 0x6180 +#define regSDMA1_SDMA_DEC_START 0x0600 +#define regSDMA1_SDMA_DEC_START_BASE_IDX 0 +#define regSDMA1_SDMA_MCU_MISC_CNTL 0x0601 +#define regSDMA1_SDMA_MCU_MISC_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UCODE_REV 0x0603 +#define regSDMA1_SDMA_UCODE_REV_BASE_IDX 0 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_LO 0x0605 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_HI 0x0606 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA1_SDMA_POWER_CNTL 0x060c +#define regSDMA1_SDMA_POWER_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_CNTL 0x060d +#define regSDMA1_SDMA_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_CHICKEN_BITS 0x060e +#define regSDMA1_SDMA_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA1_SDMA_CACHE_CNTL 0x060f +#define regSDMA1_SDMA_CACHE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_RB_RPTR_FETCH 0x0620 +#define regSDMA1_SDMA_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA1_SDMA_RB_RPTR_FETCH_HI 0x0621 +#define regSDMA1_SDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA1_SDMA_IB_OFFSET_FETCH 0x0622 +#define regSDMA1_SDMA_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA1_SDMA_PROGRAM 0x0623 +#define regSDMA1_SDMA_PROGRAM_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS_REG 0x0624 +#define regSDMA1_SDMA_STATUS_REG_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS1_REG 0x0625 +#define regSDMA1_SDMA_STATUS1_REG_BASE_IDX 0 +#define regSDMA1_SDMA_CNTL1 0x0626 +#define regSDMA1_SDMA_CNTL1_BASE_IDX 0 +#define regSDMA1_SDMA_HBM_PAGE_CONFIG 0x0627 +#define regSDMA1_SDMA_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA1_SDMA_FREEZE 0x0628 +#define regSDMA1_SDMA_FREEZE_BASE_IDX 0 +#define regSDMA1_SDMA_PROCESS_QUANTUM0 0x0629 +#define regSDMA1_SDMA_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA1_SDMA_PROCESS_QUANTUM1 0x062a +#define regSDMA1_SDMA_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA1_SDMA_WATCHDOG_CNTL 0x062b +#define regSDMA1_SDMA_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_STATUS0 0x062c +#define regSDMA1_SDMA_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_STATUS1 0x062d +#define regSDMA1_SDMA_QUEUE_STATUS1_BASE_IDX 0 +#define regSDMA1_SDMA_ID 0x062e +#define regSDMA1_SDMA_ID_BASE_IDX 0 +#define regSDMA1_SDMA_VERSION 0x062f +#define regSDMA1_SDMA_VERSION_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS2_REG 0x0630 +#define regSDMA1_SDMA_STATUS2_REG_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_CNTL 0x0631 +#define regSDMA1_SDMA_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_PERMS_CNTL 0x0632 +#define regSDMA1_SDMA_ATOMIC_PERMS_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_PREOP_LO 0x0633 +#define regSDMA1_SDMA_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_PREOP_HI 0x0634 +#define regSDMA1_SDMA_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA1_SDMA_DCC_CNTL 0x0635 +#define regSDMA1_SDMA_DCC_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WARMUPL2_CNTL 0x0636 +#define regSDMA1_SDMA_UTCL1_WARMUPL2_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_CNTL 0x0637 +#define regSDMA1_SDMA_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WATERMK 0x0638 +#define regSDMA1_SDMA_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_TIMEOUT 0x0639 +#define regSDMA1_SDMA_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_PAGE 0x063a +#define regSDMA1_SDMA_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA1_SDMA_EXTERNAL_FROZEN 0x063b +#define regSDMA1_SDMA_EXTERNAL_FROZEN_BASE_IDX 0 +#define regSDMA1_SDMA_FREEZE_TRIGGER 0x063c +#define regSDMA1_SDMA_FREEZE_TRIGGER_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_CACHE_CNTL 0x0640 +#define regSDMA1_SDMA_UTCL1_CACHE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_RD_STATUS 0x0641 +#define regSDMA1_SDMA_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WR_STATUS 0x0642 +#define regSDMA1_SDMA_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_INV0 0x0643 +#define regSDMA1_SDMA_UTCL1_INV0_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_INV1 0x0644 +#define regSDMA1_SDMA_UTCL1_INV1_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_INV2 0x0645 +#define regSDMA1_SDMA_UTCL1_INV2_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_RD_XNACK0 0x0646 +#define regSDMA1_SDMA_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_RD_XNACK1 0x0647 +#define regSDMA1_SDMA_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WR_XNACK0 0x0648 +#define regSDMA1_SDMA_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WR_XNACK1 0x0649 +#define regSDMA1_SDMA_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA1_SDMA_CHICKEN_BITS_2 0x064a +#define regSDMA1_SDMA_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS3_REG 0x064b +#define regSDMA1_SDMA_STATUS3_REG_BASE_IDX 0 +#define regSDMA1_SDMA_GLOBAL_QUANTUM 0x064c +#define regSDMA1_SDMA_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA1_SDMA_ERROR_LOG 0x064d +#define regSDMA1_SDMA_ERROR_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG0 0x064e +#define regSDMA1_SDMA_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG1 0x064f +#define regSDMA1_SDMA_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG2 0x0650 +#define regSDMA1_SDMA_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG3 0x0651 +#define regSDMA1_SDMA_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA1_SDMA_MCU_COUNTER 0x0652 +#define regSDMA1_SDMA_MCU_COUNTER_BASE_IDX 0 +#define regSDMA1_SDMA_CRD_CNTL 0x0653 +#define regSDMA1_SDMA_CRD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_RLC_CGCG_CTRL 0x0654 +#define regSDMA1_SDMA_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG 0x0655 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_AQL_STATUS 0x0657 +#define regSDMA1_SDMA_AQL_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_TLBI_GCR_CNTL 0x0660 +#define regSDMA1_SDMA_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_INT_STATUS 0x0661 +#define regSDMA1_SDMA_INT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG2 0x0662 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define regSDMA1_SDMA_INVALID_ADDR_LO 0x0663 +#define regSDMA1_SDMA_INVALID_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_INVALID_ADDR_HI 0x0664 +#define regSDMA1_SDMA_INVALID_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_INVALID_ADDR_SOURCE 0x0665 +#define regSDMA1_SDMA_INVALID_ADDR_SOURCE_BASE_IDX 0 +#define regSDMA1_SDMA_CLOCK_GATING_STATUS 0x0666 +#define regSDMA1_SDMA_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS4_REG 0x0667 +#define regSDMA1_SDMA_STATUS4_REG_BASE_IDX 0 +#define regSDMA1_SDMA_SCRATCH_RAM_DATA 0x0668 +#define regSDMA1_SDMA_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA1_SDMA_SCRATCH_RAM_ADDR 0x0669 +#define regSDMA1_SDMA_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA1_SDMA_TIMESTAMP_CNTL 0x066a +#define regSDMA1_SDMA_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS5_REG 0x066b +#define regSDMA1_SDMA_STATUS5_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_RESET_REQ 0x066c +#define regSDMA1_SDMA_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_DEQUEUE_REQUEST 0x066d +#define regSDMA1_SDMA_QUEUE_DEQUEUE_REQUEST_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS6_REG 0x066e +#define regSDMA1_SDMA_STATUS6_REG_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS7_REG 0x066f +#define regSDMA1_SDMA_STATUS7_REG_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS8_REG 0x0670 +#define regSDMA1_SDMA_STATUS8_REG_BASE_IDX 0 +#define regSDMA1_SDMA_CE_CTRL 0x0671 +#define regSDMA1_SDMA_CE_CTRL_BASE_IDX 0 +#define regSDMA1_SDMA_RAS_STATUS 0x0672 +#define regSDMA1_SDMA_RAS_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_POISON_INFO 0x0673 +#define regSDMA1_SDMA_POISON_INFO_BASE_IDX 0 +#define regSDMA1_SDMA_MEMHUB_CNTL 0x0674 +#define regSDMA1_SDMA_MEMHUB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_CNTL 0x0800 +#define regSDMA1_SDMA_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_BASE 0x0801 +#define regSDMA1_SDMA_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_BASE_HI 0x0802 +#define regSDMA1_SDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR 0x0803 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_HI 0x0804 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR 0x0805 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_HI 0x0806 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO 0x0807 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI 0x0808 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_CNTL 0x0809 +#define regSDMA1_SDMA_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_RPTR 0x080a +#define regSDMA1_SDMA_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_OFFSET 0x080b +#define regSDMA1_SDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_BASE_LO 0x080c +#define regSDMA1_SDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_BASE_HI 0x080d +#define regSDMA1_SDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_SIZE 0x080e +#define regSDMA1_SDMA_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DOORBELL 0x080f +#define regSDMA1_SDMA_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_LOG 0x0810 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_OFFSET 0x0811 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_LO 0x0812 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_HI 0x0813 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_SCHEDULE_CNTL 0x0814 +#define regSDMA1_SDMA_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_SUB_REMAIN 0x0815 +#define regSDMA1_SDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_PREEMPT 0x0816 +#define regSDMA1_SDMA_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG 0x0817 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x0818 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x0819 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_AQL_CNTL 0x081a +#define regSDMA1_SDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE 0x081b +#define regSDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS 0x081e +#define regSDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_CNTL 0x081f +#define regSDMA1_SDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA0 0x0820 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA1 0x0821 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA2 0x0822 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA3 0x0823 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA4 0x0824 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA5 0x0825 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA6 0x0826 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA7 0x0827 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA8 0x0828 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA9 0x0829 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA10 0x082a +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_LO 0x082b +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_HI 0x082c +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD 0x082d +#define regSDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO 0x082e +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI 0x082f +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MQD_CONTROL 0x0830 +#define regSDMA1_SDMA_QUEUE0_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CONTEXT_STATUS 0x0831 +#define regSDMA1_SDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG1 0x0832 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG2 0x0833 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_CNTL 0x083c +#define regSDMA1_SDMA_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_BASE 0x083d +#define regSDMA1_SDMA_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_BASE_HI 0x083e +#define regSDMA1_SDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR 0x083f +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_HI 0x0840 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR 0x0841 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_HI 0x0842 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO 0x0843 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI 0x0844 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_CNTL 0x0845 +#define regSDMA1_SDMA_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_RPTR 0x0846 +#define regSDMA1_SDMA_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_OFFSET 0x0847 +#define regSDMA1_SDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_LO 0x0848 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_HI 0x0849 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_SIZE 0x084a +#define regSDMA1_SDMA_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DOORBELL 0x084b +#define regSDMA1_SDMA_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DOORBELL_LOG 0x084c +#define regSDMA1_SDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DOORBELL_OFFSET 0x084d +#define regSDMA1_SDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_LO 0x084e +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_HI 0x084f +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_SCHEDULE_CNTL 0x0850 +#define regSDMA1_SDMA_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_SUB_REMAIN 0x0851 +#define regSDMA1_SDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_PREEMPT 0x0852 +#define regSDMA1_SDMA_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG 0x0853 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x0854 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x0855 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_AQL_CNTL 0x0856 +#define regSDMA1_SDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE 0x0857 +#define regSDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS 0x085a +#define regSDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_CNTL 0x085b +#define regSDMA1_SDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA0 0x085c +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA1 0x085d +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA2 0x085e +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA3 0x085f +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA4 0x0860 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA5 0x0861 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA6 0x0862 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA7 0x0863 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA8 0x0864 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA9 0x0865 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA10 0x0866 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_LO 0x0867 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_HI 0x0868 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD 0x0869 +#define regSDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO 0x086a +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI 0x086b +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MQD_CONTROL 0x086c +#define regSDMA1_SDMA_QUEUE1_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CONTEXT_STATUS 0x086d +#define regSDMA1_SDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG1 0x086e +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG2 0x086f +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_CNTL 0x0878 +#define regSDMA1_SDMA_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_BASE 0x0879 +#define regSDMA1_SDMA_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_BASE_HI 0x087a +#define regSDMA1_SDMA_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR 0x087b +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_HI 0x087c +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR 0x087d +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_HI 0x087e +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO 0x087f +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI 0x0880 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_CNTL 0x0881 +#define regSDMA1_SDMA_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_RPTR 0x0882 +#define regSDMA1_SDMA_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_OFFSET 0x0883 +#define regSDMA1_SDMA_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_LO 0x0884 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_HI 0x0885 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_SIZE 0x0886 +#define regSDMA1_SDMA_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DOORBELL 0x0887 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_LOG 0x0888 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_OFFSET 0x0889 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_LO 0x088a +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_HI 0x088b +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_SCHEDULE_CNTL 0x088c +#define regSDMA1_SDMA_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_SUB_REMAIN 0x088d +#define regSDMA1_SDMA_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_PREEMPT 0x088e +#define regSDMA1_SDMA_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG 0x088f +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0890 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0891 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_AQL_CNTL 0x0892 +#define regSDMA1_SDMA_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE 0x0893 +#define regSDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS 0x0896 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_CNTL 0x0897 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA0 0x0898 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA1 0x0899 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA2 0x089a +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA3 0x089b +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA4 0x089c +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA5 0x089d +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA6 0x089e +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA7 0x089f +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA8 0x08a0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA9 0x08a1 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA10 0x08a2 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_LO 0x08a3 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_HI 0x08a4 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD 0x08a5 +#define regSDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO 0x08a6 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI 0x08a7 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MQD_CONTROL 0x08a8 +#define regSDMA1_SDMA_QUEUE2_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_STATUS 0x08a9 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG1 0x08aa +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG2 0x08ab +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_CNTL 0x08b4 +#define regSDMA1_SDMA_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_BASE 0x08b5 +#define regSDMA1_SDMA_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_BASE_HI 0x08b6 +#define regSDMA1_SDMA_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR 0x08b7 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_HI 0x08b8 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR 0x08b9 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_HI 0x08ba +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO 0x08bb +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI 0x08bc +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_CNTL 0x08bd +#define regSDMA1_SDMA_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_RPTR 0x08be +#define regSDMA1_SDMA_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_OFFSET 0x08bf +#define regSDMA1_SDMA_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_LO 0x08c0 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_HI 0x08c1 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_SIZE 0x08c2 +#define regSDMA1_SDMA_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DOORBELL 0x08c3 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_LOG 0x08c4 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_OFFSET 0x08c5 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_LO 0x08c6 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_HI 0x08c7 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_SCHEDULE_CNTL 0x08c8 +#define regSDMA1_SDMA_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_SUB_REMAIN 0x08c9 +#define regSDMA1_SDMA_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_PREEMPT 0x08ca +#define regSDMA1_SDMA_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG 0x08cb +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x08cc +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x08cd +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_AQL_CNTL 0x08ce +#define regSDMA1_SDMA_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE 0x08cf +#define regSDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS 0x08d2 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_CNTL 0x08d3 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA0 0x08d4 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA1 0x08d5 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA2 0x08d6 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA3 0x08d7 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA4 0x08d8 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA5 0x08d9 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA6 0x08da +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA7 0x08db +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA8 0x08dc +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA9 0x08dd +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA10 0x08de +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_LO 0x08df +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_HI 0x08e0 +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD 0x08e1 +#define regSDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO 0x08e2 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI 0x08e3 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MQD_CONTROL 0x08e4 +#define regSDMA1_SDMA_QUEUE3_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_STATUS 0x08e5 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG1 0x08e6 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG2 0x08e7 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_CNTL 0x08f0 +#define regSDMA1_SDMA_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_BASE 0x08f1 +#define regSDMA1_SDMA_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_BASE_HI 0x08f2 +#define regSDMA1_SDMA_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR 0x08f3 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_HI 0x08f4 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR 0x08f5 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_HI 0x08f6 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO 0x08f7 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI 0x08f8 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_CNTL 0x08f9 +#define regSDMA1_SDMA_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_RPTR 0x08fa +#define regSDMA1_SDMA_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_OFFSET 0x08fb +#define regSDMA1_SDMA_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_BASE_LO 0x08fc +#define regSDMA1_SDMA_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_BASE_HI 0x08fd +#define regSDMA1_SDMA_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_SIZE 0x08fe +#define regSDMA1_SDMA_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DOORBELL 0x08ff +#define regSDMA1_SDMA_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_LOG 0x0900 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_OFFSET 0x0901 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_LO 0x0902 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_HI 0x0903 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_SCHEDULE_CNTL 0x0904 +#define regSDMA1_SDMA_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_SUB_REMAIN 0x0905 +#define regSDMA1_SDMA_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_PREEMPT 0x0906 +#define regSDMA1_SDMA_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG 0x0907 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0908 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0909 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_AQL_CNTL 0x090a +#define regSDMA1_SDMA_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE 0x090b +#define regSDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS 0x090e +#define regSDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_CNTL 0x090f +#define regSDMA1_SDMA_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA0 0x0910 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA1 0x0911 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA2 0x0912 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA3 0x0913 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA4 0x0914 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA5 0x0915 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA6 0x0916 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA7 0x0917 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA8 0x0918 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA9 0x0919 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA10 0x091a +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_LO 0x091b +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_HI 0x091c +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD 0x091d +#define regSDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO 0x091e +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI 0x091f +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MQD_CONTROL 0x0920 +#define regSDMA1_SDMA_QUEUE4_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CONTEXT_STATUS 0x0921 +#define regSDMA1_SDMA_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG1 0x0922 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG2 0x0923 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_CNTL 0x092c +#define regSDMA1_SDMA_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_BASE 0x092d +#define regSDMA1_SDMA_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_BASE_HI 0x092e +#define regSDMA1_SDMA_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR 0x092f +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_HI 0x0930 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR 0x0931 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_HI 0x0932 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO 0x0933 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI 0x0934 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_CNTL 0x0935 +#define regSDMA1_SDMA_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_RPTR 0x0936 +#define regSDMA1_SDMA_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_OFFSET 0x0937 +#define regSDMA1_SDMA_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_LO 0x0938 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_HI 0x0939 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_SIZE 0x093a +#define regSDMA1_SDMA_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DOORBELL 0x093b +#define regSDMA1_SDMA_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DOORBELL_LOG 0x093c +#define regSDMA1_SDMA_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DOORBELL_OFFSET 0x093d +#define regSDMA1_SDMA_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_LO 0x093e +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_HI 0x093f +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_SCHEDULE_CNTL 0x0940 +#define regSDMA1_SDMA_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_SUB_REMAIN 0x0941 +#define regSDMA1_SDMA_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_PREEMPT 0x0942 +#define regSDMA1_SDMA_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG 0x0943 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x0944 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x0945 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_AQL_CNTL 0x0946 +#define regSDMA1_SDMA_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE 0x0947 +#define regSDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS 0x094a +#define regSDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_CNTL 0x094b +#define regSDMA1_SDMA_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA0 0x094c +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA1 0x094d +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA2 0x094e +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA3 0x094f +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA4 0x0950 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA5 0x0951 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA6 0x0952 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA7 0x0953 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA8 0x0954 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA9 0x0955 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA10 0x0956 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_LO 0x0957 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_HI 0x0958 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD 0x0959 +#define regSDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO 0x095a +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI 0x095b +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MQD_CONTROL 0x095c +#define regSDMA1_SDMA_QUEUE5_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CONTEXT_STATUS 0x095d +#define regSDMA1_SDMA_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG1 0x095e +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG2 0x095f +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_CNTL 0x0968 +#define regSDMA1_SDMA_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_BASE 0x0969 +#define regSDMA1_SDMA_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_BASE_HI 0x096a +#define regSDMA1_SDMA_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR 0x096b +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_HI 0x096c +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR 0x096d +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_HI 0x096e +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO 0x096f +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI 0x0970 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_CNTL 0x0971 +#define regSDMA1_SDMA_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_RPTR 0x0972 +#define regSDMA1_SDMA_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_OFFSET 0x0973 +#define regSDMA1_SDMA_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_LO 0x0974 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_HI 0x0975 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_SIZE 0x0976 +#define regSDMA1_SDMA_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DOORBELL 0x0977 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_LOG 0x0978 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_OFFSET 0x0979 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_LO 0x097a +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_HI 0x097b +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_SCHEDULE_CNTL 0x097c +#define regSDMA1_SDMA_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_SUB_REMAIN 0x097d +#define regSDMA1_SDMA_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_PREEMPT 0x097e +#define regSDMA1_SDMA_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG 0x097f +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x0980 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x0981 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_AQL_CNTL 0x0982 +#define regSDMA1_SDMA_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE 0x0983 +#define regSDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS 0x0986 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_CNTL 0x0987 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA0 0x0988 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA1 0x0989 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA2 0x098a +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA3 0x098b +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA4 0x098c +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA5 0x098d +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA6 0x098e +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA7 0x098f +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA8 0x0990 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA9 0x0991 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA10 0x0992 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_LO 0x0993 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_HI 0x0994 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD 0x0995 +#define regSDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO 0x0996 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI 0x0997 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MQD_CONTROL 0x0998 +#define regSDMA1_SDMA_QUEUE6_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_STATUS 0x0999 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG1 0x099a +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG2 0x099b +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_CNTL 0x09a4 +#define regSDMA1_SDMA_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_BASE 0x09a5 +#define regSDMA1_SDMA_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_BASE_HI 0x09a6 +#define regSDMA1_SDMA_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR 0x09a7 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_HI 0x09a8 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR 0x09a9 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_HI 0x09aa +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO 0x09ab +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI 0x09ac +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_CNTL 0x09ad +#define regSDMA1_SDMA_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_RPTR 0x09ae +#define regSDMA1_SDMA_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_OFFSET 0x09af +#define regSDMA1_SDMA_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_LO 0x09b0 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_HI 0x09b1 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_SIZE 0x09b2 +#define regSDMA1_SDMA_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DOORBELL 0x09b3 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_LOG 0x09b4 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_OFFSET 0x09b5 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_LO 0x09b6 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_HI 0x09b7 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_SCHEDULE_CNTL 0x09b8 +#define regSDMA1_SDMA_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_SUB_REMAIN 0x09b9 +#define regSDMA1_SDMA_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_PREEMPT 0x09ba +#define regSDMA1_SDMA_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG 0x09bb +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x09bc +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x09bd +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_AQL_CNTL 0x09be +#define regSDMA1_SDMA_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE 0x09bf +#define regSDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS 0x09c2 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_CNTL 0x09c3 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA0 0x09c4 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA1 0x09c5 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA2 0x09c6 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA3 0x09c7 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA4 0x09c8 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA5 0x09c9 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA6 0x09ca +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA7 0x09cb +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA8 0x09cc +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA9 0x09cd +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA10 0x09ce +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_LO 0x09cf +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_HI 0x09d0 +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD 0x09d1 +#define regSDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO 0x09d2 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI 0x09d3 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MQD_CONTROL 0x09d4 +#define regSDMA1_SDMA_QUEUE7_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_STATUS 0x09d5 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG1 0x09d6 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG2 0x09d7 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_CNTL 0x09e0 +#define regSDMA1_SDMA_QUEUE8_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_BASE 0x09e1 +#define regSDMA1_SDMA_QUEUE8_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_BASE_HI 0x09e2 +#define regSDMA1_SDMA_QUEUE8_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR 0x09e3 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_HI 0x09e4 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR 0x09e5 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_HI 0x09e6 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO 0x09e7 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI 0x09e8 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_CNTL 0x09e9 +#define regSDMA1_SDMA_QUEUE8_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_RPTR 0x09ea +#define regSDMA1_SDMA_QUEUE8_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_OFFSET 0x09eb +#define regSDMA1_SDMA_QUEUE8_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_BASE_LO 0x09ec +#define regSDMA1_SDMA_QUEUE8_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_BASE_HI 0x09ed +#define regSDMA1_SDMA_QUEUE8_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_SIZE 0x09ee +#define regSDMA1_SDMA_QUEUE8_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL 0x09ef +#define regSDMA1_SDMA_QUEUE8_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_LOG 0x09f0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_OFFSET 0x09f1 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_LO 0x09f2 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_HI 0x09f3 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_SCHEDULE_CNTL 0x09f4 +#define regSDMA1_SDMA_QUEUE8_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_SUB_REMAIN 0x09f5 +#define regSDMA1_SDMA_QUEUE8_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_PREEMPT 0x09f6 +#define regSDMA1_SDMA_QUEUE8_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG 0x09f7 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO 0x09f8 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI 0x09f9 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_AQL_CNTL 0x09fa +#define regSDMA1_SDMA_QUEUE8_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE 0x09fb +#define regSDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS 0x09fe +#define regSDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_CNTL 0x09ff +#define regSDMA1_SDMA_QUEUE8_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA0 0x0a00 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA1 0x0a01 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA2 0x0a02 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA3 0x0a03 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA4 0x0a04 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA5 0x0a05 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA6 0x0a06 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA7 0x0a07 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA8 0x0a08 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA9 0x0a09 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA10 0x0a0a +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_LO 0x0a0b +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_HI 0x0a0c +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD 0x0a0d +#define regSDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO 0x0a0e +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI 0x0a0f +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MQD_CONTROL 0x0a10 +#define regSDMA1_SDMA_QUEUE8_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CONTEXT_STATUS 0x0a11 +#define regSDMA1_SDMA_QUEUE8_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG1 0x0a12 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG2 0x0a13 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_CNTL 0x0a1c +#define regSDMA1_SDMA_QUEUE9_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_BASE 0x0a1d +#define regSDMA1_SDMA_QUEUE9_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_BASE_HI 0x0a1e +#define regSDMA1_SDMA_QUEUE9_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR 0x0a1f +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_HI 0x0a20 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR 0x0a21 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_HI 0x0a22 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO 0x0a23 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI 0x0a24 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_CNTL 0x0a25 +#define regSDMA1_SDMA_QUEUE9_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_RPTR 0x0a26 +#define regSDMA1_SDMA_QUEUE9_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_OFFSET 0x0a27 +#define regSDMA1_SDMA_QUEUE9_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_LO 0x0a28 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_HI 0x0a29 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_SIZE 0x0a2a +#define regSDMA1_SDMA_QUEUE9_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DOORBELL 0x0a2b +#define regSDMA1_SDMA_QUEUE9_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DOORBELL_LOG 0x0a2c +#define regSDMA1_SDMA_QUEUE9_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DOORBELL_OFFSET 0x0a2d +#define regSDMA1_SDMA_QUEUE9_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_LO 0x0a2e +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_HI 0x0a2f +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_SCHEDULE_CNTL 0x0a30 +#define regSDMA1_SDMA_QUEUE9_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_SUB_REMAIN 0x0a31 +#define regSDMA1_SDMA_QUEUE9_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_PREEMPT 0x0a32 +#define regSDMA1_SDMA_QUEUE9_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG 0x0a33 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO 0x0a34 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI 0x0a35 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_AQL_CNTL 0x0a36 +#define regSDMA1_SDMA_QUEUE9_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE 0x0a37 +#define regSDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS 0x0a3a +#define regSDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_CNTL 0x0a3b +#define regSDMA1_SDMA_QUEUE9_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA0 0x0a3c +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA1 0x0a3d +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA2 0x0a3e +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA3 0x0a3f +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA4 0x0a40 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA5 0x0a41 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA6 0x0a42 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA7 0x0a43 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA8 0x0a44 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA9 0x0a45 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA10 0x0a46 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_LO 0x0a47 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_HI 0x0a48 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD 0x0a49 +#define regSDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO 0x0a4a +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI 0x0a4b +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MQD_CONTROL 0x0a4c +#define regSDMA1_SDMA_QUEUE9_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CONTEXT_STATUS 0x0a4d +#define regSDMA1_SDMA_QUEUE9_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG1 0x0a4e +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG2 0x0a4f +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG2_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec:1 +// base address: 0x3e2c0 +#define regSDMA1_SDMA_VM_CTX_LO 0x58b0 +#define regSDMA1_SDMA_VM_CTX_LO_BASE_IDX 1 +#define regSDMA1_SDMA_VM_CTX_HI 0x58b1 +#define regSDMA1_SDMA_VM_CTX_HI_BASE_IDX 1 +#define regSDMA1_SDMA_ACTIVE_FCN_ID 0x58b2 +#define regSDMA1_SDMA_ACTIVE_FCN_ID_BASE_IDX 1 +#define regSDMA1_SDMA_VM_CTX_CNTL 0x58b3 +#define regSDMA1_SDMA_VM_CTX_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_VIRT_RESET_REQ 0x58b4 +#define regSDMA1_SDMA_VIRT_RESET_REQ_BASE_IDX 1 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE0 0x58b5 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE1 0x58b6 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE2 0x58b7 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE0 0x58b8 +#define regSDMA1_SDMA_PUB_REG_TYPE0_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE1 0x58b9 +#define regSDMA1_SDMA_PUB_REG_TYPE1_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE2 0x58ba +#define regSDMA1_SDMA_PUB_REG_TYPE2_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE3 0x58bb +#define regSDMA1_SDMA_PUB_REG_TYPE3_BASE_IDX 1 +#define regSDMA1_SDMA_VM_CNTL 0x58bd +#define regSDMA1_SDMA_VM_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_MCU_CNTL 0x58be +#define regSDMA1_SDMA_MCU_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_IC_BASE_LO 0x58ca +#define regSDMA1_SDMA_IC_BASE_LO_BASE_IDX 1 +#define regSDMA1_SDMA_IC_BASE_HI 0x58cb +#define regSDMA1_SDMA_IC_BASE_HI_BASE_IDX 1 +#define regSDMA1_SDMA_IC_BASE_CNTL 0x58cc +#define regSDMA1_SDMA_IC_BASE_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_IC_OP_CNTL 0x58cd +#define regSDMA1_SDMA_IC_OP_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_IC_CNTL 0x58cf +#define regSDMA1_SDMA_IC_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec:1 +// base address: 0x3f340 +#define regSDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET 0x5d14 +#define regSDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec:1 +// base address: 0x378e0 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG 0x3e38 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG 0x3e39 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG 0x3e3a +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e3b +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_MISC_CNTL 0x3e3c +#define regSDMA1_SDMA_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT 0x3e3d +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT1 0x3e3e +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT 0x3e3f +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT1 0x3e40 +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT 0x3e41 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT1 0x3e42 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT 0x3e43 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT1 0x3e44 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT 0x3e45 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT1 0x3e46 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT 0x3e47 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT1 0x3e48 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec:1 +// base address: 0x359e0 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_LO 0x3678 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_HI 0x3679 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_LO 0x367a +#define regSDMA1_SDMA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_HI 0x367b +#define regSDMA1_SDMA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_LO 0x367c +#define regSDMA1_SDMA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_HI 0x367d +#define regSDMA1_SDMA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_LO 0x367e +#define regSDMA1_SDMA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_HI 0x367f +#define regSDMA1_SDMA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_LO 0x3680 +#define regSDMA1_SDMA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_HI 0x3681 +#define regSDMA1_SDMA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_LO 0x3682 +#define regSDMA1_SDMA_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_HI 0x3683 +#define regSDMA1_SDMA_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_LO 0x3684 +#define regSDMA1_SDMA_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_HI 0x3685 +#define regSDMA1_SDMA_PERFCOUNTER5_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec:1 +// base address: 0x3c434 +#define regSDMA1_GFX_ICG_SDMA_CTRL 0x510d +#define regSDMA1_GFX_ICG_SDMA_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbmdec +// base address: 0x8000 +#define regGRBM_CNTL 0x0da0 +#define regGRBM_CNTL_BASE_IDX 0 +#define regGRBM_SKEW_CNTL 0x0da1 +#define regGRBM_SKEW_CNTL_BASE_IDX 0 +#define regGRBM_STATUS2 0x0da2 +#define regGRBM_STATUS2_BASE_IDX 0 +#define regGRBM_PWR_CNTL 0x0da3 +#define regGRBM_PWR_CNTL_BASE_IDX 0 +#define regGRBM_STATUS 0x0da4 +#define regGRBM_STATUS_BASE_IDX 0 +#define regGRBM_STATUS_SE0 0x0da5 +#define regGRBM_STATUS_SE0_BASE_IDX 0 +#define regGRBM_STATUS_SE1 0x0da6 +#define regGRBM_STATUS_SE1_BASE_IDX 0 +#define regGRBM_STATUS3 0x0da7 +#define regGRBM_STATUS3_BASE_IDX 0 +#define regGRBM_SOFT_RESET 0x0da8 +#define regGRBM_SOFT_RESET_BASE_IDX 0 +#define regGRBM_FAO_CNT 0x0dab +#define regGRBM_FAO_CNT_BASE_IDX 0 +#define regGRBM_GFX_CLKEN_CNTL 0x0dac +#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBM_WAIT_IDLE_CLOCKS 0x0dad +#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define regGRBM_READ_ERROR 0x0db6 +#define regGRBM_READ_ERROR_BASE_IDX 0 +#define regGRBM_READ_ERROR2 0x0db7 +#define regGRBM_READ_ERROR2_BASE_IDX 0 +#define regGRBM_INT_CNTL 0x0db8 +#define regGRBM_INT_CNTL_BASE_IDX 0 +#define regGRBM_TRAP_OP 0x0db9 +#define regGRBM_TRAP_OP_BASE_IDX 0 +#define regGRBM_TRAP_ADDR 0x0dba +#define regGRBM_TRAP_ADDR_BASE_IDX 0 +#define regGRBM_TRAP_ADDR_MSK 0x0dbb +#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define regGRBM_TRAP_WD 0x0dbc +#define regGRBM_TRAP_WD_BASE_IDX 0 +#define regGRBM_TRAP_WD_MSK 0x0dbd +#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define regGRBM_DSM_BYPASS 0x0dbe +#define regGRBM_DSM_BYPASS_BASE_IDX 0 +#define regGRBM_WRITE_ERROR 0x0dbf +#define regGRBM_WRITE_ERROR_BASE_IDX 0 +#define regGRBM_IOV_ERROR_FIFO 0x0dc0 +#define regGRBM_IOV_ERROR_FIFO_BASE_IDX 0 +#define regGRBM_CHIP_REVISION 0x0dc1 +#define regGRBM_CHIP_REVISION_BASE_IDX 0 +#define regGRBM_RSMU_CFG 0x0dc3 +#define regGRBM_RSMU_CFG_BASE_IDX 0 +#define regGRBM_IH_CREDIT 0x0dc4 +#define regGRBM_IH_CREDIT_BASE_IDX 0 +#define regGRBM_PWR_CNTL2 0x0dc5 +#define regGRBM_PWR_CNTL2_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 +#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 +#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define regGRBM_RSMU_READ_ERROR 0x0dc8 +#define regGRBM_RSMU_READ_ERROR_BASE_IDX 0 +#define regGRBM_INVALID_PIPE 0x0dc9 +#define regGRBM_INVALID_PIPE_BASE_IDX 0 +#define regGRBM_FENCE_RANGE0 0x0dca +#define regGRBM_FENCE_RANGE0_BASE_IDX 0 +#define regGRBM_FENCE_RANGE1 0x0dcb +#define regGRBM_FENCE_RANGE1_BASE_IDX 0 +#define regGRBM_CHICKEN_BITS0 0x0dcc +#define regGRBM_CHICKEN_BITS0_BASE_IDX 0 +#define regGRBM_CHICKEN_BITS1 0x0dcd +#define regGRBM_CHICKEN_BITS1_BASE_IDX 0 +#define regCC_GC_FULL_SA_UNIT_DISABLE 0x0dd9 +#define regCC_GC_FULL_SA_UNIT_DISABLE_BASE_IDX 0 +#define regGRBM_SCRATCH_REG0 0x0de0 +#define regGRBM_SCRATCH_REG0_BASE_IDX 0 +#define regGRBM_SCRATCH_REG1 0x0de1 +#define regGRBM_SCRATCH_REG1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG2 0x0de2 +#define regGRBM_SCRATCH_REG2_BASE_IDX 0 +#define regGRBM_SCRATCH_REG3 0x0de3 +#define regGRBM_SCRATCH_REG3_BASE_IDX 0 +#define regGRBM_SCRATCH_REG4 0x0de4 +#define regGRBM_SCRATCH_REG4_BASE_IDX 0 +#define regGRBM_SCRATCH_REG5 0x0de5 +#define regGRBM_SCRATCH_REG5_BASE_IDX 0 +#define regGRBM_SCRATCH_REG6 0x0de6 +#define regGRBM_SCRATCH_REG6_BASE_IDX 0 +#define regGRBM_SCRATCH_REG7 0x0de7 +#define regGRBM_SCRATCH_REG7_BASE_IDX 0 +#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 +#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 +#define regGRBM_INTF_CNTL 0x0df6 +#define regGRBM_INTF_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpdec +// base address: 0x8200 +#define regCP_CPC_DEBUG_CNTL 0x0e20 +#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPC_DEBUG_DATA 0x0e21 +#define regCP_CPC_DEBUG_DATA_BASE_IDX 0 +#define regCP_CPF_DEBUG_CNTL 0x0e22 +#define regCP_CPF_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPF_DEBUG_DATA 0x0e23 +#define regCP_CPF_DEBUG_DATA_BASE_IDX 0 +#define regCP_CPC_STATUS 0x0e24 +#define regCP_CPC_STATUS_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT 0x0e25 +#define regCP_CPC_BUSY_STAT_BASE_IDX 0 +#define regCP_CPC_STALLED_STAT1 0x0e26 +#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPF_STATUS 0x0e27 +#define regCP_CPF_STATUS_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT 0x0e28 +#define regCP_CPF_BUSY_STAT_BASE_IDX 0 +#define regCP_CPF_STALLED_STAT1 0x0e29 +#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT2 0x0e2a +#define regCP_CPC_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_GRBM_FREE_COUNT 0x0e2b +#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c +#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR_HI 0x0e2d +#define regCP_CPC_PRIV_VIOLATION_ADDR_HI_BASE_IDX 0 +#define regCP_MEC_ME1_HEADER_DUMP 0x0e2e +#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define regCP_CPC_SCRATCH_INDEX 0x0e30 +#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define regCP_CPC_SCRATCH_DATA 0x0e31 +#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define regCP_CPF_GRBM_FREE_COUNT 0x0e32 +#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT2 0x0e33 +#define regCP_CPF_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_HALT_HYST_COUNT 0x0e47 +#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define regCP_STALLED_STAT3 0x0f3c +#define regCP_STALLED_STAT3_BASE_IDX 0 +#define regCP_STALLED_STAT1 0x0f3d +#define regCP_STALLED_STAT1_BASE_IDX 0 +#define regCP_STALLED_STAT2 0x0f3e +#define regCP_STALLED_STAT2_BASE_IDX 0 +#define regCP_BUSY_STAT 0x0f3f +#define regCP_BUSY_STAT_BASE_IDX 0 +#define regCP_STAT 0x0f40 +#define regCP_STAT_BASE_IDX 0 +#define regCP_ME_HEADER_DUMP 0x0f41 +#define regCP_ME_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_HEADER_DUMP 0x0f42 +#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define regCP_GRBM_FREE_COUNT 0x0f43 +#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_PFP_INSTR_PNTR 0x0f45 +#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define regCP_ME_INSTR_PNTR 0x0f46 +#define regCP_ME_INSTR_PNTR_BASE_IDX 0 +#define regCP_CSF_STAT 0x0f54 +#define regCP_CSF_STAT_BASE_IDX 0 +#define regCP_CNTX_STAT 0x0f58 +#define regCP_CNTX_STAT_BASE_IDX 0 +#define regCP_ME_PREEMPTION 0x0f59 +#define regCP_ME_PREEMPTION_BASE_IDX 0 +#define regCP_RB0_RPTR 0x0f60 +#define regCP_RB0_RPTR_BASE_IDX 0 +#define regCP_RB_RPTR 0x0f60 +#define regCP_RB_RPTR_BASE_IDX 0 +#define regCP_RB_WPTR_DELAY 0x0f61 +#define regCP_RB_WPTR_DELAY_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_CNTL 0x0f62 +#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_ROQ1_THRESHOLDS 0x0f75 +#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ2_THRESHOLDS 0x0f76 +#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define regCP_STQ_THRESHOLDS 0x0f77 +#define regCP_STQ_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_THRESHOLDS 0x0f79 +#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_AVAIL 0x0f7a +#define regCP_ROQ_AVAIL_BASE_IDX 0 +#define regCP_STQ_AVAIL 0x0f7b +#define regCP_STQ_AVAIL_BASE_IDX 0 +#define regCP_ROQ2_AVAIL 0x0f7c +#define regCP_ROQ2_AVAIL_BASE_IDX 0 +#define regCP_MEQ_AVAIL 0x0f7d +#define regCP_MEQ_AVAIL_BASE_IDX 0 +#define regCP_CMD_INDEX 0x0f7e +#define regCP_CMD_INDEX_BASE_IDX 0 +#define regCP_CMD_DATA 0x0f7f +#define regCP_CMD_DATA_BASE_IDX 0 +#define regCP_ROQ_RB_STAT 0x0f80 +#define regCP_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_ROQ_IB1_STAT 0x0f81 +#define regCP_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_ROQ_IB2_STAT 0x0f82 +#define regCP_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_STQ_STAT 0x0f83 +#define regCP_STQ_STAT_BASE_IDX 0 +#define regCP_STQ_WR_STAT 0x0f84 +#define regCP_STQ_WR_STAT_BASE_IDX 0 +#define regCP_MEQ_STAT 0x0f85 +#define regCP_MEQ_STAT_BASE_IDX 0 +#define regCP_ROQ3_THRESHOLDS 0x0f8c +#define regCP_ROQ3_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_DB_STAT 0x0f8d +#define regCP_ROQ_DB_STAT_BASE_IDX 0 +#define regCP_INT_STAT_DEBUG 0x0f97 +#define regCP_INT_STAT_DEBUG_BASE_IDX 0 +#define regCP_DEBUG_CNTL 0x0f98 +#define regCP_DEBUG_CNTL_BASE_IDX 0 +#define regCP_DEBUG_DATA 0x0f99 +#define regCP_DEBUG_DATA_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR 0x0f9a +#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR_HI 0x0f9b +#define regCP_PRIV_VIOLATION_ADDR_HI_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_padec +// base address: 0x8800 +#define regVGT_DMA_DATA_FIFO_DEPTH 0x0fcd +#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DMA_REQ_FIFO_DEPTH 0x0fce +#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf +#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_MC_LAT_CNTL 0x0fd6 +#define regVGT_MC_LAT_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS_2 0x0fd7 +#define regIA_UTCL1_STATUS_2_BASE_IDX 0 +#define regGE_WD_CNTL_STATUS 0x0fdf +#define regGE_WD_CNTL_STATUS_BASE_IDX 0 +#define regWD_UTCL1_CNTL 0x0fe3 +#define regWD_UTCL1_CNTL_BASE_IDX 0 +#define regWD_UTCL1_STATUS 0x0fe4 +#define regWD_UTCL1_STATUS_BASE_IDX 0 +#define regIA_UTCL1_CNTL 0x0fe6 +#define regIA_UTCL1_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS 0x0fe7 +#define regIA_UTCL1_STATUS_BASE_IDX 0 +#define regCC_GC_SA_UNIT_DISABLE 0x0fe9 +#define regCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 +#define regGE_FED_STATUS 0x0fea +#define regGE_FED_STATUS_BASE_IDX 0 +#define regGE_PRIV_CONTROL 0x1004 +#define regGE_PRIV_CONTROL_BASE_IDX 0 +#define regGE_STATUS 0x1005 +#define regGE_STATUS_BASE_IDX 0 +#define regVGT_GS_MAX_WAVE_ID 0x1009 +#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define regGFX_PIPE_CONTROL 0x100d +#define regGFX_PIPE_CONTROL_BASE_IDX 0 +#define regVGT_RESET_DEBUG 0x1014 +#define regVGT_RESET_DEBUG_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_shdec +// base address: 0xb000 +#define regCOMPUTE_DISPATCH_INITIATOR 0x1ba0 +#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define regCOMPUTE_DIM_X 0x1ba1 +#define regCOMPUTE_DIM_X_BASE_IDX 0 +#define regCOMPUTE_DIM_Y 0x1ba2 +#define regCOMPUTE_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_DIM_Z 0x1ba3 +#define regCOMPUTE_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_START_X 0x1ba4 +#define regCOMPUTE_START_X_BASE_IDX 0 +#define regCOMPUTE_START_Y 0x1ba5 +#define regCOMPUTE_START_Y_BASE_IDX 0 +#define regCOMPUTE_START_Z 0x1ba6 +#define regCOMPUTE_START_Z_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_X 0x1ba7 +#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Y 0x1ba8 +#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Z 0x1ba9 +#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define regCOMPUTE_PIPELINESTAT_ENABLE 0x1baa +#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PERFCOUNT_ENABLE 0x1bab +#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PGM_LO 0x1bac +#define regCOMPUTE_PGM_LO_BASE_IDX 0 +#define regCOMPUTE_PGM_HI 0x1bad +#define regCOMPUTE_PGM_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC1 0x1bb2 +#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC2 0x1bb3 +#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define regCOMPUTE_VMID 0x1bb4 +#define regCOMPUTE_VMID_BASE_IDX 0 +#define regCOMPUTE_RESOURCE_LIMITS 0x1bb5 +#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define regCOMPUTE_TMPRING_SIZE 0x1bb6 +#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define regCOMPUTE_RESTART_X 0x1bb7 +#define regCOMPUTE_RESTART_X_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y 0x1bb8 +#define regCOMPUTE_RESTART_Y_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z 0x1bb9 +#define regCOMPUTE_RESTART_Z_BASE_IDX 0 +#define regCOMPUTE_THREAD_TRACE_ENABLE 0x1bba +#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define regCOMPUTE_MISC_RESERVED 0x1bbb +#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_ID 0x1bbc +#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define regCOMPUTE_THREADGROUP_ID 0x1bbd +#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define regCOMPUTE_REQ_CTRL 0x1bbe +#define regCOMPUTE_REQ_CTRL_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_0 0x1bbf +#define regCOMPUTE_USER_ACCUM_0_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_1 0x1bc0 +#define regCOMPUTE_USER_ACCUM_1_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_2 0x1bc1 +#define regCOMPUTE_USER_ACCUM_2_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_3 0x1bc2 +#define regCOMPUTE_USER_ACCUM_3_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC3 0x1bc3 +#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 +#define regCOMPUTE_DDID_INDEX 0x1bc4 +#define regCOMPUTE_DDID_INDEX_BASE_IDX 0 +#define regCOMPUTE_SHADER_CHKSUM 0x1bc5 +#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INTERLEAVE 0x1bc6 +#define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 0 +#define regCOMPUTE_CURRENT_LOGICAL_XCC_ID 0x1bc7 +#define regCOMPUTE_CURRENT_LOGICAL_XCC_ID_BASE_IDX 0 +#define regCOMPUTE_RESTART_CG_TG_ID 0x1bc8 +#define regCOMPUTE_RESTART_CG_TG_ID_BASE_IDX 0 +#define regCOMPUTE_TG_CHUNK_SIZE 0x1bc9 +#define regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX 0 +#define regCOMPUTE_RESTORE_TG_CHUNK_SIZE 0x1bca +#define regCOMPUTE_RESTORE_TG_CHUNK_SIZE_BASE_IDX 0 +#define regCOMPUTE_SPARE_1 0x1bcb +#define regCOMPUTE_SPARE_1_BASE_IDX 0 +#define regCOMPUTE_SPARE_2 0x1bcc +#define regCOMPUTE_SPARE_2_BASE_IDX 0 +#define regCOMPUTE_PRESCALED_DIM_X 0x1bcd +#define regCOMPUTE_PRESCALED_DIM_X_BASE_IDX 0 +#define regCOMPUTE_PRESCALED_DIM_Y 0x1bce +#define regCOMPUTE_PRESCALED_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_PRESCALED_DIM_Z 0x1bcf +#define regCOMPUTE_PRESCALED_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE0 0x1bd0 +#define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bd0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE1 0x1bd1 +#define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bd1 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE2 0x1bd2 +#define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bd2 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE3 0x1bd3 +#define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bd3 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x1bd4 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x1bd5 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x1bd6 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x1bd7 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE8 0x1bd8 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_0 0x1be0 +#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_1 0x1be1 +#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_2 0x1be2 +#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_3 0x1be3 +#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_4 0x1be4 +#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_5 0x1be5 +#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_6 0x1be6 +#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_7 0x1be7 +#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_8 0x1be8 +#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_9 0x1be9 +#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_10 0x1bea +#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_11 0x1beb +#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_12 0x1bec +#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_13 0x1bed +#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_14 0x1bee +#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_15 0x1bef +#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_16 0x1bf0 +#define regCOMPUTE_USER_DATA_16_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_17 0x1bf1 +#define regCOMPUTE_USER_DATA_17_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_18 0x1bf2 +#define regCOMPUTE_USER_DATA_18_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_19 0x1bf3 +#define regCOMPUTE_USER_DATA_19_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_20 0x1bf4 +#define regCOMPUTE_USER_DATA_20_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_21 0x1bf5 +#define regCOMPUTE_USER_DATA_21_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_22 0x1bf6 +#define regCOMPUTE_USER_DATA_22_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_23 0x1bf7 +#define regCOMPUTE_USER_DATA_23_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_24 0x1bf8 +#define regCOMPUTE_USER_DATA_24_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_25 0x1bf9 +#define regCOMPUTE_USER_DATA_25_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_26 0x1bfa +#define regCOMPUTE_USER_DATA_26_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_27 0x1bfb +#define regCOMPUTE_USER_DATA_27_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_28 0x1bfc +#define regCOMPUTE_USER_DATA_28_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_29 0x1bfd +#define regCOMPUTE_USER_DATA_29_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_30 0x1bfe +#define regCOMPUTE_USER_DATA_30_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_31 0x1bff +#define regCOMPUTE_USER_DATA_31_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH 0x1c0d +#define regCOMPUTE_RELAUNCH_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH_STATE_PAYLOAD 0x1c0d +#define regCOMPUTE_RELAUNCH_STATE_PAYLOAD_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1c0e +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1c0f +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH2 0x1c10 +#define regCOMPUTE_RELAUNCH2_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH2_STATE_PAYLOAD 0x1c10 +#define regCOMPUTE_RELAUNCH2_STATE_PAYLOAD_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_TUNNEL 0x1c1d +#define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_END 0x1c1e +#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 +#define regCOMPUTE_NOWHERE 0x1c1f +#define regCOMPUTE_NOWHERE_BASE_IDX 0 +#define regSH_RESERVED_REG0 0x1c20 +#define regSH_RESERVED_REG0_BASE_IDX 0 +#define regSH_RESERVED_REG1 0x1c21 +#define regSH_RESERVED_REG1_BASE_IDX 0 +#define regCOMPUTE_PREALLOC_CR_DB_BUFFER_SIZE 0x1c22 +#define regCOMPUTE_PREALLOC_CR_DB_BUFFER_SIZE_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gccacdec +// base address: 0x2eb40 +#define regGC_CAC_CTRL_1 0x1ad0 +#define regGC_CAC_CTRL_1_BASE_IDX 1 +#define regGC_CAC_CTRL_2 0x1ad1 +#define regGC_CAC_CTRL_2_BASE_IDX 1 +#define regGC_CAC_AGGR_LOWER 0x1ad2 +#define regGC_CAC_AGGR_LOWER_BASE_IDX 1 +#define regGC_CAC_AGGR_UPPER 0x1ad3 +#define regGC_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE0_CAC_AGGR_LOWER 0x1ad4 +#define regSE0_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE0_CAC_AGGR_UPPER 0x1ad5 +#define regSE0_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE1_CAC_AGGR_LOWER 0x1ad6 +#define regSE1_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE1_CAC_AGGR_UPPER 0x1ad7 +#define regSE1_CAC_AGGR_UPPER_BASE_IDX 1 +#define regGC_CAC_AGGR_GFXCLK_CYCLE 0x1ae6 +#define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE 0x1ae7 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE 0x1ae8 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regGC_CAC_OVR_VAL_LOWER 0x1af0 +#define regGC_CAC_OVR_VAL_LOWER_BASE_IDX 1 +#define regGC_CAC_OVR_VAL_UPPER 0x1af1 +#define regGC_CAC_OVR_VAL_UPPER_BASE_IDX 1 +#define regGC_EDC_CTRL 0x1af4 +#define regGC_EDC_CTRL_BASE_IDX 1 +#define regGC_EDC_STRETCH_CTRL 0x1af5 +#define regGC_EDC_STRETCH_CTRL_BASE_IDX 1 +#define regGC_EDC_THRESHOLD_LO 0x1af6 +#define regGC_EDC_THRESHOLD_LO_BASE_IDX 1 +#define regGC_EDC_THRESHOLD_HI 0x1af7 +#define regGC_EDC_THRESHOLD_HI_BASE_IDX 1 +#define regGC_EDC_STRETCH_THRESHOLD_LO 0x1af8 +#define regGC_EDC_STRETCH_THRESHOLD_LO_BASE_IDX 1 +#define regGC_EDC_STRETCH_THRESHOLD_HI 0x1af9 +#define regGC_EDC_STRETCH_THRESHOLD_HI_BASE_IDX 1 +#define regEDC_HYSTERESIS_CNTL 0x1afa +#define regEDC_HYSTERESIS_CNTL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL 0x1afb +#define regGC_THROTTLE_CTRL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL1 0x1afc +#define regGC_THROTTLE_CTRL1_BASE_IDX 1 +#define regGC_THROTTLE_CTRL2 0x1afd +#define regGC_THROTTLE_CTRL2_BASE_IDX 1 +#define regEDC_STALL_PATTERN_CTRL 0x1afe +#define regEDC_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPCC_STALL_PATTERN_CTRL 0x1aff +#define regPCC_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_CTRL 0x1b00 +#define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regEDC_STALL_PATTERN_1_2 0x1b01 +#define regEDC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regEDC_STALL_PATTERN_3_4 0x1b02 +#define regEDC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regEDC_STALL_PATTERN_5_6 0x1b03 +#define regEDC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regEDC_STALL_PATTERN_7 0x1b04 +#define regEDC_STALL_PATTERN_7_BASE_IDX 1 +#define regPCC_STALL_PATTERN_1_2 0x1b05 +#define regPCC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPCC_STALL_PATTERN_3_4 0x1b06 +#define regPCC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPCC_STALL_PATTERN_5_6 0x1b07 +#define regPCC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPCC_STALL_PATTERN_7 0x1b08 +#define regPCC_STALL_PATTERN_7_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_1_2 0x1b09 +#define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_3_4 0x1b0a +#define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_5_6 0x1b0b +#define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_7 0x1b0c +#define regPWRBRK_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_CTRL 0x1b0d +#define regDIDT_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_1_2 0x1b0e +#define regDIDT_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_3_4 0x1b0f +#define regDIDT_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_5_6 0x1b10 +#define regDIDT_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_7 0x1b11 +#define regDIDT_STALL_PATTERN_7_BASE_IDX 1 +#define regPCC_PWRBRK_HYSTERESIS_CTRL 0x1b12 +#define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX 1 +#define regEDC_STRETCH_PERF_COUNTER 0x1b13 +#define regEDC_STRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_UNSTRETCH_PERF_COUNTER 0x1b14 +#define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_STRETCH_NUM_PERF_COUNTER 0x1b15 +#define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX 1 +#define regGC_EDC_STATUS 0x1b16 +#define regGC_EDC_STATUS_BASE_IDX 1 +#define regGC_EDC_OVERFLOW 0x1b17 +#define regGC_EDC_OVERFLOW_BASE_IDX 1 +#define regGC_EDC_ROLLING_POWER_DELTA_LO 0x1b18 +#define regGC_EDC_ROLLING_POWER_DELTA_LO_BASE_IDX 1 +#define regGC_EDC_ROLLING_POWER_DELTA_HI 0x1b19 +#define regGC_EDC_ROLLING_POWER_DELTA_HI_BASE_IDX 1 +#define regGC_EDC_AVG_POWER_DELTA_LO 0x1b1a +#define regGC_EDC_AVG_POWER_DELTA_LO_BASE_IDX 1 +#define regGC_EDC_AVG_POWER_DELTA_HI 0x1b1b +#define regGC_EDC_AVG_POWER_DELTA_HI_BASE_IDX 1 +#define regGC_THROTTLE_STATUS 0x1b1c +#define regGC_THROTTLE_STATUS_BASE_IDX 1 +#define regEDC_PERF_COUNTER 0x1b1d +#define regEDC_PERF_COUNTER_BASE_IDX 1 +#define regPCC_PERF_COUNTER 0x1b1e +#define regPCC_PERF_COUNTER_BASE_IDX 1 +#define regPWRBRK_PERF_COUNTER 0x1b1f +#define regPWRBRK_PERF_COUNTER_BASE_IDX 1 +#define regEDC_HYSTERESIS_STAT 0x1b20 +#define regEDC_HYSTERESIS_STAT_BASE_IDX 1 +#define regDIDT_HYSTERESIS_STAT 0x1b21 +#define regDIDT_HYSTERESIS_STAT_BASE_IDX 1 +#define regDIDT_PERF_COUNTER 0x1b22 +#define regDIDT_PERF_COUNTER_BASE_IDX 1 +#define regGC_EDC_CLK_MONITOR_CTRL 0x1b23 +#define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX 1 +#define regGC_CAC_SOFT_CTRL 0x1b24 +#define regGC_CAC_SOFT_CTRL_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_0 0x1b30 +#define regGC_CAC_WEIGHT_CP_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_1 0x1b31 +#define regGC_CAC_WEIGHT_CP_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PMM_0 0x1b4b +#define regGC_CAC_WEIGHT_PMM_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_0 0x1b50 +#define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_1 0x1b51 +#define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_2 0x1b52 +#define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_3 0x1b53 +#define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_4 0x1b54 +#define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_5 0x1b55 +#define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_0 0x1b56 +#define regGC_CAC_WEIGHT_CHC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_1 0x1b57 +#define regGC_CAC_WEIGHT_CHC_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_RLC_0 0x1b5a +#define regGC_CAC_WEIGHT_RLC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GRBM_0 0x1b5e +#define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_6 0x1b76 +#define regGC_CAC_WEIGHT_SDMA_6_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_7 0x1b77 +#define regGC_CAC_WEIGHT_SDMA_7_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GLARB_0 0x1b78 +#define regGC_CAC_WEIGHT_GLARB_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GLARB_1 0x1b79 +#define regGC_CAC_WEIGHT_GLARB_1_BASE_IDX 1 +#define regXCD_TOTAL_CAC_AGGR_LOWER 0x1b7c +#define regXCD_TOTAL_CAC_AGGR_LOWER_BASE_IDX 1 +#define regXCD_TOTAL_CAC_AGGR_UPPER 0x1b7d +#define regXCD_TOTAL_CAC_AGGR_UPPER_BASE_IDX 1 +#define regGC_EDC_WEIGHTED_DATA_MULTIPLIER 0x1b7e +#define regGC_EDC_WEIGHTED_DATA_MULTIPLIER_BASE_IDX 1 +#define regGC_CAC_IND_INDEX 0x1b8e +#define regGC_CAC_IND_INDEX_BASE_IDX 1 +#define regGC_CAC_IND_DATA 0x1b8f +#define regGC_CAC_IND_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gc_ea_cpwd_gceadec +// base address: 0xa800 +#define regGC_EA_CPWD_VC_MAP 0x17a0 +#define regGC_EA_CPWD_VC_MAP_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_ARB_FINAL 0x17a1 +#define regGC_EA_CPWD_SDP_ARB_FINAL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_PRIORITY 0x17a2 +#define regGC_EA_CPWD_SDP_PRIORITY_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_CREDITS 0x17a3 +#define regGC_EA_CPWD_SDP_CREDITS_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_TAG_RESERVE0 0x17a4 +#define regGC_EA_CPWD_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_TAG_RESERVE1 0x17a5 +#define regGC_EA_CPWD_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_TAG_RESERVE2 0x17a6 +#define regGC_EA_CPWD_SDP_TAG_RESERVE2_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCC_RESERVE0 0x17a7 +#define regGC_EA_CPWD_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCC_RESERVE1 0x17a8 +#define regGC_EA_CPWD_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCD_RESERVE0 0x17a9 +#define regGC_EA_CPWD_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCD_RESERVE1 0x17aa +#define regGC_EA_CPWD_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_REQ_CNTL 0x17ab +#define regGC_EA_CPWD_SDP_REQ_CNTL_BASE_IDX 0 +#define regGC_EA_CPWD_MISC 0x17ac +#define regGC_EA_CPWD_MISC_BASE_IDX 0 +#define regGC_EA_CPWD_ERR_STATUS 0x17ad +#define regGC_EA_CPWD_ERR_STATUS_BASE_IDX 0 +#define regGC_EA_CPWD_MISC2 0x17ae +#define regGC_EA_CPWD_MISC2_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0 0x17af +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE 0x17b0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1 0x17b1 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE 0x17b2 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0 0x17b3 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE 0x17b4 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1 0x17b5 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE 0x17b6 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2 0x17b7 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE 0x17b8 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL 0x17b9 +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE 0x17ba +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_INVALID_OPCODE 0x17bb +#define regGC_EA_CPWD_INVALID_OPCODE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL 0x17bc +#define regGC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_POISON_ERR_LOG 0x17bd +#define regGC_EA_CPWD_SDP_POISON_ERR_LOG_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL 0x17be +#define regGC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_PARITY_ERR_LOG 0x17bf +#define regGC_EA_CPWD_SDP_PARITY_ERR_LOG_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_ENABLE 0x181f +#define regGC_EA_CPWD_SDP_ENABLE_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gcrdec +// base address: 0x9f80 +#define regGCR_PIO_CNTL 0x1580 +#define regGCR_PIO_CNTL_BASE_IDX 0 +#define regGCR_PIO_DATA 0x1581 +#define regGCR_PIO_DATA_BASE_IDX 0 +#define regGCR_NHTOE_CNTL 0x1584 +#define regGCR_NHTOE_CNTL_BASE_IDX 0 +#define regGCR_NHTOE_DATA 0x1585 +#define regGCR_NHTOE_DATA_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cppdec +// base address: 0xc080 +#define regCPC_INT_ADDR1 0x1dd1 +#define regCPC_INT_ADDR1_BASE_IDX 0 +#define regCP_CU_MASK_ADDR_LO 0x1dd2 +#define regCP_CU_MASK_ADDR_LO_BASE_IDX 0 +#define regCP_CU_MASK_ADDR_HI 0x1dd3 +#define regCP_CU_MASK_ADDR_HI_BASE_IDX 0 +#define regCP_CU_MASK_CNTL 0x1dd4 +#define regCP_CU_MASK_CNTL_BASE_IDX 0 +#define regCP_EOPQ_WAIT_TIME 0x1dd5 +#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define regCP_CPC_MGCG_SYNC_CNTL 0x1dd6 +#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define regCPC_INT_INFO 0x1dd7 +#define regCPC_INT_INFO_BASE_IDX 0 +#define regCP_VIRT_STATUS 0x1dd8 +#define regCP_VIRT_STATUS_BASE_IDX 0 +#define regCPC_INT_ADDR 0x1dd9 +#define regCPC_INT_ADDR_BASE_IDX 0 +#define regCPC_INT_PASID 0x1dda +#define regCPC_INT_PASID_BASE_IDX 0 +#define regCP_GFX_ERROR 0x1ddb +#define regCP_GFX_ERROR_BASE_IDX 0 +#define regCPG_UTCL1_CNTL 0x1ddc +#define regCPG_UTCL1_CNTL_BASE_IDX 0 +#define regCPC_UTCL1_CNTL 0x1ddd +#define regCPC_UTCL1_CNTL_BASE_IDX 0 +#define regCPF_UTCL1_CNTL 0x1dde +#define regCPF_UTCL1_CNTL_BASE_IDX 0 +#define regCP_AQL_SMM_STATUS 0x1ddf +#define regCP_AQL_SMM_STATUS_BASE_IDX 0 +#define regCP_RB0_BASE 0x1de0 +#define regCP_RB0_BASE_BASE_IDX 0 +#define regCP_RB_BASE 0x1de0 +#define regCP_RB_BASE_BASE_IDX 0 +#define regCP_RB0_CNTL 0x1de1 +#define regCP_RB0_CNTL_BASE_IDX 0 +#define regCP_RB_CNTL 0x1de1 +#define regCP_RB_CNTL_BASE_IDX 0 +#define regCP_RB_RPTR_WR 0x1de2 +#define regCP_RB_RPTR_WR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR 0x1de3 +#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR 0x1de3 +#define regCP_RB_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR_HI 0x1de4 +#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR_HI 0x1de4 +#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_BUFSZ_MASK 0x1de5 +#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_BUFSZ_MASK 0x1de5 +#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define regCP_ME3_INT_STAT_DEBUG 0x1de6 +#define regCP_ME3_INT_STAT_DEBUG_BASE_IDX 0 +#define regGC_PRIV_MODE 0x1de8 +#define regGC_PRIV_MODE_BASE_IDX 0 +#define regCP_INT_CNTL 0x1de9 +#define regCP_INT_CNTL_BASE_IDX 0 +#define regCP_INT_STATUS 0x1dea +#define regCP_INT_STATUS_BASE_IDX 0 +#define regCP_DEVICE_ID 0x1deb +#define regCP_DEVICE_ID_BASE_IDX 0 +#define regCP_ME0_PIPE_PRIORITY_CNTS 0x1dec +#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_RING_PRIORITY_CNTS 0x1dec +#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME0_PIPE0_PRIORITY 0x1ded +#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_RING0_PRIORITY 0x1ded +#define regCP_RING0_PRIORITY_BASE_IDX 0 +#define regCP_FATAL_ERROR 0x1df0 +#define regCP_FATAL_ERROR_BASE_IDX 0 +#define regCP_RB_VMID 0x1df1 +#define regCP_RB_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE0_VMID 0x1df2 +#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define regCP_RB0_WPTR 0x1df4 +#define regCP_RB0_WPTR_BASE_IDX 0 +#define regCP_RB_WPTR 0x1df4 +#define regCP_RB_WPTR_BASE_IDX 0 +#define regCP_RB0_WPTR_HI 0x1df5 +#define regCP_RB0_WPTR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_HI 0x1df5 +#define regCP_RB_WPTR_HI_BASE_IDX 0 +#define regCP_PROCESS_QUANTUM 0x1df9 +#define regCP_PROCESS_QUANTUM_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_LOWER 0x1dfa +#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_UPPER 0x1dfb +#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc +#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd +#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCPG_UTCL1_ERROR 0x1dfe +#define regCPG_UTCL1_ERROR_BASE_IDX 0 +#define regCPC_UTCL1_ERROR 0x1dff +#define regCPC_UTCL1_ERROR_BASE_IDX 0 +#define regCPF_FED_STATUS 0x1e05 +#define regCPF_FED_STATUS_BASE_IDX 0 +#define regCPC_FED_STATUS 0x1e06 +#define regCPC_FED_STATUS_BASE_IDX 0 +#define regCPG_FED_STATUS 0x1e07 +#define regCPG_FED_STATUS_BASE_IDX 0 +#define regCP_IB1_BUFFER_COUNT 0x1e08 +#define regCP_IB1_BUFFER_COUNT_BASE_IDX 0 +#define regCP_IB2_BUFFER_COUNT 0x1e09 +#define regCP_IB2_BUFFER_COUNT_BASE_IDX 0 +#define regCP_INT_CNTL_RING0 0x1e0a +#define regCP_INT_CNTL_RING0_BASE_IDX 0 +#define regCP_DEBUG_2 0x1e0c +#define regCP_DEBUG_2_BASE_IDX 0 +#define regCP_INT_STATUS_RING0 0x1e0d +#define regCP_INT_STATUS_RING0_BASE_IDX 0 +#define regCP_ME_F32_INTERRUPT 0x1e13 +#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PFP_F32_INTERRUPT 0x1e14 +#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC1_F32_INTERRUPT 0x1e16 +#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PWR_CNTL 0x1e18 +#define regCP_PWR_CNTL_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE 0x1e1a +#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b +#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define regGB_EDC_MODE 0x1e1e +#define regGB_EDC_MODE_BASE_IDX 0 +#define regCP_DEBUG 0x1e1f +#define regCP_DEBUG_BASE_IDX 0 +#define regCP_CPF_DEBUG 0x1e20 +#define regCP_CPF_DEBUG_BASE_IDX 0 +#define regCP_CPC_DEBUG 0x1e21 +#define regCP_CPC_DEBUG_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL 0x1e23 +#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL1 0x1e24 +#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_CNTL 0x1e25 +#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_CNTL 0x1e26 +#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_CNTL 0x1e27 +#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_CNTL 0x1e28 +#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_STATUS 0x1e2d +#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_STATUS 0x1e2e +#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_STATUS 0x1e2f +#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_STATUS 0x1e30 +#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_INT_STAT_DEBUG 0x1e35 +#define regCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 +#define regCP_GFX_QUEUE_INDEX 0x1e37 +#define regCP_GFX_QUEUE_INDEX_BASE_IDX 0 +#define regCC_GC_EDC_CONFIG 0x1e38 +#define regCC_GC_EDC_CONFIG_BASE_IDX 0 +#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 +#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME1_PIPE0_PRIORITY 0x1e3a +#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE1_PRIORITY 0x1e3b +#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE2_PRIORITY 0x1e3c +#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE3_PRIORITY 0x1e3d +#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START 0x1e44 +#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START 0x1e45 +#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC1_PRGRM_CNTR_START 0x1e46 +#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START 0x1e49 +#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START 0x1e4a +#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC1_INTR_ROUTINE_START 0x1e4b +#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_CONTEXT_CNTL 0x1e4d +#define regCP_CONTEXT_CNTL_BASE_IDX 0 +#define regCP_MAX_CONTEXT 0x1e4e +#define regCP_MAX_CONTEXT_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME1 0x1e4f +#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME2 0x1e50 +#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define regCP_RB0_BASE_HI 0x1e51 +#define regCP_RB0_BASE_HI_BASE_IDX 0 +#define regCP_VMID_RESET 0x1e53 +#define regCP_VMID_RESET_BASE_IDX 0 +#define regCPC_INT_CNTL 0x1e54 +#define regCPC_INT_CNTL_BASE_IDX 0 +#define regCPC_INT_STATUS 0x1e55 +#define regCPC_INT_STATUS_BASE_IDX 0 +#define regCP_VMID_PREEMPT 0x1e56 +#define regCP_VMID_PREEMPT_BASE_IDX 0 +#define regCPC_INT_CNTX_ID 0x1e57 +#define regCPC_INT_CNTX_ID_BASE_IDX 0 +#define regCP_PQ_STATUS 0x1e58 +#define regCP_PQ_STATUS_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START_HI 0x1e59 +#define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_MAX_DRAW_COUNT 0x1e5c +#define regCP_MAX_DRAW_COUNT_BASE_IDX 0 +#define regCP_VMID_STATUS 0x1e5f +#define regCP_VMID_STATUS_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 +#define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 +#define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 +#define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCPC_OS_PIPES 0x1e67 +#define regCPC_OS_PIPES_BASE_IDX 0 +#define regCP_SUSPEND_RESUME_REQ 0x1e68 +#define regCP_SUSPEND_RESUME_REQ_BASE_IDX 0 +#define regCP_SUSPEND_CNTL 0x1e69 +#define regCP_SUSPEND_CNTL_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME3 0x1e6a +#define regCP_IQ_WAIT_TIME3_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_LO 0x1e6b +#define regCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_LO 0x1e6b +#define regCP_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_HI 0x1e6c +#define regCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_HI 0x1e6c +#define regCP_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_DDID_CNTL 0x1e6d +#define regCPC_DDID_CNTL_BASE_IDX 0 +#define regCP_DDID_CNTL 0x1e6d +#define regCP_DDID_CNTL_BASE_IDX 0 +#define regCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e +#define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_GFX_DDID_WPTR 0x1e6f +#define regCP_GFX_DDID_WPTR_BASE_IDX 0 +#define regCP_GFX_DDID_RPTR 0x1e70 +#define regCP_GFX_DDID_RPTR_BASE_IDX 0 +#define regCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 +#define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_GFX_HPD_STATUS0 0x1e72 +#define regCP_GFX_HPD_STATUS0_BASE_IDX 0 +#define regCP_GFX_HPD_CONTROL0 0x1e73 +#define regCP_GFX_HPD_CONTROL0_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 +#define regCP_GFX_INDEX_MUTEX 0x1e78 +#define regCP_GFX_INDEX_MUTEX_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START_HI 0x1e79 +#define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START_HI 0x1e7a +#define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START_HI 0x1e7b +#define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR 0x1e7e +#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR_HI 0x1e7f +#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_ACTIVE 0x1e80 +#define regCP_GFX_HQD_ACTIVE_BASE_IDX 0 +#define regCP_GFX_HQD_VMID 0x1e81 +#define regCP_GFX_HQD_VMID_BASE_IDX 0 +#define regCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 +#define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_GFX_HQD_QUANTUM 0x1e85 +#define regCP_GFX_HQD_QUANTUM_BASE_IDX 0 +#define regCP_GFX_HQD_BASE 0x1e86 +#define regCP_GFX_HQD_BASE_BASE_IDX 0 +#define regCP_GFX_HQD_BASE_HI 0x1e87 +#define regCP_GFX_HQD_BASE_HI_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR 0x1e88 +#define regCP_GFX_HQD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR 0x1e89 +#define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a +#define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_LO 0x1e8b +#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_HI 0x1e8c +#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL 0x1e8d +#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_OFFSET 0x1e8e +#define regCP_GFX_HQD_OFFSET_BASE_IDX 0 +#define regCP_GFX_HQD_CNTL 0x1e8f +#define regCP_GFX_HQD_CNTL_BASE_IDX 0 +#define regCP_GFX_HQD_CSMD_RPTR 0x1e90 +#define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR 0x1e91 +#define regCP_GFX_HQD_WPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR_HI 0x1e92 +#define regCP_GFX_HQD_WPTR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 +#define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_GFX_HQD_MAPPED 0x1e94 +#define regCP_GFX_HQD_MAPPED_BASE_IDX 0 +#define regCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 +#define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_IQ_TIMER 0x1e96 +#define regCP_GFX_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_STATUS0 0x1e98 +#define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_CONTROL0 0x1e99 +#define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_GFX_MQD_CONTROL 0x1e9a +#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_CONTROL 0x1e9f +#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_STATUS 0x1ea0 +#define regCP_HQD_GFX_STATUS_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_LO 0x1ec0 +#define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_HI 0x1ec1 +#define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH0_MASK 0x1ec2 +#define regCP_DMA_WATCH0_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH0_CNTL 0x1ec3 +#define regCP_DMA_WATCH0_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_LO 0x1ec4 +#define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_HI 0x1ec5 +#define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH1_MASK 0x1ec6 +#define regCP_DMA_WATCH1_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH1_CNTL 0x1ec7 +#define regCP_DMA_WATCH1_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_LO 0x1ec8 +#define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_HI 0x1ec9 +#define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH2_MASK 0x1eca +#define regCP_DMA_WATCH2_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH2_CNTL 0x1ecb +#define regCP_DMA_WATCH2_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_LO 0x1ecc +#define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_HI 0x1ecd +#define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH3_MASK 0x1ece +#define regCP_DMA_WATCH3_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH3_CNTL 0x1ecf +#define regCP_DMA_WATCH3_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 +#define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 +#define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT 0x1ed2 +#define regCP_DMA_WATCH_STAT_BASE_IDX 0 +#define regCP_PFP_JT_STAT 0x1ed3 +#define regCP_PFP_JT_STAT_BASE_IDX 0 +#define regCP_MEC_JT_STAT 0x1ed5 +#define regCP_MEC_JT_STAT_BASE_IDX 0 +#define regCP_CPC_BUSY_HYSTERESIS 0x1edb +#define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS1 0x1edc +#define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS2 0x1edd +#define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS1 0x1ede +#define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS2 0x1edf +#define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCPF_FED_ERROR_ADDR_LO 0x1ee0 +#define regCPF_FED_ERROR_ADDR_LO_BASE_IDX 0 +#define regCPF_FED_ERROR_ADDR_HI 0x1ee1 +#define regCPF_FED_ERROR_ADDR_HI_BASE_IDX 0 +#define regCPC_FED_ERROR_ADDR_LO 0x1ee2 +#define regCPC_FED_ERROR_ADDR_LO_BASE_IDX 0 +#define regCPC_FED_ERROR_ADDR_HI 0x1ee3 +#define regCPC_FED_ERROR_ADDR_HI_BASE_IDX 0 +#define regCPG_FED_ERROR_ADDR_LO 0x1ee4 +#define regCPG_FED_ERROR_ADDR_LO_BASE_IDX 0 +#define regCPG_FED_ERROR_ADDR_HI 0x1ee5 +#define regCPG_FED_ERROR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_DOORBELL_CLEAR 0x1f28 +#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define regCP_RB0_ACTIVE 0x1f40 +#define regCP_RB0_ACTIVE_BASE_IDX 0 +#define regCP_RB_ACTIVE 0x1f40 +#define regCP_RB_ACTIVE_BASE_IDX 0 +#define regCP_RB_STATUS 0x1f43 +#define regCP_RB_STATUS_BASE_IDX 0 +#define regCPG_RCIU_CAM_INDEX 0x1f44 +#define regCPG_RCIU_CAM_INDEX_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA 0x1f45 +#define regCPG_RCIU_CAM_DATA_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE0 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE1 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE2 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE3 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE3_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c +#define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d +#define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 +#define regCP_SDMA_DMA_DONE 0x1f4e +#define regCP_SDMA_DMA_DONE_BASE_IDX 0 +#define regCP_PFP_SDMA_CS 0x1f4f +#define regCP_PFP_SDMA_CS_BASE_IDX 0 +#define regCP_ME_SDMA_CS 0x1f50 +#define regCP_ME_SDMA_CS_BASE_IDX 0 +#define regCPF_GCR_CNTL 0x1f53 +#define regCPF_GCR_CNTL_BASE_IDX 0 +#define regCPG_UTCL1_STATUS 0x1f54 +#define regCPG_UTCL1_STATUS_BASE_IDX 0 +#define regCPC_UTCL1_STATUS 0x1f55 +#define regCPC_UTCL1_STATUS_BASE_IDX 0 +#define regCPF_UTCL1_STATUS 0x1f56 +#define regCPF_UTCL1_STATUS_BASE_IDX 0 +#define regCP_SD_CNTL 0x1f57 +#define regCP_SD_CNTL_BASE_IDX 0 +#define regCP_SOFT_RESET_CNTL 0x1f59 +#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define regCP_CPC_GFX_CNTL 0x1f5a +#define regCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpphqddec +// base address: 0xc800 +#define regCP_HPD_UTCL1_CNTL 0x1fa3 +#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR 0x1fa7 +#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 +#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR 0x1fa9 +#define regCP_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR_HI 0x1faa +#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_ACTIVE 0x1fab +#define regCP_HQD_ACTIVE_BASE_IDX 0 +#define regCP_HQD_VMID 0x1fac +#define regCP_HQD_VMID_BASE_IDX 0 +#define regCP_HQD_PERSISTENT_STATE 0x1fad +#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define regCP_HQD_PIPE_PRIORITY 0x1fae +#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUEUE_PRIORITY 0x1faf +#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUANTUM 0x1fb0 +#define regCP_HQD_QUANTUM_BASE_IDX 0 +#define regCP_HQD_PQ_BASE 0x1fb1 +#define regCP_HQD_PQ_BASE_BASE_IDX 0 +#define regCP_HQD_PQ_BASE_HI 0x1fb2 +#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR 0x1fb3 +#define regCP_HQD_PQ_RPTR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 +#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_CONTROL 0x1fba +#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR 0x1fbb +#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR_HI 0x1fbc +#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_IB_RPTR 0x1fbd +#define regCP_HQD_IB_RPTR_BASE_IDX 0 +#define regCP_HQD_IB_CONTROL 0x1fbe +#define regCP_HQD_IB_CONTROL_BASE_IDX 0 +#define regCP_HQD_IQ_TIMER 0x1fbf +#define regCP_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_HQD_IQ_RPTR 0x1fc0 +#define regCP_HQD_IQ_RPTR_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 +#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_HQD_DMA_OFFLOAD 0x1fc2 +#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_OFFLOAD 0x1fc2 +#define regCP_HQD_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_MSG_TYPE 0x1fc4 +#define regCP_HQD_MSG_TYPE_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 +#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 +#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 +#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 +#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER0 0x1fc9 +#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS0 0x1fc9 +#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL0 0x1fca +#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER1 0x1fca +#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define regCP_MQD_CONTROL 0x1fcb +#define regCP_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS1 0x1fcc +#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL1 0x1fcd +#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR 0x1fce +#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR_HI 0x1fcf +#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_EOP_CONTROL 0x1fd0 +#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define regCP_HQD_EOP_RPTR 0x1fd1 +#define regCP_HQD_EOP_RPTR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR 0x1fd2 +#define regCP_HQD_EOP_WPTR_BASE_IDX 0 +#define regCP_HQD_EOP_EVENTS 0x1fd3 +#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_CONTROL 0x1fd6 +#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_OFFSET 0x1fd7 +#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_SIZE 0x1fd8 +#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCP_HQD_WG_STATE_OFFSET 0x1fd9 +#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_SIZE 0x1fda +#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCP_HQD_GDS_RESOURCE_STATE 0x1fdb +#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define regCP_HQD_ERROR 0x1fdc +#define regCP_HQD_ERROR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR_MEM 0x1fdd +#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL 0x1fde +#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_LO 0x1fdf +#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_HI 0x1fe0 +#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_DDID_RPTR 0x1fe4 +#define regCP_HQD_DDID_RPTR_BASE_IDX 0 +#define regCP_HQD_DDID_WPTR 0x1fe5 +#define regCP_HQD_DDID_WPTR_BASE_IDX 0 +#define regCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 +#define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 +#define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_STATUS 0x1fe8 +#define regCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL_1 0x1fe9 +#define regCP_HQD_AQL_CONTROL_1_BASE_IDX 0 +#define regCP_HQD_AQL_DISPATCH_ID 0x1fea +#define regCP_HQD_AQL_DISPATCH_ID_BASE_IDX 0 +#define regCP_HQD_AQL_DISPATCH_ID_HI 0x1feb +#define regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX 0 +#define regCP_HQD_KD_BASE 0x1fec +#define regCP_HQD_KD_BASE_BASE_IDX 0 +#define regCP_HQD_KD_BASE_HI 0x1fed +#define regCP_HQD_KD_BASE_HI_BASE_IDX 0 +#define regCP_HQD_KD_CNTL 0x1fee +#define regCP_HQD_KD_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxdec0 +// base address: 0x28000 +#define regCOHER_DEST_BASE_HI_0 0x007a +#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_1 0x007b +#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_2 0x007c +#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_3 0x007d +#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_2 0x007e +#define regCOHER_DEST_BASE_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_3 0x007f +#define regCOHER_DEST_BASE_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_0 0x0092 +#define regCOHER_DEST_BASE_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_1 0x0093 +#define regCOHER_DEST_BASE_1_BASE_IDX 1 +#define regCP_PERFMON_CNTX_CNTL 0x00d8 +#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define regCP_PIPEID 0x00d9 +#define regCP_PIPEID_BASE_IDX 1 +#define regCP_RINGID 0x00d9 +#define regCP_RINGID_BASE_IDX 1 +#define regCP_VMID 0x00da +#define regCP_VMID_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG0 0x00db +#define regCONTEXT_RESERVED_REG0_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG1 0x00dc +#define regCONTEXT_RESERVED_REG1_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define regGFX_COPY_STATE 0x01f4 +#define regGFX_COPY_STATE_BASE_IDX 1 +#define regVGT_DMA_BASE_HI 0x01f9 +#define regVGT_DMA_BASE_HI_BASE_IDX 1 +#define regVGT_DMA_BASE 0x01fa +#define regVGT_DMA_BASE_BASE_IDX 1 +#define regVGT_DRAW_INITIATOR 0x01fc +#define regVGT_DRAW_INITIATOR_BASE_IDX 1 +#define regVGT_EVENT_ADDRESS_REG 0x01fe +#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define regGE_IA_ENHANCE 0x029c +#define regGE_IA_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_SIZE 0x029d +#define regVGT_DMA_SIZE_BASE_IDX 1 +#define regVGT_DMA_MAX_SIZE 0x029e +#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define regVGT_DMA_INDEX_TYPE 0x029f +#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define regGE_WD_ENHANCE 0x02a0 +#define regGE_WD_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_NUM_INSTANCES 0x02a2 +#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_EVENT_INITIATOR 0x02a4 +#define regVGT_EVENT_INITIATOR_BASE_IDX 1 +#define regVGT_SHADER_STAGES_EN 0x02a6 +#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define regVGT_TF_PARAM 0x02a9 +#define regVGT_TF_PARAM_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define regVGT_TESS_DISTRIBUTION 0x02d4 +#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define regVGT_LS_HS_CONFIG 0x02d6 +#define regVGT_LS_HS_CONFIG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_cpdec +// base address: 0x2a000 +#define regCONFIG_RESERVED_REG0 0x0800 +#define regCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regCONFIG_RESERVED_REG1 0x0801 +#define regCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_MEC_CNTL 0x0802 +#define regCP_MEC_CNTL_BASE_IDX 1 +#define regCP_ME_CNTL 0x0803 +#define regCP_ME_CNTL_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE0 0x0840 +#define regCP_UNMAPPED_QUEUE0_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE1 0x0841 +#define regCP_UNMAPPED_QUEUE1_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE2 0x0842 +#define regCP_UNMAPPED_QUEUE2_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE3 0x0843 +#define regCP_UNMAPPED_QUEUE3_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE4 0x0844 +#define regCP_UNMAPPED_QUEUE4_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE5 0x0845 +#define regCP_UNMAPPED_QUEUE5_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE6 0x0846 +#define regCP_UNMAPPED_QUEUE6_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE7 0x0847 +#define regCP_UNMAPPED_QUEUE7_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE8 0x0848 +#define regCP_UNMAPPED_QUEUE8_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE9 0x0849 +#define regCP_UNMAPPED_QUEUE9_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE10 0x084a +#define regCP_UNMAPPED_QUEUE10_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE11 0x084b +#define regCP_UNMAPPED_QUEUE11_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE12 0x084c +#define regCP_UNMAPPED_QUEUE12_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE13 0x084d +#define regCP_UNMAPPED_QUEUE13_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE14 0x084e +#define regCP_UNMAPPED_QUEUE14_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE15 0x084f +#define regCP_UNMAPPED_QUEUE15_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE16 0x0850 +#define regCP_UNMAPPED_QUEUE16_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE17 0x0851 +#define regCP_UNMAPPED_QUEUE17_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE18 0x0852 +#define regCP_UNMAPPED_QUEUE18_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE19 0x0853 +#define regCP_UNMAPPED_QUEUE19_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE20 0x0854 +#define regCP_UNMAPPED_QUEUE20_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE21 0x0855 +#define regCP_UNMAPPED_QUEUE21_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE22 0x0856 +#define regCP_UNMAPPED_QUEUE22_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE23 0x0857 +#define regCP_UNMAPPED_QUEUE23_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE24 0x0858 +#define regCP_UNMAPPED_QUEUE24_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE25 0x0859 +#define regCP_UNMAPPED_QUEUE25_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE26 0x085a +#define regCP_UNMAPPED_QUEUE26_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE27 0x085b +#define regCP_UNMAPPED_QUEUE27_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE28 0x085c +#define regCP_UNMAPPED_QUEUE28_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE29 0x085d +#define regCP_UNMAPPED_QUEUE29_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE30 0x085e +#define regCP_UNMAPPED_QUEUE30_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE31 0x085f +#define regCP_UNMAPPED_QUEUE31_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE32 0x0860 +#define regCP_UNMAPPED_QUEUE32_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE33 0x0861 +#define regCP_UNMAPPED_QUEUE33_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE34 0x0862 +#define regCP_UNMAPPED_QUEUE34_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE35 0x0863 +#define regCP_UNMAPPED_QUEUE35_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE36 0x0864 +#define regCP_UNMAPPED_QUEUE36_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE37 0x0865 +#define regCP_UNMAPPED_QUEUE37_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE38 0x0866 +#define regCP_UNMAPPED_QUEUE38_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE39 0x0867 +#define regCP_UNMAPPED_QUEUE39_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE40 0x0868 +#define regCP_UNMAPPED_QUEUE40_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE41 0x0869 +#define regCP_UNMAPPED_QUEUE41_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE42 0x086a +#define regCP_UNMAPPED_QUEUE42_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE43 0x086b +#define regCP_UNMAPPED_QUEUE43_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE44 0x086c +#define regCP_UNMAPPED_QUEUE44_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE45 0x086d +#define regCP_UNMAPPED_QUEUE45_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE46 0x086e +#define regCP_UNMAPPED_QUEUE46_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE47 0x086f +#define regCP_UNMAPPED_QUEUE47_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE48 0x0870 +#define regCP_UNMAPPED_QUEUE48_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE49 0x0871 +#define regCP_UNMAPPED_QUEUE49_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE50 0x0872 +#define regCP_UNMAPPED_QUEUE50_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE51 0x0873 +#define regCP_UNMAPPED_QUEUE51_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE52 0x0874 +#define regCP_UNMAPPED_QUEUE52_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE53 0x0875 +#define regCP_UNMAPPED_QUEUE53_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE54 0x0876 +#define regCP_UNMAPPED_QUEUE54_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE55 0x0877 +#define regCP_UNMAPPED_QUEUE55_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE56 0x0878 +#define regCP_UNMAPPED_QUEUE56_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE57 0x0879 +#define regCP_UNMAPPED_QUEUE57_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE58 0x087a +#define regCP_UNMAPPED_QUEUE58_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE59 0x087b +#define regCP_UNMAPPED_QUEUE59_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE60 0x087c +#define regCP_UNMAPPED_QUEUE60_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE61 0x087d +#define regCP_UNMAPPED_QUEUE61_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE62 0x087e +#define regCP_UNMAPPED_QUEUE62_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE63 0x087f +#define regCP_UNMAPPED_QUEUE63_BASE_IDX 1 +#define regCP_UNMAPPED_DOORBELL 0x0880 +#define regCP_UNMAPPED_DOORBELL_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE_BANK0 0x0881 +#define regCP_UNMAPPED_QUEUE_BANK0_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE_BANK1 0x0882 +#define regCP_UNMAPPED_QUEUE_BANK1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_grbmdec +// base address: 0x2a400 +#define regGRBM_GFX_CNTL 0x0900 +#define regGRBM_GFX_CNTL_BASE_IDX 1 +#define regGRBM_NOWHERE 0x0901 +#define regGRBM_NOWHERE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpdec +// base address: 0x2e000 +#define regCP_FETCHER_SOURCE 0x1801 +#define regCP_FETCHER_SOURCE_BASE_IDX 1 +#define regCP_DFY_CNTL 0x1804 +#define regCP_DFY_CNTL_BASE_IDX 1 +#define regCP_DFY_STAT 0x1805 +#define regCP_DFY_STAT_BASE_IDX 1 +#define regCP_DFY_ADDR_HI 0x1806 +#define regCP_DFY_ADDR_HI_BASE_IDX 1 +#define regCP_DFY_ADDR_LO 0x1807 +#define regCP_DFY_ADDR_LO_BASE_IDX 1 +#define regCP_DFY_DATA_0 0x1808 +#define regCP_DFY_DATA_0_BASE_IDX 1 +#define regCP_DFY_DATA_1 0x1809 +#define regCP_DFY_DATA_1_BASE_IDX 1 +#define regCP_DFY_DATA_2 0x180a +#define regCP_DFY_DATA_2_BASE_IDX 1 +#define regCP_DFY_DATA_3 0x180b +#define regCP_DFY_DATA_3_BASE_IDX 1 +#define regCP_DFY_DATA_4 0x180c +#define regCP_DFY_DATA_4_BASE_IDX 1 +#define regCP_DFY_DATA_5 0x180d +#define regCP_DFY_DATA_5_BASE_IDX 1 +#define regCP_DFY_DATA_6 0x180e +#define regCP_DFY_DATA_6_BASE_IDX 1 +#define regCP_DFY_DATA_7 0x180f +#define regCP_DFY_DATA_7_BASE_IDX 1 +#define regCP_DFY_DATA_8 0x1810 +#define regCP_DFY_DATA_8_BASE_IDX 1 +#define regCP_DFY_DATA_9 0x1811 +#define regCP_DFY_DATA_9_BASE_IDX 1 +#define regCP_DFY_DATA_10 0x1812 +#define regCP_DFY_DATA_10_BASE_IDX 1 +#define regCP_DFY_DATA_11 0x1813 +#define regCP_DFY_DATA_11_BASE_IDX 1 +#define regCP_DFY_DATA_12 0x1814 +#define regCP_DFY_DATA_12_BASE_IDX 1 +#define regCP_DFY_DATA_13 0x1815 +#define regCP_DFY_DATA_13_BASE_IDX 1 +#define regCP_DFY_DATA_14 0x1816 +#define regCP_DFY_DATA_14_BASE_IDX 1 +#define regCP_DFY_DATA_15 0x1817 +#define regCP_DFY_DATA_15_BASE_IDX 1 +#define regCP_DFY_CMD 0x1818 +#define regCP_DFY_CMD_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpphqddec +// base address: 0x2e080 +#define regCP_HPD_MES_ROQ_OFFSETS 0x1821 +#define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_ROQ_OFFSETS 0x1821 +#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_STATUS0 0x1822 +#define regCP_HPD_STATUS0_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gcrdec +// base address: 0x2e640 +#define regGCR_GENERAL_CNTL 0x1990 +#define regGCR_GENERAL_CNTL_BASE_IDX 1 +#define regGCR_TARGET_DISABLE 0x1991 +#define regGCR_TARGET_DISABLE_BASE_IDX 1 +#define regGCR_CMD_STATUS 0x1992 +#define regGCR_CMD_STATUS_BASE_IDX 1 +#define regGCR_SPARE 0x1993 +#define regGCR_SPARE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxudec +// base address: 0x30000 +#define regCP_EOP_DONE_ADDR_LO 0x2000 +#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define regCP_EOP_DONE_ADDR_HI 0x2001 +#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_LO 0x2002 +#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_HI 0x2003 +#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_LO 0x2004 +#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_HI 0x2005 +#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_LO 0x2018 +#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_HI 0x2019 +#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_LO 0x201a +#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_HI 0x201b +#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_LO 0x201c +#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_HI 0x201d +#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_LO 0x201e +#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_HI 0x201f +#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_LO 0x2028 +#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_HI 0x2029 +#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_LO 0x202a +#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_HI 0x202b +#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_LO 0x202c +#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_HI 0x202d +#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_LO 0x202e +#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_HI 0x202f +#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_LO 0x2032 +#define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_HI 0x2033 +#define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_CONTROL 0x203d +#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define regSCRATCH_REG0 0x2040 +#define regSCRATCH_REG0_BASE_IDX 1 +#define regSCRATCH_REG1 0x2041 +#define regSCRATCH_REG1_BASE_IDX 1 +#define regSCRATCH_REG2 0x2042 +#define regSCRATCH_REG2_BASE_IDX 1 +#define regSCRATCH_REG3 0x2043 +#define regSCRATCH_REG3_BASE_IDX 1 +#define regSCRATCH_REG4 0x2044 +#define regSCRATCH_REG4_BASE_IDX 1 +#define regSCRATCH_REG5 0x2045 +#define regSCRATCH_REG5_BASE_IDX 1 +#define regSCRATCH_REG6 0x2046 +#define regSCRATCH_REG6_BASE_IDX 1 +#define regSCRATCH_REG7 0x2047 +#define regSCRATCH_REG7_BASE_IDX 1 +#define regSCRATCH_REG_ATOMIC 0x2048 +#define regSCRATCH_REG_ATOMIC_BASE_IDX 1 +#define regSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 +#define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 +#define regCP_APPEND_DDID_CNT 0x204b +#define regCP_APPEND_DDID_CNT_BASE_IDX 1 +#define regCP_APPEND_DATA_HI 0x204c +#define regCP_APPEND_DATA_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_APPEND_ADDR_LO 0x2058 +#define regCP_APPEND_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_ADDR_HI 0x2059 +#define regCP_APPEND_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_DATA 0x205a +#define regCP_APPEND_DATA_BASE_IDX 1 +#define regCP_APPEND_DATA_LO 0x205a +#define regCP_APPEND_DATA_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE 0x205b +#define regCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE 0x205c +#define regCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_LO 0x205d +#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_LO 0x205d +#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_HI 0x205e +#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_HI 0x205e +#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_MC_WADDR_LO 0x2069 +#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_WADDR_HI 0x206a +#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define regCP_ME_MC_WDATA_LO 0x206b +#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define regCP_ME_MC_WDATA_HI 0x206c +#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define regCP_ME_MC_RADDR_LO 0x206d +#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_RADDR_HI 0x206e +#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define regCP_DMA_PFP_CONTROL 0x2077 +#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_CONTROL 0x2078 +#define regCP_DMA_ME_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR 0x2080 +#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR 0x2082 +#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR_HI 0x2083 +#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_COMMAND 0x2084 +#define regCP_DMA_ME_COMMAND_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR 0x2085 +#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR 0x2087 +#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_COMMAND 0x2089 +#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define regCP_DMA_CNTL 0x208a +#define regCP_DMA_CNTL_BASE_IDX 1 +#define regCP_DMA_READ_TAGS 0x208b +#define regCP_DMA_READ_TAGS_BASE_IDX 1 +#define regCP_PFP_IB_CONTROL 0x208d +#define regCP_PFP_IB_CONTROL_BASE_IDX 1 +#define regCP_PFP_LOAD_CONTROL 0x208e +#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define regCP_SCRATCH_INDEX 0x208f +#define regCP_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_SCRATCH_DATA 0x2090 +#define regCP_SCRATCH_DATA_BASE_IDX 1 +#define regCP_RB_OFFSET 0x2091 +#define regCP_RB_OFFSET_BASE_IDX 1 +#define regCP_IB1_OFFSET 0x2092 +#define regCP_IB1_OFFSET_BASE_IDX 1 +#define regCP_IB2_OFFSET 0x2093 +#define regCP_IB2_OFFSET_BASE_IDX 1 +#define regCP_IB1_PREAMBLE_BEGIN 0x2094 +#define regCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB1_PREAMBLE_END 0x2095 +#define regCP_IB1_PREAMBLE_END_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_BEGIN 0x2096 +#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_END 0x2097 +#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_LO 0x209c +#define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_HI 0x209d +#define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_LO 0x209e +#define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_HI 0x209f +#define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG0 0x20a2 +#define regUCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG1 0x20a3 +#define regUCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_LO 0x20a4 +#define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_HI 0x20a5 +#define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_LO 0x20a6 +#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_HI 0x20a7 +#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_IB1_CMD_BUFSZ 0x20c0 +#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB2_CMD_BUFSZ 0x20c1 +#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_ST_CMD_BUFSZ 0x20c2 +#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB1_BASE_LO 0x20cc +#define regCP_IB1_BASE_LO_BASE_IDX 1 +#define regCP_IB1_BASE_HI 0x20cd +#define regCP_IB1_BASE_HI_BASE_IDX 1 +#define regCP_IB1_BUFSZ 0x20ce +#define regCP_IB1_BUFSZ_BASE_IDX 1 +#define regCP_IB2_BASE_LO 0x20cf +#define regCP_IB2_BASE_LO_BASE_IDX 1 +#define regCP_IB2_BASE_HI 0x20d0 +#define regCP_IB2_BASE_HI_BASE_IDX 1 +#define regCP_IB2_BUFSZ 0x20d1 +#define regCP_IB2_BUFSZ_BASE_IDX 1 +#define regCP_ST_BASE_LO 0x20d2 +#define regCP_ST_BASE_LO_BASE_IDX 1 +#define regCP_ST_BASE_HI 0x20d3 +#define regCP_ST_BASE_HI_BASE_IDX 1 +#define regCP_ST_BUFSZ 0x20d4 +#define regCP_ST_BUFSZ_BASE_IDX 1 +#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_CNTL 0x20d6 +#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_CNTX_ID 0x20d7 +#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define regCP_DB_BASE_LO 0x20d8 +#define regCP_DB_BASE_LO_BASE_IDX 1 +#define regCP_DB_BASE_HI 0x20d9 +#define regCP_DB_BASE_HI_BASE_IDX 1 +#define regCP_DB_BUFSZ 0x20da +#define regCP_DB_BUFSZ_BASE_IDX 1 +#define regCP_DB_CMD_BUFSZ 0x20db +#define regCP_DB_CMD_BUFSZ_BASE_IDX 1 +#define regCP_PFP_COMPLETION_STATUS 0x20ec +#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_PRED_NOT_VISIBLE 0x20ee +#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR 0x20f6 +#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR 0x20f8 +#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR_HI 0x20f9 +#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_TYPE 0x20fa +#define regCP_INDEX_TYPE_BASE_IDX 1 +#define regCP_SAMPLE_STATUS 0x20fd +#define regCP_SAMPLE_STATUS_BASE_IDX 1 +#define regCP_ME_COHER_CNTL 0x20fe +#define regCP_ME_COHER_CNTL_BASE_IDX 1 +#define regCP_ME_COHER_SIZE 0x20ff +#define regCP_ME_COHER_SIZE_BASE_IDX 1 +#define regCP_ME_COHER_SIZE_HI 0x2100 +#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_ME_COHER_BASE 0x2101 +#define regCP_ME_COHER_BASE_BASE_IDX 1 +#define regCP_ME_COHER_BASE_HI 0x2102 +#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define regCP_ME_COHER_STATUS 0x2103 +#define regCP_ME_COHER_STATUS_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_0 0x2140 +#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_1 0x2141 +#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define regGRBM_GFX_INDEX 0x2200 +#define regGRBM_GFX_INDEX_BASE_IDX 1 +#define regGRBM_NOWHERE_2 0x2201 +#define regGRBM_NOWHERE_2_BASE_IDX 1 +#define regVGT_PRIMITIVE_TYPE 0x2242 +#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define regVGT_INDEX_TYPE 0x2243 +#define regVGT_INDEX_TYPE_BASE_IDX 1 +#define regGE_MIN_VTX_INDX 0x2249 +#define regGE_MIN_VTX_INDX_BASE_IDX 1 +#define regGE_INDX_OFFSET 0x224a +#define regGE_INDX_OFFSET_BASE_IDX 1 +#define regGE_MULTI_PRIM_IB_RESET_EN 0x224b +#define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define regVGT_NUM_INDICES 0x224c +#define regVGT_NUM_INDICES_BASE_IDX 1 +#define regVGT_NUM_INSTANCES 0x224d +#define regVGT_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE 0x2250 +#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define regGE_GS_THROTTLE 0x2254 +#define regGE_GS_THROTTLE_BASE_IDX 1 +#define regGE_MAX_VTX_INDX 0x2259 +#define regGE_MAX_VTX_INDX_BASE_IDX 1 +#define regVGT_INSTANCE_BASE_ID 0x225a +#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define regGE_CNTL 0x225b +#define regGE_CNTL_BASE_IDX 1 +#define regGE_USER_VGPR1 0x225c +#define regGE_USER_VGPR1_BASE_IDX 1 +#define regGE_USER_VGPR2 0x225d +#define regGE_USER_VGPR2_BASE_IDX 1 +#define regGE_USER_VGPR3 0x225e +#define regGE_USER_VGPR3_BASE_IDX 1 +#define regGE_STEREO_CNTL 0x225f +#define regGE_STEREO_CNTL_BASE_IDX 1 +#define regGE_USER_VGPR_EN 0x2260 +#define regGE_USER_VGPR_EN_BASE_IDX 1 +#define regVGT_PRIMITIVEID_EN 0x2262 +#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define regGE_VRS_RATE 0x2263 +#define regGE_VRS_RATE_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM 0x2264 +#define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1 0x2265 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX 1 +#define regVGT_GS_OUT_PRIM_TYPE 0x2266 +#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE_HI 0x2267 +#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define regGE_GS_ORDERED_ID_BASE 0x226c +#define regGE_GS_ORDERED_ID_BASE_BASE_IDX 1 +#define regVGT_PRIMITIVEID_RESET 0x226d +#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cprs64dec +// base address: 0x32000 +#define regCP_MES_PRGRM_CNTR_START 0x2800 +#define regCP_MES_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START 0x2801 +#define regCP_MES_INTR_ROUTINE_START_BASE_IDX 1 +#define regCP_MES_MTVEC_LO 0x2801 +#define regCP_MES_MTVEC_LO_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START_HI 0x2802 +#define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 +#define regCP_MES_MTVEC_HI 0x2802 +#define regCP_MES_MTVEC_HI_BASE_IDX 1 +#define regCP_MES_CNTL 0x2807 +#define regCP_MES_CNTL_BASE_IDX 1 +#define regCP_MES_PIPE_PRIORITY_CNTS 0x2808 +#define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regCP_MES_PIPE0_PRIORITY 0x2809 +#define regCP_MES_PIPE0_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE1_PRIORITY 0x280a +#define regCP_MES_PIPE1_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE2_PRIORITY 0x280b +#define regCP_MES_PIPE2_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE3_PRIORITY 0x280c +#define regCP_MES_PIPE3_PRIORITY_BASE_IDX 1 +#define regCP_MES_HEADER_DUMP 0x280d +#define regCP_MES_HEADER_DUMP_BASE_IDX 1 +#define regCP_MES_MIE_LO 0x280e +#define regCP_MES_MIE_LO_BASE_IDX 1 +#define regCP_MES_MIE_HI 0x280f +#define regCP_MES_MIE_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT 0x2810 +#define regCP_MES_INTERRUPT_BASE_IDX 1 +#define regCP_MES_SCRATCH_INDEX 0x2811 +#define regCP_MES_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_MES_SCRATCH_DATA 0x2812 +#define regCP_MES_SCRATCH_DATA_BASE_IDX 1 +#define regCP_MES_INSTR_PNTR 0x2813 +#define regCP_MES_INSTR_PNTR_BASE_IDX 1 +#define regCP_MES_MSCRATCH_HI 0x2814 +#define regCP_MES_MSCRATCH_HI_BASE_IDX 1 +#define regCP_MES_MSCRATCH_LO 0x2815 +#define regCP_MES_MSCRATCH_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_LO 0x2816 +#define regCP_MES_MSTATUS_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_HI 0x2817 +#define regCP_MES_MSTATUS_HI_BASE_IDX 1 +#define regCP_MES_MEPC_LO 0x2818 +#define regCP_MES_MEPC_LO_BASE_IDX 1 +#define regCP_MES_MEPC_HI 0x2819 +#define regCP_MES_MEPC_HI_BASE_IDX 1 +#define regCP_MES_MCAUSE_LO 0x281a +#define regCP_MES_MCAUSE_LO_BASE_IDX 1 +#define regCP_MES_MCAUSE_HI 0x281b +#define regCP_MES_MCAUSE_HI_BASE_IDX 1 +#define regCP_MES_MBADADDR_LO 0x281c +#define regCP_MES_MBADADDR_LO_BASE_IDX 1 +#define regCP_MES_MBADADDR_HI 0x281d +#define regCP_MES_MBADADDR_HI_BASE_IDX 1 +#define regCP_MES_MIP_LO 0x281e +#define regCP_MES_MIP_LO_BASE_IDX 1 +#define regCP_MES_MIP_HI 0x281f +#define regCP_MES_MIP_HI_BASE_IDX 1 +#define regCP_MES_IC_OP_CNTL 0x2820 +#define regCP_MES_IC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MCYCLE_LO 0x2826 +#define regCP_MES_MCYCLE_LO_BASE_IDX 1 +#define regCP_MES_MCYCLE_HI 0x2827 +#define regCP_MES_MCYCLE_HI_BASE_IDX 1 +#define regCP_MES_MTIME_LO 0x2828 +#define regCP_MES_MTIME_LO_BASE_IDX 1 +#define regCP_MES_MTIME_HI 0x2829 +#define regCP_MES_MTIME_HI_BASE_IDX 1 +#define regCP_MES_MINSTRET_LO 0x282a +#define regCP_MES_MINSTRET_LO_BASE_IDX 1 +#define regCP_MES_MINSTRET_HI 0x282b +#define regCP_MES_MINSTRET_HI_BASE_IDX 1 +#define regCP_MES_MISA_LO 0x282c +#define regCP_MES_MISA_LO_BASE_IDX 1 +#define regCP_MES_MISA_HI 0x282d +#define regCP_MES_MISA_HI_BASE_IDX 1 +#define regCP_MES_MVENDORID_LO 0x282e +#define regCP_MES_MVENDORID_LO_BASE_IDX 1 +#define regCP_MES_MVENDORID_HI 0x282f +#define regCP_MES_MVENDORID_HI_BASE_IDX 1 +#define regCP_MES_MARCHID_LO 0x2830 +#define regCP_MES_MARCHID_LO_BASE_IDX 1 +#define regCP_MES_MARCHID_HI 0x2831 +#define regCP_MES_MARCHID_HI_BASE_IDX 1 +#define regCP_MES_MIMPID_LO 0x2832 +#define regCP_MES_MIMPID_LO_BASE_IDX 1 +#define regCP_MES_MIMPID_HI 0x2833 +#define regCP_MES_MIMPID_HI_BASE_IDX 1 +#define regCP_MES_MHARTID_LO 0x2834 +#define regCP_MES_MHARTID_LO_BASE_IDX 1 +#define regCP_MES_MHARTID_HI 0x2835 +#define regCP_MES_MHARTID_HI_BASE_IDX 1 +#define regCP_MES_DC_BASE_CNTL 0x2836 +#define regCP_MES_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_OP_CNTL 0x2837 +#define regCP_MES_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MTIMECMP_LO 0x2838 +#define regCP_MES_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MES_MTIMECMP_HI 0x2839 +#define regCP_MES_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE0 0x283a +#define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE1 0x283b +#define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL1 0x283c +#define regCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL2 0x283d +#define regCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL3 0x283e +#define regCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL4 0x283f +#define regCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL5 0x2840 +#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL6 0x2841 +#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 +#define regCP_MES_GP0_LO 0x2843 +#define regCP_MES_GP0_LO_BASE_IDX 1 +#define regCP_MES_GP0_HI 0x2844 +#define regCP_MES_GP0_HI_BASE_IDX 1 +#define regCP_MES_GP1_LO 0x2845 +#define regCP_MES_GP1_LO_BASE_IDX 1 +#define regCP_MES_GP1_HI 0x2846 +#define regCP_MES_GP1_HI_BASE_IDX 1 +#define regCP_MES_GP2_LO 0x2847 +#define regCP_MES_GP2_LO_BASE_IDX 1 +#define regCP_MES_GP2_HI 0x2848 +#define regCP_MES_GP2_HI_BASE_IDX 1 +#define regCP_MES_GP3_LO 0x2849 +#define regCP_MES_GP3_LO_BASE_IDX 1 +#define regCP_MES_GP3_HI 0x284a +#define regCP_MES_GP3_HI_BASE_IDX 1 +#define regCP_MES_GP4_LO 0x284b +#define regCP_MES_GP4_LO_BASE_IDX 1 +#define regCP_MES_GP4_HI 0x284c +#define regCP_MES_GP4_HI_BASE_IDX 1 +#define regCP_MES_GP5_LO 0x284d +#define regCP_MES_GP5_LO_BASE_IDX 1 +#define regCP_MES_GP5_HI 0x284e +#define regCP_MES_GP5_HI_BASE_IDX 1 +#define regCP_MES_GP6_LO 0x284f +#define regCP_MES_GP6_LO_BASE_IDX 1 +#define regCP_MES_GP6_HI 0x2850 +#define regCP_MES_GP6_HI_BASE_IDX 1 +#define regCP_MES_GP7_LO 0x2851 +#define regCP_MES_GP7_LO_BASE_IDX 1 +#define regCP_MES_GP7_HI 0x2852 +#define regCP_MES_GP7_HI_BASE_IDX 1 +#define regCP_MES_GP8_LO 0x2853 +#define regCP_MES_GP8_LO_BASE_IDX 1 +#define regCP_MES_GP8_HI 0x2854 +#define regCP_MES_GP8_HI_BASE_IDX 1 +#define regCP_MES_GP9_LO 0x2855 +#define regCP_MES_GP9_LO_BASE_IDX 1 +#define regCP_MES_GP9_HI 0x2856 +#define regCP_MES_GP9_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_LO 0x2883 +#define regCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_HI 0x2884 +#define regCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_LO 0x2885 +#define regCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_HI 0x2886 +#define regCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_APERTURE 0x2887 +#define regCP_MES_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_LO 0x2888 +#define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_HI 0x2889 +#define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_LO 0x288a +#define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_HI 0x288b +#define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_APERTURE 0x288c +#define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_APERTURE 0x288d +#define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_LO 0x288e +#define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_HI 0x288f +#define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MES_PERFCOUNT_CNTL 0x2899 +#define regCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MES_PENDING_INTERRUPT 0x289a +#define regCP_MES_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MES_RS64_EXCEPTION_STATUS 0x289c +#define regCP_MES_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_MES_PRGRM_CNTR_START_HI 0x289d +#define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_16 0x289f +#define regCP_MES_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_17 0x28a0 +#define regCP_MES_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_18 0x28a1 +#define regCP_MES_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_19 0x28a2 +#define regCP_MES_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_20 0x28a3 +#define regCP_MES_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_21 0x28a4 +#define regCP_MES_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_22 0x28a5 +#define regCP_MES_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_23 0x28a6 +#define regCP_MES_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_24 0x28a7 +#define regCP_MES_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_25 0x28a8 +#define regCP_MES_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_26 0x28a9 +#define regCP_MES_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_27 0x28aa +#define regCP_MES_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_28 0x28ab +#define regCP_MES_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_29 0x28ac +#define regCP_MES_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_30 0x28ad +#define regCP_MES_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_31 0x28ae +#define regCP_MES_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_MES_METADATA_CNTL 0x28df +#define regCP_MES_METADATA_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START 0x2900 +#define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MEC_MTVEC_LO 0x2901 +#define regCP_MEC_MTVEC_LO_BASE_IDX 1 +#define regCP_MEC_MTVEC_HI 0x2902 +#define regCP_MEC_MTVEC_HI_BASE_IDX 1 +#define regCP_MEC_RS64_CNTL 0x2904 +#define regCP_MEC_RS64_CNTL_BASE_IDX 1 +#define regCP_MEC_MIE_LO 0x2905 +#define regCP_MEC_MIE_LO_BASE_IDX 1 +#define regCP_MEC_MIE_HI 0x2906 +#define regCP_MEC_MIE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT 0x2907 +#define regCP_MEC_RS64_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_INSTR_PNTR 0x2908 +#define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX 1 +#define regCP_MEC_MIP_LO 0x2909 +#define regCP_MEC_MIP_LO_BASE_IDX 1 +#define regCP_MEC_MIP_HI 0x290a +#define regCP_MEC_MIP_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_CNTL 0x290b +#define regCP_MEC_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_OP_CNTL 0x290c +#define regCP_MEC_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_LO 0x290d +#define regCP_MEC_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_HI 0x290e +#define regCP_MEC_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MEC_GP0_LO 0x2910 +#define regCP_MEC_GP0_LO_BASE_IDX 1 +#define regCP_MEC_GP0_HI 0x2911 +#define regCP_MEC_GP0_HI_BASE_IDX 1 +#define regCP_MEC_GP1_LO 0x2912 +#define regCP_MEC_GP1_LO_BASE_IDX 1 +#define regCP_MEC_GP1_HI 0x2913 +#define regCP_MEC_GP1_HI_BASE_IDX 1 +#define regCP_MEC_GP2_LO 0x2914 +#define regCP_MEC_GP2_LO_BASE_IDX 1 +#define regCP_MEC_GP2_HI 0x2915 +#define regCP_MEC_GP2_HI_BASE_IDX 1 +#define regCP_MEC_GP3_LO 0x2916 +#define regCP_MEC_GP3_LO_BASE_IDX 1 +#define regCP_MEC_GP3_HI 0x2917 +#define regCP_MEC_GP3_HI_BASE_IDX 1 +#define regCP_MEC_GP4_LO 0x2918 +#define regCP_MEC_GP4_LO_BASE_IDX 1 +#define regCP_MEC_GP4_HI 0x2919 +#define regCP_MEC_GP4_HI_BASE_IDX 1 +#define regCP_MEC_GP5_LO 0x291a +#define regCP_MEC_GP5_LO_BASE_IDX 1 +#define regCP_MEC_GP5_HI 0x291b +#define regCP_MEC_GP5_HI_BASE_IDX 1 +#define regCP_MEC_GP6_LO 0x291c +#define regCP_MEC_GP6_LO_BASE_IDX 1 +#define regCP_MEC_GP6_HI 0x291d +#define regCP_MEC_GP6_HI_BASE_IDX 1 +#define regCP_MEC_GP7_LO 0x291e +#define regCP_MEC_GP7_LO_BASE_IDX 1 +#define regCP_MEC_GP7_HI 0x291f +#define regCP_MEC_GP7_HI_BASE_IDX 1 +#define regCP_MEC_GP8_LO 0x2920 +#define regCP_MEC_GP8_LO_BASE_IDX 1 +#define regCP_MEC_GP8_HI 0x2921 +#define regCP_MEC_GP8_HI_BASE_IDX 1 +#define regCP_MEC_GP9_LO 0x2922 +#define regCP_MEC_GP9_LO_BASE_IDX 1 +#define regCP_MEC_GP9_HI 0x2923 +#define regCP_MEC_GP9_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_LO 0x2927 +#define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_HI 0x2928 +#define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_LO 0x2929 +#define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_HI 0x292a +#define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_APERTURE 0x292b +#define regCP_MEC_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_LO 0x292c +#define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_HI 0x292d +#define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_LO 0x292e +#define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_HI 0x292f +#define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_APERTURE 0x2930 +#define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE 0x2931 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO 0x2932 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI 0x2933 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_PERFCOUNT_CNTL 0x2934 +#define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PENDING_INTERRUPT 0x2935 +#define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_EXCEPTION_STATUS 0x2937 +#define regCP_MEC_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI 0x2938 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_16 0x293a +#define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_17 0x293b +#define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_18 0x293c +#define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_19 0x293d +#define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_20 0x293e +#define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_21 0x293f +#define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_22 0x2940 +#define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_23 0x2941 +#define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_24 0x2942 +#define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_25 0x2943 +#define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_26 0x2944 +#define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_27 0x2945 +#define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_28 0x2946 +#define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_29 0x2947 +#define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_30 0x2948 +#define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_31 0x2949 +#define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_CPC_IC_OP_CNTL 0x297a +#define regCP_CPC_IC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT0 0x2a01 +#define regCP_GFX_RS64_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN0 0x2a02 +#define regCP_GFX_RS64_INTR_EN0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN1 0x2a03 +#define regCP_GFX_RS64_INTR_EN1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE_CNTL 0x2a08 +#define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_DC_OP_CNTL 0x2a09 +#define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_LO 0x2a0a +#define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_HI 0x2a0b +#define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_LO 0x2a0c +#define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_HI 0x2a0d +#define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_APERTURE 0x2a0e +#define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO 0x2a0f +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI 0x2a10 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO 0x2a11 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI 0x2a12 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE 0x2a13 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE 0x2a14 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO 0x2a15 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI 0x2a16 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_PFP_RS64_EXCEPTION_STATUS 0x2a19 +#define regCP_PFP_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL0 0x2a1a +#define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL1 0x2a1b +#define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO0 0x2a1c +#define regCP_GFX_RS64_MIP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO1 0x2a1d +#define regCP_GFX_RS64_MIP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI0 0x2a1e +#define regCP_GFX_RS64_MIP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI1 0x2a1f +#define regCP_GFX_RS64_MIP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO0 0x2a20 +#define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO1 0x2a21 +#define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI0 0x2a22 +#define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI1 0x2a23 +#define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO0 0x2a24 +#define regCP_GFX_RS64_GP0_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO1 0x2a25 +#define regCP_GFX_RS64_GP0_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI0 0x2a26 +#define regCP_GFX_RS64_GP0_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI1 0x2a27 +#define regCP_GFX_RS64_GP0_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO0 0x2a28 +#define regCP_GFX_RS64_GP1_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO1 0x2a29 +#define regCP_GFX_RS64_GP1_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI0 0x2a2a +#define regCP_GFX_RS64_GP1_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI1 0x2a2b +#define regCP_GFX_RS64_GP1_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO0 0x2a2c +#define regCP_GFX_RS64_GP2_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO1 0x2a2d +#define regCP_GFX_RS64_GP2_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI0 0x2a2e +#define regCP_GFX_RS64_GP2_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI1 0x2a2f +#define regCP_GFX_RS64_GP2_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO0 0x2a30 +#define regCP_GFX_RS64_GP3_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO1 0x2a31 +#define regCP_GFX_RS64_GP3_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI0 0x2a32 +#define regCP_GFX_RS64_GP3_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI1 0x2a33 +#define regCP_GFX_RS64_GP3_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO0 0x2a34 +#define regCP_GFX_RS64_GP4_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO1 0x2a35 +#define regCP_GFX_RS64_GP4_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI0 0x2a36 +#define regCP_GFX_RS64_GP4_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI1 0x2a37 +#define regCP_GFX_RS64_GP4_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO0 0x2a38 +#define regCP_GFX_RS64_GP5_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO1 0x2a39 +#define regCP_GFX_RS64_GP5_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI0 0x2a3a +#define regCP_GFX_RS64_GP5_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI1 0x2a3b +#define regCP_GFX_RS64_GP5_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_LO 0x2a3c +#define regCP_GFX_RS64_GP6_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_HI 0x2a3d +#define regCP_GFX_RS64_GP6_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_LO 0x2a3e +#define regCP_GFX_RS64_GP7_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_HI 0x2a3f +#define regCP_GFX_RS64_GP7_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_LO 0x2a40 +#define regCP_GFX_RS64_GP8_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_HI 0x2a41 +#define regCP_GFX_RS64_GP8_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_LO 0x2a42 +#define regCP_GFX_RS64_GP9_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_HI 0x2a43 +#define regCP_GFX_RS64_GP9_HI_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR0 0x2a44 +#define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR1 0x2a45 +#define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT0 0x2a46 +#define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT1 0x2a47 +#define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0 0x2a49 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK0 0x2a4a +#define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0 0x2a4b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE0 0x2a4c +#define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK0 0x2a4d +#define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0 0x2a4e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE0 0x2a4f +#define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0 0x2a50 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0 0x2a51 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0 0x2a52 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0 0x2a53 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0 0x2a54 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0 0x2a55 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0 0x2a56 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0 0x2a57 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0 0x2a58 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0 0x2a59 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0 0x2a5a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE0 0x2a5b +#define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK0 0x2a5c +#define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0 0x2a5d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE0 0x2a5e +#define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK0 0x2a5f +#define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0 0x2a60 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0 0x2a61 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0 0x2a62 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0 0x2a63 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0 0x2a64 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0 0x2a65 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0 0x2a66 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0 0x2a67 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0 0x2a68 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0 0x2a69 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE0 0x2a6a +#define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK0 0x2a6b +#define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0 0x2a6c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE0 0x2a6d +#define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK0 0x2a6e +#define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0 0x2a6f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0 0x2a70 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0 0x2a71 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0 0x2a72 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0 0x2a73 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0 0x2a74 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0 0x2a75 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0 0x2a76 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0 0x2a77 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0 0x2a78 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1 0x2a79 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK1 0x2a7a +#define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1 0x2a7b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE1 0x2a7c +#define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK1 0x2a7d +#define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1 0x2a7e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE1 0x2a7f +#define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1 0x2a80 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1 0x2a81 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1 0x2a82 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1 0x2a83 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1 0x2a84 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1 0x2a85 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1 0x2a86 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1 0x2a87 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1 0x2a88 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1 0x2a89 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1 0x2a8a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE1 0x2a8b +#define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK1 0x2a8c +#define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1 0x2a8d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE1 0x2a8e +#define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK1 0x2a8f +#define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1 0x2a90 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1 0x2a91 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1 0x2a92 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1 0x2a93 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1 0x2a94 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1 0x2a95 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1 0x2a96 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1 0x2a97 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1 0x2a98 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1 0x2a99 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE1 0x2a9a +#define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK1 0x2a9b +#define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1 0x2a9c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE1 0x2a9d +#define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK1 0x2a9e +#define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1 0x2a9f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1 0x2aa0 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1 0x2aa1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1 0x2aa2 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1 0x2aa3 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1 0x2aa4 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1 0x2aa5 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1 0x2aa6 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1 0x2aa7 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1 0x2aa8 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX 1 +#define regCP_ME_RS64_EXCEPTION_STATUS 0x2aaa +#define regCP_ME_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT1 0x2aac +#define regCP_GFX_RS64_INTERRUPT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_chdec +// base address: 0x33600 +#define regCH_ARB_CTRL 0x2d80 +#define regCH_ARB_CTRL_BASE_IDX 1 +#define regCH_DRAM_BURST_MASK 0x2d82 +#define regCH_DRAM_BURST_MASK_BASE_IDX 1 +#define regCH_ARB_STATUS 0x2d83 +#define regCH_ARB_STATUS_BASE_IDX 1 +#define regCH_DRAM_BURST_CTRL 0x2d84 +#define regCH_DRAM_BURST_CTRL_BASE_IDX 1 +#define regCHA_CHC_CREDITS 0x2d88 +#define regCHA_CHC_CREDITS_BASE_IDX 1 +#define regCHA_CLIENT_FREE_DELAY 0x2d89 +#define regCHA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regCHI_CHR_REP_FGCG_OVERRIDE 0x2d8c +#define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regCHC_CTRL 0x2dc0 +#define regCHC_CTRL_BASE_IDX 1 +#define regCHC_STATUS 0x2dc1 +#define regCHC_STATUS_BASE_IDX 1 +#define regCHC_STATUS2 0x2dc3 +#define regCHC_STATUS2_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_glarbdec +// base address: 0x33c00 +#define regGLARB_ARB_CTRL 0x2f00 +#define regGLARB_ARB_CTRL_BASE_IDX 1 +#define regGLARB_DRAM_BURST_MASK 0x2f02 +#define regGLARB_DRAM_BURST_MASK_BASE_IDX 1 +#define regGLARB_ARB_STATUS 0x2f03 +#define regGLARB_ARB_STATUS_BASE_IDX 1 +#define regGLARB_DRAM_BURST_CTRL 0x2f04 +#define regGLARB_DRAM_BURST_CTRL_BASE_IDX 1 +#define regGLARBA_GLARBC_CREDITS 0x2f08 +#define regGLARBA_GLARBC_CREDITS_BASE_IDX 1 +#define regGLARBA_CLIENT_FREE_DELAY 0x2f09 +#define regGLARBA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regGLARBI_GLARBR_REP_FGCG_OVERRIDE 0x2f0c +#define regGLARBI_GLARBR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGLARBC_CTRL 0x2f40 +#define regGLARBC_CTRL_BASE_IDX 1 +#define regGLARBC_STATUS 0x2f41 +#define regGLARBC_STATUS_BASE_IDX 1 +#define regGLARBC_CTRL2 0x2f42 +#define regGLARBC_CTRL2_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfddec +// base address: 0x34000 +#define regCPG_PERFCOUNTER1_LO 0x3000 +#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER1_HI 0x3001 +#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_LO 0x3002 +#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_HI 0x3003 +#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_LO 0x3004 +#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_HI 0x3005 +#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_LO 0x3006 +#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_HI 0x3007 +#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_LO 0x3008 +#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_HI 0x3009 +#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_LO 0x300a +#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_HI 0x300b +#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_LATENCY_STATS_DATA 0x300c +#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPG_LATENCY_STATS_DATA 0x300d +#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPC_LATENCY_STATS_DATA 0x300e +#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_LO 0x3040 +#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_HI 0x3041 +#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_LO 0x3043 +#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_HI 0x3044 +#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_LO 0x30a4 +#define regGE1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_HI 0x30a5 +#define regGE1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_LO 0x30a6 +#define regGE1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_HI 0x30a7 +#define regGE1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_LO 0x30a8 +#define regGE1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_HI 0x30a9 +#define regGE1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_LO 0x30aa +#define regGE1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_HI 0x30ab +#define regGE1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_LO 0x30ac +#define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_HI 0x30ad +#define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_LO 0x30ae +#define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_HI 0x30af +#define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_LO 0x30b0 +#define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_HI 0x30b1 +#define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_LO 0x30b2 +#define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_HI 0x30b3 +#define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_LO 0x3270 +#define regGC_EA_CPWD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_HI 0x3271 +#define regGC_EA_CPWD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER1_LO 0x3272 +#define regGC_EA_CPWD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER1_HI 0x3273 +#define regGC_EA_CPWD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_LO 0x33c0 +#define regCHC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_HI 0x33c1 +#define regCHC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_LO 0x33c2 +#define regCHC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_HI 0x33c3 +#define regCHC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_LO 0x33c4 +#define regCHC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_HI 0x33c5 +#define regCHC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_LO 0x33c6 +#define regCHC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_HI 0x33c7 +#define regCHC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_LO 0x33e0 +#define regGLARBA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_HI 0x33e1 +#define regGLARBA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_LO 0x33e2 +#define regGLARBA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_HI 0x33e3 +#define regGLARBA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_LO 0x33e4 +#define regGLARBA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_HI 0x33e5 +#define regGLARBA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_LO 0x33e6 +#define regGLARBA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_HI 0x33e7 +#define regGLARBA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_LO 0x33f0 +#define regGLARBC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_HI 0x33f1 +#define regGLARBC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_LO 0x33f2 +#define regGLARBC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_HI 0x33f3 +#define regGLARBC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_LO 0x33f4 +#define regGLARBC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_HI 0x33f5 +#define regGLARBC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_LO 0x33f6 +#define regGLARBC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_HI 0x33f7 +#define regGLARBC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_LO 0x3480 +#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_HI 0x3481 +#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_LO 0x3482 +#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_HI 0x3483 +#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_LO 0x3520 +#define regGCR_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_HI 0x3521 +#define regGCR_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_LO 0x3522 +#define regGCR_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_HI 0x3523 +#define regGCR_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_LO 0x3600 +#define regCHA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_HI 0x3601 +#define regCHA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_LO 0x3602 +#define regCHA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_HI 0x3603 +#define regCHA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_LO 0x3604 +#define regCHA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_HI 0x3605 +#define regCHA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_LO 0x3606 +#define regCHA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_HI 0x3607 +#define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec +// base address: 0x36000 +#define regCPG_PERFCOUNTER1_SELECT 0x3800 +#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT1 0x3801 +#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT 0x3802 +#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_SELECT 0x3803 +#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT1 0x3804 +#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_SELECT 0x3805 +#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT1 0x3806 +#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT 0x3807 +#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCP_PERFMON_CNTL 0x3808 +#define regCP_PERFMON_CNTL_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT 0x3809 +#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPF_LATENCY_STATS_SELECT 0x380c +#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPG_LATENCY_STATS_SELECT 0x380d +#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_LATENCY_STATS_SELECT 0x380e +#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT 0x380f +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT 0x3810 +#define regCP_DRAW_OBJECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT_COUNTER 0x3811 +#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define regCP_DRAW_WINDOW_MASK_HI 0x3812 +#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_HI 0x3813 +#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_LO 0x3814 +#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define regCP_DRAW_WINDOW_CNTL 0x3815 +#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT 0x3840 +#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT 0x3841 +#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT_HI 0x384d +#define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT_HI 0x384e +#define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT 0x38a4 +#define regGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT1 0x38a5 +#define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT 0x38a6 +#define regGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT1 0x38a7 +#define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT 0x38a8 +#define regGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT1 0x38a9 +#define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT 0x38aa +#define regGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT1 0x38ab +#define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT 0x38ac +#define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad +#define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT 0x38ae +#define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT1 0x38af +#define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 +#define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 +#define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 +#define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT 0x3a20 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT1 0x3a21 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER1_SELECT 0x3a22 +#define regGC_EA_CPWD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT 0x3bc0 +#define regCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT1 0x3bc1 +#define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_SELECT 0x3bc2 +#define regCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_SELECT1 0x3bc3 +#define regCHC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_SELECT 0x3bc4 +#define regCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_SELECT1 0x3bc5 +#define regCHC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_SELECT 0x3bc6 +#define regCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_SELECT1 0x3bc7 +#define regCHC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_SELECT 0x3be0 +#define regGLARBA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_SELECT1 0x3be1 +#define regGLARBA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_SELECT 0x3be2 +#define regGLARBA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_SELECT1 0x3be3 +#define regGLARBA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_SELECT 0x3be4 +#define regGLARBA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_SELECT1 0x3be5 +#define regGLARBA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_SELECT 0x3be6 +#define regGLARBA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_SELECT1 0x3be7 +#define regGLARBA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_SELECT 0x3bf0 +#define regGLARBC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_SELECT1 0x3bf1 +#define regGLARBC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_SELECT 0x3bf2 +#define regGLARBC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_SELECT1 0x3bf3 +#define regGLARBC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_SELECT 0x3bf4 +#define regGLARBC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_SELECT1 0x3bf5 +#define regGLARBC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_SELECT 0x3bf6 +#define regGLARBC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_SELECT1 0x3bf7 +#define regGLARBC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regRLC_SPM_PERFMON_CNTL 0x3c80 +#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define regRLC_SPM_RING_WRPTR 0x3c84 +#define regRLC_SPM_RING_WRPTR_BASE_IDX 1 +#define regRLC_SPM_RING_RDPTR 0x3c85 +#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c86 +#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c87 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c88 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c89 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c8a +#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_DATA 0x3c8b +#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_0 0x3c8c +#define regRLC_SPM_SE_USER_DATA_0_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_1 0x3c8d +#define regRLC_SPM_SE_USER_DATA_1_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_2 0x3c8e +#define regRLC_SPM_SE_USER_DATA_2_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_3 0x3c8f +#define regRLC_SPM_SE_USER_DATA_3_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_ADDR 0x3c92 +#define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_DATA 0x3c93 +#define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3c94 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3c95 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c96 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c97 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3c98 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 +#define regRLC_SPM_ACCUM_STATUS 0x3c99 +#define regRLC_SPM_ACCUM_STATUS_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRL 0x3c9a +#define regRLC_SPM_ACCUM_CTRL_BASE_IDX 1 +#define regRLC_SPM_ACCUM_MODE 0x3c9b +#define regRLC_SPM_ACCUM_MODE_BASE_IDX 1 +#define regRLC_SPM_ACCUM_THRESHOLD 0x3c9c +#define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3c9f +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 +#define regRLC_SPM_PAUSE 0x3ca2 +#define regRLC_SPM_PAUSE_BASE_IDX 1 +#define regRLC_SPM_STATUS 0x3ca3 +#define regRLC_SPM_STATUS_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca4 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca5 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 +#define regRLC_SPM_GTS_TRIGGER_VALUE_LO 0x3ca6 +#define regRLC_SPM_GTS_TRIGGER_VALUE_LO_BASE_IDX 1 +#define regRLC_SPM_GTS_TRIGGER_VALUE_HI 0x3ca7 +#define regRLC_SPM_GTS_TRIGGER_VALUE_HI_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_0 0x3ca8 +#define regRLC_SPM_GLOBAL_USER_DATA_0_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_1 0x3ca9 +#define regRLC_SPM_GLOBAL_USER_DATA_1_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_2 0x3caa +#define regRLC_SPM_GLOBAL_USER_DATA_2_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_3 0x3cab +#define regRLC_SPM_GLOBAL_USER_DATA_3_BASE_IDX 1 +#define regRLC_SPM_MODE 0x3cad +#define regRLC_SPM_MODE_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_DATA 0x3cae +#define regRLC_SPM_RSPM_REQ_DATA_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_OP 0x3cb0 +#define regRLC_SPM_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_DATA 0x3cb1 +#define regRLC_SPM_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_OP 0x3cb2 +#define regRLC_SPM_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_DATA 0x3cb3 +#define regRLC_SPM_SE_RSPM_REQ_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_OP 0x3cb5 +#define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_DATA 0x3cb6 +#define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_OP 0x3cb7 +#define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD 0x3cb8 +#define regRLC_SPM_RSPM_CMD_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD_ACK 0x3cb9 +#define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX 1 +#define regRLC_SPM_SPARE 0x3cbf +#define regRLC_SPM_SPARE_BASE_IDX 1 +#define regRLC_PERFMON_CNTL 0x3cc0 +#define regRLC_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT 0x3d60 +#define regGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT1 0x3d61 +#define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_SELECT 0x3d62 +#define regGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_SELECT1 0x3d63 +#define regGCR_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT 0x3de0 +#define regCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT1 0x3de1 +#define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_SELECT 0x3de2 +#define regCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_SELECT1 0x3de3 +#define regCHA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_SELECT 0x3de4 +#define regCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_SELECT1 0x3de5 +#define regCHA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_SELECT 0x3de6 +#define regCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_SELECT1 0x3de7 +#define regCHA_PERFCOUNTER3_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk +// base address: 0x3a014 +#define regXVMIN_XVMIN_WR_DATA 0x4806 +#define regXVMIN_XVMIN_WR_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_hypdec +// base address: 0x3e000 +#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define regRLC_FED_DRVR_STATUS 0x5b04 +#define regRLC_FED_DRVR_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG6 0x5b06 +#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define regRLC_SDMA0_STATUS 0x5b18 +#define regRLC_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_STATUS 0x5b19 +#define regRLC_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_STATUS 0x5b1a +#define regRLC_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_STATUS 0x5b1b +#define regRLC_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_SDMA0_BUSY_STATUS 0x5b1c +#define regRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_BUSY_STATUS 0x5b1d +#define regRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_BUSY_STATUS 0x5b1e +#define regRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_BUSY_STATUS 0x5b1f +#define regRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG8 0x5b20 +#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_MASK 0x5b2d +#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_0 0x5b2e +#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_1 0x5b2f +#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_BUSY_CLK_CNTL 0x5b30 +#define regRLC_BUSY_CLK_CNTL_BASE_IDX 1 +#define regRLC_CLK_CNTL 0x5b31 +#define regRLC_CLK_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG1 0x5b35 +#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG2 0x5b36 +#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_0 0x5b38 +#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_3 0x5b3a +#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_1 0x5b3b +#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_2 0x5b3c +#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define regRLC_IH_COOKIE 0x5b41 +#define regRLC_IH_COOKIE_BASE_IDX 1 +#define regRLC_IH_COOKIE_CNTL 0x5b42 +#define regRLC_IH_COOKIE_CNTL_BASE_IDX 1 +#define regRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 +#define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a +#define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c +#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 +#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_2 0x5b52 +#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_3 0x5b53 +#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPM_UCODE_ADDR 0x5b60 +#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPM_UCODE_DATA 0x5b61 +#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_IRAM_ADDR 0x5b62 +#define regRLC_GPM_IRAM_ADDR_BASE_IDX 1 +#define regRLC_GPM_IRAM_DATA 0x5b63 +#define regRLC_GPM_IRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_DRAM_ADDR 0x5b68 +#define regRLC_LX6_DRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_DRAM_DATA 0x5b69 +#define regRLC_LX6_DRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_IRAM_ADDR 0x5b6a +#define regRLC_LX6_IRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_IRAM_DATA 0x5b6b +#define regRLC_LX6_IRAM_DATA_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_ADDR 0x5b6e +#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_DATA 0x5b6f +#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_SRM_DRAM_ADDR 0x5b71 +#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_DRAM_DATA 0x5b72 +#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define regRLC_SRM_ARAM_ADDR 0x5b73 +#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_ARAM_DATA 0x5b74 +#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define regRLC_GTS_OFFSET_LSB 0x5b79 +#define regRLC_GTS_OFFSET_LSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_MSB 0x5b7a +#define regRLC_GTS_OFFSET_MSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_SNAP_LSB 0x5b7b +#define regRLC_GTS_OFFSET_SNAP_LSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_SNAP_MSB 0x5b7c +#define regRLC_GTS_OFFSET_SNAP_MSB_BASE_IDX 1 +#define regRLC_GAP_PWROK 0x5b7d +#define regRLC_GAP_PWROK_BASE_IDX 1 +#define regRLC_GAP_PWROK_COUNT 0x5b7e +#define regRLC_GAP_PWROK_COUNT_BASE_IDX 1 +#define regGLARB_HASH_CFG 0x5b87 +#define regGLARB_HASH_CFG_BASE_IDX 1 +#define regCH_PIPE_STEER 0x5b88 +#define regCH_PIPE_STEER_BASE_IDX 1 +#define regGLARB_PIPE_STEER_LSB 0x5b89 +#define regGLARB_PIPE_STEER_LSB_BASE_IDX 1 +#define regGLARB_PIPE_STEER_MSB 0x5b8a +#define regGLARB_PIPE_STEER_MSB_BASE_IDX 1 +#define regCH_HASH_CFG 0x5b8b +#define regCH_HASH_CFG_BASE_IDX 1 +#define regGLARB_LPDDR_PIPE_STEER_LSB 0x5b8c +#define regGLARB_LPDDR_PIPE_STEER_LSB_BASE_IDX 1 +#define regGLARB_LPDDR_PIPE_STEER_MSB 0x5b8d +#define regGLARB_LPDDR_PIPE_STEER_MSB_BASE_IDX 1 +#define regGLARB_LOCAL_CAC 0x5b8e +#define regGLARB_LOCAL_CAC_BASE_IDX 1 +#define regGLARB_AID_SEL_CFG 0x5b8f +#define regGLARB_AID_SEL_CFG_BASE_IDX 1 +#define regGC_USER_FULL_SA_UNIT_DISABLE 0x5b91 +#define regGC_USER_FULL_SA_UNIT_DISABLE_BASE_IDX 1 +#define regGC_USER_SA_UNIT_DISABLE 0x5b92 +#define regGC_USER_SA_UNIT_DISABLE_BASE_IDX 1 +#define regGC_USER_HBM_DISABLE 0x5b93 +#define regGC_USER_HBM_DISABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 +#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 +#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 +#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 +#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 +#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 +#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 +#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 +#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cphypdec +// base address: 0x3e000 +#define regCP_HYP_CONTEXT_RANGE_BASE 0x580a +#define regCP_HYP_CONTEXT_RANGE_BASE_BASE_IDX 1 +#define regCP_HYP_CONTEXT_RANGE_END 0x580b +#define regCP_HYP_CONTEXT_RANGE_END_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_ADDR 0x5814 +#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_PFP_UCODE_ADDR 0x5814 +#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_DATA 0x5815 +#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_UCODE_DATA 0x5815 +#define regCP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_ADDR 0x5816 +#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define regCP_ME_RAM_RADDR 0x5816 +#define regCP_ME_RAM_RADDR_BASE_IDX 1 +#define regCP_ME_RAM_WADDR 0x5816 +#define regCP_ME_RAM_WADDR_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_DATA 0x5817 +#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define regCP_ME_RAM_DATA 0x5817 +#define regCP_ME_RAM_DATA_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_ADDR 0x581a +#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_ADDR 0x581a +#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_DATA 0x581b +#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_DATA 0x581b +#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_CHKSUM 0x581e +#define regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_CHKSUM 0x5820 +#define regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_MEC_ME1_UCODE_CHKSUM 0x5821 +#define regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_PFP_IC_BASE_LO 0x5840 +#define regCP_PFP_IC_BASE_LO_BASE_IDX 1 +#define regCP_PFP_IC_BASE_HI 0x5841 +#define regCP_PFP_IC_BASE_HI_BASE_IDX 1 +#define regCP_PFP_IC_BASE_CNTL 0x5842 +#define regCP_PFP_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_PFP_IC_OP_CNTL 0x5843 +#define regCP_PFP_IC_OP_CNTL_BASE_IDX 1 +#define regCP_ME_IC_BASE_LO 0x5844 +#define regCP_ME_IC_BASE_LO_BASE_IDX 1 +#define regCP_ME_IC_BASE_HI 0x5845 +#define regCP_ME_IC_BASE_HI_BASE_IDX 1 +#define regCP_ME_IC_BASE_CNTL 0x5846 +#define regCP_ME_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_ME_IC_OP_CNTL 0x5847 +#define regCP_ME_IC_OP_CNTL_BASE_IDX 1 +#define regCP_CPC_IC_BASE_LO 0x584c +#define regCP_CPC_IC_BASE_LO_BASE_IDX 1 +#define regCP_CPC_IC_BASE_HI 0x584d +#define regCP_CPC_IC_BASE_HI_BASE_IDX 1 +#define regCP_CPC_IC_BASE_CNTL 0x584e +#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_IC_BASE_LO 0x5850 +#define regCP_MES_IC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MIBASE_LO 0x5850 +#define regCP_MES_MIBASE_LO_BASE_IDX 1 +#define regCP_MES_IC_BASE_HI 0x5851 +#define regCP_MES_IC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MIBASE_HI 0x5851 +#define regCP_MES_MIBASE_HI_BASE_IDX 1 +#define regCP_MES_IC_BASE_CNTL 0x5852 +#define regCP_MES_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_BASE_LO 0x5854 +#define regCP_MES_DC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MDBASE_LO 0x5854 +#define regCP_MES_MDBASE_LO_BASE_IDX 1 +#define regCP_MES_DC_BASE_HI 0x5855 +#define regCP_MES_DC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MDBASE_HI 0x5855 +#define regCP_MES_MDBASE_HI_BASE_IDX 1 +#define regCP_MES_MIBOUND_LO 0x585b +#define regCP_MES_MIBOUND_LO_BASE_IDX 1 +#define regCP_MES_MIBOUND_HI 0x585c +#define regCP_MES_MIBOUND_HI_BASE_IDX 1 +#define regCP_MES_MDBOUND_LO 0x585d +#define regCP_MES_MDBOUND_LO_BASE_IDX 1 +#define regCP_MES_MDBOUND_HI 0x585e +#define regCP_MES_MDBOUND_HI_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_VERS 0x5861 +#define regCP_HYP_PFP_UCODE_VERS_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_VERS 0x5862 +#define regCP_HYP_ME_UCODE_VERS_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_LO 0x5863 +#define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_LO 0x5864 +#define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_HI 0x5865 +#define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_HI 0x5866 +#define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_LO 0x586c +#define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_HI 0x586d +#define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_LO 0x5870 +#define regCP_MEC_DC_BASE_LO_BASE_IDX 1 +#define regCP_MEC_MDBASE_LO 0x5870 +#define regCP_MEC_MDBASE_LO_BASE_IDX 1 +#define regCP_MEC_DC_BASE_HI 0x5871 +#define regCP_MEC_DC_BASE_HI_BASE_IDX 1 +#define regCP_MEC_MDBASE_HI 0x5871 +#define regCP_MEC_MDBASE_HI_BASE_IDX 1 +#define regCP_MEC_MIBOUND_LO 0x5872 +#define regCP_MEC_MIBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MIBOUND_HI 0x5873 +#define regCP_MEC_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_MDBOUND_LO 0x5874 +#define regCP_MEC_MDBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MDBOUND_HI 0x5875 +#define regCP_MEC_MDBOUND_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbm_hypdec +// base address: 0x3eea0 +#define regGRBM_GFX_INDEX_SR_SELECT 0x5ba8 +#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_DATA 0x5ba9 +#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_SELECT 0x5baa +#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_DATA 0x5bab +#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define regGC_IH_COOKIE_0_PTR_HIGH 0x5bac +#define regGC_IH_COOKIE_0_PTR_HIGH_BASE_IDX 1 +#define regGC_IH_COOKIE_0_PTR 0x5baf +#define regGC_IH_COOKIE_0_PTR_BASE_IDX 1 +#define regGRBM_SE_REMAP_CNTL 0x5bb0 +#define regGRBM_SE_REMAP_CNTL_BASE_IDX 1 +#define regGRBM_SA_REMAP_CNTL 0x5bb1 +#define regGRBM_SA_REMAP_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcdec +// base address: 0x3b000 +#define regRLC_CNTL 0x4c00 +#define regRLC_CNTL_BASE_IDX 1 +#define regRLC_F32_UCODE_VERSION 0x4c03 +#define regRLC_F32_UCODE_VERSION_BASE_IDX 1 +#define regRLC_STAT 0x4c04 +#define regRLC_STAT_BASE_IDX 1 +#define regRLC_ACTIVE_MASK 0x4c05 +#define regRLC_ACTIVE_MASK_BASE_IDX 1 +#define regRLC_GFX_SE_STATUS 0x4c06 +#define regRLC_GFX_SE_STATUS_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_0 0x4c0e +#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_1 0x4c0f +#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_2 0x4c10 +#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_3 0x4c11 +#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_4 0x4c12 +#define regRLC_GPM_TIMER_INT_4_BASE_IDX 1 +#define regRLC_GPM_TIMER_CTRL 0x4c13 +#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define regRLC_GPM_TIMER_STAT 0x4c14 +#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_STAT 0x4c16 +#define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_CLEAR 0x4c17 +#define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 +#define regRLC_INT_STAT 0x4c18 +#define regRLC_INT_STAT_BASE_IDX 1 +#define regRLC_MGCG_CTRL 0x4c1a +#define regRLC_MGCG_CTRL_BASE_IDX 1 +#define regRLC_MCA_DF_RASINTRCTRL_REG_CTRL 0x4c1c +#define regRLC_MCA_DF_RASINTRCTRL_REG_CTRL_BASE_IDX 1 +#define regRLC_JUMP_TABLE_RESTORE 0x4c1e +#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define regRLC_PG_DELAY_2 0x4c1f +#define regRLC_PG_DELAY_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define regRLC_UCODE_CNTL 0x4c27 +#define regRLC_UCODE_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_RESET 0x4c28 +#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define regRLC_GPM_THREAD_INVALIDATE_CACHE 0x4c2b +#define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX 1 +#define regRLC_MCA_DF_RASINTRCTRL_REG_LO 0x4c2c +#define regRLC_MCA_DF_RASINTRCTRL_REG_LO_BASE_IDX 1 +#define regRLC_MCA_DF_RASINTRCTRL_REG_HI 0x4c2d +#define regRLC_MCA_DF_RASINTRCTRL_REG_HI_BASE_IDX 1 +#define regRLC_MCA_INTR_CTRL 0x4c2e +#define regRLC_MCA_INTR_CTRL_BASE_IDX 1 +#define regRLC_MCA_INTR_INFO 0x4c2f +#define regRLC_MCA_INTR_INFO_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 +#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 +#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 +#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 +#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_CTRL 0x4c34 +#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 +#define regRLC_CLK_COUNT_STAT 0x4c35 +#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_CNTL 0x4c36 +#define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_STAT 0x4c37 +#define regRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 +#define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 +#define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a +#define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b +#define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c +#define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d +#define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e +#define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f +#define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32 0x4c42 +#define regRLC_GPU_CLOCK_32_BASE_IDX 1 +#define regRLC_PG_CNTL 0x4c43 +#define regRLC_PG_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_PRIORITY 0x4c44 +#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define regRLC_GPM_THREAD_ENABLE 0x4c45 +#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_RANGE 0x4c47 +#define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL 0x4c49 +#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL 0x4c4a +#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define regRLC_DYN_PG_STATUS 0x4c4b +#define regRLC_DYN_PG_STATUS_BASE_IDX 1 +#define regRLC_DYN_PG_REQUEST 0x4c4c +#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define regRLC_PG_DELAY 0x4c4d +#define regRLC_PG_DELAY_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL_2 0x4c4e +#define regRLC_CGCG_CGLS_CTRL_2_BASE_IDX 1 +#define regRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 +#define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 +#define regRLC_MAX_PG_WGP 0x4c54 +#define regRLC_MAX_PG_WGP_BASE_IDX 1 +#define regRLC_AUTO_PG_CTRL 0x4c55 +#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define regRLC_SERDES_RD_INDEX 0x4c59 +#define regRLC_SERDES_RD_INDEX_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_0 0x4c5a +#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_1 0x4c5b +#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_2 0x4c5c +#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_3 0x4c5d +#define regRLC_SERDES_RD_DATA_3_BASE_IDX 1 +#define regRLC_SERDES_MASK 0x4c5e +#define regRLC_SERDES_MASK_BASE_IDX 1 +#define regRLC_SERDES_CTRL 0x4c5f +#define regRLC_SERDES_CTRL_BASE_IDX 1 +#define regRLC_SERDES_DATA 0x4c60 +#define regRLC_SERDES_DATA_BASE_IDX 1 +#define regRLC_SERDES_BUSY 0x4c61 +#define regRLC_SERDES_BUSY_BASE_IDX 1 +#define regRLC_GPM_GENERAL_0 0x4c63 +#define regRLC_GPM_GENERAL_0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_1 0x4c64 +#define regRLC_GPM_GENERAL_1_BASE_IDX 1 +#define regRLC_GPM_GENERAL_2 0x4c65 +#define regRLC_GPM_GENERAL_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_3 0x4c66 +#define regRLC_GPM_GENERAL_3_BASE_IDX 1 +#define regRLC_GPM_GENERAL_4 0x4c67 +#define regRLC_GPM_GENERAL_4_BASE_IDX 1 +#define regRLC_GPM_GENERAL_5 0x4c68 +#define regRLC_GPM_GENERAL_5_BASE_IDX 1 +#define regRLC_GPM_GENERAL_6 0x4c69 +#define regRLC_GPM_GENERAL_6_BASE_IDX 1 +#define regRLC_GPM_GENERAL_7 0x4c6a +#define regRLC_GPM_GENERAL_7_BASE_IDX 1 +#define regRLC_STATIC_PG_STATUS 0x4c6e +#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define regRLC_GPM_GENERAL_16 0x4c76 +#define regRLC_GPM_GENERAL_16_BASE_IDX 1 +#define regRLC_PG_DELAY_3 0x4c78 +#define regRLC_PG_DELAY_3_BASE_IDX 1 +#define regRLC_GPR_REG1 0x4c79 +#define regRLC_GPR_REG1_BASE_IDX 1 +#define regRLC_GPR_REG2 0x4c7a +#define regRLC_GPR_REG2_BASE_IDX 1 +#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_DISABLE 0x4c7d +#define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH0 0x4c7e +#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define regRLC_SRM_CNTL 0x4c80 +#define regRLC_SRM_CNTL_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define regRLC_SRM_STAT 0x4c9b +#define regRLC_SRM_STAT_BASE_IDX 1 +#define regRLC_LX6_UTCL1_ERROR_2 0x4ca8 +#define regRLC_LX6_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_8 0x4cad +#define regRLC_GPM_GENERAL_8_BASE_IDX 1 +#define regRLC_GPM_GENERAL_9 0x4cae +#define regRLC_GPM_GENERAL_9_BASE_IDX 1 +#define regRLC_GPM_GENERAL_10 0x4caf +#define regRLC_GPM_GENERAL_10_BASE_IDX 1 +#define regRLC_GPM_GENERAL_11 0x4cb0 +#define regRLC_GPM_GENERAL_11_BASE_IDX 1 +#define regRLC_GPM_GENERAL_12 0x4cb1 +#define regRLC_GPM_GENERAL_12_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define regRLC_SPM_UTCL1_CNTL 0x4cb5 +#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_UTCL1_STATUS_2 0x4cb6 +#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_0 0x4cc7 +#define regRLC_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_SEMAPHORE_1 0x4cc8 +#define regRLC_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_SEMAPHORE_2 0x4cc9 +#define regRLC_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_3 0x4cca +#define regRLC_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_SRM_UTCL1_CNTL 0x4ccc +#define regRLC_SRM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_SRM_UTCL1_ERROR_1 0x4ccd +#define regRLC_SRM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SRM_UTCL1_ERROR_2 0x4cce +#define regRLC_SRM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_DLG_UTCL1_ERROR_2 0x4cd1 +#define regRLC_DLG_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_UTCL1_STATUS 0x4cd4 +#define regRLC_UTCL1_STATUS_BASE_IDX 1 +#define regRLC_R2I_CNTL_0 0x4cd5 +#define regRLC_R2I_CNTL_0_BASE_IDX 1 +#define regRLC_R2I_CNTL_1 0x4cd6 +#define regRLC_R2I_CNTL_1_BASE_IDX 1 +#define regRLC_R2I_CNTL_2 0x4cd7 +#define regRLC_R2I_CNTL_2_BASE_IDX 1 +#define regRLC_R2I_CNTL_3 0x4cd8 +#define regRLC_R2I_CNTL_3_BASE_IDX 1 +#define regRLC_GPM_INT_STAT_TH0 0x4cdc +#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_13 0x4cdd +#define regRLC_GPM_GENERAL_13_BASE_IDX 1 +#define regRLC_GPM_GENERAL_14 0x4cde +#define regRLC_GPM_GENERAL_14_BASE_IDX 1 +#define regRLC_GPM_GENERAL_15 0x4cdf +#define regRLC_GPM_GENERAL_15_BASE_IDX 1 +#define regRLC_LX6_UTCL1_ERROR_1 0x4ce3 +#define regRLC_LX6_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_LX6_UTCL1_CNTL 0x4ce4 +#define regRLC_LX6_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_DMA_UTCL1_ERROR_1 0x4ce6 +#define regRLC_DMA_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_DMA_UTCL1_ERROR_2 0x4ce7 +#define regRLC_DMA_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb +#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec +#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_RANGE 0x4cf0 +#define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_CNTL 0x4cf1 +#define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_STAT 0x4cf2 +#define regRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 +#define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 +#define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 +#define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 +#define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 +#define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 +#define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 +#define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa +#define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4cfb +#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4cfc +#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT 0x4d00 +#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 +#define regRLC_SMU_CLK_REQ 0x4d08 +#define regRLC_SMU_CLK_REQ_BASE_IDX 1 +#define regRLC_SPARE 0x4d0b +#define regRLC_SPARE_BASE_IDX 1 +#define regRLC_SPP_CTRL 0x4d0c +#define regRLC_SPP_CTRL_BASE_IDX 1 +#define regRLC_SPP_SHADER_PROFILE_EN 0x4d0d +#define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_CAPTURE_EN 0x4d0e +#define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_0 0x4d0f +#define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_1 0x4d10 +#define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_2 0x4d11 +#define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 +#define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_DATA 0x4d13 +#define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_1 0x4d18 +#define regRLC_SPP_PROF_INFO_1_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_2 0x4d19 +#define regRLC_SPP_PROF_INFO_2_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID 0x4d1a +#define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b +#define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 +#define regRLC_SPP_STATUS 0x4d1c +#define regRLC_SPP_STATUS_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_0 0x4d1d +#define regRLC_SPP_PVT_STAT_0_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_1 0x4d1e +#define regRLC_SPP_PVT_STAT_1_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_2 0x4d1f +#define regRLC_SPP_PVT_STAT_2_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_3 0x4d20 +#define regRLC_SPP_PVT_STAT_3_BASE_IDX 1 +#define regRLC_SPP_PVT_LEVEL_MAX 0x4d21 +#define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 +#define regRLC_SPP_STALL_STATE_UPDATE 0x4d22 +#define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 +#define regRLC_SPP_PBB_INFO 0x4d23 +#define regRLC_SPP_PBB_INFO_BASE_IDX 1 +#define regRLC_SPP_RESET 0x4d24 +#define regRLC_SPP_RESET_BASE_IDX 1 +#define regRLC_CAC_MASK_CNTL 0x4d45 +#define regRLC_CAC_MASK_CNTL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL 0x4d48 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL 0x4d49 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_CNTR_CTRL 0x4d4a +#define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_CNTR_CTRL 0x4d4b +#define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_CNTR_CTRL 0x4d4c +#define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL 0x4d4d +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR 0x4d50 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR 0x4d51 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_EVENT_CNTR 0x4d52 +#define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR 0x4d53 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR 0x4d54 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR 0x4d55 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_REF_CNTR 0x4d58 +#define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_REF_CNTR 0x4d59 +#define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_REF_CNTR 0x4d5a +#define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_REF_CNTR 0x4d5b +#define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_REF_CNTR 0x4d5c +#define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_REF_CNTR 0x4d5d +#define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_CTRL 0x4d5e +#define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX 1 +#define regRLC_GFX_IH_ARBITER_STAT 0x4d5f +#define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L 0x4d60 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H 0x4d61 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT 0x4d62 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT 0x4d63 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR 0x4d64 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA 0x4d65 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_ADDR 0x4d66 +#define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_DATA 0x4d67 +#define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR 0x4d68 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA 0x4d69 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_BLK_EN_MASK_IND_ADDR 0x4d6a +#define regRLC_SPM_SE_BLK_EN_MASK_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_BLK_EN_MASK_IND_DATA 0x4d6b +#define regRLC_SPM_SE_BLK_EN_MASK_IND_DATA_BASE_IDX 1 +#define regRLC_GFX_IH_22BEAT_STAT 0x4d6c +#define regRLC_GFX_IH_22BEAT_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_ARBITER_STAT_22BEAT 0x4d6d +#define regRLC_GFX_IH_ARBITER_STAT_22BEAT_BASE_IDX 1 +#define regRLC_LX6_CNTL 0x4d80 +#define regRLC_LX6_CNTL_BASE_IDX 1 +#define regRLC_LX6_STATUS 0x4d81 +#define regRLC_LX6_STATUS_BASE_IDX 1 +#define regRLC_LX6_FW_STATUS 0x4dcb +#define regRLC_LX6_FW_STATUS_BASE_IDX 1 +#define regRLC_LX6_FW_VERSION 0x4dcc +#define regRLC_LX6_FW_VERSION_BASE_IDX 1 +#define regRLC_XT_CORE_STATUS 0x4dd4 +#define regRLC_XT_CORE_STATUS_BASE_IDX 1 +#define regRLC_XT_CORE_INTERRUPT 0x4dd5 +#define regRLC_XT_CORE_INTERRUPT_BASE_IDX 1 +#define regRLC_XT_CORE_FAULT_INFO 0x4dd6 +#define regRLC_XT_CORE_FAULT_INFO_BASE_IDX 1 +#define regRLC_XT_CORE_ALT_RESET_VEC 0x4dd7 +#define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX 1 +#define regRLC_XT_CORE_RESERVED 0x4dd8 +#define regRLC_XT_CORE_RESERVED_BASE_IDX 1 +#define regRLC_XT_INT_VEC_FORCE 0x4dd9 +#define regRLC_XT_INT_VEC_FORCE_BASE_IDX 1 +#define regRLC_XT_INT_VEC_CLEAR 0x4dda +#define regRLC_XT_INT_VEC_CLEAR_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_SEL 0x4ddb +#define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_INT_SEL 0x4ddc +#define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 +#define regRLC_SPM_THREAD_TRACE_CTRL 0x4de6 +#define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regRLC_SPP_CAM_ADDR 0x4de8 +#define regRLC_SPP_CAM_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_DATA 0x4de9 +#define regRLC_SPP_CAM_DATA_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_ADDR 0x4dea +#define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_DATA 0x4deb +#define regRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1 +#define regRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_STAT 0x4df2 +#define regRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_DATA_LSB 0x4df3 +#define regRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_DATA_MSB 0x4df4 +#define regRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX 1 +#define regRLC_XT_DOORBELL_RANGE 0x4df5 +#define regRLC_XT_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_XT_DOORBELL_CNTL 0x4df6 +#define regRLC_XT_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_XT_DOORBELL_STAT 0x4df7 +#define regRLC_XT_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_LO 0x4df8 +#define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_HI 0x4df9 +#define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_LO 0x4dfa +#define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_HI 0x4dfb +#define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_LO 0x4dfc +#define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_HI 0x4dfd +#define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_LO 0x4dfe +#define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_HI 0x4dff +#define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_MEM_SLP_CNTL 0x4e00 +#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define regRLC_RLCV_SAFE_MODE 0x4e02 +#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define regRLC_SMU_SAFE_MODE 0x4e03 +#define regRLC_SMU_SAFE_MODE_BASE_IDX 1 +#define regRLC_RLCV_COMMAND 0x4e04 +#define regRLC_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_SMU_MESSAGE 0x4e05 +#define regRLC_SMU_MESSAGE_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_1 0x4e06 +#define regRLC_SMU_MESSAGE_1_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_2 0x4e07 +#define regRLC_SMU_MESSAGE_2_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND 0x4e08 +#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define regRLC_SRM_GPM_ABORT 0x4e09 +#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define regRLC_SMU_COMMAND 0x4e0a +#define regRLC_SMU_COMMAND_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_1 0x4e0b +#define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_2 0x4e0c +#define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_3 0x4e0d +#define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_4 0x4e0e +#define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_5 0x4e0f +#define regRLC_SMU_ARGUMENT_5_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_HI 0x4e10 +#define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_LO 0x4e11 +#define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_SIZE 0x4e12 +#define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX 1 +#define regRLC_IMU_MISC 0x4e16 +#define regRLC_IMU_MISC_BASE_IDX 1 +#define regRLC_IMU_RESET_VECTOR 0x4e17 +#define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec +// base address: 0x3b980 +#define regRLC_RLCS_DEC_START 0x4e60 +#define regRLC_RLCS_DEC_START_BASE_IDX 1 +#define regRLC_RLCS_DEC_DUMP_ADDR 0x4e61 +#define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_1 0x4e62 +#define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_2 0x4e63 +#define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_3 0x4e64 +#define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_4 0x4e65 +#define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 +#define regRLC_RLCS_FENCE_CNTL 0x4e66 +#define regRLC_RLCS_FENCE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_CGCG_REQUEST 0x4e67 +#define regRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 +#define regRLC_RLCS_CGCG_STATUS 0x4e68 +#define regRLC_RLCS_CGCG_STATUS_BASE_IDX 1 +#define regRLC_RLCS_SOC_DS_CNTL 0x4e69 +#define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_CNTL 0x4e6a +#define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL 0x4e6b +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX 1 +#define regRLC_GPM_STAT 0x4e6c +#define regRLC_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT 0x4e6c +#define regRLC_RLCS_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6d +#define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 +#define regRLC_RLCS_IOV_CMD_STATUS 0x4e6e +#define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e6f +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 +#define regRLC_RLCS_IOV_SCH_BLOCK 0x4e70 +#define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e71 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT_2 0x4e72 +#define regRLC_RLCS_GPM_STAT_2_BASE_IDX 1 +#define regRLC_RLCS_GRBM_SOFT_RESET 0x4e73 +#define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_STATUS 0x4e74 +#define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_READ 0x4e75 +#define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 +#define regRLC_RLCS_IH_SEMAPHORE 0x4e76 +#define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e77 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_1 0x4e78 +#define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_2 0x4e79 +#define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_1 0x4e7a +#define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_2 0x4e7b +#define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_CTRL 0x4e7c +#define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_1 0x4e7d +#define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_2 0x4e7e +#define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_DSM_TRIG 0x4e7f +#define regRLC_RLCS_DSM_TRIG_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_STATUS 0x4e80 +#define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4e81 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4e82 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 +#define regRLC_RLCS_CMP_IDLE_CNTL 0x4e83 +#define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_0 0x4e84 +#define regRLC_RLCS_GENERAL_0_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_1 0x4e85 +#define regRLC_RLCS_GENERAL_1_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_2 0x4e86 +#define regRLC_RLCS_GENERAL_2_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_3 0x4e87 +#define regRLC_RLCS_GENERAL_3_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_4 0x4e88 +#define regRLC_RLCS_GENERAL_4_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_5 0x4e89 +#define regRLC_RLCS_GENERAL_5_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_6 0x4e8a +#define regRLC_RLCS_GENERAL_6_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_7 0x4e8b +#define regRLC_RLCS_GENERAL_7_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_8 0x4e8c +#define regRLC_RLCS_GENERAL_8_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_9 0x4e8d +#define regRLC_RLCS_GENERAL_9_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_10 0x4e8e +#define regRLC_RLCS_GENERAL_10_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_11 0x4e8f +#define regRLC_RLCS_GENERAL_11_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_12 0x4e90 +#define regRLC_RLCS_GENERAL_12_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_13 0x4e91 +#define regRLC_RLCS_GENERAL_13_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_14 0x4e92 +#define regRLC_RLCS_GENERAL_14_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_15 0x4e93 +#define regRLC_RLCS_GENERAL_15_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_16 0x4e94 +#define regRLC_RLCS_GENERAL_16_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_1 0x4ec1 +#define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_2 0x4ec2 +#define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_3 0x4ec3 +#define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_4 0x4ec4 +#define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 +#define regRLC_RLCS_SPM_SQTT_MODE 0x4ec5 +#define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 +#define regRLC_RLCS_CP_DMA_SRCID_OVER 0x4ec6 +#define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4ec7 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4ec8 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL1 0x4ec9 +#define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL2 0x4eca +#define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ecb +#define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ecc +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_0 0x4ed3 +#define regRLC_RLCS_GCR_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_1 0x4ed4 +#define regRLC_RLCS_GCR_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_2 0x4ed5 +#define regRLC_RLCS_GCR_DATA_2_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_3 0x4ed6 +#define regRLC_RLCS_GCR_DATA_3_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_4 0x4ed7 +#define regRLC_RLCS_GCR_DATA_4_BASE_IDX 1 +#define regRLC_RLCS_GCR_STATUS 0x4ed8 +#define regRLC_RLCS_GCR_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4ed9 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_CNTL 0x4eda +#define regRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA0 0x4edb +#define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA1 0x4edc +#define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA2 0x4edd +#define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA3 0x4ede +#define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA4 0x4edf +#define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL 0x4ee0 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL 0x4ee1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0 0x4ee2 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL 0x4ee3 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL 0x4ee4 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL 0x4ee5 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_STATUS 0x4ee6 +#define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_STATUS 0x4ee7 +#define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_1 0x4ee8 +#define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB 0x4ee9 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB 0x4eea +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_0 0x4eeb +#define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB 0x4eec +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB 0x4eed +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_CNTL 0x4eee +#define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE 0x4eef +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_1 0x4ef1 +#define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_2 0x4ef2 +#define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_STAT 0x4ef3 +#define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_INFO 0x4ef4 +#define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_0 0x4ef5 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_0_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_1 0x4ef6 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_2 0x4ef7 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_IH_CTRL_1 0x4f01 +#define regRLC_RLCS_IH_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_IH_CTRL_2 0x4f02 +#define regRLC_RLCS_IH_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_IH_CTRL_3 0x4f03 +#define regRLC_RLCS_IH_CTRL_3_BASE_IDX 1 +#define regRLC_RLCS_IH_STATUS 0x4f04 +#define regRLC_RLCS_IH_STATUS_BASE_IDX 1 +#define regRLC_RLCS_FED_STATUS 0x4f05 +#define regRLC_RLCS_FED_STATUS_BASE_IDX 1 +#define regRLC_RLCS_FED_RESP 0x4f06 +#define regRLC_RLCS_FED_RESP_BASE_IDX 1 +#define regRLC_RLCS_FED_INT_MASK 0x4f07 +#define regRLC_RLCS_FED_INT_MASK_BASE_IDX 1 +#define regRLC_RLCS_MEM_FED 0x4f08 +#define regRLC_RLCS_MEM_FED_BASE_IDX 1 +#define regRLC_RLCS_SE_PWR_CTRL 0x4f09 +#define regRLC_RLCS_SE_PWR_CTRL_BASE_IDX 1 +#define regRLC_UTCL2_FED_STATUS_SNAP 0x4f0a +#define regRLC_UTCL2_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_SE0_FED_STATUS_SNAP 0x4f0b +#define regRLC_SE0_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_SE1_FED_STATUS_SNAP 0x4f0c +#define regRLC_SE1_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_CANE_FED_STATUS_SNAP 0x4f0d +#define regRLC_CANE_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_CONSOLIDATED_FED_STS 0x4f0e +#define regRLC_CONSOLIDATED_FED_STS_BASE_IDX 1 +#define regRLC_HOST_FED_ACK 0x4f0f +#define regRLC_HOST_FED_ACK_BASE_IDX 1 +#define regRLC_RLCS_SB_RLC_ROM_STATUS 0x4f71 +#define regRLC_RLCS_SB_RLC_ROM_STATUS_BASE_IDX 1 +#define regRLC_RLCS_SB_ROM_STATUS 0x4f72 +#define regRLC_RLCS_SB_ROM_STATUS_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_BUSY_CNTL 0x4f73 +#define regRLC_RLCS_UTCL2_BUSY_CNTL_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_BUSY_STAT 0x4f74 +#define regRLC_RLCS_UTCL2_BUSY_STAT_BASE_IDX 1 +#define regRLC_RLCS_DEC_END 0x4fff +#define regRLC_RLCS_DEC_END_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvfdec_rlc +// base address: 0x2a600 +#define regRLC_SAFE_MODE 0x0980 +#define regRLC_SAFE_MODE_BASE_IDX 1 +#define regRLC_SPM_SAMPLE_CNT 0x0981 +#define regRLC_SPM_SAMPLE_CNT_BASE_IDX 1 +#define regRLC_SPM_MC_CNTL 0x0982 +#define regRLC_SPM_MC_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_CNTL 0x0983 +#define regRLC_SPM_INT_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_STATUS 0x0984 +#define regRLC_SPM_INT_STATUS_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_1 0x0985 +#define regRLC_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_2 0x0986 +#define regRLC_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_CSIB_ADDR_LO 0x0987 +#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define regRLC_CSIB_ADDR_HI 0x0988 +#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define regRLC_CSIB_LENGTH 0x0989 +#define regRLC_CSIB_LENGTH_BASE_IDX 1 +#define regRLC_CP_SCHEDULERS 0x098a +#define regRLC_CP_SCHEDULERS_BASE_IDX 1 +#define regRLC_CP_EOF_INT 0x098b +#define regRLC_CP_EOF_INT_BASE_IDX 1 +#define regRLC_CP_EOF_INT_CNTL 0x098c +#define regRLC_CP_EOF_INT_CNTL_BASE_IDX 1 +#define regRLC_SPARE_INT_0 0x098d +#define regRLC_SPARE_INT_0_BASE_IDX 1 +#define regRLC_SPARE_INT_1 0x098e +#define regRLC_SPARE_INT_1_BASE_IDX 1 +#define regRLC_SPARE_INT_2 0x098f +#define regRLC_SPARE_INT_2_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT_1 0x0992 +#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 +#define regRLC_VFI_CMD 0x099a +#define regRLC_VFI_CMD_BASE_IDX 1 +#define regRLC_VFI_STAT 0x099b +#define regRLC_VFI_STAT_BASE_IDX 1 +#define regRLC_VFI_GRBM_GFX_INDEX 0x099c +#define regRLC_VFI_GRBM_GFX_INDEX_BASE_IDX 1 +#define regRLC_VFI_GRBM_GFX_CNTL 0x099d +#define regRLC_VFI_GRBM_GFX_CNTL_BASE_IDX 1 +#define regRLC_VFI_ADDR 0x099e +#define regRLC_VFI_ADDR_BASE_IDX 1 +#define regRLC_VFI_DATA 0x099f +#define regRLC_VFI_DATA_BASE_IDX 1 + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pwrdec +// base address: 0x3c000 +#define regGRBMX_GLARB_BUSY_MASK 0x504d +#define regGRBMX_GLARB_BUSY_MASK_BASE_IDX 1 +#define regCGTT_IA_CLK_CTRL 0x5085 +#define regCGTT_IA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_WD_CLK_CTRL 0x5086 +#define regCGTT_WD_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CP_CLK_CTRL 0x50b0 +#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPF_CLK_CTRL 0x50b1 +#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPC_CLK_CTRL 0x50b2 +#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_RLC_CLK_CTRL 0x50b5 +#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_GCR_CTRL 0x50c2 +#define regGFX_ICG_GCR_CTRL_BASE_IDX 1 +#define regGC_EA_CPWD_ICG_CTRL 0x50c6 +#define regGC_EA_CPWD_ICG_CTRL_BASE_IDX 1 +#define regGFX_ICG_GC_CAC_CLK_CTRL 0x50d8 +#define regGFX_ICG_GC_CAC_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_GRBM_CTRL 0x50e0 +#define regGFX_ICG_GRBM_CTRL_BASE_IDX 1 +#define regCC_GC_HBM_DISABLE 0x50e1 +#define regCC_GC_HBM_DISABLE_BASE_IDX 1 +#define regGRBMX_LPDDR_DISABLE_0 0x50e2 +#define regGRBMX_LPDDR_DISABLE_0_BASE_IDX 1 +#define regGRBMX_LPDDR_DISABLE_1 0x50e3 +#define regGRBMX_LPDDR_DISABLE_1_BASE_IDX 1 +#define regGLARBI_GLARBR_MGCG_OVERRIDE 0x50f4 +#define regGLARBI_GLARBR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_GLARBA_CTRL 0x50f5 +#define regICG_GLARBA_CTRL_BASE_IDX 1 +#define regICG_GLARBC_CLK_CTRL 0x50f6 +#define regICG_GLARBC_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pspdec +// base address: 0x3f000 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0 0x5c61 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1 0x5c62 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_ERR_CTRL 0x5c64 +#define regGC_EA_CPWD_SDP_ERR_CTRL_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2 0x5c66 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3 0x5c67 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3_BASE_IDX 1 +#define regGRBM_SRCID_CAM_INDEX 0x5e00 +#define regGRBM_SRCID_CAM_INDEX_BASE_IDX 1 +#define regGRBM_SRCID_CAM_DATA 0x5e01 +#define regGRBM_SRCID_CAM_DATA_BASE_IDX 1 +#define regGRBM_IOV_RANGE_ENABLE 0x5e06 +#define regGRBM_IOV_RANGE_ENABLE_BASE_IDX 1 +#define regGRBM_IOV_RANGE_READ_BLOCK_ENABLE 0x5e08 +#define regGRBM_IOV_RANGE_READ_BLOCK_ENABLE_BASE_IDX 1 +#define regGRBM_SEC_CNTL 0x5e0d +#define regGRBM_SEC_CNTL_BASE_IDX 1 +#define regGRBM_IOV_SPARE_RANGE_START 0x5e0e +#define regGRBM_IOV_SPARE_RANGE_START_BASE_IDX 1 +#define regGRBM_IOV_SPARE_RANGE_END 0x5e0f +#define regGRBM_IOV_SPARE_RANGE_END_BASE_IDX 1 +#define regGRBM_CAM_INDEX 0x5e10 +#define regGRBM_CAM_INDEX_BASE_IDX 1 +#define regGRBM_CAM_DATA 0x5e11 +#define regGRBM_CAM_DATA_BASE_IDX 1 +#define regGRBM_CAM_DATA_UPPER 0x5e12 +#define regGRBM_CAM_DATA_UPPER_BASE_IDX 1 +#define regRLC_REG_SEC_INT_STATUS 0x5f3d +#define regRLC_REG_SEC_INT_STATUS_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR 0x5f3e +#define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR_HI 0x5f3f +#define regRLC_FWL_FIRST_VIOL_ADDR_HI_BASE_IDX 1 +#define regRLC_UTC_BYPASS_CNTL 0x5f42 +#define regRLC_UTC_BYPASS_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cp_pspdec +// base address: 0x3f000 +#define regCP_MES_DM_INDEX_ADDR 0x5c00 +#define regCP_MES_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MES_DM_INDEX_DATA 0x5c01 +#define regCP_MES_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_ADDR 0x5c02 +#define regCP_MEC_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_DATA 0x5c03 +#define regCP_MEC_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_ADDR 0x5c04 +#define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_DATA 0x5c05 +#define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX 1 +#define regCPG_PSP_DEBUG 0x5c10 +#define regCPG_PSP_DEBUG_BASE_IDX 1 +#define regCPC_PSP_DEBUG 0x5c11 +#define regCPC_PSP_DEBUG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_ch_pwrdec +// base address: 0x3c3b0 +#define regCHI_CHR_MGCG_OVERRIDE 0x50ec +#define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_CHA_CTRL 0x50ed +#define regICG_CHA_CTRL_BASE_IDX 1 +#define regICG_CHC_CLK_CTRL 0x50ee +#define regICG_CHC_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imudec +// base address: 0x38000 +#define regGFX_IMU_C2PMSG_0 0x4000 +#define regGFX_IMU_C2PMSG_0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_1 0x4001 +#define regGFX_IMU_C2PMSG_1_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_2 0x4002 +#define regGFX_IMU_C2PMSG_2_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_3 0x4003 +#define regGFX_IMU_C2PMSG_3_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_4 0x4004 +#define regGFX_IMU_C2PMSG_4_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_5 0x4005 +#define regGFX_IMU_C2PMSG_5_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_6 0x4006 +#define regGFX_IMU_C2PMSG_6_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_7 0x4007 +#define regGFX_IMU_C2PMSG_7_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_8 0x4008 +#define regGFX_IMU_C2PMSG_8_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_9 0x4009 +#define regGFX_IMU_C2PMSG_9_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_10 0x400a +#define regGFX_IMU_C2PMSG_10_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_11 0x400b +#define regGFX_IMU_C2PMSG_11_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_12 0x400c +#define regGFX_IMU_C2PMSG_12_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_13 0x400d +#define regGFX_IMU_C2PMSG_13_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_14 0x400e +#define regGFX_IMU_C2PMSG_14_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_15 0x400f +#define regGFX_IMU_C2PMSG_15_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_16 0x4010 +#define regGFX_IMU_C2PMSG_16_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_17 0x4011 +#define regGFX_IMU_C2PMSG_17_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_18 0x4012 +#define regGFX_IMU_C2PMSG_18_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_19 0x4013 +#define regGFX_IMU_C2PMSG_19_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_20 0x4014 +#define regGFX_IMU_C2PMSG_20_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_21 0x4015 +#define regGFX_IMU_C2PMSG_21_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_22 0x4016 +#define regGFX_IMU_C2PMSG_22_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_23 0x4017 +#define regGFX_IMU_C2PMSG_23_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_24 0x4018 +#define regGFX_IMU_C2PMSG_24_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_25 0x4019 +#define regGFX_IMU_C2PMSG_25_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_26 0x401a +#define regGFX_IMU_C2PMSG_26_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_27 0x401b +#define regGFX_IMU_C2PMSG_27_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_28 0x401c +#define regGFX_IMU_C2PMSG_28_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_29 0x401d +#define regGFX_IMU_C2PMSG_29_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_30 0x401e +#define regGFX_IMU_C2PMSG_30_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_31 0x401f +#define regGFX_IMU_C2PMSG_31_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_32 0x4020 +#define regGFX_IMU_C2PMSG_32_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_33 0x4021 +#define regGFX_IMU_C2PMSG_33_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_34 0x4022 +#define regGFX_IMU_C2PMSG_34_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_35 0x4023 +#define regGFX_IMU_C2PMSG_35_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_36 0x4024 +#define regGFX_IMU_C2PMSG_36_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_37 0x4025 +#define regGFX_IMU_C2PMSG_37_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_38 0x4026 +#define regGFX_IMU_C2PMSG_38_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_39 0x4027 +#define regGFX_IMU_C2PMSG_39_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_40 0x4028 +#define regGFX_IMU_C2PMSG_40_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_41 0x4029 +#define regGFX_IMU_C2PMSG_41_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_42 0x402a +#define regGFX_IMU_C2PMSG_42_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_43 0x402b +#define regGFX_IMU_C2PMSG_43_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_44 0x402c +#define regGFX_IMU_C2PMSG_44_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_45 0x402d +#define regGFX_IMU_C2PMSG_45_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_46 0x402e +#define regGFX_IMU_C2PMSG_46_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_47 0x402f +#define regGFX_IMU_C2PMSG_47_BASE_IDX 1 +#define regGFX_IMU_MSG_FLAGS 0x403f +#define regGFX_IMU_MSG_FLAGS_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0 0x4040 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1 0x4041 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX 1 +#define regGFX_IMU_PWRMGT_IRQ_CTRL 0x4042 +#define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX 1 +#define regGFX_IMU_MP1_MUTEX 0x4043 +#define regGFX_IMU_MP1_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_4 0x4046 +#define regGFX_IMU_RLC_DATA_4_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_3 0x4047 +#define regGFX_IMU_RLC_DATA_3_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_2 0x4048 +#define regGFX_IMU_RLC_DATA_2_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_1 0x4049 +#define regGFX_IMU_RLC_DATA_1_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_0 0x404a +#define regGFX_IMU_RLC_DATA_0_BASE_IDX 1 +#define regGFX_IMU_RLC_CMD 0x404b +#define regGFX_IMU_RLC_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_MUTEX 0x404c +#define regGFX_IMU_RLC_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_MSG_STATUS 0x404f +#define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX 1 +#define regRLC_GFX_IMU_DATA_0 0x4052 +#define regRLC_GFX_IMU_DATA_0_BASE_IDX 1 +#define regRLC_GFX_IMU_CMD 0x4053 +#define regRLC_GFX_IMU_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_STATUS 0x4054 +#define regGFX_IMU_RLC_STATUS_BASE_IDX 1 +#define regGFX_IMU_STATUS 0x4055 +#define regGFX_IMU_STATUS_BASE_IDX 1 +#define regGFX_IMU_SOC_DATA 0x4059 +#define regGFX_IMU_SOC_DATA_BASE_IDX 1 +#define regGFX_IMU_SOC_ADDR 0x405a +#define regGFX_IMU_SOC_ADDR_BASE_IDX 1 +#define regGFX_IMU_SOC_REQ 0x405b +#define regGFX_IMU_SOC_REQ_BASE_IDX 1 +#define regGFX_IMU_VF_CTRL 0x405c +#define regGFX_IMU_VF_CTRL_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_0 0x4068 +#define regGFX_IMU_SCRATCH_0_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_1 0x4069 +#define regGFX_IMU_SCRATCH_1_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_2 0x406a +#define regGFX_IMU_SCRATCH_2_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_3 0x406b +#define regGFX_IMU_SCRATCH_3_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_4 0x406c +#define regGFX_IMU_SCRATCH_4_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_5 0x406d +#define regGFX_IMU_SCRATCH_5_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_6 0x406e +#define regGFX_IMU_SCRATCH_6_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_7 0x406f +#define regGFX_IMU_SCRATCH_7_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_8 0x4070 +#define regGFX_IMU_SCRATCH_8_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_9 0x4071 +#define regGFX_IMU_SCRATCH_9_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_10 0x4072 +#define regGFX_IMU_SCRATCH_10_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_11 0x4073 +#define regGFX_IMU_SCRATCH_11_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_12 0x4074 +#define regGFX_IMU_SCRATCH_12_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_13 0x4075 +#define regGFX_IMU_SCRATCH_13_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_14 0x4076 +#define regGFX_IMU_SCRATCH_14_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_15 0x4077 +#define regGFX_IMU_SCRATCH_15_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_LO 0x4078 +#define regGFX_IMU_FW_GTS_LO_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_HI 0x4079 +#define regGFX_IMU_FW_GTS_HI_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_LO 0x407a +#define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_HI 0x407b +#define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_LO 0x407c +#define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_HI 0x407d +#define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_CORE_INT_STATUS 0x407f +#define regGFX_IMU_CORE_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_MASK 0x4080 +#define regGFX_IMU_PIC_INT_MASK_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_LVL 0x4081 +#define regGFX_IMU_PIC_INT_LVL_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_EDGE 0x4082 +#define regGFX_IMU_PIC_INT_EDGE_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_0 0x4083 +#define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_1 0x4084 +#define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_2 0x4085 +#define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_3 0x4086 +#define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_4 0x4087 +#define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_5 0x4088 +#define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_6 0x4089 +#define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_7 0x408a +#define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_STATUS 0x408b +#define regGFX_IMU_PIC_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR 0x408c +#define regGFX_IMU_PIC_INTR_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR_ID 0x408d +#define regGFX_IMU_PIC_INTR_ID_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_1 0x4090 +#define regGFX_IMU_IH_CTRL_1_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_2 0x4091 +#define regGFX_IMU_IH_CTRL_2_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_3 0x4092 +#define regGFX_IMU_IH_CTRL_3_BASE_IDX 1 +#define regGFX_IMU_IH_STATUS 0x4093 +#define regGFX_IMU_IH_STATUS_BASE_IDX 1 +#define regGFX_IMU_FUSESTRAP 0x4094 +#define regGFX_IMU_FUSESTRAP_BASE_IDX 1 +#define regGFX_IMU_GFXCLK_BYPASS_CTRL 0x409c +#define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX 1 +#define regGFX_IMU_CLK_CTRL 0x409d +#define regGFX_IMU_CLK_CTRL_BASE_IDX 1 +#define regGFX_IMU_DOORBELL_CONTROL 0x409f +#define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX 1 +#define regGFX_IMU_RLC_CG_CTRL 0x40a0 +#define regGFX_IMU_RLC_CG_CTRL_BASE_IDX 1 +#define regGFX_IMU_RLC_THROTTLE_GFX 0x40a1 +#define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX 1 +#define regGFX_IMU_RLC_RESET_VECTOR 0x40a2 +#define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX 1 +#define regGFX_IMU_RLC_OVERRIDE 0x40a3 +#define regGFX_IMU_RLC_OVERRIDE_BASE_IDX 1 +#define regGFX_IMU_DPM_CONTROL 0x40a8 +#define regGFX_IMU_DPM_CONTROL_BASE_IDX 1 +#define regGFX_IMU_DPM_ACC 0x40a9 +#define regGFX_IMU_DPM_ACC_BASE_IDX 1 +#define regGFX_IMU_DPM_REF_COUNTER 0x40aa +#define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_INDEX 0x40ac +#define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_HIGH 0x40ad +#define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_LOW 0x40ae +#define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_DATA 0x40af +#define regGFX_IMU_RLC_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_FENCE_CTRL 0x40b0 +#define regGFX_IMU_FENCE_CTRL_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_INIT 0x40b1 +#define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_ADDR 0x40b2 +#define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX 1 +#define regGFX_IMU_PROGRAM_CTR 0x40b5 +#define regGFX_IMU_PROGRAM_CTR_BASE_IDX 1 +#define regGFX_IMU_CORE_CTRL 0x40b6 +#define regGFX_IMU_CORE_CTRL_BASE_IDX 1 +#define regGFX_IMU_CORE_STATUS 0x40b7 +#define regGFX_IMU_CORE_STATUS_BASE_IDX 1 +#define regGFX_IMU_PWROKRAW 0x40b8 +#define regGFX_IMU_PWROKRAW_BASE_IDX 1 +#define regGFX_IMU_PWROK 0x40b9 +#define regGFX_IMU_PWROK_BASE_IDX 1 +#define regGFX_IMU_GAP_PWROK 0x40ba +#define regGFX_IMU_GAP_PWROK_BASE_IDX 1 +#define regGFX_IMU_RESETn 0x40bb +#define regGFX_IMU_RESETn_BASE_IDX 1 +#define regGFX_IMU_GFX_RESET_CTRL 0x40bc +#define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_VDCI_RESET_CTRL 0x40be +#define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_GFX_ISO_CTRL 0x40bf +#define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL0 0x40c0 +#define regGFX_IMU_TIMER0_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL1 0x40c1 +#define regGFX_IMU_TIMER0_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_AUTOINC 0x40c2 +#define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_INTEN 0x40c3 +#define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP0 0x40c4 +#define regGFX_IMU_TIMER0_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP1 0x40c5 +#define regGFX_IMU_TIMER0_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP3 0x40c7 +#define regGFX_IMU_TIMER0_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER0_VALUE 0x40c8 +#define regGFX_IMU_TIMER0_VALUE_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL0 0x40c9 +#define regGFX_IMU_TIMER1_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL1 0x40ca +#define regGFX_IMU_TIMER1_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_AUTOINC 0x40cb +#define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_INTEN 0x40cc +#define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP0 0x40cd +#define regGFX_IMU_TIMER1_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP1 0x40ce +#define regGFX_IMU_TIMER1_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP3 0x40d0 +#define regGFX_IMU_TIMER1_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER1_VALUE 0x40d1 +#define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 +#define regGFX_IMU_FUSE_CTRL 0x40e0 +#define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 +#define regGFX_IMU_D_RAM_ADDR 0x40fc +#define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_D_RAM_DATA 0x40fd +#define regGFX_IMU_D_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_GFX_IH_GASKET_CTRL 0x40ff +#define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imu_pspdec +// base address: 0x3fe00 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI 0x5f81 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO 0x5f82 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE 0x5f83 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX 1 +#define regGFX_IMU_I_RAM_ADDR 0x5f90 +#define regGFX_IMU_I_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_I_RAM_DATA 0x5f91 +#define regGFX_IMU_I_RAM_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec +// base address: 0x8180 +#define regGRBMH_CNTL 0x0e00 +#define regGRBMH_CNTL_BASE_IDX 0 +#define regGRBMH_INTF_CNTL 0x0e01 +#define regGRBMH_INTF_CNTL_BASE_IDX 0 +#define regGRBMH_STATUS 0x0e02 +#define regGRBMH_STATUS_BASE_IDX 0 +#define regGRBMH_FGCG0_TARG 0x0e04 +#define regGRBMH_FGCG0_TARG_BASE_IDX 0 +#define regGRBMH_SOFT_RESET 0x0e05 +#define regGRBMH_SOFT_RESET_BASE_IDX 0 +#define regGRBMH_READ_ERROR 0x0e06 +#define regGRBMH_READ_ERROR_BASE_IDX 0 +#define regGRBMH_GFX_CLKEN_CNTL 0x0e0d +#define regGRBMH_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBMH_FGCG2_MISC 0x0e0e +#define regGRBMH_FGCG2_MISC_BASE_IDX 0 +#define regGRBMH_FGCG1_TARGVF 0x0e0f +#define regGRBMH_FGCG1_TARGVF_BASE_IDX 0 +#define regGRBMH_NOWHERE 0x0e10 +#define regGRBMH_NOWHERE_BASE_IDX 0 +#define regGRBMH_INVALID_PIPE 0x0e12 +#define regGRBMH_INVALID_PIPE_BASE_IDX 0 +#define regGRBMH_SYNC 0x0e13 +#define regGRBMH_SYNC_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_padec +// base address: 0x8800 +#define regGE_RATE_CNTL_1 0x0ff4 +#define regGE_RATE_CNTL_1_BASE_IDX 0 +#define regGE_RATE_CNTL_2 0x0ff5 +#define regGE_RATE_CNTL_2_BASE_IDX 0 +#define regCC_GC_SHADER_ARRAY_CONFIG 0x100f +#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regGE_SE_CNTL_STATUS 0x1011 +#define regGE_SE_CNTL_STATUS_BASE_IDX 0 +#define regGE_SPI_IF_SAFE_REG 0x1018 +#define regGE_SPI_IF_SAFE_REG_BASE_IDX 0 +#define regGE_PA_IF_SAFE_REG 0x1019 +#define regGE_PA_IF_SAFE_REG_BASE_IDX 0 +#define regPA_SU_DEBUG_CNTL 0x1020 +#define regPA_SU_DEBUG_CNTL_BASE_IDX 0 +#define regPA_CL_CNTL_STATUS 0x1024 +#define regPA_CL_CNTL_STATUS_BASE_IDX 0 +#define regPA_CL_ENHANCE 0x1025 +#define regPA_CL_ENHANCE_BASE_IDX 0 +#define regPA_CL_RESET_DEBUG 0x1026 +#define regPA_CL_RESET_DEBUG_BASE_IDX 0 +#define regPA_SU_CNTL_STATUS 0x1034 +#define regPA_SU_CNTL_STATUS_BASE_IDX 0 +#define regPA_SC_FIFO_DEPTH_CNTL 0x1035 +#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 +#define regPA_PH_DEBUG_CNTL 0x1082 +#define regPA_PH_DEBUG_CNTL_BASE_IDX 0 +#define regPA_SC_DEBUG_CNTL 0x1096 +#define regPA_SC_DEBUG_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_sqdec +// base address: 0x8c00 +#define regSQ_CONFIG 0x10a0 +#define regSQ_CONFIG_BASE_IDX 0 +#define regSQC_CONFIG 0x10a1 +#define regSQC_CONFIG_BASE_IDX 0 +#define regSQ_RANDOM_WAVE_PRI 0x10a3 +#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define regSQG_STATUS 0x10a4 +#define regSQG_STATUS_BASE_IDX 0 +#define regSQ_FIFO_SIZES 0x10a5 +#define regSQ_FIFO_SIZES_BASE_IDX 0 +#define regSQ_DSM_CNTL 0x10a6 +#define regSQ_DSM_CNTL_BASE_IDX 0 +#define regSQ_DSM_CNTL2 0x10a7 +#define regSQ_DSM_CNTL2_BASE_IDX 0 +#define regSQ_PIT_WEIGHT 0x10a8 +#define regSQ_PIT_WEIGHT_BASE_IDX 0 +#define regSQG_THREAD_TRACE_CONFIG 0x10aa +#define regSQG_THREAD_TRACE_CONFIG_BASE_IDX 0 +#define regSP_CONFIG 0x10ab +#define regSP_CONFIG_BASE_IDX 0 +#define regSQ_ARB_CONFIG 0x10ac +#define regSQ_ARB_CONFIG_BASE_IDX 0 +#define regSQ_DYN_VGPR 0x10ad +#define regSQ_DYN_VGPR_BASE_IDX 0 +#define regSQ_SHADER_CYCLES_LO 0x10ae +#define regSQ_SHADER_CYCLES_LO_BASE_IDX 0 +#define regSQ_SHADER_CYCLES_HI 0x10af +#define regSQ_SHADER_CYCLES_HI_BASE_IDX 0 +#define regSQ_DEBUG_HOST_TRAP_STATUS 0x10b6 +#define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX 0 +#define regSQG_GL1X_CTRL 0x10b8 +#define regSQG_GL1X_CTRL_BASE_IDX 0 +#define regSQG_GL1X_STATUS 0x10b9 +#define regSQG_GL1X_STATUS_BASE_IDX 0 +#define regSQG_CONFIG 0x10ba +#define regSQG_CONFIG_BASE_IDX 0 +#define regSQ_PERF_SNAPSHOT_CTRL 0x10bb +#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 +#define regCC_GC_SHADER_RATE_CONFIG_1 0x10bc +#define regCC_GC_SHADER_RATE_CONFIG_1_BASE_IDX 0 +#define regSQ_INTERRUPT_AUTO_MASK 0x10be +#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define regSQ_INTERRUPT_MSG_CTRL 0x10bf +#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_H 0x10d0 +#define regSQ_WATCH0_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_L 0x10d1 +#define regSQ_WATCH0_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH0_CNTL 0x10d2 +#define regSQ_WATCH0_CNTL_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_H 0x10d3 +#define regSQ_WATCH1_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_L 0x10d4 +#define regSQ_WATCH1_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH1_CNTL 0x10d5 +#define regSQ_WATCH1_CNTL_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_H 0x10d6 +#define regSQ_WATCH2_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_L 0x10d7 +#define regSQ_WATCH2_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH2_CNTL 0x10d8 +#define regSQ_WATCH2_CNTL_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_H 0x10d9 +#define regSQ_WATCH3_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_L 0x10da +#define regSQ_WATCH3_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH3_CNTL 0x10db +#define regSQ_WATCH3_CNTL_BASE_IDX 0 +#define regSQG_UTCL0_STATUS 0x10dc +#define regSQG_UTCL0_STATUS_BASE_IDX 0 +#define regSQG_UTCL0_CNTL1 0x10dd +#define regSQG_UTCL0_CNTL1_BASE_IDX 0 +#define regSQG_UTCL0_CNTL2 0x10de +#define regSQG_UTCL0_CNTL2_BASE_IDX 0 +#define regSQG_UTCL0_RETRY 0x10df +#define regSQG_UTCL0_RETRY_BASE_IDX 0 +#define regSQG_VMID_FED_STATUS 0x10e0 +#define regSQG_VMID_FED_STATUS_BASE_IDX 0 +#define regSQG_VMID_FED_CLEAR 0x10e1 +#define regSQG_VMID_FED_CLEAR_BASE_IDX 0 +#define regSQG_SE_PIT_CONTROL 0x10e2 +#define regSQG_SE_PIT_CONTROL_BASE_IDX 0 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_HI 0x10e3 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_HI_BASE_IDX 0 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_LO 0x10e4 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_LO_BASE_IDX 0 +#define regSQG_WS_INSERTION_COUNT 0x10e5 +#define regSQG_WS_INSERTION_COUNT_BASE_IDX 0 +#define regSQG_WS_SPI_STATUS 0x10e6 +#define regSQG_WS_SPI_STATUS_BASE_IDX 0 +#define regSQ_IND_INDEX 0x1118 +#define regSQ_IND_INDEX_BASE_IDX 0 +#define regSQ_IND_DATA 0x1119 +#define regSQ_IND_DATA_BASE_IDX 0 +#define regSQ_CMD 0x111b +#define regSQ_CMD_BASE_IDX 0 +#define regSQC_WSM_CONTROL 0x1174 +#define regSQC_WSM_CONTROL_BASE_IDX 0 +#define regSQC_PIT_CONTROL0 0x1175 +#define regSQC_PIT_CONTROL0_BASE_IDX 0 +#define regSQC_PIT_CONTROL1 0x1176 +#define regSQC_PIT_CONTROL1_BASE_IDX 0 +#define regSQC_PIT_CONTROL2 0x1177 +#define regSQC_PIT_CONTROL2_BASE_IDX 0 +#define regSQC_UTCL0_RETRY 0x1178 +#define regSQC_UTCL0_RETRY_BASE_IDX 0 +#define regSQC_MISC_CONFIG 0x1179 +#define regSQC_MISC_CONFIG_BASE_IDX 0 +#define regSQ_TIMEOUT_CONFIG 0x117a +#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0 +#define regSQ_TIMEOUT_STATUS_SIMD01 0x117b +#define regSQ_TIMEOUT_STATUS_SIMD01_BASE_IDX 0 +#define regSQ_TIMEOUT_STATUS_SIMD23 0x117c +#define regSQ_TIMEOUT_STATUS_SIMD23_BASE_IDX 0 +#define regSQC_UTCL0_STATUS 0x117d +#define regSQC_UTCL0_STATUS_BASE_IDX 0 +#define regSQC_UTCL0_CNTL1 0x117e +#define regSQC_UTCL0_CNTL1_BASE_IDX 0 +#define regSQC_UTCL0_CNTL2 0x117f +#define regSQC_UTCL0_CNTL2_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shsdec +// base address: 0x9000 +#define regSX_DEBUG_BUSY 0x11b4 +#define regSX_DEBUG_BUSY_BASE_IDX 0 +#define regSX_DEBUG_BUSY_2 0x11b5 +#define regSX_DEBUG_BUSY_2_BASE_IDX 0 +#define regSX_DEBUG_BUSY_3 0x11b6 +#define regSX_DEBUG_BUSY_3_BASE_IDX 0 +#define regSX_DEBUG_BUSY_4 0x11b7 +#define regSX_DEBUG_BUSY_4_BASE_IDX 0 +#define regSX_DEBUG_1 0x11b8 +#define regSX_DEBUG_1_BASE_IDX 0 +#define regSX_DEBUG_BUSY_5 0x11b9 +#define regSX_DEBUG_BUSY_5_BASE_IDX 0 +#define regSX_DEBUG_BUSY_6 0x11ba +#define regSX_DEBUG_BUSY_6_BASE_IDX 0 +#define regSX_DEBUG_BUSY_7 0x11bb +#define regSX_DEBUG_BUSY_7_BASE_IDX 0 +#define regSX_DEBUG_BUSY_8 0x11bc +#define regSX_DEBUG_BUSY_8_BASE_IDX 0 +#define regSX_DEBUG_BUSY_9 0x11bd +#define regSX_DEBUG_BUSY_9_BASE_IDX 0 +#define regSX_DEBUG_BUSY_10 0x11be +#define regSX_DEBUG_BUSY_10_BASE_IDX 0 +#define regSPI_PS_MAX_WAVE_ID 0x11da +#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define regSPI_SCRATCH_ADDR_STATUS 0x11db +#define regSPI_SCRATCH_ADDR_STATUS_BASE_IDX 0 +#define regSPI_GFX_CNTL 0x11dc +#define regSPI_GFX_CNTL_BASE_IDX 0 +#define regSPI_DEBUG_CNTL_2 0x11de +#define regSPI_DEBUG_CNTL_2_BASE_IDX 0 +#define regSPI_DEBUG_CNTL_3 0x11df +#define regSPI_DEBUG_CNTL_3_BASE_IDX 0 +#define regSPI_DEBUG_CNTL 0x11e1 +#define regSPI_DEBUG_CNTL_BASE_IDX 0 +#define regSPI_DEBUG_READ 0x11e2 +#define regSPI_DEBUG_READ_BASE_IDX 0 +#define regSPI_DSM_CNTL 0x11e3 +#define regSPI_DSM_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL2 0x11e4 +#define regSPI_DSM_CNTL2_BASE_IDX 0 +#define regSPI_EDC_CNT 0x11e5 +#define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPIRA_DEBUG_READ 0x11e6 +#define regSPIRA_DEBUG_READ_BASE_IDX 0 +#define regSPI_DEBUG_BUSY 0x11f0 +#define regSPI_DEBUG_BUSY_BASE_IDX 0 +#define regSPI_CONFIG_PS_CU_EN 0x11f2 +#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_GFX0 0x11f3 +#define regSPI_CONFIG_CU_MASK_GFX0_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_HP3D0 0x11f4 +#define regSPI_CONFIG_CU_MASK_HP3D0_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_GFX1 0x11f5 +#define regSPI_CONFIG_CU_MASK_GFX1_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_HP3D1 0x11f6 +#define regSPI_CONFIG_CU_MASK_HP3D1_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS0 0x11f7 +#define regSPI_CONFIG_CU_MASK_CS0_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS1 0x11f8 +#define regSPI_CONFIG_CU_MASK_CS1_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS2 0x11f9 +#define regSPI_CONFIG_CU_MASK_CS2_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS3 0x11fa +#define regSPI_CONFIG_CU_MASK_CS3_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS4 0x11fb +#define regSPI_CONFIG_CU_MASK_CS4_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS5 0x11fc +#define regSPI_CONFIG_CU_MASK_CS5_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS6 0x11fd +#define regSPI_CONFIG_CU_MASK_CS6_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS7 0x11fe +#define regSPI_CONFIG_CU_MASK_CS7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_CNTL 0x124a +#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_0 0x124b +#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_2 0x124d +#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_3 0x124e +#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_4 0x124f +#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_5 0x1250 +#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_0 0x1255 +#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_2 0x1257 +#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_4 0x1259 +#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_6 0x125b +#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_7 0x125c +#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_9 0x125e +#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_11 0x1260 +#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_13 0x1262 +#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_14 0x1263 +#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_15 0x1264 +#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_16 0x1265 +#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_17 0x1266 +#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_18 0x1267 +#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_19 0x1268 +#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_20 0x1269 +#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define regSPI_WF_LIFETIME_DEBUG 0x126a +#define regSPI_WF_LIFETIME_DEBUG_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_21 0x126b +#define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 +#define regSPI_WGP_WORK_PENDING 0x126c +#define regSPI_WGP_WORK_PENDING_BASE_IDX 0 +#define regSPI_CREST_MODE 0x126d +#define regSPI_CREST_MODE_BASE_IDX 0 +#define regSPI_SLAVE_DEBUG_BUSY 0x1273 +#define regSPI_SLAVE_DEBUG_BUSY_BASE_IDX 0 +#define regSPI_LB_CTR_CTRL 0x1274 +#define regSPI_LB_CTR_CTRL_BASE_IDX 0 +#define regSPI_LB_WGP_MASK 0x1275 +#define regSPI_LB_WGP_MASK_BASE_IDX 0 +#define regSPI_LB_DATA_REG 0x1276 +#define regSPI_LB_DATA_REG_BASE_IDX 0 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 +#define regSPI_GDS_CREDITS 0x1278 +#define regSPI_GDS_CREDITS_BASE_IDX 0 +#define regSPI_SX_EXPORT_BUFFER_SIZES 0x1279 +#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_STATUS 0x127b +#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x1280 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x1281 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x1282 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x1283 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 +#define regSPI_LB_DATA_WAVES 0x1284 +#define regSPI_LB_DATA_WAVES_BASE_IDX 0 +#define regSPI_LB_DATA_PERWGP_WAVE_HSGS 0x1285 +#define regSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX 0 +#define regSPI_LB_DATA_PERWGP_WAVE_PS 0x1286 +#define regSPI_LB_DATA_PERWGP_WAVE_PS_BASE_IDX 0 +#define regSPI_LB_DATA_PERWGP_WAVE_CS 0x1287 +#define regSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX 0 +#define regSPI_WF_ACTIVE_COUNT_GFX 0x1288 +#define regSPI_WF_ACTIVE_COUNT_GFX_BASE_IDX 0 +#define regSPI_WF_ACTIVE_COUNT_HPG 0x1289 +#define regSPI_WF_ACTIVE_COUNT_HPG_BASE_IDX 0 +#define regSPIS_DEBUG_READ 0x128a +#define regSPIS_DEBUG_READ_BASE_IDX 0 +#define regBCI_DEBUG_READ 0x128b +#define regBCI_DEBUG_READ_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_GFX_CRAWLER_CONFIG 0x1296 +#define regSPI_GFX_CRAWLER_CONFIG_BASE_IDX 0 +#define regSPI_CS_CRAWLER_CONFIG 0x1297 +#define regSPI_CS_CRAWLER_CONFIG_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tpdec +// base address: 0x9400 +#define regTD_CNTL 0x12c5 +#define regTD_CNTL_BASE_IDX 0 +#define regTD_STATUS 0x12c6 +#define regTD_STATUS_BASE_IDX 0 +#define regTD_DEBUG_DATA 0x12c9 +#define regTD_DEBUG_DATA_BASE_IDX 0 +#define regTD_POWER_CNTL 0x12ca +#define regTD_POWER_CNTL_BASE_IDX 0 +#define regTD_CNTL2 0x12cb +#define regTD_CNTL2_BASE_IDX 0 +#define regTD_DSM_CNTL 0x12cf +#define regTD_DSM_CNTL_BASE_IDX 0 +#define regTD_DSM_CNTL2 0x12d0 +#define regTD_DSM_CNTL2_BASE_IDX 0 +#define regTD_SCRATCH 0x12d3 +#define regTD_SCRATCH_BASE_IDX 0 +#define regTA_CNTL 0x12e1 +#define regTA_CNTL_BASE_IDX 0 +#define regTA_CNTL_AUX 0x12e2 +#define regTA_CNTL_AUX_BASE_IDX 0 +#define regTA_CNTL2 0x12e5 +#define regTA_CNTL2_BASE_IDX 0 +#define regTA_STATUS 0x12e8 +#define regTA_STATUS_BASE_IDX 0 +#define regTA_SCRATCH 0x1304 +#define regTA_SCRATCH_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_rbdec +// base address: 0x9800 +#define regDB_DEBUG 0x13ac +#define regDB_DEBUG_BASE_IDX 0 +#define regDB_DEBUG2 0x13ad +#define regDB_DEBUG2_BASE_IDX 0 +#define regDB_DEBUG3 0x13ae +#define regDB_DEBUG3_BASE_IDX 0 +#define regDB_DEBUG4 0x13af +#define regDB_DEBUG4_BASE_IDX 0 +#define regDB_CREDIT_LIMIT 0x13b4 +#define regDB_CREDIT_LIMIT_BASE_IDX 0 +#define regDB_WATERMARKS 0x13b5 +#define regDB_WATERMARKS_BASE_IDX 0 +#define regDB_FREE_CACHELINES 0x13b7 +#define regDB_FREE_CACHELINES_BASE_IDX 0 +#define regDB_FIFO_DEPTH1 0x13b8 +#define regDB_FIFO_DEPTH1_BASE_IDX 0 +#define regDB_FIFO_DEPTH2 0x13b9 +#define regDB_FIFO_DEPTH2_BASE_IDX 0 +#define regDB_RING_CONTROL 0x13bb +#define regDB_RING_CONTROL_BASE_IDX 0 +#define regDB_MEM_ARB_WATERMARKS 0x13bc +#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define regDB_FIFO_DEPTH3 0x13bd +#define regDB_FIFO_DEPTH3_BASE_IDX 0 +#define regDB_DEBUG6 0x13be +#define regDB_DEBUG6_BASE_IDX 0 +#define regDB_EXCEPTION_CONTROL 0x13bf +#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define regDB_DEBUG7 0x13d0 +#define regDB_DEBUG7_BASE_IDX 0 +#define regDB_DEBUG5 0x13d1 +#define regDB_DEBUG5_BASE_IDX 0 +#define regDB_MEM_CONFIG 0x13d2 +#define regDB_MEM_CONFIG_BASE_IDX 0 +#define regDB_ARB_CONFIG 0x13d3 +#define regDB_ARB_CONFIG_BASE_IDX 0 +#define regDB_DFD_INDIRECT_SEL 0x13d4 +#define regDB_DFD_INDIRECT_SEL_BASE_IDX 0 +#define regDB_DFD_INDIRECT_DAT 0x13d5 +#define regDB_DFD_INDIRECT_DAT_BASE_IDX 0 +#define regDB_SUMMARIZER_TIMEOUTS 0x13d6 +#define regDB_SUMMARIZER_TIMEOUTS_BASE_IDX 0 +#define regDB_FGCG_SRAMS_CLK_CTRL 0x13d7 +#define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 +#define regDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 +#define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 +#define regDB_FIFO_DEPTH4 0x13d9 +#define regDB_FIFO_DEPTH4_BASE_IDX 0 +#define regCC_RB_BACKEND_DISABLE 0x13dd +#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define regGB_ADDR_CONFIG_1 0x13de +#define regGB_ADDR_CONFIG_1_BASE_IDX 0 +#define regGB_BACKEND_MAP 0x13df +#define regGB_BACKEND_MAP_BASE_IDX 0 +#define regGB_GPU_ID 0x13e0 +#define regGB_GPU_ID_BASE_IDX 0 +#define regGB_ADDR_CONFIG_READ 0x13e2 +#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regCB_HW_CONTROL_4 0x1422 +#define regCB_HW_CONTROL_4_BASE_IDX 0 +#define regCB_HW_CONTROL_3 0x1423 +#define regCB_HW_CONTROL_3_BASE_IDX 0 +#define regCB_HW_CONTROL 0x1424 +#define regCB_HW_CONTROL_BASE_IDX 0 +#define regCB_HW_CONTROL_1 0x1425 +#define regCB_HW_CONTROL_1_BASE_IDX 0 +#define regCB_HW_CONTROL_2 0x1426 +#define regCB_HW_CONTROL_2_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_CTL 0x1428 +#define regCB_HW_MEM_ARBITER_CTL_BASE_IDX 0 +#define regCB_FGCG_SRAM_OVERRIDE 0x142a +#define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX 0 +#define regCB_CACHE_EVICT_POINTS 0x142e +#define regCB_CACHE_EVICT_POINTS_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec2 +// base address: 0x9c80 +#define regSPI_PQEV_CTRL 0x14c0 +#define regSPI_PQEV_CTRL_BASE_IDX 0 +#define regSPI_EXP_THROTTLE_CTRL 0x14c3 +#define regSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_rmi_gfx_se_rmidec +// base address: 0x2e200 +#define regRMI_GENERAL_CNTL 0x1880 +#define regRMI_GENERAL_CNTL_BASE_IDX 1 +#define regRMI_GENERAL_CNTL1 0x1881 +#define regRMI_GENERAL_CNTL1_BASE_IDX 1 +#define regRMI_GENERAL_STATUS 0x1882 +#define regRMI_GENERAL_STATUS_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS0 0x1883 +#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS1 0x1884 +#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS2 0x1885 +#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS3 0x1886 +#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 1 +#define regRMI_XBAR_CONFIG 0x1887 +#define regRMI_XBAR_CONFIG_BASE_IDX 1 +#define regRMI_PROBE_POP_LOGIC_CNTL 0x1888 +#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 1 +#define regRMI_UTC_XNACK_N_MISC_CNTL 0x1889 +#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 1 +#define regRMI_DEMUX_CNTL 0x188a +#define regRMI_DEMUX_CNTL_BASE_IDX 1 +#define regRMI_UTCL1_CNTL1 0x188b +#define regRMI_UTCL1_CNTL1_BASE_IDX 1 +#define regRMI_UTCL1_CNTL2 0x188c +#define regRMI_UTCL1_CNTL2_BASE_IDX 1 +#define regRMI_UTC_UNIT_CONFIG 0x188d +#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER0_CNTL 0x188e +#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER1_CNTL 0x188f +#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_CNTL 0x1890 +#define regRMI_SCOREBOARD_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS0 0x1891 +#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS1 0x1892 +#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS2 0x1893 +#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG 0x1894 +#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG_1 0x1895 +#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 1 +#define regRMI_CLOCK_CNTRL 0x1896 +#define regRMI_CLOCK_CNTRL_BASE_IDX 1 +#define regRMI_UTCL1_STATUS 0x1897 +#define regRMI_UTCL1_STATUS_BASE_IDX 1 +#define regRMI_RB_GLX_CID_MAP 0x1898 +#define regRMI_RB_GLX_CID_MAP_BASE_IDX 1 +#define regRMI_XNACK_DEBUG 0x189e +#define regRMI_XNACK_DEBUG_BASE_IDX 1 +#define regRMI_SPARE 0x189f +#define regRMI_SPARE_BASE_IDX 1 +#define regRMI_SPARE_1 0x18a0 +#define regRMI_SPARE_1_BASE_IDX 1 +#define regRMI_SPARE_2 0x18a1 +#define regRMI_SPARE_2_BASE_IDX 1 +#define regCC_RMI_REDUNDANCY 0x18a2 +#define regCC_RMI_REDUNDANCY_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_utcl1dec +// base address: 0x9fb0 +#define regUTCL1_CTRL_1 0x158c +#define regUTCL1_CTRL_1_BASE_IDX 0 +#define regUTCL1_HASH_CTRL 0x158e +#define regUTCL1_HASH_CTRL_BASE_IDX 0 +#define regUTCL1_ALOG 0x158f +#define regUTCL1_ALOG_BASE_IDX 0 +#define regUTCL1_STATUS 0x1594 +#define regUTCL1_STATUS_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shdec +// base address: 0xb000 +#define regSPI_SHADER_PGM_CHKSUM_PS 0x19a5 +#define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_PS 0x19a6 +#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_PS 0x19a7 +#define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_PS 0x19a8 +#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_PS 0x19a9 +#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_PS 0x19aa +#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_PS 0x19ab +#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_0 0x19ac +#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_1 0x19ad +#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_2 0x19ae +#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_3 0x19af +#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_4 0x19b0 +#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_5 0x19b1 +#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_6 0x19b2 +#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_7 0x19b3 +#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_8 0x19b4 +#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_9 0x19b5 +#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_10 0x19b6 +#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_11 0x19b7 +#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_12 0x19b8 +#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_13 0x19b9 +#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_14 0x19ba +#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_15 0x19bb +#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_16 0x19bc +#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_17 0x19bd +#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_18 0x19be +#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_19 0x19bf +#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_20 0x19c0 +#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_21 0x19c1 +#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_22 0x19c2 +#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_23 0x19c3 +#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_24 0x19c4 +#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_25 0x19c5 +#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_26 0x19c6 +#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_27 0x19c7 +#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_28 0x19c8 +#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_29 0x19c9 +#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_30 0x19ca +#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_31 0x19cb +#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_PS 0x19d0 +#define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 +#define regSPI_SHADER_GS_OUT_CONFIG_PS 0x19d1 +#define regSPI_SHADER_GS_OUT_CONFIG_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_0 0x19d2 +#define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_1 0x19d3 +#define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_2 0x19d4 +#define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_3 0x19d5 +#define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_GS 0x1a20 +#define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_GS 0x1a24 +#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_GS 0x1a25 +#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES 0x1a26 +#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_GS 0x1a27 +#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_GS 0x1a28 +#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES 0x1a29 +#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_GS 0x1a2a +#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS 0x1a2b +#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_0 0x1a2c +#define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_1 0x1a2d +#define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_2 0x1a2e +#define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_3 0x1a2f +#define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_4 0x1a30 +#define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_5 0x1a31 +#define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_6 0x1a32 +#define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_7 0x1a33 +#define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_8 0x1a34 +#define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_9 0x1a35 +#define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_10 0x1a36 +#define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_11 0x1a37 +#define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_12 0x1a38 +#define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_13 0x1a39 +#define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_14 0x1a3a +#define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_15 0x1a3b +#define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_16 0x1a3c +#define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_17 0x1a3d +#define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_18 0x1a3e +#define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_19 0x1a3f +#define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_20 0x1a40 +#define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_21 0x1a41 +#define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_22 0x1a42 +#define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_23 0x1a43 +#define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_24 0x1a44 +#define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_25 0x1a45 +#define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_26 0x1a46 +#define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_27 0x1a47 +#define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_28 0x1a48 +#define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_29 0x1a49 +#define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_30 0x1a4a +#define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_31 0x1a4b +#define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_DIM 0x1a4c +#define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC 0x1a4d +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_CTRL 0x1a4e +#define regSPI_SHADER_GS_MESHLET_CTRL_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_ESGS 0x1a50 +#define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 +#define regSPI_SHADER_GS_OUT_CONFIG_PS_GS 0x1a51 +#define regSPI_SHADER_GS_OUT_CONFIG_PS_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 +#define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 +#define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 +#define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 +#define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 +#define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_HS 0x1aa4 +#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_HS 0x1aa5 +#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS 0x1aa6 +#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_HS 0x1aa7 +#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_HS 0x1aa8 +#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS 0x1aa9 +#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_HS 0x1aaa +#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_HS 0x1aab +#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_0 0x1aac +#define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_1 0x1aad +#define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_2 0x1aae +#define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_3 0x1aaf +#define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_4 0x1ab0 +#define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_5 0x1ab1 +#define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_6 0x1ab2 +#define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_7 0x1ab3 +#define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_8 0x1ab4 +#define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_9 0x1ab5 +#define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_10 0x1ab6 +#define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_11 0x1ab7 +#define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_12 0x1ab8 +#define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_13 0x1ab9 +#define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_14 0x1aba +#define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_15 0x1abb +#define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_16 0x1abc +#define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_17 0x1abd +#define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_18 0x1abe +#define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_19 0x1abf +#define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_20 0x1ac0 +#define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_21 0x1ac1 +#define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_22 0x1ac2 +#define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_23 0x1ac3 +#define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_24 0x1ac4 +#define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_25 0x1ac5 +#define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_26 0x1ac6 +#define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_27 0x1ac7 +#define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_28 0x1ac8 +#define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_29 0x1ac9 +#define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_30 0x1aca +#define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_31 0x1acb +#define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 +#define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 +#define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 +#define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 +#define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 +#define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec +// base address: 0xc700 +#define regSPI_ARB_PRIORITY 0x1f60 +#define regSPI_ARB_PRIORITY_BASE_IDX 0 +#define regSPI_ARB_CYCLES_0 0x1f61 +#define regSPI_ARB_CYCLES_0_BASE_IDX 0 +#define regSPI_ARB_CYCLES_1 0x1f62 +#define regSPI_ARB_CYCLES_1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_GFX 0x1f67 +#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 +#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS0 0x1f69 +#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS1 0x1f6a +#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS2 0x1f6b +#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS3 0x1f6c +#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS4 0x1f6d +#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS5 0x1f6e +#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS6 0x1f6f +#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS7 0x1f70 +#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define regSPI_USER_ACCUM_VMID_CNTL 0x1f71 +#define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 +#define regSPI_GDBG_PER_VMID_CNTL 0x1f72 +#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 +#define regSPI_COMPUTE_QUEUE_RESET 0x1f73 +#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define regSPI_COMPUTE_WF_CTX_SAVE 0x1f74 +#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 +#define regSPI_SAVE_RESTORE_STATUS 0x1f75 +#define regSPI_SAVE_RESTORE_STATUS_BASE_IDX 0 +#define regSPI_CONFIG_DIDT_CNTL 0x1f76 +#define regSPI_CONFIG_DIDT_CNTL_BASE_IDX 0 +#define regSPI_CONFIG_DIDT_TYPEMASK 0x1f77 +#define regSPI_CONFIG_DIDT_TYPEMASK_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tcpdec +// base address: 0xca80 +#define regTCP_WATCH0_ADDR_H 0x2048 +#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH0_ADDR_L 0x2049 +#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH0_CNTL 0x204a +#define regTCP_WATCH0_CNTL_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_H 0x204b +#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_L 0x204c +#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH1_CNTL 0x204d +#define regTCP_WATCH1_CNTL_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_H 0x204e +#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_L 0x204f +#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH2_CNTL 0x2050 +#define regTCP_WATCH2_CNTL_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_H 0x2051 +#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_L 0x2052 +#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH3_CNTL 0x2053 +#define regTCP_WATCH3_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxdec0 +// base address: 0x28000 +#define regDB_RENDER_CONTROL 0x0000 +#define regDB_RENDER_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_VIEW 0x0001 +#define regDB_DEPTH_VIEW_BASE_IDX 1 +#define regDB_DEPTH_VIEW1 0x0002 +#define regDB_DEPTH_VIEW1_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE 0x0003 +#define regDB_RENDER_OVERRIDE_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE2 0x0004 +#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define regDB_DEPTH_SIZE_XY 0x0005 +#define regDB_DEPTH_SIZE_XY_BASE_IDX 1 +#define regDB_Z_INFO 0x0006 +#define regDB_Z_INFO_BASE_IDX 1 +#define regDB_STENCIL_INFO 0x0007 +#define regDB_STENCIL_INFO_BASE_IDX 1 +#define regDB_Z_READ_BASE 0x0008 +#define regDB_Z_READ_BASE_BASE_IDX 1 +#define regDB_Z_READ_BASE_HI 0x0009 +#define regDB_Z_READ_BASE_HI_BASE_IDX 1 +#define regDB_Z_WRITE_BASE 0x000a +#define regDB_Z_WRITE_BASE_BASE_IDX 1 +#define regDB_Z_WRITE_BASE_HI 0x000b +#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE 0x000c +#define regDB_STENCIL_READ_BASE_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE_HI 0x000d +#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE 0x000e +#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE_HI 0x000f +#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_GL1_INTERFACE_CONTROL 0x0010 +#define regDB_GL1_INTERFACE_CONTROL_BASE_IDX 1 +#define regDB_MEM_TEMPORAL 0x0012 +#define regDB_MEM_TEMPORAL_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MIN 0x0014 +#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MAX 0x0015 +#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define regDB_COUNT_CONTROL 0x0018 +#define regDB_COUNT_CONTROL_BASE_IDX 1 +#define regDB_VIEWPORT_CONTROL 0x0019 +#define regDB_VIEWPORT_CONTROL_BASE_IDX 1 +#define regDB_SPI_VRS_CENTER_LOCATION 0x001a +#define regDB_SPI_VRS_CENTER_LOCATION_BASE_IDX 1 +#define regDB_SHADER_CONTROL 0x001b +#define regDB_SHADER_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_CONTROL 0x001c +#define regDB_DEPTH_CONTROL_BASE_IDX 1 +#define regDB_STENCIL_CONTROL 0x001d +#define regDB_STENCIL_CONTROL_BASE_IDX 1 +#define regDB_EQAA 0x001e +#define regDB_EQAA_BASE_IDX 1 +#define regDB_ALPHA_TO_MASK 0x001f +#define regDB_ALPHA_TO_MASK_BASE_IDX 1 +#define regTA_BC_BASE_ADDR 0x0020 +#define regTA_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_BC_BASE_ADDR_HI 0x0021 +#define regTA_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regDB_STENCIL_REF 0x0022 +#define regDB_STENCIL_REF_BASE_IDX 1 +#define regDB_STENCIL_OPVAL 0x0023 +#define regDB_STENCIL_OPVAL_BASE_IDX 1 +#define regDB_STENCIL_READ_MASK 0x0024 +#define regDB_STENCIL_READ_MASK_BASE_IDX 1 +#define regDB_STENCIL_WRITE_MASK 0x0025 +#define regDB_STENCIL_WRITE_MASK_BASE_IDX 1 +#define regSC_MEM_TEMPORAL 0x003e +#define regSC_MEM_TEMPORAL_BASE_IDX 1 +#define regSC_MEM_SPEC_READ 0x003f +#define regSC_MEM_SPEC_READ_BASE_IDX 1 +#define regPA_SC_VPORT_0_TL 0x0040 +#define regPA_SC_VPORT_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_0_BR 0x0041 +#define regPA_SC_VPORT_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_1_TL 0x0042 +#define regPA_SC_VPORT_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_1_BR 0x0043 +#define regPA_SC_VPORT_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_2_TL 0x0044 +#define regPA_SC_VPORT_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_2_BR 0x0045 +#define regPA_SC_VPORT_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_3_TL 0x0046 +#define regPA_SC_VPORT_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_3_BR 0x0047 +#define regPA_SC_VPORT_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_4_TL 0x0048 +#define regPA_SC_VPORT_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_4_BR 0x0049 +#define regPA_SC_VPORT_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_5_TL 0x004a +#define regPA_SC_VPORT_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_5_BR 0x004b +#define regPA_SC_VPORT_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_6_TL 0x004c +#define regPA_SC_VPORT_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_6_BR 0x004d +#define regPA_SC_VPORT_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_7_TL 0x004e +#define regPA_SC_VPORT_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_7_BR 0x004f +#define regPA_SC_VPORT_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_8_TL 0x0050 +#define regPA_SC_VPORT_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_8_BR 0x0051 +#define regPA_SC_VPORT_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_9_TL 0x0052 +#define regPA_SC_VPORT_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_9_BR 0x0053 +#define regPA_SC_VPORT_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_10_TL 0x0054 +#define regPA_SC_VPORT_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_10_BR 0x0055 +#define regPA_SC_VPORT_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_11_TL 0x0056 +#define regPA_SC_VPORT_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_11_BR 0x0057 +#define regPA_SC_VPORT_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_12_TL 0x0058 +#define regPA_SC_VPORT_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_12_BR 0x0059 +#define regPA_SC_VPORT_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_13_TL 0x005a +#define regPA_SC_VPORT_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_13_BR 0x005b +#define regPA_SC_VPORT_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_14_TL 0x005c +#define regPA_SC_VPORT_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_14_BR 0x005d +#define regPA_SC_VPORT_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_15_TL 0x005e +#define regPA_SC_VPORT_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_15_BR 0x005f +#define regPA_SC_VPORT_15_BR_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_TL 0x0060 +#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_BR 0x0061 +#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_WINDOW_OFFSET 0x0080 +#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_RULE 0x0083 +#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_TL 0x0084 +#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_BR 0x0085 +#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_TL 0x0086 +#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_BR 0x0087 +#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_TL 0x0088 +#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_BR 0x0089 +#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_TL 0x008a +#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_BR 0x008b +#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define regPA_SC_EDGERULE 0x008c +#define regPA_SC_EDGERULE_BASE_IDX 1 +#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define regPA_CL_UCP_0_X 0x00b4 +#define regPA_CL_UCP_0_X_BASE_IDX 1 +#define regPA_CL_UCP_0_Y 0x00b5 +#define regPA_CL_UCP_0_Y_BASE_IDX 1 +#define regPA_CL_UCP_0_Z 0x00b6 +#define regPA_CL_UCP_0_Z_BASE_IDX 1 +#define regPA_CL_UCP_0_W 0x00b7 +#define regPA_CL_UCP_0_W_BASE_IDX 1 +#define regPA_CL_UCP_1_X 0x00b8 +#define regPA_CL_UCP_1_X_BASE_IDX 1 +#define regPA_CL_UCP_1_Y 0x00b9 +#define regPA_CL_UCP_1_Y_BASE_IDX 1 +#define regPA_CL_UCP_1_Z 0x00ba +#define regPA_CL_UCP_1_Z_BASE_IDX 1 +#define regPA_CL_UCP_1_W 0x00bb +#define regPA_CL_UCP_1_W_BASE_IDX 1 +#define regPA_CL_UCP_2_X 0x00bc +#define regPA_CL_UCP_2_X_BASE_IDX 1 +#define regPA_CL_UCP_2_Y 0x00bd +#define regPA_CL_UCP_2_Y_BASE_IDX 1 +#define regPA_CL_UCP_2_Z 0x00be +#define regPA_CL_UCP_2_Z_BASE_IDX 1 +#define regPA_CL_UCP_2_W 0x00bf +#define regPA_CL_UCP_2_W_BASE_IDX 1 +#define regPA_CL_UCP_3_X 0x00c0 +#define regPA_CL_UCP_3_X_BASE_IDX 1 +#define regPA_CL_UCP_3_Y 0x00c1 +#define regPA_CL_UCP_3_Y_BASE_IDX 1 +#define regPA_CL_UCP_3_Z 0x00c2 +#define regPA_CL_UCP_3_Z_BASE_IDX 1 +#define regPA_CL_UCP_3_W 0x00c3 +#define regPA_CL_UCP_3_W_BASE_IDX 1 +#define regPA_CL_UCP_4_X 0x00c4 +#define regPA_CL_UCP_4_X_BASE_IDX 1 +#define regPA_CL_UCP_4_Y 0x00c5 +#define regPA_CL_UCP_4_Y_BASE_IDX 1 +#define regPA_CL_UCP_4_Z 0x00c6 +#define regPA_CL_UCP_4_Z_BASE_IDX 1 +#define regPA_CL_UCP_4_W 0x00c7 +#define regPA_CL_UCP_4_W_BASE_IDX 1 +#define regPA_CL_UCP_5_X 0x00c8 +#define regPA_CL_UCP_5_X_BASE_IDX 1 +#define regPA_CL_UCP_5_Y 0x00c9 +#define regPA_CL_UCP_5_Y_BASE_IDX 1 +#define regPA_CL_UCP_5_Z 0x00ca +#define regPA_CL_UCP_5_Z_BASE_IDX 1 +#define regPA_CL_UCP_5_W 0x00cb +#define regPA_CL_UCP_5_W_BASE_IDX 1 +#define regPA_CL_PROG_NEAR_CLIP_Z 0x00cc +#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 +#define regPA_RATE_CNTL 0x00cd +#define regPA_RATE_CNTL_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG 0x00d4 +#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG_1 0x00d5 +#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_EXT 0x00dd +#define regPA_SC_CLIPRECT_0_EXT_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_EXT 0x00de +#define regPA_SC_CLIPRECT_1_EXT_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_EXT 0x00df +#define regPA_SC_CLIPRECT_2_EXT_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_EXT 0x00e0 +#define regPA_SC_CLIPRECT_3_EXT_BASE_IDX 1 +#define regPA_SC_VRS_OVERRIDE_CNTL 0x00f4 +#define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE 0x00f5 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00f6 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00f7 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX 1 +#define regPA_SC_VRS_INFO 0x00f8 +#define regPA_SC_VRS_INFO_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE 0x00fc +#define regPA_SC_VRS_RATE_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE_EXT 0x00fd +#define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_SIZE_XY 0x00fe +#define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX 1 +#define regCB_RMI_GL2_CACHE_CONTROL 0x0104 +#define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 +#define regCB_BLEND_RED 0x0105 +#define regCB_BLEND_RED_BASE_IDX 1 +#define regCB_BLEND_GREEN 0x0106 +#define regCB_BLEND_GREEN_BASE_IDX 1 +#define regCB_BLEND_BLUE 0x0107 +#define regCB_BLEND_BLUE_BASE_IDX 1 +#define regCB_BLEND_ALPHA 0x0108 +#define regCB_BLEND_ALPHA_BASE_IDX 1 +#define regPA_CL_GB_VERT_CLIP_ADJ 0x010b +#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_VERT_DISC_ADJ 0x010c +#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_CLIP_ADJ 0x010d +#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_DISC_ADJ 0x010e +#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE 0x010f +#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET 0x0110 +#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE 0x0111 +#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET 0x0112 +#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE 0x0113 +#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET 0x0114 +#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_0 0x0115 +#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_0 0x0116 +#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_1 0x0117 +#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_1 0x0118 +#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_1 0x0119 +#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_1 0x011a +#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_1 0x011b +#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_1 0x011c +#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_1 0x011d +#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_1 0x011e +#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_2 0x011f +#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_2 0x0120 +#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_2 0x0121 +#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_2 0x0122 +#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_2 0x0123 +#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_2 0x0124 +#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_2 0x0125 +#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_2 0x0126 +#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_3 0x0127 +#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_3 0x0128 +#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_3 0x0129 +#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_3 0x012a +#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_3 0x012b +#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_3 0x012c +#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_3 0x012d +#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_3 0x012e +#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_4 0x012f +#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_4 0x0130 +#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_4 0x0131 +#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_4 0x0132 +#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_4 0x0133 +#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_4 0x0134 +#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_4 0x0135 +#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_4 0x0136 +#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_5 0x0137 +#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_5 0x0138 +#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_5 0x0139 +#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_5 0x013a +#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_5 0x013b +#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_5 0x013c +#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_5 0x013d +#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_5 0x013e +#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_6 0x013f +#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_6 0x0140 +#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_6 0x0141 +#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_6 0x0142 +#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_6 0x0143 +#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_6 0x0144 +#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_6 0x0145 +#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_6 0x0146 +#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_7 0x0147 +#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_7 0x0148 +#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_7 0x0149 +#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_7 0x014a +#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_7 0x014b +#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_7 0x014c +#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_7 0x014d +#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_7 0x014e +#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_8 0x014f +#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_8 0x0150 +#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_8 0x0151 +#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_8 0x0152 +#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_8 0x0153 +#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_8 0x0154 +#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_8 0x0155 +#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_8 0x0156 +#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_9 0x0157 +#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_9 0x0158 +#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_9 0x0159 +#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_9 0x015a +#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_9 0x015b +#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_9 0x015c +#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_9 0x015d +#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_9 0x015e +#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_10 0x015f +#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_10 0x0160 +#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_10 0x0161 +#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_10 0x0162 +#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_10 0x0163 +#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_10 0x0164 +#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_10 0x0165 +#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_10 0x0166 +#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_11 0x0167 +#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_11 0x0168 +#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_11 0x0169 +#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_11 0x016a +#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_11 0x016b +#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_11 0x016c +#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_11 0x016d +#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_11 0x016e +#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_12 0x016f +#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_12 0x0170 +#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_12 0x0171 +#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_12 0x0172 +#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_12 0x0173 +#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_12 0x0174 +#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_12 0x0175 +#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_12 0x0176 +#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_13 0x0177 +#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_13 0x0178 +#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_13 0x0179 +#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_13 0x017a +#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_13 0x017b +#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_13 0x017c +#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_13 0x017d +#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_13 0x017e +#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_14 0x017f +#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_14 0x0180 +#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_14 0x0181 +#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_14 0x0182 +#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_14 0x0183 +#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_14 0x0184 +#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_14 0x0185 +#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_14 0x0186 +#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_15 0x0187 +#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_15 0x0188 +#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_15 0x0189 +#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_15 0x018a +#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_15 0x018b +#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_15 0x018c +#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_15 0x018d +#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_15 0x018e +#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define regSPI_PS_IN_CONTROL 0x0190 +#define regSPI_PS_IN_CONTROL_BASE_IDX 1 +#define regSPI_INTERP_CONTROL_0 0x0191 +#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define regSPI_SHADER_IDX_FORMAT 0x0192 +#define regSPI_SHADER_IDX_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_POS_FORMAT 0x0193 +#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_Z_FORMAT 0x0194 +#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_COL_FORMAT 0x0195 +#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define regSPI_BARYC_CNTL 0x0196 +#define regSPI_BARYC_CNTL_BASE_IDX 1 +#define regSPI_PS_INPUT_ENA 0x0197 +#define regSPI_PS_INPUT_ENA_BASE_IDX 1 +#define regSPI_PS_INPUT_ADDR 0x0198 +#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_0 0x0199 +#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_1 0x019a +#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_2 0x019b +#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_3 0x019c +#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_4 0x019d +#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_5 0x019e +#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_6 0x019f +#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_7 0x01a0 +#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_8 0x01a1 +#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_9 0x01a2 +#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_10 0x01a3 +#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_11 0x01a4 +#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_12 0x01a5 +#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_13 0x01a6 +#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_14 0x01a7 +#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_15 0x01a8 +#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_16 0x01a9 +#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_17 0x01aa +#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_18 0x01ab +#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_19 0x01ac +#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_20 0x01ad +#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_21 0x01ae +#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_22 0x01af +#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_23 0x01b0 +#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_24 0x01b1 +#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_25 0x01b2 +#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_26 0x01b3 +#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_27 0x01b4 +#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_28 0x01b5 +#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_29 0x01b6 +#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_30 0x01b7 +#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_31 0x01b8 +#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define regSPI_BARYC_SSAA_CNTL 0x01b9 +#define regSPI_BARYC_SSAA_CNTL_BASE_IDX 1 +#define regSPI_TMPRING_SIZE 0x01ba +#define regSPI_TMPRING_SIZE_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_LO 0x01bb +#define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_HI 0x01bc +#define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT_CONTROL 0x01d4 +#define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT 0x01d5 +#define regSX_PS_DOWNCONVERT_BASE_IDX 1 +#define regSX_BLEND_OPT_EPSILON 0x01d6 +#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 +#define regSX_BLEND_OPT_CONTROL 0x01d7 +#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 +#define regSX_MRT0_BLEND_OPT 0x01d8 +#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT1_BLEND_OPT 0x01d9 +#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT2_BLEND_OPT 0x01da +#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT3_BLEND_OPT 0x01db +#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT4_BLEND_OPT 0x01dc +#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT5_BLEND_OPT 0x01dd +#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT6_BLEND_OPT 0x01de +#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT7_BLEND_OPT 0x01df +#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 +#define regCB_BLEND0_CONTROL 0x01e0 +#define regCB_BLEND0_CONTROL_BASE_IDX 1 +#define regCB_BLEND1_CONTROL 0x01e1 +#define regCB_BLEND1_CONTROL_BASE_IDX 1 +#define regCB_BLEND2_CONTROL 0x01e2 +#define regCB_BLEND2_CONTROL_BASE_IDX 1 +#define regCB_BLEND3_CONTROL 0x01e3 +#define regCB_BLEND3_CONTROL_BASE_IDX 1 +#define regCB_BLEND4_CONTROL 0x01e4 +#define regCB_BLEND4_CONTROL_BASE_IDX 1 +#define regCB_BLEND5_CONTROL 0x01e5 +#define regCB_BLEND5_CONTROL_BASE_IDX 1 +#define regCB_BLEND6_CONTROL 0x01e6 +#define regCB_BLEND6_CONTROL_BASE_IDX 1 +#define regCB_BLEND7_CONTROL 0x01e7 +#define regCB_BLEND7_CONTROL_BASE_IDX 1 +#define regPA_CL_POINT_X_RAD 0x01f5 +#define regPA_CL_POINT_X_RAD_BASE_IDX 1 +#define regPA_CL_POINT_Y_RAD 0x01f6 +#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define regPA_CL_POINT_SIZE 0x01f7 +#define regPA_CL_POINT_SIZE_BASE_IDX 1 +#define regPA_CL_POINT_CULL_RAD 0x01f8 +#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define regGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff +#define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 +#define regPA_CL_CLIP_CNTL 0x0204 +#define regPA_CL_CLIP_CNTL_BASE_IDX 1 +#define regPA_CL_VTE_CNTL 0x0205 +#define regPA_CL_VTE_CNTL_BASE_IDX 1 +#define regPA_CL_VS_OUT_CNTL 0x0206 +#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define regPA_SU_SC_MODE_CNTL 0x0207 +#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define regPA_CL_NANINF_CNTL 0x0208 +#define regPA_CL_NANINF_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_SCALE 0x020a +#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define regPA_SU_PRIM_FILTER_CNTL 0x020b +#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_CL_NGG_CNTL 0x020e +#define regPA_CL_NGG_CNTL_BASE_IDX 1 +#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_STEREO_CNTL 0x0210 +#define regPA_STEREO_CNTL_BASE_IDX 1 +#define regPA_STATE_STEREO_X 0x0211 +#define regPA_STATE_STEREO_X_BASE_IDX 1 +#define regPA_CL_VRS_CNTL 0x0212 +#define regPA_CL_VRS_CNTL_BASE_IDX 1 +#define regCB_TARGET_MASK 0x0214 +#define regCB_TARGET_MASK_BASE_IDX 1 +#define regCB_SHADER_MASK 0x0215 +#define regCB_SHADER_MASK_BASE_IDX 1 +#define regCB_COLOR_CONTROL 0x0216 +#define regCB_COLOR_CONTROL_BASE_IDX 1 +#define regPA_SU_POINT_SIZE 0x0280 +#define regPA_SU_POINT_SIZE_BASE_IDX 1 +#define regPA_SU_POINT_MINMAX 0x0281 +#define regPA_SU_POINT_MINMAX_BASE_IDX 1 +#define regPA_SU_LINE_CNTL 0x0282 +#define regPA_SU_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE 0x0283 +#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_RESET 0x0291 +#define regPA_SC_LINE_STIPPLE_RESET_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_0 0x0292 +#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_1 0x0293 +#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define regGE_SE_ENHANCE 0x0294 +#define regGE_SE_ENHANCE_BASE_IDX 1 +#define regVGT_REUSE_OFF 0x02a7 +#define regVGT_REUSE_OFF_BASE_IDX 1 +#define regVGT_DRAW_PAYLOAD_CNTL 0x02a8 +#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define regDB_HTILE_SURFACE 0x02af +#define regDB_HTILE_SURFACE_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define regVGT_GS_MAX_VERT_OUT 0x02ce +#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define regVGT_GS_INSTANCE_CNT 0x02cf +#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define regGE_NGG_SUBGRP_CNTL 0x02d3 +#define regGE_NGG_SUBGRP_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_CLAMP 0x02df +#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define regPA_SC_HIZ_INFO 0x02e5 +#define regPA_SC_HIZ_INFO_BASE_IDX 1 +#define regPA_SC_HIS_INFO 0x02e6 +#define regPA_SC_HIS_INFO_BASE_IDX 1 +#define regPA_SC_HIZ_BASE 0x02e7 +#define regPA_SC_HIZ_BASE_BASE_IDX 1 +#define regPA_SC_HIZ_BASE_EXT 0x02e8 +#define regPA_SC_HIZ_BASE_EXT_BASE_IDX 1 +#define regPA_SC_HIZ_SIZE_XY 0x02e9 +#define regPA_SC_HIZ_SIZE_XY_BASE_IDX 1 +#define regPA_SC_HIS_BASE 0x02ea +#define regPA_SC_HIS_BASE_BASE_IDX 1 +#define regPA_SC_HIS_BASE_EXT 0x02eb +#define regPA_SC_HIS_BASE_EXT_BASE_IDX 1 +#define regPA_SC_HIS_SIZE_XY 0x02ec +#define regPA_SC_HIS_SIZE_XY_BASE_IDX 1 +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL 0x02ed +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL_BASE_IDX 1 +#define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT 0x02ee +#define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT_BASE_IDX 1 +#define regPA_SC_HISZ_CONTROL 0x02ef +#define regPA_SC_HISZ_CONTROL_BASE_IDX 1 +#define regPA_SC_HISZ_RENDER_OVERRIDE 0x02f0 +#define regPA_SC_HISZ_RENDER_OVERRIDE_BASE_IDX 1 +#define regPA_SC_LINE_CNTL 0x02f7 +#define regPA_SC_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_AA_CONFIG 0x02f8 +#define regPA_SC_AA_CONFIG_BASE_IDX 1 +#define regPA_SU_VTX_CNTL 0x02f9 +#define regPA_SU_VTX_CNTL_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_0 0x02fc +#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_1 0x02fd +#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER 0x0310 +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_0 0x0311 +#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_1 0x0312 +#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_2 0x0313 +#define regPA_SC_BINNER_CNTL_2_BASE_IDX 1 +#define regPA_SC_NGG_MODE_CNTL 0x0314 +#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0315 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_SC_SHADER_CONTROL 0x0316 +#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define regPA_SC_SAMPLE_PROPERTIES 0x0317 +#define regPA_SC_SAMPLE_PROPERTIES_BASE_IDX 1 +#define regCB_COLOR0_BASE 0x0318 +#define regCB_COLOR0_BASE_BASE_IDX 1 +#define regCB_COLOR0_VIEW 0x0319 +#define regCB_COLOR0_VIEW_BASE_IDX 1 +#define regCB_COLOR0_VIEW2 0x031a +#define regCB_COLOR0_VIEW2_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB 0x031b +#define regCB_COLOR0_ATTRIB_BASE_IDX 1 +#define regCB_COLOR0_FDCC_CONTROL 0x031c +#define regCB_COLOR0_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB2 0x031e +#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB3 0x031f +#define regCB_COLOR0_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR1_BASE 0x0321 +#define regCB_COLOR1_BASE_BASE_IDX 1 +#define regCB_COLOR1_VIEW 0x0322 +#define regCB_COLOR1_VIEW_BASE_IDX 1 +#define regCB_COLOR1_VIEW2 0x0323 +#define regCB_COLOR1_VIEW2_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB 0x0324 +#define regCB_COLOR1_ATTRIB_BASE_IDX 1 +#define regCB_COLOR1_FDCC_CONTROL 0x0325 +#define regCB_COLOR1_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB2 0x0327 +#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB3 0x0328 +#define regCB_COLOR1_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR2_BASE 0x032a +#define regCB_COLOR2_BASE_BASE_IDX 1 +#define regCB_COLOR2_VIEW 0x032b +#define regCB_COLOR2_VIEW_BASE_IDX 1 +#define regCB_COLOR2_VIEW2 0x032c +#define regCB_COLOR2_VIEW2_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB 0x032d +#define regCB_COLOR2_ATTRIB_BASE_IDX 1 +#define regCB_COLOR2_FDCC_CONTROL 0x032e +#define regCB_COLOR2_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB2 0x0330 +#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB3 0x0331 +#define regCB_COLOR2_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR3_BASE 0x0333 +#define regCB_COLOR3_BASE_BASE_IDX 1 +#define regCB_COLOR3_VIEW 0x0334 +#define regCB_COLOR3_VIEW_BASE_IDX 1 +#define regCB_COLOR3_VIEW2 0x0335 +#define regCB_COLOR3_VIEW2_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB 0x0336 +#define regCB_COLOR3_ATTRIB_BASE_IDX 1 +#define regCB_COLOR3_FDCC_CONTROL 0x0337 +#define regCB_COLOR3_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB2 0x0339 +#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB3 0x033a +#define regCB_COLOR3_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR4_BASE 0x033c +#define regCB_COLOR4_BASE_BASE_IDX 1 +#define regCB_COLOR4_VIEW 0x033d +#define regCB_COLOR4_VIEW_BASE_IDX 1 +#define regCB_COLOR4_VIEW2 0x033e +#define regCB_COLOR4_VIEW2_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB 0x033f +#define regCB_COLOR4_ATTRIB_BASE_IDX 1 +#define regCB_COLOR4_FDCC_CONTROL 0x0340 +#define regCB_COLOR4_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB2 0x0342 +#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB3 0x0343 +#define regCB_COLOR4_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR5_BASE 0x0345 +#define regCB_COLOR5_BASE_BASE_IDX 1 +#define regCB_COLOR5_VIEW 0x0346 +#define regCB_COLOR5_VIEW_BASE_IDX 1 +#define regCB_COLOR5_VIEW2 0x0347 +#define regCB_COLOR5_VIEW2_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB 0x0348 +#define regCB_COLOR5_ATTRIB_BASE_IDX 1 +#define regCB_COLOR5_FDCC_CONTROL 0x0349 +#define regCB_COLOR5_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB2 0x034b +#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB3 0x034c +#define regCB_COLOR5_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR6_BASE 0x034e +#define regCB_COLOR6_BASE_BASE_IDX 1 +#define regCB_COLOR6_VIEW 0x034f +#define regCB_COLOR6_VIEW_BASE_IDX 1 +#define regCB_COLOR6_VIEW2 0x0350 +#define regCB_COLOR6_VIEW2_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB 0x0351 +#define regCB_COLOR6_ATTRIB_BASE_IDX 1 +#define regCB_COLOR6_FDCC_CONTROL 0x0352 +#define regCB_COLOR6_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB2 0x0354 +#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB3 0x0355 +#define regCB_COLOR6_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR7_BASE 0x0357 +#define regCB_COLOR7_BASE_BASE_IDX 1 +#define regCB_COLOR7_VIEW 0x0358 +#define regCB_COLOR7_VIEW_BASE_IDX 1 +#define regCB_COLOR7_VIEW2 0x0359 +#define regCB_COLOR7_VIEW2_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB 0x035a +#define regCB_COLOR7_ATTRIB_BASE_IDX 1 +#define regCB_COLOR7_FDCC_CONTROL 0x035b +#define regCB_COLOR7_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB2 0x035d +#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB3 0x035e +#define regCB_COLOR7_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR0_BASE_EXT 0x0390 +#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_BASE_EXT 0x0391 +#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_BASE_EXT 0x0392 +#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_BASE_EXT 0x0393 +#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_BASE_EXT 0x0394 +#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_BASE_EXT 0x0395 +#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_BASE_EXT 0x0396 +#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_BASE_EXT 0x0397 +#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_INFO 0x03b0 +#define regCB_COLOR0_INFO_BASE_IDX 1 +#define regCB_COLOR1_INFO 0x03b1 +#define regCB_COLOR1_INFO_BASE_IDX 1 +#define regCB_COLOR2_INFO 0x03b2 +#define regCB_COLOR2_INFO_BASE_IDX 1 +#define regCB_COLOR3_INFO 0x03b3 +#define regCB_COLOR3_INFO_BASE_IDX 1 +#define regCB_COLOR4_INFO 0x03b4 +#define regCB_COLOR4_INFO_BASE_IDX 1 +#define regCB_COLOR5_INFO 0x03b5 +#define regCB_COLOR5_INFO_BASE_IDX 1 +#define regCB_COLOR6_INFO 0x03b6 +#define regCB_COLOR6_INFO_BASE_IDX 1 +#define regCB_COLOR7_INFO 0x03b7 +#define regCB_COLOR7_INFO_BASE_IDX 1 +#define regCB_MEM0_INFO 0x03c0 +#define regCB_MEM0_INFO_BASE_IDX 1 +#define regCB_MEM1_INFO 0x03c1 +#define regCB_MEM1_INFO_BASE_IDX 1 +#define regCB_MEM2_INFO 0x03c2 +#define regCB_MEM2_INFO_BASE_IDX 1 +#define regCB_MEM3_INFO 0x03c3 +#define regCB_MEM3_INFO_BASE_IDX 1 +#define regCB_MEM4_INFO 0x03c4 +#define regCB_MEM4_INFO_BASE_IDX 1 +#define regCB_MEM5_INFO 0x03c5 +#define regCB_MEM5_INFO_BASE_IDX 1 +#define regCB_MEM6_INFO 0x03c6 +#define regCB_MEM6_INFO_BASE_IDX 1 +#define regCB_MEM7_INFO 0x03c7 +#define regCB_MEM7_INFO_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_padec +// base address: 0x2a500 +#define regPA_SC_VRS_SURFACE_CNTL 0x0940 +#define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_ENHANCE 0x0941 +#define regPA_SC_ENHANCE_BASE_IDX 1 +#define regPA_SC_ENHANCE_1 0x0942 +#define regPA_SC_ENHANCE_1_BASE_IDX 1 +#define regPA_SC_ENHANCE_2 0x0943 +#define regPA_SC_ENHANCE_2_BASE_IDX 1 +#define regPA_SC_ENHANCE_3 0x0944 +#define regPA_SC_ENHANCE_3_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_OVERRIDE 0x0946 +#define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 1 +#define regPA_SC_PBB_OVERRIDE_FLAG 0x0947 +#define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 1 +#define regPA_SC_DSM_CNTL 0x0948 +#define regPA_SC_DSM_CNTL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x0949 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 1 +#define regPA_SC_FIFO_SIZE 0x094a +#define regPA_SC_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_IF_FIFO_SIZE 0x094b +#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_PACKER_WAVE_ID_CNTL 0x094c +#define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX 1 +#define regPA_SC_ATM_CNTL 0x094d +#define regPA_SC_ATM_CNTL_BASE_IDX 1 +#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x094e +#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 1 +#define regPA_SC_FORCE_EOV_MAX_CNTS 0x094f +#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_0 0x0950 +#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_1 0x0951 +#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_2 0x0952 +#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_3 0x0953 +#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 1 +#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x0954 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_0 0x0955 +#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_1 0x0956 +#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_2 0x0957 +#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_3 0x0958 +#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x095b +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x095c +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x095d +#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_PH_INTERFACE_FIFO_SIZE 0x095e +#define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 1 +#define regPA_PH_ENHANCE 0x095f +#define regPA_PH_ENHANCE_BASE_IDX 1 +#define regPA_SC_VRS_SURFACE_CNTL_1 0x0960 +#define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX 1 +#define regPA_SC_HIZ_SURFACE_CNTL 0x0961 +#define regPA_SC_HIZ_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_HIS_SURFACE_CNTL 0x0962 +#define regPA_SC_HIS_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_HIZ_DEBUG 0x0963 +#define regPA_SC_HIZ_DEBUG_BASE_IDX 1 +#define regPA_SC_HIS_DEBUG 0x0964 +#define regPA_SC_HIS_DEBUG_BASE_IDX 1 +#define regSC_MEM_SCOPE 0x0965 +#define regSC_MEM_SCOPE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_sqdec +// base address: 0x2a780 +#define regSQ_RUNTIME_CONFIG 0x09e0 +#define regSQ_RUNTIME_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL 0x09e1 +#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL2 0x09e2 +#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 1 +#define regSH_MEM_BASES 0x09e3 +#define regSH_MEM_BASES_BASE_IDX 1 +#define regSH_MEM_CONFIG 0x09e4 +#define regSH_MEM_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG 0x09e5 +#define regSQ_DEBUG_BASE_IDX 1 +#define regSQ_SHADER_TBA_LO 0x09e6 +#define regSQ_SHADER_TBA_LO_BASE_IDX 1 +#define regSQ_SHADER_TBA_HI 0x09e7 +#define regSQ_SHADER_TBA_HI_BASE_IDX 1 +#define regSQ_SHADER_TMA_LO 0x09e8 +#define regSQ_SHADER_TMA_LO_BASE_IDX 1 +#define regSQ_SHADER_TMA_HI 0x09e9 +#define regSQ_SHADER_TMA_HI_BASE_IDX 1 +#define regSQ_IND_INDEX_USER 0x09ea +#define regSQ_IND_INDEX_USER_BASE_IDX 1 +#define regSQ_CMD_USER 0x09eb +#define regSQ_CMD_USER_BASE_IDX 1 +#define regSQ_IND_DATA_USER 0x09ec +#define regSQ_IND_DATA_USER_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_spidec +// base address: 0x2e500 +#define regSPI_CDBG_SYS_GFX 0x1940 +#define regSPI_CDBG_SYS_GFX_BASE_IDX 1 +#define regSPI_CDBG_SYS_HP3D 0x1941 +#define regSPI_CDBG_SYS_HP3D_BASE_IDX 1 +#define regSPI_CDBG_SYS_CS0 0x1942 +#define regSPI_CDBG_SYS_CS0_BASE_IDX 1 +#define regSPI_GDBG_WAVE_CNTL 0x1943 +#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 1 +#define regSPI_GDBG_TRAP_CONFIG 0x1944 +#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 1 +#define regSPI_GDBG_WAVE_CNTL3 0x1945 +#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 +#define regSPI_RESET_DEBUG 0x1946 +#define regSPI_RESET_DEBUG_BASE_IDX 1 +#define regGDS_COMPUTE_MAX_WAVE_ID 0x1947 +#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 1 +#define regSPI_ARB_CNTL_0 0x1949 +#define regSPI_ARB_CNTL_0_BASE_IDX 1 +#define regSPI_FEATURE_CTRL 0x194a +#define regSPI_FEATURE_CTRL_BASE_IDX 1 +#define regSPI_SHADER_RSRC_LIMIT_CTRL 0x194b +#define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 1 +#define regPC_CONFIG_CNTL_0 0x194c +#define regPC_CONFIG_CNTL_0_BASE_IDX 1 +#define regPC_CONFIG_CNTL_1 0x194d +#define regPC_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS 0x194e +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_utcl1dec +// base address: 0x2e600 +#define regUTCL1_CTRL_0 0x1980 +#define regUTCL1_CTRL_0_BASE_IDX 1 +#define regUTCL1_UTCL0_INVREQ_DISABLE 0x1981 +#define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 1 +#define regUTCL1_CTRL_2 0x1982 +#define regUTCL1_CTRL_2_BASE_IDX 1 +#define regUTCL1_FIFO_SIZING 0x1983 +#define regUTCL1_FIFO_SIZING_BASE_IDX 1 +#define regGCRD_SA0_TARGETS_DISABLE 0x1984 +#define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_SA1_TARGETS_DISABLE 0x1985 +#define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_CREDIT_SAFE 0x1986 +#define regGCRD_CREDIT_SAFE_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE0 0x1987 +#define regUTCL1_IDENTITY_MODE0_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE1 0x1988 +#define regUTCL1_IDENTITY_MODE1_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE2 0x1989 +#define regUTCL1_IDENTITY_MODE2_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE3 0x198a +#define regUTCL1_IDENTITY_MODE3_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE4 0x198b +#define regUTCL1_IDENTITY_MODE4_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE5 0x198c +#define regUTCL1_IDENTITY_MODE5_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE6 0x198d +#define regUTCL1_IDENTITY_MODE6_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE7 0x198e +#define regUTCL1_IDENTITY_MODE7_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_tcpdec +// base address: 0x2ef40 +#define regTCP_INVALIDATE 0x1bd0 +#define regTCP_INVALIDATE_BASE_IDX 1 +#define regTCP_STATUS 0x1bd1 +#define regTCP_STATUS_BASE_IDX 1 +#define regTCP_CNTL 0x1bd2 +#define regTCP_CNTL_BASE_IDX 1 +#define regTCP_CNTL2 0x1bd3 +#define regTCP_CNTL2_BASE_IDX 1 +#define regTCP_CREDIT 0x1bd4 +#define regTCP_CREDIT_BASE_IDX 1 +#define regTCP_DEBUG_DATA 0x1bd6 +#define regTCP_DEBUG_DATA_BASE_IDX 1 +#define regTCP_COMPRESSION_CNTL 0x1bd7 +#define regTCP_COMPRESSION_CNTL_BASE_IDX 1 +#define regTCP_ARB 0x1bd8 +#define regTCP_ARB_BASE_IDX 1 +#define regTCP_UTCL0_CNTL1 0x1bd9 +#define regTCP_UTCL0_CNTL1_BASE_IDX 1 +#define regTCP_UTCL0_CNTL2 0x1bda +#define regTCP_UTCL0_CNTL2_BASE_IDX 1 +#define regTCP_UTCL0_STATUS 0x1bdb +#define regTCP_UTCL0_STATUS_BASE_IDX 1 +#define regTCP_RQID_HASH_CNTL 0x1bdc +#define regTCP_RQID_HASH_CNTL_BASE_IDX 1 +#define regTCP_SET_HASH_CFG 0x1bdd +#define regTCP_SET_HASH_CFG_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET0 0x1bde +#define regTCP_SET_HASH_MASK_64_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET1 0x1bdf +#define regTCP_SET_HASH_MASK_64_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET2 0x1be0 +#define regTCP_SET_HASH_MASK_64_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET3 0x1be1 +#define regTCP_SET_HASH_MASK_64_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET0 0x1be2 +#define regTCP_SET_HASH_MASK_128_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET1 0x1be3 +#define regTCP_SET_HASH_MASK_128_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET2 0x1be4 +#define regTCP_SET_HASH_MASK_128_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET3 0x1be5 +#define regTCP_SET_HASH_MASK_128_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET4 0x1be6 +#define regTCP_SET_HASH_MASK_128_SET4_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET0 0x1be7 +#define regTCP_SET_HASH_MASK_192_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET1 0x1be8 +#define regTCP_SET_HASH_MASK_192_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET2 0x1be9 +#define regTCP_SET_HASH_MASK_192_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET3 0x1bea +#define regTCP_SET_HASH_MASK_192_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET0 0x1beb +#define regTCP_SET_HASH_MASK_256_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET1 0x1bec +#define regTCP_SET_HASH_MASK_256_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET2 0x1bed +#define regTCP_SET_HASH_MASK_256_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET3 0x1bee +#define regTCP_SET_HASH_MASK_256_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET4 0x1bef +#define regTCP_SET_HASH_MASK_256_SET4_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET5 0x1bf0 +#define regTCP_SET_HASH_MASK_256_SET5_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET0 0x1bf1 +#define regTCP_SET_HASH_MASK_320_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET1 0x1bf2 +#define regTCP_SET_HASH_MASK_320_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET2 0x1bf3 +#define regTCP_SET_HASH_MASK_320_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET3 0x1bf4 +#define regTCP_SET_HASH_MASK_320_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET0 0x1bf5 +#define regTCP_SET_HASH_MASK_384_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET1 0x1bf6 +#define regTCP_SET_HASH_MASK_384_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET2 0x1bf7 +#define regTCP_SET_HASH_MASK_384_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET3 0x1bf8 +#define regTCP_SET_HASH_MASK_384_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET4 0x1bf9 +#define regTCP_SET_HASH_MASK_384_SET4_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET0 0x1bfa +#define regTCP_SET_HASH_MASK_448_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET1 0x1bfb +#define regTCP_SET_HASH_MASK_448_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET2 0x1bfc +#define regTCP_SET_HASH_MASK_448_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET3 0x1bfd +#define regTCP_SET_HASH_MASK_448_SET3_BASE_IDX 1 +#define regTCP_CNTL3 0x1bfe +#define regTCP_CNTL3_BASE_IDX 1 +#define regLDS_CONFIG 0x1bff +#define regLDS_CONFIG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_spidec +// base address: 0x2f000 +#define regSPI_RESOURCE_RESERVE_CU_0 0x1c00 +#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_1 0x1c01 +#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_2 0x1c02 +#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_3 0x1c03 +#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_4 0x1c04 +#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_5 0x1c05 +#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_6 0x1c06 +#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_7 0x1c07 +#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_8 0x1c08 +#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_9 0x1c09 +#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_10 0x1c0a +#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_11 0x1c0b +#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_12 0x1c0c +#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_13 0x1c0d +#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_14 0x1c0e +#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_15 0x1c0f +#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x1c10 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x1c11 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x1c12 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x1c13 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x1c14 +#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x1c15 +#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x1c16 +#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x1c17 +#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x1c18 +#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x1c19 +#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x1c1a +#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x1c1b +#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x1c1c +#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x1c1d +#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x1c1e +#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x1c1f +#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_tcpdec +// base address: 0x2f4c0 +#define regTCP_UTCL0_THRASHING_CTRL 0x1d30 +#define regTCP_UTCL0_THRASHING_CTRL_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER 0x1d31 +#define regTCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER 0x1d32 +#define regTCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER_BASE_IDX 1 +#define regTCP_UTCL0_XNACK_RETRY 0x1d33 +#define regTCP_UTCL0_XNACK_RETRY_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_LO 0x1d34 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_LO_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_HI 0x1d35 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_HI_BASE_IDX 1 +#define regTXA_CNTL 0x1d36 +#define regTXA_CNTL_BASE_IDX 1 +#define regTXA_CNTL_AUX 0x1d37 +#define regTXA_CNTL_AUX_BASE_IDX 1 +#define regTXA_CNTL2 0x1d38 +#define regTXA_CNTL2_BASE_IDX 1 +#define regTXA_STATUS 0x1d39 +#define regTXA_STATUS_BASE_IDX 1 +#define regTXA_TDM_ARB_CNTL 0x1d3a +#define regTXA_TDM_ARB_CNTL_BASE_IDX 1 +#define regTCP_CREDIT2 0x1d3b +#define regTCP_CREDIT2_BASE_IDX 1 +#define regVC_CONGESTION_CONTROL 0x1d3c +#define regVC_CONGESTION_CONTROL_BASE_IDX 1 +#define regTXA_TDM_CNTL 0x1d3d +#define regTXA_TDM_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxudec +// base address: 0x30000 +#define regVGT_TF_RING_SIZE 0x224e +#define regVGT_TF_RING_SIZE_BASE_IDX 1 +#define regVGT_HS_OFFCHIP_PARAM 0x224f +#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define regGE_POS_RING_BASE 0x2268 +#define regGE_POS_RING_BASE_BASE_IDX 1 +#define regGE_POS_RING_SIZE 0x2269 +#define regGE_POS_RING_SIZE_BASE_IDX 1 +#define regGE_PRIM_RING_BASE 0x226a +#define regGE_PRIM_RING_BASE_BASE_IDX 1 +#define regGE_PRIM_RING_SIZE 0x226b +#define regGE_PRIM_RING_SIZE_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_STATE 0x2281 +#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_H 0x22b1 +#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_V 0x22b2 +#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_4 0x2344 +#define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_5 0x2345 +#define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_6 0x2346 +#define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_7 0x2347 +#define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 +#define regSQC_CACHES 0x2348 +#define regSQC_CACHES_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR 0x2380 +#define regTA_CS_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR_HI 0x2381 +#define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_HI 0x23c1 +#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_HI 0x23c3 +#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_HI 0x23c5 +#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_HI 0x23c7 +#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define regSPI_CONFIG_CNTL 0x2440 +#define regSPI_CONFIG_CNTL_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_1 0x2441 +#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_2 0x2442 +#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL1 0x2444 +#define regSPI_GS_THROTTLE_CNTL1_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL2 0x2445 +#define regSPI_GS_THROTTLE_CNTL2_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_BASE 0x2446 +#define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_SIZE 0x2447 +#define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX 1 +#define regSPI_SQG_EVENT_CTL 0x2448 +#define regSPI_SQG_EVENT_CTL_BASE_IDX 1 +#define regSPI_COMPUTE_WGS_CONTROL 0x2449 +#define regSPI_COMPUTE_WGS_CONTROL_BASE_IDX 1 +#define regSPI_GRP_LAUNCH_GUARANTEE_ENABLE 0x244a +#define regSPI_GRP_LAUNCH_GUARANTEE_ENABLE_BASE_IDX 1 +#define regSPI_GRP_LAUNCH_GUARANTEE_CTRL 0x244b +#define regSPI_GRP_LAUNCH_GUARANTEE_CTRL_BASE_IDX 1 +#define regSPI_GOG_ALLOCATION_CTRL 0x244c +#define regSPI_GOG_ALLOCATION_CTRL_BASE_IDX 1 +#define regSPI_TCP_CNTL 0x244d +#define regSPI_TCP_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_comp_wgsdec +// base address: 0x31a00 +#define regWGS_COMPUTE_DISPATCH_INITIATOR 0x2680 +#define regWGS_COMPUTE_DISPATCH_INITIATOR_BASE_IDX 1 +#define regWGS_COMPUTE_DIM_X 0x2681 +#define regWGS_COMPUTE_DIM_X_BASE_IDX 1 +#define regWGS_COMPUTE_DIM_Y 0x2682 +#define regWGS_COMPUTE_DIM_Y_BASE_IDX 1 +#define regWGS_COMPUTE_DIM_Z 0x2683 +#define regWGS_COMPUTE_DIM_Z_BASE_IDX 1 +#define regWGS_COMPUTE_START_X 0x2684 +#define regWGS_COMPUTE_START_X_BASE_IDX 1 +#define regWGS_COMPUTE_START_Y 0x2685 +#define regWGS_COMPUTE_START_Y_BASE_IDX 1 +#define regWGS_COMPUTE_START_Z 0x2686 +#define regWGS_COMPUTE_START_Z_BASE_IDX 1 +#define regWGS_COMPUTE_NUM_THREAD_X 0x2687 +#define regWGS_COMPUTE_NUM_THREAD_X_BASE_IDX 1 +#define regWGS_COMPUTE_NUM_THREAD_Y 0x2688 +#define regWGS_COMPUTE_NUM_THREAD_Y_BASE_IDX 1 +#define regWGS_COMPUTE_NUM_THREAD_Z 0x2689 +#define regWGS_COMPUTE_NUM_THREAD_Z_BASE_IDX 1 +#define regWGS_COMPUTE_PIPELINESTAT_ENABLE 0x268a +#define regWGS_COMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 1 +#define regWGS_COMPUTE_PERFCOUNT_ENABLE 0x268b +#define regWGS_COMPUTE_PERFCOUNT_ENABLE_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_LO 0x268c +#define regWGS_COMPUTE_PGM_LO_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_HI 0x268d +#define regWGS_COMPUTE_PGM_HI_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_LO 0x268e +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_HI 0x268f +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO 0x2690 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI 0x2691 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_RSRC1 0x2692 +#define regWGS_COMPUTE_PGM_RSRC1_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_RSRC2 0x2693 +#define regWGS_COMPUTE_PGM_RSRC2_BASE_IDX 1 +#define regWGS_COMPUTE_VMID 0x2694 +#define regWGS_COMPUTE_VMID_BASE_IDX 1 +#define regWGS_COMPUTE_RESOURCE_LIMITS 0x2695 +#define regWGS_COMPUTE_RESOURCE_LIMITS_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE0 0x2696 +#define regWGS_COMPUTE_DESTINATION_EN_SE0_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE0 0x2696 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE1 0x2697 +#define regWGS_COMPUTE_DESTINATION_EN_SE1_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE1 0x2697 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 1 +#define regWGS_COMPUTE_TMPRING_SIZE 0x2698 +#define regWGS_COMPUTE_TMPRING_SIZE_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE2 0x2699 +#define regWGS_COMPUTE_DESTINATION_EN_SE2_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE2 0x2699 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE3 0x269a +#define regWGS_COMPUTE_DESTINATION_EN_SE3_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE3 0x269a +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 1 +#define regWGS_COMPUTE_RESTART_X 0x269b +#define regWGS_COMPUTE_RESTART_X_BASE_IDX 1 +#define regWGS_COMPUTE_RESTART_Y 0x269c +#define regWGS_COMPUTE_RESTART_Y_BASE_IDX 1 +#define regWGS_COMPUTE_RESTART_Z 0x269d +#define regWGS_COMPUTE_RESTART_Z_BASE_IDX 1 +#define regWGS_COMPUTE_THREAD_TRACE_ENABLE 0x269e +#define regWGS_COMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 1 +#define regWGS_COMPUTE_MISC_RESERVED 0x269f +#define regWGS_COMPUTE_MISC_RESERVED_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_ID 0x26a0 +#define regWGS_COMPUTE_DISPATCH_ID_BASE_IDX 1 +#define regWGS_COMPUTE_THREADGROUP_ID 0x26a1 +#define regWGS_COMPUTE_THREADGROUP_ID_BASE_IDX 1 +#define regWGS_COMPUTE_REQ_CTRL 0x26a2 +#define regWGS_COMPUTE_REQ_CTRL_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE8 0x26a3 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE8_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_0 0x26a4 +#define regWGS_COMPUTE_USER_ACCUM_0_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_1 0x26a5 +#define regWGS_COMPUTE_USER_ACCUM_1_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_2 0x26a6 +#define regWGS_COMPUTE_USER_ACCUM_2_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_3 0x26a7 +#define regWGS_COMPUTE_USER_ACCUM_3_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_RSRC3 0x26a8 +#define regWGS_COMPUTE_PGM_RSRC3_BASE_IDX 1 +#define regWGS_COMPUTE_DDID_INDEX 0x26a9 +#define regWGS_COMPUTE_DDID_INDEX_BASE_IDX 1 +#define regWGS_COMPUTE_SHADER_CHKSUM 0x26aa +#define regWGS_COMPUTE_SHADER_CHKSUM_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE4 0x26ab +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE5 0x26ac +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE6 0x26ad +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE7 0x26ae +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_INTERLEAVE 0x26af +#define regWGS_COMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 1 +#define regWGS_COMPUTE_RELAUNCH 0x26b0 +#define regWGS_COMPUTE_RELAUNCH_BASE_IDX 1 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_LO 0x26b1 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 1 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_HI 0x26b2 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 1 +#define regWGS_COMPUTE_RELAUNCH2 0x26b3 +#define regWGS_COMPUTE_RELAUNCH2_BASE_IDX 1 +#define regWGS_COMPUTE_PRESCALED_DIM_X 0x26b5 +#define regWGS_COMPUTE_PRESCALED_DIM_X_BASE_IDX 1 +#define regWGS_COMPUTE_PRESCALED_DIM_Y 0x26b6 +#define regWGS_COMPUTE_PRESCALED_DIM_Y_BASE_IDX 1 +#define regWGS_COMPUTE_PRESCALED_DIM_Z 0x26b7 +#define regWGS_COMPUTE_PRESCALED_DIM_Z_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_0 0x26c0 +#define regWGS_COMPUTE_USER_DATA_0_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_1 0x26c1 +#define regWGS_COMPUTE_USER_DATA_1_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_2 0x26c2 +#define regWGS_COMPUTE_USER_DATA_2_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_3 0x26c3 +#define regWGS_COMPUTE_USER_DATA_3_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_4 0x26c4 +#define regWGS_COMPUTE_USER_DATA_4_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_5 0x26c5 +#define regWGS_COMPUTE_USER_DATA_5_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_6 0x26c6 +#define regWGS_COMPUTE_USER_DATA_6_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_7 0x26c7 +#define regWGS_COMPUTE_USER_DATA_7_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_8 0x26c8 +#define regWGS_COMPUTE_USER_DATA_8_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_9 0x26c9 +#define regWGS_COMPUTE_USER_DATA_9_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_10 0x26ca +#define regWGS_COMPUTE_USER_DATA_10_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_11 0x26cb +#define regWGS_COMPUTE_USER_DATA_11_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_12 0x26cc +#define regWGS_COMPUTE_USER_DATA_12_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_13 0x26cd +#define regWGS_COMPUTE_USER_DATA_13_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_14 0x26ce +#define regWGS_COMPUTE_USER_DATA_14_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_15 0x26cf +#define regWGS_COMPUTE_USER_DATA_15_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_TUNNEL 0x26fd +#define regWGS_COMPUTE_DISPATCH_TUNNEL_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_END 0x26fe +#define regWGS_COMPUTE_DISPATCH_END_BASE_IDX 1 +#define regWGS_COMPUTE_NOWHERE 0x26ff +#define regWGS_COMPUTE_NOWHERE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_wgsdec +// base address: 0x31c00 +#define regWGS_MGCG_SYNC_CNTL 0x2708 +#define regWGS_MGCG_SYNC_CNTL_BASE_IDX 1 +#define regWGS_INT_INFO 0x2709 +#define regWGS_INT_INFO_BASE_IDX 1 +#define regWGS_INT_CNTXID_LO 0x270a +#define regWGS_INT_CNTXID_LO_BASE_IDX 1 +#define regWGS_INT_CNTXID_HI 0x270b +#define regWGS_INT_CNTXID_HI_BASE_IDX 1 +#define regWGS_ERROR 0x270c +#define regWGS_ERROR_BASE_IDX 1 +#define regWGS_ENDIAN_SWAP 0x270d +#define regWGS_ENDIAN_SWAP_BASE_IDX 1 +#define regWGS_GEN_BASE_LO 0x2710 +#define regWGS_GEN_BASE_LO_BASE_IDX 1 +#define regWGS_GEN_BASE_HI 0x2711 +#define regWGS_GEN_BASE_HI_BASE_IDX 1 +#define regCGTT_WGS_CLK_CTRL 0x2712 +#define regCGTT_WGS_CLK_CTRL_BASE_IDX 1 +#define regWGS_ME1_UCODE_ADDR 0x2713 +#define regWGS_ME1_UCODE_ADDR_BASE_IDX 1 +#define regWGS_ME1_UCODE_DATA 0x2714 +#define regWGS_ME1_UCODE_DATA_BASE_IDX 1 +#define regWGS_ME1_UCODE_CHKSUM 0x2717 +#define regWGS_ME1_UCODE_CHKSUM_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x2719 +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x271a +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_CONTROL 0x271b +#define regWGS_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 1 +#define regWGS_SUSPEND_CNTL_STACK_OFFSET 0x271c +#define regWGS_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 1 +#define regWGS_SUSPEND_CNTL_STACK_SIZE 0x271d +#define regWGS_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 1 +#define regWGS_SUSPEND_WG_STATE_OFFSET 0x271e +#define regWGS_SUSPEND_WG_STATE_OFFSET_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_SIZE 0x271f +#define regWGS_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 1 +#define regWGS_OS_PIPES 0x2720 +#define regWGS_OS_PIPES_BASE_IDX 1 +#define regWGS_SUSPEND_RESUME_REQ 0x2721 +#define regWGS_SUSPEND_RESUME_REQ_BASE_IDX 1 +#define regWGS_IQ_WAIT_TIME3 0x2723 +#define regWGS_IQ_WAIT_TIME3_BASE_IDX 1 +#define regWGS_DDID_BASE_ADDR_LO 0x2724 +#define regWGS_DDID_BASE_ADDR_LO_BASE_IDX 1 +#define regWGS_DDID_BASE_ADDR_HI 0x2725 +#define regWGS_DDID_BASE_ADDR_HI_BASE_IDX 1 +#define regWGS_DDID_CNTL 0x2726 +#define regWGS_DDID_CNTL_BASE_IDX 1 +#define regWGS_RS64_PRGRM_CNTR_START 0x2727 +#define regWGS_RS64_PRGRM_CNTR_START_BASE_IDX 1 +#define regWGS_MTVEC_LO 0x2728 +#define regWGS_MTVEC_LO_BASE_IDX 1 +#define regWGS_MTVEC_HI 0x2729 +#define regWGS_MTVEC_HI_BASE_IDX 1 +#define regWGS_RS64_CNTL 0x272b +#define regWGS_RS64_CNTL_BASE_IDX 1 +#define regWGS_MIE_LO 0x272c +#define regWGS_MIE_LO_BASE_IDX 1 +#define regWGS_MIE_HI 0x272d +#define regWGS_MIE_HI_BASE_IDX 1 +#define regWGS_RS64_INTERRUPT 0x272e +#define regWGS_RS64_INTERRUPT_BASE_IDX 1 +#define regWGS_RS64_INSTR_PNTR 0x272f +#define regWGS_RS64_INSTR_PNTR_BASE_IDX 1 +#define regWGS_MIP_LO 0x2730 +#define regWGS_MIP_LO_BASE_IDX 1 +#define regWGS_MIP_HI 0x2731 +#define regWGS_MIP_HI_BASE_IDX 1 +#define regWGS_DC_BASE_CNTL 0x2732 +#define regWGS_DC_BASE_CNTL_BASE_IDX 1 +#define regWGS_DC_OP_CNTL 0x2733 +#define regWGS_DC_OP_CNTL_BASE_IDX 1 +#define regWGS_MTIMECMP_LO 0x2734 +#define regWGS_MTIMECMP_LO_BASE_IDX 1 +#define regWGS_MTIMECMP_HI 0x2735 +#define regWGS_MTIMECMP_HI_BASE_IDX 1 +#define regWGS_GP0_LO 0x2737 +#define regWGS_GP0_LO_BASE_IDX 1 +#define regWGS_GP0_HI 0x2738 +#define regWGS_GP0_HI_BASE_IDX 1 +#define regWGS_GP1_LO 0x2739 +#define regWGS_GP1_LO_BASE_IDX 1 +#define regWGS_GP1_HI 0x273a +#define regWGS_GP1_HI_BASE_IDX 1 +#define regWGS_GP2_LO 0x273b +#define regWGS_GP2_LO_BASE_IDX 1 +#define regWGS_GP2_HI 0x273c +#define regWGS_GP2_HI_BASE_IDX 1 +#define regWGS_GP3_LO 0x273d +#define regWGS_GP3_LO_BASE_IDX 1 +#define regWGS_GP3_HI 0x273e +#define regWGS_GP3_HI_BASE_IDX 1 +#define regWGS_GP4_LO 0x273f +#define regWGS_GP4_LO_BASE_IDX 1 +#define regWGS_GP4_HI 0x2740 +#define regWGS_GP4_HI_BASE_IDX 1 +#define regWGS_GP5_LO 0x2741 +#define regWGS_GP5_LO_BASE_IDX 1 +#define regWGS_GP5_HI 0x2742 +#define regWGS_GP5_HI_BASE_IDX 1 +#define regWGS_GP6_LO 0x2743 +#define regWGS_GP6_LO_BASE_IDX 1 +#define regWGS_GP6_HI 0x2744 +#define regWGS_GP6_HI_BASE_IDX 1 +#define regWGS_GP7_LO 0x2745 +#define regWGS_GP7_LO_BASE_IDX 1 +#define regWGS_GP7_HI 0x2746 +#define regWGS_GP7_HI_BASE_IDX 1 +#define regWGS_GP8_LO 0x2747 +#define regWGS_GP8_LO_BASE_IDX 1 +#define regWGS_GP8_HI 0x2748 +#define regWGS_GP8_HI_BASE_IDX 1 +#define regWGS_GP9_LO 0x2749 +#define regWGS_GP9_LO_BASE_IDX 1 +#define regWGS_GP9_HI 0x274a +#define regWGS_GP9_HI_BASE_IDX 1 +#define regWGS_DM_INDEX_ADDR 0x274b +#define regWGS_DM_INDEX_ADDR_BASE_IDX 1 +#define regWGS_DM_INDEX_DATA 0x274c +#define regWGS_DM_INDEX_DATA_BASE_IDX 1 +#define regWGS_LOCAL_BASE0_LO 0x274e +#define regWGS_LOCAL_BASE0_LO_BASE_IDX 1 +#define regWGS_LOCAL_BASE0_HI 0x274f +#define regWGS_LOCAL_BASE0_HI_BASE_IDX 1 +#define regWGS_LOCAL_MASK0_LO 0x2750 +#define regWGS_LOCAL_MASK0_LO_BASE_IDX 1 +#define regWGS_LOCAL_MASK0_HI 0x2751 +#define regWGS_LOCAL_MASK0_HI_BASE_IDX 1 +#define regWGS_LOCAL_APERTURE 0x2752 +#define regWGS_LOCAL_APERTURE_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_BASE_LO 0x2753 +#define regWGS_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_BASE_HI 0x2754 +#define regWGS_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_MASK_LO 0x2755 +#define regWGS_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_MASK_HI 0x2756 +#define regWGS_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_APERTURE 0x2757 +#define regWGS_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regWGS_LOCAL_SCRATCH_APERTURE 0x2758 +#define regWGS_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regWGS_LOCAL_SCRATCH_BASE_LO 0x2759 +#define regWGS_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regWGS_LOCAL_SCRATCH_BASE_HI 0x275a +#define regWGS_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regWGS_RS64_PERFCOUNT_CNTL 0x275b +#define regWGS_RS64_PERFCOUNT_CNTL_BASE_IDX 1 +#define regWGS_RS64_PENDING_INTERRUPT 0x275c +#define regWGS_RS64_PENDING_INTERRUPT_BASE_IDX 1 +#define regWGS_RS64_EXCEPTION_STATUS 0x275e +#define regWGS_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regWGS_RS64_PRGRM_CNTR_START_HI 0x275f +#define regWGS_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regWGS_DC_BASE_LO 0x2799 +#define regWGS_DC_BASE_LO_BASE_IDX 1 +#define regWGS_MDBASE_LO 0x2799 +#define regWGS_MDBASE_LO_BASE_IDX 1 +#define regWGS_DC_BASE_HI 0x279a +#define regWGS_DC_BASE_HI_BASE_IDX 1 +#define regWGS_MDBASE_HI 0x279a +#define regWGS_MDBASE_HI_BASE_IDX 1 +#define regWGS_MIBOUND_LO 0x279b +#define regWGS_MIBOUND_LO_BASE_IDX 1 +#define regWGS_MIBOUND_HI 0x279c +#define regWGS_MIBOUND_HI_BASE_IDX 1 +#define regWGS_MDBOUND_LO 0x279d +#define regWGS_MDBOUND_LO_BASE_IDX 1 +#define regWGS_MDBOUND_HI 0x279e +#define regWGS_MDBOUND_HI_BASE_IDX 1 +#define regWGS_IC_OP_CNTL 0x279f +#define regWGS_IC_OP_CNTL_BASE_IDX 1 +#define regWGS_INT_STATUS 0x27a3 +#define regWGS_INT_STATUS_BASE_IDX 1 +#define regWGS_IH_FREE_COUNT 0x27a4 +#define regWGS_IH_FREE_COUNT_BASE_IDX 1 +#define regWGS_ME1_PIPE_PRIORITY_CNTS 0x27a6 +#define regWGS_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regWGS_ME1_PIPE0_PRIORITY 0x27a7 +#define regWGS_ME1_PIPE0_PRIORITY_BASE_IDX 1 +#define regWGS_ME1_PIPE1_PRIORITY 0x27a8 +#define regWGS_ME1_PIPE1_PRIORITY_BASE_IDX 1 +#define regWGS_ME1_PIPE2_PRIORITY 0x27a9 +#define regWGS_ME1_PIPE2_PRIORITY_BASE_IDX 1 +#define regWGS_ME1_PIPE3_PRIORITY 0x27aa +#define regWGS_ME1_PIPE3_PRIORITY_BASE_IDX 1 +#define regWGS_IQ_WAIT_TIME1 0x27b4 +#define regWGS_IQ_WAIT_TIME1_BASE_IDX 1 +#define regWGS_IQ_WAIT_TIME2 0x27b5 +#define regWGS_IQ_WAIT_TIME2_BASE_IDX 1 +#define regWGS_IC_BASE_LO 0x27b7 +#define regWGS_IC_BASE_LO_BASE_IDX 1 +#define regWGS_IC_BASE_HI 0x27b8 +#define regWGS_IC_BASE_HI_BASE_IDX 1 +#define regWGS_IC_BASE_CNTL 0x27b9 +#define regWGS_IC_BASE_CNTL_BASE_IDX 1 +#define regWGS_UCODE_VERS 0x27bb +#define regWGS_UCODE_VERS_BASE_IDX 1 +#define regWGS_BUSY_HYSTERESIS 0x27bd +#define regWGS_BUSY_HYSTERESIS_BASE_IDX 1 +#define regWGS_STATUS 0x27d0 +#define regWGS_STATUS_BASE_IDX 1 +#define regWGS_BUSY_STAT 0x27d1 +#define regWGS_BUSY_STAT_BASE_IDX 1 +#define regWGS_STALLED_STAT1 0x27d2 +#define regWGS_STALLED_STAT1_BASE_IDX 1 +#define regWGS_BUSY_STAT2 0x27d3 +#define regWGS_BUSY_STAT2_BASE_IDX 1 +#define regWGS_ME1_HEADER_DUMP 0x27d4 +#define regWGS_ME1_HEADER_DUMP_BASE_IDX 1 +#define regWGS_SCRATCH_INDEX 0x27d6 +#define regWGS_SCRATCH_INDEX_BASE_IDX 1 +#define regWGS_SCRATCH_DATA 0x27d7 +#define regWGS_SCRATCH_DATA_BASE_IDX 1 +#define regWGS_LATENCY_STATS_SELECT 0x27d8 +#define regWGS_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regWGS_LATENCY_STATS_DATA 0x27d9 +#define regWGS_LATENCY_STATS_DATA_BASE_IDX 1 +#define regWGS_TC_PERF_COUNTER_WINDOW_SELECT 0x27da +#define regWGS_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regWGS_DATA1 0x27db +#define regWGS_DATA1_BASE_IDX 1 +#define regWGS_DATA2 0x27dc +#define regWGS_DATA2_BASE_IDX 1 +#define regWGS_DATA3 0x27dd +#define regWGS_DATA3_BASE_IDX 1 +#define regWGS_DATA4 0x27de +#define regWGS_DATA4_BASE_IDX 1 +#define regWGS_DATA5 0x27df +#define regWGS_DATA5_BASE_IDX 1 +#define regWGS_DATA6 0x27e0 +#define regWGS_DATA6_BASE_IDX 1 +#define regWGS_DATA7 0x27e1 +#define regWGS_DATA7_BASE_IDX 1 +#define regWGS_DATA8 0x27e2 +#define regWGS_DATA8_BASE_IDX 1 +#define regWGS_DATA9 0x27e3 +#define regWGS_DATA9_BASE_IDX 1 +#define regWGS_DATA10 0x27e4 +#define regWGS_DATA10_BASE_IDX 1 +#define regWGS_DATA11 0x27e5 +#define regWGS_DATA11_BASE_IDX 1 +#define regWGS_DATA12 0x27e6 +#define regWGS_DATA12_BASE_IDX 1 +#define regWGS_DATA13 0x27e7 +#define regWGS_DATA13_BASE_IDX 1 +#define regWGS_DATA14 0x27e8 +#define regWGS_DATA14_BASE_IDX 1 +#define regWGS_DATA15 0x27e9 +#define regWGS_DATA15_BASE_IDX 1 +#define regWGS_DATA16 0x27ea +#define regWGS_DATA16_BASE_IDX 1 +#define regWGS_METADATA_BASE_ADDR_LO 0x27eb +#define regWGS_METADATA_BASE_ADDR_LO_BASE_IDX 1 +#define regWGS_METADATA_BASE_ADDR_HI 0x27ec +#define regWGS_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regWGS_METADATA_CNTL 0x27ed +#define regWGS_METADATA_CNTL_BASE_IDX 1 +#define regWGS_IQ_TIMER 0x27ee +#define regWGS_IQ_TIMER_BASE_IDX 1 +#define regWGS_HALT_HYST_COUNT 0x27ef +#define regWGS_HALT_HYST_COUNT_BASE_IDX 1 +#define regWGS_IQ_TIMER_MESSAGE 0x27f0 +#define regWGS_IQ_TIMER_MESSAGE_BASE_IDX 1 +#define regWGS_RS64_THREAD_CNTL 0x27f6 +#define regWGS_RS64_THREAD_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1dec +// base address: 0x33400 +#define regGL1_ARB_CTRL 0x2d00 +#define regGL1_ARB_CTRL_BASE_IDX 1 +#define regGL1_DRAM_BURST_MASK 0x2d02 +#define regGL1_DRAM_BURST_MASK_BASE_IDX 1 +#define regGL1_ARB_STATUS 0x2d03 +#define regGL1_ARB_STATUS_BASE_IDX 1 +#define regGL1_DRAM_BURST_CTRL 0x2d04 +#define regGL1_DRAM_BURST_CTRL_BASE_IDX 1 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE 0x2d05 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGL1A_GL1C_CREDITS 0x2d08 +#define regGL1A_GL1C_CREDITS_BASE_IDX 1 +#define regGL1A_CLIENT_FREE_DELAY 0x2d09 +#define regGL1A_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regGL1X_ARB_CTRL 0x2d20 +#define regGL1X_ARB_CTRL_BASE_IDX 1 +#define regGL1X_DRAM_BURST_MASK 0x2d22 +#define regGL1X_DRAM_BURST_MASK_BASE_IDX 1 +#define regGL1X_ARB_STATUS 0x2d23 +#define regGL1X_ARB_STATUS_BASE_IDX 1 +#define regGL1X_DRAM_BURST_CTRL 0x2d24 +#define regGL1X_DRAM_BURST_CTRL_BASE_IDX 1 +#define regGL1XI_GL1XR_REP_FGCG_OVERRIDE 0x2d25 +#define regGL1XI_GL1XR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGL1XA_GL1XC_CREDITS 0x2d28 +#define regGL1XA_GL1XC_CREDITS_BASE_IDX 1 +#define regGL1XA_CLIENT_FREE_DELAY 0x2d29 +#define regGL1XA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regGL1XA_COMPRESSION_MODE 0x2d2a +#define regGL1XA_COMPRESSION_MODE_BASE_IDX 1 +#define regGL1XA_COMPRESSOR_OVERRIDE 0x2d2b +#define regGL1XA_COMPRESSOR_OVERRIDE_BASE_IDX 1 +#define regGL1C_CTRL 0x2d40 +#define regGL1C_CTRL_BASE_IDX 1 +#define regGL1C_STATUS 0x2d41 +#define regGL1C_STATUS_BASE_IDX 1 +#define regGL1C_CTRL2 0x2d46 +#define regGL1C_CTRL2_BASE_IDX 1 +#define regGL1XC_CTRL 0x2d47 +#define regGL1XC_CTRL_BASE_IDX 1 +#define regGL1XC_STATUS 0x2d48 +#define regGL1XC_STATUS_BASE_IDX 1 +#define regGL1XC_UTCL0_CNTL1 0x2d49 +#define regGL1XC_UTCL0_CNTL1_BASE_IDX 1 +#define regGL1XC_UTCL0_CNTL2 0x2d4a +#define regGL1XC_UTCL0_CNTL2_BASE_IDX 1 +#define regGL1XC_UTCL0_STATUS 0x2d4b +#define regGL1XC_UTCL0_STATUS_BASE_IDX 1 +#define regGL1XC_UTCL0_RETRY 0x2d4c +#define regGL1XC_UTCL0_RETRY_BASE_IDX 1 +#define regGL1XC_CTRL2 0x2d4d +#define regGL1XC_CTRL2_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_secacdec +// base address: 0x2f1c0 +#define regSE_CAC_CTRL_1 0x1c70 +#define regSE_CAC_CTRL_1_BASE_IDX 1 +#define regSE_CAC_CTRL_2 0x1c71 +#define regSE_CAC_CTRL_2_BASE_IDX 1 +#define regSE_CAC_SOFT_CTRL 0x1c72 +#define regSE_CAC_SOFT_CTRL_BASE_IDX 1 +#define regSE_CAC_OVR_VAL_LOWER 0x1c74 +#define regSE_CAC_OVR_VAL_LOWER_BASE_IDX 1 +#define regSE_CAC_OVR_VAL_UPPER 0x1c75 +#define regSE_CAC_OVR_VAL_UPPER_BASE_IDX 1 +#define regSE_CAC_WINDOW_AGGR_VALUE_LO 0x1c76 +#define regSE_CAC_WINDOW_AGGR_VALUE_LO_BASE_IDX 1 +#define regSE_CAC_WINDOW_AGGR_VALUE_HI 0x1c77 +#define regSE_CAC_WINDOW_AGGR_VALUE_HI_BASE_IDX 1 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE 0x1c78 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX 1 +#define regDIDT_EDC_CTRL 0x1c7c +#define regDIDT_EDC_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THROTTLE_CTRL 0x1c7d +#define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THRESHOLD 0x1c7e +#define regDIDT_EDC_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_STRETCH_THRESHOLD 0x1c7f +#define regDIDT_EDC_STRETCH_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_CLK_COUNTER_THRESHOLD 0x1c80 +#define regDIDT_EDC_CLK_COUNTER_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_1_2 0x1c81 +#define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_3_4 0x1c82 +#define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_5_6 0x1c83 +#define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_7 0x1c84 +#define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_EDC_STATUS 0x1c85 +#define regDIDT_EDC_STATUS_BASE_IDX 1 +#define regDIDT_EDC_OVERFLOW 0x1c86 +#define regDIDT_EDC_OVERFLOW_BASE_IDX 1 +#define regDIDT_EDC_ROLLING_POWER_DELTA 0x1c87 +#define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 +#define regDIDT_EDC_AVG_POWER_DELTA_HI 0x1c88 +#define regDIDT_EDC_AVG_POWER_DELTA_HI_BASE_IDX 1 +#define regDIDT_EDC_AVG_POWER_DELTA_LO 0x1c89 +#define regDIDT_EDC_AVG_POWER_DELTA_LO_BASE_IDX 1 +#define regDIDT_EDC_STALL_PERF_COUNTER 0x1c8a +#define regDIDT_EDC_STALL_PERF_COUNTER_BASE_IDX 1 +#define regDIDT_THRESHOLD 0x1c8c +#define regDIDT_THRESHOLD_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_0 0x1c93 +#define regSE_CAC_WEIGHT_LDS1_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_1 0x1c94 +#define regSE_CAC_WEIGHT_LDS1_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_2 0x1c95 +#define regSE_CAC_WEIGHT_LDS1_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_3 0x1c96 +#define regSE_CAC_WEIGHT_LDS1_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_0 0x1c9d +#define regSE_CAC_WEIGHT_TCP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_1 0x1c9e +#define regSE_CAC_WEIGHT_TCP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_2 0x1c9f +#define regSE_CAC_WEIGHT_TCP_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_3 0x1ca0 +#define regSE_CAC_WEIGHT_TCP_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_0 0x1ca1 +#define regSE_CAC_WEIGHT_SQ_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_1 0x1ca2 +#define regSE_CAC_WEIGHT_SQ_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_2 0x1ca3 +#define regSE_CAC_WEIGHT_SQ_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_0 0x1ca4 +#define regSE_CAC_WEIGHT_SP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_1 0x1ca5 +#define regSE_CAC_WEIGHT_SP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_2 0x1ca6 +#define regSE_CAC_WEIGHT_SP_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_0 0x1ca7 +#define regSE_CAC_WEIGHT_LDS0_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_1 0x1ca8 +#define regSE_CAC_WEIGHT_LDS0_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_2 0x1ca9 +#define regSE_CAC_WEIGHT_LDS0_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_3 0x1caa +#define regSE_CAC_WEIGHT_LDS0_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_0 0x1cac +#define regSE_CAC_WEIGHT_SQC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_1 0x1cad +#define regSE_CAC_WEIGHT_SQC_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CU_0 0x1cae +#define regSE_CAC_WEIGHT_CU_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_UTCL1_0 0x1cc3 +#define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_0 0x1cc4 +#define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_1 0x1cc5 +#define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_0 0x1cc6 +#define regSE_CAC_WEIGHT_SPI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_1 0x1cc7 +#define regSE_CAC_WEIGHT_SPI_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_2 0x1cc8 +#define regSE_CAC_WEIGHT_SPI_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_4 0x1cdc +#define regSE_CAC_WEIGHT_TCP_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_5 0x1cdd +#define regSE_CAC_WEIGHT_TCP_5_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_6 0x1cde +#define regSE_CAC_WEIGHT_TCP_6_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_7 0x1cdf +#define regSE_CAC_WEIGHT_TCP_7_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_8 0x1ce0 +#define regSE_CAC_WEIGHT_TCP_8_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_9 0x1ce1 +#define regSE_CAC_WEIGHT_TCP_9_BASE_IDX 1 +#define regSE_CAC_IND_INDEX 0x1d2e +#define regSE_CAC_IND_INDEX_BASE_IDX 1 +#define regSE_CAC_IND_DATA 0x1d2f +#define regSE_CAC_IND_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfddec +// base address: 0x34000 +#define regGE2_SE_PERFCOUNTER0_LO 0x30b4 +#define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_HI 0x30b5 +#define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_LO 0x30b6 +#define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_HI 0x30b7 +#define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_LO 0x30b8 +#define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_HI 0x30b9 +#define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_LO 0x30ba +#define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_HI 0x30bb +#define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER0_LO 0x30f8 +#define regGRBMH_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER0_HI 0x30f9 +#define regGRBMH_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER1_LO 0x30fa +#define regGRBMH_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER1_HI 0x30fb +#define regGRBMH_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_LO 0x3100 +#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_HI 0x3101 +#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_LO 0x3102 +#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_HI 0x3103 +#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_LO 0x3104 +#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_HI 0x3105 +#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_LO 0x3106 +#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_HI 0x3107 +#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_LO 0x3140 +#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_HI 0x3141 +#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_LO 0x3142 +#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_HI 0x3143 +#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_LO 0x3144 +#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_HI 0x3145 +#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_LO 0x3146 +#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_HI 0x3147 +#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_LO 0x3148 +#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_HI 0x3149 +#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_LO 0x314a +#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_HI 0x314b +#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_LO 0x314c +#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_HI 0x314d +#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_LO 0x314e +#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_HI 0x314f +#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_HI 0x3180 +#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_LO 0x3181 +#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_HI 0x3182 +#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_LO 0x3183 +#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_HI 0x3184 +#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_LO 0x3185 +#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_HI 0x3186 +#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_LO 0x3187 +#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_HI 0x3188 +#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_LO 0x3189 +#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_HI 0x318a +#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_LO 0x318b +#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER0_HI 0x318c +#define regPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER0_LO 0x318d +#define regPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER1_HI 0x318e +#define regPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER1_LO 0x318f +#define regPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER2_HI 0x3190 +#define regPC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER2_LO 0x3191 +#define regPC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER3_HI 0x3192 +#define regPC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER3_LO 0x3193 +#define regPC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_LO 0x31c0 +#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_LO 0x31c2 +#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_LO 0x31c4 +#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_LO 0x31c6 +#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_LO 0x31c8 +#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_LO 0x31ca +#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_LO 0x31cc +#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_LO 0x31ce +#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_LO 0x31e4 +#define regSQG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_HI 0x31e5 +#define regSQG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_LO 0x31e6 +#define regSQG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_HI 0x31e7 +#define regSQG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_LO 0x31e8 +#define regSQG_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_HI 0x31e9 +#define regSQG_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_LO 0x31ea +#define regSQG_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_HI 0x31eb +#define regSQG_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_LO 0x31ec +#define regSQG_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_HI 0x31ed +#define regSQG_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_LO 0x31ee +#define regSQG_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_HI 0x31ef +#define regSQG_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_LO 0x31f0 +#define regSQG_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_HI 0x31f1 +#define regSQG_PERFCOUNTER6_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_LO 0x31f2 +#define regSQG_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_HI 0x31f3 +#define regSQG_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER0_LO 0x3240 +#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER0_HI 0x3241 +#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER1_LO 0x3242 +#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER1_HI 0x3243 +#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER2_LO 0x3244 +#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER2_HI 0x3245 +#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER3_LO 0x3246 +#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER3_HI 0x3247 +#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER0_LO 0x32c0 +#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER0_HI 0x32c1 +#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER1_LO 0x32c2 +#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER1_HI 0x32c3 +#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER0_LO 0x3300 +#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER0_HI 0x3301 +#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER1_LO 0x3302 +#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER1_HI 0x3303 +#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_LO 0x3340 +#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_HI 0x3341 +#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_LO 0x3342 +#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_HI 0x3343 +#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_LO 0x3344 +#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_HI 0x3345 +#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_LO 0x3346 +#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_HI 0x3347 +#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER4_LO 0x3348 +#define regTCP_PERFCOUNTER4_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER4_HI 0x3349 +#define regTCP_PERFCOUNTER4_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER5_LO 0x334a +#define regTCP_PERFCOUNTER5_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER5_HI 0x334b +#define regTCP_PERFCOUNTER5_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER6_LO 0x334c +#define regTCP_PERFCOUNTER6_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER6_HI 0x334d +#define regTCP_PERFCOUNTER6_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER7_LO 0x334e +#define regTCP_PERFCOUNTER7_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER7_HI 0x334f +#define regTCP_PERFCOUNTER7_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER 0x3350 +#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER2 0x3351 +#define regTCP_PERFCOUNTER_FILTER2_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER_EN 0x3352 +#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 1 +#define regTCP_PERFCOUNTER_SET_DEFINE 0x3353 +#define regTCP_PERFCOUNTER_SET_DEFINE_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_LO 0x33a0 +#define regGL1C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_HI 0x33a1 +#define regGL1C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_LO 0x33a2 +#define regGL1C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_HI 0x33a3 +#define regGL1C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_LO 0x33a4 +#define regGL1C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_HI 0x33a5 +#define regGL1C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_LO 0x33a6 +#define regGL1C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_HI 0x33a7 +#define regGL1C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_LO 0x33a8 +#define regGL1XC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_HI 0x33a9 +#define regGL1XC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_LO 0x33aa +#define regGL1XC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_HI 0x33ab +#define regGL1XC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_LO 0x33ac +#define regGL1XC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_HI 0x33ad +#define regGL1XC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_LO 0x33ae +#define regGL1XC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_HI 0x33af +#define regGL1XC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER0_LO 0x3406 +#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER0_HI 0x3407 +#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER1_LO 0x3408 +#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER1_HI 0x3409 +#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER2_LO 0x340a +#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER2_HI 0x340b +#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER3_LO 0x340c +#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER3_HI 0x340d +#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER0_LO 0x3440 +#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER0_HI 0x3441 +#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER1_LO 0x3442 +#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER1_HI 0x3443 +#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER2_LO 0x3444 +#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER2_HI 0x3445 +#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER3_LO 0x3446 +#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER3_HI 0x3447 +#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_LO 0x34c0 +#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_HI 0x34c1 +#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_LO 0x34c2 +#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_HI 0x34c3 +#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_LO 0x34c4 +#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_HI 0x34c5 +#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_LO 0x34c6 +#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_HI 0x34c7 +#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_LO 0x3580 +#define regPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_HI 0x3581 +#define regPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_LO 0x3582 +#define regPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_HI 0x3583 +#define regPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_LO 0x3584 +#define regPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_HI 0x3585 +#define regPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_LO 0x3586 +#define regPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_HI 0x3587 +#define regPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_LO 0x3588 +#define regPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_HI 0x3589 +#define regPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_LO 0x358a +#define regPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_HI 0x358b +#define regPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_LO 0x358c +#define regPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_HI 0x358d +#define regPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_LO 0x358e +#define regPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_HI 0x358f +#define regPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_LO 0x35a0 +#define regUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_HI 0x35a1 +#define regUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_LO 0x35a2 +#define regUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_HI 0x35a3 +#define regUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_LO 0x35a4 +#define regUTCL1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_HI 0x35a5 +#define regUTCL1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_LO 0x35a6 +#define regUTCL1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_HI 0x35a7 +#define regUTCL1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regWGS_PERFCOUNTER1_LO 0x35b0 +#define regWGS_PERFCOUNTER1_LO_BASE_IDX 1 +#define regWGS_PERFCOUNTER1_HI 0x35b1 +#define regWGS_PERFCOUNTER1_HI_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_LO 0x35b2 +#define regWGS_PERFCOUNTER0_LO_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_HI 0x35b3 +#define regWGS_PERFCOUNTER0_HI_BASE_IDX 1 +#define regWGS_PERFMON_CNTL 0x35b4 +#define regWGS_PERFMON_CNTL_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_LO 0x35c0 +#define regGL1A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_HI 0x35c1 +#define regGL1A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_LO 0x35c2 +#define regGL1A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_HI 0x35c3 +#define regGL1A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_LO 0x35c4 +#define regGL1A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_HI 0x35c5 +#define regGL1A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_LO 0x35c6 +#define regGL1A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_HI 0x35c7 +#define regGL1A_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_LO 0x35c8 +#define regGL1XA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_HI 0x35c9 +#define regGL1XA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_LO 0x35ca +#define regGL1XA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_HI 0x35cb +#define regGL1XA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_LO 0x35cc +#define regGL1XA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_HI 0x35cd +#define regGL1XA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_LO 0x35ce +#define regGL1XA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_HI 0x35cf +#define regGL1XA_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfsdec +// base address: 0x36000 +#define regGE2_SE_PERFCOUNTER0_SELECT 0x38b4 +#define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 +#define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT 0x38b6 +#define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 +#define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT 0x38b8 +#define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 +#define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT 0x38ba +#define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT1 0x38bb +#define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER0_SELECT 0x38f8 +#define regGRBMH_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER1_SELECT 0x38f9 +#define regGRBMH_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT1 0x3905 +#define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT 0x3906 +#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT1 0x3907 +#define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT 0x3980 +#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT 0x3981 +#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT 0x3982 +#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT 0x3983 +#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT 0x3984 +#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT 0x3985 +#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT1 0x3986 +#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT1 0x3987 +#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT1 0x3988 +#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT1 0x3989 +#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT1 0x398a +#define regSPI_PERFCOUNTER4_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT1 0x398b +#define regSPI_PERFCOUNTER5_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER_BINS 0x398c +#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT 0x3990 +#define regPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT 0x3991 +#define regPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT 0x3992 +#define regPC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT 0x3993 +#define regPC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT1 0x3994 +#define regPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT1 0x3995 +#define regPC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT1 0x3996 +#define regPC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT1 0x3997 +#define regPC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_SELECT 0x39c0 +#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_SELECT 0x39c1 +#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_SELECT 0x39c2 +#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_SELECT 0x39c3 +#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_SELECT 0x39c4 +#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_SELECT 0x39c5 +#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_SELECT 0x39c6 +#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_SELECT 0x39c7 +#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_SELECT 0x39c8 +#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_SELECT 0x39c9 +#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_SELECT 0x39ca +#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_SELECT 0x39cb +#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_SELECT 0x39cc +#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_SELECT 0x39cd +#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_SELECT 0x39ce +#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_SELECT 0x39cf +#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_SELECT 0x39d0 +#define regSQG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_SELECT 0x39d1 +#define regSQG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_SELECT 0x39d2 +#define regSQG_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_SELECT 0x39d3 +#define regSQG_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_SELECT 0x39d4 +#define regSQG_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_SELECT 0x39d5 +#define regSQG_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_SELECT 0x39d6 +#define regSQG_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_SELECT 0x39d7 +#define regSQG_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL 0x39d8 +#define regSQG_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL2 0x39da +#define regSQG_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQG_PERF_SAMPLE_FINISH 0x39db +#define regSQG_PERF_SAMPLE_FINISH_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL 0x39e0 +#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL2 0x39e2 +#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_SIZE 0x39e6 +#define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_BASE_LO 0x39e7 +#define regSQ_THREAD_TRACE_BUF0_BASE_LO_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_BASE_HI 0x39e8 +#define regSQ_THREAD_TRACE_BUF0_BASE_HI_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_SIZE 0x39e9 +#define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_BASE_LO 0x39ea +#define regSQ_THREAD_TRACE_BUF1_BASE_LO_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_BASE_HI 0x39eb +#define regSQ_THREAD_TRACE_BUF1_BASE_HI_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CTRL 0x39ec +#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MASK 0x39ed +#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK 0x39ee +#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_WPTR 0x39ef +#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HALT 0x39f0 +#define regSQ_THREAD_TRACE_HALT_BASE_IDX 1 +#define regSQ_THREAD_TRACE_POWEROFF_RESTORE_1 0x39f1 +#define regSQ_THREAD_TRACE_POWEROFF_RESTORE_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS 0x39f4 +#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS2 0x39f5 +#define regSQ_THREAD_TRACE_STATUS2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x39f6 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x39f7 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x39f8 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x39f9 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_DROPPED_CNTR 0x39fa +#define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_FINISH_DONE_DEBUG 0x39fb +#define regSQ_THREAD_TRACE_FINISH_DONE_DEBUG_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT 0x3a40 +#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT 0x3a41 +#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT 0x3a42 +#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT 0x3a43 +#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT1 0x3a44 +#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT1 0x3a45 +#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT1 0x3a46 +#define regSX_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT1 0x3a47 +#define regSX_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT 0x3ac0 +#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER1_SELECT 0x3ac2 +#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT 0x3b00 +#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT1 0x3b01 +#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTD_PERFCOUNTER1_SELECT 0x3b02 +#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT 0x3b40 +#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT 0x3b42 +#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT 0x3b44 +#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT1 0x3b45 +#define regTCP_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT 0x3b46 +#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT1 0x3b47 +#define regTCP_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER4_SELECT 0x3b4a +#define regTCP_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER5_SELECT 0x3b4b +#define regTCP_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER6_SELECT 0x3b4c +#define regTCP_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER7_SELECT 0x3b4d +#define regTCP_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT 0x3ba0 +#define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT1 0x3ba1 +#define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_SELECT 0x3ba2 +#define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_SELECT1 0x3ba3 +#define regGL1C_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_SELECT 0x3ba4 +#define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_SELECT1 0x3ba5 +#define regGL1C_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_SELECT 0x3ba6 +#define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_SELECT1 0x3ba7 +#define regGL1C_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_SELECT 0x3ba8 +#define regGL1XC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_SELECT1 0x3ba9 +#define regGL1XC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_SELECT 0x3baa +#define regGL1XC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_SELECT1 0x3bab +#define regGL1XC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_SELECT 0x3bac +#define regGL1XC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_SELECT1 0x3bad +#define regGL1XC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_SELECT 0x3bae +#define regGL1XC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_SELECT1 0x3baf +#define regGL1XC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER_FILTER 0x3c00 +#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT 0x3c01 +#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT1 0x3c02 +#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER1_SELECT 0x3c03 +#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER2_SELECT 0x3c04 +#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER3_SELECT 0x3c05 +#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT 0x3c40 +#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT1 0x3c41 +#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT 0x3c42 +#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT1 0x3c43 +#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT 0x3c44 +#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT1 0x3c45 +#define regDB_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT 0x3c46 +#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT1 0x3c47 +#define regDB_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT 0x3d00 +#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_SELECT 0x3d02 +#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT 0x3d03 +#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_SELECT 0x3d05 +#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRMI_PERF_COUNTER_CNTL 0x3d06 +#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT 0x3d80 +#define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT1 0x3d81 +#define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT 0x3d82 +#define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT 0x3d83 +#define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT 0x3d84 +#define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_SELECT 0x3d85 +#define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_SELECT 0x3d86 +#define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_SELECT 0x3d87 +#define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_SELECT 0x3d88 +#define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT1 0x3d90 +#define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT1 0x3d91 +#define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT1 0x3d92 +#define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_SELECT 0x3da0 +#define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_SELECT1 0x3da1 +#define regUTCL1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_SELECT 0x3da2 +#define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_SELECT1 0x3da3 +#define regUTCL1_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_SELECT 0x3da4 +#define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_SELECT 0x3da5 +#define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regWGS_PERFCOUNTER1_SELECT 0x3db0 +#define regWGS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_SELECT1 0x3db1 +#define regWGS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_SELECT 0x3db3 +#define regWGS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT 0x3dc0 +#define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT1 0x3dc1 +#define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_SELECT 0x3dc2 +#define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_SELECT1 0x3dc3 +#define regGL1A_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_SELECT 0x3dc4 +#define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_SELECT1 0x3dc5 +#define regGL1A_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_SELECT 0x3dc6 +#define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_SELECT1 0x3dc7 +#define regGL1A_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_SELECT 0x3dc8 +#define regGL1XA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_SELECT1 0x3dc9 +#define regGL1XA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_SELECT 0x3dca +#define regGL1XA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_SELECT1 0x3dcb +#define regGL1XA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_SELECT 0x3dcc +#define regGL1XA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_SELECT1 0x3dcd +#define regGL1XA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_SELECT 0x3dce +#define regGL1XA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_SELECT1 0x3dcf +#define regGL1XA_PERFCOUNTER3_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pwrdec +// base address: 0x3c000 +#define regGFX_ICG_SPI_RA0_CLK_CTRL 0x507a +#define regGFX_ICG_SPI_RA0_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_RA1_CLK_CTRL 0x507b +#define regGFX_ICG_SPI_RA1_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_CS_CTRL 0x507c +#define regGFX_ICG_SPI_CS_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_PS_CTRL 0x507d +#define regGFX_ICG_SPI_PS_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPIS_CTRL 0x507e +#define regGFX_ICG_SPIS_CTRL_BASE_IDX 1 +#define regCGTX_SPI_DEBUG_CLK_CTRL 0x507f +#define regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_CTRL 0x5080 +#define regGFX_ICG_SPI_CTRL_BASE_IDX 1 +#define regGFX_ICG_PC_CLK_CTRL 0x5081 +#define regGFX_ICG_PC_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_BCI_CTRL 0x5082 +#define regGFX_ICG_BCI_CTRL_BASE_IDX 1 +#define regCGTT_VGT_CLK_CTRL 0x5084 +#define regCGTT_VGT_CLK_CTRL_BASE_IDX 1 +#define regCGTT_GS_NGG_CLK_CTRL 0x5087 +#define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PA_CLK_CTRL 0x5088 +#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SQ_CLK_CTRL 0x508c +#define regCGTT_SQ_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SQG_CLK_CTRL 0x508d +#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define regSQ_ALU_CLK_CTRL 0x508e +#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define regSQ_TEX_CLK_CTRL 0x508f +#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define regSQ_LDS_CLK_CTRL 0x5090 +#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define regSQ_CLK_CTRL 0x5091 +#define regSQ_CLK_CTRL_BASE_IDX 1 +#define regICG_SQ_CLK_CTRL 0x5092 +#define regICG_SQ_CLK_CTRL_BASE_IDX 1 +#define regICG_SP_CLK_CTRL 0x5093 +#define regICG_SP_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL0 0x5094 +#define regGFX_ICG_SX_CLK_CTRL0_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL1 0x5095 +#define regGFX_ICG_SX_CLK_CTRL1_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL2 0x5096 +#define regGFX_ICG_SX_CLK_CTRL2_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL3 0x5097 +#define regGFX_ICG_SX_CLK_CTRL3_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL4 0x5098 +#define regGFX_ICG_SX_CLK_CTRL4_BASE_IDX 1 +#define regGFX_ICG_TA_CTRL 0x509e +#define regGFX_ICG_TA_CTRL_BASE_IDX 1 +#define regGFX_ICG_TD_CTRL 0x509f +#define regGFX_ICG_TD_CTRL_BASE_IDX 1 +#define regDB_CGTT_CLK_CTRL_0 0x50a4 +#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define regGFX_ICG_CB_CTRL 0x50a9 +#define regGFX_ICG_CB_CTRL_BASE_IDX 1 +#define regGFX_ICG_RMI_CTRL 0x50c0 +#define regGFX_ICG_RMI_CTRL_BASE_IDX 1 +#define regGFX_ICG_SE_CAC_CLK_CTRL 0x50d0 +#define regGFX_ICG_SE_CAC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL0 0x50f8 +#define regCGTT_PH_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL1 0x50f9 +#define regCGTT_PH_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL2 0x50fa +#define regCGTT_PH_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL3 0x50fb +#define regCGTT_PH_CLK_CTRL3_BASE_IDX 1 +#define regGFX_ICG_TCP_CTRL 0x5101 +#define regGFX_ICG_TCP_CTRL_BASE_IDX 1 +#define regGFX_ICG_TCP_CTRL2 0x5102 +#define regGFX_ICG_TCP_CTRL2_BASE_IDX 1 +#define regICG_LDS_CLK_CTRL 0x5114 +#define regICG_LDS_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_UTCL1_CTRL 0x511c +#define regGFX_ICG_UTCL1_CTRL_BASE_IDX 1 +#define regGFX_ICG_GRBMH_CTRL 0x5120 +#define regGFX_ICG_GRBMH_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_sc_pwrdec +// base address: 0x3c344 +#define regCGTT_SC_CLK_CTRL0 0x50d1 +#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL1 0x50d2 +#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL2 0x50d3 +#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL3 0x50d4 +#define regCGTT_SC_CLK_CTRL3_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL4 0x50d5 +#define regCGTT_SC_CLK_CTRL4_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1_pwrdec +// base address: 0x3c364 +#define regICG_GL1C_CLK_CTRL 0x50d9 +#define regICG_GL1C_CLK_CTRL_BASE_IDX 1 +#define regGL1I_GL1R_MGCG_OVERRIDE 0x50da +#define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX 1 +#define regGL1XI_GL1XR_MGCG_OVERRIDE 0x50db +#define regGL1XI_GL1XR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_GL1XC_CLK_CTRL 0x50dc +#define regICG_GL1XC_CLK_CTRL_BASE_IDX 1 +#define regICG_GL1A_CTRL 0x50dd +#define regICG_GL1A_CTRL_BASE_IDX 1 +#define regICG_GL1XA_CTRL 0x50de +#define regICG_GL1XA_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_hypdec +// base address: 0x3e000 +#define regGL1_PIPE_STEER_LSB 0x5b84 +#define regGL1_PIPE_STEER_LSB_BASE_IDX 1 +#define regGL1_PIPE_STEER_MSB 0x5b85 +#define regGL1_PIPE_STEER_MSB_BASE_IDX 1 +#define regGL1_HASH_CFG 0x5b86 +#define regGL1_HASH_CFG_BASE_IDX 1 +#define regGC_USER_SHADER_ARRAY_CONFIG 0x5b90 +#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 1 +#define regGC_USER_RB_BACKEND_DISABLE 0x5b94 +#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 1 +#define regGC_USER_RMI_REDUNDANCY 0x5b95 +#define regGC_USER_RMI_REDUNDANCY_BASE_IDX 1 +#define regGC_USER_SHADER_RATE_CONFIG_1 0x5b97 +#define regGC_USER_SHADER_RATE_CONFIG_1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmh_hypdec +// base address: 0x3ee80 +#define regGRBMH_WGP_SA0_REMAP_CNTL 0x5ba0 +#define regGRBMH_WGP_SA0_REMAP_CNTL_BASE_IDX 1 +#define regGRBMH_WGP_SA1_REMAP_CNTL 0x5ba1 +#define regGRBMH_WGP_SA1_REMAP_CNTL_BASE_IDX 1 +#define regGRBMH_RB_SA0_REMAP_CNTL 0x5ba2 +#define regGRBMH_RB_SA0_REMAP_CNTL_BASE_IDX 1 +#define regGRBMH_RB_SA1_REMAP_CNTL 0x5ba3 +#define regGRBMH_RB_SA1_REMAP_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpfdec +// base address: 0xa000 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x15a0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x15a1 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regGCUTCL2_ICG_CTRL 0x15a2 +#define regGCUTCL2_ICG_CTRL_BASE_IDX 0 +#define regGCMC_SHARED_ACTIVE_FCN_ID 0x15a3 +#define regGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 +#define regGCUTCL2_CGTT_BUSY_CTRL 0x15a4 +#define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS 0x15a5 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pfdec +// base address: 0xa090 +#define regGCVM_L2_CNTL 0x15c4 +#define regGCVM_L2_CNTL_BASE_IDX 0 +#define regGCVM_L2_CNTL2 0x15c5 +#define regGCVM_L2_CNTL2_BASE_IDX 0 +#define regGCVM_L2_CNTL3 0x15c6 +#define regGCVM_L2_CNTL3_BASE_IDX 0 +#define regGCVM_L2_STATUS 0x15c7 +#define regGCVM_L2_STATUS_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c8 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c9 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15ca +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_CNTL 0x15cb +#define regGCVM_INVALIDATE_CNTL_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL_LO32 0x15cc +#define regGCVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL_HI32 0x15cd +#define regGCVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL2 0x15ce +#define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15cf +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15d0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_LO32 0x15d1 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_HI32 0x15d2 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15d3 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15d4 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15d5 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15d6 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_DEBUG 0x15d7 +#define regGCVM_DEBUG_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15d8 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15d9 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15da +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15db +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15dc +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15dd +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regGCVM_L2_CNTL4 0x15de +#define regGCVM_L2_CNTL4_BASE_IDX 0 +#define regGCVM_L2_MM_GROUP_RT_CLASSES 0x15df +#define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID 0x15e0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15e1 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regGCVM_L2_CACHE_PARITY_CNTL 0x15e2 +#define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regGCVM_L2_ICG_CTRL 0x15e3 +#define regGCVM_L2_ICG_CTRL_BASE_IDX 0 +#define regGCVM_L2_CNTL5 0x15e4 +#define regGCVM_L2_CNTL5_BASE_IDX 0 +#define regGCVM_L2_GCR_CNTL 0x15e5 +#define regGCVM_L2_GCR_CNTL_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15e6 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15e7 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15e8 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15e9 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVM_L2_CGTT_BUSY_CTRL 0x15ea +#define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15eb +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_READ 0x15ec +#define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 +#define regGCVML2_MAIN_DEBUG 0x15ed +#define regGCVML2_MAIN_DEBUG_BASE_IDX 0 +#define regGCVML2_WALKER_DEBUG 0x15ee +#define regGCVML2_WALKER_DEBUG_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32 0x15ef +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32 0x15f0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR 0x15f1 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32 0x15f2 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32 0x15f3 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR 0x15f4 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_MASKS 0x15f5 +#define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x15f6 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x15f7 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x15f8 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x15f9 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x15fa +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 +#define regGCVM_L2_UTCL2_FED_VMID_STS 0x15fb +#define regGCVM_L2_UTCL2_FED_VMID_STS_BASE_IDX 0 +#define regGCVM_L2_UTCL2_FED_ACK_REG 0x15fc +#define regGCVM_L2_UTCL2_FED_ACK_REG_BASE_IDX 0 +#define regGCVML2_IH_FAULT_INTERRUPT_CNTL 0x15fd +#define regGCVML2_IH_FAULT_INTERRUPT_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpfdec +// base address: 0xa1d0 +#define regGC_L2TLB_TLB0_STATUS 0x1615 +#define regGC_L2TLB_TLB0_STATUS_BASE_IDX 0 +#define regGC_L2TLB_TLB0_RETRY_CNTL 0x1616 +#define regGC_L2TLB_TLB0_RETRY_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvcdec +// base address: 0xa210 +#define regGCMC_VM_FB_LOCATION_BASE_LO32 0x1624 +#define regGCMC_VM_FB_LOCATION_BASE_LO32_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_BASE_HI32 0x1625 +#define regGCMC_VM_FB_LOCATION_BASE_HI32_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_TOP_LO32 0x1626 +#define regGCMC_VM_FB_LOCATION_TOP_LO32_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_TOP_HI32 0x1627 +#define regGCMC_VM_FB_LOCATION_TOP_HI32_BASE_IDX 0 +#define regGCMC_VM_AGP_TOP_LO32 0x1628 +#define regGCMC_VM_AGP_TOP_LO32_BASE_IDX 0 +#define regGCMC_VM_AGP_TOP_HI32 0x1629 +#define regGCMC_VM_AGP_TOP_HI32_BASE_IDX 0 +#define regGCMC_VM_AGP_BOT_LO32 0x162a +#define regGCMC_VM_AGP_BOT_LO32_BASE_IDX 0 +#define regGCMC_VM_AGP_BOT_HI32 0x162b +#define regGCMC_VM_AGP_BOT_HI32_BASE_IDX 0 +#define regGCMC_VM_AGP_BASE_LO32 0x162c +#define regGCMC_VM_AGP_BASE_LO32_BASE_IDX 0 +#define regGCMC_VM_AGP_BASE_HI32 0x162d +#define regGCMC_VM_AGP_BASE_HI32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 0x162e +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 0x162f +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 0x1630 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 0x1631 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regGCMC_VM_MX_L1_TLB_CNTL 0x1632 +#define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2vcdec +// base address: 0xa250 +#define regGCVM_CONTEXT0_CNTL 0x1634 +#define regGCVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT1_CNTL 0x1635 +#define regGCVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT2_CNTL 0x1636 +#define regGCVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT3_CNTL 0x1637 +#define regGCVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT4_CNTL 0x1638 +#define regGCVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT5_CNTL 0x1639 +#define regGCVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT6_CNTL 0x163a +#define regGCVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT7_CNTL 0x163b +#define regGCVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT8_CNTL 0x163c +#define regGCVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT9_CNTL 0x163d +#define regGCVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT10_CNTL 0x163e +#define regGCVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT11_CNTL 0x163f +#define regGCVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT12_CNTL 0x1640 +#define regGCVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT13_CNTL 0x1641 +#define regGCVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT14_CNTL 0x1642 +#define regGCVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT15_CNTL 0x1643 +#define regGCVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXTS_DISABLE 0x1644 +#define regGCVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_SEM 0x1645 +#define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_SEM 0x1646 +#define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_SEM 0x1647 +#define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_SEM 0x1648 +#define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_SEM 0x1649 +#define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_SEM 0x164a +#define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_SEM 0x164b +#define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_SEM 0x164c +#define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_SEM 0x164d +#define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_SEM 0x164e +#define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_SEM 0x164f +#define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_SEM 0x1650 +#define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_SEM 0x1651 +#define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_SEM 0x1652 +#define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_SEM 0x1653 +#define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_SEM 0x1654 +#define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_SEM 0x1655 +#define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_SEM 0x1656 +#define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_REQ 0x1657 +#define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_REQ 0x1658 +#define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_REQ 0x1659 +#define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_REQ 0x165a +#define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_REQ 0x165b +#define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_REQ 0x165c +#define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_REQ 0x165d +#define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_REQ 0x165e +#define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_REQ 0x165f +#define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_REQ 0x1660 +#define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_REQ 0x1661 +#define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_REQ 0x1662 +#define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_REQ 0x1663 +#define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_REQ 0x1664 +#define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_REQ 0x1665 +#define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_REQ 0x1666 +#define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_REQ 0x1667 +#define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_REQ 0x1668 +#define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ACK 0x1669 +#define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ACK 0x166a +#define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ACK 0x166b +#define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ACK 0x166c +#define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ACK 0x166d +#define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ACK 0x166e +#define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ACK 0x166f +#define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ACK 0x1670 +#define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ACK 0x1671 +#define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ACK 0x1672 +#define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ACK 0x1673 +#define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ACK 0x1674 +#define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ACK 0x1675 +#define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ACK 0x1676 +#define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ACK 0x1677 +#define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ACK 0x1678 +#define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ACK 0x1679 +#define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ACK 0x167a +#define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x167b +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x167c +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x167d +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x167e +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x167f +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x1680 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x1681 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x1682 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x1683 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x1684 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x1685 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x1686 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x1687 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x1688 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x1689 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x168a +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x168b +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x168c +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x168d +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x168e +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x168f +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x1690 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x1691 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x1692 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x1693 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x1694 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x1695 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x1696 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x1697 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x1698 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x1699 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x169a +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x169b +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x169c +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x169d +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x169e +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x169f +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x16a0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x16a1 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x16a2 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x16a3 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x16a4 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x16a5 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x16a6 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x16a7 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x16a8 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x16a9 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x16aa +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x16ab +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x16ac +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x16ad +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x16ae +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x16af +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x16b0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x16b1 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x16b2 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x16b3 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x16b4 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x16b5 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x16b6 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x16b7 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x16b8 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x16b9 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x16ba +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x16bb +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x16bc +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x16bd +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x16be +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x16bf +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x16c0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x16c1 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x16c2 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x16c3 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x16c4 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x16c5 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x16c6 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x16c7 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x16c8 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x16c9 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x16ca +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x16cb +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x16cc +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x16cd +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x16ce +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x16cf +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x16d0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x16d1 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x16d2 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x16d3 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x16d4 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x16d5 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x16d6 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x16d7 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x16d8 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x16d9 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x16da +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x16db +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x16dc +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x16dd +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x16de +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x16df +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x16e0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x16e1 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x16e2 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x16e3 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x16e4 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x16e5 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x16e6 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x16e7 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x16e8 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x16e9 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x16ea +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x16eb +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x16ec +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x16ed +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x16ee +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x16ef +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x16f0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x16f1 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x16f2 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x16f3 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x16f4 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x16f5 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x16f6 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x16f7 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x16f8 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x16f9 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x16fa +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x16fb +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x16fc +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x16fd +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x16fe +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16ff +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1700 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1701 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1702 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1703 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1704 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1705 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1706 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1707 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1708 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1709 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170a +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170b +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170c +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170d +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170e +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170f +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvfdec +// base address: 0xa5d0 +#define regGCMC_VM_PCIE_ATOMIC_SUPPORTED 0x1714 +#define regGCMC_VM_PCIE_ATOMIC_SUPPORTED_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbvfdec +// base address: 0xa5e0 +#define regGC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC 0x1718 +#define regGC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2prdec +// base address: 0x35380 +#define regGCMC_VM_L2_PERFCOUNTER_LO 0x34e0 +#define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_HI 0x34e1 +#define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_LO 0x34e2 +#define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_HI 0x34e3 +#define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2prdec +// base address: 0x353c0 +#define regGC_ATC_L2_PERFCOUNTER_LO 0x34f0 +#define regGC_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER_HI 0x34f1 +#define regGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec +// base address: 0x353f0 +#define regGC_L2TLB_PERFCOUNTER_LO 0x34fc +#define regGC_L2TLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER_HI 0x34fd +#define regGC_L2TLB_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pldec +// base address: 0x37b00 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG 0x3ec0 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG 0x3ec1 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG 0x3ec2 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG 0x3ec3 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG 0x3ec4 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG 0x3ec5 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG 0x3ec6 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG 0x3ec7 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER8_CFG 0x3ec8 +#define regGCMC_VM_L2_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER9_CFG 0x3ec9 +#define regGCMC_VM_L2_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER10_CFG 0x3eca +#define regGCMC_VM_L2_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER11_CFG 0x3ecb +#define regGCMC_VM_L2_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER12_CFG 0x3ecc +#define regGCMC_VM_L2_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER13_CFG 0x3ecd +#define regGCMC_VM_L2_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER14_CFG 0x3ece +#define regGCMC_VM_L2_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER15_CFG 0x3ecf +#define regGCMC_VM_L2_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3ed0 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER0_CFG 0x3ed1 +#define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER1_CFG 0x3ed2 +#define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER2_CFG 0x3ed3 +#define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER3_CFG 0x3ed4 +#define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3ed5 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT 0x3ed6 +#define regGCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2pldec +// base address: 0x37b60 +#define regGC_ATC_L2_PERFCOUNTER0_CFG 0x3ed8 +#define regGC_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER1_CFG 0x3ed9 +#define regGC_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER2_CFG 0x3eda +#define regGC_ATC_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER3_CFG 0x3edb +#define regGC_ATC_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER4_CFG 0x3edc +#define regGC_ATC_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER5_CFG 0x3edd +#define regGC_ATC_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER6_CFG 0x3ede +#define regGC_ATC_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER7_CFG 0x3edf +#define regGC_ATC_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER8_CFG 0x3ee0 +#define regGC_ATC_L2_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER9_CFG 0x3ee1 +#define regGC_ATC_L2_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER10_CFG 0x3ee2 +#define regGC_ATC_L2_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER11_CFG 0x3ee3 +#define regGC_ATC_L2_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER12_CFG 0x3ee4 +#define regGC_ATC_L2_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER13_CFG 0x3ee5 +#define regGC_ATC_L2_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER14_CFG 0x3ee6 +#define regGC_ATC_L2_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER15_CFG 0x3ee7 +#define regGC_ATC_L2_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3ee8 +#define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec +// base address: 0x37c50 +#define regGC_L2TLB_PERFCOUNTER0_CFG 0x3f14 +#define regGC_L2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER1_CFG 0x3f15 +#define regGC_L2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER2_CFG 0x3f16 +#define regGC_L2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER3_CFG 0x3f17 +#define regGC_L2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER_RSLT_CNTL 0x3f18 +#define regGC_L2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedhvdec +// base address: 0x3e800 +#define regGCVM_PCIE_ATS_CNTL 0x5a00 +#define regGCVM_PCIE_ATS_CNTL_BASE_IDX 1 +#define regGCMC_VM_NB_MMIOBASE 0x5a01 +#define regGCMC_VM_NB_MMIOBASE_BASE_IDX 1 +#define regGCMC_VM_NB_MMIOLIMIT 0x5a02 +#define regGCMC_VM_NB_MMIOLIMIT_BASE_IDX 1 +#define regGCMC_VM_NB_PCI_CTRL 0x5a03 +#define regGCMC_VM_NB_PCI_CTRL_BASE_IDX 1 +#define regGCMC_VM_NB_PCI_ARB 0x5a04 +#define regGCMC_VM_NB_PCI_ARB_BASE_IDX 1 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x5a05 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x5a06 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x5a07 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 +#define regGCMC_VM_STEERING 0x5a08 +#define regGCMC_VM_STEERING_BASE_IDX 1 +#define regGCMC_SHARED_VIRT_RESET_REQ 0x5a09 +#define regGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 +#define regGCMC_VM_XGMI_LFB_CNTL 0x5a0a +#define regGCMC_VM_XGMI_LFB_CNTL_BASE_IDX 1 +#define regGCMC_VM_XGMI_LFB_SIZE 0x5a0b +#define regGCMC_VM_XGMI_LFB_SIZE_BASE_IDX 1 +#define regGCMC_VM_HOST_MAPPING 0x5a0c +#define regGCMC_VM_HOST_MAPPING_BASE_IDX 1 +#define regGCMC_VM_XGMI_GPUIOV_ENABLE 0x5a0d +#define regGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x5a0e +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x5a0f +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x5a10 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x5a11 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_LPDDR_ADDRESS_START 0x5a12 +#define regGCMC_VM_LPDDR_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_LPDDR_ADDRESS_END 0x5a13 +#define regGCMC_VM_LPDDR_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_APT_CNTL 0x5a14 +#define regGCMC_VM_APT_CNTL_BASE_IDX 1 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS 0x5a15 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 +#define regGCUTCL2_ROUTER_DEBUG 0x5a16 +#define regGCUTCL2_ROUTER_DEBUG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2dec +// base address: 0x3e9f0 +#define regGC_ATC_L2_CNTL 0x5a7c +#define regGC_ATC_L2_CNTL_BASE_IDX 1 +#define regGC_ATC_L2_CNTL2 0x5a7d +#define regGC_ATC_L2_CNTL2_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA0 0x5a80 +#define regGC_ATC_L2_CACHE_DATA0_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA1 0x5a81 +#define regGC_ATC_L2_CACHE_DATA1_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA2 0x5a82 +#define regGC_ATC_L2_CACHE_DATA2_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA3 0x5a83 +#define regGC_ATC_L2_CACHE_DATA3_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA4 0x5a84 +#define regGC_ATC_L2_CACHE_DATA4_BASE_IDX 1 +#define regGC_ATC_L2_CNTL3 0x5a85 +#define regGC_ATC_L2_CNTL3_BASE_IDX 1 +#define regGC_ATC_L2_STATUS 0x5a86 +#define regGC_ATC_L2_STATUS_BASE_IDX 1 +#define regGC_ATC_L2_MISC_CG 0x5a87 +#define regGC_ATC_L2_MISC_CG_BASE_IDX 1 +#define regGC_ATC_L2_ICG_CTRL 0x5a88 +#define regGC_ATC_L2_ICG_CTRL_BASE_IDX 1 +#define regGC_ATC_L2_SDPPORT_CTRL 0x5a8b +#define regGC_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 +#define regGC_ATC_L2_MISC_DEBUG 0x5a8c +#define regGC_ATC_L2_MISC_DEBUG_BASE_IDX 1 +#define regGC_ATC_L2_BANK_SELECT_MASKS 0x5a8d +#define regGC_ATC_L2_BANK_SELECT_MASKS_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_CNTL 0x5a8e +#define regGC_ATC_L2_FAULT_CNTL_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_STATUS 0x5a8f +#define regGC_ATC_L2_FAULT_STATUS_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_ADDR_LO 0x5a90 +#define regGC_ATC_L2_FAULT_ADDR_LO_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_ADDR_HI 0x5a91 +#define regGC_ATC_L2_FAULT_ADDR_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbhvdec +// base address: 0x3eb20 +#define regGC_L2TLB_TMZ_CNTL 0x5ac9 +#define regGC_L2TLB_TMZ_CNTL_BASE_IDX 1 +#define regGC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x5aca +#define regGC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 +#define regGC_L2TLB_GCC_MTYPE_ENCODING_CNTL 0x5acb +#define regGC_L2TLB_GCC_MTYPE_ENCODING_CNTL_BASE_IDX 1 +#define regGC_L2TLB_FB_COMP_EN_CNTL 0x5acc +#define regGC_L2TLB_FB_COMP_EN_CNTL_BASE_IDX 1 +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_0 0x5acd +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_0_BASE_IDX 1 +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_1 0x5ace +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_1_BASE_IDX 1 +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_2 0x5acf +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_2_BASE_IDX 1 +#define regGC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS 0x5ad0 +#define regGC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pspdec +// base address: 0x3f900 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5e40 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 +#define regGCVML2_SEC_MASTER 0x5e41 +#define regGCVML2_SEC_MASTER_BASE_IDX 1 +#define regGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x5e42 +#define regGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 1 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x5e43 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 +#define regGCVM_IOMMU_CONTROL_REGISTER 0x5e44 +#define regGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define regGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5e45 +#define regGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL0 0x5e46 +#define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL1 0x5e47 +#define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 +#define regGCUTCL2_COMP_EN_OVERRIDES 0x5e49 +#define regGCUTCL2_COMP_EN_OVERRIDES_BASE_IDX 1 +#define regGCUTCL2_ROUTER_CNTL 0x5e4a +#define regGCUTCL2_ROUTER_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpspdec +// base address: 0x3f950 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0 0x5e54 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1 0x5e55 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2 0x5e56 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3 0x5e57 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4 0x5e58 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5 0x5e59 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6 0x5e5a +#define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7 0x5e5b +#define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regGCMC_VM_FB_OFFSET 0x5e5c +#define regGCMC_VM_FB_OFFSET_BASE_IDX 1 +#define regGCMC_VM_LOCAL_FB_ADDRESS_START 0x5e5d +#define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END 0x5e5e +#define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x5e5f +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 +#define regGCUTCL2_MISC_CNTL 0x5e64 +#define regGCUTCL2_MISC_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpspdec +// base address: 0x3fa00 +#define regGC_L2TLB_TLB0_CAM_ECC_CNTL 0x5e80 +#define regGC_L2TLB_TLB0_CAM_ECC_CNTL_BASE_IDX 1 + + +// addressBlock: gfx_se_sqind +// base address: 0x0 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_WAVE_ACTIVE 0x000a +#define ixSQ_WAVE_VALID_AND_IDLE 0x000b +#define ixSQ_WAVE_MODE 0x0101 +#define ixSQ_WAVE_STATUS 0x0102 +#define ixSQ_WAVE_STATE_PRIV 0x0104 +#define ixSQ_WAVE_GPR_ALLOC 0x0105 +#define ixSQ_WAVE_LDS_ALLOC 0x0106 +#define ixSQ_WAVE_IB_STS 0x0107 +#define ixSQ_PERF_SNAPSHOT_DATA 0x010a +#define ixSQ_PERF_SNAPSHOT_PC_LO 0x010b +#define ixSQ_PERF_SNAPSHOT_PC_HI 0x010c +#define ixSQ_WAVE_IB_DBG1 0x010d +#define ixSQ_WAVE_FLUSH_IB 0x010e +#define ixSQ_PERF_SNAPSHOT_DATA1 0x010f +#define ixSQ_PERF_SNAPSHOT_DATA2 0x0110 +#define ixSQ_WAVE_EXCP_FLAG_PRIV 0x0111 +#define ixSQ_WAVE_EXCP_FLAG_USER 0x0112 +#define ixSQ_WAVE_TRAP_CTRL 0x0113 +#define ixSQ_WAVE_SCRATCH_BASE_LO 0x0114 +#define ixSQ_WAVE_SCRATCH_BASE_HI 0x0115 +#define ixSQ_WAVE_HW_ID1 0x0117 +#define ixSQ_WAVE_HW_ID2 0x0118 +#define ixSQ_WAVE_SCHED_MODE 0x011a +#define ixSQ_WAVE_IB_STS2 0x011c +#define ixSQ_WAVE_DVGPR_ALLOC_LO 0x011f +#define ixSQ_WAVE_DVGPR_ALLOC_HI 0x0120 +#define ixSQ_WAVE_XNACK_STATE_PRIV 0x0121 +#define ixSQ_WAVE_XNACK_MASK 0x0122 +#define ixSQ_WAVE_PC_LO 0x0140 +#define ixSQ_WAVE_PC_HI 0x0141 +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP2 0x026e +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027d +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h new file mode 100644 index 0000000000000..f606c5cd03c59 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -0,0 +1,44638 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_0_SH_MASK_HEADER +#define _gc_12_1_0_SH_MASK_HEADER + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec +//SDMA0_SDMA_DEC_START +#define SDMA0_SDMA_DEC_START__START__SHIFT 0x0 +#define SDMA0_SDMA_DEC_START__START_MASK 0xFFFFFFFFL +//SDMA0_SDMA_MCU_MISC_CNTL +#define SDMA0_SDMA_MCU_MISC_CNTL__MCU_WAKEUP__SHIFT 0x0 +#define SDMA0_SDMA_MCU_MISC_CNTL__MCU_WAKEUP_MASK 0x00000001L +//SDMA0_SDMA_UCODE_REV +#define SDMA0_SDMA_UCODE_REV__P4_CL__SHIFT 0x0 +#define SDMA0_SDMA_UCODE_REV__DEBUG_VER__SHIFT 0x18 +#define SDMA0_SDMA_UCODE_REV__VARIANT_ID__SHIFT 0x1c +#define SDMA0_SDMA_UCODE_REV__P4_CL_MASK 0x00FFFFFFL +#define SDMA0_SDMA_UCODE_REV__DEBUG_VER_MASK 0x0F000000L +#define SDMA0_SDMA_UCODE_REV__VARIANT_ID_MASK 0xF0000000L +//SDMA0_SDMA_GLOBAL_TIMESTAMP_LO +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_GLOBAL_TIMESTAMP_HI +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_POWER_CNTL +#define SDMA0_SDMA_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//SDMA0_SDMA_CNTL +#define SDMA0_SDMA_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_CNTL__RESERVED__SHIFT 0x2 +#define SDMA0_SDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_SDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_SDMA_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 +#define SDMA0_SDMA_CNTL__CP_MES_SYNC_ENABLE__SHIFT 0x7 +#define SDMA0_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_SDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_SDMA_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_SDMA_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define SDMA0_SDMA_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_CNTL__RESERVED_MASK 0x00000004L +#define SDMA0_SDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_SDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_SDMA_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L +#define SDMA0_SDMA_CNTL__CP_MES_SYNC_ENABLE_MASK 0x00000080L +#define SDMA0_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_SDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_SDMA_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define SDMA0_SDMA_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//SDMA0_SDMA_CHICKEN_BITS +#define SDMA0_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 +#define SDMA0_SDMA_CHICKEN_BITS__RD_BURST__SHIFT 0x6 +#define SDMA0_SDMA_CHICKEN_BITS__WR_BURST__SHIFT 0x8 +#define SDMA0_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe +#define SDMA0_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf +#define SDMA0_SDMA_CHICKEN_BITS__OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 +#define SDMA0_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 +#define SDMA0_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 +#define SDMA0_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x1a +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK__SHIFT 0x1b +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG__SHIFT 0x1c +#define SDMA0_SDMA_CHICKEN_BITS__RESERVED__SHIFT 0x1d +#define SDMA0_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L +#define SDMA0_SDMA_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L +#define SDMA0_SDMA_CHICKEN_BITS__WR_BURST_MASK 0x00000300L +#define SDMA0_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L +#define SDMA0_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L +#define SDMA0_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L +#define SDMA0_SDMA_CHICKEN_BITS__OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L +#define SDMA0_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L +#define SDMA0_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L +#define SDMA0_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL_MASK 0x04000000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK_MASK 0x08000000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG_MASK 0x10000000L +#define SDMA0_SDMA_CHICKEN_BITS__RESERVED_MASK 0xE0000000L +//SDMA0_SDMA_CACHE_CNTL +#define SDMA0_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT__SHIFT 0x0 +#define SDMA0_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT__SHIFT 0x3 +#define SDMA0_SDMA_CACHE_CNTL__RD_SCOPE__SHIFT 0xc +#define SDMA0_SDMA_CACHE_CNTL__WR_SCOPE__SHIFT 0xe +#define SDMA0_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT_MASK 0x00000007L +#define SDMA0_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT_MASK 0x00000038L +#define SDMA0_SDMA_CACHE_CNTL__RD_SCOPE_MASK 0x00003000L +#define SDMA0_SDMA_CACHE_CNTL__WR_SCOPE_MASK 0x0000C000L +//SDMA0_SDMA_RB_RPTR_FETCH +#define SDMA0_SDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_SDMA_RB_RPTR_FETCH_HI +#define SDMA0_SDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_IB_OFFSET_FETCH +#define SDMA0_SDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_PROGRAM +#define SDMA0_SDMA_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_SDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_SDMA_STATUS_REG +#define SDMA0_SDMA_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_SDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_SDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_SDMA_STATUS_REG__RESERVED_3__SHIFT 0x3 +#define SDMA0_SDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_SDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_SDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_SDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_SDMA_STATUS_REG__CORE_IDLE__SHIFT 0x8 +#define SDMA0_SDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_SDMA_STATUS_REG__FETCH_IDLE__SHIFT 0xa +#define SDMA0_SDMA_STATUS_REG__CGCG_FENCE__SHIFT 0xb +#define SDMA0_SDMA_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_SDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_SDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_SDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_SDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_SDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_SDMA_STATUS_REG__RESERVED_24_21__SHIFT 0x15 +#define SDMA0_SDMA_STATUS_REG__EXEC_ENG_IDLE__SHIFT 0x19 +#define SDMA0_SDMA_STATUS_REG__PROC_CNTL_IDLE__SHIFT 0x1a +#define SDMA0_SDMA_STATUS_REG__UCODE_INIT_DONE__SHIFT 0x1b +#define SDMA0_SDMA_STATUS_REG__RESERVED_29_28__SHIFT 0x1c +#define SDMA0_SDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_SDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_SDMA_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_SDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_SDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_SDMA_STATUS_REG__RESERVED_3_MASK 0x00000008L +#define SDMA0_SDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_SDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_SDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_SDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_SDMA_STATUS_REG__CORE_IDLE_MASK 0x00000100L +#define SDMA0_SDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_SDMA_STATUS_REG__FETCH_IDLE_MASK 0x00000400L +#define SDMA0_SDMA_STATUS_REG__CGCG_FENCE_MASK 0x00000800L +#define SDMA0_SDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_SDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_SDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_SDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_SDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_SDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_SDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_SDMA_STATUS_REG__RESERVED_24_21_MASK 0x01E00000L +#define SDMA0_SDMA_STATUS_REG__EXEC_ENG_IDLE_MASK 0x02000000L +#define SDMA0_SDMA_STATUS_REG__PROC_CNTL_IDLE_MASK 0x04000000L +#define SDMA0_SDMA_STATUS_REG__UCODE_INIT_DONE_MASK 0x08000000L +#define SDMA0_SDMA_STATUS_REG__RESERVED_29_28_MASK 0x30000000L +#define SDMA0_SDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_SDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_SDMA_STATUS1_REG +#define SDMA0_SDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_SDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE__SHIFT 0x2 +#define SDMA0_SDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_SDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_SDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_SDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE__SHIFT 0x7 +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE__SHIFT 0x8 +#define SDMA0_SDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_SDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb +#define SDMA0_SDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc +#define SDMA0_SDMA_STATUS1_REG__EX_START__SHIFT 0xd +#define SDMA0_SDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf +#define SDMA0_SDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 +#define SDMA0_SDMA_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 +#define SDMA0_SDMA_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_IDLE__SHIFT 0x14 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT__SHIFT 0x15 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT__SHIFT 0x16 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL__SHIFT 0x17 +#define SDMA0_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW__SHIFT 0x18 +#define SDMA0_SDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_SDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE_MASK 0x00000004L +#define SDMA0_SDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_SDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_SDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_SDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE_MASK 0x00000080L +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE_MASK 0x00000100L +#define SDMA0_SDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_SDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_SDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L +#define SDMA0_SDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L +#define SDMA0_SDMA_STATUS1_REG__EX_START_MASK 0x00002000L +#define SDMA0_SDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L +#define SDMA0_SDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L +#define SDMA0_SDMA_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L +#define SDMA0_SDMA_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L +#define SDMA0_SDMA_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_IDLE_MASK 0x00100000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT_MASK 0x00200000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT_MASK 0x00400000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL_MASK 0x00800000L +#define SDMA0_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW_MASK 0x03000000L +//SDMA0_SDMA_CNTL1 +#define SDMA0_SDMA_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 +#define SDMA0_SDMA_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL +//SDMA0_SDMA_HBM_PAGE_CONFIG +#define SDMA0_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_SDMA_FREEZE +#define SDMA0_SDMA_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_SDMA_FREEZE__MCU_FREEZE__SHIFT 0x6 +#define SDMA0_SDMA_FREEZE__IMU_FSM_STATE__SHIFT 0x8 +#define SDMA0_SDMA_FREEZE__EXTERNAL_FROZEN__SHIFT 0xc +#define SDMA0_SDMA_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_SDMA_FREEZE__MCU_FREEZE_MASK 0x00000040L +#define SDMA0_SDMA_FREEZE__IMU_FSM_STATE_MASK 0x00000300L +#define SDMA0_SDMA_FREEZE__EXTERNAL_FROZEN_MASK 0x00001000L +//SDMA0_SDMA_PROCESS_QUANTUM0 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//SDMA0_SDMA_PROCESS_QUANTUM1 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//SDMA0_SDMA_WATCHDOG_CNTL +#define SDMA0_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define SDMA0_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define SDMA0_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define SDMA0_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE_STATUS0 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//SDMA0_SDMA_QUEUE_STATUS1 +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE8_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE9_STATUS__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE8_STATUS_MASK 0x0000000FL +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE9_STATUS_MASK 0x000000F0L +//SDMA0_SDMA_ID +#define SDMA0_SDMA_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_SDMA_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_SDMA_VERSION +#define SDMA0_SDMA_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_SDMA_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_SDMA_VERSION__REV__SHIFT 0x10 +#define SDMA0_SDMA_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_SDMA_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_SDMA_VERSION__REV_MASK 0x003F0000L +//SDMA0_SDMA_STATUS2_REG +#define SDMA0_SDMA_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA0_SDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_SDMA_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA0_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA0_SDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_SDMA_ATOMIC_CNTL +#define SDMA0_SDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_SDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_SDMA_ATOMIC_PERMS_CNTL +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED__SHIFT 0x1 +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC_MASK 0x00000001L +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED_MASK 0x00000002L +//SDMA0_SDMA_ATOMIC_PREOP_LO +#define SDMA0_SDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_ATOMIC_PREOP_HI +#define SDMA0_SDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_DCC_CNTL +#define SDMA0_SDMA_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0__SHIFT 0x1 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0__SHIFT 0x2 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0__SHIFT 0x3 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0__SHIFT 0x4 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1__SHIFT 0x5 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1__SHIFT 0x6 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1__SHIFT 0x7 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1__SHIFT 0x8 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2__SHIFT 0x9 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2__SHIFT 0xa +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2__SHIFT 0xb +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2__SHIFT 0xc +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3__SHIFT 0xd +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3__SHIFT 0xe +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3__SHIFT 0xf +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3__SHIFT 0x10 +#define SDMA0_SDMA_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0_MASK 0x00000002L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0_MASK 0x00000004L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0_MASK 0x00000008L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0_MASK 0x00000010L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1_MASK 0x00000020L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1_MASK 0x00000040L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1_MASK 0x00000080L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1_MASK 0x00000100L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2_MASK 0x00000200L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2_MASK 0x00000400L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2_MASK 0x00000800L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2_MASK 0x00001000L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3_MASK 0x00002000L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3_MASK 0x00004000L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3_MASK 0x00008000L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3_MASK 0x00010000L +//SDMA0_SDMA_UTCL1_WARMUPL2_CNTL +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__GRANU__SHIFT 0x8 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA_MASK 0x0000007EL +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__GRANU_MASK 0x00007F00L +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL_MASK 0x00070000L +//SDMA0_SDMA_UTCL1_CNTL +#define SDMA0_SDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 +#define SDMA0_SDMA_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xc +#define SDMA0_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0xe +#define SDMA0_SDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xf +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x13 +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT__SHIFT 0x19 +#define SDMA0_SDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL +#define SDMA0_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L +#define SDMA0_SDMA_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00001000L +#define SDMA0_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00002000L +#define SDMA0_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00004000L +#define SDMA0_SDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00078000L +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x01F80000L +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT_MASK 0x7E000000L +//SDMA0_SDMA_UTCL1_WATERMK +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L +//SDMA0_SDMA_UTCL1_TIMEOUT +#define SDMA0_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_PAGE +#define SDMA0_SDMA_UTCL1_PAGE__INVALID_ADDR__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_PAGE__USE_IO__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc +#define SDMA0_SDMA_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe +#define SDMA0_SDMA_UTCL1_PAGE__USE_BC__SHIFT 0x16 +#define SDMA0_SDMA_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE__SHIFT 0x18 +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN__SHIFT 0x19 +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x1e +#define SDMA0_SDMA_UTCL1_PAGE__INVALID_ADDR_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000003EL +#define SDMA0_SDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x00000380L +#define SDMA0_SDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L +#define SDMA0_SDMA_UTCL1_PAGE__USE_IO_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L +#define SDMA0_SDMA_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L +#define SDMA0_SDMA_UTCL1_PAGE__USE_BC_MASK 0x00400000L +#define SDMA0_SDMA_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE_MASK 0x01000000L +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN_MASK 0x02000000L +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x18000000L +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x40000000L +//SDMA0_SDMA_EXTERNAL_FROZEN +#define SDMA0_SDMA_EXTERNAL_FROZEN__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_EXTERNAL_FROZEN__THRESHOLD_MASK 0x0000FFFFL +//SDMA0_SDMA_FREEZE_TRIGGER +#define SDMA0_SDMA_FREEZE_TRIGGER__CORE_FREEZE__SHIFT 0x0 +#define SDMA0_SDMA_FREEZE_TRIGGER__CORE_FREEZE_MASK 0x00000001L +//SDMA0_SDMA_UTCL1_CACHE_CNTL +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x14 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x15 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC__SHIFT 0x19 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION__SHIFT 0x1d +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x00100000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x00600000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC_MASK 0x02000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION_MASK 0x20000000L +//SDMA0_SDMA_UTCL1_RD_STATUS +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE__SHIFT 0x1d +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE__SHIFT 0x1e +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE__SHIFT 0x1f +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE_MASK 0x00010000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE_MASK 0x10000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE_MASK 0x20000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE_MASK 0x40000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE_MASK 0x80000000L +//SDMA0_SDMA_UTCL1_WR_STATUS +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL__SHIFT 0x6 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL_MASK 0x00000040L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE_MASK 0x00010000L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L +//SDMA0_SDMA_UTCL1_INV0 +#define SDMA0_SDMA_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 +#define SDMA0_SDMA_UTCL1_INV0__INV_TYPE__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L +#define SDMA0_SDMA_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L +//SDMA0_SDMA_UTCL1_INV1 +#define SDMA0_SDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_INV2 +#define SDMA0_SDMA_UTCL1_INV2__CPF_VMID__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL +#define SDMA0_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L +#define SDMA0_SDMA_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L +//SDMA0_SDMA_UTCL1_RD_XNACK0 +#define SDMA0_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_RD_XNACK1 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA0_SDMA_UTCL1_WR_XNACK0 +#define SDMA0_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_WR_XNACK1 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA0_SDMA_CHICKEN_BITS_2 +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE__SHIFT 0x5 +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_7_6__SHIFT 0x6 +#define SDMA0_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf +#define SDMA0_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define SDMA0_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN__SHIFT 0x14 +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_30__SHIFT 0x1e +#define SDMA0_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN_MASK 0x00000010L +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE_MASK 0x00000020L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_7_6_MASK 0x000000C0L +#define SDMA0_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L +#define SDMA0_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define SDMA0_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN_MASK 0x00700000L +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_30_MASK 0x40000000L +#define SDMA0_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L +//SDMA0_SDMA_STATUS3_REG +#define SDMA0_SDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_SDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 +#define SDMA0_SDMA_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 +#define SDMA0_SDMA_STATUS3_REG__GCR_IDLE__SHIFT 0x17 +#define SDMA0_SDMA_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 +#define SDMA0_SDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 +#define SDMA0_SDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a +#define SDMA0_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e +#define SDMA0_SDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_SDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA0_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L +#define SDMA0_SDMA_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L +#define SDMA0_SDMA_STATUS3_REG__GCR_IDLE_MASK 0x00800000L +#define SDMA0_SDMA_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L +#define SDMA0_SDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L +#define SDMA0_SDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L +#define SDMA0_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L +//SDMA0_SDMA_GLOBAL_QUANTUM +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_ERROR_LOG +#define SDMA0_SDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_SDMA_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_SDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_SDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_SDMA_PUB_DUMMY_REG0 +#define SDMA0_SDMA_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_DUMMY_REG1 +#define SDMA0_SDMA_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_DUMMY_REG2 +#define SDMA0_SDMA_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_DUMMY_REG3 +#define SDMA0_SDMA_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_MCU_COUNTER +#define SDMA0_SDMA_MCU_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_MCU_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_CRD_CNTL +#define SDMA0_SDMA_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 +#define SDMA0_SDMA_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 +#define SDMA0_SDMA_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L +#define SDMA0_SDMA_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L +//SDMA0_SDMA_RLC_CGCG_CTRL +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 +#define SDMA0_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW__SHIFT 0x4 +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L +#define SDMA0_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW_MASK 0x00000010L +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L +//SDMA0_SDMA_GPU_IOV_VIOLATION_LOG +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x07C00000L +//SDMA0_SDMA_AQL_STATUS +#define SDMA0_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 +#define SDMA0_SDMA_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 +#define SDMA0_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L +#define SDMA0_SDMA_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L +//SDMA0_SDMA_TLBI_GCR_CNTL +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L +//SDMA0_SDMA_INT_STATUS +#define SDMA0_SDMA_INT_STATUS__DATA__SHIFT 0x0 +#define SDMA0_SDMA_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_GPU_IOV_VIOLATION_LOG2 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL +//SDMA0_SDMA_INVALID_ADDR_LO +#define SDMA0_SDMA_INVALID_ADDR_LO__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_INVALID_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_INVALID_ADDR_HI +#define SDMA0_SDMA_INVALID_ADDR_HI__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_INVALID_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_INVALID_ADDR_SOURCE +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__ID__SHIFT 0x0 +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VMID__SHIFT 0x6 +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VFID__SHIFT 0xa +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VF__SHIFT 0xf +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__ID_MASK 0x0000003FL +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VMID_MASK 0x000003C0L +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VFID_MASK 0x00007C00L +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VF_MASK 0x00008000L +//SDMA0_SDMA_CLOCK_GATING_STATUS +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS__SHIFT 0x9 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS__SHIFT 0xa +#define SDMA0_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS__SHIFT 0xb +#define SDMA0_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS__SHIFT 0xc +#define SDMA0_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS__SHIFT 0xd +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS__SHIFT 0xe +#define SDMA0_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS__SHIFT 0xf +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS__SHIFT 0x10 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS__SHIFT 0x11 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS__SHIFT 0x12 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS__SHIFT 0x13 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS__SHIFT 0x14 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS__SHIFT 0x15 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS__SHIFT 0x16 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS_MASK 0x00000200L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS_MASK 0x00000400L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS_MASK 0x00000800L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS_MASK 0x00001000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS_MASK 0x00002000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS_MASK 0x00004000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS_MASK 0x00008000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS_MASK 0x00010000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS_MASK 0x00020000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS_MASK 0x00040000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS_MASK 0x00080000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS_MASK 0x00100000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS_MASK 0x00200000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS_MASK 0x00400000L +//SDMA0_SDMA_STATUS4_REG +#define SDMA0_SDMA_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA0_SDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA0_SDMA_STATUS4_REG__RESERVED__SHIFT 0x3 +#define SDMA0_SDMA_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA0_SDMA_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA0_SDMA_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 +#define SDMA0_SDMA_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 +#define SDMA0_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING__SHIFT 0xa +#define SDMA0_SDMA_STATUS4_REG__RESERVED_11__SHIFT 0xb +#define SDMA0_SDMA_STATUS4_REG__RESERVED_13_12__SHIFT 0xc +#define SDMA0_SDMA_STATUS4_REG__RESERVED_15_14__SHIFT 0xe +#define SDMA0_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA0_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 +#define SDMA0_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b +#define SDMA0_SDMA_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA0_SDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_MASK 0x00000008L +#define SDMA0_SDMA_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA0_SDMA_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA0_SDMA_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L +#define SDMA0_SDMA_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L +#define SDMA0_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING_MASK 0x00000400L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_11_MASK 0x00000800L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L +#define SDMA0_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA0_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L +#define SDMA0_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L +//SDMA0_SDMA_SCRATCH_RAM_DATA +#define SDMA0_SDMA_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA0_SDMA_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_SCRATCH_RAM_ADDR +#define SDMA0_SDMA_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA0_SDMA_TIMESTAMP_CNTL +#define SDMA0_SDMA_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define SDMA0_SDMA_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//SDMA0_SDMA_STATUS5_REG +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS__SHIFT 0x9 +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x10 +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x11 +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x12 +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x13 +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS_MASK 0x00000200L +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00010000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00020000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00040000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00080000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L +//SDMA0_SDMA_QUEUE_RESET_REQ +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET_MASK 0x00000200L +//SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ_MASK 0x00000200L +//SDMA0_SDMA_STATUS6_REG +#define SDMA0_SDMA_STATUS6_REG__ID__SHIFT 0x0 +#define SDMA0_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA0_SDMA_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 +#define SDMA0_SDMA_STATUS6_REG__ID_MASK 0x00000003L +#define SDMA0_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA0_SDMA_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L +//SDMA0_SDMA_STATUS7_REG +#define SDMA0_SDMA_STATUS7_REG__BLT_REQ_DROP__SHIFT 0x0 +#define SDMA0_SDMA_STATUS7_REG__BLT_REQ_DROP_MASK 0x00000001L +//SDMA0_SDMA_STATUS8_REG +#define SDMA0_SDMA_STATUS8_REG__LD_CTXSW_COND__SHIFT 0x0 +#define SDMA0_SDMA_STATUS8_REG__LD_CTXSW_COND_MASK 0xFFFFFFFFL +//SDMA0_SDMA_CE_CTRL +#define SDMA0_SDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA0_SDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA0_SDMA_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA0_SDMA_CE_CTRL__RESERVED__SHIFT 0x9 +#define SDMA0_SDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA0_SDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA0_SDMA_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA0_SDMA_CE_CTRL__RESERVED_MASK 0xFFFFFE00L +//SDMA0_SDMA_RAS_STATUS +#define SDMA0_SDMA_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA0_SDMA_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA0_SDMA_RAS_STATUS__MCU_DATA_ECC__SHIFT 0x2 +#define SDMA0_SDMA_RAS_STATUS__WPTR_POLL_ECC__SHIFT 0x3 +#define SDMA0_SDMA_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA0_SDMA_RAS_STATUS__INSTR_FETCH_ECC__SHIFT 0x5 +#define SDMA0_SDMA_RAS_STATUS__ATOMIC_ECC__SHIFT 0x6 +#define SDMA0_SDMA_RAS_STATUS__FRONTEND_ECC__SHIFT 0x7 +#define SDMA0_SDMA_RAS_STATUS__SRAM_ECC__SHIFT 0x10 +#define SDMA0_SDMA_RAS_STATUS__BUS_PARITY__SHIFT 0x12 +#define SDMA0_SDMA_RAS_STATUS__VMID__SHIFT 0x14 +#define SDMA0_SDMA_RAS_STATUS__VFID__SHIFT 0x18 +#define SDMA0_SDMA_RAS_STATUS__VF__SHIFT 0x1d +#define SDMA0_SDMA_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA0_SDMA_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA0_SDMA_RAS_STATUS__MCU_DATA_ECC_MASK 0x00000004L +#define SDMA0_SDMA_RAS_STATUS__WPTR_POLL_ECC_MASK 0x00000008L +#define SDMA0_SDMA_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA0_SDMA_RAS_STATUS__INSTR_FETCH_ECC_MASK 0x00000020L +#define SDMA0_SDMA_RAS_STATUS__ATOMIC_ECC_MASK 0x00000040L +#define SDMA0_SDMA_RAS_STATUS__FRONTEND_ECC_MASK 0x00000080L +#define SDMA0_SDMA_RAS_STATUS__SRAM_ECC_MASK 0x00010000L +#define SDMA0_SDMA_RAS_STATUS__BUS_PARITY_MASK 0x00040000L +#define SDMA0_SDMA_RAS_STATUS__VMID_MASK 0x00F00000L +#define SDMA0_SDMA_RAS_STATUS__VFID_MASK 0x1F000000L +#define SDMA0_SDMA_RAS_STATUS__VF_MASK 0x20000000L +//SDMA0_SDMA_POISON_INFO +#define SDMA0_SDMA_POISON_INFO__VMID__SHIFT 0x0 +#define SDMA0_SDMA_POISON_INFO__VFID__SHIFT 0x4 +#define SDMA0_SDMA_POISON_INFO__VF__SHIFT 0x9 +#define SDMA0_SDMA_POISON_INFO__VMID_MASK 0x0000000FL +#define SDMA0_SDMA_POISON_INFO__VFID_MASK 0x000001F0L +#define SDMA0_SDMA_POISON_INFO__VF_MASK 0x00000200L +//SDMA0_SDMA_MEMHUB_CNTL +#define SDMA0_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ__SHIFT 0x0 +#define SDMA0_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ_MASK 0x00000003L +//SDMA0_SDMA_QUEUE0_RB_CNTL +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE0_RB_BASE +#define SDMA0_SDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_BASE_HI +#define SDMA0_SDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE0_RB_RPTR +#define SDMA0_SDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_WPTR +#define SDMA0_SDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_IB_CNTL +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE0_IB_RPTR +#define SDMA0_SDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE0_IB_OFFSET +#define SDMA0_SDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE0_IB_BASE_LO +#define SDMA0_SDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_IB_BASE_HI +#define SDMA0_SDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_IB_SIZE +#define SDMA0_SDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE0_DOORBELL +#define SDMA0_SDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE0_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE0_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE0_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE0_PREEMPT +#define SDMA0_SDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE0_DUMMY_REG +#define SDMA0_SDMA_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE0_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE0_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE0_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MQD_CONTROL +#define SDMA0_SDMA_QUEUE0_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE0_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE0_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_CNTL +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE1_RB_BASE +#define SDMA0_SDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_BASE_HI +#define SDMA0_SDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE1_RB_RPTR +#define SDMA0_SDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_WPTR +#define SDMA0_SDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_IB_CNTL +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE1_IB_RPTR +#define SDMA0_SDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE1_IB_OFFSET +#define SDMA0_SDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE1_IB_BASE_LO +#define SDMA0_SDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_IB_BASE_HI +#define SDMA0_SDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_IB_SIZE +#define SDMA0_SDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE1_DOORBELL +#define SDMA0_SDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE1_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE1_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE1_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE1_PREEMPT +#define SDMA0_SDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE1_DUMMY_REG +#define SDMA0_SDMA_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE1_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE1_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE1_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MQD_CONTROL +#define SDMA0_SDMA_QUEUE1_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE1_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE1_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_CNTL +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE2_RB_BASE +#define SDMA0_SDMA_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_BASE_HI +#define SDMA0_SDMA_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE2_RB_RPTR +#define SDMA0_SDMA_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_WPTR +#define SDMA0_SDMA_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_IB_CNTL +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE2_IB_RPTR +#define SDMA0_SDMA_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE2_IB_OFFSET +#define SDMA0_SDMA_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE2_IB_BASE_LO +#define SDMA0_SDMA_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_IB_BASE_HI +#define SDMA0_SDMA_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_IB_SIZE +#define SDMA0_SDMA_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE2_DOORBELL +#define SDMA0_SDMA_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE2_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE2_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE2_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE2_PREEMPT +#define SDMA0_SDMA_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE2_DUMMY_REG +#define SDMA0_SDMA_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE2_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE2_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE2_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MQD_CONTROL +#define SDMA0_SDMA_QUEUE2_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE2_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE2_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_CNTL +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE3_RB_BASE +#define SDMA0_SDMA_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_BASE_HI +#define SDMA0_SDMA_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE3_RB_RPTR +#define SDMA0_SDMA_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_WPTR +#define SDMA0_SDMA_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_IB_CNTL +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE3_IB_RPTR +#define SDMA0_SDMA_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE3_IB_OFFSET +#define SDMA0_SDMA_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE3_IB_BASE_LO +#define SDMA0_SDMA_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_IB_BASE_HI +#define SDMA0_SDMA_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_IB_SIZE +#define SDMA0_SDMA_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE3_DOORBELL +#define SDMA0_SDMA_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE3_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE3_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE3_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE3_PREEMPT +#define SDMA0_SDMA_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE3_DUMMY_REG +#define SDMA0_SDMA_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE3_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE3_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE3_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MQD_CONTROL +#define SDMA0_SDMA_QUEUE3_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE3_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE3_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_CNTL +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE4_RB_BASE +#define SDMA0_SDMA_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_BASE_HI +#define SDMA0_SDMA_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE4_RB_RPTR +#define SDMA0_SDMA_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_WPTR +#define SDMA0_SDMA_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_IB_CNTL +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE4_IB_RPTR +#define SDMA0_SDMA_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE4_IB_OFFSET +#define SDMA0_SDMA_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE4_IB_BASE_LO +#define SDMA0_SDMA_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_IB_BASE_HI +#define SDMA0_SDMA_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_IB_SIZE +#define SDMA0_SDMA_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE4_DOORBELL +#define SDMA0_SDMA_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE4_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE4_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE4_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE4_PREEMPT +#define SDMA0_SDMA_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE4_DUMMY_REG +#define SDMA0_SDMA_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE4_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE4_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE4_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MQD_CONTROL +#define SDMA0_SDMA_QUEUE4_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE4_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE4_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_CNTL +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE5_RB_BASE +#define SDMA0_SDMA_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_BASE_HI +#define SDMA0_SDMA_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE5_RB_RPTR +#define SDMA0_SDMA_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_WPTR +#define SDMA0_SDMA_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_IB_CNTL +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE5_IB_RPTR +#define SDMA0_SDMA_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE5_IB_OFFSET +#define SDMA0_SDMA_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE5_IB_BASE_LO +#define SDMA0_SDMA_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_IB_BASE_HI +#define SDMA0_SDMA_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_IB_SIZE +#define SDMA0_SDMA_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE5_DOORBELL +#define SDMA0_SDMA_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE5_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE5_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE5_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE5_PREEMPT +#define SDMA0_SDMA_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE5_DUMMY_REG +#define SDMA0_SDMA_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE5_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE5_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE5_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MQD_CONTROL +#define SDMA0_SDMA_QUEUE5_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE5_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE5_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_CNTL +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE6_RB_BASE +#define SDMA0_SDMA_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_BASE_HI +#define SDMA0_SDMA_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE6_RB_RPTR +#define SDMA0_SDMA_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_WPTR +#define SDMA0_SDMA_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_IB_CNTL +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE6_IB_RPTR +#define SDMA0_SDMA_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE6_IB_OFFSET +#define SDMA0_SDMA_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE6_IB_BASE_LO +#define SDMA0_SDMA_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_IB_BASE_HI +#define SDMA0_SDMA_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_IB_SIZE +#define SDMA0_SDMA_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE6_DOORBELL +#define SDMA0_SDMA_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE6_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE6_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE6_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE6_PREEMPT +#define SDMA0_SDMA_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE6_DUMMY_REG +#define SDMA0_SDMA_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE6_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE6_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE6_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MQD_CONTROL +#define SDMA0_SDMA_QUEUE6_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE6_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE6_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_CNTL +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE7_RB_BASE +#define SDMA0_SDMA_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_BASE_HI +#define SDMA0_SDMA_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE7_RB_RPTR +#define SDMA0_SDMA_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_WPTR +#define SDMA0_SDMA_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_IB_CNTL +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE7_IB_RPTR +#define SDMA0_SDMA_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE7_IB_OFFSET +#define SDMA0_SDMA_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE7_IB_BASE_LO +#define SDMA0_SDMA_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_IB_BASE_HI +#define SDMA0_SDMA_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_IB_SIZE +#define SDMA0_SDMA_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE7_DOORBELL +#define SDMA0_SDMA_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE7_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE7_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE7_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE7_PREEMPT +#define SDMA0_SDMA_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE7_DUMMY_REG +#define SDMA0_SDMA_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE7_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE7_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE7_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MQD_CONTROL +#define SDMA0_SDMA_QUEUE7_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE7_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE7_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_CNTL +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE8_RB_BASE +#define SDMA0_SDMA_QUEUE8_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_BASE_HI +#define SDMA0_SDMA_QUEUE8_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE8_RB_RPTR +#define SDMA0_SDMA_QUEUE8_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE8_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_WPTR +#define SDMA0_SDMA_QUEUE8_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE8_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_IB_CNTL +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE8_IB_RPTR +#define SDMA0_SDMA_QUEUE8_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE8_IB_OFFSET +#define SDMA0_SDMA_QUEUE8_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE8_IB_BASE_LO +#define SDMA0_SDMA_QUEUE8_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_IB_BASE_HI +#define SDMA0_SDMA_QUEUE8_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_IB_SIZE +#define SDMA0_SDMA_QUEUE8_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE8_DOORBELL +#define SDMA0_SDMA_QUEUE8_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE8_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE8_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE8_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE8_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE8_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE8_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE8_PREEMPT +#define SDMA0_SDMA_QUEUE8_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE8_DUMMY_REG +#define SDMA0_SDMA_QUEUE8_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE8_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE8_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE8_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MQD_CONTROL +#define SDMA0_SDMA_QUEUE8_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE8_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE8_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_CNTL +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE9_RB_BASE +#define SDMA0_SDMA_QUEUE9_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_BASE_HI +#define SDMA0_SDMA_QUEUE9_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE9_RB_RPTR +#define SDMA0_SDMA_QUEUE9_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE9_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_WPTR +#define SDMA0_SDMA_QUEUE9_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE9_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_IB_CNTL +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE9_IB_RPTR +#define SDMA0_SDMA_QUEUE9_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE9_IB_OFFSET +#define SDMA0_SDMA_QUEUE9_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE9_IB_BASE_LO +#define SDMA0_SDMA_QUEUE9_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_IB_BASE_HI +#define SDMA0_SDMA_QUEUE9_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_IB_SIZE +#define SDMA0_SDMA_QUEUE9_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE9_DOORBELL +#define SDMA0_SDMA_QUEUE9_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE9_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE9_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE9_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE9_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE9_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE9_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE9_PREEMPT +#define SDMA0_SDMA_QUEUE9_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE9_DUMMY_REG +#define SDMA0_SDMA_QUEUE9_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE9_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE9_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE9_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MQD_CONTROL +#define SDMA0_SDMA_QUEUE9_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE9_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE9_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec +//SDMA0_SDMA_VM_CTX_LO +#define SDMA0_SDMA_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_VM_CTX_HI +#define SDMA0_SDMA_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_ACTIVE_FCN_ID +#define SDMA0_SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x7 +#define SDMA0_SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x8 +#define SDMA0_SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define SDMA0_SDMA_ACTIVE_FCN_ID__VF_MASK 0x00000080L +#define SDMA0_SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0xFFFFFF00L +//SDMA0_SDMA_VM_CTX_CNTL +#define SDMA0_SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_PHY__SHIFT 0x8 +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_MTYPE__SHIFT 0xa +#define SDMA0_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_PHY_MASK 0x00000300L +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_MTYPE_MASK 0x00000C00L +#define SDMA0_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE_MASK 0x00010000L +//SDMA0_SDMA_VIRT_RESET_REQ +#define SDMA0_SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_SDMA_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL +#define SDMA0_SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_SDMA_CONTEXT_REG_TYPE0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL__SHIFT 0x0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE__SHIFT 0x1 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR__SHIFT 0x3 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR__SHIFT 0x5 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO__SHIFT 0x7 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL__SHIFT 0x9 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR__SHIFT 0xa +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET__SHIFT 0xb +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO__SHIFT 0xc +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI__SHIFT 0xd +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE__SHIFT 0xe +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL__SHIFT 0xf +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG__SHIFT 0x10 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET__SHIFT 0x11 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO__SHIFT 0x12 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI__SHIFT 0x13 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL__SHIFT 0x14 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN__SHIFT 0x15 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT__SHIFT 0x16 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG__SHIFT 0x17 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__SHIFT 0x18 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__SHIFT 0x19 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL__SHIFT 0x1a +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE__SHIFT 0x1b +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SHIFT 0x1e +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL__SHIFT 0x1f +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL_MASK 0x00000001L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_MASK 0x00000002L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_MASK 0x00000008L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_MASK 0x00000020L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO_MASK 0x00000080L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL_MASK 0x00000200L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR_MASK 0x00000400L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET_MASK 0x00000800L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO_MASK 0x00001000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI_MASK 0x00002000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE_MASK 0x00004000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_MASK 0x00008000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG_MASK 0x00010000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET_MASK 0x00020000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO_MASK 0x00040000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI_MASK 0x00080000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL_MASK 0x00100000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN_MASK 0x00200000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT_MASK 0x00400000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG_MASK 0x00800000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_MASK 0x01000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_MASK 0x02000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL_MASK 0x04000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE_MASK 0x08000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_MASK 0x40000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL_MASK 0x80000000L +//SDMA0_SDMA_CONTEXT_REG_TYPE1 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9__SHIFT 0x9 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10__SHIFT 0xa +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO__SHIFT 0xb +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI__SHIFT 0xc +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD__SHIFT 0xd +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO__SHIFT 0xe +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI__SHIFT 0xf +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL__SHIFT 0x10 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x14 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9_MASK 0x00000200L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10_MASK 0x00000400L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO_MASK 0x00000800L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI_MASK 0x00001000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD_MASK 0x00002000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO_MASK 0x00004000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI_MASK 0x00008000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL_MASK 0x00010000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFF00000L +//SDMA0_SDMA_CONTEXT_REG_TYPE2 +#define SDMA0_SDMA_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_REG_TYPE0 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_DEC_START__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CNTL__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE0__RESERVED__SHIFT 0x15 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_DEC_START_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CNTL_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE0__RESERVED_MASK 0xFFE00000L +//SDMA0_SDMA_PUB_REG_TYPE1 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH__SHIFT 0x2 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG__SHIFT 0x4 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_CNTL1__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG__SHIFT 0x7 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE__SHIFT 0x8 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0__SHIFT 0x9 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1__SHIFT 0xa +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL__SHIFT 0xb +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ID__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_VERSION__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG__SHIFT 0x10 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL__SHIFT 0x11 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL__SHIFT 0x12 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO__SHIFT 0x13 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI__SHIFT 0x14 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL__SHIFT 0x15 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL__SHIFT 0x16 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL__SHIFT 0x17 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK__SHIFT 0x18 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT__SHIFT 0x19 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE__SHIFT 0x1a +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN__SHIFT 0x1b +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER__SHIFT 0x1c +#define SDMA0_SDMA_PUB_REG_TYPE1__RESERVED__SHIFT 0x1d +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH_MASK 0x00000004L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG_MASK 0x00000010L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_CNTL1_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG_MASK 0x00000080L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_MASK 0x00000100L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0_MASK 0x00000200L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1_MASK 0x00000400L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL_MASK 0x00000800L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ID_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_VERSION_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG_MASK 0x00010000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL_MASK 0x00020000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL_MASK 0x00040000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO_MASK 0x00080000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI_MASK 0x00100000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL_MASK 0x00200000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL_MASK 0x00400000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL_MASK 0x00800000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK_MASK 0x01000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT_MASK 0x02000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE_MASK 0x04000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN_MASK 0x08000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER_MASK 0x10000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__RESERVED_MASK 0xE0000000L +//SDMA0_SDMA_PUB_REG_TYPE2 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS__SHIFT 0x2 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1__SHIFT 0x4 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1__SHIFT 0x7 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0__SHIFT 0x8 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1__SHIFT 0x9 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2__SHIFT 0xa +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG__SHIFT 0xb +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2__SHIFT 0x10 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3__SHIFT 0x11 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER__SHIFT 0x12 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL__SHIFT 0x13 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL__SHIFT 0x14 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG__SHIFT 0x15 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS__SHIFT 0x17 +#define SDMA0_SDMA_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS_MASK 0x00000004L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1_MASK 0x00000010L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1_MASK 0x00000080L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0_MASK 0x00000100L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1_MASK 0x00000200L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2_MASK 0x00000400L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG_MASK 0x00000800L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2_MASK 0x00010000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3_MASK 0x00020000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER_MASK 0x00040000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL_MASK 0x00080000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL_MASK 0x00100000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG_MASK 0x00200000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS_MASK 0x00800000L +#define SDMA0_SDMA_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_SDMA_PUB_REG_TYPE3 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI__SHIFT 0x4 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG__SHIFT 0x7 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA__SHIFT 0x8 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR__SHIFT 0x9 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL__SHIFT 0xa +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG__SHIFT 0xb +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS__SHIFT 0x10 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO__SHIFT 0x11 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL__SHIFT 0x12 +#define SDMA0_SDMA_PUB_REG_TYPE3__RESERVED__SHIFT 0x13 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI_MASK 0x00000010L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG_MASK 0x00000080L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA_MASK 0x00000100L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR_MASK 0x00000200L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL_MASK 0x00000400L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG_MASK 0x00000800L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS_MASK 0x00010000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO_MASK 0x00020000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL_MASK 0x00040000L +#define SDMA0_SDMA_PUB_REG_TYPE3__RESERVED_MASK 0xFFF80000L +//SDMA0_SDMA_VM_CNTL +#define SDMA0_SDMA_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_SDMA_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_SDMA_MCU_CNTL +#define SDMA0_SDMA_MCU_CNTL__HALT__SHIFT 0x0 +#define SDMA0_SDMA_MCU_CNTL__RESET__SHIFT 0x1 +#define SDMA0_SDMA_MCU_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA0_SDMA_MCU_CNTL__HALT_MASK 0x00000001L +#define SDMA0_SDMA_MCU_CNTL__RESET_MASK 0x00000002L +#define SDMA0_SDMA_MCU_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +//SDMA0_SDMA_IC_BASE_LO +#define SDMA0_SDMA_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define SDMA0_SDMA_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//SDMA0_SDMA_IC_BASE_HI +#define SDMA0_SDMA_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define SDMA0_SDMA_IC_BASE_HI__IC_BASE_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_IC_BASE_CNTL +#define SDMA0_SDMA_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_IC_BASE_CNTL__MTYPE__SHIFT 0x4 +#define SDMA0_SDMA_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define SDMA0_SDMA_IC_BASE_CNTL__TEMPORAL_HINT__SHIFT 0x18 +#define SDMA0_SDMA_IC_BASE_CNTL__SCOPE__SHIFT 0x1c +#define SDMA0_SDMA_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define SDMA0_SDMA_IC_BASE_CNTL__MTYPE_MASK 0x00000030L +#define SDMA0_SDMA_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define SDMA0_SDMA_IC_BASE_CNTL__TEMPORAL_HINT_MASK 0x07000000L +#define SDMA0_SDMA_IC_BASE_CNTL__SCOPE_MASK 0x30000000L +//SDMA0_SDMA_IC_OP_CNTL +#define SDMA0_SDMA_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define SDMA0_SDMA_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define SDMA0_SDMA_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define SDMA0_SDMA_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define SDMA0_SDMA_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define SDMA0_SDMA_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//SDMA0_SDMA_IC_CNTL +#define SDMA0_SDMA_IC_CNTL__CID_SEL__SHIFT 0x0 +#define SDMA0_SDMA_IC_CNTL__GPA__SHIFT 0x2 +#define SDMA0_SDMA_IC_CNTL__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define SDMA0_SDMA_IC_CNTL__AUTO_PRIME_ICACHE__SHIFT 0x5 +#define SDMA0_SDMA_IC_CNTL__CID_SEL_MASK 0x00000001L +#define SDMA0_SDMA_IC_CNTL__GPA_MASK 0x0000000CL +#define SDMA0_SDMA_IC_CNTL__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define SDMA0_SDMA_IC_CNTL__AUTO_PRIME_ICACHE_MASK 0x00000020L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec +//SDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET +#define SDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA__SHIFT 0x0 +#define SDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec +//SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA0_SDMA_PERFCNT_MISC_CNTL +#define SDMA0_SDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA0_SDMA_PERFCOUNTER0_SELECT +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER0_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER1_SELECT +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER1_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER2_SELECT +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER2_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER3_SELECT +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER3_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER4_SELECT +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER4_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER5_SELECT +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER5_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec +//SDMA0_SDMA_PERFCNT_PERFCOUNTER_LO +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA0_SDMA_PERFCOUNTER0_LO +#define SDMA0_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER0_HI +#define SDMA0_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER1_LO +#define SDMA0_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER1_HI +#define SDMA0_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER2_LO +#define SDMA0_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER2_HI +#define SDMA0_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER3_LO +#define SDMA0_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER3_HI +#define SDMA0_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER4_LO +#define SDMA0_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER4_HI +#define SDMA0_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER5_LO +#define SDMA0_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER5_HI +#define SDMA0_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec +//SDMA0_GFX_ICG_SDMA_CTRL +#define SDMA0_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x1 +#define SDMA0_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x2 +#define SDMA0_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x3 +#define SDMA0_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x4 +#define SDMA0_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x5 +#define SDMA0_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x6 +#define SDMA0_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x7 +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x8 +#define SDMA0_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x9 +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xa +#define SDMA0_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xb +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xc +#define SDMA0_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xd +#define SDMA0_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xe +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xf +#define SDMA0_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x10 +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x11 +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x12 +#define SDMA0_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST__SHIFT 0x18 +#define SDMA0_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000002L +#define SDMA0_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000004L +#define SDMA0_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000008L +#define SDMA0_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000010L +#define SDMA0_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000020L +#define SDMA0_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000040L +#define SDMA0_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000080L +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000100L +#define SDMA0_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000200L +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000400L +#define SDMA0_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000800L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00001000L +#define SDMA0_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00002000L +#define SDMA0_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00004000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00008000L +#define SDMA0_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00010000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00020000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00040000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec:1 +//SDMA1_SDMA_DEC_START +#define SDMA1_SDMA_DEC_START__START__SHIFT 0x0 +#define SDMA1_SDMA_DEC_START__START_MASK 0xFFFFFFFFL +//SDMA1_SDMA_MCU_MISC_CNTL +#define SDMA1_SDMA_MCU_MISC_CNTL__MCU_WAKEUP__SHIFT 0x0 +#define SDMA1_SDMA_MCU_MISC_CNTL__MCU_WAKEUP_MASK 0x00000001L +//SDMA1_SDMA_UCODE_REV +#define SDMA1_SDMA_UCODE_REV__P4_CL__SHIFT 0x0 +#define SDMA1_SDMA_UCODE_REV__DEBUG_VER__SHIFT 0x18 +#define SDMA1_SDMA_UCODE_REV__VARIANT_ID__SHIFT 0x1c +#define SDMA1_SDMA_UCODE_REV__P4_CL_MASK 0x00FFFFFFL +#define SDMA1_SDMA_UCODE_REV__DEBUG_VER_MASK 0x0F000000L +#define SDMA1_SDMA_UCODE_REV__VARIANT_ID_MASK 0xF0000000L +//SDMA1_SDMA_GLOBAL_TIMESTAMP_LO +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_GLOBAL_TIMESTAMP_HI +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_POWER_CNTL +#define SDMA1_SDMA_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//SDMA1_SDMA_CNTL +#define SDMA1_SDMA_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_CNTL__RESERVED__SHIFT 0x2 +#define SDMA1_SDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_SDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_SDMA_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 +#define SDMA1_SDMA_CNTL__CP_MES_SYNC_ENABLE__SHIFT 0x7 +#define SDMA1_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_SDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_SDMA_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_SDMA_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define SDMA1_SDMA_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_CNTL__RESERVED_MASK 0x00000004L +#define SDMA1_SDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_SDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_SDMA_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L +#define SDMA1_SDMA_CNTL__CP_MES_SYNC_ENABLE_MASK 0x00000080L +#define SDMA1_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_SDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_SDMA_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define SDMA1_SDMA_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//SDMA1_SDMA_CHICKEN_BITS +#define SDMA1_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 +#define SDMA1_SDMA_CHICKEN_BITS__RD_BURST__SHIFT 0x6 +#define SDMA1_SDMA_CHICKEN_BITS__WR_BURST__SHIFT 0x8 +#define SDMA1_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe +#define SDMA1_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf +#define SDMA1_SDMA_CHICKEN_BITS__OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 +#define SDMA1_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 +#define SDMA1_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 +#define SDMA1_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x1a +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK__SHIFT 0x1b +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG__SHIFT 0x1c +#define SDMA1_SDMA_CHICKEN_BITS__RESERVED__SHIFT 0x1d +#define SDMA1_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L +#define SDMA1_SDMA_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L +#define SDMA1_SDMA_CHICKEN_BITS__WR_BURST_MASK 0x00000300L +#define SDMA1_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L +#define SDMA1_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L +#define SDMA1_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L +#define SDMA1_SDMA_CHICKEN_BITS__OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L +#define SDMA1_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L +#define SDMA1_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L +#define SDMA1_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL_MASK 0x04000000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK_MASK 0x08000000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG_MASK 0x10000000L +#define SDMA1_SDMA_CHICKEN_BITS__RESERVED_MASK 0xE0000000L +//SDMA1_SDMA_CACHE_CNTL +#define SDMA1_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT__SHIFT 0x0 +#define SDMA1_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT__SHIFT 0x3 +#define SDMA1_SDMA_CACHE_CNTL__RD_SCOPE__SHIFT 0xc +#define SDMA1_SDMA_CACHE_CNTL__WR_SCOPE__SHIFT 0xe +#define SDMA1_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT_MASK 0x00000007L +#define SDMA1_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT_MASK 0x00000038L +#define SDMA1_SDMA_CACHE_CNTL__RD_SCOPE_MASK 0x00003000L +#define SDMA1_SDMA_CACHE_CNTL__WR_SCOPE_MASK 0x0000C000L +//SDMA1_SDMA_RB_RPTR_FETCH +#define SDMA1_SDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_SDMA_RB_RPTR_FETCH_HI +#define SDMA1_SDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_IB_OFFSET_FETCH +#define SDMA1_SDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_PROGRAM +#define SDMA1_SDMA_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_SDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_SDMA_STATUS_REG +#define SDMA1_SDMA_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_SDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_SDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_SDMA_STATUS_REG__RESERVED_3__SHIFT 0x3 +#define SDMA1_SDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_SDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_SDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_SDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_SDMA_STATUS_REG__CORE_IDLE__SHIFT 0x8 +#define SDMA1_SDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_SDMA_STATUS_REG__FETCH_IDLE__SHIFT 0xa +#define SDMA1_SDMA_STATUS_REG__CGCG_FENCE__SHIFT 0xb +#define SDMA1_SDMA_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_SDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_SDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_SDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_SDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_SDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_SDMA_STATUS_REG__RESERVED_24_21__SHIFT 0x15 +#define SDMA1_SDMA_STATUS_REG__EXEC_ENG_IDLE__SHIFT 0x19 +#define SDMA1_SDMA_STATUS_REG__PROC_CNTL_IDLE__SHIFT 0x1a +#define SDMA1_SDMA_STATUS_REG__UCODE_INIT_DONE__SHIFT 0x1b +#define SDMA1_SDMA_STATUS_REG__RESERVED_29_28__SHIFT 0x1c +#define SDMA1_SDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_SDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_SDMA_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_SDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_SDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_SDMA_STATUS_REG__RESERVED_3_MASK 0x00000008L +#define SDMA1_SDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_SDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_SDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_SDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_SDMA_STATUS_REG__CORE_IDLE_MASK 0x00000100L +#define SDMA1_SDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_SDMA_STATUS_REG__FETCH_IDLE_MASK 0x00000400L +#define SDMA1_SDMA_STATUS_REG__CGCG_FENCE_MASK 0x00000800L +#define SDMA1_SDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_SDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_SDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_SDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_SDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_SDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_SDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_SDMA_STATUS_REG__RESERVED_24_21_MASK 0x01E00000L +#define SDMA1_SDMA_STATUS_REG__EXEC_ENG_IDLE_MASK 0x02000000L +#define SDMA1_SDMA_STATUS_REG__PROC_CNTL_IDLE_MASK 0x04000000L +#define SDMA1_SDMA_STATUS_REG__UCODE_INIT_DONE_MASK 0x08000000L +#define SDMA1_SDMA_STATUS_REG__RESERVED_29_28_MASK 0x30000000L +#define SDMA1_SDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_SDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_SDMA_STATUS1_REG +#define SDMA1_SDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_SDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE__SHIFT 0x2 +#define SDMA1_SDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_SDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_SDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_SDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE__SHIFT 0x7 +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE__SHIFT 0x8 +#define SDMA1_SDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_SDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb +#define SDMA1_SDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc +#define SDMA1_SDMA_STATUS1_REG__EX_START__SHIFT 0xd +#define SDMA1_SDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf +#define SDMA1_SDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 +#define SDMA1_SDMA_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 +#define SDMA1_SDMA_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_IDLE__SHIFT 0x14 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT__SHIFT 0x15 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT__SHIFT 0x16 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL__SHIFT 0x17 +#define SDMA1_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW__SHIFT 0x18 +#define SDMA1_SDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_SDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE_MASK 0x00000004L +#define SDMA1_SDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_SDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_SDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_SDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE_MASK 0x00000080L +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE_MASK 0x00000100L +#define SDMA1_SDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_SDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_SDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L +#define SDMA1_SDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L +#define SDMA1_SDMA_STATUS1_REG__EX_START_MASK 0x00002000L +#define SDMA1_SDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L +#define SDMA1_SDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L +#define SDMA1_SDMA_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L +#define SDMA1_SDMA_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L +#define SDMA1_SDMA_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_IDLE_MASK 0x00100000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT_MASK 0x00200000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT_MASK 0x00400000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL_MASK 0x00800000L +#define SDMA1_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW_MASK 0x03000000L +//SDMA1_SDMA_CNTL1 +#define SDMA1_SDMA_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 +#define SDMA1_SDMA_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL +//SDMA1_SDMA_HBM_PAGE_CONFIG +#define SDMA1_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA1_SDMA_FREEZE +#define SDMA1_SDMA_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_SDMA_FREEZE__MCU_FREEZE__SHIFT 0x6 +#define SDMA1_SDMA_FREEZE__IMU_FSM_STATE__SHIFT 0x8 +#define SDMA1_SDMA_FREEZE__EXTERNAL_FROZEN__SHIFT 0xc +#define SDMA1_SDMA_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_SDMA_FREEZE__MCU_FREEZE_MASK 0x00000040L +#define SDMA1_SDMA_FREEZE__IMU_FSM_STATE_MASK 0x00000300L +#define SDMA1_SDMA_FREEZE__EXTERNAL_FROZEN_MASK 0x00001000L +//SDMA1_SDMA_PROCESS_QUANTUM0 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//SDMA1_SDMA_PROCESS_QUANTUM1 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//SDMA1_SDMA_WATCHDOG_CNTL +#define SDMA1_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define SDMA1_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define SDMA1_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define SDMA1_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE_STATUS0 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//SDMA1_SDMA_QUEUE_STATUS1 +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE8_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE9_STATUS__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE8_STATUS_MASK 0x0000000FL +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE9_STATUS_MASK 0x000000F0L +//SDMA1_SDMA_ID +#define SDMA1_SDMA_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_SDMA_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_SDMA_VERSION +#define SDMA1_SDMA_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_SDMA_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_SDMA_VERSION__REV__SHIFT 0x10 +#define SDMA1_SDMA_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_SDMA_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_SDMA_VERSION__REV_MASK 0x003F0000L +//SDMA1_SDMA_STATUS2_REG +#define SDMA1_SDMA_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA1_SDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_SDMA_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA1_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA1_SDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_SDMA_ATOMIC_CNTL +#define SDMA1_SDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_SDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_SDMA_ATOMIC_PERMS_CNTL +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED__SHIFT 0x1 +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC_MASK 0x00000001L +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED_MASK 0x00000002L +//SDMA1_SDMA_ATOMIC_PREOP_LO +#define SDMA1_SDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_ATOMIC_PREOP_HI +#define SDMA1_SDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_DCC_CNTL +#define SDMA1_SDMA_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0__SHIFT 0x1 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0__SHIFT 0x2 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0__SHIFT 0x3 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0__SHIFT 0x4 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1__SHIFT 0x5 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1__SHIFT 0x6 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1__SHIFT 0x7 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1__SHIFT 0x8 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2__SHIFT 0x9 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2__SHIFT 0xa +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2__SHIFT 0xb +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2__SHIFT 0xc +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3__SHIFT 0xd +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3__SHIFT 0xe +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3__SHIFT 0xf +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3__SHIFT 0x10 +#define SDMA1_SDMA_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0_MASK 0x00000002L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0_MASK 0x00000004L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0_MASK 0x00000008L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0_MASK 0x00000010L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1_MASK 0x00000020L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1_MASK 0x00000040L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1_MASK 0x00000080L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1_MASK 0x00000100L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2_MASK 0x00000200L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2_MASK 0x00000400L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2_MASK 0x00000800L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2_MASK 0x00001000L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3_MASK 0x00002000L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3_MASK 0x00004000L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3_MASK 0x00008000L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3_MASK 0x00010000L +//SDMA1_SDMA_UTCL1_WARMUPL2_CNTL +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__GRANU__SHIFT 0x8 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA_MASK 0x0000007EL +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__GRANU_MASK 0x00007F00L +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL_MASK 0x00070000L +//SDMA1_SDMA_UTCL1_CNTL +#define SDMA1_SDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 +#define SDMA1_SDMA_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xc +#define SDMA1_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0xe +#define SDMA1_SDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xf +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x13 +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT__SHIFT 0x19 +#define SDMA1_SDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL +#define SDMA1_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L +#define SDMA1_SDMA_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00001000L +#define SDMA1_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00002000L +#define SDMA1_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00004000L +#define SDMA1_SDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00078000L +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x01F80000L +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT_MASK 0x7E000000L +//SDMA1_SDMA_UTCL1_WATERMK +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L +//SDMA1_SDMA_UTCL1_TIMEOUT +#define SDMA1_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_PAGE +#define SDMA1_SDMA_UTCL1_PAGE__INVALID_ADDR__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_PAGE__USE_IO__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc +#define SDMA1_SDMA_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe +#define SDMA1_SDMA_UTCL1_PAGE__USE_BC__SHIFT 0x16 +#define SDMA1_SDMA_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE__SHIFT 0x18 +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN__SHIFT 0x19 +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x1e +#define SDMA1_SDMA_UTCL1_PAGE__INVALID_ADDR_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000003EL +#define SDMA1_SDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x00000380L +#define SDMA1_SDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L +#define SDMA1_SDMA_UTCL1_PAGE__USE_IO_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L +#define SDMA1_SDMA_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L +#define SDMA1_SDMA_UTCL1_PAGE__USE_BC_MASK 0x00400000L +#define SDMA1_SDMA_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE_MASK 0x01000000L +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN_MASK 0x02000000L +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x18000000L +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x40000000L +//SDMA1_SDMA_EXTERNAL_FROZEN +#define SDMA1_SDMA_EXTERNAL_FROZEN__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_EXTERNAL_FROZEN__THRESHOLD_MASK 0x0000FFFFL +//SDMA1_SDMA_FREEZE_TRIGGER +#define SDMA1_SDMA_FREEZE_TRIGGER__CORE_FREEZE__SHIFT 0x0 +#define SDMA1_SDMA_FREEZE_TRIGGER__CORE_FREEZE_MASK 0x00000001L +//SDMA1_SDMA_UTCL1_CACHE_CNTL +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x14 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x15 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC__SHIFT 0x19 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION__SHIFT 0x1d +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x00100000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x00600000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC_MASK 0x02000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION_MASK 0x20000000L +//SDMA1_SDMA_UTCL1_RD_STATUS +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE__SHIFT 0x1d +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE__SHIFT 0x1e +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE__SHIFT 0x1f +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE_MASK 0x00010000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE_MASK 0x10000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE_MASK 0x20000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE_MASK 0x40000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE_MASK 0x80000000L +//SDMA1_SDMA_UTCL1_WR_STATUS +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL__SHIFT 0x6 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL_MASK 0x00000040L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE_MASK 0x00010000L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L +//SDMA1_SDMA_UTCL1_INV0 +#define SDMA1_SDMA_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 +#define SDMA1_SDMA_UTCL1_INV0__INV_TYPE__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L +#define SDMA1_SDMA_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L +//SDMA1_SDMA_UTCL1_INV1 +#define SDMA1_SDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_INV2 +#define SDMA1_SDMA_UTCL1_INV2__CPF_VMID__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL +#define SDMA1_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L +#define SDMA1_SDMA_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L +//SDMA1_SDMA_UTCL1_RD_XNACK0 +#define SDMA1_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_RD_XNACK1 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA1_SDMA_UTCL1_WR_XNACK0 +#define SDMA1_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_WR_XNACK1 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA1_SDMA_CHICKEN_BITS_2 +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE__SHIFT 0x5 +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_7_6__SHIFT 0x6 +#define SDMA1_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf +#define SDMA1_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define SDMA1_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN__SHIFT 0x14 +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_30__SHIFT 0x1e +#define SDMA1_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN_MASK 0x00000010L +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE_MASK 0x00000020L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_7_6_MASK 0x000000C0L +#define SDMA1_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L +#define SDMA1_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define SDMA1_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN_MASK 0x00700000L +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_30_MASK 0x40000000L +#define SDMA1_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L +//SDMA1_SDMA_STATUS3_REG +#define SDMA1_SDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_SDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 +#define SDMA1_SDMA_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 +#define SDMA1_SDMA_STATUS3_REG__GCR_IDLE__SHIFT 0x17 +#define SDMA1_SDMA_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 +#define SDMA1_SDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 +#define SDMA1_SDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a +#define SDMA1_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e +#define SDMA1_SDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_SDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA1_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L +#define SDMA1_SDMA_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L +#define SDMA1_SDMA_STATUS3_REG__GCR_IDLE_MASK 0x00800000L +#define SDMA1_SDMA_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L +#define SDMA1_SDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L +#define SDMA1_SDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L +#define SDMA1_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L +//SDMA1_SDMA_GLOBAL_QUANTUM +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_ERROR_LOG +#define SDMA1_SDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_SDMA_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_SDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_SDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_SDMA_PUB_DUMMY_REG0 +#define SDMA1_SDMA_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_DUMMY_REG1 +#define SDMA1_SDMA_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_DUMMY_REG2 +#define SDMA1_SDMA_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_DUMMY_REG3 +#define SDMA1_SDMA_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_MCU_COUNTER +#define SDMA1_SDMA_MCU_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_MCU_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_CRD_CNTL +#define SDMA1_SDMA_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 +#define SDMA1_SDMA_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 +#define SDMA1_SDMA_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L +#define SDMA1_SDMA_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L +//SDMA1_SDMA_RLC_CGCG_CTRL +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 +#define SDMA1_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW__SHIFT 0x4 +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L +#define SDMA1_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW_MASK 0x00000010L +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L +//SDMA1_SDMA_GPU_IOV_VIOLATION_LOG +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x07C00000L +//SDMA1_SDMA_AQL_STATUS +#define SDMA1_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 +#define SDMA1_SDMA_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 +#define SDMA1_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L +#define SDMA1_SDMA_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L +//SDMA1_SDMA_TLBI_GCR_CNTL +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L +//SDMA1_SDMA_INT_STATUS +#define SDMA1_SDMA_INT_STATUS__DATA__SHIFT 0x0 +#define SDMA1_SDMA_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_GPU_IOV_VIOLATION_LOG2 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL +//SDMA1_SDMA_INVALID_ADDR_LO +#define SDMA1_SDMA_INVALID_ADDR_LO__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_INVALID_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_INVALID_ADDR_HI +#define SDMA1_SDMA_INVALID_ADDR_HI__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_INVALID_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_INVALID_ADDR_SOURCE +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__ID__SHIFT 0x0 +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VMID__SHIFT 0x6 +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VFID__SHIFT 0xa +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VF__SHIFT 0xf +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__ID_MASK 0x0000003FL +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VMID_MASK 0x000003C0L +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VFID_MASK 0x00007C00L +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VF_MASK 0x00008000L +//SDMA1_SDMA_CLOCK_GATING_STATUS +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS__SHIFT 0x9 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS__SHIFT 0xa +#define SDMA1_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS__SHIFT 0xb +#define SDMA1_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS__SHIFT 0xc +#define SDMA1_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS__SHIFT 0xd +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS__SHIFT 0xe +#define SDMA1_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS__SHIFT 0xf +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS__SHIFT 0x10 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS__SHIFT 0x11 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS__SHIFT 0x12 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS__SHIFT 0x13 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS__SHIFT 0x14 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS__SHIFT 0x15 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS__SHIFT 0x16 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS_MASK 0x00000200L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS_MASK 0x00000400L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS_MASK 0x00000800L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS_MASK 0x00001000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS_MASK 0x00002000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS_MASK 0x00004000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS_MASK 0x00008000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS_MASK 0x00010000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS_MASK 0x00020000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS_MASK 0x00040000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS_MASK 0x00080000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS_MASK 0x00100000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS_MASK 0x00200000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS_MASK 0x00400000L +//SDMA1_SDMA_STATUS4_REG +#define SDMA1_SDMA_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA1_SDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA1_SDMA_STATUS4_REG__RESERVED__SHIFT 0x3 +#define SDMA1_SDMA_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA1_SDMA_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA1_SDMA_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 +#define SDMA1_SDMA_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 +#define SDMA1_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING__SHIFT 0xa +#define SDMA1_SDMA_STATUS4_REG__RESERVED_11__SHIFT 0xb +#define SDMA1_SDMA_STATUS4_REG__RESERVED_13_12__SHIFT 0xc +#define SDMA1_SDMA_STATUS4_REG__RESERVED_15_14__SHIFT 0xe +#define SDMA1_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA1_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 +#define SDMA1_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b +#define SDMA1_SDMA_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA1_SDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_MASK 0x00000008L +#define SDMA1_SDMA_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA1_SDMA_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA1_SDMA_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L +#define SDMA1_SDMA_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L +#define SDMA1_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING_MASK 0x00000400L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_11_MASK 0x00000800L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L +#define SDMA1_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA1_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L +#define SDMA1_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L +//SDMA1_SDMA_SCRATCH_RAM_DATA +#define SDMA1_SDMA_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA1_SDMA_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_SCRATCH_RAM_ADDR +#define SDMA1_SDMA_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA1_SDMA_TIMESTAMP_CNTL +#define SDMA1_SDMA_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define SDMA1_SDMA_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//SDMA1_SDMA_STATUS5_REG +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS__SHIFT 0x9 +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x10 +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x11 +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x12 +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x13 +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS_MASK 0x00000200L +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00010000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00020000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00040000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00080000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L +//SDMA1_SDMA_QUEUE_RESET_REQ +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET_MASK 0x00000200L +//SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ_MASK 0x00000200L +//SDMA1_SDMA_STATUS6_REG +#define SDMA1_SDMA_STATUS6_REG__ID__SHIFT 0x0 +#define SDMA1_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA1_SDMA_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 +#define SDMA1_SDMA_STATUS6_REG__ID_MASK 0x00000003L +#define SDMA1_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA1_SDMA_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L +//SDMA1_SDMA_STATUS7_REG +#define SDMA1_SDMA_STATUS7_REG__BLT_REQ_DROP__SHIFT 0x0 +#define SDMA1_SDMA_STATUS7_REG__BLT_REQ_DROP_MASK 0x00000001L +//SDMA1_SDMA_STATUS8_REG +#define SDMA1_SDMA_STATUS8_REG__LD_CTXSW_COND__SHIFT 0x0 +#define SDMA1_SDMA_STATUS8_REG__LD_CTXSW_COND_MASK 0xFFFFFFFFL +//SDMA1_SDMA_CE_CTRL +#define SDMA1_SDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA1_SDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA1_SDMA_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA1_SDMA_CE_CTRL__RESERVED__SHIFT 0x9 +#define SDMA1_SDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA1_SDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA1_SDMA_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA1_SDMA_CE_CTRL__RESERVED_MASK 0xFFFFFE00L +//SDMA1_SDMA_RAS_STATUS +#define SDMA1_SDMA_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA1_SDMA_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA1_SDMA_RAS_STATUS__MCU_DATA_ECC__SHIFT 0x2 +#define SDMA1_SDMA_RAS_STATUS__WPTR_POLL_ECC__SHIFT 0x3 +#define SDMA1_SDMA_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA1_SDMA_RAS_STATUS__INSTR_FETCH_ECC__SHIFT 0x5 +#define SDMA1_SDMA_RAS_STATUS__ATOMIC_ECC__SHIFT 0x6 +#define SDMA1_SDMA_RAS_STATUS__FRONTEND_ECC__SHIFT 0x7 +#define SDMA1_SDMA_RAS_STATUS__SRAM_ECC__SHIFT 0x10 +#define SDMA1_SDMA_RAS_STATUS__BUS_PARITY__SHIFT 0x12 +#define SDMA1_SDMA_RAS_STATUS__VMID__SHIFT 0x14 +#define SDMA1_SDMA_RAS_STATUS__VFID__SHIFT 0x18 +#define SDMA1_SDMA_RAS_STATUS__VF__SHIFT 0x1d +#define SDMA1_SDMA_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA1_SDMA_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA1_SDMA_RAS_STATUS__MCU_DATA_ECC_MASK 0x00000004L +#define SDMA1_SDMA_RAS_STATUS__WPTR_POLL_ECC_MASK 0x00000008L +#define SDMA1_SDMA_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA1_SDMA_RAS_STATUS__INSTR_FETCH_ECC_MASK 0x00000020L +#define SDMA1_SDMA_RAS_STATUS__ATOMIC_ECC_MASK 0x00000040L +#define SDMA1_SDMA_RAS_STATUS__FRONTEND_ECC_MASK 0x00000080L +#define SDMA1_SDMA_RAS_STATUS__SRAM_ECC_MASK 0x00010000L +#define SDMA1_SDMA_RAS_STATUS__BUS_PARITY_MASK 0x00040000L +#define SDMA1_SDMA_RAS_STATUS__VMID_MASK 0x00F00000L +#define SDMA1_SDMA_RAS_STATUS__VFID_MASK 0x1F000000L +#define SDMA1_SDMA_RAS_STATUS__VF_MASK 0x20000000L +//SDMA1_SDMA_POISON_INFO +#define SDMA1_SDMA_POISON_INFO__VMID__SHIFT 0x0 +#define SDMA1_SDMA_POISON_INFO__VFID__SHIFT 0x4 +#define SDMA1_SDMA_POISON_INFO__VF__SHIFT 0x9 +#define SDMA1_SDMA_POISON_INFO__VMID_MASK 0x0000000FL +#define SDMA1_SDMA_POISON_INFO__VFID_MASK 0x000001F0L +#define SDMA1_SDMA_POISON_INFO__VF_MASK 0x00000200L +//SDMA1_SDMA_MEMHUB_CNTL +#define SDMA1_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ__SHIFT 0x0 +#define SDMA1_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ_MASK 0x00000003L +//SDMA1_SDMA_QUEUE0_RB_CNTL +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE0_RB_BASE +#define SDMA1_SDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_BASE_HI +#define SDMA1_SDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE0_RB_RPTR +#define SDMA1_SDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_WPTR +#define SDMA1_SDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_IB_CNTL +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE0_IB_RPTR +#define SDMA1_SDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE0_IB_OFFSET +#define SDMA1_SDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE0_IB_BASE_LO +#define SDMA1_SDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_IB_BASE_HI +#define SDMA1_SDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_IB_SIZE +#define SDMA1_SDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE0_DOORBELL +#define SDMA1_SDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE0_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE0_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE0_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE0_PREEMPT +#define SDMA1_SDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE0_DUMMY_REG +#define SDMA1_SDMA_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE0_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE0_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE0_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MQD_CONTROL +#define SDMA1_SDMA_QUEUE0_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE0_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE0_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_CNTL +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE1_RB_BASE +#define SDMA1_SDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_BASE_HI +#define SDMA1_SDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE1_RB_RPTR +#define SDMA1_SDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_WPTR +#define SDMA1_SDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_IB_CNTL +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE1_IB_RPTR +#define SDMA1_SDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE1_IB_OFFSET +#define SDMA1_SDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE1_IB_BASE_LO +#define SDMA1_SDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_IB_BASE_HI +#define SDMA1_SDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_IB_SIZE +#define SDMA1_SDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE1_DOORBELL +#define SDMA1_SDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE1_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE1_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE1_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE1_PREEMPT +#define SDMA1_SDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE1_DUMMY_REG +#define SDMA1_SDMA_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE1_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE1_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE1_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MQD_CONTROL +#define SDMA1_SDMA_QUEUE1_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE1_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE1_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_CNTL +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE2_RB_BASE +#define SDMA1_SDMA_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_BASE_HI +#define SDMA1_SDMA_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE2_RB_RPTR +#define SDMA1_SDMA_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_WPTR +#define SDMA1_SDMA_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_IB_CNTL +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE2_IB_RPTR +#define SDMA1_SDMA_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE2_IB_OFFSET +#define SDMA1_SDMA_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE2_IB_BASE_LO +#define SDMA1_SDMA_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_IB_BASE_HI +#define SDMA1_SDMA_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_IB_SIZE +#define SDMA1_SDMA_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE2_DOORBELL +#define SDMA1_SDMA_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE2_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE2_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE2_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE2_PREEMPT +#define SDMA1_SDMA_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE2_DUMMY_REG +#define SDMA1_SDMA_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE2_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE2_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE2_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MQD_CONTROL +#define SDMA1_SDMA_QUEUE2_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE2_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE2_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_CNTL +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE3_RB_BASE +#define SDMA1_SDMA_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_BASE_HI +#define SDMA1_SDMA_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE3_RB_RPTR +#define SDMA1_SDMA_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_WPTR +#define SDMA1_SDMA_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_IB_CNTL +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE3_IB_RPTR +#define SDMA1_SDMA_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE3_IB_OFFSET +#define SDMA1_SDMA_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE3_IB_BASE_LO +#define SDMA1_SDMA_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_IB_BASE_HI +#define SDMA1_SDMA_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_IB_SIZE +#define SDMA1_SDMA_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE3_DOORBELL +#define SDMA1_SDMA_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE3_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE3_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE3_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE3_PREEMPT +#define SDMA1_SDMA_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE3_DUMMY_REG +#define SDMA1_SDMA_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE3_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE3_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE3_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MQD_CONTROL +#define SDMA1_SDMA_QUEUE3_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE3_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE3_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_CNTL +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE4_RB_BASE +#define SDMA1_SDMA_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_BASE_HI +#define SDMA1_SDMA_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE4_RB_RPTR +#define SDMA1_SDMA_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_WPTR +#define SDMA1_SDMA_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_IB_CNTL +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE4_IB_RPTR +#define SDMA1_SDMA_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE4_IB_OFFSET +#define SDMA1_SDMA_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE4_IB_BASE_LO +#define SDMA1_SDMA_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_IB_BASE_HI +#define SDMA1_SDMA_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_IB_SIZE +#define SDMA1_SDMA_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE4_DOORBELL +#define SDMA1_SDMA_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE4_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE4_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE4_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE4_PREEMPT +#define SDMA1_SDMA_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE4_DUMMY_REG +#define SDMA1_SDMA_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE4_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE4_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE4_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MQD_CONTROL +#define SDMA1_SDMA_QUEUE4_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE4_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE4_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_CNTL +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE5_RB_BASE +#define SDMA1_SDMA_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_BASE_HI +#define SDMA1_SDMA_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE5_RB_RPTR +#define SDMA1_SDMA_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_WPTR +#define SDMA1_SDMA_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_IB_CNTL +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE5_IB_RPTR +#define SDMA1_SDMA_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE5_IB_OFFSET +#define SDMA1_SDMA_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE5_IB_BASE_LO +#define SDMA1_SDMA_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_IB_BASE_HI +#define SDMA1_SDMA_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_IB_SIZE +#define SDMA1_SDMA_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE5_DOORBELL +#define SDMA1_SDMA_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE5_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE5_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE5_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE5_PREEMPT +#define SDMA1_SDMA_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE5_DUMMY_REG +#define SDMA1_SDMA_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE5_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE5_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE5_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MQD_CONTROL +#define SDMA1_SDMA_QUEUE5_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE5_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE5_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_CNTL +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE6_RB_BASE +#define SDMA1_SDMA_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_BASE_HI +#define SDMA1_SDMA_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE6_RB_RPTR +#define SDMA1_SDMA_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_WPTR +#define SDMA1_SDMA_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_IB_CNTL +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE6_IB_RPTR +#define SDMA1_SDMA_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE6_IB_OFFSET +#define SDMA1_SDMA_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE6_IB_BASE_LO +#define SDMA1_SDMA_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_IB_BASE_HI +#define SDMA1_SDMA_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_IB_SIZE +#define SDMA1_SDMA_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE6_DOORBELL +#define SDMA1_SDMA_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE6_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE6_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE6_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE6_PREEMPT +#define SDMA1_SDMA_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE6_DUMMY_REG +#define SDMA1_SDMA_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE6_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE6_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE6_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MQD_CONTROL +#define SDMA1_SDMA_QUEUE6_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE6_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE6_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_CNTL +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE7_RB_BASE +#define SDMA1_SDMA_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_BASE_HI +#define SDMA1_SDMA_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE7_RB_RPTR +#define SDMA1_SDMA_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_WPTR +#define SDMA1_SDMA_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_IB_CNTL +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE7_IB_RPTR +#define SDMA1_SDMA_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE7_IB_OFFSET +#define SDMA1_SDMA_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE7_IB_BASE_LO +#define SDMA1_SDMA_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_IB_BASE_HI +#define SDMA1_SDMA_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_IB_SIZE +#define SDMA1_SDMA_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE7_DOORBELL +#define SDMA1_SDMA_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE7_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE7_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE7_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE7_PREEMPT +#define SDMA1_SDMA_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE7_DUMMY_REG +#define SDMA1_SDMA_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE7_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE7_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE7_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MQD_CONTROL +#define SDMA1_SDMA_QUEUE7_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE7_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE7_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_CNTL +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE8_RB_BASE +#define SDMA1_SDMA_QUEUE8_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_BASE_HI +#define SDMA1_SDMA_QUEUE8_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE8_RB_RPTR +#define SDMA1_SDMA_QUEUE8_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE8_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_WPTR +#define SDMA1_SDMA_QUEUE8_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE8_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_IB_CNTL +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE8_IB_RPTR +#define SDMA1_SDMA_QUEUE8_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE8_IB_OFFSET +#define SDMA1_SDMA_QUEUE8_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE8_IB_BASE_LO +#define SDMA1_SDMA_QUEUE8_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_IB_BASE_HI +#define SDMA1_SDMA_QUEUE8_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_IB_SIZE +#define SDMA1_SDMA_QUEUE8_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE8_DOORBELL +#define SDMA1_SDMA_QUEUE8_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE8_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE8_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE8_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE8_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE8_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE8_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE8_PREEMPT +#define SDMA1_SDMA_QUEUE8_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE8_DUMMY_REG +#define SDMA1_SDMA_QUEUE8_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE8_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE8_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE8_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MQD_CONTROL +#define SDMA1_SDMA_QUEUE8_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE8_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE8_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_CNTL +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE9_RB_BASE +#define SDMA1_SDMA_QUEUE9_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_BASE_HI +#define SDMA1_SDMA_QUEUE9_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE9_RB_RPTR +#define SDMA1_SDMA_QUEUE9_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE9_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_WPTR +#define SDMA1_SDMA_QUEUE9_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE9_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_IB_CNTL +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE9_IB_RPTR +#define SDMA1_SDMA_QUEUE9_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE9_IB_OFFSET +#define SDMA1_SDMA_QUEUE9_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE9_IB_BASE_LO +#define SDMA1_SDMA_QUEUE9_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_IB_BASE_HI +#define SDMA1_SDMA_QUEUE9_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_IB_SIZE +#define SDMA1_SDMA_QUEUE9_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE9_DOORBELL +#define SDMA1_SDMA_QUEUE9_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE9_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE9_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE9_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE9_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE9_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE9_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE9_PREEMPT +#define SDMA1_SDMA_QUEUE9_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE9_DUMMY_REG +#define SDMA1_SDMA_QUEUE9_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE9_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE9_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE9_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MQD_CONTROL +#define SDMA1_SDMA_QUEUE9_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE9_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE9_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec:1 +//SDMA1_SDMA_VM_CTX_LO +#define SDMA1_SDMA_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_VM_CTX_HI +#define SDMA1_SDMA_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_ACTIVE_FCN_ID +#define SDMA1_SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x7 +#define SDMA1_SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x8 +#define SDMA1_SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define SDMA1_SDMA_ACTIVE_FCN_ID__VF_MASK 0x00000080L +#define SDMA1_SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0xFFFFFF00L +//SDMA1_SDMA_VM_CTX_CNTL +#define SDMA1_SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_PHY__SHIFT 0x8 +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_MTYPE__SHIFT 0xa +#define SDMA1_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA1_SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_PHY_MASK 0x00000300L +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_MTYPE_MASK 0x00000C00L +#define SDMA1_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE_MASK 0x00010000L +//SDMA1_SDMA_VIRT_RESET_REQ +#define SDMA1_SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_SDMA_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL +#define SDMA1_SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA1_SDMA_CONTEXT_REG_TYPE0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL__SHIFT 0x0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE__SHIFT 0x1 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR__SHIFT 0x3 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI__SHIFT 0x4 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR__SHIFT 0x5 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI__SHIFT 0x6 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO__SHIFT 0x7 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL__SHIFT 0x9 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR__SHIFT 0xa +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET__SHIFT 0xb +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO__SHIFT 0xc +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI__SHIFT 0xd +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE__SHIFT 0xe +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL__SHIFT 0xf +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG__SHIFT 0x10 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET__SHIFT 0x11 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO__SHIFT 0x12 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI__SHIFT 0x13 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL__SHIFT 0x14 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN__SHIFT 0x15 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT__SHIFT 0x16 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG__SHIFT 0x17 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__SHIFT 0x18 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__SHIFT 0x19 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL__SHIFT 0x1a +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE__SHIFT 0x1b +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SHIFT 0x1e +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL__SHIFT 0x1f +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL_MASK 0x00000001L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_MASK 0x00000002L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI_MASK 0x00000004L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_MASK 0x00000008L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI_MASK 0x00000010L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_MASK 0x00000020L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI_MASK 0x00000040L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO_MASK 0x00000080L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL_MASK 0x00000200L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR_MASK 0x00000400L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET_MASK 0x00000800L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO_MASK 0x00001000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI_MASK 0x00002000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE_MASK 0x00004000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_MASK 0x00008000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG_MASK 0x00010000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET_MASK 0x00020000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO_MASK 0x00040000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI_MASK 0x00080000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL_MASK 0x00100000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN_MASK 0x00200000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT_MASK 0x00400000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG_MASK 0x00800000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_MASK 0x01000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_MASK 0x02000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL_MASK 0x04000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE_MASK 0x08000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_MASK 0x40000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL_MASK 0x80000000L +//SDMA1_SDMA_CONTEXT_REG_TYPE1 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9__SHIFT 0x9 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10__SHIFT 0xa +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO__SHIFT 0xb +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI__SHIFT 0xc +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD__SHIFT 0xd +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO__SHIFT 0xe +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI__SHIFT 0xf +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL__SHIFT 0x10 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1__SHIFT 0x12 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2__SHIFT 0x13 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x14 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9_MASK 0x00000200L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10_MASK 0x00000400L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO_MASK 0x00000800L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI_MASK 0x00001000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD_MASK 0x00002000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO_MASK 0x00004000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI_MASK 0x00008000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL_MASK 0x00010000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1_MASK 0x00040000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2_MASK 0x00080000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFF00000L +//SDMA1_SDMA_CONTEXT_REG_TYPE2 +#define SDMA1_SDMA_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_REG_TYPE0 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_DEC_START__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CNTL__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE0__RESERVED__SHIFT 0x15 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_DEC_START_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CNTL_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE0__RESERVED_MASK 0xFFE00000L +//SDMA1_SDMA_PUB_REG_TYPE1 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH__SHIFT 0x2 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG__SHIFT 0x4 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_CNTL1__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG__SHIFT 0x7 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE__SHIFT 0x8 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0__SHIFT 0x9 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1__SHIFT 0xa +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL__SHIFT 0xb +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ID__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_VERSION__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG__SHIFT 0x10 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL__SHIFT 0x11 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL__SHIFT 0x12 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO__SHIFT 0x13 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI__SHIFT 0x14 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL__SHIFT 0x15 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL__SHIFT 0x16 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL__SHIFT 0x17 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK__SHIFT 0x18 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT__SHIFT 0x19 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE__SHIFT 0x1a +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN__SHIFT 0x1b +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER__SHIFT 0x1c +#define SDMA1_SDMA_PUB_REG_TYPE1__RESERVED__SHIFT 0x1d +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH_MASK 0x00000004L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG_MASK 0x00000010L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_CNTL1_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG_MASK 0x00000080L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_MASK 0x00000100L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0_MASK 0x00000200L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1_MASK 0x00000400L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL_MASK 0x00000800L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ID_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_VERSION_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG_MASK 0x00010000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL_MASK 0x00020000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL_MASK 0x00040000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO_MASK 0x00080000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI_MASK 0x00100000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL_MASK 0x00200000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL_MASK 0x00400000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL_MASK 0x00800000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK_MASK 0x01000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT_MASK 0x02000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE_MASK 0x04000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN_MASK 0x08000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER_MASK 0x10000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__RESERVED_MASK 0xE0000000L +//SDMA1_SDMA_PUB_REG_TYPE2 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS__SHIFT 0x2 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1__SHIFT 0x4 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1__SHIFT 0x7 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0__SHIFT 0x8 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1__SHIFT 0x9 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2__SHIFT 0xa +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG__SHIFT 0xb +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2__SHIFT 0x10 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3__SHIFT 0x11 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER__SHIFT 0x12 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL__SHIFT 0x13 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL__SHIFT 0x14 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG__SHIFT 0x15 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS__SHIFT 0x17 +#define SDMA1_SDMA_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS_MASK 0x00000004L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1_MASK 0x00000010L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1_MASK 0x00000080L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0_MASK 0x00000100L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1_MASK 0x00000200L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2_MASK 0x00000400L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG_MASK 0x00000800L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2_MASK 0x00010000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3_MASK 0x00020000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER_MASK 0x00040000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL_MASK 0x00080000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL_MASK 0x00100000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG_MASK 0x00200000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS_MASK 0x00800000L +#define SDMA1_SDMA_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA1_SDMA_PUB_REG_TYPE3 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI__SHIFT 0x4 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG__SHIFT 0x7 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA__SHIFT 0x8 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR__SHIFT 0x9 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL__SHIFT 0xa +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG__SHIFT 0xb +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS__SHIFT 0x10 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO__SHIFT 0x11 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL__SHIFT 0x12 +#define SDMA1_SDMA_PUB_REG_TYPE3__RESERVED__SHIFT 0x13 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI_MASK 0x00000010L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG_MASK 0x00000080L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA_MASK 0x00000100L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR_MASK 0x00000200L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL_MASK 0x00000400L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG_MASK 0x00000800L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS_MASK 0x00010000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO_MASK 0x00020000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL_MASK 0x00040000L +#define SDMA1_SDMA_PUB_REG_TYPE3__RESERVED_MASK 0xFFF80000L +//SDMA1_SDMA_VM_CNTL +#define SDMA1_SDMA_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_SDMA_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA1_SDMA_MCU_CNTL +#define SDMA1_SDMA_MCU_CNTL__HALT__SHIFT 0x0 +#define SDMA1_SDMA_MCU_CNTL__RESET__SHIFT 0x1 +#define SDMA1_SDMA_MCU_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA1_SDMA_MCU_CNTL__HALT_MASK 0x00000001L +#define SDMA1_SDMA_MCU_CNTL__RESET_MASK 0x00000002L +#define SDMA1_SDMA_MCU_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +//SDMA1_SDMA_IC_BASE_LO +#define SDMA1_SDMA_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define SDMA1_SDMA_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//SDMA1_SDMA_IC_BASE_HI +#define SDMA1_SDMA_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define SDMA1_SDMA_IC_BASE_HI__IC_BASE_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_IC_BASE_CNTL +#define SDMA1_SDMA_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_IC_BASE_CNTL__MTYPE__SHIFT 0x4 +#define SDMA1_SDMA_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define SDMA1_SDMA_IC_BASE_CNTL__TEMPORAL_HINT__SHIFT 0x18 +#define SDMA1_SDMA_IC_BASE_CNTL__SCOPE__SHIFT 0x1c +#define SDMA1_SDMA_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define SDMA1_SDMA_IC_BASE_CNTL__MTYPE_MASK 0x00000030L +#define SDMA1_SDMA_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define SDMA1_SDMA_IC_BASE_CNTL__TEMPORAL_HINT_MASK 0x07000000L +#define SDMA1_SDMA_IC_BASE_CNTL__SCOPE_MASK 0x30000000L +//SDMA1_SDMA_IC_OP_CNTL +#define SDMA1_SDMA_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define SDMA1_SDMA_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define SDMA1_SDMA_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define SDMA1_SDMA_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define SDMA1_SDMA_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define SDMA1_SDMA_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//SDMA1_SDMA_IC_CNTL +#define SDMA1_SDMA_IC_CNTL__CID_SEL__SHIFT 0x0 +#define SDMA1_SDMA_IC_CNTL__GPA__SHIFT 0x2 +#define SDMA1_SDMA_IC_CNTL__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define SDMA1_SDMA_IC_CNTL__AUTO_PRIME_ICACHE__SHIFT 0x5 +#define SDMA1_SDMA_IC_CNTL__CID_SEL_MASK 0x00000001L +#define SDMA1_SDMA_IC_CNTL__GPA_MASK 0x0000000CL +#define SDMA1_SDMA_IC_CNTL__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define SDMA1_SDMA_IC_CNTL__AUTO_PRIME_ICACHE_MASK 0x00000020L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec:1 +//SDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET +#define SDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA__SHIFT 0x0 +#define SDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec:1 +//SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA1_SDMA_PERFCNT_MISC_CNTL +#define SDMA1_SDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA1_SDMA_PERFCOUNTER0_SELECT +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER0_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER1_SELECT +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER1_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER2_SELECT +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER2_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER3_SELECT +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER3_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER4_SELECT +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER4_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER5_SELECT +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER5_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec:1 +//SDMA1_SDMA_PERFCNT_PERFCOUNTER_LO +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA1_SDMA_PERFCOUNTER0_LO +#define SDMA1_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER0_HI +#define SDMA1_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER1_LO +#define SDMA1_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER1_HI +#define SDMA1_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER2_LO +#define SDMA1_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER2_HI +#define SDMA1_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER3_LO +#define SDMA1_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER3_HI +#define SDMA1_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER4_LO +#define SDMA1_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER4_HI +#define SDMA1_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER5_LO +#define SDMA1_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER5_HI +#define SDMA1_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec:1 +//SDMA1_GFX_ICG_SDMA_CTRL +#define SDMA1_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x1 +#define SDMA1_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x2 +#define SDMA1_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x3 +#define SDMA1_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x4 +#define SDMA1_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x5 +#define SDMA1_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x6 +#define SDMA1_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x7 +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x8 +#define SDMA1_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x9 +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xa +#define SDMA1_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xb +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xc +#define SDMA1_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xd +#define SDMA1_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xe +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xf +#define SDMA1_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x10 +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x11 +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x12 +#define SDMA1_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST__SHIFT 0x18 +#define SDMA1_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000002L +#define SDMA1_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000004L +#define SDMA1_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000008L +#define SDMA1_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000010L +#define SDMA1_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000020L +#define SDMA1_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000040L +#define SDMA1_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000080L +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000100L +#define SDMA1_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000200L +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000400L +#define SDMA1_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000800L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00001000L +#define SDMA1_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00002000L +#define SDMA1_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00004000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00008000L +#define SDMA1_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00010000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00020000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00040000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbmdec +//GRBM_CNTL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__SED_READ_TIMEOUT__SHIFT 0x10 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x0000FFFFL +#define GRBM_CNTL__SED_READ_TIMEOUT_MASK 0x0FFF0000L +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBM_SKEW_CNTL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L +//GRBM_STATUS2 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf +#define GRBM_STATUS2__CANE_BUSY__SHIFT 0x10 +#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 +#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT 0x13 +#define GRBM_STATUS2__CANE_LINK_BUSY__SHIFT 0x14 +#define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15 +#define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16 +#define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x1a +#define GRBM_STATUS2__TCP_BUSY__SHIFT 0x1b +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L +#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L +#define GRBM_STATUS2__CANE_BUSY_MASK 0x00010000L +#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L +#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK 0x00080000L +#define GRBM_STATUS2__CANE_LINK_BUSY_MASK 0x00100000L +#define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L +#define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L +#define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L +#define GRBM_STATUS2__RLC_BUSY_MASK 0x04000000L +#define GRBM_STATUS2__TCP_BUSY_MASK 0x08000000L +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +//GRBM_PWR_CNTL +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L +//GRBM_STATUS +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__SDMA_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__GE_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__ANY_ACTIVE__SHIFT 0x1b +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS__SDMA_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__GE_BUSY_MASK 0x00200000L +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__ANY_ACTIVE_MASK 0x08000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +//GRBM_STATUS_SE0 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE0__GL1XCC_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE0__WGS_BUSY__SHIFT 0x14 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE0__GL1XCC_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE0__WGS_BUSY_MASK 0x00100000L +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE1 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE1__GL1XCC_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE1__WGS_BUSY__SHIFT 0x14 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE1__GL1XCC_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE1__WGS_BUSY_MASK 0x00100000L +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS3 +#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5 +#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7 +#define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS3__CH_BUSY__SHIFT 0xe +#define GRBM_STATUS3__GLARB_BUSY__SHIFT 0xf +#define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10 +#define GRBM_STATUS3__WGS_BUSY__SHIFT 0x11 +#define GRBM_STATUS3__GL1XCC_BUSY__SHIFT 0x1b +#define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e +#define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f +#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L +#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L +#define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L +#define GRBM_STATUS3__GLARB_BUSY_MASK 0x00008000L +#define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L +#define GRBM_STATUS3__WGS_BUSY_MASK 0x00020000L +#define GRBM_STATUS3__GL1XCC_BUSY_MASK 0x08000000L +#define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L +#define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L +//GRBM_SOFT_RESET +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT 0xf +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_SOFT_RESET__SOFT_RESET_CANE__SHIFT 0x15 +#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17 +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK 0x00008000L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L +#define GRBM_SOFT_RESET__SOFT_RESET_CANE_MASK 0x00200000L +#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L +//GRBM_FAO_CNT +#define GRBM_FAO_CNT__GRBM_FAO_CNT__SHIFT 0x0 +#define GRBM_FAO_CNT__GRBM_FAO_CNT_MASK 0x0000FFFFL +//GRBM_GFX_CLKEN_CNTL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBM_WAIT_IDLE_CLOCKS +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL +//GRBM_READ_ERROR +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBM_READ_ERROR2 +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT 0x9 +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT 0xa +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT 0xb +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT 0xc +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT 0xd +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT 0xe +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK 0x00000200L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK 0x00000400L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK 0x00000800L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK 0x00001000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK 0x00002000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK 0x00004000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +//GRBM_INT_CNTL +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +//GRBM_TRAP_OP +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_OP__RW_MASK 0x00000001L +//GRBM_TRAP_ADDR +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_ADDR_MSK +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_WD +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL +//GRBM_TRAP_WD_MSK +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL +//GRBM_DSM_BYPASS +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L +//GRBM_WRITE_ERROR +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x7 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000003CL +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x00000F80L +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L +#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L +//GRBM_IOV_ERROR_FIFO +#define GRBM_IOV_ERROR_FIFO__IOV_ADDR__SHIFT 0x0 +#define GRBM_IOV_ERROR_FIFO__IOV_VFID__SHIFT 0x12 +#define GRBM_IOV_ERROR_FIFO__IOV_SSRCID__SHIFT 0x18 +#define GRBM_IOV_ERROR_FIFO__IOV_OP__SHIFT 0x1c +#define GRBM_IOV_ERROR_FIFO__IOV_VF__SHIFT 0x1d +#define GRBM_IOV_ERROR_FIFO__FIFO_OVERFLOW__SHIFT 0x1e +#define GRBM_IOV_ERROR_FIFO__READ_VALID__SHIFT 0x1f +#define GRBM_IOV_ERROR_FIFO__IOV_ADDR_MASK 0x0003FFFFL +#define GRBM_IOV_ERROR_FIFO__IOV_VFID_MASK 0x00FC0000L +#define GRBM_IOV_ERROR_FIFO__IOV_SSRCID_MASK 0x0F000000L +#define GRBM_IOV_ERROR_FIFO__IOV_OP_MASK 0x10000000L +#define GRBM_IOV_ERROR_FIFO__IOV_VF_MASK 0x20000000L +#define GRBM_IOV_ERROR_FIFO__FIFO_OVERFLOW_MASK 0x40000000L +#define GRBM_IOV_ERROR_FIFO__READ_VALID_MASK 0x80000000L +//GRBM_CHIP_REVISION +#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL +//GRBM_RSMU_CFG +#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 +#define GRBM_RSMU_CFG__QOS__SHIFT 0xc +#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 +#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11 +#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL +#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L +#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L +#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L +//GRBM_IH_CREDIT +#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//GRBM_PWR_CNTL2 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L +//GRBM_UTCL2_INVAL_RANGE_START +#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL +//GRBM_UTCL2_INVAL_RANGE_END +#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL +//GRBM_RSMU_READ_ERROR +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L +//GRBM_INVALID_PIPE +#define GRBM_INVALID_PIPE__ADDR__SHIFT 0x2 +#define GRBM_INVALID_PIPE__PIPEID__SHIFT 0x14 +#define GRBM_INVALID_PIPE__MEID__SHIFT 0x16 +#define GRBM_INVALID_PIPE__QUEUEID__SHIFT 0x18 +#define GRBM_INVALID_PIPE__SSRCID__SHIFT 0x1b +#define GRBM_INVALID_PIPE__INVALID_PIPE__SHIFT 0x1f +#define GRBM_INVALID_PIPE__ADDR_MASK 0x000FFFFCL +#define GRBM_INVALID_PIPE__PIPEID_MASK 0x00300000L +#define GRBM_INVALID_PIPE__MEID_MASK 0x00C00000L +#define GRBM_INVALID_PIPE__QUEUEID_MASK 0x07000000L +#define GRBM_INVALID_PIPE__SSRCID_MASK 0x78000000L +#define GRBM_INVALID_PIPE__INVALID_PIPE_MASK 0x80000000L +//GRBM_FENCE_RANGE0 +#define GRBM_FENCE_RANGE0__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE0__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L +//GRBM_FENCE_RANGE1 +#define GRBM_FENCE_RANGE1__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE1__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L +//GRBM_CHICKEN_BITS0 +#define GRBM_CHICKEN_BITS0__GRBM_SDMA0_reg_fgcg_chick_bit__SHIFT 0x0 +#define GRBM_CHICKEN_BITS0__GRBM_SDMA1_reg_fgcg_chick_bit__SHIFT 0x1 +#define GRBM_CHICKEN_BITS0__GRBM_CPG_reg_fgcg_chick_bit__SHIFT 0x2 +#define GRBM_CHICKEN_BITS0__GRBM_CPF_reg_fgcg_chick_bit__SHIFT 0x3 +#define GRBM_CHICKEN_BITS0__GRBM_UTCL2_reg_fgcg_chick_bit__SHIFT 0x5 +#define GRBM_CHICKEN_BITS0__GRBM_TARG0_mcd_reg_clken_chick_bit__SHIFT 0x6 +#define GRBM_CHICKEN_BITS0__GRBM_TARG1_targvf_reg_clken_chick_bit__SHIFT 0x7 +#define GRBM_CHICKEN_BITS0__GRBM_TARG2_targvf_reg_clken_chick_bit__SHIFT 0x8 +#define GRBM_CHICKEN_BITS0__GRBM_TARG3_targvf_reg_clken_chick_bit__SHIFT 0x9 +#define GRBM_CHICKEN_BITS0__GRBM_TARG4_targvf_reg_clken_chick_bit__SHIFT 0xa +#define GRBM_CHICKEN_BITS0__GRBM_TARG5_reg_clken_chick_bit__SHIFT 0xb +#define GRBM_CHICKEN_BITS0__GRBM_TARG6_reg_clken_chick_bit__SHIFT 0xc +#define GRBM_CHICKEN_BITS0__GRBM_TARG7_reg_clken_chick_bit__SHIFT 0xd +#define GRBM_CHICKEN_BITS0__GRBM_TARG8_reg_clken_chick_bit__SHIFT 0xe +#define GRBM_CHICKEN_BITS0__GRBM_TARG9_reg_clken_chick_bit__SHIFT 0xf +#define GRBM_CHICKEN_BITS0__GRBM_TARG10_reg_clken_chick_bit__SHIFT 0x10 +#define GRBM_CHICKEN_BITS0__GRBM_TARG11_reg_clken_chick_bit__SHIFT 0x11 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE0_reg_clken_chick_bit__SHIFT 0x12 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE1_reg_clken_chick_bit__SHIFT 0x13 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE2_reg_clken_chick_bit__SHIFT 0x14 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE3_reg_clken_chick_bit__SHIFT 0x15 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE4_reg_clken_chick_bit__SHIFT 0x16 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE5_reg_clken_chick_bit__SHIFT 0x17 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE6_reg_clken_chick_bit__SHIFT 0x18 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE7_reg_clken_chick_bit__SHIFT 0x19 +#define GRBM_CHICKEN_BITS0__GRBM_CPC_reg_clken_chick_bit__SHIFT 0x1c +#define GRBM_CHICKEN_BITS0__GRBM_RLC_reg_clken_chick_bit__SHIFT 0x1f +#define GRBM_CHICKEN_BITS0__GRBM_SDMA0_reg_fgcg_chick_bit_MASK 0x00000001L +#define GRBM_CHICKEN_BITS0__GRBM_SDMA1_reg_fgcg_chick_bit_MASK 0x00000002L +#define GRBM_CHICKEN_BITS0__GRBM_CPG_reg_fgcg_chick_bit_MASK 0x00000004L +#define GRBM_CHICKEN_BITS0__GRBM_CPF_reg_fgcg_chick_bit_MASK 0x00000008L +#define GRBM_CHICKEN_BITS0__GRBM_UTCL2_reg_fgcg_chick_bit_MASK 0x00000020L +#define GRBM_CHICKEN_BITS0__GRBM_TARG0_mcd_reg_clken_chick_bit_MASK 0x00000040L +#define GRBM_CHICKEN_BITS0__GRBM_TARG1_targvf_reg_clken_chick_bit_MASK 0x00000080L +#define GRBM_CHICKEN_BITS0__GRBM_TARG2_targvf_reg_clken_chick_bit_MASK 0x00000100L +#define GRBM_CHICKEN_BITS0__GRBM_TARG3_targvf_reg_clken_chick_bit_MASK 0x00000200L +#define GRBM_CHICKEN_BITS0__GRBM_TARG4_targvf_reg_clken_chick_bit_MASK 0x00000400L +#define GRBM_CHICKEN_BITS0__GRBM_TARG5_reg_clken_chick_bit_MASK 0x00000800L +#define GRBM_CHICKEN_BITS0__GRBM_TARG6_reg_clken_chick_bit_MASK 0x00001000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG7_reg_clken_chick_bit_MASK 0x00002000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG8_reg_clken_chick_bit_MASK 0x00004000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG9_reg_clken_chick_bit_MASK 0x00008000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG10_reg_clken_chick_bit_MASK 0x00010000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG11_reg_clken_chick_bit_MASK 0x00020000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE0_reg_clken_chick_bit_MASK 0x00040000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE1_reg_clken_chick_bit_MASK 0x00080000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE2_reg_clken_chick_bit_MASK 0x00100000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE3_reg_clken_chick_bit_MASK 0x00200000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE4_reg_clken_chick_bit_MASK 0x00400000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE5_reg_clken_chick_bit_MASK 0x00800000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE6_reg_clken_chick_bit_MASK 0x01000000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE7_reg_clken_chick_bit_MASK 0x02000000L +#define GRBM_CHICKEN_BITS0__GRBM_CPC_reg_clken_chick_bit_MASK 0x10000000L +#define GRBM_CHICKEN_BITS0__GRBM_RLC_reg_clken_chick_bit_MASK 0x80000000L +//GRBM_CHICKEN_BITS1 +#define GRBM_CHICKEN_BITS1__GRBM_UTCL2MCA_reg_clken_chick_bit__SHIFT 0xd +#define GRBM_CHICKEN_BITS1__GRBM_MCA0_reg_clken_chick_bit__SHIFT 0xe +#define GRBM_CHICKEN_BITS1__GRBM_MCA1_reg_clken_chick_bit__SHIFT 0xf +#define GRBM_CHICKEN_BITS1__GRBM_MCA2_reg_clken_chick_bit__SHIFT 0x10 +#define GRBM_CHICKEN_BITS1__GRBM_MCA3_reg_clken_chick_bit__SHIFT 0x11 +#define GRBM_CHICKEN_BITS1__GRBM_MCA4_reg_clken_chick_bit__SHIFT 0x12 +#define GRBM_CHICKEN_BITS1__GRBM_MCA5_reg_clken_chick_bit__SHIFT 0x13 +#define GRBM_CHICKEN_BITS1__GRBM_MCA6_reg_clken_chick_bit__SHIFT 0x14 +#define GRBM_CHICKEN_BITS1__GRBM_MCA7_reg_clken_chick_bit__SHIFT 0x15 +#define GRBM_CHICKEN_BITS1__GRBM_MCA8_reg_clken_chick_bit__SHIFT 0x16 +#define GRBM_CHICKEN_BITS1__GRBM_MCA9_reg_clken_chick_bit__SHIFT 0x17 +#define GRBM_CHICKEN_BITS1__GRBM_MCA10_reg_clken_chick_bit__SHIFT 0x18 +#define GRBM_CHICKEN_BITS1__GRBM_UTCL2MCA_reg_clken_chick_bit_MASK 0x00002000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA0_reg_clken_chick_bit_MASK 0x00004000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA1_reg_clken_chick_bit_MASK 0x00008000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA2_reg_clken_chick_bit_MASK 0x00010000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA3_reg_clken_chick_bit_MASK 0x00020000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA4_reg_clken_chick_bit_MASK 0x00040000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA5_reg_clken_chick_bit_MASK 0x00080000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA6_reg_clken_chick_bit_MASK 0x00100000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA7_reg_clken_chick_bit_MASK 0x00200000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA8_reg_clken_chick_bit_MASK 0x00400000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA9_reg_clken_chick_bit_MASK 0x00800000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA10_reg_clken_chick_bit_MASK 0x01000000L +//CC_GC_FULL_SA_UNIT_DISABLE +#define CC_GC_FULL_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define CC_GC_FULL_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x03FFFF00L +//GRBM_SCRATCH_REG0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG1 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG2 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG3 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG4 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG5 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG6 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG7 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//VIOLATION_DATA_ASYNC_VF_PROG +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L +//GRBM_INTF_CNTL +#define GRBM_INTF_CNTL__GRBM_BRIDGE_DISABLE__SHIFT 0x0 +#define GRBM_INTF_CNTL__GRBM_BRIDGE_DISABLE_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpdec +//CP_CPC_DEBUG_CNTL +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_CPC_DEBUG_DATA +#define CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_CPF_DEBUG_CNTL +#define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_CPF_DEBUG_DATA +#define CP_CPF_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_CPF_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_CPC_STATUS +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf +#define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10 +#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 +#define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12 +#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 +#define CP_CPC_STATUS__MES_DATA_CACHE_BUSY__SHIFT 0x14 +#define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY__SHIFT 0x15 +#define CP_CPC_STATUS__CANEIU_BUSY__SHIFT 0x16 +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L +#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L +#define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L +#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L +#define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L +#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L +#define CP_CPC_STATUS__MES_DATA_CACHE_BUSY_MASK 0x00100000L +#define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY_MASK 0x00200000L +#define CP_CPC_STATUS__CANEIU_BUSY_MASK 0x00400000L +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x20000000L +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x40000000L +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L +//CP_CPC_BUSY_STAT +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//CP_CPC_STALLED_STAT1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x7 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000080L +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L +//CP_CPF_STATUS +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12 +#define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13 +#define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14 +#define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15 +#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16 +#define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17 +#define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L +#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L +#define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L +#define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L +#define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L +#define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L +#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L +#define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L +#define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L +//CP_CPF_BUSY_STAT +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L +#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L +#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L +//CP_CPF_STALLED_STAT1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb +#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc +#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L +#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L +#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L +//CP_CPC_BUSY_STAT2 +#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT2__MES_PIPE0_DC_BUSY__SHIFT 0xe +#define CP_CPC_BUSY_STAT2__MES_PIPE1_DC_BUSY__SHIFT 0xf +#define CP_CPC_BUSY_STAT2__MES_PIPE2_DC_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT2__MES_PIPE3_DC_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE0_DC_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE1_DC_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE2_DC_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE3_DC_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT2__MES_PIPE0_DC_BUSY_MASK 0x00004000L +#define CP_CPC_BUSY_STAT2__MES_PIPE1_DC_BUSY_MASK 0x00008000L +#define CP_CPC_BUSY_STAT2__MES_PIPE2_DC_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT2__MES_PIPE3_DC_BUSY_MASK 0x00020000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE0_DC_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE1_DC_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE2_DC_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE3_DC_BUSY_MASK 0x00200000L +//CP_CPC_GRBM_FREE_COUNT +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +//CP_CPC_PRIV_VIOLATION_ADDR +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT 0x1 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x2 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK 0x00000001L +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK 0x00000002L +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0xFFFFFFFCL +//CP_CPC_PRIV_VIOLATION_ADDR_HI +#define CP_CPC_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR_MASK 0x000000FFL +//CP_MEC_ME1_HEADER_DUMP +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_CPC_SCRATCH_INDEX +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_CPC_SCRATCH_DATA +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_CPF_GRBM_FREE_COUNT +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L +//CP_CPF_BUSY_STAT2 +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT2__MES_UNMAPPED_DOORBELL_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT2__MES_UNMAPPED_DOORBELL_BUSY_MASK 0x80000000L +//CP_CPC_HALT_HYST_COUNT +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//CP_STALLED_STAT3 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L +#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L +//CP_STALLED_STAT1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT 0x4 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT 0x5 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK 0x00000010L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK 0x00000020L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L +//CP_STALLED_STAT2 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT 0x15 +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK 0x00200000L +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +//CP_BUSY_STAT +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__PFP_DATA_CACHE_BUSY__SHIFT 0x1 +#define CP_BUSY_STAT__ME_DATA_CACHE_BUSY__SHIFT 0x2 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_BUSY_STAT__PFP_PIPE0_DC_BUSY__SHIFT 0x17 +#define CP_BUSY_STAT__ME_PIPE0_DC_BUSY__SHIFT 0x18 +#define CP_BUSY_STAT__PFP_PIPE1_DC_BUSY__SHIFT 0x19 +#define CP_BUSY_STAT__ME_PIPE1_DC_BUSY__SHIFT 0x1a +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__PFP_DATA_CACHE_BUSY_MASK 0x00000002L +#define CP_BUSY_STAT__ME_DATA_CACHE_BUSY_MASK 0x00000004L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +#define CP_BUSY_STAT__PFP_PIPE0_DC_BUSY_MASK 0x00800000L +#define CP_BUSY_STAT__ME_PIPE0_DC_BUSY_MASK 0x01000000L +#define CP_BUSY_STAT__PFP_PIPE1_DC_BUSY_MASK 0x02000000L +#define CP_BUSY_STAT__ME_PIPE1_DC_BUSY_MASK 0x04000000L +//CP_STAT +#define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5 +#define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6 +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__GCRIU_BUSY__SHIFT 0x19 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L +#define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__GCRIU_BUSY_MASK 0x02000000L +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +//CP_ME_HEADER_DUMP +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_HEADER_DUMP +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_GRBM_FREE_COUNT +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L +//CP_PFP_INSTR_PNTR +#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_ME_INSTR_PNTR +#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CSF_STAT +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L +//CP_CNTX_STAT +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +//CP_ME_PREEMPTION +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L +//CP_RB0_RPTR +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L +//CP_RB_WPTR_POLL_CNTL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//CP_ROQ1_THRESHOLDS +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L +//CP_ROQ2_THRESHOLDS +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L +//CP_STQ_THRESHOLDS +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L +//CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L +//CP_ROQ_AVAIL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L +//CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000003FFL +//CP_ROQ2_AVAIL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL +#define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L +//CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL +//CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L +//CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL +//CP_ROQ_RB_STAT +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L +//CP_ROQ_IB1_STAT +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L +//CP_ROQ_IB2_STAT +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L +//CP_STQ_STAT +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL +//CP_STQ_WR_STAT +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL +//CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L +//CP_ROQ3_THRESHOLDS +#define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0 +#define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa +#define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL +#define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L +//CP_ROQ_DB_STAT +#define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0 +#define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10 +#define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL +#define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L +//CP_INT_STAT_DEBUG +#define CP_INT_STAT_DEBUG__RESUME_INT_ASSERTED__SHIFT 0x8 +#define CP_INT_STAT_DEBUG__SUSPEND_INT_ASSERTED__SHIFT 0x9 +#define CP_INT_STAT_DEBUG__DMA_WATCH_INT_ASSERTED__SHIFT 0xa +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_INT_STAT_DEBUG__FUE_INT_STATUS_DEBUG__SHIFT 0xf +#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_INT_STAT_DEBUG__RESUME_INT_ASSERTED_MASK 0x00000100L +#define CP_INT_STAT_DEBUG__SUSPEND_INT_ASSERTED_MASK 0x00000200L +#define CP_INT_STAT_DEBUG__DMA_WATCH_INT_ASSERTED_MASK 0x00000400L +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_INT_STAT_DEBUG__FUE_INT_STATUS_DEBUG_MASK 0x00008000L +#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CP_DEBUG_CNTL +#define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_DEBUG_DATA +#define CP_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_PRIV_VIOLATION_ADDR +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT 0x1 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x2 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK 0x00000001L +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK 0x00000002L +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0xFFFFFFFCL +//CP_PRIV_VIOLATION_ADDR_HI +#define CP_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR_HI__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR_HI_MASK 0x000000FFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_padec +//VGT_DMA_DATA_FIFO_DEPTH +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL +//VGT_DMA_REQ_FIFO_DEPTH +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL +//VGT_DRAW_INIT_FIFO_DEPTH +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL +//VGT_MC_LAT_CNTL +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL +//IA_UTCL1_STATUS_2 +#define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS_2__FAULT_VMID__SHIFT 0x4 +#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS_2__FAULT_INSTANCEID__SHIFT 0xe +#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS_2__RETRY_INSTANCEID__SHIFT 0x16 +#define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS_2__PRT_INSTANCEID__SHIFT 0x1e +#define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS_2__FAULT_VMID_MASK 0x000000F0L +#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS_2__FAULT_INSTANCEID_MASK 0x0000C000L +#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS_2__RETRY_INSTANCEID_MASK 0x00C00000L +#define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L +#define IA_UTCL1_STATUS_2__PRT_INSTANCEID_MASK 0xC0000000L +//GE_WD_CNTL_STATUS +#define GE_WD_CNTL_STATUS__DIST_BUSY__SHIFT 0x0 +#define GE_WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT 0x1 +#define GE_WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT 0x2 +#define GE_WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT 0x3 +#define GE_WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT 0x4 +#define GE_WD_CNTL_STATUS__WLC_BUSY__SHIFT 0x5 +#define GE_WD_CNTL_STATUS__DIST_BUSY_MASK 0x00000001L +#define GE_WD_CNTL_STATUS__DIST_BE_BUSY_MASK 0x00000002L +#define GE_WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK 0x00000004L +#define GE_WD_CNTL_STATUS__WD_TE11_BUSY_MASK 0x00000008L +#define GE_WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK 0x00000010L +#define GE_WD_CNTL_STATUS__WLC_BUSY_MASK 0x00000020L +//WD_UTCL1_CNTL +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L +//WD_UTCL1_STATUS +#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define WD_UTCL1_STATUS__FAULT_VMID__SHIFT 0x4 +#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define WD_UTCL1_STATUS__FAULT_INSTANCEID__SHIFT 0xe +#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define WD_UTCL1_STATUS__RETRY_INSTANCEID__SHIFT 0x16 +#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define WD_UTCL1_STATUS__PRT_INSTANCEID__SHIFT 0x1e +#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define WD_UTCL1_STATUS__FAULT_VMID_MASK 0x000000F0L +#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define WD_UTCL1_STATUS__FAULT_INSTANCEID_MASK 0x0000C000L +#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define WD_UTCL1_STATUS__RETRY_INSTANCEID_MASK 0x00C00000L +#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define WD_UTCL1_STATUS__PRT_INSTANCEID_MASK 0xC0000000L +//IA_UTCL1_CNTL +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L +//IA_UTCL1_STATUS +#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS__FAULT_VMID__SHIFT 0x4 +#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS__FAULT_INSTANCEID__SHIFT 0xe +#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS__RETRY_INSTANCEID__SHIFT 0x16 +#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS__PRT_INSTANCEID__SHIFT 0x1e +#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS__FAULT_VMID_MASK 0x000000F0L +#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS__FAULT_INSTANCEID_MASK 0x0000C000L +#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS__RETRY_INSTANCEID_MASK 0x00C00000L +#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define IA_UTCL1_STATUS__PRT_INSTANCEID_MASK 0xC0000000L +//CC_GC_SA_UNIT_DISABLE +#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L +//GE_FED_STATUS +#define GE_FED_STATUS__DMA_C0_FED_ERROR__SHIFT 0x0 +#define GE_FED_STATUS__DMA_C1_FED_ERROR__SHIFT 0x1 +#define GE_FED_STATUS__TF_REQ_FED_ERROR__SHIFT 0x2 +#define GE_FED_STATUS__DMA_C0_FED_ERROR_MASK 0x00000001L +#define GE_FED_STATUS__DMA_C1_FED_ERROR_MASK 0x00000002L +#define GE_FED_STATUS__TF_REQ_FED_ERROR_MASK 0x00000004L +//GE_PRIV_CONTROL +#define GE_PRIV_CONTROL__RESERVED__SHIFT 0x0 +#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1 +#define GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT 0xf +#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT 0x10 +#define GE_PRIV_CONTROL__MIN_ATTR_GRPS__SHIFT 0x12 +#define GE_PRIV_CONTROL__RESERVED_MASK 0x00000001L +#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL +#define GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK 0x00008000L +#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK 0x00010000L +#define GE_PRIV_CONTROL__MIN_ATTR_GRPS_MASK 0x003C0000L +//GE_STATUS +#define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0 +#define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1 +#define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L +#define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L +//VGT_GS_MAX_WAVE_ID +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GFX_PIPE_CONTROL +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT 0x11 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK 0x00020000L +//VGT_RESET_DEBUG +#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 +#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 +#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE0__SHIFT 0x3 +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE1__SHIFT 0x4 +#define VGT_RESET_DEBUG__ENABLE_VMID_RESET_UTCL1__SHIFT 0x5 +#define VGT_RESET_DEBUG__DISABLE_PREFETCH__SHIFT 0x6 +#define VGT_RESET_DEBUG__DISABLE_SWITCH_MODE_STALL_FIX__SHIFT 0x7 +#define VGT_RESET_DEBUG__DISABLE_SENDING_MULTIPLE_SE_IN_PD__SHIFT 0x8 +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_ON_OFF__SHIFT 0x9 +#define VGT_RESET_DEBUG__DISABLE_PATCH_OPTIMIZATION__SHIFT 0xa +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_OFF_ON__SHIFT 0xb +#define VGT_RESET_DEBUG__DISABLE_MERGE_GRP_PERF_FIX__SHIFT 0xc +#define VGT_RESET_DEBUG__DISABLE_MESH_SHADER_ATTR_PACKING__SHIFT 0xd +#define VGT_RESET_DEBUG__ENABLE_SMALL_INST_PACK_ADJ_GS_OFF__SHIFT 0xe +#define VGT_RESET_DEBUG__DISABLE_PATCH_DIST_LAST_DONUT_SE_SWITCH_LOGIC__SHIFT 0xf +#define VGT_RESET_DEBUG__DISABLE_GE1_FED_OPT__SHIFT 0x10 +#define VGT_RESET_DEBUG__DISABLE_GE2_DIST_FED_OPT__SHIFT 0x11 +#define VGT_RESET_DEBUG__SPARE__SHIFT 0x12 +#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L +#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L +#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE0_MASK 0x00000008L +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE1_MASK 0x00000010L +#define VGT_RESET_DEBUG__ENABLE_VMID_RESET_UTCL1_MASK 0x00000020L +#define VGT_RESET_DEBUG__DISABLE_PREFETCH_MASK 0x00000040L +#define VGT_RESET_DEBUG__DISABLE_SWITCH_MODE_STALL_FIX_MASK 0x00000080L +#define VGT_RESET_DEBUG__DISABLE_SENDING_MULTIPLE_SE_IN_PD_MASK 0x00000100L +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_ON_OFF_MASK 0x00000200L +#define VGT_RESET_DEBUG__DISABLE_PATCH_OPTIMIZATION_MASK 0x00000400L +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_OFF_ON_MASK 0x00000800L +#define VGT_RESET_DEBUG__DISABLE_MERGE_GRP_PERF_FIX_MASK 0x00001000L +#define VGT_RESET_DEBUG__DISABLE_MESH_SHADER_ATTR_PACKING_MASK 0x00002000L +#define VGT_RESET_DEBUG__ENABLE_SMALL_INST_PACK_ADJ_GS_OFF_MASK 0x00004000L +#define VGT_RESET_DEBUG__DISABLE_PATCH_DIST_LAST_DONUT_SE_SWITCH_LOGIC_MASK 0x00008000L +#define VGT_RESET_DEBUG__DISABLE_GE1_FED_OPT_MASK 0x00010000L +#define VGT_RESET_DEBUG__DISABLE_GE2_DIST_FED_OPT_MASK 0x00020000L +#define VGT_RESET_DEBUG__SPARE_MASK 0xFFFC0000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_shdec +//COMPUTE_DISPATCH_INITIATOR +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L0_INV__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L0_INV__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf +#define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT 0x10 +#define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT 0x11 +#define COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN__SHIFT 0x12 +#define COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH__SHIFT 0x13 +#define COMPUTE_DISPATCH_INITIATOR__CLUSTER_EN__SHIFT 0x14 +#define COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID__SHIFT 0x1d +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x000000C0L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L0_INV_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L0_INV_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L +#define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK 0x00010000L +#define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK 0x00020000L +#define COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN_MASK 0x00040000L +#define COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH_MASK 0x00080000L +#define COMPUTE_DISPATCH_INITIATOR__CLUSTER_EN_MASK 0x00100000L +#define COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID_MASK 0xE0000000L +//COMPUTE_DIM_X +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Y +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Z +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_START_X +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Y +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Z +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//COMPUTE_NUM_THREAD_X +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X__SHIFT 0xd +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x00001FFFL +#define COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X_MASK 0x0000E000L +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Y +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y__SHIFT 0xd +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x00001FFFL +#define COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y_MASK 0x0000E000L +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Z +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_PIPELINESTAT_ENABLE +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//COMPUTE_PERFCOUNT_ENABLE +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//COMPUTE_PGM_LO +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PGM_HI +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0x0001FFFFL +//COMPUTE_DISPATCH_PKT_ADDR_LO +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_PKT_ADDR_HI +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x0001FFFFL +//COMPUTE_PGM_RSRC1 +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__WG_RR_EN__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define COMPUTE_PGM_RSRC1__DISABLE_PERF__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define COMPUTE_PGM_RSRC1__FLAT_SCRATCH_IS_NV__SHIFT 0x1b +#define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d +#define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e +#define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__WG_RR_EN_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define COMPUTE_PGM_RSRC1__DISABLE_PERF_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +#define COMPUTE_PGM_RSRC1__FLAT_SCRATCH_IS_NV_MASK 0x08000000L +#define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L +#define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L +#define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L +//COMPUTE_PGM_RSRC2 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_PGM_RSRC2__WGP_TAKEOVER__SHIFT 0x1f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000007EL +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define COMPUTE_PGM_RSRC2__WGP_TAKEOVER_MASK 0x80000000L +//COMPUTE_VMID +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_VMID__DATA_MASK 0x0000000FL +//COMPUTE_RESOURCE_LIMITS +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_RESOURCE_LIMITS__CLUSTER_PER_SE__SHIFT 0x1b +#define COMPUTE_RESOURCE_LIMITS__SIMD_WALK_PATTERN__SHIFT 0x1f +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__CLUSTER_PER_SE_MASK 0x78000000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_WALK_PATTERN_MASK 0x80000000L +//COMPUTE_TMPRING_SIZE +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x3FFFF000L +//COMPUTE_RESTART_X +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_THREAD_TRACE_ENABLE +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//COMPUTE_MISC_RESERVED +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x0000000FL +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//COMPUTE_DISPATCH_ID +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//COMPUTE_THREADGROUP_ID +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//COMPUTE_REQ_CTRL +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 +#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L +#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L +//COMPUTE_USER_ACCUM_0 +#define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_1 +#define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_2 +#define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_3 +#define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_PGM_RSRC3 +#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 +#define COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT 0x4 +#define COMPUTE_PGM_RSRC3__GLG_EN__SHIFT 0xd +#define COMPUTE_PGM_RSRC3__NAMED_BAR_CNT__SHIFT 0xe +#define COMPUTE_PGM_RSRC3__DYNAMIC_VGPR__SHIFT 0x11 +#define COMPUTE_PGM_RSRC3__TCP_SPLIT__SHIFT 0x12 +#define COMPUTE_PGM_RSRC3__DIDT_THROTTLE__SHIFT 0x15 +#define COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT 0x1f +#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL +#define COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK 0x00000FF0L +#define COMPUTE_PGM_RSRC3__GLG_EN_MASK 0x00002000L +#define COMPUTE_PGM_RSRC3__NAMED_BAR_CNT_MASK 0x0001C000L +#define COMPUTE_PGM_RSRC3__DYNAMIC_VGPR_MASK 0x00020000L +#define COMPUTE_PGM_RSRC3__TCP_SPLIT_MASK 0x001C0000L +#define COMPUTE_PGM_RSRC3__DIDT_THROTTLE_MASK 0x00200000L +#define COMPUTE_PGM_RSRC3__IMAGE_OP_MASK 0x80000000L +//COMPUTE_DDID_INDEX +#define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 +#define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL +//COMPUTE_SHADER_CHKSUM +#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_INTERLEAVE +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D__SHIFT 0x0 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE__SHIFT 0x10 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE__SHIFT 0x15 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_Z_SIZE__SHIFT 0x1a +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D_MASK 0x000003FFL +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE_MASK 0x001F0000L +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE_MASK 0x03E00000L +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_Z_SIZE_MASK 0x7C000000L +//COMPUTE_CURRENT_LOGICAL_XCC_ID +#define COMPUTE_CURRENT_LOGICAL_XCC_ID__CURRENT_LOGICAL_XCC_ID__SHIFT 0x0 +#define COMPUTE_CURRENT_LOGICAL_XCC_ID__CURRENT_LOGICAL_XCC_ID_MASK 0x0000000FL +//COMPUTE_RESTART_CG_TG_ID +#define COMPUTE_RESTART_CG_TG_ID__RESTART_CG_TG_ID__SHIFT 0x0 +#define COMPUTE_RESTART_CG_TG_ID__RESTART_CG_TG_ID_MASK 0x000FFFFFL +//COMPUTE_TG_CHUNK_SIZE +#define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE__SHIFT 0x0 +#define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE_MASK 0x0000FFFFL +//COMPUTE_RESTORE_TG_CHUNK_SIZE +#define COMPUTE_RESTORE_TG_CHUNK_SIZE__RESTORE_TG_CHUNK_SIZE__SHIFT 0x0 +#define COMPUTE_RESTORE_TG_CHUNK_SIZE__RESTORE_TG_CHUNK_SIZE_MASK 0x0000FFFFL +//COMPUTE_SPARE_1 +#define COMPUTE_SPARE_1__SIZE__SHIFT 0x0 +#define COMPUTE_SPARE_1__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_SPARE_2 +#define COMPUTE_SPARE_2__SIZE__SHIFT 0x0 +#define COMPUTE_SPARE_2__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_PRESCALED_DIM_X +#define COMPUTE_PRESCALED_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_PRESCALED_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_PRESCALED_DIM_Y +#define COMPUTE_PRESCALED_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_PRESCALED_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_PRESCALED_DIM_Z +#define COMPUTE_PRESCALED_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_PRESCALED_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DESTINATION_EN_SE0 +#define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE1 +#define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE1 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE2 +#define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE2 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE3 +#define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE3 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE4 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE5 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE6 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE7 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE8 +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_USER_DATA_0 +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_1 +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_2 +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_3 +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_4 +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_5 +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_6 +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_7 +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_8 +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_9 +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_10 +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_11 +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_12 +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_13 +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_14 +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_15 +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_16 +#define COMPUTE_USER_DATA_16__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_16__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_17 +#define COMPUTE_USER_DATA_17__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_17__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_18 +#define COMPUTE_USER_DATA_18__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_18__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_19 +#define COMPUTE_USER_DATA_19__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_19__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_20 +#define COMPUTE_USER_DATA_20__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_20__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_21 +#define COMPUTE_USER_DATA_21__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_21__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_22 +#define COMPUTE_USER_DATA_22__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_22__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_23 +#define COMPUTE_USER_DATA_23__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_23__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_24 +#define COMPUTE_USER_DATA_24__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_24__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_25 +#define COMPUTE_USER_DATA_25__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_25__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_26 +#define COMPUTE_USER_DATA_26__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_26__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_27 +#define COMPUTE_USER_DATA_27__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_27__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_28 +#define COMPUTE_USER_DATA_28__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_28__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_29 +#define COMPUTE_USER_DATA_29__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_29__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_30 +#define COMPUTE_USER_DATA_30__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_30__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_31 +#define COMPUTE_USER_DATA_31__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_31__DATA_MASK 0xFFFFFFFFL +//COMPUTE_RELAUNCH +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//COMPUTE_RELAUNCH_STATE_PAYLOAD +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__VGPRS__SHIFT 0x0 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_TAKEOVER__SHIFT 0x6 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SPLIT__SHIFT 0x7 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SIZE__SHIFT 0xa +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__TG_PER_CU__SHIFT 0x13 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__SCRATCH_EN__SHIFT 0x17 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__W32_EN__SHIFT 0x18 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_CENTRIC__SHIFT 0x19 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__NAMED_BAR_CNT__SHIFT 0x1a +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__DYNAMIC_VGPR__SHIFT 0x1d +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__VGPRS_MASK 0x0000003FL +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_TAKEOVER_MASK 0x00000040L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SPLIT_MASK 0x00000380L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SIZE_MASK 0x0007FC00L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__TG_PER_CU_MASK 0x00780000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__SCRATCH_EN_MASK 0x00800000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__W32_EN_MASK 0x01000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_CENTRIC_MASK 0x02000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__NAMED_BAR_CNT_MASK 0x1C000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__DYNAMIC_VGPR_MASK 0x20000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_STATE_MASK 0x80000000L +//COMPUTE_WAVE_RESTORE_ADDR_LO +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//COMPUTE_WAVE_RESTORE_ADDR_HI +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0x01FFFFFFL +//COMPUTE_RELAUNCH2 +#define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L +//COMPUTE_RELAUNCH2_STATE_PAYLOAD +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM0__SHIFT 0x0 +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM1__SHIFT 0x7 +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM2__SHIFT 0xe +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM3__SHIFT 0x15 +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__BULKY__SHIFT 0x1c +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM0_MASK 0x0000007FL +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM1_MASK 0x00003F80L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM2_MASK 0x001FC000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM3_MASK 0x0FE00000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__BULKY_MASK 0x10000000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_STATE_MASK 0x80000000L +//COMPUTE_DISPATCH_TUNNEL +#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 +#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x00001FFFL +//COMPUTE_DISPATCH_END +#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//COMPUTE_NOWHERE +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL +//SH_RESERVED_REG0 +#define SH_RESERVED_REG0__DATA__SHIFT 0x0 +#define SH_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//SH_RESERVED_REG1 +#define SH_RESERVED_REG1__DATA__SHIFT 0x0 +#define SH_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE__SHIFT 0x0 +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_RESV__SHIFT 0x7 +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_EN__SHIFT 0x1f +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_MASK 0x0000007FL +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_RESV_MASK 0x7FFFFF80L +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_EN_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gccacdec +//GC_CAC_CTRL_1 +#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 +#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL +#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L +//GC_CAC_CTRL_2 +#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x1 +#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x2 +#define GC_CAC_CTRL_2__TOGGLE_EN__SHIFT 0x3 +#define GC_CAC_CTRL_2__INTR_EN__SHIFT 0x4 +#define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL__SHIFT 0x5 +#define GC_CAC_CTRL_2__SE_AGGR_ACC_EN__SHIFT 0x6 +#define GC_CAC_CTRL_2__GC_AGGR_ACC_EN__SHIFT 0xf +#define GC_CAC_CTRL_2__GC_LCAC_OVR_EN__SHIFT 0x10 +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x11 +#define GC_CAC_CTRL_2__CAC_INTR_MAX_HYSTERESIS__SHIFT 0x12 +#define GC_CAC_CTRL_2__CAC_TDP_AGGR_MODE__SHIFT 0x18 +#define GC_CAC_CTRL_2__LOCAL_REP_FGCG_OVERRIDE__SHIFT 0x19 +#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000002L +#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000004L +#define GC_CAC_CTRL_2__TOGGLE_EN_MASK 0x00000008L +#define GC_CAC_CTRL_2__INTR_EN_MASK 0x00000010L +#define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL_MASK 0x00000020L +#define GC_CAC_CTRL_2__SE_AGGR_ACC_EN_MASK 0x00007FC0L +#define GC_CAC_CTRL_2__GC_AGGR_ACC_EN_MASK 0x00008000L +#define GC_CAC_CTRL_2__GC_LCAC_OVR_EN_MASK 0x00010000L +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00020000L +#define GC_CAC_CTRL_2__CAC_INTR_MAX_HYSTERESIS_MASK 0x00FC0000L +#define GC_CAC_CTRL_2__CAC_TDP_AGGR_MODE_MASK 0x01000000L +#define GC_CAC_CTRL_2__LOCAL_REP_FGCG_OVERRIDE_MASK 0x02000000L +//GC_CAC_AGGR_LOWER +#define GC_CAC_AGGR_LOWER__GC_AGGR_31_0__SHIFT 0x0 +#define GC_CAC_AGGR_LOWER__GC_AGGR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_UPPER +#define GC_CAC_AGGR_UPPER__GC_AGGR_63_32__SHIFT 0x0 +#define GC_CAC_AGGR_UPPER__GC_AGGR_63_32_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_LOWER +#define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0__SHIFT 0x0 +#define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_UPPER +#define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32__SHIFT 0x0 +#define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_LOWER +#define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0__SHIFT 0x0 +#define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_UPPER +#define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32__SHIFT 0x0 +#define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_GFXCLK_CYCLE +#define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_GFXCLK_CYCLE +#define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_GFXCLK_CYCLE +#define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//GC_CAC_OVR_VAL_LOWER +#define GC_CAC_OVR_VAL_LOWER__GC_LCAC_OVR_VAL_LOWER__SHIFT 0x0 +#define GC_CAC_OVR_VAL_LOWER__GC_LCAC_OVR_VAL_LOWER_MASK 0xFFFFFFFFL +//GC_CAC_OVR_VAL_UPPER +#define GC_CAC_OVR_VAL_UPPER__GC_LCAC_OVR_VAL_UPPER__SHIFT 0x0 +#define GC_CAC_OVR_VAL_UPPER__GC_LCAC_OVR_VAL_UPPER_MASK 0xFFFFFFFFL +//GC_EDC_CTRL +#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xa +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xb +#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf +#define GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0x10 +#define GC_EDC_CTRL__EDC_AVGDIV__SHIFT 0x11 +#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT 0x15 +#define GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT 0x18 +#define GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT 0x19 +#define GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT 0x1a +#define GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT 0x1b +#define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS__SHIFT 0x1c +#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00007800L +#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L +#define GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00010000L +#define GC_EDC_CTRL__EDC_AVGDIV_MASK 0x001E0000L +#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK 0x00E00000L +#define GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK 0x01000000L +#define GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK 0x02000000L +#define GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK 0x04000000L +#define GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK 0x08000000L +#define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS_MASK 0xF0000000L +//GC_EDC_STRETCH_CTRL +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT 0x0 +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT 0x1 +#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT 0xa +#define GC_EDC_STRETCH_CTRL__ROLLING_POWER_MODE__SHIFT 0x13 +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK 0x00000001L +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK 0x000003FEL +#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK 0x0007FC00L +#define GC_EDC_STRETCH_CTRL__ROLLING_POWER_MODE_MASK 0x00080000L +//GC_EDC_THRESHOLD_LO +#define GC_EDC_THRESHOLD_LO__EDC_THRESHOLD_LO__SHIFT 0x0 +#define GC_EDC_THRESHOLD_LO__EDC_THRESHOLD_LO_MASK 0xFFFFFFFFL +//GC_EDC_THRESHOLD_HI +#define GC_EDC_THRESHOLD_HI__EDC_THRESHOLD_HI__SHIFT 0x0 +#define GC_EDC_THRESHOLD_HI__EDC_THRESHOLD_HI_MASK 0xFFFFFFFFL +//GC_EDC_STRETCH_THRESHOLD_LO +#define GC_EDC_STRETCH_THRESHOLD_LO__EDC_STRETCH_THRESHOLD_LO__SHIFT 0x0 +#define GC_EDC_STRETCH_THRESHOLD_LO__EDC_STRETCH_THRESHOLD_LO_MASK 0xFFFFFFFFL +//GC_EDC_STRETCH_THRESHOLD_HI +#define GC_EDC_STRETCH_THRESHOLD_HI__EDC_STRETCH_THRESHOLD_HI__SHIFT 0x0 +#define GC_EDC_STRETCH_THRESHOLD_HI__EDC_STRETCH_THRESHOLD_HI_MASK 0xFFFFFFFFL +//EDC_HYSTERESIS_CNTL +#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER__SHIFT 0x8 +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN__SHIFT 0x10 +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE__SHIFT 0x11 +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE__SHIFT 0x14 +#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER_MASK 0x0000FF00L +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN_MASK 0x00010000L +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE_MASK 0x000E0000L +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE_MASK 0x00100000L +//GC_THROTTLE_CTRL +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 +#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3 +#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4 +#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5 +#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6 +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7 +#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8 +#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9 +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb +#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc +#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd +#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17 +#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x18 +#define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e +#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT 0x1f +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L +#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L +#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L +#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L +#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L +#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L +#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L +#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L +#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L +#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L +#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x1F000000L +#define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L +#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK 0x80000000L +//GC_THROTTLE_CTRL1 +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa +#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12 +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17 +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x1a +#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT 0x1e +#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT 0x1f +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L +#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x0C000000L +#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK 0x40000000L +#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK 0x80000000L +//GC_THROTTLE_CTRL2 +#define GC_THROTTLE_CTRL2__EDC_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa +#define GC_THROTTLE_CTRL2__PATTERN_COUNTER_NO_RESTART__SHIFT 0xd +#define GC_THROTTLE_CTRL2__EDC_THROTTLE_LEVEL_COUNTER_EN__SHIFT 0xe +#define GC_THROTTLE_CTRL2__EDC_POWER_DELTA_ALGO2_EN__SHIFT 0xf +#define GC_THROTTLE_CTRL2__EDC_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MAX_STEP_MASK 0x000003E0L +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L +#define GC_THROTTLE_CTRL2__PATTERN_COUNTER_NO_RESTART_MASK 0x00002000L +#define GC_THROTTLE_CTRL2__EDC_THROTTLE_LEVEL_COUNTER_EN_MASK 0x00004000L +#define GC_THROTTLE_CTRL2__EDC_POWER_DELTA_ALGO2_EN_MASK 0x00008000L +//EDC_STALL_PATTERN_CTRL +#define EDC_STALL_PATTERN_CTRL__EDC_STEP_INTERVAL__SHIFT 0x0 +#define EDC_STALL_PATTERN_CTRL__EDC_BEGIN_STEP__SHIFT 0xa +#define EDC_STALL_PATTERN_CTRL__EDC_END_STEP__SHIFT 0xf +#define EDC_STALL_PATTERN_CTRL__EDC_DITHER_MODE__SHIFT 0x14 +#define EDC_STALL_PATTERN_CTRL__EDC_STEP_INTERVAL_MASK 0x000003FFL +#define EDC_STALL_PATTERN_CTRL__EDC_BEGIN_STEP_MASK 0x00007C00L +#define EDC_STALL_PATTERN_CTRL__EDC_END_STEP_MASK 0x000F8000L +#define EDC_STALL_PATTERN_CTRL__EDC_DITHER_MODE_MASK 0x00100000L +//PCC_STALL_PATTERN_CTRL +#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0 +#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa +#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf +#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18 +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19 +#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a +#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL +#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L +#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L +#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L +#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L +//PWRBRK_STALL_PATTERN_CTRL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +//EDC_STALL_PATTERN_1_2 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_3_4 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_5_6 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_7 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_0__SHIFT 0x10 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_0_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_1_2 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_3_4 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_5_6 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_7 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL +//PWRBRK_STALL_PATTERN_1_2 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_3_4 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_5_6 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_7 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_STALL_PATTERN_CTRL +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN__SHIFT 0x0 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST__SHIFT 0x1 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x3 +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN__SHIFT 0x7 +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE__SHIFT 0x8 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_STRETCH_EN__SHIFT 0xb +#define DIDT_STALL_PATTERN_CTRL__DIDT_MAX_HYSTERESIS__SHIFT 0xc +#define DIDT_STALL_PATTERN_CTRL__DIDT_PERF_COUNTER_EN__SHIFT 0x14 +#define DIDT_STALL_PATTERN_CTRL__PSM_DIDT_THROTTLE_SRC_SEL__SHIFT 0x15 +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC0_MASK__SHIFT 0x18 +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC1_MASK__SHIFT 0x19 +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC2_MASK__SHIFT 0x1a +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC3_MASK__SHIFT 0x1b +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN_MASK 0x00000001L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST_MASK 0x00000002L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x00000078L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN_MASK 0x00000080L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE_MASK 0x00000700L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_STRETCH_EN_MASK 0x00000800L +#define DIDT_STALL_PATTERN_CTRL__DIDT_MAX_HYSTERESIS_MASK 0x000FF000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PERF_COUNTER_EN_MASK 0x00100000L +#define DIDT_STALL_PATTERN_CTRL__PSM_DIDT_THROTTLE_SRC_SEL_MASK 0x00E00000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC0_MASK_MASK 0x01000000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC1_MASK_MASK 0x02000000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC2_MASK_MASK 0x04000000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC3_MASK_MASK 0x08000000L +//DIDT_STALL_PATTERN_1_2 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_3_4 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_5_6 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_7 +#define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//PCC_PWRBRK_HYSTERESIS_CTRL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT 0x0 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x8 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK 0x000000FFL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x0000FF00L +//EDC_STRETCH_PERF_COUNTER +#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT 0x0 +#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_UNSTRETCH_PERF_COUNTER +#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT 0x0 +#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_STRETCH_NUM_PERF_COUNTER +#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT 0x0 +#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_EDC_STATUS +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 +#define GC_EDC_STATUS__GPIO_IN_0__SHIFT 0x3 +#define GC_EDC_STATUS__GPIO_IN_1__SHIFT 0x4 +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L +#define GC_EDC_STATUS__GPIO_IN_0_MASK 0x00000008L +#define GC_EDC_STATUS__GPIO_IN_1_MASK 0x00000010L +//GC_EDC_OVERFLOW +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//GC_EDC_ROLLING_POWER_DELTA_LO +#define GC_EDC_ROLLING_POWER_DELTA_LO__EDC_ROLLING_POWER_DELTA_LO__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA_LO__EDC_ROLLING_POWER_DELTA_LO_MASK 0xFFFFFFFFL +//GC_EDC_ROLLING_POWER_DELTA_HI +#define GC_EDC_ROLLING_POWER_DELTA_HI__EDC_ROLLING_POWER_DELTA_HI__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA_HI__EDC_ROLLING_POWER_DELTA_HI_MASK 0xFFFFFFFFL +//GC_EDC_AVG_POWER_DELTA_LO +#define GC_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO__SHIFT 0x0 +#define GC_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO_MASK 0xFFFFFFFFL +//GC_EDC_AVG_POWER_DELTA_HI +#define GC_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI__SHIFT 0x0 +#define GC_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI_MASK 0xFFFFFFFFL +//GC_THROTTLE_STATUS +#define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0 +#define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4 +#define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL +#define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000001F0L +//EDC_PERF_COUNTER +#define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 +#define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PCC_PERF_COUNTER +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PWRBRK_PERF_COUNTER +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_HYSTERESIS_STAT +#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 +#define EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT 0x8 +#define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_STAT__SHIFT 0x9 +#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL +#define EDC_HYSTERESIS_STAT__EDC_STATUS_MASK 0x00000100L +#define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_STAT_MASK 0x00000200L +//DIDT_HYSTERESIS_STAT +#define DIDT_HYSTERESIS_STAT__DIDT_HYSTERESIS_CNT__SHIFT 0x0 +#define DIDT_HYSTERESIS_STAT__DIDT_DROOP_STATUS__SHIFT 0x8 +#define DIDT_HYSTERESIS_STAT__DIDT_HYSTERESIS_CNT_MASK 0x000000FFL +#define DIDT_HYSTERESIS_STAT__DIDT_DROOP_STATUS_MASK 0x00000100L +//DIDT_PERF_COUNTER +#define DIDT_PERF_COUNTER__DIDT_PERF_COUNTER__SHIFT 0x0 +#define DIDT_PERF_COUNTER__DIDT_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_EDC_CLK_MONITOR_CTRL +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN__SHIFT 0x0 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT 0x1 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT 0x5 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN_MASK 0x00000001L +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK 0x0000001EL +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK 0x0001FFE0L +//GC_CAC_SOFT_CTRL +#define GC_CAC_SOFT_CTRL__CAC_SOFT_SNAP__SHIFT 0x0 +#define GC_CAC_SOFT_CTRL__CAC_SOFT_SNAP_MASK 0x00000001L +//GC_CAC_WEIGHT_CP_0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_1 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_PMM_0 +#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_SDMA_0 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_1 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_2 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_3 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_4 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_5 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CHC_0 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CHC_1 +#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_RLC_0 +#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GRBM_0 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_6 +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG12__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG13__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG12_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG13_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_7 +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG14__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG15__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG14_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG15_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GLARB_0 +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GLARB_1 +#define GC_CAC_WEIGHT_GLARB_1__WEIGHT_GLARB_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GLARB_1__WEIGHT_GLARB_SIG2_MASK 0x0000FFFFL +//XCD_TOTAL_CAC_AGGR_LOWER +#define XCD_TOTAL_CAC_AGGR_LOWER__XCD_TOTAL_AGGR_31_0__SHIFT 0x0 +#define XCD_TOTAL_CAC_AGGR_LOWER__XCD_TOTAL_AGGR_31_0_MASK 0xFFFFFFFFL +//XCD_TOTAL_CAC_AGGR_UPPER +#define XCD_TOTAL_CAC_AGGR_UPPER__XCD_TOTAL_AGGR_63_32__SHIFT 0x0 +#define XCD_TOTAL_CAC_AGGR_UPPER__XCD_TOTAL_AGGR_63_32_MASK 0xFFFFFFFFL +//GC_EDC_WEIGHTED_DATA_MULTIPLIER +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALE__SHIFT 0x0 +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALING_EN__SHIFT 0x10 +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALE_MASK 0x0000FFFFL +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALING_EN_MASK 0x00010000L +//GC_CAC_IND_INDEX +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//GC_CAC_IND_DATA +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gc_ea_cpwd_gceadec +//GC_EA_CPWD_VC_MAP +#define GC_EA_CPWD_VC_MAP__DRAM_VC__SHIFT 0x0 +#define GC_EA_CPWD_VC_MAP__IO_RD_VC__SHIFT 0x3 +#define GC_EA_CPWD_VC_MAP__IO_WR_VC__SHIFT 0x6 +#define GC_EA_CPWD_VC_MAP__GMI_VC__SHIFT 0x9 +#define GC_EA_CPWD_VC_MAP__NPA_VC__SHIFT 0xc +#define GC_EA_CPWD_VC_MAP__NPAS_VC__SHIFT 0xf +#define GC_EA_CPWD_VC_MAP__LPDDR_VC__SHIFT 0x12 +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRCKR_CHECK_EN_ON_RSP_CREDIT__SHIFT 0x15 +#define GC_EA_CPWD_VC_MAP__PRB_RSP_SEND_WO_PRB_RTN_DAT_AVAIL__SHIFT 0x16 +#define GC_EA_CPWD_VC_MAP__REG_ATOMIC_RPC_CMD_SELECT__SHIFT 0x17 +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRACKER_FIFO_SPACE__SHIFT 0x18 +#define GC_EA_CPWD_VC_MAP__DRAM_VC_MASK 0x00000007L +#define GC_EA_CPWD_VC_MAP__IO_RD_VC_MASK 0x00000038L +#define GC_EA_CPWD_VC_MAP__IO_WR_VC_MASK 0x000001C0L +#define GC_EA_CPWD_VC_MAP__GMI_VC_MASK 0x00000E00L +#define GC_EA_CPWD_VC_MAP__NPA_VC_MASK 0x00007000L +#define GC_EA_CPWD_VC_MAP__NPAS_VC_MASK 0x00038000L +#define GC_EA_CPWD_VC_MAP__LPDDR_VC_MASK 0x001C0000L +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRCKR_CHECK_EN_ON_RSP_CREDIT_MASK 0x00200000L +#define GC_EA_CPWD_VC_MAP__PRB_RSP_SEND_WO_PRB_RTN_DAT_AVAIL_MASK 0x00400000L +#define GC_EA_CPWD_VC_MAP__REG_ATOMIC_RPC_CMD_SELECT_MASK 0x00800000L +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRACKER_FIFO_SPACE_MASK 0xFF000000L +//GC_EA_CPWD_SDP_ARB_FINAL +#define GC_EA_CPWD_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_ARB_FINAL__LPDDR_BURST_LIMIT__SHIFT 0x5 +#define GC_EA_CPWD_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define GC_EA_CPWD_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define GC_EA_CPWD_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11 +#define GC_EA_CPWD_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12 +#define GC_EA_CPWD_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x13 +#define GC_EA_CPWD_SDP_ARB_FINAL__HDM_BURST_LIMIT__SHIFT 0x18 +#define GC_EA_CPWD_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define GC_EA_CPWD_SDP_ARB_FINAL__LPDDR_BURST_LIMIT_MASK 0x000003E0L +#define GC_EA_CPWD_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define GC_EA_CPWD_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define GC_EA_CPWD_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L +#define GC_EA_CPWD_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L +#define GC_EA_CPWD_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x00F80000L +#define GC_EA_CPWD_SDP_ARB_FINAL__HDM_BURST_LIMIT_MASK 0x1F000000L +//GC_EA_CPWD_SDP_PRIORITY +#define GC_EA_CPWD_SDP_PRIORITY__DRAM_PRIORITY__SHIFT 0x0 +#define GC_EA_CPWD_SDP_PRIORITY__IO_RD_PRIORITY__SHIFT 0x4 +#define GC_EA_CPWD_SDP_PRIORITY__IO_WR_PRIORITY__SHIFT 0x8 +#define GC_EA_CPWD_SDP_PRIORITY__MAM_WR_PRIORITY__SHIFT 0xc +#define GC_EA_CPWD_SDP_PRIORITY__GMI_PRIORITY__SHIFT 0x10 +#define GC_EA_CPWD_SDP_PRIORITY__HDM_PRIORITY__SHIFT 0x14 +#define GC_EA_CPWD_SDP_PRIORITY__LPDDR_PRIORITY__SHIFT 0x18 +#define GC_EA_CPWD_SDP_PRIORITY__DRAM_PRIORITY_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_PRIORITY__IO_RD_PRIORITY_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_PRIORITY__IO_WR_PRIORITY_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_PRIORITY__MAM_WR_PRIORITY_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_PRIORITY__GMI_PRIORITY_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_PRIORITY__HDM_PRIORITY_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_PRIORITY__LPDDR_PRIORITY_MASK 0x0F000000L +//GC_EA_CPWD_SDP_CREDITS +#define GC_EA_CPWD_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x9 +#define GC_EA_CPWD_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define GC_EA_CPWD_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x17 +#define GC_EA_CPWD_SDP_CREDITS__TAG_LIMIT_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x0000FE00L +#define GC_EA_CPWD_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +#define GC_EA_CPWD_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F800000L +//GC_EA_CPWD_SDP_TAG_RESERVE0 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC1__SHIFT 0x9 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC2__SHIFT 0x12 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC0_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC1_MASK 0x0003FE00L +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC2_MASK 0x07FC0000L +//GC_EA_CPWD_SDP_TAG_RESERVE1 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC3__SHIFT 0x0 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC4__SHIFT 0x9 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC5__SHIFT 0x12 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC3_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC4_MASK 0x0003FE00L +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC5_MASK 0x07FC0000L +//GC_EA_CPWD_SDP_TAG_RESERVE2 +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC6__SHIFT 0x0 +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC7__SHIFT 0x9 +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC6_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC7_MASK 0x0003FE00L +//GC_EA_CPWD_SDP_VCC_RESERVE0 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GC_EA_CPWD_SDP_VCC_RESERVE1 +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GC_EA_CPWD_SDP_VCD_RESERVE0 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GC_EA_CPWD_SDP_VCD_RESERVE1 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCD_RESERVE1__PRB_CREDITS__SHIFT 0x12 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__POOL_CREDITS__SHIFT 0x18 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__PRB_CREDITS_MASK 0x00FC0000L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__POOL_CREDITS_MASK 0x3F000000L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GC_EA_CPWD_SDP_REQ_CNTL +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define GC_EA_CPWD_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x3 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x4 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x6 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0x8 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0xa +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0xb +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_HDM__SHIFT 0xc +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_LPDDR__SHIFT 0xd +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define GC_EA_CPWD_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000008L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x00000030L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x000000C0L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000300L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000400L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000800L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_HDM_MASK 0x00001000L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_LPDDR_MASK 0x00002000L +//GC_EA_CPWD_MISC +#define GC_EA_CPWD_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x0 +#define GC_EA_CPWD_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x2 +#define GC_EA_CPWD_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x4 +#define GC_EA_CPWD_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x6 +#define GC_EA_CPWD_MISC__LINKMGR_CREDITRESET_CGCG_IGNORE__SHIFT 0xb +#define GC_EA_CPWD_MISC__RSP_ACK_TRACKER_FIFO_SPACE_RSP_PATH__SHIFT 0xc +#define GC_EA_CPWD_MISC__RSP_ACK_PRB_LINK_BUSY__SHIFT 0x14 +#define GC_EA_CPWD_MISC__RSP_ACK_TAG_RELEASE__SHIFT 0x15 +#define GC_EA_CPWD_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000003L +#define GC_EA_CPWD_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x0000000CL +#define GC_EA_CPWD_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000030L +#define GC_EA_CPWD_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000007C0L +#define GC_EA_CPWD_MISC__LINKMGR_CREDITRESET_CGCG_IGNORE_MASK 0x00000800L +#define GC_EA_CPWD_MISC__RSP_ACK_TRACKER_FIFO_SPACE_RSP_PATH_MASK 0x000FF000L +#define GC_EA_CPWD_MISC__RSP_ACK_PRB_LINK_BUSY_MASK 0x00100000L +#define GC_EA_CPWD_MISC__RSP_ACK_TAG_RELEASE_MASK 0x00200000L +//GC_EA_CPWD_ERR_STATUS +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GC_EA_CPWD_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_COMP_KEY_PARITY_ERROR__SHIFT 0xb +#define GC_EA_CPWD_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xc +#define GC_EA_CPWD_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xd +#define GC_EA_CPWD_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define GC_EA_CPWD_ERR_STATUS__FUE_FLAG__SHIFT 0xf +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GC_EA_CPWD_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_COMP_KEY_PARITY_ERROR_MASK 0x00000800L +#define GC_EA_CPWD_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00001000L +#define GC_EA_CPWD_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00002000L +#define GC_EA_CPWD_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define GC_EA_CPWD_ERR_STATUS__FUE_FLAG_MASK 0x00008000L +//GC_EA_CPWD_MISC2 +#define GC_EA_CPWD_MISC2__BLOCK_REQUESTS__SHIFT 0x0 +#define GC_EA_CPWD_MISC2__REQUESTS_BLOCKED__SHIFT 0x1 +#define GC_EA_CPWD_MISC2__FGCLKEN_OVERRIDE__SHIFT 0x2 +#define GC_EA_CPWD_MISC2__LINKMGR_CRBUSY_MASK__SHIFT 0x3 +#define GC_EA_CPWD_MISC2__RDRET_FED_MASK__SHIFT 0x4 +#define GC_EA_CPWD_MISC2__BLOCK_REQUESTS_MASK 0x00000001L +#define GC_EA_CPWD_MISC2__REQUESTS_BLOCKED_MASK 0x00000002L +#define GC_EA_CPWD_MISC2__FGCLKEN_OVERRIDE_MASK 0x00000004L +#define GC_EA_CPWD_MISC2__LINKMGR_CRBUSY_MASK_MASK 0x00000008L +#define GC_EA_CPWD_MISC2__RDRET_FED_MASK_MASK 0x00000010L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBR_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBRSP_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__RSP_ACK_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBR_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBRSP_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__RSP_ACK_CREDITS_RECEIVED_MASK 0x001FC000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBR_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBRSP_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__RSP_ACK_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBR_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBRSP_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__RSP_ACK_CREDITS_RECEIVED_MASK 0x001FC000L +//GC_EA_CPWD_SDP_BACKDOOR_MISCCTL +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL__SDP_ORIGCLKCTL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL__SDP_ORIGCLKCTL_MASK 0x00000001L +//GC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE__SDP_ORIGCLKCTL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE__SDP_ORIGCLKCTL_MASK 0x00000001L +//GC_EA_CPWD_INVALID_OPCODE +#define GC_EA_CPWD_INVALID_OPCODE__INVALID_COMMAND__SHIFT 0x0 +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE__SHIFT 0x1 +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE_VFID__SHIFT 0xc +#define GC_EA_CPWD_INVALID_OPCODE__INVALID_COMMAND_MASK 0x00000001L +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE_MASK 0x000001FEL +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE_VFID_MASK 0x0001F000L +//GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_CNT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_EN__SHIFT 0x7 +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_CNT__SHIFT 0x8 +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_EN__SHIFT 0xf +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_CNT_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_EN_MASK 0x00000080L +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_CNT_MASK 0x00007F00L +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_EN_MASK 0x00008000L +//GC_EA_CPWD_SDP_POISON_ERR_LOG +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__EGRESS_POISON_ERR_CNT_LOG__SHIFT 0x0 +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__INGRESS_POISON_ERR_CNT_LOG__SHIFT 0x8 +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__EGRESS_POISON_ERR_CNT_LOG_MASK 0x000000FFL +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__INGRESS_POISON_ERR_CNT_LOG_MASK 0x0000FF00L +//GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_CNT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_EN__SHIFT 0x7 +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_CNT__SHIFT 0x8 +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_EN__SHIFT 0xf +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_CNT_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_EN_MASK 0x00000080L +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_CNT_MASK 0x00007F00L +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_EN_MASK 0x00008000L +//GC_EA_CPWD_SDP_PARITY_ERR_LOG +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__EGRESS_ORIGDATA_PARITY_ERR_CNT_LOG__SHIFT 0x0 +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__INGRESS_RDRSPDATA_PARITY_ERR_CNT_LOG__SHIFT 0x8 +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__EGRESS_ORIGDATA_PARITY_ERR_CNT_LOG_MASK 0x000000FFL +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__INGRESS_RDRSPDATA_PARITY_ERR_CNT_LOG_MASK 0x0000FF00L +//GC_EA_CPWD_SDP_ENABLE +#define GC_EA_CPWD_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define GC_EA_CPWD_SDP_ENABLE__EARLY_CREDIT_REQUEST__SHIFT 0x1 +#define GC_EA_CPWD_SDP_ENABLE__ENABLE_MASK 0x00000001L +#define GC_EA_CPWD_SDP_ENABLE__EARLY_CREDIT_REQUEST_MASK 0x00000002L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gcrdec +//GCR_PIO_CNTL +#define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0 +#define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x3 +#define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x4 +#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10 +#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e +#define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f +#define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000007L +#define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000008L +#define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000010L +#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L +#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L +#define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L +//GCR_PIO_DATA +#define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0 +#define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL +//GCR_NHTOE_CNTL +#define GCR_NHTOE_CNTL__GCR_DATA_INDEX__SHIFT 0x0 +#define GCR_NHTOE_CNTL__GCR_REG_DONE__SHIFT 0x3 +#define GCR_NHTOE_CNTL__GCR_REG_RESET__SHIFT 0x4 +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_TAG__SHIFT 0x10 +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_DONE__SHIFT 0x1e +#define GCR_NHTOE_CNTL__GCR_READY__SHIFT 0x1f +#define GCR_NHTOE_CNTL__GCR_DATA_INDEX_MASK 0x00000007L +#define GCR_NHTOE_CNTL__GCR_REG_DONE_MASK 0x00000008L +#define GCR_NHTOE_CNTL__GCR_REG_RESET_MASK 0x00000010L +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_TAG_MASK 0x00FF0000L +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_DONE_MASK 0x40000000L +#define GCR_NHTOE_CNTL__GCR_READY_MASK 0x80000000L +//GCR_NHTOE_DATA +#define GCR_NHTOE_DATA__GCR_DATA__SHIFT 0x0 +#define GCR_NHTOE_DATA__GCR_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cppdec +//CPC_INT_ADDR1 +#define CPC_INT_ADDR1__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR1__ADDR_MASK 0x000001FFL +//CP_CU_MASK_ADDR_LO +#define CP_CU_MASK_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_CU_MASK_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_CU_MASK_ADDR_HI +#define CP_CU_MASK_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CU_MASK_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_CU_MASK_CNTL +#define CP_CU_MASK_CNTL__POLICY__SHIFT 0x0 +#define CP_CU_MASK_CNTL__SCOPE__SHIFT 0x2 +#define CP_CU_MASK_CNTL__POLICY_MASK 0x00000003L +#define CP_CU_MASK_CNTL__SCOPE_MASK 0x0000000CL +//CP_EOPQ_WAIT_TIME +#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa +#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L +//CP_CPC_MGCG_SYNC_CNTL +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//CPC_INT_INFO +#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 +#define CPC_INT_INFO__TYPE__SHIFT 0x10 +#define CPC_INT_INFO__VMID__SHIFT 0x14 +#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c +#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL +#define CPC_INT_INFO__TYPE_MASK 0x00010000L +#define CPC_INT_INFO__VMID_MASK 0x00F00000L +#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L +//CP_VIRT_STATUS +#define CP_VIRT_STATUS__VF__SHIFT 0x0 +#define CP_VIRT_STATUS__PF__SHIFT 0x1f +#define CP_VIRT_STATUS__VF_MASK 0x00FFFFFFL +#define CP_VIRT_STATUS__PF_MASK 0x80000000L +//CPC_INT_ADDR +#define CPC_INT_ADDR__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL +//CPC_INT_PASID +#define CPC_INT_PASID__PASID__SHIFT 0x0 +#define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10 +#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL +#define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L +//CP_GFX_ERROR +#define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x0 +#define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x1 +#define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR__SHIFT 0x2 +#define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR__SHIFT 0x3 +#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6 +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e +#define CP_GFX_ERROR__RESERVED__SHIFT 0x1f +#define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000001L +#define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000002L +#define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR_MASK 0x00000004L +#define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR_MASK 0x00000008L +#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L +#define CP_GFX_ERROR__RESERVED_MASK 0x80000000L +//CPG_UTCL1_CNTL +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPC_UTCL1_CNTL +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPC_UTCL1_CNTL__EN_RETRY_ON_ATOMIC__SHIFT 0x15 +#define CPC_UTCL1_CNTL__PCIE_ATOMIC_SUPPORTED__SHIFT 0x16 +#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPC_UTCL1_CNTL__EN_RETRY_ON_ATOMIC_MASK 0x00200000L +#define CPC_UTCL1_CNTL__PCIE_ATOMIC_SUPPORTED_MASK 0x00400000L +#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPF_UTCL1_CNTL +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L +//CP_AQL_SMM_STATUS +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL +//CP_RB0_BASE +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB0_CNTL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB0_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB0_CNTL__SCOPE__SHIFT 0x12 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB0_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB0_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB0_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB0_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB0_CNTL__SCOPE_MASK 0x000C0000L +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB0_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB_CNTL__SCOPE__SHIFT 0x12 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB_CNTL__SCOPE_MASK 0x000C0000L +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL +//CP_RB0_RPTR_ADDR +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB0_RPTR_ADDR_HI +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_RPTR_ADDR_HI +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_BUFSZ_MASK +#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_BUFSZ_MASK +#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_ME3_INT_STAT_DEBUG +#define CP_ME3_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME3_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME3_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME3_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME3_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_ME3_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_ME3_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_ME3_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//GC_PRIV_MODE +#define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT 0x0 +#define GC_PRIV_MODE__MC_PRIV_MODE_MASK 0x00000001L +//CP_INT_CNTL +#define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8 +#define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9 +#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L +#define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L +#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS +#define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8 +#define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9 +#define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L +#define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L +#define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_DEVICE_ID +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL +//CP_ME0_PIPE_PRIORITY_CNTS +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_RING_PRIORITY_CNTS +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME0_PIPE0_PRIORITY +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING0_PRIORITY +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_FATAL_ERROR +#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 +#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 +#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 +#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L +#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L +#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L +//CP_RB_VMID +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL +#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L +#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L +//CP_ME0_PIPE0_VMID +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL +//CP_RB0_WPTR +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB0_WPTR_HI +#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR_HI +#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_PROCESS_QUANTUM +#define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0 +#define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c +#define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d +#define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f +#define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L +#define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L +#define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L +//CP_RB_DOORBELL_RANGE_LOWER +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL +//CP_RB_DOORBELL_RANGE_UPPER +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL +//CP_MEC_DOORBELL_RANGE_LOWER +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL +//CP_MEC_DOORBELL_RANGE_UPPER +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL +//CPG_UTCL1_ERROR +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPC_UTCL1_ERROR +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPF_FED_STATUS +#define CPF_FED_STATUS__FED_ERROR__SHIFT 0x0 +#define CPF_FED_STATUS__FED_ERROR_ID__SHIFT 0x1 +#define CPF_FED_STATUS__FED_RING_ID__SHIFT 0x18 +#define CPF_FED_STATUS__FED_VF_ID__SHIFT 0x1a +#define CPF_FED_STATUS__FED_VF_PF__SHIFT 0x1f +#define CPF_FED_STATUS__FED_ERROR_MASK 0x00000001L +#define CPF_FED_STATUS__FED_ERROR_ID_MASK 0x0000003EL +#define CPF_FED_STATUS__FED_RING_ID_MASK 0x03000000L +#define CPF_FED_STATUS__FED_VF_ID_MASK 0x7C000000L +#define CPF_FED_STATUS__FED_VF_PF_MASK 0x80000000L +//CPC_FED_STATUS +#define CPC_FED_STATUS__FED_ERROR__SHIFT 0x0 +#define CPC_FED_STATUS__FED_ERROR_ID__SHIFT 0x1 +#define CPC_FED_STATUS__FED_RING_ID__SHIFT 0x18 +#define CPC_FED_STATUS__FED_VF_ID__SHIFT 0x1a +#define CPC_FED_STATUS__FED_VF_PF__SHIFT 0x1f +#define CPC_FED_STATUS__FED_ERROR_MASK 0x00000001L +#define CPC_FED_STATUS__FED_ERROR_ID_MASK 0x0000003EL +#define CPC_FED_STATUS__FED_RING_ID_MASK 0x03000000L +#define CPC_FED_STATUS__FED_VF_ID_MASK 0x7C000000L +#define CPC_FED_STATUS__FED_VF_PF_MASK 0x80000000L +//CPG_FED_STATUS +#define CPG_FED_STATUS__FED_ERROR__SHIFT 0x0 +#define CPG_FED_STATUS__FED_ERROR_ID__SHIFT 0x1 +#define CPG_FED_STATUS__FED_RING_ID__SHIFT 0x18 +#define CPG_FED_STATUS__FED_VF_ID__SHIFT 0x1a +#define CPG_FED_STATUS__FED_VF_PF__SHIFT 0x1f +#define CPG_FED_STATUS__FED_ERROR_MASK 0x00000001L +#define CPG_FED_STATUS__FED_ERROR_ID_MASK 0x0000003EL +#define CPG_FED_STATUS__FED_RING_ID_MASK 0x03000000L +#define CPG_FED_STATUS__FED_VF_ID_MASK 0x7C000000L +#define CPG_FED_STATUS__FED_VF_PF_MASK 0x80000000L +//CP_IB1_BUFFER_COUNT +#define CP_IB1_BUFFER_COUNT__COUNT__SHIFT 0x0 +#define CP_IB1_BUFFER_COUNT__COUNT_MASK 0x000FFFFFL +//CP_IB2_BUFFER_COUNT +#define CP_IB2_BUFFER_COUNT__COUNT__SHIFT 0x0 +#define CP_IB2_BUFFER_COUNT__COUNT_MASK 0x000FFFFFL +//CP_INT_CNTL_RING0 +#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8 +#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9 +#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L +#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L +#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_DEBUG_2 +#define CP_DEBUG_2__CPG_CHIU_HDM_OVERRIDE__SHIFT 0x9 +#define CP_DEBUG_2__CPG_CHIU_TEE_OVERRIDE__SHIFT 0xa +#define CP_DEBUG_2__HEADER_TRAP_DIS__SHIFT 0xb +#define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE__SHIFT 0xe +#define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE__SHIFT 0xf +#define CP_DEBUG_2__NOP_DISCARD_DISABLE__SHIFT 0x10 +#define CP_DEBUG_2__DC_INTERLEAVE_DISABLE__SHIFT 0x11 +#define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE__SHIFT 0x1b +#define CP_DEBUG_2__DC_FORCE_CLK_EN__SHIFT 0x1c +#define CP_DEBUG_2__DC_DISABLE_BROADCAST__SHIFT 0x1d +#define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE__SHIFT 0x1e +#define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE__SHIFT 0x1f +#define CP_DEBUG_2__CPG_CHIU_HDM_OVERRIDE_MASK 0x00000200L +#define CP_DEBUG_2__CPG_CHIU_TEE_OVERRIDE_MASK 0x00000400L +#define CP_DEBUG_2__HEADER_TRAP_DIS_MASK 0x00000800L +#define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE_MASK 0x00004000L +#define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE_MASK 0x00008000L +#define CP_DEBUG_2__NOP_DISCARD_DISABLE_MASK 0x00010000L +#define CP_DEBUG_2__DC_INTERLEAVE_DISABLE_MASK 0x00020000L +#define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE_MASK 0x08000000L +#define CP_DEBUG_2__DC_FORCE_CLK_EN_MASK 0x10000000L +#define CP_DEBUG_2__DC_DISABLE_BROADCAST_MASK 0x20000000L +#define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE_MASK 0x40000000L +#define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE_MASK 0x80000000L +//CP_INT_STATUS_RING0 +#define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8 +#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9 +#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L +#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L +#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_ME_F32_INTERRUPT +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L +//CP_PFP_F32_INTERRUPT +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L +//CP_MEC1_F32_INTERRUPT +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_PWR_CNTL +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L +//CP_ECC_FIRSTOCCURRENCE +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE_RING0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL +//GB_EDC_MODE +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +//CP_DEBUG +#define CP_DEBUG__PERFMON_RING_SEL__SHIFT 0x0 +#define CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT 0x2 +#define CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0x8 +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CP_DEBUG__PACKET_FILTER_DISABLE__SHIFT 0xa +#define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE__SHIFT 0xb +#define CP_DEBUG__CPG_CHIU_RO_DISABLE__SHIFT 0xc +#define CP_DEBUG__CPG_GCR_CNTL_BYPASS__SHIFT 0xd +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT 0xe +#define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE__SHIFT 0xf +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x10 +#define CP_DEBUG__CPG_DATA_POISONING_INT_DISABLE__SHIFT 0x13 +#define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 +#define CP_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x17 +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE__SHIFT 0x1b +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT 0x1e +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT 0x1f +#define CP_DEBUG__PERFMON_RING_SEL_MASK 0x00000003L +#define CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK 0x000000FCL +#define CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00000100L +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define CP_DEBUG__PACKET_FILTER_DISABLE_MASK 0x00000400L +#define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE_MASK 0x00000800L +#define CP_DEBUG__CPG_CHIU_RO_DISABLE_MASK 0x00001000L +#define CP_DEBUG__CPG_GCR_CNTL_BYPASS_MASK 0x00002000L +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK 0x00004000L +#define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE_MASK 0x00008000L +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L +#define CP_DEBUG__CPG_DATA_POISONING_INT_DISABLE_MASK 0x00080000L +#define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L +#define CP_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE_MASK 0x08000000L +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK 0x40000000L +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK 0x80000000L +//CP_CPF_DEBUG +#define CP_CPF_DEBUG__PRIVATE_REG_ACC_DISABLE__SHIFT 0x6 +#define CP_CPF_DEBUG__CPF_CHIU_TEE_OVERRIDE__SHIFT 0x7 +#define CP_CPF_DEBUG__CPF_CHIU_HDM_OVERRIDE__SHIFT 0xd +#define CP_CPF_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe +#define CP_CPF_DEBUG__MES_DOORBELL_HIT_BUSY_OVERRIDE__SHIFT 0xf +#define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT 0x10 +#define CP_CPF_DEBUG__CPF_GCR_CNTL_BYPASS__SHIFT 0x11 +#define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPF_DEBUG__CPF_DATA_POISONING_INT_DISABLE__SHIFT 0x13 +#define CP_CPF_DEBUG__CLOCK_ACTIVE_DELAY_OVERRIDE__SHIFT 0x16 +#define CP_CPF_DEBUG__CLOCK_ACTIVE_OVERRIDE__SHIFT 0x17 +#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPF_DEBUG__CE_FETCHER_DISABLE__SHIFT 0x1b +#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT 0x1d +#define CP_CPF_DEBUG__CPF_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e +#define CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT 0x1f +#define CP_CPF_DEBUG__PRIVATE_REG_ACC_DISABLE_MASK 0x00000040L +#define CP_CPF_DEBUG__CPF_CHIU_TEE_OVERRIDE_MASK 0x00000080L +#define CP_CPF_DEBUG__CPF_CHIU_HDM_OVERRIDE_MASK 0x00002000L +#define CP_CPF_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L +#define CP_CPF_DEBUG__MES_DOORBELL_HIT_BUSY_OVERRIDE_MASK 0x00008000L +#define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK 0x00010000L +#define CP_CPF_DEBUG__CPF_GCR_CNTL_BYPASS_MASK 0x00020000L +#define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPF_DEBUG__CPF_DATA_POISONING_INT_DISABLE_MASK 0x00080000L +#define CP_CPF_DEBUG__CLOCK_ACTIVE_DELAY_OVERRIDE_MASK 0x00400000L +#define CP_CPF_DEBUG__CLOCK_ACTIVE_OVERRIDE_MASK 0x00800000L +#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPF_DEBUG__CE_FETCHER_DISABLE_MASK 0x08000000L +#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK 0x20000000L +#define CP_CPF_DEBUG__CPF_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L +#define CP_CPF_DEBUG__DBGU_TRIGGER_MASK 0x80000000L +//CP_CPC_DEBUG +#define CP_CPC_DEBUG__PIPE_SELECT__SHIFT 0x0 +#define CP_CPC_DEBUG__ME_SELECT__SHIFT 0x2 +#define CP_CPC_DEBUG__CPC_CHIU_TEE_OVERRIDE__SHIFT 0x3 +#define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE__SHIFT 0x4 +#define CP_CPC_DEBUG__CPC_CHIU_HDM_OVERRIDE__SHIFT 0x5 +#define CP_CPC_DEBUG__DISP_MODE1_FAST_SKIP_DISABLE__SHIFT 0x6 +#define CP_CPC_DEBUG__DISABLE_PER_QUEUE_ADC_STATE_STORE__SHIFT 0xb +#define CP_CPC_DEBUG__ENABLE_CONF_CS_DIST__SHIFT 0xd +#define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT 0xf +#define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS__SHIFT 0x11 +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPC_DEBUG__CPC_DATA_POISONING_INT_DISABLE__SHIFT 0x13 +#define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT 0x15 +#define CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 +#define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE__SHIFT 0x17 +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT 0x1f +#define CP_CPC_DEBUG__PIPE_SELECT_MASK 0x00000003L +#define CP_CPC_DEBUG__ME_SELECT_MASK 0x00000004L +#define CP_CPC_DEBUG__CPC_CHIU_TEE_OVERRIDE_MASK 0x00000008L +#define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE_MASK 0x00000010L +#define CP_CPC_DEBUG__CPC_CHIU_HDM_OVERRIDE_MASK 0x00000020L +#define CP_CPC_DEBUG__DISP_MODE1_FAST_SKIP_DISABLE_MASK 0x00000040L +#define CP_CPC_DEBUG__DISABLE_PER_QUEUE_ADC_STATE_STORE_MASK 0x00000800L +#define CP_CPC_DEBUG__ENABLE_CONF_CS_DIST_MASK 0x00002000L +#define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK 0x00008000L +#define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS_MASK 0x00020000L +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPC_DEBUG__CPC_DATA_POISONING_INT_DISABLE_MASK 0x00080000L +#define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK 0x00200000L +#define CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L +#define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE_MASK 0x00800000L +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL1 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL +//CP_ME1_PIPE0_INT_CNTL +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE1_INT_CNTL +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE2_INT_CNTL +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE3_INT_CNTL +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE0_INT_STATUS +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE1_INT_STATUS +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE2_INT_STATUS +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE3_INT_STATUS +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_INT_STAT_DEBUG +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CP_GFX_QUEUE_INDEX +#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0 +#define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4 +#define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8 +#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L +#define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L +#define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L +//CC_GC_EDC_CONFIG +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//CP_ME1_PIPE_PRIORITY_CNTS +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME1_PIPE0_PRIORITY +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE1_PRIORITY +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE2_PRIORITY +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE3_PRIORITY +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_PFP_PRGRM_CNTR_START +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_ME_PRGRM_CNTR_START +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MEC1_PRGRM_CNTR_START +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL +//CP_PFP_INTR_ROUTINE_START +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_ME_INTR_ROUTINE_START +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_MEC1_INTR_ROUTINE_START +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL +//CP_CONTEXT_CNTL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x0000000FL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x000000F0L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x000F0000L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00F00000L +//CP_MAX_CONTEXT +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L +//CP_IQ_WAIT_TIME1 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//CP_IQ_WAIT_TIME2 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//CP_RB0_BASE_HI +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_VMID_RESET +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10 +#define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L +#define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L +//CPC_INT_CNTL +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CPC_INT_STATUS +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_VMID_PREEMPT +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L +//CPC_INT_CNTX_ID +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PQ_STATUS +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L +#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L +//CP_PFP_PRGRM_CNTR_START_HI +#define CP_PFP_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MAX_DRAW_COUNT +#define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT__SHIFT 0x0 +#define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT_MASK 0xFFFFFFFFL +//CP_VMID_STATUS +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L +//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CPC_SUSPEND_CTX_SAVE_CONTROL +#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__SCOPE__SHIFT 0x5 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define CPC_SUSPEND_CTX_SAVE_CONTROL__SCOPE_MASK 0x00000060L +#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CPC_SUSPEND_CNTL_STACK_OFFSET +#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CPC_SUSPEND_CNTL_STACK_SIZE +#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CPC_SUSPEND_WG_STATE_OFFSET +#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CPC_SUSPEND_CTX_SAVE_SIZE +#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//CPC_OS_PIPES +#define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0 +#define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL +//CP_SUSPEND_RESUME_REQ +#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 +#define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 +#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L +#define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L +//CP_SUSPEND_CNTL +#define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0 +#define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1 +#define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2 +#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3 +#define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L +#define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L +#define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L +#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L +//CP_IQ_WAIT_TIME3 +#define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 +#define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL +//CPC_DDID_BASE_ADDR_LO +#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//CP_DDID_BASE_ADDR_LO +#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//CPC_DDID_BASE_ADDR_HI +#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x01FFFFFFL +//CP_DDID_BASE_ADDR_HI +#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x01FFFFFFL +//CPC_DDID_CNTL +#define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define CPC_DDID_CNTL__SIZE__SHIFT 0x10 +#define CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define CPC_DDID_CNTL__SCOPE__SHIFT 0x18 +#define CPC_DDID_CNTL__POLICY__SHIFT 0x1c +#define CPC_DDID_CNTL__MODE__SHIFT 0x1e +#define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f +#define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define CPC_DDID_CNTL__SIZE_MASK 0x00010000L +#define CPC_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define CPC_DDID_CNTL__SCOPE_MASK 0x03000000L +#define CPC_DDID_CNTL__POLICY_MASK 0x30000000L +#define CPC_DDID_CNTL__MODE_MASK 0x40000000L +#define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L +//CP_DDID_CNTL +#define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define CP_DDID_CNTL__SIZE__SHIFT 0x10 +#define CP_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define CP_DDID_CNTL__VMID__SHIFT 0x14 +#define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18 +#define CP_DDID_CNTL__SCOPE__SHIFT 0x1a +#define CP_DDID_CNTL__POLICY__SHIFT 0x1c +#define CP_DDID_CNTL__MODE__SHIFT 0x1e +#define CP_DDID_CNTL__ENABLE__SHIFT 0x1f +#define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define CP_DDID_CNTL__SIZE_MASK 0x00010000L +#define CP_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define CP_DDID_CNTL__VMID_MASK 0x00F00000L +#define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L +#define CP_DDID_CNTL__SCOPE_MASK 0x0C000000L +#define CP_DDID_CNTL__POLICY_MASK 0x30000000L +#define CP_DDID_CNTL__MODE_MASK 0x40000000L +#define CP_DDID_CNTL__ENABLE_MASK 0x80000000L +//CP_GFX_DDID_INFLIGHT_COUNT +#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_WPTR +#define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_RPTR +#define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_DELTA_RPT_COUNT +#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL +//CP_GFX_HPD_STATUS0 +#define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10 +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c +#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d +#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L +#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L +#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L +//CP_GFX_HPD_CONTROL0 +#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0 +#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4 +#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L +#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L +//CP_GFX_HPD_OSPRE_FENCE_ADDR_LO +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_GFX_HPD_OSPRE_FENCE_ADDR_HI +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_GFX_HPD_OSPRE_FENCE_DATA_LO +#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_GFX_HPD_OSPRE_FENCE_DATA_HI +#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_GFX_INDEX_MUTEX +#define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0 +#define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1 +#define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L +#define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL +//CP_ME_PRGRM_CNTR_START_HI +#define CP_ME_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_PFP_INTR_ROUTINE_START_HI +#define CP_PFP_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL +//CP_ME_INTR_ROUTINE_START_HI +#define CP_ME_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL +//CP_GFX_MQD_BASE_ADDR +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_MQD_BASE_ADDR_HI +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L +//CP_GFX_HQD_ACTIVE +#define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_GFX_HQD_VMID +#define CP_GFX_HQD_VMID__VMID__SHIFT 0x0 +#define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL +//CP_GFX_HQD_QUEUE_PRIORITY +#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_GFX_HQD_QUANTUM +#define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3 +#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L +#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L +#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_GFX_HQD_BASE +#define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0 +#define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_GFX_HQD_BASE_HI +#define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_GFX_HQD_RPTR +#define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_GFX_HQD_RPTR_ADDR +#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_HQD_RPTR_ADDR_HI +#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_WPTR_POLL_ADDR_LO +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL +//CP_RB_WPTR_POLL_ADDR_HI +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_DOORBELL_CONTROL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_GFX_HQD_OFFSET +#define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f +#define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L +//CP_GFX_HQD_CNTL +#define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_GFX_HQD_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_GFX_HQD_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10 +#define CP_GFX_HQD_CNTL__SCOPE__SHIFT 0x12 +#define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c +#define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_GFX_HQD_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_GFX_HQD_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_GFX_HQD_CNTL__SCOPE_MASK 0x000C0000L +#define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L +#define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_GFX_HQD_CSMD_RPTR +#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_GFX_HQD_WPTR +#define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_GFX_HQD_WPTR_HI +#define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_GFX_HQD_DEQUEUE_REQUEST +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_GFX_HQD_DEQUEUE_REQUEST__REQ_TYPE__SHIFT 0x1 +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L +#define CP_GFX_HQD_DEQUEUE_REQUEST__REQ_TYPE_MASK 0x0000000EL +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_GFX_HQD_MAPPED +#define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0 +#define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L +//CP_GFX_HQD_QUE_MGR_CONTROL +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT__SHIFT 0x0 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE__SHIFT 0x4 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT__SHIFT 0x5 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN__SHIFT 0x6 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN__SHIFT 0x7 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE__SHIFT 0x8 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE__SHIFT 0xb +#define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE__SHIFT 0xd +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR__SHIFT 0xf +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE__SHIFT 0x10 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE__SHIFT 0x11 +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT__SHIFT 0x12 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG__SHIFT 0x17 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT_MASK 0x00000001L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE_MASK 0x00000010L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT_MASK 0x00000020L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN_MASK 0x00000040L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN_MASK 0x00000080L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_MASK 0x00000700L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE_MASK 0x00000800L +#define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE_MASK 0x00002000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR_MASK 0x00008000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE_MASK 0x00010000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE_MASK 0x00020000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT_MASK 0x00040000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG_MASK 0x00800000L +//CP_GFX_HQD_IQ_TIMER +#define CP_GFX_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define CP_GFX_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_GFX_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_GFX_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define CP_GFX_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_GFX_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_GFX_HQD_HQ_STATUS0 +#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4 +#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6 +#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L +#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L +#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L +#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +//CP_GFX_HQD_HQ_CONTROL0 +#define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0 +#define CP_GFX_HQD_HQ_CONTROL0__SPARES__SHIFT 0x4 +#define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL +#define CP_GFX_HQD_HQ_CONTROL0__SPARES_MASK 0x000000F0L +//CP_GFX_MQD_CONTROL +#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_MQD_CONTROL__SCOPE__SHIFT 0x1a +#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_MQD_CONTROL__SCOPE_MASK 0x0C000000L +//CP_HQD_GFX_CONTROL +#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 +#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf +#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL +#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L +//CP_HQD_GFX_STATUS +#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 +#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL +//CP_DMA_WATCH0_ADDR_LO +#define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH0_ADDR_HI +#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH0_MASK +#define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH0_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH0_CNTL +#define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH1_ADDR_LO +#define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH1_ADDR_HI +#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH1_MASK +#define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH1_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH1_CNTL +#define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH2_ADDR_LO +#define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH2_ADDR_HI +#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH2_MASK +#define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH2_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH2_CNTL +#define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH3_ADDR_LO +#define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH3_ADDR_HI +#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH3_MASK +#define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH3_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH3_CNTL +#define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH_STAT_ADDR_LO +#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_WATCH_STAT_ADDR_HI +#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CP_DMA_WATCH_STAT +#define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0 +#define CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT 0x4 +#define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8 +#define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc +#define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10 +#define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14 +#define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f +#define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH_STAT__QUEUE_ID_MASK 0x00000070L +#define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L +#define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L +#define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L +#define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L +#define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L +//CP_PFP_JT_STAT +#define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0 +#define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10 +#define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L +#define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L +//CP_MEC_JT_STAT +#define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0 +#define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10 +#define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL +#define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L +//CP_CPC_BUSY_HYSTERESIS +#define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY_MASK 0x0000FF00L +//CP_CPF_BUSY_HYSTERESIS1 +#define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY_MASK 0x0000FF00L +#define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY_MASK 0x00FF0000L +#define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L +//CP_CPF_BUSY_HYSTERESIS2 +#define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL +//CP_CPG_BUSY_HYSTERESIS1 +#define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY__SHIFT 0x8 +#define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY__SHIFT 0x10 +#define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 +#define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY_MASK 0x0000FF00L +#define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY_MASK 0x00FF0000L +#define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L +//CP_CPG_BUSY_HYSTERESIS2 +#define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0__SHIFT 0x8 +#define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0_MASK 0x0000FF00L +//CPF_FED_ERROR_ADDR_LO +#define CPF_FED_ERROR_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CPF_FED_ERROR_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CPF_FED_ERROR_ADDR_HI +#define CPF_FED_ERROR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPF_FED_ERROR_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CPC_FED_ERROR_ADDR_LO +#define CPC_FED_ERROR_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CPC_FED_ERROR_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CPC_FED_ERROR_ADDR_HI +#define CPC_FED_ERROR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPC_FED_ERROR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CPG_FED_ERROR_ADDR_LO +#define CPG_FED_ERROR_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CPG_FED_ERROR_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CPG_FED_ERROR_ADDR_HI +#define CPG_FED_ERROR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPG_FED_ERROR_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CP_RB_DOORBELL_CLEAR +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L +//CP_RB0_ACTIVE +#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_ACTIVE +#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_STATUS +#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CPG_RCIU_CAM_INDEX +#define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0 +#define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL +//CPG_RCIU_CAM_DATA +#define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE0 +#define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18 +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19 +#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f +#define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L +#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L +//CPG_RCIU_CAM_DATA_PHASE1 +#define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE2 +#define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE3 +#define CPG_RCIU_CAM_DATA_PHASE3__ADDR_HI__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE3__ADDR_HI_MASK 0x000FFFFFL +//CP_GPU_TIMESTAMP_OFFSET_LO +#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT 0x0 +#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK 0xFFFFFFFFL +//CP_GPU_TIMESTAMP_OFFSET_HI +#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT 0x0 +#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK 0xFFFFFFFFL +//CP_SDMA_DMA_DONE +#define CP_SDMA_DMA_DONE__SDMA_ID__SHIFT 0x0 +#define CP_SDMA_DMA_DONE__SDMA_ID_MASK 0x0000000FL +//CP_PFP_SDMA_CS +#define CP_PFP_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 +#define CP_PFP_SDMA_CS__SDMA_ID__SHIFT 0x4 +#define CP_PFP_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 +#define CP_PFP_SDMA_CS__SDMA_COUNT__SHIFT 0xc +#define CP_PFP_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L +#define CP_PFP_SDMA_CS__SDMA_ID_MASK 0x000000F0L +#define CP_PFP_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L +#define CP_PFP_SDMA_CS__SDMA_COUNT_MASK 0x00003000L +//CP_ME_SDMA_CS +#define CP_ME_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 +#define CP_ME_SDMA_CS__SDMA_ID__SHIFT 0x4 +#define CP_ME_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 +#define CP_ME_SDMA_CS__SDMA_COUNT__SHIFT 0xc +#define CP_ME_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L +#define CP_ME_SDMA_CS__SDMA_ID_MASK 0x000000F0L +#define CP_ME_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L +#define CP_ME_SDMA_CS__SDMA_COUNT_MASK 0x00003000L +//CPF_GCR_CNTL +#define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0 +#define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL +//CPG_UTCL1_STATUS +#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPC_UTCL1_STATUS +#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPF_UTCL1_STATUS +#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CP_SD_CNTL +#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 +#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 +#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 +#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 +#define CP_SD_CNTL__GE_EN__SHIFT 0x5 +#define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6 +#define CP_SD_CNTL__EA_EN__SHIFT 0x9 +#define CP_SD_CNTL__SDMA_EN__SHIFT 0xa +#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f +#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L +#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L +#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L +#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L +#define CP_SD_CNTL__GE_EN_MASK 0x00000020L +#define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L +#define CP_SD_CNTL__EA_EN_MASK 0x00000200L +#define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L +#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L +//CP_SOFT_RESET_CNTL +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 +#define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET__SHIFT 0x7 +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L +#define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET_MASK 0x00000080L +//CP_CPC_GFX_CNTL +#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 +#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 +#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 +#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 +#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L +#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L +#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L +#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpphqddec +//CP_HPD_UTCL1_CNTL +#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 +#define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT 0xa +#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL +#define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT_MASK 0x00000400L +//CP_HPD_UTCL1_ERROR +#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 +#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x1b +#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x1c +#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x01FFFFFFL +#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x08000000L +#define CP_HPD_UTCL1_ERROR__VMID_MASK 0xF0000000L +//CP_HPD_UTCL1_ERROR_ADDR +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L +//CP_MQD_BASE_ADDR +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_MQD_BASE_ADDR_HI +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_ACTIVE +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L +//CP_HQD_VMID +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_VMID__VMID_MASK 0x0000000FL +#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L +#define CP_HQD_VMID__VQID_MASK 0x03FF0000L +//CP_HQD_PERSISTENT_STATE +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE__SHIFT 0x1 +#define CP_HQD_PERSISTENT_STATE__WGS_QUEUE__SHIFT 0x4 +#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT__SHIFT 0x12 +#define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS__SHIFT 0x13 +#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14 +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L +#define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE_MASK 0x00000002L +#define CP_HQD_PERSISTENT_STATE__WGS_QUEUE_MASK 0x00000010L +#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L +#define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT_MASK 0x00040000L +#define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS_MASK 0x00080000L +#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L +//CP_HQD_PIPE_PRIORITY +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L +//CP_HQD_QUEUE_PRIORITY +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_HQD_QUANTUM +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_HQD_PQ_BASE +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_PQ_BASE_HI +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x0001FFFFL +//CP_HQD_PQ_RPTR +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_RPTR_REPORT_ADDR +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_PQ_RPTR_REPORT_ADDR_HI +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_PQ_WPTR_POLL_ADDR +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L +//CP_HQD_PQ_WPTR_POLL_ADDR_HI +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_PQ_DOORBELL_CONTROL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_HQD_PQ_CONTROL +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 +#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe +#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__SCOPE__SHIFT 0x10 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 +#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL +#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L +#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L +#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L +#define CP_HQD_PQ_CONTROL__SCOPE_MASK 0x00030000L +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L +#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L +#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L +//CP_HQD_IB_BASE_ADDR +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_IB_BASE_ADDR_HI +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_IB_RPTR +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL +//CP_HQD_IB_CONTROL +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__IB_SCOPE__SHIFT 0x1a +#define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT 0x1e +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_IB_CONTROL__IB_SCOPE_MASK 0x0C000000L +#define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK 0x40000000L +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L +//CP_HQD_IQ_TIMER +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_HQD_IQ_RPTR +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL +//CP_HQD_DEQUEUE_REQUEST +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_HQD_DMA_OFFLOAD +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_OFFLOAD +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_MSG_TYPE +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L +//CP_HQD_ATOMIC0_PREOP_LO +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC0_PREOP_HI +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_LO +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_HI +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER0 +#define CP_HQD_HQ_SCHEDULER0__CWSR__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS__SHIFT 0x1 +#define CP_HQD_HQ_SCHEDULER0__RSRV__SHIFT 0x2 +#define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE__SHIFT 0x3 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID__SHIFT 0x9 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS__SHIFT 0xd +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_DEBUG_EN__SHIFT 0xe +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED__SHIFT 0xf +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED__SHIFT 0x14 +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE__SHIFT 0x15 +#define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_SCHEDULER0__CWSR_MASK 0x00000001L +#define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS_MASK 0x00000002L +#define CP_HQD_HQ_SCHEDULER0__RSRV_MASK 0x00000004L +#define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE_MASK 0x00000038L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x00000040L +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID_MASK 0x00000200L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS_MASK 0x00002000L +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_DEBUG_EN_MASK 0x00004000L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED_MASK 0x00100000L +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE_MASK 0x00600000L +#define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_STATUS0 +#define CP_HQD_HQ_STATUS0__CWSR__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__SAVE_STATUS__SHIFT 0x1 +#define CP_HQD_HQ_STATUS0__RSRV__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__STATIC_QUEUE__SHIFT 0x3 +#define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__C_INHERIT_VMID__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa +#define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS__SHIFT 0xd +#define CP_HQD_HQ_STATUS0__C_QUEUE_DEBUG_EN__SHIFT 0xe +#define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED__SHIFT 0xf +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED__SHIFT 0x14 +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE__SHIFT 0x15 +#define CP_HQD_HQ_STATUS0__DFWX_QUEUE_SUPPORTED__SHIFT 0x17 +#define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 +#define CP_HQD_HQ_STATUS0__PLATFORM_ATOMICS_SUPPORTED__SHIFT 0x1d +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_STATUS0__CWSR_MASK 0x00000001L +#define CP_HQD_HQ_STATUS0__SAVE_STATUS_MASK 0x00000002L +#define CP_HQD_HQ_STATUS0__RSRV_MASK 0x00000004L +#define CP_HQD_HQ_STATUS0__STATIC_QUEUE_MASK 0x00000038L +#define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE_MASK 0x00000040L +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_STATUS0__C_INHERIT_VMID_MASK 0x00000200L +#define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L +#define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS_MASK 0x00002000L +#define CP_HQD_HQ_STATUS0__C_QUEUE_DEBUG_EN_MASK 0x00004000L +#define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED_MASK 0x00100000L +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE_MASK 0x00600000L +#define CP_HQD_HQ_STATUS0__DFWX_QUEUE_SUPPORTED_MASK 0x00800000L +#define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L +#define CP_HQD_HQ_STATUS0__PLATFORM_ATOMICS_SUPPORTED_MASK 0x20000000L +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_CONTROL0 +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER1 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL +//CP_MQD_CONTROL +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__SCOPE__SHIFT 0x1a +#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_MQD_CONTROL__SCOPE_MASK 0x0C000000L +//CP_HQD_HQ_STATUS1 +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL +//CP_HQD_HQ_CONTROL1 +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR_HI +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0001FFFFL +//CP_HQD_EOP_CONTROL +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__SCOPE__SHIFT 0x13 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 +#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L +#define CP_HQD_EOP_CONTROL__SCOPE_MASK 0x00180000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L +#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L +//CP_HQD_EOP_RPTR +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L +//CP_HQD_EOP_WPTR +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L +//CP_HQD_EOP_EVENTS +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__RESTORE_EOP__SHIFT 0xf +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL +#define CP_HQD_EOP_EVENTS__RESTORE_EOP_MASK 0x00008000L +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L +//CP_HQD_CTX_SAVE_BASE_ADDR_LO +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CP_HQD_CTX_SAVE_BASE_ADDR_HI +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_CTX_SAVE_CONTROL +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CTX_SAVE_CONTROL__SCOPE__SHIFT 0x8 +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define CP_HQD_CTX_SAVE_CONTROL__SCOPE_MASK 0x00000300L +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CP_HQD_CNTL_STACK_OFFSET +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_CNTL_STACK_SIZE +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CP_HQD_WG_STATE_OFFSET +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CP_HQD_CTX_SAVE_SIZE +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//CP_HQD_GDS_RESOURCE_STATE +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L +//CP_HQD_ERROR +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 +#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 +#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 +#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa +#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc +#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 +#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 +#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 +#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L +#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L +#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L +#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L +#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L +#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L +#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L +#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L +#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L +//CP_HQD_EOP_WPTR_MEM +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL +//CP_HQD_AQL_CONTROL +#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf +#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 +#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f +#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL +#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L +#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L +#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L +//CP_HQD_PQ_WPTR_LO +#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_WPTR_HI +#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL +//CP_HQD_SUSPEND_CNTL_STACK_OFFSET +#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_SUSPEND_CNTL_STACK_DW_CNT +#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0 +#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00003FFFL +//CP_HQD_SUSPEND_WG_STATE_OFFSET +#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CP_HQD_DDID_RPTR +#define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL +//CP_HQD_DDID_WPTR +#define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL +//CP_HQD_DDID_INFLIGHT_COUNT +#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 +#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL +//CP_HQD_DDID_DELTA_RPT_COUNT +#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 +#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL +//CP_HQD_DEQUEUE_STATUS +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0 +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L +//CP_HQD_AQL_CONTROL_1 +#define CP_HQD_AQL_CONTROL_1__RESERVED__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL_1__RESERVED_MASK 0xFFFFFFFFL +//CP_HQD_AQL_DISPATCH_ID +#define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_AQL_DISPATCH_ID_HI +#define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_KD_BASE +#define CP_HQD_KD_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_KD_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_KD_BASE_HI +#define CP_HQD_KD_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_KD_BASE_HI__ADDR_HI_MASK 0x0001FFFFL +//CP_HQD_KD_CNTL +#define CP_HQD_KD_CNTL__KD_SIZE__SHIFT 0x0 +#define CP_HQD_KD_CNTL__KD_FETCHER_ENABLE__SHIFT 0x10 +#define CP_HQD_KD_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_KD_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_KD_CNTL__SCOPE__SHIFT 0x1a +#define CP_HQD_KD_CNTL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_KD_CNTL__KD_SIZE_MASK 0x00000003L +#define CP_HQD_KD_CNTL__KD_FETCHER_ENABLE_MASK 0x00010000L +#define CP_HQD_KD_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_KD_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_KD_CNTL__SCOPE_MASK 0x0C000000L +#define CP_HQD_KD_CNTL__PRIV_STATE_MASK 0x40000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxdec0 +//COHER_DEST_BASE_HI_0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_1 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_2 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_3 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL +//CP_PERFMON_CNTX_CNTL +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +//CP_PIPEID +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x00000003L +//CP_RINGID +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_RINGID__RINGID_MASK 0x00000003L +//CP_VMID +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0x0000000FL +//CONTEXT_RESERVED_REG0 +#define CONTEXT_RESERVED_REG0__DATA__SHIFT 0x0 +#define CONTEXT_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//CONTEXT_RESERVED_REG1 +#define CONTEXT_RESERVED_REG1__DATA__SHIFT 0x0 +#define CONTEXT_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL +//GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//VGT_DMA_BASE_HI +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL +//VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL +//VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L +//VGT_EVENT_ADDRESS_REG +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL +//VGT_HOS_MAX_TESS_LEVEL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_MIN_TESS_LEVEL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL +//GE_IA_ENHANCE +#define GE_IA_ENHANCE__MISC__SHIFT 0x0 +#define GE_IA_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_DMA_MAX_SIZE +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL +//VGT_DMA_INDEX_TYPE +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb +#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe +#define VGT_DMA_INDEX_TYPE__TEMPORAL__SHIFT 0xf +#define VGT_DMA_INDEX_TYPE__SPEC_DATA_READ__SHIFT 0x11 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L +#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L +#define VGT_DMA_INDEX_TYPE__TEMPORAL_MASK 0x00018000L +#define VGT_DMA_INDEX_TYPE__SPEC_DATA_READ_MASK 0x00060000L +//GE_WD_ENHANCE +#define GE_WD_ENHANCE__MISC__SHIFT 0x0 +#define GE_WD_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_NUM_INSTANCES +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//VGT_SHADER_STAGES_EN +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 +#define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15 +#define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16 +#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18 +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG__SHIFT 0x1a +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L +#define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L +#define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L +#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG_MASK 0x04000000L +//VGT_TF_PARAM +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__TEMPORAL__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13 +#define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14 +#define VGT_TF_PARAM__MTYPE__SHIFT 0x17 +#define VGT_TF_PARAM__SPEC_DATA_READ__SHIFT 0x1c +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__TEMPORAL_MASK 0x00018000L +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L +#define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L +#define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L +#define VGT_TF_PARAM__MTYPE_MASK 0x03800000L +#define VGT_TF_PARAM__SPEC_DATA_READ_MASK 0x30000000L +//VGT_STRMOUT_DRAW_OPAQUE_OFFSET +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL +//VGT_TESS_DISTRIBUTION +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L +//VGT_LS_HS_CONFIG +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_cpdec +//CONFIG_RESERVED_REG0 +#define CONFIG_RESERVED_REG0__DATA__SHIFT 0x0 +#define CONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//CONFIG_RESERVED_REG1 +#define CONFIG_RESERVED_REG1__DATA__SHIFT 0x0 +#define CONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//CP_MEC_CNTL +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L +//CP_ME_CNTL +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__PFP_PIPE0_DISABLE__SHIFT 0xc +#define CP_ME_CNTL__PFP_PIPE1_DISABLE__SHIFT 0xd +#define CP_ME_CNTL__ME_PIPE0_DISABLE__SHIFT 0xe +#define CP_ME_CNTL__ME_PIPE1_DISABLE__SHIFT 0xf +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__PFP_PIPE0_DISABLE_MASK 0x00001000L +#define CP_ME_CNTL__PFP_PIPE1_DISABLE_MASK 0x00002000L +#define CP_ME_CNTL__ME_PIPE0_DISABLE_MASK 0x00004000L +#define CP_ME_CNTL__ME_PIPE1_DISABLE_MASK 0x00008000L +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L +#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L +#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L +#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +//CP_UNMAPPED_QUEUE0 +#define CP_UNMAPPED_QUEUE0__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE0__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE1 +#define CP_UNMAPPED_QUEUE1__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE1__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE2 +#define CP_UNMAPPED_QUEUE2__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE2__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE3 +#define CP_UNMAPPED_QUEUE3__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE3__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE4 +#define CP_UNMAPPED_QUEUE4__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE4__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE5 +#define CP_UNMAPPED_QUEUE5__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE5__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE6 +#define CP_UNMAPPED_QUEUE6__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE6__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE7 +#define CP_UNMAPPED_QUEUE7__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE7__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE8 +#define CP_UNMAPPED_QUEUE8__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE8__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE9 +#define CP_UNMAPPED_QUEUE9__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE9__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE10 +#define CP_UNMAPPED_QUEUE10__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE10__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE11 +#define CP_UNMAPPED_QUEUE11__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE11__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE12 +#define CP_UNMAPPED_QUEUE12__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE12__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE13 +#define CP_UNMAPPED_QUEUE13__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE13__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE14 +#define CP_UNMAPPED_QUEUE14__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE14__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE15 +#define CP_UNMAPPED_QUEUE15__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE15__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE16 +#define CP_UNMAPPED_QUEUE16__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE16__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE17 +#define CP_UNMAPPED_QUEUE17__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE17__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE18 +#define CP_UNMAPPED_QUEUE18__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE18__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE19 +#define CP_UNMAPPED_QUEUE19__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE19__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE20 +#define CP_UNMAPPED_QUEUE20__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE20__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE21 +#define CP_UNMAPPED_QUEUE21__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE21__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE22 +#define CP_UNMAPPED_QUEUE22__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE22__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE23 +#define CP_UNMAPPED_QUEUE23__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE23__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE24 +#define CP_UNMAPPED_QUEUE24__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE24__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE25 +#define CP_UNMAPPED_QUEUE25__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE25__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE26 +#define CP_UNMAPPED_QUEUE26__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE26__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE27 +#define CP_UNMAPPED_QUEUE27__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE27__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE28 +#define CP_UNMAPPED_QUEUE28__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE28__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE29 +#define CP_UNMAPPED_QUEUE29__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE29__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE30 +#define CP_UNMAPPED_QUEUE30__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE30__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE31 +#define CP_UNMAPPED_QUEUE31__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE31__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE32 +#define CP_UNMAPPED_QUEUE32__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE32__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE33 +#define CP_UNMAPPED_QUEUE33__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE33__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE34 +#define CP_UNMAPPED_QUEUE34__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE34__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE35 +#define CP_UNMAPPED_QUEUE35__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE35__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE36 +#define CP_UNMAPPED_QUEUE36__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE36__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE37 +#define CP_UNMAPPED_QUEUE37__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE37__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE38 +#define CP_UNMAPPED_QUEUE38__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE38__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE39 +#define CP_UNMAPPED_QUEUE39__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE39__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE40 +#define CP_UNMAPPED_QUEUE40__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE40__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE41 +#define CP_UNMAPPED_QUEUE41__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE41__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE42 +#define CP_UNMAPPED_QUEUE42__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE42__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE43 +#define CP_UNMAPPED_QUEUE43__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE43__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE44 +#define CP_UNMAPPED_QUEUE44__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE44__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE45 +#define CP_UNMAPPED_QUEUE45__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE45__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE46 +#define CP_UNMAPPED_QUEUE46__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE46__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE47 +#define CP_UNMAPPED_QUEUE47__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE47__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE48 +#define CP_UNMAPPED_QUEUE48__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE48__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE49 +#define CP_UNMAPPED_QUEUE49__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE49__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE50 +#define CP_UNMAPPED_QUEUE50__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE50__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE51 +#define CP_UNMAPPED_QUEUE51__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE51__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE52 +#define CP_UNMAPPED_QUEUE52__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE52__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE53 +#define CP_UNMAPPED_QUEUE53__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE53__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE54 +#define CP_UNMAPPED_QUEUE54__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE54__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE55 +#define CP_UNMAPPED_QUEUE55__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE55__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE56 +#define CP_UNMAPPED_QUEUE56__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE56__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE57 +#define CP_UNMAPPED_QUEUE57__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE57__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE58 +#define CP_UNMAPPED_QUEUE58__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE58__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE59 +#define CP_UNMAPPED_QUEUE59__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE59__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE60 +#define CP_UNMAPPED_QUEUE60__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE60__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE61 +#define CP_UNMAPPED_QUEUE61__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE61__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE62 +#define CP_UNMAPPED_QUEUE62__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE62__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE63 +#define CP_UNMAPPED_QUEUE63__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE63__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_DOORBELL +#define CP_UNMAPPED_DOORBELL__ENABLE__SHIFT 0x0 +#define CP_UNMAPPED_DOORBELL__DBELL_MSG_BLOCK__SHIFT 0x1 +#define CP_UNMAPPED_DOORBELL__CLEAR_ALL__SHIFT 0x2 +#define CP_UNMAPPED_DOORBELL__QUEUE_LSB__SHIFT 0x4 +#define CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT 0x8 +#define CP_UNMAPPED_DOORBELL__ENABLE_MASK 0x00000001L +#define CP_UNMAPPED_DOORBELL__DBELL_MSG_BLOCK_MASK 0x00000002L +#define CP_UNMAPPED_DOORBELL__CLEAR_ALL_MASK 0x00000004L +#define CP_UNMAPPED_DOORBELL__QUEUE_LSB_MASK 0x000000F0L +#define CP_UNMAPPED_DOORBELL__PROC_LSB_MASK 0x00001F00L +//CP_UNMAPPED_QUEUE_BANK0 +#define CP_UNMAPPED_QUEUE_BANK0__BANK_HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE_BANK0__BANK_HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE_BANK1 +#define CP_UNMAPPED_QUEUE_BANK1__BANK_HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE_BANK1__BANK_HIT_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_grbmdec +//GRBM_GFX_CNTL +#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL__CTXID__SHIFT 0xb +#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L +#define GRBM_GFX_CNTL__CTXID_MASK 0x00003800L +//GRBM_NOWHERE +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpdec +//CP_FETCHER_SOURCE +#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 +#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L +//CP_DFY_CNTL +#define CP_DFY_CNTL__SCOPE__SHIFT 0x6 +#define CP_DFY_CNTL__POLICY__SHIFT 0x8 +#define CP_DFY_CNTL__MTYPE__SHIFT 0xc +#define CP_DFY_CNTL__SPEC_DATA_READ__SHIFT 0xf +#define CP_DFY_CNTL__REPEATER_FGCG_DISABLE__SHIFT 0x19 +#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a +#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c +#define CP_DFY_CNTL__MODE__SHIFT 0x1d +#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f +#define CP_DFY_CNTL__SCOPE_MASK 0x000000C0L +#define CP_DFY_CNTL__POLICY_MASK 0x00000300L +#define CP_DFY_CNTL__MTYPE_MASK 0x00003000L +#define CP_DFY_CNTL__SPEC_DATA_READ_MASK 0x00018000L +#define CP_DFY_CNTL__REPEATER_FGCG_DISABLE_MASK 0x02000000L +#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L +#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L +#define CP_DFY_CNTL__MODE_MASK 0x60000000L +#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L +//CP_DFY_STAT +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL +#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L +#define CP_DFY_STAT__BUSY_MASK 0x80000000L +//CP_DFY_ADDR_HI +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_DFY_ADDR_LO +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CP_DFY_DATA_0 +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_1 +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_2 +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_3 +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_4 +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_5 +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_6 +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_7 +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_8 +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_9 +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_10 +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_11 +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_12 +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_13 +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_14 +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_15 +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL +//CP_DFY_CMD +#define CP_DFY_CMD__SIZE__SHIFT 0x10 +#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpphqddec +//CP_HPD_MES_ROQ_OFFSETS +#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L +//CP_HPD_ROQ_OFFSETS +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_ROQ_OFFSETS__KD_OFFSET__SHIFT 0x18 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L +#define CP_HPD_ROQ_OFFSETS__KD_OFFSET_MASK 0xFF000000L +//CP_HPD_STATUS0 +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 +#define CP_HPD_STATUS0__ENABLE_MSG_NO_DISC__SHIFT 0x13 +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c +#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e +#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L +#define CP_HPD_STATUS0__ENABLE_MSG_NO_DISC_MASK 0x00080000L +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L +#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L +#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gcrdec +//GCR_GENERAL_CNTL +#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0 +#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1 +#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2 +#define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3 +#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4 +#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6 +#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7 +#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8 +#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9 +#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa +#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd +#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe +#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf +#define GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT 0x10 +#define GCR_GENERAL_CNTL__UTCL2_REQ_LIMIT__SHIFT 0x11 +#define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14 +#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L +#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L +#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L +#define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L +#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L +#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L +#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L +#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L +#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L +#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L +#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L +#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L +#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L +#define GCR_GENERAL_CNTL__DISABLE_FGCG_MASK 0x00010000L +#define GCR_GENERAL_CNTL__UTCL2_REQ_LIMIT_MASK 0x000E0000L +#define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L +//GCR_TARGET_DISABLE +#define GCR_TARGET_DISABLE__DISABLE_SE0_PHY__SHIFT 0x0 +#define GCR_TARGET_DISABLE__DISABLE_SE0_VIRT__SHIFT 0x1 +#define GCR_TARGET_DISABLE__DISABLE_SE1_PHY__SHIFT 0x2 +#define GCR_TARGET_DISABLE__DISABLE_SE1_VIRT__SHIFT 0x3 +#define GCR_TARGET_DISABLE__DISABLE_SE2_PHY__SHIFT 0x4 +#define GCR_TARGET_DISABLE__DISABLE_SE2_VIRT__SHIFT 0x5 +#define GCR_TARGET_DISABLE__DISABLE_SE3_PHY__SHIFT 0x6 +#define GCR_TARGET_DISABLE__DISABLE_SE3_VIRT__SHIFT 0x7 +#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT 0x8 +#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT 0x9 +#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0xa +#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT 0xb +#define GCR_TARGET_DISABLE__SE0_INACTIVE_STATUS__SHIFT 0x10 +#define GCR_TARGET_DISABLE__SE1_INACTIVE_STATUS__SHIFT 0x11 +#define GCR_TARGET_DISABLE__SE2_INACTIVE_STATUS__SHIFT 0x12 +#define GCR_TARGET_DISABLE__SE3_INACTIVE_STATUS__SHIFT 0x13 +#define GCR_TARGET_DISABLE__GL2A0_DISABLE_STATUS__SHIFT 0x18 +#define GCR_TARGET_DISABLE__GL2A1_DISABLE_STATUS__SHIFT 0x19 +#define GCR_TARGET_DISABLE__GL2A2_DISABLE_STATUS__SHIFT 0x1a +#define GCR_TARGET_DISABLE__GL2A3_DISABLE_STATUS__SHIFT 0x1b +#define GCR_TARGET_DISABLE__DISABLE_SE0_PHY_MASK 0x00000001L +#define GCR_TARGET_DISABLE__DISABLE_SE0_VIRT_MASK 0x00000002L +#define GCR_TARGET_DISABLE__DISABLE_SE1_PHY_MASK 0x00000004L +#define GCR_TARGET_DISABLE__DISABLE_SE1_VIRT_MASK 0x00000008L +#define GCR_TARGET_DISABLE__DISABLE_SE2_PHY_MASK 0x00000010L +#define GCR_TARGET_DISABLE__DISABLE_SE2_VIRT_MASK 0x00000020L +#define GCR_TARGET_DISABLE__DISABLE_SE3_PHY_MASK 0x00000040L +#define GCR_TARGET_DISABLE__DISABLE_SE3_VIRT_MASK 0x00000080L +#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK 0x00000100L +#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK 0x00000200L +#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK 0x00000400L +#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK 0x00000800L +#define GCR_TARGET_DISABLE__SE0_INACTIVE_STATUS_MASK 0x00010000L +#define GCR_TARGET_DISABLE__SE1_INACTIVE_STATUS_MASK 0x00020000L +#define GCR_TARGET_DISABLE__SE2_INACTIVE_STATUS_MASK 0x00040000L +#define GCR_TARGET_DISABLE__SE3_INACTIVE_STATUS_MASK 0x00080000L +#define GCR_TARGET_DISABLE__GL2A0_DISABLE_STATUS_MASK 0x01000000L +#define GCR_TARGET_DISABLE__GL2A1_DISABLE_STATUS_MASK 0x02000000L +#define GCR_TARGET_DISABLE__GL2A2_DISABLE_STATUS_MASK 0x04000000L +#define GCR_TARGET_DISABLE__GL2A3_DISABLE_STATUS_MASK 0x08000000L +//GCR_CMD_STATUS +#define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0 +#define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x13 +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17 +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18 +#define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c +#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e +#define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f +#define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL +#define GCR_CMD_STATUS__GCR_SRC_MASK 0x00780000L +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L +#define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L +#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L +#define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L +//GCR_SPARE +#define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1 +#define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2 +#define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3 +#define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4 +#define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5 +#define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6 +#define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define GCR_SPARE__UTCL2_REQ_CREDIT__SHIFT 0x8 +#define GCR_SPARE__GCRD_GL2A_REQ_CREDIT__SHIFT 0x10 +#define GCR_SPARE__GCRD_SE_REQ_CREDIT__SHIFT 0x14 +#define GCR_SPARE__SPARE_BIT_31_24__SHIFT 0x18 +#define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L +#define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L +#define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L +#define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L +#define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L +#define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L +#define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define GCR_SPARE__UTCL2_REQ_CREDIT_MASK 0x0000FF00L +#define GCR_SPARE__GCRD_GL2A_REQ_CREDIT_MASK 0x000F0000L +#define GCR_SPARE__GCRD_SE_REQ_CREDIT_MASK 0x00F00000L +#define GCR_SPARE__SPARE_BIT_31_24_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxudec +//CP_EOP_DONE_ADDR_LO +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_EOP_DONE_ADDR_HI +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_EOP_DONE_DATA_LO +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_EOP_DONE_DATA_HI +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_LO +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_HI +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_ADDR_LO +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL +//CP_PIPE_STATS_ADDR_HI +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL +//CP_VGT_IAVERT_COUNT_LO +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAVERT_COUNT_HI +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_LO +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_HI +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_LO +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_HI +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_LO +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_HI +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_LO +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_HI +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_LO +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_HI +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_LO +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_HI +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_LO +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_HI +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_LO +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_HI +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_LO +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_HI +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_LO +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_HI +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_LO +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_HI +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_ASINVOC_COUNT_LO +#define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_ASINVOC_COUNT_HI +#define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_CONTROL +#define CP_PIPE_STATS_CONTROL__SCOPE__SHIFT 0x17 +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__SCOPE_MASK 0x01800000L +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L +//SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//SCRATCH_REG_ATOMIC +#define SCRATCH_REG_ATOMIC__IMMED__SHIFT 0x0 +#define SCRATCH_REG_ATOMIC__ID__SHIFT 0x18 +#define SCRATCH_REG_ATOMIC__reserved27__SHIFT 0x1b +#define SCRATCH_REG_ATOMIC__OP__SHIFT 0x1c +#define SCRATCH_REG_ATOMIC__reserved31__SHIFT 0x1f +#define SCRATCH_REG_ATOMIC__IMMED_MASK 0x00FFFFFFL +#define SCRATCH_REG_ATOMIC__ID_MASK 0x07000000L +#define SCRATCH_REG_ATOMIC__reserved27_MASK 0x08000000L +#define SCRATCH_REG_ATOMIC__OP_MASK 0x70000000L +#define SCRATCH_REG_ATOMIC__reserved31_MASK 0x80000000L +//SCRATCH_REG_CMPSWAP_ATOMIC +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT 0x0 +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT 0xc +#define SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT 0x18 +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT 0x1b +#define SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT 0x1c +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT 0x1f +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK 0x00000FFFL +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK 0x00FFF000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK 0x07000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK 0x08000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK 0x70000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK 0x80000000L +//CP_APPEND_DDID_CNT +#define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0 +#define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL +//CP_APPEND_DATA_HI +#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_HI +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_HI +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_LO +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_HI +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_APPEND_ADDR_LO +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_ADDR_HI +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__FENCE_SIZE__SHIFT 0x12 +#define CP_APPEND_ADDR_HI__PWS_ENABLE__SHIFT 0x13 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__SCOPE__SHIFT 0x1b +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L +#define CP_APPEND_ADDR_HI__FENCE_SIZE_MASK 0x00040000L +#define CP_APPEND_ADDR_HI__PWS_ENABLE_MASK 0x00080000L +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L +#define CP_APPEND_ADDR_HI__SCOPE_MASK 0x18000000L +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L +//CP_APPEND_DATA +#define CP_APPEND_DATA__DATA__SHIFT 0x0 +#define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_DATA_LO +#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_LO +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_LO +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_LO +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_LO +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_HI +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_HI +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_WADDR_LO +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_WADDR_HI +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__WRITE_CONFIRM__SHIFT 0x11 +#define CP_ME_MC_WADDR_HI__WRITE64__SHIFT 0x12 +#define CP_ME_MC_WADDR_HI__SCOPE__SHIFT 0x14 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WADDR_HI__VMID__SHIFT 0x18 +#define CP_ME_MC_WADDR_HI__RINGID__SHIFT 0x1c +#define CP_ME_MC_WADDR_HI__PRIVILEGE__SHIFT 0x1f +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_WADDR_HI__WRITE_CONFIRM_MASK 0x00020000L +#define CP_ME_MC_WADDR_HI__WRITE64_MASK 0x00040000L +#define CP_ME_MC_WADDR_HI__SCOPE_MASK 0x00300000L +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L +#define CP_ME_MC_WADDR_HI__VMID_MASK 0x0F000000L +#define CP_ME_MC_WADDR_HI__RINGID_MASK 0x30000000L +#define CP_ME_MC_WADDR_HI__PRIVILEGE_MASK 0x80000000L +//CP_ME_MC_WDATA_LO +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL +//CP_ME_MC_WDATA_HI +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_RADDR_LO +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_RADDR_HI +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__SIZE__SHIFT 0x10 +#define CP_ME_MC_RADDR_HI__SCOPE__SHIFT 0x14 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_RADDR_HI__VMID__SHIFT 0x18 +#define CP_ME_MC_RADDR_HI__PRIVILEGE__SHIFT 0x1f +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_RADDR_HI__SIZE_MASK 0x000F0000L +#define CP_ME_MC_RADDR_HI__SCOPE_MASK 0x00300000L +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L +#define CP_ME_MC_RADDR_HI__VMID_MASK 0x0F000000L +#define CP_ME_MC_RADDR_HI__PRIVILEGE_MASK 0x80000000L +//CP_WAIT_REG_MEM_TIMEOUT +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL +//CP_DMA_PFP_CONTROL +#define CP_DMA_PFP_CONTROL__VMID__SHIFT 0x0 +#define CP_DMA_PFP_CONTROL__TMZ__SHIFT 0x4 +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__SRC_SCOPE__SHIFT 0xf +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__DST_SCOPE__SHIFT 0x1b +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_CONTROL__VMID_MASK 0x0000000FL +#define CP_DMA_PFP_CONTROL__TMZ_MASK 0x00000010L +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L +#define CP_DMA_PFP_CONTROL__SRC_SCOPE_MASK 0x00018000L +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L +#define CP_DMA_PFP_CONTROL__DST_SCOPE_MASK 0x18000000L +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_CONTROL +#define CP_DMA_ME_CONTROL__VMID__SHIFT 0x0 +#define CP_DMA_ME_CONTROL__TMZ__SHIFT 0x4 +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__SRC_SCOPE__SHIFT 0xf +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__DST_SCOPE__SHIFT 0x1b +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_CONTROL__VMID_MASK 0x0000000FL +#define CP_DMA_ME_CONTROL__TMZ_MASK 0x00000010L +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L +#define CP_DMA_ME_CONTROL__SRC_SCOPE_MASK 0x00018000L +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L +#define CP_DMA_ME_CONTROL__DST_SCOPE_MASK 0x18000000L +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_SRC_ADDR +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_SRC_ADDR_HI +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_TYPE__SHIFT 0x1b +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_VMID__SHIFT 0x1c +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_TYPE_MASK 0x08000000L +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_VMID_MASK 0xF0000000L +//CP_DMA_ME_DST_ADDR +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_DST_ADDR_HI +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_TYPE__SHIFT 0x1b +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_VMID__SHIFT 0x1c +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_TYPE_MASK 0x08000000L +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_VMID_MASK 0xF0000000L +//CP_DMA_ME_COMMAND +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_PFP_SRC_ADDR +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_SRC_ADDR_HI +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_DST_ADDR +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_DST_ADDR_HI +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_COMMAND +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_CNTL +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 +#define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__SPECULATIVE_DATA_READ__SHIFT 0x6 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L +#define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__SPECULATIVE_DATA_READ_MASK 0x000000C0L +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L +//CP_DMA_READ_TAGS +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +//CP_PFP_IB_CONTROL +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL +//CP_PFP_LOAD_CONTROL +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL__SHIFT 0x1f +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +#define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL_MASK 0x80000000L +//CP_SCRATCH_INDEX +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_SCRATCH_DATA +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_RB_OFFSET +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_IB1_OFFSET +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_IB2_OFFSET +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_BEGIN +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_END +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_BEGIN +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_END +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL +//CP_DMA_ME_CMD_ADDR_LO +#define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_ME_CMD_ADDR_HI +#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_PFP_CMD_ADDR_LO +#define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_PFP_CMD_ADDR_HI +#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L +//UCONFIG_RESERVED_REG0 +#define UCONFIG_RESERVED_REG0__DATA__SHIFT 0x0 +#define UCONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//UCONFIG_RESERVED_REG1 +#define UCONFIG_RESERVED_REG1__DATA__SHIFT 0x0 +#define UCONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//CP_PA_MSPRIM_COUNT_LO +#define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_MSPRIM_COUNT_HI +#define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_GE_MSINVOC_COUNT_LO +#define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_GE_MSINVOC_COUNT_HI +#define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_IB1_CMD_BUFSZ +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB2_CMD_BUFSZ +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_ST_CMD_BUFSZ +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB1_BASE_LO +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB1_BASE_HI +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_IB2_BASE_LO +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB2_BASE_HI +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_ST_BASE_LO +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL +//CP_ST_BASE_HI +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL +//CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL +//CP_EOP_DONE_EVENT_CNTL +#define CP_EOP_DONE_EVENT_CNTL__SCOPE__SHIFT 0x7 +#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c +#define CP_EOP_DONE_EVENT_CNTL__GLK_INV__SHIFT 0x1e +#define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE__SHIFT 0x1f +#define CP_EOP_DONE_EVENT_CNTL__SCOPE_MASK 0x00000180L +#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x01FFF000L +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L +#define CP_EOP_DONE_EVENT_CNTL__GLK_INV_MASK 0x40000000L +#define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE_MASK 0x80000000L +//CP_EOP_DONE_DATA_CNTL +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT 0x14 +#define CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT 0x16 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK 0x00300000L +#define CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK 0x00C00000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L +//CP_EOP_DONE_CNTX_ID +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_DB_BASE_LO +#define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 +#define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL +//CP_DB_BASE_HI +#define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 +#define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL +//CP_DB_BUFSZ +#define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 +#define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL +//CP_DB_CMD_BUFSZ +#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 +#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL +//CP_PFP_COMPLETION_STATUS +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_PRED_NOT_VISIBLE +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L +//CP_PFP_METADATA_BASE_ADDR +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_PFP_METADATA_BASE_ADDR_HI +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DRAW_INDX_INDR_ADDR +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DRAW_INDX_INDR_ADDR_HI +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DISPATCH_INDR_ADDR +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DISPATCH_INDR_ADDR_HI +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_BASE_ADDR +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_INDEX_BASE_ADDR_HI +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_TYPE +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +//CP_SAMPLE_STATUS +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L +//CP_ME_COHER_CNTL +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +//CP_ME_COHER_SIZE +#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_SIZE_HI +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_BASE +#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_BASE_HI +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_STATUS +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL +#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L +//RLC_GPM_PERF_COUNT_0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L +//RLC_GPM_PERF_COUNT_1 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L +//GRBM_GFX_INDEX +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x0000007FL +#define GRBM_GFX_INDEX__SA_INDEX_MASK 0x00000300L +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x000F0000L +#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_NOWHERE_2 +#define GRBM_NOWHERE_2__DATA__SHIFT 0x0 +#define GRBM_NOWHERE_2__DATA_MASK 0xFFFFFFFFL +//VGT_PRIMITIVE_TYPE +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__NUM_INPUT_CP__SHIFT 0x6 +#define VGT_PRIMITIVE_TYPE__PRIMS_PER_SUBGROUP__SHIFT 0xc +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +#define VGT_PRIMITIVE_TYPE__NUM_INPUT_CP_MASK 0x00000FC0L +#define VGT_PRIMITIVE_TYPE__PRIMS_PER_SUBGROUP_MASK 0x001FF000L +//VGT_INDEX_TYPE +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L +//GE_MIN_VTX_INDX +#define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL +//GE_INDX_OFFSET +#define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL +//GE_MULTI_PRIM_IB_RESET_EN +#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 +#define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX__SHIFT 0x2 +#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L +#define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX_MASK 0x00000004L +//VGT_NUM_INDICES +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_NUM_INSTANCES +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_TF_MEMORY_BASE +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL +//GE_GS_THROTTLE +#define GE_GS_THROTTLE__T0__SHIFT 0x0 +#define GE_GS_THROTTLE__T1__SHIFT 0x3 +#define GE_GS_THROTTLE__T2__SHIFT 0x6 +#define GE_GS_THROTTLE__STALL_CYCLES__SHIFT 0x9 +#define GE_GS_THROTTLE__FACTOR1__SHIFT 0x10 +#define GE_GS_THROTTLE__FACTOR2__SHIFT 0x13 +#define GE_GS_THROTTLE__ENABLE_THROTTLE__SHIFT 0x16 +#define GE_GS_THROTTLE__NUM_INIT_GRPS__SHIFT 0x17 +#define GE_GS_THROTTLE__T0_MASK 0x00000007L +#define GE_GS_THROTTLE__T1_MASK 0x00000038L +#define GE_GS_THROTTLE__T2_MASK 0x000001C0L +#define GE_GS_THROTTLE__STALL_CYCLES_MASK 0x0000FE00L +#define GE_GS_THROTTLE__FACTOR1_MASK 0x00070000L +#define GE_GS_THROTTLE__FACTOR2_MASK 0x00380000L +#define GE_GS_THROTTLE__ENABLE_THROTTLE_MASK 0x00400000L +#define GE_GS_THROTTLE__NUM_INIT_GRPS_MASK 0x7F800000L +//GE_MAX_VTX_INDX +#define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL +//VGT_INSTANCE_BASE_ID +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL +//GE_CNTL +#define GE_CNTL__PRIMS_PER_SUBGRP__SHIFT 0x0 +#define GE_CNTL__VERTS_PER_SUBGRP__SHIFT 0x9 +#define GE_CNTL__BREAK_SUBGRP_AT_EOI__SHIFT 0x12 +#define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13 +#define GE_CNTL__BREAK_PRIMGRP_AT_EOI__SHIFT 0x14 +#define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x15 +#define GE_CNTL__GCR_DISABLE__SHIFT 0x1e +#define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP__SHIFT 0x1f +#define GE_CNTL__PRIMS_PER_SUBGRP_MASK 0x000001FFL +#define GE_CNTL__VERTS_PER_SUBGRP_MASK 0x0003FE00L +#define GE_CNTL__BREAK_SUBGRP_AT_EOI_MASK 0x00040000L +#define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L +#define GE_CNTL__BREAK_PRIMGRP_AT_EOI_MASK 0x00100000L +#define GE_CNTL__PRIM_GRP_SIZE_MASK 0x3FE00000L +#define GE_CNTL__GCR_DISABLE_MASK 0x40000000L +#define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP_MASK 0x80000000L +//GE_USER_VGPR1 +#define GE_USER_VGPR1__DATA__SHIFT 0x0 +#define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL +//GE_USER_VGPR2 +#define GE_USER_VGPR2__DATA__SHIFT 0x0 +#define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL +//GE_USER_VGPR3 +#define GE_USER_VGPR3__DATA__SHIFT 0x0 +#define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL +//GE_STEREO_CNTL +#define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0 +#define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3 +#define GE_STEREO_CNTL__UNUSED__SHIFT 0x7 +#define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8 +#define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L +#define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L +#define GE_STEREO_CNTL__UNUSED_MASK 0x00000080L +#define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L +//GE_USER_VGPR_EN +#define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0 +#define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1 +#define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2 +#define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L +#define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L +#define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L +//VGT_PRIMITIVEID_EN +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L +//GE_VRS_RATE +#define GE_VRS_RATE__RATE_X__SHIFT 0x0 +#define GE_VRS_RATE__RATE_Y__SHIFT 0x4 +#define GE_VRS_RATE__RATE_X_MASK 0x00000003L +#define GE_VRS_RATE__RATE_Y_MASK 0x00000030L +//GE_GS_FAST_LAUNCH_WG_DIM +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X__SHIFT 0x0 +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y__SHIFT 0x10 +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X_MASK 0x0000FFFFL +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y_MASK 0xFFFF0000L +//GE_GS_FAST_LAUNCH_WG_DIM_1 +#define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z__SHIFT 0x0 +#define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z_MASK 0x0000FFFFL +//VGT_GS_OUT_PRIM_TYPE +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL +//VGT_TF_MEMORY_BASE_HI +#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL +//GE_GS_ORDERED_ID_BASE +#define GE_GS_ORDERED_ID_BASE__BASE__SHIFT 0x0 +#define GE_GS_ORDERED_ID_BASE__BASE_MASK 0x00000FFFL +//VGT_PRIMITIVEID_RESET +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cprs64dec +//CP_MES_PRGRM_CNTR_START +#define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MES_INTR_ROUTINE_START +#define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_MES_MTVEC_LO +#define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_INTR_ROUTINE_START_HI +#define CP_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL +//CP_MES_MTVEC_HI +#define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_CNTL +#define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 +#define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 +#define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 +#define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 +#define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a +#define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b +#define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c +#define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d +#define CP_MES_CNTL__MES_HALT__SHIFT 0x1e +#define CP_MES_CNTL__MES_STEP__SHIFT 0x1f +#define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L +#define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L +#define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L +#define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L +#define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L +#define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L +#define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L +#define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L +#define CP_MES_CNTL__MES_HALT_MASK 0x40000000L +#define CP_MES_CNTL__MES_STEP_MASK 0x80000000L +//CP_MES_PIPE_PRIORITY_CNTS +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_MES_PIPE0_PRIORITY +#define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE1_PRIORITY +#define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE2_PRIORITY +#define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE3_PRIORITY +#define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_HEADER_DUMP +#define CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MES_MIE_LO +#define CP_MES_MIE_LO__MES_INT__SHIFT 0x0 +#define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_MIE_HI +#define CP_MES_MIE_HI__MES_INT__SHIFT 0x0 +#define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT +#define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0 +#define CP_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_SCRATCH_INDEX +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_MES_SCRATCH_DATA +#define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_MES_INSTR_PNTR +#define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//CP_MES_MSCRATCH_HI +#define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0 +#define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_MSCRATCH_LO +#define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0 +#define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_MSTATUS_LO +#define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 +#define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL +//CP_MES_MSTATUS_HI +#define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 +#define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL +//CP_MES_MEPC_LO +#define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 +#define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL +//CP_MES_MEPC_HI +#define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 +#define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL +//CP_MES_MCAUSE_LO +#define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 +#define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL +//CP_MES_MCAUSE_HI +#define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 +#define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL +//CP_MES_MBADADDR_LO +#define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 +#define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_MBADADDR_HI +#define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_MES_MIP_LO +#define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0 +#define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//CP_MES_MIP_HI +#define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0 +#define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//CP_MES_IC_OP_CNTL +#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_MES_MCYCLE_LO +#define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 +#define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL +//CP_MES_MCYCLE_HI +#define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 +#define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL +//CP_MES_MTIME_LO +#define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0 +#define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MES_MTIME_HI +#define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0 +#define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MES_MINSTRET_LO +#define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 +#define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL +//CP_MES_MINSTRET_HI +#define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 +#define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL +//CP_MES_MISA_LO +#define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0 +#define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL +//CP_MES_MISA_HI +#define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0 +#define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL +//CP_MES_MVENDORID_LO +#define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 +#define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL +//CP_MES_MVENDORID_HI +#define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 +#define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL +//CP_MES_MARCHID_LO +#define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 +#define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL +//CP_MES_MARCHID_HI +#define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 +#define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL +//CP_MES_MIMPID_LO +#define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 +#define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL +//CP_MES_MIMPID_HI +#define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 +#define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL +//CP_MES_MHARTID_LO +#define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 +#define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL +//CP_MES_MHARTID_HI +#define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 +#define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL +//CP_MES_DC_BASE_CNTL +#define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MES_DC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_MES_DC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_MES_DC_OP_CNTL +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//CP_MES_MTIMECMP_LO +#define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MES_MTIMECMP_HI +#define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MES_PROCESS_QUANTUM_PIPE0 +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0 +#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L +//CP_MES_PROCESS_QUANTUM_PIPE1 +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0 +#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL1 +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL2 +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL3 +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL4 +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL5 +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL6 +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_GP0_LO +#define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MES_GP0_LO__DATA__SHIFT 0x1 +#define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL +//CP_MES_GP0_HI +#define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MES_GP1_LO +#define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MES_GP1_HI +#define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MES_GP2_LO +#define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MES_GP2_HI +#define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MES_GP3_LO +#define CP_MES_GP3_LO__DATA__SHIFT 0x0 +#define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP3_HI +#define CP_MES_GP3_HI__DATA__SHIFT 0x0 +#define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP4_LO +#define CP_MES_GP4_LO__DATA__SHIFT 0x0 +#define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP4_HI +#define CP_MES_GP4_HI__DATA__SHIFT 0x0 +#define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP5_LO +#define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MES_GP5_LO__DATA__SHIFT 0x1 +#define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL +//CP_MES_GP5_HI +#define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MES_GP6_LO +#define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MES_GP6_HI +#define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MES_GP7_LO +#define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MES_GP7_HI +#define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MES_GP8_LO +#define CP_MES_GP8_LO__DATA__SHIFT 0x0 +#define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP8_HI +#define CP_MES_GP8_HI__DATA__SHIFT 0x0 +#define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP9_LO +#define CP_MES_GP9_LO__DATA__SHIFT 0x0 +#define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP9_HI +#define CP_MES_GP9_HI__DATA__SHIFT 0x0 +#define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_LOCAL_BASE0_LO +#define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_BASE0_HI +#define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_MASK0_LO +#define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_MASK0_HI +#define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_APERTURE +#define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MES_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MES_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MES_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MES_LOCAL_INSTR_BASE_LO +#define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_INSTR_BASE_HI +#define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_INSTR_MASK_LO +#define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_INSTR_MASK_HI +#define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_INSTR_APERTURE +#define CP_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MES_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MES_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MES_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MES_LOCAL_SCRATCH_APERTURE +#define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_MES_LOCAL_SCRATCH_BASE_LO +#define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_SCRATCH_BASE_HI +#define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MES_PERFCOUNT_CNTL +#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//CP_MES_PENDING_INTERRUPT +#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_MES_RS64_EXCEPTION_STATUS +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_MES_PRGRM_CNTR_START_HI +#define CP_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MES_INTERRUPT_DATA_16 +#define CP_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_17 +#define CP_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_18 +#define CP_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_19 +#define CP_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_20 +#define CP_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_21 +#define CP_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_22 +#define CP_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_23 +#define CP_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_24 +#define CP_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_25 +#define CP_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_26 +#define CP_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_27 +#define CP_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_28 +#define CP_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_29 +#define CP_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_30 +#define CP_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_31 +#define CP_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//CP_MES_METADATA_CNTL +#define CP_MES_METADATA_CNTL__SCOPE__SHIFT 0x6 +#define CP_MES_METADATA_CNTL__TEMPORAL__SHIFT 0x8 +#define CP_MES_METADATA_CNTL__SCOPE_MASK 0x000000C0L +#define CP_MES_METADATA_CNTL__TEMPORAL_MASK 0x00000700L +//CP_MEC_RS64_PRGRM_CNTR_START +#define CP_MEC_RS64_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC_RS64_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MEC_MTVEC_LO +#define CP_MEC_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define CP_MEC_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MEC_MTVEC_HI +#define CP_MEC_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define CP_MEC_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MEC_RS64_CNTL +#define CP_MEC_RS64_CNTL__SPARE__SHIFT 0x0 +#define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE__SHIFT 0x1a +#define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE__SHIFT 0x1b +#define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE__SHIFT 0x1c +#define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE__SHIFT 0x1d +#define CP_MEC_RS64_CNTL__MEC_HALT__SHIFT 0x1e +#define CP_MEC_RS64_CNTL__MEC_STEP__SHIFT 0x1f +#define CP_MEC_RS64_CNTL__SPARE_MASK 0x0000000FL +#define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE_MASK 0x04000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE_MASK 0x08000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE_MASK 0x10000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE_MASK 0x20000000L +#define CP_MEC_RS64_CNTL__MEC_HALT_MASK 0x40000000L +#define CP_MEC_RS64_CNTL__MEC_STEP_MASK 0x80000000L +//CP_MEC_MIE_LO +#define CP_MEC_MIE_LO__MEC_INT__SHIFT 0x0 +#define CP_MEC_MIE_LO__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_MIE_HI +#define CP_MEC_MIE_HI__MEC_INT__SHIFT 0x0 +#define CP_MEC_MIE_HI__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT +#define CP_MEC_RS64_INTERRUPT__MEC_INT__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INSTR_PNTR +#define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//CP_MEC_MIP_LO +#define CP_MEC_MIP_LO__MIP_LO__SHIFT 0x0 +#define CP_MEC_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//CP_MEC_MIP_HI +#define CP_MEC_MIP_HI__MIP_HI__SHIFT 0x0 +#define CP_MEC_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//CP_MEC_DC_BASE_CNTL +#define CP_MEC_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MEC_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MEC_DC_OP_CNTL +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_MEC_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_MEC_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//CP_MEC_MTIMECMP_LO +#define CP_MEC_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define CP_MEC_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MEC_MTIMECMP_HI +#define CP_MEC_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define CP_MEC_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP0_LO +#define CP_MEC_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MEC_GP0_LO__DATA__SHIFT 0x1 +#define CP_MEC_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MEC_GP0_LO__DATA_MASK 0xFFFFFFFEL +//CP_MEC_GP0_HI +#define CP_MEC_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MEC_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MEC_GP1_LO +#define CP_MEC_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MEC_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP1_HI +#define CP_MEC_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MEC_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP2_LO +#define CP_MEC_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MEC_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP2_HI +#define CP_MEC_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MEC_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP3_LO +#define CP_MEC_GP3_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP3_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP3_HI +#define CP_MEC_GP3_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP3_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP4_LO +#define CP_MEC_GP4_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP4_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP4_HI +#define CP_MEC_GP4_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP4_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP5_LO +#define CP_MEC_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MEC_GP5_LO__DATA__SHIFT 0x1 +#define CP_MEC_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MEC_GP5_LO__DATA_MASK 0xFFFFFFFEL +//CP_MEC_GP5_HI +#define CP_MEC_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MEC_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MEC_GP6_LO +#define CP_MEC_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MEC_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP6_HI +#define CP_MEC_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MEC_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP7_LO +#define CP_MEC_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MEC_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP7_HI +#define CP_MEC_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MEC_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP8_LO +#define CP_MEC_GP8_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP8_HI +#define CP_MEC_GP8_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP9_LO +#define CP_MEC_GP9_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP9_HI +#define CP_MEC_GP9_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_LOCAL_BASE0_LO +#define CP_MEC_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_BASE0_HI +#define CP_MEC_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_BASE0_HI__BASE0_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_MASK0_LO +#define CP_MEC_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_MASK0_HI +#define CP_MEC_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_MASK0_HI__MASK0_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_APERTURE +#define CP_MEC_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MEC_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MEC_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MEC_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MEC_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MEC_LOCAL_INSTR_BASE_LO +#define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_INSTR_BASE_HI +#define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_INSTR_MASK_LO +#define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_INSTR_MASK_HI +#define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_INSTR_APERTURE +#define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MEC_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MEC_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MEC_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MEC_LOCAL_SCRATCH_APERTURE +#define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_MEC_LOCAL_SCRATCH_BASE_LO +#define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_SCRATCH_BASE_HI +#define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_RS64_PERFCOUNT_CNTL +#define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//CP_MEC_RS64_PENDING_INTERRUPT +#define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_EXCEPTION_STATUS +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_MEC_RS64_PRGRM_CNTR_START_HI +#define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_16 +#define CP_MEC_RS64_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_17 +#define CP_MEC_RS64_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_18 +#define CP_MEC_RS64_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_19 +#define CP_MEC_RS64_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_20 +#define CP_MEC_RS64_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_21 +#define CP_MEC_RS64_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_22 +#define CP_MEC_RS64_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_23 +#define CP_MEC_RS64_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_24 +#define CP_MEC_RS64_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_25 +#define CP_MEC_RS64_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_26 +#define CP_MEC_RS64_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_27 +#define CP_MEC_RS64_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_28 +#define CP_MEC_RS64_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_29 +#define CP_MEC_RS64_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_30 +#define CP_MEC_RS64_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_31 +#define CP_MEC_RS64_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//CP_CPC_IC_OP_CNTL +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_CPC_IC_OP_CNTL__RESERVED__SHIFT 0x2 +#define CP_CPC_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_CPC_IC_OP_CNTL__RESERVED_MASK 0x00000004L +#define CP_CPC_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_GFX_RS64_INTERRUPT0 +#define CP_GFX_RS64_INTERRUPT0__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTERRUPT0__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INTR_EN0 +#define CP_GFX_RS64_INTR_EN0__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTR_EN0__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INTR_EN1 +#define CP_GFX_RS64_INTR_EN1__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTR_EN1__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_BASE_CNTL +#define CP_GFX_RS64_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_RS64_DC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_GFX_RS64_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_RS64_DC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_GFX_RS64_DC_OP_CNTL +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_GFX_RS64_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +#define CP_GFX_RS64_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L +//CP_GFX_RS64_LOCAL_BASE0_LO +#define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_BASE0_HI +#define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_MASK0_LO +#define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_MASK0_HI +#define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_APERTURE +#define CP_GFX_RS64_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define CP_GFX_RS64_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_LOCAL_INSTR_BASE_LO +#define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_INSTR_BASE_HI +#define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_INSTR_MASK_LO +#define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_INSTR_MASK_HI +#define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_INSTR_APERTURE +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_LOCAL_SCRATCH_APERTURE +#define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_PFP_RS64_EXCEPTION_STATUS +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_GFX_RS64_PERFCOUNT_CNTL0 +#define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL__SHIFT 0x0 +#define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL_MASK 0x0000001FL +//CP_GFX_RS64_PERFCOUNT_CNTL1 +#define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL__SHIFT 0x0 +#define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL_MASK 0x0000001FL +//CP_GFX_RS64_MIP_LO0 +#define CP_GFX_RS64_MIP_LO0__MIP_LO__SHIFT 0x0 +#define CP_GFX_RS64_MIP_LO0__MIP_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_LO1 +#define CP_GFX_RS64_MIP_LO1__MIP_LO__SHIFT 0x0 +#define CP_GFX_RS64_MIP_LO1__MIP_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_HI0 +#define CP_GFX_RS64_MIP_HI0__MIP_HI__SHIFT 0x0 +#define CP_GFX_RS64_MIP_HI0__MIP_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_HI1 +#define CP_GFX_RS64_MIP_HI1__MIP_HI__SHIFT 0x0 +#define CP_GFX_RS64_MIP_HI1__MIP_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_LO0 +#define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_LO1 +#define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_HI0 +#define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_HI1 +#define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP0_LO0 +#define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP0_LO0__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP0_LO0__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP0_LO1 +#define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP0_LO1__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP0_LO1__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP0_HI0 +#define CP_GFX_RS64_GP0_HI0__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP0_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP0_HI1 +#define CP_GFX_RS64_GP0_HI1__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP0_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_LO0 +#define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_LO1 +#define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_HI0 +#define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_HI1 +#define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_LO0 +#define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_LO1 +#define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_HI0 +#define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_HI1 +#define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_LO0 +#define CP_GFX_RS64_GP3_LO0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_LO0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_LO1 +#define CP_GFX_RS64_GP3_LO1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_LO1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_HI0 +#define CP_GFX_RS64_GP3_HI0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_HI0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_HI1 +#define CP_GFX_RS64_GP3_HI1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_HI1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_LO0 +#define CP_GFX_RS64_GP4_LO0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_LO0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_LO1 +#define CP_GFX_RS64_GP4_LO1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_LO1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_HI0 +#define CP_GFX_RS64_GP4_HI0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_HI0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_HI1 +#define CP_GFX_RS64_GP4_HI1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_HI1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP5_LO0 +#define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP5_LO0__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP5_LO0__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP5_LO1 +#define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP5_LO1__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP5_LO1__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP5_HI0 +#define CP_GFX_RS64_GP5_HI0__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP5_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP5_HI1 +#define CP_GFX_RS64_GP5_HI1__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP5_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP6_LO +#define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP6_HI +#define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP7_LO +#define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP7_HI +#define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP8_LO +#define CP_GFX_RS64_GP8_LO__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP8_HI +#define CP_GFX_RS64_GP8_HI__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP9_LO +#define CP_GFX_RS64_GP9_LO__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP9_HI +#define CP_GFX_RS64_GP9_HI__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INSTR_PNTR0 +#define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR__SHIFT 0x0 +#define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR_MASK 0x000FFFFFL +//CP_GFX_RS64_INSTR_PNTR1 +#define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR__SHIFT 0x0 +#define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR_MASK 0x000FFFFFL +//CP_GFX_RS64_PENDING_INTERRUPT0 +#define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_PENDING_INTERRUPT1 +#define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_BASE0 +#define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_MASK0 +#define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_CNTL0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE1_BASE0 +#define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_MASK0 +#define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_CNTL0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE2_BASE0 +#define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_MASK0 +#define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_CNTL0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE3_BASE0 +#define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_MASK0 +#define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_CNTL0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE4_BASE0 +#define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_MASK0 +#define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_CNTL0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE5_BASE0 +#define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_MASK0 +#define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_CNTL0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE6_BASE0 +#define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_MASK0 +#define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_CNTL0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE7_BASE0 +#define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_MASK0 +#define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_CNTL0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE8_BASE0 +#define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_MASK0 +#define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_CNTL0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE9_BASE0 +#define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_MASK0 +#define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_CNTL0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE10_BASE0 +#define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_MASK0 +#define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_CNTL0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE11_BASE0 +#define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_MASK0 +#define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_CNTL0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE12_BASE0 +#define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_MASK0 +#define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_CNTL0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE13_BASE0 +#define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_MASK0 +#define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_CNTL0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE14_BASE0 +#define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_MASK0 +#define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_CNTL0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE15_BASE0 +#define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_MASK0 +#define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_CNTL0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE0_BASE1 +#define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_MASK1 +#define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_CNTL1 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE1_BASE1 +#define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_MASK1 +#define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_CNTL1 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE2_BASE1 +#define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_MASK1 +#define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_CNTL1 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE3_BASE1 +#define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_MASK1 +#define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_CNTL1 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE4_BASE1 +#define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_MASK1 +#define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_CNTL1 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE5_BASE1 +#define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_MASK1 +#define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_CNTL1 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE6_BASE1 +#define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_MASK1 +#define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_CNTL1 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE7_BASE1 +#define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_MASK1 +#define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_CNTL1 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE8_BASE1 +#define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_MASK1 +#define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_CNTL1 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE9_BASE1 +#define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_MASK1 +#define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_CNTL1 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE10_BASE1 +#define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_MASK1 +#define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_CNTL1 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE11_BASE1 +#define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_MASK1 +#define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_CNTL1 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE12_BASE1 +#define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_MASK1 +#define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_CNTL1 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE13_BASE1 +#define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_MASK1 +#define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_CNTL1 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE14_BASE1 +#define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_MASK1 +#define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_CNTL1 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE15_BASE1 +#define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_MASK1 +#define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_CNTL1 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_ME_RS64_EXCEPTION_STATUS +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_GFX_RS64_INTERRUPT1 +#define CP_GFX_RS64_INTERRUPT1__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTERRUPT1__ME_INT_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_chdec +//CH_ARB_CTRL +#define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define CH_ARB_CTRL__FGCG_DISABLE__SHIFT 0x2 +#define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x3 +#define CH_ARB_CTRL__CHICKEN_BITS__SHIFT 0x4 +#define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000001L +#define CH_ARB_CTRL__FGCG_DISABLE_MASK 0x00000004L +#define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000008L +#define CH_ARB_CTRL__CHICKEN_BITS_MASK 0x00000FF0L +//CH_DRAM_BURST_MASK +#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//CH_ARB_STATUS +#define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//CH_DRAM_BURST_CTRL +#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +//CHA_CHC_CREDITS +#define CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT 0x0 +#define CHA_CHC_CREDITS__CHC_DATA_CREDITS__SHIFT 0x8 +#define CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK 0x000000FFL +#define CHA_CHC_CREDITS__CHC_DATA_CREDITS_MASK 0x0000FF00L +//CHA_CLIENT_FREE_DELAY +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +//CHI_CHR_REP_FGCG_OVERRIDE +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//CHC_CTRL +#define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define CHC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define CHC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define CHC_CTRL__DISABLE_CMPSWAP_DATA_REPLICATE__SHIFT 0x14 +#define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define CHC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define CHC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define CHC_CTRL__DISABLE_CMPSWAP_DATA_REPLICATE_MASK 0x00100000L +//CHC_STATUS +#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x15 +#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x16 +#define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x17 +#define CHC_STATUS__BUFFER_FULL__SHIFT 0x18 +#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x001FFC00L +#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00200000L +#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00400000L +#define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00800000L +#define CHC_STATUS__BUFFER_FULL_MASK 0x01000000L +//CHC_STATUS2 +#define CHC_STATUS2__DCC_OUT_ERROR_CODE__SHIFT 0x0 +#define CHC_STATUS2__DCC_OUT_ERROR_CODE_MASK 0x00000FFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_glarbdec +//GLARB_ARB_CTRL +#define GLARB_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define GLARB_ARB_CTRL__FGCG_DISABLE__SHIFT 0x4 +#define GLARB_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x5 +#define GLARB_ARB_CTRL__GCRD_TARGET_DISABLE__SHIFT 0x6 +#define GLARB_ARB_CTRL__NPS_MODE__SHIFT 0x12 +#define GLARB_ARB_CTRL__CHICKEN_BITS__SHIFT 0x14 +#define GLARB_ARB_CTRL__NUM_MEM_PIPES_MASK 0x0000000FL +#define GLARB_ARB_CTRL__FGCG_DISABLE_MASK 0x00000010L +#define GLARB_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000020L +#define GLARB_ARB_CTRL__GCRD_TARGET_DISABLE_MASK 0x0003FFC0L +#define GLARB_ARB_CTRL__NPS_MODE_MASK 0x000C0000L +#define GLARB_ARB_CTRL__CHICKEN_BITS_MASK 0x01F00000L +//GLARB_DRAM_BURST_MASK +#define GLARB_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GLARB_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GLARB_ARB_STATUS +#define GLARB_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GLARB_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GLARB_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GLARB_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GLARB_DRAM_BURST_CTRL +#define GLARB_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define GLARB_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_BURST_DISABLE__SHIFT 0x5 +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT 0x6 +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_BURST_DISABLE__SHIFT 0x7 +#define GLARB_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT 0x8 +#define GLARB_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define GLARB_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_BURST_DISABLE_MASK 0x00000020L +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK 0x00000040L +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_BURST_DISABLE_MASK 0x00000080L +#define GLARB_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK 0x00000100L +//GLARBA_GLARBC_CREDITS +#define GLARBA_GLARBC_CREDITS__GLARBC_REQ_CREDITS__SHIFT 0x0 +#define GLARBA_GLARBC_CREDITS__GLARBC_DATA_CREDITS__SHIFT 0x8 +#define GLARBA_GLARBC_CREDITS__GLARBCG_REQ_CREDITS__SHIFT 0x10 +#define GLARBA_GLARBC_CREDITS__GLARBC_REQ_CREDITS_MASK 0x000000FFL +#define GLARBA_GLARBC_CREDITS__GLARBC_DATA_CREDITS_MASK 0x0000FF00L +#define GLARBA_GLARBC_CREDITS__GLARBCG_REQ_CREDITS_MASK 0x00FF0000L +//GLARBA_CLIENT_FREE_DELAY +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +//GLARBI_GLARBR_REP_FGCG_OVERRIDE +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIW_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIR_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIW_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIR_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GLARBC_CTRL +#define GLARBC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define GLARBC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define GLARBC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define GLARBC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define GLARBC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define GLARBC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT 0x14 +#define GLARBC_CTRL__OC_EA_REQ_D_CREDIT__SHIFT 0x15 +#define GLARBC_CTRL__OC_EA_REQ_I_CREDIT__SHIFT 0x1a +#define GLARBC_CTRL__CREST_MODE_ENABLE__SHIFT 0x1f +#define GLARBC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define GLARBC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define GLARBC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define GLARBC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define GLARBC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define GLARBC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK 0x00100000L +#define GLARBC_CTRL__OC_EA_REQ_D_CREDIT_MASK 0x03E00000L +#define GLARBC_CTRL__OC_EA_REQ_I_CREDIT_MASK 0x7C000000L +#define GLARBC_CTRL__CREST_MODE_ENABLE_MASK 0x80000000L +//GLARBC_STATUS +#define GLARBC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GLARBC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 +#define GLARBC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GLARBC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GLARBC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GLARBC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GLARBC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GLARBC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GLARBC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GLARBC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define GLARBC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define GLARBC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define GLARBC_STATUS__BUFFER_FULL__SHIFT 0x17 +#define GLARBC_STATUS__DCC_OUT_ERROR_CODE__SHIFT 0x18 +#define GLARBC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GLARBC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L +#define GLARBC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GLARBC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GLARBC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GLARBC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GLARBC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GLARBC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GLARBC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GLARBC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define GLARBC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define GLARBC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define GLARBC_STATUS__BUFFER_FULL_MASK 0x00800000L +#define GLARBC_STATUS__DCC_OUT_ERROR_CODE_MASK 0x1F000000L +//GLARBC_CTRL2 +#define GLARBC_CTRL2__DCC_COMP_TO_CONSTANT_EN__SHIFT 0x0 +#define GLARBC_CTRL2__DCC_COMP_TO_SINGLE_EN__SHIFT 0x1 +#define GLARBC_CTRL2__DCC_COMP_ERROR_DETECTION_EN__SHIFT 0x2 +#define GLARBC_CTRL2__DCC_CLEAR_ERROR_CODE__SHIFT 0x6 +#define GLARBC_CTRL2__DCC_COMP_TRANSFER_SIZE_ENABLE__SHIFT 0x7 +#define GLARBC_CTRL2__DCC_COMP_SKIP_LOW_COMP_RATIOS__SHIFT 0xa +#define GLARBC_CTRL2__DCC_COMP_TO_CONSTANT_EN_MASK 0x00000001L +#define GLARBC_CTRL2__DCC_COMP_TO_SINGLE_EN_MASK 0x00000002L +#define GLARBC_CTRL2__DCC_COMP_ERROR_DETECTION_EN_MASK 0x0000003CL +#define GLARBC_CTRL2__DCC_CLEAR_ERROR_CODE_MASK 0x00000040L +#define GLARBC_CTRL2__DCC_COMP_TRANSFER_SIZE_ENABLE_MASK 0x00000380L +#define GLARBC_CTRL2__DCC_COMP_SKIP_LOW_COMP_RATIOS_MASK 0x00000400L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfddec +//CPG_PERFCOUNTER1_LO +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER1_HI +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_LO +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_HI +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_LO +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_HI +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_LO +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_HI +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_LO +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_HI +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_LO +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_HI +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_LATENCY_STATS_DATA +#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_LATENCY_STATS_DATA +#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPC_LATENCY_STATS_DATA +#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_LO +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_HI +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_LO +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_HI +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER0_LO +#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER0_HI +#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER1_LO +#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER1_HI +#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER2_LO +#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER2_HI +#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER3_LO +#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER3_HI +#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER0_LO +#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER0_HI +#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER1_LO +#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER1_HI +#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER2_LO +#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER2_HI +#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER3_LO +#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER3_HI +#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER0_LO +#define GC_EA_CPWD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER0_HI +#define GC_EA_CPWD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER1_LO +#define GC_EA_CPWD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER1_HI +#define GC_EA_CPWD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER0_LO +#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER0_HI +#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER1_LO +#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER1_HI +#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER2_LO +#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER2_HI +#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER3_LO +#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER3_HI +#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER0_LO +#define GLARBA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER0_HI +#define GLARBA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER1_LO +#define GLARBA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER1_HI +#define GLARBA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER2_LO +#define GLARBA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER2_HI +#define GLARBA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER3_LO +#define GLARBA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER3_HI +#define GLARBA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER0_LO +#define GLARBC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER0_HI +#define GLARBC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER1_LO +#define GLARBC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER1_HI +#define GLARBC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER2_LO +#define GLARBC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER2_HI +#define GLARBC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER3_LO +#define GLARBC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER3_HI +#define GLARBC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_LO +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_HI +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_LO +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_HI +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_LO +#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_HI +#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER1_LO +#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER1_HI +#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER0_LO +#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER0_HI +#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER1_LO +#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER1_HI +#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER2_LO +#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER2_HI +#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER3_LO +#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER3_HI +#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec +//CPG_PERFCOUNTER1_SELECT +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT1 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER1_SELECT +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPC_PERFCOUNTER0_SELECT1 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER1_SELECT +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT1 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//CPC_PERFCOUNTER0_SELECT +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_TC_PERF_COUNTER_WINDOW_SELECT +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPG_TC_PERF_COUNTER_WINDOW_SELECT +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPF_LATENCY_STATS_SELECT +#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPG_LATENCY_STATS_SELECT +#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_LATENCY_STATS_SELECT +#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_TC_PERF_COUNTER_WINDOW_SELECT +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CP_DRAW_OBJECT +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL +//CP_DRAW_OBJECT_COUNTER +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL +//CP_DRAW_WINDOW_MASK_HI +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_HI +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_LO +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L +//CP_DRAW_WINDOW_CNTL +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L +//GRBM_PERFCOUNTER0_SELECT +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER0_SELECT__CANE_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER0_SELECT__CANE_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBM_PERFCOUNTER1_SELECT +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER1_SELECT__CANE_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER1_SELECT__CANE_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBM_PERFCOUNTER0_SELECT_HI +#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 +#define GRBM_PERFCOUNTER0_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK__SHIFT 0x2 +#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 +#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 +#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBM_PERFCOUNTER0_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L +#define GRBM_PERFCOUNTER0_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK_MASK 0x00000004L +#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L +#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L +#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBM_PERFCOUNTER0_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +//GRBM_PERFCOUNTER1_SELECT_HI +#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 +#define GRBM_PERFCOUNTER1_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK__SHIFT 0x2 +#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 +#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 +#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBM_PERFCOUNTER1_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L +#define GRBM_PERFCOUNTER1_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK_MASK 0x00000004L +#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L +#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L +#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBM_PERFCOUNTER1_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +//GE1_PERFCOUNTER0_SELECT +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER0_SELECT1 +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER1_SELECT +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER1_SELECT1 +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER2_SELECT +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER2_SELECT1 +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER3_SELECT +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER3_SELECT1 +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER0_SELECT +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER0_SELECT1 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER1_SELECT +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER1_SELECT1 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER2_SELECT +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER2_SELECT1 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER3_SELECT +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER3_SELECT1 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_EA_CPWD_PERFCOUNTER0_SELECT +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GC_EA_CPWD_PERFCOUNTER0_SELECT1 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_EA_CPWD_PERFCOUNTER1_SELECT +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER0_SELECT +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER0_SELECT1 +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHC_PERFCOUNTER1_SELECT +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER1_SELECT1 +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHC_PERFCOUNTER2_SELECT +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER2_SELECT1 +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHC_PERFCOUNTER3_SELECT +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER3_SELECT1 +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER0_SELECT +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER0_SELECT1 +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER1_SELECT +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER1_SELECT1 +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER2_SELECT +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER2_SELECT1 +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER3_SELECT +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER3_SELECT1 +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER0_SELECT +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER0_SELECT1 +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER1_SELECT +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER1_SELECT1 +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER2_SELECT +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER2_SELECT1 +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER3_SELECT +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER3_SELECT1 +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RLC_SPM_PERFMON_CNTL +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_START_MODE__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_TYPE__SHIFT 0xf +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x00000FFFL +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_START_MODE_MASK 0x00004000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_TYPE_MASK 0x00008000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_BASE_LO +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_RING_BASE_HI +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x19 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x01FFFFFFL +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFE000000L +//RLC_SPM_PERFMON_RING_SIZE +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL +//RLC_SPM_RING_WRPTR +#define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0 +#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5 +#define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL +#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L +//RLC_SPM_RING_RDPTR +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL +//RLC_SPM_SEGMENT_THRESHOLD +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL +#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PERFMON_SEGMENT_SIZE +#define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT__SHIFT 0x18 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT_MASK 0x00FF0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT_MASK 0xFF000000L +//RLC_SPM_GLOBAL_MUXSEL_ADDR +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR_MASK 0x000003FFL +//RLC_SPM_GLOBAL_MUXSEL_DATA +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1__SHIFT 0x10 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L +//RLC_SPM_SE_MUXSEL_ADDR +#define RLC_SPM_SE_MUXSEL_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_ADDR__ADDR_MASK 0x000003FFL +//RLC_SPM_SE_MUXSEL_DATA +#define RLC_SPM_SE_MUXSEL_DATA__SEL0__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__SEL1__SHIFT 0x10 +#define RLC_SPM_SE_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL +#define RLC_SPM_SE_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_0 +#define RLC_SPM_SE_USER_DATA_0__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_0__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_0__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_0__HI_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_1 +#define RLC_SPM_SE_USER_DATA_1__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_1__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_1__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_1__HI_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_2 +#define RLC_SPM_SE_USER_DATA_2__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_2__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_2__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_2__HI_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_3 +#define RLC_SPM_SE_USER_DATA_3__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_3__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_3__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_3__HI_MASK 0xFFFF0000L +//RLC_SPM_ACCUM_DATARAM_ADDR +#define RLC_SPM_ACCUM_DATARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_ADDR__ADDR_MASK 0x0000007FL +//RLC_SPM_ACCUM_DATARAM_DATA +#define RLC_SPM_ACCUM_DATARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_ACCUM_SWA_DATARAM_ADDR +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__ADDR_MASK 0x0000007FL +//RLC_SPM_ACCUM_SWA_DATARAM_DATA +#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_ACCUM_CTRLRAM_ADDR +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__ADDR_MASK 0x000007FFL +//RLC_SPM_ACCUM_CTRLRAM_DATA +#define RLC_SPM_ACCUM_CTRLRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_DATA__DATA_MASK 0x000000FFL +//RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT 0x10 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK 0x000000FFL +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK 0x0000FF00L +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK 0x00FF0000L +//RLC_SPM_ACCUM_STATUS +#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0 +#define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8 +#define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9 +#define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa +#define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb +#define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc +#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd +#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe +#define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf +#define RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT 0x10 +#define RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT 0x11 +#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT 0x12 +#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT 0x13 +#define RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT 0x14 +#define RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT 0x15 +#define RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT 0x16 +#define RLC_SPM_ACCUM_STATUS__MultiSampleAborted__SHIFT 0x17 +#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL +#define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L +#define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L +#define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L +#define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L +#define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L +#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L +#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L +#define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK 0x00010000L +#define RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK 0x00020000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK 0x00040000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK 0x00080000L +#define RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK 0x00100000L +#define RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK 0x00200000L +#define RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK 0x00400000L +#define RLC_SPM_ACCUM_STATUS__MultiSampleAborted_MASK 0x00800000L +//RLC_SPM_ACCUM_CTRL +#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1 +#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2 +#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT 0x3 +#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x4 +#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT 0x9 +#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT 0xa +#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L +#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L +#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L +#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK 0x00000008L +#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000000F0L +#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK 0x00000100L +#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK 0x00000200L +#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK 0x00000400L +//RLC_SPM_ACCUM_MODE +#define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0 +#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT 0x1 +#define RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT 0x2 +#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x3 +#define RLC_SPM_ACCUM_MODE__RESERVED_4__SHIFT 0x4 +#define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x5 +#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT 0x6 +#define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x7 +#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT 0x8 +#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x9 +#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT 0xa +#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0xb +#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT 0xc +#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0xd +#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT 0xe +#define RLC_SPM_ACCUM_MODE__RESERVED_16_15__SHIFT 0xf +#define RLC_SPM_ACCUM_MODE__RESERVED_18_17__SHIFT 0x11 +#define RLC_SPM_ACCUM_MODE__RESERVED_20_19__SHIFT 0x13 +#define RLC_SPM_ACCUM_MODE__RESERVED_22_21__SHIFT 0x15 +#define RLC_SPM_ACCUM_MODE__RESERVED_24_23__SHIFT 0x17 +#define RLC_SPM_ACCUM_MODE__RESERVED_26_25__SHIFT 0x19 +#define RLC_SPM_ACCUM_MODE__RESERVED_31_27__SHIFT 0x1b +#define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L +#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK 0x00000002L +#define RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK 0x00000004L +#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000008L +#define RLC_SPM_ACCUM_MODE__RESERVED_4_MASK 0x00000010L +#define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000020L +#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK 0x00000040L +#define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000080L +#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK 0x00000100L +#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000200L +#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK 0x00000400L +#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000800L +#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK 0x00001000L +#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00002000L +#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK 0x00004000L +#define RLC_SPM_ACCUM_MODE__RESERVED_16_15_MASK 0x00018000L +#define RLC_SPM_ACCUM_MODE__RESERVED_18_17_MASK 0x00060000L +#define RLC_SPM_ACCUM_MODE__RESERVED_20_19_MASK 0x00180000L +#define RLC_SPM_ACCUM_MODE__RESERVED_22_21_MASK 0x00600000L +#define RLC_SPM_ACCUM_MODE__RESERVED_24_23_MASK 0x01800000L +#define RLC_SPM_ACCUM_MODE__RESERVED_26_25_MASK 0x06000000L +#define RLC_SPM_ACCUM_MODE__RESERVED_31_27_MASK 0xF8000000L +//RLC_SPM_ACCUM_THRESHOLD +#define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0 +#define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL +//RLC_SPM_ACCUM_SAMPLES_REQUESTED +#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0 +#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL +//RLC_SPM_ACCUM_DATARAM_WRCOUNT +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL +//RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT 0x8 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK 0x000000FFL +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK 0x0000FF00L +//RLC_SPM_PAUSE +#define RLC_SPM_PAUSE__PAUSE__SHIFT 0x0 +#define RLC_SPM_PAUSE__PAUSED__SHIFT 0x1 +#define RLC_SPM_PAUSE__PAUSE_MASK 0x00000001L +#define RLC_SPM_PAUSE__PAUSED_MASK 0x00000002L +//RLC_SPM_STATUS +#define RLC_SPM_STATUS__CTL_BUSY__SHIFT 0x0 +#define RLC_SPM_STATUS__RSPM_REG_BUSY__SHIFT 0x1 +#define RLC_SPM_STATUS__SPM_RSPM_BUSY__SHIFT 0x2 +#define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY__SHIFT 0x3 +#define RLC_SPM_STATUS__SE_RSPM_IO_BUSY__SHIFT 0x4 +#define RLC_SPM_STATUS__ACCUM_BUSY__SHIFT 0xf +#define RLC_SPM_STATUS__FSM_MASTER_STATE__SHIFT 0x10 +#define RLC_SPM_STATUS__FSM_MEMORY_STATE__SHIFT 0x14 +#define RLC_SPM_STATUS__CTL_REQ_STATE__SHIFT 0x18 +#define RLC_SPM_STATUS__CTL_RET_STATE__SHIFT 0x1a +#define RLC_SPM_STATUS__CTL_BUSY_MASK 0x00000001L +#define RLC_SPM_STATUS__RSPM_REG_BUSY_MASK 0x00000002L +#define RLC_SPM_STATUS__SPM_RSPM_BUSY_MASK 0x00000004L +#define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY_MASK 0x00000008L +#define RLC_SPM_STATUS__SE_RSPM_IO_BUSY_MASK 0x00000FF0L +#define RLC_SPM_STATUS__ACCUM_BUSY_MASK 0x00008000L +#define RLC_SPM_STATUS__FSM_MASTER_STATE_MASK 0x000F0000L +#define RLC_SPM_STATUS__FSM_MEMORY_STATE_MASK 0x00F00000L +#define RLC_SPM_STATUS__CTL_REQ_STATE_MASK 0x03000000L +#define RLC_SPM_STATUS__CTL_RET_STATE_MASK 0x04000000L +//RLC_SPM_GFXCLOCK_LOWCOUNT +#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT 0x0 +#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK 0xFFFFFFFFL +//RLC_SPM_GFXCLOCK_HIGHCOUNT +#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT 0x0 +#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK 0xFFFFFFFFL +//RLC_SPM_GTS_TRIGGER_VALUE_LO +#define RLC_SPM_GTS_TRIGGER_VALUE_LO__VALUE_LO__SHIFT 0x0 +#define RLC_SPM_GTS_TRIGGER_VALUE_LO__VALUE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_GTS_TRIGGER_VALUE_HI +#define RLC_SPM_GTS_TRIGGER_VALUE_HI__VALUE_HI__SHIFT 0x0 +#define RLC_SPM_GTS_TRIGGER_VALUE_HI__VALUE_HI_MASK 0x00FFFFFFL +//RLC_SPM_GLOBAL_USER_DATA_0 +#define RLC_SPM_GLOBAL_USER_DATA_0__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_0__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_0__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_0__HI_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_USER_DATA_1 +#define RLC_SPM_GLOBAL_USER_DATA_1__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_1__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_1__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_1__HI_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_USER_DATA_2 +#define RLC_SPM_GLOBAL_USER_DATA_2__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_2__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_2__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_2__HI_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_USER_DATA_3 +#define RLC_SPM_GLOBAL_USER_DATA_3__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_3__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_3__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_3__HI_MASK 0xFFFF0000L +//RLC_SPM_MODE +#define RLC_SPM_MODE__MODE__SHIFT 0x0 +#define RLC_SPM_MODE__MODE_MASK 0x00000001L +//RLC_SPM_RSPM_REQ_DATA +#define RLC_SPM_RSPM_REQ_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_DATA__DATA_MASK 0x0000000FL +//RLC_SPM_RSPM_REQ_OP +#define RLC_SPM_RSPM_REQ_OP__OP__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_OP__OP_MASK 0x0000000FL +//RLC_SPM_RSPM_RET_DATA +#define RLC_SPM_RSPM_RET_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RSPM_RET_OP +#define RLC_SPM_RSPM_RET_OP__OP__SHIFT 0x0 +#define RLC_SPM_RSPM_RET_OP__VALID__SHIFT 0x8 +#define RLC_SPM_RSPM_RET_OP__OP_MASK 0x0000000FL +#define RLC_SPM_RSPM_RET_OP__VALID_MASK 0x00000100L +//RLC_SPM_SE_RSPM_REQ_DATA +#define RLC_SPM_SE_RSPM_REQ_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_DATA__DATA_MASK 0x0000000FL +//RLC_SPM_SE_RSPM_REQ_OP +#define RLC_SPM_SE_RSPM_REQ_OP__OP__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_OP__OP_MASK 0x0000000FL +//RLC_SPM_SE_RSPM_RET_DATA +#define RLC_SPM_SE_RSPM_RET_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_SE_RSPM_RET_OP +#define RLC_SPM_SE_RSPM_RET_OP__OP__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_RET_OP__VALID__SHIFT 0x8 +#define RLC_SPM_SE_RSPM_RET_OP__OP_MASK 0x0000000FL +#define RLC_SPM_SE_RSPM_RET_OP__VALID_MASK 0x00000100L +//RLC_SPM_RSPM_CMD +#define RLC_SPM_RSPM_CMD__CMD__SHIFT 0x0 +#define RLC_SPM_RSPM_CMD__CMD_MASK 0x0000000FL +//RLC_SPM_RSPM_CMD_ACK +#define RLC_SPM_RSPM_CMD_ACK__SE0_ACK__SHIFT 0x0 +#define RLC_SPM_RSPM_CMD_ACK__SE1_ACK__SHIFT 0x1 +#define RLC_SPM_RSPM_CMD_ACK__SE2_ACK__SHIFT 0x2 +#define RLC_SPM_RSPM_CMD_ACK__SE3_ACK__SHIFT 0x3 +#define RLC_SPM_RSPM_CMD_ACK__SE4_ACK__SHIFT 0x4 +#define RLC_SPM_RSPM_CMD_ACK__SE5_ACK__SHIFT 0x5 +#define RLC_SPM_RSPM_CMD_ACK__SE6_ACK__SHIFT 0x6 +#define RLC_SPM_RSPM_CMD_ACK__SE7_ACK__SHIFT 0x7 +#define RLC_SPM_RSPM_CMD_ACK__SPM_ACK__SHIFT 0x8 +#define RLC_SPM_RSPM_CMD_ACK__SE0_ACK_MASK 0x00000001L +#define RLC_SPM_RSPM_CMD_ACK__SE1_ACK_MASK 0x00000002L +#define RLC_SPM_RSPM_CMD_ACK__SE2_ACK_MASK 0x00000004L +#define RLC_SPM_RSPM_CMD_ACK__SE3_ACK_MASK 0x00000008L +#define RLC_SPM_RSPM_CMD_ACK__SE4_ACK_MASK 0x00000010L +#define RLC_SPM_RSPM_CMD_ACK__SE5_ACK_MASK 0x00000020L +#define RLC_SPM_RSPM_CMD_ACK__SE6_ACK_MASK 0x00000040L +#define RLC_SPM_RSPM_CMD_ACK__SE7_ACK_MASK 0x00000080L +#define RLC_SPM_RSPM_CMD_ACK__SPM_ACK_MASK 0x00000100L +//RLC_SPM_SPARE +#define RLC_SPM_SPARE__SPARE__SHIFT 0x0 +#define RLC_SPM_SPARE__SPARE_MASK 0xFFFFFFFFL +//RLC_PERFMON_CNTL +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__RESERVED_9_3__SHIFT 0x3 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFMON_CNTL__RESERVED__SHIFT 0xb +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__RESERVED_9_3_MASK 0x000003F8L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define RLC_PERFMON_CNTL__RESERVED_MASK 0xFFFFF800L +//RLC_PERFCOUNTER0_SELECT +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL +//RLC_PERFCOUNTER1_SELECT +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL +//RLC_GPU_IOV_PERF_CNT_CNTL +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_GPU_IOV_PERF_CNT_WR_ADDR +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x5 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x7 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000001FL +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000060L +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_GPU_IOV_PERF_CNT_WR_DATA +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_PERF_CNT_RD_ADDR +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x5 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x7 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000001FL +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000060L +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_GPU_IOV_PERF_CNT_RD_DATA +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_SELECT +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GCR_PERFCOUNTER0_SELECT1 +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GCR_PERFCOUNTER1_SELECT +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GCR_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCR_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GCR_PERFCOUNTER1_SELECT1 +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER0_SELECT +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER0_SELECT1 +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER1_SELECT +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER1_SELECT1 +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER2_SELECT +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER2_SELECT1 +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER3_SELECT +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER3_SELECT1 +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk +//XVMIN_XVMIN_WR_DATA +#define XVMIN_XVMIN_WR_DATA__XVMINDATA__SHIFT 0x0 +#define XVMIN_XVMIN_WR_DATA__XVMINDATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_hypdec +//RLC_GPU_IOV_VF_ENABLE +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L +//RLC_FED_DRVR_STATUS +#define RLC_FED_DRVR_STATUS__PENDING__SHIFT 0x0 +#define RLC_FED_DRVR_STATUS__PENDING_MASK 0x00000007L +//RLC_GPU_IOV_CFG_REG6 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L +//RLC_SDMA0_STATUS +#define RLC_SDMA0_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA1_STATUS +#define RLC_SDMA1_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA2_STATUS +#define RLC_SDMA2_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA3_STATUS +#define RLC_SDMA3_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA0_BUSY_STATUS +#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA1_BUSY_STATUS +#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA2_BUSY_STATUS +#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA3_BUSY_STATUS +#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_CFG_REG8 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VF_DOORBELL_STATUS +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L +//RLC_GPU_IOV_VF_MASK +#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 +#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x1f +#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0x80000000L +//RLC_HYP_SEMAPHORE_0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +//RLC_HYP_SEMAPHORE_1 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +//RLC_BUSY_CLK_CNTL +#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0 +#define RLC_BUSY_CLK_CNTL__RESERVED__SHIFT 0x6 +#define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY__SHIFT 0x8 +#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL +#define RLC_BUSY_CLK_CNTL__RESERVED_MASK 0x000000C0L +#define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY_MASK 0x00003F00L +//RLC_CLK_CNTL +#define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE__SHIFT 0x1 +#define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE__SHIFT 0x2 +#define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE__SHIFT 0x3 +#define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE__SHIFT 0x4 +#define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE__SHIFT 0x5 +#define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE__SHIFT 0x6 +#define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE__SHIFT 0x7 +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 +#define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9 +#define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT 0xa +#define RLC_CLK_CNTL__RESERVED_11__SHIFT 0xb +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc +#define RLC_CLK_CNTL__RLC_DFLL_ICG_OVERRIDE__SHIFT 0xd +#define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf +#define RLC_CLK_CNTL__RLC_LX6_CORE_ICG_OVERRIDE__SHIFT 0x10 +#define RLC_CLK_CNTL__RLC_LX6_ICG_OVERRIDE__SHIFT 0x11 +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 +#define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE__SHIFT 0x13 +#define RLC_CLK_CNTL__RLC_BRIDGE_ICG_OVERRIDE__SHIFT 0x14 +#define RLC_CLK_CNTL__RLC_DMA_ICG_OVERRIDE__SHIFT 0x15 +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x16 +#define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE_MASK 0x00000001L +#define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE_MASK 0x00000002L +#define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE_MASK 0x00000004L +#define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE_MASK 0x00000008L +#define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE_MASK 0x00000010L +#define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE_MASK 0x00000020L +#define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE_MASK 0x00000040L +#define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE_MASK 0x00000080L +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L +#define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L +#define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE_MASK 0x00000400L +#define RLC_CLK_CNTL__RESERVED_11_MASK 0x00000800L +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L +#define RLC_CLK_CNTL__RLC_DFLL_ICG_OVERRIDE_MASK 0x00002000L +#define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L +#define RLC_CLK_CNTL__RLC_LX6_CORE_ICG_OVERRIDE_MASK 0x00010000L +#define RLC_CLK_CNTL__RLC_LX6_ICG_OVERRIDE_MASK 0x00020000L +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L +#define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE_MASK 0x00080000L +#define RLC_CLK_CNTL__RLC_BRIDGE_ICG_OVERRIDE_MASK 0x00100000L +#define RLC_CLK_CNTL__RLC_DMA_ICG_OVERRIDE_MASK 0x00200000L +#define RLC_CLK_CNTL__RESERVED_MASK 0xFFC00000L +//RLC_GPU_IOV_SCH_BLOCK +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x0000FF00L +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0xFFFF0000L +//RLC_GPU_IOV_CFG_REG1 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__PF_VF__SHIFT 0xf +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x00007F00L +#define RLC_GPU_IOV_CFG_REG1__PF_VF_MASK 0x00008000L +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L +//RLC_GPU_IOV_CFG_REG2 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VM_BUSY_STATUS +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_ACTIVE_FCN_ID +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_6_5__SHIFT 0x5 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x7 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__ACTIVE_FCN_ID_STATUS__SHIFT 0x8 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_31_12__SHIFT 0xc +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_6_5_MASK 0x00000060L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x00000080L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__ACTIVE_FCN_ID_STATUS_MASK 0x00000F00L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_31_12_MASK 0xFFFFF000L +//RLC_GPU_IOV_SCH_3 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_1 +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_2 +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL +//RLC_IH_COOKIE +#define RLC_IH_COOKIE__DATA__SHIFT 0x0 +#define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL +//RLC_IH_COOKIE_CNTL +#define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0 +#define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2 +#define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L +#define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L +//RLC_HYP_RLCG_UCODE_CHKSUM +#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SMU_RESPONSE +#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VIRT_RESET_REQ +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L +//RLC_GPU_IOV_RLC_RESPONSE +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_HYP_SEMAPHORE_2 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +//RLC_HYP_SEMAPHORE_3 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +//RLC_GPM_UCODE_ADDR +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L +//RLC_GPM_UCODE_DATA +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPM_IRAM_ADDR +#define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL +//RLC_GPM_IRAM_DATA +#define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_DRAM_ADDR +#define RLC_LX6_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_LX6_DRAM_ADDR__ADDR_MASK 0x000007FFL +//RLC_LX6_DRAM_DATA +#define RLC_LX6_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_LX6_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_IRAM_ADDR +#define RLC_LX6_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_LX6_IRAM_ADDR__ADDR_MASK 0x00000FFFL +//RLC_LX6_IRAM_DATA +#define RLC_LX6_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_LX6_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_SCRATCH_ADDR +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL +//RLC_GPM_SCRATCH_DATA +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_DRAM_ADDR +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xd +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00001FFFL +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFE000L +//RLC_SRM_DRAM_DATA +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_ARAM_ADDR +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xd +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00001FFFL +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFE000L +//RLC_SRM_ARAM_DATA +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_LSB +#define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_MSB +#define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_SNAP_LSB +#define RLC_GTS_OFFSET_SNAP_LSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_SNAP_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_SNAP_MSB +#define RLC_GTS_OFFSET_SNAP_MSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_SNAP_MSB__DATA_MASK 0xFFFFFFFFL +//RLC_GAP_PWROK +#define RLC_GAP_PWROK__GAP_PWROK__SHIFT 0x0 +#define RLC_GAP_PWROK__GAP_PWROK_MASK 0x00000001L +//RLC_GAP_PWROK_COUNT +#define RLC_GAP_PWROK_COUNT__COUNT__SHIFT 0x0 +#define RLC_GAP_PWROK_COUNT__COUNT_MASK 0x0000000FL +//GLARB_HASH_CFG +#define GLARB_HASH_CFG__HPA_HASH_EN__SHIFT 0x0 +#define GLARB_HASH_CFG__CHANNEL_HASH_EN__SHIFT 0x13 +#define GLARB_HASH_CFG__RESERVED__SHIFT 0x14 +#define GLARB_HASH_CFG__HPA_HASH_EN_MASK 0x00000001L +#define GLARB_HASH_CFG__CHANNEL_HASH_EN_MASK 0x00080000L +#define GLARB_HASH_CFG__RESERVED_MASK 0xFFF00000L +//CH_PIPE_STEER +#define CH_PIPE_STEER__PIPE0__SHIFT 0x0 +#define CH_PIPE_STEER__PIPE1__SHIFT 0x1 +#define CH_PIPE_STEER__MODE__SHIFT 0x2 +#define CH_PIPE_STEER__PIPE0_MASK 0x00000001L +#define CH_PIPE_STEER__PIPE1_MASK 0x00000002L +#define CH_PIPE_STEER__MODE_MASK 0x00000004L +//GLARB_PIPE_STEER_LSB +#define GLARB_PIPE_STEER_LSB__PIPE0__SHIFT 0x0 +#define GLARB_PIPE_STEER_LSB__PIPE1__SHIFT 0x4 +#define GLARB_PIPE_STEER_LSB__PIPE2__SHIFT 0x8 +#define GLARB_PIPE_STEER_LSB__PIPE3__SHIFT 0xc +#define GLARB_PIPE_STEER_LSB__PIPE4__SHIFT 0x10 +#define GLARB_PIPE_STEER_LSB__PIPE5__SHIFT 0x14 +#define GLARB_PIPE_STEER_LSB__PIPE6__SHIFT 0x18 +#define GLARB_PIPE_STEER_LSB__PIPE7__SHIFT 0x1c +#define GLARB_PIPE_STEER_LSB__PIPE0_MASK 0x0000000FL +#define GLARB_PIPE_STEER_LSB__PIPE1_MASK 0x000000F0L +#define GLARB_PIPE_STEER_LSB__PIPE2_MASK 0x00000F00L +#define GLARB_PIPE_STEER_LSB__PIPE3_MASK 0x0000F000L +#define GLARB_PIPE_STEER_LSB__PIPE4_MASK 0x000F0000L +#define GLARB_PIPE_STEER_LSB__PIPE5_MASK 0x00F00000L +#define GLARB_PIPE_STEER_LSB__PIPE6_MASK 0x0F000000L +#define GLARB_PIPE_STEER_LSB__PIPE7_MASK 0xF0000000L +//GLARB_PIPE_STEER_MSB +#define GLARB_PIPE_STEER_MSB__PIPE8__SHIFT 0x0 +#define GLARB_PIPE_STEER_MSB__PIPE9__SHIFT 0x4 +#define GLARB_PIPE_STEER_MSB__PIPE10__SHIFT 0x8 +#define GLARB_PIPE_STEER_MSB__PIPE11__SHIFT 0xc +#define GLARB_PIPE_STEER_MSB__MODE__SHIFT 0x10 +#define GLARB_PIPE_STEER_MSB__PIPE8_MASK 0x0000000FL +#define GLARB_PIPE_STEER_MSB__PIPE9_MASK 0x000000F0L +#define GLARB_PIPE_STEER_MSB__PIPE10_MASK 0x00000F00L +#define GLARB_PIPE_STEER_MSB__PIPE11_MASK 0x0000F000L +#define GLARB_PIPE_STEER_MSB__MODE_MASK 0x00010000L +//CH_HASH_CFG +#define CH_HASH_CFG__CHANNEL_FLIP__SHIFT 0x12 +#define CH_HASH_CFG__CHANNEL_HASH_EN__SHIFT 0x13 +#define CH_HASH_CFG__RESERVED__SHIFT 0x14 +#define CH_HASH_CFG__CHANNEL_FLIP_MASK 0x00040000L +#define CH_HASH_CFG__CHANNEL_HASH_EN_MASK 0x00080000L +#define CH_HASH_CFG__RESERVED_MASK 0xFFF00000L +//GLARB_LPDDR_PIPE_STEER_LSB +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE0__SHIFT 0x0 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE1__SHIFT 0x4 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE2__SHIFT 0x8 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE3__SHIFT 0xc +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE4__SHIFT 0x10 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE5__SHIFT 0x14 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE6__SHIFT 0x18 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE7__SHIFT 0x1c +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE0_MASK 0x0000000FL +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE1_MASK 0x000000F0L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE2_MASK 0x00000F00L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE3_MASK 0x0000F000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE4_MASK 0x000F0000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE5_MASK 0x00F00000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE6_MASK 0x0F000000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE7_MASK 0xF0000000L +//GLARB_LPDDR_PIPE_STEER_MSB +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE8__SHIFT 0x0 +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE9__SHIFT 0x4 +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE10__SHIFT 0x8 +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE11__SHIFT 0xc +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE8_MASK 0x0000000FL +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE9_MASK 0x000000F0L +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE10_MASK 0x00000F00L +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE11_MASK 0x0000F000L +//GLARB_LOCAL_CAC +#define GLARB_LOCAL_CAC__THRESHOLD__SHIFT 0x0 +#define GLARB_LOCAL_CAC__OVERRIDE_EN__SHIFT 0x10 +#define GLARB_LOCAL_CAC__OVERRIDE_VAL__SHIFT 0x11 +#define GLARB_LOCAL_CAC__THRESHOLD_MASK 0x0000FFFFL +#define GLARB_LOCAL_CAC__OVERRIDE_EN_MASK 0x00010000L +#define GLARB_LOCAL_CAC__OVERRIDE_VAL_MASK 0x1FFE0000L +//GLARB_AID_SEL_CFG +#define GLARB_AID_SEL_CFG__AS_SEL__SHIFT 0x0 +#define GLARB_AID_SEL_CFG__RESERVED__SHIFT 0x5 +#define GLARB_AID_SEL_CFG__AS_SEL_MASK 0x0000001FL +#define GLARB_AID_SEL_CFG__RESERVED_MASK 0xFFFFFFE0L +//GC_USER_FULL_SA_UNIT_DISABLE +#define GC_USER_FULL_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define GC_USER_FULL_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x03FFFF00L +//GC_USER_SA_UNIT_DISABLE +#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L +//GC_USER_HBM_DISABLE +#define GC_USER_HBM_DISABLE__GC_USER_HBM_DISABLE__SHIFT 0x10 +#define GC_USER_HBM_DISABLE__GC_USER_HBM_DISABLE_MASK 0x0FFF0000L +//RLC_GPU_IOV_SDMA0_STATUS +#define RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_STATUS +#define RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA2_STATUS +#define RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_STATUS +#define RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_STATUS +#define RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_STATUS +#define RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_STATUS +#define RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_STATUS +#define RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA0_BUSY_STATUS +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_BUSY_STATUS +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA2_BUSY_STATUS +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_BUSY_STATUS +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_BUSY_STATUS +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_BUSY_STATUS +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_BUSY_STATUS +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_BUSY_STATUS +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cphypdec +//CP_HYP_CONTEXT_RANGE_BASE +#define CP_HYP_CONTEXT_RANGE_BASE__BASE__SHIFT 0x0 +#define CP_HYP_CONTEXT_RANGE_BASE__BASE_MASK 0x0003FFFFL +//CP_HYP_CONTEXT_RANGE_END +#define CP_HYP_CONTEXT_RANGE_END__END__SHIFT 0x0 +#define CP_HYP_CONTEXT_RANGE_END__END_MASK 0x0003FFFFL +//CP_HYP_PFP_UCODE_ADDR +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_ADDR__PIPE_SEL__SHIFT 0x1f +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_HYP_PFP_UCODE_ADDR__PIPE_SEL_MASK 0x80000000L +//CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__PIPE_SEL__SHIFT 0x1f +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_PFP_UCODE_ADDR__PIPE_SEL_MASK 0x80000000L +//CP_HYP_PFP_UCODE_DATA +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_ADDR +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_ME_UCODE_ADDR__PIPE_SEL__SHIFT 0x1f +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_HYP_ME_UCODE_ADDR__PIPE_SEL_MASK 0x80000000L +//CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_RADDR__PIPE_SEL__SHIFT 0x1f +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000000FFL +#define CP_ME_RAM_RADDR__PIPE_SEL_MASK 0x80000000L +//CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__PIPE_SEL__SHIFT 0x1f +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000000FFL +#define CP_ME_RAM_WADDR__PIPE_SEL_MASK 0x80000000L +//CP_HYP_ME_UCODE_DATA +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC1_UCODE_ADDR +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_ADDR__PIPE_SEL__SHIFT 0x1e +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_HYP_MEC1_UCODE_ADDR__PIPE_SEL_MASK 0xC0000000L +//CP_MEC_ME1_UCODE_ADDR +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__PIPE_SEL__SHIFT 0x1e +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_MEC_ME1_UCODE_ADDR__PIPE_SEL_MASK 0xC0000000L +//CP_HYP_MEC1_UCODE_DATA +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME1_UCODE_DATA +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_PFP_UCODE_CHKSUM +#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_CHKSUM +#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_MEC_ME1_UCODE_CHKSUM +#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_PFP_IC_BASE_LO +#define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_PFP_IC_BASE_HI +#define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_PFP_IC_BASE_CNTL +#define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_PFP_IC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_PFP_IC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_PFP_IC_OP_CNTL +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_PFP_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_PFP_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_ME_IC_BASE_LO +#define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_ME_IC_BASE_HI +#define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_ME_IC_BASE_CNTL +#define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_ME_IC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_ME_IC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_ME_IC_OP_CNTL +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_ME_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_ME_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_CPC_IC_BASE_LO +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_CPC_IC_BASE_HI +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x01FFFFFFL +//CP_CPC_IC_BASE_CNTL +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__PER_PIPE__SHIFT 0x5 +#define CP_CPC_IC_BASE_CNTL__SCOPE__SHIFT 0x6 +#define CP_CPC_IC_BASE_CNTL__TEMPORAL__SHIFT 0x8 +#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_CPC_IC_BASE_CNTL__PER_PIPE_MASK 0x00000020L +#define CP_CPC_IC_BASE_CNTL__SCOPE_MASK 0x000000C0L +#define CP_CPC_IC_BASE_CNTL__TEMPORAL_MASK 0x00000700L +#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MES_IC_BASE_LO +#define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_MES_MIBASE_LO +#define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_MES_IC_BASE_HI +#define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x01FFFFFFL +//CP_MES_MIBASE_HI +#define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_MES_IC_BASE_CNTL +#define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MES_IC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_MES_IC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_MES_DC_BASE_LO +#define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_MES_MDBASE_LO +#define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_DC_BASE_HI +#define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x01FFFFFFL +//CP_MES_MDBASE_HI +#define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_MDBASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MES_MIBOUND_LO +#define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MES_MIBOUND_HI +#define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_MES_MDBOUND_LO +#define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MES_MDBOUND_HI +#define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_HYP_PFP_UCODE_VERS +#define CP_HYP_PFP_UCODE_VERS__ENGINE__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_VERS__COMMON__SHIFT 0xa +#define CP_HYP_PFP_UCODE_VERS__HEADER__SHIFT 0x14 +#define CP_HYP_PFP_UCODE_VERS__STEP__SHIFT 0x1e +#define CP_HYP_PFP_UCODE_VERS__ENGINE_MASK 0x000003FFL +#define CP_HYP_PFP_UCODE_VERS__COMMON_MASK 0x000FFC00L +#define CP_HYP_PFP_UCODE_VERS__HEADER_MASK 0x3FF00000L +#define CP_HYP_PFP_UCODE_VERS__STEP_MASK 0xC0000000L +//CP_HYP_ME_UCODE_VERS +#define CP_HYP_ME_UCODE_VERS__ENGINE__SHIFT 0x0 +#define CP_HYP_ME_UCODE_VERS__COMMON__SHIFT 0xa +#define CP_HYP_ME_UCODE_VERS__HEADER__SHIFT 0x14 +#define CP_HYP_ME_UCODE_VERS__STEP__SHIFT 0x1e +#define CP_HYP_ME_UCODE_VERS__ENGINE_MASK 0x000003FFL +#define CP_HYP_ME_UCODE_VERS__COMMON_MASK 0x000FFC00L +#define CP_HYP_ME_UCODE_VERS__HEADER_MASK 0x3FF00000L +#define CP_HYP_ME_UCODE_VERS__STEP_MASK 0xC0000000L +//CP_GFX_RS64_DC_BASE0_LO +#define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_DC_BASE1_LO +#define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_DC_BASE0_HI +#define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_DC_BASE1_HI +#define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_MIBOUND_LO +#define CP_GFX_RS64_MIBOUND_LO__BOUND__SHIFT 0x0 +#define CP_GFX_RS64_MIBOUND_LO__BOUND_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIBOUND_HI +#define CP_GFX_RS64_MIBOUND_HI__BOUND__SHIFT 0x0 +#define CP_GFX_RS64_MIBOUND_HI__BOUND_MASK 0xFFFFFFFFL +//CP_MEC_DC_BASE_LO +#define CP_MEC_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_MEC_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_MEC_MDBASE_LO +#define CP_MEC_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_DC_BASE_HI +#define CP_MEC_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_MEC_DC_BASE_HI__DC_BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_MDBASE_HI +#define CP_MEC_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_MDBASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_MIBOUND_LO +#define CP_MEC_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MEC_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MEC_MIBOUND_HI +#define CP_MEC_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MEC_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_MEC_MDBOUND_LO +#define CP_MEC_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MEC_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MEC_MDBOUND_HI +#define CP_MEC_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MEC_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbm_hypdec +//GRBM_GFX_INDEX_SR_SELECT +#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_INDEX_SR_DATA +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x0000007FL +#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x00000300L +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x000F0000L +#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_SELECT +#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_DATA +#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL_SR_DATA__CTXID__SHIFT 0xb +#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L +#define GRBM_GFX_CNTL_SR_DATA__CTXID_MASK 0x00003800L +//GC_IH_COOKIE_0_PTR_HIGH +#define GC_IH_COOKIE_0_PTR_HIGH__ADDR__SHIFT 0x0 +#define GC_IH_COOKIE_0_PTR_HIGH__ADDR_MASK 0x0000FFFFL +//GC_IH_COOKIE_0_PTR +#define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0 +#define GC_IH_COOKIE_0_PTR__ADDR_MASK 0xFFFFFFFFL +//GRBM_SE_REMAP_CNTL +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT 0x0 +#define GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT 0x1 +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT 0x4 +#define GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT 0x5 +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT 0x8 +#define GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT 0x9 +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT 0xc +#define GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT 0xd +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT 0x10 +#define GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT 0x11 +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT 0x14 +#define GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT 0x15 +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT 0x18 +#define GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT 0x19 +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT 0x1c +#define GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT 0x1d +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK 0x00000001L +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK 0x0000000EL +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK 0x00000010L +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK 0x000000E0L +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK 0x00000100L +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK 0x00000E00L +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK 0x00001000L +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK 0x0000E000L +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK 0x00010000L +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK 0x000E0000L +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK 0x00100000L +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK 0x00E00000L +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK 0x01000000L +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK 0x0E000000L +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK 0x10000000L +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK 0xE0000000L +//GRBM_SA_REMAP_CNTL +#define GRBM_SA_REMAP_CNTL__SE0_SA_REMAP__SHIFT 0x0 +#define GRBM_SA_REMAP_CNTL__SE1_SA_REMAP__SHIFT 0x2 +#define GRBM_SA_REMAP_CNTL__SE2_SA_REMAP__SHIFT 0x4 +#define GRBM_SA_REMAP_CNTL__SE3_SA_REMAP__SHIFT 0x6 +#define GRBM_SA_REMAP_CNTL__SE4_SA_REMAP__SHIFT 0x8 +#define GRBM_SA_REMAP_CNTL__SE5_SA_REMAP__SHIFT 0xa +#define GRBM_SA_REMAP_CNTL__SE6_SA_REMAP__SHIFT 0xc +#define GRBM_SA_REMAP_CNTL__SE7_SA_REMAP__SHIFT 0xe +#define GRBM_SA_REMAP_CNTL__SE0_SA_REMAP_MASK 0x00000003L +#define GRBM_SA_REMAP_CNTL__SE1_SA_REMAP_MASK 0x0000000CL +#define GRBM_SA_REMAP_CNTL__SE2_SA_REMAP_MASK 0x00000030L +#define GRBM_SA_REMAP_CNTL__SE3_SA_REMAP_MASK 0x000000C0L +#define GRBM_SA_REMAP_CNTL__SE4_SA_REMAP_MASK 0x00000300L +#define GRBM_SA_REMAP_CNTL__SE5_SA_REMAP_MASK 0x00000C00L +#define GRBM_SA_REMAP_CNTL__SE6_SA_REMAP_MASK 0x00003000L +#define GRBM_SA_REMAP_CNTL__SE7_SA_REMAP_MASK 0x0000C000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcdec +//RLC_CNTL +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__POISON_INTR_ON_IH_COOKIE_OR_IH_GASKET__SHIFT 0x4 +#define RLC_CNTL__POISON_INTERRUPT_TO_PF__SHIFT 0x5 +#define RLC_CNTL__RESERVED__SHIFT 0x6 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__POISON_INTR_ON_IH_COOKIE_OR_IH_GASKET_MASK 0x00000010L +#define RLC_CNTL__POISON_INTERRUPT_TO_PF_MASK 0x00000020L +#define RLC_CNTL__RESERVED_MASK 0xFFFFFFC0L +//RLC_F32_UCODE_VERSION +#define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0 +#define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa +#define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14 +#define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL +#define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L +#define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L +//RLC_STAT +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 +#define RLC_STAT__MC_BUSY__SHIFT 0x4 +#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 +#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 +#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 +#define RLC_STAT__RLC_DMA_BUSY__SHIFT 0x8 +#define RLC_STAT__RESERVED__SHIFT 0x9 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L +#define RLC_STAT__MC_BUSY_MASK 0x00000010L +#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L +#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L +#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L +#define RLC_STAT__RLC_DMA_BUSY_MASK 0x00000100L +#define RLC_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_ACTIVE_MASK +#define RLC_ACTIVE_MASK__SE__SHIFT 0x0 +#define RLC_ACTIVE_MASK__SE_MASK 0x000000FFL +//RLC_GFX_SE_STATUS +#define RLC_GFX_SE_STATUS__SQG_TTRACE_HALT__SHIFT 0x0 +#define RLC_GFX_SE_STATUS__SQG_TTRACE_HALT_MASK 0x00000003L +//RLC_REFCLOCK_TIMESTAMP_LSB +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL +//RLC_REFCLOCK_TIMESTAMP_MSB +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_0 +#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_1 +#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_2 +#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_3 +#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_4 +#define RLC_GPM_TIMER_INT_4__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_4__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_CTRL +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 +#define RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT 0x4 +#define RLC_GPM_TIMER_CTRL__RESERVED_1__SHIFT 0x5 +#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x8 +#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x9 +#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0xa +#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0xb +#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT 0xc +#define RLC_GPM_TIMER_CTRL__RESERVED_2__SHIFT 0xd +#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x10 +#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x11 +#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0x12 +#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0x13 +#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT 0x14 +#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x15 +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L +#define RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK 0x00000010L +#define RLC_GPM_TIMER_CTRL__RESERVED_1_MASK 0x000000E0L +#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000100L +#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000200L +#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000400L +#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000800L +#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK 0x00001000L +#define RLC_GPM_TIMER_CTRL__RESERVED_2_MASK 0x0000E000L +#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00010000L +#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00020000L +#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00040000L +#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00080000L +#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK 0x00100000L +#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFE00000L +//RLC_GPM_TIMER_STAT +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 +#define RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT 0x4 +#define RLC_GPM_TIMER_STAT__RESERVED_1__SHIFT 0x5 +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb +#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT 0xc +#define RLC_GPM_TIMER_STAT__RESERVED_2__SHIFT 0xd +#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0x10 +#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0x11 +#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0x12 +#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0x13 +#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT 0x14 +#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x15 +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L +#define RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK 0x00000010L +#define RLC_GPM_TIMER_STAT__RESERVED_1_MASK 0x000000E0L +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L +#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK 0x00001000L +#define RLC_GPM_TIMER_STAT__RESERVED_2_MASK 0x0000E000L +#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00010000L +#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00020000L +#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00040000L +#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00080000L +#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK 0x00100000L +#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFE00000L +//RLC_GPM_LEGACY_INT_STAT +#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_STAT__RESERVED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_STAT__STORE_LOAD_TIMER3_EXPIRED_T0__SHIFT 0x4 +#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_STAT__RESERVED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +#define RLC_GPM_LEGACY_INT_STAT__STORE_LOAD_TIMER3_EXPIRED_T0_MASK 0x00000010L +//RLC_GPM_LEGACY_INT_CLEAR +#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_4__SHIFT 0x4 +#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_4_MASK 0x00000010L +//RLC_INT_STAT +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 +#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 +#define RLC_INT_STAT__RESERVED__SHIFT 0x9 +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL +#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L +#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_MGCG_CTRL +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L +#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L +//RLC_MCA_DF_RASINTRCTRL_REG_CTRL +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VMID__SHIFT 0x0 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_SRCID__SHIFT 0x4 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_CTXID__SHIFT 0x8 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_ME_ID__SHIFT 0xb +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_PIPE_ID__SHIFT 0xd +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_QUEUE_ID__SHIFT 0xf +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_TMZ__SHIFT 0x12 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VF__SHIFT 0x13 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VFID__SHIFT 0x14 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VMID_MASK 0x0000000FL +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_SRCID_MASK 0x000000F0L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_CTXID_MASK 0x00000700L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_ME_ID_MASK 0x00001800L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_PIPE_ID_MASK 0x00006000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_QUEUE_ID_MASK 0x00038000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_TMZ_MASK 0x00040000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VF_MASK 0x00080000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VFID_MASK 0x01F00000L +//RLC_JUMP_TABLE_RESTORE +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_2 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L +//RLC_GPU_CLOCK_COUNT_LSB +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL +//RLC_UCODE_CNTL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL +//RLC_GPM_THREAD_RESET +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_CP_DMA_COMPLETE_T0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_CP_DMA_COMPLETE_T1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_THREAD_INVALIDATE_CACHE +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE__SHIFT 0x0 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE__SHIFT 0x1 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE__SHIFT 0x2 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE__SHIFT 0x3 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE_MASK 0x00000001L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE_MASK 0x00000002L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE_MASK 0x00000004L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE_MASK 0x00000008L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED_MASK 0xFFFFFFF0L +//RLC_MCA_DF_RASINTRCTRL_REG_LO +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__ADDR__SHIFT 0x0 +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__APERTURE__SHIFT 0x14 +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__ADDR_MASK 0x000FFFFFL +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__APERTURE_MASK 0xFFF00000L +//RLC_MCA_DF_RASINTRCTRL_REG_HI +#define RLC_MCA_DF_RASINTRCTRL_REG_HI__MCM_ADDR__SHIFT 0x0 +#define RLC_MCA_DF_RASINTRCTRL_REG_HI__MCM_ADDR_MASK 0x0000FFFFL +//RLC_MCA_INTR_CTRL +#define RLC_MCA_INTR_CTRL__MCA_INTR_HYSTERISIS_CNTR__SHIFT 0x0 +#define RLC_MCA_INTR_CTRL__MCA_INTR_BY_RLC_FW__SHIFT 0x10 +#define RLC_MCA_INTR_CTRL__MCA_INTR_HYSTERISIS_CNTR_MASK 0x0000FFFFL +#define RLC_MCA_INTR_CTRL__MCA_INTR_BY_RLC_FW_MASK 0x00010000L +//RLC_MCA_INTR_INFO +#define RLC_MCA_INTR_INFO__MCA_INTREQ_INFO__SHIFT 0x0 +#define RLC_MCA_INTR_INFO__MCA_FatalOut_INFO__SHIFT 0x8 +#define RLC_MCA_INTR_INFO__MCA_MASTERCOREID_REG_OFFSET__SHIFT 0x10 +#define RLC_MCA_INTR_INFO__MCA_INTERRUPT_SERVICED_BY_RLC_FW__SHIFT 0x1f +#define RLC_MCA_INTR_INFO__MCA_INTREQ_INFO_MASK 0x0000000FL +#define RLC_MCA_INTR_INFO__MCA_FatalOut_INFO_MASK 0x00000100L +#define RLC_MCA_INTR_INFO__MCA_MASTERCOREID_REG_OFFSET_MASK 0x01FF0000L +#define RLC_MCA_INTR_INFO__MCA_INTERRUPT_SERVICED_BY_RLC_FW_MASK 0x80000000L +//RLC_CLK_COUNT_GFXCLK_LSB +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_GFXCLK_MSB +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_LSB +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_MSB +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_CTRL +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L +//RLC_CLK_COUNT_STAT +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 +#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 +#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L +#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L +#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCG_DOORBELL_CNTL +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCG_DOORBELL_CNTL__RESERVED__SHIFT 0x8 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_31_22__SHIFT 0x16 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_MASK 0x0000FF00L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_31_22_MASK 0xFFC00000L +//RLC_RLCG_DOORBELL_STAT +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCG_DOORBELL_0_DATA_LO +#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_0_DATA_HI +#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_1_DATA_LO +#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_1_DATA_HI +#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_2_DATA_LO +#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_2_DATA_HI +#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_3_DATA_LO +#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_3_DATA_HI +#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_32_RES_SEL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_CLOCK_32 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL +//RLC_PG_CNTL +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__MEM_DS_DISABLE__SHIFT 0xd +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 +#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT 0x17 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L +#define RLC_PG_CNTL__RESERVED_MASK 0x00001FE0L +#define RLC_PG_CNTL__MEM_DS_DISABLE_MASK 0x00002000L +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__RESERVED1_MASK 0x00180000L +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L +#define RLC_PG_CNTL__RESERVED2_MASK 0x00400000L +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK 0x00800000L +//RLC_GPM_THREAD_PRIORITY +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L +//RLC_GPM_THREAD_ENABLE +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCG_DOORBELL_RANGE +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_15_12__SHIFT 0xc +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_31_28__SHIFT 0x1c +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_15_12_MASK 0x0000F000L +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_31_28_MASK 0xF0000000L +//RLC_CGTT_MGCG_OVERRIDE +#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT 0x0 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT 0xa +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_11__SHIFT 0xb +#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK 0x00000001L +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK 0x00000400L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_11_MASK 0xFFFFF800L +//RLC_CGCG_CGLS_CTRL +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_DYN_PG_STATUS +#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 +#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_DYN_PG_REQUEST +#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_PG_DELAY +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L +//RLC_CGCG_CGLS_CTRL_2 +#define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL_2__RESERVED__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_PG_ALWAYS_ON_WGP_MASK +#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0 +#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_MAX_PG_WGP +#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0 +#define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8 +#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL +#define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L +//RLC_AUTO_PG_CTRL +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L +//RLC_SERDES_RD_INDEX +#define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0 +#define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2 +#define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L +#define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL +//RLC_SERDES_RD_DATA_0 +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_1 +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_2 +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_3 +#define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_MASK +#define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0 +#define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1 +#define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L +#define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L +//RLC_SERDES_CTRL +#define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0 +#define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1 +#define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2 +#define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x4 +#define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10 +#define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L +#define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L +#define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L +#define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x007FF0L +#define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L +//RLC_SERDES_DATA +#define RLC_SERDES_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_BUSY +#define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0 +#define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1 +#define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2 +#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e +#define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f +#define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L +#define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L +#define RLC_SERDES_BUSY__RESERVED_MASK 0x3FFFFFFCL +#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L +#define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L +//RLC_GPM_GENERAL_0 +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_1 +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_2 +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_3 +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_4 +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_5 +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_6 +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_7 +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_STATIC_PG_STATUS +#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_16 +#define RLC_GPM_GENERAL_16__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_16__DATA_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_3 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xFFFFFFFFL +//RLC_GPR_REG1 +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL +//RLC_GPR_REG2 +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK 0xFFFFFFFFL +//RLC_GPM_LEGACY_INT_DISABLE +#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_DISABLE__RESERVED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_DISABLE__STORE_LOAD_TIMER3_EXPIRED_T0__SHIFT 0x4 +#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_DISABLE__RESERVED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +#define RLC_GPM_LEGACY_INT_DISABLE__STORE_LOAD_TIMER3_EXPIRED_T0_MASK 0x00000010L +//RLC_GPM_INT_FORCE_TH0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK 0xFFFFFFFFL +//RLC_SRM_CNTL +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__SRM_GPM_FIFO_RESET__SHIFT 0x2 +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x3 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L +#define RLC_SRM_CNTL__SRM_GPM_FIFO_RESET_MASK 0x00000004L +#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_SRM_GPM_COMMAND_STATUS +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_OVERFLOW__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x3 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_OVERFLOW_MASK 0x00000004L +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFF8L +//RLC_SRM_INDEX_CNTL_ADDR_0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_1 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_2 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_3 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_4 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_5 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_6 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_7 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_DATA_0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_1 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_2 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_3 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_4 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_5 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_6 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_7 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_STAT +#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 +#define RLC_SRM_STAT__RESERVED__SHIFT 0x1 +#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L +#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFEL +//RLC_LX6_UTCL1_ERROR_2 +#define RLC_LX6_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_LX6_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_8 +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_9 +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_10 +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_11 +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_12 +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_CNTL_0 +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_23_20__SHIFT 0x14 +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_23_20_MASK 0x00F00000L +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xE0000000L +//RLC_SPM_UTCL1_CNTL +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SPM_UTCL1_CNTL__RESERVED_23_20__SHIFT 0x14 +#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1d +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SPM_UTCL1_CNTL__RESERVED_23_20_MASK 0x00F00000L +#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xE0000000L +//RLC_UTCL1_STATUS_2 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_BUSY__SHIFT 0x4 +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_BUSY__SHIFT 0x5 +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_BUSY__SHIFT 0x6 +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_BUSY__SHIFT 0x7 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x8 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x9 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0xa +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0xb +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_StallOnTrans__SHIFT 0xc +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_StallOnTrans__SHIFT 0xd +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_StallOnTrans__SHIFT 0xe +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_StallOnTrans__SHIFT 0xf +#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0x10 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_BUSY_MASK 0x00000010L +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_BUSY_MASK 0x00000020L +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_BUSY_MASK 0x00000040L +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_BUSY_MASK 0x00000080L +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000100L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000200L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000400L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000800L +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_StallOnTrans_MASK 0x00001000L +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_StallOnTrans_MASK 0x00002000L +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_StallOnTrans_MASK 0x00004000L +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_StallOnTrans_MASK 0x00008000L +#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_UTCL1_ERROR_1 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_SPM_UTCL1_ERROR_2 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_1 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_GPM_UTCL1_TH0_ERROR_2 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_SEMAPHORE_0 +#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +//RLC_SEMAPHORE_1 +#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +//RLC_SEMAPHORE_2 +#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +//RLC_SEMAPHORE_3 +#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +//RLC_SRM_UTCL1_CNTL +#define RLC_SRM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SRM_UTCL1_CNTL__RESERVED_23_20__SHIFT 0x14 +#define RLC_SRM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SRM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SRM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SRM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SRM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SRM_UTCL1_CNTL__RESERVED__SHIFT 0x1d +#define RLC_SRM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SRM_UTCL1_CNTL__RESERVED_23_20_MASK 0x00F00000L +#define RLC_SRM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SRM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SRM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SRM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SRM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SRM_UTCL1_CNTL__RESERVED_MASK 0xE0000000L +//RLC_SRM_UTCL1_ERROR_1 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_SRM_UTCL1_ERROR_2 +#define RLC_SRM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SRM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_DLG_UTCL1_ERROR_2 +#define RLC_DLG_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_DLG_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_UTCL1_STATUS +#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 +#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e +#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L +#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L +//RLC_R2I_CNTL_0 +#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_1 +#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_2 +#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_3 +#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL +//RLC_GPM_INT_STAT_TH0 +#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 +#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_13 +#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_14 +#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_15 +#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_UTCL1_ERROR_1 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_LX6_UTCL1_CNTL +#define RLC_LX6_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_LX6_UTCL1_CNTL__RESERVED_23_20__SHIFT 0x14 +#define RLC_LX6_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_LX6_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_LX6_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_LX6_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_LX6_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_LX6_UTCL1_CNTL__RESERVED__SHIFT 0x1d +#define RLC_LX6_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_LX6_UTCL1_CNTL__RESERVED_23_20_MASK 0x00F00000L +#define RLC_LX6_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_LX6_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_LX6_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_LX6_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_LX6_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_LX6_UTCL1_CNTL__RESERVED_MASK 0xE0000000L +//RLC_DMA_UTCL1_ERROR_1 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_DMA_UTCL1_ERROR_2 +#define RLC_DMA_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_DMA_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_CLOCK_COUNT_LSB_2 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_2 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_2 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_DOORBELL_RANGE +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCV_DOORBELL_RANGE__RESERVED__SHIFT 0x1c +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +#define RLC_RLCV_DOORBELL_RANGE__RESERVED_MASK 0xF0000000L +//RLC_RLCV_DOORBELL_CNTL +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCV_DOORBELL_CNTL__RESERVED__SHIFT 0x16 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_RLCV_DOORBELL_CNTL__RESERVED_MASK 0xFFC00000L +//RLC_RLCV_DOORBELL_STAT +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCV_DOORBELL_0_DATA_LO +#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_0_DATA_HI +#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_1_DATA_LO +#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_1_DATA_HI +#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_2_DATA_LO +#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_2_DATA_HI +#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_3_DATA_LO +#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_3_DATA_HI +#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_LSB_1 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_1 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_RLCV_SPARE_INT +#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_CLK_REQ +#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 +#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L +//RLC_SPARE +#define RLC_SPARE__SPARE__SHIFT 0x0 +#define RLC_SPARE__SPARE_MASK 0xFFFFFFFFL +//RLC_SPP_CTRL +#define RLC_SPP_CTRL__ENABLE__SHIFT 0x0 +#define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1 +#define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2 +#define RLC_SPP_CTRL__PAUSE__SHIFT 0x3 +#define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L +#define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L +#define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L +#define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L +//RLC_SPP_SHADER_PROFILE_EN +#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0 +#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2 +#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3 +#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4 +#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5 +#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xb +#define RLC_SPP_SHADER_PROFILE_EN__CSG_START_CONDITION__SHIFT 0xc +#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf +#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10 +#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L +#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L +#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L +#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L +#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L +#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00000800L +#define RLC_SPP_SHADER_PROFILE_EN__CSG_START_CONDITION_MASK 0x00001000L +#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L +#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L +//RLC_SPP_SSF_CAPTURE_EN +#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0 +#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2 +#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3 +#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT 0x4 +#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5 +#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L +#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L +#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L +#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK 0x00000010L +#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L +//RLC_SPP_SSF_THRESHOLD_0 +#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_0__RESERVED__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_0__RESERVED_MASK 0xFFFF0000L +//RLC_SPP_SSF_THRESHOLD_1 +#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L +//RLC_SPP_SSF_THRESHOLD_2 +#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L +//RLC_SPP_INFLIGHT_RD_ADDR +#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL +//RLC_SPP_INFLIGHT_RD_DATA +#define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPP_PROF_INFO_1 +#define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0 +#define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL +//RLC_SPP_PROF_INFO_2 +#define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0 +#define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x5 +#define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x6 +#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x7 +#define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000001FL +#define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000020L +#define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000040L +#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000080L +//RLC_SPP_GLOBAL_SH_ID +#define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0 +#define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL +//RLC_SPP_GLOBAL_SH_ID_VALID +#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0 +#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L +//RLC_SPP_STATUS +#define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0 +#define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1 +#define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2 +#define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f +#define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L +#define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L +#define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L +#define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L +//RLC_SPP_PVT_STAT_0 +#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_1 +#define RLC_SPP_PVT_STAT_1__LEVEL_4_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_1__LEVEL_4_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_2 +#define RLC_SPP_PVT_STAT_2__LEVEL_8_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_2__LEVEL_9_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_2__LEVEL_8_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_2__LEVEL_9_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_3 +#define RLC_SPP_PVT_STAT_3__LEVEL_12_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_3__LEVEL_13_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_3__LEVEL_14_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_3__LEVEL_12_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_3__LEVEL_13_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_3__LEVEL_14_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_LEVEL_MAX +#define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0 +#define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL +//RLC_SPP_STALL_STATE_UPDATE +#define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0 +#define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1 +#define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L +#define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L +//RLC_SPP_PBB_INFO +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0 +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1 +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2 +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3 +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L +//RLC_SPP_RESET +#define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0 +#define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1 +#define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2 +#define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3 +#define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L +#define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L +#define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L +#define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L +//RLC_CAC_MASK_CNTL +#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT 0x0 +#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK 0xFFFFFFFFL +//RLC_POWER_RESIDENCY_CNTR_CTRL +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_CLK_RESIDENCY_CNTR_CTRL +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_DS_RESIDENCY_CNTR_CTRL +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_ULV_RESIDENCY_CNTR_CTRL +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_PCC_RESIDENCY_CNTR_CTRL +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_GENERAL_RESIDENCY_CNTR_CTRL +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_POWER_RESIDENCY_EVENT_CNTR +#define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_CLK_RESIDENCY_EVENT_CNTR +#define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_DS_RESIDENCY_EVENT_CNTR +#define RLC_DS_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_DS_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_ULV_RESIDENCY_EVENT_CNTR +#define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_PCC_RESIDENCY_EVENT_CNTR +#define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GENERAL_RESIDENCY_EVENT_CNTR +#define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_POWER_RESIDENCY_REF_CNTR +#define RLC_POWER_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_CLK_RESIDENCY_REF_CNTR +#define RLC_CLK_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_DS_RESIDENCY_REF_CNTR +#define RLC_DS_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_DS_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_ULV_RESIDENCY_REF_CNTR +#define RLC_ULV_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_PCC_RESIDENCY_REF_CNTR +#define RLC_PCC_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GENERAL_RESIDENCY_REF_CNTR +#define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IH_CLIENT_CTRL +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_13__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_MASK__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_29__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_ERROR_CLEAR__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_CTRL__IH_HALT__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK_MASK 0x000000FFL +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_13_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_MASK_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR_MASK 0x00FF0000L +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_29_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_ERROR_CLEAR_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_CTRL__IH_HALT_MASK 0x80000000L +//RLC_GFX_IH_ARBITER_STAT +#define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED__SHIFT 0x0 +#define RLC_GFX_IH_ARBITER_STAT__RESERVED__SHIFT 0x10 +#define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED__SHIFT 0x1c +#define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED_MASK 0x0000FFFFL +#define RLC_GFX_IH_ARBITER_STAT__RESERVED_MASK 0x0FFF0000L +#define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED_MASK 0xF0000000L +//RLC_GFX_IH_CLIENT_SE_STAT_L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_SE_STAT_H +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_SDMA_STAT +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_OTHER_STAT +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_24__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED_MASK 0x000000FFL +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED_MASK 0x0000FF00L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_24_MASK 0xFF000000L +//RLC_SPM_GLOBAL_DELAY_IND_ADDR +#define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_GLOBAL_DELAY_IND_DATA +#define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA_MASK 0x0000003FL +//RLC_SPM_SE_DELAY_IND_ADDR +#define RLC_SPM_SE_DELAY_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_SE_DELAY_IND_DATA +#define RLC_SPM_SE_DELAY_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_DELAY_IND_DATA__DATA_MASK 0x0000003FL +//RLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_SE_BLK_EN_MASK_IND_ADDR +#define RLC_SPM_SE_BLK_EN_MASK_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_BLK_EN_MASK_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_SE_BLK_EN_MASK_IND_DATA +#define RLC_SPM_SE_BLK_EN_MASK_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_BLK_EN_MASK_IND_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IH_22BEAT_STAT +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LOADING__SHIFT 0x8 +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_PROTOCOL_ERROR__SHIFT 0x9 +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_OVERFLOW__SHIFT 0xa +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_RESERVED__SHIFT 0xb +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LEVEL_MASK 0x000000FFL +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LOADING_MASK 0x00000100L +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_PROTOCOL_ERROR_MASK 0x00000200L +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_OVERFLOW_MASK 0x00000400L +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_RESERVED_MASK 0xFFFFF800L +//RLC_GFX_IH_ARBITER_STAT_22BEAT +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__CLIENT_GRANTED__SHIFT 0x0 +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__RESERVED__SHIFT 0x10 +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__LAST_CLIENT_GRANTED__SHIFT 0x1c +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__CLIENT_GRANTED_MASK 0x0000FFFFL +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__RESERVED_MASK 0x0FFF0000L +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__LAST_CLIENT_GRANTED_MASK 0xF0000000L +//RLC_LX6_CNTL +#define RLC_LX6_CNTL__BRESET__SHIFT 0x0 +#define RLC_LX6_CNTL__RUNSTALL__SHIFT 0x1 +#define RLC_LX6_CNTL__PDEBUG_ENABLE__SHIFT 0x2 +#define RLC_LX6_CNTL__STAT_VECTOR_SEL__SHIFT 0x3 +#define RLC_LX6_CNTL__BRESET_MASK 0x00000001L +#define RLC_LX6_CNTL__RUNSTALL_MASK 0x00000002L +#define RLC_LX6_CNTL__PDEBUG_ENABLE_MASK 0x00000004L +#define RLC_LX6_CNTL__STAT_VECTOR_SEL_MASK 0x00000008L +//RLC_LX6_STATUS +#define RLC_LX6_STATUS__CORE0_CORE_BUSY__SHIFT 0x0 +#define RLC_LX6_STATUS__CORE0_PIF_GASKET_BUSY__SHIFT 0x1 +#define RLC_LX6_STATUS__CORE0_INT_PENDING__SHIFT 0x2 +#define RLC_LX6_STATUS__CORE0_GRBMT_BUSY__SHIFT 0x3 +#define RLC_LX6_STATUS__CORE1_CORE_BUSY__SHIFT 0x4 +#define RLC_LX6_STATUS__CORE1_PIF_GASKET_BUSY__SHIFT 0x5 +#define RLC_LX6_STATUS__CORE1_INT_PENDING__SHIFT 0x6 +#define RLC_LX6_STATUS__CORE1_GRBMT_BUSY__SHIFT 0x7 +#define RLC_LX6_STATUS__GRBMT_BUSY__SHIFT 0x8 +#define RLC_LX6_STATUS__CORE0_CORE_BUSY_MASK 0x00000001L +#define RLC_LX6_STATUS__CORE0_PIF_GASKET_BUSY_MASK 0x00000002L +#define RLC_LX6_STATUS__CORE0_INT_PENDING_MASK 0x00000004L +#define RLC_LX6_STATUS__CORE0_GRBMT_BUSY_MASK 0x00000008L +#define RLC_LX6_STATUS__CORE1_CORE_BUSY_MASK 0x00000010L +#define RLC_LX6_STATUS__CORE1_PIF_GASKET_BUSY_MASK 0x00000020L +#define RLC_LX6_STATUS__CORE1_INT_PENDING_MASK 0x00000040L +#define RLC_LX6_STATUS__CORE1_GRBMT_BUSY_MASK 0x00000080L +#define RLC_LX6_STATUS__GRBMT_BUSY_MASK 0x00000100L +//RLC_LX6_FW_STATUS +#define RLC_LX6_FW_STATUS__STATUS__SHIFT 0x0 +#define RLC_LX6_FW_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_LX6_FW_VERSION +#define RLC_LX6_FW_VERSION__VERSION__SHIFT 0x0 +#define RLC_LX6_FW_VERSION__VERSION_MASK 0xFFFFFFFFL +//RLC_XT_CORE_STATUS +#define RLC_XT_CORE_STATUS__P_WAIT_MODE__SHIFT 0x0 +#define RLC_XT_CORE_STATUS__P_FATAL_ERROR__SHIFT 0x1 +#define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR__SHIFT 0x2 +#define RLC_XT_CORE_STATUS__P_WAIT_MODE_MASK 0x00000001L +#define RLC_XT_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000002L +#define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR_MASK 0x00000004L +//RLC_XT_CORE_INTERRUPT +#define RLC_XT_CORE_INTERRUPT__EXTINT1__SHIFT 0x0 +#define RLC_XT_CORE_INTERRUPT__EXTINT2__SHIFT 0x1a +#define RLC_XT_CORE_INTERRUPT__NMI__SHIFT 0x1b +#define RLC_XT_CORE_INTERRUPT__EXTINT1_MASK 0x03FFFFFFL +#define RLC_XT_CORE_INTERRUPT__EXTINT2_MASK 0x04000000L +#define RLC_XT_CORE_INTERRUPT__NMI_MASK 0x08000000L +//RLC_XT_CORE_FAULT_INFO +#define RLC_XT_CORE_FAULT_INFO__FAULT_INFO__SHIFT 0x0 +#define RLC_XT_CORE_FAULT_INFO__FAULT_INFO_MASK 0xFFFFFFFFL +//RLC_XT_CORE_ALT_RESET_VEC +#define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC__SHIFT 0x0 +#define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC_MASK 0xFFFFFFFFL +//RLC_XT_CORE_RESERVED +#define RLC_XT_CORE_RESERVED__RESERVED__SHIFT 0x0 +#define RLC_XT_CORE_RESERVED__RESERVED_MASK 0xFFFFFFFFL +//RLC_XT_INT_VEC_FORCE +#define RLC_XT_INT_VEC_FORCE__NUM_0__SHIFT 0x0 +#define RLC_XT_INT_VEC_FORCE__NUM_1__SHIFT 0x1 +#define RLC_XT_INT_VEC_FORCE__NUM_2__SHIFT 0x2 +#define RLC_XT_INT_VEC_FORCE__NUM_3__SHIFT 0x3 +#define RLC_XT_INT_VEC_FORCE__NUM_4__SHIFT 0x4 +#define RLC_XT_INT_VEC_FORCE__NUM_5__SHIFT 0x5 +#define RLC_XT_INT_VEC_FORCE__NUM_6__SHIFT 0x6 +#define RLC_XT_INT_VEC_FORCE__NUM_7__SHIFT 0x7 +#define RLC_XT_INT_VEC_FORCE__NUM_8__SHIFT 0x8 +#define RLC_XT_INT_VEC_FORCE__NUM_9__SHIFT 0x9 +#define RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT 0xa +#define RLC_XT_INT_VEC_FORCE__NUM_11__SHIFT 0xb +#define RLC_XT_INT_VEC_FORCE__NUM_12__SHIFT 0xc +#define RLC_XT_INT_VEC_FORCE__NUM_13__SHIFT 0xd +#define RLC_XT_INT_VEC_FORCE__NUM_14__SHIFT 0xe +#define RLC_XT_INT_VEC_FORCE__NUM_15__SHIFT 0xf +#define RLC_XT_INT_VEC_FORCE__NUM_16__SHIFT 0x10 +#define RLC_XT_INT_VEC_FORCE__NUM_17__SHIFT 0x11 +#define RLC_XT_INT_VEC_FORCE__NUM_18__SHIFT 0x12 +#define RLC_XT_INT_VEC_FORCE__NUM_19__SHIFT 0x13 +#define RLC_XT_INT_VEC_FORCE__NUM_20__SHIFT 0x14 +#define RLC_XT_INT_VEC_FORCE__NUM_21__SHIFT 0x15 +#define RLC_XT_INT_VEC_FORCE__NUM_22__SHIFT 0x16 +#define RLC_XT_INT_VEC_FORCE__NUM_23__SHIFT 0x17 +#define RLC_XT_INT_VEC_FORCE__NUM_24__SHIFT 0x18 +#define RLC_XT_INT_VEC_FORCE__NUM_25__SHIFT 0x19 +#define RLC_XT_INT_VEC_FORCE__NUM_0_MASK 0x00000001L +#define RLC_XT_INT_VEC_FORCE__NUM_1_MASK 0x00000002L +#define RLC_XT_INT_VEC_FORCE__NUM_2_MASK 0x00000004L +#define RLC_XT_INT_VEC_FORCE__NUM_3_MASK 0x00000008L +#define RLC_XT_INT_VEC_FORCE__NUM_4_MASK 0x00000010L +#define RLC_XT_INT_VEC_FORCE__NUM_5_MASK 0x00000020L +#define RLC_XT_INT_VEC_FORCE__NUM_6_MASK 0x00000040L +#define RLC_XT_INT_VEC_FORCE__NUM_7_MASK 0x00000080L +#define RLC_XT_INT_VEC_FORCE__NUM_8_MASK 0x00000100L +#define RLC_XT_INT_VEC_FORCE__NUM_9_MASK 0x00000200L +#define RLC_XT_INT_VEC_FORCE__NUM_10_MASK 0x00000400L +#define RLC_XT_INT_VEC_FORCE__NUM_11_MASK 0x00000800L +#define RLC_XT_INT_VEC_FORCE__NUM_12_MASK 0x00001000L +#define RLC_XT_INT_VEC_FORCE__NUM_13_MASK 0x00002000L +#define RLC_XT_INT_VEC_FORCE__NUM_14_MASK 0x00004000L +#define RLC_XT_INT_VEC_FORCE__NUM_15_MASK 0x00008000L +#define RLC_XT_INT_VEC_FORCE__NUM_16_MASK 0x00010000L +#define RLC_XT_INT_VEC_FORCE__NUM_17_MASK 0x00020000L +#define RLC_XT_INT_VEC_FORCE__NUM_18_MASK 0x00040000L +#define RLC_XT_INT_VEC_FORCE__NUM_19_MASK 0x00080000L +#define RLC_XT_INT_VEC_FORCE__NUM_20_MASK 0x00100000L +#define RLC_XT_INT_VEC_FORCE__NUM_21_MASK 0x00200000L +#define RLC_XT_INT_VEC_FORCE__NUM_22_MASK 0x00400000L +#define RLC_XT_INT_VEC_FORCE__NUM_23_MASK 0x00800000L +#define RLC_XT_INT_VEC_FORCE__NUM_24_MASK 0x01000000L +#define RLC_XT_INT_VEC_FORCE__NUM_25_MASK 0x02000000L +//RLC_XT_INT_VEC_CLEAR +#define RLC_XT_INT_VEC_CLEAR__NUM_0__SHIFT 0x0 +#define RLC_XT_INT_VEC_CLEAR__NUM_1__SHIFT 0x1 +#define RLC_XT_INT_VEC_CLEAR__NUM_2__SHIFT 0x2 +#define RLC_XT_INT_VEC_CLEAR__NUM_3__SHIFT 0x3 +#define RLC_XT_INT_VEC_CLEAR__NUM_4__SHIFT 0x4 +#define RLC_XT_INT_VEC_CLEAR__NUM_5__SHIFT 0x5 +#define RLC_XT_INT_VEC_CLEAR__NUM_6__SHIFT 0x6 +#define RLC_XT_INT_VEC_CLEAR__NUM_7__SHIFT 0x7 +#define RLC_XT_INT_VEC_CLEAR__NUM_8__SHIFT 0x8 +#define RLC_XT_INT_VEC_CLEAR__NUM_9__SHIFT 0x9 +#define RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT 0xa +#define RLC_XT_INT_VEC_CLEAR__NUM_11__SHIFT 0xb +#define RLC_XT_INT_VEC_CLEAR__NUM_12__SHIFT 0xc +#define RLC_XT_INT_VEC_CLEAR__NUM_13__SHIFT 0xd +#define RLC_XT_INT_VEC_CLEAR__NUM_14__SHIFT 0xe +#define RLC_XT_INT_VEC_CLEAR__NUM_15__SHIFT 0xf +#define RLC_XT_INT_VEC_CLEAR__NUM_16__SHIFT 0x10 +#define RLC_XT_INT_VEC_CLEAR__NUM_17__SHIFT 0x11 +#define RLC_XT_INT_VEC_CLEAR__NUM_18__SHIFT 0x12 +#define RLC_XT_INT_VEC_CLEAR__NUM_19__SHIFT 0x13 +#define RLC_XT_INT_VEC_CLEAR__NUM_20__SHIFT 0x14 +#define RLC_XT_INT_VEC_CLEAR__NUM_21__SHIFT 0x15 +#define RLC_XT_INT_VEC_CLEAR__NUM_22__SHIFT 0x16 +#define RLC_XT_INT_VEC_CLEAR__NUM_23__SHIFT 0x17 +#define RLC_XT_INT_VEC_CLEAR__NUM_24__SHIFT 0x18 +#define RLC_XT_INT_VEC_CLEAR__NUM_25__SHIFT 0x19 +#define RLC_XT_INT_VEC_CLEAR__NUM_0_MASK 0x00000001L +#define RLC_XT_INT_VEC_CLEAR__NUM_1_MASK 0x00000002L +#define RLC_XT_INT_VEC_CLEAR__NUM_2_MASK 0x00000004L +#define RLC_XT_INT_VEC_CLEAR__NUM_3_MASK 0x00000008L +#define RLC_XT_INT_VEC_CLEAR__NUM_4_MASK 0x00000010L +#define RLC_XT_INT_VEC_CLEAR__NUM_5_MASK 0x00000020L +#define RLC_XT_INT_VEC_CLEAR__NUM_6_MASK 0x00000040L +#define RLC_XT_INT_VEC_CLEAR__NUM_7_MASK 0x00000080L +#define RLC_XT_INT_VEC_CLEAR__NUM_8_MASK 0x00000100L +#define RLC_XT_INT_VEC_CLEAR__NUM_9_MASK 0x00000200L +#define RLC_XT_INT_VEC_CLEAR__NUM_10_MASK 0x00000400L +#define RLC_XT_INT_VEC_CLEAR__NUM_11_MASK 0x00000800L +#define RLC_XT_INT_VEC_CLEAR__NUM_12_MASK 0x00001000L +#define RLC_XT_INT_VEC_CLEAR__NUM_13_MASK 0x00002000L +#define RLC_XT_INT_VEC_CLEAR__NUM_14_MASK 0x00004000L +#define RLC_XT_INT_VEC_CLEAR__NUM_15_MASK 0x00008000L +#define RLC_XT_INT_VEC_CLEAR__NUM_16_MASK 0x00010000L +#define RLC_XT_INT_VEC_CLEAR__NUM_17_MASK 0x00020000L +#define RLC_XT_INT_VEC_CLEAR__NUM_18_MASK 0x00040000L +#define RLC_XT_INT_VEC_CLEAR__NUM_19_MASK 0x00080000L +#define RLC_XT_INT_VEC_CLEAR__NUM_20_MASK 0x00100000L +#define RLC_XT_INT_VEC_CLEAR__NUM_21_MASK 0x00200000L +#define RLC_XT_INT_VEC_CLEAR__NUM_22_MASK 0x00400000L +#define RLC_XT_INT_VEC_CLEAR__NUM_23_MASK 0x00800000L +#define RLC_XT_INT_VEC_CLEAR__NUM_24_MASK 0x01000000L +#define RLC_XT_INT_VEC_CLEAR__NUM_25_MASK 0x02000000L +//RLC_XT_INT_VEC_MUX_SEL +#define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL__SHIFT 0x0 +#define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL_MASK 0x0000001FL +//RLC_XT_INT_VEC_MUX_INT_SEL +#define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL__SHIFT 0x0 +#define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL_MASK 0x0000003FL +//RLC_GPU_CLOCK_COUNT_SPM_LSB +#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_SPM_MSB +#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_SPM_THREAD_TRACE_CTRL +#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0 +#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L +//RLC_SPP_CAM_ADDR +#define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL +//RLC_SPP_CAM_DATA +#define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8 +#define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL +#define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L +//RLC_SPP_CAM_EXT_ADDR +#define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL +//RLC_SPP_CAM_EXT_DATA +#define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0 +#define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1 +#define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L +#define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L +//RLC_CPAXI_DOORBELL_MON_CTRL +#define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT 0x1 +#define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK 0x00000001L +#define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK 0x0000003EL +//RLC_CPAXI_DOORBELL_MON_STAT +#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT 0x1 +#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT 0x2 +#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK 0x00000001L +#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK 0x00000002L +#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK 0x0FFFFFFCL +//RLC_CPAXI_DOORBELL_MON_DATA_LSB +#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_CPAXI_DOORBELL_MON_DATA_MSB +#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_RANGE +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_XT_DOORBELL_RANGE__RESERVED_15_12__SHIFT 0xc +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_XT_DOORBELL_RANGE__RESERVED_31_28__SHIFT 0x1c +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_XT_DOORBELL_RANGE__RESERVED_15_12_MASK 0x0000F000L +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +#define RLC_XT_DOORBELL_RANGE__RESERVED_31_28_MASK 0xF0000000L +//RLC_XT_DOORBELL_CNTL +#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_XT_DOORBELL_CNTL__RESERVED_15_8__SHIFT 0x8 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_XT_DOORBELL_CNTL__RESERVED_31_22__SHIFT 0x16 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_XT_DOORBELL_CNTL__RESERVED_15_8_MASK 0x0000FF00L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_XT_DOORBELL_CNTL__RESERVED_31_22_MASK 0xFFC00000L +//RLC_XT_DOORBELL_STAT +#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_XT_DOORBELL_0_DATA_LO +#define RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_0_DATA_HI +#define RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_1_DATA_LO +#define RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_1_DATA_HI +#define RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_2_DATA_LO +#define RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_2_DATA_HI +#define RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_3_DATA_LO +#define RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_3_DATA_HI +#define RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_MEM_SLP_CNTL +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE__SHIFT 0x3 +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE__SHIFT 0x4 +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE__SHIFT 0x5 +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x6 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE__SHIFT 0x18 +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE__SHIFT 0x19 +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_LS_OVERRIDE__SHIFT 0x1a +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_DS_OVERRIDE__SHIFT 0x1b +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_LS_OVERRIDE__SHIFT 0x1c +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_DS_OVERRIDE__SHIFT 0x1d +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x1e +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE_MASK 0x00000004L +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE_MASK 0x00000008L +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE_MASK 0x00000010L +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE_MASK 0x00000020L +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x00000040L +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE_MASK 0x01000000L +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE_MASK 0x02000000L +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_LS_OVERRIDE_MASK 0x04000000L +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_DS_OVERRIDE_MASK 0x08000000L +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_LS_OVERRIDE_MASK 0x10000000L +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_DS_OVERRIDE_MASK 0x20000000L +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xC0000000L +//RLC_RLCV_SAFE_MODE +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SMU_SAFE_MODE +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_RLCV_COMMAND +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L +//RLC_SMU_MESSAGE +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_MESSAGE_1 +#define RLC_SMU_MESSAGE_1__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE_1__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_MESSAGE_2 +#define RLC_SMU_MESSAGE_2__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE_2__CMD_MASK 0xFFFFFFFFL +//RLC_SRM_GPM_COMMAND +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x12 +#define RLC_SRM_GPM_COMMAND__RESERVED__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0003FFE0L +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x7FFC0000L +#define RLC_SRM_GPM_COMMAND__RESERVED_MASK 0x80000000L +//RLC_SRM_GPM_ABORT +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_COMMAND +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_1 +#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_2 +#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_3 +#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_4 +#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_5 +#define RLC_SMU_ARGUMENT_5__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_5__ARG_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_ADDR_HI +#define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_ADDR_LO +#define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_SIZE +#define RLC_IMU_BOOTLOAD_SIZE__SIZE__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_SIZE__RESERVED__SHIFT 0x1a +#define RLC_IMU_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL +#define RLC_IMU_BOOTLOAD_SIZE__RESERVED_MASK 0xFC000000L +//RLC_IMU_MISC +#define RLC_IMU_MISC__THROTTLE_GFX__SHIFT 0x0 +#define RLC_IMU_MISC__EARLY_MGCG__SHIFT 0x1 +#define RLC_IMU_MISC__RESERVED__SHIFT 0x2 +#define RLC_IMU_MISC__THROTTLE_GFX_MASK 0x00000001L +#define RLC_IMU_MISC__EARLY_MGCG_MASK 0x00000002L +#define RLC_IMU_MISC__RESERVED_MASK 0xFFFFFFFCL +//RLC_IMU_RESET_VECTOR +#define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0 +#define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1 +#define RLC_IMU_RESET_VECTOR__VECTOR__SHIFT 0x2 +#define RLC_IMU_RESET_VECTOR__RESERVED__SHIFT 0x8 +#define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L +#define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L +#define RLC_IMU_RESET_VECTOR__VECTOR_MASK 0x000000FCL +#define RLC_IMU_RESET_VECTOR__RESERVED_MASK 0xFFFFFF00L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec +//RLC_RLCS_DEC_START +//RLC_RLCS_DEC_DUMP_ADDR +//RLC_RLCS_EXCEPTION_REG_1 +#define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_2 +#define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_3 +#define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_4 +#define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_FENCE_CNTL +#define RLC_RLCS_FENCE_CNTL__MODE__SHIFT 0x0 +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC_EN__SHIFT 0x2 +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC__SHIFT 0x4 +#define RLC_RLCS_FENCE_CNTL__MODE_MASK 0x00000003L +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC_EN_MASK 0x00000004L +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC_MASK 0x000000F0L +//RLC_RLCS_CGCG_REQUEST +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0 +#define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x1 +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L +#define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_CGCG_STATUS +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0 +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2 +#define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x3 +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L +#define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFF8L +//RLC_RLCS_SOC_DS_CNTL +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_4_3__SHIFT 0x3 +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_5__SHIFT 0x5 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_31_24__SHIFT 0x18 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_4_3_MASK 0x00000018L +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_5_MASK 0x00000020L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_31_24_MASK 0xFF000000L +//RLC_RLCS_GFX_DS_CNTL +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_4_3__SHIFT 0x3 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_5__SHIFT 0x5 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK__SHIFT 0x8 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_15_9__SHIFT 0x9 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED__SHIFT 0x18 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_4_3_MASK 0x00000018L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_5_MASK 0x00000020L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK_MASK 0x00000100L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_15_9_MASK 0x0000FE00L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_MASK 0xFF000000L +//RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL +//RLC_GPM_STAT +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 +#define RLC_GPM_STAT__RESERVED_1__SHIFT 0x13 +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L +#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L +#define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L +#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L +#define RLC_GPM_STAT__RESERVED_1_MASK 0x00180000L +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_RLCS_GPM_STAT +#define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 +#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12 +#define RLC_RLCS_GPM_STAT__RESERVED_1__SHIFT 0x13 +#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L +#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L +#define RLC_RLCS_GPM_STAT__RESERVED_1_MASK 0x00180000L +#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_RLCS_ABORTED_PD_SEQUENCE +#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0 +#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10 +#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL +#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IOV_CMD_STATUS +#define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IOV_CNTX_LOC_SIZE +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8 +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L +//RLC_RLCS_IOV_SCH_BLOCK +#define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IOV_VM_BUSY_STATUS +#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GPM_STAT_2 +#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0 +#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1 +#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2 +#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3 +#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT 0x4 +#define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x5 +#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L +#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L +#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L +#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L +#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK 0x00000010L +#define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_GRBM_SOFT_RESET +#define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0 +#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1 +#define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L +#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_PG_CHANGE_STATUS +#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0 +#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1 +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3 +#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L +#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L +#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_PG_CHANGE_READ +#define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x0 +#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1 +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3 +#define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0x00000001L +#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L +//RLC_RLCS_IH_SEMAPHORE +#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0 +#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL +//RLC_RLCS_IH_COOKIE_SEMAPHORE +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0 +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL +//RLC_RLCS_CP_INT_CTRL_1 +#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1 +#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_CP_INT_CTRL_2 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0 +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE__SHIFT 0x2 +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE__SHIFT 0x3 +#define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING__SHIFT 0x4 +#define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x5 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE_MASK 0x00000004L +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE_MASK 0x00000008L +#define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING_MASK 0x00000010L +#define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_CP_INT_INFO_1 +#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_RLCS_CP_INT_INFO_2 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L +#define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L +//RLC_RLCS_SPM_INT_CTRL +#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1 +#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_SPM_INT_INFO_1 +#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_RLCS_SPM_INT_INFO_2 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L +#define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L +//RLC_RLCS_DSM_TRIG +#define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0 +#define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1 +#define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L +#define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_BOOTLOAD_STATUS +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_FUSE_DIST_DONE__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_STATUS__STATUS_6_30__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_FUSE_DIST_DONE_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_STATUS__STATUS_6_30_MASK 0x7FFFFFC0L +#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L +//RLC_RLCS_GRBM_IDLE_BUSY_STAT +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT 0x0 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x10 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x11 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT 0x12 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT 0x13 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT 0x14 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT 0x15 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT 0x16 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT 0x17 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x18 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x19 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT 0x1a +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT 0x1b +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT 0x1c +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT 0x1d +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT 0x1e +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT 0x1f +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK 0x00000003L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00010000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00020000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK 0x00040000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK 0x00080000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK 0x00100000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK 0x00200000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK 0x00400000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK 0x00800000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x01000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x02000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK 0x04000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK 0x08000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK 0x10000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK 0x20000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK 0x40000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK 0x80000000L +//RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT 0x2 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT 0x3 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT 0x4 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT 0x5 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT 0x6 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT 0x7 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK 0x00000004L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK 0x00000008L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK 0x00000010L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK 0x00000020L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK 0x00000040L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK 0x00000080L +//RLC_RLCS_CMP_IDLE_CNTL +#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1 +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2 +#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3 +#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb +#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13 +#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L +#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L +#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L +#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_RLCS_GENERAL_0 +#define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_1 +#define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_2 +#define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_3 +#define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_4 +#define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_5 +#define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_6 +#define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_7 +#define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_8 +#define RLC_RLCS_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_9 +#define RLC_RLCS_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_10 +#define RLC_RLCS_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_11 +#define RLC_RLCS_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_12 +#define RLC_RLCS_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_13 +#define RLC_RLCS_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_14 +#define RLC_RLCS_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_15 +#define RLC_RLCS_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_16 +#define RLC_RLCS_GENERAL_16__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_16__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_AUXILIARY_REG_1 +#define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_2 +#define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_3 +#define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_4 +#define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_SPM_SQTT_MODE +#define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0 +#define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L +//RLC_RLCS_CP_DMA_SRCID_OVER +#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0 +#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L +//RLC_RLCS_BOOTLOAD_ID_STATUS1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L +//RLC_RLCS_BOOTLOAD_ID_STATUS2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L +//RLC_RLCS_KMD_LOG_CNTL1 +#define RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT 0x0 +#define RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_KMD_LOG_CNTL2 +#define RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT 0x0 +#define RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GPM_LEGACY_INT_STAT +#define RLC_RLCS_GPM_LEGACY_INT_STAT__RESERVED__SHIFT 0x0 +#define RLC_RLCS_GPM_LEGACY_INT_STAT__RESERVED_MASK 0x00000001L +//RLC_RLCS_GPM_LEGACY_INT_DISABLE +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__RESERVED__SHIFT 0x0 +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__RESERVED_MASK 0x00000001L +//RLC_RLCS_GCR_DATA_0 +#define RLC_RLCS_GCR_DATA_0__PHASE_0__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_0__PHASE_1__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_0__PHASE_0_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_0__PHASE_1_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_1 +#define RLC_RLCS_GCR_DATA_1__PHASE_2__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_1__PHASE_3__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_1__PHASE_2_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_1__PHASE_3_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_2 +#define RLC_RLCS_GCR_DATA_2__PHASE_4__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_2__PHASE_5__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_2__PHASE_4_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_2__PHASE_5_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_3 +#define RLC_RLCS_GCR_DATA_3__PHASE_6__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_3__PHASE_7__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_3__PHASE_6_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_3__PHASE_7_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_4 +#define RLC_RLCS_GCR_DATA_4__PHASE_8__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_4__PHASE_9__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_4__PHASE_8_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_4__PHASE_9_MASK 0xFFFF0000L +//RLC_RLCS_GCR_STATUS +#define RLC_RLCS_GCR_STATUS__GCR_BUSY__SHIFT 0x0 +#define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT__SHIFT 0x1 +#define RLC_RLCS_GCR_STATUS__RESERVED_2__SHIFT 0x5 +#define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG__SHIFT 0x8 +#define RLC_RLCS_GCR_STATUS__RESERVED__SHIFT 0x10 +#define RLC_RLCS_GCR_STATUS__GCR_BUSY_MASK 0x00000001L +#define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT_MASK 0x0000001EL +#define RLC_RLCS_GCR_STATUS__RESERVED_2_MASK 0x000000E0L +#define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG_MASK 0x0000FF00L +#define RLC_RLCS_GCR_STATUS__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_PERFMON_CLK_CNTL_UCODE +#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L +//RLC_RLCS_UTCL2_CNTL +#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1 +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2 +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3 +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5 +#define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x6 +#define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x7 +#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L +#define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK 0x00000040L +#define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFF80L +//RLC_RLCS_IMU_RLC_MSG_DATA0 +#define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA1 +#define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA2 +#define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA3 +#define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA4 +#define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_CONTROL +#define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_CNTL +#define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_RLC_IMU_MSG_DATA0 +#define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_RLC_IMU_MSG_CONTROL +#define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_RLC_IMU_MSG_CNTL +#define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG__SHIFT 0x1 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG_MASK 0x00000001L +#define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG_MASK 0x00000002L +#define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_RLC_MUTEX_CNTL +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_RLC_STATUS +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_STATUS__STATUS_14_2__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_STATUS__STATUS_14_2_MASK 0x00007FFCL +#define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_RLC_IMU_STATUS +#define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE__SHIFT 0x1 +#define RLC_RLCS_RLC_IMU_STATUS__STATUS_3_2__SHIFT 0x2 +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE_MASK 0x00000001L +#define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE_MASK 0x00000002L +#define RLC_RLCS_RLC_IMU_STATUS__STATUS_3_2_MASK 0x0000000CL +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_IMU_RAM_DATA_1 +#define RLC_RLCS_IMU_RAM_DATA_1__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_1_LSB +#define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_1_MSB +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RAM_DATA_0 +#define RLC_RLCS_IMU_RAM_DATA_0__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_0_LSB +#define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_0_MSB +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RAM_CNTL +#define RLC_RLCS_IMU_RAM_CNTL__REQTOG__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_CNTL__ACKTOG__SHIFT 0x1 +#define RLC_RLCS_IMU_RAM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RAM_CNTL__REQTOG_MASK 0x00000001L +#define RLC_RLCS_IMU_RAM_CNTL__ACKTOG_MASK 0x00000002L +#define RLC_RLCS_IMU_RAM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_GFX_DOORBELL_FENCE +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE__SHIFT 0x0 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK__SHIFT 0x1 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE_MASK 0x00000001L +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK_MASK 0x00000002L +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_CNTL_1 +#define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID__SHIFT 0x1 +#define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED__SHIFT 0x2 +#define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID_MASK 0x00000002L +#define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_CNTL_2 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE__SHIFT 0x1 +#define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED__SHIFT 0x2 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN_MASK 0x00000001L +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE_MASK 0x00000002L +#define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_STAT +#define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST__SHIFT 0x8 +#define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID__SHIFT 0x10 +#define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING__SHIFT 0x11 +#define RLC_RLCS_SDMA_INT_STAT__RESERVED__SHIFT 0x12 +#define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST_MASK 0x000000FFL +#define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST_MASK 0x0000FF00L +#define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID_MASK 0x00010000L +#define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING_MASK 0x00020000L +#define RLC_RLCS_SDMA_INT_STAT__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_SDMA_INT_INFO +#define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW__SHIFT 0x8 +#define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_SDMA_INT_INFO__RESERVED__SHIFT 0x11 +#define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW_MASK 0x000000FFL +#define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW_MASK 0x0000FF00L +#define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID_MASK 0x00010000L +#define RLC_RLCS_SDMA_INT_INFO__RESERVED_MASK 0xFFFE0000L +//RLC_RLCS_GFX_MEM_POWER_CTRL_0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_0__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GFX_MEM_POWER_CTRL_1 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_1__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GFX_MEM_POWER_CTRL_2 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_2__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IH_CTRL_1 +#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT 0x0 +#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK 0xFFFFFFFFL +//RLC_RLCS_IH_CTRL_2 +#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT 0x0 +#define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT 0x8 +#define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT 0x10 +#define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT 0x14 +#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK 0x000000FFL +#define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK 0x0000FF00L +#define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK 0x000F0000L +#define RLC_RLCS_IH_CTRL_2__RESERVED_MASK 0xFFF00000L +//RLC_RLCS_IH_CTRL_3 +#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT 0x0 +#define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT 0x8 +#define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT 0xd +#define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT 0xe +#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK 0x000000FFL +#define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK 0x00001F00L +#define RLC_RLCS_IH_CTRL_3__IH_VF_MASK 0x00002000L +#define RLC_RLCS_IH_CTRL_3__RESERVED_MASK 0xFFFFC000L +//RLC_RLCS_IH_STATUS +#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT 0x0 +#define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT 0x6 +#define RLC_RLCS_IH_STATUS__IH_WRITE_DONE__SHIFT 0x7 +#define RLC_RLCS_IH_STATUS__RESERVED__SHIFT 0x8 +#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK 0x0000003FL +#define RLC_RLCS_IH_STATUS__IH_BUSY_MASK 0x00000040L +#define RLC_RLCS_IH_STATUS__IH_WRITE_DONE_MASK 0x00000080L +#define RLC_RLCS_IH_STATUS__RESERVED_MASK 0xFFFFFF00L +//RLC_RLCS_FED_STATUS +#define RLC_RLCS_FED_STATUS__RLC_FED_ERR__SHIFT 0x0 +#define RLC_RLCS_FED_STATUS__UTCL2_FED_ERR__SHIFT 0x1 +#define RLC_RLCS_FED_STATUS__GE_FED_ERR__SHIFT 0x2 +#define RLC_RLCS_FED_STATUS__CPC_FED_ERR__SHIFT 0x3 +#define RLC_RLCS_FED_STATUS__CPF_FED_ERR__SHIFT 0x4 +#define RLC_RLCS_FED_STATUS__CPG_FED_ERR__SHIFT 0x5 +#define RLC_RLCS_FED_STATUS__SDMA0_FED_ERR__SHIFT 0x6 +#define RLC_RLCS_FED_STATUS__SDMA1_FED_ERR__SHIFT 0x7 +#define RLC_RLCS_FED_STATUS__RESERVED_9_8__SHIFT 0x8 +#define RLC_RLCS_FED_STATUS__SE0_FED_ERR__SHIFT 0xa +#define RLC_RLCS_FED_STATUS__SE1_FED_ERR__SHIFT 0xb +#define RLC_RLCS_FED_STATUS__CANE_FED_ERR__SHIFT 0xc +#define RLC_RLCS_FED_STATUS__RESERVED_17_13__SHIFT 0xd +#define RLC_RLCS_FED_STATUS__AID0_FED_ERR__SHIFT 0x12 +#define RLC_RLCS_FED_STATUS__AID1_FED_ERR__SHIFT 0x13 +#define RLC_RLCS_FED_STATUS__RLC_FED_ERR_MASK 0x00000001L +#define RLC_RLCS_FED_STATUS__UTCL2_FED_ERR_MASK 0x00000002L +#define RLC_RLCS_FED_STATUS__GE_FED_ERR_MASK 0x00000004L +#define RLC_RLCS_FED_STATUS__CPC_FED_ERR_MASK 0x00000008L +#define RLC_RLCS_FED_STATUS__CPF_FED_ERR_MASK 0x00000010L +#define RLC_RLCS_FED_STATUS__CPG_FED_ERR_MASK 0x00000020L +#define RLC_RLCS_FED_STATUS__SDMA0_FED_ERR_MASK 0x00000040L +#define RLC_RLCS_FED_STATUS__SDMA1_FED_ERR_MASK 0x00000080L +#define RLC_RLCS_FED_STATUS__RESERVED_9_8_MASK 0x00000300L +#define RLC_RLCS_FED_STATUS__SE0_FED_ERR_MASK 0x00000400L +#define RLC_RLCS_FED_STATUS__SE1_FED_ERR_MASK 0x00000800L +#define RLC_RLCS_FED_STATUS__CANE_FED_ERR_MASK 0x00001000L +#define RLC_RLCS_FED_STATUS__RESERVED_17_13_MASK 0x0003E000L +#define RLC_RLCS_FED_STATUS__AID0_FED_ERR_MASK 0x00040000L +#define RLC_RLCS_FED_STATUS__AID1_FED_ERR_MASK 0x00080000L +//RLC_RLCS_FED_RESP +#define RLC_RLCS_FED_RESP__RLC_FED_ACK__SHIFT 0x0 +#define RLC_RLCS_FED_RESP__UTCL2_FED_ACK__SHIFT 0x1 +#define RLC_RLCS_FED_RESP__GE_FED_ACK__SHIFT 0x2 +#define RLC_RLCS_FED_RESP__CPC_FED_ACK__SHIFT 0x3 +#define RLC_RLCS_FED_RESP__CPF_FED_ACK__SHIFT 0x4 +#define RLC_RLCS_FED_RESP__CPG_FED_ACK__SHIFT 0x5 +#define RLC_RLCS_FED_RESP__SDMA0_FED_ACK__SHIFT 0x6 +#define RLC_RLCS_FED_RESP__SDMA1_FED_ACK__SHIFT 0x7 +#define RLC_RLCS_FED_RESP__CANE_FED_ACK__SHIFT 0xc +#define RLC_RLCS_FED_RESP__SE0_FED_ACK__SHIFT 0xd +#define RLC_RLCS_FED_RESP__SE1_FED_ACK__SHIFT 0xe +#define RLC_RLCS_FED_RESP__RLC_FED_ACK_MASK 0x00000001L +#define RLC_RLCS_FED_RESP__UTCL2_FED_ACK_MASK 0x00000002L +#define RLC_RLCS_FED_RESP__GE_FED_ACK_MASK 0x00000004L +#define RLC_RLCS_FED_RESP__CPC_FED_ACK_MASK 0x00000008L +#define RLC_RLCS_FED_RESP__CPF_FED_ACK_MASK 0x00000010L +#define RLC_RLCS_FED_RESP__CPG_FED_ACK_MASK 0x00000020L +#define RLC_RLCS_FED_RESP__SDMA0_FED_ACK_MASK 0x00000040L +#define RLC_RLCS_FED_RESP__SDMA1_FED_ACK_MASK 0x00000080L +#define RLC_RLCS_FED_RESP__CANE_FED_ACK_MASK 0x00001000L +#define RLC_RLCS_FED_RESP__SE0_FED_ACK_MASK 0x00002000L +#define RLC_RLCS_FED_RESP__SE1_FED_ACK_MASK 0x00004000L +//RLC_RLCS_FED_INT_MASK +#define RLC_RLCS_FED_INT_MASK__RLC__SHIFT 0x0 +#define RLC_RLCS_FED_INT_MASK__UTCL2__SHIFT 0x1 +#define RLC_RLCS_FED_INT_MASK__GE__SHIFT 0x2 +#define RLC_RLCS_FED_INT_MASK__CPC__SHIFT 0x3 +#define RLC_RLCS_FED_INT_MASK__CPF__SHIFT 0x4 +#define RLC_RLCS_FED_INT_MASK__CPG__SHIFT 0x5 +#define RLC_RLCS_FED_INT_MASK__SDMA0__SHIFT 0x6 +#define RLC_RLCS_FED_INT_MASK__SDMA1__SHIFT 0x7 +#define RLC_RLCS_FED_INT_MASK__RESERVED_9_8__SHIFT 0x8 +#define RLC_RLCS_FED_INT_MASK__SE0__SHIFT 0xa +#define RLC_RLCS_FED_INT_MASK__SE1__SHIFT 0xb +#define RLC_RLCS_FED_INT_MASK__CANE__SHIFT 0xc +#define RLC_RLCS_FED_INT_MASK__RESERVED_17_13__SHIFT 0xd +#define RLC_RLCS_FED_INT_MASK__AID0__SHIFT 0x12 +#define RLC_RLCS_FED_INT_MASK__AID1__SHIFT 0x13 +#define RLC_RLCS_FED_INT_MASK__RLC_MASK 0x00000001L +#define RLC_RLCS_FED_INT_MASK__UTCL2_MASK 0x00000002L +#define RLC_RLCS_FED_INT_MASK__GE_MASK 0x00000004L +#define RLC_RLCS_FED_INT_MASK__CPC_MASK 0x00000008L +#define RLC_RLCS_FED_INT_MASK__CPF_MASK 0x00000010L +#define RLC_RLCS_FED_INT_MASK__CPG_MASK 0x00000020L +#define RLC_RLCS_FED_INT_MASK__SDMA0_MASK 0x00000040L +#define RLC_RLCS_FED_INT_MASK__SDMA1_MASK 0x00000080L +#define RLC_RLCS_FED_INT_MASK__RESERVED_9_8_MASK 0x00000300L +#define RLC_RLCS_FED_INT_MASK__SE0_MASK 0x00000400L +#define RLC_RLCS_FED_INT_MASK__SE1_MASK 0x00000800L +#define RLC_RLCS_FED_INT_MASK__CANE_MASK 0x00001000L +#define RLC_RLCS_FED_INT_MASK__RESERVED_17_13_MASK 0x0003E000L +#define RLC_RLCS_FED_INT_MASK__AID0_MASK 0x00040000L +#define RLC_RLCS_FED_INT_MASK__AID1_MASK 0x00080000L +//RLC_RLCS_MEM_FED +#define RLC_RLCS_MEM_FED__RESERVED_3_0__SHIFT 0x0 +#define RLC_RLCS_MEM_FED__LX6_RD_ERR__SHIFT 0x4 +#define RLC_RLCS_MEM_FED__TH2_RD_ERR__SHIFT 0x5 +#define RLC_RLCS_MEM_FED__TH1_RD_ERR__SHIFT 0x6 +#define RLC_RLCS_MEM_FED__TH0_RD_ERR__SHIFT 0x7 +#define RLC_RLCS_MEM_FED__DMA_RD_ERR__SHIFT 0x8 +#define RLC_RLCS_MEM_FED__SRM_RD_ERR__SHIFT 0x9 +#define RLC_RLCS_MEM_FED__RESERVED_11_10__SHIFT 0xa +#define RLC_RLCS_MEM_FED__LX6_TR_ERR__SHIFT 0xc +#define RLC_RLCS_MEM_FED__TH2_TR_ERR__SHIFT 0xd +#define RLC_RLCS_MEM_FED__TH1_TR_ERR__SHIFT 0xe +#define RLC_RLCS_MEM_FED__TH0_TR_ERR__SHIFT 0xf +#define RLC_RLCS_MEM_FED__SPM_TR_ERR__SHIFT 0x10 +#define RLC_RLCS_MEM_FED__DMA_TR_ERR__SHIFT 0x11 +#define RLC_RLCS_MEM_FED__DLG_TR_ERR__SHIFT 0x12 +#define RLC_RLCS_MEM_FED__SRM_TR_ERR__SHIFT 0x13 +#define RLC_RLCS_MEM_FED__RESERVED_3_0_MASK 0x0000000FL +#define RLC_RLCS_MEM_FED__LX6_RD_ERR_MASK 0x00000010L +#define RLC_RLCS_MEM_FED__TH2_RD_ERR_MASK 0x00000020L +#define RLC_RLCS_MEM_FED__TH1_RD_ERR_MASK 0x00000040L +#define RLC_RLCS_MEM_FED__TH0_RD_ERR_MASK 0x00000080L +#define RLC_RLCS_MEM_FED__DMA_RD_ERR_MASK 0x00000100L +#define RLC_RLCS_MEM_FED__SRM_RD_ERR_MASK 0x00000200L +#define RLC_RLCS_MEM_FED__RESERVED_11_10_MASK 0x00000C00L +#define RLC_RLCS_MEM_FED__LX6_TR_ERR_MASK 0x00001000L +#define RLC_RLCS_MEM_FED__TH2_TR_ERR_MASK 0x00002000L +#define RLC_RLCS_MEM_FED__TH1_TR_ERR_MASK 0x00004000L +#define RLC_RLCS_MEM_FED__TH0_TR_ERR_MASK 0x00008000L +#define RLC_RLCS_MEM_FED__SPM_TR_ERR_MASK 0x00010000L +#define RLC_RLCS_MEM_FED__DMA_TR_ERR_MASK 0x00020000L +#define RLC_RLCS_MEM_FED__DLG_TR_ERR_MASK 0x00040000L +#define RLC_RLCS_MEM_FED__SRM_TR_ERR_MASK 0x00080000L +//RLC_RLCS_SE_PWR_CTRL +#define RLC_RLCS_SE_PWR_CTRL__SE_GFXCLK_CLKEN__SHIFT 0x0 +#define RLC_RLCS_SE_PWR_CTRL__SE_GFX_HARD_RESETB__SHIFT 0x8 +#define RLC_RLCS_SE_PWR_CTRL__SE_EA_HARD_RESETB__SHIFT 0x10 +#define RLC_RLCS_SE_PWR_CTRL__SE_GFXCLK_CLKEN_MASK 0x00000003L +#define RLC_RLCS_SE_PWR_CTRL__SE_GFX_HARD_RESETB_MASK 0x00000300L +#define RLC_RLCS_SE_PWR_CTRL__SE_EA_HARD_RESETB_MASK 0x00030000L +//RLC_UTCL2_FED_STATUS_SNAP +#define RLC_UTCL2_FED_STATUS_SNAP__UTCL2_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_UTCL2_FED_STATUS_SNAP__UTCL2_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_SE0_FED_STATUS_SNAP +#define RLC_SE0_FED_STATUS_SNAP__SE0_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_SE0_FED_STATUS_SNAP__SE0_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_SE1_FED_STATUS_SNAP +#define RLC_SE1_FED_STATUS_SNAP__SE1_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_SE1_FED_STATUS_SNAP__SE1_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_CANE_FED_STATUS_SNAP +#define RLC_CANE_FED_STATUS_SNAP__CANE_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_CANE_FED_STATUS_SNAP__CANE_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_CONSOLIDATED_FED_STS +#define RLC_CONSOLIDATED_FED_STS__RLC_CONSOLIDATED_FED_STS__SHIFT 0x0 +#define RLC_CONSOLIDATED_FED_STS__NEED_TO_APPLY_FLR__SHIFT 0x10 +#define RLC_CONSOLIDATED_FED_STS__RESERVED__SHIFT 0x11 +#define RLC_CONSOLIDATED_FED_STS__RLC_CONSOLIDATED_FED_STS_MASK 0x0000FFFFL +#define RLC_CONSOLIDATED_FED_STS__NEED_TO_APPLY_FLR_MASK 0x00010000L +#define RLC_CONSOLIDATED_FED_STS__RESERVED_MASK 0xFFFE0000L +//RLC_HOST_FED_ACK +#define RLC_HOST_FED_ACK__RLC_HOST_FED_ACK__SHIFT 0x0 +#define RLC_HOST_FED_ACK__RESERVED__SHIFT 0x10 +#define RLC_HOST_FED_ACK__RLC_HOST_FED_ACK_MASK 0x0000FFFFL +#define RLC_HOST_FED_ACK__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_SB_RLC_ROM_STATUS +#define RLC_RLCS_SB_RLC_ROM_STATUS__STATUS__SHIFT 0x0 +#define RLC_RLCS_SB_RLC_ROM_STATUS__STATUS_MASK 0x00000003L +//RLC_RLCS_SB_ROM_STATUS +#define RLC_RLCS_SB_ROM_STATUS__RESERVED__SHIFT 0x1f +#define RLC_RLCS_SB_ROM_STATUS__RESERVED_MASK 0x80000000L +//RLC_RLCS_UTCL2_BUSY_CNTL +#define RLC_RLCS_UTCL2_BUSY_CNTL__AUTO_HDSHK__SHIFT 0x0 +#define RLC_RLCS_UTCL2_BUSY_CNTL__ACK__SHIFT 0x1 +#define RLC_RLCS_UTCL2_BUSY_CNTL__SPARE__SHIFT 0x2 +#define RLC_RLCS_UTCL2_BUSY_CNTL__HW_CHK_DIS__SHIFT 0x4 +#define RLC_RLCS_UTCL2_BUSY_CNTL__AUTO_HDSHK_MASK 0x00000001L +#define RLC_RLCS_UTCL2_BUSY_CNTL__ACK_MASK 0x00000002L +#define RLC_RLCS_UTCL2_BUSY_CNTL__SPARE_MASK 0x0000000CL +#define RLC_RLCS_UTCL2_BUSY_CNTL__HW_CHK_DIS_MASK 0x00000070L +//RLC_RLCS_UTCL2_BUSY_STAT +#define RLC_RLCS_UTCL2_BUSY_STAT__REQ_STATUS__SHIFT 0x0 +#define RLC_RLCS_UTCL2_BUSY_STAT__ACK_STATUS__SHIFT 0x1 +#define RLC_RLCS_UTCL2_BUSY_STAT__REQ_STATUS_MASK 0x00000001L +#define RLC_RLCS_UTCL2_BUSY_STAT__ACK_STATUS_MASK 0x00000002L +//RLC_RLCS_DEC_END + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvfdec_rlc +//RLC_SAFE_MODE +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SPM_SAMPLE_CNT +#define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0 +#define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL +//RLC_SPM_MC_CNTL +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_MC_CNTL__RLC_SPM_SDR__SHIFT 0x4 +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6 +#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7 +#define RLC_SPM_MC_CNTL__RLC_SPM_TEMPORAL__SHIFT 0x8 +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP__SHIFT 0xb +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP_OVER__SHIFT 0xd +#define RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT 0xe +#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x10 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x11 +#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x13 +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL +#define RLC_SPM_MC_CNTL__RLC_SPM_SDR_MASK 0x00000030L +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L +#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L +#define RLC_SPM_MC_CNTL__RLC_SPM_TEMPORAL_MASK 0x00000700L +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP_MASK 0x00001800L +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP_OVER_MASK 0x00002000L +#define RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK 0x00004000L +#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00010000L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00060000L +#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_SPM_INT_CNTL +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_STATUS +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_INFO_1 +#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_SPM_INT_INFO_2 +#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18 +#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L +#define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L +//RLC_CSIB_ADDR_LO +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL +//RLC_CSIB_ADDR_HI +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x01FFFFFFL +//RLC_CSIB_LENGTH +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL +//RLC_CP_SCHEDULERS +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L +//RLC_CP_EOF_INT +#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 +#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 +#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L +#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CP_EOF_INT_CNTL +#define RLC_CP_EOF_INT_CNTL__DATA__SHIFT 0x0 +#define RLC_CP_EOF_INT_CNTL__DATA_MASK 0xFFFFFFFFL +//RLC_SPARE_INT_0 +#define RLC_SPARE_INT_0__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_0__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_0__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_0__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_0__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_0__COMPLETE_MASK 0x80000000L +//RLC_SPARE_INT_1 +#define RLC_SPARE_INT_1__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_1__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_1__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_1__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_1__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_1__COMPLETE_MASK 0x80000000L +//RLC_SPARE_INT_2 +#define RLC_SPARE_INT_2__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_2__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_2__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_2__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_2__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_2__COMPLETE_MASK 0x80000000L +//RLC_RLCV_SPARE_INT_1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_VFI_CMD +#define RLC_VFI_CMD__VFI_CMD__SHIFT 0x0 +#define RLC_VFI_CMD__VFI_CMD_MASK 0xFFFFFFFFL +//RLC_VFI_STAT +#define RLC_VFI_STAT__VFI_STATUS__SHIFT 0x0 +#define RLC_VFI_STAT__VFI_STATUS_MASK 0xFFFFFFFFL +//RLC_VFI_GRBM_GFX_INDEX +#define RLC_VFI_GRBM_GFX_INDEX__VFI_GRBM_GFX_INDEX__SHIFT 0x0 +#define RLC_VFI_GRBM_GFX_INDEX__VFI_GRBM_GFX_INDEX_MASK 0xFFFFFFFFL +//RLC_VFI_GRBM_GFX_CNTL +#define RLC_VFI_GRBM_GFX_CNTL__VFI_GRBM_GFX_CNTL__SHIFT 0x0 +#define RLC_VFI_GRBM_GFX_CNTL__VFI_GRBM_GFX_CNTL_MASK 0xFFFFFFFFL +//RLC_VFI_ADDR +#define RLC_VFI_ADDR__VFI_ADDR__SHIFT 0x0 +#define RLC_VFI_ADDR__VFI_ADDR_MASK 0xFFFFFFFFL +//RLC_VFI_DATA +#define RLC_VFI_DATA__VFI_DATA__SHIFT 0x0 +#define RLC_VFI_DATA__VFI_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pwrdec +//GRBMX_GLARB_BUSY_MASK +#define GRBMX_GLARB_BUSY_MASK__GLARB0C_BUSY_MASK__SHIFT 0x0 +#define GRBMX_GLARB_BUSY_MASK__GLARB0A_BUSY_MASK__SHIFT 0xf +#define GRBMX_GLARB_BUSY_MASK__GLARB1C_BUSY_MASK__SHIFT 0x10 +#define GRBMX_GLARB_BUSY_MASK__GLARB1A_BUSY_MASK__SHIFT 0x1f +#define GRBMX_GLARB_BUSY_MASK__GLARB0C_BUSY_MASK_MASK 0x00000FFFL +#define GRBMX_GLARB_BUSY_MASK__GLARB0A_BUSY_MASK_MASK 0x00008000L +#define GRBMX_GLARB_BUSY_MASK__GLARB1C_BUSY_MASK_MASK 0x0FFF0000L +#define GRBMX_GLARB_BUSY_MASK__GLARB1A_BUSY_MASK_MASK 0x80000000L +//CGTT_IA_CLK_CTRL +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__DIST_OVERRIDE__SHIFT 0x1a +#define CGTT_IA_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__PCM_OVERRIDE__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__TESS_DIST_OVERRIDE__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_IA_CLK_CTRL__DIST_OVERRIDE_MASK 0x04000000L +#define CGTT_IA_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_IA_CLK_CTRL__PCM_OVERRIDE_MASK 0x10000000L +#define CGTT_IA_CLK_CTRL__TESS_DIST_OVERRIDE_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_WD_CLK_CTRL +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_WD_CLK_CTRL__FE_OUT_OVERRIDE__SHIFT 0x17 +#define CGTT_WD_CLK_CTRL__UNUSED__SHIFT 0x18 +#define CGTT_WD_CLK_CTRL__DMA_PROC0_OVERRIDE__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__DMA_PROC1_OVERRIDE__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__DMA_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_WD_CLK_CTRL__FE_OUT_OVERRIDE_MASK 0x00800000L +#define CGTT_WD_CLK_CTRL__UNUSED_MASK 0x01000000L +#define CGTT_WD_CLK_CTRL__DMA_PROC0_OVERRIDE_MASK 0x02000000L +#define CGTT_WD_CLK_CTRL__DMA_PROC1_OVERRIDE_MASK 0x04000000L +#define CGTT_WD_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_WD_CLK_CTRL__DMA_OVERRIDE_MASK 0x10000000L +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_CP_CLK_CTRL +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPF_CLK_CTRL +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPC_CLK_CTRL +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_RLC_CLK_CTRL +#define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0xFFFFFFFFL +//GFX_ICG_GCR_CTRL +#define GFX_ICG_GCR_CTRL__ON_DELAY__SHIFT 0x0 +#define GFX_ICG_GCR_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GFX_ICG_GCR_CTRL__ON_DELAY_MASK 0x0000000FL +#define GFX_ICG_GCR_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//GC_EA_CPWD_ICG_CTRL +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x0 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_DRAM_FE__SHIFT 0x1 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_IO_FE__SHIFT 0x2 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x4 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_MAM__SHIFT 0x5 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_CREST__SHIFT 0x6 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_GMI__SHIFT 0x7 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_HDM__SHIFT 0x8 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PRB__SHIFT 0x9 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_LPDDR__SHIFT 0xa +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x00000001L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_DRAM_FE_MASK 0x00000002L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_IO_FE_MASK 0x00000004L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x00000010L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_MAM_MASK 0x00000020L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_CREST_MASK 0x00000040L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_GMI_MASK 0x00000080L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_HDM_MASK 0x00000100L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PRB_MASK 0x00000200L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_LPDDR_MASK 0x00000400L +//GFX_ICG_GC_CAC_CLK_CTRL +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_DYNAMIC_ICG_OVERRIDE__SHIFT 0x0 +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_REG_ICG_OVERRIDE__SHIFT 0x1 +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_DYNAMIC_ICG_OVERRIDE_MASK 0x00000001L +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_REG_ICG_OVERRIDE_MASK 0x00000002L +//GFX_ICG_GRBM_CTRL +#define GFX_ICG_GRBM_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_SE__SHIFT 0x10 +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GFX_ICG_GRBM_CTRL__OFF_HYSTERESIS_MASK 0x000003F0L +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_SE_MASK 0x00FF0000L +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +//CC_GC_HBM_DISABLE +#define CC_GC_HBM_DISABLE__CC_GC_HBM_DISABLE__SHIFT 0x10 +#define CC_GC_HBM_DISABLE__CC_GC_HBM_DISABLE_MASK 0x0FFF0000L +//GRBMX_LPDDR_DISABLE_0 +#define GRBMX_LPDDR_DISABLE_0__DISABLE__SHIFT 0x10 +#define GRBMX_LPDDR_DISABLE_0__DISABLE_MASK 0xFFFF0000L +//GRBMX_LPDDR_DISABLE_1 +#define GRBMX_LPDDR_DISABLE_1__DISABLE__SHIFT 0x10 +#define GRBMX_LPDDR_DISABLE_1__DISABLE_MASK 0xFFFF0000L +//GLARBI_GLARBR_MGCG_OVERRIDE +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//ICG_GLARBA_CTRL +#define ICG_GLARBA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GLARBA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GLARBA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GLARBA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GLARBA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GLARBA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GLARBA_CTRL__LOCAL_CAC_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GLARBA_CTRL__GCRD_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GLARBA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GLARBA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GLARBA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GLARBA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GLARBA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GLARBA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GLARBA_CTRL__LOCAL_CAC_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GLARBA_CTRL__GCRD_CLK_OVERRIDE_MASK 0x00000080L +//ICG_GLARBC_CLK_CTRL +#define ICG_GLARBC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GLARBC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GLARBC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GLARBC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GLARBC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GLARBC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GLARBC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GLARBC_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GLARBC_CLK_CTRL__CREST_RET_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GLARBC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GLARBC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GLARBC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GLARBC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GLARBC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GLARBC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GLARBC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GLARBC_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GLARBC_CLK_CTRL__CREST_RET_CLK_OVERRIDE_MASK 0x00000100L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pspdec +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID0_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID1_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID2_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID3_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID4_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID5_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID6_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID7_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID0_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID1_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID2_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID3_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID4_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID5_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID6_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID7_SECLEVEL_MASK 0xF0000000L +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID8_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID9_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID10_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID11_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID12_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID13_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID14_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID15_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID8_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID9_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID10_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID11_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID12_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID13_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID14_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID15_SECLEVEL_MASK 0xF0000000L +//GC_EA_CPWD_SDP_ERR_CTRL +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_GC_TO_SDP_ERREVENT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_SDP_TO_GC_UER__SHIFT 0x1 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_READ_RESPONSE_PARITY_EN__SHIFT 0x2 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_WRITE_RESPONSE_PARITY_EN__SHIFT 0x3 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_PARITY_EN__SHIFT 0x4 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_RSP_PARITY_EN__SHIFT 0x5 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_ACKCH_PARITY_EN__SHIFT 0x6 +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_GC_TO_SDP_ERREVENT_MASK 0x00000001L +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_SDP_TO_GC_UER_MASK 0x00000002L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_READ_RESPONSE_PARITY_EN_MASK 0x00000004L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_WRITE_RESPONSE_PARITY_EN_MASK 0x00000008L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_PARITY_EN_MASK 0x00000010L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_RSP_PARITY_EN_MASK 0x00000020L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_ACKCH_PARITY_EN_MASK 0x00000040L +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID0_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID1_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID2_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID3_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID4_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID5_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID6_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID7_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID0_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID1_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID2_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID3_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID4_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID5_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID6_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID7_SECLEVEL_MASK 0xF0000000L +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID8_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID9_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID10_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID11_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID12_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID13_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID14_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID15_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID8_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID9_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID10_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID11_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID12_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID13_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID14_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID15_SECLEVEL_MASK 0xF0000000L +//GRBM_SRCID_CAM_INDEX +#define GRBM_SRCID_CAM_INDEX__INDEX__SHIFT 0x0 +#define GRBM_SRCID_CAM_INDEX__INDEX_MASK 0x00000007L +//GRBM_SRCID_CAM_DATA +#define GRBM_SRCID_CAM_DATA__PROG_SRCID__SHIFT 0x0 +#define GRBM_SRCID_CAM_DATA__TRUST_LEVEL__SHIFT 0x18 +#define GRBM_SRCID_CAM_DATA__PROG_SRCID_MASK 0x0001FFFFL +#define GRBM_SRCID_CAM_DATA__TRUST_LEVEL_MASK 0x0F000000L +//GRBM_IOV_RANGE_ENABLE +#define GRBM_IOV_RANGE_ENABLE__ENABLE__SHIFT 0x0 +#define GRBM_IOV_RANGE_ENABLE__ENABLE_MASK 0xFFFFFFFFL +//GRBM_IOV_RANGE_READ_BLOCK_ENABLE +#define GRBM_IOV_RANGE_READ_BLOCK_ENABLE__ENABLE__SHIFT 0x0 +#define GRBM_IOV_RANGE_READ_BLOCK_ENABLE__ENABLE_MASK 0xFFFFFFFFL +//GRBM_SEC_CNTL +#define GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT 0x0 +#define GRBM_SEC_CNTL__DEBUG_ENABLE_MASK 0x00000001L +//GRBM_IOV_SPARE_RANGE_START +#define GRBM_IOV_SPARE_RANGE_START__START__SHIFT 0x0 +#define GRBM_IOV_SPARE_RANGE_START__START_MASK 0x0003FFFFL +//GRBM_IOV_SPARE_RANGE_END +#define GRBM_IOV_SPARE_RANGE_END__END__SHIFT 0x0 +#define GRBM_IOV_SPARE_RANGE_END__END_MASK 0x0003FFFFL +//GRBM_CAM_INDEX +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL +//GRBM_CAM_DATA +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_CAM_DATA_UPPER +#define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L +#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L +//RLC_REG_SEC_INT_STATUS +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT__SHIFT 0x0 +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_OVERFLOW__SHIFT 0x10 +#define RLC_REG_SEC_INT_STATUS__RESERVED__SHIFT 0x11 +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_MASK 0x0000FFFFL +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_OVERFLOW_MASK 0x00010000L +#define RLC_REG_SEC_INT_STATUS__RESERVED_MASK 0xFFFE0000L +//RLC_FWL_FIRST_VIOL_ADDR +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x0 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x12 +#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x13 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003FFFFL +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x00040000L +#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0xFFF80000L +//RLC_FWL_FIRST_VIOL_ADDR_HI +#define RLC_FWL_FIRST_VIOL_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define RLC_FWL_FIRST_VIOL_ADDR_HI__RESERVED__SHIFT 0x1c +#define RLC_FWL_FIRST_VIOL_ADDR_HI__ADDR_HI_MASK 0x0FFFFFFFL +#define RLC_FWL_FIRST_VIOL_ADDR_HI__RESERVED_MASK 0xF0000000L +//RLC_UTC_BYPASS_CNTL +#define RLC_UTC_BYPASS_CNTL__SPM__SHIFT 0x0 +#define RLC_UTC_BYPASS_CNTL__TH0__SHIFT 0x1 +#define RLC_UTC_BYPASS_CNTL__TH1__SHIFT 0x2 +#define RLC_UTC_BYPASS_CNTL__TH2__SHIFT 0x3 +#define RLC_UTC_BYPASS_CNTL__LX6__SHIFT 0x4 +#define RLC_UTC_BYPASS_CNTL__DMA__SHIFT 0x5 +#define RLC_UTC_BYPASS_CNTL__SRM__SHIFT 0x6 +#define RLC_UTC_BYPASS_CNTL__DLG__SHIFT 0x7 +#define RLC_UTC_BYPASS_CNTL__RESERVED__SHIFT 0x8 +#define RLC_UTC_BYPASS_CNTL__SPM_MASK 0x00000001L +#define RLC_UTC_BYPASS_CNTL__TH0_MASK 0x00000002L +#define RLC_UTC_BYPASS_CNTL__TH1_MASK 0x00000004L +#define RLC_UTC_BYPASS_CNTL__TH2_MASK 0x00000008L +#define RLC_UTC_BYPASS_CNTL__LX6_MASK 0x00000010L +#define RLC_UTC_BYPASS_CNTL__DMA_MASK 0x00000020L +#define RLC_UTC_BYPASS_CNTL__SRM_MASK 0x00000040L +#define RLC_UTC_BYPASS_CNTL__DLG_MASK 0x00000080L +#define RLC_UTC_BYPASS_CNTL__RESERVED_MASK 0xFFFFFF00L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cp_pspdec +//CP_MES_DM_INDEX_ADDR +#define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_MES_DM_INDEX_DATA +#define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CP_MEC_DM_INDEX_ADDR +#define CP_MEC_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_MEC_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_MEC_DM_INDEX_DATA +#define CP_MEC_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_MEC_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DM_INDEX_ADDR +#define CP_GFX_RS64_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_GFX_RS64_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DM_INDEX_DATA +#define CP_GFX_RS64_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_GFX_RS64_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_PSP_DEBUG +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x2 +#define CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 +#define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 +#define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L +#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L +#define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L +#define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L +//CPC_PSP_DEBUG +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 +#define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 +#define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L +#define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L +#define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_ch_pwrdec +//CHI_CHR_MGCG_OVERRIDE +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//ICG_CHA_CTRL +#define ICG_CHA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +//ICG_CHC_CLK_CTRL +#define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_CHC_CLK_CTRL__OC_IREQ_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_CHC_CLK_CTRL__OC_OREQ_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_CHC_CLK_CTRL__DCC_COMP_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_CHC_CLK_CTRL__OC_IREQ_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_CHC_CLK_CTRL__OC_OREQ_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_CHC_CLK_CTRL__DCC_COMP_CLK_OVERRIDE_MASK 0x00000200L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imudec +//GFX_IMU_C2PMSG_0 +#define GFX_IMU_C2PMSG_0__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_1 +#define GFX_IMU_C2PMSG_1__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_2 +#define GFX_IMU_C2PMSG_2__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_3 +#define GFX_IMU_C2PMSG_3__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_4 +#define GFX_IMU_C2PMSG_4__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_5 +#define GFX_IMU_C2PMSG_5__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_5__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_6 +#define GFX_IMU_C2PMSG_6__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_6__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_7 +#define GFX_IMU_C2PMSG_7__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_7__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_8 +#define GFX_IMU_C2PMSG_8__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_8__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_9 +#define GFX_IMU_C2PMSG_9__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_9__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_10 +#define GFX_IMU_C2PMSG_10__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_10__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_11 +#define GFX_IMU_C2PMSG_11__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_11__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_12 +#define GFX_IMU_C2PMSG_12__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_12__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_13 +#define GFX_IMU_C2PMSG_13__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_13__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_14 +#define GFX_IMU_C2PMSG_14__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_14__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_15 +#define GFX_IMU_C2PMSG_15__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_15__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_16 +#define GFX_IMU_C2PMSG_16__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_16__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_17 +#define GFX_IMU_C2PMSG_17__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_17__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_18 +#define GFX_IMU_C2PMSG_18__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_18__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_19 +#define GFX_IMU_C2PMSG_19__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_19__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_20 +#define GFX_IMU_C2PMSG_20__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_20__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_21 +#define GFX_IMU_C2PMSG_21__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_21__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_22 +#define GFX_IMU_C2PMSG_22__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_22__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_23 +#define GFX_IMU_C2PMSG_23__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_23__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_24 +#define GFX_IMU_C2PMSG_24__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_24__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_25 +#define GFX_IMU_C2PMSG_25__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_25__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_26 +#define GFX_IMU_C2PMSG_26__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_26__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_27 +#define GFX_IMU_C2PMSG_27__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_27__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_28 +#define GFX_IMU_C2PMSG_28__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_28__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_29 +#define GFX_IMU_C2PMSG_29__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_29__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_30 +#define GFX_IMU_C2PMSG_30__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_30__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_31 +#define GFX_IMU_C2PMSG_31__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_31__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_32 +#define GFX_IMU_C2PMSG_32__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_32__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_33 +#define GFX_IMU_C2PMSG_33__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_33__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_34 +#define GFX_IMU_C2PMSG_34__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_34__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_35 +#define GFX_IMU_C2PMSG_35__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_35__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_36 +#define GFX_IMU_C2PMSG_36__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_36__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_37 +#define GFX_IMU_C2PMSG_37__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_37__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_38 +#define GFX_IMU_C2PMSG_38__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_38__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_39 +#define GFX_IMU_C2PMSG_39__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_39__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_40 +#define GFX_IMU_C2PMSG_40__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_40__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_41 +#define GFX_IMU_C2PMSG_41__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_41__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_42 +#define GFX_IMU_C2PMSG_42__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_42__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_43 +#define GFX_IMU_C2PMSG_43__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_43__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_44 +#define GFX_IMU_C2PMSG_44__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_44__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_45 +#define GFX_IMU_C2PMSG_45__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_45__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_46 +#define GFX_IMU_C2PMSG_46__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_46__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_47 +#define GFX_IMU_C2PMSG_47__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_47__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_MSG_FLAGS +#define GFX_IMU_MSG_FLAGS__STATUS__SHIFT 0x0 +#define GFX_IMU_MSG_FLAGS__STATUS_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_ACCESS_CTRL0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0__SHIFT 0x0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1__SHIFT 0x3 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2__SHIFT 0x6 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3__SHIFT 0x9 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4__SHIFT 0xc +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5__SHIFT 0xf +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6__SHIFT 0x12 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7__SHIFT 0x15 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0_MASK 0x00000007L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1_MASK 0x00000038L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2_MASK 0x000001C0L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3_MASK 0x00000E00L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4_MASK 0x00007000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5_MASK 0x00038000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6_MASK 0x001C0000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7_MASK 0x00E00000L +//GFX_IMU_C2PMSG_ACCESS_CTRL1 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15__SHIFT 0x0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23__SHIFT 0x3 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31__SHIFT 0x6 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39__SHIFT 0x9 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47__SHIFT 0xc +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15_MASK 0x00000007L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23_MASK 0x00000038L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31_MASK 0x000001C0L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39_MASK 0x00000E00L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47_MASK 0x00007000L +//GFX_IMU_PWRMGT_IRQ_CTRL +#define GFX_IMU_PWRMGT_IRQ_CTRL__REQ__SHIFT 0x0 +#define GFX_IMU_PWRMGT_IRQ_CTRL__REQ_MASK 0x00000001L +//GFX_IMU_MP1_MUTEX +#define GFX_IMU_MP1_MUTEX__MUTEX__SHIFT 0x0 +#define GFX_IMU_MP1_MUTEX__MUTEX_MASK 0x00000003L +//GFX_IMU_RLC_DATA_4 +#define GFX_IMU_RLC_DATA_4__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_3 +#define GFX_IMU_RLC_DATA_3__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_2 +#define GFX_IMU_RLC_DATA_2__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_1 +#define GFX_IMU_RLC_DATA_1__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_0 +#define GFX_IMU_RLC_DATA_0__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_CMD +#define GFX_IMU_RLC_CMD__CMD__SHIFT 0x0 +#define GFX_IMU_RLC_CMD__CMD_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_MUTEX +#define GFX_IMU_RLC_MUTEX__MUTEX__SHIFT 0x0 +#define GFX_IMU_RLC_MUTEX__MUTEX_MASK 0x00000003L +//GFX_IMU_RLC_MSG_STATUS +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY__SHIFT 0x0 +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR__SHIFT 0x1 +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE__SHIFT 0x10 +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG__SHIFT 0x1e +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG__SHIFT 0x1f +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY_MASK 0x00000001L +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR_MASK 0x00000002L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE_MASK 0x00010000L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG_MASK 0x40000000L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG_MASK 0x80000000L +//RLC_GFX_IMU_DATA_0 +#define RLC_GFX_IMU_DATA_0__DATA__SHIFT 0x0 +#define RLC_GFX_IMU_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IMU_CMD +#define RLC_GFX_IMU_CMD__CMD__SHIFT 0x0 +#define RLC_GFX_IMU_CMD__CMD_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_STATUS +#define GFX_IMU_RLC_STATUS__PD_ACTIVE__SHIFT 0x0 +#define GFX_IMU_RLC_STATUS__RLC_ALIVE__SHIFT 0x1 +#define GFX_IMU_RLC_STATUS__TBD2__SHIFT 0x2 +#define GFX_IMU_RLC_STATUS__TBD3__SHIFT 0x3 +#define GFX_IMU_RLC_STATUS__PD_ACTIVE_MASK 0x00000001L +#define GFX_IMU_RLC_STATUS__RLC_ALIVE_MASK 0x00000002L +#define GFX_IMU_RLC_STATUS__TBD2_MASK 0x00000004L +#define GFX_IMU_RLC_STATUS__TBD3_MASK 0x00000008L +//GFX_IMU_STATUS +#define GFX_IMU_STATUS__ALLOW_GFXOFF__SHIFT 0x0 +#define GFX_IMU_STATUS__ALLOW_FA_DCS__SHIFT 0x1 +#define GFX_IMU_STATUS__TBD4__SHIFT 0x4 +#define GFX_IMU_STATUS__TBD5__SHIFT 0x5 +#define GFX_IMU_STATUS__TBD6__SHIFT 0x6 +#define GFX_IMU_STATUS__TBD7__SHIFT 0x7 +#define GFX_IMU_STATUS__TBD8__SHIFT 0x8 +#define GFX_IMU_STATUS__TBD9__SHIFT 0x9 +#define GFX_IMU_STATUS__TBD10__SHIFT 0xa +#define GFX_IMU_STATUS__TBD11__SHIFT 0xb +#define GFX_IMU_STATUS__TBD12__SHIFT 0xc +#define GFX_IMU_STATUS__TBD13__SHIFT 0xd +#define GFX_IMU_STATUS__TBD14__SHIFT 0xe +#define GFX_IMU_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf +#define GFX_IMU_STATUS__ALLOW_GFXOFF_MASK 0x00000001L +#define GFX_IMU_STATUS__ALLOW_FA_DCS_MASK 0x00000002L +#define GFX_IMU_STATUS__TBD4_MASK 0x00000010L +#define GFX_IMU_STATUS__TBD5_MASK 0x00000020L +#define GFX_IMU_STATUS__TBD6_MASK 0x00000040L +#define GFX_IMU_STATUS__TBD7_MASK 0x00000080L +#define GFX_IMU_STATUS__TBD8_MASK 0x00000100L +#define GFX_IMU_STATUS__TBD9_MASK 0x00000200L +#define GFX_IMU_STATUS__TBD10_MASK 0x00000400L +#define GFX_IMU_STATUS__TBD11_MASK 0x00000800L +#define GFX_IMU_STATUS__TBD12_MASK 0x00001000L +#define GFX_IMU_STATUS__TBD13_MASK 0x00002000L +#define GFX_IMU_STATUS__TBD14_MASK 0x00004000L +#define GFX_IMU_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L +//GFX_IMU_SOC_DATA +#define GFX_IMU_SOC_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_SOC_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SOC_ADDR +#define GFX_IMU_SOC_ADDR__ADDR__SHIFT 0x0 +#define GFX_IMU_SOC_ADDR__ADDR_MASK 0xFFFFFFFFL +//GFX_IMU_SOC_REQ +#define GFX_IMU_SOC_REQ__REQ_BUSY__SHIFT 0x0 +#define GFX_IMU_SOC_REQ__R_W__SHIFT 0x1 +#define GFX_IMU_SOC_REQ__ERR__SHIFT 0x1f +#define GFX_IMU_SOC_REQ__REQ_BUSY_MASK 0x00000001L +#define GFX_IMU_SOC_REQ__R_W_MASK 0x00000002L +#define GFX_IMU_SOC_REQ__ERR_MASK 0x80000000L +//GFX_IMU_VF_CTRL +#define GFX_IMU_VF_CTRL__VF__SHIFT 0x0 +#define GFX_IMU_VF_CTRL__VFID__SHIFT 0x1 +#define GFX_IMU_VF_CTRL__QOS__SHIFT 0x7 +#define GFX_IMU_VF_CTRL__VF_MASK 0x00000001L +#define GFX_IMU_VF_CTRL__VFID_MASK 0x0000007EL +#define GFX_IMU_VF_CTRL__QOS_MASK 0x00000780L +//GFX_IMU_SCRATCH_0 +#define GFX_IMU_SCRATCH_0__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_1 +#define GFX_IMU_SCRATCH_1__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_2 +#define GFX_IMU_SCRATCH_2__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_3 +#define GFX_IMU_SCRATCH_3__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_4 +#define GFX_IMU_SCRATCH_4__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_5 +#define GFX_IMU_SCRATCH_5__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_5__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_6 +#define GFX_IMU_SCRATCH_6__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_6__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_7 +#define GFX_IMU_SCRATCH_7__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_7__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_8 +#define GFX_IMU_SCRATCH_8__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_8__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_9 +#define GFX_IMU_SCRATCH_9__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_9__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_10 +#define GFX_IMU_SCRATCH_10__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_10__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_11 +#define GFX_IMU_SCRATCH_11__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_11__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_12 +#define GFX_IMU_SCRATCH_12__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_12__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_13 +#define GFX_IMU_SCRATCH_13__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_13__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_14 +#define GFX_IMU_SCRATCH_14__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_14__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_15 +#define GFX_IMU_SCRATCH_15__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_15__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_FW_GTS_LO +#define GFX_IMU_FW_GTS_LO__TSTAMP_LO__SHIFT 0x0 +#define GFX_IMU_FW_GTS_LO__TSTAMP_LO_MASK 0xFFFFFFFFL +//GFX_IMU_FW_GTS_HI +#define GFX_IMU_FW_GTS_HI__TSTAMP_HI__SHIFT 0x0 +#define GFX_IMU_FW_GTS_HI__TSTAMP_HI_MASK 0x00FFFFFFL +//GFX_IMU_GTS_OFFSET_LO +#define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 +#define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL +//GFX_IMU_GTS_OFFSET_HI +#define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 +#define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL +//GFX_IMU_RLC_GTS_OFFSET_LO +#define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 +#define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_GTS_OFFSET_HI +#define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 +#define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL +//GFX_IMU_CORE_INT_STATUS +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24__SHIFT 0x18 +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25__SHIFT 0x19 +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29__SHIFT 0x1d +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24_MASK 0x01000000L +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25_MASK 0x02000000L +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29_MASK 0x20000000L +//GFX_IMU_PIC_INT_MASK +#define GFX_IMU_PIC_INT_MASK__MASK_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_MASK__MASK_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_MASK__MASK_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_MASK__MASK_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_MASK__MASK_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_MASK__MASK_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_MASK__MASK_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_MASK__MASK_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_MASK__MASK_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_MASK__MASK_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_MASK__MASK_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_MASK__MASK_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_MASK__MASK_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_MASK__MASK_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_MASK__MASK_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_MASK__MASK_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_MASK__MASK_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_MASK__MASK_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_MASK__MASK_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_MASK__MASK_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_MASK__MASK_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_MASK__MASK_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_MASK__MASK_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_MASK__MASK_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_MASK__MASK_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_MASK__MASK_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_MASK__MASK_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_MASK__MASK_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_MASK__MASK_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_MASK__MASK_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_MASK__MASK_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_MASK__MASK_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_MASK__MASK_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_MASK__MASK_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_MASK__MASK_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_MASK__MASK_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_MASK__MASK_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_MASK__MASK_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_MASK__MASK_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_MASK__MASK_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_MASK__MASK_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_MASK__MASK_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_MASK__MASK_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_MASK__MASK_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_MASK__MASK_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_MASK__MASK_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_MASK__MASK_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_MASK__MASK_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_MASK__MASK_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_MASK__MASK_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_MASK__MASK_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_MASK__MASK_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_MASK__MASK_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_MASK__MASK_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_MASK__MASK_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_MASK__MASK_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_MASK__MASK_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_MASK__MASK_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_MASK__MASK_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_MASK__MASK_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_MASK__MASK_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_MASK__MASK_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_MASK__MASK_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_LVL +#define GFX_IMU_PIC_INT_LVL__LVL_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_LVL__LVL_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_LVL__LVL_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_LVL__LVL_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_LVL__LVL_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_LVL__LVL_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_LVL__LVL_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_LVL__LVL_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_LVL__LVL_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_LVL__LVL_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_LVL__LVL_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_LVL__LVL_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_LVL__LVL_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_LVL__LVL_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_LVL__LVL_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_LVL__LVL_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_LVL__LVL_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_LVL__LVL_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_LVL__LVL_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_LVL__LVL_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_LVL__LVL_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_LVL__LVL_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_LVL__LVL_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_LVL__LVL_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_LVL__LVL_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_LVL__LVL_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_LVL__LVL_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_LVL__LVL_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_LVL__LVL_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_LVL__LVL_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_LVL__LVL_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_LVL__LVL_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_LVL__LVL_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_LVL__LVL_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_LVL__LVL_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_LVL__LVL_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_LVL__LVL_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_LVL__LVL_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_LVL__LVL_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_LVL__LVL_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_LVL__LVL_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_LVL__LVL_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_LVL__LVL_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_LVL__LVL_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_LVL__LVL_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_LVL__LVL_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_LVL__LVL_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_LVL__LVL_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_LVL__LVL_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_LVL__LVL_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_LVL__LVL_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_LVL__LVL_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_LVL__LVL_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_LVL__LVL_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_LVL__LVL_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_LVL__LVL_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_LVL__LVL_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_LVL__LVL_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_LVL__LVL_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_LVL__LVL_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_LVL__LVL_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_LVL__LVL_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_LVL__LVL_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_EDGE +#define GFX_IMU_PIC_INT_EDGE__EDGE_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_EDGE__EDGE_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_EDGE__EDGE_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_EDGE__EDGE_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_EDGE__EDGE_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_EDGE__EDGE_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_EDGE__EDGE_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_EDGE__EDGE_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_EDGE__EDGE_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_EDGE__EDGE_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_EDGE__EDGE_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_EDGE__EDGE_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_EDGE__EDGE_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_EDGE__EDGE_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_EDGE__EDGE_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_EDGE__EDGE_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_EDGE__EDGE_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_EDGE__EDGE_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_EDGE__EDGE_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_EDGE__EDGE_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_EDGE__EDGE_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_EDGE__EDGE_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_EDGE__EDGE_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_EDGE__EDGE_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_EDGE__EDGE_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_EDGE__EDGE_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_EDGE__EDGE_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_EDGE__EDGE_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_EDGE__EDGE_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_EDGE__EDGE_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_EDGE__EDGE_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_EDGE__EDGE_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_EDGE__EDGE_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_EDGE__EDGE_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_EDGE__EDGE_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_EDGE__EDGE_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_EDGE__EDGE_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_EDGE__EDGE_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_EDGE__EDGE_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_EDGE__EDGE_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_EDGE__EDGE_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_EDGE__EDGE_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_EDGE__EDGE_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_EDGE__EDGE_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_PRI_0 +#define GFX_IMU_PIC_INT_PRI_0__PRI_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_0__PRI_1__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_0__PRI_2__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_0__PRI_3__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_0__PRI_0_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_0__PRI_1_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_0__PRI_2_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_0__PRI_3_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_1 +#define GFX_IMU_PIC_INT_PRI_1__PRI_4__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_1__PRI_5__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_1__PRI_6__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_1__PRI_7__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_1__PRI_4_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_1__PRI_5_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_1__PRI_6_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_1__PRI_7_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_2 +#define GFX_IMU_PIC_INT_PRI_2__PRI_8__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_2__PRI_9__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_2__PRI_10__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_2__PRI_11__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_2__PRI_8_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_2__PRI_9_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_2__PRI_10_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_2__PRI_11_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_3 +#define GFX_IMU_PIC_INT_PRI_3__PRI_12__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_3__PRI_13__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_3__PRI_14__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_3__PRI_15__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_3__PRI_12_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_3__PRI_13_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_3__PRI_14_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_3__PRI_15_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_4 +#define GFX_IMU_PIC_INT_PRI_4__PRI_16__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_4__PRI_17__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_4__PRI_18__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_4__PRI_19__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_4__PRI_16_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_4__PRI_17_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_4__PRI_18_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_4__PRI_19_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_5 +#define GFX_IMU_PIC_INT_PRI_5__PRI_20__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_5__PRI_21__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_5__PRI_22__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_5__PRI_23__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_5__PRI_20_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_5__PRI_21_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_5__PRI_22_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_5__PRI_23_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_6 +#define GFX_IMU_PIC_INT_PRI_6__PRI_24__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_6__PRI_25__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_6__PRI_26__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_6__PRI_27__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_6__PRI_24_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_6__PRI_25_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_6__PRI_26_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_6__PRI_27_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_7 +#define GFX_IMU_PIC_INT_PRI_7__PRI_28__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_7__PRI_29__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_7__PRI_30__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_7__PRI_31__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_7__PRI_28_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_7__PRI_29_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_7__PRI_30_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_7__PRI_31_MASK 0xFF000000L +//GFX_IMU_PIC_INT_STATUS +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT 0xa +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS11__SHIFT 0xb +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS12__SHIFT 0xc +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS13__SHIFT 0xd +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS14__SHIFT 0xe +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS15__SHIFT 0xf +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS31_MASK 0x80000000L +//GFX_IMU_PIC_INTR +#define GFX_IMU_PIC_INTR__INTR_n__SHIFT 0x0 +#define GFX_IMU_PIC_INTR__INTR_n_MASK 0x00000001L +//GFX_IMU_PIC_INTR_ID +#define GFX_IMU_PIC_INTR_ID__INTR_n__SHIFT 0x0 +#define GFX_IMU_PIC_INTR_ID__INTR_n_MASK 0x000000FFL +//GFX_IMU_IH_CTRL_1 +#define GFX_IMU_IH_CTRL_1__CONTEXT_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_1__CONTEXT_ID_MASK 0xFFFFFFFFL +//GFX_IMU_IH_CTRL_2 +#define GFX_IMU_IH_CTRL_2__CONTEXT_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_2__RING_ID__SHIFT 0x8 +#define GFX_IMU_IH_CTRL_2__VM_ID__SHIFT 0x10 +#define GFX_IMU_IH_CTRL_2__SRSTB__SHIFT 0x1f +#define GFX_IMU_IH_CTRL_2__CONTEXT_ID_MASK 0x000000FFL +#define GFX_IMU_IH_CTRL_2__RING_ID_MASK 0x0000FF00L +#define GFX_IMU_IH_CTRL_2__VM_ID_MASK 0x000F0000L +#define GFX_IMU_IH_CTRL_2__SRSTB_MASK 0x80000000L +//GFX_IMU_IH_CTRL_3 +#define GFX_IMU_IH_CTRL_3__SOURCE_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_3__VF_ID__SHIFT 0x8 +#define GFX_IMU_IH_CTRL_3__VF__SHIFT 0xd +#define GFX_IMU_IH_CTRL_3__SOURCE_ID_MASK 0x000000FFL +#define GFX_IMU_IH_CTRL_3__VF_ID_MASK 0x00001F00L +#define GFX_IMU_IH_CTRL_3__VF_MASK 0x00002000L +//GFX_IMU_IH_STATUS +#define GFX_IMU_IH_STATUS__IH_BUSY__SHIFT 0x0 +#define GFX_IMU_IH_STATUS__IH_BUSY_MASK 0x00000001L +//GFX_IMU_FUSESTRAP +//GFX_IMU_GFXCLK_BYPASS_CTRL +#define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL__SHIFT 0x0 +#define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL_MASK 0x00000001L +//GFX_IMU_CLK_CTRL +#define GFX_IMU_CLK_CTRL__CG_OVR__SHIFT 0x0 +#define GFX_IMU_CLK_CTRL__CG_OVR_CORE__SHIFT 0x1 +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV__SHIFT 0x10 +#define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD__SHIFT 0x1c +#define GFX_IMU_CLK_CTRL__CG_OVR_MASK 0x00000001L +#define GFX_IMU_CLK_CTRL__CG_OVR_CORE_MASK 0x00000002L +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV_MASK 0x007F0000L +#define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD_MASK 0xF0000000L +//GFX_IMU_DOORBELL_CONTROL +#define GFX_IMU_DOORBELL_CONTROL__OVR_EN__SHIFT 0x0 +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR__SHIFT 0x1 +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS__SHIFT 0x1f +#define GFX_IMU_DOORBELL_CONTROL__OVR_EN_MASK 0x00000001L +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR_MASK 0x00000002L +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS_MASK 0x80000000L +//GFX_IMU_RLC_CG_CTRL +#define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG__SHIFT 0x0 +#define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN__SHIFT 0x1 +#define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG_MASK 0x00000001L +#define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN_MASK 0x00000002L +//GFX_IMU_RLC_THROTTLE_GFX +#define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN__SHIFT 0x0 +#define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN_MASK 0x00000001L +//GFX_IMU_RLC_RESET_VECTOR +#define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF__SHIFT 0x0 +#define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2 +#define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3 +#define GFX_IMU_RLC_RESET_VECTOR__VECTOR__SHIFT 0x6 +#define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF_MASK 0x00000001L +#define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L +#define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L +#define GFX_IMU_RLC_RESET_VECTOR__VECTOR_MASK 0x000000C0L +//GFX_IMU_RLC_OVERRIDE +#define GFX_IMU_RLC_OVERRIDE__DS_ALLOW__SHIFT 0x0 +#define GFX_IMU_RLC_OVERRIDE__DS_ALLOW_MASK 0x00000001L +//GFX_IMU_DPM_CONTROL +#define GFX_IMU_DPM_CONTROL__ACC_RESET__SHIFT 0x0 +#define GFX_IMU_DPM_CONTROL__ACC_START__SHIFT 0x1 +#define GFX_IMU_DPM_CONTROL__BUSY_MASK__SHIFT 0x2 +#define GFX_IMU_DPM_CONTROL__ACC_RESET_MASK 0x00000001L +#define GFX_IMU_DPM_CONTROL__ACC_START_MASK 0x00000002L +#define GFX_IMU_DPM_CONTROL__BUSY_MASK_MASK 0x0003FFFCL +//GFX_IMU_DPM_ACC +#define GFX_IMU_DPM_ACC__COUNT__SHIFT 0x0 +#define GFX_IMU_DPM_ACC__COUNT_MASK 0x00FFFFFFL +//GFX_IMU_DPM_REF_COUNTER +#define GFX_IMU_DPM_REF_COUNTER__COUNT__SHIFT 0x0 +#define GFX_IMU_DPM_REF_COUNTER__COUNT_MASK 0x00FFFFFFL +//GFX_IMU_RLC_RAM_INDEX +#define GFX_IMU_RLC_RAM_INDEX__INDEX__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX__SHIFT 0x10 +#define GFX_IMU_RLC_RAM_INDEX__RAM_VALID__SHIFT 0x1f +#define GFX_IMU_RLC_RAM_INDEX__INDEX_MASK 0x000000FFL +#define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX_MASK 0x00FF0000L +#define GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK 0x80000000L +//GFX_IMU_RLC_RAM_ADDR_HIGH +#define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB_MASK 0x0000FFFFL +//GFX_IMU_RLC_RAM_ADDR_LOW +#define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_RAM_DATA +#define GFX_IMU_RLC_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_FENCE_CTRL +#define GFX_IMU_FENCE_CTRL__ENABLED__SHIFT 0x0 +#define GFX_IMU_FENCE_CTRL__ARM_LOG__SHIFT 0x1 +#define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS__SHIFT 0x3 +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN__SHIFT 0x8 +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR__SHIFT 0x9 +#define GFX_IMU_FENCE_CTRL__ENABLED_MASK 0x00000001L +#define GFX_IMU_FENCE_CTRL__ARM_LOG_MASK 0x00000002L +#define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS_MASK 0x00000008L +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN_MASK 0x00000100L +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_MASK 0x00000200L +//GFX_IMU_FENCE_LOG_INIT +#define GFX_IMU_FENCE_LOG_INIT__UNIT_ID__SHIFT 0x0 +#define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID__SHIFT 0x7 +#define GFX_IMU_FENCE_LOG_INIT__UNIT_ID_MASK 0x0000007FL +#define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID_MASK 0x0001FF80L +//GFX_IMU_FENCE_LOG_ADDR +#define GFX_IMU_FENCE_LOG_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_FENCE_LOG_ADDR__ADDR_MASK 0x000FFFFCL +//GFX_IMU_PROGRAM_CTR +#define GFX_IMU_PROGRAM_CTR__PC__SHIFT 0x0 +#define GFX_IMU_PROGRAM_CTR__PC_MASK 0xFFFFFFFFL +//GFX_IMU_CORE_CTRL +#define GFX_IMU_CORE_CTRL__CRESET__SHIFT 0x0 +#define GFX_IMU_CORE_CTRL__CSTALL__SHIFT 0x1 +#define GFX_IMU_CORE_CTRL__CDBGENABLE__SHIFT 0x2 +#define GFX_IMU_CORE_CTRL__DRESET__SHIFT 0x3 +#define GFX_IMU_CORE_CTRL__HALT_ON_RESET__SHIFT 0x4 +#define GFX_IMU_CORE_CTRL__BREAK_IN__SHIFT 0x8 +#define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK__SHIFT 0x9 +#define GFX_IMU_CORE_CTRL__CRESET_MASK 0x00000001L +#define GFX_IMU_CORE_CTRL__CSTALL_MASK 0x00000002L +#define GFX_IMU_CORE_CTRL__CDBGENABLE_MASK 0x00000004L +#define GFX_IMU_CORE_CTRL__DRESET_MASK 0x00000008L +#define GFX_IMU_CORE_CTRL__HALT_ON_RESET_MASK 0x00000010L +#define GFX_IMU_CORE_CTRL__BREAK_IN_MASK 0x00000100L +#define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK_MASK 0x00000200L +//GFX_IMU_CORE_STATUS +#define GFX_IMU_CORE_STATUS__CBUSY__SHIFT 0x0 +#define GFX_IMU_CORE_STATUS__PWAIT_MODE__SHIFT 0x1 +#define GFX_IMU_CORE_STATUS__CINTLEVEL__SHIFT 0x4 +#define GFX_IMU_CORE_STATUS__BREAK_IN_ACK__SHIFT 0x8 +#define GFX_IMU_CORE_STATUS__BREAK_OUT__SHIFT 0x9 +#define GFX_IMU_CORE_STATUS__P_FATAL_ERROR__SHIFT 0xb +#define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL__SHIFT 0x18 +#define GFX_IMU_CORE_STATUS__FAULT_TYPE__SHIFT 0x1c +#define GFX_IMU_CORE_STATUS__CBUSY_MASK 0x00000001L +#define GFX_IMU_CORE_STATUS__PWAIT_MODE_MASK 0x00000002L +#define GFX_IMU_CORE_STATUS__CINTLEVEL_MASK 0x000000F0L +#define GFX_IMU_CORE_STATUS__BREAK_IN_ACK_MASK 0x00000100L +#define GFX_IMU_CORE_STATUS__BREAK_OUT_MASK 0x00000200L +#define GFX_IMU_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000800L +#define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL_MASK 0x0F000000L +#define GFX_IMU_CORE_STATUS__FAULT_TYPE_MASK 0xF0000000L +//GFX_IMU_PWROKRAW +#define GFX_IMU_PWROKRAW__PWROKRAW__SHIFT 0x0 +#define GFX_IMU_PWROKRAW__PWROKRAW_MASK 0x00000001L +//GFX_IMU_PWROK +#define GFX_IMU_PWROK__PWROK__SHIFT 0x0 +#define GFX_IMU_PWROK__PWROK_MASK 0x00000001L +//GFX_IMU_GAP_PWROK +#define GFX_IMU_GAP_PWROK__GAP_PWROK__SHIFT 0x0 +#define GFX_IMU_GAP_PWROK__GAP_PWROK_MASK 0x00000001L +//GFX_IMU_RESETn +#define GFX_IMU_RESETn__Cpl_RESETn__SHIFT 0x0 +#define GFX_IMU_RESETn__Cpl_RESETn_MASK 0x00000001L +//GFX_IMU_GFX_RESET_CTRL +#define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB__SHIFT 0x0 +#define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB__SHIFT 0x3 +#define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB__SHIFT 0x4 +#define GFX_IMU_GFX_RESET_CTRL__DFLL_SRESETB__SHIFT 0x5 +#define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB_MASK 0x00000001L +#define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB_MASK 0x00000008L +#define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB_MASK 0x00000010L +#define GFX_IMU_GFX_RESET_CTRL__DFLL_SRESETB_MASK 0x00000020L +//GFX_IMU_VDCI_RESET_CTRL +#define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn__SHIFT 0x0 +#define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET__SHIFT 0x1 +#define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET__SHIFT 0x2 +#define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn__SHIFT 0x4 +#define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn_MASK 0x00000001L +#define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET_MASK 0x00000002L +#define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET_MASK 0x00000004L +#define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn_MASK 0x00000010L +//GFX_IMU_GFX_ISO_CTRL +#define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn__SHIFT 0x0 +#define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN__SHIFT 0x1 +#define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN__SHIFT 0x2 +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn__SHIFT 0x3 +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn__SHIFT 0x4 +#define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn_MASK 0x00000001L +#define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN_MASK 0x00000002L +#define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN_MASK 0x00000004L +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn_MASK 0x00000008L +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn_MASK 0x00000010L +//GFX_IMU_TIMER0_CTRL0 +#define GFX_IMU_TIMER0_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER0_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER0_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER0_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER0_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER0_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER0_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER0_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER0_CTRL1 +#define GFX_IMU_TIMER0_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER0_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER0_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER0_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER0_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER0_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER0_CMP_AUTOINC +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER0_CMP_INTEN +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER0_CMP0 +#define GFX_IMU_TIMER0_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_CMP1 +#define GFX_IMU_TIMER0_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_CMP3 +#define GFX_IMU_TIMER0_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_VALUE +#define GFX_IMU_TIMER0_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CTRL0 +#define GFX_IMU_TIMER1_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER1_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER1_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER1_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER1_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER1_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER1_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER1_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER1_CTRL1 +#define GFX_IMU_TIMER1_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER1_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER1_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER1_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER1_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER1_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER1_CMP_AUTOINC +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER1_CMP_INTEN +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER1_CMP0 +#define GFX_IMU_TIMER1_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CMP1 +#define GFX_IMU_TIMER1_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CMP3 +#define GFX_IMU_TIMER1_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_VALUE +#define GFX_IMU_TIMER1_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_FUSE_CTRL +#define GFX_IMU_FUSE_CTRL__DIV_OVR__SHIFT 0x0 +#define GFX_IMU_FUSE_CTRL__DIV_OVR_EN__SHIFT 0x5 +#define GFX_IMU_FUSE_CTRL__FORCE_DONE__SHIFT 0x6 +#define GFX_IMU_FUSE_CTRL__DIV_OVR_MASK 0x0000001FL +#define GFX_IMU_FUSE_CTRL__DIV_OVR_EN_MASK 0x00000020L +#define GFX_IMU_FUSE_CTRL__FORCE_DONE_MASK 0x00000040L +//GFX_IMU_D_RAM_ADDR +#define GFX_IMU_D_RAM_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_D_RAM_ADDR__ADDR_MASK 0x0000FFFCL +//GFX_IMU_D_RAM_DATA +#define GFX_IMU_D_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_D_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_GFX_IH_GASKET_CTRL +#define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB__SHIFT 0x0 +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL__SHIFT 0x10 +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW__SHIFT 0x14 +#define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB_MASK 0x00000001L +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL_MASK 0x000F0000L +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW_MASK 0x00100000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imu_pspdec +//GFX_IMU_RLC_BOOTLOADER_ADDR_HI +#define GFX_IMU_RLC_BOOTLOADER_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define GFX_IMU_RLC_BOOTLOADER_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_BOOTLOADER_ADDR_LO +#define GFX_IMU_RLC_BOOTLOADER_ADDR_LO__ADDR_LO__SHIFT 0x0 +#define GFX_IMU_RLC_BOOTLOADER_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_BOOTLOADER_SIZE +#define GFX_IMU_RLC_BOOTLOADER_SIZE__SIZE__SHIFT 0x0 +#define GFX_IMU_RLC_BOOTLOADER_SIZE__SIZE_MASK 0x03FFFFFFL +//GFX_IMU_I_RAM_ADDR +#define GFX_IMU_I_RAM_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_I_RAM_ADDR__ADDR_MASK 0x0000FFFCL +//GFX_IMU_I_RAM_DATA +#define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec +//GRBMH_CNTL +#define GRBMH_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBMH_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBMH_CNTL__READ_TIMEOUT_MASK 0x000000FFL +#define GRBMH_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBMH_INTF_CNTL +#define GRBMH_INTF_CNTL__RSMUSE_PATH_DISABLE__SHIFT 0x0 +#define GRBMH_INTF_CNTL__GRBM_PATH_DISABLE__SHIFT 0x1 +#define GRBMH_INTF_CNTL__RSMUSE_PATH_DISABLE_MASK 0x00000001L +#define GRBMH_INTF_CNTL__GRBM_PATH_DISABLE_MASK 0x00000002L +//GRBMH_STATUS +#define GRBMH_STATUS__SC_CLEAN__SHIFT 0x0 +#define GRBMH_STATUS__DB_CLEAN__SHIFT 0x1 +#define GRBMH_STATUS__CB_CLEAN__SHIFT 0x2 +#define GRBMH_STATUS__UTCL1_BUSY__SHIFT 0x3 +#define GRBMH_STATUS__TCP_BUSY__SHIFT 0x4 +#define GRBMH_STATUS__GL1CC_BUSY__SHIFT 0x5 +#define GRBMH_STATUS__GL1XCC_BUSY__SHIFT 0x6 +#define GRBMH_STATUS__GE_BUSY__SHIFT 0x9 +#define GRBMH_STATUS__RLC_BUSY__SHIFT 0xa +#define GRBMH_STATUS__WGS_BUSY__SHIFT 0xb +#define GRBMH_STATUS__EA_LINK_BUSY__SHIFT 0xc +#define GRBMH_STATUS__EA_BUSY__SHIFT 0xd +#define GRBMH_STATUS__GL2C_BUSY__SHIFT 0xe +#define GRBMH_STATUS__GL2A_BUSY__SHIFT 0xf +#define GRBMH_STATUS__SC_BUSY__SHIFT 0x11 +#define GRBMH_STATUS__GL1A_BUSY__SHIFT 0x12 +#define GRBMH_STATUS__BCI_BUSY__SHIFT 0x14 +#define GRBMH_STATUS__SQG_BUSY__SHIFT 0x17 +#define GRBMH_STATUS__PA_BUSY__SHIFT 0x18 +#define GRBMH_STATUS__TA_BUSY__SHIFT 0x19 +#define GRBMH_STATUS__SX_BUSY__SHIFT 0x1a +#define GRBMH_STATUS__SPI_BUSY__SHIFT 0x1b +#define GRBMH_STATUS__DB_BUSY__SHIFT 0x1e +#define GRBMH_STATUS__CB_BUSY__SHIFT 0x1f +#define GRBMH_STATUS__SC_CLEAN_MASK 0x00000001L +#define GRBMH_STATUS__DB_CLEAN_MASK 0x00000002L +#define GRBMH_STATUS__CB_CLEAN_MASK 0x00000004L +#define GRBMH_STATUS__UTCL1_BUSY_MASK 0x00000008L +#define GRBMH_STATUS__TCP_BUSY_MASK 0x00000010L +#define GRBMH_STATUS__GL1CC_BUSY_MASK 0x00000020L +#define GRBMH_STATUS__GL1XCC_BUSY_MASK 0x00000040L +#define GRBMH_STATUS__GE_BUSY_MASK 0x00000200L +#define GRBMH_STATUS__RLC_BUSY_MASK 0x00000400L +#define GRBMH_STATUS__WGS_BUSY_MASK 0x00000800L +#define GRBMH_STATUS__EA_LINK_BUSY_MASK 0x00001000L +#define GRBMH_STATUS__EA_BUSY_MASK 0x00002000L +#define GRBMH_STATUS__GL2C_BUSY_MASK 0x00004000L +#define GRBMH_STATUS__GL2A_BUSY_MASK 0x00008000L +#define GRBMH_STATUS__SC_BUSY_MASK 0x00020000L +#define GRBMH_STATUS__GL1A_BUSY_MASK 0x00040000L +#define GRBMH_STATUS__BCI_BUSY_MASK 0x00100000L +#define GRBMH_STATUS__SQG_BUSY_MASK 0x00800000L +#define GRBMH_STATUS__PA_BUSY_MASK 0x01000000L +#define GRBMH_STATUS__TA_BUSY_MASK 0x02000000L +#define GRBMH_STATUS__SX_BUSY_MASK 0x04000000L +#define GRBMH_STATUS__SPI_BUSY_MASK 0x08000000L +#define GRBMH_STATUS__DB_BUSY_MASK 0x40000000L +#define GRBMH_STATUS__CB_BUSY_MASK 0x80000000L +//GRBMH_FGCG0_TARG +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG0_CHICK_BIT__SHIFT 0x0 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG1_CHICK_BIT__SHIFT 0x1 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG2_CHICK_BIT__SHIFT 0x2 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG3_CHICK_BIT__SHIFT 0x3 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG4_CHICK_BIT__SHIFT 0x4 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG5_CHICK_BIT__SHIFT 0x5 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG6_CHICK_BIT__SHIFT 0x6 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG7_CHICK_BIT__SHIFT 0x7 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG8_CHICK_BIT__SHIFT 0x8 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG9_CHICK_BIT__SHIFT 0x9 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG10_CHICK_BIT__SHIFT 0xa +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG11_CHICK_BIT__SHIFT 0xb +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG12_CHICK_BIT__SHIFT 0xc +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG13_CHICK_BIT__SHIFT 0xd +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG14_CHICK_BIT__SHIFT 0xe +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG15_CHICK_BIT__SHIFT 0xf +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG16_CHICK_BIT__SHIFT 0x10 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG17_CHICK_BIT__SHIFT 0x11 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG18_CHICK_BIT__SHIFT 0x12 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG19_CHICK_BIT__SHIFT 0x13 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG20_CHICK_BIT__SHIFT 0x14 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG21_CHICK_BIT__SHIFT 0x15 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG22_CHICK_BIT__SHIFT 0x16 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG23_CHICK_BIT__SHIFT 0x17 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG24_CHICK_BIT__SHIFT 0x18 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG25_CHICK_BIT__SHIFT 0x19 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG26_CHICK_BIT__SHIFT 0x1a +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG27_CHICK_BIT__SHIFT 0x1b +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG28_CHICK_BIT__SHIFT 0x1c +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG29_CHICK_BIT__SHIFT 0x1d +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG30_CHICK_BIT__SHIFT 0x1e +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG31_CHICK_BIT__SHIFT 0x1f +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG0_CHICK_BIT_MASK 0x00000001L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG1_CHICK_BIT_MASK 0x00000002L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG2_CHICK_BIT_MASK 0x00000004L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG3_CHICK_BIT_MASK 0x00000008L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG4_CHICK_BIT_MASK 0x00000010L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG5_CHICK_BIT_MASK 0x00000020L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG6_CHICK_BIT_MASK 0x00000040L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG7_CHICK_BIT_MASK 0x00000080L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG8_CHICK_BIT_MASK 0x00000100L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG9_CHICK_BIT_MASK 0x00000200L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG10_CHICK_BIT_MASK 0x00000400L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG11_CHICK_BIT_MASK 0x00000800L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG12_CHICK_BIT_MASK 0x00001000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG13_CHICK_BIT_MASK 0x00002000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG14_CHICK_BIT_MASK 0x00004000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG15_CHICK_BIT_MASK 0x00008000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG16_CHICK_BIT_MASK 0x00010000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG17_CHICK_BIT_MASK 0x00020000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG18_CHICK_BIT_MASK 0x00040000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG19_CHICK_BIT_MASK 0x00080000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG20_CHICK_BIT_MASK 0x00100000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG21_CHICK_BIT_MASK 0x00200000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG22_CHICK_BIT_MASK 0x00400000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG23_CHICK_BIT_MASK 0x00800000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG24_CHICK_BIT_MASK 0x01000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG25_CHICK_BIT_MASK 0x02000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG26_CHICK_BIT_MASK 0x04000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG27_CHICK_BIT_MASK 0x08000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG28_CHICK_BIT_MASK 0x10000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG29_CHICK_BIT_MASK 0x20000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG30_CHICK_BIT_MASK 0x40000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG31_CHICK_BIT_MASK 0x80000000L +//GRBMH_SOFT_RESET +#define GRBMH_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x0 +#define GRBMH_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x1 +#define GRBMH_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x2 +#define GRBMH_SOFT_RESET__SOFT_RESET_WGS__SHIFT 0x4 +#define GRBMH_SOFT_RESET__SOFT_RESET_RLCSE__SHIFT 0x5 +#define GRBMH_SOFT_RESET__SOFT_RESET_WGPCAC__SHIFT 0x6 +#define GRBMH_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x7 +#define GRBMH_SOFT_RESET__SOFT_RESET_TA__SHIFT 0x9 +#define GRBMH_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00000001L +#define GRBMH_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000002L +#define GRBMH_SOFT_RESET__SOFT_RESET_EA_MASK 0x00000004L +#define GRBMH_SOFT_RESET__SOFT_RESET_WGS_MASK 0x00000010L +#define GRBMH_SOFT_RESET__SOFT_RESET_RLCSE_MASK 0x00000020L +#define GRBMH_SOFT_RESET__SOFT_RESET_WGPCAC_MASK 0x00000040L +#define GRBMH_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00000080L +#define GRBMH_SOFT_RESET__SOFT_RESET_TA_MASK 0x00000200L +//GRBMH_READ_ERROR +#define GRBMH_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBMH_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBMH_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBMH_READ_ERROR__READ_REQUESTER_RLC__SHIFT 0x1b +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_GFX_PIPE0__SHIFT 0x1c +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_NBP_PIPE__SHIFT 0x1e +#define GRBMH_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBMH_READ_ERROR__READ_ADDRESS_MASK 0x000FFFFCL +#define GRBMH_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBMH_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBMH_READ_ERROR__READ_REQUESTER_RLC_MASK 0x08000000L +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_GFX_PIPE0_MASK 0x10000000L +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_NBP_PIPE_MASK 0x40000000L +#define GRBMH_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBMH_GFX_CLKEN_CNTL +#define GRBMH_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBMH_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBMH_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBMH_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBMH_FGCG2_MISC +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SPI_CHICK_BIT__SHIFT 0x0 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SQG_CHICK_BIT__SHIFT 0x1 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGS_CHICK_BIT__SHIFT 0x2 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_GESE_CHICK_BIT__SHIFT 0x3 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP0_CHICK_BIT__SHIFT 0x4 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP1_CHICK_BIT__SHIFT 0x5 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS0_CHICK_BIT__SHIFT 0x6 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS1_CHICK_BIT__SHIFT 0x7 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP4_CHICK_BIT__SHIFT 0x8 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP5_CHICK_BIT__SHIFT 0x9 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP6_CHICK_BIT__SHIFT 0xa +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP7_CHICK_BIT__SHIFT 0xb +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB0_CHICK_BIT__SHIFT 0xc +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB1_CHICK_BIT__SHIFT 0xd +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB2_CHICK_BIT__SHIFT 0xe +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB3_CHICK_BIT__SHIFT 0xf +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB4_CHICK_BIT__SHIFT 0x10 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB5_CHICK_BIT__SHIFT 0x11 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB6_CHICK_BIT__SHIFT 0x12 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB7_CHICK_BIT__SHIFT 0x13 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP8_CHICK_BIT__SHIFT 0x14 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SPI_CHICK_BIT_MASK 0x00000001L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SQG_CHICK_BIT_MASK 0x00000002L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGS_CHICK_BIT_MASK 0x00000004L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_GESE_CHICK_BIT_MASK 0x00000008L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP0_CHICK_BIT_MASK 0x00000010L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP1_CHICK_BIT_MASK 0x00000020L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS0_CHICK_BIT_MASK 0x00000040L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS1_CHICK_BIT_MASK 0x00000080L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP4_CHICK_BIT_MASK 0x00000100L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP5_CHICK_BIT_MASK 0x00000200L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP6_CHICK_BIT_MASK 0x00000400L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP7_CHICK_BIT_MASK 0x00000800L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB0_CHICK_BIT_MASK 0x00001000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB1_CHICK_BIT_MASK 0x00002000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB2_CHICK_BIT_MASK 0x00004000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB3_CHICK_BIT_MASK 0x00008000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB4_CHICK_BIT_MASK 0x00010000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB5_CHICK_BIT_MASK 0x00020000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB6_CHICK_BIT_MASK 0x00040000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB7_CHICK_BIT_MASK 0x00080000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP8_CHICK_BIT_MASK 0x00100000L +//GRBMH_FGCG1_TARGVF +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF0_CHICK_BIT__SHIFT 0x0 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF1_CHICK_BIT__SHIFT 0x1 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF2_CHICK_BIT__SHIFT 0x2 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF3_CHICK_BIT__SHIFT 0x3 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF4_CHICK_BIT__SHIFT 0x4 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF5_CHICK_BIT__SHIFT 0x5 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF6_CHICK_BIT__SHIFT 0x6 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF7_CHICK_BIT__SHIFT 0x7 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF8_CHICK_BIT__SHIFT 0x8 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF9_CHICK_BIT__SHIFT 0x9 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF10_CHICK_BIT__SHIFT 0xa +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF11_CHICK_BIT__SHIFT 0xb +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF12_CHICK_BIT__SHIFT 0xc +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF13_CHICK_BIT__SHIFT 0xd +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF14_CHICK_BIT__SHIFT 0xe +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF15_CHICK_BIT__SHIFT 0xf +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF16_CHICK_BIT__SHIFT 0x10 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF17_CHICK_BIT__SHIFT 0x11 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF18_CHICK_BIT__SHIFT 0x12 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF19_CHICK_BIT__SHIFT 0x13 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF20_CHICK_BIT__SHIFT 0x14 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF21_CHICK_BIT__SHIFT 0x15 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF22_CHICK_BIT__SHIFT 0x16 +#define GRBMH_FGCG1_TARGVF__AID_READ_ERROR_CHICK_BIT__SHIFT 0x17 +#define GRBMH_FGCG1_TARGVF__SE_STRAP_MATCH_ENABLE_CHICK_BIT__SHIFT 0x18 +#define GRBMH_FGCG1_TARGVF__GRBMH_RLCSE_reg_clken_CHICK_BIT__SHIFT 0x19 +#define GRBMH_FGCG1_TARGVF__GRBM_GRBMH_reg_clken_CHICK_BIT__SHIFT 0x1a +#define GRBMH_FGCG1_TARGVF__AID_FGCG_CHICK_BIT__SHIFT 0x1b +#define GRBMH_FGCG1_TARGVF__GRBMH_GRBM_fgcg_CHICK_BIT__SHIFT 0x1c +#define GRBMH_FGCG1_TARGVF__GRBMH_SPI_reg_clken_CHICK_BIT__SHIFT 0x1d +#define GRBMH_FGCG1_TARGVF__GRBM_WGS_reg_clken_CHICK_BIT__SHIFT 0x1e +#define GRBMH_FGCG1_TARGVF__GRBMH_ALWAYSON_reg_clken_CHICK_BIT__SHIFT 0x1f +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF0_CHICK_BIT_MASK 0x00000001L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF1_CHICK_BIT_MASK 0x00000002L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF2_CHICK_BIT_MASK 0x00000004L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF3_CHICK_BIT_MASK 0x00000008L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF4_CHICK_BIT_MASK 0x00000010L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF5_CHICK_BIT_MASK 0x00000020L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF6_CHICK_BIT_MASK 0x00000040L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF7_CHICK_BIT_MASK 0x00000080L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF8_CHICK_BIT_MASK 0x00000100L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF9_CHICK_BIT_MASK 0x00000200L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF10_CHICK_BIT_MASK 0x00000400L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF11_CHICK_BIT_MASK 0x00000800L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF12_CHICK_BIT_MASK 0x00001000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF13_CHICK_BIT_MASK 0x00002000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF14_CHICK_BIT_MASK 0x00004000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF15_CHICK_BIT_MASK 0x00008000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF16_CHICK_BIT_MASK 0x00010000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF17_CHICK_BIT_MASK 0x00020000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF18_CHICK_BIT_MASK 0x00040000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF19_CHICK_BIT_MASK 0x00080000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF20_CHICK_BIT_MASK 0x00100000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF21_CHICK_BIT_MASK 0x00200000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF22_CHICK_BIT_MASK 0x00400000L +#define GRBMH_FGCG1_TARGVF__AID_READ_ERROR_CHICK_BIT_MASK 0x00800000L +#define GRBMH_FGCG1_TARGVF__SE_STRAP_MATCH_ENABLE_CHICK_BIT_MASK 0x01000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_RLCSE_reg_clken_CHICK_BIT_MASK 0x02000000L +#define GRBMH_FGCG1_TARGVF__GRBM_GRBMH_reg_clken_CHICK_BIT_MASK 0x04000000L +#define GRBMH_FGCG1_TARGVF__AID_FGCG_CHICK_BIT_MASK 0x08000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_GRBM_fgcg_CHICK_BIT_MASK 0x10000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_SPI_reg_clken_CHICK_BIT_MASK 0x20000000L +#define GRBMH_FGCG1_TARGVF__GRBM_WGS_reg_clken_CHICK_BIT_MASK 0x40000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_ALWAYSON_reg_clken_CHICK_BIT_MASK 0x80000000L +//GRBMH_NOWHERE +#define GRBMH_NOWHERE__DATA__SHIFT 0x0 +#define GRBMH_NOWHERE__DATA_MASK 0xFFFFFFFFL +//GRBMH_INVALID_PIPE +#define GRBMH_INVALID_PIPE__ADDR__SHIFT 0x2 +#define GRBMH_INVALID_PIPE__PIPEID__SHIFT 0x14 +#define GRBMH_INVALID_PIPE__MEID__SHIFT 0x16 +#define GRBMH_INVALID_PIPE__QUEUEID__SHIFT 0x18 +#define GRBMH_INVALID_PIPE__SSRCID__SHIFT 0x1b +#define GRBMH_INVALID_PIPE__INVALID_PIPE__SHIFT 0x1f +#define GRBMH_INVALID_PIPE__ADDR_MASK 0x000FFFFCL +#define GRBMH_INVALID_PIPE__PIPEID_MASK 0x00300000L +#define GRBMH_INVALID_PIPE__MEID_MASK 0x00C00000L +#define GRBMH_INVALID_PIPE__QUEUEID_MASK 0x07000000L +#define GRBMH_INVALID_PIPE__SSRCID_MASK 0x78000000L +#define GRBMH_INVALID_PIPE__INVALID_PIPE_MASK 0x80000000L +//GRBMH_SYNC +#define GRBMH_SYNC__GFX_PIPE0_PERFMON_SYNC__SHIFT 0x0 +#define GRBMH_SYNC__GFX_PIPE0_SYNC__SHIFT 0x10 +#define GRBMH_SYNC__GFX_SYNC_SET_CLR__SHIFT 0x1f +#define GRBMH_SYNC__GFX_PIPE0_PERFMON_SYNC_MASK 0x00000001L +#define GRBMH_SYNC__GFX_PIPE0_SYNC_MASK 0x00010000L +#define GRBMH_SYNC__GFX_SYNC_SET_CLR_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_padec +//GE_RATE_CNTL_1 +#define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT__SHIFT 0x0 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT__SHIFT 0x4 +#define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT__SHIFT 0x8 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT__SHIFT 0xc +#define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT__SHIFT 0x10 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT__SHIFT 0x14 +#define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM__SHIFT 0x18 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM__SHIFT 0x1c +#define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT_MASK 0x0000000FL +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT_MASK 0x000000F0L +#define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT_MASK 0x00000F00L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT_MASK 0x0000F000L +#define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT_MASK 0x000F0000L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT_MASK 0x00F00000L +#define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM_MASK 0x0F000000L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM_MASK 0xF0000000L +//GE_RATE_CNTL_2 +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS__SHIFT 0x10 +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES__SHIFT 0x14 +#define GE_RATE_CNTL_2__MERGED_HS_GS_MODE__SHIFT 0x18 +#define GE_RATE_CNTL_2__MERGED_LS_ES_MODE__SHIFT 0x19 +#define GE_RATE_CNTL_2__ENABLE_RATE_CNTL__SHIFT 0x1a +#define GE_RATE_CNTL_2__SWAP_PRIORITY__SHIFT 0x1b +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS_MASK 0x000F0000L +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES_MASK 0x00F00000L +#define GE_RATE_CNTL_2__MERGED_HS_GS_MODE_MASK 0x01000000L +#define GE_RATE_CNTL_2__MERGED_LS_ES_MODE_MASK 0x02000000L +#define GE_RATE_CNTL_2__ENABLE_RATE_CNTL_MASK 0x04000000L +#define GE_RATE_CNTL_2__SWAP_PRIORITY_MASK 0x08000000L +//CC_GC_SHADER_ARRAY_CONFIG +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L +//GE_SE_CNTL_STATUS +#define GE_SE_CNTL_STATUS__TE_BUSY__SHIFT 0x0 +#define GE_SE_CNTL_STATUS__NGG_BUSY__SHIFT 0x1 +#define GE_SE_CNTL_STATUS__HS_BUSY__SHIFT 0x2 +#define GE_SE_CNTL_STATUS__TE_BUSY_MASK 0x00000001L +#define GE_SE_CNTL_STATUS__NGG_BUSY_MASK 0x00000002L +#define GE_SE_CNTL_STATUS__HS_BUSY_MASK 0x00000004L +//GE_SPI_IF_SAFE_REG +#define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA__SHIFT 0x0 +#define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA__SHIFT 0x6 +#define GE_SPI_IF_SAFE_REG__GE_SPI_GRP__SHIFT 0xc +#define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA_MASK 0x0000003FL +#define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA_MASK 0x00000FC0L +#define GE_SPI_IF_SAFE_REG__GE_SPI_GRP_MASK 0x0003F000L +//GE_PA_IF_SAFE_REG +#define GE_PA_IF_SAFE_REG__GE_PA_CSB__SHIFT 0x0 +#define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT 0xa +#define GE_PA_IF_SAFE_REG__GE_PA_CSB_MASK 0x000003FFL +#define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD_MASK 0x000FFC00L +//PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000003FL +//PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +//PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x12 +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x13 +#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x14 +#define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE__SHIFT 0x15 +#define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL__SHIFT 0x16 +#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT 0x17 +#define PA_CL_ENHANCE__PA_W_GL1X_SRC_CLK_OVERRIDE__SHIFT 0x18 +#define PA_CL_ENHANCE__PA_W_GL1X_REQ_CLK_OVERRIDE__SHIFT 0x19 +#define PA_CL_ENHANCE__PA_R_GL1X_REQ_CLK_OVERRIDE__SHIFT 0x1a +#define PA_CL_ENHANCE__PAF_GEWD_CSB_CLK_OVERRIDE__SHIFT 0x1b +#define PA_CL_ENHANCE__BROADCAST_PMODE_PRIMS__SHIFT 0x1c +#define PA_CL_ENHANCE__BROADCAST_PERP_ENDCAP_PRIMS__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00040000L +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00080000L +#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00100000L +#define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE_MASK 0x00200000L +#define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL_MASK 0x00400000L +#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK 0x00800000L +#define PA_CL_ENHANCE__PA_W_GL1X_SRC_CLK_OVERRIDE_MASK 0x01000000L +#define PA_CL_ENHANCE__PA_W_GL1X_REQ_CLK_OVERRIDE_MASK 0x02000000L +#define PA_CL_ENHANCE__PA_R_GL1X_REQ_CLK_OVERRIDE_MASK 0x04000000L +#define PA_CL_ENHANCE__PAF_GEWD_CSB_CLK_OVERRIDE_MASK 0x08000000L +#define PA_CL_ENHANCE__BROADCAST_PMODE_PRIMS_MASK 0x10000000L +#define PA_CL_ENHANCE__BROADCAST_PERP_ENDCAP_PRIMS_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +//PA_CL_RESET_DEBUG +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 +#define PA_CL_RESET_DEBUG__DISABLE_PAF_WR_SHUNT__SHIFT 0x1 +#define PA_CL_RESET_DEBUG__DISABLE_PAB_RD_SHUNT__SHIFT 0x2 +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L +#define PA_CL_RESET_DEBUG__DISABLE_PAF_WR_SHUNT_MASK 0x00000002L +#define PA_CL_RESET_DEBUG__DISABLE_PAB_RD_SHUNT_MASK 0x00000004L +//PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +//PA_SC_FIFO_DEPTH_CNTL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL +//PA_PH_DEBUG_CNTL +#define PA_PH_DEBUG_CNTL__PH_DEBUG_INDX__SHIFT 0x0 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS__SHIFT 0x8 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_EVENT_HISTORY_DATA__SHIFT 0x9 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xa +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xb +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_0__SHIFT 0xc +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_1__SHIFT 0x12 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_2__SHIFT 0x18 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_INDX_MASK 0x000000FFL +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS_MASK 0x00000100L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_EVENT_HISTORY_DATA_MASK 0x00000200L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000400L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000800L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_0_MASK 0x0003F000L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_1_MASK 0x00FC0000L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_2_MASK 0x3F000000L +//PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS__SHIFT 0x8 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_EVENT_HISTORY_DATA__SHIFT 0x9 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xa +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xb +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_0__SHIFT 0xc +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_1__SHIFT 0x12 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_2__SHIFT 0x18 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_BUS_FLOP_EN__SHIFT 0x1e +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x000000FFL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS_MASK 0x00000100L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_EVENT_HISTORY_DATA_MASK 0x00000200L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000400L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000800L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_0_MASK 0x0003F000L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_1_MASK 0x00FC0000L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_2_MASK 0x3F000000L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_BUS_FLOP_EN_MASK 0x40000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_sqdec +//SQ_CONFIG +#define SQ_CONFIG__ECO_SPARE__SHIFT 0x0 +#define SQ_CONFIG__DISABLE_SGPR_RD_PERSIST__SHIFT 0x7 +#define SQ_CONFIG__NEW_TRANS_ARB_SCHEME__SHIFT 0x8 +#define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP__SHIFT 0x9 +#define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT 0xa +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0xb +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS__SHIFT 0x13 +#define SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT 0x15 +#define SQ_CONFIG__DISABLE_ILLEGAL_OPCODE_DETECTION__SHIFT 0x17 +#define SQ_CONFIG__DISABLE_ILLEGAL_TO_NOP_DETECTION__SHIFT 0x18 +#define SQ_CONFIG__DISABLE_ILLEGAL_EXPORT_DETECTION__SHIFT 0x19 +#define SQ_CONFIG__DISABLE_ILLEGAL_CLAUSE_DETECTION__SHIFT 0x1a +#define SQ_CONFIG__DISABLE_END_CLAUSE_TX__SHIFT 0x1b +#define SQ_CONFIG__DISABLE_DIFF_WAVE_VALU_COISSUE__SHIFT 0x1c +#define SQ_CONFIG__DISABLE_IHP_STALL__SHIFT 0x1d +#define SQ_CONFIG__DISABLE_SP_SINGLE_ISSUE_WAVE64_TRANS__SHIFT 0x1e +#define SQ_CONFIG__DISABLE_ISC_PREFETCH_LIMITER__SHIFT 0x1f +#define SQ_CONFIG__ECO_SPARE_MASK 0x0000007FL +#define SQ_CONFIG__DISABLE_SGPR_RD_PERSIST_MASK 0x00000080L +#define SQ_CONFIG__NEW_TRANS_ARB_SCHEME_MASK 0x00000100L +#define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP_MASK 0x00000200L +#define SQ_CONFIG__DISABLE_SGPR_RD_KILL_MASK 0x00000400L +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0003F800L +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS_MASK 0x00040000L +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS_MASK 0x00180000L +#define SQ_CONFIG__WCLK_HYSTERESIS_CNT_MASK 0x00600000L +#define SQ_CONFIG__DISABLE_ILLEGAL_OPCODE_DETECTION_MASK 0x00800000L +#define SQ_CONFIG__DISABLE_ILLEGAL_TO_NOP_DETECTION_MASK 0x01000000L +#define SQ_CONFIG__DISABLE_ILLEGAL_EXPORT_DETECTION_MASK 0x02000000L +#define SQ_CONFIG__DISABLE_ILLEGAL_CLAUSE_DETECTION_MASK 0x04000000L +#define SQ_CONFIG__DISABLE_END_CLAUSE_TX_MASK 0x08000000L +#define SQ_CONFIG__DISABLE_DIFF_WAVE_VALU_COISSUE_MASK 0x10000000L +#define SQ_CONFIG__DISABLE_IHP_STALL_MASK 0x20000000L +#define SQ_CONFIG__DISABLE_SP_SINGLE_ISSUE_WAVE64_TRANS_MASK 0x40000000L +#define SQ_CONFIG__DISABLE_ISC_PREFETCH_LIMITER_MASK 0x80000000L +//SQC_CONFIG +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x9 +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xa +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xc +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xd +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0xe +#define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE__SHIFT 0x16 +#define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG__SHIFT 0x17 +#define SQC_CONFIG__PIT_PM_STATUS_FGCG_OVERRIDE__SHIFT 0x1a +#define SQC_CONFIG__EXEC_POP_CNT_25PCT__SHIFT 0x1b +#define SQC_CONFIG__SQC_SQ_INV_REG_GCR_SEL__SHIFT 0x1c +#define SQC_CONFIG__SPARE__SHIFT 0x1d +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000200L +#define SQC_CONFIG__EVICT_LRU_MASK 0x00000C00L +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00001000L +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00002000L +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x003FC000L +#define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE_MASK 0x00400000L +#define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG_MASK 0x03800000L +#define SQC_CONFIG__PIT_PM_STATUS_FGCG_OVERRIDE_MASK 0x04000000L +#define SQC_CONFIG__EXEC_POP_CNT_25PCT_MASK 0x08000000L +#define SQC_CONFIG__SQC_SQ_INV_REG_GCR_SEL_MASK 0x10000000L +#define SQC_CONFIG__SPARE_MASK 0xE0000000L +//SQ_RANDOM_WAVE_PRI +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT 0x1f +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L +#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK 0x80000000L +//SQG_STATUS +#define SQG_STATUS__REG_BUSY__SHIFT 0x0 +#define SQG_STATUS__POWEROFF_RESTORE__SHIFT 0x1 +#define SQG_STATUS__REG_BUSY_MASK 0x00000001L +#define SQG_STATUS__POWEROFF_RESTORE_MASK 0x00000002L +//SQ_FIFO_SIZES +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED__SHIFT 0xc +#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe +#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT__SHIFT 0x14 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L +#define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED_MASK 0x00003000L +#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L +#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L +#define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT_MASK 0x00300000L +//SQ_DSM_CNTL +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQ_DSM_CNTL2 +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe +#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L +#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L +//SQ_PIT_WEIGHT +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP0__SHIFT 0x0 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP1__SHIFT 0x3 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP2__SHIFT 0x6 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP3__SHIFT 0x9 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP4__SHIFT 0xc +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP5__SHIFT 0xf +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP6__SHIFT 0x12 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP7__SHIFT 0x15 +#define SQ_PIT_WEIGHT__UNUSED__SHIFT 0x18 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP0_MASK 0x00000007L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP1_MASK 0x00000038L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP2_MASK 0x000001C0L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP3_MASK 0x00000E00L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP4_MASK 0x00007000L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP5_MASK 0x00038000L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP6_MASK 0x001C0000L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP7_MASK 0x00E00000L +#define SQ_PIT_WEIGHT__UNUSED_MASK 0xFF000000L +//SQG_THREAD_TRACE_CONFIG +#define SQG_THREAD_TRACE_CONFIG__ALL_VMID__SHIFT 0x0 +#define SQG_THREAD_TRACE_CONFIG__ALL_VMID_MASK 0x00000001L +//SP_CONFIG +#define SP_CONFIG__ECO_SPARE__SHIFT 0x0 +#define SP_CONFIG__MGCG_SYNC_PULSE__SHIFT 0x1 +#define SP_CONFIG__DISABLE_MGCG_OVERSHOOT_MITIGATION__SHIFT 0x2 +#define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3 +#define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x4 +#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT 0x5 +#define SP_CONFIG__DISABLE_XDL_COEXEC__SHIFT 0x6 +#define SP_CONFIG__ECO_SPARE_2__SHIFT 0x7 +#define SP_CONFIG__ECO_SPARE_MASK 0x00000001L +#define SP_CONFIG__MGCG_SYNC_PULSE_MASK 0x00000002L +#define SP_CONFIG__DISABLE_MGCG_OVERSHOOT_MITIGATION_MASK 0x00000004L +#define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L +#define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000010L +#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK 0x00000020L +#define SP_CONFIG__DISABLE_XDL_COEXEC_MASK 0x00000040L +#define SP_CONFIG__ECO_SPARE_2_MASK 0x00000380L +//SQ_ARB_CONFIG +#define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0 +#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4 +#define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L +#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L +//SQ_DYN_VGPR +#define SQ_DYN_VGPR__WAVE_LIMIT__SHIFT 0x0 +#define SQ_DYN_VGPR__FWD_PROGRESS__SHIFT 0x4 +#define SQ_DYN_VGPR__MAX_BLOCK_ALLOC__SHIFT 0x5 +#define SQ_DYN_VGPR__BLOCK_SIZE__SHIFT 0x8 +#define SQ_DYN_VGPR__WAVE_LIMIT_MASK 0x0000000FL +#define SQ_DYN_VGPR__FWD_PROGRESS_MASK 0x00000010L +#define SQ_DYN_VGPR__MAX_BLOCK_ALLOC_MASK 0x000000E0L +#define SQ_DYN_VGPR__BLOCK_SIZE_MASK 0x00000100L +//SQ_SHADER_CYCLES_LO +#define SQ_SHADER_CYCLES_LO__CYCLES_LO__SHIFT 0x0 +#define SQ_SHADER_CYCLES_LO__CYCLES_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_CYCLES_HI +#define SQ_SHADER_CYCLES_HI__CYCLES_HI__SHIFT 0x0 +#define SQ_SHADER_CYCLES_HI__CYCLES_HI_MASK 0x0FFFFFFFL +//SQ_DEBUG_HOST_TRAP_STATUS +#define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT__SHIFT 0x0 +#define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT_MASK 0x0000007FL +//SQG_GL1X_CTRL +#define SQG_GL1X_CTRL__TEMPORAL__SHIFT 0x0 +#define SQG_GL1X_CTRL__SCOPE__SHIFT 0x4 +#define SQG_GL1X_CTRL__TEMPORAL_MASK 0x00000007L +#define SQG_GL1X_CTRL__SCOPE_MASK 0x00000030L +//SQG_GL1X_STATUS +#define SQG_GL1X_STATUS__ACK_ERR_DETECTED__SHIFT 0x0 +#define SQG_GL1X_STATUS__XNACK_ERR_DETECTED__SHIFT 0x1 +#define SQG_GL1X_STATUS__ACK_ERR_DETECTED_MASK 0x00000001L +#define SQG_GL1X_STATUS__XNACK_ERR_DETECTED_MASK 0x00000002L +//SQG_CONFIG +#define SQG_CONFIG__SQG_ICPFT_EN__SHIFT 0x0 +#define SQG_CONFIG__SQG_ICPFT_CLR__SHIFT 0x1 +#define SQG_CONFIG__XNACK_INTR_MASK__SHIFT 0x10 +#define SQG_CONFIG__SQG_ICPFT_EN_MASK 0x00000001L +#define SQG_CONFIG__SQG_ICPFT_CLR_MASK 0x00000002L +#define SQG_CONFIG__XNACK_INTR_MASK_MASK 0xFFFF0000L +//SQ_PERF_SNAPSHOT_CTRL +#define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT 0x1 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT 0x11 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL__SHIFT 0x12 +#define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE__SHIFT 0x16 +#define SQ_PERF_SNAPSHOT_CTRL__RANDOM_SEED__SHIFT 0x17 +#define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF_MASK 0x00000001L +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK 0x0001FFFEL +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK 0x00020000L +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL_MASK 0x003C0000L +#define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE_MASK 0x00400000L +#define SQ_PERF_SNAPSHOT_CTRL__RANDOM_SEED_MASK 0x07800000L +//CC_GC_SHADER_RATE_CONFIG_1 +#define CC_GC_SHADER_RATE_CONFIG_1__SHADER_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG_1__SHADER_RATE_MASK 0x000007FEL +//SQ_INTERRUPT_AUTO_MASK +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL +//SQ_INTERRUPT_MSG_CTRL +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L +//SQ_WATCH0_ADDR_H +#define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH0_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH0_ADDR_L +#define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH0_CNTL +#define SQ_WATCH0_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH0_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH1_ADDR_H +#define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH1_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH1_ADDR_L +#define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH1_CNTL +#define SQ_WATCH1_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH1_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH2_ADDR_H +#define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH2_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH2_ADDR_L +#define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH2_CNTL +#define SQ_WATCH2_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH2_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH3_ADDR_H +#define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH3_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH3_ADDR_L +#define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH3_CNTL +#define SQ_WATCH3_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH3_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L +//SQG_UTCL0_STATUS +#define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQG_UTCL0_STATUS__RESERVED__SHIFT 0x3 +#define SQG_UTCL0_STATUS__UNUSED__SHIFT 0x8 +#define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQG_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQG_UTCL0_STATUS__RESERVED_MASK 0x000000F8L +#define SQG_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L +//SQG_UTCL0_CNTL1 +#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQG_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQG_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define SQG_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE__SHIFT 0x19 +#define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQG_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQG_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQG_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define SQG_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE_MASK 0x02000000L +#define SQG_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQG_UTCL0_CNTL2 +#define SQG_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define SQG_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 +#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQG_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQG_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQG_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define SQG_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f +#define SQG_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define SQG_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L +#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQG_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQG_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQG_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define SQG_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L +//SQG_UTCL0_RETRY +#define SQG_UTCL0_RETRY__INCR__SHIFT 0x0 +#define SQG_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define SQG_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define SQG_UTCL0_RETRY__COUNT_MASK 0x00000F00L +//SQG_VMID_FED_STATUS +#define SQG_VMID_FED_STATUS__VMID_MASK__SHIFT 0x0 +#define SQG_VMID_FED_STATUS__VMID_MASK_MASK 0x0000FFFFL +//SQG_VMID_FED_CLEAR +#define SQG_VMID_FED_CLEAR__VMID_MASK__SHIFT 0x0 +#define SQG_VMID_FED_CLEAR__VMID_MASK_MASK 0x0000FFFFL +//SQG_SE_PIT_CONTROL +#define SQG_SE_PIT_CONTROL__PIT_PM_ENABLE__SHIFT 0x0 +#define SQG_SE_PIT_CONTROL__PIT_PM_PRIMING_COOLDOWN__SHIFT 0x1 +#define SQG_SE_PIT_CONTROL__PIT_PM_STATUS_AVG_LENGTH__SHIFT 0x6 +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_THRESHOLD__SHIFT 0x8 +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_CYCLES__SHIFT 0xc +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_THRESHOLD__SHIFT 0x12 +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_CYCLES__SHIFT 0x16 +#define SQG_SE_PIT_CONTROL__PIT_PM_ENABLE_MASK 0x00000001L +#define SQG_SE_PIT_CONTROL__PIT_PM_PRIMING_COOLDOWN_MASK 0x00000006L +#define SQG_SE_PIT_CONTROL__PIT_PM_STATUS_AVG_LENGTH_MASK 0x000000C0L +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_THRESHOLD_MASK 0x00000F00L +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_CYCLES_MASK 0x0003F000L +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_THRESHOLD_MASK 0x003C0000L +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_CYCLES_MASK 0x0FC00000L +//SQG_UTCL0_RETRY_TIMER_THRESHOLD_HI +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE__SHIFT 0x0 +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE_MASK 0xFFFFFFFFL +//SQG_UTCL0_RETRY_TIMER_THRESHOLD_LO +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE__SHIFT 0x0 +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE_MASK 0xFFFFFFFFL +//SQG_WS_INSERTION_COUNT +#define SQG_WS_INSERTION_COUNT__COUNT__SHIFT 0x0 +#define SQG_WS_INSERTION_COUNT__COUNT_MASK 0x0000FFFFL +//SQG_WS_SPI_STATUS +#define SQG_WS_SPI_STATUS__COUNT__SHIFT 0x0 +#define SQG_WS_SPI_STATUS__WS_COUNT__SHIFT 0x10 +#define SQG_WS_SPI_STATUS__COUNT_MASK 0x0000FFFFL +#define SQG_WS_SPI_STATUS__WS_COUNT_MASK 0xFFFF0000L +//SQ_IND_INDEX +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL +#define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L +#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L +//SQ_IND_DATA +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL +//SQ_CMD +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_CMD__CMD_MASK 0x0000000FL +#define SQ_CMD__MODE_MASK 0x00000070L +#define SQ_CMD__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD__DATA_MASK 0x00000F00L +#define SQ_CMD__WAVE_ID_MASK 0x001F0000L +#define SQ_CMD__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD__VM_ID_MASK 0xF0000000L +//SQC_WSM_CONTROL +#define SQC_WSM_CONTROL__WS_GO__SHIFT 0x0 +#define SQC_WSM_CONTROL__WS_INTENSITY__SHIFT 0x1 +#define SQC_WSM_CONTROL__WS_PRIORITY_MODE__SHIFT 0x3 +#define SQC_WSM_CONTROL__WS_PERIOD__SHIFT 0x4 +#define SQC_WSM_CONTROL__WS_RATE__SHIFT 0xc +#define SQC_WSM_CONTROL__WS_PERIOD_COUNT__SHIFT 0x14 +#define SQC_WSM_CONTROL__WS_GO_MASK 0x00000001L +#define SQC_WSM_CONTROL__WS_INTENSITY_MASK 0x00000006L +#define SQC_WSM_CONTROL__WS_PRIORITY_MODE_MASK 0x00000008L +#define SQC_WSM_CONTROL__WS_PERIOD_MASK 0x00000FF0L +#define SQC_WSM_CONTROL__WS_RATE_MASK 0x000FF000L +#define SQC_WSM_CONTROL__WS_PERIOD_COUNT_MASK 0x00F00000L +//SQC_PIT_CONTROL0 +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_2__SHIFT 0x0 +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_4__SHIFT 0x3 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_2__SHIFT 0x6 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_4__SHIFT 0x9 +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_LEVEL__SHIFT 0xc +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_RATE__SHIFT 0xf +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_CYCLES__SHIFT 0x11 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_LEVEL__SHIFT 0x15 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_RATE__SHIFT 0x18 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_CYCLES__SHIFT 0x1a +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_2_MASK 0x00000007L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_4_MASK 0x00000038L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_2_MASK 0x000001C0L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_4_MASK 0x00000E00L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_LEVEL_MASK 0x00007000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_RATE_MASK 0x00018000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_CYCLES_MASK 0x001E0000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_LEVEL_MASK 0x00E00000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_RATE_MASK 0x03000000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_CYCLES_MASK 0x3C000000L +//SQC_PIT_CONTROL1 +#define SQC_PIT_CONTROL1__LOCAL_THROTTLE_EN__SHIFT 0x0 +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_2__SHIFT 0x1 +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_4__SHIFT 0x4 +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_2__SHIFT 0x7 +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_4__SHIFT 0xa +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_RATE__SHIFT 0xd +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_CYCLES__SHIFT 0xf +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_LEVEL__SHIFT 0x13 +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_RATE__SHIFT 0x16 +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_CYCLES__SHIFT 0x18 +#define SQC_PIT_CONTROL1__LOCAL_THROTTLE_EN_MASK 0x00000001L +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_2_MASK 0x0000000EL +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_4_MASK 0x00000070L +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_2_MASK 0x00000380L +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_4_MASK 0x00001C00L +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_RATE_MASK 0x00006000L +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_CYCLES_MASK 0x00078000L +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_LEVEL_MASK 0x00380000L +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_RATE_MASK 0x00C00000L +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_CYCLES_MASK 0x0F000000L +//SQC_PIT_CONTROL2 +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_WINDOW__SHIFT 0x0 +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_IDLE_THRESHOLD__SHIFT 0x2 +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_ACTIVE_THRESHOLD__SHIFT 0x8 +#define SQC_PIT_CONTROL2__PIT_PF_LEVEL__SHIFT 0xe +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES__SHIFT 0x13 +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES_MIN__SHIFT 0x17 +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_SA_STEP__SHIFT 0x1b +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_WGP_STEP__SHIFT 0x1d +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_WINDOW_MASK 0x00000003L +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_IDLE_THRESHOLD_MASK 0x000000FCL +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_ACTIVE_THRESHOLD_MASK 0x00003F00L +#define SQC_PIT_CONTROL2__PIT_PF_LEVEL_MASK 0x0007C000L +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES_MASK 0x00780000L +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES_MIN_MASK 0x07800000L +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_SA_STEP_MASK 0x18000000L +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_WGP_STEP_MASK 0x60000000L +//SQC_UTCL0_RETRY +#define SQC_UTCL0_RETRY__INCR__SHIFT 0x0 +#define SQC_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define SQC_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define SQC_UTCL0_RETRY__COUNT_MASK 0x00000F00L +//SQC_MISC_CONFIG +#define SQC_MISC_CONFIG__SQC_SQ_MGCG_OVERSHOOT_PROG_DELAY__SHIFT 0x0 +#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT 0x5 +#define SQC_MISC_CONFIG__SQ_SPI_MSG_FGCG_OVERRIDE__SHIFT 0x6 +#define SQC_MISC_CONFIG__SPI_SQ_EXPALLOC_FGCG_OVERRIDE__SHIFT 0x7 +#define SQC_MISC_CONFIG__SQC_SQ_DATA_RET_FGCG_OVERRIDE__SHIFT 0x8 +#define SQC_MISC_CONFIG__SQC_SQ_INST_RET_FGCG_OVERRIDE__SHIFT 0x9 +#define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE__SHIFT 0xa +#define SQC_MISC_CONFIG__ICLK_MGCG_DISABLE__SHIFT 0xb +#define SQC_MISC_CONFIG__ICLK_BANK_MGCG_DISABLE__SHIFT 0xc +#define SQC_MISC_CONFIG__DCLK_MGCG_DISABLE__SHIFT 0xd +#define SQC_MISC_CONFIG__GCLK_MGCG_DISABLE__SHIFT 0xe +#define SQC_MISC_CONFIG__MCLK_MGCG_DISABLE__SHIFT 0xf +#define SQC_MISC_CONFIG__PCLK_MGCG_DISABLE__SHIFT 0x10 +#define SQC_MISC_CONFIG__BCLK_MGCG_DISABLE__SHIFT 0x11 +#define SQC_MISC_CONFIG__SQC_TA_RESET_FGCG_OVERRIDE__SHIFT 0x12 +#define SQC_MISC_CONFIG__SQC_MCA_FGCG_OVERRIDE__SHIFT 0x13 +#define SQC_MISC_CONFIG__DCLK_BANK_MGCG_DISABLE__SHIFT 0x14 +#define SQC_MISC_CONFIG__SQC_SQ_BARRIER_DONE_FGCG_OVERRIDE__SHIFT 0x15 +#define SQC_MISC_CONFIG__SQC_SQ_MSGDONE_FGCG_OVERRIDE__SHIFT 0x16 +#define SQC_MISC_CONFIG__CMCLK_MGCG_DISABLE__SHIFT 0x17 +#define SQC_MISC_CONFIG__SQC_GL1_CLKEN_OVERRIDE__SHIFT 0x18 +#define SQC_MISC_CONFIG__SQC_CORE_OVERRIDE__SHIFT 0x19 +#define SQC_MISC_CONFIG__ICLK_HMF_BS_MGCG_DISABLE__SHIFT 0x1a +#define SQC_MISC_CONFIG__ICLK_CC_MGCG_DISABLE__SHIFT 0x1b +#define SQC_MISC_CONFIG__DCLK_HMF_BS_MGCG_DISABLE__SHIFT 0x1c +#define SQC_MISC_CONFIG__DCLK_CC_MGCG_DISABLE__SHIFT 0x1d +#define SQC_MISC_CONFIG__SQC_SQ_INVALIDATE_FGCG_DISABLE__SHIFT 0x1e +#define SQC_MISC_CONFIG__SQC_UTCL0_FGCG_OVERRIDE__SHIFT 0x1f +#define SQC_MISC_CONFIG__SQC_SQ_MGCG_OVERSHOOT_PROG_DELAY_MASK 0x0000001FL +#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L +#define SQC_MISC_CONFIG__SQ_SPI_MSG_FGCG_OVERRIDE_MASK 0x00000040L +#define SQC_MISC_CONFIG__SPI_SQ_EXPALLOC_FGCG_OVERRIDE_MASK 0x00000080L +#define SQC_MISC_CONFIG__SQC_SQ_DATA_RET_FGCG_OVERRIDE_MASK 0x00000100L +#define SQC_MISC_CONFIG__SQC_SQ_INST_RET_FGCG_OVERRIDE_MASK 0x00000200L +#define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE_MASK 0x00000400L +#define SQC_MISC_CONFIG__ICLK_MGCG_DISABLE_MASK 0x00000800L +#define SQC_MISC_CONFIG__ICLK_BANK_MGCG_DISABLE_MASK 0x00001000L +#define SQC_MISC_CONFIG__DCLK_MGCG_DISABLE_MASK 0x00002000L +#define SQC_MISC_CONFIG__GCLK_MGCG_DISABLE_MASK 0x00004000L +#define SQC_MISC_CONFIG__MCLK_MGCG_DISABLE_MASK 0x00008000L +#define SQC_MISC_CONFIG__PCLK_MGCG_DISABLE_MASK 0x00010000L +#define SQC_MISC_CONFIG__BCLK_MGCG_DISABLE_MASK 0x00020000L +#define SQC_MISC_CONFIG__SQC_TA_RESET_FGCG_OVERRIDE_MASK 0x00040000L +#define SQC_MISC_CONFIG__SQC_MCA_FGCG_OVERRIDE_MASK 0x00080000L +#define SQC_MISC_CONFIG__DCLK_BANK_MGCG_DISABLE_MASK 0x00100000L +#define SQC_MISC_CONFIG__SQC_SQ_BARRIER_DONE_FGCG_OVERRIDE_MASK 0x00200000L +#define SQC_MISC_CONFIG__SQC_SQ_MSGDONE_FGCG_OVERRIDE_MASK 0x00400000L +#define SQC_MISC_CONFIG__CMCLK_MGCG_DISABLE_MASK 0x00800000L +#define SQC_MISC_CONFIG__SQC_GL1_CLKEN_OVERRIDE_MASK 0x01000000L +#define SQC_MISC_CONFIG__SQC_CORE_OVERRIDE_MASK 0x02000000L +#define SQC_MISC_CONFIG__ICLK_HMF_BS_MGCG_DISABLE_MASK 0x04000000L +#define SQC_MISC_CONFIG__ICLK_CC_MGCG_DISABLE_MASK 0x08000000L +#define SQC_MISC_CONFIG__DCLK_HMF_BS_MGCG_DISABLE_MASK 0x10000000L +#define SQC_MISC_CONFIG__DCLK_CC_MGCG_DISABLE_MASK 0x20000000L +#define SQC_MISC_CONFIG__SQC_SQ_INVALIDATE_FGCG_DISABLE_MASK 0x40000000L +#define SQC_MISC_CONFIG__SQC_UTCL0_FGCG_OVERRIDE_MASK 0x80000000L +//SQ_TIMEOUT_CONFIG +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT 0x0 +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT 0x6 +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK 0x0000003FL +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK 0x00000040L +//SQ_TIMEOUT_STATUS_SIMD01 +#define SQ_TIMEOUT_STATUS_SIMD01__WAVE_TIMEOUT__SHIFT 0x0 +#define SQ_TIMEOUT_STATUS_SIMD01__WAVE_TIMEOUT_MASK 0xFFFFFFFFL +//SQ_TIMEOUT_STATUS_SIMD23 +#define SQ_TIMEOUT_STATUS_SIMD23__WAVE_TIMEOUT__SHIFT 0x0 +#define SQ_TIMEOUT_STATUS_SIMD23__WAVE_TIMEOUT_MASK 0xFFFFFFFFL +//SQC_UTCL0_STATUS +#define SQC_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_UTCL0_STATUS__RESERVED__SHIFT 0x3 +#define SQC_UTCL0_STATUS__UNUSED__SHIFT 0x8 +#define SQC_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQC_UTCL0_STATUS__RESERVED_MASK 0x000000F8L +#define SQC_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L +//SQC_UTCL0_CNTL1 +#define SQC_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define SQC_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define SQC_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define SQC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE__SHIFT 0x19 +#define SQC_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define SQC_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define SQC_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define SQC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE_MASK 0x02000000L +#define SQC_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_UTCL0_CNTL2 +#define SQC_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define SQC_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 +#define SQC_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define SQC_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define SQC_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f +#define SQC_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L +#define SQC_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define SQC_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQC_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define SQC_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shsdec +//SX_DEBUG_BUSY +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ3__SHIFT 0x0 +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ2__SHIFT 0x1 +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ1__SHIFT 0x2 +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALID__SHIFT 0x3 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ3__SHIFT 0x4 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ2__SHIFT 0x5 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ1__SHIFT 0x6 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALID__SHIFT 0x7 +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x9 +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0xa +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0xb +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0xc +#define SX_DEBUG_BUSY__SX_SX_IN_VALID__SHIFT 0xd +#define SX_DEBUG_BUSY__SX_SX_OUT_VALID__SHIFT 0xe +#define SX_DEBUG_BUSY__RESERVED__SHIFT 0xf +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ3_MASK 0x00000001L +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ2_MASK 0x00000002L +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ1_MASK 0x00000004L +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALID_MASK 0x00000008L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ3_MASK 0x00000010L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ2_MASK 0x00000020L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ1_MASK 0x00000040L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALID_MASK 0x00000080L +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x00000200L +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x00000400L +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x00000800L +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x00001000L +#define SX_DEBUG_BUSY__SX_SX_IN_VALID_MASK 0x00002000L +#define SX_DEBUG_BUSY__SX_SX_OUT_VALID_MASK 0x00004000L +#define SX_DEBUG_BUSY__RESERVED_MASK 0xFFFF8000L +//SX_DEBUG_BUSY_2 +#define SX_DEBUG_BUSY_2__COL_SCBD0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_2__COL_DBIF3_QUAD_FREE__SHIFT 0xf +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_2__COL_DBIF2_QUAD_FREE__SHIFT 0x12 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_2__COL_DBIF1_QUAD_FREE__SHIFT 0x15 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_2__COL_DBIF0_QUAD_FREE__SHIFT 0x18 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_2__COL_SCBD0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_QUAD_FREE_MASK 0x00008000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_QUAD_FREE_MASK 0x00040000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_QUAD_FREE_MASK 0x00200000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_QUAD_FREE_MASK 0x01000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_1 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x7 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc +#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd +#define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf +#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11 +#define SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT 0x12 +#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT 0x13 +#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT 0x14 +#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT 0x16 +#define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT__SHIFT 0x17 +#define SX_DEBUG_1__DISABLE_DBIF_PIX_ENABLE_FGCG__SHIFT 0x18 +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x19 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL +#define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00000080L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L +#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L +#define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L +#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L +#define SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK 0x00040000L +#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK 0x00080000L +#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK 0x00100000L +#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK 0x00400000L +#define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT_MASK 0x00800000L +#define SX_DEBUG_1__DISABLE_DBIF_PIX_ENABLE_FGCG_MASK 0x01000000L +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFE000000L +//SX_DEBUG_BUSY_5 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK6_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK6_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_6 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK6_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_6__COL_REQ3_CREDIT_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_6__COL_REQ3_FLOP_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_6__COL_REQ2_CREDIT_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_6__COL_REQ2_FLOP_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_6__COL_REQ1_CREDIT_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_6__COL_REQ1_FLOP_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_6__COL_REQ0_CREDIT_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK6_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_6__COL_REQ3_CREDIT_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_6__COL_REQ3_FLOP_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_6__COL_REQ2_CREDIT_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_6__COL_REQ2_FLOP_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_6__COL_REQ1_CREDIT_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_6__COL_REQ1_FLOP_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_6__COL_REQ0_CREDIT_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_7 +#define SX_DEBUG_BUSY_7__COL_REQ0_FLOP_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_7__COL_SCBD1_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x2 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x3 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x4 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x5 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x6 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x7 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALID_OUT__SHIFT 0x8 +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x9 +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0xa +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ2__SHIFT 0xb +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ3__SHIFT 0xc +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ4__SHIFT 0xd +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ5__SHIFT 0xe +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALID_OUT__SHIFT 0xf +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1__SHIFT 0x10 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0x11 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ2__SHIFT 0x12 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ3__SHIFT 0x13 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ4__SHIFT 0x14 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x15 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALID_OUT__SHIFT 0x16 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x17 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x18 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x19 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x1a +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x1b +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x1c +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALID_OUT__SHIFT 0x1d +#define SX_DEBUG_BUSY_7__RESERVED__SHIFT 0x1e +#define SX_DEBUG_BUSY_7__COL_REQ0_FLOP_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_7__COL_SCBD1_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_MASK 0x00000004L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x00000008L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ2_MASK 0x00000010L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000020L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000040L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000080L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALID_OUT_MASK 0x00000100L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000200L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000400L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000800L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ3_MASK 0x00001000L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ4_MASK 0x00002000L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ5_MASK 0x00004000L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALID_OUT_MASK 0x00008000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_MASK 0x00010000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00020000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ2_MASK 0x00040000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ3_MASK 0x00080000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ4_MASK 0x00100000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ5_MASK 0x00200000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALID_OUT_MASK 0x00400000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_MASK 0x00800000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x01000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ2_MASK 0x02000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ3_MASK 0x04000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ4_MASK 0x08000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ5_MASK 0x10000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALID_OUT_MASK 0x20000000L +#define SX_DEBUG_BUSY_7__RESERVED_MASK 0xC0000000L +//SX_DEBUG_BUSY_8 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL3_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL2_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL1_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL0_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_8__POS_BANK5VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_8__POS_BANK5VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_8__POS_BANK5VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_8__POS_BANK5VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_8__POS_BANK4VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_8__POS_BANK4VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_8__POS_BANK4VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_8__POS_BANK4VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_8__POS_BANK3VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_8__POS_BANK3VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_8__POS_BANK3VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_8__POS_BANK3VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL3_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL2_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL1_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL0_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_8__POS_BANK1VAL3_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_8__POS_BANK1VAL2_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_8__POS_BANK1VAL1_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_8__POS_BANK1VAL0_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_8__POS_BANK0VAL3_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_8__POS_BANK0VAL2_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_8__POS_BANK0VAL1_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_8__POS_BANK0VAL0_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_8__POS_BANK7VAL3_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_8__POS_BANK7VAL2_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_8__POS_BANK7VAL1_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_8__POS_BANK7VAL0_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL3_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL2_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL1_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL0_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL3_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL2_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL1_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL0_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL3_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL2_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL1_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL0_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL3_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL2_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL1_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL0_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL3_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL2_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL1_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL0_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL3_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL2_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL1_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL0_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL3_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL2_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL1_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL0_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_9 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL3_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL2_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL1_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL0_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL3_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL2_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL1_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL0_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL3_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL2_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL1_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL0_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL3_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL2_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL1_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL0_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL3_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL2_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL1_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL0_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL3_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL2_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL1_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL0_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL3_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL2_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL1_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL0_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL3_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL2_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL1_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL0_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL3_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL2_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL1_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL0_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL3_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL2_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL1_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL0_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL3_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL2_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL1_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL0_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL3_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL2_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL1_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL0_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_10 +#define SX_DEBUG_BUSY_10__POS_SCBD_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_10__POS_FREE_OR_VALIDS__SHIFT 0x1 +#define SX_DEBUG_BUSY_10__POS_REQUESTER_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_10__PA_SX_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ3__SHIFT 0x4 +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ2__SHIFT 0x5 +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ1__SHIFT 0x6 +#define SX_DEBUG_BUSY_10__IDX_SCBD_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_10__IDX_FREE_OR_VALIDS__SHIFT 0x8 +#define SX_DEBUG_BUSY_10__IDX_REQUESTER_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_10__PA_SX_IDX_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ3__SHIFT 0xb +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ2__SHIFT 0xc +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ1__SHIFT 0xd +#define SX_DEBUG_BUSY_10__RESERVED__SHIFT 0xe +#define SX_DEBUG_BUSY_10__POS_SCBD_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_10__POS_FREE_OR_VALIDS_MASK 0x00000002L +#define SX_DEBUG_BUSY_10__POS_REQUESTER_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_10__PA_SX_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ3_MASK 0x00000010L +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ2_MASK 0x00000020L +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ1_MASK 0x00000040L +#define SX_DEBUG_BUSY_10__IDX_SCBD_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_10__IDX_FREE_OR_VALIDS_MASK 0x00000100L +#define SX_DEBUG_BUSY_10__IDX_REQUESTER_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_10__PA_SX_IDX_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ3_MASK 0x00000800L +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ2_MASK 0x00001000L +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ1_MASK 0x00002000L +#define SX_DEBUG_BUSY_10__RESERVED_MASK 0xFFFFC000L +//SPI_PS_MAX_WAVE_ID +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L +//SPI_SCRATCH_ADDR_STATUS +#define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED__SHIFT 0x1 +#define SPI_SCRATCH_ADDR_STATUS__ME_ID__SHIFT 0x2 +#define SPI_SCRATCH_ADDR_STATUS__PIPE_ID__SHIFT 0x4 +#define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED_MASK 0x00000002L +#define SPI_SCRATCH_ADDR_STATUS__ME_ID_MASK 0x0000000CL +#define SPI_SCRATCH_ADDR_STATUS__PIPE_ID_MASK 0x00000030L +//SPI_GFX_CNTL +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L +//SPI_DEBUG_CNTL_2 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_0__SHIFT 0x0 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_1__SHIFT 0x1 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_2__SHIFT 0x2 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_3__SHIFT 0x3 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_4__SHIFT 0x4 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_5__SHIFT 0x5 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_6__SHIFT 0x6 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_7__SHIFT 0x7 +#define SPI_DEBUG_CNTL_2__DISABLE_INTRA_PRIM_CONFLICT__SHIFT 0x8 +#define SPI_DEBUG_CNTL_2__DISABLE_PS_AGE_SORT__SHIFT 0x9 +#define SPI_DEBUG_CNTL_2__DISABLE_VSGS_AGE_SORT__SHIFT 0xa +#define SPI_DEBUG_CNTL_2__PA_CSB_DEPTH__SHIFT 0xb +#define SPI_DEBUG_CNTL_2__DISABLE_PSUD_SAME_ADDR_OPT__SHIFT 0xf +#define SPI_DEBUG_CNTL_2__SPI_S_WAVE_WR_CTL_BUSY__SHIFT 0x10 +#define SPI_DEBUG_CNTL_2__DISABLE_EARLY_COL_QUEUE_RD__SHIFT 0x11 +#define SPI_DEBUG_CNTL_2__DISABLE_EGM_SAME_ADDR_OPT__SHIFT 0x12 +#define SPI_DEBUG_CNTL_2__SPI_S_WB_WCT_BUSY__SHIFT 0x16 +#define SPI_DEBUG_CNTL_2__DISABLE_CSG_CRAWLER_ACTIVE_FGCG_OPT__SHIFT 0x17 +#define SPI_DEBUG_CNTL_2__DISABLE_CSC_CRAWLER_ACTIVE_FGCG_OPT__SHIFT 0x18 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_0_MASK 0x00000001L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_1_MASK 0x00000002L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_2_MASK 0x00000004L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_3_MASK 0x00000008L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_4_MASK 0x00000010L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_5_MASK 0x00000020L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_6_MASK 0x00000040L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_7_MASK 0x00000080L +#define SPI_DEBUG_CNTL_2__DISABLE_INTRA_PRIM_CONFLICT_MASK 0x00000100L +#define SPI_DEBUG_CNTL_2__DISABLE_PS_AGE_SORT_MASK 0x00000200L +#define SPI_DEBUG_CNTL_2__DISABLE_VSGS_AGE_SORT_MASK 0x00000400L +#define SPI_DEBUG_CNTL_2__PA_CSB_DEPTH_MASK 0x00007800L +#define SPI_DEBUG_CNTL_2__DISABLE_PSUD_SAME_ADDR_OPT_MASK 0x00008000L +#define SPI_DEBUG_CNTL_2__SPI_S_WAVE_WR_CTL_BUSY_MASK 0x00010000L +#define SPI_DEBUG_CNTL_2__DISABLE_EARLY_COL_QUEUE_RD_MASK 0x00020000L +#define SPI_DEBUG_CNTL_2__DISABLE_EGM_SAME_ADDR_OPT_MASK 0x00040000L +#define SPI_DEBUG_CNTL_2__SPI_S_WB_WCT_BUSY_MASK 0x00400000L +#define SPI_DEBUG_CNTL_2__DISABLE_CSG_CRAWLER_ACTIVE_FGCG_OPT_MASK 0x00800000L +#define SPI_DEBUG_CNTL_2__DISABLE_CSC_CRAWLER_ACTIVE_FGCG_OPT_MASK 0x01000000L +//SPI_DEBUG_CNTL_3 +#define SPI_DEBUG_CNTL_3__CSC_PUSH_CREDITS__SHIFT 0x0 +#define SPI_DEBUG_CNTL_3__CSC_POP_CREDITS__SHIFT 0x5 +#define SPI_DEBUG_CNTL_3__CSC_PUSH_CREDITS_MASK 0x0000001FL +#define SPI_DEBUG_CNTL_3__CSC_POP_CREDITS_MASK 0x000003E0L +//SPI_DEBUG_CNTL +#define SPI_DEBUG_CNTL__DEBUG_GFX_PIPE_SEL__SHIFT 0x0 +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 +#define SPI_DEBUG_CNTL__PS_PSTNT_STATE_PIPELINE_ENABLE__SHIFT 0x13 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP0_OVERRIDE__SHIFT 0x15 +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP1_OVERRIDE__SHIFT 0x16 +#define SPI_DEBUG_CNTL__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x17 +#define SPI_DEBUG_CNTL__CGTT_LEGACY_MODE__SHIFT 0x18 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 +#define SPI_DEBUG_CNTL__DEBUG_PIXEL_PIPE_SEL__SHIFT 0x1c +#define SPI_DEBUG_CNTL__BCI_PIPE_PER_STAGE_CG_OVERRIDE__SHIFT 0x1e +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f +#define SPI_DEBUG_CNTL__DEBUG_GFX_PIPE_SEL_MASK 0x00000001L +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000000EL +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003F0L +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000FC00L +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L +#define SPI_DEBUG_CNTL__PS_PSTNT_STATE_PIPELINE_ENABLE_MASK 0x00080000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP0_OVERRIDE_MASK 0x00200000L +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP1_OVERRIDE_MASK 0x00400000L +#define SPI_DEBUG_CNTL__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00800000L +#define SPI_DEBUG_CNTL__CGTT_LEGACY_MODE_MASK 0x01000000L +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0E000000L +#define SPI_DEBUG_CNTL__DEBUG_PIXEL_PIPE_SEL_MASK 0x30000000L +#define SPI_DEBUG_CNTL__BCI_PIPE_PER_STAGE_CG_OVERRIDE_MASK 0x40000000L +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L +//SPI_DEBUG_READ +#define SPI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//SPI_DSM_CNTL +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +//SPI_DSM_CNTL2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L +//SPI_EDC_CNT +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L +//SPIRA_DEBUG_READ +#define SPIRA_DEBUG_READ__DATA__SHIFT 0x0 +#define SPIRA_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//SPI_DEBUG_BUSY +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0 +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1 +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x2 +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x3 +#define SPI_DEBUG_BUSY__PS2_BUSY__SHIFT 0x4 +#define SPI_DEBUG_BUSY__PS3_BUSY__SHIFT 0x5 +#define SPI_DEBUG_BUSY__CSG0_BUSY__SHIFT 0x6 +#define SPI_DEBUG_BUSY__CSG1_BUSY__SHIFT 0x7 +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x12 +#define SPI_DEBUG_BUSY__OFC_LDS_BUSY__SHIFT 0x13 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x14 +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x15 +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x16 +#define SPI_DEBUG_BUSY__RSRC_ALLOC_BUSY__SHIFT 0x17 +#define SPI_DEBUG_BUSY__PWS_BUSY__SHIFT 0x18 +#define SPI_DEBUG_BUSY__SPP_BUSY__SHIFT 0x19 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000001L +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000002L +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000004L +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000008L +#define SPI_DEBUG_BUSY__PS2_BUSY_MASK 0x00000010L +#define SPI_DEBUG_BUSY__PS3_BUSY_MASK 0x00000020L +#define SPI_DEBUG_BUSY__CSG0_BUSY_MASK 0x00000040L +#define SPI_DEBUG_BUSY__CSG1_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00040000L +#define SPI_DEBUG_BUSY__OFC_LDS_BUSY_MASK 0x00080000L +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00100000L +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00200000L +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00400000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC_BUSY_MASK 0x00800000L +#define SPI_DEBUG_BUSY__PWS_BUSY_MASK 0x01000000L +#define SPI_DEBUG_BUSY__SPP_BUSY_MASK 0x02000000L +//SPI_CONFIG_PS_CU_EN +#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT 0x0 +#define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET__SHIFT 0x4 +#define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET__SHIFT 0x8 +#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK 0x0000000FL +#define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET_MASK 0x000000F0L +#define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET_MASK 0x00000F00L +//SPI_CONFIG_CU_MASK_GFX0 +#define SPI_CONFIG_CU_MASK_GFX0__HS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_GFX0__GS_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_GFX0__HS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_GFX0__GS_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_HP3D0 +#define SPI_CONFIG_CU_MASK_HP3D0__HS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_HP3D0__GS_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_HP3D0__HS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_HP3D0__GS_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_GFX1 +#define SPI_CONFIG_CU_MASK_GFX1__PS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_GFX1__CSG_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_GFX1__PS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_GFX1__CSG_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_HP3D1 +#define SPI_CONFIG_CU_MASK_HP3D1__PS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_HP3D1__CSG_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_HP3D1__PS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_HP3D1__CSG_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS0 +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS1 +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS2 +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS3 +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS4 +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS5 +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS6 +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS7 +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_WF_LIFETIME_CNTL +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L +//SPI_WF_LIFETIME_LIMIT_0 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_2 +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_3 +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_4 +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_5 +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_0 +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_2 +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_4 +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_6 +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_7 +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_9 +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_11 +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_13 +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_14 +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_15 +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_16 +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_17 +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_18 +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_19 +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_20 +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_DEBUG +#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f +#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_21 +#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK 0x80000000L +//SPI_WGP_WORK_PENDING +#define SPI_WGP_WORK_PENDING__SPI_WGP_WORK_PENDING__SHIFT 0x0 +#define SPI_WGP_WORK_PENDING__SA0_WGP8_WORK_PENDING__SHIFT 0x10 +#define SPI_WGP_WORK_PENDING__RESERVED__SHIFT 0x11 +#define SPI_WGP_WORK_PENDING__SPI_WGP_WORK_PENDING_MASK 0x0000FFFFL +#define SPI_WGP_WORK_PENDING__SA0_WGP8_WORK_PENDING_MASK 0x00010000L +#define SPI_WGP_WORK_PENDING__RESERVED_MASK 0xFFFE0000L +//SPI_CREST_MODE +#define SPI_CREST_MODE__ENABLE_CREST__SHIFT 0x0 +#define SPI_CREST_MODE__ENABLE_CREST_MASK 0x00000001L +//SPI_SLAVE_DEBUG_BUSY +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x4 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x5 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x6 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x7 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER_BUSY__SHIFT 0x8 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WR_WCTL_BUSY__SHIFT 0x9 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0xa +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0xb +#define SPI_SLAVE_DEBUG_BUSY__WR_CTL_MUX_BUSY__SHIFT 0xc +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000010L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000020L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000040L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000080L +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER_BUSY_MASK 0x00000100L +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WR_WCTL_BUSY_MASK 0x00000200L +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00000400L +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x00000800L +#define SPI_SLAVE_DEBUG_BUSY__WR_CTL_MUX_BUSY_MASK 0x00001000L +//SPI_LB_CTR_CTRL +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 +#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L +#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L +//SPI_LB_WGP_MASK +#define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0 +#define SPI_LB_WGP_MASK__WGP_MASK_MASK 0x0000FFFFL +//SPI_LB_DATA_REG +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL +//SPI_PG_ENABLE_STATIC_WGP_MASK +#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0x0000FFFFL +//SPI_GDS_CREDITS +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L +//SPI_SX_EXPORT_BUFFER_SIZES +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L +//SPI_SX_SCOREBOARD_BUFFER_SIZES +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L +//SPI_CSQ_WF_ACTIVE_STATUS +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL +//SPI_CSQ_WF_ACTIVE_COUNT_0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_1 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_2 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_3 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_4 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_5 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_6 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_7 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L +//SPI_LB_DATA_WAVES +#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 +#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 +#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL +#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L +//SPI_LB_DATA_PERWGP_WAVE_HSGS +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0 +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10 +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERWGP_WAVE_PS +#define SPI_LB_DATA_PERWGP_WAVE_PS__WGP_USED_PS__SHIFT 0x0 +#define SPI_LB_DATA_PERWGP_WAVE_PS__WGP_USED_PS_MASK 0x0000FFFFL +//SPI_LB_DATA_PERWGP_WAVE_CS +#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0 +#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0x0000FFFFL +//SPI_WF_ACTIVE_COUNT_GFX +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ALLOCATED__SHIFT 0x0 +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ACTIVE__SHIFT 0x8 +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ALLOCATED_MASK 0x000000FFL +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ACTIVE_MASK 0x00FFFF00L +//SPI_WF_ACTIVE_COUNT_HPG +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ALLOCATED__SHIFT 0x0 +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ACTIVE__SHIFT 0x8 +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ALLOCATED_MASK 0x000000FFL +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ACTIVE_MASK 0x00FFFF00L +//SPIS_DEBUG_READ +#define SPIS_DEBUG_READ__DATA__SHIFT 0x0 +#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//BCI_DEBUG_READ +#define BCI_DEBUG_READ__DATA__SHIFT 0x0 +#define BCI_DEBUG_READ__DATA_MASK 0x00FFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_LO +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_HI +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P0_TRAP_SCREEN_PSMA_LO +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSMA_HI +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P0_TRAP_SCREEN_GPR_MIN +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x0000003FL +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x000003C0L +//SPI_P1_TRAP_SCREEN_PSBA_LO +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSBA_HI +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P1_TRAP_SCREEN_PSMA_LO +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSMA_HI +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P1_TRAP_SCREEN_GPR_MIN +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x0000003FL +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x000003C0L +//SPI_GFX_CRAWLER_CONFIG +#define SPI_GFX_CRAWLER_CONFIG__PS_DEPTH__SHIFT 0x0 +#define SPI_GFX_CRAWLER_CONFIG__GS_DEPTH__SHIFT 0x5 +#define SPI_GFX_CRAWLER_CONFIG__HS_DEPTH__SHIFT 0xb +#define SPI_GFX_CRAWLER_CONFIG__PS_ALLOC_DEPTH__SHIFT 0x11 +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_DEPTH__SHIFT 0x16 +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_CNTL__SHIFT 0x19 +#define SPI_GFX_CRAWLER_CONFIG__RA_PSWAVE_CREDITS__SHIFT 0x1a +#define SPI_GFX_CRAWLER_CONFIG__PS_DEPTH_MASK 0x0000001FL +#define SPI_GFX_CRAWLER_CONFIG__GS_DEPTH_MASK 0x000007E0L +#define SPI_GFX_CRAWLER_CONFIG__HS_DEPTH_MASK 0x0001F800L +#define SPI_GFX_CRAWLER_CONFIG__PS_ALLOC_DEPTH_MASK 0x003E0000L +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_DEPTH_MASK 0x01C00000L +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_CNTL_MASK 0x02000000L +#define SPI_GFX_CRAWLER_CONFIG__RA_PSWAVE_CREDITS_MASK 0x1C000000L +//SPI_CS_CRAWLER_CONFIG +#define SPI_CS_CRAWLER_CONFIG__CSG_DEPTH__SHIFT 0x0 +#define SPI_CS_CRAWLER_CONFIG__CSC_DEPTH__SHIFT 0x6 +#define SPI_CS_CRAWLER_CONFIG__CSG_DEPTH_MASK 0x0000003FL +#define SPI_CS_CRAWLER_CONFIG__CSC_DEPTH_MASK 0x00000FC0L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tpdec +//TD_CNTL +#define TD_CNTL__DISABLE_MEDIAN_CALC_FOR_CUBECORNER_PHANTOM_TEXELS__SHIFT 0x0 +#define TD_CNTL__PRESERVE_VGPR_ON_UTC_ERROR__SHIFT 0xd +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 +#define TD_CNTL__FORCE_RT_BVH4_ARBITER_TO_PING_PONG__SHIFT 0x11 +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 +#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT 0x16 +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 +#define TD_CNTL__ARBITER_ROUND_ROBIN__SHIFT 0x18 +#define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT 0x19 +#define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT 0x1a +#define TD_CNTL__DISABLE_MEDIAN_CALC_FOR_CUBECORNER_PHANTOM_TEXELS_MASK 0x00000001L +#define TD_CNTL__PRESERVE_VGPR_ON_UTC_ERROR_MASK 0x00002000L +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L +#define TD_CNTL__FORCE_RT_BVH4_ARBITER_TO_PING_PONG_MASK 0x00020000L +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L +#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L +#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK 0x00400000L +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L +#define TD_CNTL__ARBITER_ROUND_ROBIN_MASK 0x01000000L +#define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK 0x02000000L +#define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK 0xFC000000L +//TD_STATUS +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_STATUS__BUSY_MASK 0x80000000L +//TD_DEBUG_DATA +#define TD_DEBUG_DATA__DATA__SHIFT 0x0 +#define TD_DEBUG_DATA__DATA_MASK 0xFFFFFFFFL +//TD_POWER_CNTL +#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT 0x6 +#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT 0x7 +#define TD_POWER_CNTL__ENABLE_DEBUG_REG__SHIFT 0x8 +#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK 0x00000040L +#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK 0x00000080L +#define TD_POWER_CNTL__ENABLE_DEBUG_REG_MASK 0x00000100L +//TD_CNTL2 +#define TD_CNTL2__LDS_RETURN_FIFO_CREDIT__SHIFT 0x0 +#define TD_CNTL2__MULTI_CYCLE_16FP__SHIFT 0x3 +#define TD_CNTL2__DISABLE_BLEND_PRT_FOR_LOADS__SHIFT 0x4 +#define TD_CNTL2__LDS_RETURN_FIFO_CREDIT_MASK 0x00000007L +#define TD_CNTL2__MULTI_CYCLE_16FP_MASK 0x00000008L +#define TD_CNTL2__DISABLE_BLEND_PRT_FOR_LOADS_MASK 0x00000010L +//TD_DSM_CNTL +//TD_DSM_CNTL2 +//TD_SCRATCH +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_CNTL +#define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT 0x0 +#define TA_CNTL__TA_INPUT_RDATA_PER_BANK_FGCG_OVERRIDE__SHIFT 0x2 +#define TA_CNTL__TA_INPUT_CFIFO_VEC64_OPT_OVERRIDE__SHIFT 0x3 +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x8 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK 0x00000001L +#define TA_CNTL__TA_INPUT_RDATA_PER_BANK_FGCG_OVERRIDE_MASK 0x00000004L +#define TA_CNTL__TA_INPUT_CFIFO_VEC64_OPT_OVERRIDE_MASK 0x00000008L +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x00001F00L +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L +//TA_CNTL_AUX +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS__SHIFT 0x1 +#define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM__SHIFT 0x2 +#define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS__SHIFT 0x3 +#define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4 +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 +#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 +#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8 +#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 +#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc +#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd +#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe +#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c +#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d +#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L +#define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS_MASK 0x00000002L +#define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM_MASK 0x00000004L +#define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS_MASK 0x00000008L +#define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L +#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L +#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L +#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L +#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L +#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L +#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L +#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L +#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L +#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L +//TA_CNTL2 +#define TA_CNTL2__STORE_COMPONENT_MODE__SHIFT 0x0 +#define TA_CNTL2__MAX_RQ_ID__SHIFT 0x4 +#define TA_CNTL2__ELEMSIZE_HASH_DIS__SHIFT 0x11 +#define TA_CNTL2__TRUNCATE_COORD_MODE__SHIFT 0x12 +#define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS__SHIFT 0x13 +#define TA_CNTL2__PRTPLUS_ACCUM_MODE__SHIFT 0x14 +#define TA_CNTL2__STORE_COMPONENT_MODE_MASK 0x00000001L +#define TA_CNTL2__MAX_RQ_ID_MASK 0x00000070L +#define TA_CNTL2__ELEMSIZE_HASH_DIS_MASK 0x00020000L +#define TA_CNTL2__TRUNCATE_COORD_MODE_MASK 0x00040000L +#define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS_MASK 0x00080000L +#define TA_CNTL2__PRTPLUS_ACCUM_MODE_MASK 0x00300000L +//TA_STATUS +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__BUSY_MASK 0x80000000L +//TA_SCRATCH +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_rbdec +//DB_DEBUG +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__ENABLE_COMPRESSION_ON_BYPASS__SHIFT 0x2 +#define DB_DEBUG__DISABLE_TILE_RATE_1XAA__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__RESERVED_FIELD_1__SHIFT 0x1e +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__ENABLE_COMPRESSION_ON_BYPASS_MASK 0x00000004L +#define DB_DEBUG__DISABLE_TILE_RATE_1XAA_MASK 0x00000008L +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__RESERVED_FIELD_1_MASK 0xC0000000L +//DB_DEBUG2 +#define DB_DEBUG2__TRAP_ENABLE__SHIFT 0x1 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT 0xe +#define DB_DEBUG2__FL_FLUSH_ONE_STILE_AT_A_TIME__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x14 +#define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES__SHIFT 0x15 +#define DB_DEBUG2__FL_DISABLE_PLANE_REPACK__SHIFT 0x1a +#define DB_DEBUG2__DEBUG_BUS_FLOP_EN__SHIFT 0x1b +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG2__TRAP_ENABLE_MASK 0x00000002L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L +#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK 0x00004000L +#define DB_DEBUG2__FL_FLUSH_ONE_STILE_AT_A_TIME_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00100000L +#define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES_MASK 0x00200000L +#define DB_DEBUG2__FL_DISABLE_PLANE_REPACK_MASK 0x04000000L +#define DB_DEBUG2__DEBUG_BUS_FLOP_EN_MASK 0x08000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +//DB_DEBUG3 +#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f +#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L +#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L +//DB_DEBUG4 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4 +#define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK__SHIFT 0x5 +#define DB_DEBUG4__DISABLE_1PLANE_PMASK_OPTIMIZATION__SHIFT 0x7 +#define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK__SHIFT 0x8 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf +#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10 +#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L +#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L +#define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK_MASK 0x00000020L +#define DB_DEBUG4__DISABLE_1PLANE_PMASK_OPTIMIZATION_MASK 0x00000080L +#define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK_MASK 0x00000100L +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L +#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L +#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L +//DB_CREDIT_LIMIT +#define DB_CREDIT_LIMIT__DB_SC_UPDATE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_EXPORT_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS__SHIFT 0xd +#define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS__SHIFT 0x12 +#define DB_CREDIT_LIMIT__DB_SC_UPDATE_CREDITS_MASK 0x0000001FL +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L +#define DB_CREDIT_LIMIT__DB_CB_EXPORT_CREDITS_MASK 0x00001C00L +#define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS_MASK 0x0003E000L +#define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS_MASK 0x007C0000L +//DB_WATERMARKS +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8 +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10 +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L +//DB_FREE_CACHELINES +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L +//DB_FIFO_DEPTH1 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L +//DB_FIFO_DEPTH2 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L +//DB_RING_CONTROL +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L +//DB_MEM_ARB_WATERMARKS +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L +//DB_FIFO_DEPTH3 +#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18 +#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L +//DB_DEBUG6 +#define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT__SHIFT 0x0 +#define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT__SHIFT 0x1 +#define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT__SHIFT 0x2 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL__SHIFT 0x3 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ID__SHIFT 0x4 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT 0xa +#define DB_DEBUG6__NEVER_DB_SC_WAVE_CONFLICT__SHIFT 0xb +#define DB_DEBUG6__DISABLE_PWS_PLUS_STC_TAG_LIVENESS_STALL__SHIFT 0xc +#define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID__SHIFT 0xd +#define DB_DEBUG6__NEVER_DB_SC_WAVE_HARD_CONFLICT__SHIFT 0xf +#define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL__SHIFT 0x10 +#define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT__SHIFT 0x18 +#define DB_DEBUG6__FORCE_MAX_STILES_IN_WAVE_CHECK__SHIFT 0x19 +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX__SHIFT 0x1a +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC__SHIFT 0x1b +#define DB_DEBUG6__FORCE_ZC_WRITEMASK_TO_FULL__SHIFT 0x1c +#define DB_DEBUG6__SPARE_BITS_31_28__SHIFT 0x1d +#define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT_MASK 0x00000001L +#define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT_MASK 0x00000002L +#define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT_MASK 0x00000004L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL_MASK 0x00000008L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ID_MASK 0x000003F0L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_EN_MASK 0x00000400L +#define DB_DEBUG6__NEVER_DB_SC_WAVE_CONFLICT_MASK 0x00000800L +#define DB_DEBUG6__DISABLE_PWS_PLUS_STC_TAG_LIVENESS_STALL_MASK 0x00001000L +#define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID_MASK 0x00006000L +#define DB_DEBUG6__NEVER_DB_SC_WAVE_HARD_CONFLICT_MASK 0x00008000L +#define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL_MASK 0x00FF0000L +#define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT_MASK 0x01000000L +#define DB_DEBUG6__FORCE_MAX_STILES_IN_WAVE_CHECK_MASK 0x02000000L +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX_MASK 0x04000000L +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC_MASK 0x08000000L +#define DB_DEBUG6__FORCE_ZC_WRITEMASK_TO_FULL_MASK 0x10000000L +#define DB_DEBUG6__SPARE_BITS_31_28_MASK 0xE0000000L +//DB_EXCEPTION_CONTROL +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 +#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 +#define DB_EXCEPTION_CONTROL__CAM_FREE_WATERMARK__SHIFT 0x18 +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L +#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L +#define DB_EXCEPTION_CONTROL__CAM_FREE_WATERMARK_MASK 0xFF000000L +//DB_DEBUG7 +#define DB_DEBUG7__SPARE_BITS__SHIFT 0x0 +#define DB_DEBUG7__SPARE_BITS_MASK 0xFFFFFFFFL +//DB_DEBUG5 +#define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT__SHIFT 0x3 +#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT 0x4 +#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT 0x5 +#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT 0x7 +#define DB_DEBUG5__DISABLE_VRS_1X2_2XAA__SHIFT 0x8 +#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT 0x9 +#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT 0xd +#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT 0xe +#define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK__SHIFT 0xf +#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT 0x10 +#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT 0x11 +#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT 0x12 +#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT 0x13 +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT 0x14 +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT 0x15 +#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT 0x16 +#define DB_DEBUG5__SPARE_BITS__SHIFT 0x18 +#define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT_MASK 0x00000008L +#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK 0x00000010L +#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK 0x00000020L +#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK 0x00000080L +#define DB_DEBUG5__DISABLE_VRS_1X2_2XAA_MASK 0x00000100L +#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK 0x00000200L +#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK 0x00002000L +#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK 0x00004000L +#define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK_MASK 0x00008000L +#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK 0x00010000L +#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK 0x00020000L +#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK 0x00040000L +#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK 0x00080000L +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK 0x00100000L +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK 0x00200000L +#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK 0x00400000L +#define DB_DEBUG5__SPARE_BITS_MASK 0xFF000000L +//DB_MEM_CONFIG +#define DB_MEM_CONFIG__Z_SCOPE__SHIFT 0x0 +#define DB_MEM_CONFIG__STENCIL_SCOPE__SHIFT 0x2 +#define DB_MEM_CONFIG__OCCLUSION_SCOPE__SHIFT 0x4 +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_Z__SHIFT 0x6 +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_STENCIL__SHIFT 0x7 +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_OCCLUSION__SHIFT 0x8 +#define DB_MEM_CONFIG__Z_OVERRIDE_COMPRESSION_MODE__SHIFT 0x9 +#define DB_MEM_CONFIG__STENCIL_OVERRIDE_COMPRESSION_MODE__SHIFT 0xb +#define DB_MEM_CONFIG__OCCLUSION_OVERRIDE_COMPRESSION_MODE__SHIFT 0xd +#define DB_MEM_CONFIG__FL_DISABLE_SINGLE_COMPRESS__SHIFT 0xf +#define DB_MEM_CONFIG__Z_SCOPE_MASK 0x00000003L +#define DB_MEM_CONFIG__STENCIL_SCOPE_MASK 0x0000000CL +#define DB_MEM_CONFIG__OCCLUSION_SCOPE_MASK 0x00000030L +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_Z_MASK 0x00000040L +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_STENCIL_MASK 0x00000080L +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_OCCLUSION_MASK 0x00000100L +#define DB_MEM_CONFIG__Z_OVERRIDE_COMPRESSION_MODE_MASK 0x00000600L +#define DB_MEM_CONFIG__STENCIL_OVERRIDE_COMPRESSION_MODE_MASK 0x00001800L +#define DB_MEM_CONFIG__OCCLUSION_OVERRIDE_COMPRESSION_MODE_MASK 0x00006000L +#define DB_MEM_CONFIG__FL_DISABLE_SINGLE_COMPRESS_MASK 0x00008000L +//DB_ARB_CONFIG +#define DB_ARB_CONFIG__ARB_MODE__SHIFT 0x0 +#define DB_ARB_CONFIG__CREDITS_MAX_RD__SHIFT 0x2 +#define DB_ARB_CONFIG__CREDITS_WEIGHT_RD__SHIFT 0x7 +#define DB_ARB_CONFIG__CREDITS_MAX_WR__SHIFT 0xc +#define DB_ARB_CONFIG__CREDITS_WEIGHT_WR__SHIFT 0x11 +#define DB_ARB_CONFIG__ARB_MODE_MASK 0x00000003L +#define DB_ARB_CONFIG__CREDITS_MAX_RD_MASK 0x0000007CL +#define DB_ARB_CONFIG__CREDITS_WEIGHT_RD_MASK 0x00000F80L +#define DB_ARB_CONFIG__CREDITS_MAX_WR_MASK 0x0001F000L +#define DB_ARB_CONFIG__CREDITS_WEIGHT_WR_MASK 0x003E0000L +//DB_DFD_INDIRECT_SEL +#define DB_DFD_INDIRECT_SEL__DFD_INDEX__SHIFT 0x0 +#define DB_DFD_INDIRECT_SEL__DFD_INDEX_MASK 0x000000FFL +//DB_DFD_INDIRECT_DAT +#define DB_DFD_INDIRECT_DAT__DFD_DATA__SHIFT 0x0 +#define DB_DFD_INDIRECT_DAT__DFD_DATA_MASK 0xFFFFFFFFL +//DB_SUMMARIZER_TIMEOUTS +#define DB_SUMMARIZER_TIMEOUTS__SUMM_CNTL_EVICT_TIMEOUT__SHIFT 0x0 +#define DB_SUMMARIZER_TIMEOUTS__SUMM_EVICT_TIMEOUT__SHIFT 0x10 +#define DB_SUMMARIZER_TIMEOUTS__SUMM_CNTL_EVICT_TIMEOUT_MASK 0x00000FFFL +#define DB_SUMMARIZER_TIMEOUTS__SUMM_EVICT_TIMEOUT_MASK 0x0FFF0000L +//DB_FGCG_SRAMS_CLK_CTRL +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27__SHIFT 0x1b +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28__SHIFT 0x1c +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29__SHIFT 0x1d +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30__SHIFT 0x1e +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31__SHIFT 0x1f +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27_MASK 0x08000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28_MASK 0x10000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29_MASK 0x20000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30_MASK 0x40000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31_MASK 0x80000000L +//DB_FGCG_INTERFACES_CLK_CTRL +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE__SHIFT 0x2 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_COMP_REQ_OVERRIDE__SHIFT 0x3 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_SRC_OVERRIDE__SHIFT 0x4 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_UPDATE_OVERRIDE__SHIFT 0x5 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE__SHIFT 0x7 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE__SHIFT 0x8 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE_MASK 0x00000004L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_COMP_REQ_OVERRIDE_MASK 0x00000008L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_SRC_OVERRIDE_MASK 0x00000010L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_UPDATE_OVERRIDE_MASK 0x00000020L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE_MASK 0x00000080L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE_MASK 0x00000100L +//DB_FIFO_DEPTH4 +#define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH__SHIFT 0x18 +#define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH_MASK 0xFF000000L +//CC_RB_BACKEND_DISABLE +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x000000F0L +//GB_ADDR_CONFIG_1 +#define GB_ADDR_CONFIG_1__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_1__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_1__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_1__NUM_PKRS__SHIFT 0x8 +#define GB_ADDR_CONFIG_1__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_1__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_1__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_1__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_1__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_1__NUM_PKRS_MASK 0x00000700L +#define GB_ADDR_CONFIG_1__NUM_SHADER_ENGINES_MASK 0x00780000L +#define GB_ADDR_CONFIG_1__NUM_RB_PER_SE_MASK 0x0C000000L +//GB_BACKEND_MAP +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL +//GB_GPU_ID +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL +//GB_ADDR_CONFIG_READ +#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00780000L +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//CB_HW_CONTROL_4 +#define CB_HW_CONTROL_4__ENABLE_READ_RESIDENCY_TIMEOUT_CNTR__SHIFT 0x0 +#define CB_HW_CONTROL_4__THRESHOLD_READ_RESIDENCY_TIMEOUT_CNTR__SHIFT 0x1 +#define CB_HW_CONTROL_4__DISABLE_FRAGOP_MULTI_FRAGMENT__SHIFT 0xe +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD__SHIFT 0x10 +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD__SHIFT 0x11 +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD__SHIFT 0x12 +#define CB_HW_CONTROL_4__ENABLE_READ_RESIDENCY_TIMEOUT_CNTR_MASK 0x00000001L +#define CB_HW_CONTROL_4__THRESHOLD_READ_RESIDENCY_TIMEOUT_CNTR_MASK 0x00000006L +#define CB_HW_CONTROL_4__DISABLE_FRAGOP_MULTI_FRAGMENT_MASK 0x00004000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD_MASK 0x00010000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD_MASK 0x00020000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD_MASK 0x00040000L +//CB_HW_CONTROL_3 +#define CB_HW_CONTROL_3__FORCE_GLX_REQ_CLKEN_HIGH__SHIFT 0x3 +#define CB_HW_CONTROL_3__FORCE_GLX_SRC_CLKEN_HIGH__SHIFT 0x4 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x6 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_FMASK_OPT_WA_AND_FULLY_COVERED__SHIFT 0x15 +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_OVERRIDE_ROH_COMP__SHIFT 0x19 +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_INSERT_BUBBLES_B2B__SHIFT 0x1a +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_CLEAR_KEY_OVERRIDE_FROM_ILLEGAL_DECODE__SHIFT 0x1b +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_WAIT_SECOND_64B__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_256B_CLEARS_BECOME_1FRAG__SHIFT 0x1d +#define CB_HW_CONTROL_3__FORCE_GLX_REQ_CLKEN_HIGH_MASK 0x00000008L +#define CB_HW_CONTROL_3__FORCE_GLX_SRC_CLKEN_HIGH_MASK 0x00000010L +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000040L +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000080L +#define CB_HW_CONTROL_3__DISABLE_FMASK_OPT_WA_AND_FULLY_COVERED_MASK 0x00200000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_OVERRIDE_ROH_COMP_MASK 0x02000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_INSERT_BUBBLES_B2B_MASK 0x04000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_CLEAR_KEY_OVERRIDE_FROM_ILLEGAL_DECODE_MASK 0x08000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_WAIT_SECOND_64B_MASK 0x10000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_256B_CLEARS_BECOME_1FRAG_MASK 0x20000000L +//CB_HW_CONTROL +#define CB_HW_CONTROL__DISABLE_GRBM_BUSY_CNTR__SHIFT 0x0 +#define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT 0x1 +#define CB_HW_CONTROL__GLX_CREDITS__SHIFT 0x6 +#define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES__SHIFT 0xc +#define CB_HW_CONTROL__DISABLE_EVICT_ILLEGAL_KEY_OVERRIDE__SHIFT 0xf +#define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID__SHIFT 0x10 +#define CB_HW_CONTROL__FORCE_WAIT_EOP_DONE_FLUSH__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__DISABLE_USE_OF_SET_HASH__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__ENABLE_SINGLE_KEY_WR_OPT__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_POWER_OPT_HC__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__DISABLE_MULTICYCLE_WRITES__SHIFT 0x1c +#define CB_HW_CONTROL__DISABLE_HOLE_COLLAPSE__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_FMASK_REREAD_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__EN_KEY_OVERRIDE__SHIFT 0x1f +#define CB_HW_CONTROL__DISABLE_GRBM_BUSY_CNTR_MASK 0x00000001L +#define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK 0x00000002L +#define CB_HW_CONTROL__GLX_CREDITS_MASK 0x000003C0L +#define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES_MASK 0x00007000L +#define CB_HW_CONTROL__DISABLE_EVICT_ILLEGAL_KEY_OVERRIDE_MASK 0x00008000L +#define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID_MASK 0x00010000L +#define CB_HW_CONTROL__FORCE_WAIT_EOP_DONE_FLUSH_MASK 0x00040000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__DISABLE_USE_OF_SET_HASH_MASK 0x00100000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__ENABLE_SINGLE_KEY_WR_OPT_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_POWER_OPT_HC_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__DISABLE_MULTICYCLE_WRITES_MASK 0x10000000L +#define CB_HW_CONTROL__DISABLE_HOLE_COLLAPSE_MASK 0x20000000L +#define CB_HW_CONTROL__DISABLE_FMASK_REREAD_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__EN_KEY_OVERRIDE_MASK 0x80000000L +//CB_HW_CONTROL_1 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__DISABLE_SRC_FIFO_BYP__SHIFT 0x15 +#define CB_HW_CONTROL_1__DISABLE_RDLAT_FIFO_BYP__SHIFT 0x16 +#define CB_HW_CONTROL_1__ENABLE_COMPRESSION_ON_BYPASS__SHIFT 0x17 +#define CB_HW_CONTROL_1__COLOR_SCOPE__SHIFT 0x18 +#define CB_HW_CONTROL_1__GLX_NOFILL__SHIFT 0x1a +#define CB_HW_CONTROL_1__GLX_VQID__SHIFT 0x1b +#define CB_HW_CONTROL_1__GLX_PERF_CNTR_EN__SHIFT 0x1f +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0000003FL +#define CB_HW_CONTROL_1__DISABLE_SRC_FIFO_BYP_MASK 0x00200000L +#define CB_HW_CONTROL_1__DISABLE_RDLAT_FIFO_BYP_MASK 0x00400000L +#define CB_HW_CONTROL_1__ENABLE_COMPRESSION_ON_BYPASS_MASK 0x00800000L +#define CB_HW_CONTROL_1__COLOR_SCOPE_MASK 0x03000000L +#define CB_HW_CONTROL_1__GLX_NOFILL_MASK 0x04000000L +#define CB_HW_CONTROL_1__GLX_VQID_MASK 0x78000000L +#define CB_HW_CONTROL_1__GLX_PERF_CNTR_EN_MASK 0x80000000L +//CB_HW_CONTROL_2 +#define CB_HW_CONTROL_2__RESERVED__SHIFT 0x0 +#define CB_HW_CONTROL_2__RESERVED_MASK 0x00000001L +//CB_HW_MEM_ARBITER_CTL +#define CB_HW_MEM_ARBITER_CTL__ARB_MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_CTL__READ_CYC_WEIGHT__SHIFT 0x1 +#define CB_HW_MEM_ARBITER_CTL__READ_CRED_CNT_MAX__SHIFT 0x7 +#define CB_HW_MEM_ARBITER_CTL__WRITE_CYC_WEIGHT__SHIFT 0xd +#define CB_HW_MEM_ARBITER_CTL__WRITE_CRED_CNT_MAX__SHIFT 0x13 +#define CB_HW_MEM_ARBITER_CTL__WRITE_CREDIT_MODE__SHIFT 0x1b +#define CB_HW_MEM_ARBITER_CTL__READ_CREDIT_MODE__SHIFT 0x1c +#define CB_HW_MEM_ARBITER_CTL__ARB_MODE_MASK 0x00000001L +#define CB_HW_MEM_ARBITER_CTL__READ_CYC_WEIGHT_MASK 0x0000003EL +#define CB_HW_MEM_ARBITER_CTL__READ_CRED_CNT_MAX_MASK 0x00000F80L +#define CB_HW_MEM_ARBITER_CTL__WRITE_CYC_WEIGHT_MASK 0x0003E000L +#define CB_HW_MEM_ARBITER_CTL__WRITE_CRED_CNT_MAX_MASK 0x00F80000L +#define CB_HW_MEM_ARBITER_CTL__WRITE_CREDIT_MODE_MASK 0x08000000L +#define CB_HW_MEM_ARBITER_CTL__READ_CREDIT_MODE_MASK 0x10000000L +//CB_FGCG_SRAM_OVERRIDE +#define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG__SHIFT 0x0 +#define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG_MASK 0x000007FFL +//CB_CACHE_EVICT_POINTS +#define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT__SHIFT 0x0 +#define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT__SHIFT 0x8 +#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT_MASK 0x000000FFL +#define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT_MASK 0x0000FF00L +#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec2 +//SPI_PQEV_CTRL +#define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0 +#define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa +#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10 +#define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL +#define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L +#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L +//SPI_EXP_THROTTLE_CTRL +#define SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT 0x0 +#define SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT 0x1 +#define SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT 0x5 +#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT 0x9 +#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT 0xd +#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT 0x10 +#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT 0x13 +#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT 0x1a +#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT 0x1d +#define SPI_EXP_THROTTLE_CTRL__ENABLE_MASK 0x00000001L +#define SPI_EXP_THROTTLE_CTRL__PERIOD_MASK 0x0000001EL +#define SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK 0x000001E0L +#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK 0x00001E00L +#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK 0x0000E000L +#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK 0x00070000L +#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK 0x03F80000L +#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK 0x1C000000L +#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK 0x20000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_rmi_gfx_se_rmidec +//RMI_GENERAL_CNTL +#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 +#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L +//RMI_GENERAL_CNTL1 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb +#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe +#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf +#define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS__SHIFT 0x10 +#define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS__SHIFT 0x16 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L +#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L +#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L +#define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS_MASK 0x003F0000L +#define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS_MASK 0x0FC00000L +//RMI_GENERAL_STATUS +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 +#define RMI_GENERAL_STATUS__RESERVED_BIT_6__SHIFT 0x6 +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf +#define RMI_GENERAL_STATUS__RESERVED_BIT_18__SHIFT 0x12 +#define RMI_GENERAL_STATUS__RESERVED_BIT_19__SHIFT 0x13 +#define RMI_GENERAL_STATUS__RESERVED_BIT_20__SHIFT 0x14 +#define RMI_GENERAL_STATUS__RESERVED_BITS_28_21__SHIFT 0x15 +#define RMI_GENERAL_STATUS__RESERVED_BIT_29__SHIFT 0x1d +#define RMI_GENERAL_STATUS__RESERVED_BIT_30__SHIFT 0x1e +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L +#define RMI_GENERAL_STATUS__RESERVED_BIT_6_MASK 0x00000040L +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_18_MASK 0x00040000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_19_MASK 0x00080000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_20_MASK 0x00100000L +#define RMI_GENERAL_STATUS__RESERVED_BITS_28_21_MASK 0x1FE00000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_29_MASK 0x20000000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_30_MASK 0x40000000L +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L +//RMI_SUBBLOCK_STATUS0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L +//RMI_SUBBLOCK_STATUS1 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L +//RMI_SUBBLOCK_STATUS2 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L +//RMI_SUBBLOCK_STATUS3 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L +//RMI_XBAR_CONFIG +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L +#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L +//RMI_PROBE_POP_LOGIC_CNTL +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L +//RMI_UTC_XNACK_N_MISC_CNTL +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L +//RMI_DEMUX_CNTL +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L +//RMI_UTCL1_CNTL1 +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//RMI_UTCL1_CNTL2 +#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b +#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c +#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d +#define RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define RMI_UTCL1_CNTL2__RESERVED__SHIFT 0x1f +#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L +#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L +#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L +#define RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define RMI_UTCL1_CNTL2__RESERVED_MASK 0x80000000L +//RMI_UTC_UNIT_CONFIG +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL +//RMI_TCIW_FORMATTER0_CNTL +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L +//RMI_TCIW_FORMATTER1_CNTL +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L +//RMI_SCOREBOARD_CNTL +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L +//RMI_SCOREBOARD_STATUS0 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 +#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L +#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L +//RMI_SCOREBOARD_STATUS1 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L +//RMI_SCOREBOARD_STATUS2 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L +//RMI_XBAR_ARBITER_CONFIG +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L +//RMI_XBAR_ARBITER_CONFIG_1 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L +//RMI_CLOCK_CNTRL +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L +//RMI_UTCL1_STATUS +#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//RMI_RB_GLX_CID_MAP +#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0 +#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4 +#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8 +#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc +#define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10 +#define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14 +#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18 +#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c +#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL +#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L +#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L +#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L +#define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L +#define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L +#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L +#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L +//RMI_XNACK_DEBUG +#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0 +#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL +//RMI_SPARE +#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1 +#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2 +#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3 +#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4 +#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5 +#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT 0x6 +#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8 +#define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9 +#define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa +#define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb +#define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc +#define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd +#define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe +#define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf +#define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10 +#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L +#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L +#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L +#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L +#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L +#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK 0x00000040L +#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L +#define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L +#define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L +#define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L +#define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L +#define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L +#define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L +#define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L +#define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L +//RMI_SPARE_1 +#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT 0x0 +#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 +#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 +#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 +#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 +#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 +#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 +#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 +#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8 +#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 +#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK 0x00000001L +#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L +#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L +#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L +#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L +#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L +#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L +#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L +#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L +#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L +//RMI_SPARE_2 +#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT 0x0 +#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 +#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 +#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK 0x0000FFFFL +#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L +#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L +//CC_RMI_REDUNDANCY +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 +#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 +#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L +#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L +#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_utcl1dec +//UTCL1_CTRL_1 +#define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x0 +#define UTCL1_CTRL_1__UTCL1_TCP_BYPASS__SHIFT 0x1 +#define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS__SHIFT 0x2 +#define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS__SHIFT 0x3 +#define UTCL1_CTRL_1__UTCL1_RMI_BYPASS__SHIFT 0x4 +#define UTCL1_CTRL_1__UTCL1_SQG_BYPASS__SHIFT 0x5 +#define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x6 +#define UTCL1_CTRL_1__RESERVED_0__SHIFT 0x7 +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0x8 +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1__SHIFT 0x9 +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2__SHIFT 0xb +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3__SHIFT 0xd +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4__SHIFT 0xf +#define UTCL1_CTRL_1__RESERVED_1__SHIFT 0x11 +#define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000001L +#define UTCL1_CTRL_1__UTCL1_TCP_BYPASS_MASK 0x00000002L +#define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS_MASK 0x00000004L +#define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS_MASK 0x00000008L +#define UTCL1_CTRL_1__UTCL1_RMI_BYPASS_MASK 0x00000010L +#define UTCL1_CTRL_1__UTCL1_SQG_BYPASS_MASK 0x00000020L +#define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000040L +#define UTCL1_CTRL_1__RESERVED_0_MASK 0x00000080L +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000100L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1_MASK 0x00000600L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2_MASK 0x00001800L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3_MASK 0x00006000L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4_MASK 0x00018000L +#define UTCL1_CTRL_1__RESERVED_1_MASK 0xFFFE0000L +//UTCL1_HASH_CTRL +#define UTCL1_HASH_CTRL__UTCL1_BANK_SELECT_BASE__SHIFT 0x0 +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK0__SHIFT 0x5 +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK1__SHIFT 0x9 +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK0__SHIFT 0xd +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK1__SHIFT 0x11 +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK2__SHIFT 0x15 +#define UTCL1_HASH_CTRL__UTCL1_XOR_ONLY_HIGHER_WAYS__SHIFT 0x19 +#define UTCL1_HASH_CTRL__UTCL1_WAY_SELECT_OFFSET__SHIFT 0x1a +#define UTCL1_HASH_CTRL__RESERVED__SHIFT 0x1f +#define UTCL1_HASH_CTRL__UTCL1_BANK_SELECT_BASE_MASK 0x0000001FL +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK0_MASK 0x000001E0L +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK1_MASK 0x00001E00L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK0_MASK 0x0001E000L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK1_MASK 0x001E0000L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK2_MASK 0x01E00000L +#define UTCL1_HASH_CTRL__UTCL1_XOR_ONLY_HIGHER_WAYS_MASK 0x02000000L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SELECT_OFFSET_MASK 0x7C000000L +#define UTCL1_HASH_CTRL__RESERVED_MASK 0x80000000L +//UTCL1_ALOG +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3 +#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4 +#define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5 +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6 +#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9 +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa +#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc +#define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf +#define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10 +#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L +#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L +#define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L +#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L +#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L +#define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L +#define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L +#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L +//UTCL1_STATUS +#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT 0x0 +#define UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT 0x1 +#define UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT 0x2 +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT 0x3 +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT 0x4 +#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT 0x5 +#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT 0x7 +#define UTCL1_STATUS__RESERVED__SHIFT 0x8 +#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK 0x00000001L +#define UTCL1_STATUS__UTCL1_MH_BUSY_MASK 0x00000002L +#define UTCL1_STATUS__UTCL1_INV_BUSY_MASK 0x00000004L +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK 0x00000008L +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK 0x00000010L +#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK 0x00000060L +#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK 0x00000080L +#define UTCL1_STATUS__RESERVED_MASK 0x00000100L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shdec +//SPI_SHADER_PGM_CHKSUM_PS +#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC3_PS +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL +//SPI_SHADER_PGM_RSRC4_PS +#define SPI_SHADER_PGM_RSRC4_PS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_PS__LDS_GROUP_SIZE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC4_PS__DIDT_THROTTLE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_PS__WAVE_LIMIT_MASK 0x000003FFL +#define SPI_SHADER_PGM_RSRC4_PS__LDS_GROUP_SIZE_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC4_PS__DIDT_THROTTLE_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE_MASK 0x00FF0000L +#define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_LO_PS +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_PS +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000FFL +//SPI_SHADER_PGM_RSRC1_PS +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__WG_RR_EN__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_PS__DISABLE_PERF__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__WG_RR_EN_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_PS__DISABLE_PERF_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L +//SPI_SHADER_PGM_RSRC2_PS +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_PS_0 +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_1 +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_2 +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_3 +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_4 +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_5 +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_6 +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_7 +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_8 +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_9 +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_10 +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_11 +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_12 +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_13 +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_14 +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_15 +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_16 +#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_17 +#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_18 +#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_19 +#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_20 +#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_21 +#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_22 +#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_23 +#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_24 +#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_25 +#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_26 +#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_27 +#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_28 +#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_29 +#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_30 +#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_31 +#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_REQ_CTRL_PS +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_GS_OUT_CONFIG_PS +#define SPI_SHADER_GS_OUT_CONFIG_PS__VS_EXPORT_COUNT__SHIFT 0x0 +#define SPI_SHADER_GS_OUT_CONFIG_PS__PRIM_EXPORT_COUNT__SHIFT 0x5 +#define SPI_SHADER_GS_OUT_CONFIG_PS__NO_PC_EXPORT__SHIFT 0xa +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_INTERP__SHIFT 0xb +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_PRIM_INTERP__SHIFT 0x11 +#define SPI_SHADER_GS_OUT_CONFIG_PS__VS_EXPORT_COUNT_MASK 0x0000001FL +#define SPI_SHADER_GS_OUT_CONFIG_PS__PRIM_EXPORT_COUNT_MASK 0x000003E0L +#define SPI_SHADER_GS_OUT_CONFIG_PS__NO_PC_EXPORT_MASK 0x00000400L +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_INTERP_MASK 0x0001F800L +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_PRIM_INTERP_MASK 0x003E0000L +//SPI_SHADER_USER_ACCUM_PS_0 +#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_1 +#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_2 +#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_3 +#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_CHKSUM_GS +#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_LO_GS +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_GS +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_GS +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_GS +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000FFL +//SPI_SHADER_PGM_RSRC3_GS +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_GS +#define SPI_SHADER_PGM_RSRC4_GS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_GS__GLG_EN_OVERRIDE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC4_GS__GLG_FORCE_DISABLE__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC4_GS__DIDT_THROTTLE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN__SHIFT 0xe +#define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN__SHIFT 0xf +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_GS__WAVE_LIMIT_MASK 0x000003FFL +#define SPI_SHADER_PGM_RSRC4_GS__GLG_EN_OVERRIDE_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC4_GS__GLG_FORCE_DISABLE_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC4_GS__DIDT_THROTTLE_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN_MASK 0x00004000L +#define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN_MASK 0x00008000L +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L +#define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE_MASK 0x7F800000L +#define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_LO_ES +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC1_GS +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__WG_RR_EN__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_GS__DISABLE_PERF__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__WG_RR_EN_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_GS__DISABLE_PERF_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_GS +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_GS_0 +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_1 +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_2 +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_3 +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_4 +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_5 +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_6 +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_7 +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_8 +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_9 +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_10 +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_11 +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_12 +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_13 +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_14 +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_15 +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_16 +#define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_17 +#define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_18 +#define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_19 +#define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_20 +#define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_21 +#define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_22 +#define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_23 +#define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_24 +#define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_25 +#define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_26 +#define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_27 +#define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_28 +#define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_29 +#define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_30 +#define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_31 +#define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_GS_MESHLET_DIM +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y__SHIFT 0x8 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z__SHIFT 0x10 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE__SHIFT 0x18 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X_MASK 0x000000FFL +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y_MASK 0x0000FF00L +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z_MASK 0x00FF0000L +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE_MASK 0xFF000000L +//SPI_SHADER_GS_MESHLET_EXP_ALLOC +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS__SHIFT 0x9 +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS_MASK 0x000001FFL +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS_MASK 0x0003FE00L +//SPI_SHADER_GS_MESHLET_CTRL +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_X__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_Y__SHIFT 0x4 +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_X_MASK 0x0000000FL +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_Y_MASK 0x000000F0L +//SPI_SHADER_REQ_CTRL_ESGS +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_GS_OUT_CONFIG_PS_GS +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__VS_EXPORT_COUNT__SHIFT 0x0 +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__PRIM_EXPORT_COUNT__SHIFT 0x5 +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NO_PC_EXPORT__SHIFT 0xa +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_INTERP__SHIFT 0xb +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_PRIM_INTERP__SHIFT 0x11 +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__VS_EXPORT_COUNT_MASK 0x0000001FL +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__PRIM_EXPORT_COUNT_MASK 0x000003E0L +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NO_PC_EXPORT_MASK 0x00000400L +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_INTERP_MASK 0x0001F800L +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_PRIM_INTERP_MASK 0x003E0000L +//SPI_SHADER_USER_ACCUM_ESGS_0 +#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_1 +#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_2 +#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_3 +#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_CHKSUM_HS +#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_LO_HS +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_HS +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_HS +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_HS +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000FFL +//SPI_SHADER_PGM_RSRC3_HS +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_HS +#define SPI_SHADER_PGM_RSRC4_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_HS__GLG_EN_OVERRIDE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC4_HS__GLG_FORCE_DISABLE__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC4_HS__DIDT_THROTTLE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_HS__WAVE_LIMIT_MASK 0x000003FFL +#define SPI_SHADER_PGM_RSRC4_HS__GLG_EN_OVERRIDE_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC4_HS__GLG_FORCE_DISABLE_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC4_HS__DIDT_THROTTLE_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE_MASK 0x00FF0000L +#define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_LO_LS +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC1_HS +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__WG_RR_EN__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_HS__DISABLE_PERF__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__WG_RR_EN_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_HS__DISABLE_PERF_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L +//SPI_SHADER_PGM_RSRC2_HS +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_HS_0 +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_1 +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_2 +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_3 +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_4 +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_5 +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_6 +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_7 +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_8 +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_9 +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_10 +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_11 +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_12 +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_13 +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_14 +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_15 +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_16 +#define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_17 +#define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_18 +#define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_19 +#define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_20 +#define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_21 +#define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_22 +#define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_23 +#define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_24 +#define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_25 +#define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_26 +#define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_27 +#define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_28 +#define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_29 +#define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_30 +#define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_31 +#define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_REQ_CTRL_LSHS +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_USER_ACCUM_LSHS_0 +#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_1 +#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_2 +#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_3 +#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec +//SPI_ARB_PRIORITY +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L +//SPI_ARB_CYCLES_0 +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L +//SPI_ARB_CYCLES_1 +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L +//SPI_WCL_PIPE_PERCENT_GFX +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_HP3D +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_CS0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS1 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS2 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS3 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS4 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS5 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS6 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS7 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x0000007FL +//SPI_USER_ACCUM_VMID_CNTL +#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0 +#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL +//SPI_GDBG_PER_VMID_CNTL +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT 0xe +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT 0xf +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x00000001L +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x00000006L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x00000008L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x00001FF0L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x00002000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK 0x00004000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK 0x00008000L +//SPI_COMPUTE_QUEUE_RESET +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x00000001L +//SPI_COMPUTE_WF_CTX_SAVE +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L +//SPI_SAVE_RESTORE_STATUS +#define SPI_SAVE_RESTORE_STATUS__PERFCOUNTER_EN__SHIFT 0x0 +#define SPI_SAVE_RESTORE_STATUS__THREAD_TRACE_EN__SHIFT 0x1 +#define SPI_SAVE_RESTORE_STATUS__PERFCOUNTER_EN_MASK 0x00000001L +#define SPI_SAVE_RESTORE_STATUS__THREAD_TRACE_EN_MASK 0x00000002L +//SPI_CONFIG_DIDT_CNTL +#define SPI_CONFIG_DIDT_CNTL__DELAY_SELECT__SHIFT 0x0 +#define SPI_CONFIG_DIDT_CNTL__INCR_EVENT__SHIFT 0x6 +#define SPI_CONFIG_DIDT_CNTL__THRESHOLD__SHIFT 0x8 +#define SPI_CONFIG_DIDT_CNTL__STALL_WAVES__SHIFT 0xe +#define SPI_CONFIG_DIDT_CNTL__STALL_RATE__SHIFT 0x10 +#define SPI_CONFIG_DIDT_CNTL__THROTTLE_EN__SHIFT 0x15 +#define SPI_CONFIG_DIDT_CNTL__DELAY_SELECT_MASK 0x0000003FL +#define SPI_CONFIG_DIDT_CNTL__INCR_EVENT_MASK 0x000000C0L +#define SPI_CONFIG_DIDT_CNTL__THRESHOLD_MASK 0x00003F00L +#define SPI_CONFIG_DIDT_CNTL__STALL_WAVES_MASK 0x0000C000L +#define SPI_CONFIG_DIDT_CNTL__STALL_RATE_MASK 0x001F0000L +#define SPI_CONFIG_DIDT_CNTL__THROTTLE_EN_MASK 0x00200000L +//SPI_CONFIG_DIDT_TYPEMASK +#define SPI_CONFIG_DIDT_TYPEMASK__GFX_TYPE_ENABLE__SHIFT 0x0 +#define SPI_CONFIG_DIDT_TYPEMASK__ACE_TYPE_ENABLE__SHIFT 0x4 +#define SPI_CONFIG_DIDT_TYPEMASK__GFX_TYPE_ENABLE_MASK 0x0000000FL +#define SPI_CONFIG_DIDT_TYPEMASK__ACE_TYPE_ENABLE_MASK 0x00000FF0L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tcpdec +//TCP_WATCH0_ADDR_H +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH0_ADDR_L +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH0_CNTL +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH1_ADDR_H +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH1_ADDR_L +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH1_CNTL +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH2_ADDR_H +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH2_ADDR_L +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH2_CNTL +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH3_ADDR_H +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH3_ADDR_L +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH3_CNTL +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxdec0 +//DB_RENDER_CONTROL +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__RESERVED_FIELD_1__SHIFT 0x2 +#define DB_RENDER_CONTROL__RESERVED_FIELD_2__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESERVED_FIELD_4__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT 0xe +#define DB_RENDER_CONTROL__OREO_MODE__SHIFT 0x10 +#define DB_RENDER_CONTROL__FORCE_OREO_MODE__SHIFT 0x12 +#define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER__SHIFT 0x13 +#define DB_RENDER_CONTROL__MAX_ALLOWED_STILES_IN_WAVE__SHIFT 0x14 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__RESERVED_FIELD_1_MASK 0x00000004L +#define DB_RENDER_CONTROL__RESERVED_FIELD_2_MASK 0x00000008L +#define DB_RENDER_CONTROL__RESERVED_FIELD_4_MASK 0x00000010L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L +#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK 0x00004000L +#define DB_RENDER_CONTROL__OREO_MODE_MASK 0x00030000L +#define DB_RENDER_CONTROL__FORCE_OREO_MODE_MASK 0x00040000L +#define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER_MASK 0x00080000L +#define DB_RENDER_CONTROL__MAX_ALLOWED_STILES_IN_WAVE_MASK 0x00F00000L +//DB_DEPTH_VIEW +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x10 +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x00003FFFL +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x3FFF0000L +//DB_DEPTH_VIEW1 +#define DB_DEPTH_VIEW1__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW1__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_DEPTH_VIEW1__MIPID__SHIFT 0x1a +#define DB_DEPTH_VIEW1__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW1__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW1__MIPID_MASK 0x7C000000L +//DB_RENDER_OVERRIDE +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +//DB_RENDER_OVERRIDE2 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_5__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_6__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_1__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_Z_RANGE_TO_MAX__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_STENCIL_RANGE_TO_MAX__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_2__SHIFT 0xd +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 +#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT 0x1b +#define DB_RENDER_OVERRIDE2__DISABLE_NOZ__SHIFT 0x1d +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_5_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_6_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_1_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_Z_RANGE_TO_MAX_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_STENCIL_RANGE_TO_MAX_MASK 0x00001000L +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_2_MASK 0x001FE000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L +#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK 0x18000000L +#define DB_RENDER_OVERRIDE2__DISABLE_NOZ_MASK 0x20000000L +//DB_DEPTH_SIZE_XY +#define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10 +#define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x0000FFFFL +#define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0xFFFF0000L +//DB_Z_INFO +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__SW_MODE__SHIFT 0x4 +#define DB_Z_INFO__RESERVED_FIELD_2__SHIFT 0x9 +#define DB_Z_INFO__RESERVED_FIELD_11__SHIFT 0xb +#define DB_Z_INFO__RESERVED_FIELD_12__SHIFT 0xc +#define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd +#define DB_Z_INFO__MAXMIP__SHIFT 0xf +#define DB_Z_INFO__RESERVED_FIELD_20__SHIFT 0x14 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__RESERVED_FIELD_27__SHIFT 0x1b +#define DB_Z_INFO__RESERVED_FIELD_28__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL +#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L +#define DB_Z_INFO__RESERVED_FIELD_2_MASK 0x00000600L +#define DB_Z_INFO__RESERVED_FIELD_11_MASK 0x00000800L +#define DB_Z_INFO__RESERVED_FIELD_12_MASK 0x00001000L +#define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x00006000L +#define DB_Z_INFO__MAXMIP_MASK 0x000F8000L +#define DB_Z_INFO__RESERVED_FIELD_20_MASK 0x00100000L +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L +#define DB_Z_INFO__RESERVED_FIELD_27_MASK 0x08000000L +#define DB_Z_INFO__RESERVED_FIELD_28_MASK 0x10000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +//DB_STENCIL_INFO +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 +#define DB_STENCIL_INFO__RESERVED_FIELD_2__SHIFT 0x9 +#define DB_STENCIL_INFO__RESERVED_FIELD_11__SHIFT 0xb +#define DB_STENCIL_INFO__RESERVED_FIELD_12__SHIFT 0xc +#define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd +#define DB_STENCIL_INFO__RESERVED_FIELD_20__SHIFT 0x14 +#define DB_STENCIL_INFO__RESERVED_FIELD_27__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L +#define DB_STENCIL_INFO__RESERVED_FIELD_2_MASK 0x00000600L +#define DB_STENCIL_INFO__RESERVED_FIELD_11_MASK 0x00000800L +#define DB_STENCIL_INFO__RESERVED_FIELD_12_MASK 0x00001000L +#define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L +#define DB_STENCIL_INFO__RESERVED_FIELD_20_MASK 0x00100000L +#define DB_STENCIL_INFO__RESERVED_FIELD_27_MASK 0x08000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +//DB_Z_READ_BASE +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_READ_BASE_HI +#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_Z_WRITE_BASE +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_WRITE_BASE_HI +#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_READ_BASE +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_READ_BASE_HI +#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_WRITE_BASE +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_WRITE_BASE_HI +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_GL1_INTERFACE_CONTROL +#define DB_GL1_INTERFACE_CONTROL__Z_SPECULATIVE_READ__SHIFT 0x0 +#define DB_GL1_INTERFACE_CONTROL__STENCIL_SPECULATIVE_READ__SHIFT 0x2 +#define DB_GL1_INTERFACE_CONTROL__Z_COMPRESSION_MODE__SHIFT 0x4 +#define DB_GL1_INTERFACE_CONTROL__STENCIL_COMPRESSION_MODE__SHIFT 0x6 +#define DB_GL1_INTERFACE_CONTROL__OCCLUSION_COMPRESSION_MODE__SHIFT 0x8 +#define DB_GL1_INTERFACE_CONTROL__Z_SPECULATIVE_READ_MASK 0x00000003L +#define DB_GL1_INTERFACE_CONTROL__STENCIL_SPECULATIVE_READ_MASK 0x0000000CL +#define DB_GL1_INTERFACE_CONTROL__Z_COMPRESSION_MODE_MASK 0x00000030L +#define DB_GL1_INTERFACE_CONTROL__STENCIL_COMPRESSION_MODE_MASK 0x000000C0L +#define DB_GL1_INTERFACE_CONTROL__OCCLUSION_COMPRESSION_MODE_MASK 0x00000300L +//DB_MEM_TEMPORAL +#define DB_MEM_TEMPORAL__Z_TEMPORAL_READ__SHIFT 0x0 +#define DB_MEM_TEMPORAL__Z_TEMPORAL_WRITE__SHIFT 0x3 +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_READ__SHIFT 0x6 +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_WRITE__SHIFT 0x9 +#define DB_MEM_TEMPORAL__OCCLUSION_TEMPORAL_WRITE__SHIFT 0xc +#define DB_MEM_TEMPORAL__Z_TEMPORAL_READ_MASK 0x00000007L +#define DB_MEM_TEMPORAL__Z_TEMPORAL_WRITE_MASK 0x00000038L +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_READ_MASK 0x000001C0L +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_WRITE_MASK 0x00000E00L +#define DB_MEM_TEMPORAL__OCCLUSION_TEMPORAL_WRITE_MASK 0x00007000L +//DB_DEPTH_BOUNDS_MIN +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL +//DB_DEPTH_BOUNDS_MAX +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL +//DB_COUNT_CONTROL +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2 +#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L +#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L +//DB_VIEWPORT_CONTROL +#define DB_VIEWPORT_CONTROL__DISABLE_VIEWPORT_CLAMP__SHIFT 0x0 +#define DB_VIEWPORT_CONTROL__DISABLE_VIEWPORT_CLAMP_MASK 0x00000001L +//DB_SPI_VRS_CENTER_LOCATION +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X1__SHIFT 0x0 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X1__SHIFT 0x4 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X1__SHIFT 0x8 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X1__SHIFT 0xc +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X2__SHIFT 0x10 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X2__SHIFT 0x14 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X2__SHIFT 0x18 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X2__SHIFT 0x1c +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X1_MASK 0x0000000FL +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X1_MASK 0x000000F0L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X1_MASK 0x00000F00L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X1_MASK 0x0000F000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X2_MASK 0x000F0000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X2_MASK 0x00F00000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X2_MASK 0x0F000000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X2_MASK 0xF0000000L +//DB_SHADER_CONTROL +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 +#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17 +#define DB_SHADER_CONTROL__OREO_BLEND_ENABLE__SHIFT 0x18 +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE__SHIFT 0x19 +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE__SHIFT 0x1a +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L +#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L +#define DB_SHADER_CONTROL__OREO_BLEND_ENABLE_MASK 0x01000000L +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE_MASK 0x02000000L +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_MASK 0x1C000000L +//DB_DEPTH_CONTROL +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__RESERVED_FIELD_30__SHIFT 0x1e +#define DB_DEPTH_CONTROL__RESERVED_FIELD_31__SHIFT 0x1f +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__RESERVED_FIELD_30_MASK 0x40000000L +#define DB_DEPTH_CONTROL__RESERVED_FIELD_31_MASK 0x80000000L +//DB_STENCIL_CONTROL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L +//DB_EQAA +#define DB_EQAA__RESERVED_FIELD_1__SHIFT 0x0 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__RESERVED_FIELD_17__SHIFT 0x11 +#define DB_EQAA__RESERVED_FIELD_18__SHIFT 0x12 +#define DB_EQAA__RESERVED_FIELD_19__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__RESERVED_FIELD_21__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_EQAA__RESERVED_FIELD_1_MASK 0x00000007L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__RESERVED_FIELD_17_MASK 0x00020000L +#define DB_EQAA__RESERVED_FIELD_18_MASK 0x00040000L +#define DB_EQAA__RESERVED_FIELD_19_MASK 0x00080000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__RESERVED_FIELD_21_MASK 0x00200000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +//DB_ALPHA_TO_MASK +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +//TA_BC_BASE_ADDR +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_BC_BASE_ADDR_HI +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//DB_STENCIL_REF +#define DB_STENCIL_REF__TESTVAL__SHIFT 0x0 +#define DB_STENCIL_REF__TESTVAL_BF__SHIFT 0x8 +#define DB_STENCIL_REF__TESTVAL_MASK 0x000000FFL +#define DB_STENCIL_REF__TESTVAL_BF_MASK 0x0000FF00L +//DB_STENCIL_OPVAL +#define DB_STENCIL_OPVAL__OPVAL__SHIFT 0x0 +#define DB_STENCIL_OPVAL__OPVAL_BF__SHIFT 0x8 +#define DB_STENCIL_OPVAL__OPVAL_MASK 0x000000FFL +#define DB_STENCIL_OPVAL__OPVAL_BF_MASK 0x0000FF00L +//DB_STENCIL_READ_MASK +#define DB_STENCIL_READ_MASK__TESTMASK__SHIFT 0x0 +#define DB_STENCIL_READ_MASK__TESTMASK_BF__SHIFT 0x8 +#define DB_STENCIL_READ_MASK__TESTMASK_MASK 0x000000FFL +#define DB_STENCIL_READ_MASK__TESTMASK_BF_MASK 0x0000FF00L +//DB_STENCIL_WRITE_MASK +#define DB_STENCIL_WRITE_MASK__WRITEMASK__SHIFT 0x0 +#define DB_STENCIL_WRITE_MASK__WRITEMASK_BF__SHIFT 0x8 +#define DB_STENCIL_WRITE_MASK__WRITEMASK_MASK 0x000000FFL +#define DB_STENCIL_WRITE_MASK__WRITEMASK_BF_MASK 0x0000FF00L +//SC_MEM_TEMPORAL +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_READ__SHIFT 0x0 +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_WRITE__SHIFT 0x3 +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_READ__SHIFT 0x6 +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_WRITE__SHIFT 0x9 +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_READ__SHIFT 0xc +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_WRITE__SHIFT 0xf +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_READ_MASK 0x00000007L +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_WRITE_MASK 0x00000038L +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_READ_MASK 0x000001C0L +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_WRITE_MASK 0x00000E00L +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_READ_MASK 0x00007000L +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_WRITE_MASK 0x00038000L +//SC_MEM_SPEC_READ +#define SC_MEM_SPEC_READ__VRS_SPECULATIVE_READ__SHIFT 0x0 +#define SC_MEM_SPEC_READ__HIZ_SPECULATIVE_READ__SHIFT 0x2 +#define SC_MEM_SPEC_READ__HIS_SPECULATIVE_READ__SHIFT 0x4 +#define SC_MEM_SPEC_READ__VRS_SPECULATIVE_READ_MASK 0x00000003L +#define SC_MEM_SPEC_READ__HIZ_SPECULATIVE_READ_MASK 0x0000000CL +#define SC_MEM_SPEC_READ__HIS_SPECULATIVE_READ_MASK 0x00000030L +//PA_SC_VPORT_0_TL +#define PA_SC_VPORT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_0_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_0_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_0_BR +#define PA_SC_VPORT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_0_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_0_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_1_TL +#define PA_SC_VPORT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_1_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_1_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_1_BR +#define PA_SC_VPORT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_1_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_1_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_2_TL +#define PA_SC_VPORT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_2_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_2_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_2_BR +#define PA_SC_VPORT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_2_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_2_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_3_TL +#define PA_SC_VPORT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_3_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_3_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_3_BR +#define PA_SC_VPORT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_3_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_3_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_4_TL +#define PA_SC_VPORT_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_4_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_4_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_4_BR +#define PA_SC_VPORT_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_4_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_4_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_5_TL +#define PA_SC_VPORT_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_5_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_5_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_5_BR +#define PA_SC_VPORT_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_5_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_5_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_6_TL +#define PA_SC_VPORT_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_6_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_6_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_6_BR +#define PA_SC_VPORT_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_6_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_6_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_7_TL +#define PA_SC_VPORT_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_7_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_7_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_7_BR +#define PA_SC_VPORT_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_7_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_7_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_8_TL +#define PA_SC_VPORT_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_8_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_8_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_8_BR +#define PA_SC_VPORT_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_8_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_8_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_9_TL +#define PA_SC_VPORT_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_9_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_9_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_9_BR +#define PA_SC_VPORT_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_9_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_9_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_10_TL +#define PA_SC_VPORT_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_10_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_10_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_10_BR +#define PA_SC_VPORT_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_10_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_10_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_11_TL +#define PA_SC_VPORT_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_11_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_11_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_11_BR +#define PA_SC_VPORT_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_11_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_11_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_12_TL +#define PA_SC_VPORT_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_12_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_12_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_12_BR +#define PA_SC_VPORT_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_12_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_12_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_13_TL +#define PA_SC_VPORT_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_13_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_13_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_13_BR +#define PA_SC_VPORT_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_13_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_13_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_14_TL +#define PA_SC_VPORT_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_14_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_14_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_14_BR +#define PA_SC_VPORT_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_14_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_14_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_15_TL +#define PA_SC_VPORT_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_15_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_15_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_15_BR +#define PA_SC_VPORT_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_15_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_15_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_CLIPRECT_RULE +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL +//PA_SC_CLIPRECT_0_TL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_0_BR +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_TL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_BR +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_TL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_BR +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_TL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_BR +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_EDGERULE +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L +//PA_SU_HARDWARE_SCREEN_OFFSET +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x00000FFFL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x0FFF0000L +//PA_SC_GENERIC_SCISSOR_TL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_GENERIC_SCISSOR_BR +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_0_TL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_0_BR +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_1_TL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_1_BR +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_2_TL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_2_BR +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_3_TL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_3_BR +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_4_TL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_4_BR +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_5_TL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_5_BR +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_6_TL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_6_BR +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_7_TL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_7_BR +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_8_TL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_8_BR +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_9_TL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_9_BR +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_10_TL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_10_BR +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_11_TL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_11_BR +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_12_TL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_12_BR +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_13_TL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_13_BR +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_14_TL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_14_BR +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_15_TL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_15_BR +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0xFFFF0000L +//PA_CL_UCP_0_X +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Y +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Z +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_W +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_X +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Y +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Z +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_W +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_X +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Y +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Z +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_W +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_X +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Y +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Z +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_W +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_X +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Y +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Z +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_W +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_X +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Y +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Z +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_W +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_PROG_NEAR_CLIP_Z +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_RATE_CNTL +#define PA_RATE_CNTL__VERTEX_RATE__SHIFT 0x0 +#define PA_RATE_CNTL__PRIM_RATE__SHIFT 0x4 +#define PA_RATE_CNTL__VERTEX_RATE_MASK 0x0000000FL +#define PA_RATE_CNTL__PRIM_RATE_MASK 0x000000F0L +//PA_SC_RASTER_CONFIG +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L +//PA_SC_RASTER_CONFIG_1 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L +//PA_SC_SCREEN_EXTENT_CONTROL +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL +//PA_SC_TILE_STEERING_OVERRIDE +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14 +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00300000L +//PA_SC_CLIPRECT_0_EXT +#define PA_SC_CLIPRECT_0_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_0_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_0_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_0_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_0_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_0_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_0_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_CLIPRECT_1_EXT +#define PA_SC_CLIPRECT_1_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_1_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_1_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_1_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_1_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_1_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_1_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_CLIPRECT_2_EXT +#define PA_SC_CLIPRECT_2_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_2_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_2_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_2_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_2_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_2_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_2_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_CLIPRECT_3_EXT +#define PA_SC_CLIPRECT_3_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_3_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_3_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_3_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_3_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_3_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_3_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_VRS_OVERRIDE_CNTL +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT 0x0 +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE__SHIFT 0x4 +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE__SHIFT 0xc +#define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE__SHIFT 0xd +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0xe +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK 0x00000007L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE_MASK 0x000000F0L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE_MASK 0x00001000L +#define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE_MASK 0x00002000L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00004000L +//PA_SC_VRS_RATE_FEEDBACK_BASE +#define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VRS_RATE_FEEDBACK_BASE_EXT +#define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_VRS_RATE_FEEDBACK_SIZE_XY +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//PA_SC_VRS_INFO +#define PA_SC_VRS_INFO__RATE_SW_MODE__SHIFT 0x0 +#define PA_SC_VRS_INFO__FEEDBACK_SW_MODE__SHIFT 0x3 +#define PA_SC_VRS_INFO__RATE_SW_MODE_MASK 0x00000007L +#define PA_SC_VRS_INFO__FEEDBACK_SW_MODE_MASK 0x00000038L +//PA_SC_VRS_RATE_BASE +#define PA_SC_VRS_RATE_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VRS_RATE_BASE_EXT +#define PA_SC_VRS_RATE_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID__SHIFT 0x1c +#define PA_SC_VRS_RATE_BASE_EXT__BASE_256B_MASK 0x000000FFL +#define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID_MASK 0xF0000000L +//PA_SC_VRS_RATE_SIZE_XY +#define PA_SC_VRS_RATE_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_VRS_RATE_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_VRS_RATE_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_VRS_RATE_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//CB_RMI_GL2_CACHE_CONTROL +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x2 +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x0000000CL +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L +//CB_BLEND_RED +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL +//CB_BLEND_GREEN +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL +//CB_BLEND_BLUE +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL +//CB_BLEND_ALPHA +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_1 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_1 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_1 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_1 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_1 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_1 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_1 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_1 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_2 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_2 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_2 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_2 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_2 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_2 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_2 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_2 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_3 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_3 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_3 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_3 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_3 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_3 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_3 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_3 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_4 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_4 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_4 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_4 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_4 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_4 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_4 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_4 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_5 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_5 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_5 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_5 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_5 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_5 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_5 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_5 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_6 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_6 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_6 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_6 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_6 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_6 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_6 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_6 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_7 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_7 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_7 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_7 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_7 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_7 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_7 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_7 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_8 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_8 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_8 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_8 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_8 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_8 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_8 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_8 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_9 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_9 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_9 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_9 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_9 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_9 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_9 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_9 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_10 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_10 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_10 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_10 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_10 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_10 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_10 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_10 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_11 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_11 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_11 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_11 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_11 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_11 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_11 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_11 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_12 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_12 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_12 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_12 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_12 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_12 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_12 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_12 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_13 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_13 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_13 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_13 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_13 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_13 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_13 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_13 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_14 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_14 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_14 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_14 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_14 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_14 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_14 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_14 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_15 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_15 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_15 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_15 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_15 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_15 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_15 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_15 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL +//SPI_PS_IN_CONTROL +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +#define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L +//SPI_INTERP_CONTROL_0 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +//SPI_SHADER_IDX_FORMAT +#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_POS_FORMAT +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L +//SPI_SHADER_Z_FORMAT +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_COL_FORMAT +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L +//SPI_BARYC_CNTL +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +//SPI_PS_INPUT_ENA +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ENA__COVERAGE_TO_SHADER_SELECT__SHIFT 0x10 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +#define SPI_PS_INPUT_ENA__COVERAGE_TO_SHADER_SELECT_MASK 0x00030000L +//SPI_PS_INPUT_ADDR +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_PS_INPUT_CNTL_0 +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_0__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_0__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_1 +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_1__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_1__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_2 +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_2__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_2__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_3 +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_3__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_3__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_4 +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_4__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_4__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_5 +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_5__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_5__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_6 +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_6__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_6__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_7 +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_7__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_7__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_8 +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_8__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_8__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_9 +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_9__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_9__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_10 +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_10__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_10__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_11 +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_11__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_11__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_12 +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_12__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_12__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_13 +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_13__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_13__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_14 +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_14__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_14__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_15 +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_15__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_15__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_16 +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_16__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_16__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_17 +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_17__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_17__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_18 +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_18__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_18__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_19 +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_19__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_19__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_20 +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_20__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_20__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_21 +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_21__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_21__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_22 +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_22__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_22__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_23 +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_23__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_23__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_24 +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_24__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_24__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_25 +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_25__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_25__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_26 +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_26__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_26__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_27 +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_27__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_27__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_28 +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_28__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_28__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_29 +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_29__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_29__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_30 +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_30__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_30__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_31 +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_31__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_31__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L +//SPI_BARYC_SSAA_CNTL +#define SPI_BARYC_SSAA_CNTL__CENTER_SSAA_MODE__SHIFT 0x0 +#define SPI_BARYC_SSAA_CNTL__CENTROID_SSAA_MODE__SHIFT 0x1 +#define SPI_BARYC_SSAA_CNTL__COVERED_CENTROID_IS_CENTER__SHIFT 0x2 +#define SPI_BARYC_SSAA_CNTL__CENTER_SSAA_MODE_MASK 0x00000001L +#define SPI_BARYC_SSAA_CNTL__CENTROID_SSAA_MODE_MASK 0x00000002L +#define SPI_BARYC_SSAA_CNTL__COVERED_CENTROID_IS_CENTER_MASK 0x00000004L +//SPI_TMPRING_SIZE +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x3FFFF000L +//SPI_GFX_SCRATCH_BASE_LO +#define SPI_GFX_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define SPI_GFX_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//SPI_GFX_SCRATCH_BASE_HI +#define SPI_GFX_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define SPI_GFX_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//SX_PS_DOWNCONVERT_CONTROL +#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT 0x0 +#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT 0x1 +#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT 0x2 +#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT 0x3 +#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT 0x4 +#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT 0x5 +#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT 0x6 +#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT 0x7 +#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK 0x00000001L +#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK 0x00000002L +#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK 0x00000004L +#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK 0x00000008L +#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK 0x00000010L +#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK 0x00000020L +#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK 0x00000040L +#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK 0x00000080L +//SX_PS_DOWNCONVERT +#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 +#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 +#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc +#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 +#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 +#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 +#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c +#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL +#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L +#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L +#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L +#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L +#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L +#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L +#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L +//SX_BLEND_OPT_EPSILON +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L +//SX_BLEND_OPT_CONTROL +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L +//SX_MRT0_BLEND_OPT +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT1_BLEND_OPT +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT2_BLEND_OPT +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT3_BLEND_OPT +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT4_BLEND_OPT +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT5_BLEND_OPT +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT6_BLEND_OPT +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT7_BLEND_OPT +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//CB_BLEND0_CONTROL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND1_CONTROL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND2_CONTROL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND3_CONTROL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND4_CONTROL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND5_CONTROL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND6_CONTROL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND7_CONTROL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//PA_CL_POINT_X_RAD +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_Y_RAD +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_SIZE +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_CULL_RAD +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//GE_MAX_OUTPUT_PER_SUBGROUP +#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0 +#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL +//PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L +//PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +//PA_CL_VS_OUT_CNTL +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b +#define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT 0x1c +#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT 0x1d +#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT 0x1e +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK 0x10000000L +#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK 0x20000000L +#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK 0x40000000L +//PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L +//PA_CL_NANINF_CNTL +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +//PA_SU_LINE_STIPPLE_CNTL +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +//PA_SU_LINE_STIPPLE_SCALE +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL +//PA_SU_PRIM_FILTER_CNTL +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +//PA_SU_SMALL_PRIM_FILTER_CNTL +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L +//PA_CL_NGG_CNTL +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT 0x2 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L +#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK 0x000003FCL +//PA_SU_OVER_RASTERIZATION_CNTL +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L +//PA_STEREO_CNTL +#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 +#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 +#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 +#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10 +#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13 +#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL +#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L +#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L +#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L +#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L +//PA_STATE_STEREO_X +#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 +#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL +//PA_CL_VRS_CNTL +#define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT 0x0 +#define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT 0x3 +#define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT 0x6 +#define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT 0x9 +#define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT 0xd +#define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT 0xe +#define PA_CL_VRS_CNTL__SAMPLE_COVERAGE_ENCODING__SHIFT 0xf +#define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK 0x00000007L +#define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK 0x00000038L +#define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK 0x000001C0L +#define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK 0x00000E00L +#define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK 0x00002000L +#define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK 0x00004000L +#define PA_CL_VRS_CNTL__SAMPLE_COVERAGE_ENCODING_MASK 0x00008000L +//CB_TARGET_MASK +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L +//CB_SHADER_MASK +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L +//CB_COLOR_CONTROL +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT 0x1 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L +#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK 0x00000002L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L +//PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L +//PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L +//PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL +//PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +//PA_SC_LINE_STIPPLE_RESET +#define PA_SC_LINE_STIPPLE_RESET__AUTO_RESET_CNTL__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_RESET__AUTO_RESET_CNTL_MASK 0x00000003L +//PA_SC_MODE_CNTL_0 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 +#define PA_SC_MODE_CNTL_0__IMPLICIT_VPORT_SCISSOR_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L +#define PA_SC_MODE_CNTL_0__IMPLICIT_VPORT_SCISSOR_ENABLE_MASK 0x00000080L +//PA_SC_MODE_CNTL_1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +//GE_SE_ENHANCE +#define GE_SE_ENHANCE__MISC__SHIFT 0x0 +#define GE_SE_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_REUSE_OFF +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +//VGT_DRAW_PAYLOAD_CNTL +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 +#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3 +#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4 +#define VGT_DRAW_PAYLOAD_CNTL__UNUSED__SHIFT 0x5 +#define VGT_DRAW_PAYLOAD_CNTL__EN_VRS_RATE__SHIFT 0x6 +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L +#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L +#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L +#define VGT_DRAW_PAYLOAD_CNTL__UNUSED_MASK 0x00000020L +#define VGT_DRAW_PAYLOAD_CNTL__EN_VRS_RATE_MASK 0x00000040L +//DB_HTILE_SURFACE +#define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0 +#define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2 +#define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3 +#define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4 +#define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 +#define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L +#define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L +#define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L +#define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L +#define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L +//DB_SRESULTS_COMPARE_STATE0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L +//DB_SRESULTS_COMPARE_STATE1 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L +//VGT_GS_MAX_VERT_OUT +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL +//VGT_GS_INSTANCE_CNT +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000000FCL +#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L +//GE_NGG_SUBGRP_CNTL +#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0 +#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9 +#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL +#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L +//PA_SU_POLY_OFFSET_DB_FMT_CNTL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +//PA_SU_POLY_OFFSET_CLAMP +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SC_HIZ_INFO +#define PA_SC_HIZ_INFO__SURFACE_ENABLE__SHIFT 0x0 +#define PA_SC_HIZ_INFO__FORMAT__SHIFT 0x1 +#define PA_SC_HIZ_INFO__SW_MODE__SHIFT 0x2 +#define PA_SC_HIZ_INFO__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x19 +#define PA_SC_HIZ_INFO__SURFACE_ENABLE_MASK 0x00000001L +#define PA_SC_HIZ_INFO__FORMAT_MASK 0x00000002L +#define PA_SC_HIZ_INFO__SW_MODE_MASK 0x0000001CL +#define PA_SC_HIZ_INFO__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x02000000L +//PA_SC_HIS_INFO +#define PA_SC_HIS_INFO__SURFACE_ENABLE__SHIFT 0x0 +#define PA_SC_HIS_INFO__SW_MODE__SHIFT 0x1 +#define PA_SC_HIS_INFO__SURFACE_ENABLE_MASK 0x00000001L +#define PA_SC_HIS_INFO__SW_MODE_MASK 0x0000000EL +//PA_SC_HIZ_BASE +#define PA_SC_HIZ_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_HIZ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_HIZ_BASE_EXT +#define PA_SC_HIZ_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_HIZ_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_HIZ_SIZE_XY +#define PA_SC_HIZ_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_HIZ_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_HIZ_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_HIZ_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//PA_SC_HIS_BASE +#define PA_SC_HIS_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_HIS_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_HIS_BASE_EXT +#define PA_SC_HIS_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_HIS_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_HIS_SIZE_XY +#define PA_SC_HIS_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_HIS_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_HIS_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_HIS_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL +#define PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL__THRESHOLD_MASK 0x0000FFFFL +//PA_SC_BINNER_DYNAMIC_BATCH_LIMIT +#define PA_SC_BINNER_DYNAMIC_BATCH_LIMIT__LIMIT__SHIFT 0x0 +#define PA_SC_BINNER_DYNAMIC_BATCH_LIMIT__LIMIT_MASK 0x000007FFL +//PA_SC_HISZ_CONTROL +#define PA_SC_HISZ_CONTROL__ROUND__SHIFT 0x0 +#define PA_SC_HISZ_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x3 +#define PA_SC_HISZ_CONTROL__ROUND_MASK 0x00000007L +#define PA_SC_HISZ_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00000018L +//PA_SC_HISZ_RENDER_OVERRIDE +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIS_ENABLE__SHIFT 0x2 +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x4 +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x5 +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x6 +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x8 +#define PA_SC_HISZ_RENDER_OVERRIDE__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x9 +#define PA_SC_HISZ_RENDER_OVERRIDE__PRESERVE_ZRANGE__SHIFT 0xa +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_FAST_PASS__SHIFT 0xb +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIS_ENABLE_MASK 0x0000000CL +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000010L +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000020L +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x000000C0L +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x00000100L +#define PA_SC_HISZ_RENDER_OVERRIDE__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000200L +#define PA_SC_HISZ_RENDER_OVERRIDE__PRESERVE_ZRANGE_MASK 0x00000400L +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_FAST_PASS_MASK 0x00000800L +//PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L +//PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_CONFIG__PS_ITER_SAMPLES__SHIFT 0x1e +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__PS_ITER_SAMPLES_MASK 0xC0000000L +//PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +//PA_SC_CENTROID_PRIORITY_0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L +//PA_SC_CENTROID_PRIORITY_1 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_MASK_X0Y0_X1Y0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L +//PA_SC_AA_MASK_X0Y1_X1Y1 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L +//PA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER +#define PA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_CNTL_0 +#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d +#define PA_SC_BINNER_CNTL_0__RESERVED_31__SHIFT 0x1f +#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L +#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L +#define PA_SC_BINNER_CNTL_0__RESERVED_31_MASK 0x80000000L +//PA_SC_BINNER_CNTL_1 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L +//PA_SC_BINNER_CNTL_2 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X__SHIFT 0x1 +#define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_2__RESERVED_LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_2__ZPP_ENABLED__SHIFT 0xb +#define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED__SHIFT 0xc +#define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD__SHIFT 0xd +#define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION__SHIFT 0x15 +#define PA_SC_BINNER_CNTL_2__SBB_ENABLE__SHIFT 0x16 +#define PA_SC_BINNER_CNTL_2__ENABLE_PING_PONG_BIN_ORDER__SHIFT 0x17 +#define PA_SC_BINNER_CNTL_2__PING_PONG_BIN_ORDER_FLIP__SHIFT 0x18 +#define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT 0x1a +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X_MASK 0x00000001L +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X_MASK 0x00000002L +#define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_2__RESERVED_LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN_MASK 0x00000780L +#define PA_SC_BINNER_CNTL_2__ZPP_ENABLED_MASK 0x00000800L +#define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED_MASK 0x00001000L +#define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD_MASK 0x001FE000L +#define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION_MASK 0x00200000L +#define PA_SC_BINNER_CNTL_2__SBB_ENABLE_MASK 0x00400000L +#define PA_SC_BINNER_CNTL_2__ENABLE_PING_PONG_BIN_ORDER_MASK 0x00800000L +#define PA_SC_BINNER_CNTL_2__PING_PONG_BIN_ORDER_FLIP_MASK 0x03000000L +#define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK 0x7C000000L +//PA_SC_NGG_MODE_CNTL +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 +#define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT__SHIFT 0xc +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC__SHIFT 0xd +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0xe +#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10 +#define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x18 +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL +#define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT_MASK 0x00001000L +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC_MASK 0x00002000L +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00004000L +#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L +#define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0xFF000000L +//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L +//PA_SC_SHADER_CONTROL +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 +#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5 +#define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x7 +#define PA_SC_SHADER_CONTROL__PS_ITER_SAMPLE__SHIFT 0x8 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L +#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L +#define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x00000080L +#define PA_SC_SHADER_CONTROL__PS_ITER_SAMPLE_MASK 0x00000100L +//PA_SC_SAMPLE_PROPERTIES +#define PA_SC_SAMPLE_PROPERTIES__MAX_SAMPLE_DIST__SHIFT 0x0 +#define PA_SC_SAMPLE_PROPERTIES__MAX_SAMPLE_DIST_MASK 0x0000000FL +//CB_COLOR0_BASE +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_VIEW +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR0_VIEW2 +#define CB_COLOR0_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR0_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR0_ATTRIB +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR0_FDCC_CONTROL +#define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR0_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR0_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR0_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR0_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR0_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR0_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR0_ATTRIB2 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR0_ATTRIB3 +#define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR0_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR0_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR0_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR0_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR1_BASE +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_VIEW +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR1_VIEW2 +#define CB_COLOR1_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR1_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR1_ATTRIB +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR1_FDCC_CONTROL +#define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR1_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR1_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR1_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR1_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR1_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR1_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR1_ATTRIB2 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR1_ATTRIB3 +#define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR1_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR1_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR1_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR1_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR2_BASE +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_VIEW +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR2_VIEW2 +#define CB_COLOR2_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR2_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR2_ATTRIB +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR2_FDCC_CONTROL +#define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR2_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR2_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR2_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR2_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR2_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR2_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR2_ATTRIB2 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR2_ATTRIB3 +#define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR2_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR2_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR2_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR2_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR3_BASE +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_VIEW +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR3_VIEW2 +#define CB_COLOR3_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR3_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR3_ATTRIB +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR3_FDCC_CONTROL +#define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR3_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR3_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR3_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR3_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR3_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR3_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR3_ATTRIB2 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR3_ATTRIB3 +#define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR3_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR3_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR3_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR3_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR4_BASE +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_VIEW +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR4_VIEW2 +#define CB_COLOR4_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR4_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR4_ATTRIB +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR4_FDCC_CONTROL +#define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR4_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR4_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR4_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR4_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR4_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR4_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR4_ATTRIB2 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR4_ATTRIB3 +#define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR4_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR4_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR4_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR4_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR5_BASE +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_VIEW +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR5_VIEW2 +#define CB_COLOR5_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR5_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR5_ATTRIB +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR5_FDCC_CONTROL +#define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR5_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR5_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR5_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR5_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR5_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR5_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR5_ATTRIB2 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR5_ATTRIB3 +#define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR5_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR5_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR5_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR5_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR6_BASE +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_VIEW +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR6_VIEW2 +#define CB_COLOR6_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR6_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR6_ATTRIB +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR6_FDCC_CONTROL +#define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR6_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR6_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR6_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR6_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR6_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR6_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR6_ATTRIB2 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR6_ATTRIB3 +#define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR6_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR6_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR6_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR6_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR7_BASE +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_VIEW +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR7_VIEW2 +#define CB_COLOR7_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR7_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR7_ATTRIB +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR7_FDCC_CONTROL +#define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR7_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR7_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR7_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR7_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR7_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR7_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR7_ATTRIB2 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR7_ATTRIB3 +#define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR7_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR7_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR7_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR7_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR0_BASE_EXT +#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_BASE_EXT +#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_BASE_EXT +#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_BASE_EXT +#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_BASE_EXT +#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_BASE_EXT +#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_BASE_EXT +#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_BASE_EXT +#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_INFO +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR1_INFO +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR2_INFO +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR3_INFO +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR4_INFO +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR5_INFO +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR6_INFO +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR7_INFO +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_MEM0_INFO +#define CB_MEM0_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM0_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM0_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM0_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM1_INFO +#define CB_MEM1_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM1_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM1_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM1_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM2_INFO +#define CB_MEM2_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM2_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM2_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM2_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM3_INFO +#define CB_MEM3_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM3_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM3_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM3_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM4_INFO +#define CB_MEM4_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM4_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM4_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM4_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM5_INFO +#define CB_MEM5_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM5_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM5_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM5_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM6_INFO +#define CB_MEM6_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM6_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM6_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM6_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM7_INFO +#define CB_MEM7_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM7_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM7_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM7_INFO__TEMPORAL_WRITE_MASK 0x00000038L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_padec +//PA_SC_VRS_SURFACE_CNTL +#define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0x7 +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00000080L +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_ENHANCE +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L +//PA_SC_ENHANCE_1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 +#define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb +#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_COUNT_PIXELS__SHIFT 0xd +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_STILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e +#define PA_SC_ENHANCE_1__RESERVED_31__SHIFT 0x1f +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L +#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L +#define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE_MASK 0x00000020L +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L +#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_COUNT_PIXELS_MASK 0x00002000L +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_STILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L +#define PA_SC_ENHANCE_1__RESERVED_31_MASK 0x80000000L +//PA_SC_ENHANCE_2 +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x2 +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT 0x3 +#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4 +#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7 +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8 +#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9 +#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa +#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb +#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc +#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe +#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf +#define PA_SC_ENHANCE_2__RESERVED_16__SHIFT 0x10 +#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11 +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12 +#define PA_SC_ENHANCE_2__RESERVED_22__SHIFT 0x16 +#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17 +#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a +#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b +#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT 0x1e +#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1f +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000004L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK 0x00000008L +#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L +#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L +#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L +#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L +#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L +#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L +#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L +#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L +#define PA_SC_ENHANCE_2__RESERVED_16_MASK 0x00010000L +#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L +#define PA_SC_ENHANCE_2__RESERVED_22_MASK 0x00400000L +#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L +#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L +#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L +#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK 0x40000000L +#define PA_SC_ENHANCE_2__RSVD_MASK 0x80000000L +//PA_SC_ENHANCE_3 +#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT 0x0 +#define PA_SC_ENHANCE_3__ECO_SPARE2__SHIFT 0x1 +#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST__SHIFT 0x2 +#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 +#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT 0x4 +#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT 0x5 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER__SHIFT 0x6 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER__SHIFT 0x7 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS__SHIFT 0x8 +#define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY__SHIFT 0x9 +#define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT 0xa +#define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION__SHIFT 0xb +#define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED__SHIFT 0xc +#define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0xd +#define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION__SHIFT 0xe +#define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN__SHIFT 0xf +#define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS__SHIFT 0x10 +#define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM__SHIFT 0x11 +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x14 +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x15 +#define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE__SHIFT 0x16 +#define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION__SHIFT 0x17 +#define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY__SHIFT 0x18 +#define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL__SHIFT 0x19 +#define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL__SHIFT 0x1a +#define PA_SC_ENHANCE_3__APPLY_AA_MASK_AT_EXPOSED_RATE_FOR_VRS_COURSE_QUADS_WITH_CR__SHIFT 0x1b +#define PA_SC_ENHANCE_3__ECO_SPARE0__SHIFT 0x1c +#define PA_SC_ENHANCE_3__ECO_SPARE1__SHIFT 0x1d +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_SRC_FINE_CLOCK_GATE__SHIFT 0x1e +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_REQ_FINE_CLOCK_GATE__SHIFT 0x1f +#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK 0x00000001L +#define PA_SC_ENHANCE_3__ECO_SPARE2_MASK 0x00000002L +#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST_MASK 0x00000004L +#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L +#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK 0x00000010L +#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK 0x00000020L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER_MASK 0x00000040L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_MASK 0x00000080L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS_MASK 0x00000100L +#define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY_MASK 0x00000200L +#define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES_MASK 0x00000400L +#define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION_MASK 0x00000800L +#define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED_MASK 0x00001000L +#define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00002000L +#define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION_MASK 0x00004000L +#define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN_MASK 0x00008000L +#define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS_MASK 0x00010000L +#define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM_MASK 0x00020000L +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00100000L +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00200000L +#define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE_MASK 0x00400000L +#define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION_MASK 0x00800000L +#define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY_MASK 0x01000000L +#define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL_MASK 0x02000000L +#define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL_MASK 0x04000000L +#define PA_SC_ENHANCE_3__APPLY_AA_MASK_AT_EXPOSED_RATE_FOR_VRS_COURSE_QUADS_WITH_CR_MASK 0x08000000L +#define PA_SC_ENHANCE_3__ECO_SPARE0_MASK 0x10000000L +#define PA_SC_ENHANCE_3__ECO_SPARE1_MASK 0x20000000L +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_SRC_FINE_CLOCK_GATE_MASK 0x40000000L +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_REQ_FINE_CLOCK_GATE_MASK 0x80000000L +//PA_SC_BINNER_CNTL_OVERRIDE +#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L +//PA_SC_PBB_OVERRIDE_FLAG +#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0 +#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1 +#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L +#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L +//PA_SC_DSM_CNTL +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L +//PA_SC_TILE_STEERING_CREST_OVERRIDE +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L +//PA_SC_FIFO_SIZE +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L +//PA_SC_IF_FIFO_SIZE +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L +//PA_SC_PACKER_WAVE_ID_CNTL +#define PA_SC_PACKER_WAVE_ID_CNTL__WAVES_IN_FLIGHT_LIMIT__SHIFT 0x0 +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT 0xa +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN__SHIFT 0x10 +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE__SHIFT 0x11 +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN__SHIFT 0x17 +#define PA_SC_PACKER_WAVE_ID_CNTL__DEBUG_CONFLICT_QUAD__SHIFT 0x18 +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x1f +#define PA_SC_PACKER_WAVE_ID_CNTL__WAVES_IN_FLIGHT_LIMIT_MASK 0x000001FFL +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE_MASK 0x0000FC00L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN_MASK 0x00010000L +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE_MASK 0x007E0000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN_MASK 0x00800000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DEBUG_CONFLICT_QUAD_MASK 0x0F000000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x80000000L +//PA_SC_ATM_CNTL +#define PA_SC_ATM_CNTL__SC_PC_IF_SIZE__SHIFT 0x0 +#define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN__SHIFT 0x7 +#define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x8 +#define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0x10 +#define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES__SHIFT 0x11 +#define PA_SC_ATM_CNTL__SC_PC_IF_SIZE_MASK 0x0000003FL +#define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN_MASK 0x00000080L +#define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0x0000FF00L +#define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00010000L +#define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES_MASK 0x00020000L +//PA_SC_PKR_WAVE_TABLE_CNTL +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL +//PA_SC_FORCE_EOV_MAX_CNTS +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L +//PA_SC_BINNER_EVENT_CNTL_0 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_0__EVENT_STATE_CHANGE__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_0__EVENT_STATE_CHANGE_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_1 +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_2 +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_3 +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L +//PA_SC_BINNER_TIMEOUT_COUNTER +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_PERF_CNTL_0 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L +//PA_SC_BINNER_PERF_CNTL_1 +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L +//PA_SC_BINNER_PERF_CNTL_2 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L +//PA_SC_BINNER_PERF_CNTL_3 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_P3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_TRAP_SCREEN_HV_LOCK +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_PH_INTERFACE_FIFO_SIZE +#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10 +#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL +#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L +//PA_PH_ENHANCE +#define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0 +#define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1 +#define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2 +#define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3 +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4 +#define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5 +#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6 +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7 +#define PA_PH_ENHANCE__DISABLE_PH_DEBUG_REG_FGCG__SHIFT 0x8 +#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9 +#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa +#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT 0xd +#define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS__SHIFT 0xe +#define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON__SHIFT 0xf +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE__SHIFT 0x10 +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE__SHIFT 0x11 +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE__SHIFT 0x12 +#define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L +#define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L +#define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L +#define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L +#define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L +#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L +#define PA_PH_ENHANCE__DISABLE_PH_DEBUG_REG_FGCG_MASK 0x00000100L +#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L +#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L +#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK 0x00002000L +#define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS_MASK 0x00004000L +#define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON_MASK 0x00008000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_MASK 0x00010000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE_MASK 0x00020000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE_MASK 0x00040000L +//PA_SC_VRS_SURFACE_CNTL_1 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE__SHIFT 0x0 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE__SHIFT 0x1 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE__SHIFT 0x2 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_16XAA__SHIFT 0x3 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL__SHIFT 0x4 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED__SHIFT 0x5 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT__SHIFT 0x6 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS__SHIFT 0x7 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_8XAA__SHIFT 0x8 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTRINSIC_RATE_GT_4XAA__SHIFT 0x9 +#define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG__SHIFT 0xa +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION__SHIFT 0xc +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE__SHIFT 0xf +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE__SHIFT 0x13 +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING__SHIFT 0x14 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0__SHIFT 0x15 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1__SHIFT 0x16 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2__SHIFT 0x17 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3__SHIFT 0x18 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4__SHIFT 0x19 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5__SHIFT 0x1a +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6__SHIFT 0x1b +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7__SHIFT 0x1c +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8__SHIFT 0x1d +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9__SHIFT 0x1e +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10__SHIFT 0x1f +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK 0x00000001L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE_MASK 0x00000002L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE_MASK 0x00000004L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_16XAA_MASK 0x00000008L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL_MASK 0x00000010L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED_MASK 0x00000020L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT_MASK 0x00000040L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS_MASK 0x00000080L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_8XAA_MASK 0x00000100L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTRINSIC_RATE_GT_4XAA_MASK 0x00000200L +#define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG_MASK 0x00000400L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION_MASK 0x00001000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE_MASK 0x00008000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE_MASK 0x00080000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING_MASK 0x00100000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0_MASK 0x00200000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1_MASK 0x00400000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2_MASK 0x00800000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3_MASK 0x01000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4_MASK 0x02000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5_MASK 0x04000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6_MASK 0x08000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7_MASK 0x10000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8_MASK 0x20000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9_MASK 0x40000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10_MASK 0x80000000L +//PA_SC_HIZ_SURFACE_CNTL +#define PA_SC_HIZ_SURFACE_CNTL__HZC_OUTSTANDING_CONTEXT_FILTERING_DISABLE__SHIFT 0x5 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_DB_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x7 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_HIZ_SURFACE_CNTL__HZC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_HIZ_SURFACE_CNTL__HZC_OUTSTANDING_CONTEXT_FILTERING_DISABLE_MASK 0x00000020L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_DB_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000080L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_HIS_SURFACE_CNTL +#define PA_SC_HIS_SURFACE_CNTL__HSC_OUTSTANDING_CONTEXT_FILTERING_DISABLE__SHIFT 0x5 +#define PA_SC_HIS_SURFACE_CNTL__HSC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_HIS_SURFACE_CNTL__HSC_DB_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x7 +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_HIS_SURFACE_CNTL__HSC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_HIS_SURFACE_CNTL__HSC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_HIS_SURFACE_CNTL__HSC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_HIS_SURFACE_CNTL__HSC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_HIS_SURFACE_CNTL__HSC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_HIS_SURFACE_CNTL__HSC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_HIS_SURFACE_CNTL__HSC_OUTSTANDING_CONTEXT_FILTERING_DISABLE_MASK 0x00000020L +#define PA_SC_HIS_SURFACE_CNTL__HSC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_HIS_SURFACE_CNTL__HSC_DB_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000080L +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_HIS_SURFACE_CNTL__HSC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_HIZ_DEBUG +#define PA_SC_HIZ_DEBUG__FORCE_Z_MODE__SHIFT 0x1 +#define PA_SC_HIZ_DEBUG__FORCE_DEPTH_READ__SHIFT 0x3 +#define PA_SC_HIZ_DEBUG__FORCE_HIZ_ENABLE__SHIFT 0x4 +#define PA_SC_HIZ_DEBUG__FAST_Z_DISABLE__SHIFT 0x6 +#define PA_SC_HIZ_DEBUG__NOOP_CULL_DISABLE__SHIFT 0x7 +#define PA_SC_HIZ_DEBUG__FORCE_TILE_OP__SHIFT 0x8 +#define PA_SC_HIZ_DEBUG__FORCE_HITEST_RESULTS__SHIFT 0xc +#define PA_SC_HIZ_DEBUG__DISABLE_4X_TILE_PICKING__SHIFT 0x11 +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_SET_WITHOUT_HIZ_SURFACE__SHIFT 0x12 +#define PA_SC_HIZ_DEBUG__FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define PA_SC_HIZ_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_HIZ_DEBUG__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x16 +#define PA_SC_HIZ_DEBUG__DISABLE_VPZ_EVENT_FILTERING__SHIFT 0x17 +#define PA_SC_HIZ_DEBUG__DISABLE_REPLICATE_DETAIL_LOCATIONS_TO_SURFACE_RATE_FOR_SURF_GT_DETAIL_RATE__SHIFT 0x18 +#define PA_SC_HIZ_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY__SHIFT 0x19 +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE__SHIFT 0x1a +#define PA_SC_HIZ_DEBUG__FORCE_Z_MODE_MASK 0x00000006L +#define PA_SC_HIZ_DEBUG__FORCE_DEPTH_READ_MASK 0x00000008L +#define PA_SC_HIZ_DEBUG__FORCE_HIZ_ENABLE_MASK 0x00000030L +#define PA_SC_HIZ_DEBUG__FAST_Z_DISABLE_MASK 0x00000040L +#define PA_SC_HIZ_DEBUG__NOOP_CULL_DISABLE_MASK 0x00000080L +#define PA_SC_HIZ_DEBUG__FORCE_TILE_OP_MASK 0x00000F00L +#define PA_SC_HIZ_DEBUG__FORCE_HITEST_RESULTS_MASK 0x0001F000L +#define PA_SC_HIZ_DEBUG__DISABLE_4X_TILE_PICKING_MASK 0x00020000L +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_SET_WITHOUT_HIZ_SURFACE_MASK 0x00040000L +#define PA_SC_HIZ_DEBUG__FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define PA_SC_HIZ_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_HIZ_DEBUG__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00400000L +#define PA_SC_HIZ_DEBUG__DISABLE_VPZ_EVENT_FILTERING_MASK 0x00800000L +#define PA_SC_HIZ_DEBUG__DISABLE_REPLICATE_DETAIL_LOCATIONS_TO_SURFACE_RATE_FOR_SURF_GT_DETAIL_RATE_MASK 0x01000000L +#define PA_SC_HIZ_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY_MASK 0x02000000L +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE_MASK 0x04000000L +//PA_SC_HIS_DEBUG +#define PA_SC_HIS_DEBUG__FORCE_STENCIL_READ__SHIFT 0x1 +#define PA_SC_HIS_DEBUG__FORCE_HIS_ENABLE__SHIFT 0x2 +#define PA_SC_HIS_DEBUG__FAST_STENCIL_DISABLE__SHIFT 0x6 +#define PA_SC_HIS_DEBUG__NOOP_CULL_DISABLE__SHIFT 0x7 +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_PRE_HISZ__SHIFT 0x8 +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_POST_HISZ__SHIFT 0x9 +#define PA_SC_HIS_DEBUG__DROP_UNLIT_STILES_AFTER_DETAIL_WALK__SHIFT 0xa +#define PA_SC_HIS_DEBUG__DROP_DUPLICATE_SC_DB_STILE_UPDATE_BEFORE_DETAIL_WALK__SHIFT 0xb +#define PA_SC_HIS_DEBUG__FULLY_COVERED_IS_STILE_QUAD_MASK_BASED__SHIFT 0xc +#define PA_SC_HIS_DEBUG__FORCE_SURFACE_ENABLED_TO_HISZ__SHIFT 0xd +#define PA_SC_HIS_DEBUG__USE_DETAIL_RATE_IN_PRE_HISZ_STW__SHIFT 0xe +#define PA_SC_HIS_DEBUG__DISABLE_SINGLE_STENCIL__SHIFT 0xf +#define PA_SC_HIS_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY__SHIFT 0x10 +#define PA_SC_HIS_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE__SHIFT 0x11 +#define PA_SC_HIS_DEBUG__FORCE_STENCIL_READ_MASK 0x00000002L +#define PA_SC_HIS_DEBUG__FORCE_HIS_ENABLE_MASK 0x0000000CL +#define PA_SC_HIS_DEBUG__FAST_STENCIL_DISABLE_MASK 0x00000040L +#define PA_SC_HIS_DEBUG__NOOP_CULL_DISABLE_MASK 0x00000080L +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_PRE_HISZ_MASK 0x00000100L +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_POST_HISZ_MASK 0x00000200L +#define PA_SC_HIS_DEBUG__DROP_UNLIT_STILES_AFTER_DETAIL_WALK_MASK 0x00000400L +#define PA_SC_HIS_DEBUG__DROP_DUPLICATE_SC_DB_STILE_UPDATE_BEFORE_DETAIL_WALK_MASK 0x00000800L +#define PA_SC_HIS_DEBUG__FULLY_COVERED_IS_STILE_QUAD_MASK_BASED_MASK 0x00001000L +#define PA_SC_HIS_DEBUG__FORCE_SURFACE_ENABLED_TO_HISZ_MASK 0x00002000L +#define PA_SC_HIS_DEBUG__USE_DETAIL_RATE_IN_PRE_HISZ_STW_MASK 0x00004000L +#define PA_SC_HIS_DEBUG__DISABLE_SINGLE_STENCIL_MASK 0x00008000L +#define PA_SC_HIS_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY_MASK 0x00010000L +#define PA_SC_HIS_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE_MASK 0x00020000L +//SC_MEM_SCOPE +#define SC_MEM_SCOPE__VRS_RATE_SCOPE__SHIFT 0x0 +#define SC_MEM_SCOPE__VRS_FEEDBACK_SCOPE__SHIFT 0x2 +#define SC_MEM_SCOPE__HIZ_SCOPE__SHIFT 0x4 +#define SC_MEM_SCOPE__HIS_SCOPE__SHIFT 0x6 +#define SC_MEM_SCOPE__VRS_RATE_SCOPE_MASK 0x00000003L +#define SC_MEM_SCOPE__VRS_FEEDBACK_SCOPE_MASK 0x0000000CL +#define SC_MEM_SCOPE__HIZ_SCOPE_MASK 0x00000030L +#define SC_MEM_SCOPE__HIS_SCOPE_MASK 0x000000C0L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_sqdec +//SQ_RUNTIME_CONFIG +#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0 +#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L +//SQ_DEBUG_STS_GLOBAL +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000FFF0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0FFF0000L +//SQ_DEBUG_STS_GLOBAL2 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0_MASK 0x000000FFL +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1_MASK 0x0000FF00L +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE_MASK 0x00FF0000L +//SH_MEM_BASES +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0xa +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FC00L +#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L +//SH_MEM_CONFIG +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 +#define SH_MEM_CONFIG__F8_MODE__SHIFT 0x8 +#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe +#define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12 +#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0x13 +#define SH_MEM_CONFIG__RETRY_DEBUG__SHIFT 0x14 +#define SH_MEM_CONFIG__XCNT_DEBUG__SHIFT 0x15 +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000004L +#define SH_MEM_CONFIG__F8_MODE_MASK 0x00000100L +#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L +#define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L +#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00080000L +#define SH_MEM_CONFIG__RETRY_DEBUG_MASK 0x00100000L +#define SH_MEM_CONFIG__XCNT_DEBUG_MASK 0x00200000L +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 +#define SQ_DEBUG__SINGLE_ALU_OP__SHIFT 0x1 +#define SQ_DEBUG__WAIT_DEP_CTR_ZERO__SHIFT 0x2 +#define SQ_DEBUG__SU_VDST_WKILL_DIS__SHIFT 0x3 +#define SQ_DEBUG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x4 +#define SQ_DEBUG__DISABLE_VGPR_DEALLOC__SHIFT 0x5 +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +#define SQ_DEBUG__SINGLE_ALU_OP_MASK 0x00000002L +#define SQ_DEBUG__WAIT_DEP_CTR_ZERO_MASK 0x00000004L +#define SQ_DEBUG__SU_VDST_WKILL_DIS_MASK 0x00000008L +#define SQ_DEBUG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000010L +#define SQ_DEBUG__DISABLE_VGPR_DEALLOC_MASK 0x00000020L +//SQ_SHADER_TBA_LO +#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TBA_HI +#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f +#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x0001FFFFL +#define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L +//SQ_SHADER_TMA_LO +#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TMA_HI +#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x0001FFFFL +//SQ_IND_INDEX_USER +#define SQ_IND_INDEX_USER__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX_USER__WORKITEM_ID__SHIFT 0x5 +#define SQ_IND_INDEX_USER__AUTO_INCR__SHIFT 0xb +#define SQ_IND_INDEX_USER__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX_USER__WAVE_ID_MASK 0x0000001FL +#define SQ_IND_INDEX_USER__WORKITEM_ID_MASK 0x000007E0L +#define SQ_IND_INDEX_USER__AUTO_INCR_MASK 0x00000800L +#define SQ_IND_INDEX_USER__INDEX_MASK 0xFFFF0000L +//SQ_CMD_USER +#define SQ_CMD_USER__CMD__SHIFT 0x0 +#define SQ_CMD_USER__MODE__SHIFT 0x4 +#define SQ_CMD_USER__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD_USER__DATA__SHIFT 0x8 +#define SQ_CMD_USER__WAVE_ID__SHIFT 0x10 +#define SQ_CMD_USER__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD_USER__VM_ID__SHIFT 0x1c +#define SQ_CMD_USER__CMD_MASK 0x0000000FL +#define SQ_CMD_USER__MODE_MASK 0x00000070L +#define SQ_CMD_USER__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD_USER__DATA_MASK 0x00000F00L +#define SQ_CMD_USER__WAVE_ID_MASK 0x001F0000L +#define SQ_CMD_USER__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD_USER__VM_ID_MASK 0xF0000000L +//SQ_IND_DATA_USER +#define SQ_IND_DATA_USER__DATA__SHIFT 0x0 +#define SQ_IND_DATA_USER__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_spidec +//SPI_CDBG_SYS_GFX +#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x00000001L +#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x00000004L +#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x00000010L +#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x00000040L +//SPI_CDBG_SYS_HP3D +#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_HP3D__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x00000001L +#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x00000004L +#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x00000010L +#define SPI_CDBG_SYS_HP3D__CS_EN_MASK 0x00000040L +//SPI_CDBG_SYS_CS0 +#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL +#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L +#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L +#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_STATUS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH_MASK 0x00000002L +#define SPI_GDBG_WAVE_CNTL__STALL_STATUS_MASK 0x00000004L +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_RESET_DEBUG +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x00000001L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x00000002L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x00000004L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x00000008L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x00000010L +//GDS_COMPUTE_MAX_WAVE_ID +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//SPI_ARB_CNTL_0 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L +//SPI_FEATURE_CTRL +#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x0 +#define SPI_FEATURE_CTRL__RA_PROBE_IGNORE__SHIFT 0x4 +#define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT__SHIFT 0x5 +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL__SHIFT 0xb +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL__SHIFT 0xd +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE__SHIFT 0xe +#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0x0000000FL +#define SPI_FEATURE_CTRL__RA_PROBE_IGNORE_MASK 0x00000010L +#define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT_MASK 0x000007E0L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL_MASK 0x00001800L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL_MASK 0x00002000L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE_MASK 0x00004000L +//SPI_SHADER_RSRC_LIMIT_CTRL +#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0 +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5 +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13 +#define SPI_SHADER_RSRC_LIMIT_CTRL__NAMED_BARRIER_LIMIT__SHIFT 0x14 +#define SPI_SHADER_RSRC_LIMIT_CTRL__CLUSTER_LIMIT__SHIFT 0x1c +#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f +#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__NAMED_BARRIER_LIMIT_MASK 0x00F00000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__CLUSTER_LIMIT_MASK 0x70000000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L +//PC_CONFIG_CNTL_0 +#define PC_CONFIG_CNTL_0__PQ_FIFO_DEPTH__SHIFT 0x0 +#define PC_CONFIG_CNTL_0__READ_RET_DEPTH__SHIFT 0x5 +#define PC_CONFIG_CNTL_0__MAX_PRIMS_PER_PROBE__SHIFT 0xa +#define PC_CONFIG_CNTL_0__GL1_CREDIT_COUNT__SHIFT 0xe +#define PC_CONFIG_CNTL_0__SC_PC_RATE_CNTL__SHIFT 0x12 +#define PC_CONFIG_CNTL_0__MW_PQ_RATE_CNTL__SHIFT 0x16 +#define PC_CONFIG_CNTL_0__PC_DEALLOC_TIMEOUT__SHIFT 0x1a +#define PC_CONFIG_CNTL_0__MW_DISABLE_EARLY_HIT__SHIFT 0x1e +#define PC_CONFIG_CNTL_0__DISABLE_DEALLOC_ON_TIMEOUT__SHIFT 0x1f +#define PC_CONFIG_CNTL_0__PQ_FIFO_DEPTH_MASK 0x0000001FL +#define PC_CONFIG_CNTL_0__READ_RET_DEPTH_MASK 0x000003E0L +#define PC_CONFIG_CNTL_0__MAX_PRIMS_PER_PROBE_MASK 0x00003C00L +#define PC_CONFIG_CNTL_0__GL1_CREDIT_COUNT_MASK 0x0003C000L +#define PC_CONFIG_CNTL_0__SC_PC_RATE_CNTL_MASK 0x003C0000L +#define PC_CONFIG_CNTL_0__MW_PQ_RATE_CNTL_MASK 0x03C00000L +#define PC_CONFIG_CNTL_0__PC_DEALLOC_TIMEOUT_MASK 0x3C000000L +#define PC_CONFIG_CNTL_0__MW_DISABLE_EARLY_HIT_MASK 0x40000000L +#define PC_CONFIG_CNTL_0__DISABLE_DEALLOC_ON_TIMEOUT_MASK 0x80000000L +//PC_CONFIG_CNTL_1 +#define PC_CONFIG_CNTL_1__DISABLE_LWC_SLOT_REUSE__SHIFT 0x0 +#define PC_CONFIG_CNTL_1__DISABLE_LWC_WAVE_REUSE__SHIFT 0x1 +#define PC_CONFIG_CNTL_1__LIMIT_BANK_ACCESS__SHIFT 0x2 +#define PC_CONFIG_CNTL_1__FORCE_BANK_SERIALIZE__SHIFT 0x3 +#define PC_CONFIG_CNTL_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x4 +#define PC_CONFIG_CNTL_1__DEBUG_REG_EN__SHIFT 0x5 +#define PC_CONFIG_CNTL_1__DEBUG_GROUP_SEL__SHIFT 0x6 +#define PC_CONFIG_CNTL_1__FORCE_SA_SERIALIZE__SHIFT 0xc +#define PC_CONFIG_CNTL_1__PC_GL1H_FGCG_OVERRIDE__SHIFT 0xd +#define PC_CONFIG_CNTL_1__PC_LDS_FGCG_OVERRIDE__SHIFT 0xe +#define PC_CONFIG_CNTL_1__PC_MAX_BCD__SHIFT 0xf +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_EVENT__SHIFT 0x11 +#define PC_CONFIG_CNTL_1__MAX_PSTATE_IDS__SHIFT 0x12 +#define PC_CONFIG_CNTL_1__MAX_PC_SPI_PROBES__SHIFT 0x14 +#define PC_CONFIG_CNTL_1__CMM_USE_POLICY__SHIFT 0x18 +#define PC_CONFIG_CNTL_1__SPECULATIVE_DATA_READ__SHIFT 0x1b +#define PC_CONFIG_CNTL_1__CMM_SCOPE__SHIFT 0x1d +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_PC_IDLE__SHIFT 0x1f +#define PC_CONFIG_CNTL_1__DISABLE_LWC_SLOT_REUSE_MASK 0x00000001L +#define PC_CONFIG_CNTL_1__DISABLE_LWC_WAVE_REUSE_MASK 0x00000002L +#define PC_CONFIG_CNTL_1__LIMIT_BANK_ACCESS_MASK 0x00000004L +#define PC_CONFIG_CNTL_1__FORCE_BANK_SERIALIZE_MASK 0x00000008L +#define PC_CONFIG_CNTL_1__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00000010L +#define PC_CONFIG_CNTL_1__DEBUG_REG_EN_MASK 0x00000020L +#define PC_CONFIG_CNTL_1__DEBUG_GROUP_SEL_MASK 0x00000FC0L +#define PC_CONFIG_CNTL_1__FORCE_SA_SERIALIZE_MASK 0x00001000L +#define PC_CONFIG_CNTL_1__PC_GL1H_FGCG_OVERRIDE_MASK 0x00002000L +#define PC_CONFIG_CNTL_1__PC_LDS_FGCG_OVERRIDE_MASK 0x00004000L +#define PC_CONFIG_CNTL_1__PC_MAX_BCD_MASK 0x00018000L +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_EVENT_MASK 0x00020000L +#define PC_CONFIG_CNTL_1__MAX_PSTATE_IDS_MASK 0x000C0000L +#define PC_CONFIG_CNTL_1__MAX_PC_SPI_PROBES_MASK 0x00F00000L +#define PC_CONFIG_CNTL_1__CMM_USE_POLICY_MASK 0x07000000L +#define PC_CONFIG_CNTL_1__SPECULATIVE_DATA_READ_MASK 0x18000000L +#define PC_CONFIG_CNTL_1__CMM_SCOPE_MASK 0x60000000L +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_PC_IDLE_MASK 0x80000000L +//SPI_COMPUTE_WF_CTX_SAVE_STATUS +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY__SHIFT 0x3 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY__SHIFT 0x4 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY__SHIFT 0x5 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY__SHIFT 0x6 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY__SHIFT 0x7 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY__SHIFT 0x8 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY__SHIFT 0x9 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT 0xa +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY__SHIFT 0xb +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY__SHIFT 0xc +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY__SHIFT 0xd +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY__SHIFT 0xe +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY__SHIFT 0xf +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY__SHIFT 0x10 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY__SHIFT 0x11 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY__SHIFT 0x12 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY__SHIFT 0x13 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY__SHIFT 0x14 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY__SHIFT 0x15 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY__SHIFT 0x16 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY__SHIFT 0x17 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY__SHIFT 0x18 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY__SHIFT 0x19 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY__SHIFT 0x1a +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY__SHIFT 0x1b +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY__SHIFT 0x1c +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY__SHIFT 0x1d +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY_MASK 0x00000008L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY_MASK 0x00000010L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY_MASK 0x00000020L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY_MASK 0x00000040L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY_MASK 0x00000080L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY_MASK 0x00000100L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY_MASK 0x00000200L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY_MASK 0x00000400L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY_MASK 0x00000800L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY_MASK 0x00001000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY_MASK 0x00002000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY_MASK 0x00004000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY_MASK 0x00008000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY_MASK 0x00010000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY_MASK 0x00020000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY_MASK 0x00040000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY_MASK 0x00080000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY_MASK 0x00100000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY_MASK 0x00200000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY_MASK 0x00400000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY_MASK 0x00800000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY_MASK 0x01000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY_MASK 0x02000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY_MASK 0x04000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY_MASK 0x08000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY_MASK 0x10000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY_MASK 0x20000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_utcl1dec +//UTCL1_CTRL_0 +#define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE__SHIFT 0x0 +#define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE__SHIFT 0x1 +#define UTCL1_CTRL_0__UTCL1_MH_B2B_DUPLICATES_DET_DISABLE__SHIFT 0x2 +#define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_UNIFIED_IF__SHIFT 0x3 +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS__SHIFT 0x9 +#define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE__SHIFT 0xd +#define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE__SHIFT 0xe +#define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xf +#define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID__SHIFT 0x10 +#define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0x11 +#define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0x12 +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT 0x13 +#define UTCL1_CTRL_0__GCRD_FGCG_DISABLE__SHIFT 0x14 +#define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE__SHIFT 0x15 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x16 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x17 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x18 +#define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL__SHIFT 0x19 +#define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1b +#define UTCL1_CTRL_0__UTCL1_HIT_DETECTION_BASED_ON_PAGE_SIZE__SHIFT 0x1d +#define UTCL1_CTRL_0__UTCL1_MH_DUPL_DETECT_ON_NATIVE_PG_SZ__SHIFT 0x1e +#define UTCL1_CTRL_0__UTCL1_FORCE_INV_ALL__SHIFT 0x1f +#define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE_MASK 0x00000001L +#define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE_MASK 0x00000002L +#define UTCL1_CTRL_0__UTCL1_MH_B2B_DUPLICATES_DET_DISABLE_MASK 0x00000004L +#define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_UNIFIED_IF_MASK 0x000001F8L +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS_MASK 0x00001E00L +#define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE_MASK 0x00002000L +#define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE_MASK 0x00004000L +#define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00008000L +#define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID_MASK 0x00010000L +#define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00020000L +#define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00040000L +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK 0x00080000L +#define UTCL1_CTRL_0__GCRD_FGCG_DISABLE_MASK 0x00100000L +#define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE_MASK 0x00200000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00400000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00800000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x01000000L +#define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL_MASK 0x06000000L +#define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE_MASK 0x18000000L +#define UTCL1_CTRL_0__UTCL1_HIT_DETECTION_BASED_ON_PAGE_SIZE_MASK 0x20000000L +#define UTCL1_CTRL_0__UTCL1_MH_DUPL_DETECT_ON_NATIVE_PG_SZ_MASK 0x40000000L +#define UTCL1_CTRL_0__UTCL1_FORCE_INV_ALL_MASK 0x80000000L +//UTCL1_UTCL0_INVREQ_DISABLE +#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0 +#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0xFFFFFFFFL +//UTCL1_CTRL_2 +#define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD__SHIFT 0x0 +#define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE__SHIFT 0x4 +#define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT 0xa +#define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE__SHIFT 0xb +#define UTCL1_CTRL_2__UTCL1_SPARE0__SHIFT 0xc +#define UTCL1_CTRL_2__UTCL2_UTCL1_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0xd +#define UTCL1_CTRL_2__UTCL1_IDENTITY_MODE_CONFIG_SELECTOR__SHIFT 0xe +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SA01__SHIFT 0x14 +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SAX__SHIFT 0x1a +#define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD_MASK 0x0000000FL +#define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE_MASK 0x000003F0L +#define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM_MASK 0x00000400L +#define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE_MASK 0x00000800L +#define UTCL1_CTRL_2__UTCL1_SPARE0_MASK 0x00001000L +#define UTCL1_CTRL_2__UTCL2_UTCL1_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00002000L +#define UTCL1_CTRL_2__UTCL1_IDENTITY_MODE_CONFIG_SELECTOR_MASK 0x000FC000L +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SA01_MASK 0x03F00000L +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SAX_MASK 0xFC000000L +//UTCL1_FIFO_SIZING +#define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH__SHIFT 0x0 +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW__SHIFT 0x3 +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH__SHIFT 0x10 +#define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH_MASK 0x00000007L +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW_MASK 0x0000FFF8L +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH_MASK 0xFFFF0000L +//GCRD_SA0_TARGETS_DISABLE +#define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE__SHIFT 0x0 +#define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE_MASK 0x00FFFFFFL +//GCRD_SA1_TARGETS_DISABLE +#define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE__SHIFT 0x0 +#define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE_MASK 0x00FFFFFFL +//GCRD_CREDIT_SAFE +#define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG__SHIFT 0x0 +#define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG__SHIFT 0x4 +#define GCRD_CREDIT_SAFE__GCRD_RSP_CREDIT_SAFE_REG__SHIFT 0x8 +#define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG_MASK 0x00000007L +#define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG_MASK 0x00000070L +#define GCRD_CREDIT_SAFE__GCRD_RSP_CREDIT_SAFE_REG_MASK 0x00000F00L +//UTCL1_IDENTITY_MODE0 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE0__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE0__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE1 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE1__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE1__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE2 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE2__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE2__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE3 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE3__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE3__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE4 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE4__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE4__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE5 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE5__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE5__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE6 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE6__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE6__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE7 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE7__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE7__RESERVED_MASK 0xFE000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_tcpdec +//TCP_INVALIDATE +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_INVALIDATE__START_MASK 0x00000001L +//TCP_STATUS +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY_PORT0__SHIFT 0x1 +#define TCP_STATUS__INPUT_BUSY_PORT1__SHIFT 0x2 +#define TCP_STATUS__ADRS_BUSY_PORT0__SHIFT 0x3 +#define TCP_STATUS__ADRS_BUSY_PORT1__SHIFT 0x4 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x5 +#define TCP_STATUS__VM_BUSY__SHIFT 0x6 +#define TCP_STATUS__MEMIF_BUSY__SHIFT 0x7 +#define TCP_STATUS__GCR_BUSY__SHIFT 0x8 +#define TCP_STATUS__CNTRL_BUSY_PORT0__SHIFT 0x9 +#define TCP_STATUS__CNTRL_BUSY_PORT1__SHIFT 0xa +#define TCP_STATUS__LFIFO_BUSY_PORT0__SHIFT 0xb +#define TCP_STATUS__LFIFO_BUSY_PORT1__SHIFT 0xc +#define TCP_STATUS__OFIFO_BUSY_PORT0__SHIFT 0xd +#define TCP_STATUS__OFIFO_BUSY_PORT1__SHIFT 0xe +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT0__SHIFT 0xf +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT1__SHIFT 0x12 +#define TCP_STATUS__READ_BUSY_PORT1__SHIFT 0x15 +#define TCP_STATUS__READ_BUSY_PORT0__SHIFT 0x16 +#define TCP_STATUS__CL_PENDING__SHIFT 0x17 +#define TCP_STATUS__VRX_BUSY__SHIFT 0x18 +#define TCP_STATUS__PKR_BUSY_PORT0__SHIFT 0x19 +#define TCP_STATUS__PKR_BUSY_PORT1__SHIFT 0x1a +#define TCP_STATUS__LDS_BUSY_PORT0__SHIFT 0x1b +#define TCP_STATUS__LDS_BUSY_PORT1__SHIFT 0x1c +#define TCP_STATUS__XNACK_PRT__SHIFT 0x1d +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__INPUT_BUSY_PORT0_MASK 0x00000002L +#define TCP_STATUS__INPUT_BUSY_PORT1_MASK 0x00000004L +#define TCP_STATUS__ADRS_BUSY_PORT0_MASK 0x00000008L +#define TCP_STATUS__ADRS_BUSY_PORT1_MASK 0x00000010L +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000020L +#define TCP_STATUS__VM_BUSY_MASK 0x00000040L +#define TCP_STATUS__MEMIF_BUSY_MASK 0x00000080L +#define TCP_STATUS__GCR_BUSY_MASK 0x00000100L +#define TCP_STATUS__CNTRL_BUSY_PORT0_MASK 0x00000200L +#define TCP_STATUS__CNTRL_BUSY_PORT1_MASK 0x00000400L +#define TCP_STATUS__LFIFO_BUSY_PORT0_MASK 0x00000800L +#define TCP_STATUS__LFIFO_BUSY_PORT1_MASK 0x00001000L +#define TCP_STATUS__OFIFO_BUSY_PORT0_MASK 0x00002000L +#define TCP_STATUS__OFIFO_BUSY_PORT1_MASK 0x00004000L +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT0_MASK 0x00018000L +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT1_MASK 0x000C0000L +#define TCP_STATUS__READ_BUSY_PORT1_MASK 0x00200000L +#define TCP_STATUS__READ_BUSY_PORT0_MASK 0x00400000L +#define TCP_STATUS__CL_PENDING_MASK 0x00800000L +#define TCP_STATUS__VRX_BUSY_MASK 0x01000000L +#define TCP_STATUS__PKR_BUSY_PORT0_MASK 0x02000000L +#define TCP_STATUS__PKR_BUSY_PORT1_MASK 0x04000000L +#define TCP_STATUS__LDS_BUSY_PORT0_MASK 0x08000000L +#define TCP_STATUS__LDS_BUSY_PORT1_MASK 0x10000000L +#define TCP_STATUS__XNACK_PRT_MASK 0x20000000L +//TCP_CNTL +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__STORE_ATOMIC_COLLAPSE_CLAUSE_LIMIT__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__TD_DATA_EN_OVERRIDE__SHIFT 0x6 +#define TCP_CNTL__TCP_SPILL_CACHE_DISABLE__SHIFT 0x7 +#define TCP_CNTL__DISABLE_WRITE_COMBINING__SHIFT 0x9 +#define TCP_CNTL__FORCE_SCOPE_EOW__SHIFT 0xa +#define TCP_CNTL__FORCE_TEMPORAL_EOW__SHIFT 0xb +#define TCP_CNTL__DISABLE_DCOPY_SET_THRASH_OPT__SHIFT 0xc +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_SET_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_FULL_CL_ACCESS__SHIFT 0x1b +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__ENABLE_64B_SCRATCH_STRIDE__SHIFT 0x1d +#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1f +#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L +#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L +#define TCP_CNTL__STORE_ATOMIC_COLLAPSE_CLAUSE_LIMIT_MASK 0x0000001CL +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L +#define TCP_CNTL__TD_DATA_EN_OVERRIDE_MASK 0x00000040L +#define TCP_CNTL__TCP_SPILL_CACHE_DISABLE_MASK 0x00000080L +#define TCP_CNTL__DISABLE_WRITE_COMBINING_MASK 0x00000200L +#define TCP_CNTL__FORCE_SCOPE_EOW_MASK 0x00000400L +#define TCP_CNTL__FORCE_TEMPORAL_EOW_MASK 0x00000800L +#define TCP_CNTL__DISABLE_DCOPY_SET_THRASH_OPT_MASK 0x00001000L +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L +#define TCP_CNTL__FORCE_EOW_SET_CNT_MASK 0x07C00000L +#define TCP_CNTL__DISABLE_FULL_CL_ACCESS_MASK 0x08000000L +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L +#define TCP_CNTL__ENABLE_64B_SCRATCH_STRIDE_MASK 0x20000000L +#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x80000000L +//TCP_CNTL2 +#define TCP_CNTL2__TCP_FMT_MGCG_DISABLE__SHIFT 0x8 +#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9 +#define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa +#define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE__SHIFT 0xb +#define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT 0xc +#define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT 0xd +#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT 0xe +#define TCP_CNTL2__TX_SP_READ_FGCG_DISABLE__SHIFT 0xf +#define TCP_CNTL2__POWER_OPT_DISABLE__SHIFT 0x10 +#define TCP_CNTL2__GCR_RSP_FGCG_DISABLE__SHIFT 0x11 +#define TCP_CNTL2__PERF_EN_OVERRIDE__SHIFT 0x12 +#define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE__SHIFT 0x16 +#define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE__SHIFT 0x17 +#define TCP_CNTL2__TCP_FORCE_2X_TO_LOAD__SHIFT 0x18 +#define TCP_CNTL2__DISABLE_FLAT_BUF_DATARAM_SWIZZLE__SHIFT 0x19 +#define TCP_CNTL2__VC_UTC_PERMISSIONS_ATOMIC_ALL_SCOPES__SHIFT 0x1a +#define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE__SHIFT 0x1b +#define TCP_CNTL2__TCP_REQ_MGCG_DISABLE__SHIFT 0x1d +#define TCP_CNTL2__TCP_MISS_MGCG_DISABLE__SHIFT 0x1e +#define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING__SHIFT 0x1f +#define TCP_CNTL2__TCP_FMT_MGCG_DISABLE_MASK 0x00000100L +#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L +#define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE_MASK 0x00000400L +#define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE_MASK 0x00000800L +#define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE_MASK 0x00001000L +#define TCP_CNTL2__V64_COMBINE_ENABLE_MASK 0x00002000L +#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK 0x00004000L +#define TCP_CNTL2__TX_SP_READ_FGCG_DISABLE_MASK 0x00008000L +#define TCP_CNTL2__POWER_OPT_DISABLE_MASK 0x00010000L +#define TCP_CNTL2__GCR_RSP_FGCG_DISABLE_MASK 0x00020000L +#define TCP_CNTL2__PERF_EN_OVERRIDE_MASK 0x000C0000L +#define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE_MASK 0x00400000L +#define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE_MASK 0x00800000L +#define TCP_CNTL2__TCP_FORCE_2X_TO_LOAD_MASK 0x01000000L +#define TCP_CNTL2__DISABLE_FLAT_BUF_DATARAM_SWIZZLE_MASK 0x02000000L +#define TCP_CNTL2__VC_UTC_PERMISSIONS_ATOMIC_ALL_SCOPES_MASK 0x04000000L +#define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE_MASK 0x18000000L +#define TCP_CNTL2__TCP_REQ_MGCG_DISABLE_MASK 0x20000000L +#define TCP_CNTL2__TCP_MISS_MGCG_DISABLE_MASK 0x40000000L +#define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING_MASK 0x80000000L +//TCP_CREDIT +#define TCP_CREDIT__LFIFO_RAM_DEPTH__SHIFT 0x0 +#define TCP_CREDIT__GL1_REQ_CREDIT__SHIFT 0xa +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x11 +#define TCP_CREDIT__TD_RAM_CREDIT__SHIFT 0x17 +#define TCP_CREDIT__TD_DATA_CREDIT__SHIFT 0x1d +#define TCP_CREDIT__LFIFO_RAM_DEPTH_MASK 0x000003FFL +#define TCP_CREDIT__GL1_REQ_CREDIT_MASK 0x0001FC00L +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007E0000L +#define TCP_CREDIT__TD_RAM_CREDIT_MASK 0x0F800000L +#define TCP_CREDIT__TD_DATA_CREDIT_MASK 0xE0000000L +//TCP_DEBUG_DATA +#define TCP_DEBUG_DATA__DATA__SHIFT 0x0 +#define TCP_DEBUG_DATA__DATA_MASK 0xFFFFFFFFL +//TCP_COMPRESSION_CNTL +#define TCP_COMPRESSION_CNTL__IMAGE_COMPRESSION_OVERRIDE__SHIFT 0x0 +#define TCP_COMPRESSION_CNTL__IMAGE_BYPASS_COMPRESSION__SHIFT 0x1 +#define TCP_COMPRESSION_CNTL__IMAGE_WRITE_COMPRESSION_DISABLE__SHIFT 0x2 +#define TCP_COMPRESSION_CNTL__BUFFER_COMPRESSION_OVERRIDE__SHIFT 0x3 +#define TCP_COMPRESSION_CNTL__BUFFER_BYPASS_COMPRESSION__SHIFT 0x4 +#define TCP_COMPRESSION_CNTL__BUFFER_WRITE_COMPRESSION_DISABLE__SHIFT 0x5 +#define TCP_COMPRESSION_CNTL__FLAT_COMPRESSION_OVERRIDE__SHIFT 0x6 +#define TCP_COMPRESSION_CNTL__FLAT_BYPASS_COMPRESSION__SHIFT 0x7 +#define TCP_COMPRESSION_CNTL__FLAT_WRITE_COMPRESSION_DISABLE__SHIFT 0x8 +#define TCP_COMPRESSION_CNTL__BVH_BYPASS_COMPRESSION__SHIFT 0x9 +#define TCP_COMPRESSION_CNTL__BUF_SPECULATIVE_DATA_READ__SHIFT 0xa +#define TCP_COMPRESSION_CNTL__BUF_MAX_COMP_BLOCK_SIZE__SHIFT 0xc +#define TCP_COMPRESSION_CNTL__BUF_MAX_UNCOMP_BLOCK_SIZE__SHIFT 0xe +#define TCP_COMPRESSION_CNTL__BVH_SPECULATIVE_DATA_READ__SHIFT 0xf +#define TCP_COMPRESSION_CNTL__BVH_MAX_COMP_BLOCK_SIZE__SHIFT 0x11 +#define TCP_COMPRESSION_CNTL__BVH_MAX_UNCOMP_BLOCK_SIZE__SHIFT 0x13 +#define TCP_COMPRESSION_CNTL__IMAGE_COMPRESSION_OVERRIDE_MASK 0x00000001L +#define TCP_COMPRESSION_CNTL__IMAGE_BYPASS_COMPRESSION_MASK 0x00000002L +#define TCP_COMPRESSION_CNTL__IMAGE_WRITE_COMPRESSION_DISABLE_MASK 0x00000004L +#define TCP_COMPRESSION_CNTL__BUFFER_COMPRESSION_OVERRIDE_MASK 0x00000008L +#define TCP_COMPRESSION_CNTL__BUFFER_BYPASS_COMPRESSION_MASK 0x00000010L +#define TCP_COMPRESSION_CNTL__BUFFER_WRITE_COMPRESSION_DISABLE_MASK 0x00000020L +#define TCP_COMPRESSION_CNTL__FLAT_COMPRESSION_OVERRIDE_MASK 0x00000040L +#define TCP_COMPRESSION_CNTL__FLAT_BYPASS_COMPRESSION_MASK 0x00000080L +#define TCP_COMPRESSION_CNTL__FLAT_WRITE_COMPRESSION_DISABLE_MASK 0x00000100L +#define TCP_COMPRESSION_CNTL__BVH_BYPASS_COMPRESSION_MASK 0x00000200L +#define TCP_COMPRESSION_CNTL__BUF_SPECULATIVE_DATA_READ_MASK 0x00000C00L +#define TCP_COMPRESSION_CNTL__BUF_MAX_COMP_BLOCK_SIZE_MASK 0x00003000L +#define TCP_COMPRESSION_CNTL__BUF_MAX_UNCOMP_BLOCK_SIZE_MASK 0x00004000L +#define TCP_COMPRESSION_CNTL__BVH_SPECULATIVE_DATA_READ_MASK 0x00018000L +#define TCP_COMPRESSION_CNTL__BVH_MAX_COMP_BLOCK_SIZE_MASK 0x00060000L +#define TCP_COMPRESSION_CNTL__BVH_MAX_UNCOMP_BLOCK_SIZE_MASK 0x00080000L +//TCP_ARB +#define TCP_ARB__WEIGHT__SHIFT 0x0 +#define TCP_ARB__END_CLAUSE__SHIFT 0x3 +#define TCP_ARB__WEIGHT_MASK 0x00000007L +#define TCP_ARB__END_CLAUSE_MASK 0x00000008L +//TCP_UTCL0_CNTL1 +#define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define TCP_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define TCP_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define TCP_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define TCP_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define TCP_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x11 +#define TCP_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x16 +#define TCP_UTCL0_CNTL1__ATOMIC_REQUESTER_EN__SHIFT 0x17 +#define TCP_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x18 +#define TCP_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x19 +#define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1a +#define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1d +#define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define TCP_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define TCP_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define TCP_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define TCP_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define TCP_UTCL0_CNTL1__REG_INV_VMID_MASK 0x001E0000L +#define TCP_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x00400000L +#define TCP_UTCL0_CNTL1__ATOMIC_REQUESTER_EN_MASK 0x00800000L +#define TCP_UTCL0_CNTL1__FORCE_MISS_MASK 0x01000000L +#define TCP_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x02000000L +#define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x1C000000L +#define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xE0000000L +//TCP_UTCL0_CNTL2 +#define TCP_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define TCP_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa +#define TCP_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define TCP_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define TCP_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define TCP_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define TCP_UTCL0_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE__SHIFT 0x1b +#define TCP_UTCL0_CNTL2__THRASHING_ENABLE__SHIFT 0x1c +#define TCP_UTCL0_CNTL2__DISABLE_SPECULATIVE_PREFETCH__SHIFT 0x1d +#define TCP_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define TCP_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC__SHIFT 0x1f +#define TCP_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define TCP_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L +#define TCP_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define TCP_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define TCP_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define TCP_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define TCP_UTCL0_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE_MASK 0x08000000L +#define TCP_UTCL0_CNTL2__THRASHING_ENABLE_MASK 0x10000000L +#define TCP_UTCL0_CNTL2__DISABLE_SPECULATIVE_PREFETCH_MASK 0x20000000L +#define TCP_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define TCP_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC_MASK 0x80000000L +//TCP_UTCL0_STATUS +#define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL0_STATUS__TIMEOUT_DETECTED__SHIFT 0x3 +#define TCP_UTCL0_STATUS__VMID_BUSY__SHIFT 0x4 +#define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +#define TCP_UTCL0_STATUS__TIMEOUT_DETECTED_MASK 0x00000008L +#define TCP_UTCL0_STATUS__VMID_BUSY_MASK 0x000FFFF0L +//TCP_RQID_HASH_CNTL +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_MASK__SHIFT 0x0 +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_SHIFT__SHIFT 0x4 +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_MASK__SHIFT 0x7 +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_SHIFT__SHIFT 0xb +#define TCP_RQID_HASH_CNTL__SIMD_ID_MASK__SHIFT 0xe +#define TCP_RQID_HASH_CNTL__SIMD_ID_SHIFT__SHIFT 0xf +#define TCP_RQID_HASH_CNTL__TYPE_MASK__SHIFT 0x12 +#define TCP_RQID_HASH_CNTL__TYPE_SHIFT__SHIFT 0x14 +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_MASK_MASK 0x0000000FL +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_SHIFT_MASK 0x00000070L +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_MASK_MASK 0x00000780L +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_SHIFT_MASK 0x00003800L +#define TCP_RQID_HASH_CNTL__SIMD_ID_MASK_MASK 0x00004000L +#define TCP_RQID_HASH_CNTL__SIMD_ID_SHIFT_MASK 0x00038000L +#define TCP_RQID_HASH_CNTL__TYPE_MASK_MASK 0x000C0000L +#define TCP_RQID_HASH_CNTL__TYPE_SHIFT_MASK 0x00700000L +//TCP_SET_HASH_CFG +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_192__SHIFT 0x1 +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_320__SHIFT 0x5 +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_384__SHIFT 0x9 +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_448__SHIFT 0xd +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_192_MASK 0x0000001EL +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_320_MASK 0x000001E0L +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_384_MASK 0x00001E00L +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_448_MASK 0x0001E000L +//TCP_SET_HASH_MASK_64_SET0 +#define TCP_SET_HASH_MASK_64_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_64_SET1 +#define TCP_SET_HASH_MASK_64_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_64_SET2 +#define TCP_SET_HASH_MASK_64_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_64_SET3 +#define TCP_SET_HASH_MASK_64_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET0 +#define TCP_SET_HASH_MASK_128_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET1 +#define TCP_SET_HASH_MASK_128_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET2 +#define TCP_SET_HASH_MASK_128_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET3 +#define TCP_SET_HASH_MASK_128_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET4 +#define TCP_SET_HASH_MASK_128_SET4__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET4__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET0 +#define TCP_SET_HASH_MASK_192_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET1 +#define TCP_SET_HASH_MASK_192_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET2 +#define TCP_SET_HASH_MASK_192_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET3 +#define TCP_SET_HASH_MASK_192_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET0 +#define TCP_SET_HASH_MASK_256_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET1 +#define TCP_SET_HASH_MASK_256_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET2 +#define TCP_SET_HASH_MASK_256_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET3 +#define TCP_SET_HASH_MASK_256_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET4 +#define TCP_SET_HASH_MASK_256_SET4__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET4__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET5 +#define TCP_SET_HASH_MASK_256_SET5__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET5__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET0 +#define TCP_SET_HASH_MASK_320_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET1 +#define TCP_SET_HASH_MASK_320_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET2 +#define TCP_SET_HASH_MASK_320_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET3 +#define TCP_SET_HASH_MASK_320_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET0 +#define TCP_SET_HASH_MASK_384_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET1 +#define TCP_SET_HASH_MASK_384_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET2 +#define TCP_SET_HASH_MASK_384_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET3 +#define TCP_SET_HASH_MASK_384_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET4 +#define TCP_SET_HASH_MASK_384_SET4__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET4__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET0 +#define TCP_SET_HASH_MASK_448_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET1 +#define TCP_SET_HASH_MASK_448_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET2 +#define TCP_SET_HASH_MASK_448_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET3 +#define TCP_SET_HASH_MASK_448_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET3__MASK_MASK 0x0007FFFFL +//TCP_CNTL3 +#define TCP_CNTL3__TCS_PORT_PRIORITY_EVENT__SHIFT 0x0 +#define TCP_CNTL3__TCS_PORT_PRIORITY_WEIGHT__SHIFT 0x2 +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_EVENT__SHIFT 0x7 +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_WEIGHT__SHIFT 0x9 +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_EVENT__SHIFT 0xe +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_WEIGHT__SHIFT 0x10 +#define TCP_CNTL3__QM_CAC_OUTPUT__SHIFT 0x15 +#define TCP_CNTL3__DISABLE_COALESCING_FOR_PAGE_TRANSLATION__SHIFT 0x1a +#define TCP_CNTL3__OOO_HWT_SHOOTDOWN_DRAIN_DIS__SHIFT 0x1b +#define TCP_CNTL3__ASYNC_INFLIGHT_VRX_SINGLE_PORT__SHIFT 0x1c +#define TCP_CNTL3__VC_DP_INV_STALL_EN__SHIFT 0x1d +#define TCP_CNTL3__DISABLE_EARLY_WRITE_ACK__SHIFT 0x1e +#define TCP_CNTL3__CL_256B_COMBINE_DIS__SHIFT 0x1f +#define TCP_CNTL3__TCS_PORT_PRIORITY_EVENT_MASK 0x00000003L +#define TCP_CNTL3__TCS_PORT_PRIORITY_WEIGHT_MASK 0x0000007CL +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_EVENT_MASK 0x00000180L +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_WEIGHT_MASK 0x00003E00L +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_EVENT_MASK 0x0000C000L +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_WEIGHT_MASK 0x001F0000L +#define TCP_CNTL3__QM_CAC_OUTPUT_MASK 0x00200000L +#define TCP_CNTL3__DISABLE_COALESCING_FOR_PAGE_TRANSLATION_MASK 0x04000000L +#define TCP_CNTL3__OOO_HWT_SHOOTDOWN_DRAIN_DIS_MASK 0x08000000L +#define TCP_CNTL3__ASYNC_INFLIGHT_VRX_SINGLE_PORT_MASK 0x10000000L +#define TCP_CNTL3__VC_DP_INV_STALL_EN_MASK 0x20000000L +#define TCP_CNTL3__DISABLE_EARLY_WRITE_ACK_MASK 0x40000000L +#define TCP_CNTL3__CL_256B_COMBINE_DIS_MASK 0x80000000L +//LDS_CONFIG +#define LDS_CONFIG__CONF_BIT_1__SHIFT 0x0 +#define LDS_CONFIG__PC_CNTRL_OUT_FGCG_OVERRIDE__SHIFT 0x1 +#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT 0x2 +#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT 0x3 +#define LDS_CONFIG__CONF_BIT_5__SHIFT 0x4 +#define LDS_CONFIG__CONF_BIT_6__SHIFT 0x5 +#define LDS_CONFIG__CONF_BIT_7__SHIFT 0x6 +#define LDS_CONFIG__CONF_BIT_8__SHIFT 0x7 +#define LDS_CONFIG__PEND_CNT_WIDTH__SHIFT 0x8 +#define LDS_CONFIG__LDSI_ROUNDROBIN_ARB__SHIFT 0xe +#define LDS_CONFIG__CONF_BIT_1_MASK 0x00000001L +#define LDS_CONFIG__PC_CNTRL_OUT_FGCG_OVERRIDE_MASK 0x00000002L +#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK 0x00000004L +#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK 0x00000008L +#define LDS_CONFIG__CONF_BIT_5_MASK 0x00000010L +#define LDS_CONFIG__CONF_BIT_6_MASK 0x00000020L +#define LDS_CONFIG__CONF_BIT_7_MASK 0x00000040L +#define LDS_CONFIG__CONF_BIT_8_MASK 0x00000080L +#define LDS_CONFIG__PEND_CNT_WIDTH_MASK 0x00003F00L +#define LDS_CONFIG__LDSI_ROUNDROBIN_ARB_MASK 0x00004000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_spidec +//SPI_RESOURCE_RESERVE_CU_0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_1 +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_2 +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_3 +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_4 +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_5 +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_6 +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_7 +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_8 +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_9 +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_10 +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_11 +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_12 +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_13 +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_14 +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_15 +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_2 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_3 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_4 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_5 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_6 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_7 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_8 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_9 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_11 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_12 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_13 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_14 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_15 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_tcpdec +//TCP_UTCL0_THRASHING_CTRL +#define TCP_UTCL0_THRASHING_CTRL__THRASHING_EN__SHIFT 0x0 +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_DOWN_EN__SHIFT 0x2 +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_UP_EN__SHIFT 0x3 +#define TCP_UTCL0_THRASHING_CTRL__STALL_TIMEOUT_PROTECT_ENABLE__SHIFT 0x4 +#define TCP_UTCL0_THRASHING_CTRL__STALL_TARGET_FRAGMENT_SIZE__SHIFT 0x5 +#define TCP_UTCL0_THRASHING_CTRL__RETRY_TARGET_FRAGMENT_SIZE__SHIFT 0x9 +#define TCP_UTCL0_THRASHING_CTRL__THRASHING_EN_MASK 0x00000003L +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_DOWN_EN_MASK 0x00000004L +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_UP_EN_MASK 0x00000008L +#define TCP_UTCL0_THRASHING_CTRL__STALL_TIMEOUT_PROTECT_ENABLE_MASK 0x00000010L +#define TCP_UTCL0_THRASHING_CTRL__STALL_TARGET_FRAGMENT_SIZE_MASK 0x000001E0L +#define TCP_UTCL0_THRASHING_CTRL__RETRY_TARGET_FRAGMENT_SIZE_MASK 0x00001E00L +//TCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER +#define TCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER__DOWN_COUNTER__SHIFT 0x0 +#define TCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER__DOWN_COUNTER_MASK 0xFFFFFFFFL +//TCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER +#define TCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER__UP_COUNTER__SHIFT 0x0 +#define TCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER__UP_COUNTER_MASK 0xFFFFFFFFL +//TCP_UTCL0_XNACK_RETRY +#define TCP_UTCL0_XNACK_RETRY__INCR__SHIFT 0x0 +#define TCP_UTCL0_XNACK_RETRY__COUNT__SHIFT 0x8 +#define TCP_UTCL0_XNACK_RETRY__INCR_MASK 0x000000FFL +#define TCP_UTCL0_XNACK_RETRY__COUNT_MASK 0x00000F00L +//TCP_UTCL0_RETRY_TIMER_THRESHOLD_LO +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE__SHIFT 0x0 +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE_MASK 0xFFFFFFFFL +//TCP_UTCL0_RETRY_TIMER_THRESHOLD_HI +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE__SHIFT 0x0 +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE_MASK 0xFFFFFFFFL +//TXA_CNTL +#define TXA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT 0x0 +#define TXA_CNTL__TXA_CFG_CHG_STALL__SHIFT 0x1 +#define TXA_CNTL__TXA_ALIGNER_LDS_B96_LOAD_CYCLING__SHIFT 0x2 +#define TXA_CNTL__ALIGNER_CREDIT__SHIFT 0x8 +#define TXA_CNTL__ALIGNER_CREDIT_LDS__SHIFT 0x10 +#define TXA_CNTL__DISABLE_ASYNC_LOAD_DIRECT_COPY__SHIFT 0x15 +#define TXA_CNTL__DISABLE_ASYNC_STORE_DIRECT_COPY__SHIFT 0x16 +#define TXA_CNTL__INPUT_XNACK_RESET_CREDIT__SHIFT 0x17 +#define TXA_CNTL__ENABLE_B128_DIRECT_COPY_STORE__SHIFT 0x1a +#define TXA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK 0x00000001L +#define TXA_CNTL__TXA_CFG_CHG_STALL_MASK 0x00000002L +#define TXA_CNTL__TXA_ALIGNER_LDS_B96_LOAD_CYCLING_MASK 0x00000004L +#define TXA_CNTL__ALIGNER_CREDIT_MASK 0x00001F00L +#define TXA_CNTL__ALIGNER_CREDIT_LDS_MASK 0x001F0000L +#define TXA_CNTL__DISABLE_ASYNC_LOAD_DIRECT_COPY_MASK 0x00200000L +#define TXA_CNTL__DISABLE_ASYNC_STORE_DIRECT_COPY_MASK 0x00400000L +#define TXA_CNTL__INPUT_XNACK_RESET_CREDIT_MASK 0x03800000L +#define TXA_CNTL__ENABLE_B128_DIRECT_COPY_STORE_MASK 0x04000000L +//TXA_CNTL_AUX +#define TXA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 +#define TXA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TXA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TXA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TXA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TXA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TXA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L +#define TXA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TXA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TXA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TXA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TXA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +//TXA_CNTL2 +#define TXA_CNTL2__ELEMSIZE_HASH_DIS__SHIFT 0x11 +#define TXA_CNTL2__ELEMSIZE_HASH_DIS_MASK 0x00020000L +//TXA_STATUS +#define TXA_STATUS__TXA0_BUSY__SHIFT 0x10 +#define TXA_STATUS__TXA1_BUSY__SHIFT 0x11 +#define TXA_STATUS__TXA0_BUSY_MASK 0x00010000L +#define TXA_STATUS__TXA1_BUSY_MASK 0x00020000L +//TXA_TDM_ARB_CNTL +#define TXA_TDM_ARB_CNTL__INTERLEAVE_MODE__SHIFT 0x0 +#define TXA_TDM_ARB_CNTL__INTERLEAVE_STEP__SHIFT 0x2 +#define TXA_TDM_ARB_CNTL__PR_EN__SHIFT 0x6 +#define TXA_TDM_ARB_CNTL__BAL_TM_ON_BUS__SHIFT 0x8 +#define TXA_TDM_ARB_CNTL__PR_RATE__SHIFT 0x9 +#define TXA_TDM_ARB_CNTL__PR_CNTX_RESTORE__SHIFT 0xc +#define TXA_TDM_ARB_CNTL__DIS_DIRECT_FETCH__SHIFT 0xd +#define TXA_TDM_ARB_CNTL__REPLAY_SLEEP_CNT__SHIFT 0xe +#define TXA_TDM_ARB_CNTL__INFLIGHT_CNT_MAX__SHIFT 0x15 +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_LOAD_DC__SHIFT 0x1e +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_STORE_DC__SHIFT 0x1f +#define TXA_TDM_ARB_CNTL__INTERLEAVE_MODE_MASK 0x00000003L +#define TXA_TDM_ARB_CNTL__INTERLEAVE_STEP_MASK 0x0000003CL +#define TXA_TDM_ARB_CNTL__PR_EN_MASK 0x000000C0L +#define TXA_TDM_ARB_CNTL__BAL_TM_ON_BUS_MASK 0x00000100L +#define TXA_TDM_ARB_CNTL__PR_RATE_MASK 0x00000E00L +#define TXA_TDM_ARB_CNTL__PR_CNTX_RESTORE_MASK 0x00001000L +#define TXA_TDM_ARB_CNTL__DIS_DIRECT_FETCH_MASK 0x00002000L +#define TXA_TDM_ARB_CNTL__REPLAY_SLEEP_CNT_MASK 0x001FC000L +#define TXA_TDM_ARB_CNTL__INFLIGHT_CNT_MAX_MASK 0x3FE00000L +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_LOAD_DC_MASK 0x40000000L +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_STORE_DC_MASK 0x80000000L +//TCP_CREDIT2 +#define TCP_CREDIT2__LDSO0_ARB0_HANDLER_CREDIT__SHIFT 0x0 +#define TCP_CREDIT2__LDSO1_ARB1_HANDLER_CREDIT__SHIFT 0x4 +#define TCP_CREDIT2__VRX_TXD0_HANDLER_CREDIT__SHIFT 0x8 +#define TCP_CREDIT2__VRX_TXD1_HANDLER_CREDIT__SHIFT 0xc +#define TCP_CREDIT2__LDSO0_ARB0_HANDLER_CREDIT_MASK 0x0000000FL +#define TCP_CREDIT2__LDSO1_ARB1_HANDLER_CREDIT_MASK 0x000000F0L +#define TCP_CREDIT2__VRX_TXD0_HANDLER_CREDIT_MASK 0x00000F00L +#define TCP_CREDIT2__VRX_TXD1_HANDLER_CREDIT_MASK 0x0000F000L +//VC_CONGESTION_CONTROL +#define VC_CONGESTION_CONTROL__LFIFO_LIMIT__SHIFT 0x0 +#define VC_CONGESTION_CONTROL__SET_PENDING_LIMIT__SHIFT 0xa +#define VC_CONGESTION_CONTROL__UTCL0_LFIFO_LIMIT__SHIFT 0xf +#define VC_CONGESTION_CONTROL__LFIFO_LIMIT_MASK 0x000003FFL +#define VC_CONGESTION_CONTROL__SET_PENDING_LIMIT_MASK 0x00007C00L +#define VC_CONGESTION_CONTROL__UTCL0_LFIFO_LIMIT_MASK 0x007F8000L +//TXA_TDM_CNTL +#define TXA_TDM_CNTL__DIS_DONE_INTERLEAVE__SHIFT 0x0 +#define TXA_TDM_CNTL__DIS_CFG_STALL_UPD__SHIFT 0x1 +#define TXA_TDM_CNTL__EN_ADS_SLOT_RELEASE__SHIFT 0x2 +#define TXA_TDM_CNTL__EN_DC_STORE_B128__SHIFT 0x3 +#define TXA_TDM_CNTL__CTRL_SPARE0__SHIFT 0x4 +#define TXA_TDM_CNTL__CTRL_SPARE1__SHIFT 0x5 +#define TXA_TDM_CNTL__CTRL_SPARE2__SHIFT 0x6 +#define TXA_TDM_CNTL__CTRL_SPARE3__SHIFT 0x7 +#define TXA_TDM_CNTL__CTRL_SPARE4__SHIFT 0x8 +#define TXA_TDM_CNTL__DIS_DONE_INTERLEAVE_MASK 0x00000001L +#define TXA_TDM_CNTL__DIS_CFG_STALL_UPD_MASK 0x00000002L +#define TXA_TDM_CNTL__EN_ADS_SLOT_RELEASE_MASK 0x00000004L +#define TXA_TDM_CNTL__EN_DC_STORE_B128_MASK 0x00000008L +#define TXA_TDM_CNTL__CTRL_SPARE0_MASK 0x00000010L +#define TXA_TDM_CNTL__CTRL_SPARE1_MASK 0x00000020L +#define TXA_TDM_CNTL__CTRL_SPARE2_MASK 0x00000040L +#define TXA_TDM_CNTL__CTRL_SPARE3_MASK 0x00000080L +#define TXA_TDM_CNTL__CTRL_SPARE4_MASK 0x00000100L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxudec +//VGT_TF_RING_SIZE +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL +//VGT_HS_OFFCHIP_PARAM +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0xa +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000003FFL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000C00L +//GE_POS_RING_BASE +#define GE_POS_RING_BASE__BASE__SHIFT 0x0 +#define GE_POS_RING_BASE__BASE_MASK 0xFFFFFFFFL +//GE_POS_RING_SIZE +#define GE_POS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define GE_POS_RING_SIZE__MEM_SIZE_MASK 0x00003FFFL +//GE_PRIM_RING_BASE +#define GE_PRIM_RING_BASE__BASE__SHIFT 0x0 +#define GE_PRIM_RING_BASE__BASE_MASK 0xFFFFFFFFL +//GE_PRIM_RING_SIZE +#define GE_PRIM_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define GE_PRIM_RING_SIZE__SCOPE__SHIFT 0x10 +#define GE_PRIM_RING_SIZE__PAF_TEMPORAL__SHIFT 0x12 +#define GE_PRIM_RING_SIZE__PAB_TEMPORAL__SHIFT 0x15 +#define GE_PRIM_RING_SIZE__SPEC_DATA_READ__SHIFT 0x18 +#define GE_PRIM_RING_SIZE__FORCE_SE_SCOPE__SHIFT 0x1a +#define GE_PRIM_RING_SIZE__PAB_NOFILL__SHIFT 0x1b +#define GE_PRIM_RING_SIZE__MEM_SIZE_MASK 0x000007FFL +#define GE_PRIM_RING_SIZE__SCOPE_MASK 0x00030000L +#define GE_PRIM_RING_SIZE__PAF_TEMPORAL_MASK 0x001C0000L +#define GE_PRIM_RING_SIZE__PAB_TEMPORAL_MASK 0x00E00000L +#define GE_PRIM_RING_SIZE__SPEC_DATA_READ_MASK 0x03000000L +#define GE_PRIM_RING_SIZE__FORCE_SE_SCOPE_MASK 0x04000000L +#define GE_PRIM_RING_SIZE__PAB_NOFILL_MASK 0x08000000L +//PA_SU_LINE_STIPPLE_VALUE +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL +//PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L +//PA_SC_SCREEN_EXTENT_MIN_0 +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_0 +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MIN_1 +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_1 +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L +//PA_SC_P3D_TRAP_SCREEN_HV_EN +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_P3D_TRAP_SCREEN_H +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_V +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_COUNT +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_HV_EN +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_HP3D_TRAP_SCREEN_H +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_V +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_COUNT +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_HV_EN +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_TRAP_SCREEN_H +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_V +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_OCCURRENCE +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_COUNT +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_USERDATA_0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_1 +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_2 +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_3 +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_4 +#define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_5 +#define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_6 +#define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_7 +#define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL +//SQC_CACHES +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x00000001L +#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L +#define SQC_CACHES__INVALIDATE_MASK 0x00000004L +#define SQC_CACHES__COMPLETE_MASK 0x00010000L +//TA_CS_BC_BASE_ADDR +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_CS_BC_BASE_ADDR_HI +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//DB_OCCLUSION_COUNT0_LOW +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT0_HI +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT1_LOW +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT1_HI +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT2_LOW +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT2_HI +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT3_LOW +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT3_HI +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL +//SPI_CONFIG_CNTL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L +//SPI_CONFIG_CNTL_1 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf +#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10 +#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15 +#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT 0x16 +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT__SHIFT 0x17 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L +#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L +#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L +#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK 0x00400000L +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MASK 0xFF800000L +//SPI_CONFIG_CNTL_2 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT 0xa +#define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE__SHIFT 0xb +#define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY__SHIFT 0xc +#define SPI_CONFIG_CNTL_2__SPP_TIMEOUT_CTR__SHIFT 0x11 +#define SPI_CONFIG_CNTL_2__PC_CONTEXT_DONE_SYNC_ENABLE__SHIFT 0x15 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L +#define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE_MASK 0x00000400L +#define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE_MASK 0x00000800L +#define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY_MASK 0x0001F000L +#define SPI_CONFIG_CNTL_2__SPP_TIMEOUT_CTR_MASK 0x001E0000L +#define SPI_CONFIG_CNTL_2__PC_CONTEXT_DONE_SYNC_ENABLE_MASK 0x00200000L +//SPI_GS_THROTTLE_CNTL1 +#define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL__SHIFT 0x0 +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE__SHIFT 0x4 +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE__SHIFT 0x8 +#define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD__SHIFT 0xc +#define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD__SHIFT 0x10 +#define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL__SHIFT 0x14 +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE__SHIFT 0x18 +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE__SHIFT 0x1c +#define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL_MASK 0x0000000FL +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE_MASK 0x000000F0L +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE_MASK 0x00000F00L +#define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD_MASK 0x0000F000L +#define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD_MASK 0x000F0000L +#define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL_MASK 0x00F00000L +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE_MASK 0x0F000000L +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE_MASK 0xF0000000L +//SPI_GS_THROTTLE_CNTL2 +#define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE__SHIFT 0x0 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD__SHIFT 0x2 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR__SHIFT 0x6 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1__SHIFT 0x8 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2__SHIFT 0xb +#define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD__SHIFT 0xe +#define SPI_GS_THROTTLE_CNTL2__PH_MODE__SHIFT 0x10 +#define SPI_GS_THROTTLE_CNTL2__RESERVED__SHIFT 0x11 +#define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE_MASK 0x00000003L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_MASK 0x0000003CL +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR_MASK 0x000000C0L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1_MASK 0x00000700L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2_MASK 0x00003800L +#define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD_MASK 0x0000C000L +#define SPI_GS_THROTTLE_CNTL2__PH_MODE_MASK 0x00010000L +#define SPI_GS_THROTTLE_CNTL2__RESERVED_MASK 0xFFFE0000L +//SPI_ATTRIBUTE_RING_BASE +#define SPI_ATTRIBUTE_RING_BASE__BASE__SHIFT 0x0 +#define SPI_ATTRIBUTE_RING_BASE__BASE_MASK 0xFFFFFFFFL +//SPI_ATTRIBUTE_RING_SIZE +#define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE__SHIFT 0x10 +#define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY__SHIFT 0x11 +#define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY__SHIFT 0x13 +#define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC__SHIFT 0x15 +#define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE__SHIFT 0x16 +#define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE_MASK 0x000000FFL +#define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE_MASK 0x00010000L +#define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY_MASK 0x00060000L +#define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY_MASK 0x00180000L +#define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC_MASK 0x00200000L +#define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE_MASK 0x00400000L +//SPI_SQG_EVENT_CTL +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x0 +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x1 +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_TOP_EVENTS_MASK 0x00000001L +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_BOP_EVENTS_MASK 0x00000002L +//SPI_COMPUTE_WGS_CONTROL +#define SPI_COMPUTE_WGS_CONTROL__WGS_ENABLE__SHIFT 0x0 +#define SPI_COMPUTE_WGS_CONTROL__WGS_ENABLE_MASK 0x00000001L +//SPI_GRP_LAUNCH_GUARANTEE_ENABLE +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__ENABLE__SHIFT 0x0 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__HS_ASSIST_EN__SHIFT 0x1 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GS_ASSIST_EN__SHIFT 0x2 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__MRT_ASSIST_EN__SHIFT 0x3 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_GLG_DISABLE__SHIFT 0x4 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GFX_NUM_LOCK_WGP__SHIFT 0x5 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_NUM_LOCK_WGP__SHIFT 0x8 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_PERIOD__SHIFT 0xb +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_MAINT_COUNT__SHIFT 0xf +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CLUSTER_LOCK_DISABLE__SHIFT 0x12 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__ENABLE_MASK 0x00000001L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__HS_ASSIST_EN_MASK 0x00000002L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GS_ASSIST_EN_MASK 0x00000004L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__MRT_ASSIST_EN_MASK 0x00000008L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_GLG_DISABLE_MASK 0x00000010L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GFX_NUM_LOCK_WGP_MASK 0x000000E0L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_NUM_LOCK_WGP_MASK 0x00000700L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_PERIOD_MASK 0x00007800L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_MAINT_COUNT_MASK 0x00038000L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CLUSTER_LOCK_DISABLE_MASK 0x00040000L +//SPI_GRP_LAUNCH_GUARANTEE_CTRL +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__NUM_MRT_THRESHOLD__SHIFT 0x0 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_PENDING_THRESHOLD__SHIFT 0x3 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__PRIORITY_LOST_THRESHOLD__SHIFT 0x6 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__ALLOC_SUCCESS_THRESHOLD__SHIFT 0xa +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_WAVE_THRESHOLD_HIGH__SHIFT 0xe +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CS_WAVE_THRESHOLD_HIGH__SHIFT 0x13 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CU_MASK_ROTATE_PERIODS__SHIFT 0x18 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__EQUAL_PRIORITY_LOST_THRESHOLD__SHIFT 0x1a +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__NUM_MRT_THRESHOLD_MASK 0x00000007L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_PENDING_THRESHOLD_MASK 0x00000038L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__PRIORITY_LOST_THRESHOLD_MASK 0x000003C0L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__ALLOC_SUCCESS_THRESHOLD_MASK 0x00003C00L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_WAVE_THRESHOLD_HIGH_MASK 0x0007C000L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CS_WAVE_THRESHOLD_HIGH_MASK 0x00F80000L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CU_MASK_ROTATE_PERIODS_MASK 0x03000000L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__EQUAL_PRIORITY_LOST_THRESHOLD_MASK 0x3C000000L +//SPI_GOG_ALLOCATION_CTRL +#define SPI_GOG_ALLOCATION_CTRL__GOG_ALLOCATION_TIME_OUT__SHIFT 0x0 +#define SPI_GOG_ALLOCATION_CTRL__GOG_RETRY_DELAY__SHIFT 0x6 +#define SPI_GOG_ALLOCATION_CTRL__GOG_ALLOCATION_TIME_OUT_MASK 0x0000003FL +#define SPI_GOG_ALLOCATION_CTRL__GOG_RETRY_DELAY_MASK 0x00000FC0L +//SPI_TCP_CNTL +#define SPI_TCP_CNTL__DEFAULT_LDS_PARTITIONS__SHIFT 0x0 +#define SPI_TCP_CNTL__MIN_LDS_PARTITIONS__SHIFT 0x4 +#define SPI_TCP_CNTL__MAX_LDS_PARTITIONS__SHIFT 0xc +#define SPI_TCP_CNTL__IDLE_ALLOC_OPT_DIS__SHIFT 0x10 +#define SPI_TCP_CNTL__PARTIAL_DRAIN_DIS__SHIFT 0x11 +#define SPI_TCP_CNTL__LDS_PINGPONG_DIS__SHIFT 0x12 +#define SPI_TCP_CNTL__DEFAULT_LDS_PARTITIONS_MASK 0x00000007L +#define SPI_TCP_CNTL__MIN_LDS_PARTITIONS_MASK 0x00000070L +#define SPI_TCP_CNTL__MAX_LDS_PARTITIONS_MASK 0x00007000L +#define SPI_TCP_CNTL__IDLE_ALLOC_OPT_DIS_MASK 0x00010000L +#define SPI_TCP_CNTL__PARTIAL_DRAIN_DIS_MASK 0x00020000L +#define SPI_TCP_CNTL__LDS_PINGPONG_DIS_MASK 0x00040000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_comp_wgsdec +//WGS_COMPUTE_DISPATCH_INITIATOR +#define WGS_COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define WGS_COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define WGS_COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define WGS_COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define WGS_COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define WGS_COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN__SHIFT 0xc +#define WGS_COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd +#define WGS_COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define WGS_COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf +#define WGS_COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT 0x10 +#define WGS_COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT 0x11 +#define WGS_COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN__SHIFT 0x12 +#define WGS_COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH__SHIFT 0x13 +#define WGS_COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID__SHIFT 0x1d +#define WGS_COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define WGS_COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define WGS_COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define WGS_COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define WGS_COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define WGS_COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define WGS_COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN_MASK 0x00001000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK 0x00010000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK 0x00020000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN_MASK 0x00040000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH_MASK 0x00080000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID_MASK 0xE0000000L +//WGS_COMPUTE_DIM_X +#define WGS_COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DIM_Y +#define WGS_COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DIM_Z +#define WGS_COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_START_X +#define WGS_COMPUTE_START_X__START__SHIFT 0x0 +#define WGS_COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//WGS_COMPUTE_START_Y +#define WGS_COMPUTE_START_Y__START__SHIFT 0x0 +#define WGS_COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//WGS_COMPUTE_START_Z +#define WGS_COMPUTE_START_Z__START__SHIFT 0x0 +#define WGS_COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//WGS_COMPUTE_NUM_THREAD_X +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define WGS_COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X__SHIFT 0xd +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x00001FFFL +#define WGS_COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X_MASK 0x0000E000L +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//WGS_COMPUTE_NUM_THREAD_Y +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define WGS_COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y__SHIFT 0xd +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x00001FFFL +#define WGS_COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y_MASK 0x0000E000L +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//WGS_COMPUTE_NUM_THREAD_Z +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//WGS_COMPUTE_PIPELINESTAT_ENABLE +#define WGS_COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define WGS_COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//WGS_COMPUTE_PERFCOUNT_ENABLE +#define WGS_COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define WGS_COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//WGS_COMPUTE_PGM_LO +#define WGS_COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define WGS_COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_PGM_HI +#define WGS_COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define WGS_COMPUTE_PGM_HI__DATA_MASK 0x000000FFL +//WGS_COMPUTE_DISPATCH_PKT_ADDR_LO +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DISPATCH_PKT_ADDR_HI +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//WGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//WGS_COMPUTE_PGM_RSRC1 +#define WGS_COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define WGS_COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define WGS_COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define WGS_COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define WGS_COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define WGS_COMPUTE_PGM_RSRC1__WG_RR_EN__SHIFT 0x15 +#define WGS_COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define WGS_COMPUTE_PGM_RSRC1__DISABLE_PERF__SHIFT 0x17 +#define WGS_COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define WGS_COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define WGS_COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define WGS_COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d +#define WGS_COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f +#define WGS_COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define WGS_COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define WGS_COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define WGS_COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define WGS_COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define WGS_COMPUTE_PGM_RSRC1__WG_RR_EN_MASK 0x00200000L +#define WGS_COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define WGS_COMPUTE_PGM_RSRC1__DISABLE_PERF_MASK 0x00800000L +#define WGS_COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define WGS_COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define WGS_COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +#define WGS_COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L +#define WGS_COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L +//WGS_COMPUTE_PGM_RSRC2 +#define WGS_COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define WGS_COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define WGS_COMPUTE_PGM_RSRC2__DYNAMIC_VGPR__SHIFT 0x6 +#define WGS_COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define WGS_COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define WGS_COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define WGS_COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define WGS_COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define WGS_COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define WGS_COMPUTE_PGM_RSRC2__WGP_TAKEOVER__SHIFT 0x1f +#define WGS_COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define WGS_COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL +#define WGS_COMPUTE_PGM_RSRC2__DYNAMIC_VGPR_MASK 0x00000040L +#define WGS_COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define WGS_COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define WGS_COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define WGS_COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define WGS_COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define WGS_COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define WGS_COMPUTE_PGM_RSRC2__WGP_TAKEOVER_MASK 0x80000000L +//WGS_COMPUTE_VMID +#define WGS_COMPUTE_VMID__DATA__SHIFT 0x0 +#define WGS_COMPUTE_VMID__DATA_MASK 0x0000000FL +//WGS_COMPUTE_RESOURCE_LIMITS +#define WGS_COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define WGS_COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define WGS_COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define WGS_COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define WGS_COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define WGS_COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define WGS_COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define WGS_COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define WGS_COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define WGS_COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define WGS_COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define WGS_COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +//WGS_COMPUTE_DESTINATION_EN_SE0 +#define WGS_COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_DESTINATION_EN_SE1 +#define WGS_COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE1 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_TMPRING_SIZE +#define WGS_COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define WGS_COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define WGS_COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define WGS_COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x3FFFF000L +//WGS_COMPUTE_DESTINATION_EN_SE2 +#define WGS_COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE2 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_DESTINATION_EN_SE3 +#define WGS_COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE3 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_RESTART_X +#define WGS_COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define WGS_COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//WGS_COMPUTE_RESTART_Y +#define WGS_COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define WGS_COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//WGS_COMPUTE_RESTART_Z +#define WGS_COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define WGS_COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//WGS_COMPUTE_THREAD_TRACE_ENABLE +#define WGS_COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define WGS_COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//WGS_COMPUTE_MISC_RESERVED +#define WGS_COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define WGS_COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define WGS_COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define WGS_COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x0000000FL +#define WGS_COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L +#define WGS_COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//WGS_COMPUTE_DISPATCH_ID +#define WGS_COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//WGS_COMPUTE_THREADGROUP_ID +#define WGS_COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define WGS_COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//WGS_COMPUTE_REQ_CTRL +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 +#define WGS_COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define WGS_COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define WGS_COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define WGS_COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define WGS_COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L +#define WGS_COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define WGS_COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define WGS_COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define WGS_COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +#define WGS_COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE8 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_USER_ACCUM_0 +#define WGS_COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_USER_ACCUM_1 +#define WGS_COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_USER_ACCUM_2 +#define WGS_COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_USER_ACCUM_3 +#define WGS_COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_PGM_RSRC3 +#define WGS_COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 +#define WGS_COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT 0x4 +#define WGS_COMPUTE_PGM_RSRC3__GLG_EN__SHIFT 0xd +#define WGS_COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT 0x1f +#define WGS_COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL +#define WGS_COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK 0x00000FF0L +#define WGS_COMPUTE_PGM_RSRC3__GLG_EN_MASK 0x00002000L +#define WGS_COMPUTE_PGM_RSRC3__IMAGE_OP_MASK 0x80000000L +//WGS_COMPUTE_DDID_INDEX +#define WGS_COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 +#define WGS_COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL +//WGS_COMPUTE_SHADER_CHKSUM +#define WGS_COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define WGS_COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE4 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE5 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE6 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE7 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_DISPATCH_INTERLEAVE +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE__SHIFT 0x10 +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE__SHIFT 0x18 +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D_MASK 0x000003FFL +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE_MASK 0x000F0000L +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE_MASK 0x0F000000L +//WGS_COMPUTE_RELAUNCH +#define WGS_COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define WGS_COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define WGS_COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define WGS_COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define WGS_COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define WGS_COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//WGS_COMPUTE_WAVE_RESTORE_ADDR_LO +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//WGS_COMPUTE_WAVE_RESTORE_ADDR_HI +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0x0000FFFFL +//WGS_COMPUTE_RELAUNCH2 +#define WGS_COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 +#define WGS_COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e +#define WGS_COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f +#define WGS_COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL +#define WGS_COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L +#define WGS_COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L +//WGS_COMPUTE_PRESCALED_DIM_X +#define WGS_COMPUTE_PRESCALED_DIM_X__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_PRESCALED_DIM_X__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_PRESCALED_DIM_Y +#define WGS_COMPUTE_PRESCALED_DIM_Y__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_PRESCALED_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_PRESCALED_DIM_Z +#define WGS_COMPUTE_PRESCALED_DIM_Z__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_PRESCALED_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_0 +#define WGS_COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_1 +#define WGS_COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_2 +#define WGS_COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_3 +#define WGS_COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_4 +#define WGS_COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_5 +#define WGS_COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_6 +#define WGS_COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_7 +#define WGS_COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_8 +#define WGS_COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_9 +#define WGS_COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_10 +#define WGS_COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_11 +#define WGS_COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_12 +#define WGS_COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_13 +#define WGS_COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_14 +#define WGS_COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_15 +#define WGS_COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DISPATCH_TUNNEL +#define WGS_COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x00001FFFL +//WGS_COMPUTE_DISPATCH_END +#define WGS_COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_NOWHERE +#define WGS_COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define WGS_COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_wgsdec +//WGS_MGCG_SYNC_CNTL +#define WGS_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define WGS_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define WGS_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define WGS_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//WGS_INT_INFO +#define WGS_INT_INFO__RING_ID__SHIFT 0x0 +#define WGS_INT_INFO__VMID__SHIFT 0x8 +#define WGS_INT_INFO__RING_ID_MASK 0x000000FFL +#define WGS_INT_INFO__VMID_MASK 0x00000F00L +//WGS_INT_CNTXID_LO +#define WGS_INT_CNTXID_LO__DATA__SHIFT 0x0 +#define WGS_INT_CNTXID_LO__DATA_MASK 0xFFFFFFFFL +//WGS_INT_CNTXID_HI +#define WGS_INT_CNTXID_HI__DATA__SHIFT 0x0 +#define WGS_INT_CNTXID_HI__DATA_MASK 0x000000FFL +//WGS_ERROR +#define WGS_ERROR__RESERVED__SHIFT 0x0 +#define WGS_ERROR__RESERVED_MASK 0xFFFFFFFFL +//WGS_ENDIAN_SWAP +#define WGS_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 +#define WGS_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x00000003L +//WGS_GEN_BASE_LO +#define WGS_GEN_BASE_LO__BASE_LO__SHIFT 0xc +#define WGS_GEN_BASE_LO__BASE_LO_MASK 0xFFFFF000L +//WGS_GEN_BASE_HI +#define WGS_GEN_BASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_GEN_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CGTT_WGS_CLK_CTRL +#define CGTT_WGS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WGS_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_WGS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_WGS_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//WGS_ME1_UCODE_ADDR +#define WGS_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define WGS_ME1_UCODE_ADDR__PIPE_SEL__SHIFT 0x1e +#define WGS_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x007FFFFFL +#define WGS_ME1_UCODE_ADDR__PIPE_SEL_MASK 0xC0000000L +//WGS_ME1_UCODE_DATA +#define WGS_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define WGS_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//WGS_ME1_UCODE_CHKSUM +#define WGS_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define WGS_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//WGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//WGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//WGS_SUSPEND_CTX_SAVE_CONTROL +#define WGS_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define WGS_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define WGS_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define WGS_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//WGS_SUSPEND_CNTL_STACK_OFFSET +#define WGS_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define WGS_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//WGS_SUSPEND_CNTL_STACK_SIZE +#define WGS_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define WGS_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//WGS_SUSPEND_WG_STATE_OFFSET +#define WGS_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define WGS_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//WGS_SUSPEND_CTX_SAVE_SIZE +#define WGS_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define WGS_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//WGS_OS_PIPES +#define WGS_OS_PIPES__OS_PIPES__SHIFT 0x0 +#define WGS_OS_PIPES__OS_PIPES_MASK 0x000000FFL +//WGS_SUSPEND_RESUME_REQ +#define WGS_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 +#define WGS_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 +#define WGS_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L +#define WGS_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L +//WGS_IQ_WAIT_TIME3 +#define WGS_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 +#define WGS_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL +//WGS_DDID_BASE_ADDR_LO +#define WGS_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define WGS_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//WGS_DDID_BASE_ADDR_HI +#define WGS_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define WGS_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//WGS_DDID_CNTL +#define WGS_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define WGS_DDID_CNTL__SIZE__SHIFT 0x10 +#define WGS_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define WGS_DDID_CNTL__POLICY__SHIFT 0x1c +#define WGS_DDID_CNTL__MODE__SHIFT 0x1e +#define WGS_DDID_CNTL__ENABLE__SHIFT 0x1f +#define WGS_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define WGS_DDID_CNTL__SIZE_MASK 0x00010000L +#define WGS_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define WGS_DDID_CNTL__POLICY_MASK 0x30000000L +#define WGS_DDID_CNTL__MODE_MASK 0x40000000L +#define WGS_DDID_CNTL__ENABLE_MASK 0x80000000L +//WGS_RS64_PRGRM_CNTR_START +#define WGS_RS64_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define WGS_RS64_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//WGS_MTVEC_LO +#define WGS_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define WGS_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//WGS_MTVEC_HI +#define WGS_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define WGS_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//WGS_RS64_CNTL +#define WGS_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define WGS_RS64_CNTL__RSRV8__SHIFT 0x10 +#define WGS_RS64_CNTL__RSRV7__SHIFT 0x11 +#define WGS_RS64_CNTL__RSRV6__SHIFT 0x12 +#define WGS_RS64_CNTL__RSRV5__SHIFT 0x13 +#define WGS_RS64_CNTL__RSRV4__SHIFT 0x1a +#define WGS_RS64_CNTL__RSRV3__SHIFT 0x1b +#define WGS_RS64_CNTL__RSRV2__SHIFT 0x1c +#define WGS_RS64_CNTL__RSRV1__SHIFT 0x1d +#define WGS_RS64_CNTL__MEC_HALT__SHIFT 0x1e +#define WGS_RS64_CNTL__MEC_STEP__SHIFT 0x1f +#define WGS_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define WGS_RS64_CNTL__RSRV8_MASK 0x00010000L +#define WGS_RS64_CNTL__RSRV7_MASK 0x00020000L +#define WGS_RS64_CNTL__RSRV6_MASK 0x00040000L +#define WGS_RS64_CNTL__RSRV5_MASK 0x00080000L +#define WGS_RS64_CNTL__RSRV4_MASK 0x04000000L +#define WGS_RS64_CNTL__RSRV3_MASK 0x08000000L +#define WGS_RS64_CNTL__RSRV2_MASK 0x10000000L +#define WGS_RS64_CNTL__RSRV1_MASK 0x20000000L +#define WGS_RS64_CNTL__MEC_HALT_MASK 0x40000000L +#define WGS_RS64_CNTL__MEC_STEP_MASK 0x80000000L +//WGS_MIE_LO +#define WGS_MIE_LO__MEC_INT__SHIFT 0x0 +#define WGS_MIE_LO__MEC_INT_MASK 0xFFFFFFFFL +//WGS_MIE_HI +#define WGS_MIE_HI__MEC_INT__SHIFT 0x0 +#define WGS_MIE_HI__MEC_INT_MASK 0xFFFFFFFFL +//WGS_RS64_INTERRUPT +#define WGS_RS64_INTERRUPT__MEC_INT__SHIFT 0x0 +#define WGS_RS64_INTERRUPT__MEC_INT_MASK 0xFFFFFFFFL +//WGS_RS64_INSTR_PNTR +#define WGS_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define WGS_RS64_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//WGS_MIP_LO +#define WGS_MIP_LO__MIP_LO__SHIFT 0x0 +#define WGS_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//WGS_MIP_HI +#define WGS_MIP_HI__MIP_HI__SHIFT 0x0 +#define WGS_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//WGS_DC_BASE_CNTL +#define WGS_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define WGS_DC_BASE_CNTL__VMID_MASK 0x0000000FL +//WGS_DC_OP_CNTL +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define WGS_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define WGS_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//WGS_MTIMECMP_LO +#define WGS_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define WGS_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//WGS_MTIMECMP_HI +#define WGS_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define WGS_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//WGS_GP0_LO +#define WGS_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define WGS_GP0_LO__DATA__SHIFT 0x1 +#define WGS_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define WGS_GP0_LO__DATA_MASK 0xFFFFFFFEL +//WGS_GP0_HI +#define WGS_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define WGS_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//WGS_GP1_LO +#define WGS_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define WGS_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//WGS_GP1_HI +#define WGS_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define WGS_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//WGS_GP2_LO +#define WGS_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define WGS_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//WGS_GP2_HI +#define WGS_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define WGS_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//WGS_GP3_LO +#define WGS_GP3_LO__DATA__SHIFT 0x0 +#define WGS_GP3_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP3_HI +#define WGS_GP3_HI__DATA__SHIFT 0x0 +#define WGS_GP3_HI__DATA_MASK 0xFFFFFFFFL +//WGS_GP4_LO +#define WGS_GP4_LO__DATA__SHIFT 0x0 +#define WGS_GP4_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP4_HI +#define WGS_GP4_HI__DATA__SHIFT 0x0 +#define WGS_GP4_HI__DATA_MASK 0xFFFFFFFFL +//WGS_GP5_LO +#define WGS_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define WGS_GP5_LO__DATA__SHIFT 0x1 +#define WGS_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define WGS_GP5_LO__DATA_MASK 0xFFFFFFFEL +//WGS_GP5_HI +#define WGS_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define WGS_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//WGS_GP6_LO +#define WGS_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define WGS_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//WGS_GP6_HI +#define WGS_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define WGS_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//WGS_GP7_LO +#define WGS_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define WGS_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//WGS_GP7_HI +#define WGS_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define WGS_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//WGS_GP8_LO +#define WGS_GP8_LO__DATA__SHIFT 0x0 +#define WGS_GP8_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP8_HI +#define WGS_GP8_HI__DATA__SHIFT 0x0 +#define WGS_GP8_HI__DATA_MASK 0xFFFFFFFFL +//WGS_GP9_LO +#define WGS_GP9_LO__DATA__SHIFT 0x0 +#define WGS_GP9_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP9_HI +#define WGS_GP9_HI__DATA__SHIFT 0x0 +#define WGS_GP9_HI__DATA_MASK 0xFFFFFFFFL +//WGS_DM_INDEX_ADDR +#define WGS_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define WGS_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//WGS_DM_INDEX_DATA +#define WGS_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define WGS_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//WGS_LOCAL_BASE0_LO +#define WGS_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define WGS_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//WGS_LOCAL_BASE0_HI +#define WGS_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define WGS_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//WGS_LOCAL_MASK0_LO +#define WGS_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define WGS_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//WGS_LOCAL_MASK0_HI +#define WGS_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define WGS_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//WGS_LOCAL_APERTURE +#define WGS_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define WGS_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define WGS_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define WGS_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define WGS_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define WGS_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//WGS_LOCAL_INSTR_BASE_LO +#define WGS_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define WGS_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//WGS_LOCAL_INSTR_BASE_HI +#define WGS_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//WGS_LOCAL_INSTR_MASK_LO +#define WGS_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define WGS_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//WGS_LOCAL_INSTR_MASK_HI +#define WGS_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define WGS_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//WGS_LOCAL_INSTR_APERTURE +#define WGS_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define WGS_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define WGS_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define WGS_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define WGS_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define WGS_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//WGS_LOCAL_SCRATCH_APERTURE +#define WGS_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define WGS_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//WGS_LOCAL_SCRATCH_BASE_LO +#define WGS_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define WGS_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//WGS_LOCAL_SCRATCH_BASE_HI +#define WGS_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//WGS_RS64_PERFCOUNT_CNTL +#define WGS_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define WGS_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//WGS_RS64_PENDING_INTERRUPT +#define WGS_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define WGS_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//WGS_RS64_EXCEPTION_STATUS +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//WGS_RS64_PRGRM_CNTR_START_HI +#define WGS_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define WGS_RS64_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//WGS_DC_BASE_LO +#define WGS_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define WGS_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//WGS_MDBASE_LO +#define WGS_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define WGS_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//WGS_DC_BASE_HI +#define WGS_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define WGS_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL +//WGS_MDBASE_HI +#define WGS_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL +//WGS_MIBOUND_LO +#define WGS_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define WGS_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//WGS_MIBOUND_HI +#define WGS_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define WGS_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//WGS_MDBOUND_LO +#define WGS_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define WGS_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//WGS_MDBOUND_HI +#define WGS_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define WGS_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//WGS_IC_OP_CNTL +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define WGS_IC_OP_CNTL__HALT_ON_PRIME__SHIFT 0x2 +#define WGS_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define WGS_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define WGS_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define WGS_IC_OP_CNTL__HALT_ON_PRIME_MASK 0x00000004L +#define WGS_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define WGS_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define WGS_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//WGS_INT_STATUS +#define WGS_INT_STATUS__SOURCE_ID__SHIFT 0x0 +#define WGS_INT_STATUS__SEND__SHIFT 0x8 +#define WGS_INT_STATUS__SOURCE_ID_MASK 0x000000FFL +#define WGS_INT_STATUS__SEND_MASK 0x00000100L +//WGS_IH_FREE_COUNT +#define WGS_IH_FREE_COUNT__COUNT__SHIFT 0x0 +#define WGS_IH_FREE_COUNT__COUNT_MASK 0x000000FFL +//WGS_ME1_PIPE_PRIORITY_CNTS +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//WGS_ME1_PIPE0_PRIORITY +#define WGS_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_ME1_PIPE1_PRIORITY +#define WGS_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_ME1_PIPE2_PRIORITY +#define WGS_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_ME1_PIPE3_PRIORITY +#define WGS_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_IQ_WAIT_TIME1 +#define WGS_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define WGS_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define WGS_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define WGS_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define WGS_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define WGS_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define WGS_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define WGS_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//WGS_IQ_WAIT_TIME2 +#define WGS_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define WGS_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define WGS_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define WGS_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define WGS_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define WGS_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//WGS_IC_BASE_LO +#define WGS_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define WGS_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//WGS_IC_BASE_HI +#define WGS_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define WGS_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//WGS_IC_BASE_CNTL +#define WGS_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define WGS_IC_BASE_CNTL__PER_PIPE__SHIFT 0x5 +#define WGS_IC_BASE_CNTL__SCOPE__SHIFT 0x6 +#define WGS_IC_BASE_CNTL__TEMPORAL__SHIFT 0x8 +#define WGS_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define WGS_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define WGS_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define WGS_IC_BASE_CNTL__PER_PIPE_MASK 0x00000020L +#define WGS_IC_BASE_CNTL__SCOPE_MASK 0x000000C0L +#define WGS_IC_BASE_CNTL__TEMPORAL_MASK 0x00000700L +#define WGS_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define WGS_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//WGS_UCODE_VERS +#define WGS_UCODE_VERS__ENGINE__SHIFT 0x0 +#define WGS_UCODE_VERS__COMMON__SHIFT 0xa +#define WGS_UCODE_VERS__HEADER__SHIFT 0x14 +#define WGS_UCODE_VERS__STEP__SHIFT 0x1e +#define WGS_UCODE_VERS__ENGINE_MASK 0x000003FFL +#define WGS_UCODE_VERS__COMMON_MASK 0x000FFC00L +#define WGS_UCODE_VERS__HEADER_MASK 0x3FF00000L +#define WGS_UCODE_VERS__STEP_MASK 0xC0000000L +//WGS_BUSY_HYSTERESIS +#define WGS_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT 0x0 +#define WGS_BUSY_HYSTERESIS__CPC_BUSY__SHIFT 0x8 +#define WGS_BUSY_HYSTERESIS__CAC_ACTIVE_MASK 0x000000FFL +#define WGS_BUSY_HYSTERESIS__CPC_BUSY_MASK 0x0000FF00L +//WGS_STATUS +#define WGS_STATUS__MEC1_BUSY__SHIFT 0x0 +#define WGS_STATUS__MEC2_BUSY__SHIFT 0x1 +#define WGS_STATUS__DC0_BUSY__SHIFT 0x2 +#define WGS_STATUS__DC1_BUSY__SHIFT 0x3 +#define WGS_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define WGS_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define WGS_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define WGS_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define WGS_STATUS__TMZ_STATE__SHIFT 0x8 +#define WGS_STATUS__VMID_TMZ__SHIFT 0x9 +#define WGS_STATUS__TCIU_BUSY__SHIFT 0xa +#define WGS_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define WGS_STATUS__QU_BUSY__SHIFT 0xc +#define WGS_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define WGS_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define WGS_STATUS__GCRIU_BUSY__SHIFT 0xf +#define WGS_STATUS__MES_BUSY__SHIFT 0x10 +#define WGS_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 +#define WGS_STATUS__RCIU3_BUSY__SHIFT 0x12 +#define WGS_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 +#define WGS_STATUS__MES_DATA_CACHE_BUSY__SHIFT 0x14 +#define WGS_STATUS__MEC_DATA_CACHE_BUSY__SHIFT 0x15 +#define WGS_STATUS__GL1_XNACK__SHIFT 0x16 +#define WGS_STATUS__RSRV__SHIFT 0x18 +#define WGS_STATUS__WGS_BUSY__SHIFT 0x1f +#define WGS_STATUS__MEC1_BUSY_MASK 0x00000001L +#define WGS_STATUS__MEC2_BUSY_MASK 0x00000002L +#define WGS_STATUS__DC0_BUSY_MASK 0x00000004L +#define WGS_STATUS__DC1_BUSY_MASK 0x00000008L +#define WGS_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define WGS_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define WGS_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define WGS_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define WGS_STATUS__TMZ_STATE_MASK 0x00000100L +#define WGS_STATUS__VMID_TMZ_MASK 0x00000200L +#define WGS_STATUS__TCIU_BUSY_MASK 0x00000400L +#define WGS_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define WGS_STATUS__QU_BUSY_MASK 0x00001000L +#define WGS_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define WGS_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define WGS_STATUS__GCRIU_BUSY_MASK 0x00008000L +#define WGS_STATUS__MES_BUSY_MASK 0x00010000L +#define WGS_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L +#define WGS_STATUS__RCIU3_BUSY_MASK 0x00040000L +#define WGS_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L +#define WGS_STATUS__MES_DATA_CACHE_BUSY_MASK 0x00100000L +#define WGS_STATUS__MEC_DATA_CACHE_BUSY_MASK 0x00200000L +#define WGS_STATUS__GL1_XNACK_MASK 0x00C00000L +#define WGS_STATUS__RSRV_MASK 0x7F000000L +#define WGS_STATUS__WGS_BUSY_MASK 0x80000000L +//WGS_BUSY_STAT +#define WGS_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define WGS_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define WGS_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define WGS_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define WGS_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define WGS_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define WGS_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define WGS_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define WGS_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define WGS_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define WGS_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define WGS_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define WGS_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define WGS_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define WGS_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define WGS_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define WGS_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define WGS_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define WGS_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define WGS_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define WGS_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define WGS_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define WGS_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define WGS_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define WGS_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define WGS_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define WGS_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define WGS_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define WGS_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define WGS_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define WGS_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define WGS_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define WGS_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define WGS_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define WGS_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define WGS_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define WGS_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define WGS_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define WGS_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define WGS_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define WGS_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define WGS_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define WGS_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define WGS_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define WGS_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define WGS_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define WGS_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define WGS_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define WGS_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define WGS_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define WGS_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define WGS_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//WGS_STALLED_STAT1 +#define WGS_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define WGS_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define WGS_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define WGS_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x7 +#define WGS_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define WGS_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define WGS_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define WGS_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 +#define WGS_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define WGS_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define WGS_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define WGS_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000080L +#define WGS_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define WGS_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define WGS_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +#define WGS_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L +//WGS_BUSY_STAT2 +#define WGS_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 +#define WGS_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 +#define WGS_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 +#define WGS_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 +#define WGS_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 +#define WGS_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa +#define WGS_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb +#define WGS_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc +#define WGS_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd +#define WGS_BUSY_STAT2__MEC1_PIPE0_DC_BUSY__SHIFT 0x12 +#define WGS_BUSY_STAT2__MEC1_PIPE1_DC_BUSY__SHIFT 0x13 +#define WGS_BUSY_STAT2__MEC1_PIPE2_DC_BUSY__SHIFT 0x14 +#define WGS_BUSY_STAT2__MEC1_PIPE3_DC_BUSY__SHIFT 0x15 +#define WGS_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L +#define WGS_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L +#define WGS_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L +#define WGS_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L +#define WGS_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L +#define WGS_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L +#define WGS_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L +#define WGS_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L +#define WGS_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L +#define WGS_BUSY_STAT2__MEC1_PIPE0_DC_BUSY_MASK 0x00040000L +#define WGS_BUSY_STAT2__MEC1_PIPE1_DC_BUSY_MASK 0x00080000L +#define WGS_BUSY_STAT2__MEC1_PIPE2_DC_BUSY_MASK 0x00100000L +#define WGS_BUSY_STAT2__MEC1_PIPE3_DC_BUSY_MASK 0x00200000L +//WGS_ME1_HEADER_DUMP +#define WGS_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define WGS_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//WGS_SCRATCH_INDEX +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//WGS_SCRATCH_DATA +#define WGS_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define WGS_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//WGS_LATENCY_STATS_SELECT +#define WGS_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define WGS_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define WGS_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define WGS_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define WGS_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define WGS_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//WGS_LATENCY_STATS_DATA +#define WGS_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define WGS_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//WGS_TC_PERF_COUNTER_WINDOW_SELECT +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//WGS_DATA1 +#define WGS_DATA1__DATA__SHIFT 0x0 +#define WGS_DATA1__DATA_MASK 0xFFFFFFFFL +//WGS_DATA2 +#define WGS_DATA2__DATA__SHIFT 0x0 +#define WGS_DATA2__DATA_MASK 0xFFFFFFFFL +//WGS_DATA3 +#define WGS_DATA3__DATA__SHIFT 0x0 +#define WGS_DATA3__DATA_MASK 0xFFFFFFFFL +//WGS_DATA4 +#define WGS_DATA4__DATA__SHIFT 0x0 +#define WGS_DATA4__DATA_MASK 0xFFFFFFFFL +//WGS_DATA5 +#define WGS_DATA5__DATA__SHIFT 0x0 +#define WGS_DATA5__DATA_MASK 0xFFFFFFFFL +//WGS_DATA6 +#define WGS_DATA6__DATA__SHIFT 0x0 +#define WGS_DATA6__DATA_MASK 0xFFFFFFFFL +//WGS_DATA7 +#define WGS_DATA7__DATA__SHIFT 0x0 +#define WGS_DATA7__DATA_MASK 0xFFFFFFFFL +//WGS_DATA8 +#define WGS_DATA8__DATA__SHIFT 0x0 +#define WGS_DATA8__DATA_MASK 0xFFFFFFFFL +//WGS_DATA9 +#define WGS_DATA9__DATA__SHIFT 0x0 +#define WGS_DATA9__DATA_MASK 0xFFFFFFFFL +//WGS_DATA10 +#define WGS_DATA10__DATA__SHIFT 0x0 +#define WGS_DATA10__DATA_MASK 0xFFFFFFFFL +//WGS_DATA11 +#define WGS_DATA11__DATA__SHIFT 0x0 +#define WGS_DATA11__DATA_MASK 0xFFFFFFFFL +//WGS_DATA12 +#define WGS_DATA12__DATA__SHIFT 0x0 +#define WGS_DATA12__DATA_MASK 0xFFFFFFFFL +//WGS_DATA13 +#define WGS_DATA13__DATA__SHIFT 0x0 +#define WGS_DATA13__DATA_MASK 0xFFFFFFFFL +//WGS_DATA14 +#define WGS_DATA14__DATA__SHIFT 0x0 +#define WGS_DATA14__DATA_MASK 0xFFFFFFFFL +//WGS_DATA15 +#define WGS_DATA15__DATA__SHIFT 0x0 +#define WGS_DATA15__DATA_MASK 0xFFFFFFFFL +//WGS_DATA16 +#define WGS_DATA16__DATA__SHIFT 0x0 +#define WGS_DATA16__DATA_MASK 0xFFFFFFFFL +//WGS_METADATA_BASE_ADDR_LO +#define WGS_METADATA_BASE_ADDR_LO__MD_BASE_LO__SHIFT 0x2 +#define WGS_METADATA_BASE_ADDR_LO__MD_BASE_LO_MASK 0xFFFFFFFCL +//WGS_METADATA_BASE_ADDR_HI +#define WGS_METADATA_BASE_ADDR_HI__MD_BASE_HI__SHIFT 0x0 +#define WGS_METADATA_BASE_ADDR_HI__MD_BASE_HI_MASK 0x0000FFFFL +//WGS_METADATA_CNTL +#define WGS_METADATA_CNTL__VMID__SHIFT 0x0 +#define WGS_METADATA_CNTL__EVENT_MODE__SHIFT 0x4 +#define WGS_METADATA_CNTL__SCOPE__SHIFT 0x6 +#define WGS_METADATA_CNTL__TEMPORAL__SHIFT 0x8 +#define WGS_METADATA_CNTL__EVENT1__SHIFT 0xb +#define WGS_METADATA_CNTL__QUEUE_ID__SHIFT 0xc +#define WGS_METADATA_CNTL__VMID_MASK 0x0000000FL +#define WGS_METADATA_CNTL__EVENT_MODE_MASK 0x00000030L +#define WGS_METADATA_CNTL__SCOPE_MASK 0x000000C0L +#define WGS_METADATA_CNTL__TEMPORAL_MASK 0x00000700L +#define WGS_METADATA_CNTL__EVENT1_MASK 0x00000800L +#define WGS_METADATA_CNTL__QUEUE_ID_MASK 0x00007000L +//WGS_IQ_TIMER +#define WGS_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define WGS_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define WGS_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define WGS_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define WGS_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define WGS_IQ_TIMER__RESERVED3__SHIFT 0x10 +#define WGS_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define WGS_IQ_TIMER__RESERVED2__SHIFT 0x17 +#define WGS_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define WGS_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define WGS_IQ_TIMER__RESERVED1__SHIFT 0x1d +#define WGS_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define WGS_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define WGS_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define WGS_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define WGS_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define WGS_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define WGS_IQ_TIMER__RESERVED3_MASK 0x003F0000L +#define WGS_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define WGS_IQ_TIMER__RESERVED2_MASK 0x07800000L +#define WGS_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define WGS_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define WGS_IQ_TIMER__RESERVED1_MASK 0x60000000L +#define WGS_IQ_TIMER__ACTIVE_MASK 0x80000000L +//WGS_HALT_HYST_COUNT +#define WGS_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define WGS_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//WGS_IQ_TIMER_MESSAGE +#define WGS_IQ_TIMER_MESSAGE__MESSAGE__SHIFT 0x0 +#define WGS_IQ_TIMER_MESSAGE__MESSAGE_MASK 0x000000FFL +//WGS_RS64_THREAD_CNTL +#define WGS_RS64_THREAD_CNTL__MEC_STATUS__SHIFT 0x0 +#define WGS_RS64_THREAD_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_RESET__SHIFT 0x10 +#define WGS_RS64_THREAD_CNTL__RSRV7__SHIFT 0x11 +#define WGS_RS64_THREAD_CNTL__RSRV6__SHIFT 0x12 +#define WGS_RS64_THREAD_CNTL__RSRV5__SHIFT 0x13 +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_ACTIVE__SHIFT 0x1a +#define WGS_RS64_THREAD_CNTL__RSRV4__SHIFT 0x1b +#define WGS_RS64_THREAD_CNTL__RSRV3__SHIFT 0x1c +#define WGS_RS64_THREAD_CNTL__RSRV2__SHIFT 0x1d +#define WGS_RS64_THREAD_CNTL__SPARE__SHIFT 0x1e +#define WGS_RS64_THREAD_CNTL__RSRV1__SHIFT 0x1f +#define WGS_RS64_THREAD_CNTL__MEC_STATUS_MASK 0x0000000FL +#define WGS_RS64_THREAD_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_RESET_MASK 0x00010000L +#define WGS_RS64_THREAD_CNTL__RSRV7_MASK 0x00020000L +#define WGS_RS64_THREAD_CNTL__RSRV6_MASK 0x00040000L +#define WGS_RS64_THREAD_CNTL__RSRV5_MASK 0x00080000L +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_ACTIVE_MASK 0x04000000L +#define WGS_RS64_THREAD_CNTL__RSRV4_MASK 0x08000000L +#define WGS_RS64_THREAD_CNTL__RSRV3_MASK 0x10000000L +#define WGS_RS64_THREAD_CNTL__RSRV2_MASK 0x20000000L +#define WGS_RS64_THREAD_CNTL__SPARE_MASK 0x40000000L +#define WGS_RS64_THREAD_CNTL__RSRV1_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1dec +//GL1_ARB_CTRL +#define GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define GL1_ARB_CTRL__FGCG_DISABLE__SHIFT 0x4 +#define GL1_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x5 +#define GL1_ARB_CTRL__CHICKEN_BITS__SHIFT 0x6 +#define GL1_ARB_CTRL__RETURN_ARB_MODE_COUNTER__SHIFT 0xe +#define GL1_ARB_CTRL__RETURN_256B_ARB_MODE_COUNTER__SHIFT 0x12 +#define GL1_ARB_CTRL__NUM_MEM_PIPES_MASK 0x0000000FL +#define GL1_ARB_CTRL__FGCG_DISABLE_MASK 0x00000010L +#define GL1_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000020L +#define GL1_ARB_CTRL__CHICKEN_BITS_MASK 0x00003FC0L +#define GL1_ARB_CTRL__RETURN_ARB_MODE_COUNTER_MASK 0x0003C000L +#define GL1_ARB_CTRL__RETURN_256B_ARB_MODE_COUNTER_MASK 0x003C0000L +//GL1_DRAM_BURST_MASK +#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GL1_ARB_STATUS +#define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GL1_DRAM_BURST_CTRL +#define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +//GL1I_GL1R_REP_FGCG_OVERRIDE +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GL1A_GL1C_CREDITS +#define GL1A_GL1C_CREDITS__GL1C_REQ_CREDITS__SHIFT 0x0 +#define GL1A_GL1C_CREDITS__GL1C_DATA_CREDITS__SHIFT 0x8 +#define GL1A_GL1C_CREDITS__GL1C_REQ_CREDITS_MASK 0x000000FFL +#define GL1A_GL1C_CREDITS__GL1C_DATA_CREDITS_MASK 0x0000FF00L +//GL1A_CLIENT_FREE_DELAY +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +//GL1X_ARB_CTRL +#define GL1X_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define GL1X_ARB_CTRL__FGCG_DISABLE__SHIFT 0x2 +#define GL1X_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x3 +#define GL1X_ARB_CTRL__CHICKEN_BITS__SHIFT 0x4 +#define GL1X_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000003L +#define GL1X_ARB_CTRL__FGCG_DISABLE_MASK 0x00000004L +#define GL1X_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000008L +#define GL1X_ARB_CTRL__CHICKEN_BITS_MASK 0x00000FF0L +//GL1X_DRAM_BURST_MASK +#define GL1X_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GL1X_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GL1X_ARB_STATUS +#define GL1X_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GL1X_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GL1X_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GL1X_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GL1X_DRAM_BURST_CTRL +#define GL1X_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define GL1X_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GL1X_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define GL1X_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +//GL1XI_GL1XR_REP_FGCG_OVERRIDE +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIR_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIW_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIR_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIW_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GL1XA_GL1XC_CREDITS +#define GL1XA_GL1XC_CREDITS__GL1XC_REQ_CREDITS__SHIFT 0x0 +#define GL1XA_GL1XC_CREDITS__GL1XC_DATA_CREDITS__SHIFT 0x8 +#define GL1XA_GL1XC_CREDITS__GL1XC_REQ_CREDITS_MASK 0x000000FFL +#define GL1XA_GL1XC_CREDITS__GL1XC_DATA_CREDITS_MASK 0x0000FF00L +//GL1XA_CLIENT_FREE_DELAY +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY__SHIFT 0xf +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY_MASK 0x00038000L +//GL1XA_COMPRESSION_MODE +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_OVERRIDE__SHIFT 0x0 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_WRITE_COMPRESSION_DISABLE__SHIFT 0x1 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_BYPASS_COMPRESSION__SHIFT 0x2 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_OVERRIDE__SHIFT 0x3 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_WRITE_COMPRESSION_DISABLE__SHIFT 0x4 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_BYPASS_COMPRESSION__SHIFT 0x5 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_OVERRIDE__SHIFT 0x6 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_WRITE_COMPRESSION_DISABLE__SHIFT 0x7 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_BYPASS_COMPRESSION__SHIFT 0x8 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_OVERRIDE__SHIFT 0x9 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_WRITE_COMPRESSION_DISABLE__SHIFT 0xa +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_BYPASS_COMPRESSION__SHIFT 0xb +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_OVERRIDE__SHIFT 0xc +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_WRITE_COMPRESSION_DISABLE__SHIFT 0xd +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_BYPASS_COMPRESSION__SHIFT 0xe +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_OVERRIDE__SHIFT 0xf +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_WRITE_COMPRESSION_DISABLE__SHIFT 0x10 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_BYPASS_COMPRESSION__SHIFT 0x11 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_OVERRIDE__SHIFT 0x12 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_WRITE_COMPRESSION_DISABLE__SHIFT 0x13 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_BYPASS_COMPRESSION__SHIFT 0x14 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_OVERRIDE__SHIFT 0x15 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_WRITE_COMPRESSION_DISABLE__SHIFT 0x16 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_BYPASS_COMPRESSION__SHIFT 0x17 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_OVERRIDE_MASK 0x00000001L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_WRITE_COMPRESSION_DISABLE_MASK 0x00000002L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_BYPASS_COMPRESSION_MASK 0x00000004L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_OVERRIDE_MASK 0x00000008L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_WRITE_COMPRESSION_DISABLE_MASK 0x00000010L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_BYPASS_COMPRESSION_MASK 0x00000020L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_OVERRIDE_MASK 0x00000040L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_WRITE_COMPRESSION_DISABLE_MASK 0x00000080L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_BYPASS_COMPRESSION_MASK 0x00000100L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_OVERRIDE_MASK 0x00000200L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_WRITE_COMPRESSION_DISABLE_MASK 0x00000400L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_BYPASS_COMPRESSION_MASK 0x00000800L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_OVERRIDE_MASK 0x00001000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_WRITE_COMPRESSION_DISABLE_MASK 0x00002000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_BYPASS_COMPRESSION_MASK 0x00004000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_OVERRIDE_MASK 0x00008000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_WRITE_COMPRESSION_DISABLE_MASK 0x00010000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_BYPASS_COMPRESSION_MASK 0x00020000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_OVERRIDE_MASK 0x00040000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_WRITE_COMPRESSION_DISABLE_MASK 0x00080000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_BYPASS_COMPRESSION_MASK 0x00100000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_OVERRIDE_MASK 0x00200000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_WRITE_COMPRESSION_DISABLE_MASK 0x00400000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_BYPASS_COMPRESSION_MASK 0x00800000L +//GL1XA_COMPRESSOR_OVERRIDE +#define GL1XA_COMPRESSOR_OVERRIDE__DATA_FORMAT__SHIFT 0x0 +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_COMP_BLOCK_SIZE__SHIFT 0x7 +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_UNCOMP_BLOCK_SIZE__SHIFT 0x9 +#define GL1XA_COMPRESSOR_OVERRIDE__MICRO_TILE_MODE__SHIFT 0xa +#define GL1XA_COMPRESSOR_OVERRIDE__NUM_SAMPLES_LOG2__SHIFT 0xc +#define GL1XA_COMPRESSOR_OVERRIDE__NUMBER_TYPE__SHIFT 0xe +#define GL1XA_COMPRESSOR_OVERRIDE__DATA_FORMAT_MASK 0x0000003FL +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_COMP_BLOCK_SIZE_MASK 0x00000180L +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_UNCOMP_BLOCK_SIZE_MASK 0x00000200L +#define GL1XA_COMPRESSOR_OVERRIDE__MICRO_TILE_MODE_MASK 0x00000C00L +#define GL1XA_COMPRESSOR_OVERRIDE__NUM_SAMPLES_LOG2_MASK 0x00003000L +#define GL1XA_COMPRESSOR_OVERRIDE__NUMBER_TYPE_MASK 0x0001C000L +//GL1C_CTRL +#define GL1C_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define GL1C_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define GL1C_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define GL1C_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define GL1C_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define GL1C_CTRL__GL1C_LDBDCST_TIMER__SHIFT 0x14 +#define GL1C_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define GL1C_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define GL1C_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define GL1C_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define GL1C_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define GL1C_CTRL__GL1C_LDBDCST_TIMER_MASK 0x1FF00000L +//GL1C_STATUS +#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GL1C_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define GL1C_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define GL1C_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define GL1C_STATUS__BUFFER_FULL__SHIFT 0x17 +#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GL1C_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define GL1C_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define GL1C_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define GL1C_STATUS__BUFFER_FULL_MASK 0x00800000L +//GL1C_CTRL2 +#define GL1C_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED__SHIFT 0x8 +#define GL1C_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE__SHIFT 0x9 +#define GL1C_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED_MASK 0x00000100L +#define GL1C_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE_MASK 0x00000200L +//GL1XC_CTRL +#define GL1XC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define GL1XC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define GL1XC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define GL1XC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define GL1XC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define GL1XC_CTRL__GCR_RSP_FGCG_DISABLE__SHIFT 0x14 +#define GL1XC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define GL1XC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define GL1XC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define GL1XC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define GL1XC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define GL1XC_CTRL__GCR_RSP_FGCG_DISABLE_MASK 0x00100000L +//GL1XC_STATUS +#define GL1XC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GL1XC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GL1XC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GL1XC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GL1XC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GL1XC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GL1XC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GL1XC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GL1XC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GL1XC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GL1XC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define GL1XC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define GL1XC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define GL1XC_STATUS__BUFFER_FULL__SHIFT 0x17 +#define GL1XC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GL1XC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GL1XC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GL1XC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GL1XC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GL1XC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GL1XC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GL1XC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GL1XC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GL1XC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GL1XC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define GL1XC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define GL1XC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define GL1XC_STATUS__BUFFER_FULL_MASK 0x00800000L +//GL1XC_UTCL0_CNTL1 +#define GL1XC_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define GL1XC_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define GL1XC_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define GL1XC_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define GL1XC_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define GL1XC_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define GL1XC_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define GL1XC_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define GL1XC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE__SHIFT 0x19 +#define GL1XC_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define GL1XC_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define GL1XC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define GL1XC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define GL1XC_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define GL1XC_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define GL1XC_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define GL1XC_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define GL1XC_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define GL1XC_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define GL1XC_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define GL1XC_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define GL1XC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE_MASK 0x02000000L +#define GL1XC_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define GL1XC_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define GL1XC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define GL1XC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//GL1XC_UTCL0_CNTL2 +#define GL1XC_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define GL1XC_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define GL1XC_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define GL1XC_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define GL1XC_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define GL1XC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define GL1XC_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define GL1XC_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC__SHIFT 0x1f +#define GL1XC_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define GL1XC_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define GL1XC_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define GL1XC_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define GL1XC_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define GL1XC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define GL1XC_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define GL1XC_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC_MASK 0x80000000L +//GL1XC_UTCL0_STATUS +#define GL1XC_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define GL1XC_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define GL1XC_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define GL1XC_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define GL1XC_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define GL1XC_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +//GL1XC_UTCL0_RETRY +#define GL1XC_UTCL0_RETRY__INCR__SHIFT 0x0 +#define GL1XC_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define GL1XC_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define GL1XC_UTCL0_RETRY__COUNT_MASK 0x00000F00L +//GL1XC_CTRL2 +#define GL1XC_CTRL2__UTCL0_INFLIGHT_MAX__SHIFT 0x0 +#define GL1XC_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED__SHIFT 0x8 +#define GL1XC_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE__SHIFT 0x9 +#define GL1XC_CTRL2__UTCL0_INFLIGHT_MAX_MASK 0x000000FFL +#define GL1XC_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED_MASK 0x00000100L +#define GL1XC_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE_MASK 0x00000200L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_secacdec +//SE_CAC_CTRL_1 +#define SE_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define SE_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 +#define SE_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL +#define SE_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L +//SE_CAC_CTRL_2 +#define SE_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define SE_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x1 +#define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE__SHIFT 0x2 +#define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x3 +#define SE_CAC_CTRL_2__SE_LCAC_OVR_EN__SHIFT 0x4 +#define SE_CAC_CTRL_2__WGP_LCAC_OVR_EN__SHIFT 0x5 +#define SE_CAC_CTRL_2__WGP_LCAC_MODE__SHIFT 0x6 +#define SE_CAC_CTRL_2__SE_CAC_SOFT_CTRL_ENABLE__SHIFT 0x7 +#define SE_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define SE_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000002L +#define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE_MASK 0x00000004L +#define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000008L +#define SE_CAC_CTRL_2__SE_LCAC_OVR_EN_MASK 0x00000010L +#define SE_CAC_CTRL_2__WGP_LCAC_OVR_EN_MASK 0x00000020L +#define SE_CAC_CTRL_2__WGP_LCAC_MODE_MASK 0x00000040L +#define SE_CAC_CTRL_2__SE_CAC_SOFT_CTRL_ENABLE_MASK 0x00000080L +//SE_CAC_SOFT_CTRL +#define SE_CAC_SOFT_CTRL__SE_CAC_SOFT_SNAP__SHIFT 0x0 +#define SE_CAC_SOFT_CTRL__SE_CAC_SOFT_SNAP_MASK 0x00000001L +//SE_CAC_OVR_VAL_LOWER +#define SE_CAC_OVR_VAL_LOWER__SE_LCAC_OVR_VAL_LOWER__SHIFT 0x0 +#define SE_CAC_OVR_VAL_LOWER__SE_LCAC_OVR_VAL_LOWER_MASK 0xFFFFFFFFL +//SE_CAC_OVR_VAL_UPPER +#define SE_CAC_OVR_VAL_UPPER__SE_LCAC_OVR_VAL_UPPER__SHIFT 0x0 +#define SE_CAC_OVR_VAL_UPPER__SE_LCAC_OVR_VAL_UPPER_MASK 0xFFFFFFFFL +//SE_CAC_WINDOW_AGGR_VALUE_LO +#define SE_CAC_WINDOW_AGGR_VALUE_LO__SE_CAC_WINDOW_AGGR_VALUE_LO__SHIFT 0x0 +#define SE_CAC_WINDOW_AGGR_VALUE_LO__SE_CAC_WINDOW_AGGR_VALUE_LO_MASK 0xFFFFFFFFL +//SE_CAC_WINDOW_AGGR_VALUE_HI +#define SE_CAC_WINDOW_AGGR_VALUE_HI__SE_CAC_WINDOW_AGGR_VALUE_HI__SHIFT 0x0 +#define SE_CAC_WINDOW_AGGR_VALUE_HI__SE_CAC_WINDOW_AGGR_VALUE_HI_MASK 0x000000FFL +//SE_CAC_WINDOW_GFXCLK_CYCLE +#define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE__SHIFT 0x0 +#define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE_MASK 0x0000FFFFL +//DIDT_EDC_CTRL +#define DIDT_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0xa +#define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xe +#define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0xf +#define DIDT_EDC_CTRL__EDC_AVGDIV__SHIFT 0x10 +#define DIDT_EDC_CTRL__EDC_THRESHOLD_SEL__SHIFT 0x14 +#define DIDT_EDC_CTRL__EDC_PERF_COUNTER_EN__SHIFT 0x15 +#define DIDT_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L +#define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x00003C00L +#define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00004000L +#define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00008000L +#define DIDT_EDC_CTRL__EDC_AVGDIV_MASK 0x000F0000L +#define DIDT_EDC_CTRL__EDC_THRESHOLD_SEL_MASK 0x00100000L +#define DIDT_EDC_CTRL__EDC_PERF_COUNTER_EN_MASK 0x00200000L +//DIDT_EDC_THROTTLE_CTRL +#define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN__SHIFT 0x0 +#define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN__SHIFT 0x1 +#define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN__SHIFT 0x2 +#define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN__SHIFT 0x3 +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN__SHIFT 0x4 +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE__SHIFT 0x5 +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_EN__SHIFT 0x8 +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_SRC_SEL__SHIFT 0x9 +#define DIDT_EDC_THROTTLE_CTRL__EDC_MAX_HYSTERESIS__SHIFT 0xa +#define DIDT_EDC_THROTTLE_CTRL__EDC_STALL_CLAMP_EN__SHIFT 0x12 +#define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN_MASK 0x00000001L +#define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN_MASK 0x00000002L +#define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN_MASK 0x00000004L +#define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN_MASK 0x00000008L +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN_MASK 0x00000010L +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE_MASK 0x000000E0L +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_EN_MASK 0x00000100L +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_SRC_SEL_MASK 0x00000200L +#define DIDT_EDC_THROTTLE_CTRL__EDC_MAX_HYSTERESIS_MASK 0x0003FC00L +#define DIDT_EDC_THROTTLE_CTRL__EDC_STALL_CLAMP_EN_MASK 0x00040000L +//DIDT_EDC_THRESHOLD +#define DIDT_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_EDC_STRETCH_THRESHOLD +#define DIDT_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_EDC_CLK_COUNTER_THRESHOLD +#define DIDT_EDC_CLK_COUNTER_THRESHOLD__EDC_CLK_COUNTER_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_CLK_COUNTER_THRESHOLD__EDC_CLK_COUNTER_THRESHOLD_MASK 0x0000FFFFL +//DIDT_EDC_STALL_PATTERN_1_2 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_3_4 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_5_6 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_7 +#define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_EDC_STATUS +#define DIDT_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_EDC_STATUS__EDC_HYSTERESIS_CNT__SHIFT 0x4 +#define DIDT_EDC_STATUS__EDC_THRESHOLD_STAT__SHIFT 0xc +#define DIDT_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +#define DIDT_EDC_STATUS__EDC_HYSTERESIS_CNT_MASK 0x00000FF0L +#define DIDT_EDC_STATUS__EDC_THRESHOLD_STAT_MASK 0x00001000L +//DIDT_EDC_OVERFLOW +#define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_EDC_ROLLING_POWER_DELTA +#define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_EDC_AVG_POWER_DELTA_HI +#define DIDT_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI_MASK 0xFFFFFFFFL +//DIDT_EDC_AVG_POWER_DELTA_LO +#define DIDT_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO__SHIFT 0x0 +#define DIDT_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO_MASK 0xFFFFFFFFL +//DIDT_EDC_STALL_PERF_COUNTER +#define DIDT_EDC_STALL_PERF_COUNTER__EDC_STALL_PERF_COUNTER__SHIFT 0x0 +#define DIDT_EDC_STALL_PERF_COUNTER__EDC_STALL_PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_THRESHOLD +#define DIDT_THRESHOLD__DIDT_THRESHOLD__SHIFT 0x0 +#define DIDT_THRESHOLD__DIDT_THRESHOLD_MASK 0xFFFFFFFFL +//SE_CAC_WEIGHT_LDS1_0 +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS1_1 +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS1_2 +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS1_3 +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_0 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_1 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_2 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_3 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_0 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_1 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_2 +#define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_SP_0 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SP_1 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SP_2 +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_0 +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_1 +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_2 +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_3 +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQC_0 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQC_1 +#define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_CU_0 +#define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_UTCL1_0 +#define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_GL1C_0 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_GL1C_1 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_0 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_1 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_2 +#define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_TCP_4 +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG8__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG9__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG8_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG9_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_5 +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG10__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG11__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG10_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG11_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_6 +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG12__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG13__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG12_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG13_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_7 +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG14__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG15__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG14_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG15_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_8 +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG16__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG17__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG16_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG17_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_9 +#define SE_CAC_WEIGHT_TCP_9__WEIGHT_TCP_SIG18__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_9__WEIGHT_TCP_SIG18_MASK 0x0000FFFFL +//SE_CAC_IND_INDEX +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//SE_CAC_IND_DATA +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfddec +//GE2_SE_PERFCOUNTER0_LO +#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER0_HI +#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER1_LO +#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER1_HI +#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER2_LO +#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER2_HI +#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER3_LO +#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER3_HI +#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER0_LO +#define GRBMH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER0_HI +#define GRBMH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER1_LO +#define GRBMH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER1_HI +#define GRBMH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_LO +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_LO +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_LO +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_LO +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_LO +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_LO +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_HI +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_LO +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_HI +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_LO +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_HI +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_LO +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_HI +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_LO +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_HI +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_LO +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_HI +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_LO +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_HI +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_HI +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_LO +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_HI +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_LO +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_HI +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_LO +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_HI +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_LO +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_HI +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_LO +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_HI +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_LO +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER0_HI +#define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER0_LO +#define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER1_HI +#define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER1_LO +#define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER2_HI +#define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER2_LO +#define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER3_HI +#define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER3_LO +#define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_LO +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_LO +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_LO +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_LO +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_LO +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_LO +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_LO +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_LO +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER0_LO +#define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER0_HI +#define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER1_LO +#define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER1_HI +#define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER2_LO +#define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER2_HI +#define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER3_LO +#define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER3_HI +#define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER4_LO +#define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER4_HI +#define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER5_LO +#define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER5_HI +#define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER6_LO +#define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER6_HI +#define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER7_LO +#define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER7_HI +#define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_LO +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_LO +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_HI +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_LO +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_HI +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_LO +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_HI +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_LO +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_HI +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_LO +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_HI +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_LO +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_HI +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_LO +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_HI +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_LO +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_HI +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_LO +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_HI +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_LO +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_HI +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_LO +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_HI +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER4_LO +#define TCP_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER4_HI +#define TCP_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER5_LO +#define TCP_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER5_HI +#define TCP_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER6_LO +#define TCP_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER6_HI +#define TCP_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER7_LO +#define TCP_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER7_HI +#define TCP_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER_FILTER +#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0xc +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd +#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11 +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16 +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18 +#define TCP_PERFCOUNTER_FILTER__TMPRL__SHIFT 0x1b +#define TCP_PERFCOUNTER_FILTER__SCOPE__SHIFT 0x1e +#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x00001000L +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L +#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L +#define TCP_PERFCOUNTER_FILTER__TMPRL_MASK 0x38000000L +#define TCP_PERFCOUNTER_FILTER__SCOPE_MASK 0xC0000000L +//TCP_PERFCOUNTER_FILTER2 +#define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x0000000FL +//TCP_PERFCOUNTER_FILTER_EN +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 +#define TCP_PERFCOUNTER_FILTER_EN__TMPRL__SHIFT 0x8 +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc +#define TCP_PERFCOUNTER_FILTER_EN__SCOPE__SHIFT 0xd +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L +#define TCP_PERFCOUNTER_FILTER_EN__TMPRL_MASK 0x00000100L +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L +#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L +#define TCP_PERFCOUNTER_FILTER_EN__SCOPE_MASK 0x00002000L +//TCP_PERFCOUNTER_SET_DEFINE +#define TCP_PERFCOUNTER_SET_DEFINE__SET_A__SHIFT 0x0 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_B__SHIFT 0x8 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_C__SHIFT 0x10 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_D__SHIFT 0x18 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_A_MASK 0x000000FFL +#define TCP_PERFCOUNTER_SET_DEFINE__SET_B_MASK 0x0000FF00L +#define TCP_PERFCOUNTER_SET_DEFINE__SET_C_MASK 0x00FF0000L +#define TCP_PERFCOUNTER_SET_DEFINE__SET_D_MASK 0xFF000000L +//GL1C_PERFCOUNTER0_LO +#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER0_HI +#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER1_LO +#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER1_HI +#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER2_LO +#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER2_HI +#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER3_LO +#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER3_HI +#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER0_LO +#define GL1XC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER0_HI +#define GL1XC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER1_LO +#define GL1XC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER1_HI +#define GL1XC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER2_LO +#define GL1XC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER2_HI +#define GL1XC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER3_LO +#define GL1XC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER3_HI +#define GL1XC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_LO +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_HI +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_LO +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_HI +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_LO +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_HI +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_LO +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_HI +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_LO +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_HI +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_LO +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_HI +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_LO +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_HI +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_LO +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_HI +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_LO +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_HI +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_LO +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_HI +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_LO +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_HI +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_LO +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_HI +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER0_LO +#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER0_HI +#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER1_LO +#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER1_HI +#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER2_LO +#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER2_HI +#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER3_LO +#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER3_HI +#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER4_LO +#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER4_HI +#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER5_LO +#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER5_HI +#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER6_LO +#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER6_HI +#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER7_LO +#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER7_HI +#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER0_LO +#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER0_HI +#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER1_LO +#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER1_HI +#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER2_LO +#define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER2_HI +#define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER3_LO +#define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER3_HI +#define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER1_LO +#define WGS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WGS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER1_HI +#define WGS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WGS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER0_LO +#define WGS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WGS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER0_HI +#define WGS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WGS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WGS_PERFMON_CNTL +#define WGS_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define WGS_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define WGS_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define WGS_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define WGS_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define WGS_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define WGS_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define WGS_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//GL1A_PERFCOUNTER0_LO +#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER0_HI +#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER1_LO +#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER1_HI +#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER2_LO +#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER2_HI +#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER3_LO +#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER3_HI +#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER0_LO +#define GL1XA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER0_HI +#define GL1XA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER1_LO +#define GL1XA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER1_HI +#define GL1XA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER2_LO +#define GL1XA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER2_HI +#define GL1XA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER3_LO +#define GL1XA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER3_HI +#define GL1XA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfsdec +//GE2_SE_PERFCOUNTER0_SELECT +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER0_SELECT1 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER1_SELECT +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER1_SELECT1 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER2_SELECT +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER2_SELECT1 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER3_SELECT +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER3_SELECT1 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GRBMH_PERFCOUNTER0_SELECT +#define GRBMH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMH_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMH_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMH_PERFCOUNTER0_SELECT__SQG_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMH_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMH_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMH_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMH_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMH_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMH_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMH_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMH_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMH_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMH_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMH_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMH_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMH_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMH_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMH_PERFCOUNTER0_SELECT__GL1A_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMH_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMH_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMH_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMH_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMH_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMH_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMH_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMH_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMH_PERFCOUNTER0_SELECT__SQG_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMH_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMH_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMH_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMH_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMH_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMH_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMH_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMH_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMH_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMH_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMH_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMH_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMH_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMH_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMH_PERFCOUNTER0_SELECT__GL1A_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMH_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMH_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMH_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMH_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMH_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMH_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBMH_PERFCOUNTER1_SELECT +#define GRBMH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMH_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMH_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMH_PERFCOUNTER1_SELECT__SQG_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMH_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMH_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMH_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMH_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMH_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMH_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMH_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMH_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMH_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMH_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMH_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMH_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMH_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMH_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMH_PERFCOUNTER1_SELECT__GL1A_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMH_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMH_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMH_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMH_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMH_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMH_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMH_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMH_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMH_PERFCOUNTER1_SELECT__SQG_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMH_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMH_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMH_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMH_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMH_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMH_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMH_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMH_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMH_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMH_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMH_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMH_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMH_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMH_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMH_PERFCOUNTER1_SELECT__GL1A_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMH_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMH_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMH_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMH_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMH_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMH_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER0_SELECT1 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT1 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT1 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT1 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT1 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER1_SELECT +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER2_SELECT +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER3_SELECT +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER4_SELECT +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER5_SELECT +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER6_SELECT +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER7_SELECT +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER0_SELECT +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER4_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER5_SELECT +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER5_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER5_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER0_SELECT1 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT1 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT1 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT1 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT1 +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER5_SELECT1 +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER_BINS +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L +//PC_PERFCOUNTER0_SELECT +#define PC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER1_SELECT +#define PC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER2_SELECT +#define PC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER3_SELECT +#define PC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER0_SELECT1 +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER1_SELECT1 +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER2_SELECT1 +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER3_SELECT1 +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER4_SELECT +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER5_SELECT +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER6_SELECT +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER7_SELECT +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER8_SELECT +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER9_SELECT +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER10_SELECT +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER11_SELECT +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER12_SELECT +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER13_SELECT +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER14_SELECT +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER15_SELECT +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER0_SELECT +#define SQG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER1_SELECT +#define SQG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER2_SELECT +#define SQG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER3_SELECT +#define SQG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER4_SELECT +#define SQG_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER5_SELECT +#define SQG_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER6_SELECT +#define SQG_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER7_SELECT +#define SQG_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER_CTRL +#define SQG_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQG_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQG_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQG_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 +#define SQG_PERFCOUNTER_CTRL__POLL_BEFORE_PERF_READ__SHIFT 0x1f +#define SQG_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQG_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQG_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQG_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L +#define SQG_PERFCOUNTER_CTRL__POLL_BEFORE_PERF_READ_MASK 0x80000000L +//SQG_PERFCOUNTER_CTRL2 +#define SQG_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQG_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 +#define SQG_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQG_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL +//SQG_PERF_SAMPLE_FINISH +#define SQG_PERF_SAMPLE_FINISH__STATUS__SHIFT 0x0 +#define SQG_PERF_SAMPLE_FINISH__STATUS_MASK 0x0000007FL +//SQ_PERFCOUNTER_CTRL +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L +//SQ_PERFCOUNTER_CTRL2 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL +//SQ_THREAD_TRACE_BUF0_SIZE +#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_BUF0_BASE_LO +#define SQ_THREAD_TRACE_BUF0_BASE_LO__BASE_LO__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_BASE_LO__BASE_LO_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BUF0_BASE_HI +#define SQ_THREAD_TRACE_BUF0_BASE_HI__BASE_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_BASE_HI__BASE_HI_MASK 0x00001FFFL +//SQ_THREAD_TRACE_BUF1_SIZE +#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_BUF1_BASE_LO +#define SQ_THREAD_TRACE_BUF1_BASE_LO__BASE_LO__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_BASE_LO__BASE_LO_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BUF1_BASE_HI +#define SQ_THREAD_TRACE_BUF1_BASE_HI__BASE_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_BASE_HI__BASE_HI_MASK 0x00001FFFL +//SQ_THREAD_TRACE_CTRL +#define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0 +#define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN__SHIFT 0x3 +#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4 +#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5 +#define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6 +#define SQ_THREAD_TRACE_CTRL__REG_AT_HWM__SHIFT 0x9 +#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xb +#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xc +#define SQ_THREAD_TRACE_CTRL__STALL_ALL_SIMDS__SHIFT 0xd +#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xe +#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xf +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12 +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13 +#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT 0x14 +#define SQ_THREAD_TRACE_CTRL__GL1X_PREFETCH_PAGE__SHIFT 0x17 +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT 0x1c +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_CTRL__NCP_REG_TOKEN_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L +#define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN_MASK 0x00000008L +#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L +#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L +#define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L +#define SQ_THREAD_TRACE_CTRL__REG_AT_HWM_MASK 0x00000600L +#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000800L +#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00001000L +#define SQ_THREAD_TRACE_CTRL__STALL_ALL_SIMDS_MASK 0x00002000L +#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00004000L +#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x00018000L +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L +#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK 0x00700000L +#define SQ_THREAD_TRACE_CTRL__GL1X_PREFETCH_PAGE_MASK 0x07800000L +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK 0x10000000L +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_CTRL__NCP_REG_TOKEN_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L +//SQ_THREAD_TRACE_MASK +#define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4 +#define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9 +#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA__SHIFT 0x11 +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_WAVESTART_EXT__SHIFT 0x12 +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_ALLOC__SHIFT 0x13 +#define SQ_THREAD_TRACE_MASK__SIMD_POWER__SHIFT 0x14 +#define SQ_THREAD_TRACE_MASK__SIMD_POWER_FREQ__SHIFT 0x15 +#define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L +#define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L +#define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L +#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA_MASK 0x00020000L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_WAVESTART_EXT_MASK 0x00040000L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_ALLOC_MASK 0x00080000L +#define SQ_THREAD_TRACE_MASK__SIMD_POWER_MASK 0x00100000L +#define SQ_THREAD_TRACE_MASK__SIMD_POWER_FREQ_MASK 0x00200000L +//SQ_THREAD_TRACE_TOKEN_MASK +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC__SHIFT 0xc +#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT 0xd +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_BARRIER_WAIT__SHIFT 0xe +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_ALUEXEC5__SHIFT 0xf +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT 0x1a +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x00000FFFL +#define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC_MASK 0x00001000L +#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK 0x00002000L +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_BARRIER_WAIT_MASK 0x00004000L +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_ALUEXEC5_MASK 0x00008000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK 0x1C000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L +//SQ_THREAD_TRACE_WPTR +#define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f +#define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL +#define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L +//SQ_THREAD_TRACE_HALT +#define SQ_THREAD_TRACE_HALT__ENTER_CGCG__SHIFT 0x0 +#define SQ_THREAD_TRACE_HALT__CGCG_READY__SHIFT 0x1 +#define SQ_THREAD_TRACE_HALT__ENTER_POWEROFF__SHIFT 0x2 +#define SQ_THREAD_TRACE_HALT__POWEROFF_READY__SHIFT 0x3 +#define SQ_THREAD_TRACE_HALT__ENTER_CGCG_MASK 0x00000001L +#define SQ_THREAD_TRACE_HALT__CGCG_READY_MASK 0x00000002L +#define SQ_THREAD_TRACE_HALT__ENTER_POWEROFF_MASK 0x00000004L +#define SQ_THREAD_TRACE_HALT__POWEROFF_READY_MASK 0x00000008L +//SQ_THREAD_TRACE_POWEROFF_RESTORE_1 +#define SQ_THREAD_TRACE_POWEROFF_RESTORE_1__STATES__SHIFT 0x0 +#define SQ_THREAD_TRACE_POWEROFF_RESTORE_1__STATES_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_STATUS +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc +#define SQ_THREAD_TRACE_STATUS__WRITE_ERROR__SHIFT 0x18 +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19 +#define SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT 0x1c +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L +#define SQ_THREAD_TRACE_STATUS__WRITE_ERROR_MASK 0x01000000L +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L +#define SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK 0xF0000000L +//SQ_THREAD_TRACE_STATUS2 +#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT 0x1 +#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT 0x4 +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS__SHIFT 0x8 +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE__SHIFT 0xd +#define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL__SHIFT 0xe +#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK 0x00000001L +#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK 0x00000002L +#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK 0x00000010L +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS_MASK 0x00001F00L +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_MASK 0x00002000L +#define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL_MASK 0x00004000L +//SQ_THREAD_TRACE_GFX_DRAW_CNTR +#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_GFX_MARKER_CNTR +#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_HP3D_DRAW_CNTR +#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_HP3D_MARKER_CNTR +#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_DROPPED_CNTR +#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_FINISH_DONE_DEBUG +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__GFX__SHIFT 0x0 +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__EXP__SHIFT 0xa +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__GFX_MASK 0x000003FFL +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__EXP_MASK 0x0000FC00L +//SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT +#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT +#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT +#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER0_SELECT1 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT1 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT1 +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT1 +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT1 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER1_SELECT +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT1 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TD_PERFCOUNTER1_SELECT +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT1 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT1 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT1 +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT1 +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER4_SELECT +#define TCP_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER5_SELECT +#define TCP_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER6_SELECT +#define TCP_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER7_SELECT +#define TCP_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER0_SELECT +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER0_SELECT1 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1C_PERFCOUNTER1_SELECT +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER1_SELECT1 +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1C_PERFCOUNTER2_SELECT +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER2_SELECT1 +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1C_PERFCOUNTER3_SELECT +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER3_SELECT1 +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER0_SELECT +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER0_SELECT1 +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER1_SELECT +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER1_SELECT1 +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER2_SELECT +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER2_SELECT1 +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER3_SELECT +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER3_SELECT1 +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER_FILTER +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L +//CB_PERFCOUNTER0_SELECT +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER0_SELECT1 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER1_SELECT +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER2_SELECT +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER3_SELECT +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT1 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT1 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT1 +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT1 +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT1 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER1_SELECT +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT1 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER3_SELECT +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERF_COUNTER_CNTL +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L +//PA_PH_PERFCOUNTER0_SELECT +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER0_SELECT1 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER1_SELECT +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER2_SELECT +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER3_SELECT +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER4_SELECT +#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER5_SELECT +#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER6_SELECT +#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER7_SELECT +#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER1_SELECT1 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER2_SELECT1 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER3_SELECT1 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER0_SELECT +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define UTCL1_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE1__SHIFT 0x18 +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE1_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER0_SELECT1 +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE3__SHIFT 0x18 +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE2__SHIFT 0x1c +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE3_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER1_SELECT +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define UTCL1_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE1__SHIFT 0x18 +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE1_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER1_SELECT1 +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE3__SHIFT 0x18 +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE2__SHIFT 0x1c +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE3_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER2_SELECT +#define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER3_SELECT +#define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE_MASK 0xF0000000L +//WGS_PERFCOUNTER1_SELECT +#define WGS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WGS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define WGS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define WGS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//WGS_PERFCOUNTER0_SELECT1 +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//WGS_PERFCOUNTER0_SELECT +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define WGS_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define WGS_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//GL1A_PERFCOUNTER0_SELECT +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER0_SELECT1 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1A_PERFCOUNTER1_SELECT +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER1_SELECT1 +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1A_PERFCOUNTER2_SELECT +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER2_SELECT1 +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1A_PERFCOUNTER3_SELECT +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER3_SELECT1 +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER0_SELECT +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER0_SELECT1 +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER1_SELECT +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER1_SELECT1 +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER2_SELECT +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER2_SELECT1 +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER3_SELECT +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER3_SELECT1 +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pwrdec +//GFX_ICG_SPI_RA0_CLK_CTRL +#define GFX_ICG_SPI_RA0_CLK_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_RA0_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SPI_RA0_CLK_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_RA0_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SPI_RA1_CLK_CTRL +#define GFX_ICG_SPI_RA1_CLK_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_RA1_CLK_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +//GFX_ICG_SPI_CS_CTRL +#define GFX_ICG_SPI_CS_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_CS_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_SPI_CS_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_CS_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +//GFX_ICG_SPI_PS_CTRL +#define GFX_ICG_SPI_PS_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_PS_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_SPI_PS_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_PS_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +//GFX_ICG_SPIS_CTRL +#define GFX_ICG_SPIS_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPIS_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SPIS_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPIS_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTX_SPI_DEBUG_CLK_CTRL +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x0 +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x6 +#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x7 +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x0000003FL +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x00000040L +#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x00000080L +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +//GFX_ICG_SPI_CTRL +#define GFX_ICG_SPI_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_SPI_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SPI_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +#define GFX_ICG_SPI_CTRL__REG_OVERRIDE_MASK 0x80000000L +//GFX_ICG_PC_CLK_CTRL +#define GFX_ICG_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define GFX_ICG_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_PC_CLK_CTRL__PC_GLOBAL_MGCG_OVERRIDE__SHIFT 0xc +#define GFX_ICG_PC_CLK_CTRL__PC_SC_INT_MGCG_OVERRIDE__SHIFT 0xd +#define GFX_ICG_PC_CLK_CTRL__MISS_WALKER_MGCG_OVERRIDE__SHIFT 0xe +#define GFX_ICG_PC_CLK_CTRL__PRIM_QUEUE_MGCG_OVERRIDE__SHIFT 0xf +#define GFX_ICG_PC_CLK_CTRL__GL1_IF_MGCG_OVERRIDE__SHIFT 0x10 +#define GFX_ICG_PC_CLK_CTRL__GL1_READ_RETURN_MGCG_OVERRIDE__SHIFT 0x11 +#define GFX_ICG_PC_CLK_CTRL__PC_MEM_MGCG_OVERRIDE__SHIFT 0x12 +#define GFX_ICG_PC_CLK_CTRL__LDS_WRITE_CNTL_MGCG_OVERRIDE__SHIFT 0x13 +#define GFX_ICG_PC_CLK_CTRL__LDS_OUT_MGCG_OVERRIDE__SHIFT 0x14 +#define GFX_ICG_PC_CLK_CTRL__PC_REGS_MGCG_OVERRIDE__SHIFT 0x15 +#define GFX_ICG_PC_CLK_CTRL__PC_PERFMON_MGCG_OVERRIDE__SHIFT 0x16 +#define GFX_ICG_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define GFX_ICG_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GFX_ICG_PC_CLK_CTRL__PC_GLOBAL_MGCG_OVERRIDE_MASK 0x00001000L +#define GFX_ICG_PC_CLK_CTRL__PC_SC_INT_MGCG_OVERRIDE_MASK 0x00002000L +#define GFX_ICG_PC_CLK_CTRL__MISS_WALKER_MGCG_OVERRIDE_MASK 0x00004000L +#define GFX_ICG_PC_CLK_CTRL__PRIM_QUEUE_MGCG_OVERRIDE_MASK 0x00008000L +#define GFX_ICG_PC_CLK_CTRL__GL1_IF_MGCG_OVERRIDE_MASK 0x00010000L +#define GFX_ICG_PC_CLK_CTRL__GL1_READ_RETURN_MGCG_OVERRIDE_MASK 0x00020000L +#define GFX_ICG_PC_CLK_CTRL__PC_MEM_MGCG_OVERRIDE_MASK 0x00040000L +#define GFX_ICG_PC_CLK_CTRL__LDS_WRITE_CNTL_MGCG_OVERRIDE_MASK 0x00080000L +#define GFX_ICG_PC_CLK_CTRL__LDS_OUT_MGCG_OVERRIDE_MASK 0x00100000L +#define GFX_ICG_PC_CLK_CTRL__PC_REGS_MGCG_OVERRIDE_MASK 0x00200000L +#define GFX_ICG_PC_CLK_CTRL__PC_PERFMON_MGCG_OVERRIDE_MASK 0x00400000L +//GFX_ICG_BCI_CTRL +#define GFX_ICG_BCI_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_BCI_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_BCI_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_BCI_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_BCI_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +#define GFX_ICG_BCI_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_VGT_CLK_CTRL +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_VGT_CLK_CTRL__PI1_OVERRIDE__SHIFT 0x17 +#define CGTT_VGT_CLK_CTRL__PI0_OVERRIDE__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__HS_OVERRIDE__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__DEPRICATED_RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_VGT_CLK_CTRL__PI1_OVERRIDE_MASK 0x00800000L +#define CGTT_VGT_CLK_CTRL__PI0_OVERRIDE_MASK 0x01000000L +#define CGTT_VGT_CLK_CTRL__HS_OVERRIDE_MASK 0x02000000L +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_VGT_CLK_CTRL__DEPRICATED_RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_GS_NGG_CLK_CTRL +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1c +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x10000000L +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PA_CLK_CTRL +#define CGTT_PA_CLK_CTRL__PAB_CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__PAB_SXIFCCG_CLK_OVERRIDE__SHIFT 0x1 +#define CGTT_PA_CLK_CTRL__PAB_AG_CLK_OVERRIDE__SHIFT 0x2 +#define CGTT_PA_CLK_CTRL__PAB_VE_VTE_REC_CLK_OVERRIDE__SHIFT 0x3 +#define CGTT_PA_CLK_CTRL__PAB_ENGG_CLK_OVERRIDE__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_CLK_OVERRIDE__SHIFT 0x5 +#define CGTT_PA_CLK_CTRL__PAB_AG_REG_CLK_OVERRIDE__SHIFT 0x6 +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_REG_CLK_OVERRIDE__SHIFT 0x7 +#define CGTT_PA_CLK_CTRL__PAB_VTE_REG_CLK_OVERRIDE__SHIFT 0x8 +#define CGTT_PA_CLK_CTRL__PAB_NGG_INDEX_CLK_OVERRIDE__SHIFT 0x9 +#define CGTT_PA_CLK_CTRL__PAB_NGG_CSB_CLK_OVERRIDE__SHIFT 0xa +#define CGTT_PA_CLK_CTRL__PAB_SU_CLK_OVERRIDE__SHIFT 0xb +#define CGTT_PA_CLK_CTRL__PAB_CL_CLK_OVERRIDE__SHIFT 0xc +#define CGTT_PA_CLK_CTRL__PAB_SU_CL_REG_CLK_OVERRIDE__SHIFT 0xd +#define CGTT_PA_CLK_CTRL__PAB_GLX_CLIENT_CLK_OVERRIDE__SHIFT 0xe +#define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT 0xf +#define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE__SHIFT 0x10 +#define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE__SHIFT 0x11 +#define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE__SHIFT 0x12 +#define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE__SHIFT 0x13 +#define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE__SHIFT 0x15 +#define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE__SHIFT 0x16 +#define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE__SHIFT 0x17 +#define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__GLX_CLIENT_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x1f +#define CGTT_PA_CLK_CTRL__PAB_CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK 0x00000001L +#define CGTT_PA_CLK_CTRL__PAB_SXIFCCG_CLK_OVERRIDE_MASK 0x00000002L +#define CGTT_PA_CLK_CTRL__PAB_AG_CLK_OVERRIDE_MASK 0x00000004L +#define CGTT_PA_CLK_CTRL__PAB_VE_VTE_REC_CLK_OVERRIDE_MASK 0x00000008L +#define CGTT_PA_CLK_CTRL__PAB_ENGG_CLK_OVERRIDE_MASK 0x00000010L +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_CLK_OVERRIDE_MASK 0x00000020L +#define CGTT_PA_CLK_CTRL__PAB_AG_REG_CLK_OVERRIDE_MASK 0x00000040L +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_REG_CLK_OVERRIDE_MASK 0x00000080L +#define CGTT_PA_CLK_CTRL__PAB_VTE_REG_CLK_OVERRIDE_MASK 0x00000100L +#define CGTT_PA_CLK_CTRL__PAB_NGG_INDEX_CLK_OVERRIDE_MASK 0x00000200L +#define CGTT_PA_CLK_CTRL__PAB_NGG_CSB_CLK_OVERRIDE_MASK 0x00000400L +#define CGTT_PA_CLK_CTRL__PAB_SU_CLK_OVERRIDE_MASK 0x00000800L +#define CGTT_PA_CLK_CTRL__PAB_CL_CLK_OVERRIDE_MASK 0x00001000L +#define CGTT_PA_CLK_CTRL__PAB_SU_CL_REG_CLK_OVERRIDE_MASK 0x00002000L +#define CGTT_PA_CLK_CTRL__PAB_GLX_CLIENT_CLK_OVERRIDE_MASK 0x00004000L +#define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK 0x00008000L +#define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE_MASK 0x00010000L +#define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE_MASK 0x00020000L +#define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE_MASK 0x00040000L +#define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE_MASK 0x00080000L +#define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE_MASK 0x00200000L +#define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE_MASK 0x00400000L +#define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE_MASK 0x00800000L +#define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__GLX_CLIENT_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x80000000L +//CGTT_SQ_CLK_CTRL +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SQG_CLK_CTRL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__CLUSTER_OVERRIDE__SHIFT 0xc +#define CGTT_SQG_CLK_CTRL__UTCL0_OVERRIDE__SHIFT 0xd +#define CGTT_SQG_CLK_CTRL__PM_OVERRIDE__SHIFT 0xe +#define CGTT_SQG_CLK_CTRL__FORCE_GCR_RSP_FGCG__SHIFT 0xf +#define CGTT_SQG_CLK_CTRL__PM_PIT_PRIME_FGCG_OVERRIDE__SHIFT 0x10 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQG_CLK_CTRL__FORCE_GL1X_CLKEN__SHIFT 0x17 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG__SHIFT 0x18 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG__SHIFT 0x19 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG__SHIFT 0x1a +#define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG__SHIFT 0x1b +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQG_CLK_CTRL__CLUSTER_OVERRIDE_MASK 0x00001000L +#define CGTT_SQG_CLK_CTRL__UTCL0_OVERRIDE_MASK 0x00002000L +#define CGTT_SQG_CLK_CTRL__PM_OVERRIDE_MASK 0x00004000L +#define CGTT_SQG_CLK_CTRL__FORCE_GCR_RSP_FGCG_MASK 0x00008000L +#define CGTT_SQG_CLK_CTRL__PM_PIT_PRIME_FGCG_OVERRIDE_MASK 0x00010000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQG_CLK_CTRL__FORCE_GL1X_CLKEN_MASK 0x00800000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG_MASK 0x01000000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG_MASK 0x02000000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG_MASK 0x04000000L +#define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG_MASK 0x08000000L +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//SQ_ALU_CLK_CTRL +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_TEX_CLK_CTRL +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_LDS_CLK_CTRL +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_CLK_CTRL +#define SQ_CLK_CTRL__SQ_SPI_MSG_FGCG_OVERRIDE__SHIFT 0x2 +#define SQ_CLK_CTRL__SQ_SPI_EXPREQ_FGCG_OVERRIDE__SHIFT 0x3 +#define SQ_CLK_CTRL__SQ_SX_EXPCMD_FGCG_OVERRIDE__SHIFT 0x4 +#define SQ_CLK_CTRL__SQ_SQC_TTRACE_FGCG_OVERRIDE__SHIFT 0x5 +#define SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT 0x6 +#define SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x7 +#define SQ_CLK_CTRL__OVERRIDE_LDS_IDX_BUSY__SHIFT 0x8 +#define SQ_CLK_CTRL__OVERRIDE_LDS_DIRECT_BUSY__SHIFT 0x9 +#define SQ_CLK_CTRL__WCLK_SLEEP_VMEM_OVERRIDE__SHIFT 0xa +#define SQ_CLK_CTRL__WCLK_SLEEP_EXPALLOC_OVERRIDE__SHIFT 0xb +#define SQ_CLK_CTRL__SQ_SP_CMD_FGCG_OVERRIDE__SHIFT 0xc +#define SQ_CLK_CTRL__SQ_SP_CONST_FGCG_OVERRIDE__SHIFT 0xd +#define SQ_CLK_CTRL__SQ_SP_EXP_FGCG_OVERRIDE__SHIFT 0xe +#define SQ_CLK_CTRL__SQ_SP_VMEM_FGCG_OVERRIDE__SHIFT 0xf +#define SQ_CLK_CTRL__SQ_LDS_DIRECT_FGCG_OVERRIDE__SHIFT 0x10 +#define SQ_CLK_CTRL__IS_WAVECLK_IB_WCLK_OVERRIDE__SHIFT 0x11 +#define SQ_CLK_CTRL__ISC_SET_FGCG_OVERRIDE__SHIFT 0x12 +#define SQ_CLK_CTRL__ISC_CTRL_FGCG_OVERRIDE__SHIFT 0x13 +#define SQ_CLK_CTRL__ISC_WAVE_CTRL_FGCG_OVERRIDE__SHIFT 0x14 +#define SQ_CLK_CTRL__IB_IBUF_FGCG_OVERRIDE__SHIFT 0x15 +#define SQ_CLK_CTRL__IB_WINFO_FGCG_OVERRIDE__SHIFT 0x16 +#define SQ_CLK_CTRL__IB_MISC_FGCG_OVERRIDE__SHIFT 0x17 +#define SQ_CLK_CTRL__EX_SALU_FGCG_OVERRIDE__SHIFT 0x18 +#define SQ_CLK_CTRL__EX_VALU_FGCG_OVERRIDE__SHIFT 0x19 +#define SQ_CLK_CTRL__EX_BRMSG_FGCG_OVERRIDE__SHIFT 0x1a +#define SQ_CLK_CTRL__SQ_SP_ICG_FGCG_OVERRIDE__SHIFT 0x1b +#define SQ_CLK_CTRL__SQ_MCA_FGCG_OVERRIDE__SHIFT 0x1c +#define SQ_CLK_CTRL__SQ_TA_VMEMCMD_FGCG_OVERRIDE__SHIFT 0x1d +#define SQ_CLK_CTRL__SQ_SPI_MSG_FGCG_OVERRIDE_MASK 0x00000004L +#define SQ_CLK_CTRL__SQ_SPI_EXPREQ_FGCG_OVERRIDE_MASK 0x00000008L +#define SQ_CLK_CTRL__SQ_SX_EXPCMD_FGCG_OVERRIDE_MASK 0x00000010L +#define SQ_CLK_CTRL__SQ_SQC_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L +#define SQ_CLK_CTRL__WCLK_OVERRIDE_MASK 0x00000040L +#define SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x00000080L +#define SQ_CLK_CTRL__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000100L +#define SQ_CLK_CTRL__OVERRIDE_LDS_DIRECT_BUSY_MASK 0x00000200L +#define SQ_CLK_CTRL__WCLK_SLEEP_VMEM_OVERRIDE_MASK 0x00000400L +#define SQ_CLK_CTRL__WCLK_SLEEP_EXPALLOC_OVERRIDE_MASK 0x00000800L +#define SQ_CLK_CTRL__SQ_SP_CMD_FGCG_OVERRIDE_MASK 0x00001000L +#define SQ_CLK_CTRL__SQ_SP_CONST_FGCG_OVERRIDE_MASK 0x00002000L +#define SQ_CLK_CTRL__SQ_SP_EXP_FGCG_OVERRIDE_MASK 0x00004000L +#define SQ_CLK_CTRL__SQ_SP_VMEM_FGCG_OVERRIDE_MASK 0x00008000L +#define SQ_CLK_CTRL__SQ_LDS_DIRECT_FGCG_OVERRIDE_MASK 0x00010000L +#define SQ_CLK_CTRL__IS_WAVECLK_IB_WCLK_OVERRIDE_MASK 0x00020000L +#define SQ_CLK_CTRL__ISC_SET_FGCG_OVERRIDE_MASK 0x00040000L +#define SQ_CLK_CTRL__ISC_CTRL_FGCG_OVERRIDE_MASK 0x00080000L +#define SQ_CLK_CTRL__ISC_WAVE_CTRL_FGCG_OVERRIDE_MASK 0x00100000L +#define SQ_CLK_CTRL__IB_IBUF_FGCG_OVERRIDE_MASK 0x00200000L +#define SQ_CLK_CTRL__IB_WINFO_FGCG_OVERRIDE_MASK 0x00400000L +#define SQ_CLK_CTRL__IB_MISC_FGCG_OVERRIDE_MASK 0x00800000L +#define SQ_CLK_CTRL__EX_SALU_FGCG_OVERRIDE_MASK 0x01000000L +#define SQ_CLK_CTRL__EX_VALU_FGCG_OVERRIDE_MASK 0x02000000L +#define SQ_CLK_CTRL__EX_BRMSG_FGCG_OVERRIDE_MASK 0x04000000L +#define SQ_CLK_CTRL__SQ_SP_ICG_FGCG_OVERRIDE_MASK 0x08000000L +#define SQ_CLK_CTRL__SQ_MCA_FGCG_OVERRIDE_MASK 0x10000000L +#define SQ_CLK_CTRL__SQ_TA_VMEMCMD_FGCG_OVERRIDE_MASK 0x20000000L +//ICG_SQ_CLK_CTRL +#define ICG_SQ_CLK_CTRL__STATIC_OCLK_OVERRIDE__SHIFT 0x0 +#define ICG_SQ_CLK_CTRL__BOUNDARY_DCLK_OVERRIDE__SHIFT 0x1 +#define ICG_SQ_CLK_CTRL__BOUNDARY_CCLK_OVERRIDE__SHIFT 0x2 +#define ICG_SQ_CLK_CTRL__BOUNDARY_RCLK_OVERRIDE__SHIFT 0x3 +#define ICG_SQ_CLK_CTRL__DCLK_OVERRIDE__SHIFT 0x4 +#define ICG_SQ_CLK_CTRL__RCLK_OVERRIDE__SHIFT 0x5 +#define ICG_SQ_CLK_CTRL__PCLK_OVERRIDE__SHIFT 0x6 +#define ICG_SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT 0x7 +#define ICG_SQ_CLK_CTRL__SALU_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_SQ_CLK_CTRL__VALU_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_SQ_CLK_CTRL__VALU_SGPR_CLK_OVERRIDE__SHIFT 0xa +#define ICG_SQ_CLK_CTRL__VMEM_CLK_OVERRIDE__SHIFT 0xb +#define ICG_SQ_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0xc +#define ICG_SQ_CLK_CTRL__TTRACE_CLK_OVERRIDE__SHIFT 0xd +#define ICG_SQ_CLK_CTRL__SQC_RET_CLK_OVERRIDE__SHIFT 0xe +#define ICG_SQ_CLK_CTRL__WAVEUPD_CLK_OVERRIDE__SHIFT 0xf +#define ICG_SQ_CLK_CTRL__WAVE_NEWDONE_CLK_OVERRIDE__SHIFT 0x10 +#define ICG_SQ_CLK_CTRL__WAVE_STATE_CLK_OVERRIDE__SHIFT 0x11 +#define ICG_SQ_CLK_CTRL__SFPU_CLK_OVERRIDE__SHIFT 0x12 +#define ICG_SQ_CLK_CTRL__SQC_SPECIAL_OP_CLK_OVERRIDE__SHIFT 0x13 +#define ICG_SQ_CLK_CTRL__WAVE_INSTBUF_CLK_OVERRIDE__SHIFT 0x14 +#define ICG_SQ_CLK_CTRL__IS_WAVECLK_OVERRIDE__SHIFT 0x15 +#define ICG_SQ_CLK_CTRL__SMEM_CLK_OVERRIDE__SHIFT 0x16 +#define ICG_SQ_CLK_CTRL__SDST_FIFO_CLK_OVERRIDE__SHIFT 0x17 +#define ICG_SQ_CLK_CTRL__SCALAR_BUF_CLK_OVERRIDE__SHIFT 0x18 +#define ICG_SQ_CLK_CTRL__SALU_PIPE_CLK_OVERRIDE__SHIFT 0x19 +#define ICG_SQ_CLK_CTRL__BRMSG_CLK_OVERRIDE__SHIFT 0x1a +#define ICG_SQ_CLK_CTRL__TAG_CLK_OVERRIDE__SHIFT 0x1b +#define ICG_SQ_CLK_CTRL__TAG_STATUS_CLK_OVERRIDE__SHIFT 0x1c +#define ICG_SQ_CLK_CTRL__EXP_CLK_OVERRIDE__SHIFT 0x1d +#define ICG_SQ_CLK_CTRL__VALU2_SGPR_CLK_OVERRIDE__SHIFT 0x1e +#define ICG_SQ_CLK_CTRL__STATIC_OCLK_OVERRIDE_MASK 0x00000001L +#define ICG_SQ_CLK_CTRL__BOUNDARY_DCLK_OVERRIDE_MASK 0x00000002L +#define ICG_SQ_CLK_CTRL__BOUNDARY_CCLK_OVERRIDE_MASK 0x00000004L +#define ICG_SQ_CLK_CTRL__BOUNDARY_RCLK_OVERRIDE_MASK 0x00000008L +#define ICG_SQ_CLK_CTRL__DCLK_OVERRIDE_MASK 0x00000010L +#define ICG_SQ_CLK_CTRL__RCLK_OVERRIDE_MASK 0x00000020L +#define ICG_SQ_CLK_CTRL__PCLK_OVERRIDE_MASK 0x00000040L +#define ICG_SQ_CLK_CTRL__WCLK_OVERRIDE_MASK 0x00000080L +#define ICG_SQ_CLK_CTRL__SALU_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_SQ_CLK_CTRL__VALU_CLK_OVERRIDE_MASK 0x00000200L +#define ICG_SQ_CLK_CTRL__VALU_SGPR_CLK_OVERRIDE_MASK 0x00000400L +#define ICG_SQ_CLK_CTRL__VMEM_CLK_OVERRIDE_MASK 0x00000800L +#define ICG_SQ_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00001000L +#define ICG_SQ_CLK_CTRL__TTRACE_CLK_OVERRIDE_MASK 0x00002000L +#define ICG_SQ_CLK_CTRL__SQC_RET_CLK_OVERRIDE_MASK 0x00004000L +#define ICG_SQ_CLK_CTRL__WAVEUPD_CLK_OVERRIDE_MASK 0x00008000L +#define ICG_SQ_CLK_CTRL__WAVE_NEWDONE_CLK_OVERRIDE_MASK 0x00010000L +#define ICG_SQ_CLK_CTRL__WAVE_STATE_CLK_OVERRIDE_MASK 0x00020000L +#define ICG_SQ_CLK_CTRL__SFPU_CLK_OVERRIDE_MASK 0x00040000L +#define ICG_SQ_CLK_CTRL__SQC_SPECIAL_OP_CLK_OVERRIDE_MASK 0x00080000L +#define ICG_SQ_CLK_CTRL__WAVE_INSTBUF_CLK_OVERRIDE_MASK 0x00100000L +#define ICG_SQ_CLK_CTRL__IS_WAVECLK_OVERRIDE_MASK 0x00200000L +#define ICG_SQ_CLK_CTRL__SMEM_CLK_OVERRIDE_MASK 0x00400000L +#define ICG_SQ_CLK_CTRL__SDST_FIFO_CLK_OVERRIDE_MASK 0x00800000L +#define ICG_SQ_CLK_CTRL__SCALAR_BUF_CLK_OVERRIDE_MASK 0x01000000L +#define ICG_SQ_CLK_CTRL__SALU_PIPE_CLK_OVERRIDE_MASK 0x02000000L +#define ICG_SQ_CLK_CTRL__BRMSG_CLK_OVERRIDE_MASK 0x04000000L +#define ICG_SQ_CLK_CTRL__TAG_CLK_OVERRIDE_MASK 0x08000000L +#define ICG_SQ_CLK_CTRL__TAG_STATUS_CLK_OVERRIDE_MASK 0x10000000L +#define ICG_SQ_CLK_CTRL__EXP_CLK_OVERRIDE_MASK 0x20000000L +#define ICG_SQ_CLK_CTRL__VALU2_SGPR_CLK_OVERRIDE_MASK 0x40000000L +//ICG_SP_CLK_CTRL +#define ICG_SP_CLK_CTRL__CLK_OVERRIDE__SHIFT 0x0 +#define ICG_SP_CLK_CTRL__CLK_OVERRIDE_MASK 0xFFFFFFFFL +//GFX_ICG_SX_CLK_CTRL0 +#define GFX_ICG_SX_CLK_CTRL0__RESERVED__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL0__PERF_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL0__REG_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL0__RESERVED_MASK 0x3FFFFFFFL +#define GFX_ICG_SX_CLK_CTRL0__PERF_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL0__REG_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL1 +#define GFX_ICG_SX_CLK_CTRL1__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL1__RESERVED1__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL1__SX_SX_IO_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL1__BDS_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL1__RESERVED0_MASK 0x00FFFFFFL +#define GFX_ICG_SX_CLK_CTRL1__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL1__RESERVED1_MASK 0x3E000000L +#define GFX_ICG_SX_CLK_CTRL1__SX_SX_IO_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL1__BDS_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL2 +#define GFX_ICG_SX_CLK_CTRL2__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL2__COL_WRITE_SOFT_OVERRIDE__SHIFT 0x17 +#define GFX_ICG_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL2__COL_REQUESTER_SOFT_OVERRIDE__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL2__COL_EXPORT_SOFT_OVERRIDE__SHIFT 0x1a +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_SOFT_OVERRIDE__SHIFT 0x1b +#define GFX_ICG_SX_CLK_CTRL2__COL_DBIF_SOFT_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_DOWNCONVERT_SOFT_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_SX_CLK_CTRL2__COL1_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL2__COL0_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL2__RESERVED0_MASK 0x007FFFFFL +#define GFX_ICG_SX_CLK_CTRL2__COL_WRITE_SOFT_OVERRIDE_MASK 0x00800000L +#define GFX_ICG_SX_CLK_CTRL2__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_REQUESTER_SOFT_OVERRIDE_MASK 0x02000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_EXPORT_SOFT_OVERRIDE_MASK 0x04000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_SOFT_OVERRIDE_MASK 0x08000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_DBIF_SOFT_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_DOWNCONVERT_SOFT_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_SX_CLK_CTRL2__COL1_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL2__COL0_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL3 +#define GFX_ICG_SX_CLK_CTRL3__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL3__RESERVED1__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL3__POS_WRITE_SOFT_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_SX_CLK_CTRL3__POS_PAIF_SOFT_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_SX_CLK_CTRL3__POS_EXPORT_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL3__POS_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL3__RESERVED0_MASK 0x00FFFFFFL +#define GFX_ICG_SX_CLK_CTRL3__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL3__RESERVED1_MASK 0x0E000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_WRITE_SOFT_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_PAIF_SOFT_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_EXPORT_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL4 +#define GFX_ICG_SX_CLK_CTRL4__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL4__RESERVED1__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL4__IDX_WRITE_SOFT_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_SX_CLK_CTRL4__IDX_PAIF_SOFT_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_SX_CLK_CTRL4__IDX_EXPORT_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL4__IDX_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL4__RESERVED0_MASK 0x00FFFFFFL +#define GFX_ICG_SX_CLK_CTRL4__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL4__RESERVED1_MASK 0x0E000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_WRITE_SOFT_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_PAIF_SOFT_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_EXPORT_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_TA_CTRL +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE10__SHIFT 0xa +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE11__SHIFT 0xb +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE12__SHIFT 0xc +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE13__SHIFT 0xd +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE14__SHIFT 0xe +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE15__SHIFT 0xf +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE16__SHIFT 0x10 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE17__SHIFT 0x11 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE18__SHIFT 0x12 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE19__SHIFT 0x13 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE20__SHIFT 0x14 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE21__SHIFT 0x15 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE22__SHIFT 0x16 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE23__SHIFT 0x17 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE15_MASK 0x00008000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE16_MASK 0x00010000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE17_MASK 0x00020000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE18_MASK 0x00040000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE19_MASK 0x00080000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE20_MASK 0x00100000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE21_MASK 0x00200000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE22_MASK 0x00400000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE23_MASK 0x00800000L +//GFX_ICG_TD_CTRL +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE10__SHIFT 0xa +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE11__SHIFT 0xb +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE12__SHIFT 0xc +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE13__SHIFT 0xd +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE14__SHIFT 0xe +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE15__SHIFT 0xf +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE16__SHIFT 0x10 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE17__SHIFT 0x11 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE18__SHIFT 0x12 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE19__SHIFT 0x13 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE20__SHIFT 0x14 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE21__SHIFT 0x15 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE22__SHIFT 0x16 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE15_MASK 0x00008000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE16_MASK 0x00010000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE17_MASK 0x00020000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE18_MASK 0x00040000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE19_MASK 0x00080000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE20_MASK 0x00100000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE21_MASK 0x00200000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE22_MASK 0x00400000L +//DB_CGTT_CLK_CTRL_0 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x2 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x3 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x5 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x6 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8__SHIFT 0x8 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x9 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x00000001L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x00000002L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x00000004L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x00000008L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x00000010L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x00000020L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x00000040L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8_MASK 0x00000100L +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xFFFFFE00L +//GFX_ICG_CB_CTRL +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE31__SHIFT 0x0 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE30__SHIFT 0x1 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE29__SHIFT 0x2 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE28__SHIFT 0x3 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE27__SHIFT 0x4 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE26__SHIFT 0x5 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE25__SHIFT 0x6 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE24__SHIFT 0x7 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE23__SHIFT 0x8 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE22__SHIFT 0x9 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE21__SHIFT 0xa +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE19__SHIFT 0xc +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE18__SHIFT 0xd +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE17__SHIFT 0xe +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE16__SHIFT 0xf +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE15__SHIFT 0x10 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE14__SHIFT 0x11 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE11__SHIFT 0x14 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE10__SHIFT 0x15 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE9__SHIFT 0x16 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE8__SHIFT 0x17 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE31_MASK 0x00000001L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE30_MASK 0x00000002L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE29_MASK 0x00000004L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE28_MASK 0x00000008L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE27_MASK 0x00000010L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE26_MASK 0x00000020L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE25_MASK 0x00000040L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE24_MASK 0x00000080L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE23_MASK 0x00000100L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE22_MASK 0x00000200L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE21_MASK 0x00000400L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE19_MASK 0x00001000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE18_MASK 0x00002000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE17_MASK 0x00004000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE16_MASK 0x00008000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE15_MASK 0x00010000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE14_MASK 0x00020000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE11_MASK 0x00100000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE10_MASK 0x00200000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE9_MASK 0x00400000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE8_MASK 0x00800000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//GFX_ICG_RMI_CTRL +#define GFX_ICG_RMI_CTRL__ON_DELAY__SHIFT 0x0 +#define GFX_ICG_RMI_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GFX_ICG_RMI_CTRL__ON_DELAY_MASK 0x0000000FL +#define GFX_ICG_RMI_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//GFX_ICG_SE_CAC_CLK_CTRL +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_DYNAMIC_ICG_OVERRIDE__SHIFT 0x0 +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_REG_ICG_OVERRIDE__SHIFT 0x1 +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_STATIC_ICG_OVERRIDE__SHIFT 0x2 +#define GFX_ICG_SE_CAC_CLK_CTRL__FGCG_REP_OVERRIDE__SHIFT 0x3 +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_DYNAMIC_ICG_OVERRIDE_MASK 0x00000001L +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_REG_ICG_OVERRIDE_MASK 0x00000002L +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_STATIC_ICG_OVERRIDE_MASK 0x00000004L +#define GFX_ICG_SE_CAC_CLK_CTRL__FGCG_REP_OVERRIDE_MASK 0x00000008L +//CGTT_PH_CLK_CTRL0 +#define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL0__DEBUG_BUS_EN__SHIFT 0x17 +#define CGTT_PH_CLK_CTRL0__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL0__DEBUG_BUS_EN_MASK 0x00800000L +#define CGTT_PH_CLK_CTRL0__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_PH_CLK_CTRL1 +#define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +//CGTT_PH_CLK_CTRL2 +#define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +//CGTT_PH_CLK_CTRL3 +#define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +//GFX_ICG_TCP_CTRL +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_0__SHIFT 0x0 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_1__SHIFT 0x1 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_2__SHIFT 0x2 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_3__SHIFT 0x3 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_4__SHIFT 0x4 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_5__SHIFT 0x5 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_6__SHIFT 0x6 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_7__SHIFT 0x7 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_8__SHIFT 0x8 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_9__SHIFT 0x9 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_10__SHIFT 0xa +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_11__SHIFT 0xb +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_12__SHIFT 0xc +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_13__SHIFT 0xd +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_14__SHIFT 0xe +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_15__SHIFT 0xf +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_16__SHIFT 0x10 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_17__SHIFT 0x11 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_18__SHIFT 0x12 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_19__SHIFT 0x13 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_20__SHIFT 0x14 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_21__SHIFT 0x15 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_22__SHIFT 0x16 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_23__SHIFT 0x17 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_24__SHIFT 0x18 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_25__SHIFT 0x19 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_26__SHIFT 0x1a +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_27__SHIFT 0x1b +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_28__SHIFT 0x1c +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_29__SHIFT 0x1d +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_0_MASK 0x00000001L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_1_MASK 0x00000002L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_2_MASK 0x00000004L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_3_MASK 0x00000008L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_4_MASK 0x00000010L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_5_MASK 0x00000020L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_6_MASK 0x00000040L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_7_MASK 0x00000080L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_8_MASK 0x00000100L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_9_MASK 0x00000200L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_10_MASK 0x00000400L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_11_MASK 0x00000800L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_12_MASK 0x00001000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_13_MASK 0x00002000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_14_MASK 0x00004000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_15_MASK 0x00008000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_16_MASK 0x00010000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_17_MASK 0x00020000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_18_MASK 0x00040000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_19_MASK 0x00080000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_20_MASK 0x00100000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_21_MASK 0x00200000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_22_MASK 0x00400000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_23_MASK 0x00800000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_24_MASK 0x01000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_25_MASK 0x02000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_26_MASK 0x04000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_27_MASK 0x08000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_28_MASK 0x10000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_29_MASK 0x20000000L +//GFX_ICG_TCP_CTRL2 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_0__SHIFT 0x0 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_1__SHIFT 0x1 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_2__SHIFT 0x2 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_3__SHIFT 0x3 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_4__SHIFT 0x4 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_5__SHIFT 0x5 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_6__SHIFT 0x6 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_7__SHIFT 0x7 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_8__SHIFT 0x8 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_9__SHIFT 0x9 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_10__SHIFT 0xa +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_11__SHIFT 0xb +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_12__SHIFT 0xc +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_13__SHIFT 0xd +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_14__SHIFT 0xe +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_15__SHIFT 0xf +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_16__SHIFT 0x10 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_17__SHIFT 0x11 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_18__SHIFT 0x12 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_19__SHIFT 0x13 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_20__SHIFT 0x14 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_21__SHIFT 0x15 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_22__SHIFT 0x16 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_23__SHIFT 0x17 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_24__SHIFT 0x18 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_25__SHIFT 0x19 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_26__SHIFT 0x1a +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_27__SHIFT 0x1b +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_28__SHIFT 0x1c +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_29__SHIFT 0x1d +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_30__SHIFT 0x1e +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_0_MASK 0x00000001L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_1_MASK 0x00000002L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_2_MASK 0x00000004L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_3_MASK 0x00000008L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_4_MASK 0x00000010L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_5_MASK 0x00000020L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_6_MASK 0x00000040L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_7_MASK 0x00000080L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_8_MASK 0x00000100L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_9_MASK 0x00000200L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_10_MASK 0x00000400L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_11_MASK 0x00000800L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_12_MASK 0x00001000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_13_MASK 0x00002000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_14_MASK 0x00004000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_15_MASK 0x00008000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_16_MASK 0x00010000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_17_MASK 0x00020000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_18_MASK 0x00040000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_19_MASK 0x00080000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_20_MASK 0x00100000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_21_MASK 0x00200000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_22_MASK 0x00400000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_23_MASK 0x00800000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_24_MASK 0x01000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_25_MASK 0x02000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_26_MASK 0x04000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_27_MASK 0x08000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_28_MASK 0x10000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_29_MASK 0x20000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_30_MASK 0x40000000L +//ICG_LDS_CLK_CTRL +#define ICG_LDS_CLK_CTRL__HARVEST_WGP_OVERRIDE__SHIFT 0x0 +#define ICG_LDS_CLK_CTRL__CONFIG_REG_OVERRIDE__SHIFT 0x1 +#define ICG_LDS_CLK_CTRL__TD_OVERRIDE__SHIFT 0x2 +#define ICG_LDS_CLK_CTRL__ATTR_WR_OVERRIDE__SHIFT 0x3 +#define ICG_LDS_CLK_CTRL__DLOAD0_OVERRIDE__SHIFT 0x4 +#define ICG_LDS_CLK_CTRL__DLOAD1_OVERRIDE__SHIFT 0x5 +#define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE__SHIFT 0x6 +#define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE__SHIFT 0x7 +#define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE__SHIFT 0x8 +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_OVERRIDE__SHIFT 0x9 +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_BVH_OVERRIDE__SHIFT 0xa +#define ICG_LDS_CLK_CTRL__IDX_SCHED_INPUT_OVERRIDE__SHIFT 0xb +#define ICG_LDS_CLK_CTRL__IDX_BANK_CONFLICT_OVERRIDE__SHIFT 0xc +#define ICG_LDS_CLK_CTRL__IDX_SCHEDULER_OVERRIDE__SHIFT 0xd +#define ICG_LDS_CLK_CTRL__IDX_SCHED_DATA_PIPE_OVERRIDE__SHIFT 0xe +#define ICG_LDS_CLK_CTRL__IDX_SCHED_PIPE_OVERRIDE__SHIFT 0xf +#define ICG_LDS_CLK_CTRL__IDX_SCHED_OUTPUT_OVERRIDE__SHIFT 0x10 +#define ICG_LDS_CLK_CTRL__IDX_PIPE_OVERRIDE__SHIFT 0x11 +#define ICG_LDS_CLK_CTRL__IDX_DIR_OVERRIDE__SHIFT 0x12 +#define ICG_LDS_CLK_CTRL__IDX_WR_OVERRIDE__SHIFT 0x13 +#define ICG_LDS_CLK_CTRL__WGP_ARB_OVERRIDE__SHIFT 0x14 +#define ICG_LDS_CLK_CTRL__MEM_OVERRIDE__SHIFT 0x15 +#define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE__SHIFT 0x16 +#define ICG_LDS_CLK_CTRL__IDX_WR_ADDR_OVERRIDE__SHIFT 0x17 +#define ICG_LDS_CLK_CTRL__IDX_RDRTN_OVERRIDE__SHIFT 0x18 +#define ICG_LDS_CLK_CTRL__IDX_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0x19 +#define ICG_LDS_CLK_CTRL__DIR_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0x1a +#define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE__SHIFT 0x1b +#define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE__SHIFT 0x1c +#define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE__SHIFT 0x1d +#define ICG_LDS_CLK_CTRL__HARVEST_WGP_OVERRIDE_MASK 0x00000001L +#define ICG_LDS_CLK_CTRL__CONFIG_REG_OVERRIDE_MASK 0x00000002L +#define ICG_LDS_CLK_CTRL__TD_OVERRIDE_MASK 0x00000004L +#define ICG_LDS_CLK_CTRL__ATTR_WR_OVERRIDE_MASK 0x00000008L +#define ICG_LDS_CLK_CTRL__DLOAD0_OVERRIDE_MASK 0x00000010L +#define ICG_LDS_CLK_CTRL__DLOAD1_OVERRIDE_MASK 0x00000020L +#define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE_MASK 0x00000040L +#define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE_MASK 0x00000080L +#define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE_MASK 0x00000100L +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_OVERRIDE_MASK 0x00000200L +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_BVH_OVERRIDE_MASK 0x00000400L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_INPUT_OVERRIDE_MASK 0x00000800L +#define ICG_LDS_CLK_CTRL__IDX_BANK_CONFLICT_OVERRIDE_MASK 0x00001000L +#define ICG_LDS_CLK_CTRL__IDX_SCHEDULER_OVERRIDE_MASK 0x00002000L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_DATA_PIPE_OVERRIDE_MASK 0x00004000L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_PIPE_OVERRIDE_MASK 0x00008000L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_OUTPUT_OVERRIDE_MASK 0x00010000L +#define ICG_LDS_CLK_CTRL__IDX_PIPE_OVERRIDE_MASK 0x00020000L +#define ICG_LDS_CLK_CTRL__IDX_DIR_OVERRIDE_MASK 0x00040000L +#define ICG_LDS_CLK_CTRL__IDX_WR_OVERRIDE_MASK 0x00080000L +#define ICG_LDS_CLK_CTRL__WGP_ARB_OVERRIDE_MASK 0x00100000L +#define ICG_LDS_CLK_CTRL__MEM_OVERRIDE_MASK 0x00200000L +#define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE_MASK 0x00400000L +#define ICG_LDS_CLK_CTRL__IDX_WR_ADDR_OVERRIDE_MASK 0x00800000L +#define ICG_LDS_CLK_CTRL__IDX_RDRTN_OVERRIDE_MASK 0x01000000L +#define ICG_LDS_CLK_CTRL__IDX_OUTPUT_ALIGNER_OVERRIDE_MASK 0x02000000L +#define ICG_LDS_CLK_CTRL__DIR_OUTPUT_ALIGNER_OVERRIDE_MASK 0x04000000L +#define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE_MASK 0x08000000L +#define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE_MASK 0x10000000L +#define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE_MASK 0x20000000L +//GFX_ICG_UTCL1_CTRL +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10__SHIFT 0xa +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE11__SHIFT 0xb +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE12__SHIFT 0xc +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE13__SHIFT 0xd +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE14__SHIFT 0xe +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE15__SHIFT 0xf +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE16__SHIFT 0x10 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE17__SHIFT 0x11 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE18__SHIFT 0x12 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE19__SHIFT 0x13 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE20__SHIFT 0x14 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE21__SHIFT 0x15 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE22__SHIFT 0x16 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE23__SHIFT 0x17 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE24__SHIFT 0x18 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE25__SHIFT 0x19 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26__SHIFT 0x1a +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26_31__SHIFT 0x1b +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE15_MASK 0x00008000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE16_MASK 0x00010000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE17_MASK 0x00020000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE18_MASK 0x00040000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE19_MASK 0x00080000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE20_MASK 0x00100000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE21_MASK 0x00200000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE22_MASK 0x00400000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE23_MASK 0x00800000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE24_MASK 0x01000000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE25_MASK 0x02000000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26_MASK 0x04000000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26_31_MASK 0xF8000000L +//GFX_ICG_GRBMH_CTRL +#define GFX_ICG_GRBMH_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_SE__SHIFT 0x10 +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GFX_ICG_GRBMH_CTRL__OFF_HYSTERESIS_MASK 0x000003F0L +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_SE_MASK 0x00FF0000L +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_sc_pwrdec +//CGTT_SC_CLK_CTRL0 +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL0__VRC_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL0__HZC_OVERRIDE__SHIFT 0xd +#define CGTT_SC_CLK_CTRL0__HSC_OVERRIDE__SHIFT 0xe +#define CGTT_SC_CLK_CTRL0__HPF_OVERRIDE__SHIFT 0xf +#define CGTT_SC_CLK_CTRL0__G2DYN_STALL_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL0__FEDYN_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL0__GL1X_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL0__FEDYN_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL0__PERFMON_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL0__VRC_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL0__HZC_OVERRIDE_MASK 0x00002000L +#define CGTT_SC_CLK_CTRL0__HSC_OVERRIDE_MASK 0x00004000L +#define CGTT_SC_CLK_CTRL0__HPF_OVERRIDE_MASK 0x00008000L +#define CGTT_SC_CLK_CTRL0__G2DYN_STALL_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL0__FEDYN_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL0__GL1X_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL0__FEDYN_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL0__PERFMON_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL1 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL1__SC_DB_QP_SAMPLEMASK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL1__SC_DB_QP_SAMPLEMASK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL2 +#define CGTT_SC_CLK_CTRL2__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON__SHIFT 0xf +#define CGTT_SC_CLK_CTRL2__SC_DB_HISZCA_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL2__DB_SC_WAVE_INTF_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL2__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON_MASK 0x00008000L +#define CGTT_SC_CLK_CTRL2__SC_DB_HISZCA_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL2__DB_SC_WAVE_INTF_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SC_CLK_CTRL3 +#define CGTT_SC_CLK_CTRL3__RESERVED_00__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL3__RESERVED_01__SHIFT 0x1 +#define CGTT_SC_CLK_CTRL3__RESERVED_02__SHIFT 0x2 +#define CGTT_SC_CLK_CTRL3__RESERVED_03__SHIFT 0x3 +#define CGTT_SC_CLK_CTRL3__RESERVED_04__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL3__RESERVED_05__SHIFT 0x5 +#define CGTT_SC_CLK_CTRL3__RESERVED_06__SHIFT 0x6 +#define CGTT_SC_CLK_CTRL3__RESERVED_07__SHIFT 0x7 +#define CGTT_SC_CLK_CTRL3__RESERVED_08__SHIFT 0x8 +#define CGTT_SC_CLK_CTRL3__RESERVED_09__SHIFT 0x9 +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT 0xa +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE__SHIFT 0xb +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE__SHIFT 0xd +#define CGTT_SC_CLK_CTRL3__RESERVED_18__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL3__RESERVED_19__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL3__RESERVED_20__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL3__RESERVED_21__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL3__RESERVED_22__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL3__RESERVED_23__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL3__RESERVED_24__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL3__RESERVED_25__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL3__RESERVED_26__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL3__RESERVED_27__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL3__RESERVED_00_MASK 0x00000001L +#define CGTT_SC_CLK_CTRL3__RESERVED_01_MASK 0x00000002L +#define CGTT_SC_CLK_CTRL3__RESERVED_02_MASK 0x00000004L +#define CGTT_SC_CLK_CTRL3__RESERVED_03_MASK 0x00000008L +#define CGTT_SC_CLK_CTRL3__RESERVED_04_MASK 0x00000010L +#define CGTT_SC_CLK_CTRL3__RESERVED_05_MASK 0x00000020L +#define CGTT_SC_CLK_CTRL3__RESERVED_06_MASK 0x00000040L +#define CGTT_SC_CLK_CTRL3__RESERVED_07_MASK 0x00000080L +#define CGTT_SC_CLK_CTRL3__RESERVED_08_MASK 0x00000100L +#define CGTT_SC_CLK_CTRL3__RESERVED_09_MASK 0x00000200L +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE_MASK 0x00000400L +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE_MASK 0x00000800L +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE_MASK 0x00002000L +#define CGTT_SC_CLK_CTRL3__RESERVED_18_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL3__RESERVED_19_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL3__RESERVED_20_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL3__RESERVED_21_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL3__RESERVED_22_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL3__RESERVED_23_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL3__RESERVED_24_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL3__RESERVED_25_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL3__RESERVED_26_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL3__RESERVED_27_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL4 +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x1 +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE__SHIFT 0x2 +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE__SHIFT 0x3 +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x5 +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x6 +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE__SHIFT 0x8 +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE__SHIFT 0x9 +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT 0xa +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_STALL_OVERRIDE__SHIFT 0xb +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_STALL_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000001L +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000002L +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE_MASK 0x00000004L +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE_MASK 0x00000008L +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE_MASK 0x00000010L +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000020L +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000040L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE_MASK 0x00000100L +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE_MASK 0x00000200L +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE_MASK 0x00000400L +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_STALL_OVERRIDE_MASK 0x00000800L +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_STALL_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_OVERRIDE_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1_pwrdec +//ICG_GL1C_CLK_CTRL +#define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1C_CLK_CTRL__UTCL0_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER0_CLK_OVERRIDE__SHIFT 0xa +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER1_CLK_OVERRIDE__SHIFT 0xb +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER2_CLK_OVERRIDE__SHIFT 0xc +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER3_CLK_OVERRIDE__SHIFT 0xd +#define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1C_CLK_CTRL__UTCL0_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000200L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER0_CLK_OVERRIDE_MASK 0x00000400L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER1_CLK_OVERRIDE_MASK 0x00000800L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER2_CLK_OVERRIDE_MASK 0x00001000L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER3_CLK_OVERRIDE_MASK 0x00002000L +//GL1I_GL1R_MGCG_OVERRIDE +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//GL1XI_GL1XR_MGCG_OVERRIDE +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//ICG_GL1XC_CLK_CTRL +#define ICG_GL1XC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1XC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1XC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1XC_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1XC_CLK_CTRL__UTCL0_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1XC_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1XC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GL1XC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GL1XC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GL1XC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_GL1XC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1XC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1XC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1XC_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1XC_CLK_CTRL__UTCL0_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1XC_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GL1XC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GL1XC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GL1XC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_GL1XC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000200L +//ICG_GL1A_CTRL +#define ICG_GL1A_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1A_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1A_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1A_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +//ICG_GL1XA_CTRL +#define ICG_GL1XA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1XA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1XA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1XA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1XA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1XA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1XA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1XA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1XA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1XA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1XA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1XA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_hypdec +//GL1_PIPE_STEER_LSB +#define GL1_PIPE_STEER_LSB__PIPE0__SHIFT 0x0 +#define GL1_PIPE_STEER_LSB__PIPE1__SHIFT 0x4 +#define GL1_PIPE_STEER_LSB__PIPE2__SHIFT 0x8 +#define GL1_PIPE_STEER_LSB__PIPE3__SHIFT 0xc +#define GL1_PIPE_STEER_LSB__PIPE4__SHIFT 0x10 +#define GL1_PIPE_STEER_LSB__PIPE5__SHIFT 0x14 +#define GL1_PIPE_STEER_LSB__PIPE6__SHIFT 0x18 +#define GL1_PIPE_STEER_LSB__PIPE7__SHIFT 0x1c +#define GL1_PIPE_STEER_LSB__PIPE0_MASK 0x0000000FL +#define GL1_PIPE_STEER_LSB__PIPE1_MASK 0x000000F0L +#define GL1_PIPE_STEER_LSB__PIPE2_MASK 0x00000F00L +#define GL1_PIPE_STEER_LSB__PIPE3_MASK 0x0000F000L +#define GL1_PIPE_STEER_LSB__PIPE4_MASK 0x000F0000L +#define GL1_PIPE_STEER_LSB__PIPE5_MASK 0x00F00000L +#define GL1_PIPE_STEER_LSB__PIPE6_MASK 0x0F000000L +#define GL1_PIPE_STEER_LSB__PIPE7_MASK 0xF0000000L +//GL1_PIPE_STEER_MSB +#define GL1_PIPE_STEER_MSB__PIPE8__SHIFT 0x0 +#define GL1_PIPE_STEER_MSB__PIPE9__SHIFT 0x4 +#define GL1_PIPE_STEER_MSB__PIPE10__SHIFT 0x8 +#define GL1_PIPE_STEER_MSB__PIPE11__SHIFT 0xc +#define GL1_PIPE_STEER_MSB__MODE__SHIFT 0x10 +#define GL1_PIPE_STEER_MSB__PIPE8_MASK 0x0000000FL +#define GL1_PIPE_STEER_MSB__PIPE9_MASK 0x000000F0L +#define GL1_PIPE_STEER_MSB__PIPE10_MASK 0x00000F00L +#define GL1_PIPE_STEER_MSB__PIPE11_MASK 0x0000F000L +#define GL1_PIPE_STEER_MSB__MODE_MASK 0x00010000L +//GL1_HASH_CFG +#define GL1_HASH_CFG__HASH_XOR_BIT0__SHIFT 0x0 +#define GL1_HASH_CFG__HASH_XOR_BIT1__SHIFT 0x6 +#define GL1_HASH_CFG__HASH_XOR_BIT2__SHIFT 0xc +#define GL1_HASH_CFG__CHANNEL_FLIP__SHIFT 0x12 +#define GL1_HASH_CFG__CHANNEL_HASH_EN__SHIFT 0x13 +#define GL1_HASH_CFG__RESERVED__SHIFT 0x14 +#define GL1_HASH_CFG__HASH_XOR_BIT0_MASK 0x0000003FL +#define GL1_HASH_CFG__HASH_XOR_BIT1_MASK 0x00000FC0L +#define GL1_HASH_CFG__HASH_XOR_BIT2_MASK 0x0003F000L +#define GL1_HASH_CFG__CHANNEL_FLIP_MASK 0x00040000L +#define GL1_HASH_CFG__CHANNEL_HASH_EN_MASK 0x00080000L +#define GL1_HASH_CFG__RESERVED_MASK 0xFFF00000L +//GC_USER_SHADER_ARRAY_CONFIG +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L +//GC_USER_RB_BACKEND_DISABLE +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x000000F0L +//GC_USER_RMI_REDUNDANCY +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 +#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 +#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L +#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L +#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L +//GC_USER_SHADER_RATE_CONFIG_1 +#define GC_USER_SHADER_RATE_CONFIG_1__SHADER_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG_1__SHADER_RATE_MASK 0x000007FEL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmh_hypdec +//GRBMH_WGP_SA0_REMAP_CNTL +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP0_SA0_REMAP_EN__SHIFT 0x0 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP1_SA0_REMAP_EN__SHIFT 0x1 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP2_SA0_REMAP_EN__SHIFT 0x2 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP3_SA0_REMAP_EN__SHIFT 0x3 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP4_SA0_REMAP_EN__SHIFT 0x4 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP5_SA0_REMAP_EN__SHIFT 0x5 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP6_SA0_REMAP_EN__SHIFT 0x6 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP7_SA0_REMAP_EN__SHIFT 0x7 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP8_SA0_REMAP_EN__SHIFT 0x8 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP9_SA0_REMAP_EN__SHIFT 0x9 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP10_SA0_REMAP_EN__SHIFT 0xa +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_SIDE__SHIFT 0xb +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_WGP__SHIFT 0xc +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP0_SA0_REMAP_EN__SHIFT 0x10 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP1_SA0_REMAP_EN__SHIFT 0x11 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP2_SA0_REMAP_EN__SHIFT 0x12 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP3_SA0_REMAP_EN__SHIFT 0x13 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP4_SA0_REMAP_EN__SHIFT 0x14 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP5_SA0_REMAP_EN__SHIFT 0x15 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP6_SA0_REMAP_EN__SHIFT 0x16 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP7_SA0_REMAP_EN__SHIFT 0x17 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP8_SA0_REMAP_EN__SHIFT 0x18 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP9_SA0_REMAP_EN__SHIFT 0x19 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP10_SA0_REMAP_EN__SHIFT 0x1a +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_SIDE__SHIFT 0x1b +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_WGP__SHIFT 0x1c +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP0_SA0_REMAP_EN_MASK 0x00000001L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP1_SA0_REMAP_EN_MASK 0x00000002L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP2_SA0_REMAP_EN_MASK 0x00000004L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP3_SA0_REMAP_EN_MASK 0x00000008L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP4_SA0_REMAP_EN_MASK 0x00000010L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP5_SA0_REMAP_EN_MASK 0x00000020L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP6_SA0_REMAP_EN_MASK 0x00000040L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP7_SA0_REMAP_EN_MASK 0x00000080L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP8_SA0_REMAP_EN_MASK 0x00000100L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP9_SA0_REMAP_EN_MASK 0x00000200L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP10_SA0_REMAP_EN_MASK 0x00000400L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_SIDE_MASK 0x00000800L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_WGP_MASK 0x0000F000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP0_SA0_REMAP_EN_MASK 0x00010000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP1_SA0_REMAP_EN_MASK 0x00020000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP2_SA0_REMAP_EN_MASK 0x00040000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP3_SA0_REMAP_EN_MASK 0x00080000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP4_SA0_REMAP_EN_MASK 0x00100000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP5_SA0_REMAP_EN_MASK 0x00200000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP6_SA0_REMAP_EN_MASK 0x00400000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP7_SA0_REMAP_EN_MASK 0x00800000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP8_SA0_REMAP_EN_MASK 0x01000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP9_SA0_REMAP_EN_MASK 0x02000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP10_SA0_REMAP_EN_MASK 0x04000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_SIDE_MASK 0x08000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_WGP_MASK 0xF0000000L +//GRBMH_WGP_SA1_REMAP_CNTL +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP0_SA1_REMAP_EN__SHIFT 0x0 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP1_SA1_REMAP_EN__SHIFT 0x1 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP2_SA1_REMAP_EN__SHIFT 0x2 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP3_SA1_REMAP_EN__SHIFT 0x3 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP4_SA1_REMAP_EN__SHIFT 0x4 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP5_SA1_REMAP_EN__SHIFT 0x5 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP6_SA1_REMAP_EN__SHIFT 0x6 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP7_SA1_REMAP_EN__SHIFT 0x7 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP8_SA1_REMAP_EN__SHIFT 0x8 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP9_SA1_REMAP_EN__SHIFT 0x9 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP10_SA1_REMAP_EN__SHIFT 0xa +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_SIDE__SHIFT 0xb +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_WGP__SHIFT 0xc +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP0_SA1_REMAP_EN__SHIFT 0x10 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP1_SA1_REMAP_EN__SHIFT 0x11 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP2_SA1_REMAP_EN__SHIFT 0x12 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP3_SA1_REMAP_EN__SHIFT 0x13 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP4_SA1_REMAP_EN__SHIFT 0x14 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP5_SA1_REMAP_EN__SHIFT 0x15 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP6_SA1_REMAP_EN__SHIFT 0x16 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP7_SA1_REMAP_EN__SHIFT 0x17 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP8_SA1_REMAP_EN__SHIFT 0x18 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP9_SA1_REMAP_EN__SHIFT 0x19 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP10_SA1_REMAP_EN__SHIFT 0x1a +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_SIDE__SHIFT 0x1b +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_WGP__SHIFT 0x1c +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP0_SA1_REMAP_EN_MASK 0x00000001L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP1_SA1_REMAP_EN_MASK 0x00000002L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP2_SA1_REMAP_EN_MASK 0x00000004L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP3_SA1_REMAP_EN_MASK 0x00000008L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP4_SA1_REMAP_EN_MASK 0x00000010L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP5_SA1_REMAP_EN_MASK 0x00000020L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP6_SA1_REMAP_EN_MASK 0x00000040L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP7_SA1_REMAP_EN_MASK 0x00000080L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP8_SA1_REMAP_EN_MASK 0x00000100L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP9_SA1_REMAP_EN_MASK 0x00000200L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP10_SA1_REMAP_EN_MASK 0x00000400L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_SIDE_MASK 0x00000800L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_WGP_MASK 0x0000F000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP0_SA1_REMAP_EN_MASK 0x00010000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP1_SA1_REMAP_EN_MASK 0x00020000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP2_SA1_REMAP_EN_MASK 0x00040000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP3_SA1_REMAP_EN_MASK 0x00080000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP4_SA1_REMAP_EN_MASK 0x00100000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP5_SA1_REMAP_EN_MASK 0x00200000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP6_SA1_REMAP_EN_MASK 0x00400000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP7_SA1_REMAP_EN_MASK 0x00800000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP8_SA1_REMAP_EN_MASK 0x01000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP9_SA1_REMAP_EN_MASK 0x02000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP10_SA1_REMAP_EN_MASK 0x04000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_SIDE_MASK 0x08000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_WGP_MASK 0xF0000000L +//GRBMH_RB_SA0_REMAP_CNTL +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP_EN__SHIFT 0x0 +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP__SHIFT 0x1 +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP_EN__SHIFT 0x4 +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP__SHIFT 0x5 +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP_EN__SHIFT 0x8 +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP__SHIFT 0x9 +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP_EN__SHIFT 0xc +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP__SHIFT 0xd +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP_EN_MASK 0x00000001L +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP_MASK 0x0000000EL +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP_EN_MASK 0x00000010L +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP_MASK 0x000000E0L +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP_EN_MASK 0x00000100L +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP_MASK 0x00000E00L +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP_EN_MASK 0x00001000L +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP_MASK 0x0000E000L +//GRBMH_RB_SA1_REMAP_CNTL +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP_EN__SHIFT 0x0 +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP__SHIFT 0x1 +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP_EN__SHIFT 0x4 +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP__SHIFT 0x5 +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP_EN__SHIFT 0x8 +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP__SHIFT 0x9 +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP_EN__SHIFT 0xc +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP__SHIFT 0xd +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP_EN_MASK 0x00000001L +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP_MASK 0x0000000EL +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP_EN_MASK 0x00000010L +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP_MASK 0x000000E0L +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP_EN_MASK 0x00000100L +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP_MASK 0x00000E00L +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP_EN_MASK 0x00001000L +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP_MASK 0x0000E000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpfdec +//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x000000FFL +//GCUTCL2_ICG_CTRL +#define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GCMC_SHARED_ACTIVE_FCN_ID +#define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//GCUTCL2_CGTT_BUSY_CTRL +#define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//GCUTCL2_GROUP_RET_FAULT_STATUS +#define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pfdec +//GCVM_L2_CNTL +#define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//GCVM_L2_CNTL2 +#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//GCVM_L2_CNTL3 +#define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//GCVM_L2_STATUS +#define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define GCVM_L2_STATUS__FOUND_PDE3_CACHE_PARITY_ERRORS__SHIFT 0x16 +#define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +#define GCVM_L2_STATUS__FOUND_PDE3_CACHE_PARITY_ERRORS_MASK 0x00400000L +//GCVM_DUMMY_PAGE_FAULT_CNTL +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//GCVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI13__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI13_MASK 0x00001FFFL +//GCVM_INVALIDATE_CNTL +#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//GCVM_L2_PROTECTION_FAULT_CNTL_LO32 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xe +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1e +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1f +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x3FFFC000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x40000000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT_MASK 0x80000000L +//GCVM_L2_PROTECTION_FAULT_CNTL_HI32 +#define GCVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT_MASK 0x00000001L +//GCVM_L2_PROTECTION_FAULT_CNTL2 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//GCVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_STATUS_LO32 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS__SHIFT 0x5 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR__SHIFT 0xa +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__CID__SHIFT 0xb +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__RW__SHIFT 0x14 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC__SHIFT 0x15 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID__SHIFT 0x16 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VF__SHIFT 0x1a +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID__SHIFT 0x1b +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR_MASK 0x0000001EL +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS_MASK 0x000003E0L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR_MASK 0x00000400L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__CID_MASK 0x000FF800L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__RW_MASK 0x00100000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC_MASK 0x00200000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID_MASK 0x03C00000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VF_MASK 0x04000000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID_MASK 0xF8000000L +//GCVM_L2_PROTECTION_FAULT_STATUS_HI32 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__UCE__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__FED__SHIFT 0x2 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__UCE_MASK 0x00000002L +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__FED_MASK 0x00000004L +//GCVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI13__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI13_MASK 0x00001FFFL +//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI8__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI8_MASK 0x000000FFL +//GCVM_DEBUG +#define GCVM_DEBUG__FLAGS__SHIFT 0x0 +#define GCVM_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI8__SHIFT 0x0 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI8_MASK 0x000000FFL +//GCVM_L2_CNTL4 +#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//GCVM_L2_MM_GROUP_RT_CLASSES +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//GCVM_L2_BANK_SELECT_RESERVED_CID +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//GCVM_L2_BANK_SELECT_RESERVED_CID2 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//GCVM_L2_CACHE_PARITY_CNTL +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//GCVM_L2_ICG_CTRL +#define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GCVM_L2_CNTL5 +#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x10 +#define GCVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF__SHIFT 0x11 +#define GCVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ__SHIFT 0x12 +#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00010000L +#define GCVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF_MASK 0x00020000L +#define GCVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ_MASK 0x00040000L +//GCVM_L2_GCR_CNTL +#define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//GCVML2_WALKER_MACRO_THROTTLE_TIME +#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 +#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL +//GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT +#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 +#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL +//GCVML2_WALKER_MICRO_THROTTLE_TIME +#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 +#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL +//GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT +#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 +#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL +//GCVM_L2_CGTT_BUSY_CTRL +#define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//GCVM_L2_PTE_CACHE_DUMP_CNTL +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//GCVM_L2_PTE_CACHE_DUMP_READ +#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//GCVML2_MAIN_DEBUG +#define GCVML2_MAIN_DEBUG__FLAGS__SHIFT 0x0 +#define GCVML2_MAIN_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GCVML2_WALKER_DEBUG +#define GCVML2_WALKER_DEBUG__FLAGS__SHIFT 0x0 +#define GCVML2_WALKER_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32__ADDR_LO32__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32__ADDR_LO32_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32__ADDR_HI13__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32__ADDR_HI13_MASK 0x00001FFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VMID__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VFID__SHIFT 0x4 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VF__SHIFT 0x9 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__GPA__SHIFT 0xa +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__RD_PERM__SHIFT 0xc +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__WR_PERM__SHIFT 0xd +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__EX_PERM__SHIFT 0xe +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__AT_PERM__SHIFT 0xf +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__CLIENT_ID__SHIFT 0x10 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__REQ__SHIFT 0x1f +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VMID_MASK 0x0000000FL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VFID_MASK 0x000001F0L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VF_MASK 0x00000200L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__GPA_MASK 0x00000C00L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__RD_PERM_MASK 0x00001000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__WR_PERM_MASK 0x00002000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__EX_PERM_MASK 0x00004000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__AT_PERM_MASK 0x00008000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__CLIENT_ID_MASK 0x01FF0000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__REQ_MASK 0x80000000L +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32__ADDR_LO32__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32__ADDR_LO32_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32__ADDR_HI8__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32__ADDR_HI8_MASK 0x000000FFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PERMS__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__FRAGMENT_SIZE__SHIFT 0x4 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SNOOP__SHIFT 0xa +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SPA__SHIFT 0xb +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__IO__SHIFT 0xc +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PTE_TMZ__SHIFT 0xd +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NO_PTE__SHIFT 0xe +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__MTYPE__SHIFT 0xf +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__COMP_EN__SHIFT 0x11 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NACK__SHIFT 0x12 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__HDM__SHIFT 0x14 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__TMPM_RETRY__SHIFT 0x15 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__ACK__SHIFT 0x1f +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PERMS_MASK 0x0000000FL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__FRAGMENT_SIZE_MASK 0x000003F0L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SNOOP_MASK 0x00000400L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SPA_MASK 0x00000800L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__IO_MASK 0x00001000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PTE_TMZ_MASK 0x00002000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NO_PTE_MASK 0x00004000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__MTYPE_MASK 0x00018000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__COMP_EN_MASK 0x00020000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NACK_MASK 0x000C0000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__HDM_MASK 0x00100000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__TMPM_RETRY_MASK 0x00200000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__ACK_MASK 0x80000000L +//GCVM_L2_BANK_SELECT_MASKS +#define GCVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define GCVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define GCVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define GCVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define GCVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define GCVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define GCVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L +//GCVM_L2_UTCL2_FED_VMID_STS +#define GCVM_L2_UTCL2_FED_VMID_STS__VMIDS__SHIFT 0x0 +#define GCVM_L2_UTCL2_FED_VMID_STS__VMIDS_MASK 0x0000FFFFL +//GCVM_L2_UTCL2_FED_ACK_REG +#define GCVM_L2_UTCL2_FED_ACK_REG__VMIDS__SHIFT 0x0 +#define GCVM_L2_UTCL2_FED_ACK_REG__VMIDS_MASK 0x0000FFFFL +//GCVML2_IH_FAULT_INTERRUPT_CNTL +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_PF_POISON_INTERRUPT__SHIFT 0x0 +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_VF_POISON_INTERRUPT__SHIFT 0x1 +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__POISON_INTERRUPT_TO_PF__SHIFT 0x2 +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_PF_POISON_INTERRUPT_MASK 0x00000001L +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_VF_POISON_INTERRUPT_MASK 0x00000002L +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__POISON_INTERRUPT_TO_PF_MASK 0x00000004L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpfdec +//GC_L2TLB_TLB0_STATUS +#define GC_L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define GC_L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define GC_L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define GC_L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//GC_L2TLB_TLB0_RETRY_CNTL +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_COUNT__SHIFT 0x0 +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_TIMER__SHIFT 0x10 +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_ENABLE__SHIFT 0x15 +#define GC_L2TLB_TLB0_RETRY_CNTL__NON_TMPM_RETRY_ENABLE__SHIFT 0x16 +#define GC_L2TLB_TLB0_RETRY_CNTL__TMPM_RETRY_ENABLE__SHIFT 0x17 +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_COUNT_MASK 0x0000FFFFL +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_TIMER_MASK 0x001F0000L +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_ENABLE_MASK 0x00200000L +#define GC_L2TLB_TLB0_RETRY_CNTL__NON_TMPM_RETRY_ENABLE_MASK 0x00400000L +#define GC_L2TLB_TLB0_RETRY_CNTL__TMPM_RETRY_ENABLE_MASK 0x00800000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvcdec +//GCMC_VM_FB_LOCATION_BASE_LO32 +#define GCMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_FB_LOCATION_BASE_HI32 +#define GCMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK 0x00000001L +//GCMC_VM_FB_LOCATION_TOP_LO32 +#define GCMC_VM_FB_LOCATION_TOP_LO32__FB_TOP_LO32__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_TOP_LO32__FB_TOP_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_FB_LOCATION_TOP_HI32 +#define GCMC_VM_FB_LOCATION_TOP_HI32__FB_TOP_HI1__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_TOP_HI32__FB_TOP_HI1_MASK 0x00000001L +//GCMC_VM_AGP_TOP_LO32 +#define GCMC_VM_AGP_TOP_LO32__AGP_TOP_LO32__SHIFT 0x0 +#define GCMC_VM_AGP_TOP_LO32__AGP_TOP_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_AGP_TOP_HI32 +#define GCMC_VM_AGP_TOP_HI32__AGP_TOP_HI1__SHIFT 0x0 +#define GCMC_VM_AGP_TOP_HI32__AGP_TOP_HI1_MASK 0x00000001L +//GCMC_VM_AGP_BOT_LO32 +#define GCMC_VM_AGP_BOT_LO32__AGP_BOT_LO32__SHIFT 0x0 +#define GCMC_VM_AGP_BOT_LO32__AGP_BOT_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_AGP_BOT_HI32 +#define GCMC_VM_AGP_BOT_HI32__AGP_BOT_HI1__SHIFT 0x0 +#define GCMC_VM_AGP_BOT_HI32__AGP_BOT_HI1_MASK 0x00000001L +//GCMC_VM_AGP_BASE_LO32 +#define GCMC_VM_AGP_BASE_LO32__AGP_BASE_LO32__SHIFT 0x0 +#define GCMC_VM_AGP_BASE_LO32__AGP_BASE_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_AGP_BASE_HI32 +#define GCMC_VM_AGP_BASE_HI32__AGP_BASE_HI1__SHIFT 0x0 +#define GCMC_VM_AGP_BASE_HI32__AGP_BASE_HI1_MASK 0x00000001L +//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32__LOGICAL_ADDR_LO32__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32__LOGICAL_ADDR_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32__LOGICAL_ADDR_HI7__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32__LOGICAL_ADDR_HI7_MASK 0x0000007FL +//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32__LOGICAL_ADDR_LO32__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32__LOGICAL_ADDR_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32__LOGICAL_ADDR_HI7__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32__LOGICAL_ADDR_HI7_MASK 0x0000007FL +//GCMC_VM_MX_L1_TLB_CNTL +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2vcdec +//GCVM_CONTEXT0_CNTL +#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT1_CNTL +#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT2_CNTL +#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT3_CNTL +#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT4_CNTL +#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT5_CNTL +#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT6_CNTL +#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT7_CNTL +#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT8_CNTL +#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT9_CNTL +#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT10_CNTL +#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT11_CNTL +#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT12_CNTL +#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT13_CNTL +#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT14_CNTL +#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT15_CNTL +#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXTS_DISABLE +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//GCVM_INVALIDATE_ENG0_SEM +#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG1_SEM +#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG2_SEM +#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG3_SEM +#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG4_SEM +#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG5_SEM +#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG6_SEM +#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG7_SEM +#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG8_SEM +#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG9_SEM +#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG10_SEM +#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG11_SEM +#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG12_SEM +#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG13_SEM +#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG14_SEM +#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG15_SEM +#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG16_SEM +#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG17_SEM +#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG0_REQ +#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG1_REQ +#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG2_REQ +#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG3_REQ +#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG4_REQ +#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG5_REQ +#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG6_REQ +#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG7_REQ +#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG8_REQ +#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG9_REQ +#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG10_REQ +#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG11_REQ +#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG12_REQ +#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG13_REQ +#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG14_REQ +#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG15_REQ +#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG16_REQ +#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG17_REQ +#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG0_ACK +#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG1_ACK +#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG2_ACK +#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG3_ACK +#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG4_ACK +#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG5_ACK +#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG6_ACK +#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG7_ACK +#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG8_ACK +#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG9_ACK +#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG10_ACK +#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG11_ACK +#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG12_ACK +#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG13_ACK +#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG14_ACK +#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG15_ACK +#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG16_ACK +#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG17_ACK +#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvfdec +//GCMC_VM_PCIE_ATOMIC_SUPPORTED +#define GCMC_VM_PCIE_ATOMIC_SUPPORTED__PCIE_ATOMIC_SUPPORTED__SHIFT 0x0 +#define GCMC_VM_PCIE_ATOMIC_SUPPORTED__PCIE_ATOMIC_SUPPORTED_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbvfdec +//GC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC +#define GC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC__EN_RETRY_ON_ATOMIC__SHIFT 0x0 +#define GC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC__EN_RETRY_ON_ATOMIC_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2prdec +//GCMC_VM_L2_PERFCOUNTER_LO +#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCMC_VM_L2_PERFCOUNTER_HI +#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GCUTCL2_PERFCOUNTER_LO +#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_PERFCOUNTER_HI +#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2prdec +//GC_ATC_L2_PERFCOUNTER_LO +#define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GC_ATC_L2_PERFCOUNTER_HI +#define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec +//GC_L2TLB_PERFCOUNTER_LO +#define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GC_L2TLB_PERFCOUNTER_HI +#define GC_L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GC_L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GC_L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pldec +//GCMC_VM_L2_PERFCOUNTER0_CFG +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER1_CFG +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER2_CFG +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER3_CFG +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER4_CFG +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER5_CFG +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER6_CFG +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER7_CFG +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER8_CFG +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER9_CFG +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER10_CFG +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER11_CFG +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER12_CFG +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER13_CFG +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER14_CFG +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER15_CFG +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCUTCL2_PERFCOUNTER0_CFG +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER1_CFG +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER2_CFG +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER3_CFG +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET0_GROUP__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET1_GROUP__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET0_GROUP_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET1_GROUP_MASK 0x0000FF00L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2pldec +//GC_ATC_L2_PERFCOUNTER0_CFG +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER1_CFG +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER2_CFG +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER3_CFG +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER4_CFG +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER5_CFG +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER6_CFG +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER7_CFG +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER8_CFG +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER9_CFG +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER10_CFG +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER11_CFG +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER12_CFG +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER13_CFG +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER14_CFG +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER15_CFG +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec +//GC_L2TLB_PERFCOUNTER0_CFG +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER1_CFG +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER2_CFG +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER3_CFG +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER_RSLT_CNTL +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedhvdec +//GCVM_PCIE_ATS_CNTL +#define GCVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define GCVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define GCVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define GCVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//GCMC_VM_NB_MMIOBASE +#define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//GCMC_VM_NB_MMIOLIMIT +#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//GCMC_VM_NB_PCI_CTRL +#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//GCMC_VM_NB_PCI_ARB +#define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//GCMC_VM_NB_TOP_OF_DRAM_SLOT1 +#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//GCMC_VM_NB_LOWER_TOP_OF_DRAM2 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//GCMC_VM_NB_UPPER_TOP_OF_DRAM2 +#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000FFFFFL +//GCMC_VM_STEERING +#define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//GCMC_SHARED_VIRT_RESET_REQ +#define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x8 +#define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x000000FFL +#define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x00000100L +//GCMC_VM_XGMI_LFB_CNTL +#define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//GCMC_VM_XGMI_LFB_SIZE +#define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//GCMC_VM_HOST_MAPPING +#define GCMC_VM_HOST_MAPPING__MODE__SHIFT 0x0 +#define GCMC_VM_HOST_MAPPING__MODE_MASK 0x00000001L +//GCMC_VM_XGMI_GPUIOV_ENABLE +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L +//GCMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LPDDR_ADDRESS_START +#define GCMC_VM_LPDDR_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LPDDR_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LPDDR_ADDRESS_END +#define GCMC_VM_LPDDR_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LPDDR_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_APT_CNTL +#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define GCMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL__SHIFT 0x8 +#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +#define GCMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL_MASK 0x00000300L +//GCUTCL2_HARVEST_BYPASS_GROUPS +#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL +//GCUTCL2_ROUTER_DEBUG +#define GCUTCL2_ROUTER_DEBUG__FLAGS__SHIFT 0x0 +#define GCUTCL2_ROUTER_DEBUG__FLAGS_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2dec +//GC_ATC_L2_CNTL +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x2 +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x4 +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x5 +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x6 +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0x8 +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xa +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xb +#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0xc +#define GC_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0xf +#define GC_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x11 +#define GC_ATC_L2_CNTL__CLI_GVA_REQ_FRAG_SIZE__SHIFT 0x17 +#define GC_ATC_L2_CNTL__FORCE_8T_CAP_ON_AT_RETURN__SHIFT 0x1d +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x0000000CL +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000010L +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000020L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x000000C0L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00000300L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L +#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00007000L +#define GC_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00018000L +#define GC_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x007E0000L +#define GC_ATC_L2_CNTL__CLI_GVA_REQ_FRAG_SIZE_MASK 0x1F800000L +#define GC_ATC_L2_CNTL__FORCE_8T_CAP_ON_AT_RETURN_MASK 0x20000000L +//GC_ATC_L2_CNTL2 +#define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define GC_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define GC_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define GC_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//GC_ATC_L2_CACHE_DATA0 +#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL +//GC_ATC_L2_CACHE_DATA1 +#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//GC_ATC_L2_CACHE_DATA2 +#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//GC_ATC_L2_CACHE_DATA3 +#define GC_ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//GC_ATC_L2_CACHE_DATA4 +#define GC_ATC_L2_CACHE_DATA4__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA4__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0xFFFFFFFFL +//GC_ATC_L2_CNTL3 +#define GC_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define GC_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define GC_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc +#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define GC_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define GC_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define GC_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L +#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//GC_ATC_L2_STATUS +#define GC_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define GC_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define GC_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define GC_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//GC_ATC_L2_MISC_CG +#define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define GC_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define GC_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define GC_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//GC_ATC_L2_ICG_CTRL +#define GC_ATC_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GC_ATC_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GC_ATC_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GC_ATC_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GC_ATC_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GC_ATC_L2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GC_ATC_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GC_ATC_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GC_ATC_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GC_ATC_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GC_ATC_L2_SDPPORT_CTRL +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L +//GC_ATC_L2_MISC_DEBUG +#define GC_ATC_L2_MISC_DEBUG__FLAGS__SHIFT 0x0 +#define GC_ATC_L2_MISC_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GC_ATC_L2_BANK_SELECT_MASKS +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +//GC_ATC_L2_FAULT_CNTL +#define GC_ATC_L2_FAULT_CNTL__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x0 +#define GC_ATC_L2_FAULT_CNTL__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define GC_ATC_L2_FAULT_CNTL__LOG_REQUEST_ADDRESS__SHIFT 0x2 +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x3 +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x4 +#define GC_ATC_L2_FAULT_CNTL__CLEAR_FAULT_STATUS_ADDR_MASK 0x00000001L +#define GC_ATC_L2_FAULT_CNTL__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define GC_ATC_L2_FAULT_CNTL__LOG_REQUEST_ADDRESS_MASK 0x00000004L +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x00000008L +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x00000010L +//GC_ATC_L2_FAULT_STATUS +#define GC_ATC_L2_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define GC_ATC_L2_FAULT_STATUS__ERROR_TYPE__SHIFT 0x1 +#define GC_ATC_L2_FAULT_STATUS__CID__SHIFT 0x5 +#define GC_ATC_L2_FAULT_STATUS__RWXA__SHIFT 0xe +#define GC_ATC_L2_FAULT_STATUS__VMID__SHIFT 0x12 +#define GC_ATC_L2_FAULT_STATUS__VF__SHIFT 0x16 +#define GC_ATC_L2_FAULT_STATUS__VFID__SHIFT 0x17 +#define GC_ATC_L2_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define GC_ATC_L2_FAULT_STATUS__ERROR_TYPE_MASK 0x0000001EL +#define GC_ATC_L2_FAULT_STATUS__CID_MASK 0x00003FE0L +#define GC_ATC_L2_FAULT_STATUS__RWXA_MASK 0x0003C000L +#define GC_ATC_L2_FAULT_STATUS__VMID_MASK 0x003C0000L +#define GC_ATC_L2_FAULT_STATUS__VF_MASK 0x00400000L +#define GC_ATC_L2_FAULT_STATUS__VFID_MASK 0x0F800000L +//GC_ATC_L2_FAULT_ADDR_LO +#define GC_ATC_L2_FAULT_ADDR_LO__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define GC_ATC_L2_FAULT_ADDR_LO__LOGICAL_PAGE_ADDR_MASK 0xFFFFFFFFL +//GC_ATC_L2_FAULT_ADDR_HI +#define GC_ATC_L2_FAULT_ADDR_HI__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define GC_ATC_L2_FAULT_ADDR_HI__LOGICAL_PAGE_ADDR_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbhvdec +//GC_L2TLB_TMZ_CNTL +#define GC_L2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 +#define GC_L2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L +//GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L +//GC_L2TLB_GCC_MTYPE_ENCODING_CNTL +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_0__SHIFT 0x0 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_1__SHIFT 0x1 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_2__SHIFT 0x2 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_3__SHIFT 0x3 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_0_MASK 0x00000001L +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_1_MASK 0x00000002L +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_2_MASK 0x00000004L +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_3_MASK 0x00000008L +//GC_L2TLB_FB_COMP_EN_CNTL +#define GC_L2TLB_FB_COMP_EN_CNTL__COMP_EN__SHIFT 0x0 +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_NO_PTE__SHIFT 0x1 +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_PTE__SHIFT 0x2 +#define GC_L2TLB_FB_COMP_EN_CNTL__COMP_EN_MASK 0x00000001L +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_NO_PTE_MASK 0x00000002L +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_PTE_MASK 0x00000004L +//GC_L2TLB_RETRY_TIMEOUT_STATUS_0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_0__LOGICAL_ADDR__SHIFT 0x0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_0__LOGICAL_ADDR_MASK 0xFFFFFFFFL +//GC_L2TLB_RETRY_TIMEOUT_STATUS_1 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__LOGICAL_ADDR__SHIFT 0x0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VMID__SHIFT 0xd +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VFID__SHIFT 0x11 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VF__SHIFT 0x16 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__GPA__SHIFT 0x17 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__RD_PERM__SHIFT 0x19 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__WR_PERM__SHIFT 0x1a +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__EXE_PERM__SHIFT 0x1b +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__TMZ__SHIFT 0x1c +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__CLIENT_ID__SHIFT 0x1d +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__LOGICAL_ADDR_MASK 0x00001FFFL +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VMID_MASK 0x0001E000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VFID_MASK 0x003E0000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VF_MASK 0x00400000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__GPA_MASK 0x01800000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__RD_PERM_MASK 0x02000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__WR_PERM_MASK 0x04000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__EXE_PERM_MASK 0x08000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__TMZ_MASK 0x10000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__CLIENT_ID_MASK 0xE0000000L +//GC_L2TLB_RETRY_TIMEOUT_STATUS_2 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLIENT_ID__SHIFT 0x0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__BUS_ATOMIC_PERM__SHIFT 0x6 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__TLB_ID__SHIFT 0x7 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__RETRY_TIMEOUT__SHIFT 0xb +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLEAR_RETRY_TIMEOUT_STATUS__SHIFT 0x1f +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLIENT_ID_MASK 0x0000003FL +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__BUS_ATOMIC_PERM_MASK 0x00000040L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__TLB_ID_MASK 0x00000780L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__RETRY_TIMEOUT_MASK 0x00000800L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLEAR_RETRY_TIMEOUT_STATUS_MASK 0x80000000L +//GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLIENT_ID__SHIFT 0x0 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SNOOP__SHIFT 0x9 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__ATOMIC__SHIFT 0xa +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VF__SHIFT 0xb +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__HDM__SHIFT 0xc +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SPACE__SHIFT 0xd +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VFID__SHIFT 0x10 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__EXE__SHIFT 0x15 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TMZ__SHIFT 0x16 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VMID__SHIFT 0x18 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TEE__SHIFT 0x1c +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__PCIE_ATOMIC__SHIFT 0x1d +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__RESERVED_SPACE_ENCODING_DETECTED__SHIFT 0x1e +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLEAR__SHIFT 0x1f +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLIENT_ID_MASK 0x000001FFL +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SNOOP_MASK 0x00000200L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__ATOMIC_MASK 0x00000400L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VF_MASK 0x00000800L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__HDM_MASK 0x00001000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SPACE_MASK 0x0000E000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VFID_MASK 0x001F0000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__EXE_MASK 0x00200000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TMZ_MASK 0x00400000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VMID_MASK 0x0F000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TEE_MASK 0x10000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__PCIE_ATOMIC_MASK 0x20000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__RESERVED_SPACE_ENCODING_DETECTED_MASK 0x40000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLEAR_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pspdec +//GCUTCL2_TRANSLATION_BYPASS_BY_VMID +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//GCVML2_SEC_MASTER +#define GCVML2_SEC_MASTER__UNIT_ID__SHIFT 0x0 +#define GCVML2_SEC_MASTER__TRUST_LEVEL__SHIFT 0x6 +#define GCVML2_SEC_MASTER__UNIT_ID_MASK 0x0000003FL +#define GCVML2_SEC_MASTER__TRUST_LEVEL_MASK 0x000003C0L +//GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE +#define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 +#define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L +//GCVM_IOMMU_CONTROL_REGISTER +#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//GCUTC_TRANSLATION_FAULT_CNTL0 +#define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//GCUTC_TRANSLATION_FAULT_CNTL1 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x8 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x9 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0xa +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_HDM__SHIFT 0xb +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x000000FFL +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000100L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000200L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000400L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_HDM_MASK 0x00000800L +//GCUTCL2_COMP_EN_OVERRIDES +#define GCUTCL2_COMP_EN_OVERRIDES__GPA_MODE3__SHIFT 0x0 +#define GCUTCL2_COMP_EN_OVERRIDES__LOCAL_FB_PTE__SHIFT 0x1 +#define GCUTCL2_COMP_EN_OVERRIDES__REMOTE_FB_PTE__SHIFT 0x2 +#define GCUTCL2_COMP_EN_OVERRIDES__ROUTER_ATCL2__SHIFT 0x3 +#define GCUTCL2_COMP_EN_OVERRIDES__GPA_MODE3_MASK 0x00000001L +#define GCUTCL2_COMP_EN_OVERRIDES__LOCAL_FB_PTE_MASK 0x00000002L +#define GCUTCL2_COMP_EN_OVERRIDES__REMOTE_FB_PTE_MASK 0x00000004L +#define GCUTCL2_COMP_EN_OVERRIDES__ROUTER_ATCL2_MASK 0x00000008L +//GCUTCL2_ROUTER_CNTL +#define GCUTCL2_ROUTER_CNTL__OVERRIDE_GPA2_EXE_AND_ATOMIC_PERMS_GRANTED__SHIFT 0x0 +#define GCUTCL2_ROUTER_CNTL__OVERRIDE_GPA2_EXE_AND_ATOMIC_PERMS_GRANTED_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpspdec +//GCMC_VM_FB_SIZE_OFFSET_VF0 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF1 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF2 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF3 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF4 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF5 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF6 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF7 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_OFFSET +#define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_START +#define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_END +#define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//GCUTCL2_MISC_CNTL +#define GCUTCL2_MISC_CNTL__MASK_TDISP_RUN_ATC_DIS_IOMMU_DIS_NPA__SHIFT 0x0 +#define GCUTCL2_MISC_CNTL__MASK_TDISP_RUN_ATC_DIS_IOMMU_DIS_NPA_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpspdec +//GC_L2TLB_TLB0_CAM_ECC_CNTL +#define GC_L2TLB_TLB0_CAM_ECC_CNTL__FORCE_PARITY_ERROR__SHIFT 0x0 +#define GC_L2TLB_TLB0_CAM_ECC_CNTL__FORCE_PARITY_ERROR_MASK 0x00000001L + + +// addressBlock: gfx_se_sqind +//SQ_DEBUG_STS_LOCAL +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0xc +#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0xd +#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0xe +#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0xf +#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x10 +#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x11 +#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x12 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L +#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L +#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L +#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L +#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L +#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L +#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L +#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L +//SQ_DEBUG_CTRL_LOCAL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL +//SQ_WAVE_ACTIVE +#define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL +//SQ_WAVE_VALID_AND_IDLE +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0x000FFFFFL +//SQ_WAVE_MODE +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DST_VGPR_MSB__SHIFT 0xc +#define SQ_WAVE_MODE__SRC0_VGPR_MSB__SHIFT 0xe +#define SQ_WAVE_MODE__SRC1_VGPR_MSB__SHIFT 0x10 +#define SQ_WAVE_MODE__SRC2_VGPR_MSB__SHIFT 0x12 +#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 +#define SQ_WAVE_MODE__SCALAR_PREFETCH_EN__SHIFT 0x18 +#define SQ_WAVE_MODE__REPLAY_MODE__SHIFT 0x19 +#define SQ_WAVE_MODE__FLAT_SCRATCH_IS_NV__SHIFT 0x1a +#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L +#define SQ_WAVE_MODE__DST_VGPR_MSB_MASK 0x00003000L +#define SQ_WAVE_MODE__SRC0_VGPR_MSB_MASK 0x0000C000L +#define SQ_WAVE_MODE__SRC1_VGPR_MSB_MASK 0x00030000L +#define SQ_WAVE_MODE__SRC2_VGPR_MSB_MASK 0x000C0000L +#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L +#define SQ_WAVE_MODE__SCALAR_PREFETCH_EN_MASK 0x01000000L +#define SQ_WAVE_MODE__REPLAY_MODE_MASK 0x02000000L +#define SQ_WAVE_MODE__FLAT_SCRATCH_IS_NV_MASK 0x04000000L +#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L +//SQ_WAVE_STATUS +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_WG__SHIFT 0xb +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TRAP_BARRIER_COMPLETE__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__CLUSTER_TRAP_BARRIER_COMPLETE__SHIFT 0x11 +#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 +#define SQ_WAVE_STATUS__NO_VGPRS__SHIFT 0x18 +#define SQ_WAVE_STATUS__IDLE__SHIFT 0x1c +#define SQ_WAVE_STATUS__WAVE64__SHIFT 0x1d +#define SQ_WAVE_STATUS__DVGPR_EN__SHIFT 0x1e +#define SQ_WAVE_STATUS__WGP_TAKEOVER__SHIFT 0x1f +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__IN_WG_MASK 0x00000800L +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TRAP_BARRIER_COMPLETE_MASK 0x00008000L +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__CLUSTER_TRAP_BARRIER_COMPLETE_MASK 0x00020000L +#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L +#define SQ_WAVE_STATUS__NO_VGPRS_MASK 0x01000000L +#define SQ_WAVE_STATUS__IDLE_MASK 0x10000000L +#define SQ_WAVE_STATUS__WAVE64_MASK 0x20000000L +#define SQ_WAVE_STATUS__DVGPR_EN_MASK 0x40000000L +#define SQ_WAVE_STATUS__WGP_TAKEOVER_MASK 0x80000000L +//SQ_WAVE_STATE_PRIV +#define SQ_WAVE_STATE_PRIV__WG_RR_EN__SHIFT 0x0 +#define SQ_WAVE_STATE_PRIV__SLEEP_WAKEUP__SHIFT 0x1 +#define SQ_WAVE_STATE_PRIV__BARRIER_COMPLETE__SHIFT 0x2 +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_COMPLETE__SHIFT 0x3 +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_ID__SHIFT 0x4 +#define SQ_WAVE_STATE_PRIV__SCC__SHIFT 0x9 +#define SQ_WAVE_STATE_PRIV__SYS_PRIO__SHIFT 0xa +#define SQ_WAVE_STATE_PRIV__USER_PRIO__SHIFT 0xc +#define SQ_WAVE_STATE_PRIV__HALT__SHIFT 0xe +#define SQ_WAVE_STATE_PRIV__POISON_ERR__SHIFT 0xf +#define SQ_WAVE_STATE_PRIV__CLUSTER_BARRIER_COMPLETE__SHIFT 0x10 +#define SQ_WAVE_STATE_PRIV__COND_DBG_SYS__SHIFT 0x11 +#define SQ_WAVE_STATE_PRIV__SCRATCH_EN__SHIFT 0x12 +#define SQ_WAVE_STATE_PRIV__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATE_PRIV__TTRACE_EN__SHIFT 0x14 +#define SQ_WAVE_STATE_PRIV__COND_DBG_USER__SHIFT 0x15 +#define SQ_WAVE_STATE_PRIV__WG_RR_EN_MASK 0x00000001L +#define SQ_WAVE_STATE_PRIV__SLEEP_WAKEUP_MASK 0x00000002L +#define SQ_WAVE_STATE_PRIV__BARRIER_COMPLETE_MASK 0x00000004L +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_COMPLETE_MASK 0x00000008L +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_ID_MASK 0x000001F0L +#define SQ_WAVE_STATE_PRIV__SCC_MASK 0x00000200L +#define SQ_WAVE_STATE_PRIV__SYS_PRIO_MASK 0x00000C00L +#define SQ_WAVE_STATE_PRIV__USER_PRIO_MASK 0x00003000L +#define SQ_WAVE_STATE_PRIV__HALT_MASK 0x00004000L +#define SQ_WAVE_STATE_PRIV__POISON_ERR_MASK 0x00008000L +#define SQ_WAVE_STATE_PRIV__CLUSTER_BARRIER_COMPLETE_MASK 0x00010000L +#define SQ_WAVE_STATE_PRIV__COND_DBG_SYS_MASK 0x00020000L +#define SQ_WAVE_STATE_PRIV__SCRATCH_EN_MASK 0x00040000L +#define SQ_WAVE_STATE_PRIV__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATE_PRIV__TTRACE_EN_MASK 0x00100000L +#define SQ_WAVE_STATE_PRIV__COND_DBG_USER_MASK 0x00200000L +//SQ_WAVE_GPR_ALLOC +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0xc +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000000FFL +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x000FF000L +//SQ_WAVE_LDS_ALLOC +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L +#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L +//SQ_WAVE_IB_STS +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__DS_CNT__SHIFT 0x3 +#define SQ_WAVE_IB_STS__LOAD_CNT__SHIFT 0x9 +#define SQ_WAVE_IB_STS__SAMPLE_CNT__SHIFT 0xf +#define SQ_WAVE_IB_STS__BVH_CNT__SHIFT 0x15 +#define SQ_WAVE_IB_STS__STORE_CNT__SHIFT 0x18 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000007L +#define SQ_WAVE_IB_STS__DS_CNT_MASK 0x000001F8L +#define SQ_WAVE_IB_STS__LOAD_CNT_MASK 0x00007E00L +#define SQ_WAVE_IB_STS__SAMPLE_CNT_MASK 0x001F8000L +#define SQ_WAVE_IB_STS__BVH_CNT_MASK 0x00E00000L +#define SQ_WAVE_IB_STS__STORE_CNT_MASK 0x3F000000L +//SQ_PERF_SNAPSHOT_DATA +#define SQ_PERF_SNAPSHOT_DATA__VALID__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ISSUE__SHIFT 0x1 +#define SQ_PERF_SNAPSHOT_DATA__INST_TYPE__SHIFT 0x2 +#define SQ_PERF_SNAPSHOT_DATA__NO_ISSUE_REASON__SHIFT 0x6 +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ID__SHIFT 0x9 +#define SQ_PERF_SNAPSHOT_DATA__SAMPLING_LOCK_ERR__SHIFT 0xe +#define SQ_PERF_SNAPSHOT_DATA__ASYNC_CNT__SHIFT 0x14 +#define SQ_PERF_SNAPSHOT_DATA__TENSOR_CNT__SHIFT 0x1a +#define SQ_PERF_SNAPSHOT_DATA__VALID_MASK 0x00000001L +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ISSUE_MASK 0x00000002L +#define SQ_PERF_SNAPSHOT_DATA__INST_TYPE_MASK 0x0000003CL +#define SQ_PERF_SNAPSHOT_DATA__NO_ISSUE_REASON_MASK 0x000001C0L +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ID_MASK 0x00003E00L +#define SQ_PERF_SNAPSHOT_DATA__SAMPLING_LOCK_ERR_MASK 0x00004000L +#define SQ_PERF_SNAPSHOT_DATA__ASYNC_CNT_MASK 0x03F00000L +#define SQ_PERF_SNAPSHOT_DATA__TENSOR_CNT_MASK 0xFC000000L +//SQ_PERF_SNAPSHOT_PC_LO +#define SQ_PERF_SNAPSHOT_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_PERF_SNAPSHOT_PC_HI +#define SQ_PERF_SNAPSHOT_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_PC_HI__PC_HI_MASK 0x01FFFFFFL +//SQ_WAVE_IB_DBG1 +#define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18 +#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L +#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L +//SQ_WAVE_FLUSH_IB +#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 +#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL +//SQ_PERF_SNAPSHOT_DATA1 +#define SQ_PERF_SNAPSHOT_DATA1__WAVE_CNT__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_BRMSG__SHIFT 0x9 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_EXPORT__SHIFT 0xa +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS_DIRECT__SHIFT 0xb +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS__SHIFT 0xc +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_TEX__SHIFT 0xd +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_SCALAR__SHIFT 0xe +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU__SHIFT 0xf +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU_ARB_B__SHIFT 0x10 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_BRMSG__SHIFT 0x11 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_EXPORT__SHIFT 0x12 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS_DIRECT__SHIFT 0x13 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS__SHIFT 0x14 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_TEX__SHIFT 0x15 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_SCALAR__SHIFT 0x16 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU__SHIFT 0x17 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU_ARB_B__SHIFT 0x18 +#define SQ_PERF_SNAPSHOT_DATA1__XCNT__SHIFT 0x1a +#define SQ_PERF_SNAPSHOT_DATA1__WAVE_CNT_MASK 0x0000003FL +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_BRMSG_MASK 0x00000200L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_EXPORT_MASK 0x00000400L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS_DIRECT_MASK 0x00000800L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS_MASK 0x00001000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_TEX_MASK 0x00002000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_SCALAR_MASK 0x00004000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU_MASK 0x00008000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU_ARB_B_MASK 0x00010000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_BRMSG_MASK 0x00020000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_EXPORT_MASK 0x00040000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS_DIRECT_MASK 0x00080000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS_MASK 0x00100000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_TEX_MASK 0x00200000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_SCALAR_MASK 0x00400000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU_MASK 0x00800000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU_ARB_B_MASK 0x01000000L +#define SQ_PERF_SNAPSHOT_DATA1__XCNT_MASK 0xFC000000L +//SQ_PERF_SNAPSHOT_DATA2 +#define SQ_PERF_SNAPSHOT_DATA2__LOAD_CNT__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_DATA2__STORE_CNT__SHIFT 0x6 +#define SQ_PERF_SNAPSHOT_DATA2__BVH_CNT__SHIFT 0xc +#define SQ_PERF_SNAPSHOT_DATA2__SAMPLE_CNT__SHIFT 0xf +#define SQ_PERF_SNAPSHOT_DATA2__DS_CNT__SHIFT 0x15 +#define SQ_PERF_SNAPSHOT_DATA2__KM_CNT__SHIFT 0x1b +#define SQ_PERF_SNAPSHOT_DATA2__LOAD_CNT_MASK 0x0000003FL +#define SQ_PERF_SNAPSHOT_DATA2__STORE_CNT_MASK 0x00000FC0L +#define SQ_PERF_SNAPSHOT_DATA2__BVH_CNT_MASK 0x00007000L +#define SQ_PERF_SNAPSHOT_DATA2__SAMPLE_CNT_MASK 0x001F8000L +#define SQ_PERF_SNAPSHOT_DATA2__DS_CNT_MASK 0x07E00000L +#define SQ_PERF_SNAPSHOT_DATA2__KM_CNT_MASK 0xF8000000L +//SQ_WAVE_EXCP_FLAG_PRIV +#define SQ_WAVE_EXCP_FLAG_PRIV__ADDR_WATCH__SHIFT 0x0 +#define SQ_WAVE_EXCP_FLAG_PRIV__MEMVIOL__SHIFT 0x4 +#define SQ_WAVE_EXCP_FLAG_PRIV__SAVE_CONTEXT__SHIFT 0x5 +#define SQ_WAVE_EXCP_FLAG_PRIV__ILLEGAL_INST__SHIFT 0x6 +#define SQ_WAVE_EXCP_FLAG_PRIV__HOST_TRAP__SHIFT 0x7 +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_START__SHIFT 0x8 +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_END__SHIFT 0x9 +#define SQ_WAVE_EXCP_FLAG_PRIV__PERF_SNAPSHOT__SHIFT 0xa +#define SQ_WAVE_EXCP_FLAG_PRIV__TRAP_AFTER_INST__SHIFT 0xb +#define SQ_WAVE_EXCP_FLAG_PRIV__XNACK_ERROR__SHIFT 0xc +#define SQ_WAVE_EXCP_FLAG_PRIV__FIRST_MEMVIOL_SOURCE__SHIFT 0x1e +#define SQ_WAVE_EXCP_FLAG_PRIV__ADDR_WATCH_MASK 0x0000000FL +#define SQ_WAVE_EXCP_FLAG_PRIV__MEMVIOL_MASK 0x00000010L +#define SQ_WAVE_EXCP_FLAG_PRIV__SAVE_CONTEXT_MASK 0x00000020L +#define SQ_WAVE_EXCP_FLAG_PRIV__ILLEGAL_INST_MASK 0x00000040L +#define SQ_WAVE_EXCP_FLAG_PRIV__HOST_TRAP_MASK 0x00000080L +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_START_MASK 0x00000100L +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_END_MASK 0x00000200L +#define SQ_WAVE_EXCP_FLAG_PRIV__PERF_SNAPSHOT_MASK 0x00000400L +#define SQ_WAVE_EXCP_FLAG_PRIV__TRAP_AFTER_INST_MASK 0x00000800L +#define SQ_WAVE_EXCP_FLAG_PRIV__XNACK_ERROR_MASK 0x00001000L +#define SQ_WAVE_EXCP_FLAG_PRIV__FIRST_MEMVIOL_SOURCE_MASK 0xC0000000L +//SQ_WAVE_EXCP_FLAG_USER +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INVALID__SHIFT 0x0 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INPUT_DENORM__SHIFT 0x1 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_FLOAT_DIV0__SHIFT 0x2 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_OVERFLOW__SHIFT 0x3 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_UNDERFLOW__SHIFT 0x4 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INEXACT__SHIFT 0x5 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INT_DIV0__SHIFT 0x6 +#define SQ_WAVE_EXCP_FLAG_USER__BUFFER_OOB__SHIFT 0x1e +#define SQ_WAVE_EXCP_FLAG_USER__LOD_CLAMPED__SHIFT 0x1f +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INVALID_MASK 0x00000001L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INPUT_DENORM_MASK 0x00000002L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_FLOAT_DIV0_MASK 0x00000004L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_OVERFLOW_MASK 0x00000008L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_UNDERFLOW_MASK 0x00000010L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INEXACT_MASK 0x00000020L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INT_DIV0_MASK 0x00000040L +#define SQ_WAVE_EXCP_FLAG_USER__BUFFER_OOB_MASK 0x40000000L +#define SQ_WAVE_EXCP_FLAG_USER__LOD_CLAMPED_MASK 0x80000000L +//SQ_WAVE_TRAP_CTRL +#define SQ_WAVE_TRAP_CTRL__ALU_INVALID__SHIFT 0x0 +#define SQ_WAVE_TRAP_CTRL__ALU_INPUT_DENORM__SHIFT 0x1 +#define SQ_WAVE_TRAP_CTRL__ALU_FLOAT_DIV0__SHIFT 0x2 +#define SQ_WAVE_TRAP_CTRL__ALU_OVERFLOW__SHIFT 0x3 +#define SQ_WAVE_TRAP_CTRL__ALU_UNDERFLOW__SHIFT 0x4 +#define SQ_WAVE_TRAP_CTRL__ALU_INEXACT__SHIFT 0x5 +#define SQ_WAVE_TRAP_CTRL__ALU_INT_DIV0__SHIFT 0x6 +#define SQ_WAVE_TRAP_CTRL__ADDR_WATCH__SHIFT 0x7 +#define SQ_WAVE_TRAP_CTRL__WAVE_END__SHIFT 0x8 +#define SQ_WAVE_TRAP_CTRL__TRAP_AFTER_INST__SHIFT 0x9 +#define SQ_WAVE_TRAP_CTRL__ALU_INVALID_MASK 0x00000001L +#define SQ_WAVE_TRAP_CTRL__ALU_INPUT_DENORM_MASK 0x00000002L +#define SQ_WAVE_TRAP_CTRL__ALU_FLOAT_DIV0_MASK 0x00000004L +#define SQ_WAVE_TRAP_CTRL__ALU_OVERFLOW_MASK 0x00000008L +#define SQ_WAVE_TRAP_CTRL__ALU_UNDERFLOW_MASK 0x00000010L +#define SQ_WAVE_TRAP_CTRL__ALU_INEXACT_MASK 0x00000020L +#define SQ_WAVE_TRAP_CTRL__ALU_INT_DIV0_MASK 0x00000040L +#define SQ_WAVE_TRAP_CTRL__ADDR_WATCH_MASK 0x00000080L +#define SQ_WAVE_TRAP_CTRL__WAVE_END_MASK 0x00000100L +#define SQ_WAVE_TRAP_CTRL__TRAP_AFTER_INST_MASK 0x00000200L +//SQ_WAVE_SCRATCH_BASE_LO +#define SQ_WAVE_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define SQ_WAVE_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_SCRATCH_BASE_HI +#define SQ_WAVE_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define SQ_WAVE_SCRATCH_BASE_HI__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_HW_ID1 +#define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa +#define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID1__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL +#define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L +#define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L +#define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L +#define SQ_WAVE_HW_ID1__DP_RATE_MASK 0xE0000000L +//SQ_WAVE_HW_ID2 +#define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL +#define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L +#define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L +#define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L +#define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L +//SQ_WAVE_SCHED_MODE +#define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0 +#define SQ_WAVE_SCHED_MODE__DISABLE_VALU_ARB_STALL__SHIFT 0x2 +#define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L +#define SQ_WAVE_SCHED_MODE__DISABLE_VALU_ARB_STALL_MASK 0x00000004L +//SQ_WAVE_IB_STS2 +#define SQ_WAVE_IB_STS2__KM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS2__CLUSTER_ID__SHIFT 0x6 +#define SQ_WAVE_IB_STS2__ASYNC_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS2__TENSOR_CNT__SHIFT 0x12 +#define SQ_WAVE_IB_STS2__WG_IN_CLUSTER__SHIFT 0x15 +#define SQ_WAVE_IB_STS2__MWAIT__SHIFT 0x19 +#define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x1c +#define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0x1e +#define SQ_WAVE_IB_STS2__TTRACE_EN_SPI__SHIFT 0x1f +#define SQ_WAVE_IB_STS2__KM_CNT_MASK 0x0000001FL +#define SQ_WAVE_IB_STS2__CLUSTER_ID_MASK 0x000003C0L +#define SQ_WAVE_IB_STS2__ASYNC_CNT_MASK 0x0003F000L +#define SQ_WAVE_IB_STS2__TENSOR_CNT_MASK 0x000C0000L +#define SQ_WAVE_IB_STS2__WG_IN_CLUSTER_MASK 0x01E00000L +#define SQ_WAVE_IB_STS2__MWAIT_MASK 0x02000000L +#define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x30000000L +#define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x40000000L +#define SQ_WAVE_IB_STS2__TTRACE_EN_SPI_MASK 0x80000000L +//SQ_WAVE_DVGPR_ALLOC_LO +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT0__SHIFT 0x0 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT1__SHIFT 0x8 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT2__SHIFT 0x10 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT3__SHIFT 0x18 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT0_MASK 0x0000007FL +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT1_MASK 0x00007F00L +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT2_MASK 0x007F0000L +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT3_MASK 0x7F000000L +//SQ_WAVE_DVGPR_ALLOC_HI +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT4__SHIFT 0x0 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT5__SHIFT 0x8 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT6__SHIFT 0x10 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT7__SHIFT 0x18 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT4_MASK 0x0000007FL +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT5_MASK 0x00007F00L +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT6_MASK 0x007F0000L +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT7_MASK 0x7F000000L +//SQ_WAVE_XNACK_STATE_PRIV +#define SQ_WAVE_XNACK_STATE_PRIV__FXPTR__SHIFT 0x0 +#define SQ_WAVE_XNACK_STATE_PRIV__RPTR__SHIFT 0x8 +#define SQ_WAVE_XNACK_STATE_PRIV__REPLAY_W64H__SHIFT 0x10 +#define SQ_WAVE_XNACK_STATE_PRIV__GOT_XNACK__SHIFT 0x11 +#define SQ_WAVE_XNACK_STATE_PRIV__FIRST_REPLAY__SHIFT 0x12 +#define SQ_WAVE_XNACK_STATE_PRIV__FXPTR_MASK 0x0000007FL +#define SQ_WAVE_XNACK_STATE_PRIV__RPTR_MASK 0x00007F00L +#define SQ_WAVE_XNACK_STATE_PRIV__REPLAY_W64H_MASK 0x00010000L +#define SQ_WAVE_XNACK_STATE_PRIV__GOT_XNACK_MASK 0x00020000L +#define SQ_WAVE_XNACK_STATE_PRIV__FIRST_REPLAY_MASK 0x00040000L +//SQ_WAVE_XNACK_MASK +#define SQ_WAVE_XNACK_MASK__MASK__SHIFT 0x0 +#define SQ_WAVE_XNACK_MASK__MASK_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_LO +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_HI +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x01FFFFFFL +//SQ_WAVE_TTMP0 +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP1 +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP2 +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP3 +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP4 +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP5 +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP6 +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP7 +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP8 +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP9 +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP10 +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP11 +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP12 +#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP13 +#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP14 +#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP15 +#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_M0 +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_LO +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_HI +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index 12d451e5475b7..5b17d90664524 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -462,6 +462,8 @@ #define mmSQ_IND_DATA_BASE_IDX 0 #define mmSQ_CMD 0x037b #define mmSQ_CMD_BASE_IDX 0 +#define mmSQ_HOSTTRAP_STATUS 0x0376 +#define mmSQ_HOSTTRAP_STATUS_BASE_IDX 0 #define mmSQ_TIME_HI 0x037c #define mmSQ_TIME_HI_BASE_IDX 0 #define mmSQ_TIME_LO 0x037d diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 2dfa0e5b1aa3e..3e0210c2bf369 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -2616,6 +2616,11 @@ //SQ_CMD_TIMESTAMP #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_HOSTTRAP_STATUS +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L //SQ_IND_INDEX #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 diff --git a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h new file mode 100644 index 0000000000000..fa4e42a3ae9fc --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_offset.h @@ -0,0 +1,44 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _lsdma_7_1_0_OFFSET_HEADER +#define _lsdma_7_1_0_OFFSET_HEADER + +#define regLSDMA_PIO_SRC_ADDR_LO 0x0080 +#define regLSDMA_PIO_SRC_ADDR_LO_BASE_IDX 0 +#define regLSDMA_PIO_SRC_ADDR_HI 0x0081 +#define regLSDMA_PIO_SRC_ADDR_HI_BASE_IDX 0 +#define regLSDMA_PIO_DST_ADDR_LO 0x0082 +#define regLSDMA_PIO_DST_ADDR_LO_BASE_IDX 0 +#define regLSDMA_PIO_DST_ADDR_HI 0x0083 +#define regLSDMA_PIO_DST_ADDR_HI_BASE_IDX 0 +#define regLSDMA_PIO_COMMAND 0x0084 +#define regLSDMA_PIO_COMMAND_BASE_IDX 0 +#define regLSDMA_PIO_CONSTFILL_DATA 0x0085 +#define regLSDMA_PIO_CONSTFILL_DATA_BASE_IDX 0 +#define regLSDMA_PIO_CONTROL 0x0086 +#define regLSDMA_PIO_CONTROL_BASE_IDX 0 + +#define regLSDMA_PIO_STATUS 0x008a +#define regLSDMA_PIO_STATUS_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h new file mode 100644 index 0000000000000..cf83dacf4acf5 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/lsdma/lsdma_7_1_0_sh_mask.h @@ -0,0 +1,105 @@ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _lsdma_7_1_0_SH_MASK_HEADER +#define _lsdma_7_1_0_SH_MASK_HEADER + + +// addressBlock: lsdma0_lsdma0dec +//LSDMA_PIO_STATUS +#define LSDMA_PIO_STATUS__CMD_IN_FIFO__SHIFT 0x0 +#define LSDMA_PIO_STATUS__CMD_PROCESSING__SHIFT 0x3 +#define LSDMA_PIO_STATUS__ERROR_INVALID_ADDR__SHIFT 0xb +#define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT__SHIFT 0xc +#define LSDMA_PIO_STATUS__ERROR_DRAM_ECC__SHIFT 0xd +#define LSDMA_PIO_STATUS__ERROR_SRAM_ECC__SHIFT 0xe +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR__SHIFT 0xf +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR__SHIFT 0x10 +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT__SHIFT 0x11 +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT__SHIFT 0x12 +#define LSDMA_PIO_STATUS__ERROR_REQ_DROP__SHIFT 0x13 +#define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY__SHIFT 0x1c +#define LSDMA_PIO_STATUS__PIO_FIFO_FULL__SHIFT 0x1d +#define LSDMA_PIO_STATUS__PIO_IDLE__SHIFT 0x1f +#define LSDMA_PIO_STATUS__CMD_IN_FIFO_MASK 0x00000007L +#define LSDMA_PIO_STATUS__CMD_PROCESSING_MASK 0x000003F8L +#define LSDMA_PIO_STATUS__ERROR_INVALID_ADDR_MASK 0x00000800L +#define LSDMA_PIO_STATUS__ERROR_ZERO_COUNT_MASK 0x00001000L +#define LSDMA_PIO_STATUS__ERROR_DRAM_ECC_MASK 0x00002000L +#define LSDMA_PIO_STATUS__ERROR_SRAM_ECC_MASK 0x00004000L +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_GEN_ERR_MASK 0x00008000L +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_GEN_ERR_MASK 0x00010000L +#define LSDMA_PIO_STATUS__ERROR_WRRET_NACK_PRT_MASK 0x00020000L +#define LSDMA_PIO_STATUS__ERROR_RDRET_NACK_PRT_MASK 0x00040000L +#define LSDMA_PIO_STATUS__ERROR_REQ_DROP_MASK 0x00080000L +#define LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK 0x10000000L +#define LSDMA_PIO_STATUS__PIO_FIFO_FULL_MASK 0x20000000L +#define LSDMA_PIO_STATUS__PIO_IDLE_MASK 0x80000000L +//LSDMA_PIO_SRC_ADDR_LO +#define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO__SHIFT 0x0 +#define LSDMA_PIO_SRC_ADDR_LO__SRC_ADDR_LO_MASK 0xFFFFFFFFL +//LSDMA_PIO_SRC_ADDR_HI +#define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define LSDMA_PIO_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xFFFFFFFFL +//LSDMA_PIO_DST_ADDR_LO +#define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO__SHIFT 0x0 +#define LSDMA_PIO_DST_ADDR_LO__DST_ADDR_LO_MASK 0xFFFFFFFFL +//LSDMA_PIO_DST_ADDR_HI +#define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define LSDMA_PIO_DST_ADDR_HI__DST_ADDR_HI_MASK 0xFFFFFFFFL +//LSDMA_PIO_CONTROL +#define LSDMA_PIO_CONTROL__VMID__SHIFT 0x0 +#define LSDMA_PIO_CONTROL__DST_GPA__SHIFT 0x4 +#define LSDMA_PIO_CONTROL__DST_SYS__SHIFT 0x5 +#define LSDMA_PIO_CONTROL__DST_GCC__SHIFT 0x6 +#define LSDMA_PIO_CONTROL__DST_SNOOP__SHIFT 0x7 +#define LSDMA_PIO_CONTROL__DST_REUSE_HINT__SHIFT 0x8 +#define LSDMA_PIO_CONTROL__DST_COMP_EN__SHIFT 0xa +#define LSDMA_PIO_CONTROL__SRC_GPA__SHIFT 0x14 +#define LSDMA_PIO_CONTROL__SRC_SYS__SHIFT 0x15 +#define LSDMA_PIO_CONTROL__SRC_SNOOP__SHIFT 0x17 +#define LSDMA_PIO_CONTROL__SRC_REUSE_HINT__SHIFT 0x18 +#define LSDMA_PIO_CONTROL__SRC_COMP_EN__SHIFT 0x1a +#define LSDMA_PIO_CONTROL__VMID_MASK 0x0000000FL +#define LSDMA_PIO_CONTROL__DST_GPA_MASK 0x00000010L +#define LSDMA_PIO_CONTROL__DST_SYS_MASK 0x00000020L +#define LSDMA_PIO_CONTROL__DST_GCC_MASK 0x00000040L +#define LSDMA_PIO_CONTROL__DST_SNOOP_MASK 0x00000080L +#define LSDMA_PIO_CONTROL__DST_REUSE_HINT_MASK 0x00000300L +#define LSDMA_PIO_CONTROL__DST_COMP_EN_MASK 0x00000400L +#define LSDMA_PIO_CONTROL__SRC_GPA_MASK 0x00100000L +#define LSDMA_PIO_CONTROL__SRC_SYS_MASK 0x00200000L +#define LSDMA_PIO_CONTROL__SRC_SNOOP_MASK 0x00800000L +#define LSDMA_PIO_CONTROL__SRC_REUSE_HINT_MASK 0x03000000L +#define LSDMA_PIO_CONTROL__SRC_COMP_EN_MASK 0x04000000L +//LSDMA_PIO_COMMAND +#define LSDMA_PIO_COMMAND__COUNT__SHIFT 0x0 +#define LSDMA_PIO_COMMAND__RAW_WAIT__SHIFT 0x1e +#define LSDMA_PIO_COMMAND__CONSTANT_FILL__SHIFT 0x1f +#define LSDMA_PIO_COMMAND__COUNT_MASK 0x03FFFFFFL +#define LSDMA_PIO_COMMAND__RAW_WAIT_MASK 0x40000000L +#define LSDMA_PIO_COMMAND__CONSTANT_FILL_MASK 0x80000000L +//LSDMA_PIO_CONSTFILL_DATA +#define LSDMA_PIO_CONSTFILL_DATA__DATA__SHIFT 0x0 +#define LSDMA_PIO_CONSTFILL_DATA__DATA_MASK 0xFFFFFFFFL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h new file mode 100644 index 0000000000000..45fdce3feaf56 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_offset.h @@ -0,0 +1,802 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_4_2_0_OFFSET_HEADER +#define _mmhub_4_2_0_OFFSET_HEADER + + + +// addressBlock: mmhub_dagb_dagbdec +// base address: 0x60000 +#define regDAGB0_CNTL_MISC2 0x00a7 +#define regDAGB0_CNTL_MISC2_BASE_IDX 1 +#define regDAGB1_CNTL_MISC2 0x01a7 +#define regDAGB1_CNTL_MISC2_BASE_IDX 1 + + +// addressBlock: mmhub_mm_cane_mmcanedec +// base address: 0x60c20 +#define regMM_CANE_ICG_CTRL 0x0313 +#define regMM_CANE_ICG_CTRL_BASE_IDX 1 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +// base address: 0x66000 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0000 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0001 +#define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 +#define regMMUTCL2_CGTT_CLK_CTRL 0x0002 +#define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 2 +#define regMMMC_SHARED_ACTIVE_FCN_ID 0x0003 +#define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 2 +#define regMMUTCL2_CGTT_BUSY_CTRL 0x0004 +#define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 2 +#define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x0005 +#define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +// base address: 0x66090 +#define regMMVM_L2_CNTL 0x0024 +#define regMMVM_L2_CNTL_BASE_IDX 2 +#define regMMVM_L2_CNTL2 0x0025 +#define regMMVM_L2_CNTL2_BASE_IDX 2 +#define regMMVM_L2_CNTL3 0x0026 +#define regMMVM_L2_CNTL3_BASE_IDX 2 +#define regMMVM_L2_STATUS 0x0027 +#define regMMVM_L2_STATUS_BASE_IDX 2 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0028 +#define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 2 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0029 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 2 +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x002a +#define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_CNTL 0x002b +#define regMMVM_INVALIDATE_CNTL_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32 0x002c +#define regMMVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32 0x002d +#define regMMVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x002e +#define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x002f +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x0030 +#define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32 0x0031 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32 0x0032 +#define regMMVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x0033 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x0034 +#define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x0035 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 2 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0036 +#define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 2 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0038 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 2 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0039 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 2 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x003a +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 2 +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x003b +#define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 2 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x003c +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 2 +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x003d +#define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 2 +#define regMMVM_L2_CNTL4 0x003e +#define regMMVM_L2_CNTL4_BASE_IDX 2 +#define regMMVM_L2_MM_GROUP_RT_CLASSES 0x003f +#define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 2 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x0040 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 2 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x0041 +#define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 2 +#define regMMVM_L2_CACHE_PARITY_CNTL 0x0042 +#define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 2 +#define regMMVM_L2_CGTT_CLK_CTRL 0x0043 +#define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 2 +#define regMMVM_L2_CNTL5 0x0044 +#define regMMVM_L2_CNTL5_BASE_IDX 2 +#define regMMVM_L2_GCR_CNTL 0x0045 +#define regMMVM_L2_GCR_CNTL_BASE_IDX 2 +#define regMMVM_L2_CGTT_BUSY_CTRL 0x0046 +#define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 2 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0047 +#define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 2 +#define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0048 +#define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 2 +#define regMMVM_L2_BANK_SELECT_MASKS 0x0051 +#define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 2 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0052 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 2 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0053 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 2 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0054 +#define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 2 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0055 +#define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 2 +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x0056 +#define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 2 +#define regMMVML2_IH_FAULT_INTERRUPT_CNTL 0x0057 +#define regMMVML2_IH_FAULT_INTERRUPT_CNTL_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +// base address: 0x66210 +#define regMMMC_VM_L2_PERFCOUNTER_LO 0x0084 +#define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER_HI 0x0085 +#define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER_LO 0x0086 +#define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER_HI 0x0087 +#define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmatcl2prdec +// base address: 0x66250 +#define regMM_ATC_L2_PERFCOUNTER_LO 0x0094 +#define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 2 +#define regMM_ATC_L2_PERFCOUNTER_HI 0x0095 +#define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +// base address: 0x66290 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x00a4 +#define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x00a5 +#define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x00a6 +#define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x00a7 +#define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x00a8 +#define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x00a9 +#define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x00aa +#define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x00ab +#define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER8_CFG 0x00ac +#define regMMMC_VM_L2_PERFCOUNTER8_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER9_CFG 0x00ad +#define regMMMC_VM_L2_PERFCOUNTER9_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER10_CFG 0x00ae +#define regMMMC_VM_L2_PERFCOUNTER10_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER11_CFG 0x00af +#define regMMMC_VM_L2_PERFCOUNTER11_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER12_CFG 0x00b0 +#define regMMMC_VM_L2_PERFCOUNTER12_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER13_CFG 0x00b1 +#define regMMMC_VM_L2_PERFCOUNTER13_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER14_CFG 0x00b2 +#define regMMMC_VM_L2_PERFCOUNTER14_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER15_CFG 0x00b3 +#define regMMMC_VM_L2_PERFCOUNTER15_CFG_BASE_IDX 2 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x00b4 +#define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER0_CFG 0x00b5 +#define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER1_CFG 0x00b6 +#define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER2_CFG 0x00b7 +#define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER3_CFG 0x00b8 +#define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 2 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x00b9 +#define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmatcl2pldec +// base address: 0x662f0 +#define regMM_ATC_L2_PERFCOUNTER0_CFG 0x00bc +#define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 2 +#define regMM_ATC_L2_PERFCOUNTER1_CFG 0x00bd +#define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 2 +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x00cc +#define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +// base address: 0x66400 +#define regMMMC_VM_FB_LOCATION_BASE_LO32 0x0100 +#define regMMMC_VM_FB_LOCATION_BASE_LO32_BASE_IDX 2 +#define regMMMC_VM_FB_LOCATION_BASE_HI32 0x0101 +#define regMMMC_VM_FB_LOCATION_BASE_HI32_BASE_IDX 2 +#define regMMMC_VM_FB_LOCATION_TOP_LO32 0x0102 +#define regMMMC_VM_FB_LOCATION_TOP_LO32_BASE_IDX 2 +#define regMMMC_VM_FB_LOCATION_TOP_HI32 0x0103 +#define regMMMC_VM_FB_LOCATION_TOP_HI32_BASE_IDX 2 +#define regMMMC_VM_AGP_TOP_LO32 0x0104 +#define regMMMC_VM_AGP_TOP_LO32_BASE_IDX 2 +#define regMMMC_VM_AGP_TOP_HI32 0x0105 +#define regMMMC_VM_AGP_TOP_HI32_BASE_IDX 2 +#define regMMMC_VM_AGP_BOT_LO32 0x0106 +#define regMMMC_VM_AGP_BOT_LO32_BASE_IDX 2 +#define regMMMC_VM_AGP_BOT_HI32 0x0107 +#define regMMMC_VM_AGP_BOT_HI32_BASE_IDX 2 +#define regMMMC_VM_AGP_BASE_LO32 0x0108 +#define regMMMC_VM_AGP_BASE_LO32_BASE_IDX 2 +#define regMMMC_VM_AGP_BASE_HI32 0x0109 +#define regMMMC_VM_AGP_BASE_HI32_BASE_IDX 2 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 0x010a +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32_BASE_IDX 2 +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 0x010b +#define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32_BASE_IDX 2 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 0x010c +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32_BASE_IDX 2 +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 0x010d +#define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32_BASE_IDX 2 +#define regMMMC_VM_MX_L1_TLB_CNTL 0x010e +#define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +// base address: 0x66440 +#define regMMVM_CONTEXT0_CNTL 0x0110 +#define regMMVM_CONTEXT0_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT1_CNTL 0x0111 +#define regMMVM_CONTEXT1_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT2_CNTL 0x0112 +#define regMMVM_CONTEXT2_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT3_CNTL 0x0113 +#define regMMVM_CONTEXT3_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT4_CNTL 0x0114 +#define regMMVM_CONTEXT4_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT5_CNTL 0x0115 +#define regMMVM_CONTEXT5_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT6_CNTL 0x0116 +#define regMMVM_CONTEXT6_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT7_CNTL 0x0117 +#define regMMVM_CONTEXT7_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT8_CNTL 0x0118 +#define regMMVM_CONTEXT8_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT9_CNTL 0x0119 +#define regMMVM_CONTEXT9_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT10_CNTL 0x011a +#define regMMVM_CONTEXT10_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT11_CNTL 0x011b +#define regMMVM_CONTEXT11_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT12_CNTL 0x011c +#define regMMVM_CONTEXT12_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT13_CNTL 0x011d +#define regMMVM_CONTEXT13_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT14_CNTL 0x011e +#define regMMVM_CONTEXT14_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXT15_CNTL 0x011f +#define regMMVM_CONTEXT15_CNTL_BASE_IDX 2 +#define regMMVM_CONTEXTS_DISABLE 0x0120 +#define regMMVM_CONTEXTS_DISABLE_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG0_SEM 0x0121 +#define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG1_SEM 0x0122 +#define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG2_SEM 0x0123 +#define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG3_SEM 0x0124 +#define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG4_SEM 0x0125 +#define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG5_SEM 0x0126 +#define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG6_SEM 0x0127 +#define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG7_SEM 0x0128 +#define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG8_SEM 0x0129 +#define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG9_SEM 0x012a +#define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG10_SEM 0x012b +#define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG11_SEM 0x012c +#define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG12_SEM 0x012d +#define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG13_SEM 0x012e +#define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG14_SEM 0x012f +#define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG15_SEM 0x0130 +#define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG16_SEM 0x0131 +#define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG17_SEM 0x0132 +#define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG0_REQ 0x0133 +#define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG1_REQ 0x0134 +#define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG2_REQ 0x0135 +#define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG3_REQ 0x0136 +#define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG4_REQ 0x0137 +#define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG5_REQ 0x0138 +#define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG6_REQ 0x0139 +#define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG7_REQ 0x013a +#define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG8_REQ 0x013b +#define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG9_REQ 0x013c +#define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG10_REQ 0x013d +#define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG11_REQ 0x013e +#define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG12_REQ 0x013f +#define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG13_REQ 0x0140 +#define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG14_REQ 0x0141 +#define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG15_REQ 0x0142 +#define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG16_REQ 0x0143 +#define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG17_REQ 0x0144 +#define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG0_ACK 0x0145 +#define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG1_ACK 0x0146 +#define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG2_ACK 0x0147 +#define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG3_ACK 0x0148 +#define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG4_ACK 0x0149 +#define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG5_ACK 0x014a +#define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG6_ACK 0x014b +#define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG7_ACK 0x014c +#define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG8_ACK 0x014d +#define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG9_ACK 0x014e +#define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG10_ACK 0x014f +#define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG11_ACK 0x0150 +#define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG12_ACK 0x0151 +#define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG13_ACK 0x0152 +#define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG14_ACK 0x0153 +#define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG15_ACK 0x0154 +#define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG16_ACK 0x0155 +#define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG17_ACK 0x0156 +#define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0157 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0158 +#define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0159 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x015a +#define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x015b +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x015c +#define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x015d +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x015e +#define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x015f +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0160 +#define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0161 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0162 +#define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0163 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0164 +#define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0165 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0166 +#define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0167 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0168 +#define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0169 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x016a +#define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x016b +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x016c +#define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x016d +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x016e +#define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x016f +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0170 +#define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0171 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0172 +#define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0173 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0174 +#define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0175 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0176 +#define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0177 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0178 +#define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0179 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 2 +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x017a +#define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x017b +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x017c +#define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x017d +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x017e +#define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x017f +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0180 +#define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0181 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0182 +#define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0183 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0184 +#define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0185 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0186 +#define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0187 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0188 +#define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0189 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x018a +#define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x018b +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x018c +#define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x018d +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x018e +#define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x018f +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0190 +#define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0191 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0192 +#define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0193 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0194 +#define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0195 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0196 +#define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0197 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0198 +#define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0199 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x019a +#define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x019b +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x019c +#define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x019d +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x019e +#define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x019f +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x01a0 +#define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x01a1 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x01a2 +#define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x01a3 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x01a4 +#define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x01a5 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x01a6 +#define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x01a7 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x01a8 +#define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x01a9 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x01aa +#define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x01ab +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x01ac +#define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x01ad +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x01ae +#define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x01af +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x01b0 +#define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x01b1 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x01b2 +#define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x01b3 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x01b4 +#define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x01b5 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x01b6 +#define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x01b7 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x01b8 +#define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x01b9 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x01ba +#define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x01bb +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x01bc +#define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x01bd +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x01be +#define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x01bf +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x01c0 +#define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x01c1 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x01c2 +#define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x01c3 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x01c4 +#define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x01c5 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x01c6 +#define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x01c7 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x01c8 +#define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x01c9 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x01ca +#define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x01cb +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x01cc +#define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x01cd +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x01ce +#define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x01cf +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x01d0 +#define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x01d1 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x01d2 +#define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x01d3 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x01d4 +#define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x01d5 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x01d6 +#define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x01d7 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x01d8 +#define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x01d9 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2 +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x01da +#define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2 +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01db +#define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01dc +#define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01dd +#define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01de +#define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01df +#define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e0 +#define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e1 +#define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e2 +#define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e3 +#define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e4 +#define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e5 +#define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e6 +#define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e7 +#define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e8 +#define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01e9 +#define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01ea +#define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x01eb +#define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvfdec +// base address: 0x667c0 +#define regMMMC_VM_PCIE_ATOMIC_SUPPORTED 0x01f0 +#define regMMMC_VM_PCIE_ATOMIC_SUPPORTED_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +// base address: 0x667e0 +#define regMMVM_PCIE_ATS_CNTL 0x01f8 +#define regMMVM_PCIE_ATS_CNTL_BASE_IDX 2 +#define regMMMC_VM_NB_MMIOBASE 0x01f9 +#define regMMMC_VM_NB_MMIOBASE_BASE_IDX 2 +#define regMMMC_VM_NB_MMIOLIMIT 0x01fa +#define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 2 +#define regMMMC_VM_NB_PCI_CTRL 0x01fb +#define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 2 +#define regMMMC_VM_NB_PCI_ARB 0x01fc +#define regMMMC_VM_NB_PCI_ARB_BASE_IDX 2 +#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x01fd +#define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 2 +#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x01fe +#define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 2 +#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x01ff +#define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 2 +#define regMMMC_VM_STEERING 0x0200 +#define regMMMC_VM_STEERING_BASE_IDX 2 +#define regMMMC_SHARED_VIRT_RESET_REQ 0x0201 +#define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 2 +#define regMMMC_VM_XGMI_LFB_CNTL 0x0202 +#define regMMMC_VM_XGMI_LFB_CNTL_BASE_IDX 2 +#define regMMMC_VM_XGMI_LFB_SIZE 0x0203 +#define regMMMC_VM_XGMI_LFB_SIZE_BASE_IDX 2 +#define regMMMC_VM_HOST_MAPPING 0x0204 +#define regMMMC_VM_HOST_MAPPING_BASE_IDX 2 +#define regMMMC_VM_XGMI_GPUIOV_ENABLE 0x0205 +#define regMMMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 2 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0206 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 2 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0207 +#define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 2 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x0208 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 2 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x0209 +#define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 2 +#define regMMMC_VM_LPDDR_ADDRESS_START 0x020a +#define regMMMC_VM_LPDDR_ADDRESS_START_BASE_IDX 2 +#define regMMMC_VM_LPDDR_ADDRESS_END 0x020b +#define regMMMC_VM_LPDDR_ADDRESS_END_BASE_IDX 2 +#define regMMMC_VM_APT_CNTL 0x020c +#define regMMMC_VM_APT_CNTL_BASE_IDX 2 +#define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x020d +#define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmatcl2dec +// base address: 0x669d0 +#define regMM_ATC_L2_CNTL 0x0274 +#define regMM_ATC_L2_CNTL_BASE_IDX 2 +#define regMM_ATC_L2_CNTL2 0x0275 +#define regMM_ATC_L2_CNTL2_BASE_IDX 2 +#define regMM_ATC_L2_CACHE_DATA0 0x0278 +#define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 2 +#define regMM_ATC_L2_CACHE_DATA1 0x0279 +#define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 2 +#define regMM_ATC_L2_CACHE_DATA2 0x027a +#define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 2 +#define regMM_ATC_L2_CNTL3 0x027d +#define regMM_ATC_L2_CNTL3_BASE_IDX 2 +#define regMM_ATC_L2_CNTL4 0x027e +#define regMM_ATC_L2_CNTL4_BASE_IDX 2 +#define regMM_ATC_L2_CNTL5 0x027f +#define regMM_ATC_L2_CNTL5_BASE_IDX 2 +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x0280 +#define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 2 +#define regMM_ATC_L2_STATUS 0x0281 +#define regMM_ATC_L2_STATUS_BASE_IDX 2 +#define regMM_ATC_L2_MISC_CG 0x0282 +#define regMM_ATC_L2_MISC_CG_BASE_IDX 2 +#define regMM_ATC_L2_CGTT_CLK_CTRL 0x0283 +#define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 2 +#define regMM_ATC_L2_SDPPORT_CTRL 0x0287 +#define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +// base address: 0x66b40 +#define regMMVM_IOMMU_CONTROL_REGISTER 0x02d4 +#define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 2 +#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x02d5 +#define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 2 + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpspdec +// base address: 0x66b90 +#define regMMMC_VM_FB_OFFSET 0x02ec +#define regMMMC_VM_FB_OFFSET_BASE_IDX 2 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_sh_mask.h new file mode 100644 index 0000000000000..8d8cb50a3244e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_4_2_0_sh_mask.h @@ -0,0 +1,3013 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mmhub_4_2_0_SH_MASK_HEADER +#define _mmhub_4_2_0_SH_MASK_HEADER + + +// addressBlock: mmhub_dagb_dagbdec +//DAGB0_CNTL_MISC2 +#define DAGB0_CNTL_MISC2__DAGB_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0x1 +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x2 +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0x3 +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0x4 +#define DAGB0_CNTL_MISC2__DISABLE_MCA_INTR_REQ_FGCG__SHIFT 0x5 +#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000002L +#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000004L +#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000008L +#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000010L +//DAGB1_CNTL_MISC2 +#define DAGB1_CNTL_MISC2__DAGB_BUSY_OVERRIDE__SHIFT 0x0 +#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0x1 +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0x2 +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT 0x3 +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT 0x4 +#define DAGB1_CNTL_MISC2__DISABLE_MCA_INTR_REQ_FGCG__SHIFT 0x5 +#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000002L +#define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000004L +#define DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK 0x00000008L +#define DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK 0x00000010L + + +// addressBlock: mmhub_mm_cane_mmcanedec +//MM_CANE_ICG_CTRL +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_IREQ0__SHIFT 0x0 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_ATRET__SHIFT 0x1 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_OREQ__SHIFT 0x2 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_SDPM_RETURN__SHIFT 0x4 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_IREQ0_MASK 0x00000001L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_ATRET_MASK 0x00000002L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_OREQ_MASK 0x00000004L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_SDPM_RETURN_MASK 0x00000010L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x000000FFL +//MMUTCL2_CGTT_CLK_CTRL +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define MMUTCL2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define MMUTCL2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMMC_SHARED_ACTIVE_FCN_ID +#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//MMUTCL2_CGTT_BUSY_CTRL +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMUTCL2_GROUP_RET_FAULT_STATUS +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmvml2pfdec +//MMVM_L2_CNTL +#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//MMVM_L2_CNTL2 +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//MMVM_L2_CNTL3 +#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define MMVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//MMVM_L2_STATUS +#define MMVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define MMVM_L2_STATUS__FOUND_PDE3_CACHE_PARITY_ERRORS__SHIFT 0x16 +#define MMVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +//MMVM_DUMMY_PAGE_FAULT_CNTL +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI13__SHIFT 0x0 +#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI13_MASK 0x00001FFFL +//MMVM_INVALIDATE_CNTL +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//MMVM_L2_PROTECTION_FAULT_CNTL_LO32 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xe +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1e +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1f +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x3FFFC000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x40000000L +#define MMVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT_MASK 0x80000000L +//MMVM_L2_PROTECTION_FAULT_CNTL_HI32 +#define MMVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT_MASK 0x00000001L +//MMVM_L2_PROTECTION_FAULT_CNTL2 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//MMVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_STATUS_LO32 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS__SHIFT 0x5 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR__SHIFT 0xa +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__CID__SHIFT 0xb +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__RW__SHIFT 0x14 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC__SHIFT 0x15 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID__SHIFT 0x16 +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VF__SHIFT 0x1a +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID__SHIFT 0x1b +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR_MASK 0x0000001EL +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS_MASK 0x000003E0L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR_MASK 0x00000400L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__CID_MASK 0x000FF800L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__RW_MASK 0x00100000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC_MASK 0x00200000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID_MASK 0x03C00000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VF_MASK 0x04000000L +#define MMVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID_MASK 0xF8000000L +//MMVM_L2_PROTECTION_FAULT_STATUS_HI32 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__UCE__SHIFT 0x1 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__FED__SHIFT 0x2 +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT_MASK 0x00000001L +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__UCE_MASK 0x00000002L +#define MMVM_L2_PROTECTION_FAULT_STATUS_HI32__FED_MASK 0x00000004L +//MMVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI13__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI13_MASK 0x00001FFFL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI8__SHIFT 0x0 +#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI8_MASK 0x000000FFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI8__SHIFT 0x0 +#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI8_MASK 0x000000FFL +//MMVM_L2_CNTL4 +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//MMVM_L2_MM_GROUP_RT_CLASSES +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_BANK_SELECT_RESERVED_CID2 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//MMVM_L2_CACHE_PARITY_CNTL +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//MMVM_L2_CGTT_CLK_CTRL +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define MMVM_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define MMVM_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MMVM_L2_CNTL5 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT 0x10 +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x11 +#define MMVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF__SHIFT 0x12 +#define MMVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ__SHIFT 0x13 +#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK 0x00010000L +#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00020000L +#define MMVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF_MASK 0x00040000L +#define MMVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ_MASK 0x00080000L +//MMVM_L2_GCR_CNTL +#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//MMVM_L2_CGTT_BUSY_CTRL +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//MMVM_L2_PTE_CACHE_DUMP_CNTL +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//MMVM_L2_PTE_CACHE_DUMP_READ +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//MMVM_L2_BANK_SELECT_MASKS +#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L +//MMVML2_IH_FAULT_INTERRUPT_CNTL +#define MMVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_PF_POISON_INTERRUPT__SHIFT 0x0 +#define MMVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_VF_POISON_INTERRUPT__SHIFT 0x1 +#define MMVML2_IH_FAULT_INTERRUPT_CNTL__POISON_INTERRUPT_TO_PF__SHIFT 0x2 +#define MMVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_PF_POISON_INTERRUPT_MASK 0x00000001L +#define MMVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_VF_POISON_INTERRUPT_MASK 0x00000002L +#define MMVML2_IH_FAULT_INTERRUPT_CNTL__POISON_INTERRUPT_TO_PF_MASK 0x00000004L + + +// addressBlock: mmhub_mmutcl2_mmvml2prdec +//MMMC_VM_L2_PERFCOUNTER_LO +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMMC_VM_L2_PERFCOUNTER_HI +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//MMUTCL2_PERFCOUNTER_LO +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MMUTCL2_PERFCOUNTER_HI +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2prdec +//MM_ATC_L2_PERFCOUNTER_LO +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//MM_ATC_L2_PERFCOUNTER_HI +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: mmhub_mmutcl2_mmvml2pldec +//MMMC_VM_L2_PERFCOUNTER0_CFG +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER1_CFG +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER2_CFG +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER3_CFG +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER4_CFG +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER5_CFG +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER6_CFG +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER7_CFG +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER8_CFG +#define MMMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER9_CFG +#define MMMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER10_CFG +#define MMMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER11_CFG +#define MMMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER12_CFG +#define MMMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER13_CFG +#define MMMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER14_CFG +#define MMMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER15_CFG +#define MMMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define MMMC_VM_L2_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define MMMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define MMMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define MMMC_VM_L2_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define MMMC_VM_L2_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMUTCL2_PERFCOUNTER0_CFG +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER1_CFG +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER2_CFG +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER3_CFG +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//MMUTCL2_PERFCOUNTER_RSLT_CNTL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmatcl2pldec +//MM_ATC_L2_PERFCOUNTER0_CFG +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER1_CFG +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec +//MMMC_VM_FB_LOCATION_BASE_LO32 +#define MMMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_FB_LOCATION_BASE_HI32 +#define MMMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK 0x00000001L +//MMMC_VM_FB_LOCATION_TOP_LO32 +#define MMMC_VM_FB_LOCATION_TOP_LO32__FB_TOP_LO32__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_TOP_LO32__FB_TOP_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_FB_LOCATION_TOP_HI32 +#define MMMC_VM_FB_LOCATION_TOP_HI32__FB_TOP_HI1__SHIFT 0x0 +#define MMMC_VM_FB_LOCATION_TOP_HI32__FB_TOP_HI1_MASK 0x00000001L +//MMMC_VM_AGP_TOP_LO32 +#define MMMC_VM_AGP_TOP_LO32__AGP_TOP_LO32__SHIFT 0x0 +#define MMMC_VM_AGP_TOP_LO32__AGP_TOP_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_AGP_TOP_HI32 +#define MMMC_VM_AGP_TOP_HI32__AGP_TOP_HI1__SHIFT 0x0 +#define MMMC_VM_AGP_TOP_HI32__AGP_TOP_HI1_MASK 0x00000001L +//MMMC_VM_AGP_BOT_LO32 +#define MMMC_VM_AGP_BOT_LO32__AGP_BOT_LO32__SHIFT 0x0 +#define MMMC_VM_AGP_BOT_LO32__AGP_BOT_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_AGP_BOT_HI32 +#define MMMC_VM_AGP_BOT_HI32__AGP_BOT_HI1__SHIFT 0x0 +#define MMMC_VM_AGP_BOT_HI32__AGP_BOT_HI1_MASK 0x00000001L +//MMMC_VM_AGP_BASE_LO32 +#define MMMC_VM_AGP_BASE_LO32__AGP_BASE_LO32__SHIFT 0x0 +#define MMMC_VM_AGP_BASE_LO32__AGP_BASE_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_AGP_BASE_HI32 +#define MMMC_VM_AGP_BASE_HI32__AGP_BASE_HI1__SHIFT 0x0 +#define MMMC_VM_AGP_BASE_HI32__AGP_BASE_HI1_MASK 0x00000001L +//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32__LOGICAL_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32__LOGICAL_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32__LOGICAL_ADDR_HI7__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32__LOGICAL_ADDR_HI7_MASK 0x0000007FL +//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32__LOGICAL_ADDR_LO32__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32__LOGICAL_ADDR_LO32_MASK 0xFFFFFFFFL +//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32__LOGICAL_ADDR_HI7__SHIFT 0x0 +#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32__LOGICAL_ADDR_HI7_MASK 0x0000007FL +//MMMC_VM_MX_L1_TLB_CNTL +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L + + +// addressBlock: mmhub_mmutcl2_mmvml2vcdec +//MMVM_CONTEXT0_CNTL +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT1_CNTL +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT2_CNTL +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT3_CNTL +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT4_CNTL +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT5_CNTL +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT6_CNTL +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT7_CNTL +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT8_CNTL +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT9_CNTL +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT10_CNTL +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT11_CNTL +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT12_CNTL +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT13_CNTL +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT14_CNTL +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXT15_CNTL +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x18 +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x19 +#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x01000000L +#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x02000000L +//MMVM_CONTEXTS_DISABLE +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//MMVM_INVALIDATE_ENG0_SEM +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG1_SEM +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG2_SEM +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG3_SEM +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG4_SEM +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG5_SEM +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG6_SEM +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG7_SEM +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG8_SEM +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG9_SEM +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG10_SEM +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG11_SEM +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG12_SEM +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG13_SEM +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG14_SEM +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG15_SEM +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG16_SEM +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG17_SEM +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//MMVM_INVALIDATE_ENG0_REQ +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG1_REQ +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG2_REQ +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG3_REQ +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG4_REQ +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG5_REQ +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG6_REQ +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG7_REQ +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG8_REQ +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG9_REQ +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG10_REQ +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG11_REQ +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG12_REQ +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG13_REQ +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG14_REQ +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG15_REQ +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG16_REQ +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG17_REQ +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//MMVM_INVALIDATE_ENG0_ACK +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG1_ACK +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG2_ACK +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG3_ACK +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG4_ACK +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG5_ACK +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG6_ACK +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG7_ACK +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG8_ACK +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG9_ACK +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG10_ACK +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG11_ACK +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG12_ACK +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG13_ACK +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG14_ACK +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG15_ACK +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG16_ACK +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG17_ACK +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedvfdec +//MMMC_VM_PCIE_ATOMIC_SUPPORTED +#define MMMC_VM_PCIE_ATOMIC_SUPPORTED__PCIE_ATOMIC_SUPPORTED__SHIFT 0x0 +#define MMMC_VM_PCIE_ATOMIC_SUPPORTED__PCIE_ATOMIC_SUPPORTED_MASK 0x00000001L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec +//MMVM_PCIE_ATS_CNTL +#define MMVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define MMVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//MMMC_VM_NB_MMIOBASE +#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//MMMC_VM_NB_MMIOLIMIT +#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//MMMC_VM_NB_PCI_CTRL +#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//MMMC_VM_NB_PCI_ARB +#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//MMMC_VM_NB_TOP_OF_DRAM_SLOT1 +#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//MMMC_VM_NB_LOWER_TOP_OF_DRAM2 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//MMMC_VM_NB_UPPER_TOP_OF_DRAM2 +#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000FFFFFL +//MMMC_VM_STEERING +#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//MMMC_SHARED_VIRT_RESET_REQ +#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x8 +#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x000000FFL +#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x00000100L +//MMMC_VM_XGMI_LFB_CNTL +#define MMMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define MMMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define MMMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define MMMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//MMMC_VM_XGMI_LFB_SIZE +#define MMMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define MMMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//MMMC_VM_HOST_MAPPING +#define MMMC_VM_HOST_MAPPING__MODE__SHIFT 0x0 +#define MMMC_VM_HOST_MAPPING__MODE_MASK 0x00000001L +//MMMC_VM_XGMI_GPUIOV_ENABLE +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define MMMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//MMMC_VM_LPDDR_ADDRESS_START +#define MMMC_VM_LPDDR_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LPDDR_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//MMMC_VM_LPDDR_ADDRESS_END +#define MMMC_VM_LPDDR_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define MMMC_VM_LPDDR_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//MMMC_VM_APT_CNTL +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define MMMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL__SHIFT 0x8 +#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +#define MMMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL_MASK 0x00000300L +//MMUTCL2_HARVEST_BYPASS_GROUPS +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: mmhub_mmutcl2_mmatcl2dec +//MM_ATC_L2_CNTL +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x2 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x4 +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x5 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x6 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0x8 +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xa +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xb +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0xc +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0xf +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x11 +#define MM_ATC_L2_CNTL__CLI_GVA_REQ_FRAG_SIZE__SHIFT 0x17 +#define MM_ATC_L2_CNTL__FORCE_8T_CAP_ON_AT_RETURN__SHIFT 0x1d +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x0000000CL +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000010L +#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000020L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x000000C0L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00000300L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L +#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L +#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00007000L +#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00018000L +#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x007E0000L +//MM_ATC_L2_CNTL2 +#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//MM_ATC_L2_CACHE_DATA0 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL +//MM_ATC_L2_CACHE_DATA1 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//MM_ATC_L2_CACHE_DATA2 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//MM_ATC_L2_CNTL3 +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xc +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0xf +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x15 +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x18 +#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00007000L +#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x001F8000L +#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00E00000L +#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x01000000L +//MM_ATC_L2_CNTL4 +#define MM_ATC_L2_CNTL4__CANE_CLKEN_OVERRIDE__SHIFT 0x0 +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x1 +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0x7 +#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000007EL +#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x00001F80L +//MM_ATC_L2_CNTL5 +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa +#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL +#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L +//MM_ATC_L2_MM_GROUP_RT_CLASSES +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 +#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL +//MM_ATC_L2_STATUS +#define MM_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define MM_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//MM_ATC_L2_MISC_CG +#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define MM_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define MM_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//MM_ATC_L2_CGTT_CLK_CTRL +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x5 +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT 0xd +#define MM_ATC_L2_CGTT_CLK_CTRL__MIN_MGLS__SHIFT 0x1a +#define MM_ATC_L2_CGTT_CLK_CTRL__CGLS_DISABLE__SHIFT 0x1d +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT 0x1e +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT 0x1f +#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000001FL +#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00001FE0L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK 0x03FFE000L +#define MM_ATC_L2_CGTT_CLK_CTRL__MIN_MGLS_MASK 0x1C000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__CGLS_DISABLE_MASK 0x20000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK 0x40000000L +#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK 0x80000000L +//MM_ATC_L2_SDPPORT_CTRL +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L +#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L + + +// addressBlock: mmhub_mmutcl2_mmvml2pspdec +//MMVM_IOMMU_CONTROL_REGISTER +#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L + + +// addressBlock: mmhub_mmutcl2_mmvmsharedpspdec +//MMMC_VM_FB_OFFSET +#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0FFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h new file mode 100644 index 0000000000000..fe97943b9b977 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_15_0_0_OFFSET_HEADER +#define _mp_15_0_0_OFFSET_HEADER + + + +// addressBlock: mp_SmuMpASP_SmnDec +// base address: 0x0 +#define regMPASP_SMN_C2PMSG_60 0x007c +#define regMPASP_SMN_C2PMSG_60_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_61 0x007d +#define regMPASP_SMN_C2PMSG_61_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_62 0x007e +#define regMPASP_SMN_C2PMSG_62_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_63 0x007f +#define regMPASP_SMN_C2PMSG_63_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_64 0x0080 +#define regMPASP_SMN_C2PMSG_64_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_65 0x0081 +#define regMPASP_SMN_C2PMSG_65_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_66 0x0082 +#define regMPASP_SMN_C2PMSG_66_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_67 0x0083 +#define regMPASP_SMN_C2PMSG_67_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_68 0x0084 +#define regMPASP_SMN_C2PMSG_68_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_69 0x0085 +#define regMPASP_SMN_C2PMSG_69_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_70 0x0086 +#define regMPASP_SMN_C2PMSG_70_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_71 0x0087 +#define regMPASP_SMN_C2PMSG_71_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_72 0x0088 +#define regMPASP_SMN_C2PMSG_72_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_73 0x0089 +#define regMPASP_SMN_C2PMSG_73_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_74 0x008a +#define regMPASP_SMN_C2PMSG_74_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_75 0x008b +#define regMPASP_SMN_C2PMSG_75_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_76 0x008c +#define regMPASP_SMN_C2PMSG_76_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_77 0x008d +#define regMPASP_SMN_C2PMSG_77_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_78 0x008e +#define regMPASP_SMN_C2PMSG_78_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_79 0x008f +#define regMPASP_SMN_C2PMSG_79_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_100 0x00a4 +#define regMPASP_SMN_C2PMSG_100_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_101 0x00a5 +#define regMPASP_SMN_C2PMSG_101_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_102 0x00a6 +#define regMPASP_SMN_C2PMSG_102_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_103 0x00a7 +#define regMPASP_SMN_C2PMSG_103_BASE_IDX 0 +#define regMPASP_SMN_C2PMSG_109 0x00ad +#define regMPASP_SMN_C2PMSG_109_BASE_IDX 0 +#define regMPASP_SMN_IH_CREDIT 0x0140 +#define regMPASP_SMN_IH_CREDIT_BASE_IDX 0 +#define regMPASP_SMN_IH_SW_INT 0x0141 +#define regMPASP_SMN_IH_SW_INT_BASE_IDX 0 +#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142 +#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0 + +// addressBlock: mp_SmuMpASPPub_PcruDec +// base address: 0x3800000 +#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280 +#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281 +#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282 +#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283 +#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284 +#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285 +#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286 +#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3 +#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287 +#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3 + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define regMP1_SMN_C2PMSG_0 0x0040 +#define regMP1_SMN_C2PMSG_0_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_1 0x0041 +#define regMP1_SMN_C2PMSG_1_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_2 0x0042 +#define regMP1_SMN_C2PMSG_2_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_3 0x0043 +#define regMP1_SMN_C2PMSG_3_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_4 0x0044 +#define regMP1_SMN_C2PMSG_4_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_5 0x0045 +#define regMP1_SMN_C2PMSG_5_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_6 0x0046 +#define regMP1_SMN_C2PMSG_6_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_7 0x0047 +#define regMP1_SMN_C2PMSG_7_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_8 0x0048 +#define regMP1_SMN_C2PMSG_8_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_9 0x0049 +#define regMP1_SMN_C2PMSG_9_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_10 0x004a +#define regMP1_SMN_C2PMSG_10_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_11 0x004b +#define regMP1_SMN_C2PMSG_11_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_12 0x004c +#define regMP1_SMN_C2PMSG_12_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_13 0x004d +#define regMP1_SMN_C2PMSG_13_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_14 0x004e +#define regMP1_SMN_C2PMSG_14_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_15 0x004f +#define regMP1_SMN_C2PMSG_15_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_16 0x0050 +#define regMP1_SMN_C2PMSG_16_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_17 0x0051 +#define regMP1_SMN_C2PMSG_17_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_18 0x0052 +#define regMP1_SMN_C2PMSG_18_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_19 0x0053 +#define regMP1_SMN_C2PMSG_19_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_20 0x0054 +#define regMP1_SMN_C2PMSG_20_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_21 0x0055 +#define regMP1_SMN_C2PMSG_21_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_22 0x0056 +#define regMP1_SMN_C2PMSG_22_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_23 0x0057 +#define regMP1_SMN_C2PMSG_23_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_24 0x0058 +#define regMP1_SMN_C2PMSG_24_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_25 0x0059 +#define regMP1_SMN_C2PMSG_25_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_26 0x005a +#define regMP1_SMN_C2PMSG_26_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_27 0x005b +#define regMP1_SMN_C2PMSG_27_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_28 0x005c +#define regMP1_SMN_C2PMSG_28_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_29 0x005d +#define regMP1_SMN_C2PMSG_29_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_30 0x005e +#define regMP1_SMN_C2PMSG_30_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_31 0x005f +#define regMP1_SMN_C2PMSG_31_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_32 0x0060 +#define regMP1_SMN_C2PMSG_32_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_33 0x0061 +#define regMP1_SMN_C2PMSG_33_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_34 0x0062 +#define regMP1_SMN_C2PMSG_34_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_35 0x0063 +#define regMP1_SMN_C2PMSG_35_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_36 0x0064 +#define regMP1_SMN_C2PMSG_36_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_37 0x0065 +#define regMP1_SMN_C2PMSG_37_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_38 0x0066 +#define regMP1_SMN_C2PMSG_38_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_39 0x0067 +#define regMP1_SMN_C2PMSG_39_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_40 0x0068 +#define regMP1_SMN_C2PMSG_40_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_41 0x0069 +#define regMP1_SMN_C2PMSG_41_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_42 0x006a +#define regMP1_SMN_C2PMSG_42_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_43 0x006b +#define regMP1_SMN_C2PMSG_43_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_44 0x006c +#define regMP1_SMN_C2PMSG_44_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_45 0x006d +#define regMP1_SMN_C2PMSG_45_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_46 0x006e +#define regMP1_SMN_C2PMSG_46_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_47 0x006f +#define regMP1_SMN_C2PMSG_47_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_48 0x0070 +#define regMP1_SMN_C2PMSG_48_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_49 0x0071 +#define regMP1_SMN_C2PMSG_49_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_50 0x0072 +#define regMP1_SMN_C2PMSG_50_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_51 0x0073 +#define regMP1_SMN_C2PMSG_51_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_52 0x0074 +#define regMP1_SMN_C2PMSG_52_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_53 0x0075 +#define regMP1_SMN_C2PMSG_53_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_54 0x0076 +#define regMP1_SMN_C2PMSG_54_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_55 0x0077 +#define regMP1_SMN_C2PMSG_55_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_56 0x0078 +#define regMP1_SMN_C2PMSG_56_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_57 0x0079 +#define regMP1_SMN_C2PMSG_57_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_58 0x007a +#define regMP1_SMN_C2PMSG_58_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_59 0x007b +#define regMP1_SMN_C2PMSG_59_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_60 0x007c +#define regMP1_SMN_C2PMSG_60_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_61 0x007d +#define regMP1_SMN_C2PMSG_61_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_62 0x007e +#define regMP1_SMN_C2PMSG_62_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_63 0x007f +#define regMP1_SMN_C2PMSG_63_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_64 0x0080 +#define regMP1_SMN_C2PMSG_64_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_65 0x0081 +#define regMP1_SMN_C2PMSG_65_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_66 0x0082 +#define regMP1_SMN_C2PMSG_66_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_67 0x0083 +#define regMP1_SMN_C2PMSG_67_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_68 0x0084 +#define regMP1_SMN_C2PMSG_68_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_69 0x0085 +#define regMP1_SMN_C2PMSG_69_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_70 0x0086 +#define regMP1_SMN_C2PMSG_70_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_71 0x0087 +#define regMP1_SMN_C2PMSG_71_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_72 0x0088 +#define regMP1_SMN_C2PMSG_72_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_73 0x0089 +#define regMP1_SMN_C2PMSG_73_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_74 0x008a +#define regMP1_SMN_C2PMSG_74_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_75 0x008b +#define regMP1_SMN_C2PMSG_75_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_76 0x008c +#define regMP1_SMN_C2PMSG_76_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_77 0x008d +#define regMP1_SMN_C2PMSG_77_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_78 0x008e +#define regMP1_SMN_C2PMSG_78_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_79 0x008f +#define regMP1_SMN_C2PMSG_79_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_80 0x0090 +#define regMP1_SMN_C2PMSG_80_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_81 0x0091 +#define regMP1_SMN_C2PMSG_81_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_82 0x0092 +#define regMP1_SMN_C2PMSG_82_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_83 0x0093 +#define regMP1_SMN_C2PMSG_83_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_84 0x0094 +#define regMP1_SMN_C2PMSG_84_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_85 0x0095 +#define regMP1_SMN_C2PMSG_85_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_86 0x0096 +#define regMP1_SMN_C2PMSG_86_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_87 0x0097 +#define regMP1_SMN_C2PMSG_87_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_88 0x0098 +#define regMP1_SMN_C2PMSG_88_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_89 0x0099 +#define regMP1_SMN_C2PMSG_89_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_90 0x009a +#define regMP1_SMN_C2PMSG_90_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_91 0x009b +#define regMP1_SMN_C2PMSG_91_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_92 0x009c +#define regMP1_SMN_C2PMSG_92_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_93 0x009d +#define regMP1_SMN_C2PMSG_93_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_94 0x009e +#define regMP1_SMN_C2PMSG_94_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_95 0x009f +#define regMP1_SMN_C2PMSG_95_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_96 0x00a0 +#define regMP1_SMN_C2PMSG_96_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_97 0x00a1 +#define regMP1_SMN_C2PMSG_97_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_98 0x00a2 +#define regMP1_SMN_C2PMSG_98_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_99 0x00a3 +#define regMP1_SMN_C2PMSG_99_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_100 0x00a4 +#define regMP1_SMN_C2PMSG_100_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_101 0x00a5 +#define regMP1_SMN_C2PMSG_101_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_102 0x00a6 +#define regMP1_SMN_C2PMSG_102_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_103 0x00a7 +#define regMP1_SMN_C2PMSG_103_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_104 0x00a8 +#define regMP1_SMN_C2PMSG_104_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_105 0x00a9 +#define regMP1_SMN_C2PMSG_105_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_106 0x00aa +#define regMP1_SMN_C2PMSG_106_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_107 0x00ab +#define regMP1_SMN_C2PMSG_107_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_108 0x00ac +#define regMP1_SMN_C2PMSG_108_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_109 0x00ad +#define regMP1_SMN_C2PMSG_109_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_110 0x00ae +#define regMP1_SMN_C2PMSG_110_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_111 0x00af +#define regMP1_SMN_C2PMSG_111_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_112 0x00b0 +#define regMP1_SMN_C2PMSG_112_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_113 0x00b1 +#define regMP1_SMN_C2PMSG_113_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_114 0x00b2 +#define regMP1_SMN_C2PMSG_114_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_115 0x00b3 +#define regMP1_SMN_C2PMSG_115_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_116 0x00b4 +#define regMP1_SMN_C2PMSG_116_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_117 0x00b5 +#define regMP1_SMN_C2PMSG_117_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_118 0x00b6 +#define regMP1_SMN_C2PMSG_118_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_119 0x00b7 +#define regMP1_SMN_C2PMSG_119_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_120 0x00b8 +#define regMP1_SMN_C2PMSG_120_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_121 0x00b9 +#define regMP1_SMN_C2PMSG_121_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_122 0x00ba +#define regMP1_SMN_C2PMSG_122_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_123 0x00bb +#define regMP1_SMN_C2PMSG_123_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_124 0x00bc +#define regMP1_SMN_C2PMSG_124_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_125 0x00bd +#define regMP1_SMN_C2PMSG_125_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_126 0x00be +#define regMP1_SMN_C2PMSG_126_BASE_IDX 1 +#define regMP1_SMN_C2PMSG_127 0x00bf +#define regMP1_SMN_C2PMSG_127_BASE_IDX 1 +#define regMP1_SMN_IH_CREDIT 0x0140 +#define regMP1_SMN_IH_CREDIT_BASE_IDX 1 +#define regMP1_SMN_IH_SW_INT 0x0141 +#define regMP1_SMN_IH_SW_INT_BASE_IDX 1 +#define regMP1_SMN_IH_SW_INT_CTRL 0x0142 +#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 1 +#define regMP1_SMN_FPS_CNT 0x0143 +#define regMP1_SMN_FPS_CNT_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH0 0x01c0 +#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH1 0x01c1 +#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH2 0x01c2 +#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH3 0x01c3 +#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH4 0x01c4 +#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH5 0x01c5 +#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH6 0x01c6 +#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH7 0x01c7 +#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH8 0x01c8 +#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH9 0x01c9 +#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH10 0x01ca +#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH11 0x01cb +#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH12 0x01cc +#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH13 0x01cd +#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH14 0x01ce +#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH15 0x01cf +#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH16 0x01d0 +#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH17 0x01d1 +#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH18 0x01d2 +#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH19 0x01d3 +#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH20 0x01d4 +#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH21 0x01d5 +#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH22 0x01d6 +#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH23 0x01d7 +#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH24 0x01d8 +#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH25 0x01d9 +#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH26 0x01da +#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH27 0x01db +#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH28 0x01dc +#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH29 0x01dd +#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH30 0x01de +#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 1 +#define regMP1_SMN_EXT_SCRATCH31 0x01df +#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 1 + + +// addressBlock: mp_SmuMp1Pub_CruDec +// base address: 0x3b00000 +#define regMP1_CRU1_MP1_FIRMWARE_FLAGS 0x4009 +#define regMP1_CRU1_MP1_FIRMWARE_FLAGS_BASE_IDX 5 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_sh_mask.h new file mode 100644 index 0000000000000..51a08f2ad8b11 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_sh_mask.h @@ -0,0 +1,626 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _mp_15_0_0_SH_MASK_HEADER +#define _mp_15_0_0_SH_MASK_HEADER + + +// addressBlock: mp_SmuMpASP_SmnDec +//MPASP_SMN_C2PMSG_60 +#define MPASP_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_61 +#define MPASP_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_62 +#define MPASP_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_63 +#define MPASP_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_64 +#define MPASP_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_65 +#define MPASP_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_66 +#define MPASP_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_67 +#define MPASP_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_68 +#define MPASP_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_69 +#define MPASP_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_70 +#define MPASP_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_71 +#define MPASP_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_72 +#define MPASP_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_73 +#define MPASP_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_74 +#define MPASP_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_75 +#define MPASP_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_76 +#define MPASP_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_77 +#define MPASP_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_78 +#define MPASP_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_79 +#define MPASP_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_100 +#define MPASP_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_101 +#define MPASP_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_102 +#define MPASP_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_103 +#define MPASP_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_C2PMSG_109 +#define MPASP_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_IH_CREDIT +#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MPASP_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MPASP_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MPASP_SMN_IH_SW_INT +#define MPASP_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MPASP_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MPASP_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MPASP_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MPASP_SMN_IH_SW_INT_CTRL +#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_0 +#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_1 +#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_2 +#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_3 +#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_4 +#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_5 +#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_6 +#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_7 +#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_8 +#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_9 +#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_10 +#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_11 +#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_12 +#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_13 +#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_14 +#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_15 +#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_16 +#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_17 +#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_18 +#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_19 +#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_20 +#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_21 +#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_22 +#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_23 +#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_24 +#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_25 +#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_26 +#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_27 +#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_28 +#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_29 +#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_30 +#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_31 +#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_104 +#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_105 +#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_106 +#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_107 +#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_108 +#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_109 +#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_110 +#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_111 +#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_112 +#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_113 +#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_114 +#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_115 +#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_116 +#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_117 +#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_118 +#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_119 +#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_120 +#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_121 +#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_122 +#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_123 +#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_124 +#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_125 +#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_126 +#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_127 +#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH8 +#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH9 +#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH10 +#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH11 +#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH12 +#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH13 +#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH14 +#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH15 +#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH16 +#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH17 +#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH18 +#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH19 +#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH20 +#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH21 +#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH22 +#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH23 +#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH24 +#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH25 +#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH26 +#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH27 +#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH28 +#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH29 +#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH30 +#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH31 +#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_CRU1_MP1_FIRMWARE_FLAGS +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h new file mode 100644 index 0000000000000..90d0d6c3b7b64 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_offset.h @@ -0,0 +1,868 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mp_15_0_8_OFFSET_HEADER +#define _mp_15_0_8_OFFSET_HEADER + + + +// addressBlock: mp_SmuMp1_SmnDec +// base address: 0x0 +#define regMP1_SMN_C2PMSG_0 0x0040 +#define regMP1_SMN_C2PMSG_0_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_1 0x0041 +#define regMP1_SMN_C2PMSG_1_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_2 0x0042 +#define regMP1_SMN_C2PMSG_2_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_3 0x0043 +#define regMP1_SMN_C2PMSG_3_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_4 0x0044 +#define regMP1_SMN_C2PMSG_4_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_5 0x0045 +#define regMP1_SMN_C2PMSG_5_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_6 0x0046 +#define regMP1_SMN_C2PMSG_6_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_7 0x0047 +#define regMP1_SMN_C2PMSG_7_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_8 0x0048 +#define regMP1_SMN_C2PMSG_8_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_9 0x0049 +#define regMP1_SMN_C2PMSG_9_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_10 0x004a +#define regMP1_SMN_C2PMSG_10_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_11 0x004b +#define regMP1_SMN_C2PMSG_11_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_12 0x004c +#define regMP1_SMN_C2PMSG_12_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_13 0x004d +#define regMP1_SMN_C2PMSG_13_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_14 0x004e +#define regMP1_SMN_C2PMSG_14_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_15 0x004f +#define regMP1_SMN_C2PMSG_15_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_16 0x0050 +#define regMP1_SMN_C2PMSG_16_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_17 0x0051 +#define regMP1_SMN_C2PMSG_17_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_18 0x0052 +#define regMP1_SMN_C2PMSG_18_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_19 0x0053 +#define regMP1_SMN_C2PMSG_19_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_20 0x0054 +#define regMP1_SMN_C2PMSG_20_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_21 0x0055 +#define regMP1_SMN_C2PMSG_21_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_22 0x0056 +#define regMP1_SMN_C2PMSG_22_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_23 0x0057 +#define regMP1_SMN_C2PMSG_23_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_24 0x0058 +#define regMP1_SMN_C2PMSG_24_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_25 0x0059 +#define regMP1_SMN_C2PMSG_25_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_26 0x005a +#define regMP1_SMN_C2PMSG_26_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_27 0x005b +#define regMP1_SMN_C2PMSG_27_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_28 0x005c +#define regMP1_SMN_C2PMSG_28_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_29 0x005d +#define regMP1_SMN_C2PMSG_29_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_30 0x005e +#define regMP1_SMN_C2PMSG_30_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_31 0x005f +#define regMP1_SMN_C2PMSG_31_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_32 0x0060 +#define regMP1_SMN_C2PMSG_32_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_33 0x0061 +#define regMP1_SMN_C2PMSG_33_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_34 0x0062 +#define regMP1_SMN_C2PMSG_34_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_35 0x0063 +#define regMP1_SMN_C2PMSG_35_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_36 0x0064 +#define regMP1_SMN_C2PMSG_36_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_37 0x0065 +#define regMP1_SMN_C2PMSG_37_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_38 0x0066 +#define regMP1_SMN_C2PMSG_38_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_39 0x0067 +#define regMP1_SMN_C2PMSG_39_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_40 0x0068 +#define regMP1_SMN_C2PMSG_40_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_41 0x0069 +#define regMP1_SMN_C2PMSG_41_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_42 0x006a +#define regMP1_SMN_C2PMSG_42_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_43 0x006b +#define regMP1_SMN_C2PMSG_43_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_44 0x006c +#define regMP1_SMN_C2PMSG_44_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_45 0x006d +#define regMP1_SMN_C2PMSG_45_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_46 0x006e +#define regMP1_SMN_C2PMSG_46_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_47 0x006f +#define regMP1_SMN_C2PMSG_47_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_48 0x0070 +#define regMP1_SMN_C2PMSG_48_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_49 0x0071 +#define regMP1_SMN_C2PMSG_49_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_50 0x0072 +#define regMP1_SMN_C2PMSG_50_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_51 0x0073 +#define regMP1_SMN_C2PMSG_51_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_52 0x0074 +#define regMP1_SMN_C2PMSG_52_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_53 0x0075 +#define regMP1_SMN_C2PMSG_53_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_54 0x0076 +#define regMP1_SMN_C2PMSG_54_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_55 0x0077 +#define regMP1_SMN_C2PMSG_55_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_56 0x0078 +#define regMP1_SMN_C2PMSG_56_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_57 0x0079 +#define regMP1_SMN_C2PMSG_57_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_58 0x007a +#define regMP1_SMN_C2PMSG_58_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_59 0x007b +#define regMP1_SMN_C2PMSG_59_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_60 0x007c +#define regMP1_SMN_C2PMSG_60_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_61 0x007d +#define regMP1_SMN_C2PMSG_61_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_62 0x007e +#define regMP1_SMN_C2PMSG_62_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_63 0x007f +#define regMP1_SMN_C2PMSG_63_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_64 0x0080 +#define regMP1_SMN_C2PMSG_64_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_65 0x0081 +#define regMP1_SMN_C2PMSG_65_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_66 0x0082 +#define regMP1_SMN_C2PMSG_66_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_67 0x0083 +#define regMP1_SMN_C2PMSG_67_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_68 0x0084 +#define regMP1_SMN_C2PMSG_68_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_69 0x0085 +#define regMP1_SMN_C2PMSG_69_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_70 0x0086 +#define regMP1_SMN_C2PMSG_70_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_71 0x0087 +#define regMP1_SMN_C2PMSG_71_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_72 0x0088 +#define regMP1_SMN_C2PMSG_72_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_73 0x0089 +#define regMP1_SMN_C2PMSG_73_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_74 0x008a +#define regMP1_SMN_C2PMSG_74_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_75 0x008b +#define regMP1_SMN_C2PMSG_75_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_76 0x008c +#define regMP1_SMN_C2PMSG_76_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_77 0x008d +#define regMP1_SMN_C2PMSG_77_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_78 0x008e +#define regMP1_SMN_C2PMSG_78_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_79 0x008f +#define regMP1_SMN_C2PMSG_79_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_80 0x0090 +#define regMP1_SMN_C2PMSG_80_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_81 0x0091 +#define regMP1_SMN_C2PMSG_81_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_82 0x0092 +#define regMP1_SMN_C2PMSG_82_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_83 0x0093 +#define regMP1_SMN_C2PMSG_83_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_84 0x0094 +#define regMP1_SMN_C2PMSG_84_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_85 0x0095 +#define regMP1_SMN_C2PMSG_85_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_86 0x0096 +#define regMP1_SMN_C2PMSG_86_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_87 0x0097 +#define regMP1_SMN_C2PMSG_87_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_88 0x0098 +#define regMP1_SMN_C2PMSG_88_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_89 0x0099 +#define regMP1_SMN_C2PMSG_89_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_90 0x009a +#define regMP1_SMN_C2PMSG_90_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_91 0x009b +#define regMP1_SMN_C2PMSG_91_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_92 0x009c +#define regMP1_SMN_C2PMSG_92_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_93 0x009d +#define regMP1_SMN_C2PMSG_93_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_94 0x009e +#define regMP1_SMN_C2PMSG_94_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_95 0x009f +#define regMP1_SMN_C2PMSG_95_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_96 0x00a0 +#define regMP1_SMN_C2PMSG_96_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_97 0x00a1 +#define regMP1_SMN_C2PMSG_97_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_98 0x00a2 +#define regMP1_SMN_C2PMSG_98_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_99 0x00a3 +#define regMP1_SMN_C2PMSG_99_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_100 0x00a4 +#define regMP1_SMN_C2PMSG_100_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_101 0x00a5 +#define regMP1_SMN_C2PMSG_101_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_102 0x00a6 +#define regMP1_SMN_C2PMSG_102_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_103 0x00a7 +#define regMP1_SMN_C2PMSG_103_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_104 0x00a8 +#define regMP1_SMN_C2PMSG_104_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_105 0x00a9 +#define regMP1_SMN_C2PMSG_105_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_106 0x00aa +#define regMP1_SMN_C2PMSG_106_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_107 0x00ab +#define regMP1_SMN_C2PMSG_107_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_108 0x00ac +#define regMP1_SMN_C2PMSG_108_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_109 0x00ad +#define regMP1_SMN_C2PMSG_109_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_110 0x00ae +#define regMP1_SMN_C2PMSG_110_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_111 0x00af +#define regMP1_SMN_C2PMSG_111_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_112 0x00b0 +#define regMP1_SMN_C2PMSG_112_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_113 0x00b1 +#define regMP1_SMN_C2PMSG_113_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_114 0x00b2 +#define regMP1_SMN_C2PMSG_114_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_115 0x00b3 +#define regMP1_SMN_C2PMSG_115_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_116 0x00b4 +#define regMP1_SMN_C2PMSG_116_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_117 0x00b5 +#define regMP1_SMN_C2PMSG_117_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_118 0x00b6 +#define regMP1_SMN_C2PMSG_118_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_119 0x00b7 +#define regMP1_SMN_C2PMSG_119_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_120 0x00b8 +#define regMP1_SMN_C2PMSG_120_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_121 0x00b9 +#define regMP1_SMN_C2PMSG_121_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_122 0x00ba +#define regMP1_SMN_C2PMSG_122_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_123 0x00bb +#define regMP1_SMN_C2PMSG_123_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_124 0x00bc +#define regMP1_SMN_C2PMSG_124_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_125 0x00bd +#define regMP1_SMN_C2PMSG_125_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_126 0x00be +#define regMP1_SMN_C2PMSG_126_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_127 0x00bf +#define regMP1_SMN_C2PMSG_127_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_128 0x00c0 +#define regMP1_SMN_C2PMSG_128_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_129 0x00c1 +#define regMP1_SMN_C2PMSG_129_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_130 0x00c2 +#define regMP1_SMN_C2PMSG_130_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_131 0x00c3 +#define regMP1_SMN_C2PMSG_131_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_132 0x00c4 +#define regMP1_SMN_C2PMSG_132_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_133 0x00c5 +#define regMP1_SMN_C2PMSG_133_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_134 0x00c6 +#define regMP1_SMN_C2PMSG_134_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_135 0x00c7 +#define regMP1_SMN_C2PMSG_135_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_136 0x00c8 +#define regMP1_SMN_C2PMSG_136_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_137 0x00c9 +#define regMP1_SMN_C2PMSG_137_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_138 0x00ca +#define regMP1_SMN_C2PMSG_138_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_139 0x00cb +#define regMP1_SMN_C2PMSG_139_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_140 0x00cc +#define regMP1_SMN_C2PMSG_140_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_141 0x00cd +#define regMP1_SMN_C2PMSG_141_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_142 0x00ce +#define regMP1_SMN_C2PMSG_142_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_143 0x00cf +#define regMP1_SMN_C2PMSG_143_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_144 0x00d0 +#define regMP1_SMN_C2PMSG_144_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_145 0x00d1 +#define regMP1_SMN_C2PMSG_145_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_146 0x00d2 +#define regMP1_SMN_C2PMSG_146_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_147 0x00d3 +#define regMP1_SMN_C2PMSG_147_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_148 0x00d4 +#define regMP1_SMN_C2PMSG_148_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_149 0x00d5 +#define regMP1_SMN_C2PMSG_149_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_150 0x00d6 +#define regMP1_SMN_C2PMSG_150_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_151 0x00d7 +#define regMP1_SMN_C2PMSG_151_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_152 0x00d8 +#define regMP1_SMN_C2PMSG_152_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_153 0x00d9 +#define regMP1_SMN_C2PMSG_153_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_154 0x00da +#define regMP1_SMN_C2PMSG_154_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_155 0x00db +#define regMP1_SMN_C2PMSG_155_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_156 0x00dc +#define regMP1_SMN_C2PMSG_156_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_157 0x00dd +#define regMP1_SMN_C2PMSG_157_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_158 0x00de +#define regMP1_SMN_C2PMSG_158_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_159 0x00df +#define regMP1_SMN_C2PMSG_159_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_160 0x00e0 +#define regMP1_SMN_C2PMSG_160_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_161 0x00e1 +#define regMP1_SMN_C2PMSG_161_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_162 0x00e2 +#define regMP1_SMN_C2PMSG_162_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_163 0x00e3 +#define regMP1_SMN_C2PMSG_163_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_164 0x00e4 +#define regMP1_SMN_C2PMSG_164_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_165 0x00e5 +#define regMP1_SMN_C2PMSG_165_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_166 0x00e6 +#define regMP1_SMN_C2PMSG_166_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_167 0x00e7 +#define regMP1_SMN_C2PMSG_167_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_168 0x00e8 +#define regMP1_SMN_C2PMSG_168_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_169 0x00e9 +#define regMP1_SMN_C2PMSG_169_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_170 0x00ea +#define regMP1_SMN_C2PMSG_170_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_171 0x00eb +#define regMP1_SMN_C2PMSG_171_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_172 0x00ec +#define regMP1_SMN_C2PMSG_172_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_173 0x00ed +#define regMP1_SMN_C2PMSG_173_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_174 0x00ee +#define regMP1_SMN_C2PMSG_174_BASE_IDX 2 +#define regMP1_SMN_C2PMSG_175 0x00ef +#define regMP1_SMN_C2PMSG_175_BASE_IDX 2 +#define regMP1_SMN_IH_CREDIT 0x0140 +#define regMP1_SMN_IH_CREDIT_BASE_IDX 2 +#define regMP1_SMN_IH_SW_INT 0x0141 +#define regMP1_SMN_IH_SW_INT_BASE_IDX 2 +#define regMP1_SMN_IH_SW_INT_CTRL 0x0142 +#define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 2 +#define regMP1_SMN_FPS_CNT 0x0143 +#define regMP1_SMN_FPS_CNT_BASE_IDX 2 +#define regMP1_SMN_PUB_CTRL 0x0144 +#define regMP1_SMN_PUB_CTRL_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH0 0x01c0 +#define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH1 0x01c1 +#define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH2 0x01c2 +#define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH3 0x01c3 +#define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH4 0x01c4 +#define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH5 0x01c5 +#define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH6 0x01c6 +#define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH7 0x01c7 +#define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH8 0x01c8 +#define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH9 0x01c9 +#define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH10 0x01ca +#define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH11 0x01cb +#define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH12 0x01cc +#define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH13 0x01cd +#define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH14 0x01ce +#define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH15 0x01cf +#define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH16 0x01d0 +#define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH17 0x01d1 +#define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH18 0x01d2 +#define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH19 0x01d3 +#define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH20 0x01d4 +#define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH21 0x01d5 +#define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH22 0x01d6 +#define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH23 0x01d7 +#define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH24 0x01d8 +#define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH25 0x01d9 +#define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH26 0x01da +#define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH27 0x01db +#define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH28 0x01dc +#define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH29 0x01dd +#define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH30 0x01de +#define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 2 +#define regMP1_SMN_EXT_SCRATCH31 0x01df +#define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 2 + + +// addressBlock: mp_SmuMpASP_SmnDec +// base address: 0x0 +#define regMPASP_SMN_C2PMSG_0 0x0040 +#define regMPASP_SMN_C2PMSG_0_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_1 0x0041 +#define regMPASP_SMN_C2PMSG_1_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_2 0x0042 +#define regMPASP_SMN_C2PMSG_2_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_3 0x0043 +#define regMPASP_SMN_C2PMSG_3_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_4 0x0044 +#define regMPASP_SMN_C2PMSG_4_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_5 0x0045 +#define regMPASP_SMN_C2PMSG_5_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_6 0x0046 +#define regMPASP_SMN_C2PMSG_6_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_7 0x0047 +#define regMPASP_SMN_C2PMSG_7_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_8 0x0048 +#define regMPASP_SMN_C2PMSG_8_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_9 0x0049 +#define regMPASP_SMN_C2PMSG_9_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_10 0x004a +#define regMPASP_SMN_C2PMSG_10_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_11 0x004b +#define regMPASP_SMN_C2PMSG_11_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_12 0x004c +#define regMPASP_SMN_C2PMSG_12_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_13 0x004d +#define regMPASP_SMN_C2PMSG_13_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_14 0x004e +#define regMPASP_SMN_C2PMSG_14_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_15 0x004f +#define regMPASP_SMN_C2PMSG_15_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_16 0x0050 +#define regMPASP_SMN_C2PMSG_16_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_17 0x0051 +#define regMPASP_SMN_C2PMSG_17_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_18 0x0052 +#define regMPASP_SMN_C2PMSG_18_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_19 0x0053 +#define regMPASP_SMN_C2PMSG_19_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_20 0x0054 +#define regMPASP_SMN_C2PMSG_20_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_21 0x0055 +#define regMPASP_SMN_C2PMSG_21_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_22 0x0056 +#define regMPASP_SMN_C2PMSG_22_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_23 0x0057 +#define regMPASP_SMN_C2PMSG_23_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_24 0x0058 +#define regMPASP_SMN_C2PMSG_24_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_25 0x0059 +#define regMPASP_SMN_C2PMSG_25_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_26 0x005a +#define regMPASP_SMN_C2PMSG_26_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_27 0x005b +#define regMPASP_SMN_C2PMSG_27_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_28 0x005c +#define regMPASP_SMN_C2PMSG_28_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_29 0x005d +#define regMPASP_SMN_C2PMSG_29_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_30 0x005e +#define regMPASP_SMN_C2PMSG_30_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_31 0x005f +#define regMPASP_SMN_C2PMSG_31_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_32 0x0060 +#define regMPASP_SMN_C2PMSG_32_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_33 0x0061 +#define regMPASP_SMN_C2PMSG_33_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_34 0x0062 +#define regMPASP_SMN_C2PMSG_34_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_35 0x0063 +#define regMPASP_SMN_C2PMSG_35_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_36 0x0064 +#define regMPASP_SMN_C2PMSG_36_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_37 0x0065 +#define regMPASP_SMN_C2PMSG_37_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_38 0x0066 +#define regMPASP_SMN_C2PMSG_38_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_39 0x0067 +#define regMPASP_SMN_C2PMSG_39_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_40 0x0068 +#define regMPASP_SMN_C2PMSG_40_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_41 0x0069 +#define regMPASP_SMN_C2PMSG_41_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_42 0x006a +#define regMPASP_SMN_C2PMSG_42_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_43 0x006b +#define regMPASP_SMN_C2PMSG_43_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_44 0x006c +#define regMPASP_SMN_C2PMSG_44_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_45 0x006d +#define regMPASP_SMN_C2PMSG_45_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_46 0x006e +#define regMPASP_SMN_C2PMSG_46_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_47 0x006f +#define regMPASP_SMN_C2PMSG_47_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_48 0x0070 +#define regMPASP_SMN_C2PMSG_48_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_49 0x0071 +#define regMPASP_SMN_C2PMSG_49_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_50 0x0072 +#define regMPASP_SMN_C2PMSG_50_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_51 0x0073 +#define regMPASP_SMN_C2PMSG_51_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_52 0x0074 +#define regMPASP_SMN_C2PMSG_52_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_53 0x0075 +#define regMPASP_SMN_C2PMSG_53_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_54 0x0076 +#define regMPASP_SMN_C2PMSG_54_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_55 0x0077 +#define regMPASP_SMN_C2PMSG_55_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_56 0x0078 +#define regMPASP_SMN_C2PMSG_56_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_57 0x0079 +#define regMPASP_SMN_C2PMSG_57_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_58 0x007a +#define regMPASP_SMN_C2PMSG_58_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_59 0x007b +#define regMPASP_SMN_C2PMSG_59_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_60 0x007c +#define regMPASP_SMN_C2PMSG_60_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_61 0x007d +#define regMPASP_SMN_C2PMSG_61_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_62 0x007e +#define regMPASP_SMN_C2PMSG_62_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_63 0x007f +#define regMPASP_SMN_C2PMSG_63_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_64 0x0080 +#define regMPASP_SMN_C2PMSG_64_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_65 0x0081 +#define regMPASP_SMN_C2PMSG_65_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_66 0x0082 +#define regMPASP_SMN_C2PMSG_66_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_67 0x0083 +#define regMPASP_SMN_C2PMSG_67_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_68 0x0084 +#define regMPASP_SMN_C2PMSG_68_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_69 0x0085 +#define regMPASP_SMN_C2PMSG_69_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_70 0x0086 +#define regMPASP_SMN_C2PMSG_70_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_71 0x0087 +#define regMPASP_SMN_C2PMSG_71_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_72 0x0088 +#define regMPASP_SMN_C2PMSG_72_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_73 0x0089 +#define regMPASP_SMN_C2PMSG_73_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_74 0x008a +#define regMPASP_SMN_C2PMSG_74_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_75 0x008b +#define regMPASP_SMN_C2PMSG_75_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_76 0x008c +#define regMPASP_SMN_C2PMSG_76_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_77 0x008d +#define regMPASP_SMN_C2PMSG_77_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_78 0x008e +#define regMPASP_SMN_C2PMSG_78_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_79 0x008f +#define regMPASP_SMN_C2PMSG_79_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_80 0x0090 +#define regMPASP_SMN_C2PMSG_80_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_81 0x0091 +#define regMPASP_SMN_C2PMSG_81_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_82 0x0092 +#define regMPASP_SMN_C2PMSG_82_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_83 0x0093 +#define regMPASP_SMN_C2PMSG_83_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_84 0x0094 +#define regMPASP_SMN_C2PMSG_84_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_85 0x0095 +#define regMPASP_SMN_C2PMSG_85_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_86 0x0096 +#define regMPASP_SMN_C2PMSG_86_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_87 0x0097 +#define regMPASP_SMN_C2PMSG_87_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_88 0x0098 +#define regMPASP_SMN_C2PMSG_88_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_89 0x0099 +#define regMPASP_SMN_C2PMSG_89_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_90 0x009a +#define regMPASP_SMN_C2PMSG_90_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_91 0x009b +#define regMPASP_SMN_C2PMSG_91_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_92 0x009c +#define regMPASP_SMN_C2PMSG_92_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_93 0x009d +#define regMPASP_SMN_C2PMSG_93_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_94 0x009e +#define regMPASP_SMN_C2PMSG_94_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_95 0x009f +#define regMPASP_SMN_C2PMSG_95_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_96 0x00a0 +#define regMPASP_SMN_C2PMSG_96_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_97 0x00a1 +#define regMPASP_SMN_C2PMSG_97_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_98 0x00a2 +#define regMPASP_SMN_C2PMSG_98_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_99 0x00a3 +#define regMPASP_SMN_C2PMSG_99_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_100 0x00a4 +#define regMPASP_SMN_C2PMSG_100_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_101 0x00a5 +#define regMPASP_SMN_C2PMSG_101_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_102 0x00a6 +#define regMPASP_SMN_C2PMSG_102_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_103 0x00a7 +#define regMPASP_SMN_C2PMSG_103_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_104 0x00a8 +#define regMPASP_SMN_C2PMSG_104_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_105 0x00a9 +#define regMPASP_SMN_C2PMSG_105_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_106 0x00aa +#define regMPASP_SMN_C2PMSG_106_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_107 0x00ab +#define regMPASP_SMN_C2PMSG_107_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_108 0x00ac +#define regMPASP_SMN_C2PMSG_108_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_109 0x00ad +#define regMPASP_SMN_C2PMSG_109_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_110 0x00ae +#define regMPASP_SMN_C2PMSG_110_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_111 0x00af +#define regMPASP_SMN_C2PMSG_111_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_112 0x00b0 +#define regMPASP_SMN_C2PMSG_112_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_113 0x00b1 +#define regMPASP_SMN_C2PMSG_113_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_114 0x00b2 +#define regMPASP_SMN_C2PMSG_114_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_115 0x00b3 +#define regMPASP_SMN_C2PMSG_115_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_116 0x00b4 +#define regMPASP_SMN_C2PMSG_116_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_117 0x00b5 +#define regMPASP_SMN_C2PMSG_117_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_118 0x00b6 +#define regMPASP_SMN_C2PMSG_118_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_119 0x00b7 +#define regMPASP_SMN_C2PMSG_119_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_120 0x00b8 +#define regMPASP_SMN_C2PMSG_120_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_121 0x00b9 +#define regMPASP_SMN_C2PMSG_121_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_122 0x00ba +#define regMPASP_SMN_C2PMSG_122_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_123 0x00bb +#define regMPASP_SMN_C2PMSG_123_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_124 0x00bc +#define regMPASP_SMN_C2PMSG_124_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_125 0x00bd +#define regMPASP_SMN_C2PMSG_125_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_126 0x00be +#define regMPASP_SMN_C2PMSG_126_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_127 0x00bf +#define regMPASP_SMN_C2PMSG_127_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_128 0x00c0 +#define regMPASP_SMN_C2PMSG_128_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_129 0x00c1 +#define regMPASP_SMN_C2PMSG_129_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_130 0x00c2 +#define regMPASP_SMN_C2PMSG_130_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_131 0x00c3 +#define regMPASP_SMN_C2PMSG_131_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_132 0x00c4 +#define regMPASP_SMN_C2PMSG_132_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_133 0x00c5 +#define regMPASP_SMN_C2PMSG_133_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_134 0x00c6 +#define regMPASP_SMN_C2PMSG_134_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_135 0x00c7 +#define regMPASP_SMN_C2PMSG_135_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_136 0x00c8 +#define regMPASP_SMN_C2PMSG_136_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_137 0x00c9 +#define regMPASP_SMN_C2PMSG_137_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_138 0x00ca +#define regMPASP_SMN_C2PMSG_138_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_139 0x00cb +#define regMPASP_SMN_C2PMSG_139_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_140 0x00cc +#define regMPASP_SMN_C2PMSG_140_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_141 0x00cd +#define regMPASP_SMN_C2PMSG_141_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_142 0x00ce +#define regMPASP_SMN_C2PMSG_142_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_143 0x00cf +#define regMPASP_SMN_C2PMSG_143_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_144 0x00d0 +#define regMPASP_SMN_C2PMSG_144_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_145 0x00d1 +#define regMPASP_SMN_C2PMSG_145_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_146 0x00d2 +#define regMPASP_SMN_C2PMSG_146_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_147 0x00d3 +#define regMPASP_SMN_C2PMSG_147_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_148 0x00d4 +#define regMPASP_SMN_C2PMSG_148_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_149 0x00d5 +#define regMPASP_SMN_C2PMSG_149_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_150 0x00d6 +#define regMPASP_SMN_C2PMSG_150_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_151 0x00d7 +#define regMPASP_SMN_C2PMSG_151_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_152 0x00d8 +#define regMPASP_SMN_C2PMSG_152_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_153 0x00d9 +#define regMPASP_SMN_C2PMSG_153_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_154 0x00da +#define regMPASP_SMN_C2PMSG_154_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_155 0x00db +#define regMPASP_SMN_C2PMSG_155_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_156 0x00dc +#define regMPASP_SMN_C2PMSG_156_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_157 0x00dd +#define regMPASP_SMN_C2PMSG_157_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_158 0x00de +#define regMPASP_SMN_C2PMSG_158_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_159 0x00df +#define regMPASP_SMN_C2PMSG_159_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_160 0x00e0 +#define regMPASP_SMN_C2PMSG_160_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_161 0x00e1 +#define regMPASP_SMN_C2PMSG_161_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_162 0x00e2 +#define regMPASP_SMN_C2PMSG_162_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_163 0x00e3 +#define regMPASP_SMN_C2PMSG_163_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_164 0x00e4 +#define regMPASP_SMN_C2PMSG_164_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_165 0x00e5 +#define regMPASP_SMN_C2PMSG_165_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_166 0x00e6 +#define regMPASP_SMN_C2PMSG_166_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_167 0x00e7 +#define regMPASP_SMN_C2PMSG_167_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_168 0x00e8 +#define regMPASP_SMN_C2PMSG_168_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_169 0x00e9 +#define regMPASP_SMN_C2PMSG_169_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_170 0x00ea +#define regMPASP_SMN_C2PMSG_170_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_171 0x00eb +#define regMPASP_SMN_C2PMSG_171_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_172 0x00ec +#define regMPASP_SMN_C2PMSG_172_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_173 0x00ed +#define regMPASP_SMN_C2PMSG_173_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_174 0x00ee +#define regMPASP_SMN_C2PMSG_174_BASE_IDX 1 +#define regMPASP_SMN_C2PMSG_175 0x00ef +#define regMPASP_SMN_C2PMSG_175_BASE_IDX 1 +#define regMPASP_SMN_IH_CREDIT 0x0140 +#define regMPASP_SMN_IH_CREDIT_BASE_IDX 1 +#define regMPASP_SMN_IH_SW_INT 0x0141 +#define regMPASP_SMN_IH_SW_INT_BASE_IDX 1 +#define regMPASP_SMN_IH_SW_INT_CTRL 0x0142 +#define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 1 + + +// addressBlock: mp_SmuMpRASPub_CruDec +// base address: 0x0 +#define regMPRAS_CRU0_MPRAS_FIRMWARE_FLAGS 0xbeb009 +#define regMPRAS_CRU0_MPRAS_FIRMWARE_FLAGS_BASE_IDX 3 + + +// addressBlock: mp_SmuMpIFOEPub_CruDec +// base address: 0x0 +#define regMPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS 0xbeb009 +#define regMPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS_BASE_IDX 3 + + +// addressBlock: mp_SmuMp1Pub_CruDec +// base address: 0x0 +#define regMP1_CRU0_MP1_FIRMWARE_FLAGS 0xbeb009 +#define regMP1_CRU0_MP1_FIRMWARE_FLAGS_BASE_IDX 3 + + +// addressBlock: mp_SmuMpIOPub_CruDec +// base address: 0x0 +#define regMPIO_CRU0_MPIO_FIRMWARE_FLAGS 0xbeb009 +#define regMPIO_CRU0_MPIO_FIRMWARE_FLAGS_BASE_IDX 3 + + +// addressBlock: MpRASMmioPublic_SmuMpRASPub_CruDec +// base address: 0x3e00000 +#define regMPRAS_CRU1_MPRAS_FIRMWARE_FLAGS 0x4009 +#define regMPRAS_CRU1_MPRAS_FIRMWARE_FLAGS_BASE_IDX 9 + + +// addressBlock: MpIFoEMmioPublic_SmuMpIFOEPub_CruDec +// base address: 0x49d00000 +#define regMPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS 0x4009 +#define regMPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS_BASE_IDX 26 + + +// addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec +// base address: 0x3b00000 +#define regMP1_CRU1_MP1_FIRMWARE_FLAGS 0x4009 +#define regMP1_CRU1_MP1_FIRMWARE_FLAGS_BASE_IDX 6 + + +// addressBlock: MpIOMmioPublic_SmuMpIOPub_CruDec +// base address: 0xc900000 +#define regMPIO_CRU1_MPIO_FIRMWARE_FLAGS 0x4009 +#define regMPIO_CRU1_MPIO_FIRMWARE_FLAGS_BASE_IDX 23 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_sh_mask.h new file mode 100644 index 0000000000000..5f4f883ac5a2e --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_8_sh_mask.h @@ -0,0 +1,616 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _mp_15_0_8_SH_MASK_HEADER +#define _mp_15_0_8_SH_MASK_HEADER + + +// addressBlock: mp_SmuMp1_SmnDec +//MP1_SMN_C2PMSG_0 +#define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_1 +#define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_2 +#define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_3 +#define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_4 +#define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_5 +#define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_6 +#define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_7 +#define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_8 +#define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_9 +#define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_10 +#define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_11 +#define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_12 +#define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_13 +#define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_14 +#define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_15 +#define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_16 +#define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_17 +#define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_18 +#define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_19 +#define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_20 +#define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_21 +#define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_22 +#define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_23 +#define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_24 +#define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_25 +#define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_26 +#define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_27 +#define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_28 +#define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_29 +#define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_30 +#define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_31 +#define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_32 +#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_33 +#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_34 +#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_35 +#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_36 +#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_37 +#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_38 +#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_39 +#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_40 +#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_41 +#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_42 +#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_43 +#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_44 +#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_45 +#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_46 +#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_47 +#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_48 +#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_49 +#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_50 +#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_51 +#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_52 +#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_53 +#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_54 +#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_55 +#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_56 +#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_57 +#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_58 +#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_59 +#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_60 +#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_61 +#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_62 +#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_63 +#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_64 +#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_65 +#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_66 +#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_67 +#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_68 +#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_69 +#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_70 +#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_71 +#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_72 +#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_73 +#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_74 +#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_75 +#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_76 +#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_77 +#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_78 +#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_79 +#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_80 +#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_81 +#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_82 +#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_83 +#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_84 +#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_85 +#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_86 +#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_87 +#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_88 +#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_89 +#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_90 +#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_91 +#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_92 +#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_93 +#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_94 +#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_95 +#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_96 +#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_97 +#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_98 +#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_99 +#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_100 +#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_101 +#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_102 +#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_103 +#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_104 +#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_105 +#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_106 +#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_107 +#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_108 +#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_109 +#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_110 +#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_111 +#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_112 +#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_113 +#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_114 +#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_115 +#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_116 +#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_117 +#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_118 +#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_119 +#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_120 +#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_121 +#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_122 +#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_123 +#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_124 +#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_125 +#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_126 +#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_C2PMSG_127 +#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 +#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL +//MP1_SMN_IH_CREDIT +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MP1_SMN_IH_SW_INT +#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MP1_SMN_IH_SW_INT_CTRL +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +//MP1_SMN_FPS_CNT +#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +//MP1_SMN_PUB_CTRL +#define MP1_SMN_PUB_CTRL__LX3_RESET__SHIFT 0x0 +#define MP1_SMN_PUB_CTRL__LX3_RESET_MASK 0x00000001L +//MP1_SMN_EXT_SCRATCH0 +#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH1 +#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH2 +#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH3 +#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH4 +#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH5 +#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH6 +#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH7 +#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH8 +#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH9 +#define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH10 +#define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH11 +#define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH12 +#define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH13 +#define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH14 +#define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH15 +#define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH16 +#define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH17 +#define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH18 +#define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH19 +#define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH20 +#define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH21 +#define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH22 +#define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH23 +#define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH24 +#define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH25 +#define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH26 +#define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH27 +#define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH28 +#define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH29 +#define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH30 +#define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL +//MP1_SMN_EXT_SCRATCH31 +#define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 +#define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: mp_SmuMpASP_SmnDec +//MPASP_SMN_C2PMSG_81 +#define MPASP_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +#define MPASP_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +//MPASP_SMN_IH_CREDIT +#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define MPASP_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +#define MPASP_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define MPASP_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +//MPASP_SMN_IH_SW_INT +#define MPASP_SMN_IH_SW_INT__ID__SHIFT 0x0 +#define MPASP_SMN_IH_SW_INT__VALID__SHIFT 0x8 +#define MPASP_SMN_IH_SW_INT__ID_MASK 0x000000FFL +#define MPASP_SMN_IH_SW_INT__VALID_MASK 0x00000100L +//MPASP_SMN_IH_SW_INT_CTRL +#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +#define MPASP_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +#define MPASP_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L + + +// addressBlock: mp_SmuMpRASPub_CruDec +//MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS +#define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPRAS_CRU0_MPRAS_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: mp_SmuMpIFOEPub_CruDec +//MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS +#define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPIFOE_CRU0_MPIFOE_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: mp_SmuMp1Pub_CruDec +//MP1_CRU0_MP1_FIRMWARE_FLAGS +#define MP1_CRU0_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_CRU0_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_CRU0_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_CRU0_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: mp_SmuMpIOPub_CruDec +//MPIO_CRU0_MPIO_FIRMWARE_FLAGS +#define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPIO_CRU0_MPIO_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: MpRASMmioPublic_SmuMpRASPub_CruDec +//MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS +#define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPRAS_CRU1_MPRAS_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: MpIFoEMmioPublic_SmuMpIFOEPub_CruDec +//MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS +#define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPIFOE_CRU1_MPIFOE_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: Mp1MmioPublic_SmuMp1Pub_CruDec +//MP1_CRU1_MP1_FIRMWARE_FLAGS +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: MpIOMmioPublic_SmuMpIOPub_CruDec +//MPIO_CRU1_MPIO_FIRMWARE_FLAGS +#define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +#define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +#define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +#define MPIO_CRU1_MPIO_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_1_0_offset.h new file mode 100644 index 0000000000000..fd454d36b6797 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_1_0_offset.h @@ -0,0 +1,280 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _osssys_7_1_0_OFFSET_HEADER +#define _osssys_7_1_0_OFFSET_HEADER + + + +// addressBlock: osssys_osssysdec +// base address: 0x4280 +#define regIH_VMID_0_LUT 0x0000 +#define regIH_VMID_0_LUT_BASE_IDX 0 +#define regIH_VMID_1_LUT 0x0001 +#define regIH_VMID_1_LUT_BASE_IDX 0 +#define regIH_VMID_2_LUT 0x0002 +#define regIH_VMID_2_LUT_BASE_IDX 0 +#define regIH_VMID_3_LUT 0x0003 +#define regIH_VMID_3_LUT_BASE_IDX 0 +#define regIH_VMID_4_LUT 0x0004 +#define regIH_VMID_4_LUT_BASE_IDX 0 +#define regIH_VMID_5_LUT 0x0005 +#define regIH_VMID_5_LUT_BASE_IDX 0 +#define regIH_VMID_6_LUT 0x0006 +#define regIH_VMID_6_LUT_BASE_IDX 0 +#define regIH_VMID_7_LUT 0x0007 +#define regIH_VMID_7_LUT_BASE_IDX 0 +#define regIH_VMID_8_LUT 0x0008 +#define regIH_VMID_8_LUT_BASE_IDX 0 +#define regIH_VMID_9_LUT 0x0009 +#define regIH_VMID_9_LUT_BASE_IDX 0 +#define regIH_VMID_10_LUT 0x000a +#define regIH_VMID_10_LUT_BASE_IDX 0 +#define regIH_VMID_11_LUT 0x000b +#define regIH_VMID_11_LUT_BASE_IDX 0 +#define regIH_VMID_12_LUT 0x000c +#define regIH_VMID_12_LUT_BASE_IDX 0 +#define regIH_VMID_13_LUT 0x000d +#define regIH_VMID_13_LUT_BASE_IDX 0 +#define regIH_VMID_14_LUT 0x000e +#define regIH_VMID_14_LUT_BASE_IDX 0 +#define regIH_VMID_15_LUT 0x000f +#define regIH_VMID_15_LUT_BASE_IDX 0 +#define regIH_VMID_0_LUT_MM 0x0010 +#define regIH_VMID_0_LUT_MM_BASE_IDX 0 +#define regIH_VMID_1_LUT_MM 0x0011 +#define regIH_VMID_1_LUT_MM_BASE_IDX 0 +#define regIH_VMID_2_LUT_MM 0x0012 +#define regIH_VMID_2_LUT_MM_BASE_IDX 0 +#define regIH_VMID_3_LUT_MM 0x0013 +#define regIH_VMID_3_LUT_MM_BASE_IDX 0 +#define regIH_VMID_4_LUT_MM 0x0014 +#define regIH_VMID_4_LUT_MM_BASE_IDX 0 +#define regIH_VMID_5_LUT_MM 0x0015 +#define regIH_VMID_5_LUT_MM_BASE_IDX 0 +#define regIH_VMID_6_LUT_MM 0x0016 +#define regIH_VMID_6_LUT_MM_BASE_IDX 0 +#define regIH_VMID_7_LUT_MM 0x0017 +#define regIH_VMID_7_LUT_MM_BASE_IDX 0 +#define regIH_VMID_8_LUT_MM 0x0018 +#define regIH_VMID_8_LUT_MM_BASE_IDX 0 +#define regIH_VMID_9_LUT_MM 0x0019 +#define regIH_VMID_9_LUT_MM_BASE_IDX 0 +#define regIH_VMID_10_LUT_MM 0x001a +#define regIH_VMID_10_LUT_MM_BASE_IDX 0 +#define regIH_VMID_11_LUT_MM 0x001b +#define regIH_VMID_11_LUT_MM_BASE_IDX 0 +#define regIH_VMID_12_LUT_MM 0x001c +#define regIH_VMID_12_LUT_MM_BASE_IDX 0 +#define regIH_VMID_13_LUT_MM 0x001d +#define regIH_VMID_13_LUT_MM_BASE_IDX 0 +#define regIH_VMID_14_LUT_MM 0x001e +#define regIH_VMID_14_LUT_MM_BASE_IDX 0 +#define regIH_VMID_15_LUT_MM 0x001f +#define regIH_VMID_15_LUT_MM_BASE_IDX 0 +#define regIH_COOKIE_0 0x0020 +#define regIH_COOKIE_0_BASE_IDX 0 +#define regIH_COOKIE_1 0x0021 +#define regIH_COOKIE_1_BASE_IDX 0 +#define regIH_COOKIE_2 0x0022 +#define regIH_COOKIE_2_BASE_IDX 0 +#define regIH_COOKIE_3 0x0023 +#define regIH_COOKIE_3_BASE_IDX 0 +#define regIH_COOKIE_4 0x0024 +#define regIH_COOKIE_4_BASE_IDX 0 +#define regIH_COOKIE_5 0x0025 +#define regIH_COOKIE_5_BASE_IDX 0 +#define regIH_COOKIE_6 0x0026 +#define regIH_COOKIE_6_BASE_IDX 0 +#define regIH_COOKIE_7 0x0027 +#define regIH_COOKIE_7_BASE_IDX 0 +#define regIH_VMID_LUT_INDEX 0x0028 +#define regIH_VMID_LUT_INDEX_BASE_IDX 0 +#define regIH_REGISTER_LAST_PART0 0x003f +#define regIH_REGISTER_LAST_PART0_BASE_IDX 0 +#define regIH_RB_CNTL 0x0080 +#define regIH_RB_CNTL_BASE_IDX 0 +#define regIH_RB_RPTR 0x0081 +#define regIH_RB_RPTR_BASE_IDX 0 +#define regIH_RB_WPTR 0x0082 +#define regIH_RB_WPTR_BASE_IDX 0 +#define regIH_RB_BASE 0x0083 +#define regIH_RB_BASE_BASE_IDX 0 +#define regIH_RB_BASE_HI 0x0084 +#define regIH_RB_BASE_HI_BASE_IDX 0 +#define regIH_RB_WPTR_ADDR_HI 0x0085 +#define regIH_RB_WPTR_ADDR_HI_BASE_IDX 0 +#define regIH_RB_WPTR_ADDR_LO 0x0086 +#define regIH_RB_WPTR_ADDR_LO_BASE_IDX 0 +#define regIH_DOORBELL_RPTR 0x0087 +#define regIH_DOORBELL_RPTR_BASE_IDX 0 +#define regIH_DOORBELL_RETRY_CAM 0x0088 +#define regIH_DOORBELL_RETRY_CAM_BASE_IDX 0 +#define regIH_RB_CNTL_RING1 0x008c +#define regIH_RB_CNTL_RING1_BASE_IDX 0 +#define regIH_RB_RPTR_RING1 0x008d +#define regIH_RB_RPTR_RING1_BASE_IDX 0 +#define regIH_RB_WPTR_RING1 0x008e +#define regIH_RB_WPTR_RING1_BASE_IDX 0 +#define regIH_RB_BASE_RING1 0x008f +#define regIH_RB_BASE_RING1_BASE_IDX 0 +#define regIH_RB_BASE_HI_RING1 0x0090 +#define regIH_RB_BASE_HI_RING1_BASE_IDX 0 +#define regIH_DOORBELL_RPTR_RING1 0x0093 +#define regIH_DOORBELL_RPTR_RING1_BASE_IDX 0 +#define regIH_RETRY_CAM_ACK 0x00a4 +#define regIH_RETRY_CAM_ACK_BASE_IDX 0 +#define regIH_VERSION 0x00a5 +#define regIH_VERSION_BASE_IDX 0 +#define regIH_CNTL 0x00a8 +#define regIH_CNTL_BASE_IDX 0 +#define regIH_CLK_CTRL 0x00a9 +#define regIH_CLK_CTRL_BASE_IDX 0 +#define regIH_STORM_CLIENT_LIST_CNTL 0x00aa +#define regIH_STORM_CLIENT_LIST_CNTL_BASE_IDX 0 +#define regIH_LIMIT_INT_RATE_CNTL 0x00ab +#define regIH_LIMIT_INT_RATE_CNTL_BASE_IDX 0 +#define regIH_RETRY_INT_CAM_CNTL 0x00ac +#define regIH_RETRY_INT_CAM_CNTL_BASE_IDX 0 +#define regIH_MEM_POWER_CTRL 0x00ad +#define regIH_MEM_POWER_CTRL_BASE_IDX 0 +#define regIH_MEM_POWER_CTRL2 0x00ae +#define regIH_MEM_POWER_CTRL2_BASE_IDX 0 +#define regIH_CNTL2 0x00c1 +#define regIH_CNTL2_BASE_IDX 0 +#define regIH_STATUS 0x00c2 +#define regIH_STATUS_BASE_IDX 0 +#define regIH_PERFMON_CNTL 0x00c3 +#define regIH_PERFMON_CNTL_BASE_IDX 0 +#define regIH_PERFCOUNTER0_RESULT 0x00c4 +#define regIH_PERFCOUNTER0_RESULT_BASE_IDX 0 +#define regIH_PERFCOUNTER1_RESULT 0x00c5 +#define regIH_PERFCOUNTER1_RESULT_BASE_IDX 0 +#define regIH_DSM_MATCH_VALUE_BIT_31_0 0x00c7 +#define regIH_DSM_MATCH_VALUE_BIT_31_0_BASE_IDX 0 +#define regIH_DSM_MATCH_VALUE_BIT_63_32 0x00c8 +#define regIH_DSM_MATCH_VALUE_BIT_63_32_BASE_IDX 0 +#define regIH_DSM_MATCH_VALUE_BIT_95_64 0x00c9 +#define regIH_DSM_MATCH_VALUE_BIT_95_64_BASE_IDX 0 +#define regIH_DSM_MATCH_FIELD_CONTROL 0x00ca +#define regIH_DSM_MATCH_FIELD_CONTROL_BASE_IDX 0 +#define regIH_DSM_MATCH_DATA_CONTROL 0x00cb +#define regIH_DSM_MATCH_DATA_CONTROL_BASE_IDX 0 +#define regIH_DSM_MATCH_FCN_ID 0x00cc +#define regIH_DSM_MATCH_FCN_ID_BASE_IDX 0 +#define regIH_VF_RB_STATUS 0x00ce +#define regIH_VF_RB_STATUS_BASE_IDX 0 +#define regIH_VF_RB_STATUS2 0x00cf +#define regIH_VF_RB_STATUS2_BASE_IDX 0 +#define regIH_VF_RB1_STATUS 0x00d0 +#define regIH_VF_RB1_STATUS_BASE_IDX 0 +#define regIH_VF_RB1_STATUS2 0x00d1 +#define regIH_VF_RB1_STATUS2_BASE_IDX 0 +#define regIH_RB_STATUS 0x00d4 +#define regIH_RB_STATUS_BASE_IDX 0 +#define regIH_INT_FLOOD_CNTL 0x00d5 +#define regIH_INT_FLOOD_CNTL_BASE_IDX 0 +#define regIH_RB0_INT_FLOOD_STATUS 0x00d6 +#define regIH_RB0_INT_FLOOD_STATUS_BASE_IDX 0 +#define regIH_RB1_INT_FLOOD_STATUS 0x00d7 +#define regIH_RB1_INT_FLOOD_STATUS_BASE_IDX 0 +#define regIH_INT_FLOOD_STATUS 0x00d9 +#define regIH_INT_FLOOD_STATUS_BASE_IDX 0 +#define regIH_INT_FLAGS 0x00dc +#define regIH_INT_FLAGS_BASE_IDX 0 +#define regIH_SCRATCH 0x00e0 +#define regIH_SCRATCH_BASE_IDX 0 +#define regIH_CLIENT_CREDIT_ERROR 0x00e1 +#define regIH_CLIENT_CREDIT_ERROR_BASE_IDX 0 +#define regIH_GPU_IOV_VIOLATION_LOG 0x00e2 +#define regIH_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define regIH_GPU_IOV_VIOLATION_LOG2 0x00e3 +#define regIH_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define regIH_COOKIE_REC_VIOLATION_LOG 0x00e4 +#define regIH_COOKIE_REC_VIOLATION_LOG_BASE_IDX 0 +#define regIH_CREDIT_STATUS 0x00e5 +#define regIH_CREDIT_STATUS_BASE_IDX 0 +#define regIH_MMHUB_ERROR 0x00e6 +#define regIH_MMHUB_ERROR_BASE_IDX 0 +#define regIH_VF_RB_STATUS3 0x00ea +#define regIH_VF_RB_STATUS3_BASE_IDX 0 +#define regIH_VF_RB_STATUS4 0x00eb +#define regIH_VF_RB_STATUS4_BASE_IDX 0 +#define regIH_VF_RB1_STATUS3 0x00ec +#define regIH_VF_RB1_STATUS3_BASE_IDX 0 +#define regIH_MSI_STORM_CTRL 0x00f1 +#define regIH_MSI_STORM_CTRL_BASE_IDX 0 +#define regIH_MSI_STORM_CLIENT_INDEX 0x00f2 +#define regIH_MSI_STORM_CLIENT_INDEX_BASE_IDX 0 +#define regIH_MSI_STORM_CLIENT_DATA 0x00f3 +#define regIH_MSI_STORM_CLIENT_DATA_BASE_IDX 0 +#define regIH_LAST_INT_INFO0 0x00f9 +#define regIH_LAST_INT_INFO0_BASE_IDX 0 +#define regIH_LAST_INT_INFO1 0x00fa +#define regIH_LAST_INT_INFO1_BASE_IDX 0 +#define regIH_LAST_INT_INFO2 0x00fb +#define regIH_LAST_INT_INFO2_BASE_IDX 0 +#define regIH_REGISTER_LAST_PART2 0x00ff +#define regIH_REGISTER_LAST_PART2_BASE_IDX 0 +#define regSEM_MAILBOX 0x010a +#define regSEM_MAILBOX_BASE_IDX 0 +#define regSEM_MAILBOX_CLEAR 0x010b +#define regSEM_MAILBOX_CLEAR_BASE_IDX 0 +#define regSEM_REGISTER_LAST_PART2 0x011f +#define regSEM_REGISTER_LAST_PART2_BASE_IDX 0 +#define regIH_VIRT_RESET_REQ 0x0120 +#define regIH_VIRT_RESET_REQ_BASE_IDX 0 +#define regIH_CLIENT_CFG 0x0121 +#define regIH_CLIENT_CFG_BASE_IDX 0 +#define regIH_RING1_CLIENT_CFG_INDEX 0x0122 +#define regIH_RING1_CLIENT_CFG_INDEX_BASE_IDX 0 +#define regIH_RING1_CLIENT_CFG_DATA 0x0123 +#define regIH_RING1_CLIENT_CFG_DATA_BASE_IDX 0 +#define regIH_CLIENT_CFG_INDEX 0x0124 +#define regIH_CLIENT_CFG_INDEX_BASE_IDX 0 +#define regIH_CLIENT_CFG_DATA 0x0125 +#define regIH_CLIENT_CFG_DATA_BASE_IDX 0 +#define regIH_CLIENT_CFG_DATA2 0x0126 +#define regIH_CLIENT_CFG_DATA2_BASE_IDX 0 +#define regIH_CID_REMAP_INDEX 0x0127 +#define regIH_CID_REMAP_INDEX_BASE_IDX 0 +#define regIH_CID_REMAP_DATA 0x0128 +#define regIH_CID_REMAP_DATA_BASE_IDX 0 +#define regIH_CHICKEN 0x0129 +#define regIH_CHICKEN_BASE_IDX 0 +#define regIH_INT_DROP_CNTL 0x012a +#define regIH_INT_DROP_CNTL_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_VALUE0 0x012b +#define regIH_INT_DROP_MATCH_VALUE0_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_VALUE1 0x012c +#define regIH_INT_DROP_MATCH_VALUE1_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_MASK0 0x012d +#define regIH_INT_DROP_MATCH_MASK0_BASE_IDX 0 +#define regIH_INT_DROP_MATCH_MASK1 0x012e +#define regIH_INT_DROP_MATCH_MASK1_BASE_IDX 0 +#define regIH_MMHUB_CNTL 0x0147 +#define regIH_MMHUB_CNTL_BASE_IDX 0 +#define regIH_REGISTER_LAST_PART1 0x019f +#define regIH_REGISTER_LAST_PART1_BASE_IDX 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_1_0_sh_mask.h new file mode 100644 index 0000000000000..0bc2f25968ea0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/oss/osssys_7_1_0_sh_mask.h @@ -0,0 +1,1024 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _osssys_7_1_0_SH_MASK_HEADER +#define _osssys_7_1_0_SH_MASK_HEADER + + +// addressBlock: osssys_osssysdec +//IH_VMID_0_LUT +#define IH_VMID_0_LUT__PASID__SHIFT 0x0 +#define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_1_LUT +#define IH_VMID_1_LUT__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_2_LUT +#define IH_VMID_2_LUT__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_3_LUT +#define IH_VMID_3_LUT__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_4_LUT +#define IH_VMID_4_LUT__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_5_LUT +#define IH_VMID_5_LUT__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_6_LUT +#define IH_VMID_6_LUT__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_7_LUT +#define IH_VMID_7_LUT__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_8_LUT +#define IH_VMID_8_LUT__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_9_LUT +#define IH_VMID_9_LUT__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_10_LUT +#define IH_VMID_10_LUT__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_11_LUT +#define IH_VMID_11_LUT__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_12_LUT +#define IH_VMID_12_LUT__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_13_LUT +#define IH_VMID_13_LUT__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_14_LUT +#define IH_VMID_14_LUT__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_15_LUT +#define IH_VMID_15_LUT__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL +//IH_VMID_0_LUT_MM +#define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_1_LUT_MM +#define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_2_LUT_MM +#define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_3_LUT_MM +#define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_4_LUT_MM +#define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_5_LUT_MM +#define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_6_LUT_MM +#define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_7_LUT_MM +#define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_8_LUT_MM +#define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_9_LUT_MM +#define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_10_LUT_MM +#define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_11_LUT_MM +#define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_12_LUT_MM +#define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_13_LUT_MM +#define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_14_LUT_MM +#define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_VMID_15_LUT_MM +#define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 +#define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL +//IH_COOKIE_0 +#define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 +#define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 +#define IH_COOKIE_0__RING_ID__SHIFT 0x10 +#define IH_COOKIE_0__VM_ID__SHIFT 0x18 +#define IH_COOKIE_0__RESERVED__SHIFT 0x1c +#define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f +#define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL +#define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L +#define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L +#define IH_COOKIE_0__VM_ID_MASK 0x0F000000L +#define IH_COOKIE_0__RESERVED_MASK 0x70000000L +#define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L +//IH_COOKIE_1 +#define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 +#define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL +//IH_COOKIE_2 +#define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 +#define IH_COOKIE_2__RESERVED__SHIFT 0x10 +#define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f +#define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL +#define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L +#define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L +//IH_COOKIE_3 +#define IH_COOKIE_3__PAS_ID__SHIFT 0x0 +#define IH_COOKIE_3__RESERVED__SHIFT 0x10 +#define IH_COOKIE_3__FORCE_TO_PF__SHIFT 0x1e +#define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f +#define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL +#define IH_COOKIE_3__RESERVED_MASK 0x3FFF0000L +#define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L +//IH_COOKIE_4 +#define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 +#define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL +//IH_COOKIE_5 +#define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 +#define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL +//IH_COOKIE_6 +#define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 +#define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL +//IH_COOKIE_7 +#define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 +#define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL +//IH_VMID_LUT_INDEX +#define IH_VMID_LUT_INDEX__INDEX__SHIFT 0x0 +#define IH_VMID_LUT_INDEX__INDEX_MASK 0x0000000FL +//IH_REGISTER_LAST_PART0 +#define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 +#define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL +//IH_RB_CNTL +#define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 +#define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa +#define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb +#define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 +#define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 +#define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 +#define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 +#define IH_RB_CNTL__MC_RO__SHIFT 0x16 +#define IH_RB_CNTL__MC_VMID__SHIFT 0x18 +#define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L +#define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L +#define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L +#define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L +#define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L +#define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L +#define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L +#define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L +#define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L +#define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L +#define IH_RB_CNTL__MC_RO_MASK 0x00400000L +#define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L +#define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L +#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//IH_RB_RPTR +#define IH_RB_RPTR__OFFSET__SHIFT 0x2 +#define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL +//IH_RB_WPTR +#define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L +#define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL +#define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L +#define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L +//IH_RB_BASE +#define IH_RB_BASE__ADDR__SHIFT 0x0 +#define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//IH_RB_BASE_HI +#define IH_RB_BASE_HI__ADDR__SHIFT 0x0 +#define IH_RB_BASE_HI__ADDR_MASK 0x0001FFFFL +//IH_RB_WPTR_ADDR_HI +#define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x01FFFFFFL +//IH_RB_WPTR_ADDR_LO +#define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//IH_DOORBELL_RPTR +#define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL +#define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L +//IH_DOORBELL_RETRY_CAM +#define IH_DOORBELL_RETRY_CAM__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RETRY_CAM__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RETRY_CAM__OFFSET_MASK 0x03FFFFFFL +#define IH_DOORBELL_RETRY_CAM__ENABLE_MASK 0x10000000L +//IH_RB_CNTL_RING1 +#define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 +#define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 +#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 +#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa +#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb +#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 +#define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 +#define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 +#define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 +#define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 +#define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +#define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L +#define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL +#define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L +#define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L +#define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L +#define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L +#define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L +#define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L +#define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L +#define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L +#define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L +#define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L +//IH_RB_RPTR_RING1 +#define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 +#define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL +//IH_RB_WPTR_RING1 +#define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 +#define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 +#define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 +#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 +#define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L +#define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL +#define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L +#define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L +//IH_RB_BASE_RING1 +#define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 +#define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL +//IH_RB_BASE_HI_RING1 +#define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 +#define IH_RB_BASE_HI_RING1__ADDR_MASK 0x0001FFFFL +//IH_DOORBELL_RPTR_RING1 +#define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 +#define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c +#define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL +#define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L +//IH_RETRY_CAM_ACK +#define IH_RETRY_CAM_ACK__INDEX__SHIFT 0x0 +#define IH_RETRY_CAM_ACK__INDEX_MASK 0x000003FFL +//IH_VERSION +#define IH_VERSION__MINVER__SHIFT 0x0 +#define IH_VERSION__MAJVER__SHIFT 0x8 +#define IH_VERSION__REV__SHIFT 0x10 +#define IH_VERSION__MINVER_MASK 0x0000007FL +#define IH_VERSION__MAJVER_MASK 0x00007F00L +#define IH_VERSION__REV_MASK 0x003F0000L +//IH_CNTL +#define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 +#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 +#define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 +#define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 +#define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL +#define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L +#define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x0001FF00L +#define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L +//IH_CLK_CTRL +#define IH_CLK_CTRL__IH_VF_CLK_GATING_MODE__SHIFT 0x15 +#define IH_CLK_CTRL__IH_RAS_CLK_SOFT_OVERRIDE__SHIFT 0x16 +#define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x17 +#define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE__SHIFT 0x18 +#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x19 +#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE__SHIFT 0x1a +#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b +#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c +#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d +#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e +#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f +#define IH_CLK_CTRL__IH_RAS_CLK_SOFT_OVERRIDE_MASK 0x00400000L +#define IH_CLK_CTRL__IH_PASID_LUT_MEM_CLK_SOFT_OVERRIDE_MASK 0x00800000L +#define IH_CLK_CTRL__MSI_STORM_COUNTER_CLK_SOFT_OVERRIDE_MASK 0x01000000L +#define IH_CLK_CTRL__IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE_MASK 0x02000000L +#define IH_CLK_CTRL__IH_BUFFER_MEM_CLK_SOFT_OVERRIDE_MASK 0x04000000L +#define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L +#define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L +#define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L +#define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L +#define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L +//IH_STORM_CLIENT_LIST_CNTL +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L +#define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L +//IH_LIMIT_INT_RATE_CNTL +#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 +#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 +#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 +#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 +#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 +#define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L +#define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL +#define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L +#define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L +#define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L +//IH_RETRY_INT_CAM_CNTL +#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE__SHIFT 0x0 +#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE__SHIFT 0x8 +#define IH_RETRY_INT_CAM_CNTL__ENABLE__SHIFT 0x10 +#define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE__SHIFT 0x11 +#define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE__SHIFT 0x12 +#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE__SHIFT 0x14 +#define IH_RETRY_INT_CAM_CNTL__CAM_SIZE_MASK 0x0000001FL +#define IH_RETRY_INT_CAM_CNTL__BACK_PRESSURE_SKID_VALUE_MASK 0x00003F00L +#define IH_RETRY_INT_CAM_CNTL__ENABLE_MASK 0x00010000L +#define IH_RETRY_INT_CAM_CNTL__MM_BACK_PRESSURE_ENABLE_MASK 0x00020000L +#define IH_RETRY_INT_CAM_CNTL__GC_BACK_PRESSURE_ENABLE_MASK 0x00040000L +#define IH_RETRY_INT_CAM_CNTL__PER_VF_ENTRY_SIZE_MASK 0x00300000L +//IH_MEM_POWER_CTRL +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN__SHIFT 0x0 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN__SHIFT 0x1 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN__SHIFT 0x2 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN__SHIFT 0x3 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS__SHIFT 0x4 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x7 +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN__SHIFT 0x10 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN__SHIFT 0x11 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN__SHIFT 0x12 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN__SHIFT 0x13 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS__SHIFT 0x14 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x17 +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0x1e +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_CTRL_EN_MASK 0x00000001L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_LS_EN_MASK 0x00000002L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DS_EN_MASK 0x00000004L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_SD_EN_MASK 0x00000008L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_IDLE_HYSTERESIS_MASK 0x00000070L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F80L +#define IH_MEM_POWER_CTRL__IH_BUFFER_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_CTRL_EN_MASK 0x00010000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_LS_EN_MASK 0x00020000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DS_EN_MASK 0x00040000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_SD_EN_MASK 0x00080000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_IDLE_HYSTERESIS_MASK 0x00700000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_UP_RECOVER_DELAY_MASK 0x3F800000L +#define IH_MEM_POWER_CTRL__IH_RETRY_INT_CAM_MEM_POWER_DOWN_ENTER_DELAY_MASK 0xC0000000L +//IH_MEM_POWER_CTRL2 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN__SHIFT 0x0 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN__SHIFT 0x1 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN__SHIFT 0x2 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN__SHIFT 0x3 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS__SHIFT 0x4 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY__SHIFT 0x7 +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY__SHIFT 0xe +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_CTRL_EN_MASK 0x00000001L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_LS_EN_MASK 0x00000002L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DS_EN_MASK 0x00000004L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_SD_EN_MASK 0x00000008L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_IDLE_HYSTERESIS_MASK 0x00000070L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_UP_RECOVER_DELAY_MASK 0x00003F80L +#define IH_MEM_POWER_CTRL2__IH_PASID_LUT_MEM_POWER_DOWN_ENTER_DELAY_MASK 0x0000C000L +//IH_CNTL2 +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL +#define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L +//IH_STATUS +#define IH_STATUS__IDLE__SHIFT 0x0 +#define IH_STATUS__INPUT_IDLE__SHIFT 0x1 +#define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 +#define IH_STATUS__RB_FULL__SHIFT 0x3 +#define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 +#define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 +#define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 +#define IH_STATUS__MC_WR_STALL__SHIFT 0x7 +#define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 +#define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 +#define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa +#define IH_STATUS__RB1_FULL__SHIFT 0xc +#define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd +#define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe +#define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 +#define IH_STATUS__RETRY_INT_CAM_IDLE__SHIFT 0x13 +#define IH_STATUS__ZSTATES_FENCE__SHIFT 0x14 +#define IH_STATUS__IH_BUFFER_MEM_POWER_GATED__SHIFT 0x15 +#define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED__SHIFT 0x16 +#define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED__SHIFT 0x17 +#define IH_STATUS__IDLE_MASK 0x00000001L +#define IH_STATUS__INPUT_IDLE_MASK 0x00000002L +#define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L +#define IH_STATUS__RB_FULL_MASK 0x00000008L +#define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L +#define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L +#define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L +#define IH_STATUS__MC_WR_STALL_MASK 0x00000080L +#define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L +#define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L +#define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L +#define IH_STATUS__RB1_FULL_MASK 0x00001000L +#define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L +#define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L +#define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L +#define IH_STATUS__RETRY_INT_CAM_IDLE_MASK 0x00080000L +#define IH_STATUS__ZSTATES_FENCE_MASK 0x00100000L +#define IH_STATUS__IH_BUFFER_MEM_POWER_GATED_MASK 0x00200000L +#define IH_STATUS__IH_RETRY_INT_CAM_MEM_POWER_GATED_MASK 0x00400000L +#define IH_STATUS__IH_PASID_LUT_MEM_POWER_GATED_MASK 0x00800000L +//IH_PERFMON_CNTL +#define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 +#define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 +#define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 +#define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 +#define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 +#define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 +#define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L +#define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L +#define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x00000FFCL +#define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L +#define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L +#define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x0FFC0000L +//IH_PERFCOUNTER0_RESULT +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//IH_PERFCOUNTER1_RESULT +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 +#define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_VALUE_BIT_31_0 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_VALUE_BIT_63_32 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_VALUE_BIT_95_64 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL +//IH_DSM_MATCH_FIELD_CONTROL +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 +#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 +#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 +#define IH_DSM_MATCH_FIELD_CONTROL__DIEID_EN__SHIFT 0x7 +#define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L +#define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L +#define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L +#define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L +#define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L +#define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L +#define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L +#define IH_DSM_MATCH_FIELD_CONTROL__DIEID_EN_MASK 0x00000080L +//IH_DSM_MATCH_DATA_CONTROL +#define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 +#define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL +//IH_DSM_MATCH_FCN_ID +#define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x0 +#define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x7 +#define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001FL +#define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000080L +//IH_VF_RB_STATUS +#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x000000FFL +//IH_VF_RB_STATUS2 +#define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x000000FFL +//IH_VF_RB1_STATUS +#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 +#define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x000000FFL +//IH_VF_RB1_STATUS2 +#define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 +#define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x000000FFL +//IH_RB_STATUS +#define IH_RB_STATUS__RB_FULL__SHIFT 0x0 +#define IH_RB_STATUS__RB_FULL_DRAIN__SHIFT 0x1 +#define IH_RB_STATUS__RB_OVERFLOW__SHIFT 0x2 +#define IH_RB_STATUS__RB1_FULL__SHIFT 0x4 +#define IH_RB_STATUS__RB1_FULL_DRAIN__SHIFT 0x5 +#define IH_RB_STATUS__RB1_OVERFLOW__SHIFT 0x6 +#define IH_RB_STATUS__RB_FULL_MASK 0x00000001L +#define IH_RB_STATUS__RB_FULL_DRAIN_MASK 0x00000002L +#define IH_RB_STATUS__RB_OVERFLOW_MASK 0x00000004L +#define IH_RB_STATUS__RB1_FULL_MASK 0x00000010L +#define IH_RB_STATUS__RB1_FULL_DRAIN_MASK 0x00000020L +#define IH_RB_STATUS__RB1_OVERFLOW_MASK 0x00000040L +//IH_INT_FLOOD_CNTL +#define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 +#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 +#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_MODE__SHIFT 0x4 +#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x5 +#define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L +#define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L +#define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000020L +//IH_RB0_INT_FLOOD_STATUS +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x000000FFL +#define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L +//IH_RB1_INT_FLOOD_STATUS +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x000000FFL +#define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L +//IH_INT_FLOOD_STATUS +#define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1d +#define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e +#define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x1F000000L +#define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x20000000L +#define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L +//IH_INT_FLAGS +#define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 +#define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 +#define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 +#define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 +#define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 +#define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 +#define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 +#define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 +#define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 +#define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 +#define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa +#define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb +#define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc +#define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd +#define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe +#define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf +#define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 +#define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 +#define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 +#define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 +#define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 +#define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 +#define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 +#define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 +#define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 +#define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 +#define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a +#define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b +#define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c +#define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d +#define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e +#define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f +#define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L +#define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L +#define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L +#define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L +#define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L +#define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L +#define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L +#define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L +#define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L +#define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L +#define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L +#define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L +#define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L +#define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L +#define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L +#define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L +#define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L +#define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L +#define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L +#define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L +#define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L +#define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L +#define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L +#define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L +#define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L +#define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L +#define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L +#define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L +#define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L +#define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L +#define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L +#define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L +//IH_SCRATCH +#define IH_SCRATCH__DATA__SHIFT 0x0 +#define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL +//IH_CLIENT_CREDIT_ERROR +#define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa +#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb +#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc +#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd +#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe +#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf +#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 +#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a +#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b +#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c +#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d +#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e +#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f +#define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L +#define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L +//IH_GPU_IOV_VIOLATION_LOG +#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x16 +#define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x17 +#define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x18 +#define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00400000L +#define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00800000L +#define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x1F000000L +//IH_GPU_IOV_VIOLATION_LOG2 +#define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define IH_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL +//IH_COOKIE_REC_VIOLATION_LOG +#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x8 +#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x10 +#define IH_COOKIE_REC_VIOLATION_LOG__DIE_ID__SHIFT 0x1a +#define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x0000FF00L +#define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0x03FF0000L +#define IH_COOKIE_REC_VIOLATION_LOG__DIE_ID_MASK 0x3C000000L +//IH_CREDIT_STATUS +#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 +#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 +#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 +#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 +#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 +#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 +#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 +#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 +#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 +#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa +#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb +#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc +#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd +#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe +#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf +#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 +#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 +#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 +#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 +#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 +#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 +#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 +#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 +#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 +#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 +#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a +#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b +#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c +#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d +#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e +#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f +#define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L +#define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L +#define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L +#define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L +#define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L +#define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L +#define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L +#define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L +#define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L +#define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L +#define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L +#define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L +#define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L +#define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L +#define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L +#define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L +#define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L +#define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L +#define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L +#define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L +#define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L +#define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L +#define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L +#define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L +#define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L +#define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L +#define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L +#define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L +#define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L +#define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L +#define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L +//IH_MMHUB_ERROR +#define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 +#define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 +#define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 +#define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 +#define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 +#define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 +#define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L +#define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L +#define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L +#define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L +#define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L +#define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L +//IH_VF_RB_STATUS3 +#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS3__RB_OVERFLOW_VF_MASK 0x000000FFL +//IH_VF_RB_STATUS4 +#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF__SHIFT 0x0 +#define IH_VF_RB_STATUS4__BIF_INTERRUPT_LINE_VF_MASK 0x000000FFL +//IH_VF_RB1_STATUS3 +#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF__SHIFT 0x0 +#define IH_VF_RB1_STATUS3__RB_OVERFLOW_VF_MASK 0x000000FFL +//IH_MSI_STORM_CTRL +#define IH_MSI_STORM_CTRL__DELAY__SHIFT 0x0 +#define IH_MSI_STORM_CTRL__DELAY_MASK 0x00000FFFL +//IH_MSI_STORM_CLIENT_INDEX +#define IH_MSI_STORM_CLIENT_INDEX__INDEX__SHIFT 0x0 +#define IH_MSI_STORM_CLIENT_INDEX__INDEX_MASK 0x00000007L +//IH_MSI_STORM_CLIENT_DATA +#define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID__SHIFT 0x0 +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID__SHIFT 0x8 +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 +#define IH_MSI_STORM_CLIENT_DATA__UTCL2_PAGE_FAULT_CONTEXTID_MATCH_ENABLE__SHIFT 0x11 +#define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID__SHIFT 0x1f +#define IH_MSI_STORM_CLIENT_DATA__CLIENT_ID_MASK 0x000000FFL +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MASK 0x0000FF00L +#define IH_MSI_STORM_CLIENT_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L +#define IH_MSI_STORM_CLIENT_DATA__ENTRY_VALID_MASK 0x80000000L +//IH_LAST_INT_INFO0 +#define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 +#define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 +#define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 +#define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 +#define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f +#define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL +#define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L +#define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L +#define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L +#define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L +//IH_LAST_INT_INFO1 +#define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 +#define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL +//IH_LAST_INT_INFO2 +#define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 +#define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 +#define IH_LAST_INT_INFO2__VF__SHIFT 0x17 +#define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL +#define IH_LAST_INT_INFO2__VF_ID_MASK 0x001F0000L +#define IH_LAST_INT_INFO2__VF_MASK 0x00800000L +//IH_REGISTER_LAST_PART2 +#define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 +#define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL +//SEM_MAILBOX +#define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 +#define SEM_MAILBOX__RESERVED__SHIFT 0x10 +#define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL +#define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L +//SEM_MAILBOX_CLEAR +#define SEM_MAILBOX_CLEAR__CLEAR__SHIFT 0x0 +#define SEM_MAILBOX_CLEAR__RESERVED__SHIFT 0x10 +#define SEM_MAILBOX_CLEAR__CLEAR_MASK 0x0000FFFFL +#define SEM_MAILBOX_CLEAR__RESERVED_MASK 0xFFFF0000L +//SEM_REGISTER_LAST_PART2 +#define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 +#define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL +//IH_VIRT_RESET_REQ +#define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define IH_VIRT_RESET_REQ__VF_MASK 0x000000FFL +#define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L +//IH_CLIENT_CFG +#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 +#define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000007FL +//IH_RING1_CLIENT_CFG_INDEX +#define IH_RING1_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 +#define IH_RING1_CLIENT_CFG_INDEX__INDEX_MASK 0x00000007L +//IH_RING1_CLIENT_CFG_DATA +#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID__SHIFT 0x0 +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID__SHIFT 0x8 +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE__SHIFT 0x10 +#define IH_RING1_CLIENT_CFG_DATA__CLIENT_ID_MASK 0x000000FFL +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MASK 0x0000FF00L +#define IH_RING1_CLIENT_CFG_DATA__SOURCE_ID_MATCH_ENABLE_MASK 0x00010000L +//IH_CLIENT_CFG_INDEX +#define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 +#define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL +//IH_CLIENT_CFG_DATA +#define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 +#define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 +#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE__SHIFT 0x19 +#define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L +#define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L +#define IH_CLIENT_CFG_DATA__INTERFACE_TYPE_MASK 0x02000000L +//IH_CLIENT_CFG_DATA2 +#define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR__SHIFT 0x0 +#define IH_CLIENT_CFG_DATA2__CREDIT_RETURN_ADDR_MASK 0xFFFFFFFFL +//IH_CID_REMAP_INDEX +#define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 +#define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L +//IH_CID_REMAP_DATA +#define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 +#define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 +#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x18 +#define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL +#define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0003FF00L +#define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0xFF000000L +//IH_CHICKEN +#define IH_CHICKEN__DBGU_TRIGGER_ENABLE__SHIFT 0x1 +#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE__SHIFT 0x3 +#define IH_CHICKEN__MC_SPACE_GPA_ENABLE__SHIFT 0x4 +#define IH_CHICKEN__REG_FIREWALL_ENABLE__SHIFT 0x5 +#define IH_CHICKEN__DBGU_TRIGGER_ENABLE_MASK 0x00000002L +#define IH_CHICKEN__MC_SPACE_FBPA_ENABLE_MASK 0x00000008L +#define IH_CHICKEN__MC_SPACE_GPA_ENABLE_MASK 0x00000010L +#define IH_CHICKEN__REG_FIREWALL_ENABLE_MASK 0x00000020L +//IH_INT_DROP_CNTL +#define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 +#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 +#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 +#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 +#define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 +#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 +#define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 +#define IH_INT_DROP_CNTL__GCUTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 +#define IH_INT_DROP_CNTL__MMUTCL2_RETRY_INT_DROP_EN__SHIFT 0x9 +#define IH_INT_DROP_CNTL__GCUTCL2_FAULT_INT_DROP_EN__SHIFT 0xa +#define IH_INT_DROP_CNTL__MMUTCL2_FAULT_INT_DROP_EN__SHIFT 0xb +#define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 +#define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L +#define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L +#define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L +#define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L +#define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L +#define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L +#define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L +#define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L +//IH_INT_DROP_MATCH_VALUE0 +#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 +#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 +#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 +#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 +#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 +#define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL +#define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L +#define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x001F0000L +#define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L +#define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L +//IH_INT_DROP_MATCH_VALUE1 +#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 +#define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL +//IH_INT_DROP_MATCH_MASK0 +#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 +#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 +#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 +#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 +#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 +#define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL +#define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L +#define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x001F0000L +#define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L +#define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L +//IH_INT_DROP_MATCH_MASK1 +#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 +#define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL +//IH_MMHUB_CNTL +#define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 +#define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 +#define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc +#define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL +#define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000F00L +#define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x0000F000L +//IH_REGISTER_LAST_PART1 +#define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 +#define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_offset.h new file mode 100644 index 0000000000000..54e8fd6c72488 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_offset.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _smuio_15_0_0_OFFSET_HEADER +#define _smuio_15_0_0_OFFSET_HEADER + + + +// addressBlock: smuio_smuio_misc_SmuSmuioDec +// base address: 0x5a000 +#define regSMUIO_MCM_CONFIG 0x0023 +#define regSMUIO_MCM_CONFIG_BASE_IDX 0 +#define regIP_DISCOVERY_VERSION 0x0000 +#define regIP_DISCOVERY_VERSION_BASE_IDX 1 +#define regSCRATCH_REGISTER0 0x01c6 +#define regSCRATCH_REGISTER0_BASE_IDX 1 +#define regSCRATCH_REGISTER1 0x01c7 +#define regSCRATCH_REGISTER1_BASE_IDX 1 +#define regSCRATCH_REGISTER2 0x01c8 +#define regSCRATCH_REGISTER2_BASE_IDX 1 +#define regSCRATCH_REGISTER3 0x01c9 +#define regSCRATCH_REGISTER3_BASE_IDX 1 +#define regSCRATCH_REGISTER4 0x01ca +#define regSCRATCH_REGISTER4_BASE_IDX 1 +#define regSCRATCH_REGISTER5 0x01cb +#define regSCRATCH_REGISTER5_BASE_IDX 1 +#define regSCRATCH_REGISTER6 0x01cc +#define regSCRATCH_REGISTER6_BASE_IDX 1 +#define regSCRATCH_REGISTER7 0x01cd +#define regSCRATCH_REGISTER7_BASE_IDX 1 +#define regIO_SMUIO_PINSTRAP 0x01ce +#define regIO_SMUIO_PINSTRAP_BASE_IDX 1 + + +// addressBlock: smuio_smuio_reset_SmuSmuioDec +// base address: 0x5a300 +#define regSMUIO_GFX_MISC_CNTL 0x00c5 +#define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0 + + +// addressBlock: smuio_smuio_tsc_SmuSmuioDec +// base address: 0x5a8a0 +#define regPWROK_REFCLK_GAP_CYCLES 0x0028 +#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 +#define regGOLDEN_TSC_INCREMENT_UPPER 0x002b +#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 +#define regGOLDEN_TSC_INCREMENT_LOWER 0x002c +#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 +#define regGOLDEN_TSC_COUNT_UPPER 0x0030 +#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 +#define regGOLDEN_TSC_COUNT_LOWER 0x0031 +#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 +#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0032 +#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 +#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0033 +#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 +#define regSOC_GAP_PWROK 0x0034 +#define regSOC_GAP_PWROK_BASE_IDX 1 + + +// addressBlock: smuio_smuio_swtimer_SmuSmuioDec +// base address: 0x5aca8 +#define regPWR_VIRT_RESET_REQ 0x012a +#define regPWR_VIRT_RESET_REQ_BASE_IDX 1 +#define regPWR_DISP_TIMER_CONTROL 0x012b +#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER_DEBUG 0x012c +#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1 +#define regPWR_DISP_TIMER_ELAPSED_CONTROL 0x012d +#define regPWR_DISP_TIMER_ELAPSED_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER2_CONTROL 0x012e +#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER2_DEBUG 0x012f +#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1 +#define regPWR_DISP_TIMER2_ELAPSED_CONTROL 0x0130 +#define regPWR_DISP_TIMER2_ELAPSED_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0131 +#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 +#define regPWR_IH_CONTROL 0x0132 +#define regPWR_IH_CONTROL_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_sh_mask.h new file mode 100644 index 0000000000000..f10e702bf5e90 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_sh_mask.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _smuio_15_0_0_SH_MASK_HEADER +#define _smuio_15_0_0_SH_MASK_HEADER + + +// addressBlock: smuio_smuio_misc_SmuSmuioDec +//SMUIO_MCM_CONFIG +#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 +#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 +#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 +#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 +#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 +#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x12 +#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L +#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000003CL +#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00000100L +#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L +#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L +#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00040000L +//IP_DISCOVERY_VERSION +#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 +#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER0 +#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 +#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER1 +#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 +#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER2 +#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 +#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER3 +#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 +#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER4 +#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 +#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER5 +#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 +#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER6 +#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 +#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER7 +#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 +#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL +//IO_SMUIO_PINSTRAP +#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN__SHIFT 0x0 +#define IO_SMUIO_PINSTRAP__AUD__SHIFT 0x3 +#define IO_SMUIO_PINSTRAP__AUD_PORT_CONN_MASK 0x00000007L +#define IO_SMUIO_PINSTRAP__AUD_MASK 0x00000018L + + +// addressBlock: smuio_smuio_reset_SmuSmuioDec +//SMUIO_GFX_MISC_CNTL +#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0 +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 +#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L +#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L + + +// addressBlock: smuio_smuio_tsc_SmuSmuioDec +//PWROK_REFCLK_GAP_CYCLES +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L +//GOLDEN_TSC_INCREMENT_UPPER +#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 +#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL +//GOLDEN_TSC_INCREMENT_LOWER +#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 +#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL +//GOLDEN_TSC_COUNT_UPPER +#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 +#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL +//GOLDEN_TSC_COUNT_LOWER +#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 +#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL +//SOC_GOLDEN_TSC_SHADOW_UPPER +#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 +#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL +//SOC_GOLDEN_TSC_SHADOW_LOWER +#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 +#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL +//SOC_GAP_PWROK +#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 +#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L + + +// addressBlock: smuio_smuio_swtimer_SmuSmuioDec +//PWR_VIRT_RESET_REQ +#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f +#define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL +#define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L +//PWR_DISP_TIMER_CONTROL +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L +//PWR_DISP_TIMER_DEBUG +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L +//PWR_DISP_TIMER_ELAPSED_CONTROL +#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE_MASK 0x02000000L +//PWR_DISP_TIMER2_CONTROL +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L +//PWR_DISP_TIMER2_DEBUG +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L +//PWR_DISP_TIMER2_ELAPSED_CONTROL +#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_ELAPSED_TIME_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER2_ELAPSED_CONTROL__DISP_TIMER_COMP_ENABLE_MASK 0x02000000L +//PWR_DISP_TIMER_GLOBAL_CONTROL +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L +//PWR_IH_CONTROL +#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 +#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 +#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 +#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f +#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL +#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L +#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L +#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h new file mode 100644 index 0000000000000..f17a6c2bd70b0 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_offset.h @@ -0,0 +1,512 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _smuio_15_0_8_OFFSET_HEADER +#define _smuio_15_0_8_OFFSET_HEADER + + + +// addressBlock: smuio_smuio_tsc_SmuSmuioDec +// base address: 0x5a8a0 +#define regPWROK_REFCLK_GAP_CYCLES 0x0028 +#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1 +#define regGOLDEN_TSC_INCREMENT_UPPER 0x002b +#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1 +#define regGOLDEN_TSC_INCREMENT_LOWER 0x002c +#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1 +#define regGOLDEN_TSC_COUNT_UPPER 0x0030 +#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1 +#define regGOLDEN_TSC_COUNT_LOWER 0x0031 +#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1 +#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0032 +#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1 +#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0033 +#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1 +#define regSOC_GAP_PWROK 0x0034 +#define regSOC_GAP_PWROK_BASE_IDX 1 + + +// addressBlock: smuio_smuio_swtimer_SmuSmuioDec +// base address: 0x5aca8 +#define regPWR_VIRT_RESET_REQ 0x012a +#define regPWR_VIRT_RESET_REQ_BASE_IDX 1 +#define regPWR_DISP_TIMER_CONTROL 0x012b +#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER_DEBUG 0x012c +#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1 +#define regPWR_DISP_TIMER2_CONTROL 0x012d +#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1 +#define regPWR_DISP_TIMER2_DEBUG 0x012e +#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1 +#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x012f +#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1 +#define regPWR_IH_CONTROL 0x0130 +#define regPWR_IH_CONTROL_BASE_IDX 1 + + +// addressBlock: smuio_smuio_misc_SmuSmuioDec +// base address: 0x5a000 +#define regSMUIO_MCM_CONFIG 0x0023 +#define regSMUIO_MCM_CONFIG_BASE_IDX 0 +#define regIP_DISCOVERY_VERSION 0x0000 +#define regIP_DISCOVERY_VERSION_BASE_IDX 1 +#define regSCRATCH_REGISTER0 0x01c9 +#define regSCRATCH_REGISTER0_BASE_IDX 1 +#define regSCRATCH_REGISTER1 0x01ca +#define regSCRATCH_REGISTER1_BASE_IDX 1 +#define regSCRATCH_REGISTER2 0x01cb +#define regSCRATCH_REGISTER2_BASE_IDX 1 +#define regSCRATCH_REGISTER3 0x01cc +#define regSCRATCH_REGISTER3_BASE_IDX 1 +#define regSCRATCH_REGISTER4 0x01cd +#define regSCRATCH_REGISTER4_BASE_IDX 1 +#define regSCRATCH_REGISTER5 0x01ce +#define regSCRATCH_REGISTER5_BASE_IDX 1 +#define regSCRATCH_REGISTER6 0x01cf +#define regSCRATCH_REGISTER6_BASE_IDX 1 +#define regSCRATCH_REGISTER7 0x01d0 +#define regSCRATCH_REGISTER7_BASE_IDX 1 + + +// addressBlock: smuio_smuio_i2c_SmuSmuioDec +// base address: 0x5a100 +#define regCKSVII2C_IC_CON 0x0040 +#define regCKSVII2C_IC_CON_BASE_IDX 0 +#define regCKSVII2C_IC_TAR 0x0041 +#define regCKSVII2C_IC_TAR_BASE_IDX 0 +#define regCKSVII2C_IC_SAR 0x0042 +#define regCKSVII2C_IC_SAR_BASE_IDX 0 +#define regCKSVII2C_IC_HS_MADDR 0x0043 +#define regCKSVII2C_IC_HS_MADDR_BASE_IDX 0 +#define regCKSVII2C_IC_DATA_CMD 0x0044 +#define regCKSVII2C_IC_DATA_CMD_BASE_IDX 0 +#define regCKSVII2C_IC_SS_SCL_HCNT 0x0045 +#define regCKSVII2C_IC_SS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C_IC_SS_SCL_LCNT 0x0046 +#define regCKSVII2C_IC_SS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C_IC_FS_SCL_HCNT 0x0047 +#define regCKSVII2C_IC_FS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C_IC_FS_SCL_LCNT 0x0048 +#define regCKSVII2C_IC_FS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C_IC_HS_SCL_HCNT 0x0049 +#define regCKSVII2C_IC_HS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C_IC_HS_SCL_LCNT 0x004a +#define regCKSVII2C_IC_HS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C_IC_INTR_STAT 0x004b +#define regCKSVII2C_IC_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C_IC_INTR_MASK 0x004c +#define regCKSVII2C_IC_INTR_MASK_BASE_IDX 0 +#define regCKSVII2C_IC_RAW_INTR_STAT 0x004d +#define regCKSVII2C_IC_RAW_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C_IC_RX_TL 0x004e +#define regCKSVII2C_IC_RX_TL_BASE_IDX 0 +#define regCKSVII2C_IC_TX_TL 0x004f +#define regCKSVII2C_IC_TX_TL_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_INTR 0x0050 +#define regCKSVII2C_IC_CLR_INTR_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RX_UNDER 0x0051 +#define regCKSVII2C_IC_CLR_RX_UNDER_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RX_OVER 0x0052 +#define regCKSVII2C_IC_CLR_RX_OVER_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_TX_OVER 0x0053 +#define regCKSVII2C_IC_CLR_TX_OVER_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RD_REQ 0x0054 +#define regCKSVII2C_IC_CLR_RD_REQ_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_TX_ABRT 0x0055 +#define regCKSVII2C_IC_CLR_TX_ABRT_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RX_DONE 0x0056 +#define regCKSVII2C_IC_CLR_RX_DONE_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_ACTIVITY 0x0057 +#define regCKSVII2C_IC_CLR_ACTIVITY_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_STOP_DET 0x0058 +#define regCKSVII2C_IC_CLR_STOP_DET_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_START_DET 0x0059 +#define regCKSVII2C_IC_CLR_START_DET_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_GEN_CALL 0x005a +#define regCKSVII2C_IC_CLR_GEN_CALL_BASE_IDX 0 +#define regCKSVII2C_IC_ENABLE 0x005b +#define regCKSVII2C_IC_ENABLE_BASE_IDX 0 +#define regCKSVII2C_IC_STATUS 0x005c +#define regCKSVII2C_IC_STATUS_BASE_IDX 0 +#define regCKSVII2C_IC_TXFLR 0x005d +#define regCKSVII2C_IC_TXFLR_BASE_IDX 0 +#define regCKSVII2C_IC_RXFLR 0x005e +#define regCKSVII2C_IC_RXFLR_BASE_IDX 0 +#define regCKSVII2C_IC_SDA_HOLD 0x005f +#define regCKSVII2C_IC_SDA_HOLD_BASE_IDX 0 +#define regCKSVII2C_IC_TX_ABRT_SOURCE 0x0060 +#define regCKSVII2C_IC_TX_ABRT_SOURCE_BASE_IDX 0 +#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY 0x0061 +#define regCKSVII2C_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 +#define regCKSVII2C_IC_DMA_CR 0x0062 +#define regCKSVII2C_IC_DMA_CR_BASE_IDX 0 +#define regCKSVII2C_IC_DMA_TDLR 0x0063 +#define regCKSVII2C_IC_DMA_TDLR_BASE_IDX 0 +#define regCKSVII2C_IC_DMA_RDLR 0x0064 +#define regCKSVII2C_IC_DMA_RDLR_BASE_IDX 0 +#define regCKSVII2C_IC_SDA_SETUP 0x0065 +#define regCKSVII2C_IC_SDA_SETUP_BASE_IDX 0 +#define regCKSVII2C_IC_ACK_GENERAL_CALL 0x0066 +#define regCKSVII2C_IC_ACK_GENERAL_CALL_BASE_IDX 0 +#define regCKSVII2C_IC_ENABLE_STATUS 0x0067 +#define regCKSVII2C_IC_ENABLE_STATUS_BASE_IDX 0 +#define regCKSVII2C_IC_FS_SPKLEN 0x0068 +#define regCKSVII2C_IC_FS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C_IC_HS_SPKLEN 0x0069 +#define regCKSVII2C_IC_HS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C_IC_CLR_RESTART_DET 0x006a +#define regCKSVII2C_IC_CLR_RESTART_DET_BASE_IDX 0 +#define regCKSVII2C_IC_COMP_PARAM_1 0x006d +#define regCKSVII2C_IC_COMP_PARAM_1_BASE_IDX 0 +#define regCKSVII2C_IC_COMP_VERSION 0x006e +#define regCKSVII2C_IC_COMP_VERSION_BASE_IDX 0 +#define regCKSVII2C_IC_COMP_TYPE 0x006f +#define regCKSVII2C_IC_COMP_TYPE_BASE_IDX 0 +#define regCKSVII2C1_IC_CON 0x0080 +#define regCKSVII2C1_IC_CON_BASE_IDX 0 +#define regCKSVII2C1_IC_TAR 0x0081 +#define regCKSVII2C1_IC_TAR_BASE_IDX 0 +#define regCKSVII2C1_IC_SAR 0x0082 +#define regCKSVII2C1_IC_SAR_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_MADDR 0x0083 +#define regCKSVII2C1_IC_HS_MADDR_BASE_IDX 0 +#define regCKSVII2C1_IC_DATA_CMD 0x0084 +#define regCKSVII2C1_IC_DATA_CMD_BASE_IDX 0 +#define regCKSVII2C1_IC_SS_SCL_HCNT 0x0085 +#define regCKSVII2C1_IC_SS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_SS_SCL_LCNT 0x0086 +#define regCKSVII2C1_IC_SS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_FS_SCL_HCNT 0x0087 +#define regCKSVII2C1_IC_FS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_FS_SCL_LCNT 0x0088 +#define regCKSVII2C1_IC_FS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_SCL_HCNT 0x0089 +#define regCKSVII2C1_IC_HS_SCL_HCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_SCL_LCNT 0x008a +#define regCKSVII2C1_IC_HS_SCL_LCNT_BASE_IDX 0 +#define regCKSVII2C1_IC_INTR_STAT 0x008b +#define regCKSVII2C1_IC_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C1_IC_INTR_MASK 0x008c +#define regCKSVII2C1_IC_INTR_MASK_BASE_IDX 0 +#define regCKSVII2C1_IC_RAW_INTR_STAT 0x008d +#define regCKSVII2C1_IC_RAW_INTR_STAT_BASE_IDX 0 +#define regCKSVII2C1_IC_RX_TL 0x008e +#define regCKSVII2C1_IC_RX_TL_BASE_IDX 0 +#define regCKSVII2C1_IC_TX_TL 0x008f +#define regCKSVII2C1_IC_TX_TL_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_INTR 0x0090 +#define regCKSVII2C1_IC_CLR_INTR_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RX_UNDER 0x0091 +#define regCKSVII2C1_IC_CLR_RX_UNDER_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RX_OVER 0x0092 +#define regCKSVII2C1_IC_CLR_RX_OVER_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_TX_OVER 0x0093 +#define regCKSVII2C1_IC_CLR_TX_OVER_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RD_REQ 0x0094 +#define regCKSVII2C1_IC_CLR_RD_REQ_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_TX_ABRT 0x0095 +#define regCKSVII2C1_IC_CLR_TX_ABRT_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RX_DONE 0x0096 +#define regCKSVII2C1_IC_CLR_RX_DONE_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_ACTIVITY 0x0097 +#define regCKSVII2C1_IC_CLR_ACTIVITY_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_STOP_DET 0x0098 +#define regCKSVII2C1_IC_CLR_STOP_DET_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_START_DET 0x0099 +#define regCKSVII2C1_IC_CLR_START_DET_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_GEN_CALL 0x009a +#define regCKSVII2C1_IC_CLR_GEN_CALL_BASE_IDX 0 +#define regCKSVII2C1_IC_ENABLE 0x009b +#define regCKSVII2C1_IC_ENABLE_BASE_IDX 0 +#define regCKSVII2C1_IC_STATUS 0x009c +#define regCKSVII2C1_IC_STATUS_BASE_IDX 0 +#define regCKSVII2C1_IC_TXFLR 0x009d +#define regCKSVII2C1_IC_TXFLR_BASE_IDX 0 +#define regCKSVII2C1_IC_RXFLR 0x009e +#define regCKSVII2C1_IC_RXFLR_BASE_IDX 0 +#define regCKSVII2C1_IC_SDA_HOLD 0x009f +#define regCKSVII2C1_IC_SDA_HOLD_BASE_IDX 0 +#define regCKSVII2C1_IC_TX_ABRT_SOURCE 0x00a0 +#define regCKSVII2C1_IC_TX_ABRT_SOURCE_BASE_IDX 0 +#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY 0x00a1 +#define regCKSVII2C1_IC_SLV_DATA_NACK_ONLY_BASE_IDX 0 +#define regCKSVII2C1_IC_DMA_CR 0x00a2 +#define regCKSVII2C1_IC_DMA_CR_BASE_IDX 0 +#define regCKSVII2C1_IC_DMA_TDLR 0x00a3 +#define regCKSVII2C1_IC_DMA_TDLR_BASE_IDX 0 +#define regCKSVII2C1_IC_DMA_RDLR 0x00a4 +#define regCKSVII2C1_IC_DMA_RDLR_BASE_IDX 0 +#define regCKSVII2C1_IC_SDA_SETUP 0x00a5 +#define regCKSVII2C1_IC_SDA_SETUP_BASE_IDX 0 +#define regCKSVII2C1_IC_ACK_GENERAL_CALL 0x00a6 +#define regCKSVII2C1_IC_ACK_GENERAL_CALL_BASE_IDX 0 +#define regCKSVII2C1_IC_ENABLE_STATUS 0x00a7 +#define regCKSVII2C1_IC_ENABLE_STATUS_BASE_IDX 0 +#define regCKSVII2C1_IC_FS_SPKLEN 0x00a8 +#define regCKSVII2C1_IC_FS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C1_IC_HS_SPKLEN 0x00a9 +#define regCKSVII2C1_IC_HS_SPKLEN_BASE_IDX 0 +#define regCKSVII2C1_IC_CLR_RESTART_DET 0x00aa +#define regCKSVII2C1_IC_CLR_RESTART_DET_BASE_IDX 0 +#define regCKSVII2C1_IC_COMP_PARAM_1 0x00ad +#define regCKSVII2C1_IC_COMP_PARAM_1_BASE_IDX 0 +#define regCKSVII2C1_IC_COMP_VERSION 0x00ae +#define regCKSVII2C1_IC_COMP_VERSION_BASE_IDX 0 +#define regCKSVII2C1_IC_COMP_TYPE 0x00af +#define regCKSVII2C1_IC_COMP_TYPE_BASE_IDX 0 +#define regSMUIO_PWRMGT 0x018c +#define regSMUIO_PWRMGT_BASE_IDX 0 + + +// addressBlock: smuio_smuio_rom_SmuSmuioDec +// base address: 0x5a380 +#define regROM_CNTL 0x00e0 +#define regROM_CNTL_BASE_IDX 0 +#define regPAGE_MIRROR_CNTL 0x00e1 +#define regPAGE_MIRROR_CNTL_BASE_IDX 0 +#define regROM_STATUS 0x00e2 +#define regROM_STATUS_BASE_IDX 0 +#define regCGTT_ROM_CLK_CTRL0 0x00e3 +#define regCGTT_ROM_CLK_CTRL0_BASE_IDX 0 +#define regROM_INDEX 0x00e4 +#define regROM_INDEX_BASE_IDX 0 +#define regROM_DATA 0x00e5 +#define regROM_DATA_BASE_IDX 0 +#define regROM_START 0x00e6 +#define regROM_START_BASE_IDX 0 +#define regROM_SW_CNTL 0x00e8 +#define regROM_SW_CNTL_BASE_IDX 0 +#define regROM_SW_STATUS 0x00e9 +#define regROM_SW_STATUS_BASE_IDX 0 +#define regROM_SW_COMMAND 0x00ea +#define regROM_SW_COMMAND_BASE_IDX 0 +#define regROM_SW_DATA_1 0x00ec +#define regROM_SW_DATA_1_BASE_IDX 0 +#define regROM_SW_DATA_2 0x00ed +#define regROM_SW_DATA_2_BASE_IDX 0 +#define regROM_SW_DATA_3 0x00ee +#define regROM_SW_DATA_3_BASE_IDX 0 +#define regROM_SW_DATA_4 0x00ef +#define regROM_SW_DATA_4_BASE_IDX 0 +#define regROM_SW_DATA_5 0x00f0 +#define regROM_SW_DATA_5_BASE_IDX 0 +#define regROM_SW_DATA_6 0x00f1 +#define regROM_SW_DATA_6_BASE_IDX 0 +#define regROM_SW_DATA_7 0x00f2 +#define regROM_SW_DATA_7_BASE_IDX 0 +#define regROM_SW_DATA_8 0x00f3 +#define regROM_SW_DATA_8_BASE_IDX 0 +#define regROM_SW_DATA_9 0x00f4 +#define regROM_SW_DATA_9_BASE_IDX 0 +#define regROM_SW_DATA_10 0x00f5 +#define regROM_SW_DATA_10_BASE_IDX 0 +#define regROM_SW_DATA_11 0x00f6 +#define regROM_SW_DATA_11_BASE_IDX 0 +#define regROM_SW_DATA_12 0x00f7 +#define regROM_SW_DATA_12_BASE_IDX 0 +#define regROM_SW_DATA_13 0x00f8 +#define regROM_SW_DATA_13_BASE_IDX 0 +#define regROM_SW_DATA_14 0x00f9 +#define regROM_SW_DATA_14_BASE_IDX 0 +#define regROM_SW_DATA_15 0x00fa +#define regROM_SW_DATA_15_BASE_IDX 0 +#define regROM_SW_DATA_16 0x00fb +#define regROM_SW_DATA_16_BASE_IDX 0 +#define regROM_SW_DATA_17 0x00fc +#define regROM_SW_DATA_17_BASE_IDX 0 +#define regROM_SW_DATA_18 0x00fd +#define regROM_SW_DATA_18_BASE_IDX 0 +#define regROM_SW_DATA_19 0x00fe +#define regROM_SW_DATA_19_BASE_IDX 0 +#define regROM_SW_DATA_20 0x00ff +#define regROM_SW_DATA_20_BASE_IDX 0 +#define regROM_SW_DATA_21 0x0100 +#define regROM_SW_DATA_21_BASE_IDX 0 +#define regROM_SW_DATA_22 0x0101 +#define regROM_SW_DATA_22_BASE_IDX 0 +#define regROM_SW_DATA_23 0x0102 +#define regROM_SW_DATA_23_BASE_IDX 0 +#define regROM_SW_DATA_24 0x0103 +#define regROM_SW_DATA_24_BASE_IDX 0 +#define regROM_SW_DATA_25 0x0104 +#define regROM_SW_DATA_25_BASE_IDX 0 +#define regROM_SW_DATA_26 0x0105 +#define regROM_SW_DATA_26_BASE_IDX 0 +#define regROM_SW_DATA_27 0x0106 +#define regROM_SW_DATA_27_BASE_IDX 0 +#define regROM_SW_DATA_28 0x0107 +#define regROM_SW_DATA_28_BASE_IDX 0 +#define regROM_SW_DATA_29 0x0108 +#define regROM_SW_DATA_29_BASE_IDX 0 +#define regROM_SW_DATA_30 0x0109 +#define regROM_SW_DATA_30_BASE_IDX 0 +#define regROM_SW_DATA_31 0x010a +#define regROM_SW_DATA_31_BASE_IDX 0 +#define regROM_SW_DATA_32 0x010b +#define regROM_SW_DATA_32_BASE_IDX 0 +#define regROM_SW_DATA_33 0x010c +#define regROM_SW_DATA_33_BASE_IDX 0 +#define regROM_SW_DATA_34 0x010d +#define regROM_SW_DATA_34_BASE_IDX 0 +#define regROM_SW_DATA_35 0x010e +#define regROM_SW_DATA_35_BASE_IDX 0 +#define regROM_SW_DATA_36 0x010f +#define regROM_SW_DATA_36_BASE_IDX 0 +#define regROM_SW_DATA_37 0x0110 +#define regROM_SW_DATA_37_BASE_IDX 0 +#define regROM_SW_DATA_38 0x0111 +#define regROM_SW_DATA_38_BASE_IDX 0 +#define regROM_SW_DATA_39 0x0112 +#define regROM_SW_DATA_39_BASE_IDX 0 +#define regROM_SW_DATA_40 0x0113 +#define regROM_SW_DATA_40_BASE_IDX 0 +#define regROM_SW_DATA_41 0x0114 +#define regROM_SW_DATA_41_BASE_IDX 0 +#define regROM_SW_DATA_42 0x0115 +#define regROM_SW_DATA_42_BASE_IDX 0 +#define regROM_SW_DATA_43 0x0116 +#define regROM_SW_DATA_43_BASE_IDX 0 +#define regROM_SW_DATA_44 0x0117 +#define regROM_SW_DATA_44_BASE_IDX 0 +#define regROM_SW_DATA_45 0x0118 +#define regROM_SW_DATA_45_BASE_IDX 0 +#define regROM_SW_DATA_46 0x0119 +#define regROM_SW_DATA_46_BASE_IDX 0 +#define regROM_SW_DATA_47 0x011a +#define regROM_SW_DATA_47_BASE_IDX 0 +#define regROM_SW_DATA_48 0x011b +#define regROM_SW_DATA_48_BASE_IDX 0 +#define regROM_SW_DATA_49 0x011c +#define regROM_SW_DATA_49_BASE_IDX 0 +#define regROM_SW_DATA_50 0x011d +#define regROM_SW_DATA_50_BASE_IDX 0 +#define regROM_SW_DATA_51 0x011e +#define regROM_SW_DATA_51_BASE_IDX 0 +#define regROM_SW_DATA_52 0x011f +#define regROM_SW_DATA_52_BASE_IDX 0 +#define regROM_SW_DATA_53 0x0120 +#define regROM_SW_DATA_53_BASE_IDX 0 +#define regROM_SW_DATA_54 0x0121 +#define regROM_SW_DATA_54_BASE_IDX 0 +#define regROM_SW_DATA_55 0x0122 +#define regROM_SW_DATA_55_BASE_IDX 0 +#define regROM_SW_DATA_56 0x0123 +#define regROM_SW_DATA_56_BASE_IDX 0 +#define regROM_SW_DATA_57 0x0124 +#define regROM_SW_DATA_57_BASE_IDX 0 +#define regROM_SW_DATA_58 0x0125 +#define regROM_SW_DATA_58_BASE_IDX 0 +#define regROM_SW_DATA_59 0x0126 +#define regROM_SW_DATA_59_BASE_IDX 0 +#define regROM_SW_DATA_60 0x0127 +#define regROM_SW_DATA_60_BASE_IDX 0 +#define regROM_SW_DATA_61 0x0128 +#define regROM_SW_DATA_61_BASE_IDX 0 +#define regROM_SW_DATA_62 0x0129 +#define regROM_SW_DATA_62_BASE_IDX 0 +#define regROM_SW_DATA_63 0x012a +#define regROM_SW_DATA_63_BASE_IDX 0 +#define regROM_SW_DATA_64 0x012b +#define regROM_SW_DATA_64_BASE_IDX 0 + + +// addressBlock: smuio_smuio_gpio_SmuSmuioDec +// base address: 0x5a500 +#define regSMU_GPIOPAD_SW_INT_STAT 0x0140 +#define regSMU_GPIOPAD_SW_INT_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MASK 0x0141 +#define regSMU_GPIOPAD_MASK_BASE_IDX 0 +#define regSMU_GPIOPAD_A 0x0142 +#define regSMU_GPIOPAD_A_BASE_IDX 0 +#define regSMU_GPIOPAD_TXIMPSEL 0x0143 +#define regSMU_GPIOPAD_TXIMPSEL_BASE_IDX 0 +#define regSMU_GPIOPAD_EN 0x0144 +#define regSMU_GPIOPAD_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_Y 0x0145 +#define regSMU_GPIOPAD_Y_BASE_IDX 0 +#define regSMU_GPIOPAD_RXEN 0x0146 +#define regSMU_GPIOPAD_RXEN_BASE_IDX 0 +#define regSMU_GPIOPAD_RCVR_SEL0 0x0147 +#define regSMU_GPIOPAD_RCVR_SEL0_BASE_IDX 0 +#define regSMU_GPIOPAD_RCVR_SEL1 0x0148 +#define regSMU_GPIOPAD_RCVR_SEL1_BASE_IDX 0 +#define regSMU_GPIOPAD_PU_EN 0x0149 +#define regSMU_GPIOPAD_PU_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_PD_EN 0x014a +#define regSMU_GPIOPAD_PD_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_PINSTRAPS 0x014b +#define regSMU_GPIOPAD_PINSTRAPS_BASE_IDX 0 +#define regDFT_PINSTRAPS 0x014c +#define regDFT_PINSTRAPS_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_STAT_EN 0x014d +#define regSMU_GPIOPAD_INT_STAT_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_STAT 0x014e +#define regSMU_GPIOPAD_INT_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_STAT_AK 0x014f +#define regSMU_GPIOPAD_INT_STAT_AK_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_EN 0x0150 +#define regSMU_GPIOPAD_INT_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_TYPE 0x0151 +#define regSMU_GPIOPAD_INT_TYPE_BASE_IDX 0 +#define regSMU_GPIOPAD_INT_POLARITY 0x0152 +#define regSMU_GPIOPAD_INT_POLARITY_BASE_IDX 0 +#define regSMUIO_PCC_GPIO_SELECT 0x0155 +#define regSMUIO_PCC_GPIO_SELECT_BASE_IDX 0 +#define regSMU_GPIOPAD_S0 0x0156 +#define regSMU_GPIOPAD_S0_BASE_IDX 0 +#define regSMU_GPIOPAD_S1 0x0157 +#define regSMU_GPIOPAD_S1_BASE_IDX 0 +#define regSMU_GPIOPAD_SCHMEN 0x0158 +#define regSMU_GPIOPAD_SCHMEN_BASE_IDX 0 +#define regSMU_GPIOPAD_SCL_EN 0x0159 +#define regSMU_GPIOPAD_SCL_EN_BASE_IDX 0 +#define regSMU_GPIOPAD_SDA_EN 0x015a +#define regSMU_GPIOPAD_SDA_EN_BASE_IDX 0 +#define regSMUIO_GPIO_INT0_SELECT 0x015b +#define regSMUIO_GPIO_INT0_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT1_SELECT 0x015c +#define regSMUIO_GPIO_INT1_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT2_SELECT 0x015d +#define regSMUIO_GPIO_INT2_SELECT_BASE_IDX 0 +#define regSMUIO_GPIO_INT3_SELECT 0x015e +#define regSMUIO_GPIO_INT3_SELECT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT0_STAT 0x015f +#define regSMU_GPIOPAD_MP_INT0_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT1_STAT 0x0160 +#define regSMU_GPIOPAD_MP_INT1_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT2_STAT 0x0161 +#define regSMU_GPIOPAD_MP_INT2_STAT_BASE_IDX 0 +#define regSMU_GPIOPAD_MP_INT3_STAT 0x0162 +#define regSMU_GPIOPAD_MP_INT3_STAT_BASE_IDX 0 +#define regSMIO_INDEX 0x0163 +#define regSMIO_INDEX_BASE_IDX 0 +#define regS0_VID_SMIO_CNTL 0x0164 +#define regS0_VID_SMIO_CNTL_BASE_IDX 0 +#define regS1_VID_SMIO_CNTL 0x0165 +#define regS1_VID_SMIO_CNTL_BASE_IDX 0 +#define regOPEN_DRAIN_SELECT 0x0166 +#define regOPEN_DRAIN_SELECT_BASE_IDX 0 +#define regSMIO_ENABLE 0x0167 +#define regSMIO_ENABLE_BASE_IDX 0 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_sh_mask.h new file mode 100644 index 0000000000000..78b1d5cf8835d --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_8_sh_mask.h @@ -0,0 +1,1113 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _smuio_15_0_8_SH_MASK_HEADER +#define _smuio_15_0_8_SH_MASK_HEADER + + +// addressBlock: smuio_smuio_tsc_SmuSmuioDec +//PWROK_REFCLK_GAP_CYCLES +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles__SHIFT 0x0 +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles__SHIFT 0x8 +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PreAssertion_clkgap_cycles_MASK 0x000000FFL +#define PWROK_REFCLK_GAP_CYCLES__Pwrok_PostAssertion_clkgap_cycles_MASK 0x0000FF00L +//GOLDEN_TSC_INCREMENT_UPPER +#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper__SHIFT 0x0 +#define GOLDEN_TSC_INCREMENT_UPPER__GoldenTscIncrementUpper_MASK 0x00FFFFFFL +//GOLDEN_TSC_INCREMENT_LOWER +#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower__SHIFT 0x0 +#define GOLDEN_TSC_INCREMENT_LOWER__GoldenTscIncrementLower_MASK 0xFFFFFFFFL +//GOLDEN_TSC_COUNT_UPPER +#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper__SHIFT 0x0 +#define GOLDEN_TSC_COUNT_UPPER__GoldenTscCountUpper_MASK 0x00FFFFFFL +//GOLDEN_TSC_COUNT_LOWER +#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower__SHIFT 0x0 +#define GOLDEN_TSC_COUNT_LOWER__GoldenTscCountLower_MASK 0xFFFFFFFFL +//SOC_GOLDEN_TSC_SHADOW_UPPER +#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper__SHIFT 0x0 +#define SOC_GOLDEN_TSC_SHADOW_UPPER__SocGoldenTscShadowUpper_MASK 0x00FFFFFFL +//SOC_GOLDEN_TSC_SHADOW_LOWER +#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower__SHIFT 0x0 +#define SOC_GOLDEN_TSC_SHADOW_LOWER__SocGoldenTscShadowLower_MASK 0xFFFFFFFFL +//SOC_GAP_PWROK +#define SOC_GAP_PWROK__soc_gap_pwrok__SHIFT 0x0 +#define SOC_GAP_PWROK__soc_gap_pwrok_MASK 0x00000001L + + +// addressBlock: smuio_smuio_swtimer_SmuSmuioDec +//PWR_VIRT_RESET_REQ +#define PWR_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define PWR_VIRT_RESET_REQ__PF_FLR__SHIFT 0x1f +#define PWR_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL +#define PWR_VIRT_RESET_REQ__PF_FLR_MASK 0x80000000L +//PWR_DISP_TIMER_CONTROL +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L +#define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L +//PWR_DISP_TIMER_DEBUG +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x00000004L +#define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L +//PWR_DISP_TIMER2_CONTROL +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01FFFFFFL +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x04000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x08000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000L +#define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000L +//PWR_DISP_TIMER2_DEBUG +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x00000001L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x00000002L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x00000004L +#define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xFFFFFF80L +//PWR_DISP_TIMER_GLOBAL_CONTROL +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN__SHIFT 0xa +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_WIDTH_MASK 0x000003FFL +#define PWR_DISP_TIMER_GLOBAL_CONTROL__DISP_TIMER_PULSE_EN_MASK 0x00000400L +//PWR_IH_CONTROL +#define PWR_IH_CONTROL__MAX_CREDIT__SHIFT 0x0 +#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK__SHIFT 0x5 +#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK__SHIFT 0x6 +#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN__SHIFT 0x1f +#define PWR_IH_CONTROL__MAX_CREDIT_MASK 0x0000001FL +#define PWR_IH_CONTROL__DISP_TIMER_TRIGGER_MASK_MASK 0x00000020L +#define PWR_IH_CONTROL__DISP_TIMER2_TRIGGER_MASK_MASK 0x00000040L +#define PWR_IH_CONTROL__PWR_IH_CLK_GATE_EN_MASK 0x80000000L + + +// addressBlock: smuio_smuio_misc_SmuSmuioDec +//SMUIO_MCM_CONFIG +#define SMUIO_MCM_CONFIG__DIE_ID__SHIFT 0x0 +#define SMUIO_MCM_CONFIG__PKG_TYPE__SHIFT 0x2 +#define SMUIO_MCM_CONFIG__SOCKET_ID__SHIFT 0x8 +#define SMUIO_MCM_CONFIG__CONSOLE_K__SHIFT 0x10 +#define SMUIO_MCM_CONFIG__CONSOLE_A__SHIFT 0x11 +#define SMUIO_MCM_CONFIG__PKG_SUBTYPE__SHIFT 0x12 +#define SMUIO_MCM_CONFIG__TOPOLOGY_ID__SHIFT 0x13 +#define SMUIO_MCM_CONFIG__PKG_TYPE_DFX__SHIFT 0x18 +#define SMUIO_MCM_CONFIG__DIE_ID_MASK 0x00000003L +#define SMUIO_MCM_CONFIG__PKG_TYPE_MASK 0x0000003CL +#define SMUIO_MCM_CONFIG__SOCKET_ID_MASK 0x00001F00L +#define SMUIO_MCM_CONFIG__CONSOLE_K_MASK 0x00010000L +#define SMUIO_MCM_CONFIG__CONSOLE_A_MASK 0x00020000L +#define SMUIO_MCM_CONFIG__PKG_SUBTYPE_MASK 0x00040000L +#define SMUIO_MCM_CONFIG__TOPOLOGY_ID_MASK 0x00F80000L +//IP_DISCOVERY_VERSION +#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION__SHIFT 0x0 +#define IP_DISCOVERY_VERSION__IP_DISCOVERY_VERSION_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER0 +#define SCRATCH_REGISTER0__ScratchPad0__SHIFT 0x0 +#define SCRATCH_REGISTER0__ScratchPad0_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER1 +#define SCRATCH_REGISTER1__ScratchPad1__SHIFT 0x0 +#define SCRATCH_REGISTER1__ScratchPad1_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER2 +#define SCRATCH_REGISTER2__ScratchPad2__SHIFT 0x0 +#define SCRATCH_REGISTER2__ScratchPad2_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER3 +#define SCRATCH_REGISTER3__ScratchPad3__SHIFT 0x0 +#define SCRATCH_REGISTER3__ScratchPad3_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER4 +#define SCRATCH_REGISTER4__ScratchPad4__SHIFT 0x0 +#define SCRATCH_REGISTER4__ScratchPad4_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER5 +#define SCRATCH_REGISTER5__ScratchPad5__SHIFT 0x0 +#define SCRATCH_REGISTER5__ScratchPad5_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER6 +#define SCRATCH_REGISTER6__ScratchPad6__SHIFT 0x0 +#define SCRATCH_REGISTER6__ScratchPad6_MASK 0xFFFFFFFFL +//SCRATCH_REGISTER7 +#define SCRATCH_REGISTER7__ScratchPad7__SHIFT 0x0 +#define SCRATCH_REGISTER7__ScratchPad7_MASK 0xFFFFFFFFL + + +// addressBlock: smuio_smuio_i2c_SmuSmuioDec +//CKSVII2C_IC_CON +#define CKSVII2C_IC_CON__IC_MASTER_MODE__SHIFT 0x0 +#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE__SHIFT 0x1 +#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE__SHIFT 0x3 +#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER__SHIFT 0x4 +#define CKSVII2C_IC_CON__IC_RESTART_EN__SHIFT 0x5 +#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE__SHIFT 0x6 +#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED__SHIFT 0x7 +#define CKSVII2C_IC_CON__TX_EMPTY_CTRL__SHIFT 0x8 +#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL__SHIFT 0x9 +#define CKSVII2C_IC_CON__BUS_CLEAR_FEATURE_CTRL__SHIFT 0xb +#define CKSVII2C_IC_CON__IC_MASTER_MODE_MASK 0x00000001L +#define CKSVII2C_IC_CON__IC_MAX_SPEED_MODE_MASK 0x00000006L +#define CKSVII2C_IC_CON__IC_10BITADDR_SLAVE_MASK 0x00000008L +#define CKSVII2C_IC_CON__IC_10BITADDR_MASTER_MASK 0x00000010L +#define CKSVII2C_IC_CON__IC_RESTART_EN_MASK 0x00000020L +#define CKSVII2C_IC_CON__IC_SLAVE_DISABLE_MASK 0x00000040L +#define CKSVII2C_IC_CON__STOP_DET_IFADDRESSED_MASK 0x00000080L +#define CKSVII2C_IC_CON__TX_EMPTY_CTRL_MASK 0x00000100L +#define CKSVII2C_IC_CON__RX_FIFO_FULL_HLD_CTRL_MASK 0x00000200L +//CKSVII2C_IC_TAR +#define CKSVII2C_IC_TAR__IC_TAR__SHIFT 0x0 +#define CKSVII2C_IC_TAR__GC_OR_START__SHIFT 0xa +#define CKSVII2C_IC_TAR__SPECIAL__SHIFT 0xb +#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER__SHIFT 0xc +#define CKSVII2C_IC_TAR__IC_TAR_MASK 0x000003FFL +#define CKSVII2C_IC_TAR__GC_OR_START_MASK 0x00000400L +#define CKSVII2C_IC_TAR__SPECIAL_MASK 0x00000800L +#define CKSVII2C_IC_TAR__IC_10BITADDR_MASTER_MASK 0x00001000L +//CKSVII2C_IC_SAR +#define CKSVII2C_IC_SAR__IC_SAR__SHIFT 0x0 +#define CKSVII2C_IC_SAR__IC_SAR_MASK 0x000003FFL +//CKSVII2C_IC_HS_MADDR +#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR__SHIFT 0x0 +#define CKSVII2C_IC_HS_MADDR__IC_HS_MADDR_MASK 0x00000007L +//CKSVII2C_IC_DATA_CMD +#define CKSVII2C_IC_DATA_CMD__DAT__SHIFT 0x0 +#define CKSVII2C_IC_DATA_CMD__CMD__SHIFT 0x8 +#define CKSVII2C_IC_DATA_CMD__STOP__SHIFT 0x9 +#define CKSVII2C_IC_DATA_CMD__RESTART__SHIFT 0xa +#define CKSVII2C_IC_DATA_CMD__FIRST_DATA_BYTE__SHIFT 0xb +#define CKSVII2C_IC_DATA_CMD__DAT_MASK 0x000000FFL +#define CKSVII2C_IC_DATA_CMD__CMD_MASK 0x00000100L +#define CKSVII2C_IC_DATA_CMD__STOP_MASK 0x00000200L +#define CKSVII2C_IC_DATA_CMD__RESTART_MASK 0x00000400L +//CKSVII2C_IC_SS_SCL_HCNT +#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_SS_SCL_HCNT__IC_SS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_SS_SCL_LCNT +#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_SS_SCL_LCNT__IC_SS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_FS_SCL_HCNT +#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_FS_SCL_HCNT__IC_FS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_FS_SCL_LCNT +#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_FS_SCL_LCNT__IC_FS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_HS_SCL_HCNT +#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C_IC_HS_SCL_HCNT__IC_HS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_HS_SCL_LCNT +#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C_IC_HS_SCL_LCNT__IC_HS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C_IC_INTR_STAT +#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_INTR_STAT__R_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_INTR_STAT__R_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_INTR_STAT__R_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_INTR_STAT__R_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_INTR_STAT__R_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_INTR_STAT__R_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_INTR_STAT__R_START_DET__SHIFT 0xa +#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_INTR_STAT__R_SCL_STUCK_AT_LOW__SHIFT 0xe +#define CKSVII2C_IC_INTR_STAT__R_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_INTR_STAT__R_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_INTR_STAT__R_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_INTR_STAT__R_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_INTR_STAT__R_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_INTR_STAT__R_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_INTR_STAT__R_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_INTR_STAT__R_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_INTR_STAT__R_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_INTR_STAT__R_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_INTR_STAT__R_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_INTR_STAT__R_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_INTR_STAT__R_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_INTR_STAT__R_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_INTR_MASK +#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER__SHIFT 0x0 +#define CKSVII2C_IC_INTR_MASK__M_RX_OVER__SHIFT 0x1 +#define CKSVII2C_IC_INTR_MASK__M_RX_FULL__SHIFT 0x2 +#define CKSVII2C_IC_INTR_MASK__M_TX_OVER__SHIFT 0x3 +#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C_IC_INTR_MASK__M_RD_REQ__SHIFT 0x5 +#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT__SHIFT 0x6 +#define CKSVII2C_IC_INTR_MASK__M_RX_DONE__SHIFT 0x7 +#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY__SHIFT 0x8 +#define CKSVII2C_IC_INTR_MASK__M_STOP_DET__SHIFT 0x9 +#define CKSVII2C_IC_INTR_MASK__M_START_DET__SHIFT 0xa +#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL__SHIFT 0xb +#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET__SHIFT 0xc +#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C_IC_INTR_MASK__M_SCL_STUCK_AT_LOW__SHIFT 0xe +#define CKSVII2C_IC_INTR_MASK__M_RX_UNDER_MASK 0x00000001L +#define CKSVII2C_IC_INTR_MASK__M_RX_OVER_MASK 0x00000002L +#define CKSVII2C_IC_INTR_MASK__M_RX_FULL_MASK 0x00000004L +#define CKSVII2C_IC_INTR_MASK__M_TX_OVER_MASK 0x00000008L +#define CKSVII2C_IC_INTR_MASK__M_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C_IC_INTR_MASK__M_RD_REQ_MASK 0x00000020L +#define CKSVII2C_IC_INTR_MASK__M_TX_ABRT_MASK 0x00000040L +#define CKSVII2C_IC_INTR_MASK__M_RX_DONE_MASK 0x00000080L +#define CKSVII2C_IC_INTR_MASK__M_ACTIVITY_MASK 0x00000100L +#define CKSVII2C_IC_INTR_MASK__M_STOP_DET_MASK 0x00000200L +#define CKSVII2C_IC_INTR_MASK__M_START_DET_MASK 0x00000400L +#define CKSVII2C_IC_INTR_MASK__M_GEN_CALL_MASK 0x00000800L +#define CKSVII2C_IC_INTR_MASK__M_RESTART_DET_MASK 0x00001000L +#define CKSVII2C_IC_INTR_MASK__M_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C_IC_RAW_INTR_STAT +//CKSVII2C_IC_RX_TL +#define CKSVII2C_IC_RX_TL__RX_TL__SHIFT 0x0 +//CKSVII2C_IC_TX_TL +#define CKSVII2C_IC_TX_TL__TX_TL__SHIFT 0x0 +//CKSVII2C_IC_CLR_INTR +//CKSVII2C_IC_CLR_RX_UNDER +//CKSVII2C_IC_CLR_RX_OVER +//CKSVII2C_IC_CLR_TX_OVER +//CKSVII2C_IC_CLR_RD_REQ +//CKSVII2C_IC_CLR_TX_ABRT +//CKSVII2C_IC_CLR_RX_DONE +//CKSVII2C_IC_CLR_ACTIVITY +//CKSVII2C_IC_CLR_STOP_DET +//CKSVII2C_IC_CLR_START_DET +//CKSVII2C_IC_CLR_GEN_CALL +//CKSVII2C_IC_ENABLE +#define CKSVII2C_IC_ENABLE__ENABLE__SHIFT 0x0 +#define CKSVII2C_IC_ENABLE__ABORT__SHIFT 0x1 +#define CKSVII2C_IC_ENABLE__TX_CMD_BLOCK__SHIFT 0x2 +#define CKSVII2C_IC_ENABLE__SDA_STUCK_RECOVERY_ENABLE__SHIFT 0x3 +#define CKSVII2C_IC_ENABLE__ENABLE_MASK 0x00000001L +#define CKSVII2C_IC_ENABLE__ABORT_MASK 0x00000002L +//CKSVII2C_IC_STATUS +#define CKSVII2C_IC_STATUS__ACTIVITY__SHIFT 0x0 +#define CKSVII2C_IC_STATUS__TFNF__SHIFT 0x1 +#define CKSVII2C_IC_STATUS__TFE__SHIFT 0x2 +#define CKSVII2C_IC_STATUS__RFNE__SHIFT 0x3 +#define CKSVII2C_IC_STATUS__RFF__SHIFT 0x4 +#define CKSVII2C_IC_STATUS__MST_ACTIVITY__SHIFT 0x5 +#define CKSVII2C_IC_STATUS__SLV_ACTIVITY__SHIFT 0x6 +#define CKSVII2C_IC_STATUS__MST_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 +#define CKSVII2C_IC_STATUS__MST_HOLD_RX_FIFO_FULL__SHIFT 0x8 +#define CKSVII2C_IC_STATUS__SLV_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 +#define CKSVII2C_IC_STATUS__SLV_HOLD_RX_FIFO_FULL__SHIFT 0xa +#define CKSVII2C_IC_STATUS__SDA_STUCK_NOT_RECOVERED__SHIFT 0xb +#define CKSVII2C_IC_STATUS__ACTIVITY_MASK 0x00000001L +#define CKSVII2C_IC_STATUS__TFNF_MASK 0x00000002L +#define CKSVII2C_IC_STATUS__TFE_MASK 0x00000004L +#define CKSVII2C_IC_STATUS__RFNE_MASK 0x00000008L +#define CKSVII2C_IC_STATUS__RFF_MASK 0x00000010L +#define CKSVII2C_IC_STATUS__MST_ACTIVITY_MASK 0x00000020L +#define CKSVII2C_IC_STATUS__SLV_ACTIVITY_MASK 0x00000040L +//CKSVII2C_IC_TXFLR +#define CKSVII2C_IC_TXFLR__TXFLR__SHIFT 0x0 +//CKSVII2C_IC_RXFLR +#define CKSVII2C_IC_RXFLR__RXFLR__SHIFT 0x0 +//CKSVII2C_IC_SDA_HOLD +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_TX_HOLD__SHIFT 0x0 +#define CKSVII2C_IC_SDA_HOLD__IC_SDA_RX_HOLD__SHIFT 0x10 +//CKSVII2C_IC_TX_ABRT_SOURCE +//CKSVII2C_IC_SLV_DATA_NACK_ONLY +//CKSVII2C_IC_DMA_CR +//CKSVII2C_IC_DMA_TDLR +//CKSVII2C_IC_DMA_RDLR +//CKSVII2C_IC_SDA_SETUP +#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP__SHIFT 0x0 +#define CKSVII2C_IC_SDA_SETUP__SDA_SETUP_MASK 0x000000FFL +//CKSVII2C_IC_ACK_GENERAL_CALL +#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL__SHIFT 0x0 +#define CKSVII2C_IC_ACK_GENERAL_CALL__ACK_GENERAL_CALL_MASK 0x00000001L +//CKSVII2C_IC_ENABLE_STATUS +#define CKSVII2C_IC_ENABLE_STATUS__IC_EN__SHIFT 0x0 +#define CKSVII2C_IC_ENABLE_STATUS__SLV_DISABLED_WHILE_BUSY__SHIFT 0x1 +#define CKSVII2C_IC_ENABLE_STATUS__SLV_RX_DATA_LOST__SHIFT 0x2 +#define CKSVII2C_IC_ENABLE_STATUS__IC_EN_MASK 0x00000001L +//CKSVII2C_IC_FS_SPKLEN +#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN__SHIFT 0x0 +#define CKSVII2C_IC_FS_SPKLEN__FS_SPKLEN_MASK 0x000000FFL +//CKSVII2C_IC_HS_SPKLEN +#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN__SHIFT 0x0 +#define CKSVII2C_IC_HS_SPKLEN__HS_SPKLEN_MASK 0x000000FFL +//CKSVII2C_IC_CLR_RESTART_DET +//CKSVII2C_IC_COMP_PARAM_1 +#define CKSVII2C_IC_COMP_PARAM_1__APB_DATA_WIDTH__SHIFT 0x0 +#define CKSVII2C_IC_COMP_PARAM_1__MAX_SPEED_MODE__SHIFT 0x2 +#define CKSVII2C_IC_COMP_PARAM_1__HC_COUNT_VALUES__SHIFT 0x4 +#define CKSVII2C_IC_COMP_PARAM_1__INTR_IO__SHIFT 0x5 +#define CKSVII2C_IC_COMP_PARAM_1__HAS_DMA__SHIFT 0x6 +#define CKSVII2C_IC_COMP_PARAM_1__ADD_ENCODED_PARAMS__SHIFT 0x7 +#define CKSVII2C_IC_COMP_PARAM_1__RX_BUFFER_DEPTH__SHIFT 0x8 +#define CKSVII2C_IC_COMP_PARAM_1__TX_BUFFER_DEPTH__SHIFT 0x10 +//CKSVII2C_IC_COMP_VERSION +#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION__SHIFT 0x0 +#define CKSVII2C_IC_COMP_VERSION__COMP_VERSION_MASK 0xFFFFFFFFL +//CKSVII2C_IC_COMP_TYPE +#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE__SHIFT 0x0 +#define CKSVII2C_IC_COMP_TYPE__COMP_TYPE_MASK 0xFFFFFFFFL +//CKSVII2C1_IC_CON +#define CKSVII2C1_IC_CON__IC1_MASTER_MODE__SHIFT 0x0 +#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE__SHIFT 0x1 +#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE__SHIFT 0x3 +#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER__SHIFT 0x4 +#define CKSVII2C1_IC_CON__IC1_RESTART_EN__SHIFT 0x5 +#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE__SHIFT 0x6 +#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED__SHIFT 0x7 +#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL__SHIFT 0x8 +#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL__SHIFT 0x9 +#define CKSVII2C1_IC_CON__BUS_CLEAR_FEATURE_CTRL1__SHIFT 0xb +#define CKSVII2C1_IC_CON__IC1_MASTER_MODE_MASK 0x00000001L +#define CKSVII2C1_IC_CON__IC1_MAX_SPEED_MODE_MASK 0x00000006L +#define CKSVII2C1_IC_CON__IC1_10BITADDR_SLAVE_MASK 0x00000008L +#define CKSVII2C1_IC_CON__IC1_10BITADDR_MASTER_MASK 0x00000010L +#define CKSVII2C1_IC_CON__IC1_RESTART_EN_MASK 0x00000020L +#define CKSVII2C1_IC_CON__IC1_SLAVE_DISABLE_MASK 0x00000040L +#define CKSVII2C1_IC_CON__STOP1_DET_IFADDRESSED_MASK 0x00000080L +#define CKSVII2C1_IC_CON__TX1_EMPTY_CTRL_MASK 0x00000100L +#define CKSVII2C1_IC_CON__RX1_FIFO_FULL_HLD_CTRL_MASK 0x00000200L +//CKSVII2C1_IC_TAR +#define CKSVII2C1_IC_TAR__IC1_TAR__SHIFT 0x0 +#define CKSVII2C1_IC_TAR__GC1_OR_START__SHIFT 0xa +#define CKSVII2C1_IC_TAR__SPECIAL1__SHIFT 0xb +#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER__SHIFT 0xc +#define CKSVII2C1_IC_TAR__IC1_TAR_MASK 0x000003FFL +#define CKSVII2C1_IC_TAR__GC1_OR_START_MASK 0x00000400L +#define CKSVII2C1_IC_TAR__SPECIAL1_MASK 0x00000800L +#define CKSVII2C1_IC_TAR__IC1_10BITADDR_MASTER_MASK 0x00001000L +//CKSVII2C1_IC_SAR +#define CKSVII2C1_IC_SAR__IC1_SAR__SHIFT 0x0 +#define CKSVII2C1_IC_SAR__IC1_SAR_MASK 0x000003FFL +//CKSVII2C1_IC_HS_MADDR +#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR__SHIFT 0x0 +#define CKSVII2C1_IC_HS_MADDR__IC1_HS_MADDR_MASK 0x00000007L +//CKSVII2C1_IC_DATA_CMD +#define CKSVII2C1_IC_DATA_CMD__DAT1__SHIFT 0x0 +#define CKSVII2C1_IC_DATA_CMD__CMD1__SHIFT 0x8 +#define CKSVII2C1_IC_DATA_CMD__STOP1__SHIFT 0x9 +#define CKSVII2C1_IC_DATA_CMD__RESTART1__SHIFT 0xa +#define CKSVII2C1_IC_DATA_CMD__FIRST1_DATA_BYTE__SHIFT 0xb +#define CKSVII2C1_IC_DATA_CMD__DAT1_MASK 0x000000FFL +#define CKSVII2C1_IC_DATA_CMD__CMD1_MASK 0x00000100L +#define CKSVII2C1_IC_DATA_CMD__STOP1_MASK 0x00000200L +#define CKSVII2C1_IC_DATA_CMD__RESTART1_MASK 0x00000400L +//CKSVII2C1_IC_SS_SCL_HCNT +#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C1_IC_SS_SCL_HCNT__IC1_SS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_SS_SCL_LCNT +#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C1_IC_SS_SCL_LCNT__IC1_SS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_FS_SCL_HCNT +#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C1_IC_FS_SCL_HCNT__IC1_FS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_FS_SCL_LCNT +#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C1_IC_FS_SCL_LCNT__IC1_FS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_HS_SCL_HCNT +#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT__SHIFT 0x0 +#define CKSVII2C1_IC_HS_SCL_HCNT__IC1_HS_SCL_HCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_HS_SCL_LCNT +#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT__SHIFT 0x0 +#define CKSVII2C1_IC_HS_SCL_LCNT__IC1_HS_SCL_LCNT_MASK 0x0000FFFFL +//CKSVII2C1_IC_INTR_STAT +#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER__SHIFT 0x0 +#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER__SHIFT 0x1 +#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL__SHIFT 0x2 +#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER__SHIFT 0x3 +#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ__SHIFT 0x5 +#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT__SHIFT 0x6 +#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE__SHIFT 0x7 +#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY__SHIFT 0x8 +#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET__SHIFT 0x9 +#define CKSVII2C1_IC_INTR_STAT__R1_START_DET__SHIFT 0xa +#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL__SHIFT 0xb +#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET__SHIFT 0xc +#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C1_IC_INTR_STAT__R1_SCL_STUCK_AT_LOW__SHIFT 0xe +#define CKSVII2C1_IC_INTR_STAT__R1_RX_UNDER_MASK 0x00000001L +#define CKSVII2C1_IC_INTR_STAT__R1_RX_OVER_MASK 0x00000002L +#define CKSVII2C1_IC_INTR_STAT__R1_RX_FULL_MASK 0x00000004L +#define CKSVII2C1_IC_INTR_STAT__R1_TX_OVER_MASK 0x00000008L +#define CKSVII2C1_IC_INTR_STAT__R1_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C1_IC_INTR_STAT__R1_RD_REQ_MASK 0x00000020L +#define CKSVII2C1_IC_INTR_STAT__R1_TX_ABRT_MASK 0x00000040L +#define CKSVII2C1_IC_INTR_STAT__R1_RX_DONE_MASK 0x00000080L +#define CKSVII2C1_IC_INTR_STAT__R1_ACTIVITY_MASK 0x00000100L +#define CKSVII2C1_IC_INTR_STAT__R1_STOP_DET_MASK 0x00000200L +#define CKSVII2C1_IC_INTR_STAT__R1_START_DET_MASK 0x00000400L +#define CKSVII2C1_IC_INTR_STAT__R1_GEN_CALL_MASK 0x00000800L +#define CKSVII2C1_IC_INTR_STAT__R1_RESTART_DET_MASK 0x00001000L +#define CKSVII2C1_IC_INTR_STAT__R1_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C1_IC_INTR_MASK +#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER__SHIFT 0x0 +#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER__SHIFT 0x1 +#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL__SHIFT 0x2 +#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER__SHIFT 0x3 +#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY__SHIFT 0x4 +#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ__SHIFT 0x5 +#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT__SHIFT 0x6 +#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE__SHIFT 0x7 +#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY__SHIFT 0x8 +#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET__SHIFT 0x9 +#define CKSVII2C1_IC_INTR_MASK__M1_START_DET__SHIFT 0xa +#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL__SHIFT 0xb +#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET__SHIFT 0xc +#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD__SHIFT 0xd +#define CKSVII2C1_IC_INTR_MASK__M1_SCL_STUCK_AT_LOW__SHIFT 0xe +#define CKSVII2C1_IC_INTR_MASK__M1_RX_UNDER_MASK 0x00000001L +#define CKSVII2C1_IC_INTR_MASK__M1_RX_OVER_MASK 0x00000002L +#define CKSVII2C1_IC_INTR_MASK__M1_RX_FULL_MASK 0x00000004L +#define CKSVII2C1_IC_INTR_MASK__M1_TX_OVER_MASK 0x00000008L +#define CKSVII2C1_IC_INTR_MASK__M1_TX_EMPTY_MASK 0x00000010L +#define CKSVII2C1_IC_INTR_MASK__M1_RD_REQ_MASK 0x00000020L +#define CKSVII2C1_IC_INTR_MASK__M1_TX_ABRT_MASK 0x00000040L +#define CKSVII2C1_IC_INTR_MASK__M1_RX_DONE_MASK 0x00000080L +#define CKSVII2C1_IC_INTR_MASK__M1_ACTIVITY_MASK 0x00000100L +#define CKSVII2C1_IC_INTR_MASK__M1_STOP_DET_MASK 0x00000200L +#define CKSVII2C1_IC_INTR_MASK__M1_START_DET_MASK 0x00000400L +#define CKSVII2C1_IC_INTR_MASK__M1_GEN_CALL_MASK 0x00000800L +#define CKSVII2C1_IC_INTR_MASK__M1_RESTART_DET_MASK 0x00001000L +#define CKSVII2C1_IC_INTR_MASK__M1_MST_ON_HOLD_MASK 0x00002000L +//CKSVII2C1_IC_RAW_INTR_STAT +//CKSVII2C1_IC_RX_TL +#define CKSVII2C1_IC_RX_TL__RX1_TL__SHIFT 0x0 +//CKSVII2C1_IC_TX_TL +#define CKSVII2C1_IC_TX_TL__TX1_TL__SHIFT 0x0 +//CKSVII2C1_IC_CLR_INTR +//CKSVII2C1_IC_CLR_RX_UNDER +//CKSVII2C1_IC_CLR_RX_OVER +//CKSVII2C1_IC_CLR_TX_OVER +//CKSVII2C1_IC_CLR_RD_REQ +//CKSVII2C1_IC_CLR_TX_ABRT +//CKSVII2C1_IC_CLR_RX_DONE +//CKSVII2C1_IC_CLR_ACTIVITY +//CKSVII2C1_IC_CLR_STOP_DET +//CKSVII2C1_IC_CLR_START_DET +//CKSVII2C1_IC_CLR_GEN_CALL +//CKSVII2C1_IC_ENABLE +#define CKSVII2C1_IC_ENABLE__ENABLE1__SHIFT 0x0 +#define CKSVII2C1_IC_ENABLE__ABORT1__SHIFT 0x1 +#define CKSVII2C1_IC_ENABLE__TX1_CMD_BLOCK__SHIFT 0x2 +#define CKSVII2C1_IC_ENABLE__SDA1_STUCK_RECOVERY_ENABLE__SHIFT 0x3 +#define CKSVII2C1_IC_ENABLE__ENABLE1_MASK 0x00000001L +#define CKSVII2C1_IC_ENABLE__ABORT1_MASK 0x00000002L +//CKSVII2C1_IC_STATUS +#define CKSVII2C1_IC_STATUS__ACTIVITY1__SHIFT 0x0 +#define CKSVII2C1_IC_STATUS__TFNF1__SHIFT 0x1 +#define CKSVII2C1_IC_STATUS__TFE1__SHIFT 0x2 +#define CKSVII2C1_IC_STATUS__RFNE1__SHIFT 0x3 +#define CKSVII2C1_IC_STATUS__RFF1__SHIFT 0x4 +#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY__SHIFT 0x5 +#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY__SHIFT 0x6 +#define CKSVII2C1_IC_STATUS__MST1_HOLD_TX_FIFO_EMPTY__SHIFT 0x7 +#define CKSVII2C1_IC_STATUS__MST1_HOLD_RX_FIFO_FULL__SHIFT 0x8 +#define CKSVII2C1_IC_STATUS__SLV1_HOLD_TX_FIFO_EMPTY__SHIFT 0x9 +#define CKSVII2C1_IC_STATUS__SLV1_HOLD_RX_FIFO_FULL__SHIFT 0xa +#define CKSVII2C1_IC_STATUS__SDA1_STUCK_NOT_RECOVERED__SHIFT 0xb +#define CKSVII2C1_IC_STATUS__ACTIVITY1_MASK 0x00000001L +#define CKSVII2C1_IC_STATUS__TFNF1_MASK 0x00000002L +#define CKSVII2C1_IC_STATUS__TFE1_MASK 0x00000004L +#define CKSVII2C1_IC_STATUS__RFNE1_MASK 0x00000008L +#define CKSVII2C1_IC_STATUS__RFF1_MASK 0x00000010L +#define CKSVII2C1_IC_STATUS__MST1_ACTIVITY_MASK 0x00000020L +#define CKSVII2C1_IC_STATUS__SLV1_ACTIVITY_MASK 0x00000040L +//CKSVII2C1_IC_TXFLR +#define CKSVII2C1_IC_TXFLR__TXFLR1__SHIFT 0x0 +//CKSVII2C1_IC_RXFLR +#define CKSVII2C1_IC_RXFLR__RXFLR1__SHIFT 0x0 +//CKSVII2C1_IC_SDA_HOLD +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_TX_HOLD__SHIFT 0x0 +#define CKSVII2C1_IC_SDA_HOLD__IC1_SDA_RX_HOLD__SHIFT 0x10 +//CKSVII2C1_IC_TX_ABRT_SOURCE +//CKSVII2C1_IC_SLV_DATA_NACK_ONLY +//CKSVII2C1_IC_DMA_CR +//CKSVII2C1_IC_DMA_TDLR +//CKSVII2C1_IC_DMA_RDLR +//CKSVII2C1_IC_SDA_SETUP +#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP__SHIFT 0x0 +#define CKSVII2C1_IC_SDA_SETUP__SDA1_SETUP_MASK 0x000000FFL +//CKSVII2C1_IC_ACK_GENERAL_CALL +#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL__SHIFT 0x0 +#define CKSVII2C1_IC_ACK_GENERAL_CALL__ACK1_GENERAL_CALL_MASK 0x00000001L +//CKSVII2C1_IC_ENABLE_STATUS +#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN__SHIFT 0x0 +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_DISABLED_WHILE_BUSY__SHIFT 0x1 +#define CKSVII2C1_IC_ENABLE_STATUS__SLV1_RX_DATA_LOST__SHIFT 0x2 +#define CKSVII2C1_IC_ENABLE_STATUS__IC1_EN_MASK 0x00000001L +//CKSVII2C1_IC_FS_SPKLEN +#define CKSVII2C1_IC_FS_SPKLEN__FS1_SPKLEN__SHIFT 0x0 +//CKSVII2C1_IC_HS_SPKLEN +#define CKSVII2C1_IC_HS_SPKLEN__HS1_SPKLEN__SHIFT 0x0 +//CKSVII2C1_IC_CLR_RESTART_DET +//CKSVII2C1_IC_COMP_PARAM_1 +#define CKSVII2C1_IC_COMP_PARAM_1__APB1_DATA_WIDTH__SHIFT 0x0 +#define CKSVII2C1_IC_COMP_PARAM_1__MAX1_SPEED_MODE__SHIFT 0x2 +#define CKSVII2C1_IC_COMP_PARAM_1__HC1_COUNT_VALUES__SHIFT 0x4 +#define CKSVII2C1_IC_COMP_PARAM_1__INTR1_IO__SHIFT 0x5 +#define CKSVII2C1_IC_COMP_PARAM_1__HAS1_DMA__SHIFT 0x6 +#define CKSVII2C1_IC_COMP_PARAM_1__ADD1_ENCODED_PARAMS__SHIFT 0x7 +#define CKSVII2C1_IC_COMP_PARAM_1__RX1_BUFFER_DEPTH__SHIFT 0x8 +#define CKSVII2C1_IC_COMP_PARAM_1__TX1_BUFFER_DEPTH__SHIFT 0x10 +//CKSVII2C1_IC_COMP_VERSION +#define CKSVII2C1_IC_COMP_VERSION__COMP1_VERSION__SHIFT 0x0 +//CKSVII2C1_IC_COMP_TYPE +#define CKSVII2C1_IC_COMP_TYPE__COMP1_TYPE__SHIFT 0x0 +//SMUIO_PWRMGT +#define SMUIO_PWRMGT__i2c_clk_gate_en__SHIFT 0x0 +#define SMUIO_PWRMGT__i2c1_clk_gate_en__SHIFT 0x8 +#define SMUIO_PWRMGT__i2c_reg_reset__SHIFT 0x10 +#define SMUIO_PWRMGT__i2c_dwc_reset_en__SHIFT 0x11 +#define SMUIO_PWRMGT__i2c1_reg_reset__SHIFT 0x18 +#define SMUIO_PWRMGT__i2c1_dwc_reset_en__SHIFT 0x19 +#define SMUIO_PWRMGT__i2c_clk_gate_en_MASK 0x00000001L +#define SMUIO_PWRMGT__i2c1_clk_gate_en_MASK 0x00000100L + + +// addressBlock: smuio_smuio_rom_SmuSmuioDec +//ROM_CNTL +#define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x0 +#define ROM_CNTL__READ_MODE__SHIFT 0x1 +#define ROM_CNTL__READ_MODE_OVERRIDE__SHIFT 0x3 +#define ROM_CNTL__SPI_TIMING_RELAX_SCK__SHIFT 0x4 +#define ROM_CNTL__SPI_TIMING_RELAX_SCK_OVERRIDE__SHIFT 0x5 +#define ROM_CNTL__FOUR_BYTE_ADDRESS_MODE__SHIFT 0x6 +#define ROM_CNTL__DUMMY_CYCLE_NUM__SHIFT 0x8 +#define ROM_CNTL__SPI_TIMING_RELAX__SHIFT 0x13 +#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT 0x14 +#define ROM_CNTL__SPI_FAST_MODE__SHIFT 0x15 +#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT 0x16 +#define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x17 +#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT 0x1c +#define ROM_CNTL__ROM_INDEX_ADDRESS_AUTO_INCREASE__SHIFT 0x1d +#define ROM_CNTL__PAD_SAMPLE_MODE__SHIFT 0x1e +#define ROM_CNTL__PAD_SAMPLE_MODE_OVERRIDE__SHIFT 0x1f +#define ROM_CNTL__CLOCK_GATING_EN_MASK 0x00000001L +#define ROM_CNTL__SPI_TIMING_RELAX_MASK 0x00080000L +#define ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK 0x00100000L +#define ROM_CNTL__SPI_FAST_MODE_MASK 0x00200000L +#define ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK 0x00400000L +#define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0x0F800000L +#define ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK 0x10000000L +//PAGE_MIRROR_CNTL +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x1c +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0x01FFFFFFL +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x02000000L +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0x0C000000L +#define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x10000000L +//ROM_STATUS +#define ROM_STATUS__ROM_BUSY__SHIFT 0x0 +#define ROM_STATUS__ROM_BUSY_MASK 0x00000001L +//CGTT_ROM_CLK_CTRL0 +#define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +#define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +//ROM_INDEX +#define ROM_INDEX__ROM_INDEX__SHIFT 0x0 +#define ROM_INDEX__ROM_INDEX_MASK 0x01FFFFFFL +//ROM_DATA +#define ROM_DATA__ROM_DATA__SHIFT 0x0 +#define ROM_DATA__ROM_DATA_MASK 0xFFFFFFFFL +//ROM_START +#define ROM_START__ROM_START__SHIFT 0x0 +#define ROM_START__ROM_START_MASK 0x01FFFFFFL +//ROM_SW_CNTL +#define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 +#define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x13 +#define ROM_SW_CNTL__DATA_SIZE_MASK 0x0000FFFFL +#define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x00070000L +#define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x00080000L +//ROM_SW_STATUS +#define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 +#define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x00000001L +//ROM_SW_COMMAND +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 +#define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 +#define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0x000000FFL +#define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xFFFFFF00L +//ROM_SW_DATA_1 +#define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_2 +#define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_3 +#define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_4 +#define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_5 +#define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_6 +#define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_7 +#define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_8 +#define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_9 +#define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_10 +#define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_11 +#define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_12 +#define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_13 +#define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_14 +#define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_15 +#define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_16 +#define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_17 +#define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_18 +#define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_19 +#define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_20 +#define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_21 +#define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_22 +#define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_23 +#define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_24 +#define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_25 +#define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_26 +#define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_27 +#define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_28 +#define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_29 +#define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_30 +#define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_31 +#define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_32 +#define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_33 +#define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_34 +#define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_35 +#define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_36 +#define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_37 +#define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_38 +#define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_39 +#define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_40 +#define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_41 +#define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_42 +#define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_43 +#define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_44 +#define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_45 +#define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_46 +#define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_47 +#define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_48 +#define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_49 +#define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_50 +#define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_51 +#define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_52 +#define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_53 +#define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_54 +#define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_55 +#define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_56 +#define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_57 +#define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_58 +#define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_59 +#define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_60 +#define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_61 +#define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_62 +#define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_63 +#define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xFFFFFFFFL +//ROM_SW_DATA_64 +#define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 +#define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: smuio_smuio_gpio_SmuSmuioDec +//SMU_GPIOPAD_SW_INT_STAT +#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x00000001L +//SMU_GPIOPAD_MASK +#define SMU_GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 +#define SMU_GPIOPAD_MASK__GPIO_MASK_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_A +#define SMU_GPIOPAD_A__GPIO_A__SHIFT 0x0 +#define SMU_GPIOPAD_A__GPIO_A_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_TXIMPSEL +#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL__SHIFT 0x0 +#define SMU_GPIOPAD_TXIMPSEL__GPIO_TXIMPSEL_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_EN +#define SMU_GPIOPAD_EN__GPIO_EN__SHIFT 0x0 +#define SMU_GPIOPAD_EN__GPIO_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_Y +#define SMU_GPIOPAD_Y__GPIO_Y__SHIFT 0x0 +#define SMU_GPIOPAD_Y__GPIO_Y_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_RXEN +#define SMU_GPIOPAD_RXEN__GPIO_RXEN__SHIFT 0x0 +#define SMU_GPIOPAD_RXEN__GPIO_RXEN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_RCVR_SEL0 +#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0__SHIFT 0x0 +#define SMU_GPIOPAD_RCVR_SEL0__GPIO_RCVR_SEL0_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_RCVR_SEL1 +#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1__SHIFT 0x0 +#define SMU_GPIOPAD_RCVR_SEL1__GPIO_RCVR_SEL1_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_PU_EN +#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 +#define SMU_GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_PD_EN +#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 +#define SMU_GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_PINSTRAPS +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x00000001L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x00000002L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x00000004L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x00000008L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x00000010L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x00000020L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x00000040L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x00000080L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x00000100L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x00000200L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x00000400L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x00000800L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x00001000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x00002000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x00004000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x00008000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x00010000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x00020000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x00040000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x00080000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x00100000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x00200000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x00400000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x00800000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x01000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x02000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x04000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x08000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000L +#define SMU_GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000L +//DFT_PINSTRAPS +#define DFT_PINSTRAPS__DFT_PINSTRAPS__SHIFT 0x0 +#define DFT_PINSTRAPS__DFT_PINSTRAPS_MASK 0x000003FFL +//SMU_GPIOPAD_INT_STAT_EN +#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 +#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f +#define SMU_GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000L +//SMU_GPIOPAD_INT_STAT +#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f +#define SMU_GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000L +//SMU_GPIOPAD_INT_STAT_AK +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c +#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x00000001L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x00000002L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x00000004L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x00000008L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x00000010L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x00000020L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x00000040L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x00000080L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x00000100L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x00000200L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x00000400L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x00000800L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x00001000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x00002000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x00004000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x00008000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x00010000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x00020000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x00040000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x00080000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x00100000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x00200000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x00400000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x00800000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x01000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x02000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x04000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x08000000L +#define SMU_GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000L +#define SMU_GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000L +//SMU_GPIOPAD_INT_EN +#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 +#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f +#define SMU_GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000L +//SMU_GPIOPAD_INT_TYPE +#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 +#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f +#define SMU_GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000L +//SMU_GPIOPAD_INT_POLARITY +#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 +#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f +#define SMU_GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1FFFFFFFL +#define SMU_GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000L +//SMUIO_PCC_GPIO_SELECT +#define SMUIO_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 +#define SMUIO_PCC_GPIO_SELECT__GPIO_MASK 0xFFFFFFFFL +//SMU_GPIOPAD_S0 +#define SMU_GPIOPAD_S0__GPIO_S0__SHIFT 0x0 +#define SMU_GPIOPAD_S0__GPIO_S0_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_S1 +#define SMU_GPIOPAD_S1__GPIO_S1__SHIFT 0x0 +#define SMU_GPIOPAD_S1__GPIO_S1_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_SCHMEN +#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN__SHIFT 0x0 +#define SMU_GPIOPAD_SCHMEN__GPIO_SCHMEN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_SCL_EN +#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN__SHIFT 0x0 +#define SMU_GPIOPAD_SCL_EN__GPIO_SCL_EN_MASK 0x7FFFFFFFL +//SMU_GPIOPAD_SDA_EN +#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN__SHIFT 0x0 +#define SMU_GPIOPAD_SDA_EN__GPIO_SDA_EN_MASK 0x7FFFFFFFL +//SMUIO_GPIO_INT0_SELECT +#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT0_SELECT__GPIO_INT0_SELECT_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT1_SELECT +#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT1_SELECT__GPIO_INT1_SELECT_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT2_SELECT +#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT2_SELECT__GPIO_INT2_SELECT_MASK 0xFFFFFFFFL +//SMUIO_GPIO_INT3_SELECT +#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT__SHIFT 0x0 +#define SMUIO_GPIO_INT3_SELECT__GPIO_INT3_SELECT_MASK 0xFFFFFFFFL +//SMU_GPIOPAD_MP_INT0_STAT +#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT0_STAT__GPIO_MP_INT0_STAT_MASK 0x1FFFFFFFL +//SMU_GPIOPAD_MP_INT1_STAT +#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT1_STAT__GPIO_MP_INT1_STAT_MASK 0x1FFFFFFFL +//SMU_GPIOPAD_MP_INT2_STAT +#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT2_STAT__GPIO_MP_INT2_STAT_MASK 0x1FFFFFFFL +//SMU_GPIOPAD_MP_INT3_STAT +#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT__SHIFT 0x0 +#define SMU_GPIOPAD_MP_INT3_STAT__GPIO_MP_INT3_STAT_MASK 0x1FFFFFFFL +//SMIO_INDEX +#define SMIO_INDEX__SW_SMIO_INDEX__SHIFT 0x0 +#define SMIO_INDEX__SW_SMIO_INDEX_MASK 0x00000001L +//S0_VID_SMIO_CNTL +#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES__SHIFT 0x0 +#define S0_VID_SMIO_CNTL__S0_SMIO_VALUES_MASK 0xFFFFFFFFL +//S1_VID_SMIO_CNTL +#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES__SHIFT 0x0 +#define S1_VID_SMIO_CNTL__S1_SMIO_VALUES_MASK 0xFFFFFFFFL +//OPEN_DRAIN_SELECT +#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT__SHIFT 0x0 +#define OPEN_DRAIN_SELECT__RESERVED__SHIFT 0x1f +#define OPEN_DRAIN_SELECT__OPEN_DRAIN_SELECT_MASK 0x7FFFFFFFL +#define OPEN_DRAIN_SELECT__RESERVED_MASK 0x80000000L +//SMIO_ENABLE +#define SMIO_ENABLE__SMIO_ENABLE__SHIFT 0x0 +#define SMIO_ENABLE__SMIO_ENABLE_MASK 0xFFFFFFFFL + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_offset.h new file mode 100644 index 0000000000000..187390b8003cb --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_offset.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _thm_15_0_0_OFFSET_HEADER +#define _thm_15_0_0_OFFSET_HEADER + + + +// addressBlock: thm_thm_SmuThmDec +// base address: 0x59800 +#define regTHM_TCON_CUR_TMP 0x0000 +#define regTHM_TCON_CUR_TMP_BASE_IDX 0 +#define regTHM_TCON_HTC 0x0001 +#define regTHM_TCON_HTC_BASE_IDX 0 +#define regTHM_TCON_THERM_TRIP 0x0002 +#define regTHM_TCON_THERM_TRIP_BASE_IDX 0 +#define regTHM_CTF_DELAY 0x0004 +#define regTHM_CTF_DELAY_BASE_IDX 0 +#define regTHM_GPIO_PROCHOT_CTRL 0x0005 +#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0 +#define regTHM_SW_TEMP 0x0006 +#define regTHM_SW_TEMP_BASE_IDX 0 +#define regCG_MULT_THERMAL_CTRL 0x0007 +#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0 +#define regCG_MULT_THERMAL_STATUS 0x0008 +#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0 +#define regCG_THERMAL_RANGE 0x0009 +#define regCG_THERMAL_RANGE_BASE_IDX 0 +#define regTHM_TCON_LOCAL2 0x000a +#define regTHM_TCON_LOCAL2_BASE_IDX 0 +#define regTHM_TCON_LOCAL3 0x000b +#define regTHM_TCON_LOCAL3_BASE_IDX 0 +#define regTHM_TCON_LOCAL4 0x000c +#define regTHM_TCON_LOCAL4_BASE_IDX 0 +#define regTHM_TCON_LOCAL5 0x000d +#define regTHM_TCON_LOCAL5_BASE_IDX 0 +#define regTHM_TCON_LOCAL6 0x000e +#define regTHM_TCON_LOCAL6_BASE_IDX 0 +#define regTHM_TCON_LOCAL7 0x000f +#define regTHM_TCON_LOCAL7_BASE_IDX 0 +#define regTHM_TCON_LOCAL8 0x0010 +#define regTHM_TCON_LOCAL8_BASE_IDX 0 +#define regTHM_TCON_LOCAL9 0x0011 +#define regTHM_TCON_LOCAL9_BASE_IDX 0 +#define regTHM_TCON_LOCAL10 0x0012 +#define regTHM_TCON_LOCAL10_BASE_IDX 0 +#define regTHM_TCON_LOCAL11 0x0013 +#define regTHM_TCON_LOCAL11_BASE_IDX 0 +#define regTHM_TCON_LOCAL12 0x0014 +#define regTHM_TCON_LOCAL12_BASE_IDX 0 +#define regTHM_TCON_LOCAL13 0x0015 +#define regTHM_TCON_LOCAL13_BASE_IDX 0 +#define regTHM_TCON_LOCAL14 0x0016 +#define regTHM_TCON_LOCAL14_BASE_IDX 0 +#define regTHM_TCON_LOCAL15 0x0017 +#define regTHM_TCON_LOCAL15_BASE_IDX 0 +#define regTHM_PWRMGT 0x001b +#define regTHM_PWRMGT_BASE_IDX 0 +#define regTHM_DIE1_TEMP 0x001c +#define regTHM_DIE1_TEMP_BASE_IDX 0 +#define regTHM_DIE2_TEMP 0x001d +#define regTHM_DIE2_TEMP_BASE_IDX 0 +#define regTHM_DIE3_TEMP 0x001e +#define regTHM_DIE3_TEMP_BASE_IDX 0 +#define regSMUSBI_SBIREGADDR 0x0124 +#define regSMUSBI_SBIREGADDR_BASE_IDX 0 +#define regSMUSBI_SBIREGDATA 0x0125 +#define regSMUSBI_SBIREGDATA_BASE_IDX 0 +#define regSMUSBI_ERRATA_STAT_REG 0x0129 +#define regSMUSBI_ERRATA_STAT_REG_BASE_IDX 0 +#define regSMUSBI_SBICTRL 0x012a +#define regSMUSBI_SBICTRL_BASE_IDX 0 +#define regSMUSBI_CKNBIRESET 0x012b +#define regSMUSBI_CKNBIRESET_BASE_IDX 0 +#define regSMUSBI_TIMING 0x012c +#define regSMUSBI_TIMING_BASE_IDX 0 +#define regSMUSBI_HS_TIMING 0x012d +#define regSMUSBI_HS_TIMING_BASE_IDX 0 +#define regSBTSI_REMOTE_TEMP 0x012e +#define regSBTSI_REMOTE_TEMP_BASE_IDX 0 +#define regSBRMI_CONTROL 0x012f +#define regSBRMI_CONTROL_BASE_IDX 0 +#define regSBRMI_COMMAND 0x0130 +#define regSBRMI_COMMAND_BASE_IDX 0 +#define regSBRMI_WRITE_DATA0 0x0132 +#define regSBRMI_WRITE_DATA0_BASE_IDX 0 +#define regSBRMI_WRITE_DATA1 0x0133 +#define regSBRMI_WRITE_DATA1_BASE_IDX 0 +#define regSBRMI_WRITE_DATA2 0x0134 +#define regSBRMI_WRITE_DATA2_BASE_IDX 0 +#define regSBRMI_READ_DATA0 0x0136 +#define regSBRMI_READ_DATA0_BASE_IDX 0 +#define regSBRMI_READ_DATA1 0x0137 +#define regSBRMI_READ_DATA1_BASE_IDX 0 +#define regSBRMI_CORE_EN_NUMBER 0x0138 +#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0 +#define regSBRMI_CORE_EN_STATUS0 0x0139 +#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0 +#define regSBRMI_CORE_EN_STATUS1 0x013a +#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0 +#define regSBRMI_APIC_STATUS0 0x013b +#define regSBRMI_APIC_STATUS0_BASE_IDX 0 +#define regSBRMI_APIC_STATUS1 0x013c +#define regSBRMI_APIC_STATUS1_BASE_IDX 0 +#define regSBRMI_MCE_STATUS0 0x013d +#define regSBRMI_MCE_STATUS0_BASE_IDX 0 +#define regSBRMI_MCE_STATUS1 0x013e +#define regSBRMI_MCE_STATUS1_BASE_IDX 0 +#define regSMBUS_CNTL0 0x013f +#define regSMBUS_CNTL0_BASE_IDX 0 +#define regSMBUS_CNTL1 0x0140 +#define regSMBUS_CNTL1_BASE_IDX 0 +#define regSMBUS_BLKWR_CMD_CTRL0 0x0141 +#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0 +#define regSMBUS_BLKWR_CMD_CTRL1 0x0142 +#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0 +#define regSMBUS_BLKRD_CMD_CTRL0 0x0143 +#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0 +#define regSMBUS_BLKRD_CMD_CTRL1 0x0144 +#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL0 0x0145 +#define regSMBUS_TIMING_CNTL0_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL1 0x0146 +#define regSMBUS_TIMING_CNTL1_BASE_IDX 0 +#define regSMBUS_TIMING_CNTL2 0x0147 +#define regSMBUS_TIMING_CNTL2_BASE_IDX 0 +#define regSMBUS_TRIGGER_CNTL 0x0148 +#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0 +#define regSMBUS_UDID_CNTL0 0x0149 +#define regSMBUS_UDID_CNTL0_BASE_IDX 0 +#define regSMBUS_UDID_CNTL1 0x014a +#define regSMBUS_UDID_CNTL1_BASE_IDX 0 +#define regSMBUS_UDID_CNTL2 0x014b +#define regSMBUS_UDID_CNTL2_BASE_IDX 0 +#define regSMUSBI_SMBUS 0x014c +#define regSMUSBI_SMBUS_BASE_IDX 0 +#define regSMUSBI_ALERT 0x014d +#define regSMUSBI_ALERT_BASE_IDX 0 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_sh_mask.h new file mode 100644 index 0000000000000..365eab646df72 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_sh_mask.h @@ -0,0 +1,567 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _thm_15_0_0_SH_MASK_HEADER +#define _thm_15_0_0_SH_MASK_HEADER + + +// addressBlock: thm_thm_SmuThmDec +//THM_TCON_CUR_TMP +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 +#define THM_TCON_CUR_TMP__REMOTE_TJ_SEL__SHIFT 0xd +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 +#define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 +#define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 +#define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL +#define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L +#define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L +#define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L +#define THM_TCON_CUR_TMP__REMOTE_TJ_SEL_MASK 0x00006000L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L +#define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L +#define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L +#define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L +#define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L +//THM_TCON_HTC +#define THM_TCON_HTC__HTC_EN__SHIFT 0x0 +#define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 +#define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 +#define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 +#define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 +#define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 +#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT__SHIFT 0x9 +#define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa +#define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb +#define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc +#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN__SHIFT 0xf +#define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 +#define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 +#define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b +#define THM_TCON_HTC__HTC_EN_MASK 0x00000001L +#define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L +#define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L +#define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L +#define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L +#define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT_MASK 0x00000200L +#define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L +#define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L +#define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L +#define THM_TCON_HTC__DIS_PROCHOT_PIN_IN_MASK 0x00008000L +#define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L +#define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L +#define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L +//THM_TCON_THERM_TRIP +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 +#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 +#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 +#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 +#define THM_TCON_THERM_TRIP__FCH_THERMTRIP_EN__SHIFT 0xe +#define THM_TCON_THERM_TRIP__FCH_THERMTRIP_STATUS__SHIFT 0xf +#define THM_TCON_THERM_TRIP__TSV_THERMTRIP_IN__SHIFT 0x10 +#define THM_TCON_THERM_TRIP__THERM_TP_LOCAL_SENSE__SHIFT 0x1d +#define THM_TCON_THERM_TRIP__THERM_TP_LOCAL__SHIFT 0x1e +#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f +#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L +#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L +#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L +#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L +#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L +#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L +#define THM_TCON_THERM_TRIP__FCH_THERMTRIP_EN_MASK 0x00004000L +#define THM_TCON_THERM_TRIP__FCH_THERMTRIP_STATUS_MASK 0x00008000L +#define THM_TCON_THERM_TRIP__TSV_THERMTRIP_IN_MASK 0x0FFF0000L +#define THM_TCON_THERM_TRIP__THERM_TP_LOCAL_SENSE_MASK 0x20000000L +#define THM_TCON_THERM_TRIP__THERM_TP_LOCAL_MASK 0x40000000L +#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L +//THM_CTF_DELAY +#define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 +#define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL +//THM_GPIO_PROCHOT_CTRL +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 +#define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 +#define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 +#define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 +#define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 +#define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 +#define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 +#define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 +#define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 +#define THM_GPIO_PROCHOT_CTRL__S2__SHIFT 0x9 +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 +#define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 +#define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 +#define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f +#define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L +#define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L +#define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L +#define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L +#define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L +#define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L +#define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L +#define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L +#define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L +#define THM_GPIO_PROCHOT_CTRL__S2_MASK 0x00000200L +#define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L +#define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L +#define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L +#define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L +#define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L +//THM_SW_TEMP +#define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 +#define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL +//CG_MULT_THERMAL_CTRL +#define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 +#define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 +#define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L +#define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L +#define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x3FF00000L +//CG_MULT_THERMAL_STATUS +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 +#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 +#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL +#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L +//CG_THERMAL_RANGE +#define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 +#define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 +#define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL +#define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L +//THM_TCON_LOCAL2 +#define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 +#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 +#define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 +#define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 +#define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa +#define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb +#define THM_TCON_LOCAL2__use_tsen_for_temp_sel__SHIFT 0xc +#define THM_TCON_LOCAL2__use_tro_for_temp_sel__SHIFT 0xd +#define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L +#define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL +#define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L +#define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L +#define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L +#define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L +#define THM_TCON_LOCAL2__use_tsen_for_temp_sel_MASK 0x00001000L +#define THM_TCON_LOCAL2__use_tro_for_temp_sel_MASK 0x00002000L +//THM_TCON_LOCAL3 +#define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 +#define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL +//THM_TCON_LOCAL4 +#define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 +#define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000001FFL +//THM_TCON_LOCAL5 +#define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 +#define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL +//THM_TCON_LOCAL6 +#define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 +#define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000001FFL +//THM_TCON_LOCAL7 +#define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 +#define THM_TCON_LOCAL7__THERMID_MASK 0x000001FFL +//THM_TCON_LOCAL8 +#define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 +#define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL +//THM_TCON_LOCAL9 +#define THM_TCON_LOCAL9__Tj_Max_TSEN0__SHIFT 0x0 +#define THM_TCON_LOCAL9__Tj_Max_TSEN0_MASK 0x000007FFL +//THM_TCON_LOCAL10 +#define THM_TCON_LOCAL10__TSEN0_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL10__TSEN0_Tj_Max_RS_ID_MASK 0x000001FFL +//THM_TCON_LOCAL11 +#define THM_TCON_LOCAL11__Tj_Max_TSEN1__SHIFT 0x0 +#define THM_TCON_LOCAL11__Tj_Max_TSEN1_MASK 0x000007FFL +//THM_TCON_LOCAL12 +#define THM_TCON_LOCAL12__TSEN1_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL12__TSEN1_Tj_Max_RS_ID_MASK 0x000001FFL +//THM_TCON_LOCAL13 +#define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 +#define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L +//THM_TCON_LOCAL14 +#define THM_TCON_LOCAL14__Tj_Max_TSEN2__SHIFT 0x0 +#define THM_TCON_LOCAL14__Tj_Max_TSEN2_MASK 0x000007FFL +//THM_TCON_LOCAL15 +#define THM_TCON_LOCAL15__TSEN2_Tj_Max_RS_ID__SHIFT 0x0 +#define THM_TCON_LOCAL15__TSEN2_Tj_Max_RS_ID_MASK 0x000001FFL +//THM_PWRMGT +#define THM_PWRMGT__CLK_GATE_EN__SHIFT 0x0 +#define THM_PWRMGT__CLK_GATE_ST__SHIFT 0x1 +#define THM_PWRMGT__DBG_CLK_GATE_EN__SHIFT 0x2 +#define THM_PWRMGT__CLK_GATE_MAX_CNT__SHIFT 0x8 +#define THM_PWRMGT__CLK_GATE_EN_MASK 0x00000001L +#define THM_PWRMGT__CLK_GATE_ST_MASK 0x00000002L +#define THM_PWRMGT__DBG_CLK_GATE_EN_MASK 0x00000004L +#define THM_PWRMGT__CLK_GATE_MAX_CNT_MASK 0x00FFFF00L +//THM_DIE1_TEMP +#define THM_DIE1_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE1_TEMP__VALID__SHIFT 0xb +#define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE1_TEMP__VALID_MASK 0x00000800L +//THM_DIE2_TEMP +#define THM_DIE2_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE2_TEMP__VALID__SHIFT 0xb +#define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE2_TEMP__VALID_MASK 0x00000800L +//THM_DIE3_TEMP +#define THM_DIE3_TEMP__TEMP__SHIFT 0x0 +#define THM_DIE3_TEMP__VALID__SHIFT 0xb +#define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL +#define THM_DIE3_TEMP__VALID_MASK 0x00000800L +//SMUSBI_SBIREGADDR +#define SMUSBI_SBIREGADDR__Address__SHIFT 0x0 +#define SMUSBI_SBIREGADDR__TSI_RMI_SEL__SHIFT 0x8 +#define SMUSBI_SBIREGADDR__SIZE__SHIFT 0x9 +#define SMUSBI_SBIREGADDR__Address_MASK 0x000000FFL +#define SMUSBI_SBIREGADDR__TSI_RMI_SEL_MASK 0x00000100L +#define SMUSBI_SBIREGADDR__SIZE_MASK 0x00000600L +//SMUSBI_SBIREGDATA +#define SMUSBI_SBIREGDATA__SBI_REGDATA__SHIFT 0x0 +#define SMUSBI_SBIREGDATA__SBI_REGDATA_MASK 0xFFFFFFFFL +//SMUSBI_ERRATA_STAT_REG +#define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG__SHIFT 0x0 +#define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG_MASK 0xFFFFFFFFL +//SMUSBI_SBICTRL +#define SMUSBI_SBICTRL__CK_SPRSBIWRDONE__SHIFT 0x0 +#define SMUSBI_SBICTRL__NB_SBISELECT__SHIFT 0x1 +#define SMUSBI_SBICTRL__NB_SBIADDR__SHIFT 0x2 +#define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE__SHIFT 0x5 +#define SMUSBI_SBICTRL__REMOTE_SBI_EN__SHIFT 0x6 +#define SMUSBI_SBICTRL__NB_SBIADDR_EXTEND__SHIFT 0x7 +#define SMUSBI_SBICTRL__CK_SPRSBIWRDONE_MASK 0x00000001L +#define SMUSBI_SBICTRL__NB_SBISELECT_MASK 0x00000002L +#define SMUSBI_SBICTRL__NB_SBIADDR_MASK 0x0000001CL +#define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE_MASK 0x00000020L +#define SMUSBI_SBICTRL__REMOTE_SBI_EN_MASK 0x00000040L +#define SMUSBI_SBICTRL__NB_SBIADDR_EXTEND_MASK 0x00000080L +//SMUSBI_CKNBIRESET +#define SMUSBI_CKNBIRESET__CKNBIRESET__SHIFT 0x0 +#define SMUSBI_CKNBIRESET__CKNBIRESET_MASK 0x00000001L +//SMUSBI_TIMING +#define SMUSBI_TIMING__SETUP_TIME__SHIFT 0x0 +#define SMUSBI_TIMING__SETUP_TIME_OVERRIDE__SHIFT 0x8 +#define SMUSBI_TIMING__HOLD_TIME__SHIFT 0x10 +#define SMUSBI_TIMING__HOLD_TIME_OVERRIDE__SHIFT 0x18 +#define SMUSBI_TIMING__DGLT_LMT_OVERRIDE__SHIFT 0x1b +#define SMUSBI_TIMING__DGLT_LMT__SHIFT 0x1c +#define SMUSBI_TIMING__SETUP_TIME_MASK 0x0000003FL +#define SMUSBI_TIMING__SETUP_TIME_OVERRIDE_MASK 0x00000100L +#define SMUSBI_TIMING__HOLD_TIME_MASK 0x00FF0000L +#define SMUSBI_TIMING__HOLD_TIME_OVERRIDE_MASK 0x01000000L +#define SMUSBI_TIMING__DGLT_LMT_OVERRIDE_MASK 0x08000000L +#define SMUSBI_TIMING__DGLT_LMT_MASK 0xF0000000L +//SMUSBI_HS_TIMING +#define SMUSBI_HS_TIMING__HS_SETUP_TIME__SHIFT 0x0 +#define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE__SHIFT 0x8 +#define SMUSBI_HS_TIMING__HS_HOLD_TIME__SHIFT 0x10 +#define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE__SHIFT 0x18 +#define SMUSBI_HS_TIMING__HS_SETUP_TIME_MASK 0x0000003FL +#define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE_MASK 0x00000100L +#define SMUSBI_HS_TIMING__HS_HOLD_TIME_MASK 0x00FF0000L +#define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE_MASK 0x01000000L +//SBTSI_REMOTE_TEMP +#define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb +#define SBTSI_REMOTE_TEMP__UNUSED__SHIFT 0x12 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 +#define SBTSI_REMOTE_TEMP__RemoteTcenQuadId__SHIFT 0x14 +#define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0003F800L +#define SBTSI_REMOTE_TEMP__UNUSED_MASK 0x00040000L +#define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L +#define SBTSI_REMOTE_TEMP__RemoteTcenQuadId_MASK 0x00300000L +//SBRMI_CONTROL +#define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 +#define SBRMI_CONTROL__DPD__SHIFT 0x1 +#define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 +#define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L +#define SBRMI_CONTROL__DPD_MASK 0x00000002L +#define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L +//SBRMI_COMMAND +#define SBRMI_COMMAND__Command__SHIFT 0x0 +#define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 +#define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 +#define SBRMI_COMMAND__CommandSent__SHIFT 0x18 +#define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 +#define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a +#define SBRMI_COMMAND__Status__SHIFT 0x1c +#define SBRMI_COMMAND__Command_MASK 0x000000FFL +#define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L +#define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L +#define SBRMI_COMMAND__CommandSent_MASK 0x01000000L +#define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L +#define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L +#define SBRMI_COMMAND__Status_MASK 0xF0000000L +//SBRMI_WRITE_DATA0 +#define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 +#define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 +#define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 +#define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 +#define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL +#define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L +//SBRMI_WRITE_DATA1 +#define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 +#define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 +#define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 +#define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 +#define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL +#define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L +//SBRMI_WRITE_DATA2 +#define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 +#define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 +#define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 +#define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 +#define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL +#define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L +#define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L +#define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L +//SBRMI_READ_DATA0 +#define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 +#define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 +#define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 +#define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 +#define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL +#define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L +#define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L +#define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L +//SBRMI_READ_DATA1 +#define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 +#define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 +#define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 +#define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 +#define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL +#define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L +#define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L +#define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L +//SBRMI_CORE_EN_NUMBER +#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 +#define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL +//SBRMI_CORE_EN_STATUS0 +#define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 +#define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL +//SBRMI_CORE_EN_STATUS1 +#define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 +#define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL +//SBRMI_APIC_STATUS0 +#define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 +#define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL +//SBRMI_APIC_STATUS1 +#define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 +#define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL +//SBRMI_MCE_STATUS0 +#define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 +#define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL +//SBRMI_MCE_STATUS1 +#define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 +#define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL +//SMBUS_CNTL0 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 +#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 +#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 +#define SMBUS_CNTL0__THM_READY__SHIFT 0x14 +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L +#define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL +#define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L +#define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L +#define SMBUS_CNTL0__THM_READY_MASK 0x00100000L +//SMBUS_CNTL1 +#define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 +#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 +#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 +#define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L +#define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL +#define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L +//SMBUS_BLKWR_CMD_CTRL0 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L +#define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L +//SMBUS_BLKWR_CMD_CTRL1 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L +#define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L +//SMBUS_BLKRD_CMD_CTRL0 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L +#define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L +//SMBUS_BLKRD_CMD_CTRL1 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L +#define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L +//SMBUS_TIMING_CNTL0 +#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 +#define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL +#define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L +//SMBUS_TIMING_CNTL1 +#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 +#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb +#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 +#define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL +#define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L +#define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L +#define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L +//SMBUS_TIMING_CNTL2 +#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 +#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd +#define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL +#define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L +//SMBUS_TRIGGER_CNTL +#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 +#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 +#define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L +#define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L +//SMBUS_UDID_CNTL0 +#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 +#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f +#define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL +#define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L +//SMBUS_UDID_CNTL1 +#define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 +#define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL +//SMBUS_UDID_CNTL2 +#define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 +#define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 +#define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 +#define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 +#define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 +#define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa +#define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L +#define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL +#define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L +#define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L +#define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L +#define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L +//SMUSBI_SMBUS +#define SMUSBI_SMBUS__Spare0__SHIFT 0x0 +#define SMUSBI_SMBUS__Spare1__SHIFT 0x1 +#define SMUSBI_SMBUS__ResBiasEn__SHIFT 0x2 +#define SMUSBI_SMBUS__CompSel__SHIFT 0x3 +#define SMUSBI_SMBUS__NG__SHIFT 0x4 +#define SMUSBI_SMBUS__I2cRxSel0__SHIFT 0x8 +#define SMUSBI_SMBUS__I2cRxSel1__SHIFT 0x9 +#define SMUSBI_SMBUS__PdEn0__SHIFT 0xa +#define SMUSBI_SMBUS__PdEn1__SHIFT 0xb +#define SMUSBI_SMBUS__FallSlewSel0__SHIFT 0xc +#define SMUSBI_SMBUS__FallSlewSel1__SHIFT 0xd +#define SMUSBI_SMBUS__Slewn__SHIFT 0xe +#define SMUSBI_SMBUS__SpikeRcEn__SHIFT 0xf +#define SMUSBI_SMBUS__SpikeRcSel__SHIFT 0x10 +#define SMUSBI_SMBUS__CSel0p9__SHIFT 0x11 +#define SMUSBI_SMBUS__CSel1p1__SHIFT 0x12 +#define SMUSBI_SMBUS__RSel0p9__SHIFT 0x13 +#define SMUSBI_SMBUS__RSel1p1__SHIFT 0x14 +#define SMUSBI_SMBUS__BiasCrtEn__SHIFT 0x15 +#define SMUSBI_SMBUS__DI2C0__SHIFT 0x16 +#define SMUSBI_SMBUS__DI2C1__SHIFT 0x17 +#define SMUSBI_SMBUS__DI2C0_OVERRIDE__SHIFT 0x18 +#define SMUSBI_SMBUS__DI2C1_OVERRIDE__SHIFT 0x19 +#define SMUSBI_SMBUS__Y0__SHIFT 0x1e +#define SMUSBI_SMBUS__Y1__SHIFT 0x1f +#define SMUSBI_SMBUS__Spare0_MASK 0x00000001L +#define SMUSBI_SMBUS__Spare1_MASK 0x00000002L +#define SMUSBI_SMBUS__ResBiasEn_MASK 0x00000004L +#define SMUSBI_SMBUS__CompSel_MASK 0x00000008L +#define SMUSBI_SMBUS__NG_MASK 0x000000F0L +#define SMUSBI_SMBUS__I2cRxSel0_MASK 0x00000100L +#define SMUSBI_SMBUS__I2cRxSel1_MASK 0x00000200L +#define SMUSBI_SMBUS__PdEn0_MASK 0x00000400L +#define SMUSBI_SMBUS__PdEn1_MASK 0x00000800L +#define SMUSBI_SMBUS__FallSlewSel0_MASK 0x00001000L +#define SMUSBI_SMBUS__FallSlewSel1_MASK 0x00002000L +#define SMUSBI_SMBUS__Slewn_MASK 0x00004000L +#define SMUSBI_SMBUS__SpikeRcEn_MASK 0x00008000L +#define SMUSBI_SMBUS__SpikeRcSel_MASK 0x00010000L +#define SMUSBI_SMBUS__CSel0p9_MASK 0x00020000L +#define SMUSBI_SMBUS__CSel1p1_MASK 0x00040000L +#define SMUSBI_SMBUS__RSel0p9_MASK 0x00080000L +#define SMUSBI_SMBUS__RSel1p1_MASK 0x00100000L +#define SMUSBI_SMBUS__BiasCrtEn_MASK 0x00200000L +#define SMUSBI_SMBUS__DI2C0_MASK 0x00400000L +#define SMUSBI_SMBUS__DI2C1_MASK 0x00800000L +#define SMUSBI_SMBUS__DI2C0_OVERRIDE_MASK 0x01000000L +#define SMUSBI_SMBUS__DI2C1_OVERRIDE_MASK 0x02000000L +#define SMUSBI_SMBUS__Y0_MASK 0x40000000L +#define SMUSBI_SMBUS__Y1_MASK 0x80000000L +//SMUSBI_ALERT +#define SMUSBI_ALERT__TXIMPSEL__SHIFT 0x0 +#define SMUSBI_ALERT__PD__SHIFT 0x1 +#define SMUSBI_ALERT__PU__SHIFT 0x2 +#define SMUSBI_ALERT__SCHMEN__SHIFT 0x3 +#define SMUSBI_ALERT__S0__SHIFT 0x4 +#define SMUSBI_ALERT__S1__SHIFT 0x5 +#define SMUSBI_ALERT__RXEN__SHIFT 0x6 +#define SMUSBI_ALERT__RXSEL0__SHIFT 0x7 +#define SMUSBI_ALERT__RXSEL1__SHIFT 0x8 +#define SMUSBI_ALERT__S2__SHIFT 0x9 +#define SMUSBI_ALERT__OE_OVERRIDE__SHIFT 0x10 +#define SMUSBI_ALERT__OE__SHIFT 0x11 +#define SMUSBI_ALERT__A_OVERRIDE__SHIFT 0x12 +#define SMUSBI_ALERT__A__SHIFT 0x13 +#define SMUSBI_ALERT__Y__SHIFT 0x1f +#define SMUSBI_ALERT__TXIMPSEL_MASK 0x00000001L +#define SMUSBI_ALERT__PD_MASK 0x00000002L +#define SMUSBI_ALERT__PU_MASK 0x00000004L +#define SMUSBI_ALERT__SCHMEN_MASK 0x00000008L +#define SMUSBI_ALERT__S0_MASK 0x00000010L +#define SMUSBI_ALERT__S1_MASK 0x00000020L +#define SMUSBI_ALERT__RXEN_MASK 0x00000040L +#define SMUSBI_ALERT__RXSEL0_MASK 0x00000080L +#define SMUSBI_ALERT__RXSEL1_MASK 0x00000100L +#define SMUSBI_ALERT__S2_MASK 0x00000200L +#define SMUSBI_ALERT__OE_OVERRIDE_MASK 0x00010000L +#define SMUSBI_ALERT__OE_MASK 0x00020000L +#define SMUSBI_ALERT__A_OVERRIDE_MASK 0x00040000L +#define SMUSBI_ALERT__A_MASK 0x00080000L +#define SMUSBI_ALERT__Y_MASK 0x80000000L + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h new file mode 100644 index 0000000000000..1051a788c9d7f --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_offset.h @@ -0,0 +1,1783 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _vcn_5_3_0_OFFSET_HEADER +#define _vcn_5_3_0_OFFSET_HEADER + + +// addressBlock: uvdctxind +// base address: 0x0 +#define ixUVD_CGC_MEM_CTRL 0x0000 +#define ixUVD_CGC_CTRL2 0x0001 +#define ixUVD_CGC_MEM_DS_CTRL 0x0002 +#define ixUVD_CGC_MEM_SD_CTRL 0x0003 +#define ixUVD_SW_SCRATCH_00 0x0004 +#define ixUVD_SW_SCRATCH_01 0x0005 +#define ixUVD_SW_SCRATCH_02 0x0006 +#define ixUVD_SW_SCRATCH_03 0x0007 +#define ixUVD_SW_SCRATCH_04 0x0008 +#define ixUVD_SW_SCRATCH_05 0x0009 +#define ixUVD_SW_SCRATCH_06 0x000a +#define ixUVD_SW_SCRATCH_07 0x000b +#define ixUVD_SW_SCRATCH_08 0x000c +#define ixUVD_SW_SCRATCH_09 0x000d +#define ixUVD_SW_SCRATCH_10 0x000e +#define ixUVD_SW_SCRATCH_11 0x000f +#define ixUVD_SW_SCRATCH_12 0x0010 +#define ixUVD_SW_SCRATCH_13 0x0011 +#define ixUVD_SW_SCRATCH_14 0x0012 +#define ixUVD_SW_SCRATCH_15 0x0013 +#define ixUVD_IH_SEM_CTRL 0x001e + + +// addressBlock: lmi_adp_indirect +// base address: 0x0 +#define ixUVD_LMI_CRC0 0x0000 +#define ixUVD_LMI_CRC1 0x0001 +#define ixUVD_LMI_CRC2 0x0002 +#define ixUVD_LMI_CRC3 0x0003 +#define ixUVD_LMI_CRC10 0x000a +#define ixUVD_LMI_CRC11 0x000b +#define ixUVD_LMI_CRC12 0x000c +#define ixUVD_LMI_CRC13 0x000d +#define ixUVD_LMI_CRC14 0x000e +#define ixUVD_LMI_CRC15 0x000f +#define ixUVD_LMI_SWAP_CNTL2 0x0029 +#define ixUVD_MEMCHECK_SYS_INT_EN 0x0134 +#define ixUVD_MEMCHECK_SYS_INT_STAT 0x0135 +#define ixUVD_MEMCHECK_SYS_INT_ACK 0x0136 +#define ixUVD_MEMCHECK_VCPU_INT_EN 0x0137 +#define ixUVD_MEMCHECK_VCPU_INT_STAT 0x0138 +#define ixUVD_MEMCHECK_VCPU_INT_ACK 0x0139 +#define ixUVD_MEMCHECK2_SYS_INT_STAT 0x0140 +#define ixUVD_MEMCHECK2_SYS_INT_ACK 0x0141 +#define ixUVD_MEMCHECK2_VCPU_INT_STAT 0x0142 +#define ixUVD_MEMCHECK2_VCPU_INT_ACK 0x0143 + + +// addressBlock: uvd_uvd_pg_dec +// base address: 0x1f800 +#define regUVD_IPX_DLDO_CONFIG 0x0000 +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1 +#define regUVD_IPX_DLDO_STATUS 0x0001 +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1 +#define regUVD_POWER_STATUS 0x0002 +#define regUVD_POWER_STATUS_BASE_IDX 1 +#define regUVD_JPEG_POWER_STATUS 0x0003 +#define regUVD_JPEG_POWER_STATUS_BASE_IDX 1 +#define regUVD_MC_DJPEG_RD_SPACE 0x0007 +#define regUVD_MC_DJPEG_RD_SPACE_BASE_IDX 1 +#define regUVD_MC_DJPEG_WR_SPACE 0x0008 +#define regUVD_MC_DJPEG_WR_SPACE_BASE_IDX 1 +#define regUVD_PG_IND_INDEX 0x000c +#define regUVD_PG_IND_INDEX_BASE_IDX 1 +#define regUVD_PG_IND_DATA 0x000e +#define regUVD_PG_IND_DATA_BASE_IDX 1 +#define regCC_UVD_HARVESTING 0x000f +#define regCC_UVD_HARVESTING_BASE_IDX 1 +#define regUVD_DPG_LMA_CTL 0x0011 +#define regUVD_DPG_LMA_CTL_BASE_IDX 1 +#define regUVD_DPG_LMA_DATA 0x0012 +#define regUVD_DPG_LMA_DATA_BASE_IDX 1 +#define regUVD_DPG_LMA_MASK 0x0013 +#define regUVD_DPG_LMA_MASK_BASE_IDX 1 +#define regUVD_DPG_PAUSE 0x0014 +#define regUVD_DPG_PAUSE_BASE_IDX 1 +#define regUVD_SCRATCH1 0x0015 +#define regUVD_SCRATCH1_BASE_IDX 1 +#define regUVD_SCRATCH2 0x0016 +#define regUVD_SCRATCH2_BASE_IDX 1 +#define regUVD_SCRATCH3 0x0017 +#define regUVD_SCRATCH3_BASE_IDX 1 +#define regUVD_SCRATCH4 0x0018 +#define regUVD_SCRATCH4_BASE_IDX 1 +#define regUVD_SCRATCH5 0x0019 +#define regUVD_SCRATCH5_BASE_IDX 1 +#define regUVD_SCRATCH6 0x001a +#define regUVD_SCRATCH6_BASE_IDX 1 +#define regUVD_SCRATCH7 0x001b +#define regUVD_SCRATCH7_BASE_IDX 1 +#define regUVD_SCRATCH8 0x001c +#define regUVD_SCRATCH8_BASE_IDX 1 +#define regUVD_SCRATCH9 0x001d +#define regUVD_SCRATCH9_BASE_IDX 1 +#define regUVD_SCRATCH10 0x001e +#define regUVD_SCRATCH10_BASE_IDX 1 +#define regUVD_SCRATCH11 0x001f +#define regUVD_SCRATCH11_BASE_IDX 1 +#define regUVD_SCRATCH12 0x0020 +#define regUVD_SCRATCH12_BASE_IDX 1 +#define regUVD_SCRATCH13 0x0021 +#define regUVD_SCRATCH13_BASE_IDX 1 +#define regUVD_SCRATCH14 0x0022 +#define regUVD_SCRATCH14_BASE_IDX 1 +#define regUVD_FREE_COUNTER_REG 0x0023 +#define regUVD_FREE_COUNTER_REG_BASE_IDX 1 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x0024 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x0025 +#define regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_DPG_VCPU_CACHE_OFFSET0 0x0026 +#define regUVD_DPG_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define regUVD_DPG_LMI_VCPU_CACHE_VMID 0x0027 +#define regUVD_DPG_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define regUVD_REG_FILTER_EN 0x0028 +#define regUVD_REG_FILTER_EN_BASE_IDX 1 +#define regUVD_SECURITY_REG_VIO_REPORT 0x0029 +#define regUVD_SECURITY_REG_VIO_REPORT_BASE_IDX 1 +#define regUVD_FW_VERSION 0x002a +#define regUVD_FW_VERSION_BASE_IDX 1 +#define regUVD_PF_STATUS 0x002c +#define regUVD_PF_STATUS_BASE_IDX 1 +#define regUVD_DPG_CLK_EN_VCPU_REPORT 0x002e +#define regUVD_DPG_CLK_EN_VCPU_REPORT_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR_DETECT_BOT_LO 0x002f +#define regCC_UVD_VCPU_ERR_DETECT_BOT_LO_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR_DETECT_BOT_HI 0x0030 +#define regCC_UVD_VCPU_ERR_DETECT_BOT_HI_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR_DETECT_TOP_LO 0x0031 +#define regCC_UVD_VCPU_ERR_DETECT_TOP_LO_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR_DETECT_TOP_HI 0x0032 +#define regCC_UVD_VCPU_ERR_DETECT_TOP_HI_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR 0x0033 +#define regCC_UVD_VCPU_ERR_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR_INST_ADDR_LO 0x0034 +#define regCC_UVD_VCPU_ERR_INST_ADDR_LO_BASE_IDX 1 +#define regCC_UVD_VCPU_ERR_INST_ADDR_HI 0x0035 +#define regCC_UVD_VCPU_ERR_INST_ADDR_HI_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC_SPACE 0x003d +#define regUVD_LMI_MMSCH_NC_SPACE_BASE_IDX 1 +#define regUVD_LMI_ATOMIC_SPACE 0x003e +#define regUVD_LMI_ATOMIC_SPACE_BASE_IDX 1 +#define regUVD_GFX8_ADDR_CONFIG 0x0041 +#define regUVD_GFX8_ADDR_CONFIG_BASE_IDX 1 +#define regUVD_GFX10_ADDR_CONFIG 0x0042 +#define regUVD_GFX10_ADDR_CONFIG_BASE_IDX 1 +#define regUVD_GPCNT2_CNTL 0x0043 +#define regUVD_GPCNT2_CNTL_BASE_IDX 1 +#define regUVD_GPCNT2_TARGET_LOWER 0x0044 +#define regUVD_GPCNT2_TARGET_LOWER_BASE_IDX 1 +#define regUVD_GPCNT2_STATUS_LOWER 0x0045 +#define regUVD_GPCNT2_STATUS_LOWER_BASE_IDX 1 +#define regUVD_GPCNT2_TARGET_UPPER 0x0046 +#define regUVD_GPCNT2_TARGET_UPPER_BASE_IDX 1 +#define regUVD_GPCNT2_STATUS_UPPER 0x0047 +#define regUVD_GPCNT2_STATUS_UPPER_BASE_IDX 1 +#define regUVD_GPCNT3_CNTL 0x0048 +#define regUVD_GPCNT3_CNTL_BASE_IDX 1 +#define regUVD_GPCNT3_TARGET_LOWER 0x0049 +#define regUVD_GPCNT3_TARGET_LOWER_BASE_IDX 1 +#define regUVD_GPCNT3_STATUS_LOWER 0x004a +#define regUVD_GPCNT3_STATUS_LOWER_BASE_IDX 1 +#define regUVD_GPCNT3_TARGET_UPPER 0x004b +#define regUVD_GPCNT3_TARGET_UPPER_BASE_IDX 1 +#define regUVD_GPCNT3_STATUS_UPPER 0x004c +#define regUVD_GPCNT3_STATUS_UPPER_BASE_IDX 1 +#define regUVD_VCLK_DS_CNTL 0x004d +#define regUVD_VCLK_DS_CNTL_BASE_IDX 1 +#define regUVD_DCLK_DS_CNTL 0x004e +#define regUVD_DCLK_DS_CNTL_BASE_IDX 1 +#define regUVD_TSC_LOWER 0x004f +#define regUVD_TSC_LOWER_BASE_IDX 1 +#define regUVD_TSC_UPPER 0x0050 +#define regUVD_TSC_UPPER_BASE_IDX 1 +#define regVCN_FEATURES 0x0051 +#define regVCN_FEATURES_BASE_IDX 1 +#define regUVD_GPUIOV_STATUS 0x0055 +#define regUVD_GPUIOV_STATUS_BASE_IDX 1 +#define regUVD_SCRATCH15 0x005c +#define regUVD_SCRATCH15_BASE_IDX 1 +#define regUVD_VERSION 0x005d +#define regUVD_VERSION_BASE_IDX 1 +#define regVCN_UMSCH_CNTL 0x005e +#define regVCN_UMSCH_CNTL_BASE_IDX 1 +#define regVCN_JPEG_DB_CTRL 0x0068 +#define regVCN_JPEG_DB_CTRL_BASE_IDX 1 +#define regVCN_RB1_DB_CTRL 0x0072 +#define regVCN_RB1_DB_CTRL_BASE_IDX 1 +#define regVCN_RB2_DB_CTRL 0x0073 +#define regVCN_RB2_DB_CTRL_BASE_IDX 1 +#define regVCN_RB3_DB_CTRL 0x0074 +#define regVCN_RB3_DB_CTRL_BASE_IDX 1 +#define regVCN_RB4_DB_CTRL 0x0075 +#define regVCN_RB4_DB_CTRL_BASE_IDX 1 +#define regVCN_UMSCH_RB_DB_CTRL 0x0076 +#define regVCN_UMSCH_RB_DB_CTRL_BASE_IDX 1 +#define regVCN_RB_DB_CTRL 0x0077 +#define regVCN_RB_DB_CTRL_BASE_IDX 1 +#define regVCN_AGDB_CTRL0 0x0079 +#define regVCN_AGDB_CTRL0_BASE_IDX 1 +#define regVCN_AGDB_CTRL1 0x007a +#define regVCN_AGDB_CTRL1_BASE_IDX 1 +#define regVCN_AGDB_CTRL2 0x007b +#define regVCN_AGDB_CTRL2_BASE_IDX 1 +#define regVCN_AGDB_CTRL3 0x007c +#define regVCN_AGDB_CTRL3_BASE_IDX 1 +#define regVCN_AGDB_CTRL4 0x007d +#define regVCN_AGDB_CTRL4_BASE_IDX 1 +#define regVCN_AGDB_CTRL5 0x007e +#define regVCN_AGDB_CTRL5_BASE_IDX 1 +#define regVCN_AGDB_MASK0 0x007f +#define regVCN_AGDB_MASK0_BASE_IDX 1 +#define regVCN_AGDB_MASK1 0x0080 +#define regVCN_AGDB_MASK1_BASE_IDX 1 +#define regVCN_AGDB_MASK2 0x0081 +#define regVCN_AGDB_MASK2_BASE_IDX 1 +#define regVCN_AGDB_MASK3 0x0082 +#define regVCN_AGDB_MASK3_BASE_IDX 1 +#define regVCN_AGDB_MASK4 0x0083 +#define regVCN_AGDB_MASK4_BASE_IDX 1 +#define regVCN_AGDB_MASK5 0x0084 +#define regVCN_AGDB_MASK5_BASE_IDX 1 +#define regVCN_RB_ENABLE 0x0085 +#define regVCN_RB_ENABLE_BASE_IDX 1 +#define regVCN_RB_WPTR_CTRL 0x0086 +#define regVCN_RB_WPTR_CTRL_BASE_IDX 1 +#define regUVD_RB_RPTR 0x00ac +#define regUVD_RB_RPTR_BASE_IDX 1 +#define regUVD_RB_WPTR 0x00ad +#define regUVD_RB_WPTR_BASE_IDX 1 +#define regUVD_RB_RPTR2 0x00ae +#define regUVD_RB_RPTR2_BASE_IDX 1 +#define regUVD_RB_WPTR2 0x00af +#define regUVD_RB_WPTR2_BASE_IDX 1 +#define regUVD_RB_RPTR3 0x00b0 +#define regUVD_RB_RPTR3_BASE_IDX 1 +#define regUVD_RB_WPTR3 0x00b1 +#define regUVD_RB_WPTR3_BASE_IDX 1 +#define regUVD_RB_RPTR4 0x00b2 +#define regUVD_RB_RPTR4_BASE_IDX 1 +#define regUVD_RB_WPTR4 0x00b3 +#define regUVD_RB_WPTR4_BASE_IDX 1 +#define regUVD_OUT_RB_RPTR 0x00b4 +#define regUVD_OUT_RB_RPTR_BASE_IDX 1 +#define regUVD_OUT_RB_WPTR 0x00b5 +#define regUVD_OUT_RB_WPTR_BASE_IDX 1 +#define regUVD_AUDIO_RB_RPTR 0x00b6 +#define regUVD_AUDIO_RB_RPTR_BASE_IDX 1 +#define regUVD_AUDIO_RB_WPTR 0x00b7 +#define regUVD_AUDIO_RB_WPTR_BASE_IDX 1 +#define regUVD_RBC_RB_RPTR 0x00b8 +#define regUVD_RBC_RB_RPTR_BASE_IDX 1 +#define regUVD_RBC_RB_WPTR 0x00b9 +#define regUVD_RBC_RB_WPTR_BASE_IDX 1 +#define regUVD_DPG_LMA_CTL2 0x00bb +#define regUVD_DPG_LMA_CTL2_BASE_IDX 1 +#define regUVD_IPX_DLDO_CONFIG_ONO0 0x00e5 +#define regUVD_IPX_DLDO_CONFIG_ONO0_BASE_IDX 1 +#define regUVD_IPX_DLDO_CONFIG_ONO1 0x00e6 +#define regUVD_IPX_DLDO_CONFIG_ONO1_BASE_IDX 1 + + +// addressBlock: uvd_uvddec +// base address: 0x1fc00 +#define regUVD_TOP_CTRL 0x0100 +#define regUVD_TOP_CTRL_BASE_IDX 1 +#define regUVD_CGC_GATE 0x0101 +#define regUVD_CGC_GATE_BASE_IDX 1 +#define regUVD_CGC_CTRL 0x0102 +#define regUVD_CGC_CTRL_BASE_IDX 1 +#define regAVM_SUVD_CGC_GATE 0x0104 +#define regAVM_SUVD_CGC_GATE_BASE_IDX 1 +#define regEFC_SUVD_CGC_GATE 0x0104 +#define regEFC_SUVD_CGC_GATE_BASE_IDX 1 +#define regENT_SUVD_CGC_GATE 0x0104 +#define regENT_SUVD_CGC_GATE_BASE_IDX 1 +#define regIME_SUVD_CGC_GATE 0x0104 +#define regIME_SUVD_CGC_GATE_BASE_IDX 1 +#define regPPU_SUVD_CGC_GATE 0x0104 +#define regPPU_SUVD_CGC_GATE_BASE_IDX 1 +#define regSAOE_SUVD_CGC_GATE 0x0104 +#define regSAOE_SUVD_CGC_GATE_BASE_IDX 1 +#define regSCM_SUVD_CGC_GATE 0x0104 +#define regSCM_SUVD_CGC_GATE_BASE_IDX 1 +#define regSDB_SUVD_CGC_GATE 0x0104 +#define regSDB_SUVD_CGC_GATE_BASE_IDX 1 +#define regSIT0_NXT_SUVD_CGC_GATE 0x0104 +#define regSIT0_NXT_SUVD_CGC_GATE_BASE_IDX 1 +#define regSIT1_NXT_SUVD_CGC_GATE 0x0104 +#define regSIT1_NXT_SUVD_CGC_GATE_BASE_IDX 1 +#define regSIT2_NXT_SUVD_CGC_GATE 0x0104 +#define regSIT2_NXT_SUVD_CGC_GATE_BASE_IDX 1 +#define regSIT_SUVD_CGC_GATE 0x0104 +#define regSIT_SUVD_CGC_GATE_BASE_IDX 1 +#define regSMPA_SUVD_CGC_GATE 0x0104 +#define regSMPA_SUVD_CGC_GATE_BASE_IDX 1 +#define regSMP_SUVD_CGC_GATE 0x0104 +#define regSMP_SUVD_CGC_GATE_BASE_IDX 1 +#define regSRE_SUVD_CGC_GATE 0x0104 +#define regSRE_SUVD_CGC_GATE_BASE_IDX 1 +#define regUVD_SUVD_CGC_GATE 0x0104 +#define regUVD_SUVD_CGC_GATE_BASE_IDX 1 +#define regAVM_SUVD_CGC_GATE2 0x0105 +#define regAVM_SUVD_CGC_GATE2_BASE_IDX 1 +#define regDBR_SUVD_CGC_GATE2 0x0105 +#define regDBR_SUVD_CGC_GATE2_BASE_IDX 1 +#define regENT_SUVD_CGC_GATE2 0x0105 +#define regENT_SUVD_CGC_GATE2_BASE_IDX 1 +#define regIME_SUVD_CGC_GATE2 0x0105 +#define regIME_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSAOE_SUVD_CGC_GATE2 0x0105 +#define regSAOE_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSDB_SUVD_CGC_GATE2 0x0105 +#define regSDB_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSIT0_NXT_SUVD_CGC_GATE2 0x0105 +#define regSIT0_NXT_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSIT1_NXT_SUVD_CGC_GATE2 0x0105 +#define regSIT1_NXT_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSIT2_NXT_SUVD_CGC_GATE2 0x0105 +#define regSIT2_NXT_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSIT_SUVD_CGC_GATE2 0x0105 +#define regSIT_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSMPA_SUVD_CGC_GATE2 0x0105 +#define regSMPA_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSMP_SUVD_CGC_GATE2 0x0105 +#define regSMP_SUVD_CGC_GATE2_BASE_IDX 1 +#define regSRE_SUVD_CGC_GATE2 0x0105 +#define regSRE_SUVD_CGC_GATE2_BASE_IDX 1 +#define regUVD_SUVD_CGC_GATE2 0x0105 +#define regUVD_SUVD_CGC_GATE2_BASE_IDX 1 +#define regAVM_SUVD_CGC_CTRL 0x0106 +#define regAVM_SUVD_CGC_CTRL_BASE_IDX 1 +#define regDBR_SUVD_CGC_CTRL 0x0106 +#define regDBR_SUVD_CGC_CTRL_BASE_IDX 1 +#define regEFC_SUVD_CGC_CTRL 0x0106 +#define regEFC_SUVD_CGC_CTRL_BASE_IDX 1 +#define regENT_SUVD_CGC_CTRL 0x0106 +#define regENT_SUVD_CGC_CTRL_BASE_IDX 1 +#define regIME_SUVD_CGC_CTRL 0x0106 +#define regIME_SUVD_CGC_CTRL_BASE_IDX 1 +#define regPPU_SUVD_CGC_CTRL 0x0106 +#define regPPU_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSAOE_SUVD_CGC_CTRL 0x0106 +#define regSAOE_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSCM_SUVD_CGC_CTRL 0x0106 +#define regSCM_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSDB_SUVD_CGC_CTRL 0x0106 +#define regSDB_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSIT0_NXT_SUVD_CGC_CTRL 0x0106 +#define regSIT0_NXT_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSIT1_NXT_SUVD_CGC_CTRL 0x0106 +#define regSIT1_NXT_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSIT2_NXT_SUVD_CGC_CTRL 0x0106 +#define regSIT2_NXT_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSIT_SUVD_CGC_CTRL 0x0106 +#define regSIT_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSMPA_SUVD_CGC_CTRL 0x0106 +#define regSMPA_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSMP_SUVD_CGC_CTRL 0x0106 +#define regSMP_SUVD_CGC_CTRL_BASE_IDX 1 +#define regSRE_SUVD_CGC_CTRL 0x0106 +#define regSRE_SUVD_CGC_CTRL_BASE_IDX 1 +#define regUVD_SUVD_CGC_CTRL 0x0106 +#define regUVD_SUVD_CGC_CTRL_BASE_IDX 1 +#define regUVD_CGC_CTRL3 0x010a +#define regUVD_CGC_CTRL3_BASE_IDX 1 +#define regUVD_GPCOM_VCPU_DATA0 0x0110 +#define regUVD_GPCOM_VCPU_DATA0_BASE_IDX 1 +#define regUVD_GPCOM_VCPU_DATA1 0x0111 +#define regUVD_GPCOM_VCPU_DATA1_BASE_IDX 1 +#define regUVD_GPCOM_SYS_CMD 0x0112 +#define regUVD_GPCOM_SYS_CMD_BASE_IDX 1 +#define regUVD_GPCOM_SYS_DATA0 0x0113 +#define regUVD_GPCOM_SYS_DATA0_BASE_IDX 1 +#define regUVD_GPCOM_SYS_DATA1 0x0114 +#define regUVD_GPCOM_SYS_DATA1_BASE_IDX 1 +#define regUVD_VCPU_INT_EN 0x0115 +#define regUVD_VCPU_INT_EN_BASE_IDX 1 +#define regUVD_VCPU_INT_STATUS 0x0116 +#define regUVD_VCPU_INT_STATUS_BASE_IDX 1 +#define regUVD_VCPU_INT_ACK 0x0117 +#define regUVD_VCPU_INT_ACK_BASE_IDX 1 +#define regUVD_VCPU_INT_ROUTE 0x0118 +#define regUVD_VCPU_INT_ROUTE_BASE_IDX 1 +#define regUVD_DRV_FW_MSG 0x0119 +#define regUVD_DRV_FW_MSG_BASE_IDX 1 +#define regUVD_FW_DRV_MSG_ACK 0x011a +#define regUVD_FW_DRV_MSG_ACK_BASE_IDX 1 +#define regUVD_SUVD_INT_EN 0x011b +#define regUVD_SUVD_INT_EN_BASE_IDX 1 +#define regUVD_SUVD_INT_STATUS 0x011c +#define regUVD_SUVD_INT_STATUS_BASE_IDX 1 +#define regUVD_SUVD_INT_ACK 0x011d +#define regUVD_SUVD_INT_ACK_BASE_IDX 1 +#define regUVD_ENC_VCPU_INT_EN 0x011e +#define regUVD_ENC_VCPU_INT_EN_BASE_IDX 1 +#define regUVD_ENC_VCPU_INT_STATUS 0x011f +#define regUVD_ENC_VCPU_INT_STATUS_BASE_IDX 1 +#define regUVD_ENC_VCPU_INT_ACK 0x0120 +#define regUVD_ENC_VCPU_INT_ACK_BASE_IDX 1 +#define regUVD_MASTINT_EN 0x0121 +#define regUVD_MASTINT_EN_BASE_IDX 1 +#define regUVD_SYS_INT_EN 0x0122 +#define regUVD_SYS_INT_EN_BASE_IDX 1 +#define regUVD_SYS_INT_STATUS 0x0123 +#define regUVD_SYS_INT_STATUS_BASE_IDX 1 +#define regUVD_SYS_INT_ACK 0x0124 +#define regUVD_SYS_INT_ACK_BASE_IDX 1 +#define regUVD_JOB_DONE 0x0125 +#define regUVD_JOB_DONE_BASE_IDX 1 +#define regUVD_CBUF_ID 0x0126 +#define regUVD_CBUF_ID_BASE_IDX 1 +#define regUVD_CONTEXT_ID 0x0127 +#define regUVD_CONTEXT_ID_BASE_IDX 1 +#define regUVD_CONTEXT_ID2 0x0128 +#define regUVD_CONTEXT_ID2_BASE_IDX 1 +#define regUVD_NO_OP 0x0129 +#define regUVD_NO_OP_BASE_IDX 1 +#define regUVD_RB_BASE_LO 0x012a +#define regUVD_RB_BASE_LO_BASE_IDX 1 +#define regUVD_RB_BASE_HI 0x012b +#define regUVD_RB_BASE_HI_BASE_IDX 1 +#define regUVD_RB_SIZE 0x012c +#define regUVD_RB_SIZE_BASE_IDX 1 +#define regUVD_RB_BASE_LO2 0x012f +#define regUVD_RB_BASE_LO2_BASE_IDX 1 +#define regUVD_RB_BASE_HI2 0x0130 +#define regUVD_RB_BASE_HI2_BASE_IDX 1 +#define regUVD_RB_SIZE2 0x0131 +#define regUVD_RB_SIZE2_BASE_IDX 1 +#define regUVD_RB_BASE_LO3 0x0134 +#define regUVD_RB_BASE_LO3_BASE_IDX 1 +#define regUVD_RB_BASE_HI3 0x0135 +#define regUVD_RB_BASE_HI3_BASE_IDX 1 +#define regUVD_RB_SIZE3 0x0136 +#define regUVD_RB_SIZE3_BASE_IDX 1 +#define regUVD_RB_BASE_LO4 0x0139 +#define regUVD_RB_BASE_LO4_BASE_IDX 1 +#define regUVD_RB_BASE_HI4 0x013a +#define regUVD_RB_BASE_HI4_BASE_IDX 1 +#define regUVD_RB_SIZE4 0x013b +#define regUVD_RB_SIZE4_BASE_IDX 1 +#define regUVD_OUT_RB_BASE_LO 0x013e +#define regUVD_OUT_RB_BASE_LO_BASE_IDX 1 +#define regUVD_OUT_RB_BASE_HI 0x013f +#define regUVD_OUT_RB_BASE_HI_BASE_IDX 1 +#define regUVD_OUT_RB_SIZE 0x0140 +#define regUVD_OUT_RB_SIZE_BASE_IDX 1 +#define regUVD_IOV_ACTIVE_FCN_ID 0x0143 +#define regUVD_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define regUVD_IOV_MAILBOX 0x0144 +#define regUVD_IOV_MAILBOX_BASE_IDX 1 +#define regUVD_IOV_MAILBOX_RESP 0x0145 +#define regUVD_IOV_MAILBOX_RESP_BASE_IDX 1 +#define regUVD_RB_ARB_CTRL 0x0146 +#define regUVD_RB_ARB_CTRL_BASE_IDX 1 +#define regUVD_CTX_INDEX 0x0147 +#define regUVD_CTX_INDEX_BASE_IDX 1 +#define regUVD_CTX_DATA 0x0148 +#define regUVD_CTX_DATA_BASE_IDX 1 +#define regUVD_CXW_WR 0x0149 +#define regUVD_CXW_WR_BASE_IDX 1 +#define regUVD_CXW_WR_INT_ID 0x014a +#define regUVD_CXW_WR_INT_ID_BASE_IDX 1 +#define regUVD_CXW_WR_INT_CTX_ID 0x014b +#define regUVD_CXW_WR_INT_CTX_ID_BASE_IDX 1 +#define regUVD_CXW_INT_ID 0x014c +#define regUVD_CXW_INT_ID_BASE_IDX 1 +#define regUVD_MPEG2_ERROR 0x014d +#define regUVD_MPEG2_ERROR_BASE_IDX 1 +#define regUVD_YBASE 0x0150 +#define regUVD_YBASE_BASE_IDX 1 +#define regUVD_UVBASE 0x0151 +#define regUVD_UVBASE_BASE_IDX 1 +#define regUVD_PITCH 0x0152 +#define regUVD_PITCH_BASE_IDX 1 +#define regUVD_WIDTH 0x0153 +#define regUVD_WIDTH_BASE_IDX 1 +#define regUVD_HEIGHT 0x0154 +#define regUVD_HEIGHT_BASE_IDX 1 +#define regUVD_PICCOUNT 0x0155 +#define regUVD_PICCOUNT_BASE_IDX 1 +#define regUVD_MPRD_INITIAL_XY 0x0156 +#define regUVD_MPRD_INITIAL_XY_BASE_IDX 1 +#define regUVD_MPEG2_CTRL 0x0157 +#define regUVD_MPEG2_CTRL_BASE_IDX 1 +#define regUVD_MB_CTL_BUF_BASE 0x0158 +#define regUVD_MB_CTL_BUF_BASE_BASE_IDX 1 +#define regUVD_PIC_CTL_BUF_BASE 0x0159 +#define regUVD_PIC_CTL_BUF_BASE_BASE_IDX 1 +#define regUVD_DXVA_BUF_SIZE 0x015a +#define regUVD_DXVA_BUF_SIZE_BASE_IDX 1 +#define regUVD_SCRATCH_NP 0x015b +#define regUVD_SCRATCH_NP_BASE_IDX 1 +#define regUVD_CLK_SWT_HANDSHAKE 0x015c +#define regUVD_CLK_SWT_HANDSHAKE_BASE_IDX 1 +#define regUVD_GP_SCRATCH0 0x015e +#define regUVD_GP_SCRATCH0_BASE_IDX 1 +#define regUVD_GP_SCRATCH1 0x015f +#define regUVD_GP_SCRATCH1_BASE_IDX 1 +#define regUVD_GP_SCRATCH2 0x0160 +#define regUVD_GP_SCRATCH2_BASE_IDX 1 +#define regUVD_GP_SCRATCH3 0x0161 +#define regUVD_GP_SCRATCH3_BASE_IDX 1 +#define regUVD_GP_SCRATCH4 0x0162 +#define regUVD_GP_SCRATCH4_BASE_IDX 1 +#define regUVD_GP_SCRATCH5 0x0163 +#define regUVD_GP_SCRATCH5_BASE_IDX 1 +#define regUVD_GP_SCRATCH6 0x0164 +#define regUVD_GP_SCRATCH6_BASE_IDX 1 +#define regUVD_GP_SCRATCH7 0x0165 +#define regUVD_GP_SCRATCH7_BASE_IDX 1 +#define regUVD_GP_SCRATCH8 0x0166 +#define regUVD_GP_SCRATCH8_BASE_IDX 1 +#define regUVD_GP_SCRATCH9 0x0167 +#define regUVD_GP_SCRATCH9_BASE_IDX 1 +#define regUVD_GP_SCRATCH10 0x0168 +#define regUVD_GP_SCRATCH10_BASE_IDX 1 +#define regUVD_GP_SCRATCH11 0x0169 +#define regUVD_GP_SCRATCH11_BASE_IDX 1 +#define regUVD_GP_SCRATCH12 0x016a +#define regUVD_GP_SCRATCH12_BASE_IDX 1 +#define regUVD_GP_SCRATCH13 0x016b +#define regUVD_GP_SCRATCH13_BASE_IDX 1 +#define regUVD_GP_SCRATCH14 0x016c +#define regUVD_GP_SCRATCH14_BASE_IDX 1 +#define regUVD_GP_SCRATCH15 0x016d +#define regUVD_GP_SCRATCH15_BASE_IDX 1 +#define regUVD_GP_SCRATCH16 0x016e +#define regUVD_GP_SCRATCH16_BASE_IDX 1 +#define regUVD_GP_SCRATCH17 0x016f +#define regUVD_GP_SCRATCH17_BASE_IDX 1 +#define regUVD_GP_SCRATCH18 0x0170 +#define regUVD_GP_SCRATCH18_BASE_IDX 1 +#define regUVD_GP_SCRATCH19 0x0171 +#define regUVD_GP_SCRATCH19_BASE_IDX 1 +#define regUVD_GP_SCRATCH20 0x0172 +#define regUVD_GP_SCRATCH20_BASE_IDX 1 +#define regUVD_GP_SCRATCH21 0x0173 +#define regUVD_GP_SCRATCH21_BASE_IDX 1 +#define regUVD_GP_SCRATCH22 0x0174 +#define regUVD_GP_SCRATCH22_BASE_IDX 1 +#define regUVD_GP_SCRATCH23 0x0175 +#define regUVD_GP_SCRATCH23_BASE_IDX 1 +#define regUVD_AUDIO_RB_BASE_LO 0x0176 +#define regUVD_AUDIO_RB_BASE_LO_BASE_IDX 1 +#define regUVD_AUDIO_RB_BASE_HI 0x0177 +#define regUVD_AUDIO_RB_BASE_HI_BASE_IDX 1 +#define regUVD_AUDIO_RB_SIZE 0x0178 +#define regUVD_AUDIO_RB_SIZE_BASE_IDX 1 +#define regUVD_VCPU_INT_STATUS2 0x017b +#define regUVD_VCPU_INT_STATUS2_BASE_IDX 1 +#define regUVD_VCPU_INT_ACK2 0x017c +#define regUVD_VCPU_INT_ACK2_BASE_IDX 1 +#define regUVD_VCPU_INT_EN2 0x017d +#define regUVD_VCPU_INT_EN2_BASE_IDX 1 +#define regUVD_SUVD_CGC_STATUS2 0x017e +#define regUVD_SUVD_CGC_STATUS2_BASE_IDX 1 +#define regUVD_SUVD_INT_STATUS2 0x0180 +#define regUVD_SUVD_INT_STATUS2_BASE_IDX 1 +#define regUVD_SUVD_INT_EN2 0x0181 +#define regUVD_SUVD_INT_EN2_BASE_IDX 1 +#define regUVD_SUVD_INT_ACK2 0x0182 +#define regUVD_SUVD_INT_ACK2_BASE_IDX 1 +#define regUVD_STATUS 0x0183 +#define regUVD_STATUS_BASE_IDX 1 +#define regUVD_ENC_PIPE_BUSY 0x0184 +#define regUVD_ENC_PIPE_BUSY_BASE_IDX 1 +#define regUVD_FW_POWER_STATUS 0x0185 +#define regUVD_FW_POWER_STATUS_BASE_IDX 1 +#define regUVD_CNTL 0x0186 +#define regUVD_CNTL_BASE_IDX 1 +#define regUVD_SOFT_RESET 0x0187 +#define regUVD_SOFT_RESET_BASE_IDX 1 +#define regUVD_SOFT_RESET2 0x0188 +#define regUVD_SOFT_RESET2_BASE_IDX 1 +#define regUVD_MMSCH_SOFT_RESET 0x0189 +#define regUVD_MMSCH_SOFT_RESET_BASE_IDX 1 +#define regUVD_WIG_CTRL 0x018a +#define regUVD_WIG_CTRL_BASE_IDX 1 +#define regUVD_CGC_STATUS 0x018c +#define regUVD_CGC_STATUS_BASE_IDX 1 +#define regUVD_CGC_UDEC_STATUS 0x018e +#define regUVD_CGC_UDEC_STATUS_BASE_IDX 1 +#define regUVD_SUVD_CGC_STATUS 0x0190 +#define regUVD_SUVD_CGC_STATUS_BASE_IDX 1 +#define regUVD_GPCOM_VCPU_CMD 0x0192 +#define regUVD_GPCOM_VCPU_CMD_BASE_IDX 1 + + +// addressBlock: uvd_vcn_cdefe_cdefe_broadcast_dec0 +// base address: 0x1fc00 +#define regCDEFE_SUVD_CGC_GATE 0x0104 +#define regCDEFE_SUVD_CGC_GATE_BASE_IDX 1 +#define regCDEFE_SUVD_CGC_GATE2 0x0105 +#define regCDEFE_SUVD_CGC_GATE2_BASE_IDX 1 +#define regCDEFE_SUVD_CGC_CTRL 0x0106 +#define regCDEFE_SUVD_CGC_CTRL_BASE_IDX 1 + + +// addressBlock: uvd_ecpudec +// base address: 0x1ff00 +#define regUVD_VCPU_CACHE_OFFSET0 0x01c0 +#define regUVD_VCPU_CACHE_OFFSET0_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE0 0x01c1 +#define regUVD_VCPU_CACHE_SIZE0_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET1 0x01c2 +#define regUVD_VCPU_CACHE_OFFSET1_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE1 0x01c3 +#define regUVD_VCPU_CACHE_SIZE1_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET2 0x01c4 +#define regUVD_VCPU_CACHE_OFFSET2_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE2 0x01c5 +#define regUVD_VCPU_CACHE_SIZE2_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET3 0x01c6 +#define regUVD_VCPU_CACHE_OFFSET3_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE3 0x01c7 +#define regUVD_VCPU_CACHE_SIZE3_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET4 0x01c8 +#define regUVD_VCPU_CACHE_OFFSET4_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE4 0x01c9 +#define regUVD_VCPU_CACHE_SIZE4_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET5 0x01ca +#define regUVD_VCPU_CACHE_OFFSET5_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE5 0x01cb +#define regUVD_VCPU_CACHE_SIZE5_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET6 0x01cc +#define regUVD_VCPU_CACHE_OFFSET6_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE6 0x01cd +#define regUVD_VCPU_CACHE_SIZE6_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET7 0x01ce +#define regUVD_VCPU_CACHE_OFFSET7_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE7 0x01cf +#define regUVD_VCPU_CACHE_SIZE7_BASE_IDX 1 +#define regUVD_VCPU_CACHE_OFFSET8 0x01d0 +#define regUVD_VCPU_CACHE_OFFSET8_BASE_IDX 1 +#define regUVD_VCPU_CACHE_SIZE8 0x01d1 +#define regUVD_VCPU_CACHE_SIZE8_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_OFFSET0 0x01d2 +#define regUVD_VCPU_NONCACHE_OFFSET0_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_SIZE0 0x01d3 +#define regUVD_VCPU_NONCACHE_SIZE0_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_OFFSET1 0x01d4 +#define regUVD_VCPU_NONCACHE_OFFSET1_BASE_IDX 1 +#define regUVD_VCPU_NONCACHE_SIZE1 0x01d5 +#define regUVD_VCPU_NONCACHE_SIZE1_BASE_IDX 1 +#define regUVD_VCPU_CNTL 0x01d6 +#define regUVD_VCPU_CNTL_BASE_IDX 1 +#define regUVD_VCPU_PRID 0x01d7 +#define regUVD_VCPU_PRID_BASE_IDX 1 +#define regUVD_VCPU_TRCE 0x01d8 +#define regUVD_VCPU_TRCE_BASE_IDX 1 +#define regUVD_VCPU_TRCE_RD 0x01d9 +#define regUVD_VCPU_TRCE_RD_BASE_IDX 1 +#define regUVD_VCPU_IND_INDEX 0x01db +#define regUVD_VCPU_IND_INDEX_BASE_IDX 1 +#define regUVD_VCPU_IND_DATA 0x01dc +#define regUVD_VCPU_IND_DATA_BASE_IDX 1 + + +// addressBlock: uvd_lmi_adpdec +// base address: 0x20290 +#define regUVD_LMI_RE_64BIT_BAR_LOW 0x02af +#define regUVD_LMI_RE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_RE_64BIT_BAR_HIGH 0x02b0 +#define regUVD_LMI_RE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_IT_64BIT_BAR_LOW 0x02b1 +#define regUVD_LMI_IT_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_IT_64BIT_BAR_HIGH 0x02b2 +#define regUVD_LMI_IT_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MP_64BIT_BAR_LOW 0x02b3 +#define regUVD_LMI_MP_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MP_64BIT_BAR_HIGH 0x02b4 +#define regUVD_LMI_MP_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_CM_64BIT_BAR_LOW 0x02b5 +#define regUVD_LMI_CM_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_CM_64BIT_BAR_HIGH 0x02b6 +#define regUVD_LMI_CM_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_DB_64BIT_BAR_LOW 0x02b7 +#define regUVD_LMI_DB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_DB_64BIT_BAR_HIGH 0x02b8 +#define regUVD_LMI_DB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_DBW_64BIT_BAR_LOW 0x02b9 +#define regUVD_LMI_DBW_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_DBW_64BIT_BAR_HIGH 0x02ba +#define regUVD_LMI_DBW_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_IDCT_64BIT_BAR_LOW 0x02bb +#define regUVD_LMI_IDCT_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_IDCT_64BIT_BAR_HIGH 0x02bc +#define regUVD_LMI_IDCT_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW 0x02bd +#define regUVD_LMI_MPRD_S0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH 0x02be +#define regUVD_LMI_MPRD_S0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW 0x02bf +#define regUVD_LMI_MPRD_S1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH 0x02c0 +#define regUVD_LMI_MPRD_S1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW 0x02c1 +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH 0x02c2 +#define regUVD_LMI_MPRD_DBW_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x02c5 +#define regUVD_LMI_RBC_RB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x02c6 +#define regUVD_LMI_RBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x02c7 +#define regUVD_LMI_RBC_IB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x02c8 +#define regUVD_LMI_RBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_LBSI_64BIT_BAR_LOW 0x02c9 +#define regUVD_LMI_LBSI_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_LBSI_64BIT_BAR_HIGH 0x02ca +#define regUVD_LMI_LBSI_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW 0x02cb +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 0x02cc +#define regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW 0x02cd +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 0x02ce +#define regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x02cf +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x02d0 +#define regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_CENC_64BIT_BAR_LOW 0x02d1 +#define regUVD_LMI_CENC_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_CENC_64BIT_BAR_HIGH 0x02d2 +#define regUVD_LMI_CENC_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_SRE_64BIT_BAR_LOW 0x02d3 +#define regUVD_LMI_SRE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_SRE_64BIT_BAR_HIGH 0x02d4 +#define regUVD_LMI_SRE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW 0x02d5 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH 0x02d6 +#define regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW 0x02d7 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH 0x02d8 +#define regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW 0x02d9 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH 0x02da +#define regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW 0x02dd +#define regUVD_LMI_MIF_DBW_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH 0x02de +#define regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW 0x02df +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH 0x02e0 +#define regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW 0x02e1 +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH 0x02e2 +#define regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW 0x02e3 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH 0x02e4 +#define regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW 0x02e5 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH 0x02e6 +#define regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW 0x02e7 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH 0x02e8 +#define regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW 0x02e9 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH 0x02ea +#define regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW 0x02eb +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH 0x02ec +#define regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW 0x02ed +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH 0x02ee +#define regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW 0x02ef +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH 0x02f0 +#define regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW 0x02f1 +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH 0x02f2 +#define regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 0x02fb +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x02fc +#define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 0x02fd +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 0x02fe +#define regUVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 0x02ff +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 0x0300 +#define regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 0x0301 +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 0x0302 +#define regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 0x0303 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 0x0304 +#define regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 0x0305 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 0x0306 +#define regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 0x0307 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 0x0308 +#define regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 0x0309 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 0x030a +#define regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW 0x030b +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH 0x030c +#define regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW 0x030d +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH 0x030e +#define regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_SPH_64BIT_BAR_HIGH 0x030f +#define regUVD_LMI_SPH_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW 0x0318 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH 0x0319 +#define regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW 0x031a +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH 0x031b +#define regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW 0x031c +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH 0x031d +#define regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW 0x031e +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH 0x031f +#define regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_ADP_ATOMIC_CONFIG 0x0321 +#define regUVD_ADP_ATOMIC_CONFIG_BASE_IDX 1 +#define regUVD_LMI_ARB_CTRL2 0x0322 +#define regUVD_LMI_ARB_CTRL2_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI 0x0327 +#define regUVD_LMI_VCPU_CACHE_VMIDS_MULTI_BASE_IDX 1 +#define regUVD_LMI_VCPU_NC_VMIDS_MULTI 0x0328 +#define regUVD_LMI_VCPU_NC_VMIDS_MULTI_BASE_IDX 1 +#define regUVD_LMI_LAT_CTRL 0x0329 +#define regUVD_LMI_LAT_CTRL_BASE_IDX 1 +#define regUVD_LMI_LAT_CNTR 0x032a +#define regUVD_LMI_LAT_CNTR_BASE_IDX 1 +#define regUVD_LMI_AVG_LAT_CNTR 0x032b +#define regUVD_LMI_AVG_LAT_CNTR_BASE_IDX 1 +#define regUVD_LMI_SPH 0x032c +#define regUVD_LMI_SPH_BASE_IDX 1 +#define regUVD_LMI_VCPU_CACHE_VMID 0x032d +#define regUVD_LMI_VCPU_CACHE_VMID_BASE_IDX 1 +#define regUVD_LMI_CTRL2 0x032e +#define regUVD_LMI_CTRL2_BASE_IDX 1 +#define regUVD_LMI_URGENT_CTRL 0x032f +#define regUVD_LMI_URGENT_CTRL_BASE_IDX 1 +#define regUVD_LMI_CTRL 0x0330 +#define regUVD_LMI_CTRL_BASE_IDX 1 +#define regUVD_LMI_STATUS 0x0331 +#define regUVD_LMI_STATUS_BASE_IDX 1 +#define regUVD_LMI_PERFMON_CTRL 0x0334 +#define regUVD_LMI_PERFMON_CTRL_BASE_IDX 1 +#define regUVD_LMI_PERFMON_COUNT_LO 0x0335 +#define regUVD_LMI_PERFMON_COUNT_LO_BASE_IDX 1 +#define regUVD_LMI_PERFMON_COUNT_HI 0x0336 +#define regUVD_LMI_PERFMON_COUNT_HI_BASE_IDX 1 +#define regUVD_LMI_ADP_SWAP_CNTL 0x0337 +#define regUVD_LMI_ADP_SWAP_CNTL_BASE_IDX 1 +#define regUVD_LMI_RBC_RB_VMID 0x0338 +#define regUVD_LMI_RBC_RB_VMID_BASE_IDX 1 +#define regUVD_LMI_RBC_IB_VMID 0x0339 +#define regUVD_LMI_RBC_IB_VMID_BASE_IDX 1 +#define regUVD_LMI_MC_CREDITS 0x033a +#define regUVD_LMI_MC_CREDITS_BASE_IDX 1 +#define regUVD_LMI_ADP_IND_INDEX 0x033e +#define regUVD_LMI_ADP_IND_INDEX_BASE_IDX 1 +#define regUVD_LMI_ADP_IND_DATA 0x033f +#define regUVD_LMI_ADP_IND_DATA_BASE_IDX 1 +#define regUVD_LMI_ADP_PF_EN 0x0340 +#define regUVD_LMI_ADP_PF_EN_BASE_IDX 1 +#define regUVD_LMI_PREF_CTRL 0x0342 +#define regUVD_LMI_PREF_CTRL_BASE_IDX 1 + + +// addressBlock: uvd_uvd_dct_decoder_rbc_0_uvd_jrbc_dec +// base address: 0x20b00 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x04c0 +#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_CNTL 0x04c1 +#define regUVD_JRBC1_UVD_JRBC_RB_CNTL_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_IB_SIZE 0x04c2 +#define regUVD_JRBC1_UVD_JRBC_IB_SIZE_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_URGENT_CNTL 0x04c3 +#define regUVD_JRBC1_UVD_JRBC_URGENT_CNTL_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_REF_DATA 0x04c4 +#define regUVD_JRBC1_UVD_JRBC_RB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER 0x04c5 +#define regUVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_SOFT_RESET 0x04c8 +#define regUVD_JRBC1_UVD_JRBC_SOFT_RESET_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_STATUS 0x04c9 +#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x04ca +#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_BUF_STATUS 0x04cb +#define regUVD_JRBC1_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_IB_BUF_STATUS 0x04cc +#define regUVD_JRBC1_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE 0x04cd +#define regUVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER 0x04ce +#define regUVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_IB_REF_DATA 0x04cf +#define regUVD_JRBC1_UVD_JRBC_IB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JPEG_PREEMPT_CMD 0x04d0 +#define regUVD_JRBC1_UVD_JPEG_PREEMPT_CMD_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0 0x04d1 +#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1 0x04d2 +#define regUVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_RB_SIZE 0x04d3 +#define regUVD_JRBC1_UVD_JRBC_RB_SIZE_BASE_IDX 1 +#define regUVD_JRBC1_UVD_JRBC_SCRATCH0 0x04d4 +#define regUVD_JRBC1_UVD_JRBC_SCRATCH0_BASE_IDX 1 + + +// addressBlock: uvd_uvd_dct_decoder_rbc_1_uvd_jrbc_dec +// base address: 0x20c00 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0500 +#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_RB_CNTL 0x0501 +#define regUVD_JRBC2_UVD_JRBC_RB_CNTL_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_IB_SIZE 0x0502 +#define regUVD_JRBC2_UVD_JRBC_IB_SIZE_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_URGENT_CNTL 0x0503 +#define regUVD_JRBC2_UVD_JRBC_URGENT_CNTL_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_RB_REF_DATA 0x0504 +#define regUVD_JRBC2_UVD_JRBC_RB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER 0x0505 +#define regUVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_SOFT_RESET 0x0508 +#define regUVD_JRBC2_UVD_JRBC_SOFT_RESET_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0509 +#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x050a +#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_RB_BUF_STATUS 0x050b +#define regUVD_JRBC2_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_IB_BUF_STATUS 0x050c +#define regUVD_JRBC2_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE 0x050d +#define regUVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER 0x050e +#define regUVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_IB_REF_DATA 0x050f +#define regUVD_JRBC2_UVD_JRBC_IB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JPEG_PREEMPT_CMD 0x0510 +#define regUVD_JRBC2_UVD_JPEG_PREEMPT_CMD_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0511 +#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0512 +#define regUVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_RB_SIZE 0x0513 +#define regUVD_JRBC2_UVD_JRBC_RB_SIZE_BASE_IDX 1 +#define regUVD_JRBC2_UVD_JRBC_SCRATCH0 0x0514 +#define regUVD_JRBC2_UVD_JRBC_SCRATCH0_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jpeg0_jpegnpdec +// base address: 0x20f00 +#define regUVD_JPEG_CNTL 0x05c0 +#define regUVD_JPEG_CNTL_BASE_IDX 1 +#define regUVD_JPEG_RB_BASE 0x05c1 +#define regUVD_JPEG_RB_BASE_BASE_IDX 1 +#define regUVD_JPEG_RB_WPTR 0x05c2 +#define regUVD_JPEG_RB_WPTR_BASE_IDX 1 +#define regUVD_JPEG_RB_RPTR 0x05c3 +#define regUVD_JPEG_RB_RPTR_BASE_IDX 1 +#define regUVD_JPEG_RB_SIZE 0x05c4 +#define regUVD_JPEG_RB_SIZE_BASE_IDX 1 +#define regUVD_JPEG_DEC_CNT 0x05c5 +#define regUVD_JPEG_DEC_CNT_BASE_IDX 1 +#define regUVD_JPEG_SPS_INFO 0x05c6 +#define regUVD_JPEG_SPS_INFO_BASE_IDX 1 +#define regUVD_JPEG_SPS1_INFO 0x05c7 +#define regUVD_JPEG_SPS1_INFO_BASE_IDX 1 +#define regUVD_JPEG_RE_TIMER 0x05c8 +#define regUVD_JPEG_RE_TIMER_BASE_IDX 1 +#define regUVD_JPEG_DEC_SCRATCH0 0x05c9 +#define regUVD_JPEG_DEC_SCRATCH0_BASE_IDX 1 +#define regUVD_JPEG_INT_EN 0x05ca +#define regUVD_JPEG_INT_EN_BASE_IDX 1 +#define regUVD_JPEG_INT_STAT 0x05cb +#define regUVD_JPEG_INT_STAT_BASE_IDX 1 +#define regUVD_JPEG_TIER_CNTL0 0x05cc +#define regUVD_JPEG_TIER_CNTL0_BASE_IDX 1 +#define regUVD_JPEG_TIER_CNTL1 0x05cd +#define regUVD_JPEG_TIER_CNTL1_BASE_IDX 1 +#define regUVD_JPEG_TIER_CNTL2 0x05ce +#define regUVD_JPEG_TIER_CNTL2_BASE_IDX 1 +#define regUVD_JPEG_TIER_STATUS 0x05cf +#define regUVD_JPEG_TIER_STATUS_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jpeg_sclk0_jpegnpsclkdec +// base address: 0x21000 +#define regUVD_JPEG_OUTBUF_CNTL 0x0600 +#define regUVD_JPEG_OUTBUF_CNTL_BASE_IDX 1 +#define regUVD_JPEG_OUTBUF_WPTR 0x0601 +#define regUVD_JPEG_OUTBUF_WPTR_BASE_IDX 1 +#define regUVD_JPEG_OUTBUF_RPTR 0x0602 +#define regUVD_JPEG_OUTBUF_RPTR_BASE_IDX 1 +#define regUVD_JPEG_PITCH 0x0603 +#define regUVD_JPEG_PITCH_BASE_IDX 1 +#define regUVD_JPEG_UV_PITCH 0x0604 +#define regUVD_JPEG_UV_PITCH_BASE_IDX 1 +#define regJPEG_DEC_Y_GFX8_TILING_SURFACE 0x0605 +#define regJPEG_DEC_Y_GFX8_TILING_SURFACE_BASE_IDX 1 +#define regJPEG_DEC_UV_GFX8_TILING_SURFACE 0x0606 +#define regJPEG_DEC_UV_GFX8_TILING_SURFACE_BASE_IDX 1 +#define regJPEG_DEC_GFX8_ADDR_CONFIG 0x0607 +#define regJPEG_DEC_GFX8_ADDR_CONFIG_BASE_IDX 1 +#define regJPEG_DEC_Y_GFX10_TILING_SURFACE 0x0608 +#define regJPEG_DEC_Y_GFX10_TILING_SURFACE_BASE_IDX 1 +#define regJPEG_DEC_UV_GFX10_TILING_SURFACE 0x0609 +#define regJPEG_DEC_UV_GFX10_TILING_SURFACE_BASE_IDX 1 +#define regJPEG_DEC_GFX10_ADDR_CONFIG 0x060a +#define regJPEG_DEC_GFX10_ADDR_CONFIG_BASE_IDX 1 +#define regJPEG_DEC_ADDR_MODE 0x060b +#define regJPEG_DEC_ADDR_MODE_BASE_IDX 1 +#define regUVD_JPEG_OUTPUT_XY 0x060c +#define regUVD_JPEG_OUTPUT_XY_BASE_IDX 1 +#define regUVD_JPEG_GPCOM_CMD 0x060d +#define regUVD_JPEG_GPCOM_CMD_BASE_IDX 1 +#define regUVD_JPEG_GPCOM_DATA0 0x060e +#define regUVD_JPEG_GPCOM_DATA0_BASE_IDX 1 +#define regUVD_JPEG_GPCOM_DATA1 0x060f +#define regUVD_JPEG_GPCOM_DATA1_BASE_IDX 1 +#define regUVD_JPEG_SCRATCH1 0x0610 +#define regUVD_JPEG_SCRATCH1_BASE_IDX 1 +#define regUVD_JPEG_DEC_SOFT_RST 0x0611 +#define regUVD_JPEG_DEC_SOFT_RST_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jrbc0_uvd_jrbc_dec +// base address: 0x21100 +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640 +#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_CNTL 0x0641 +#define regUVD_JRBC0_UVD_JRBC_RB_CNTL_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_IB_SIZE 0x0642 +#define regUVD_JRBC0_UVD_JRBC_IB_SIZE_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_URGENT_CNTL 0x0643 +#define regUVD_JRBC0_UVD_JRBC_URGENT_CNTL_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_REF_DATA 0x0644 +#define regUVD_JRBC0_UVD_JRBC_RB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER 0x0645 +#define regUVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_SOFT_RESET 0x0648 +#define regUVD_JRBC0_UVD_JRBC_SOFT_RESET_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649 +#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a +#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_BUF_STATUS 0x064b +#define regUVD_JRBC0_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_IB_BUF_STATUS 0x064c +#define regUVD_JRBC0_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE 0x064d +#define regUVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER 0x064e +#define regUVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_IB_REF_DATA 0x064f +#define regUVD_JRBC0_UVD_JRBC_IB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JPEG_PREEMPT_CMD 0x0650 +#define regUVD_JRBC0_UVD_JPEG_PREEMPT_CMD_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0651 +#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0652 +#define regUVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_RB_SIZE 0x0653 +#define regUVD_JRBC0_UVD_JRBC_RB_SIZE_BASE_IDX 1 +#define regUVD_JRBC0_UVD_JRBC_SCRATCH0 0x0654 +#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jmi0_uvd_jmi_dec +// base address: 0x21180 +#define regUVD_JPEG_DEC_PF_CTRL 0x0660 +#define regUVD_JPEG_DEC_PF_CTRL_BASE_IDX 1 +#define regUVD_LMI_JRBC_CTRL 0x0661 +#define regUVD_LMI_JRBC_CTRL_BASE_IDX 1 +#define regUVD_LMI_JPEG_CTRL 0x0662 +#define regUVD_LMI_JPEG_CTRL_BASE_IDX 1 +#define regJPEG_LMI_DROP 0x0663 +#define regJPEG_LMI_DROP_BASE_IDX 1 +#define regUVD_LMI_JRBC_IB_VMID 0x0664 +#define regUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 +#define regUVD_LMI_JRBC_RB_VMID 0x0665 +#define regUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 +#define regUVD_LMI_JPEG_VMID 0x0666 +#define regUVD_LMI_JPEG_VMID_BASE_IDX 1 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 0x0667 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 0x0668 +#define regUVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW 0x0669 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH 0x066a +#define regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x066b +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x066c +#define regUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JPEG_PREEMPT_VMID 0x066d +#define regUVD_LMI_JPEG_PREEMPT_VMID_BASE_IDX 1 +#define regUVD_JMI_DEC_SWAP_CNTL 0x066e +#define regUVD_JMI_DEC_SWAP_CNTL_BASE_IDX 1 +#define regUVD_JMI_ATOMIC_CNTL 0x066f +#define regUVD_JMI_ATOMIC_CNTL_BASE_IDX 1 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW 0x0670 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH 0x0671 +#define regUVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x0672 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x0673 +#define regUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0674 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0675 +#define regUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW 0x0676 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH 0x0677 +#define regUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 0x0678 +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 0x0679 +#define regUVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_JMI_ATOMIC_CNTL2 0x067d +#define regUVD_JMI_ATOMIC_CNTL2_BASE_IDX 1 + + +// addressBlock: uvd_uvd_dct_decoder_rbc_2_uvd_jrbc_dec +// base address: 0x21200 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0680 +#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_RB_CNTL 0x0681 +#define regUVD_JRBC3_UVD_JRBC_RB_CNTL_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_IB_SIZE 0x0682 +#define regUVD_JRBC3_UVD_JRBC_IB_SIZE_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_URGENT_CNTL 0x0683 +#define regUVD_JRBC3_UVD_JRBC_URGENT_CNTL_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_RB_REF_DATA 0x0684 +#define regUVD_JRBC3_UVD_JRBC_RB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER 0x0685 +#define regUVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_SOFT_RESET 0x0688 +#define regUVD_JRBC3_UVD_JRBC_SOFT_RESET_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0689 +#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x068a +#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_RB_BUF_STATUS 0x068b +#define regUVD_JRBC3_UVD_JRBC_RB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_IB_BUF_STATUS 0x068c +#define regUVD_JRBC3_UVD_JRBC_IB_BUF_STATUS_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE 0x068d +#define regUVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER 0x068e +#define regUVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_IB_REF_DATA 0x068f +#define regUVD_JRBC3_UVD_JRBC_IB_REF_DATA_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JPEG_PREEMPT_CMD 0x0690 +#define regUVD_JRBC3_UVD_JPEG_PREEMPT_CMD_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0 0x0691 +#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1 0x0692 +#define regUVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_RB_SIZE 0x0693 +#define regUVD_JRBC3_UVD_JRBC_RB_SIZE_BASE_IDX 1 +#define regUVD_JRBC3_UVD_JRBC_SCRATCH0 0x0694 +#define regUVD_JRBC3_UVD_JRBC_SCRATCH0_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jmi_common_dec +// base address: 0x21300 +#define regUVD_JADP_MCIF_URGENT_CTRL 0x06c1 +#define regUVD_JADP_MCIF_URGENT_CTRL_BASE_IDX 1 +#define regUVD_JMI_URGENT_CTRL 0x06c2 +#define regUVD_JMI_URGENT_CTRL_BASE_IDX 1 +#define regUVD_JMI_CTRL 0x06c3 +#define regUVD_JMI_CTRL_BASE_IDX 1 +#define regJPEG_MEMCHECK_CLAMPING_CNTL 0x06c4 +#define regJPEG_MEMCHECK_CLAMPING_CNTL_BASE_IDX 1 +#define regJPEG_MEMCHECK_SAFE_ADDR 0x06c5 +#define regJPEG_MEMCHECK_SAFE_ADDR_BASE_IDX 1 +#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT 0x06c6 +#define regJPEG_MEMCHECK_SAFE_ADDR_64BIT_BASE_IDX 1 +#define regUVD_JMI_LAT_CTRL 0x06c7 +#define regUVD_JMI_LAT_CTRL_BASE_IDX 1 +#define regUVD_JMI_LAT_CNTR 0x06c8 +#define regUVD_JMI_LAT_CNTR_BASE_IDX 1 +#define regUVD_JMI_AVG_LAT_CNTR 0x06c9 +#define regUVD_JMI_AVG_LAT_CNTR_BASE_IDX 1 +#define regUVD_JMI_PERFMON_CTRL 0x06ca +#define regUVD_JMI_PERFMON_CTRL_BASE_IDX 1 +#define regUVD_JMI_PERFMON_COUNT_LO 0x06cb +#define regUVD_JMI_PERFMON_COUNT_LO_BASE_IDX 1 +#define regUVD_JMI_PERFMON_COUNT_HI 0x06cc +#define regUVD_JMI_PERFMON_COUNT_HI_BASE_IDX 1 +#define regUVD_JMI_CLEAN_STATUS 0x06cd +#define regUVD_JMI_CLEAN_STATUS_BASE_IDX 1 +#define regUVD_JMI_CNTL 0x06ce +#define regUVD_JMI_CNTL_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jpeg_common_dec +// base address: 0x21400 +#define regJPEG_SOFT_RESET_STATUS 0x0700 +#define regJPEG_SOFT_RESET_STATUS_BASE_IDX 1 +#define regJPEG_SYS_INT_EN 0x0701 +#define regJPEG_SYS_INT_EN_BASE_IDX 1 +#define regJPEG_SYS_INT_EN1 0x0702 +#define regJPEG_SYS_INT_EN1_BASE_IDX 1 +#define regJPEG_SYS_INT_STATUS 0x0703 +#define regJPEG_SYS_INT_STATUS_BASE_IDX 1 +#define regJPEG_SYS_INT_STATUS1 0x0704 +#define regJPEG_SYS_INT_STATUS1_BASE_IDX 1 +#define regJPEG_SYS_INT_ACK 0x0705 +#define regJPEG_SYS_INT_ACK_BASE_IDX 1 +#define regJPEG_SYS_INT_ACK1 0x0706 +#define regJPEG_SYS_INT_ACK1_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_EN 0x0707 +#define regJPEG_MEMCHECK_SYS_INT_EN_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_EN1 0x0708 +#define regJPEG_MEMCHECK_SYS_INT_EN1_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_STAT 0x0709 +#define regJPEG_MEMCHECK_SYS_INT_STAT_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_STAT1 0x070a +#define regJPEG_MEMCHECK_SYS_INT_STAT1_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_STAT2 0x070b +#define regJPEG_MEMCHECK_SYS_INT_STAT2_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_ACK 0x070c +#define regJPEG_MEMCHECK_SYS_INT_ACK_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_ACK1 0x070d +#define regJPEG_MEMCHECK_SYS_INT_ACK1_BASE_IDX 1 +#define regJPEG_MEMCHECK_SYS_INT_ACK2 0x070e +#define regJPEG_MEMCHECK_SYS_INT_ACK2_BASE_IDX 1 +#define regJPEG_MASTINT_EN 0x070f +#define regJPEG_MASTINT_EN_BASE_IDX 1 +#define regJPEG_IH_CTRL 0x0710 +#define regJPEG_IH_CTRL_BASE_IDX 1 +#define regJRBBM_ARB_CTRL 0x0712 +#define regJRBBM_ARB_CTRL_BASE_IDX 1 + + +// addressBlock: uvd_uvd_jpeg_common_sclk_dec +// base address: 0x21480 +#define regJPEG_CGC_GATE 0x0720 +#define regJPEG_CGC_GATE_BASE_IDX 1 +#define regJPEG_CGC_CTRL 0x0721 +#define regJPEG_CGC_CTRL_BASE_IDX 1 +#define regJPEG_CGC_STATUS 0x0722 +#define regJPEG_CGC_STATUS_BASE_IDX 1 +#define regJPEG_COMN_CGC_MEM_CTRL 0x0723 +#define regJPEG_COMN_CGC_MEM_CTRL_BASE_IDX 1 +#define regJPEG_DEC_CGC_MEM_CTRL 0x0724 +#define regJPEG_DEC_CGC_MEM_CTRL_BASE_IDX 1 +#define regJPEG_ENC_CGC_MEM_CTRL 0x0726 +#define regJPEG_ENC_CGC_MEM_CTRL_BASE_IDX 1 +#define regJPEG_PERF_BANK_CONF 0x0727 +#define regJPEG_PERF_BANK_CONF_BASE_IDX 1 +#define regJPEG_PERF_BANK_EVENT_SEL 0x0728 +#define regJPEG_PERF_BANK_EVENT_SEL_BASE_IDX 1 +#define regJPEG_PERF_BANK_COUNT0 0x0729 +#define regJPEG_PERF_BANK_COUNT0_BASE_IDX 1 +#define regJPEG_PERF_BANK_COUNT1 0x072a +#define regJPEG_PERF_BANK_COUNT1_BASE_IDX 1 +#define regJPEG_PERF_BANK_COUNT2 0x072b +#define regJPEG_PERF_BANK_COUNT2_BASE_IDX 1 +#define regJPEG_PERF_BANK_COUNT3 0x072c +#define regJPEG_PERF_BANK_COUNT3_BASE_IDX 1 + + +// addressBlock: uvd_vcn_umsch_dec +// base address: 0x21500 +#define regVCN_UMSCH_MES_CNTL 0x0740 +#define regVCN_UMSCH_MES_CNTL_BASE_IDX 1 +#define regUMSCH_CTL 0x0741 +#define regUMSCH_CTL_BASE_IDX 1 +#define regUMSCH_CTL2 0x0742 +#define regUMSCH_CTL2_BASE_IDX 1 +#define regVCN_UMSCH_AGDB_WPTR0 0x0743 +#define regVCN_UMSCH_AGDB_WPTR0_BASE_IDX 1 +#define regVCN_UMSCH_AGDB_WPTR1 0x0744 +#define regVCN_UMSCH_AGDB_WPTR1_BASE_IDX 1 +#define regVCN_UMSCH_AGDB_WPTR2 0x0745 +#define regVCN_UMSCH_AGDB_WPTR2_BASE_IDX 1 +#define regVCN_UMSCH_AGDB_WPTR3 0x0746 +#define regVCN_UMSCH_AGDB_WPTR3_BASE_IDX 1 +#define regVCN_UMSCH_AGDB_WPTR4 0x0747 +#define regVCN_UMSCH_AGDB_WPTR4_BASE_IDX 1 +#define regVCN_UMSCH_AGDB_WPTR5 0x0748 +#define regVCN_UMSCH_AGDB_WPTR5_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX0 0x0749 +#define regVCN_UMSCH_MAILBOX0_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX_RESP0 0x074a +#define regVCN_UMSCH_MAILBOX_RESP0_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX1 0x074b +#define regVCN_UMSCH_MAILBOX1_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX_RESP1 0x074c +#define regVCN_UMSCH_MAILBOX_RESP1_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX2 0x074d +#define regVCN_UMSCH_MAILBOX2_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX_RESP2 0x074e +#define regVCN_UMSCH_MAILBOX_RESP2_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX3 0x074f +#define regVCN_UMSCH_MAILBOX3_BASE_IDX 1 +#define regVCN_UMSCH_MAILBOX_RESP3 0x0750 +#define regVCN_UMSCH_MAILBOX_RESP3_BASE_IDX 1 +#define regVCN_UMSCH_MES_UTCL1_CNTL 0x0759 +#define regVCN_UMSCH_MES_UTCL1_CNTL_BASE_IDX 1 +#define regVCN_UMSCH_MES_BUSY 0x075a +#define regVCN_UMSCH_MES_BUSY_BASE_IDX 1 +#define regVCN_UMSCH_RB_BASE_LO 0x075b +#define regVCN_UMSCH_RB_BASE_LO_BASE_IDX 1 +#define regVCN_UMSCH_RB_BASE_HI 0x075c +#define regVCN_UMSCH_RB_BASE_HI_BASE_IDX 1 +#define regVCN_UMSCH_RB_SIZE 0x075d +#define regVCN_UMSCH_RB_SIZE_BASE_IDX 1 +#define regVCN_UMSCH_RB_RPTR 0x075e +#define regVCN_UMSCH_RB_RPTR_BASE_IDX 1 +#define regVCN_UMSCH_RB_WPTR 0x075f +#define regVCN_UMSCH_RB_WPTR_BASE_IDX 1 +#define regVCN_UMSCH_MASTINT_EN 0x0760 +#define regVCN_UMSCH_MASTINT_EN_BASE_IDX 1 +#define regVCN_UMSCH_IH_CTRL 0x0761 +#define regVCN_UMSCH_IH_CTRL_BASE_IDX 1 +#define regVCN_UMSCH_SYS_INT_EN 0x0762 +#define regVCN_UMSCH_SYS_INT_EN_BASE_IDX 1 +#define regVCN_UMSCH_SYS_INT_STATUS 0x0763 +#define regVCN_UMSCH_SYS_INT_STATUS_BASE_IDX 1 +#define regVCN_UMSCH_SYS_INT_ACK 0x0764 +#define regVCN_UMSCH_SYS_INT_ACK_BASE_IDX 1 +#define regVCN_UMSCH_SYS_INT_SRC 0x0765 +#define regVCN_UMSCH_SYS_INT_SRC_BASE_IDX 1 +#define regVCN_UMSCH_IH_CTX_CTRL 0x0766 +#define regVCN_UMSCH_IH_CTX_CTRL_BASE_IDX 1 +#define regUVD_UMSCH_FORCE 0x076b +#define regUVD_UMSCH_FORCE_BASE_IDX 1 +#define regUMSCH_MES_RESET_CTRL 0x0770 +#define regUMSCH_MES_RESET_CTRL_BASE_IDX 1 + + +// addressBlock: uvd_vcn_cprs64dec +// base address: 0x21640 +#define regVCN_MES_PRGRM_CNTR_START 0x0790 +#define regVCN_MES_PRGRM_CNTR_START_BASE_IDX 1 +#define regVCN_MES_INTR_ROUTINE_START 0x0791 +#define regVCN_MES_INTR_ROUTINE_START_BASE_IDX 1 +#define regVCN_MES_MTVEC_LO 0x0791 +#define regVCN_MES_MTVEC_LO_BASE_IDX 1 +#define regVCN_MES_INTR_ROUTINE_START_HI 0x0792 +#define regVCN_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 +#define regVCN_MES_MTVEC_HI 0x0792 +#define regVCN_MES_MTVEC_HI_BASE_IDX 1 +#define regVCN_MES_CNTL 0x0797 +#define regVCN_MES_CNTL_BASE_IDX 1 +#define regVCN_MES_PIPE_PRIORITY_CNTS 0x0798 +#define regVCN_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regVCN_MES_PIPE0_PRIORITY 0x0799 +#define regVCN_MES_PIPE0_PRIORITY_BASE_IDX 1 +#define regVCN_MES_PIPE1_PRIORITY 0x079a +#define regVCN_MES_PIPE1_PRIORITY_BASE_IDX 1 +#define regVCN_MES_PIPE2_PRIORITY 0x079b +#define regVCN_MES_PIPE2_PRIORITY_BASE_IDX 1 +#define regVCN_MES_PIPE3_PRIORITY 0x079c +#define regVCN_MES_PIPE3_PRIORITY_BASE_IDX 1 +#define regVCN_MES_HEADER_DUMP 0x079d +#define regVCN_MES_HEADER_DUMP_BASE_IDX 1 +#define regVCN_MES_MIE_LO 0x079e +#define regVCN_MES_MIE_LO_BASE_IDX 1 +#define regVCN_MES_MIE_HI 0x079f +#define regVCN_MES_MIE_HI_BASE_IDX 1 +#define regVCN_MES_INTERRUPT 0x07a0 +#define regVCN_MES_INTERRUPT_BASE_IDX 1 +#define regVCN_MES_SCRATCH_INDEX 0x07a1 +#define regVCN_MES_SCRATCH_INDEX_BASE_IDX 1 +#define regVCN_MES_SCRATCH_DATA 0x07a2 +#define regVCN_MES_SCRATCH_DATA_BASE_IDX 1 +#define regVCN_MES_INSTR_PNTR 0x07a3 +#define regVCN_MES_INSTR_PNTR_BASE_IDX 1 +#define regVCN_MES_MSCRATCH_HI 0x07a4 +#define regVCN_MES_MSCRATCH_HI_BASE_IDX 1 +#define regVCN_MES_MSCRATCH_LO 0x07a5 +#define regVCN_MES_MSCRATCH_LO_BASE_IDX 1 +#define regVCN_MES_MSTATUS_LO 0x07a6 +#define regVCN_MES_MSTATUS_LO_BASE_IDX 1 +#define regVCN_MES_MSTATUS_HI 0x07a7 +#define regVCN_MES_MSTATUS_HI_BASE_IDX 1 +#define regVCN_MES_MEPC_LO 0x07a8 +#define regVCN_MES_MEPC_LO_BASE_IDX 1 +#define regVCN_MES_MEPC_HI 0x07a9 +#define regVCN_MES_MEPC_HI_BASE_IDX 1 +#define regVCN_MES_MCAUSE_LO 0x07aa +#define regVCN_MES_MCAUSE_LO_BASE_IDX 1 +#define regVCN_MES_MCAUSE_HI 0x07ab +#define regVCN_MES_MCAUSE_HI_BASE_IDX 1 +#define regVCN_MES_MBADADDR_LO 0x07ac +#define regVCN_MES_MBADADDR_LO_BASE_IDX 1 +#define regVCN_MES_MBADADDR_HI 0x07ad +#define regVCN_MES_MBADADDR_HI_BASE_IDX 1 +#define regVCN_MES_MIP_LO 0x07ae +#define regVCN_MES_MIP_LO_BASE_IDX 1 +#define regVCN_MES_MIP_HI 0x07af +#define regVCN_MES_MIP_HI_BASE_IDX 1 +#define regVCN_MES_IC_OP_CNTL 0x07b0 +#define regVCN_MES_IC_OP_CNTL_BASE_IDX 1 +#define regVCN_MES_MCYCLE_LO 0x07b6 +#define regVCN_MES_MCYCLE_LO_BASE_IDX 1 +#define regVCN_MES_MCYCLE_HI 0x07b7 +#define regVCN_MES_MCYCLE_HI_BASE_IDX 1 +#define regVCN_MES_MTIME_LO 0x07b8 +#define regVCN_MES_MTIME_LO_BASE_IDX 1 +#define regVCN_MES_MTIME_HI 0x07b9 +#define regVCN_MES_MTIME_HI_BASE_IDX 1 +#define regVCN_MES_MINSTRET_LO 0x07ba +#define regVCN_MES_MINSTRET_LO_BASE_IDX 1 +#define regVCN_MES_MINSTRET_HI 0x07bb +#define regVCN_MES_MINSTRET_HI_BASE_IDX 1 +#define regVCN_MES_MISA_LO 0x07bc +#define regVCN_MES_MISA_LO_BASE_IDX 1 +#define regVCN_MES_MISA_HI 0x07bd +#define regVCN_MES_MISA_HI_BASE_IDX 1 +#define regVCN_MES_MVENDORID_LO 0x07be +#define regVCN_MES_MVENDORID_LO_BASE_IDX 1 +#define regVCN_MES_MVENDORID_HI 0x07bf +#define regVCN_MES_MVENDORID_HI_BASE_IDX 1 +#define regVCN_MES_MARCHID_LO 0x07c0 +#define regVCN_MES_MARCHID_LO_BASE_IDX 1 +#define regVCN_MES_MARCHID_HI 0x07c1 +#define regVCN_MES_MARCHID_HI_BASE_IDX 1 +#define regVCN_MES_MIMPID_LO 0x07c2 +#define regVCN_MES_MIMPID_LO_BASE_IDX 1 +#define regVCN_MES_MIMPID_HI 0x07c3 +#define regVCN_MES_MIMPID_HI_BASE_IDX 1 +#define regVCN_MES_MHARTID_LO 0x07c4 +#define regVCN_MES_MHARTID_LO_BASE_IDX 1 +#define regVCN_MES_MHARTID_HI 0x07c5 +#define regVCN_MES_MHARTID_HI_BASE_IDX 1 +#define regVCN_MES_DC_BASE_CNTL 0x07c6 +#define regVCN_MES_DC_BASE_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_OP_CNTL 0x07c7 +#define regVCN_MES_DC_OP_CNTL_BASE_IDX 1 +#define regVCN_MES_MTIMECMP_LO 0x07c8 +#define regVCN_MES_MTIMECMP_LO_BASE_IDX 1 +#define regVCN_MES_MTIMECMP_HI 0x07c9 +#define regVCN_MES_MTIMECMP_HI_BASE_IDX 1 +#define regVCN_MES_GP0_LO 0x07d3 +#define regVCN_MES_GP0_LO_BASE_IDX 1 +#define regVCN_MES_GP0_HI 0x07d4 +#define regVCN_MES_GP0_HI_BASE_IDX 1 +#define regVCN_MES_GP1_LO 0x07d5 +#define regVCN_MES_GP1_LO_BASE_IDX 1 +#define regVCN_MES_GP1_HI 0x07d6 +#define regVCN_MES_GP1_HI_BASE_IDX 1 +#define regVCN_MES_GP2_LO 0x07d7 +#define regVCN_MES_GP2_LO_BASE_IDX 1 +#define regVCN_MES_GP2_HI 0x07d8 +#define regVCN_MES_GP2_HI_BASE_IDX 1 +#define regVCN_MES_GP3_LO 0x07d9 +#define regVCN_MES_GP3_LO_BASE_IDX 1 +#define regVCN_MES_GP3_HI 0x07da +#define regVCN_MES_GP3_HI_BASE_IDX 1 +#define regVCN_MES_GP4_LO 0x07db +#define regVCN_MES_GP4_LO_BASE_IDX 1 +#define regVCN_MES_GP4_HI 0x07dc +#define regVCN_MES_GP4_HI_BASE_IDX 1 +#define regVCN_MES_GP5_LO 0x07dd +#define regVCN_MES_GP5_LO_BASE_IDX 1 +#define regVCN_MES_GP5_HI 0x07de +#define regVCN_MES_GP5_HI_BASE_IDX 1 +#define regVCN_MES_GP6_LO 0x07df +#define regVCN_MES_GP6_LO_BASE_IDX 1 +#define regVCN_MES_GP6_HI 0x07e0 +#define regVCN_MES_GP6_HI_BASE_IDX 1 +#define regVCN_MES_GP7_LO 0x07e1 +#define regVCN_MES_GP7_LO_BASE_IDX 1 +#define regVCN_MES_GP7_HI 0x07e2 +#define regVCN_MES_GP7_HI_BASE_IDX 1 +#define regVCN_MES_GP8_LO 0x07e3 +#define regVCN_MES_GP8_LO_BASE_IDX 1 +#define regVCN_MES_GP8_HI 0x07e4 +#define regVCN_MES_GP8_HI_BASE_IDX 1 +#define regVCN_MES_GP9_LO 0x07e5 +#define regVCN_MES_GP9_LO_BASE_IDX 1 +#define regVCN_MES_GP9_HI 0x07e6 +#define regVCN_MES_GP9_HI_BASE_IDX 1 +#define regVCN_MES_DM_INDEX_ADDR 0x0810 +#define regVCN_MES_DM_INDEX_ADDR_BASE_IDX 1 +#define regVCN_MES_DM_INDEX_DATA 0x0811 +#define regVCN_MES_DM_INDEX_DATA_BASE_IDX 1 +#define regVCN_MES_LOCAL_BASE0_LO 0x0813 +#define regVCN_MES_LOCAL_BASE0_LO_BASE_IDX 1 +#define regVCN_MES_LOCAL_BASE0_HI 0x0814 +#define regVCN_MES_LOCAL_BASE0_HI_BASE_IDX 1 +#define regVCN_MES_LOCAL_MASK0_LO 0x0815 +#define regVCN_MES_LOCAL_MASK0_LO_BASE_IDX 1 +#define regVCN_MES_LOCAL_MASK0_HI 0x0816 +#define regVCN_MES_LOCAL_MASK0_HI_BASE_IDX 1 +#define regVCN_MES_LOCAL_APERTURE 0x0817 +#define regVCN_MES_LOCAL_APERTURE_BASE_IDX 1 +#define regVCN_MES_LOCAL_INSTR_BASE_LO 0x0818 +#define regVCN_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regVCN_MES_LOCAL_INSTR_BASE_HI 0x0819 +#define regVCN_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regVCN_MES_LOCAL_INSTR_MASK_LO 0x081a +#define regVCN_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regVCN_MES_LOCAL_INSTR_MASK_HI 0x081b +#define regVCN_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regVCN_MES_LOCAL_INSTR_APERTURE 0x081c +#define regVCN_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regVCN_MES_LOCAL_SCRATCH_APERTURE 0x081d +#define regVCN_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regVCN_MES_LOCAL_SCRATCH_BASE_LO 0x081e +#define regVCN_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regVCN_MES_LOCAL_SCRATCH_BASE_HI 0x081f +#define regVCN_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regVCN_MES_PERFCOUNT_CNTL 0x0829 +#define regVCN_MES_PERFCOUNT_CNTL_BASE_IDX 1 +#define regVCN_MES_PENDING_INTERRUPT 0x082a +#define regVCN_MES_PENDING_INTERRUPT_BASE_IDX 1 +#define regVCN_MES_PRGRM_CNTR_START_HI 0x082d +#define regVCN_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_16 0x082f +#define regVCN_MES_INTERRUPT_DATA_16_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_17 0x0830 +#define regVCN_MES_INTERRUPT_DATA_17_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_18 0x0831 +#define regVCN_MES_INTERRUPT_DATA_18_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_19 0x0832 +#define regVCN_MES_INTERRUPT_DATA_19_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_20 0x0833 +#define regVCN_MES_INTERRUPT_DATA_20_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_21 0x0834 +#define regVCN_MES_INTERRUPT_DATA_21_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_22 0x0835 +#define regVCN_MES_INTERRUPT_DATA_22_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_23 0x0836 +#define regVCN_MES_INTERRUPT_DATA_23_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_24 0x0837 +#define regVCN_MES_INTERRUPT_DATA_24_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_25 0x0838 +#define regVCN_MES_INTERRUPT_DATA_25_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_26 0x0839 +#define regVCN_MES_INTERRUPT_DATA_26_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_27 0x083a +#define regVCN_MES_INTERRUPT_DATA_27_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_28 0x083b +#define regVCN_MES_INTERRUPT_DATA_28_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_29 0x083c +#define regVCN_MES_INTERRUPT_DATA_29_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_30 0x083d +#define regVCN_MES_INTERRUPT_DATA_30_BASE_IDX 1 +#define regVCN_MES_INTERRUPT_DATA_31 0x083e +#define regVCN_MES_INTERRUPT_DATA_31_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE0_BASE 0x083f +#define regVCN_MES_DC_APERTURE0_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE0_MASK 0x0840 +#define regVCN_MES_DC_APERTURE0_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE0_CNTL 0x0841 +#define regVCN_MES_DC_APERTURE0_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE1_BASE 0x0842 +#define regVCN_MES_DC_APERTURE1_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE1_MASK 0x0843 +#define regVCN_MES_DC_APERTURE1_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE1_CNTL 0x0844 +#define regVCN_MES_DC_APERTURE1_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE2_BASE 0x0845 +#define regVCN_MES_DC_APERTURE2_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE2_MASK 0x0846 +#define regVCN_MES_DC_APERTURE2_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE2_CNTL 0x0847 +#define regVCN_MES_DC_APERTURE2_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE3_BASE 0x0848 +#define regVCN_MES_DC_APERTURE3_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE3_MASK 0x0849 +#define regVCN_MES_DC_APERTURE3_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE3_CNTL 0x084a +#define regVCN_MES_DC_APERTURE3_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE4_BASE 0x084b +#define regVCN_MES_DC_APERTURE4_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE4_MASK 0x084c +#define regVCN_MES_DC_APERTURE4_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE4_CNTL 0x084d +#define regVCN_MES_DC_APERTURE4_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE5_BASE 0x084e +#define regVCN_MES_DC_APERTURE5_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE5_MASK 0x084f +#define regVCN_MES_DC_APERTURE5_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE5_CNTL 0x0850 +#define regVCN_MES_DC_APERTURE5_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE6_BASE 0x0851 +#define regVCN_MES_DC_APERTURE6_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE6_MASK 0x0852 +#define regVCN_MES_DC_APERTURE6_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE6_CNTL 0x0853 +#define regVCN_MES_DC_APERTURE6_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE7_BASE 0x0854 +#define regVCN_MES_DC_APERTURE7_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE7_MASK 0x0855 +#define regVCN_MES_DC_APERTURE7_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE7_CNTL 0x0856 +#define regVCN_MES_DC_APERTURE7_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE8_BASE 0x0857 +#define regVCN_MES_DC_APERTURE8_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE8_MASK 0x0858 +#define regVCN_MES_DC_APERTURE8_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE8_CNTL 0x0859 +#define regVCN_MES_DC_APERTURE8_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE9_BASE 0x085a +#define regVCN_MES_DC_APERTURE9_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE9_MASK 0x085b +#define regVCN_MES_DC_APERTURE9_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE9_CNTL 0x085c +#define regVCN_MES_DC_APERTURE9_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE10_BASE 0x085d +#define regVCN_MES_DC_APERTURE10_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE10_MASK 0x085e +#define regVCN_MES_DC_APERTURE10_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE10_CNTL 0x085f +#define regVCN_MES_DC_APERTURE10_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE11_BASE 0x0860 +#define regVCN_MES_DC_APERTURE11_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE11_MASK 0x0861 +#define regVCN_MES_DC_APERTURE11_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE11_CNTL 0x0862 +#define regVCN_MES_DC_APERTURE11_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE12_BASE 0x0863 +#define regVCN_MES_DC_APERTURE12_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE12_MASK 0x0864 +#define regVCN_MES_DC_APERTURE12_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE12_CNTL 0x0865 +#define regVCN_MES_DC_APERTURE12_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE13_BASE 0x0866 +#define regVCN_MES_DC_APERTURE13_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE13_MASK 0x0867 +#define regVCN_MES_DC_APERTURE13_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE13_CNTL 0x0868 +#define regVCN_MES_DC_APERTURE13_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE14_BASE 0x0869 +#define regVCN_MES_DC_APERTURE14_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE14_MASK 0x086a +#define regVCN_MES_DC_APERTURE14_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE14_CNTL 0x086b +#define regVCN_MES_DC_APERTURE14_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE15_BASE 0x086c +#define regVCN_MES_DC_APERTURE15_BASE_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE15_MASK 0x086d +#define regVCN_MES_DC_APERTURE15_MASK_BASE_IDX 1 +#define regVCN_MES_DC_APERTURE15_CNTL 0x086e +#define regVCN_MES_DC_APERTURE15_CNTL_BASE_IDX 1 + + +// addressBlock: uvd_vcn_hypdec +// base address: 0x21a00 +#define regVCN_MES_IC_BASE_LO 0x08d0 +#define regVCN_MES_IC_BASE_LO_BASE_IDX 1 +#define regVCN_MES_MIBASE_LO 0x08d0 +#define regVCN_MES_MIBASE_LO_BASE_IDX 1 +#define regVCN_MES_IC_BASE_HI 0x08d1 +#define regVCN_MES_IC_BASE_HI_BASE_IDX 1 +#define regVCN_MES_MIBASE_HI 0x08d1 +#define regVCN_MES_MIBASE_HI_BASE_IDX 1 +#define regVCN_MES_IC_BASE_CNTL 0x08d2 +#define regVCN_MES_IC_BASE_CNTL_BASE_IDX 1 +#define regVCN_MES_DC_BASE_LO 0x08d4 +#define regVCN_MES_DC_BASE_LO_BASE_IDX 1 +#define regVCN_MES_MDBASE_LO 0x08d4 +#define regVCN_MES_MDBASE_LO_BASE_IDX 1 +#define regVCN_MES_DC_BASE_HI 0x08d5 +#define regVCN_MES_DC_BASE_HI_BASE_IDX 1 +#define regVCN_MES_MDBASE_HI 0x08d5 +#define regVCN_MES_MDBASE_HI_BASE_IDX 1 +#define regVCN_MES_MIBOUND_LO 0x08db +#define regVCN_MES_MIBOUND_LO_BASE_IDX 1 +#define regVCN_MES_MIBOUND_HI 0x08dc +#define regVCN_MES_MIBOUND_HI_BASE_IDX 1 +#define regVCN_MES_MDBOUND_LO 0x08dd +#define regVCN_MES_MDBOUND_LO_BASE_IDX 1 +#define regVCN_MES_MDBOUND_HI 0x08de +#define regVCN_MES_MDBOUND_HI_BASE_IDX 1 + + +// addressBlock: uvd_slmi_adpdec +// base address: 0x21c00 +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 0x0900 +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 0x0901 +#define regUVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 0x0902 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 0x0903 +#define regUVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 0x0904 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 0x0905 +#define regUVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 0x0906 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 0x0907 +#define regUVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 0x0908 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 0x0909 +#define regUVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 0x090a +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 0x090b +#define regUVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 0x090c +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 0x090d +#define regUVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 0x090e +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_LOW_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 0x090f +#define regUVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH_BASE_IDX 1 +#define regUVD_LMI_MMSCH_NC_VMID 0x0910 +#define regUVD_LMI_MMSCH_NC_VMID_BASE_IDX 1 +#define regUVD_LMI_MMSCH_CTRL 0x0911 +#define regUVD_LMI_MMSCH_CTRL_BASE_IDX 1 +#define regUVD_MMSCH_LMI_STATUS 0x0912 +#define regUVD_MMSCH_LMI_STATUS_BASE_IDX 1 +#define regUMSCH_IOV_ACTIVE_FCN_ID 0x0920 +#define regUMSCH_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define regUVD_UMSCH_LMI_STATUS 0x0923 +#define regUVD_UMSCH_LMI_STATUS_BASE_IDX 1 + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h new file mode 100644 index 0000000000000..a2fabecd328e9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h @@ -0,0 +1,8262 @@ +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef _vcn_5_3_0_SH_MASK_HEADER +#define _vcn_5_3_0_SH_MASK_HEADER + + +// addressBlock: uvdctxind +//UVD_CGC_MEM_CTRL +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 +#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 +#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 +#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa +#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc +#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd +#define UVD_CGC_MEM_CTRL__MMSCH_LS_EN__SHIFT 0xe +#define UVD_CGC_MEM_CTRL__MPC1_LS_EN__SHIFT 0xf +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 +#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x00000001L +#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x00000002L +#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x00000004L +#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x00000008L +#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x00000010L +#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x00000020L +#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x00000040L +#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x00000080L +#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x00000100L +#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x00000200L +#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x00000400L +#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x00001000L +#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x00002000L +#define UVD_CGC_MEM_CTRL__MMSCH_LS_EN_MASK 0x00004000L +#define UVD_CGC_MEM_CTRL__MPC1_LS_EN_MASK 0x00008000L +#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L +#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L +//UVD_CGC_CTRL2 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 +#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 +#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L +#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L +#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001CL +//UVD_CGC_MEM_DS_CTRL +#define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN__SHIFT 0x0 +#define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN__SHIFT 0x1 +#define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN__SHIFT 0x2 +#define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN__SHIFT 0x3 +#define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN__SHIFT 0x4 +#define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN__SHIFT 0x5 +#define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN__SHIFT 0x6 +#define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN__SHIFT 0x7 +#define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN__SHIFT 0x8 +#define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN__SHIFT 0x9 +#define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN__SHIFT 0xa +#define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN__SHIFT 0xc +#define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN__SHIFT 0xd +#define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN__SHIFT 0xe +#define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN__SHIFT 0xf +#define UVD_CGC_MEM_DS_CTRL__LMI_MC_DS_EN_MASK 0x00000001L +#define UVD_CGC_MEM_DS_CTRL__MPC_DS_EN_MASK 0x00000002L +#define UVD_CGC_MEM_DS_CTRL__MPRD_DS_EN_MASK 0x00000004L +#define UVD_CGC_MEM_DS_CTRL__WCB_DS_EN_MASK 0x00000008L +#define UVD_CGC_MEM_DS_CTRL__UDEC_RE_DS_EN_MASK 0x00000010L +#define UVD_CGC_MEM_DS_CTRL__UDEC_CM_DS_EN_MASK 0x00000020L +#define UVD_CGC_MEM_DS_CTRL__UDEC_IT_DS_EN_MASK 0x00000040L +#define UVD_CGC_MEM_DS_CTRL__UDEC_DB_DS_EN_MASK 0x00000080L +#define UVD_CGC_MEM_DS_CTRL__UDEC_MP_DS_EN_MASK 0x00000100L +#define UVD_CGC_MEM_DS_CTRL__SYS_DS_EN_MASK 0x00000200L +#define UVD_CGC_MEM_DS_CTRL__VCPU_DS_EN_MASK 0x00000400L +#define UVD_CGC_MEM_DS_CTRL__MIF_DS_EN_MASK 0x00001000L +#define UVD_CGC_MEM_DS_CTRL__LCM_DS_EN_MASK 0x00002000L +#define UVD_CGC_MEM_DS_CTRL__MMSCH_DS_EN_MASK 0x00004000L +#define UVD_CGC_MEM_DS_CTRL__MPC1_DS_EN_MASK 0x00008000L +//UVD_CGC_MEM_SD_CTRL +#define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN__SHIFT 0x0 +#define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN__SHIFT 0x1 +#define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN__SHIFT 0x2 +#define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN__SHIFT 0x3 +#define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN__SHIFT 0x4 +#define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN__SHIFT 0x5 +#define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN__SHIFT 0x6 +#define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN__SHIFT 0x7 +#define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN__SHIFT 0x8 +#define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN__SHIFT 0x9 +#define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN__SHIFT 0xa +#define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN__SHIFT 0xc +#define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN__SHIFT 0xd +#define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN__SHIFT 0xe +#define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN__SHIFT 0xf +#define UVD_CGC_MEM_SD_CTRL__LMI_MC_SD_EN_MASK 0x00000001L +#define UVD_CGC_MEM_SD_CTRL__MPC_SD_EN_MASK 0x00000002L +#define UVD_CGC_MEM_SD_CTRL__MPRD_SD_EN_MASK 0x00000004L +#define UVD_CGC_MEM_SD_CTRL__WCB_SD_EN_MASK 0x00000008L +#define UVD_CGC_MEM_SD_CTRL__UDEC_RE_SD_EN_MASK 0x00000010L +#define UVD_CGC_MEM_SD_CTRL__UDEC_CM_SD_EN_MASK 0x00000020L +#define UVD_CGC_MEM_SD_CTRL__UDEC_IT_SD_EN_MASK 0x00000040L +#define UVD_CGC_MEM_SD_CTRL__UDEC_DB_SD_EN_MASK 0x00000080L +#define UVD_CGC_MEM_SD_CTRL__UDEC_MP_SD_EN_MASK 0x00000100L +#define UVD_CGC_MEM_SD_CTRL__SYS_SD_EN_MASK 0x00000200L +#define UVD_CGC_MEM_SD_CTRL__VCPU_SD_EN_MASK 0x00000400L +#define UVD_CGC_MEM_SD_CTRL__MIF_SD_EN_MASK 0x00001000L +#define UVD_CGC_MEM_SD_CTRL__LCM_SD_EN_MASK 0x00002000L +#define UVD_CGC_MEM_SD_CTRL__MMSCH_SD_EN_MASK 0x00004000L +#define UVD_CGC_MEM_SD_CTRL__MPC1_SD_EN_MASK 0x00008000L +//UVD_SW_SCRATCH_00 +#define UVD_SW_SCRATCH_00__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_00__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_01 +#define UVD_SW_SCRATCH_01__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_01__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_02 +#define UVD_SW_SCRATCH_02__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_02__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_03 +#define UVD_SW_SCRATCH_03__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_03__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_04 +#define UVD_SW_SCRATCH_04__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_04__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_05 +#define UVD_SW_SCRATCH_05__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_05__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_06 +#define UVD_SW_SCRATCH_06__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_06__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_07 +#define UVD_SW_SCRATCH_07__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_07__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_08 +#define UVD_SW_SCRATCH_08__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_08__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_09 +#define UVD_SW_SCRATCH_09__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_09__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_10 +#define UVD_SW_SCRATCH_10__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_10__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_11 +#define UVD_SW_SCRATCH_11__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_11__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_12 +#define UVD_SW_SCRATCH_12__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_12__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_13 +#define UVD_SW_SCRATCH_13__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_13__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_14 +#define UVD_SW_SCRATCH_14__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_14__DATA_MASK 0xFFFFFFFFL +//UVD_SW_SCRATCH_15 +#define UVD_SW_SCRATCH_15__DATA__SHIFT 0x0 +#define UVD_SW_SCRATCH_15__DATA_MASK 0xFFFFFFFFL +//UVD_IH_SEM_CTRL +#define UVD_IH_SEM_CTRL__IH_STALL_EN__SHIFT 0x0 +#define UVD_IH_SEM_CTRL__SEM_STALL_EN__SHIFT 0x1 +#define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 +#define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN__SHIFT 0x3 +#define UVD_IH_SEM_CTRL__IH_VMID__SHIFT 0x4 +#define UVD_IH_SEM_CTRL__IH_USER_DATA__SHIFT 0x8 +#define UVD_IH_SEM_CTRL__IH_RINGID__SHIFT 0x14 +#define UVD_IH_SEM_CTRL__IH_STALL_EN_MASK 0x00000001L +#define UVD_IH_SEM_CTRL__SEM_STALL_EN_MASK 0x00000002L +#define UVD_IH_SEM_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L +#define UVD_IH_SEM_CTRL__SEM_STATUS_CLEAN_MASK 0x00000008L +#define UVD_IH_SEM_CTRL__IH_VMID_MASK 0x000000F0L +#define UVD_IH_SEM_CTRL__IH_USER_DATA_MASK 0x000FFF00L +#define UVD_IH_SEM_CTRL__IH_RINGID_MASK 0x0FF00000L + + +// addressBlock: lmi_adp_indirect +//UVD_LMI_CRC0 +#define UVD_LMI_CRC0__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC1 +#define UVD_LMI_CRC1__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC2 +#define UVD_LMI_CRC2__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC3 +#define UVD_LMI_CRC3__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC10 +#define UVD_LMI_CRC10__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC10__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC11 +#define UVD_LMI_CRC11__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC11__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC12 +#define UVD_LMI_CRC12__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC12__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC13 +#define UVD_LMI_CRC13__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC13__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC14 +#define UVD_LMI_CRC14__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC14__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_CRC15 +#define UVD_LMI_CRC15__CRC32__SHIFT 0x0 +#define UVD_LMI_CRC15__CRC32_MASK 0xFFFFFFFFL +//UVD_LMI_SWAP_CNTL2 +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 +#define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x4 +#define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP__SHIFT 0xc +#define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP__SHIFT 0xe +#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x00000003L +#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0x0000000CL +#define UVD_LMI_SWAP_CNTL2__ATOMIC_MC_SWAP_MASK 0x00000FF0L +#define UVD_LMI_SWAP_CNTL2__CENC_MC_SWAP_MASK 0x00003000L +#define UVD_LMI_SWAP_CNTL2__FBC_KEY_MC_SWAP_MASK 0x0000C000L +//UVD_MEMCHECK_SYS_INT_EN +#define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN__SHIFT 0x0 +#define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN__SHIFT 0x1 +#define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN__SHIFT 0x2 +#define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN__SHIFT 0x3 +#define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN__SHIFT 0x4 +#define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN__SHIFT 0x5 +#define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 +#define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN__SHIFT 0x7 +#define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 +#define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb +#define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN__SHIFT 0xc +#define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN__SHIFT 0xf +#define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 +#define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 +#define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 +#define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 +#define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 +#define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 +#define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x1b +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1c +#define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1d +#define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1e +#define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN__SHIFT 0x1f +#define UVD_MEMCHECK_SYS_INT_EN__RE_ERR_EN_MASK 0x00000001L +#define UVD_MEMCHECK_SYS_INT_EN__IT_ERR_EN_MASK 0x00000002L +#define UVD_MEMCHECK_SYS_INT_EN__MP_ERR_EN_MASK 0x00000004L +#define UVD_MEMCHECK_SYS_INT_EN__DB_ERR_EN_MASK 0x00000008L +#define UVD_MEMCHECK_SYS_INT_EN__DBW_ERR_EN_MASK 0x00000010L +#define UVD_MEMCHECK_SYS_INT_EN__CM_ERR_EN_MASK 0x00000020L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L +#define UVD_MEMCHECK_SYS_INT_EN__VCPU_ERR_EN_MASK 0x00000080L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L +#define UVD_MEMCHECK_SYS_INT_EN__SRE_ERR_EN_MASK 0x00001000L +#define UVD_MEMCHECK_SYS_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L +#define UVD_MEMCHECK_SYS_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L +#define UVD_MEMCHECK_SYS_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L +#define UVD_MEMCHECK_SYS_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L +#define UVD_MEMCHECK_SYS_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L +#define UVD_MEMCHECK_SYS_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L +#define UVD_MEMCHECK_SYS_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP2_ERR_EN_MASK 0x08000000L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_BSP3_ERR_EN_MASK 0x10000000L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR_ERR_EN_MASK 0x20000000L +#define UVD_MEMCHECK_SYS_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x40000000L +#define UVD_MEMCHECK_SYS_INT_EN__PREF_ERR_EN_MASK 0x80000000L +//UVD_MEMCHECK_SYS_INT_STAT +#define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR__SHIFT 0x0 +#define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR__SHIFT 0x1 +#define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR__SHIFT 0x2 +#define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR__SHIFT 0x3 +#define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR__SHIFT 0x4 +#define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR__SHIFT 0x5 +#define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR__SHIFT 0x6 +#define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR__SHIFT 0x7 +#define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR__SHIFT 0x8 +#define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR__SHIFT 0x9 +#define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR__SHIFT 0xa +#define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR__SHIFT 0xb +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd +#define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR__SHIFT 0xe +#define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR__SHIFT 0xf +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 +#define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR__SHIFT 0x18 +#define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR__SHIFT 0x19 +#define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e +#define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f +#define UVD_MEMCHECK_SYS_INT_STAT__RE_LO_ERR_MASK 0x00000001L +#define UVD_MEMCHECK_SYS_INT_STAT__RE_HI_ERR_MASK 0x00000002L +#define UVD_MEMCHECK_SYS_INT_STAT__IT_LO_ERR_MASK 0x00000004L +#define UVD_MEMCHECK_SYS_INT_STAT__IT_HI_ERR_MASK 0x00000008L +#define UVD_MEMCHECK_SYS_INT_STAT__MP_LO_ERR_MASK 0x00000010L +#define UVD_MEMCHECK_SYS_INT_STAT__MP_HI_ERR_MASK 0x00000020L +#define UVD_MEMCHECK_SYS_INT_STAT__DB_LO_ERR_MASK 0x00000040L +#define UVD_MEMCHECK_SYS_INT_STAT__DB_HI_ERR_MASK 0x00000080L +#define UVD_MEMCHECK_SYS_INT_STAT__DBW_LO_ERR_MASK 0x00000100L +#define UVD_MEMCHECK_SYS_INT_STAT__DBW_HI_ERR_MASK 0x00000200L +#define UVD_MEMCHECK_SYS_INT_STAT__CM_LO_ERR_MASK 0x00000400L +#define UVD_MEMCHECK_SYS_INT_STAT__CM_HI_ERR_MASK 0x00000800L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L +#define UVD_MEMCHECK_SYS_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L +#define UVD_MEMCHECK_SYS_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L +#define UVD_MEMCHECK_SYS_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L +#define UVD_MEMCHECK_SYS_INT_STAT__SRE_LO_ERR_MASK 0x01000000L +#define UVD_MEMCHECK_SYS_INT_STAT__SRE_HI_ERR_MASK 0x02000000L +#define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L +#define UVD_MEMCHECK_SYS_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L +//UVD_MEMCHECK_SYS_INT_ACK +#define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK__SHIFT 0x0 +#define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK__SHIFT 0x1 +#define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK__SHIFT 0x2 +#define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK__SHIFT 0x3 +#define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK__SHIFT 0x4 +#define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK__SHIFT 0x5 +#define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK__SHIFT 0x6 +#define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK__SHIFT 0x7 +#define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK__SHIFT 0x8 +#define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK__SHIFT 0x9 +#define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK__SHIFT 0xa +#define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK__SHIFT 0xb +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd +#define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK__SHIFT 0xe +#define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK__SHIFT 0xf +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 +#define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK__SHIFT 0x18 +#define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK__SHIFT 0x19 +#define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e +#define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f +#define UVD_MEMCHECK_SYS_INT_ACK__RE_LO_ACK_MASK 0x00000001L +#define UVD_MEMCHECK_SYS_INT_ACK__RE_HI_ACK_MASK 0x00000002L +#define UVD_MEMCHECK_SYS_INT_ACK__IT_LO_ACK_MASK 0x00000004L +#define UVD_MEMCHECK_SYS_INT_ACK__IT_HI_ACK_MASK 0x00000008L +#define UVD_MEMCHECK_SYS_INT_ACK__MP_LO_ACK_MASK 0x00000010L +#define UVD_MEMCHECK_SYS_INT_ACK__MP_HI_ACK_MASK 0x00000020L +#define UVD_MEMCHECK_SYS_INT_ACK__DB_LO_ACK_MASK 0x00000040L +#define UVD_MEMCHECK_SYS_INT_ACK__DB_HI_ACK_MASK 0x00000080L +#define UVD_MEMCHECK_SYS_INT_ACK__DBW_LO_ACK_MASK 0x00000100L +#define UVD_MEMCHECK_SYS_INT_ACK__DBW_HI_ACK_MASK 0x00000200L +#define UVD_MEMCHECK_SYS_INT_ACK__CM_LO_ACK_MASK 0x00000400L +#define UVD_MEMCHECK_SYS_INT_ACK__CM_HI_ACK_MASK 0x00000800L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L +#define UVD_MEMCHECK_SYS_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L +#define UVD_MEMCHECK_SYS_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L +#define UVD_MEMCHECK_SYS_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L +#define UVD_MEMCHECK_SYS_INT_ACK__SRE_LO_ACK_MASK 0x01000000L +#define UVD_MEMCHECK_SYS_INT_ACK__SRE_HI_ACK_MASK 0x02000000L +#define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L +#define UVD_MEMCHECK_SYS_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L +//UVD_MEMCHECK_VCPU_INT_EN +#define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN__SHIFT 0x0 +#define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN__SHIFT 0x1 +#define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN__SHIFT 0x2 +#define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN__SHIFT 0x3 +#define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN__SHIFT 0x4 +#define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN__SHIFT 0x5 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN__SHIFT 0x6 +#define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN__SHIFT 0x7 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN__SHIFT 0x8 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN__SHIFT 0x9 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN__SHIFT 0xa +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN__SHIFT 0xb +#define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN__SHIFT 0xc +#define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN__SHIFT 0xf +#define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN__SHIFT 0x10 +#define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN__SHIFT 0x11 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN__SHIFT 0x12 +#define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN__SHIFT 0x13 +#define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN__SHIFT 0x14 +#define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN__SHIFT 0x15 +#define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN__SHIFT 0x18 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN__SHIFT 0x19 +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN__SHIFT 0x1a +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN__SHIFT 0x1b +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN__SHIFT 0x1c +#define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN__SHIFT 0x1d +#define UVD_MEMCHECK_VCPU_INT_EN__RE_ERR_EN_MASK 0x00000001L +#define UVD_MEMCHECK_VCPU_INT_EN__IT_ERR_EN_MASK 0x00000002L +#define UVD_MEMCHECK_VCPU_INT_EN__MP_ERR_EN_MASK 0x00000004L +#define UVD_MEMCHECK_VCPU_INT_EN__DB_ERR_EN_MASK 0x00000008L +#define UVD_MEMCHECK_VCPU_INT_EN__DBW_ERR_EN_MASK 0x00000010L +#define UVD_MEMCHECK_VCPU_INT_EN__CM_ERR_EN_MASK 0x00000020L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_REF_ERR_EN_MASK 0x00000040L +#define UVD_MEMCHECK_VCPU_INT_EN__VCPU_ERR_EN_MASK 0x00000080L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_DBW_ERR_EN_MASK 0x00000100L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_CM_COLOC_ERR_EN_MASK 0x00000200L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP0_ERR_EN_MASK 0x00000400L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP1_ERR_EN_MASK 0x00000800L +#define UVD_MEMCHECK_VCPU_INT_EN__SRE_ERR_EN_MASK 0x00001000L +#define UVD_MEMCHECK_VCPU_INT_EN__IT_RD_ERR_EN_MASK 0x00008000L +#define UVD_MEMCHECK_VCPU_INT_EN__CM_RD_ERR_EN_MASK 0x00010000L +#define UVD_MEMCHECK_VCPU_INT_EN__DB_RD_ERR_EN_MASK 0x00020000L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_RD_ERR_EN_MASK 0x00040000L +#define UVD_MEMCHECK_VCPU_INT_EN__IDCT_RD_ERR_EN_MASK 0x00080000L +#define UVD_MEMCHECK_VCPU_INT_EN__MPC_RD_ERR_EN_MASK 0x00100000L +#define UVD_MEMCHECK_VCPU_INT_EN__LBSI_RD_ERR_EN_MASK 0x00200000L +#define UVD_MEMCHECK_VCPU_INT_EN__RBC_RD_ERR_EN_MASK 0x01000000L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP2_ERR_EN_MASK 0x02000000L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_BSP3_ERR_EN_MASK 0x04000000L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR_ERR_EN_MASK 0x08000000L +#define UVD_MEMCHECK_VCPU_INT_EN__MIF_SCLR2_ERR_EN_MASK 0x10000000L +#define UVD_MEMCHECK_VCPU_INT_EN__PREF_ERR_EN_MASK 0x20000000L +//UVD_MEMCHECK_VCPU_INT_STAT +#define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR__SHIFT 0x0 +#define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR__SHIFT 0x1 +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR__SHIFT 0x2 +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR__SHIFT 0x3 +#define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR__SHIFT 0x4 +#define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR__SHIFT 0x5 +#define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR__SHIFT 0x6 +#define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR__SHIFT 0x7 +#define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR__SHIFT 0x8 +#define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR__SHIFT 0x9 +#define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR__SHIFT 0xa +#define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR__SHIFT 0xb +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR__SHIFT 0xc +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR__SHIFT 0xd +#define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR__SHIFT 0xe +#define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR__SHIFT 0xf +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR__SHIFT 0x10 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR__SHIFT 0x11 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR__SHIFT 0x12 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR__SHIFT 0x13 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR__SHIFT 0x14 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR__SHIFT 0x15 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR__SHIFT 0x16 +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR__SHIFT 0x17 +#define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR__SHIFT 0x18 +#define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR__SHIFT 0x19 +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR__SHIFT 0x1e +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR__SHIFT 0x1f +#define UVD_MEMCHECK_VCPU_INT_STAT__RE_LO_ERR_MASK 0x00000001L +#define UVD_MEMCHECK_VCPU_INT_STAT__RE_HI_ERR_MASK 0x00000002L +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_LO_ERR_MASK 0x00000004L +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_HI_ERR_MASK 0x00000008L +#define UVD_MEMCHECK_VCPU_INT_STAT__MP_LO_ERR_MASK 0x00000010L +#define UVD_MEMCHECK_VCPU_INT_STAT__MP_HI_ERR_MASK 0x00000020L +#define UVD_MEMCHECK_VCPU_INT_STAT__DB_LO_ERR_MASK 0x00000040L +#define UVD_MEMCHECK_VCPU_INT_STAT__DB_HI_ERR_MASK 0x00000080L +#define UVD_MEMCHECK_VCPU_INT_STAT__DBW_LO_ERR_MASK 0x00000100L +#define UVD_MEMCHECK_VCPU_INT_STAT__DBW_HI_ERR_MASK 0x00000200L +#define UVD_MEMCHECK_VCPU_INT_STAT__CM_LO_ERR_MASK 0x00000400L +#define UVD_MEMCHECK_VCPU_INT_STAT__CM_HI_ERR_MASK 0x00000800L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_LO_ERR_MASK 0x00001000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_REF_HI_ERR_MASK 0x00002000L +#define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_LO_ERR_MASK 0x00004000L +#define UVD_MEMCHECK_VCPU_INT_STAT__VCPU_HI_ERR_MASK 0x00008000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_LO_ERR_MASK 0x00010000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_DBW_HI_ERR_MASK 0x00020000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_LO_ERR_MASK 0x00040000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_CM_COLOC_HI_ERR_MASK 0x00080000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_LO_ERR_MASK 0x00100000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP0_HI_ERR_MASK 0x00200000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_LO_ERR_MASK 0x00400000L +#define UVD_MEMCHECK_VCPU_INT_STAT__MIF_BSP1_HI_ERR_MASK 0x00800000L +#define UVD_MEMCHECK_VCPU_INT_STAT__SRE_LO_ERR_MASK 0x01000000L +#define UVD_MEMCHECK_VCPU_INT_STAT__SRE_HI_ERR_MASK 0x02000000L +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_LO_ERR_MASK 0x40000000L +#define UVD_MEMCHECK_VCPU_INT_STAT__IT_RD_HI_ERR_MASK 0x80000000L +//UVD_MEMCHECK_VCPU_INT_ACK +#define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK__SHIFT 0x0 +#define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK__SHIFT 0x1 +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK__SHIFT 0x2 +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK__SHIFT 0x3 +#define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK__SHIFT 0x4 +#define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK__SHIFT 0x5 +#define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK__SHIFT 0x6 +#define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK__SHIFT 0x7 +#define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK__SHIFT 0x8 +#define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK__SHIFT 0x9 +#define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK__SHIFT 0xa +#define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK__SHIFT 0xb +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK__SHIFT 0xc +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK__SHIFT 0xd +#define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK__SHIFT 0xe +#define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK__SHIFT 0xf +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK__SHIFT 0x10 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK__SHIFT 0x11 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK__SHIFT 0x12 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK__SHIFT 0x13 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK__SHIFT 0x14 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK__SHIFT 0x15 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK__SHIFT 0x16 +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK__SHIFT 0x17 +#define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK__SHIFT 0x18 +#define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK__SHIFT 0x19 +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK__SHIFT 0x1e +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK__SHIFT 0x1f +#define UVD_MEMCHECK_VCPU_INT_ACK__RE_LO_ACK_MASK 0x00000001L +#define UVD_MEMCHECK_VCPU_INT_ACK__RE_HI_ACK_MASK 0x00000002L +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_LO_ACK_MASK 0x00000004L +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_HI_ACK_MASK 0x00000008L +#define UVD_MEMCHECK_VCPU_INT_ACK__MP_LO_ACK_MASK 0x00000010L +#define UVD_MEMCHECK_VCPU_INT_ACK__MP_HI_ACK_MASK 0x00000020L +#define UVD_MEMCHECK_VCPU_INT_ACK__DB_LO_ACK_MASK 0x00000040L +#define UVD_MEMCHECK_VCPU_INT_ACK__DB_HI_ACK_MASK 0x00000080L +#define UVD_MEMCHECK_VCPU_INT_ACK__DBW_LO_ACK_MASK 0x00000100L +#define UVD_MEMCHECK_VCPU_INT_ACK__DBW_HI_ACK_MASK 0x00000200L +#define UVD_MEMCHECK_VCPU_INT_ACK__CM_LO_ACK_MASK 0x00000400L +#define UVD_MEMCHECK_VCPU_INT_ACK__CM_HI_ACK_MASK 0x00000800L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_LO_ACK_MASK 0x00001000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_REF_HI_ACK_MASK 0x00002000L +#define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_LO_ACK_MASK 0x00004000L +#define UVD_MEMCHECK_VCPU_INT_ACK__VCPU_HI_ACK_MASK 0x00008000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_LO_ACK_MASK 0x00010000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_DBW_HI_ACK_MASK 0x00020000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_LO_ACK_MASK 0x00040000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_CM_COLOC_HI_ACK_MASK 0x00080000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_LO_ACK_MASK 0x00100000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP0_HI_ACK_MASK 0x00200000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_LO_ACK_MASK 0x00400000L +#define UVD_MEMCHECK_VCPU_INT_ACK__MIF_BSP1_HI_ACK_MASK 0x00800000L +#define UVD_MEMCHECK_VCPU_INT_ACK__SRE_LO_ACK_MASK 0x01000000L +#define UVD_MEMCHECK_VCPU_INT_ACK__SRE_HI_ACK_MASK 0x02000000L +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_LO_ACK_MASK 0x40000000L +#define UVD_MEMCHECK_VCPU_INT_ACK__IT_RD_HI_ACK_MASK 0x80000000L +//UVD_MEMCHECK2_SYS_INT_STAT +#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 +#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 +#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 +#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 +#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 +#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 +#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 +#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 +#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa +#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb +#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 +#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x16 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x17 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x18 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x19 +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x1a +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x1b +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x1c +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x1d +#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR__SHIFT 0x1e +#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR__SHIFT 0x1f +#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L +#define UVD_MEMCHECK2_SYS_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L +#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L +#define UVD_MEMCHECK2_SYS_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L +#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L +#define UVD_MEMCHECK2_SYS_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L +#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L +#define UVD_MEMCHECK2_SYS_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L +#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L +#define UVD_MEMCHECK2_SYS_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L +#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L +#define UVD_MEMCHECK2_SYS_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00400000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00800000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x01000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x02000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x04000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x08000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x10000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x20000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_LO_ERR_MASK 0x40000000L +#define UVD_MEMCHECK2_SYS_INT_STAT__PREF_HI_ERR_MASK 0x80000000L +//UVD_MEMCHECK2_SYS_INT_ACK +#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 +#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 +#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 +#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 +#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 +#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 +#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 +#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 +#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa +#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb +#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 +#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x16 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x17 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x18 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x19 +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x1a +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x1b +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x1c +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x1d +#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK__SHIFT 0x1e +#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK__SHIFT 0x1f +#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L +#define UVD_MEMCHECK2_SYS_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L +#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L +#define UVD_MEMCHECK2_SYS_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L +#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L +#define UVD_MEMCHECK2_SYS_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L +#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L +#define UVD_MEMCHECK2_SYS_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L +#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L +#define UVD_MEMCHECK2_SYS_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L +#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L +#define UVD_MEMCHECK2_SYS_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00400000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00800000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x01000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x02000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x04000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x08000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x10000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x20000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_LO_ACK_MASK 0x40000000L +#define UVD_MEMCHECK2_SYS_INT_ACK__PREF_HI_ACK_MASK 0x80000000L +//UVD_MEMCHECK2_VCPU_INT_STAT +#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR__SHIFT 0x0 +#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR__SHIFT 0x1 +#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR__SHIFT 0x2 +#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR__SHIFT 0x3 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR__SHIFT 0x4 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR__SHIFT 0x5 +#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR__SHIFT 0x6 +#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR__SHIFT 0x7 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR__SHIFT 0x8 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR__SHIFT 0x9 +#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR__SHIFT 0xa +#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR__SHIFT 0xb +#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR__SHIFT 0x10 +#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR__SHIFT 0x11 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR__SHIFT 0x12 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR__SHIFT 0x13 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR__SHIFT 0x14 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR__SHIFT 0x15 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR__SHIFT 0x16 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR__SHIFT 0x17 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR__SHIFT 0x18 +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR__SHIFT 0x19 +#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR__SHIFT 0x1a +#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR__SHIFT 0x1b +#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_LO_ERR_MASK 0x00000001L +#define UVD_MEMCHECK2_VCPU_INT_STAT__CM_RD_HI_ERR_MASK 0x00000002L +#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_LO_ERR_MASK 0x00000004L +#define UVD_MEMCHECK2_VCPU_INT_STAT__DB_RD_HI_ERR_MASK 0x00000008L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_LO_ERR_MASK 0x00000010L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_RD_HI_ERR_MASK 0x00000020L +#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_LO_ERR_MASK 0x00000040L +#define UVD_MEMCHECK2_VCPU_INT_STAT__IDCT_RD_HI_ERR_MASK 0x00000080L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_LO_ERR_MASK 0x00000100L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MPC_RD_HI_ERR_MASK 0x00000200L +#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_LO_ERR_MASK 0x00000400L +#define UVD_MEMCHECK2_VCPU_INT_STAT__LBSI_RD_HI_ERR_MASK 0x00000800L +#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_LO_ERR_MASK 0x00010000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__RBC_RD_HI_ERR_MASK 0x00020000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_LO_ERR_MASK 0x00040000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP2_HI_ERR_MASK 0x00080000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_LO_ERR_MASK 0x00100000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_BSP3_HI_ERR_MASK 0x00200000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_LO_ERR_MASK 0x00400000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR_HI_ERR_MASK 0x00800000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_LO_ERR_MASK 0x01000000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__MIF_SCLR2_HI_ERR_MASK 0x02000000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_LO_ERR_MASK 0x04000000L +#define UVD_MEMCHECK2_VCPU_INT_STAT__PREF_HI_ERR_MASK 0x08000000L +//UVD_MEMCHECK2_VCPU_INT_ACK +#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK__SHIFT 0x0 +#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK__SHIFT 0x1 +#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK__SHIFT 0x2 +#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK__SHIFT 0x3 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK__SHIFT 0x4 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK__SHIFT 0x5 +#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK__SHIFT 0x6 +#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK__SHIFT 0x7 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK__SHIFT 0x8 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK__SHIFT 0x9 +#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK__SHIFT 0xa +#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK__SHIFT 0xb +#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK__SHIFT 0x10 +#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK__SHIFT 0x11 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK__SHIFT 0x12 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK__SHIFT 0x13 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK__SHIFT 0x14 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK__SHIFT 0x15 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK__SHIFT 0x16 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK__SHIFT 0x17 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK__SHIFT 0x18 +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK__SHIFT 0x19 +#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK__SHIFT 0x1a +#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK__SHIFT 0x1b +#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_LO_ACK_MASK 0x00000001L +#define UVD_MEMCHECK2_VCPU_INT_ACK__CM_RD_HI_ACK_MASK 0x00000002L +#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_LO_ACK_MASK 0x00000004L +#define UVD_MEMCHECK2_VCPU_INT_ACK__DB_RD_HI_ACK_MASK 0x00000008L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_LO_ACK_MASK 0x00000010L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_RD_HI_ACK_MASK 0x00000020L +#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_LO_ACK_MASK 0x00000040L +#define UVD_MEMCHECK2_VCPU_INT_ACK__IDCT_RD_HI_ACK_MASK 0x00000080L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_LO_ACK_MASK 0x00000100L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MPC_RD_HI_ACK_MASK 0x00000200L +#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_LO_ACK_MASK 0x00000400L +#define UVD_MEMCHECK2_VCPU_INT_ACK__LBSI_RD_HI_ACK_MASK 0x00000800L +#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_LO_ACK_MASK 0x00010000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__RBC_RD_HI_ACK_MASK 0x00020000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_LO_ACK_MASK 0x00040000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP2_HI_ACK_MASK 0x00080000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_LO_ACK_MASK 0x00100000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_BSP3_HI_ACK_MASK 0x00200000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_LO_ACK_MASK 0x00400000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR_HI_ACK_MASK 0x00800000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_LO_ACK_MASK 0x01000000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__MIF_SCLR2_HI_ACK_MASK 0x02000000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_LO_ACK_MASK 0x04000000L +#define UVD_MEMCHECK2_VCPU_INT_ACK__PREF_HI_ACK_MASK 0x08000000L + + +// addressBlock: uvd_uvd_pg_dec +//UVD_IPX_DLDO_CONFIG +#define UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG__SHIFT 0x6 +#define UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG__SHIFT 0x8 +#define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG__SHIFT 0xa +#define UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG__SHIFT 0xc +#define UVD_IPX_DLDO_CONFIG__ONO2_PWR_CONFIG_MASK 0x000000C0L +#define UVD_IPX_DLDO_CONFIG__ONO3_PWR_CONFIG_MASK 0x00000300L +#define UVD_IPX_DLDO_CONFIG__ONO4_PWR_CONFIG_MASK 0x00000C00L +#define UVD_IPX_DLDO_CONFIG__ONO5_PWR_CONFIG_MASK 0x00003000L +//UVD_IPX_DLDO_STATUS +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x1 +#define UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT 0x2 +#define UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS__SHIFT 0x3 +#define UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS__SHIFT 0x4 +#define UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS__SHIFT 0x5 +#define UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS__SHIFT 0x6 +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002L +#define UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK 0x00000004L +#define UVD_IPX_DLDO_STATUS__ONO2_PWR_STATUS_MASK 0x00000008L +#define UVD_IPX_DLDO_STATUS__ONO3_PWR_STATUS_MASK 0x00000010L +#define UVD_IPX_DLDO_STATUS__ONO4_PWR_STATUS_MASK 0x00000020L +#define UVD_IPX_DLDO_STATUS__ONO5_PWR_STATUS_MASK 0x00000040L +//UVD_POWER_STATUS +#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 +#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 +#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 +#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 +#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb +#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f +#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000001L +#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L +#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L +#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L +#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L +#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L +#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L +//UVD_JPEG_POWER_STATUS +#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 +#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 +#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 +#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 +#define UVD_JPEG_POWER_STATUS__DCT_DECODER_0_SNOOP_DIS__SHIFT 0xa +#define UVD_JPEG_POWER_STATUS__DCT_DECODER_1_SNOOP_DIS__SHIFT 0xb +#define UVD_JPEG_POWER_STATUS__DCT_DECODER_2_SNOOP_DIS__SHIFT 0xc +#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f +#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L +#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L +#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L +#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L +#define UVD_JPEG_POWER_STATUS__DCT_DECODER_0_SNOOP_DIS_MASK 0x00000400L +#define UVD_JPEG_POWER_STATUS__DCT_DECODER_1_SNOOP_DIS_MASK 0x00000800L +#define UVD_JPEG_POWER_STATUS__DCT_DECODER_2_SNOOP_DIS_MASK 0x00001000L +#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L +//UVD_MC_DJPEG_RD_SPACE +#define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE__SHIFT 0x0 +#define UVD_MC_DJPEG_RD_SPACE__DJPEG_RD_SPACE_MASK 0x0003FFFFL +//UVD_MC_DJPEG_WR_SPACE +#define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE__SHIFT 0x0 +#define UVD_MC_DJPEG_WR_SPACE__DJPEG_WR_SPACE_MASK 0x0003FFFFL +//UVD_PG_IND_INDEX +#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL +//UVD_PG_IND_DATA +#define UVD_PG_IND_DATA__DATA__SHIFT 0x0 +#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL +//CC_UVD_HARVESTING +#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 +#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 +#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L +#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L +//UVD_DPG_LMA_CTL +#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 +#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 +#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0xe +#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L +#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L +#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L +#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L +#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFFC000L +//UVD_DPG_LMA_DATA +#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 +#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL +//UVD_DPG_LMA_MASK +#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 +#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL +//UVD_DPG_PAUSE +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L +#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L +#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L +//UVD_SCRATCH1 +#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 +#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH2 +#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 +#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH3 +#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 +#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH4 +#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 +#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH5 +#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 +#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH6 +#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 +#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH7 +#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 +#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH8 +#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 +#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH9 +#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 +#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH10 +#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 +#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH11 +#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 +#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH12 +#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 +#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH13 +#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 +#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL +//UVD_SCRATCH14 +#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 +#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL +//UVD_FREE_COUNTER_REG +#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 +#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_DPG_VCPU_CACHE_OFFSET0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL +//UVD_DPG_LMI_VCPU_CACHE_VMID +#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_REG_FILTER_EN +#define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN__SHIFT 0x0 +#define UVD_REG_FILTER_EN__MMSCH_HI_PRIV__SHIFT 0x1 +#define UVD_REG_FILTER_EN__VIDEO_PRIV_EN__SHIFT 0x2 +#define UVD_REG_FILTER_EN__JPEG_PRIV_EN__SHIFT 0x3 +#define UVD_REG_FILTER_EN__UVD_REG_FILTER_EN_MASK 0x00000001L +#define UVD_REG_FILTER_EN__MMSCH_HI_PRIV_MASK 0x00000002L +#define UVD_REG_FILTER_EN__VIDEO_PRIV_EN_MASK 0x00000004L +#define UVD_REG_FILTER_EN__JPEG_PRIV_EN_MASK 0x00000008L +//UVD_SECURITY_REG_VIO_REPORT +#define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO__SHIFT 0x0 +#define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO__SHIFT 0x1 +#define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO__SHIFT 0x2 +#define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO__SHIFT 0x3 +#define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO__SHIFT 0x4 +#define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO__SHIFT 0x5 +#define UVD_SECURITY_REG_VIO_REPORT__HOST_REG_VIO_MASK 0x00000001L +#define UVD_SECURITY_REG_VIO_REPORT__VCPU_REG_VIO_MASK 0x00000002L +#define UVD_SECURITY_REG_VIO_REPORT__VIDEO_REG_VIO_MASK 0x00000004L +#define UVD_SECURITY_REG_VIO_REPORT__DPG_REG_VIO_MASK 0x00000008L +#define UVD_SECURITY_REG_VIO_REPORT__JPEG_REG_VIO_MASK 0x00000010L +#define UVD_SECURITY_REG_VIO_REPORT__JDPG_REG_VIO_MASK 0x00000020L +//UVD_FW_VERSION +#define UVD_FW_VERSION__FW_VERSION__SHIFT 0x0 +#define UVD_FW_VERSION__FW_VERSION_MASK 0xFFFFFFFFL +//UVD_PF_STATUS +#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 +#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 +#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 +#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 +#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 +#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 +#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 +#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 +#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 +#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 +#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa +#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb +#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc +#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd +#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe +#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf +#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 +#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 +#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 +#define UVD_PF_STATUS__JPEG2_PF_OCCURED__SHIFT 0x13 +#define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED__SHIFT 0x14 +#define UVD_PF_STATUS__JPEG2_PF_CLEAR__SHIFT 0x15 +#define UVD_PF_STATUS__ENCODER5_PF_OCCURED__SHIFT 0x16 +#define UVD_PF_STATUS__ENCODER5_PF_CLEAR__SHIFT 0x17 +#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L +#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L +#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L +#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L +#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L +#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L +#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L +#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L +#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L +#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L +#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L +#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L +#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L +#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L +#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L +#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L +#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L +#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L +#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L +#define UVD_PF_STATUS__JPEG2_PF_OCCURED_MASK 0x00080000L +#define UVD_PF_STATUS__DJ2_ATM_PF_OCCURED_MASK 0x00100000L +#define UVD_PF_STATUS__JPEG2_PF_CLEAR_MASK 0x00200000L +#define UVD_PF_STATUS__ENCODER5_PF_OCCURED_MASK 0x00400000L +#define UVD_PF_STATUS__ENCODER5_PF_CLEAR_MASK 0x00800000L +//UVD_DPG_CLK_EN_VCPU_REPORT +#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 +#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 +#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L +#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL +//CC_UVD_VCPU_ERR_DETECT_BOT_LO +#define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO__SHIFT 0xc +#define CC_UVD_VCPU_ERR_DETECT_BOT_LO__UVD_VCPU_ERR_DETECT_BOT_LO_MASK 0xFFFFF000L +//CC_UVD_VCPU_ERR_DETECT_BOT_HI +#define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI__SHIFT 0x0 +#define CC_UVD_VCPU_ERR_DETECT_BOT_HI__UVD_VCPU_ERR_DETECT_BOT_HI_MASK 0xFFFFFFFFL +//CC_UVD_VCPU_ERR_DETECT_TOP_LO +#define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO__SHIFT 0xc +#define CC_UVD_VCPU_ERR_DETECT_TOP_LO__UVD_VCPU_ERR_DETECT_TOP_LO_MASK 0xFFFFF000L +//CC_UVD_VCPU_ERR_DETECT_TOP_HI +#define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI__SHIFT 0x0 +#define CC_UVD_VCPU_ERR_DETECT_TOP_HI__UVD_VCPU_ERR_DETECT_TOP_HI_MASK 0xFFFFFFFFL +//CC_UVD_VCPU_ERR +#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS__SHIFT 0x0 +#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR__SHIFT 0x1 +#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN__SHIFT 0x2 +#define CC_UVD_VCPU_ERR__UVD_TMZ_DBG_DIS__SHIFT 0x3 +#define CC_UVD_VCPU_ERR__RESET_ON_FAULT__SHIFT 0x4 +#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_STATUS_MASK 0x00000001L +#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_CLEAR_MASK 0x00000002L +#define CC_UVD_VCPU_ERR__UVD_VCPU_ERR_DETECT_EN_MASK 0x00000004L +#define CC_UVD_VCPU_ERR__UVD_TMZ_DBG_DIS_MASK 0x00000008L +#define CC_UVD_VCPU_ERR__RESET_ON_FAULT_MASK 0x00000010L +//CC_UVD_VCPU_ERR_INST_ADDR_LO +#define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO__SHIFT 0x0 +#define CC_UVD_VCPU_ERR_INST_ADDR_LO__UVD_VCPU_ERR_INST_ADDR_LO_MASK 0xFFFFFFFFL +//CC_UVD_VCPU_ERR_INST_ADDR_HI +#define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI__SHIFT 0x0 +#define CC_UVD_VCPU_ERR_INST_ADDR_HI__UVD_VCPU_ERR_INST_ADDR_HI_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC_SPACE +//UVD_LMI_ATOMIC_SPACE +//UVD_GFX8_ADDR_CONFIG +#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//UVD_GFX10_ADDR_CONFIG +#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define UVD_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define UVD_GFX10_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define UVD_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//UVD_GPCNT2_CNTL +#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 +#define UVD_GPCNT2_CNTL__START__SHIFT 0x1 +#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 +#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L +#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L +#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L +//UVD_GPCNT2_TARGET_LOWER +#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 +#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL +//UVD_GPCNT2_STATUS_LOWER +#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 +#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_GPCNT2_TARGET_UPPER +#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 +#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL +//UVD_GPCNT2_STATUS_UPPER +#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 +#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL +//UVD_GPCNT3_CNTL +#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 +#define UVD_GPCNT3_CNTL__START__SHIFT 0x1 +#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 +#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 +#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa +#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L +#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L +#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L +#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L +#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L +//UVD_GPCNT3_TARGET_LOWER +#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 +#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL +//UVD_GPCNT3_STATUS_LOWER +#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 +#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_GPCNT3_TARGET_UPPER +#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 +#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL +//UVD_GPCNT3_STATUS_UPPER +#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 +#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL +//UVD_VCLK_DS_CNTL +#define UVD_VCLK_DS_CNTL__VCLK_DS_EN__SHIFT 0x0 +#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS__SHIFT 0x4 +#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 +#define UVD_VCLK_DS_CNTL__VCLK_DS_EN_MASK 0x00000001L +#define UVD_VCLK_DS_CNTL__VCLK_DS_STATUS_MASK 0x00000010L +#define UVD_VCLK_DS_CNTL__VCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L +//UVD_DCLK_DS_CNTL +#define UVD_DCLK_DS_CNTL__DCLK_DS_EN__SHIFT 0x0 +#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS__SHIFT 0x4 +#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT__SHIFT 0x10 +#define UVD_DCLK_DS_CNTL__DCLK_DS_EN_MASK 0x00000001L +#define UVD_DCLK_DS_CNTL__DCLK_DS_STATUS_MASK 0x00000010L +#define UVD_DCLK_DS_CNTL__DCLK_DS_HYSTERESIS_CNT_MASK 0xFFFF0000L +//UVD_TSC_LOWER +#define UVD_TSC_LOWER__COUNT__SHIFT 0x0 +#define UVD_TSC_LOWER__COUNT_MASK 0xFFFFFFFFL +//UVD_TSC_UPPER +#define UVD_TSC_UPPER__COUNT__SHIFT 0x0 +#define UVD_TSC_UPPER__COUNT_MASK 0x00FFFFFFL +//VCN_FEATURES +#define VCN_FEATURES__HAS_VIDEO_DEC__SHIFT 0x0 +#define VCN_FEATURES__HAS_VIDEO_ENC__SHIFT 0x1 +#define VCN_FEATURES__HAS_MJPEG_DEC__SHIFT 0x2 +#define VCN_FEATURES__HAS_MJPEG_ENC__SHIFT 0x3 +#define VCN_FEATURES__HAS_VIDEO_VIRT__SHIFT 0x4 +#define VCN_FEATURES__HAS_H264_LEGACY_DEC__SHIFT 0x5 +#define VCN_FEATURES__HAS_UDEC_DEC__SHIFT 0x6 +#define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC__SHIFT 0x7 +#define VCN_FEATURES__HAS_SCLR_DEC__SHIFT 0x8 +#define VCN_FEATURES__HAS_VP9_DEC__SHIFT 0x9 +#define VCN_FEATURES__HAS_AV1_DEC__SHIFT 0xa +#define VCN_FEATURES__HAS_EFC_ENC__SHIFT 0xb +#define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC__SHIFT 0xc +#define VCN_FEATURES__HAS_DUAL_MJPEG_DEC__SHIFT 0xd +#define VCN_FEATURES__HAS_AV1_ENC__SHIFT 0xe +#define VCN_FEATURES__INSTANCE_ID__SHIFT 0x1c +#define VCN_FEATURES__HAS_VIDEO_DEC_MASK 0x00000001L +#define VCN_FEATURES__HAS_VIDEO_ENC_MASK 0x00000002L +#define VCN_FEATURES__HAS_MJPEG_DEC_MASK 0x00000004L +#define VCN_FEATURES__HAS_MJPEG_ENC_MASK 0x00000008L +#define VCN_FEATURES__HAS_VIDEO_VIRT_MASK 0x00000010L +#define VCN_FEATURES__HAS_H264_LEGACY_DEC_MASK 0x00000020L +#define VCN_FEATURES__HAS_UDEC_DEC_MASK 0x00000040L +#define VCN_FEATURES__HAS_MJPEG2_IDCT_DEC_MASK 0x00000080L +#define VCN_FEATURES__HAS_SCLR_DEC_MASK 0x00000100L +#define VCN_FEATURES__HAS_VP9_DEC_MASK 0x00000200L +#define VCN_FEATURES__HAS_AV1_DEC_MASK 0x00000400L +#define VCN_FEATURES__HAS_EFC_ENC_MASK 0x00000800L +#define VCN_FEATURES__HAS_EFC_HDR2SDR_ENC_MASK 0x00001000L +#define VCN_FEATURES__HAS_DUAL_MJPEG_DEC_MASK 0x00002000L +#define VCN_FEATURES__HAS_AV1_ENC_MASK 0x00004000L +#define VCN_FEATURES__INSTANCE_ID_MASK 0xF0000000L +//UVD_GPUIOV_STATUS +#define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE__SHIFT 0x0 +#define UVD_GPUIOV_STATUS__UVD_GPUIOV_STATUS_VF_ENABLE_MASK 0x00000001L +//UVD_SCRATCH15 +#define UVD_SCRATCH15__SCRATCH15_DATA__SHIFT 0x0 +#define UVD_SCRATCH15__SCRATCH15_DATA_MASK 0xFFFFFFFFL +//UVD_VERSION +#define UVD_VERSION__VARIANT_TYPE__SHIFT 0x0 +#define UVD_VERSION__MINOR_VERSION__SHIFT 0x8 +#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 +#define UVD_VERSION__INSTANCE_ID__SHIFT 0x1c +#define UVD_VERSION__VARIANT_TYPE_MASK 0x000000FFL +#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FF00L +#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L +#define UVD_VERSION__INSTANCE_ID_MASK 0xF0000000L +//VCN_UMSCH_CNTL +#define VCN_UMSCH_CNTL__umsch_fw_en__SHIFT 0x0 +#define VCN_UMSCH_CNTL__umsch_fw_en_MASK 0x00000001L +//VCN_JPEG_DB_CTRL +#define VCN_JPEG_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_JPEG_DB_CTRL__EN__SHIFT 0x1e +#define VCN_JPEG_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_JPEG_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_JPEG_DB_CTRL__EN_MASK 0x40000000L +#define VCN_JPEG_DB_CTRL__HIT_MASK 0x80000000L +//VCN_RB1_DB_CTRL +#define VCN_RB1_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_RB1_DB_CTRL__EN__SHIFT 0x1e +#define VCN_RB1_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_RB1_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_RB1_DB_CTRL__EN_MASK 0x40000000L +#define VCN_RB1_DB_CTRL__HIT_MASK 0x80000000L +//VCN_RB2_DB_CTRL +#define VCN_RB2_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_RB2_DB_CTRL__EN__SHIFT 0x1e +#define VCN_RB2_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_RB2_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_RB2_DB_CTRL__EN_MASK 0x40000000L +#define VCN_RB2_DB_CTRL__HIT_MASK 0x80000000L +//VCN_RB3_DB_CTRL +#define VCN_RB3_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_RB3_DB_CTRL__EN__SHIFT 0x1e +#define VCN_RB3_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_RB3_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_RB3_DB_CTRL__EN_MASK 0x40000000L +#define VCN_RB3_DB_CTRL__HIT_MASK 0x80000000L +//VCN_RB4_DB_CTRL +#define VCN_RB4_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_RB4_DB_CTRL__EN__SHIFT 0x1e +#define VCN_RB4_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_RB4_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_RB4_DB_CTRL__EN_MASK 0x40000000L +#define VCN_RB4_DB_CTRL__HIT_MASK 0x80000000L +//VCN_UMSCH_RB_DB_CTRL +#define VCN_UMSCH_RB_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_UMSCH_RB_DB_CTRL__EN__SHIFT 0x1e +#define VCN_UMSCH_RB_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_UMSCH_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_UMSCH_RB_DB_CTRL__EN_MASK 0x40000000L +#define VCN_UMSCH_RB_DB_CTRL__HIT_MASK 0x80000000L +//VCN_RB_DB_CTRL +#define VCN_RB_DB_CTRL__OFFSET__SHIFT 0x2 +#define VCN_RB_DB_CTRL__EN__SHIFT 0x1e +#define VCN_RB_DB_CTRL__HIT__SHIFT 0x1f +#define VCN_RB_DB_CTRL__OFFSET_MASK 0x0FFFFFFCL +#define VCN_RB_DB_CTRL__EN_MASK 0x40000000L +#define VCN_RB_DB_CTRL__HIT_MASK 0x80000000L +//VCN_AGDB_CTRL0 +#define VCN_AGDB_CTRL0__OFFSET__SHIFT 0x2 +#define VCN_AGDB_CTRL0__EN__SHIFT 0x1e +#define VCN_AGDB_CTRL0__HIT__SHIFT 0x1f +#define VCN_AGDB_CTRL0__OFFSET_MASK 0x0FFFFFFCL +#define VCN_AGDB_CTRL0__EN_MASK 0x40000000L +#define VCN_AGDB_CTRL0__HIT_MASK 0x80000000L +//VCN_AGDB_CTRL1 +#define VCN_AGDB_CTRL1__OFFSET__SHIFT 0x2 +#define VCN_AGDB_CTRL1__EN__SHIFT 0x1e +#define VCN_AGDB_CTRL1__HIT__SHIFT 0x1f +#define VCN_AGDB_CTRL1__OFFSET_MASK 0x0FFFFFFCL +#define VCN_AGDB_CTRL1__EN_MASK 0x40000000L +#define VCN_AGDB_CTRL1__HIT_MASK 0x80000000L +//VCN_AGDB_CTRL2 +#define VCN_AGDB_CTRL2__OFFSET__SHIFT 0x2 +#define VCN_AGDB_CTRL2__EN__SHIFT 0x1e +#define VCN_AGDB_CTRL2__HIT__SHIFT 0x1f +#define VCN_AGDB_CTRL2__OFFSET_MASK 0x0FFFFFFCL +#define VCN_AGDB_CTRL2__EN_MASK 0x40000000L +#define VCN_AGDB_CTRL2__HIT_MASK 0x80000000L +//VCN_AGDB_CTRL3 +#define VCN_AGDB_CTRL3__OFFSET__SHIFT 0x2 +#define VCN_AGDB_CTRL3__EN__SHIFT 0x1e +#define VCN_AGDB_CTRL3__HIT__SHIFT 0x1f +#define VCN_AGDB_CTRL3__OFFSET_MASK 0x0FFFFFFCL +#define VCN_AGDB_CTRL3__EN_MASK 0x40000000L +#define VCN_AGDB_CTRL3__HIT_MASK 0x80000000L +//VCN_AGDB_CTRL4 +#define VCN_AGDB_CTRL4__OFFSET__SHIFT 0x2 +#define VCN_AGDB_CTRL4__EN__SHIFT 0x1e +#define VCN_AGDB_CTRL4__HIT__SHIFT 0x1f +#define VCN_AGDB_CTRL4__OFFSET_MASK 0x0FFFFFFCL +#define VCN_AGDB_CTRL4__EN_MASK 0x40000000L +#define VCN_AGDB_CTRL4__HIT_MASK 0x80000000L +//VCN_AGDB_CTRL5 +#define VCN_AGDB_CTRL5__OFFSET__SHIFT 0x2 +#define VCN_AGDB_CTRL5__EN__SHIFT 0x1e +#define VCN_AGDB_CTRL5__HIT__SHIFT 0x1f +#define VCN_AGDB_CTRL5__OFFSET_MASK 0x0FFFFFFCL +#define VCN_AGDB_CTRL5__EN_MASK 0x40000000L +#define VCN_AGDB_CTRL5__HIT_MASK 0x80000000L +//VCN_AGDB_MASK0 +#define VCN_AGDB_MASK0__MASK__SHIFT 0x2 +#define VCN_AGDB_MASK0__MASK_MASK 0x0FFFFFFCL +//VCN_AGDB_MASK1 +#define VCN_AGDB_MASK1__MASK__SHIFT 0x2 +#define VCN_AGDB_MASK1__MASK_MASK 0x0FFFFFFCL +//VCN_AGDB_MASK2 +#define VCN_AGDB_MASK2__MASK__SHIFT 0x2 +#define VCN_AGDB_MASK2__MASK_MASK 0x0FFFFFFCL +//VCN_AGDB_MASK3 +#define VCN_AGDB_MASK3__MASK__SHIFT 0x2 +#define VCN_AGDB_MASK3__MASK_MASK 0x0FFFFFFCL +//VCN_AGDB_MASK4 +#define VCN_AGDB_MASK4__MASK__SHIFT 0x2 +#define VCN_AGDB_MASK4__MASK_MASK 0x0FFFFFFCL +//VCN_AGDB_MASK5 +#define VCN_AGDB_MASK5__MASK__SHIFT 0x2 +#define VCN_AGDB_MASK5__MASK_MASK 0x0FFFFFFCL +//VCN_RB_ENABLE +#define VCN_RB_ENABLE__RB_EN__SHIFT 0x0 +#define VCN_RB_ENABLE__JPEG_RB_EN__SHIFT 0x1 +#define VCN_RB_ENABLE__RB1_EN__SHIFT 0x2 +#define VCN_RB_ENABLE__RB2_EN__SHIFT 0x3 +#define VCN_RB_ENABLE__RB3_EN__SHIFT 0x4 +#define VCN_RB_ENABLE__RB4_EN__SHIFT 0x5 +#define VCN_RB_ENABLE__UMSCH_RB_EN__SHIFT 0x6 +#define VCN_RB_ENABLE__EJPEG_RB_EN__SHIFT 0x7 +#define VCN_RB_ENABLE__AUDIO_RB_EN__SHIFT 0x8 +#define VCN_RB_ENABLE__DCT_DECODER_0_RB_EN__SHIFT 0x9 +#define VCN_RB_ENABLE__DCT_DECODER_1_RB_EN__SHIFT 0xa +#define VCN_RB_ENABLE__DCT_DECODER_2_RB_EN__SHIFT 0xb +#define VCN_RB_ENABLE__RB_EN_MASK 0x00000001L +#define VCN_RB_ENABLE__JPEG_RB_EN_MASK 0x00000002L +#define VCN_RB_ENABLE__RB1_EN_MASK 0x00000004L +#define VCN_RB_ENABLE__RB2_EN_MASK 0x00000008L +#define VCN_RB_ENABLE__RB3_EN_MASK 0x00000010L +#define VCN_RB_ENABLE__RB4_EN_MASK 0x00000020L +#define VCN_RB_ENABLE__UMSCH_RB_EN_MASK 0x00000040L +#define VCN_RB_ENABLE__EJPEG_RB_EN_MASK 0x00000080L +#define VCN_RB_ENABLE__AUDIO_RB_EN_MASK 0x00000100L +#define VCN_RB_ENABLE__DCT_DECODER_0_RB_EN_MASK 0x00000200L +#define VCN_RB_ENABLE__DCT_DECODER_1_RB_EN_MASK 0x00000400L +#define VCN_RB_ENABLE__DCT_DECODER_2_RB_EN_MASK 0x00000800L +//VCN_RB_WPTR_CTRL +#define VCN_RB_WPTR_CTRL__RB_CS_EN__SHIFT 0x0 +#define VCN_RB_WPTR_CTRL__JPEG_CS_EN__SHIFT 0x1 +#define VCN_RB_WPTR_CTRL__RB1_CS_EN__SHIFT 0x2 +#define VCN_RB_WPTR_CTRL__RB2_CS_EN__SHIFT 0x3 +#define VCN_RB_WPTR_CTRL__RB3_CS_EN__SHIFT 0x4 +#define VCN_RB_WPTR_CTRL__RB4_CS_EN__SHIFT 0x5 +#define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN__SHIFT 0x6 +#define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN__SHIFT 0x7 +#define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN__SHIFT 0x8 +#define VCN_RB_WPTR_CTRL__RB_CS_EN_MASK 0x00000001L +#define VCN_RB_WPTR_CTRL__JPEG_CS_EN_MASK 0x00000002L +#define VCN_RB_WPTR_CTRL__RB1_CS_EN_MASK 0x00000004L +#define VCN_RB_WPTR_CTRL__RB2_CS_EN_MASK 0x00000008L +#define VCN_RB_WPTR_CTRL__RB3_CS_EN_MASK 0x00000010L +#define VCN_RB_WPTR_CTRL__RB4_CS_EN_MASK 0x00000020L +#define VCN_RB_WPTR_CTRL__UMSCH_RB_CS_EN_MASK 0x00000040L +#define VCN_RB_WPTR_CTRL__EJPEG_RB_CS_EN_MASK 0x00000080L +#define VCN_RB_WPTR_CTRL__AUDIO_RB_CS_EN_MASK 0x00000100L +//UVD_RB_RPTR +#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR +#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_RPTR2 +#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR2 +#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_RPTR3 +#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR3 +#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L +//UVD_RB_RPTR4 +#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 +#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L +//UVD_RB_WPTR4 +#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 +#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L +//UVD_OUT_RB_RPTR +#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_OUT_RB_WPTR +#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_AUDIO_RB_RPTR +#define UVD_AUDIO_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_AUDIO_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_AUDIO_RB_WPTR +#define UVD_AUDIO_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_AUDIO_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_RBC_RB_RPTR +#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_RBC_RB_WPTR +#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_DPG_LMA_CTL2 +#define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL__SHIFT 0x0 +#define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN__SHIFT 0x1 +#define UVD_DPG_LMA_CTL2__VID_WRITE_PTR__SHIFT 0x2 +#define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR__SHIFT 0x9 +#define UVD_DPG_LMA_CTL2__DIRECT_ACCESS_SRAM_SEL_MASK 0x00000001L +#define UVD_DPG_LMA_CTL2__FIFO_DIRECT_ACCESS_EN_MASK 0x00000002L +#define UVD_DPG_LMA_CTL2__VID_WRITE_PTR_MASK 0x000001FCL +#define UVD_DPG_LMA_CTL2__JPEG_WRITE_PTR_MASK 0x0000FE00L +//UVD_IPX_DLDO_CONFIG_ONO0 +#define UVD_IPX_DLDO_CONFIG_ONO0__ONO0_PWR_CONFIG__SHIFT 0x2 +#define UVD_IPX_DLDO_CONFIG_ONO0__ONO0_PWR_CONFIG_MASK 0x0000000CL +//UVD_IPX_DLDO_CONFIG_ONO1 +#define UVD_IPX_DLDO_CONFIG_ONO1__ONO1_PWR_CONFIG__SHIFT 0x4 +#define UVD_IPX_DLDO_CONFIG_ONO1__ONO1_PWR_CONFIG_MASK 0x00000030L + + +// addressBlock: uvd_uvddec +//UVD_TOP_CTRL +#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 +#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 +#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL +#define UVD_TOP_CTRL__STD_VERSION_MASK 0x00000010L +//UVD_CGC_GATE +#define UVD_CGC_GATE__SYS__SHIFT 0x0 +#define UVD_CGC_GATE__UDEC__SHIFT 0x1 +#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 +#define UVD_CGC_GATE__REGS__SHIFT 0x3 +#define UVD_CGC_GATE__RBC__SHIFT 0x4 +#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 +#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 +#define UVD_CGC_GATE__IDCT__SHIFT 0x7 +#define UVD_CGC_GATE__MPRD__SHIFT 0x8 +#define UVD_CGC_GATE__MPC__SHIFT 0x9 +#define UVD_CGC_GATE__LBSI__SHIFT 0xa +#define UVD_CGC_GATE__LRBBM__SHIFT 0xb +#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc +#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd +#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe +#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf +#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 +#define UVD_CGC_GATE__WCB__SHIFT 0x11 +#define UVD_CGC_GATE__VCPU__SHIFT 0x12 +#define UVD_CGC_GATE__MMSCH__SHIFT 0x14 +#define UVD_CGC_GATE__LCM0__SHIFT 0x15 +#define UVD_CGC_GATE__LCM1__SHIFT 0x16 +#define UVD_CGC_GATE__MIF__SHIFT 0x17 +#define UVD_CGC_GATE__VREG__SHIFT 0x18 +#define UVD_CGC_GATE__PE__SHIFT 0x19 +#define UVD_CGC_GATE__PPU__SHIFT 0x1a +#define UVD_CGC_GATE__SMPATN__SHIFT 0x1b +#define UVD_CGC_GATE__DRM__SHIFT 0x1c +#define UVD_CGC_GATE__VIDEO_ATOMIC__SHIFT 0x1d +#define UVD_CGC_GATE__SYS_MASK 0x00000001L +#define UVD_CGC_GATE__UDEC_MASK 0x00000002L +#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L +#define UVD_CGC_GATE__REGS_MASK 0x00000008L +#define UVD_CGC_GATE__RBC_MASK 0x00000010L +#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L +#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L +#define UVD_CGC_GATE__IDCT_MASK 0x00000080L +#define UVD_CGC_GATE__MPRD_MASK 0x00000100L +#define UVD_CGC_GATE__MPC_MASK 0x00000200L +#define UVD_CGC_GATE__LBSI_MASK 0x00000400L +#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L +#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L +#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L +#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L +#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L +#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L +#define UVD_CGC_GATE__WCB_MASK 0x00020000L +#define UVD_CGC_GATE__VCPU_MASK 0x00040000L +#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L +#define UVD_CGC_GATE__LCM0_MASK 0x00200000L +#define UVD_CGC_GATE__LCM1_MASK 0x00400000L +#define UVD_CGC_GATE__MIF_MASK 0x00800000L +#define UVD_CGC_GATE__VREG_MASK 0x01000000L +#define UVD_CGC_GATE__PE_MASK 0x02000000L +#define UVD_CGC_GATE__PPU_MASK 0x04000000L +#define UVD_CGC_GATE__SMPATN_MASK 0x08000000L +#define UVD_CGC_GATE__DRM_MASK 0x10000000L +#define UVD_CGC_GATE__VIDEO_ATOMIC_MASK 0x20000000L +//UVD_CGC_CTRL +#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 +#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 +#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb +#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc +#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd +#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe +#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf +#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 +#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 +#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 +#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 +#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 +#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 +#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a +#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b +#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c +#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d +#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f +#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL +#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L +#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L +#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L +#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L +#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L +#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L +#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L +#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L +#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L +#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L +#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L +#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L +#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L +//AVM_SUVD_CGC_GATE +#define AVM_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define AVM_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define AVM_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define AVM_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define AVM_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define AVM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define AVM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define AVM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define AVM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define AVM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define AVM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define AVM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define AVM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define AVM_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define AVM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define AVM_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define AVM_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define AVM_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define AVM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define AVM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define AVM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define AVM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define AVM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define AVM_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define AVM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define AVM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define AVM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define AVM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define AVM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define AVM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define AVM_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define AVM_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define AVM_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define AVM_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define AVM_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define AVM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define AVM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define AVM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define AVM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define AVM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define AVM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define AVM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define AVM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define AVM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define AVM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define AVM_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define AVM_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define AVM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define AVM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define AVM_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define AVM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define AVM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define AVM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define AVM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define AVM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define AVM_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define AVM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define AVM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define AVM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define AVM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define AVM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define AVM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//EFC_SUVD_CGC_GATE +#define EFC_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define EFC_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define EFC_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define EFC_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define EFC_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define EFC_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define EFC_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define EFC_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define EFC_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define EFC_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define EFC_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define EFC_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define EFC_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define EFC_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define EFC_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define EFC_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define EFC_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define EFC_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define EFC_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define EFC_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define EFC_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define EFC_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define EFC_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define EFC_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define EFC_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define EFC_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define EFC_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define EFC_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define EFC_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define EFC_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define EFC_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define EFC_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define EFC_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define EFC_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define EFC_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define EFC_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define EFC_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define EFC_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define EFC_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define EFC_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define EFC_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define EFC_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define EFC_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define EFC_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define EFC_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define EFC_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define EFC_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define EFC_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define EFC_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define EFC_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define EFC_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define EFC_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define EFC_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define EFC_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define EFC_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define EFC_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define EFC_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define EFC_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define EFC_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define EFC_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define EFC_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define EFC_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//ENT_SUVD_CGC_GATE +#define ENT_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define ENT_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define ENT_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define ENT_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define ENT_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define ENT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define ENT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define ENT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define ENT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define ENT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define ENT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define ENT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define ENT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define ENT_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define ENT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define ENT_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define ENT_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define ENT_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define ENT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define ENT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define ENT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define ENT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define ENT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define ENT_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define ENT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define ENT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define ENT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define ENT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define ENT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define ENT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define ENT_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define ENT_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define ENT_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define ENT_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define ENT_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define ENT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define ENT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define ENT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define ENT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define ENT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define ENT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define ENT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define ENT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define ENT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define ENT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define ENT_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define ENT_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define ENT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define ENT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define ENT_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define ENT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define ENT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define ENT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define ENT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define ENT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define ENT_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define ENT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define ENT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define ENT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define ENT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define ENT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define ENT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//IME_SUVD_CGC_GATE +#define IME_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define IME_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define IME_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define IME_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define IME_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define IME_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define IME_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define IME_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define IME_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define IME_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define IME_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define IME_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define IME_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define IME_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define IME_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define IME_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define IME_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define IME_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define IME_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define IME_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define IME_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define IME_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define IME_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define IME_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define IME_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define IME_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define IME_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define IME_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define IME_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define IME_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define IME_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define IME_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define IME_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define IME_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define IME_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define IME_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define IME_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define IME_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define IME_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define IME_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define IME_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define IME_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define IME_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define IME_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define IME_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define IME_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define IME_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define IME_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define IME_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define IME_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define IME_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define IME_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define IME_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define IME_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define IME_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define IME_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define IME_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define IME_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define IME_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define IME_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define IME_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define IME_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define IME_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define IME_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//PPU_SUVD_CGC_GATE +#define PPU_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define PPU_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define PPU_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define PPU_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define PPU_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define PPU_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define PPU_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define PPU_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define PPU_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define PPU_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define PPU_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define PPU_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define PPU_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define PPU_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define PPU_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define PPU_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define PPU_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define PPU_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define PPU_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define PPU_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define PPU_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define PPU_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define PPU_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define PPU_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define PPU_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define PPU_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define PPU_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define PPU_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define PPU_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define PPU_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define PPU_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define PPU_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define PPU_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define PPU_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define PPU_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define PPU_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define PPU_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define PPU_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define PPU_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define PPU_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define PPU_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define PPU_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define PPU_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define PPU_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define PPU_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define PPU_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define PPU_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define PPU_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define PPU_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define PPU_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define PPU_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define PPU_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define PPU_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define PPU_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define PPU_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define PPU_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define PPU_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define PPU_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define PPU_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define PPU_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define PPU_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define PPU_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SAOE_SUVD_CGC_GATE +#define SAOE_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SAOE_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SAOE_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SAOE_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SAOE_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SAOE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SAOE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SAOE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SAOE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SAOE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SAOE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SAOE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SAOE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SAOE_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SAOE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SAOE_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SAOE_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SAOE_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SAOE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SAOE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SAOE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SAOE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SAOE_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SAOE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SAOE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SAOE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SAOE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SAOE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SAOE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SAOE_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SAOE_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SAOE_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SAOE_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SAOE_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SAOE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SAOE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SAOE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SAOE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SAOE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SAOE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SAOE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SAOE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SAOE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SAOE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SAOE_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SAOE_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SAOE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SAOE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SAOE_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SAOE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SAOE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SAOE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SAOE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SAOE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SAOE_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SAOE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SAOE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SAOE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SAOE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SAOE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SAOE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SCM_SUVD_CGC_GATE +#define SCM_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SCM_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SCM_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SCM_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SCM_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SCM_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SCM_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SCM_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SCM_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SCM_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SCM_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SCM_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SCM_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SCM_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SCM_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SCM_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SCM_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SCM_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SCM_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SCM_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SCM_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SCM_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SCM_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SCM_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SCM_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SCM_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SCM_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SCM_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SCM_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SCM_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SCM_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SCM_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SCM_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SCM_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SCM_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SCM_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SCM_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SCM_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SCM_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SCM_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SCM_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SCM_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SCM_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SCM_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SCM_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SCM_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SCM_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SCM_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SCM_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SCM_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SCM_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SCM_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SCM_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SCM_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SCM_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SCM_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SCM_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SCM_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SCM_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SCM_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SCM_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SCM_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SDB_SUVD_CGC_GATE +#define SDB_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SDB_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SDB_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SDB_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SDB_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SDB_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SDB_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SDB_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SDB_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SDB_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SDB_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SDB_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SDB_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SDB_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SDB_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SDB_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SDB_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SDB_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SDB_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SDB_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SDB_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SDB_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SDB_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SDB_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SDB_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SDB_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SDB_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SDB_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SDB_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SDB_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SDB_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SDB_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SDB_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SDB_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SDB_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SDB_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SDB_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SDB_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SDB_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SDB_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SDB_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SDB_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SDB_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SDB_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SDB_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SDB_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SDB_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SDB_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SDB_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SDB_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SDB_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SDB_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SDB_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SDB_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SDB_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SDB_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SDB_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SDB_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SDB_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SDB_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SDB_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SDB_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SIT0_NXT_SUVD_CGC_GATE +#define SIT0_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SIT0_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SIT0_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SIT0_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SIT0_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SIT0_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SIT0_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SIT0_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SIT0_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SIT0_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SIT0_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SIT0_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SIT0_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SIT0_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SIT0_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SIT0_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SIT0_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SIT0_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SIT0_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SIT0_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SIT0_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SIT0_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SIT0_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SIT0_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SIT0_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SIT0_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SIT0_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SIT0_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SIT0_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SIT0_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SIT0_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SIT0_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SIT0_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SIT0_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SIT0_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SIT0_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SIT0_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SIT0_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SIT0_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SIT0_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SIT0_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SIT0_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SIT0_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SIT0_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SIT0_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SIT0_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SIT0_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SIT1_NXT_SUVD_CGC_GATE +#define SIT1_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SIT1_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SIT1_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SIT1_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SIT1_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SIT1_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SIT1_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SIT1_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SIT1_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SIT1_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SIT1_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SIT1_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SIT1_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SIT1_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SIT1_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SIT1_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SIT1_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SIT1_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SIT1_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SIT1_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SIT1_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SIT1_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SIT1_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SIT1_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SIT1_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SIT1_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SIT1_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SIT1_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SIT1_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SIT1_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SIT1_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SIT1_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SIT1_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SIT1_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SIT1_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SIT1_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SIT1_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SIT1_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SIT1_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SIT1_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SIT1_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SIT1_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SIT1_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SIT1_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SIT1_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SIT1_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SIT1_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SIT2_NXT_SUVD_CGC_GATE +#define SIT2_NXT_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SIT2_NXT_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SIT2_NXT_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SIT2_NXT_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SIT2_NXT_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SIT2_NXT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SIT2_NXT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SIT2_NXT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SIT2_NXT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SIT2_NXT_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SIT2_NXT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SIT2_NXT_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SIT2_NXT_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SIT2_NXT_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SIT2_NXT_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SIT2_NXT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SIT2_NXT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SIT2_NXT_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SIT2_NXT_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SIT2_NXT_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SIT2_NXT_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SIT2_NXT_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SIT2_NXT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SIT2_NXT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SIT2_NXT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SIT2_NXT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SIT2_NXT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SIT2_NXT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SIT2_NXT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SIT2_NXT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SIT2_NXT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SIT2_NXT_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SIT2_NXT_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SIT2_NXT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SIT2_NXT_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SIT2_NXT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SIT2_NXT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SIT2_NXT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SIT2_NXT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SIT2_NXT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SIT2_NXT_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SIT2_NXT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SIT2_NXT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SIT2_NXT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SIT2_NXT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SIT2_NXT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SIT2_NXT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SIT_SUVD_CGC_GATE +#define SIT_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SIT_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SIT_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SIT_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SIT_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SIT_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SIT_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SIT_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SIT_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SIT_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SIT_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SIT_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SIT_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SIT_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SIT_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SIT_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SIT_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SIT_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SIT_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SIT_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SIT_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SIT_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SIT_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SIT_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SIT_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SIT_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SIT_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SIT_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SIT_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SIT_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SIT_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SIT_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SIT_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SIT_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SIT_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SIT_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SIT_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SIT_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SIT_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SIT_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SIT_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SIT_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SIT_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SIT_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SIT_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SIT_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SIT_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SIT_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SIT_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SIT_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SIT_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SIT_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SIT_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SIT_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SIT_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SIT_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SIT_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SIT_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SIT_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SIT_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SIT_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SIT_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SMPA_SUVD_CGC_GATE +#define SMPA_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SMPA_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SMPA_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SMPA_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SMPA_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SMPA_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SMPA_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SMPA_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SMPA_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SMPA_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SMPA_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SMPA_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SMPA_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SMPA_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SMPA_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SMPA_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SMPA_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SMPA_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SMPA_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SMPA_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SMPA_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SMPA_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SMPA_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SMPA_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SMPA_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SMPA_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SMPA_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SMPA_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SMPA_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SMPA_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SMPA_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SMPA_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SMPA_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SMPA_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SMPA_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SMPA_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SMPA_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SMPA_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SMPA_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SMPA_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SMPA_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SMPA_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SMPA_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SMPA_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SMPA_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SMPA_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SMPA_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SMPA_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SMPA_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SMPA_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SMPA_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SMPA_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SMPA_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SMPA_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SMPA_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SMPA_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SMPA_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SMPA_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SMPA_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SMPA_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SMPA_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SMP_SUVD_CGC_GATE +#define SMP_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SMP_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SMP_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SMP_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SMP_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SMP_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SMP_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SMP_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SMP_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SMP_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SMP_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SMP_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SMP_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SMP_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SMP_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SMP_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SMP_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SMP_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SMP_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SMP_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SMP_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SMP_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SMP_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SMP_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SMP_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SMP_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SMP_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SMP_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SMP_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SMP_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SMP_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SMP_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SMP_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SMP_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SMP_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SMP_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SMP_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SMP_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SMP_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SMP_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SMP_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SMP_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SMP_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SMP_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SMP_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SMP_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SMP_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SMP_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SMP_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SMP_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SMP_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SMP_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SMP_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SMP_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SMP_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SMP_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SMP_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SMP_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SMP_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SMP_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SMP_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SMP_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//SRE_SUVD_CGC_GATE +#define SRE_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define SRE_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define SRE_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define SRE_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define SRE_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define SRE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define SRE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define SRE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define SRE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define SRE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define SRE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define SRE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define SRE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define SRE_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define SRE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define SRE_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define SRE_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define SRE_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define SRE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define SRE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define SRE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define SRE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define SRE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define SRE_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define SRE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define SRE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define SRE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define SRE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define SRE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define SRE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define SRE_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define SRE_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define SRE_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define SRE_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define SRE_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define SRE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define SRE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define SRE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define SRE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define SRE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define SRE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define SRE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define SRE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define SRE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define SRE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define SRE_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define SRE_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define SRE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define SRE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define SRE_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define SRE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define SRE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define SRE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define SRE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define SRE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define SRE_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define SRE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define SRE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define SRE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define SRE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define SRE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define SRE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//UVD_SUVD_CGC_GATE +#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define UVD_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define UVD_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define UVD_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define UVD_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define UVD_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define UVD_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define UVD_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define UVD_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define UVD_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define UVD_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//AVM_SUVD_CGC_GATE2 +#define AVM_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define AVM_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define AVM_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define AVM_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define AVM_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define AVM_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define AVM_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define AVM_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define AVM_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define AVM_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define AVM_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define AVM_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define AVM_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define AVM_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define AVM_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define AVM_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define AVM_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define AVM_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define AVM_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define AVM_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define AVM_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define AVM_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define AVM_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define AVM_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define AVM_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define AVM_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//DBR_SUVD_CGC_GATE2 +#define DBR_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define DBR_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define DBR_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define DBR_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define DBR_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define DBR_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define DBR_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define DBR_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define DBR_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define DBR_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define DBR_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define DBR_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define DBR_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define DBR_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define DBR_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define DBR_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define DBR_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define DBR_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define DBR_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define DBR_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define DBR_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define DBR_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define DBR_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define DBR_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define DBR_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define DBR_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//ENT_SUVD_CGC_GATE2 +#define ENT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define ENT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define ENT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define ENT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define ENT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define ENT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define ENT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define ENT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define ENT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define ENT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define ENT_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define ENT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define ENT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define ENT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define ENT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define ENT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define ENT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define ENT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define ENT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define ENT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define ENT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define ENT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define ENT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define ENT_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define ENT_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define ENT_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//IME_SUVD_CGC_GATE2 +#define IME_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define IME_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define IME_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define IME_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define IME_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define IME_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define IME_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define IME_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define IME_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define IME_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define IME_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define IME_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define IME_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define IME_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define IME_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define IME_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define IME_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define IME_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define IME_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define IME_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define IME_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define IME_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define IME_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define IME_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define IME_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define IME_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define IME_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define IME_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define IME_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define IME_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SAOE_SUVD_CGC_GATE2 +#define SAOE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SAOE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SAOE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SAOE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SAOE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SAOE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SAOE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SAOE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SAOE_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SAOE_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SAOE_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SAOE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SAOE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SAOE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SAOE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SAOE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SAOE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SAOE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SAOE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SAOE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SAOE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SAOE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SAOE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SAOE_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SAOE_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SAOE_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SDB_SUVD_CGC_GATE2 +#define SDB_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SDB_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SDB_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SDB_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SDB_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SDB_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SDB_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SDB_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SDB_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SDB_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SDB_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SDB_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SDB_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SDB_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SDB_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SDB_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SDB_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SDB_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SDB_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SDB_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SDB_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SDB_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SDB_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SDB_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SDB_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SDB_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SIT0_NXT_SUVD_CGC_GATE2 +#define SIT0_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SIT0_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SIT0_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SIT0_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SIT0_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SIT0_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SIT0_NXT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SIT0_NXT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SIT0_NXT_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SIT0_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SIT0_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SIT0_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SIT0_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SIT0_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SIT0_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SIT0_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SIT0_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SIT0_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SIT0_NXT_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SIT0_NXT_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SIT0_NXT_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SIT1_NXT_SUVD_CGC_GATE2 +#define SIT1_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SIT1_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SIT1_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SIT1_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SIT1_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SIT1_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SIT1_NXT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SIT1_NXT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SIT1_NXT_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SIT1_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SIT1_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SIT1_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SIT1_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SIT1_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SIT1_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SIT1_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SIT1_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SIT1_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SIT1_NXT_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SIT1_NXT_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SIT1_NXT_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SIT2_NXT_SUVD_CGC_GATE2 +#define SIT2_NXT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SIT2_NXT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SIT2_NXT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SIT2_NXT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SIT2_NXT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SIT2_NXT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SIT2_NXT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SIT2_NXT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SIT2_NXT_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SIT2_NXT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SIT2_NXT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SIT2_NXT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SIT2_NXT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SIT2_NXT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SIT2_NXT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SIT2_NXT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SIT2_NXT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SIT2_NXT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SIT2_NXT_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SIT2_NXT_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SIT2_NXT_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SIT_SUVD_CGC_GATE2 +#define SIT_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SIT_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SIT_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SIT_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SIT_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SIT_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SIT_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SIT_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SIT_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SIT_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SIT_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SIT_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SIT_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SIT_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SIT_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SIT_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SIT_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SIT_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SIT_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SIT_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SIT_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SIT_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SIT_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SIT_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SIT_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SIT_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SMPA_SUVD_CGC_GATE2 +#define SMPA_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SMPA_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SMPA_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SMPA_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SMPA_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SMPA_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SMPA_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SMPA_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SMPA_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SMPA_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SMPA_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SMPA_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SMPA_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SMPA_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SMPA_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SMPA_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SMPA_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SMPA_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SMPA_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SMPA_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SMPA_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SMPA_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SMPA_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SMPA_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SMPA_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SMPA_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SMP_SUVD_CGC_GATE2 +#define SMP_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SMP_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SMP_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SMP_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SMP_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SMP_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SMP_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SMP_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SMP_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SMP_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SMP_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SMP_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SMP_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SMP_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SMP_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SMP_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SMP_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SMP_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SMP_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SMP_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SMP_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SMP_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SMP_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SMP_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SMP_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SMP_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//SRE_SUVD_CGC_GATE2 +#define SRE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define SRE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define SRE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define SRE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define SRE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define SRE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define SRE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define SRE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define SRE_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define SRE_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define SRE_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define SRE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define SRE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define SRE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define SRE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define SRE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define SRE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define SRE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define SRE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define SRE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define SRE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define SRE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define SRE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define SRE_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define SRE_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define SRE_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//UVD_SUVD_CGC_GATE2 +#define UVD_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define UVD_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define UVD_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define UVD_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define UVD_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define UVD_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define UVD_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define UVD_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define UVD_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define UVD_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define UVD_SUVD_CGC_GATE2__MPCMIF__SHIFT 0xe +#define UVD_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define UVD_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define UVD_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define UVD_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define UVD_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define UVD_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define UVD_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define UVD_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define UVD_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define UVD_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define UVD_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define UVD_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define UVD_SUVD_CGC_GATE2__MPCMIF_MASK 0x00004000L +//AVM_SUVD_CGC_CTRL +#define AVM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define AVM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define AVM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define AVM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define AVM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define AVM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define AVM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define AVM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define AVM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define AVM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define AVM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define AVM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define AVM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define AVM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define AVM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define AVM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define AVM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define AVM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define AVM_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define AVM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define AVM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define AVM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define AVM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define AVM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define AVM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define AVM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define AVM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define AVM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define AVM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define AVM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define AVM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define AVM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define AVM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define AVM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define AVM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define AVM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define AVM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define AVM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define AVM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define AVM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define AVM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define AVM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define AVM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define AVM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define AVM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define AVM_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define AVM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define AVM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define AVM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//DBR_SUVD_CGC_CTRL +#define DBR_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define DBR_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define DBR_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define DBR_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define DBR_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define DBR_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define DBR_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define DBR_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define DBR_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define DBR_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define DBR_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define DBR_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define DBR_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define DBR_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define DBR_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define DBR_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define DBR_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define DBR_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define DBR_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define DBR_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define DBR_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define DBR_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define DBR_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define DBR_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define DBR_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define DBR_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define DBR_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define DBR_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define DBR_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define DBR_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define DBR_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define DBR_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define DBR_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define DBR_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define DBR_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define DBR_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define DBR_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define DBR_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define DBR_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define DBR_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define DBR_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define DBR_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define DBR_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define DBR_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define DBR_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define DBR_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define DBR_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define DBR_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define DBR_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//EFC_SUVD_CGC_CTRL +#define EFC_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define EFC_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define EFC_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define EFC_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define EFC_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define EFC_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define EFC_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define EFC_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define EFC_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define EFC_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define EFC_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define EFC_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define EFC_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define EFC_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define EFC_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define EFC_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define EFC_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define EFC_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define EFC_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define EFC_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define EFC_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define EFC_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define EFC_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define EFC_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define EFC_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define EFC_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define EFC_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define EFC_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define EFC_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define EFC_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define EFC_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define EFC_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define EFC_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define EFC_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define EFC_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define EFC_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define EFC_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define EFC_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define EFC_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define EFC_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define EFC_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define EFC_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define EFC_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define EFC_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define EFC_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define EFC_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define EFC_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define EFC_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define EFC_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//ENT_SUVD_CGC_CTRL +#define ENT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define ENT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define ENT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define ENT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define ENT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define ENT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define ENT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define ENT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define ENT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define ENT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define ENT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define ENT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define ENT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define ENT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define ENT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define ENT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define ENT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define ENT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define ENT_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define ENT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define ENT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define ENT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define ENT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define ENT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define ENT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define ENT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define ENT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define ENT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define ENT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define ENT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define ENT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define ENT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define ENT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define ENT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define ENT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define ENT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define ENT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define ENT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define ENT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define ENT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define ENT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define ENT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define ENT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define ENT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define ENT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define ENT_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define ENT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define ENT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define ENT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//IME_SUVD_CGC_CTRL +#define IME_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define IME_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define IME_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define IME_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define IME_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define IME_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define IME_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define IME_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define IME_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define IME_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define IME_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define IME_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define IME_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define IME_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define IME_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define IME_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define IME_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define IME_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define IME_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define IME_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define IME_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define IME_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define IME_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define IME_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define IME_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define IME_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define IME_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define IME_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define IME_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define IME_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define IME_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define IME_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define IME_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define IME_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define IME_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define IME_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define IME_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define IME_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define IME_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define IME_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define IME_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define IME_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define IME_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define IME_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define IME_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define IME_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define IME_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define IME_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define IME_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define IME_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define IME_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//PPU_SUVD_CGC_CTRL +#define PPU_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define PPU_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define PPU_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define PPU_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define PPU_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define PPU_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define PPU_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define PPU_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define PPU_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define PPU_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define PPU_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define PPU_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define PPU_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define PPU_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define PPU_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define PPU_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define PPU_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define PPU_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define PPU_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define PPU_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define PPU_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define PPU_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define PPU_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define PPU_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define PPU_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define PPU_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define PPU_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define PPU_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define PPU_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define PPU_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define PPU_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define PPU_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define PPU_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define PPU_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define PPU_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define PPU_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define PPU_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define PPU_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define PPU_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define PPU_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define PPU_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define PPU_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define PPU_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define PPU_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define PPU_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define PPU_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define PPU_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define PPU_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define PPU_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SAOE_SUVD_CGC_CTRL +#define SAOE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SAOE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SAOE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SAOE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SAOE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SAOE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SAOE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SAOE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SAOE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SAOE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SAOE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SAOE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SAOE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SAOE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SAOE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SAOE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SAOE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SAOE_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SAOE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SAOE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SAOE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SAOE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SAOE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SAOE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SAOE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SAOE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SAOE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SAOE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SAOE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SAOE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SAOE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SAOE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SAOE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SAOE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SAOE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SAOE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SAOE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SAOE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SAOE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SAOE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SAOE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SAOE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SAOE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SAOE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SAOE_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SAOE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SAOE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SAOE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SCM_SUVD_CGC_CTRL +#define SCM_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SCM_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SCM_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SCM_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SCM_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SCM_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SCM_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SCM_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SCM_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SCM_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SCM_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SCM_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SCM_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SCM_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SCM_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SCM_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SCM_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SCM_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SCM_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SCM_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SCM_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SCM_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SCM_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SCM_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SCM_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SCM_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SCM_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SCM_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SCM_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SCM_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SCM_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SCM_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SCM_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SCM_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SCM_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SCM_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SCM_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SCM_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SCM_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SCM_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SCM_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SCM_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SCM_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SCM_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SCM_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SCM_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SCM_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SCM_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SCM_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SDB_SUVD_CGC_CTRL +#define SDB_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SDB_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SDB_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SDB_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SDB_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SDB_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SDB_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SDB_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SDB_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SDB_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SDB_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SDB_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SDB_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SDB_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SDB_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SDB_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SDB_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SDB_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SDB_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SDB_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SDB_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SDB_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SDB_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SDB_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SDB_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SDB_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SDB_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SDB_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SDB_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SDB_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SDB_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SDB_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SDB_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SDB_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SDB_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SDB_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SDB_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SDB_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SDB_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SDB_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SDB_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SDB_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SDB_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SDB_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SDB_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SDB_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SDB_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SDB_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SDB_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SIT0_NXT_SUVD_CGC_CTRL +#define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SIT0_NXT_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SIT0_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SIT0_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SIT0_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SIT0_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SIT0_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SIT0_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SIT0_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SIT0_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SIT0_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SIT0_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SIT0_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SIT0_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SIT0_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SIT0_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SIT0_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SIT0_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SIT0_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SIT0_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SIT0_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SIT0_NXT_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SIT0_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SIT0_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SIT0_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SIT1_NXT_SUVD_CGC_CTRL +#define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SIT1_NXT_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SIT1_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SIT1_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SIT1_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SIT1_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SIT1_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SIT1_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SIT1_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SIT1_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SIT1_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SIT1_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SIT1_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SIT1_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SIT1_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SIT1_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SIT1_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SIT1_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SIT1_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SIT1_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SIT1_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SIT1_NXT_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SIT1_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SIT1_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SIT1_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SIT2_NXT_SUVD_CGC_CTRL +#define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SIT2_NXT_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SIT2_NXT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SIT2_NXT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SIT2_NXT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SIT2_NXT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SIT2_NXT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SIT2_NXT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SIT2_NXT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SIT2_NXT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SIT2_NXT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SIT2_NXT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SIT2_NXT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SIT2_NXT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SIT2_NXT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SIT2_NXT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SIT2_NXT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SIT2_NXT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SIT2_NXT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SIT2_NXT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SIT2_NXT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SIT2_NXT_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SIT2_NXT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SIT2_NXT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SIT2_NXT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SIT_SUVD_CGC_CTRL +#define SIT_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SIT_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SIT_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SIT_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SIT_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SIT_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SIT_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SIT_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SIT_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SIT_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SIT_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SIT_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SIT_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SIT_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SIT_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SIT_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SIT_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SIT_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SIT_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SIT_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SIT_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SIT_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SIT_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SIT_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SIT_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SIT_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SIT_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SIT_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SIT_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SIT_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SIT_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SIT_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SIT_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SIT_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SIT_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SIT_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SIT_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SIT_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SIT_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SIT_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SIT_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SIT_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SIT_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SIT_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SIT_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SIT_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SIT_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SIT_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SIT_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SMPA_SUVD_CGC_CTRL +#define SMPA_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SMPA_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SMPA_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SMPA_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SMPA_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SMPA_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SMPA_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SMPA_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SMPA_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SMPA_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SMPA_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SMPA_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SMPA_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SMPA_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SMPA_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SMPA_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SMPA_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SMPA_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SMPA_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SMPA_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SMPA_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SMPA_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SMPA_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SMPA_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SMPA_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SMPA_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SMPA_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SMPA_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SMPA_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SMPA_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SMPA_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SMPA_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SMPA_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SMPA_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SMPA_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SMPA_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SMPA_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SMPA_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SMPA_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SMPA_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SMPA_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SMPA_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SMPA_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SMPA_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SMPA_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SMPA_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SMPA_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SMPA_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SMP_SUVD_CGC_CTRL +#define SMP_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SMP_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SMP_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SMP_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SMP_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SMP_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SMP_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SMP_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SMP_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SMP_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SMP_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SMP_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SMP_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SMP_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SMP_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SMP_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SMP_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SMP_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SMP_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SMP_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SMP_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SMP_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SMP_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SMP_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SMP_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SMP_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SMP_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SMP_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SMP_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SMP_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SMP_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SMP_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SMP_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SMP_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SMP_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SMP_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SMP_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SMP_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SMP_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SMP_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SMP_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SMP_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SMP_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SMP_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SMP_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SMP_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SMP_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SMP_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SMP_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//SRE_SUVD_CGC_CTRL +#define SRE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define SRE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define SRE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define SRE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define SRE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define SRE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define SRE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define SRE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define SRE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define SRE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define SRE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define SRE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define SRE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define SRE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define SRE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define SRE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define SRE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define SRE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define SRE_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define SRE_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define SRE_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define SRE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define SRE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define SRE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define SRE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define SRE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define SRE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define SRE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define SRE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define SRE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define SRE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define SRE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define SRE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define SRE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define SRE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define SRE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define SRE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define SRE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define SRE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define SRE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define SRE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define SRE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define SRE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define SRE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define SRE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define SRE_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define SRE_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define SRE_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define SRE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//UVD_SUVD_CGC_CTRL +#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define UVD_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define UVD_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define UVD_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define UVD_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define UVD_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define UVD_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define UVD_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define UVD_SUVD_CGC_CTRL__MPCMIF_MODE__SHIFT 0x17 +#define UVD_SUVD_CGC_CTRL__FBC_PCLK__SHIFT 0x1c +#define UVD_SUVD_CGC_CTRL__FBC_CCLK__SHIFT 0x1d +#define UVD_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define UVD_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define UVD_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define UVD_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define UVD_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define UVD_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define UVD_SUVD_CGC_CTRL__MPCMIF_MODE_MASK 0x00800000L +#define UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 0x10000000L +#define UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK 0x20000000L +#define UVD_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L +//UVD_CGC_CTRL3 +#define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY__SHIFT 0x0 +#define UVD_CGC_CTRL3__LCM0_MODE__SHIFT 0xb +#define UVD_CGC_CTRL3__LCM1_MODE__SHIFT 0xc +#define UVD_CGC_CTRL3__MIF_MODE__SHIFT 0xd +#define UVD_CGC_CTRL3__VREG_MODE__SHIFT 0xe +#define UVD_CGC_CTRL3__PE_MODE__SHIFT 0xf +#define UVD_CGC_CTRL3__PPU_MODE__SHIFT 0x10 +#define UVD_CGC_CTRL3__SMPATN_MODE__SHIFT 0x11 +#define UVD_CGC_CTRL3__DRM_MODE__SHIFT 0x12 +#define UVD_CGC_CTRL3__VIDEO_ATOMIC_MODE__SHIFT 0x13 +#define UVD_CGC_CTRL3__CGC_CLK_OFF_DELAY_MASK 0x000000FFL +#define UVD_CGC_CTRL3__LCM0_MODE_MASK 0x00000800L +#define UVD_CGC_CTRL3__LCM1_MODE_MASK 0x00001000L +#define UVD_CGC_CTRL3__MIF_MODE_MASK 0x00002000L +#define UVD_CGC_CTRL3__VREG_MODE_MASK 0x00004000L +#define UVD_CGC_CTRL3__PE_MODE_MASK 0x00008000L +#define UVD_CGC_CTRL3__PPU_MODE_MASK 0x00010000L +#define UVD_CGC_CTRL3__SMPATN_MODE_MASK 0x00020000L +#define UVD_CGC_CTRL3__DRM_MODE_MASK 0x00040000L +#define UVD_CGC_CTRL3__VIDEO_ATOMIC_MODE_MASK 0x00080000L +//UVD_GPCOM_VCPU_DATA0 +#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_VCPU_DATA1 +#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_CMD +#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L +//UVD_GPCOM_SYS_DATA0 +#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_GPCOM_SYS_DATA1 +#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 +#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_VCPU_INT_EN +#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 +#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 +#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 +#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 +#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 +#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 +#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 +#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 +#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa +#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb +#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc +#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd +#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe +#define UVD_VCPU_INT_EN__SUVD_EN__SHIFT 0xf +#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 +#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 +#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 +#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 +#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 +#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a +#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b +#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c +#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d +#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e +#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f +#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L +#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L +#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L +#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L +#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L +#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L +#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L +#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L +#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L +#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L +#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L +#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK 0x00002000L +#define UVD_VCPU_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK 0x00004000L +#define UVD_VCPU_INT_EN__SUVD_EN_MASK 0x00008000L +#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L +#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L +#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L +#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L +#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L +#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L +#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L +#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L +#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L +#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L +#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L +#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L +//UVD_VCPU_INT_STATUS +#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 +#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 +#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT__SHIFT 0x3 +#define UVD_VCPU_INT_STATUS__SW_RB1_INT__SHIFT 0x4 +#define UVD_VCPU_INT_STATUS__SW_RB2_INT__SHIFT 0x5 +#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 +#define UVD_VCPU_INT_STATUS__SW_RB3_INT__SHIFT 0x7 +#define UVD_VCPU_INT_STATUS__SW_RB4_INT__SHIFT 0x9 +#define UVD_VCPU_INT_STATUS__SW_RB5_INT__SHIFT 0xa +#define UVD_VCPU_INT_STATUS__LBSI_INT__SHIFT 0xb +#define UVD_VCPU_INT_STATUS__UDEC_INT__SHIFT 0xc +#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd +#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe +#define UVD_VCPU_INT_STATUS__SUVD_INT__SHIFT 0xf +#define UVD_VCPU_INT_STATUS__RPTR_WR_INT__SHIFT 0x10 +#define UVD_VCPU_INT_STATUS__JOB_START_INT__SHIFT 0x11 +#define UVD_VCPU_INT_STATUS__NJ_PF_INT__SHIFT 0x12 +#define UVD_VCPU_INT_STATUS__GPCOM_INT__SHIFT 0x14 +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 +#define UVD_VCPU_INT_STATUS__IDCT_INT__SHIFT 0x18 +#define UVD_VCPU_INT_STATUS__MPRD_INT__SHIFT 0x19 +#define UVD_VCPU_INT_STATUS__AVM_INT__SHIFT 0x1a +#define UVD_VCPU_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b +#define UVD_VCPU_INT_STATUS__MIF_HWINT__SHIFT 0x1c +#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d +#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT__SHIFT 0x1e +#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT__SHIFT 0x1f +#define UVD_VCPU_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L +#define UVD_VCPU_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L +#define UVD_VCPU_INT_STATUS__NJ_PF_RPT_INT_MASK 0x00000008L +#define UVD_VCPU_INT_STATUS__SW_RB1_INT_MASK 0x00000010L +#define UVD_VCPU_INT_STATUS__SW_RB2_INT_MASK 0x00000020L +#define UVD_VCPU_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L +#define UVD_VCPU_INT_STATUS__SW_RB3_INT_MASK 0x00000080L +#define UVD_VCPU_INT_STATUS__SW_RB4_INT_MASK 0x00000200L +#define UVD_VCPU_INT_STATUS__SW_RB5_INT_MASK 0x00000400L +#define UVD_VCPU_INT_STATUS__LBSI_INT_MASK 0x00000800L +#define UVD_VCPU_INT_STATUS__UDEC_INT_MASK 0x00001000L +#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK 0x00002000L +#define UVD_VCPU_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00004000L +#define UVD_VCPU_INT_STATUS__SUVD_INT_MASK 0x00008000L +#define UVD_VCPU_INT_STATUS__RPTR_WR_INT_MASK 0x00010000L +#define UVD_VCPU_INT_STATUS__JOB_START_INT_MASK 0x00020000L +#define UVD_VCPU_INT_STATUS__NJ_PF_INT_MASK 0x00040000L +#define UVD_VCPU_INT_STATUS__GPCOM_INT_MASK 0x00100000L +#define UVD_VCPU_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L +#define UVD_VCPU_INT_STATUS__IDCT_INT_MASK 0x01000000L +#define UVD_VCPU_INT_STATUS__MPRD_INT_MASK 0x02000000L +#define UVD_VCPU_INT_STATUS__AVM_INT_MASK 0x04000000L +#define UVD_VCPU_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L +#define UVD_VCPU_INT_STATUS__MIF_HWINT_MASK 0x10000000L +#define UVD_VCPU_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L +#define UVD_VCPU_INT_STATUS__DRV_FW_REQ_INT_MASK 0x40000000L +#define UVD_VCPU_INT_STATUS__DRV_FW_ACK_INT_MASK 0x80000000L +//UVD_VCPU_INT_ACK +#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 +#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 +#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 +#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 +#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 +#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 +#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 +#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 +#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa +#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb +#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc +#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd +#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe +#define UVD_VCPU_INT_ACK__SUVD_ACK__SHIFT 0xf +#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 +#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 +#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 +#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 +#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 +#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a +#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b +#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c +#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d +#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e +#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f +#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L +#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L +#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L +#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L +#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L +#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L +#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L +#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L +#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L +#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L +#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L +#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK 0x00002000L +#define UVD_VCPU_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK 0x00004000L +#define UVD_VCPU_INT_ACK__SUVD_ACK_MASK 0x00008000L +#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L +#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L +#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L +#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L +#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L +#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L +#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L +#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L +#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L +#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L +#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L +#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L +//UVD_VCPU_INT_ROUTE +#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 +#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 +#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 +#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L +#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L +#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L +//UVD_DRV_FW_MSG +#define UVD_DRV_FW_MSG__MSG__SHIFT 0x0 +#define UVD_DRV_FW_MSG__MSG_MASK 0xFFFFFFFFL +//UVD_FW_DRV_MSG_ACK +#define UVD_FW_DRV_MSG_ACK__ACK__SHIFT 0x0 +#define UVD_FW_DRV_MSG_ACK__ACK_MASK 0x00000001L +//UVD_SUVD_INT_EN +#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN__SHIFT 0x0 +#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN__SHIFT 0x5 +#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN__SHIFT 0x6 +#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN__SHIFT 0xb +#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN__SHIFT 0xc +#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN__SHIFT 0x11 +#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN__SHIFT 0x12 +#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN__SHIFT 0x17 +#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN__SHIFT 0x18 +#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN__SHIFT 0x1d +#define UVD_SUVD_INT_EN__FBC_ERR_INT_EN__SHIFT 0x1e +#define UVD_SUVD_INT_EN__SRE_FUNC_INT_EN_MASK 0x0000001FL +#define UVD_SUVD_INT_EN__SRE_ERR_INT_EN_MASK 0x00000020L +#define UVD_SUVD_INT_EN__SIT_FUNC_INT_EN_MASK 0x000007C0L +#define UVD_SUVD_INT_EN__SIT_ERR_INT_EN_MASK 0x00000800L +#define UVD_SUVD_INT_EN__SMP_FUNC_INT_EN_MASK 0x0001F000L +#define UVD_SUVD_INT_EN__SMP_ERR_INT_EN_MASK 0x00020000L +#define UVD_SUVD_INT_EN__SCM_FUNC_INT_EN_MASK 0x007C0000L +#define UVD_SUVD_INT_EN__SCM_ERR_INT_EN_MASK 0x00800000L +#define UVD_SUVD_INT_EN__SDB_FUNC_INT_EN_MASK 0x1F000000L +#define UVD_SUVD_INT_EN__SDB_ERR_INT_EN_MASK 0x20000000L +#define UVD_SUVD_INT_EN__FBC_ERR_INT_EN_MASK 0x40000000L +//UVD_SUVD_INT_STATUS +#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT__SHIFT 0x0 +#define UVD_SUVD_INT_STATUS__SRE_ERR_INT__SHIFT 0x5 +#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT__SHIFT 0x6 +#define UVD_SUVD_INT_STATUS__SIT_ERR_INT__SHIFT 0xb +#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT__SHIFT 0xc +#define UVD_SUVD_INT_STATUS__SMP_ERR_INT__SHIFT 0x11 +#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT__SHIFT 0x12 +#define UVD_SUVD_INT_STATUS__SCM_ERR_INT__SHIFT 0x17 +#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT__SHIFT 0x18 +#define UVD_SUVD_INT_STATUS__SDB_ERR_INT__SHIFT 0x1d +#define UVD_SUVD_INT_STATUS__FBC_ERR_INT__SHIFT 0x1e +#define UVD_SUVD_INT_STATUS__SRE_FUNC_INT_MASK 0x0000001FL +#define UVD_SUVD_INT_STATUS__SRE_ERR_INT_MASK 0x00000020L +#define UVD_SUVD_INT_STATUS__SIT_FUNC_INT_MASK 0x000007C0L +#define UVD_SUVD_INT_STATUS__SIT_ERR_INT_MASK 0x00000800L +#define UVD_SUVD_INT_STATUS__SMP_FUNC_INT_MASK 0x0001F000L +#define UVD_SUVD_INT_STATUS__SMP_ERR_INT_MASK 0x00020000L +#define UVD_SUVD_INT_STATUS__SCM_FUNC_INT_MASK 0x007C0000L +#define UVD_SUVD_INT_STATUS__SCM_ERR_INT_MASK 0x00800000L +#define UVD_SUVD_INT_STATUS__SDB_FUNC_INT_MASK 0x1F000000L +#define UVD_SUVD_INT_STATUS__SDB_ERR_INT_MASK 0x20000000L +#define UVD_SUVD_INT_STATUS__FBC_ERR_INT_MASK 0x40000000L +//UVD_SUVD_INT_ACK +#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK__SHIFT 0x0 +#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK__SHIFT 0x5 +#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK__SHIFT 0x6 +#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK__SHIFT 0xb +#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK__SHIFT 0xc +#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK__SHIFT 0x11 +#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK__SHIFT 0x12 +#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK__SHIFT 0x17 +#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK__SHIFT 0x18 +#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK__SHIFT 0x1d +#define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK__SHIFT 0x1e +#define UVD_SUVD_INT_ACK__SRE_FUNC_INT_ACK_MASK 0x0000001FL +#define UVD_SUVD_INT_ACK__SRE_ERR_INT_ACK_MASK 0x00000020L +#define UVD_SUVD_INT_ACK__SIT_FUNC_INT_ACK_MASK 0x000007C0L +#define UVD_SUVD_INT_ACK__SIT_ERR_INT_ACK_MASK 0x00000800L +#define UVD_SUVD_INT_ACK__SMP_FUNC_INT_ACK_MASK 0x0001F000L +#define UVD_SUVD_INT_ACK__SMP_ERR_INT_ACK_MASK 0x00020000L +#define UVD_SUVD_INT_ACK__SCM_FUNC_INT_ACK_MASK 0x007C0000L +#define UVD_SUVD_INT_ACK__SCM_ERR_INT_ACK_MASK 0x00800000L +#define UVD_SUVD_INT_ACK__SDB_FUNC_INT_ACK_MASK 0x1F000000L +#define UVD_SUVD_INT_ACK__SDB_ERR_INT_ACK_MASK 0x20000000L +#define UVD_SUVD_INT_ACK__FBC_ERR_INT_ACK_MASK 0x40000000L +//UVD_ENC_VCPU_INT_EN +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L +//UVD_ENC_VCPU_INT_STATUS +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR_INT_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR2_INT_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_STATUS__DCE_UVD_SCAN_IN_BUFMGR3_INT_MASK 0x00000004L +//UVD_ENC_VCPU_INT_ACK +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L +#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L +//UVD_MASTINT_EN +#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L +#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//UVD_SYS_INT_EN +#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 +#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 +#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 +#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 +#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 +#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb +#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc +#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN__SHIFT 0xd +#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN__SHIFT 0xe +#define UVD_SYS_INT_EN__SUVD_EN__SHIFT 0xf +#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 +#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 +#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 +#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 +#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b +#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c +#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d +#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f +#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L +#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L +#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L +#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L +#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L +#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L +#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L +#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_LEN_EN_MASK 0x00002000L +#define UVD_SYS_INT_EN__LMI_AXI_UNSUPPORTED_ADR_ALIGN_EN_MASK 0x00004000L +#define UVD_SYS_INT_EN__SUVD_EN_MASK 0x00008000L +#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L +#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L +#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L +#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L +#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L +#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L +#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L +#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L +//UVD_SYS_INT_STATUS +#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 +#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 +#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 +#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 +#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb +#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc +#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT__SHIFT 0xd +#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0xe +#define UVD_SYS_INT_STATUS__SUVD_INT__SHIFT 0xf +#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 +#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 +#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 +#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 +#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b +#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c +#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d +#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f +#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L +#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L +#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L +#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L +#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L +#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L +#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_LEN_INT_MASK 0x00002000L +#define UVD_SYS_INT_STATUS__LMI_AXI_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00004000L +#define UVD_SYS_INT_STATUS__SUVD_INT_MASK 0x00008000L +#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L +#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L +#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L +#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L +#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L +#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L +#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L +#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L +#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L +//UVD_SYS_INT_ACK +#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 +#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 +#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 +#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 +#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb +#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc +#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK__SHIFT 0xd +#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK__SHIFT 0xe +#define UVD_SYS_INT_ACK__SUVD_ACK__SHIFT 0xf +#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 +#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 +#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 +#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b +#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c +#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d +#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f +#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L +#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L +#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L +#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L +#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L +#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L +#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_LEN_ACK_MASK 0x00002000L +#define UVD_SYS_INT_ACK__LMI_AXI_UNSUPPORTED_ADR_ALIGN_ACK_MASK 0x00004000L +#define UVD_SYS_INT_ACK__SUVD_ACK_MASK 0x00008000L +#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L +#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L +#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L +#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L +#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L +#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L +#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L +#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L +//UVD_JOB_DONE +#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 +#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L +//UVD_CBUF_ID +#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 +#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID +#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 +#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL +//UVD_CONTEXT_ID2 +#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 +#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL +//UVD_NO_OP +#define UVD_NO_OP__NO_OP__SHIFT 0x0 +#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL +//UVD_RB_BASE_LO +#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI +#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE +#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_BASE_LO2 +#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI2 +#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE2 +#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_BASE_LO3 +#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI3 +#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE3 +#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L +//UVD_RB_BASE_LO4 +#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 +#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_RB_BASE_HI4 +#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 +#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_RB_SIZE4 +#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 +#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L +//UVD_OUT_RB_BASE_LO +#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_OUT_RB_BASE_HI +#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_OUT_RB_SIZE +#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_IOV_ACTIVE_FCN_ID +#define UVD_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define UVD_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define UVD_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000003FL +#define UVD_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L +//UVD_IOV_MAILBOX +#define UVD_IOV_MAILBOX__MAILBOX__SHIFT 0x0 +#define UVD_IOV_MAILBOX__MAILBOX_MASK 0xFFFFFFFFL +//UVD_IOV_MAILBOX_RESP +#define UVD_IOV_MAILBOX_RESP__RESP__SHIFT 0x0 +#define UVD_IOV_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL +//UVD_RB_ARB_CTRL +#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 +#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 +#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 +#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 +#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 +#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 +#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 +#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 +#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 +#define UVD_RB_ARB_CTRL__UVD_RB_DBG_EN__SHIFT 0x9 +#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L +#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L +#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L +#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L +#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L +#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L +#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L +#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L +#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L +#define UVD_RB_ARB_CTRL__UVD_RB_DBG_EN_MASK 0x00000200L +//UVD_CTX_INDEX +#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 +#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL +//UVD_CTX_DATA +#define UVD_CTX_DATA__DATA__SHIFT 0x0 +#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL +//UVD_CXW_WR +#define UVD_CXW_WR__DAT__SHIFT 0x0 +#define UVD_CXW_WR__STAT__SHIFT 0x1f +#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL +#define UVD_CXW_WR__STAT_MASK 0x80000000L +//UVD_CXW_WR_INT_ID +#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 +#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL +//UVD_CXW_WR_INT_CTX_ID +#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 +#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL +//UVD_CXW_INT_ID +#define UVD_CXW_INT_ID__ID__SHIFT 0x0 +#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL +//UVD_MPEG2_ERROR +#define UVD_MPEG2_ERROR__STATUS__SHIFT 0x0 +#define UVD_MPEG2_ERROR__STATUS_MASK 0xFFFFFFFFL +//UVD_YBASE +#define UVD_YBASE__DUM__SHIFT 0x0 +#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL +//UVD_UVBASE +#define UVD_UVBASE__DUM__SHIFT 0x0 +#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL +//UVD_PITCH +#define UVD_PITCH__DUM__SHIFT 0x0 +#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL +//UVD_WIDTH +#define UVD_WIDTH__DUM__SHIFT 0x0 +#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL +//UVD_HEIGHT +#define UVD_HEIGHT__DUM__SHIFT 0x0 +#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL +//UVD_PICCOUNT +#define UVD_PICCOUNT__DUM__SHIFT 0x0 +#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL +//UVD_MPRD_INITIAL_XY +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X__SHIFT 0x0 +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y__SHIFT 0x10 +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_X_MASK 0x00000FFFL +#define UVD_MPRD_INITIAL_XY__MPRD_SCREEN_Y_MASK 0x0FFF0000L +//UVD_MPEG2_CTRL +#define UVD_MPEG2_CTRL__EN__SHIFT 0x0 +#define UVD_MPEG2_CTRL__TRICK_MODE__SHIFT 0x1 +#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB__SHIFT 0x10 +#define UVD_MPEG2_CTRL__EN_MASK 0x00000001L +#define UVD_MPEG2_CTRL__TRICK_MODE_MASK 0x00000002L +#define UVD_MPEG2_CTRL__NUM_MB_PER_JOB_MASK 0xFFFF0000L +//UVD_MB_CTL_BUF_BASE +#define UVD_MB_CTL_BUF_BASE__BASE__SHIFT 0x0 +#define UVD_MB_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//UVD_PIC_CTL_BUF_BASE +#define UVD_PIC_CTL_BUF_BASE__BASE__SHIFT 0x0 +#define UVD_PIC_CTL_BUF_BASE__BASE_MASK 0xFFFFFFFFL +//UVD_DXVA_BUF_SIZE +#define UVD_DXVA_BUF_SIZE__PIC_SIZE__SHIFT 0x0 +#define UVD_DXVA_BUF_SIZE__MB_SIZE__SHIFT 0x10 +#define UVD_DXVA_BUF_SIZE__PIC_SIZE_MASK 0x0000FFFFL +#define UVD_DXVA_BUF_SIZE__MB_SIZE_MASK 0xFFFF0000L +//UVD_SCRATCH_NP +#define UVD_SCRATCH_NP__DATA__SHIFT 0x0 +#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL +//UVD_CLK_SWT_HANDSHAKE +#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE__SHIFT 0x0 +#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT__SHIFT 0x8 +#define UVD_CLK_SWT_HANDSHAKE__CLK_SWT_TYPE_MASK 0x00000003L +#define UVD_CLK_SWT_HANDSHAKE__CLK_DOMAIN_SWT_MASK 0x00000300L +//UVD_GP_SCRATCH0 +#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH1 +#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH2 +#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH3 +#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH4 +#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH5 +#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH6 +#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH7 +#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH8 +#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH9 +#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH10 +#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH11 +#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH12 +#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH13 +#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH14 +#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH15 +#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH16 +#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH17 +#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH18 +#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH19 +#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH20 +#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH21 +#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH22 +#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL +//UVD_GP_SCRATCH23 +#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 +#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL +//UVD_AUDIO_RB_BASE_LO +#define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define UVD_AUDIO_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//UVD_AUDIO_RB_BASE_HI +#define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define UVD_AUDIO_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//UVD_AUDIO_RB_SIZE +#define UVD_AUDIO_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_AUDIO_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L +//UVD_VCPU_INT_STATUS2 +#define UVD_VCPU_INT_STATUS2__SW_RB6_INT__SHIFT 0x0 +#define UVD_VCPU_INT_STATUS2__SW_RB6_INT_MASK 0x00000001L +//UVD_VCPU_INT_ACK2 +#define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK__SHIFT 0x0 +#define UVD_VCPU_INT_ACK2__SW_RB6_INT_ACK_MASK 0x00000001L +//UVD_VCPU_INT_EN2 +#define UVD_VCPU_INT_EN2__SW_RB6_INT_EN__SHIFT 0x0 +#define UVD_VCPU_INT_EN2__SW_RB6_INT_EN_MASK 0x00000001L +//UVD_SUVD_CGC_STATUS2 +#define UVD_SUVD_CGC_STATUS2__SMPA_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS2__SMPA_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS2__MPC1_DCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS2__MPC1_SCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS2__MPC1_VCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS2__SIT0_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS2__SIT1_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS2__SIT2_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_STATUS2__FBC_PCLK__SHIFT 0x1c +#define UVD_SUVD_CGC_STATUS2__FBC_CCLK__SHIFT 0x1d +#define UVD_SUVD_CGC_STATUS2__SMPA_VCLK_MASK 0x00000001L +#define UVD_SUVD_CGC_STATUS2__SMPA_DCLK_MASK 0x00000002L +#define UVD_SUVD_CGC_STATUS2__MPBE1_DCLK_MASK 0x00000008L +#define UVD_SUVD_CGC_STATUS2__SIT_AV1_DCLK_MASK 0x00000010L +#define UVD_SUVD_CGC_STATUS2__SDB_AV1_DCLK_MASK 0x00000020L +#define UVD_SUVD_CGC_STATUS2__MPC1_DCLK_MASK 0x00000040L +#define UVD_SUVD_CGC_STATUS2__MPC1_SCLK_MASK 0x00000080L +#define UVD_SUVD_CGC_STATUS2__MPC1_VCLK_MASK 0x00000100L +#define UVD_SUVD_CGC_STATUS2__SRE_AV1_ENC_DCLK_MASK 0x00000200L +#define UVD_SUVD_CGC_STATUS2__CDEFE_DCLK_MASK 0x00000400L +#define UVD_SUVD_CGC_STATUS2__SIT0_DCLK_MASK 0x00000800L +#define UVD_SUVD_CGC_STATUS2__SIT1_DCLK_MASK 0x00001000L +#define UVD_SUVD_CGC_STATUS2__SIT2_DCLK_MASK 0x00002000L +#define UVD_SUVD_CGC_STATUS2__FBC_PCLK_MASK 0x10000000L +#define UVD_SUVD_CGC_STATUS2__FBC_CCLK_MASK 0x20000000L +//UVD_SUVD_INT_STATUS2 +#define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT__SHIFT 0x0 +#define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT__SHIFT 0x5 +#define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT__SHIFT 0x6 +#define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT__SHIFT 0xb +#define UVD_SUVD_INT_STATUS2__SMPA_FUNC_INT_MASK 0x0000001FL +#define UVD_SUVD_INT_STATUS2__SMPA_ERR_INT_MASK 0x00000020L +#define UVD_SUVD_INT_STATUS2__SDB_AV1_FUNC_INT_MASK 0x000007C0L +#define UVD_SUVD_INT_STATUS2__SDB_AV1_ERR_INT_MASK 0x00000800L +//UVD_SUVD_INT_EN2 +#define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN__SHIFT 0x0 +#define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN__SHIFT 0x5 +#define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN__SHIFT 0x6 +#define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN__SHIFT 0xb +#define UVD_SUVD_INT_EN2__SMPA_FUNC_INT_EN_MASK 0x0000001FL +#define UVD_SUVD_INT_EN2__SMPA_ERR_INT_EN_MASK 0x00000020L +#define UVD_SUVD_INT_EN2__SDB_AV1_FUNC_INT_EN_MASK 0x000007C0L +#define UVD_SUVD_INT_EN2__SDB_AV1_ERR_INT_EN_MASK 0x00000800L +//UVD_SUVD_INT_ACK2 +#define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK__SHIFT 0x0 +#define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK__SHIFT 0x5 +#define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK__SHIFT 0x6 +#define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK__SHIFT 0xb +#define UVD_SUVD_INT_ACK2__SMPA_FUNC_INT_ACK_MASK 0x0000001FL +#define UVD_SUVD_INT_ACK2__SMPA_ERR_INT_ACK_MASK 0x00000020L +#define UVD_SUVD_INT_ACK2__SDB_AV1_FUNC_INT_ACK_MASK 0x000007C0L +#define UVD_SUVD_INT_ACK2__SDB_AV1_ERR_INT_ACK_MASK 0x00000800L +//UVD_STATUS +#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 +#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 +#define UVD_STATUS__FILL_0__SHIFT 0x8 +#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 +#define UVD_STATUS__DRM_BUSY__SHIFT 0x11 +#define UVD_STATUS__FILL_1__SHIFT 0x12 +#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f +#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L +#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL +#define UVD_STATUS__FILL_0_MASK 0x0000FF00L +#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L +#define UVD_STATUS__DRM_BUSY_MASK 0x00020000L +#define UVD_STATUS__FILL_1_MASK 0x7FFC0000L +#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L +//UVD_ENC_PIPE_BUSY +#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 +#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 +#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 +#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 +#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 +#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 +#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 +#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 +#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 +#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 +#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa +#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb +#define UVD_ENC_PIPE_BUSY__EFC_BUSY__SHIFT 0xc +#define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY__SHIFT 0xd +#define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY__SHIFT 0xe +#define UVD_ENC_PIPE_BUSY__CDEFE_BUSY__SHIFT 0xf +#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 +#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e +#define UVD_ENC_PIPE_BUSY__SAOE_BUSY__SHIFT 0x1f +#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L +#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L +#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L +#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L +#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L +#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L +#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L +#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L +#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L +#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L +#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L +#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L +#define UVD_ENC_PIPE_BUSY__EFC_BUSY_MASK 0x00001000L +#define UVD_ENC_PIPE_BUSY__MDM_PPU_BUSY_MASK 0x00002000L +#define UVD_ENC_PIPE_BUSY__MIF_AUTODMA_BUSY_MASK 0x00004000L +#define UVD_ENC_PIPE_BUSY__CDEFE_BUSY_MASK 0x00008000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L +#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L +#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L +#define UVD_ENC_PIPE_BUSY__SAOE_BUSY_MASK 0x80000000L +//UVD_FW_POWER_STATUS +#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF__SHIFT 0x0 +#define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF__SHIFT 0x1 +#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF__SHIFT 0x2 +#define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF__SHIFT 0x3 +#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF__SHIFT 0x4 +#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF__SHIFT 0x5 +#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF__SHIFT 0x6 +#define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF__SHIFT 0x7 +#define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF__SHIFT 0x8 +#define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF__SHIFT 0x9 +#define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF__SHIFT 0xa +#define UVD_FW_POWER_STATUS__UVDLM_PWR_OFF__SHIFT 0xb +#define UVD_FW_POWER_STATUS__UVDBB_PWR_OFF__SHIFT 0xc +#define UVD_FW_POWER_STATUS__UVDTHA_PWR_OFF__SHIFT 0xd +#define UVD_FW_POWER_STATUS__UVDTHB_PWR_OFF__SHIFT 0xe +#define UVD_FW_POWER_STATUS__UVDTHC_PWR_OFF__SHIFT 0xf +#define UVD_FW_POWER_STATUS__UVDTHD_PWR_OFF__SHIFT 0x10 +#define UVD_FW_POWER_STATUS__UVDTHE_PWR_OFF__SHIFT 0x11 +#define UVD_FW_POWER_STATUS__UVDF_PWR_OFF_MASK 0x00000001L +#define UVD_FW_POWER_STATUS__UVDTC_PWR_OFF_MASK 0x00000002L +#define UVD_FW_POWER_STATUS__UVDB_PWR_OFF_MASK 0x00000004L +#define UVD_FW_POWER_STATUS__UVDTA_PWR_OFF_MASK 0x00000008L +#define UVD_FW_POWER_STATUS__UVDTD_PWR_OFF_MASK 0x00000010L +#define UVD_FW_POWER_STATUS__UVDTE_PWR_OFF_MASK 0x00000020L +#define UVD_FW_POWER_STATUS__UVDE_PWR_OFF_MASK 0x00000040L +#define UVD_FW_POWER_STATUS__UVDAB_PWR_OFF_MASK 0x00000080L +#define UVD_FW_POWER_STATUS__UVDTB_PWR_OFF_MASK 0x00000100L +#define UVD_FW_POWER_STATUS__UVDNA_PWR_OFF_MASK 0x00000200L +#define UVD_FW_POWER_STATUS__UVDNB_PWR_OFF_MASK 0x00000400L +#define UVD_FW_POWER_STATUS__UVDLM_PWR_OFF_MASK 0x00000800L +#define UVD_FW_POWER_STATUS__UVDBB_PWR_OFF_MASK 0x00001000L +#define UVD_FW_POWER_STATUS__UVDTHA_PWR_OFF_MASK 0x00002000L +#define UVD_FW_POWER_STATUS__UVDTHB_PWR_OFF_MASK 0x00004000L +#define UVD_FW_POWER_STATUS__UVDTHC_PWR_OFF_MASK 0x00008000L +#define UVD_FW_POWER_STATUS__UVDTHD_PWR_OFF_MASK 0x00010000L +#define UVD_FW_POWER_STATUS__UVDTHE_PWR_OFF_MASK 0x00020000L +//UVD_CNTL +#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 +#define UVD_CNTL__SUVD_EN__SHIFT 0x13 +#define UVD_CNTL__CABAC_MB_ACC__SHIFT 0x1c +#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS__SHIFT 0x1f +#define UVD_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L +#define UVD_CNTL__SUVD_EN_MASK 0x00080000L +#define UVD_CNTL__CABAC_MB_ACC_MASK 0x10000000L +#define UVD_CNTL__LRBBM_SAFE_SYNC_DIS_MASK 0x80000000L +//UVD_SOFT_RESET +#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 +#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 +#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 +#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 +#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 +#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 +#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 +#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa +#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb +#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd +#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe +#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf +#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 +#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f +#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L +#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L +#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L +#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L +#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L +#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L +#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L +#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L +#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L +#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L +#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L +#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L +#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L +#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L +#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L +#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L +#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L +#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L +#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L +#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L +#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L +#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L +#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L +#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L +#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L +#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L +#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L +#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L +#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L +//UVD_SOFT_RESET2 +#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 +#define UVD_SOFT_RESET2__PPU_SOFT_RESET__SHIFT 0x1 +#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 +#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L +#define UVD_SOFT_RESET2__PPU_SOFT_RESET_MASK 0x00000002L +#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L +#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_MMSCH_SOFT_RESET +#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 +#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 +#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f +#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L +#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L +#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L +//UVD_WIG_CTRL +#define UVD_WIG_CTRL__AVM_SOFT_RESET__SHIFT 0x0 +#define UVD_WIG_CTRL__ACAP_SOFT_RESET__SHIFT 0x1 +#define UVD_WIG_CTRL__WIG_SOFT_RESET__SHIFT 0x2 +#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON__SHIFT 0x3 +#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON__SHIFT 0x4 +#define UVD_WIG_CTRL__AVM_SOFT_RESET_MASK 0x00000001L +#define UVD_WIG_CTRL__ACAP_SOFT_RESET_MASK 0x00000002L +#define UVD_WIG_CTRL__WIG_SOFT_RESET_MASK 0x00000004L +#define UVD_WIG_CTRL__WIG_REGCLK_FORCE_ON_MASK 0x00000008L +#define UVD_WIG_CTRL__AVM_REGCLK_FORCE_ON_MASK 0x00000010L +//UVD_CGC_STATUS +#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 +#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 +#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 +#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 +#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 +#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 +#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 +#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 +#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 +#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 +#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa +#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb +#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc +#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd +#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe +#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf +#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 +#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 +#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 +#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 +#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 +#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 +#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 +#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 +#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 +#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 +#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a +#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b +#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d +#define UVD_CGC_STATUS__LRBBM_DCLK__SHIFT 0x1e +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f +#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L +#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L +#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L +#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L +#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L +#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L +#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L +#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L +#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L +#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L +#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L +#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L +#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L +#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L +#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L +#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L +#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L +#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L +#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L +#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L +#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L +#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L +#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L +#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L +#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L +#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L +#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L +#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L +#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L +#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L +#define UVD_CGC_STATUS__LRBBM_DCLK_MASK 0x40000000L +#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L +//UVD_CGC_UDEC_STATUS +#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 +#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 +#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 +#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 +#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 +#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 +#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 +#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 +#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 +#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 +#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa +#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb +#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc +#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd +#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe +#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L +#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L +#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L +#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L +#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L +#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L +#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L +#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L +#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L +#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L +#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L +#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L +#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L +#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L +#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L +//UVD_SUVD_CGC_STATUS +#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 +#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 +#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 +#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 +#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 +#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe +#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf +#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 +#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 +#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b +#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c +#define UVD_SUVD_CGC_STATUS__SAOE_DCLK__SHIFT 0x1d +#define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK__SHIFT 0x1e +#define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK__SHIFT 0x1f +#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L +#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L +#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L +#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L +#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L +#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L +#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L +#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L +#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L +#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L +#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L +#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L +#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L +#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L +#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L +#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L +#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L +#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L +#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L +#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L +#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L +#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L +#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L +#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L +#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L +#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L +#define UVD_SUVD_CGC_STATUS__SAOE_DCLK_MASK 0x20000000L +#define UVD_SUVD_CGC_STATUS__SRE_AV1_VCLK_MASK 0x40000000L +#define UVD_SUVD_CGC_STATUS__SCM_AV1_DCLK_MASK 0x80000000L +//UVD_GPCOM_VCPU_CMD +#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 +#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f +#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L +#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL +#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L + + +// addressBlock: uvd_vcn_cdefe_cdefe_broadcast_dec0 +//CDEFE_SUVD_CGC_GATE +#define CDEFE_SUVD_CGC_GATE__SRE__SHIFT 0x0 +#define CDEFE_SUVD_CGC_GATE__SIT__SHIFT 0x1 +#define CDEFE_SUVD_CGC_GATE__SMP__SHIFT 0x2 +#define CDEFE_SUVD_CGC_GATE__SCM__SHIFT 0x3 +#define CDEFE_SUVD_CGC_GATE__SDB__SHIFT 0x4 +#define CDEFE_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 +#define CDEFE_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 +#define CDEFE_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 +#define CDEFE_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 +#define CDEFE_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 +#define CDEFE_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa +#define CDEFE_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb +#define CDEFE_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc +#define CDEFE_SUVD_CGC_GATE__SCLR__SHIFT 0xd +#define CDEFE_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe +#define CDEFE_SUVD_CGC_GATE__ENT__SHIFT 0xf +#define CDEFE_SUVD_CGC_GATE__IME__SHIFT 0x10 +#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 +#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 +#define CDEFE_SUVD_CGC_GATE__SITE__SHIFT 0x13 +#define CDEFE_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 +#define CDEFE_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 +#define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 +#define CDEFE_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 +#define CDEFE_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 +#define CDEFE_SUVD_CGC_GATE__EFC__SHIFT 0x19 +#define CDEFE_SUVD_CGC_GATE__SAOE__SHIFT 0x1a +#define CDEFE_SUVD_CGC_GATE__SRE_AV1__SHIFT 0x1b +#define CDEFE_SUVD_CGC_GATE__FBC_PCLK__SHIFT 0x1c +#define CDEFE_SUVD_CGC_GATE__FBC_CCLK__SHIFT 0x1d +#define CDEFE_SUVD_CGC_GATE__SCM_AV1__SHIFT 0x1e +#define CDEFE_SUVD_CGC_GATE__SMPA__SHIFT 0x1f +#define CDEFE_SUVD_CGC_GATE__SRE_MASK 0x00000001L +#define CDEFE_SUVD_CGC_GATE__SIT_MASK 0x00000002L +#define CDEFE_SUVD_CGC_GATE__SMP_MASK 0x00000004L +#define CDEFE_SUVD_CGC_GATE__SCM_MASK 0x00000008L +#define CDEFE_SUVD_CGC_GATE__SDB_MASK 0x00000010L +#define CDEFE_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L +#define CDEFE_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L +#define CDEFE_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L +#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L +#define CDEFE_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L +#define CDEFE_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L +#define CDEFE_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L +#define CDEFE_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L +#define CDEFE_SUVD_CGC_GATE__SCLR_MASK 0x00002000L +#define CDEFE_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L +#define CDEFE_SUVD_CGC_GATE__ENT_MASK 0x00008000L +#define CDEFE_SUVD_CGC_GATE__IME_MASK 0x00010000L +#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L +#define CDEFE_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L +#define CDEFE_SUVD_CGC_GATE__SITE_MASK 0x00080000L +#define CDEFE_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L +#define CDEFE_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L +#define CDEFE_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L +#define CDEFE_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L +#define CDEFE_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L +#define CDEFE_SUVD_CGC_GATE__EFC_MASK 0x02000000L +#define CDEFE_SUVD_CGC_GATE__SAOE_MASK 0x04000000L +#define CDEFE_SUVD_CGC_GATE__SRE_AV1_MASK 0x08000000L +#define CDEFE_SUVD_CGC_GATE__FBC_PCLK_MASK 0x10000000L +#define CDEFE_SUVD_CGC_GATE__FBC_CCLK_MASK 0x20000000L +#define CDEFE_SUVD_CGC_GATE__SCM_AV1_MASK 0x40000000L +#define CDEFE_SUVD_CGC_GATE__SMPA_MASK 0x80000000L +//CDEFE_SUVD_CGC_GATE2 +#define CDEFE_SUVD_CGC_GATE2__MPBE0__SHIFT 0x0 +#define CDEFE_SUVD_CGC_GATE2__MPBE1__SHIFT 0x1 +#define CDEFE_SUVD_CGC_GATE2__SIT_AV1__SHIFT 0x2 +#define CDEFE_SUVD_CGC_GATE2__SDB_AV1__SHIFT 0x3 +#define CDEFE_SUVD_CGC_GATE2__MPC1__SHIFT 0x4 +#define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC__SHIFT 0x5 +#define CDEFE_SUVD_CGC_GATE2__CDEFE__SHIFT 0x6 +#define CDEFE_SUVD_CGC_GATE2__AVM_0__SHIFT 0x7 +#define CDEFE_SUVD_CGC_GATE2__AVM_1__SHIFT 0x8 +#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN__SHIFT 0x9 +#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC__SHIFT 0xa +#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC__SHIFT 0xb +#define CDEFE_SUVD_CGC_GATE2__SMPN_ENC__SHIFT 0xc +#define CDEFE_SUVD_CGC_GATE2__SMPN_DEC__SHIFT 0xd +#define CDEFE_SUVD_CGC_GATE2__MPCMIF_DEC__SHIFT 0xe +#define CDEFE_SUVD_CGC_GATE2__MPBE0_MASK 0x00000001L +#define CDEFE_SUVD_CGC_GATE2__MPBE1_MASK 0x00000002L +#define CDEFE_SUVD_CGC_GATE2__SIT_AV1_MASK 0x00000004L +#define CDEFE_SUVD_CGC_GATE2__SDB_AV1_MASK 0x00000008L +#define CDEFE_SUVD_CGC_GATE2__MPC1_MASK 0x00000010L +#define CDEFE_SUVD_CGC_GATE2__SRE_AV1_ENC_MASK 0x00000020L +#define CDEFE_SUVD_CGC_GATE2__CDEFE_MASK 0x00000040L +#define CDEFE_SUVD_CGC_GATE2__AVM_0_MASK 0x00000080L +#define CDEFE_SUVD_CGC_GATE2__AVM_1_MASK 0x00000100L +#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_CMN_MASK 0x00000200L +#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_DEC_MASK 0x00000400L +#define CDEFE_SUVD_CGC_GATE2__SIT_NXT_ENC_MASK 0x00000800L +#define CDEFE_SUVD_CGC_GATE2__SMPN_ENC_MASK 0x00001000L +#define CDEFE_SUVD_CGC_GATE2__SMPN_DEC_MASK 0x00002000L +#define CDEFE_SUVD_CGC_GATE2__MPCMIF_DEC_MASK 0x00004000L +//CDEFE_SUVD_CGC_CTRL +#define CDEFE_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 +#define CDEFE_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 +#define CDEFE_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 +#define CDEFE_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 +#define CDEFE_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 +#define CDEFE_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 +#define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 +#define CDEFE_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 +#define CDEFE_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 +#define CDEFE_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 +#define CDEFE_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa +#define CDEFE_SUVD_CGC_CTRL__SAOE_MODE__SHIFT 0xb +#define CDEFE_SUVD_CGC_CTRL__SMPA_MODE__SHIFT 0xc +#define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE__SHIFT 0xd +#define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE__SHIFT 0xe +#define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE__SHIFT 0xf +#define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE__SHIFT 0x10 +#define CDEFE_SUVD_CGC_CTRL__MPC1_MODE__SHIFT 0x11 +#define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE__SHIFT 0x12 +#define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE__SHIFT 0x13 +#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE__SHIFT 0x14 +#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE__SHIFT 0x15 +#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE__SHIFT 0x16 +#define CDEFE_SUVD_CGC_CTRL__MPCMIF__SHIFT 0x17 +#define CDEFE_SUVD_CGC_CTRL__FBC_PCLK_MODE__SHIFT 0x1c +#define CDEFE_SUVD_CGC_CTRL__FBC_CCLK_MODE__SHIFT 0x1d +#define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE__SHIFT 0x1e +#define CDEFE_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L +#define CDEFE_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L +#define CDEFE_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L +#define CDEFE_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L +#define CDEFE_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L +#define CDEFE_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L +#define CDEFE_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L +#define CDEFE_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L +#define CDEFE_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L +#define CDEFE_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L +#define CDEFE_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L +#define CDEFE_SUVD_CGC_CTRL__SAOE_MODE_MASK 0x00000800L +#define CDEFE_SUVD_CGC_CTRL__SMPA_MODE_MASK 0x00001000L +#define CDEFE_SUVD_CGC_CTRL__MPBE0_MODE_MASK 0x00002000L +#define CDEFE_SUVD_CGC_CTRL__MPBE1_MODE_MASK 0x00004000L +#define CDEFE_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 0x00008000L +#define CDEFE_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 0x00010000L +#define CDEFE_SUVD_CGC_CTRL__MPC1_MODE_MASK 0x00020000L +#define CDEFE_SUVD_CGC_CTRL__AVM_0_MODE_MASK 0x00040000L +#define CDEFE_SUVD_CGC_CTRL__AVM_1_MODE_MASK 0x00080000L +#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_CMN_MODE_MASK 0x00100000L +#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_DEC_MODE_MASK 0x00200000L +#define CDEFE_SUVD_CGC_CTRL__SIT_NXT_ENC_MODE_MASK 0x00400000L +#define CDEFE_SUVD_CGC_CTRL__MPCMIF_MASK 0x00800000L +#define CDEFE_SUVD_CGC_CTRL__FBC_PCLK_MODE_MASK 0x10000000L +#define CDEFE_SUVD_CGC_CTRL__FBC_CCLK_MODE_MASK 0x20000000L +#define CDEFE_SUVD_CGC_CTRL__CDEFE_MODE_MASK 0x40000000L + + +// addressBlock: uvd_ecpudec +//UVD_VCPU_CACHE_OFFSET0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET1 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE1 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET2 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE2 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET3 +#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE3 +#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET4 +#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE4 +#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET5 +#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE5 +#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET6 +#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE6 +#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET7 +#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE7 +#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_OFFSET8 +#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 +#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL +//UVD_VCPU_CACHE_SIZE8 +#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 +#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL +//UVD_VCPU_NONCACHE_OFFSET0 +#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL +//UVD_VCPU_NONCACHE_SIZE0 +#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL +//UVD_VCPU_NONCACHE_OFFSET1 +#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL +//UVD_VCPU_NONCACHE_SIZE1 +#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 +#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL +//UVD_VCPU_CNTL +#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 +#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 +#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 +#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 +#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 +#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa +#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb +#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd +#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 +#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 +#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c +#define UVD_VCPU_CNTL__RUNSTALL__SHIFT 0x1d +#define UVD_VCPU_CNTL__SRE_CMDIF_DRST__SHIFT 0x1e +#define UVD_VCPU_CNTL__SRE_CMDIF_VRST__SHIFT 0x1f +#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL +#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x00000010L +#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L +#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L +#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L +#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L +#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L +#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L +#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L +#define UVD_VCPU_CNTL__DBG_MUX_MASK 0x0000E000L +#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L +#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L +#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L +#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L +#define UVD_VCPU_CNTL__RUNSTALL_MASK 0x20000000L +#define UVD_VCPU_CNTL__SRE_CMDIF_DRST_MASK 0x40000000L +#define UVD_VCPU_CNTL__SRE_CMDIF_VRST_MASK 0x80000000L +//UVD_VCPU_PRID +#define UVD_VCPU_PRID__PRID__SHIFT 0x0 +#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL +//UVD_VCPU_TRCE +#define UVD_VCPU_TRCE__PC__SHIFT 0x0 +#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL +//UVD_VCPU_TRCE_RD +#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 +#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL +//UVD_VCPU_IND_INDEX +#define UVD_VCPU_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_VCPU_IND_INDEX__INDEX_MASK 0x000001FFL +//UVD_VCPU_IND_DATA +#define UVD_VCPU_IND_DATA__DATA__SHIFT 0x0 +#define UVD_VCPU_IND_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_lmi_adpdec +//UVD_LMI_RE_64BIT_BAR_LOW +#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RE_64BIT_BAR_HIGH +#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_IT_64BIT_BAR_LOW +#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_IT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_IT_64BIT_BAR_HIGH +#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_IT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MP_64BIT_BAR_LOW +#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MP_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MP_64BIT_BAR_HIGH +#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MP_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_CM_64BIT_BAR_LOW +#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_CM_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_CM_64BIT_BAR_HIGH +#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_CM_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_DB_64BIT_BAR_LOW +#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_DB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_DB_64BIT_BAR_HIGH +#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_DB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_DBW_64BIT_BAR_LOW +#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_DBW_64BIT_BAR_HIGH +#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_IDCT_64BIT_BAR_LOW +#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_IDCT_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_IDCT_64BIT_BAR_HIGH +#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_IDCT_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S0_64BIT_BAR_LOW +#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPRD_S0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S0_64BIT_BAR_HIGH +#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPRD_S0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S1_64BIT_BAR_LOW +#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPRD_S1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_S1_64BIT_BAR_HIGH +#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPRD_S1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_DBW_64BIT_BAR_LOW +#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MPRD_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH +#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MPRD_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_LOW +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_LOW +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_RBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_LOW +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_LBSI_64BIT_BAR_HIGH +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_CENC_64BIT_BAR_LOW +#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_CENC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_CENC_64BIT_BAR_HIGH +#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_CENC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_SRE_64BIT_BAR_LOW +#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_SRE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_SRE_64BIT_BAR_HIGH +#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_SRE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_DBW_64BIT_BAR_LOW +#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_DBW_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_DBW_64BIT_BAR_HIGH +#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_DBW_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP0_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP1_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP2_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP3_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSP3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSP3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD0_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD1_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD2_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD3_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD4_64BIT_BAR_LOW +#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_BSD4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH +#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_BSD4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR_64BIT_BAR_LOW +#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH +#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_SPH_64BIT_BAR_HIGH +#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_SPH_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_ADP_ATOMIC_CONFIG +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE__SHIFT 0x0 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE__SHIFT 0x4 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE__SHIFT 0x8 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE__SHIFT 0xc +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG__SHIFT 0x10 +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER0_WR_CACHE_MASK 0x0000000FL +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER1_WR_CACHE_MASK 0x000000F0L +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER2_WR_CACHE_MASK 0x00000F00L +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_USER3_WR_CACHE_MASK 0x0000F000L +#define UVD_ADP_ATOMIC_CONFIG__ATOMIC_RD_URG_MASK 0x000F0000L +//UVD_LMI_ARB_CTRL2 +#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 +#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa +#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 +#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL +#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L +#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L +#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L +//UVD_LMI_VCPU_CACHE_VMIDS_MULTI +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L +#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L +//UVD_LMI_VCPU_NC_VMIDS_MULTI +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L +#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L +//UVD_LMI_LAT_CTRL +#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 +#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 +#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 +#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa +#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb +#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 +#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL +#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L +#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L +#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L +#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L +#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L +//UVD_LMI_LAT_CNTR +#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 +#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 +#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL +#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L +//UVD_LMI_AVG_LAT_CNTR +#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 +#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L +#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L +//UVD_LMI_SPH +#define UVD_LMI_SPH__ADDR__SHIFT 0x0 +#define UVD_LMI_SPH__STS__SHIFT 0x1c +#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e +#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f +#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL +#define UVD_LMI_SPH__STS_MASK 0x30000000L +#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L +#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L +//UVD_LMI_VCPU_CACHE_VMID +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 +#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL +//UVD_LMI_CTRL2 +#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 +#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 +#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 +#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 +#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 +#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 +#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 +#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a +#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b +#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L +#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L +#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L +#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L +#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L +#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L +#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L +#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L +#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L +#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L +#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L +#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L +#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L +#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L +#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L +#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L +//UVD_LMI_URGENT_CTRL +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL +#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L +#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L +#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L +#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L +//UVD_LMI_CTRL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 +#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 +#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb +#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc +#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd +#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe +#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a +#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b +#define UVD_LMI_CTRL__MC_BLK_RST__SHIFT 0x1c +#define UVD_LMI_CTRL__UMC_BLK_RST__SHIFT 0x1d +#define UVD_LMI_CTRL__CRC_EN__SHIFT 0x1e +#define UVD_LMI_CTRL__CRC1_EN__SHIFT 0x1f +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL +#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L +#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L +#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L +#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L +#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L +#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L +#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L +#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x00100000L +#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L +#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L +#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L +#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L +#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L +#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L +#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L +#define UVD_LMI_CTRL__MC_BLK_RST_MASK 0x10000000L +#define UVD_LMI_CTRL__UMC_BLK_RST_MASK 0x20000000L +#define UVD_LMI_CTRL__CRC_EN_MASK 0x40000000L +#define UVD_LMI_CTRL__CRC1_EN_MASK 0x80000000L +//UVD_LMI_STATUS +#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 +#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 +#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 +#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 +#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa +#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd +#define UVD_LMI_STATUS__LMI_UMC_DMA0_WRITE_CLEAN__SHIFT 0xe +#define UVD_LMI_STATUS__LMI_UMC_DMA1_WRITE_CLEAN__SHIFT 0xf +#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 +#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 +#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 +#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 +#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 +#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L +#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L +#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L +#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L +#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L +#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L +#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L +#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L +#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L +#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L +#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L +#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L +#define UVD_LMI_STATUS__LMI_UMC_DMA0_WRITE_CLEAN_MASK 0x00004000L +#define UVD_LMI_STATUS__LMI_UMC_DMA1_WRITE_CLEAN_MASK 0x00008000L +#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L +#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L +#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L +#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L +#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L +//UVD_LMI_PERFMON_CTRL +#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 +#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 +#define UVD_LMI_PERFMON_CTRL__PERFMON_EN__SHIFT 0xd +#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L +#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L +#define UVD_LMI_PERFMON_CTRL__PERFMON_EN_MASK 0x00002000L +//UVD_LMI_PERFMON_COUNT_LO +#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 +#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL +//UVD_LMI_PERFMON_COUNT_HI +#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 +#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL +//UVD_LMI_ADP_SWAP_CNTL +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 +#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa +#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc +#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe +#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 +#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 +#define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP__SHIFT 0x14 +#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 +#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c +#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L +#define UVD_LMI_ADP_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L +#define UVD_LMI_ADP_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L +#define UVD_LMI_ADP_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L +#define UVD_LMI_ADP_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L +#define UVD_LMI_ADP_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L +#define UVD_LMI_ADP_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L +#define UVD_LMI_ADP_SWAP_CNTL__PREF_MC_SWAP_MASK 0x00300000L +#define UVD_LMI_ADP_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L +#define UVD_LMI_ADP_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L +#define UVD_LMI_ADP_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L +//UVD_LMI_RBC_RB_VMID +#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL +//UVD_LMI_RBC_IB_VMID +#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 +#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL +//UVD_LMI_MC_CREDITS +#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 +#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 +#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 +#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 +#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL +#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L +#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L +#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L +//UVD_LMI_ADP_IND_INDEX +#define UVD_LMI_ADP_IND_INDEX__INDEX__SHIFT 0x0 +#define UVD_LMI_ADP_IND_INDEX__INDEX_MASK 0x00001FFFL +//UVD_LMI_ADP_IND_DATA +#define UVD_LMI_ADP_IND_DATA__DATA__SHIFT 0x0 +#define UVD_LMI_ADP_IND_DATA__DATA_MASK 0xFFFFFFFFL +//UVD_LMI_ADP_PF_EN +#define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN__SHIFT 0x0 +#define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN__SHIFT 0x1 +#define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN__SHIFT 0x2 +#define UVD_LMI_ADP_PF_EN__VCPU_CACHE0_PF_EN_MASK 0x00000001L +#define UVD_LMI_ADP_PF_EN__VCPU_CACHE1_PF_EN_MASK 0x00000002L +#define UVD_LMI_ADP_PF_EN__VCPU_CACHE2_PF_EN_MASK 0x00000004L +//UVD_LMI_PREF_CTRL +#define UVD_LMI_PREF_CTRL__PREF_RST__SHIFT 0x0 +#define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS__SHIFT 0x1 +#define UVD_LMI_PREF_CTRL__PREF_WSTRB__SHIFT 0x2 +#define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE__SHIFT 0x3 +#define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE__SHIFT 0x4 +#define UVD_LMI_PREF_CTRL__PREF_SIZE__SHIFT 0x13 +#define UVD_LMI_PREF_CTRL__PREF_RST_MASK 0x00000001L +#define UVD_LMI_PREF_CTRL__PREF_BUSY_STATUS_MASK 0x00000002L +#define UVD_LMI_PREF_CTRL__PREF_WSTRB_MASK 0x00000004L +#define UVD_LMI_PREF_CTRL__PREF_WRITE_SIZE_MASK 0x00000008L +#define UVD_LMI_PREF_CTRL__PREF_STEP_SIZE_MASK 0x00000070L +#define UVD_LMI_PREF_CTRL__PREF_SIZE_MASK 0xFFF80000L + + +// addressBlock: uvd_uvd_dct_decoder_rbc_0_uvd_jrbc_dec +//UVD_JRBC1_UVD_JRBC_RB_WPTR +#define UVD_JRBC1_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC1_UVD_JRBC_RB_CNTL +#define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC1_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC1_UVD_JRBC_IB_SIZE +#define UVD_JRBC1_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC1_UVD_JRBC_URGENT_CNTL +#define UVD_JRBC1_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC1_UVD_JRBC_RB_REF_DATA +#define UVD_JRBC1_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC1_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC1_UVD_JRBC_SOFT_RESET +#define UVD_JRBC1_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC1_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC1_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC1_UVD_JRBC_STATUS +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC1_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC1_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC1_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC1_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC1_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC1_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC1_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC1_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC1_UVD_JRBC_RB_RPTR +#define UVD_JRBC1_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS +#define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC1_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS +#define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC1_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE +#define UVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC1_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC1_UVD_JRBC_IB_REF_DATA +#define UVD_JRBC1_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC1_UVD_JPEG_PREEMPT_CMD +#define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC1_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JRBC1_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC1_UVD_JRBC_RB_SIZE +#define UVD_JRBC1_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC1_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC1_UVD_JRBC_SCRATCH0 +#define UVD_JRBC1_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC1_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_uvd_dct_decoder_rbc_1_uvd_jrbc_dec +//UVD_JRBC2_UVD_JRBC_RB_WPTR +#define UVD_JRBC2_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC2_UVD_JRBC_RB_CNTL +#define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC2_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC2_UVD_JRBC_IB_SIZE +#define UVD_JRBC2_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC2_UVD_JRBC_URGENT_CNTL +#define UVD_JRBC2_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC2_UVD_JRBC_RB_REF_DATA +#define UVD_JRBC2_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC2_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC2_UVD_JRBC_SOFT_RESET +#define UVD_JRBC2_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC2_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC2_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC2_UVD_JRBC_STATUS +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC2_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC2_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC2_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC2_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC2_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC2_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC2_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC2_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC2_UVD_JRBC_RB_RPTR +#define UVD_JRBC2_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS +#define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC2_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS +#define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC2_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE +#define UVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC2_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC2_UVD_JRBC_IB_REF_DATA +#define UVD_JRBC2_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC2_UVD_JPEG_PREEMPT_CMD +#define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC2_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JRBC2_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC2_UVD_JRBC_RB_SIZE +#define UVD_JRBC2_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC2_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC2_UVD_JRBC_SCRATCH0 +#define UVD_JRBC2_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC2_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_uvd_jpeg0_jpegnpdec +//UVD_JPEG_CNTL +#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 +#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 +#define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 +#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L +#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L +#define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L +//UVD_JPEG_RB_BASE +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 +#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 +#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL +#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L +//UVD_JPEG_RB_WPTR +#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_RPTR +#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L +//UVD_JPEG_RB_SIZE +#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L +//UVD_JPEG_DEC_CNT +#define UVD_JPEG_DEC_CNT__DECODE_COUNT__SHIFT 0x0 +#define UVD_JPEG_DEC_CNT__DECODE_COUNT_MASK 0xFFFFFFFFL +//UVD_JPEG_SPS_INFO +#define UVD_JPEG_SPS_INFO__PIC_WIDTH__SHIFT 0x0 +#define UVD_JPEG_SPS_INFO__PIC_HEIGHT__SHIFT 0x10 +#define UVD_JPEG_SPS_INFO__PIC_WIDTH_MASK 0x0000FFFFL +#define UVD_JPEG_SPS_INFO__PIC_HEIGHT_MASK 0xFFFF0000L +//UVD_JPEG_SPS1_INFO +#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC__SHIFT 0x0 +#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT__SHIFT 0x3 +#define UVD_JPEG_SPS1_INFO__OUT_FMT_422__SHIFT 0x4 +#define UVD_JPEG_SPS1_INFO__CHROMA_FORMAT_IDC_MASK 0x00000007L +#define UVD_JPEG_SPS1_INFO__YUV422_SUBFORMAT_MASK 0x00000008L +#define UVD_JPEG_SPS1_INFO__OUT_FMT_422_MASK 0x00000010L +//UVD_JPEG_RE_TIMER +#define UVD_JPEG_RE_TIMER__TIMER_OUT__SHIFT 0x0 +#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN__SHIFT 0x10 +#define UVD_JPEG_RE_TIMER__TIMER_OUT_MASK 0x000000FFL +#define UVD_JPEG_RE_TIMER__TIMER_OUT_EN_MASK 0x00010000L +//UVD_JPEG_DEC_SCRATCH0 +#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL +//UVD_JPEG_INT_EN +#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 +#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 +#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 +#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 +#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 +#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 +#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 +#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa +#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb +#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc +#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd +#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe +#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf +#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L +#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L +#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L +#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L +#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L +#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L +#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L +#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L +#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L +#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L +#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L +#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L +#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L +//UVD_JPEG_INT_STAT +#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 +#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 +#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 +#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 +#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 +#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 +#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 +#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa +#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb +#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc +#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd +#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe +#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf +#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L +#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L +#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L +#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L +#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L +#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L +#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L +#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L +#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L +#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L +#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L +#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L +#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L +//UVD_JPEG_TIER_CNTL0 +#define UVD_JPEG_TIER_CNTL0__TIER_SEL__SHIFT 0x0 +#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID__SHIFT 0x2 +#define UVD_JPEG_TIER_CNTL0__U_COMP_ID__SHIFT 0x4 +#define UVD_JPEG_TIER_CNTL0__V_COMP_ID__SHIFT 0x6 +#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC__SHIFT 0x8 +#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC__SHIFT 0xb +#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC__SHIFT 0xe +#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC__SHIFT 0x11 +#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC__SHIFT 0x14 +#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC__SHIFT 0x17 +#define UVD_JPEG_TIER_CNTL0__Y_TQ__SHIFT 0x1a +#define UVD_JPEG_TIER_CNTL0__U_TQ__SHIFT 0x1c +#define UVD_JPEG_TIER_CNTL0__V_TQ__SHIFT 0x1e +#define UVD_JPEG_TIER_CNTL0__TIER_SEL_MASK 0x00000003L +#define UVD_JPEG_TIER_CNTL0__Y_COMP_ID_MASK 0x0000000CL +#define UVD_JPEG_TIER_CNTL0__U_COMP_ID_MASK 0x00000030L +#define UVD_JPEG_TIER_CNTL0__V_COMP_ID_MASK 0x000000C0L +#define UVD_JPEG_TIER_CNTL0__Y_H_SAMP_FAC_MASK 0x00000700L +#define UVD_JPEG_TIER_CNTL0__Y_V_SAMP_FAC_MASK 0x00003800L +#define UVD_JPEG_TIER_CNTL0__U_H_SAMP_FAC_MASK 0x0001C000L +#define UVD_JPEG_TIER_CNTL0__U_V_SAMP_FAC_MASK 0x000E0000L +#define UVD_JPEG_TIER_CNTL0__V_H_SAMP_FAC_MASK 0x00700000L +#define UVD_JPEG_TIER_CNTL0__V_V_SAMP_FAC_MASK 0x03800000L +#define UVD_JPEG_TIER_CNTL0__Y_TQ_MASK 0x0C000000L +#define UVD_JPEG_TIER_CNTL0__U_TQ_MASK 0x30000000L +#define UVD_JPEG_TIER_CNTL0__V_TQ_MASK 0xC0000000L +//UVD_JPEG_TIER_CNTL1 +#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH__SHIFT 0x0 +#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT__SHIFT 0x10 +#define UVD_JPEG_TIER_CNTL1__SRC_WIDTH_MASK 0x0000FFFFL +#define UVD_JPEG_TIER_CNTL1__SRC_HEIGHT_MASK 0xFFFF0000L +//UVD_JPEG_TIER_CNTL2 +#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL__SHIFT 0x0 +#define UVD_JPEG_TIER_CNTL2__TBL_TYPE__SHIFT 0x1 +#define UVD_JPEG_TIER_CNTL2__TQ__SHIFT 0x2 +#define UVD_JPEG_TIER_CNTL2__TH__SHIFT 0x4 +#define UVD_JPEG_TIER_CNTL2__TC__SHIFT 0x6 +#define UVD_JPEG_TIER_CNTL2__TD__SHIFT 0x7 +#define UVD_JPEG_TIER_CNTL2__TA__SHIFT 0xa +#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN__SHIFT 0xe +#define UVD_JPEG_TIER_CNTL2__DRI_VAL__SHIFT 0x10 +#define UVD_JPEG_TIER_CNTL2__TBL_ECS_SEL_MASK 0x00000001L +#define UVD_JPEG_TIER_CNTL2__TBL_TYPE_MASK 0x00000002L +#define UVD_JPEG_TIER_CNTL2__TQ_MASK 0x0000000CL +#define UVD_JPEG_TIER_CNTL2__TH_MASK 0x00000030L +#define UVD_JPEG_TIER_CNTL2__TC_MASK 0x00000040L +#define UVD_JPEG_TIER_CNTL2__TD_MASK 0x00000380L +#define UVD_JPEG_TIER_CNTL2__TA_MASK 0x00001C00L +#define UVD_JPEG_TIER_CNTL2__TIER2_HTBL_CNTLEN_MASK 0x00004000L +#define UVD_JPEG_TIER_CNTL2__DRI_VAL_MASK 0xFFFF0000L +//UVD_JPEG_TIER_STATUS +#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE__SHIFT 0x0 +#define UVD_JPEG_TIER_STATUS__DECODE_DONE__SHIFT 0x1 +#define UVD_JPEG_TIER_STATUS__BSI_FETCH_DONE_MASK 0x00000001L +#define UVD_JPEG_TIER_STATUS__DECODE_DONE_MASK 0x00000002L + + +// addressBlock: uvd_uvd_jpeg_sclk0_jpegnpsclkdec +//UVD_JPEG_OUTBUF_CNTL +#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT__SHIFT 0x0 +#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN__SHIFT 0x2 +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX__SHIFT 0x6 +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT__SHIFT 0x7 +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER__SHIFT 0x9 +#define UVD_JPEG_OUTBUF_CNTL__DIS_OBUF_AVAIL_CHECK__SHIFT 0x10 +#define UVD_JPEG_OUTBUF_CNTL__OUTBUF_CNT_MASK 0x00000003L +#define UVD_JPEG_OUTBUF_CNTL__HGT_ALIGN_MASK 0x00000004L +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_DECODE_DONE_FIX_MASK 0x00000040L +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_MAX_CNT_MASK 0x00000180L +#define UVD_JPEG_OUTBUF_CNTL__JPEG0_WR_COMB_TIMER_MASK 0x00001E00L +#define UVD_JPEG_OUTBUF_CNTL__DIS_OBUF_AVAIL_CHECK_MASK 0x00010000L +//UVD_JPEG_OUTBUF_WPTR +#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR__SHIFT 0x0 +#define UVD_JPEG_OUTBUF_WPTR__OUTBUF_WPTR_MASK 0xFFFFFFFFL +//UVD_JPEG_OUTBUF_RPTR +#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR__SHIFT 0x0 +#define UVD_JPEG_OUTBUF_RPTR__OUTBUF_RPTR_MASK 0xFFFFFFFFL +//UVD_JPEG_PITCH +#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 +#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL +//UVD_JPEG_UV_PITCH +#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 +#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL +//JPEG_DEC_Y_GFX8_TILING_SURFACE +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L +#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L +//JPEG_DEC_UV_GFX8_TILING_SURFACE +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L +#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L +//JPEG_DEC_GFX8_ADDR_CONFIG +#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L +//JPEG_DEC_Y_GFX10_TILING_SURFACE +#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_DEC_UV_GFX10_TILING_SURFACE +#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 +#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL +//JPEG_DEC_GFX10_ADDR_CONFIG +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L +#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L +#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L +//JPEG_DEC_ADDR_MODE +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 +#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L +#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL +#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L +//UVD_JPEG_OUTPUT_XY +#define UVD_JPEG_OUTPUT_XY__OUTPUT_X__SHIFT 0x0 +#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y__SHIFT 0x10 +#define UVD_JPEG_OUTPUT_XY__OUTPUT_X_MASK 0x00003FFFL +#define UVD_JPEG_OUTPUT_XY__OUTPUT_Y_MASK 0x3FFF0000L +//UVD_JPEG_GPCOM_CMD +#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 +#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL +//UVD_JPEG_GPCOM_DATA0 +#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL +//UVD_JPEG_GPCOM_DATA1 +#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 +#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL +//UVD_JPEG_SCRATCH1 +#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 +#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL +//UVD_JPEG_DEC_SOFT_RST +#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 +#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 +#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L +#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L + + +// addressBlock: uvd_uvd_jrbc0_uvd_jrbc_dec +//UVD_JRBC0_UVD_JRBC_RB_WPTR +#define UVD_JRBC0_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC0_UVD_JRBC_RB_CNTL +#define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC0_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC0_UVD_JRBC_IB_SIZE +#define UVD_JRBC0_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC0_UVD_JRBC_URGENT_CNTL +#define UVD_JRBC0_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC0_UVD_JRBC_RB_REF_DATA +#define UVD_JRBC0_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC0_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC0_UVD_JRBC_SOFT_RESET +#define UVD_JRBC0_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC0_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC0_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC0_UVD_JRBC_STATUS +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC0_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC0_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC0_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC0_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC0_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC0_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC0_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC0_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC0_UVD_JRBC_RB_RPTR +#define UVD_JRBC0_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS +#define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC0_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS +#define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC0_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE +#define UVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC0_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC0_UVD_JRBC_IB_REF_DATA +#define UVD_JRBC0_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC0_UVD_JPEG_PREEMPT_CMD +#define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC0_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JRBC0_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC0_UVD_JRBC_RB_SIZE +#define UVD_JRBC0_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC0_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC0_UVD_JRBC_SCRATCH0 +#define UVD_JRBC0_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC0_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_uvd_jmi0_uvd_jmi_dec +//UVD_JPEG_DEC_PF_CTRL +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS__SHIFT 0x0 +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING__SHIFT 0x1 +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_HANDLING_DIS_MASK 0x00000001L +#define UVD_JPEG_DEC_PF_CTRL__DEC_PF_SW_GATING_MASK 0x00000002L +//UVD_LMI_JRBC_CTRL +#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L +//UVD_LMI_JPEG_CTRL +#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 +#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 +#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 +#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 +#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 +#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 +#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L +#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L +#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L +#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L +#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L +#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L +//JPEG_LMI_DROP +#define JPEG_LMI_DROP__JPEG_WR_DROP__SHIFT 0x0 +#define JPEG_LMI_DROP__JRBC_WR_DROP__SHIFT 0x1 +#define JPEG_LMI_DROP__JPEG_RD_DROP__SHIFT 0x2 +#define JPEG_LMI_DROP__JRBC_RD_DROP__SHIFT 0x3 +#define JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP__SHIFT 0x4 +#define JPEG_LMI_DROP__JPEG_WR_DROP_MASK 0x00000001L +#define JPEG_LMI_DROP__JRBC_WR_DROP_MASK 0x00000002L +#define JPEG_LMI_DROP__JPEG_RD_DROP_MASK 0x00000004L +#define JPEG_LMI_DROP__JRBC_RD_DROP_MASK 0x00000008L +#define JPEG_LMI_DROP__JPEG_ATOMIC_WR_DROP_MASK 0x00000010L +//UVD_LMI_JRBC_IB_VMID +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L +#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_LMI_JRBC_RB_VMID +#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 +#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 +#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL +#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L +#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L +//UVD_LMI_JPEG_VMID +#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 +#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 +#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 +#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL +#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L +#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L +//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_PREEMPT_VMID +#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 +#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL +//UVD_JMI_DEC_SWAP_CNTL +#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa +#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 +#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L +#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L +#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L +#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L +#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L +//UVD_JMI_ATOMIC_CNTL +#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en__SHIFT 0x0 +#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst__SHIFT 0x1 +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop__SHIFT 0x5 +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en__SHIFT 0x6 +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG__SHIFT 0x7 +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE__SHIFT 0xb +#define UVD_JMI_ATOMIC_CNTL__atomic_arb_wait_en_MASK 0x00000001L +#define UVD_JMI_ATOMIC_CNTL__atomic_max_burst_MASK 0x0000001EL +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_drop_MASK 0x00000020L +#define UVD_JMI_ATOMIC_CNTL__atomic_wr_clamping_en_MASK 0x00000040L +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_WR_URG_MASK 0x00000780L +#define UVD_JMI_ATOMIC_CNTL__ATOMIC_SW_GATE_MASK 0x00000800L +//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_JMI_ATOMIC_USER0_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_READ_64BIT_BAR_LOW +#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_JMI_ATOMIC_CNTL2 +#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap__SHIFT 0x10 +#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP__SHIFT 0x18 +#define UVD_JMI_ATOMIC_CNTL2__atomic_uvd_swap_MASK 0x00FF0000L +#define UVD_JMI_ATOMIC_CNTL2__ATOMIC_MC_SWAP_MASK 0xFF000000L + + +// addressBlock: uvd_uvd_dct_decoder_rbc_2_uvd_jrbc_dec +//UVD_JRBC3_UVD_JRBC_RB_WPTR +#define UVD_JRBC3_UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L +//UVD_JRBC3_UVD_JRBC_RB_CNTL +#define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 +#define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L +#define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L +#define UVD_JRBC3_UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L +//UVD_JRBC3_UVD_JRBC_IB_SIZE +#define UVD_JRBC3_UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC3_UVD_JRBC_URGENT_CNTL +#define UVD_JRBC3_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L +//UVD_JRBC3_UVD_JRBC_RB_REF_DATA +#define UVD_JRBC3_UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC3_UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC3_UVD_JRBC_SOFT_RESET +#define UVD_JRBC3_UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 +#define UVD_JRBC3_UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L +#define UVD_JRBC3_UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L +//UVD_JRBC3_UVD_JRBC_STATUS +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa +#define UVD_JRBC3_UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc +#define UVD_JRBC3_UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 +#define UVD_JRBC3_UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L +#define UVD_JRBC3_UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L +#define UVD_JRBC3_UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L +#define UVD_JRBC3_UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L +#define UVD_JRBC3_UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L +#define UVD_JRBC3_UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L +//UVD_JRBC3_UVD_JRBC_RB_RPTR +#define UVD_JRBC3_UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L +//UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS +#define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC3_UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS +#define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 +#define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 +#define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL +#define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L +#define UVD_JRBC3_UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L +//UVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE +#define UVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L +//UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L +#define UVD_JRBC3_UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L +//UVD_JRBC3_UVD_JRBC_IB_REF_DATA +#define UVD_JRBC3_UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL +//UVD_JRBC3_UVD_JPEG_PREEMPT_CMD +#define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L +#define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L +#define UVD_JRBC3_UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L +//UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL +//UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 +#define UVD_JRBC3_UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL +//UVD_JRBC3_UVD_JRBC_RB_SIZE +#define UVD_JRBC3_UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 +#define UVD_JRBC3_UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L +//UVD_JRBC3_UVD_JRBC_SCRATCH0 +#define UVD_JRBC3_UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 +#define UVD_JRBC3_UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_uvd_jmi_common_dec +//UVD_JADP_MCIF_URGENT_CTRL +#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK__SHIFT 0x0 +#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK__SHIFT 0x6 +#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER__SHIFT 0xb +#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP__SHIFT 0x11 +#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP__SHIFT 0x15 +#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN__SHIFT 0x19 +#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN__SHIFT 0x1a +#define UVD_JADP_MCIF_URGENT_CTRL__WR_WATERMARK_MASK 0x0000003FL +#define UVD_JADP_MCIF_URGENT_CTRL__RD_WATERMARK_MASK 0x000007C0L +#define UVD_JADP_MCIF_URGENT_CTRL__WR_RD_URGENT_TIMER_MASK 0x0001F800L +#define UVD_JADP_MCIF_URGENT_CTRL__WR_URGENT_PROG_STEP_MASK 0x001E0000L +#define UVD_JADP_MCIF_URGENT_CTRL__RD_URGENT_PROG_STEP_MASK 0x01E00000L +#define UVD_JADP_MCIF_URGENT_CTRL__WR_QOS_EN_MASK 0x02000000L +#define UVD_JADP_MCIF_URGENT_CTRL__RD_QOS_EN_MASK 0x04000000L +//UVD_JMI_URGENT_CTRL +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x4 +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x10 +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0x14 +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x000000F0L +#define UVD_JMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00010000L +#define UVD_JMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00F00000L +//UVD_JMI_CTRL +#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 +#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 +#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 +#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 +#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 +#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L +#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L +#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L +#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L +#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L +//JPEG_MEMCHECK_CLAMPING_CNTL +#define JPEG_MEMCHECK_CLAMPING_CNTL__CLAMP_TO_SAFE_ADDR_EN__SHIFT 0x0 +#define JPEG_MEMCHECK_CLAMPING_CNTL__CLAMP_TO_SAFE_ADDR_EN_MASK 0x00000001L +//JPEG_MEMCHECK_SAFE_ADDR +#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR__SHIFT 0x0 +#define JPEG_MEMCHECK_SAFE_ADDR__MEMCHECK_SAFE_ADDR_MASK 0xFFFFFFFFL +//JPEG_MEMCHECK_SAFE_ADDR_64BIT +#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT__SHIFT 0x0 +#define JPEG_MEMCHECK_SAFE_ADDR_64BIT__MEMCHECK_SAFE_ADDR_64BIT_MASK 0xFFFFFFFFL +//UVD_JMI_LAT_CTRL +#define UVD_JMI_LAT_CTRL__SCALE__SHIFT 0x0 +#define UVD_JMI_LAT_CTRL__MAX_START__SHIFT 0x8 +#define UVD_JMI_LAT_CTRL__MIN_START__SHIFT 0x9 +#define UVD_JMI_LAT_CTRL__AVG_START__SHIFT 0xa +#define UVD_JMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb +#define UVD_JMI_LAT_CTRL__SKIP__SHIFT 0x10 +#define UVD_JMI_LAT_CTRL__SCALE_MASK 0x000000FFL +#define UVD_JMI_LAT_CTRL__MAX_START_MASK 0x00000100L +#define UVD_JMI_LAT_CTRL__MIN_START_MASK 0x00000200L +#define UVD_JMI_LAT_CTRL__AVG_START_MASK 0x00000400L +#define UVD_JMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L +#define UVD_JMI_LAT_CTRL__SKIP_MASK 0x000F0000L +//UVD_JMI_LAT_CNTR +#define UVD_JMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 +#define UVD_JMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 +#define UVD_JMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL +#define UVD_JMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L +//UVD_JMI_AVG_LAT_CNTR +#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 +#define UVD_JMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L +#define UVD_JMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L +//UVD_JMI_PERFMON_CTRL +#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 +#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 +#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L +#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L +//UVD_JMI_PERFMON_COUNT_LO +#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 +#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL +//UVD_JMI_PERFMON_COUNT_HI +#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 +#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL +//UVD_JMI_CLEAN_STATUS +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN__SHIFT 0x0 +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW__SHIFT 0x1 +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN__SHIFT 0x2 +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW__SHIFT 0x3 +#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING__SHIFT 0x4 +#define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_READ_CLEAN__SHIFT 0x8 +#define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_WRITE_CLEAN__SHIFT 0x10 +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_MASK 0x00000001L +#define UVD_JMI_CLEAN_STATUS__LMI_READ_CLEAN_RAW_MASK 0x00000002L +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_MASK 0x00000004L +#define UVD_JMI_CLEAN_STATUS__LMI_WRITE_CLEAN_RAW_MASK 0x00000008L +#define UVD_JMI_CLEAN_STATUS__MC_WRITE_PENDING_MASK 0x00000010L +#define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_READ_CLEAN_MASK 0x00000100L +#define UVD_JMI_CLEAN_STATUS__DJPEG_CORE0_WRITE_CLEAN_MASK 0x00010000L +//UVD_JMI_CNTL +#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 +#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 +#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L +#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L + + +// addressBlock: uvd_uvd_jpeg_common_dec +//JPEG_SOFT_RESET_STATUS +#define JPEG_SOFT_RESET_STATUS__JPEG0_DEC_RESET_STATUS__SHIFT 0x0 +#define JPEG_SOFT_RESET_STATUS__DJRBC0_RESET_STATUS__SHIFT 0x8 +#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x11 +#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x12 +#define JPEG_SOFT_RESET_STATUS__DCT_DECODER_0_RBC_RESET_STATUS__SHIFT 0x13 +#define JPEG_SOFT_RESET_STATUS__DCT_DECODER_1_RBC_RESET_STATUS__SHIFT 0x14 +#define JPEG_SOFT_RESET_STATUS__DCT_DECODER_2_RBC_RESET_STATUS__SHIFT 0x15 +#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x18 +#define JPEG_SOFT_RESET_STATUS__JPEG0_DEC_RESET_STATUS_MASK 0x00000001L +#define JPEG_SOFT_RESET_STATUS__DJRBC0_RESET_STATUS_MASK 0x00000100L +#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00020000L +#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00040000L +#define JPEG_SOFT_RESET_STATUS__DCT_DECODER_0_RBC_RESET_STATUS_MASK 0x00080000L +#define JPEG_SOFT_RESET_STATUS__DCT_DECODER_1_RBC_RESET_STATUS_MASK 0x00100000L +#define JPEG_SOFT_RESET_STATUS__DCT_DECODER_2_RBC_RESET_STATUS_MASK 0x00200000L +#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x01000000L +//JPEG_SYS_INT_EN +#define JPEG_SYS_INT_EN__DJPEG0_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_EN__DJPEG1_CORE__SHIFT 0x1 +#define JPEG_SYS_INT_EN__DJPEG2_CORE__SHIFT 0x2 +#define JPEG_SYS_INT_EN__DJPEG3_CORE__SHIFT 0x3 +#define JPEG_SYS_INT_EN__DJRBC0__SHIFT 0x8 +#define JPEG_SYS_INT_EN__DJRBC1__SHIFT 0x9 +#define JPEG_SYS_INT_EN__DJRBC2__SHIFT 0xa +#define JPEG_SYS_INT_EN__DJRBC3__SHIFT 0xb +#define JPEG_SYS_INT_EN__DJPEG0_PF_RPT__SHIFT 0x10 +#define JPEG_SYS_INT_EN__DJPEG1_PF_RPT__SHIFT 0x11 +#define JPEG_SYS_INT_EN__DJPEG2_PF_RPT__SHIFT 0x12 +#define JPEG_SYS_INT_EN__DJPEG3_PF_RPT__SHIFT 0x13 +#define JPEG_SYS_INT_EN__DJPEG0_RAS_CNTL__SHIFT 0x18 +#define JPEG_SYS_INT_EN__DJPEG0_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_EN__DJPEG1_CORE_MASK 0x00000002L +#define JPEG_SYS_INT_EN__DJPEG2_CORE_MASK 0x00000004L +#define JPEG_SYS_INT_EN__DJPEG3_CORE_MASK 0x00000008L +#define JPEG_SYS_INT_EN__DJRBC0_MASK 0x00000100L +#define JPEG_SYS_INT_EN__DJRBC1_MASK 0x00000200L +#define JPEG_SYS_INT_EN__DJRBC2_MASK 0x00000400L +#define JPEG_SYS_INT_EN__DJRBC3_MASK 0x00000800L +#define JPEG_SYS_INT_EN__DJPEG0_PF_RPT_MASK 0x00010000L +#define JPEG_SYS_INT_EN__DJPEG1_PF_RPT_MASK 0x00020000L +#define JPEG_SYS_INT_EN__DJPEG2_PF_RPT_MASK 0x00040000L +#define JPEG_SYS_INT_EN__DJPEG3_PF_RPT_MASK 0x00080000L +#define JPEG_SYS_INT_EN__DJPEG0_RAS_CNTL_MASK 0x01000000L +//JPEG_SYS_INT_EN1 +#define JPEG_SYS_INT_EN1__EJPEG_PF_RPT__SHIFT 0x0 +#define JPEG_SYS_INT_EN1__EJPEG_CORE__SHIFT 0x1 +#define JPEG_SYS_INT_EN1__EJRBC__SHIFT 0x2 +#define JPEG_SYS_INT_EN1__EJPEG_RAS_CNTL__SHIFT 0x3 +#define JPEG_SYS_INT_EN1__VF0_POISON_INTERRUPT_TO_PF__SHIFT 0x4 +#define JPEG_SYS_INT_EN1__EJPEG_PF_RPT_MASK 0x00000001L +#define JPEG_SYS_INT_EN1__EJPEG_CORE_MASK 0x00000002L +#define JPEG_SYS_INT_EN1__EJRBC_MASK 0x00000004L +#define JPEG_SYS_INT_EN1__EJPEG_RAS_CNTL_MASK 0x00000008L +#define JPEG_SYS_INT_EN1__VF0_POISON_INTERRUPT_TO_PF_MASK 0x00000010L +//JPEG_SYS_INT_STATUS +#define JPEG_SYS_INT_STATUS__DJPEG0_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_STATUS__DJPEG1_CORE__SHIFT 0x1 +#define JPEG_SYS_INT_STATUS__DJPEG2_CORE__SHIFT 0x2 +#define JPEG_SYS_INT_STATUS__DJPEG3_CORE__SHIFT 0x3 +#define JPEG_SYS_INT_STATUS__DJRBC0__SHIFT 0x8 +#define JPEG_SYS_INT_STATUS__DJRBC1__SHIFT 0x9 +#define JPEG_SYS_INT_STATUS__DJRBC2__SHIFT 0xa +#define JPEG_SYS_INT_STATUS__DJRBC3__SHIFT 0xb +#define JPEG_SYS_INT_STATUS__DJPEG0_PF_RPT__SHIFT 0x10 +#define JPEG_SYS_INT_STATUS__DJPEG1_PF_RPT__SHIFT 0x11 +#define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT__SHIFT 0x12 +#define JPEG_SYS_INT_STATUS__DJPEG3_PF_RPT__SHIFT 0x13 +#define JPEG_SYS_INT_STATUS__DJPEG0_RAS_CNTL__SHIFT 0x18 +#define JPEG_SYS_INT_STATUS__DJPEG0_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_STATUS__DJPEG1_CORE_MASK 0x00000002L +#define JPEG_SYS_INT_STATUS__DJPEG2_CORE_MASK 0x00000004L +#define JPEG_SYS_INT_STATUS__DJPEG3_CORE_MASK 0x00000008L +#define JPEG_SYS_INT_STATUS__DJRBC0_MASK 0x00000100L +#define JPEG_SYS_INT_STATUS__DJRBC1_MASK 0x00000200L +#define JPEG_SYS_INT_STATUS__DJRBC2_MASK 0x00000400L +#define JPEG_SYS_INT_STATUS__DJRBC3_MASK 0x00000800L +#define JPEG_SYS_INT_STATUS__DJPEG0_PF_RPT_MASK 0x00010000L +#define JPEG_SYS_INT_STATUS__DJPEG1_PF_RPT_MASK 0x00020000L +#define JPEG_SYS_INT_STATUS__DJPEG2_PF_RPT_MASK 0x00040000L +#define JPEG_SYS_INT_STATUS__DJPEG3_PF_RPT_MASK 0x00080000L +#define JPEG_SYS_INT_STATUS__DJPEG0_RAS_CNTL_MASK 0x01000000L +//JPEG_SYS_INT_STATUS1 +#define JPEG_SYS_INT_STATUS1__EJPEG_PF_RPT__SHIFT 0x0 +#define JPEG_SYS_INT_STATUS1__EJPEG_CORE__SHIFT 0x1 +#define JPEG_SYS_INT_STATUS1__EJRBC__SHIFT 0x2 +#define JPEG_SYS_INT_STATUS1__EJPEG_RAS_CNTL__SHIFT 0x3 +#define JPEG_SYS_INT_STATUS1__EJPEG_PF_RPT_MASK 0x00000001L +#define JPEG_SYS_INT_STATUS1__EJPEG_CORE_MASK 0x00000002L +#define JPEG_SYS_INT_STATUS1__EJRBC_MASK 0x00000004L +#define JPEG_SYS_INT_STATUS1__EJPEG_RAS_CNTL_MASK 0x00000008L +//JPEG_SYS_INT_ACK +#define JPEG_SYS_INT_ACK__DJPEG0_CORE__SHIFT 0x0 +#define JPEG_SYS_INT_ACK__DJPEG1_CORE__SHIFT 0x1 +#define JPEG_SYS_INT_ACK__DJPEG2_CORE__SHIFT 0x2 +#define JPEG_SYS_INT_ACK__DJPEG3_CORE__SHIFT 0x3 +#define JPEG_SYS_INT_ACK__DJRBC0__SHIFT 0x8 +#define JPEG_SYS_INT_ACK__DJRBC1__SHIFT 0x9 +#define JPEG_SYS_INT_ACK__DJRBC2__SHIFT 0xa +#define JPEG_SYS_INT_ACK__DJRBC3__SHIFT 0xb +#define JPEG_SYS_INT_ACK__DJPEG0_PF_RPT__SHIFT 0x10 +#define JPEG_SYS_INT_ACK__DJPEG1_PF_RPT__SHIFT 0x11 +#define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT__SHIFT 0x12 +#define JPEG_SYS_INT_ACK__DJPEG3_PF_RPT__SHIFT 0x13 +#define JPEG_SYS_INT_ACK__DJPEG0_RAS_CNTL__SHIFT 0x18 +#define JPEG_SYS_INT_ACK__DJPEG0_CORE_MASK 0x00000001L +#define JPEG_SYS_INT_ACK__DJPEG1_CORE_MASK 0x00000002L +#define JPEG_SYS_INT_ACK__DJPEG2_CORE_MASK 0x00000004L +#define JPEG_SYS_INT_ACK__DJPEG3_CORE_MASK 0x00000008L +#define JPEG_SYS_INT_ACK__DJRBC0_MASK 0x00000100L +#define JPEG_SYS_INT_ACK__DJRBC1_MASK 0x00000200L +#define JPEG_SYS_INT_ACK__DJRBC2_MASK 0x00000400L +#define JPEG_SYS_INT_ACK__DJRBC3_MASK 0x00000800L +#define JPEG_SYS_INT_ACK__DJPEG0_PF_RPT_MASK 0x00010000L +#define JPEG_SYS_INT_ACK__DJPEG1_PF_RPT_MASK 0x00020000L +#define JPEG_SYS_INT_ACK__DJPEG2_PF_RPT_MASK 0x00040000L +#define JPEG_SYS_INT_ACK__DJPEG3_PF_RPT_MASK 0x00080000L +#define JPEG_SYS_INT_ACK__DJPEG0_RAS_CNTL_MASK 0x01000000L +//JPEG_SYS_INT_ACK1 +#define JPEG_SYS_INT_ACK1__EJPEG_PF_RPT__SHIFT 0x0 +#define JPEG_SYS_INT_ACK1__EJPEG_CORE__SHIFT 0x1 +#define JPEG_SYS_INT_ACK1__EJRBC__SHIFT 0x2 +#define JPEG_SYS_INT_ACK1__EJPEG_RAS_CNTL__SHIFT 0x3 +#define JPEG_SYS_INT_ACK1__EJPEG_PF_RPT_MASK 0x00000001L +#define JPEG_SYS_INT_ACK1__EJPEG_CORE_MASK 0x00000002L +#define JPEG_SYS_INT_ACK1__EJRBC_MASK 0x00000004L +#define JPEG_SYS_INT_ACK1__EJPEG_RAS_CNTL_MASK 0x00000008L +//JPEG_MEMCHECK_SYS_INT_EN +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_RD_ERR_EN__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_RD_ERR_EN__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_RD_ERR_EN__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_RD_ERR_EN__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH0_RD_ERR_EN__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_WR_ERR_EN__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_WR_ERR_EN__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_WR_ERR_EN__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_WR_ERR_EN__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF0_WR_ERR_EN__SHIFT 0x18 +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF1_WR_ERR_EN__SHIFT 0x19 +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF2_WR_ERR_EN__SHIFT 0x1a +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF3_WR_ERR_EN__SHIFT 0x1b +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_RD_ERR_EN_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_RD_ERR_EN_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_RD_ERR_EN_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_RD_ERR_EN_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_EN__BSFETCH0_RD_ERR_EN_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC0_WR_ERR_EN_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC1_WR_ERR_EN_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC2_WR_ERR_EN_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_EN__DJRBC3_WR_ERR_EN_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF0_WR_ERR_EN_MASK 0x01000000L +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF1_WR_ERR_EN_MASK 0x02000000L +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF2_WR_ERR_EN_MASK 0x04000000L +#define JPEG_MEMCHECK_SYS_INT_EN__OBUF3_WR_ERR_EN_MASK 0x08000000L +//JPEG_MEMCHECK_SYS_INT_EN1 +#define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_RD_ERR_EN__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_EN1__PELFETCH_RD_ERR_EN__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_RD_ERR_EN__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_WR_ERR_EN__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_EN1__BS_WR_ERR_EN__SHIFT 0x4 +#define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_WR_ERR_EN__SHIFT 0x5 +#define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_RD_ERR_EN_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_EN1__PELFETCH_RD_ERR_EN_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_RD_ERR_EN_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_EN1__EJRBC_WR_ERR_EN_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_EN1__BS_WR_ERR_EN_MASK 0x00000010L +#define JPEG_MEMCHECK_SYS_INT_EN1__SCALAR_WR_ERR_EN_MASK 0x00000020L +//JPEG_MEMCHECK_SYS_INT_STAT +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_LO_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_HI_ERR__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_HI_ERR__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_HI_ERR__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_HI_ERR__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_LO_ERR__SHIFT 0x18 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_LO_ERR__SHIFT 0x19 +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_LO_ERR__SHIFT 0x1a +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_LO_ERR__SHIFT 0x1b +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_STAT__BSFETCH0_RD_LO_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_HI_ERR_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_HI_ERR_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_HI_ERR_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_HI_ERR_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF0_WR_LO_ERR_MASK 0x01000000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF1_WR_LO_ERR_MASK 0x02000000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF2_WR_LO_ERR_MASK 0x04000000L +#define JPEG_MEMCHECK_SYS_INT_STAT__OBUF3_WR_LO_ERR_MASK 0x08000000L +//JPEG_MEMCHECK_SYS_INT_STAT1 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_HI_ERR__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_HI_ERR__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_HI_ERR__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_LO_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_LO_ERR__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_LO_ERR__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_LO_ERR__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_HI_ERR__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_HI_ERR__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_HI_ERR__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_HI_ERR__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_LO_ERR__SHIFT 0x18 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_LO_ERR__SHIFT 0x19 +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_LO_ERR__SHIFT 0x1a +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_LO_ERR__SHIFT 0x1b +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_HI_ERR_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_HI_ERR_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_HI_ERR_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_RD_LO_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_RD_LO_ERR_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_RD_LO_ERR_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_RD_LO_ERR_MASK 0x00000800L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_HI_ERR_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_HI_ERR_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_HI_ERR_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_HI_ERR_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC0_WR_LO_ERR_MASK 0x01000000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC1_WR_LO_ERR_MASK 0x02000000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC2_WR_LO_ERR_MASK 0x04000000L +#define JPEG_MEMCHECK_SYS_INT_STAT1__DJRBC3_WR_LO_ERR_MASK 0x08000000L +//JPEG_MEMCHECK_SYS_INT_STAT2 +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_LO_ERR__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_HI_ERR__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_LO_ERR__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_HI_ERR__SHIFT 0x4 +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_LO_ERR__SHIFT 0x5 +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_HI_ERR__SHIFT 0x6 +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_LO_ERR__SHIFT 0x7 +#define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_HI_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_LO_ERR__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_LO_ERR__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_RD_LO_ERR_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_HI_ERR_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_STAT2__PELFETCH_RD_LO_ERR_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_HI_ERR_MASK 0x00000010L +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_RD_LO_ERR_MASK 0x00000020L +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_HI_ERR_MASK 0x00000040L +#define JPEG_MEMCHECK_SYS_INT_STAT2__EJRBC_WR_LO_ERR_MASK 0x00000080L +#define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_HI_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_STAT2__BS_WR_LO_ERR_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_HI_ERR_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_STAT2__SCALAR_WR_LO_ERR_MASK 0x00000800L +//JPEG_MEMCHECK_SYS_INT_ACK +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_LO_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_HI_ERR__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_HI_ERR__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_HI_ERR__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_HI_ERR__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_LO_ERR__SHIFT 0x18 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_LO_ERR__SHIFT 0x19 +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_LO_ERR__SHIFT 0x1a +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_LO_ERR__SHIFT 0x1b +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_ACK__BSFETCH0_RD_LO_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_HI_ERR_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_HI_ERR_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_HI_ERR_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_HI_ERR_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF0_WR_LO_ERR_MASK 0x01000000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF1_WR_LO_ERR_MASK 0x02000000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF2_WR_LO_ERR_MASK 0x04000000L +#define JPEG_MEMCHECK_SYS_INT_ACK__OBUF3_WR_LO_ERR_MASK 0x08000000L +//JPEG_MEMCHECK_SYS_INT_ACK1 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_HI_ERR__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_HI_ERR__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_HI_ERR__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_LO_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_LO_ERR__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_LO_ERR__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_LO_ERR__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_HI_ERR__SHIFT 0x10 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_HI_ERR__SHIFT 0x11 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_HI_ERR__SHIFT 0x12 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_HI_ERR__SHIFT 0x13 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_LO_ERR__SHIFT 0x18 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_LO_ERR__SHIFT 0x19 +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_LO_ERR__SHIFT 0x1a +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_LO_ERR__SHIFT 0x1b +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_HI_ERR_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_HI_ERR_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_HI_ERR_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_RD_LO_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_RD_LO_ERR_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_RD_LO_ERR_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_RD_LO_ERR_MASK 0x00000800L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_HI_ERR_MASK 0x00010000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_HI_ERR_MASK 0x00020000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_HI_ERR_MASK 0x00040000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_HI_ERR_MASK 0x00080000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC0_WR_LO_ERR_MASK 0x01000000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC1_WR_LO_ERR_MASK 0x02000000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC2_WR_LO_ERR_MASK 0x04000000L +#define JPEG_MEMCHECK_SYS_INT_ACK1__DJRBC3_WR_LO_ERR_MASK 0x08000000L +//JPEG_MEMCHECK_SYS_INT_ACK2 +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_HI_ERR__SHIFT 0x0 +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_LO_ERR__SHIFT 0x1 +#define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_HI_ERR__SHIFT 0x2 +#define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_LO_ERR__SHIFT 0x3 +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_HI_ERR__SHIFT 0x4 +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_LO_ERR__SHIFT 0x5 +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_HI_ERR__SHIFT 0x6 +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_LO_ERR__SHIFT 0x7 +#define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_HI_ERR__SHIFT 0x8 +#define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_LO_ERR__SHIFT 0x9 +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR__SHIFT 0xa +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_LO_ERR__SHIFT 0xb +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_HI_ERR_MASK 0x00000001L +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_RD_LO_ERR_MASK 0x00000002L +#define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_HI_ERR_MASK 0x00000004L +#define JPEG_MEMCHECK_SYS_INT_ACK2__PELFETCH_RD_LO_ERR_MASK 0x00000008L +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_HI_ERR_MASK 0x00000010L +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_RD_LO_ERR_MASK 0x00000020L +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_HI_ERR_MASK 0x00000040L +#define JPEG_MEMCHECK_SYS_INT_ACK2__EJRBC_WR_LO_ERR_MASK 0x00000080L +#define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_HI_ERR_MASK 0x00000100L +#define JPEG_MEMCHECK_SYS_INT_ACK2__BS_WR_LO_ERR_MASK 0x00000200L +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_HI_ERR_MASK 0x00000400L +#define JPEG_MEMCHECK_SYS_INT_ACK2__SCALAR_WR_LO_ERR_MASK 0x00000800L +//JPEG_MASTINT_EN +#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//JPEG_IH_CTRL +#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 +#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 +#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 +#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 +#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 +#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 +#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L +#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L +#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L +#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L +#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L +#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L +//JRBBM_ARB_CTRL +#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x0 +#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 +#define JRBBM_ARB_CTRL__DJRBC0_DROP__SHIFT 0x2 +#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000001L +#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L +#define JRBBM_ARB_CTRL__DJRBC0_DROP_MASK 0x00000004L + + +// addressBlock: uvd_uvd_jpeg_common_sclk_dec +//JPEG_CGC_GATE +#define JPEG_CGC_GATE__JPEG0_DEC__SHIFT 0x0 +#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x8 +#define JPEG_CGC_GATE__JMCIF__SHIFT 0x9 +#define JPEG_CGC_GATE__JRBBM__SHIFT 0xa +#define JPEG_CGC_GATE__JPEG0_DEC_MASK 0x00000001L +#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000100L +#define JPEG_CGC_GATE__JMCIF_MASK 0x00000200L +#define JPEG_CGC_GATE__JRBBM_MASK 0x00000400L +//JPEG_CGC_CTRL +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 +#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 +#define JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT 0x10 +#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x18 +#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x19 +#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x1a +#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L +#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL +#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x00001FE0L +#define JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK 0x00010000L +#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x01000000L +#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x02000000L +#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x04000000L +//JPEG_CGC_STATUS +#define JPEG_CGC_STATUS__JPEG0_DEC_VCLK_ACTIVE__SHIFT 0x0 +#define JPEG_CGC_STATUS__JPEG0_DEC_SCLK_ACTIVE__SHIFT 0x1 +#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x10 +#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x11 +#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x12 +#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x13 +#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x14 +#define JPEG_CGC_STATUS__JPEG0_DEC_VCLK_ACTIVE_MASK 0x00000001L +#define JPEG_CGC_STATUS__JPEG0_DEC_SCLK_ACTIVE_MASK 0x00000002L +#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00010000L +#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00020000L +#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00040000L +#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00080000L +#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00100000L +//JPEG_COMN_CGC_MEM_CTRL +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN__SHIFT 0x3 +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L +#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_SW_EN_MASK 0x00000008L +//JPEG_DEC_CGC_MEM_CTRL +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_EN__SHIFT 0x0 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_DS_EN__SHIFT 0x1 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_SD_EN__SHIFT 0x2 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_SW_EN__SHIFT 0x3 +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_EN_MASK 0x00000001L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_DS_EN_MASK 0x00000002L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_SD_EN_MASK 0x00000004L +#define JPEG_DEC_CGC_MEM_CTRL__JPEG0_DEC_LS_SW_EN_MASK 0x00000008L +//JPEG_ENC_CGC_MEM_CTRL +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN__SHIFT 0x3 +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L +#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_SW_EN_MASK 0x00000008L +//JPEG_PERF_BANK_CONF +#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 +#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 +#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 +#define JPEG_PERF_BANK_CONF__CORE_SEL__SHIFT 0x15 +#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL +#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L +#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L +#define JPEG_PERF_BANK_CONF__CORE_SEL_MASK 0x01E00000L +//JPEG_PERF_BANK_EVENT_SEL +#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 +#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 +#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 +#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 +#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL +#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L +#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L +#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L +//JPEG_PERF_BANK_COUNT0 +#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT1 +#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT2 +#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL +//JPEG_PERF_BANK_COUNT3 +#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 +#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_vcn_umsch_dec +//VCN_UMSCH_MES_CNTL +#define VCN_UMSCH_MES_CNTL__PIPE_ID__SHIFT 0x0 +#define VCN_UMSCH_MES_CNTL__PerfPipeSel__SHIFT 0x2 +#define VCN_UMSCH_MES_CNTL__RamClkGatingDisable__SHIFT 0x4 +#define VCN_UMSCH_MES_CNTL__InterruptChickenBit__SHIFT 0x5 +#define VCN_UMSCH_MES_CNTL__CpTcOneCycleWrDis__SHIFT 0x6 +#define VCN_UMSCH_MES_CNTL__PIPE_ID_MASK 0x00000003L +#define VCN_UMSCH_MES_CNTL__PerfPipeSel_MASK 0x0000000CL +#define VCN_UMSCH_MES_CNTL__RamClkGatingDisable_MASK 0x00000010L +#define VCN_UMSCH_MES_CNTL__InterruptChickenBit_MASK 0x00000020L +#define VCN_UMSCH_MES_CNTL__CpTcOneCycleWrDis_MASK 0x00000040L +//UMSCH_CTL +#define UMSCH_CTL__P_RESET__SHIFT 0x0 +#define UMSCH_CTL__UTCL2_CLIENT_ID__SHIFT 0x1 +#define UMSCH_CTL__UMSCH_BUSY__SHIFT 0xa +#define UMSCH_CTL__IllegalRegReadAckLatency__SHIFT 0xd +#define UMSCH_CTL__P_RESET_MASK 0x00000001L +#define UMSCH_CTL__UTCL2_CLIENT_ID_MASK 0x000003FEL +#define UMSCH_CTL__UMSCH_BUSY_MASK 0x00000400L +#define UMSCH_CTL__IllegalRegReadAckLatency_MASK 0x0000E000L +//UMSCH_CTL2 +#define UMSCH_CTL2__Spare__SHIFT 0x0 +#define UMSCH_CTL2__Spare_MASK 0xFFFFFFFFL +//VCN_UMSCH_AGDB_WPTR0 +#define VCN_UMSCH_AGDB_WPTR0__WPTR__SHIFT 0x0 +#define VCN_UMSCH_AGDB_WPTR0__WPTR_MASK 0xFFFFFFFFL +//VCN_UMSCH_AGDB_WPTR1 +#define VCN_UMSCH_AGDB_WPTR1__WPTR__SHIFT 0x0 +#define VCN_UMSCH_AGDB_WPTR1__WPTR_MASK 0xFFFFFFFFL +//VCN_UMSCH_AGDB_WPTR2 +#define VCN_UMSCH_AGDB_WPTR2__WPTR__SHIFT 0x0 +#define VCN_UMSCH_AGDB_WPTR2__WPTR_MASK 0xFFFFFFFFL +//VCN_UMSCH_AGDB_WPTR3 +#define VCN_UMSCH_AGDB_WPTR3__WPTR__SHIFT 0x0 +#define VCN_UMSCH_AGDB_WPTR3__WPTR_MASK 0xFFFFFFFFL +//VCN_UMSCH_AGDB_WPTR4 +#define VCN_UMSCH_AGDB_WPTR4__WPTR__SHIFT 0x0 +#define VCN_UMSCH_AGDB_WPTR4__WPTR_MASK 0xFFFFFFFFL +//VCN_UMSCH_AGDB_WPTR5 +#define VCN_UMSCH_AGDB_WPTR5__WPTR__SHIFT 0x0 +#define VCN_UMSCH_AGDB_WPTR5__WPTR_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX0 +#define VCN_UMSCH_MAILBOX0__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX0__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX_RESP0 +#define VCN_UMSCH_MAILBOX_RESP0__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX_RESP0__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX1 +#define VCN_UMSCH_MAILBOX1__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX1__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX_RESP1 +#define VCN_UMSCH_MAILBOX_RESP1__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX_RESP1__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX2 +#define VCN_UMSCH_MAILBOX2__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX2__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX_RESP2 +#define VCN_UMSCH_MAILBOX_RESP2__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX_RESP2__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX3 +#define VCN_UMSCH_MAILBOX3__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX3__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MAILBOX_RESP3 +#define VCN_UMSCH_MAILBOX_RESP3__DATA__SHIFT 0x0 +#define VCN_UMSCH_MAILBOX_RESP3__DATA_MASK 0xFFFFFFFFL +//VCN_UMSCH_MES_UTCL1_CNTL +#define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY__SHIFT 0x0 +#define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop__SHIFT 0x14 +#define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode__SHIFT 0x15 +#define VCN_UMSCH_MES_UTCL1_CNTL__DropMode__SHIFT 0x16 +#define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate__SHIFT 0x17 +#define VCN_UMSCH_MES_UTCL1_CNTL__REDO_LATENCY_MASK 0x000FFFFFL +#define VCN_UMSCH_MES_UTCL1_CNTL__ForceSnoop_MASK 0x00100000L +#define VCN_UMSCH_MES_UTCL1_CNTL__FragLimitMode_MASK 0x00200000L +#define VCN_UMSCH_MES_UTCL1_CNTL__DropMode_MASK 0x00400000L +#define VCN_UMSCH_MES_UTCL1_CNTL__Invalidate_MASK 0x00800000L +//VCN_UMSCH_MES_BUSY +#define VCN_UMSCH_MES_BUSY__MesScratchRamBusy__SHIFT 0x0 +#define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy__SHIFT 0x1 +#define VCN_UMSCH_MES_BUSY__MesDataCacheBusy__SHIFT 0x2 +#define VCN_UMSCH_MES_BUSY__MesBusy__SHIFT 0x3 +#define VCN_UMSCH_MES_BUSY__MesLoadBusy__SHIFT 0x4 +#define VCN_UMSCH_MES_BUSY__MesMutexBusy__SHIFT 0x5 +#define VCN_UMSCH_MES_BUSY__MesThreadBusy__SHIFT 0x6 +#define VCN_UMSCH_MES_BUSY__MesMessageBusy__SHIFT 0x8 +#define VCN_UMSCH_MES_BUSY__MesTcBusy__SHIFT 0xa +#define VCN_UMSCH_MES_BUSY__MesDmaPending__SHIFT 0xc +#define VCN_UMSCH_MES_BUSY__MesScratchRamBusy_MASK 0x00000001L +#define VCN_UMSCH_MES_BUSY__MesInstrCacheBusy_MASK 0x00000002L +#define VCN_UMSCH_MES_BUSY__MesDataCacheBusy_MASK 0x00000004L +#define VCN_UMSCH_MES_BUSY__MesBusy_MASK 0x00000008L +#define VCN_UMSCH_MES_BUSY__MesLoadBusy_MASK 0x00000010L +#define VCN_UMSCH_MES_BUSY__MesMutexBusy_MASK 0x00000020L +#define VCN_UMSCH_MES_BUSY__MesThreadBusy_MASK 0x000000C0L +#define VCN_UMSCH_MES_BUSY__MesMessageBusy_MASK 0x00000300L +#define VCN_UMSCH_MES_BUSY__MesTcBusy_MASK 0x00000C00L +#define VCN_UMSCH_MES_BUSY__MesDmaPending_MASK 0x00003000L +//VCN_UMSCH_RB_BASE_LO +#define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 +#define VCN_UMSCH_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L +//VCN_UMSCH_RB_BASE_HI +#define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define VCN_UMSCH_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL +//VCN_UMSCH_RB_SIZE +#define VCN_UMSCH_RB_SIZE__WPTR__SHIFT 0x4 +#define VCN_UMSCH_RB_SIZE__WPTR_MASK 0x007FFFF0L +//VCN_UMSCH_RB_RPTR +#define VCN_UMSCH_RB_RPTR__WPTR__SHIFT 0x4 +#define VCN_UMSCH_RB_RPTR__WPTR_MASK 0x007FFFF0L +//VCN_UMSCH_RB_WPTR +#define VCN_UMSCH_RB_WPTR__WPTR__SHIFT 0x4 +#define VCN_UMSCH_RB_WPTR__WPTR_MASK 0x007FFFF0L +//VCN_UMSCH_MASTINT_EN +#define VCN_UMSCH_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 +#define VCN_UMSCH_MASTINT_EN__SYS_EN__SHIFT 0x2 +#define VCN_UMSCH_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 +#define VCN_UMSCH_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L +#define VCN_UMSCH_MASTINT_EN__SYS_EN_MASK 0x00000004L +#define VCN_UMSCH_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L +//VCN_UMSCH_IH_CTRL +#define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 +#define VCN_UMSCH_IH_CTRL__IH_STALL_EN__SHIFT 0x1 +#define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 +#define VCN_UMSCH_IH_CTRL__IH_VMID__SHIFT 0x3 +#define VCN_UMSCH_IH_CTRL__IH_USER_DATA__SHIFT 0x7 +#define VCN_UMSCH_IH_CTRL__IH_RINGID__SHIFT 0x13 +#define VCN_UMSCH_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L +#define VCN_UMSCH_IH_CTRL__IH_STALL_EN_MASK 0x00000002L +#define VCN_UMSCH_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L +#define VCN_UMSCH_IH_CTRL__IH_VMID_MASK 0x00000078L +#define VCN_UMSCH_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L +#define VCN_UMSCH_IH_CTRL__IH_RINGID_MASK 0x07F80000L +//VCN_UMSCH_SYS_INT_EN +#define VCN_UMSCH_SYS_INT_EN__INT0__SHIFT 0x0 +#define VCN_UMSCH_SYS_INT_EN__INT1__SHIFT 0x1 +#define VCN_UMSCH_SYS_INT_EN__INT2__SHIFT 0x2 +#define VCN_UMSCH_SYS_INT_EN__INT3__SHIFT 0x3 +#define VCN_UMSCH_SYS_INT_EN__INT4__SHIFT 0x4 +#define VCN_UMSCH_SYS_INT_EN__INT5__SHIFT 0x5 +#define VCN_UMSCH_SYS_INT_EN__INT6__SHIFT 0x6 +#define VCN_UMSCH_SYS_INT_EN__INT7__SHIFT 0x7 +#define VCN_UMSCH_SYS_INT_EN__INT0_MASK 0x00000001L +#define VCN_UMSCH_SYS_INT_EN__INT1_MASK 0x00000002L +#define VCN_UMSCH_SYS_INT_EN__INT2_MASK 0x00000004L +#define VCN_UMSCH_SYS_INT_EN__INT3_MASK 0x00000008L +#define VCN_UMSCH_SYS_INT_EN__INT4_MASK 0x00000010L +#define VCN_UMSCH_SYS_INT_EN__INT5_MASK 0x00000020L +#define VCN_UMSCH_SYS_INT_EN__INT6_MASK 0x00000040L +#define VCN_UMSCH_SYS_INT_EN__INT7_MASK 0x00000080L +//VCN_UMSCH_SYS_INT_STATUS +#define VCN_UMSCH_SYS_INT_STATUS__INT0__SHIFT 0x0 +#define VCN_UMSCH_SYS_INT_STATUS__INT1__SHIFT 0x1 +#define VCN_UMSCH_SYS_INT_STATUS__INT2__SHIFT 0x2 +#define VCN_UMSCH_SYS_INT_STATUS__INT3__SHIFT 0x3 +#define VCN_UMSCH_SYS_INT_STATUS__INT4__SHIFT 0x4 +#define VCN_UMSCH_SYS_INT_STATUS__INT5__SHIFT 0x5 +#define VCN_UMSCH_SYS_INT_STATUS__INT6__SHIFT 0x6 +#define VCN_UMSCH_SYS_INT_STATUS__INT7__SHIFT 0x7 +#define VCN_UMSCH_SYS_INT_STATUS__INT0_MASK 0x00000001L +#define VCN_UMSCH_SYS_INT_STATUS__INT1_MASK 0x00000002L +#define VCN_UMSCH_SYS_INT_STATUS__INT2_MASK 0x00000004L +#define VCN_UMSCH_SYS_INT_STATUS__INT3_MASK 0x00000008L +#define VCN_UMSCH_SYS_INT_STATUS__INT4_MASK 0x00000010L +#define VCN_UMSCH_SYS_INT_STATUS__INT5_MASK 0x00000020L +#define VCN_UMSCH_SYS_INT_STATUS__INT6_MASK 0x00000040L +#define VCN_UMSCH_SYS_INT_STATUS__INT7_MASK 0x00000080L +//VCN_UMSCH_SYS_INT_ACK +#define VCN_UMSCH_SYS_INT_ACK__INT0__SHIFT 0x0 +#define VCN_UMSCH_SYS_INT_ACK__INT1__SHIFT 0x1 +#define VCN_UMSCH_SYS_INT_ACK__INT2__SHIFT 0x2 +#define VCN_UMSCH_SYS_INT_ACK__INT3__SHIFT 0x3 +#define VCN_UMSCH_SYS_INT_ACK__INT4__SHIFT 0x4 +#define VCN_UMSCH_SYS_INT_ACK__INT5__SHIFT 0x5 +#define VCN_UMSCH_SYS_INT_ACK__INT6__SHIFT 0x6 +#define VCN_UMSCH_SYS_INT_ACK__INT7__SHIFT 0x7 +#define VCN_UMSCH_SYS_INT_ACK__INT0_MASK 0x00000001L +#define VCN_UMSCH_SYS_INT_ACK__INT1_MASK 0x00000002L +#define VCN_UMSCH_SYS_INT_ACK__INT2_MASK 0x00000004L +#define VCN_UMSCH_SYS_INT_ACK__INT3_MASK 0x00000008L +#define VCN_UMSCH_SYS_INT_ACK__INT4_MASK 0x00000010L +#define VCN_UMSCH_SYS_INT_ACK__INT5_MASK 0x00000020L +#define VCN_UMSCH_SYS_INT_ACK__INT6_MASK 0x00000040L +#define VCN_UMSCH_SYS_INT_ACK__INT7_MASK 0x00000080L +//VCN_UMSCH_SYS_INT_SRC +#define VCN_UMSCH_SYS_INT_SRC__INT0__SHIFT 0x0 +#define VCN_UMSCH_SYS_INT_SRC__INT1__SHIFT 0x1 +#define VCN_UMSCH_SYS_INT_SRC__INT2__SHIFT 0x2 +#define VCN_UMSCH_SYS_INT_SRC__INT3__SHIFT 0x3 +#define VCN_UMSCH_SYS_INT_SRC__INT4__SHIFT 0x4 +#define VCN_UMSCH_SYS_INT_SRC__INT5__SHIFT 0x5 +#define VCN_UMSCH_SYS_INT_SRC__INT6__SHIFT 0x6 +#define VCN_UMSCH_SYS_INT_SRC__INT7__SHIFT 0x7 +#define VCN_UMSCH_SYS_INT_SRC__INT0_MASK 0x00000001L +#define VCN_UMSCH_SYS_INT_SRC__INT1_MASK 0x00000002L +#define VCN_UMSCH_SYS_INT_SRC__INT2_MASK 0x00000004L +#define VCN_UMSCH_SYS_INT_SRC__INT3_MASK 0x00000008L +#define VCN_UMSCH_SYS_INT_SRC__INT4_MASK 0x00000010L +#define VCN_UMSCH_SYS_INT_SRC__INT5_MASK 0x00000020L +#define VCN_UMSCH_SYS_INT_SRC__INT6_MASK 0x00000040L +#define VCN_UMSCH_SYS_INT_SRC__INT7_MASK 0x00000080L +//VCN_UMSCH_IH_CTX_CTRL +#define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID__SHIFT 0x0 +#define VCN_UMSCH_IH_CTX_CTRL__IH_CTX_ID_MASK 0x0FFFFFFFL +//UVD_UMSCH_FORCE +#define UVD_UMSCH_FORCE__IC_FORCE_GPUVM__SHIFT 0x0 +#define UVD_UMSCH_FORCE__DC_FORCE_GPUVM__SHIFT 0x1 +#define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE__SHIFT 0x2 +#define UVD_UMSCH_FORCE__FORCE_DROP_INT_DISABLE__SHIFT 0x3 +#define UVD_UMSCH_FORCE__BYPASS_UTCL2_ATC_AUTO_RESP__SHIFT 0x4 +#define UVD_UMSCH_FORCE__BYPASS_UTCL2_VM_INV_AUTO_RESP__SHIFT 0x5 +#define UVD_UMSCH_FORCE__IC_FORCE_GPUVM_MASK 0x00000001L +#define UVD_UMSCH_FORCE__DC_FORCE_GPUVM_MASK 0x00000002L +#define UVD_UMSCH_FORCE__FORCE_DROP_DISABLE_MASK 0x00000004L +#define UVD_UMSCH_FORCE__FORCE_DROP_INT_DISABLE_MASK 0x00000008L +#define UVD_UMSCH_FORCE__BYPASS_UTCL2_ATC_AUTO_RESP_MASK 0x00000010L +#define UVD_UMSCH_FORCE__BYPASS_UTCL2_VM_INV_AUTO_RESP_MASK 0x00000020L +//UMSCH_MES_RESET_CTRL +#define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET__SHIFT 0x0 +#define UMSCH_MES_RESET_CTRL__MES_CORE_SOFT_RESET_MASK 0x00000001L + + +// addressBlock: uvd_vcn_cprs64dec +//VCN_MES_PRGRM_CNTR_START +#define VCN_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define VCN_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//VCN_MES_INTR_ROUTINE_START +#define VCN_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define VCN_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//VCN_MES_MTVEC_LO +#define VCN_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define VCN_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//VCN_MES_INTR_ROUTINE_START_HI +#define VCN_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define VCN_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL +//VCN_MES_MTVEC_HI +#define VCN_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define VCN_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//VCN_MES_CNTL +#define VCN_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 +#define VCN_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 +#define VCN_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 +#define VCN_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 +#define VCN_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 +#define VCN_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a +#define VCN_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b +#define VCN_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c +#define VCN_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d +#define VCN_MES_CNTL__MES_HALT__SHIFT 0x1e +#define VCN_MES_CNTL__MES_STEP__SHIFT 0x1f +#define VCN_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L +#define VCN_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L +#define VCN_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L +#define VCN_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L +#define VCN_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L +#define VCN_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L +#define VCN_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L +#define VCN_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L +#define VCN_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L +#define VCN_MES_CNTL__MES_HALT_MASK 0x40000000L +#define VCN_MES_CNTL__MES_STEP_MASK 0x80000000L +//VCN_MES_PIPE_PRIORITY_CNTS +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define VCN_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//VCN_MES_PIPE0_PRIORITY +#define VCN_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define VCN_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//VCN_MES_PIPE1_PRIORITY +#define VCN_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define VCN_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//VCN_MES_PIPE2_PRIORITY +#define VCN_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define VCN_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//VCN_MES_PIPE3_PRIORITY +#define VCN_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define VCN_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//VCN_MES_HEADER_DUMP +#define VCN_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define VCN_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//VCN_MES_MIE_LO +#define VCN_MES_MIE_LO__MES_INT__SHIFT 0x0 +#define VCN_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL +//VCN_MES_MIE_HI +#define VCN_MES_MIE_HI__MES_INT__SHIFT 0x0 +#define VCN_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT +#define VCN_MES_INTERRUPT__MES_INT__SHIFT 0x0 +#define VCN_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL +//VCN_MES_SCRATCH_INDEX +#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x00000FFFL +#define VCN_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//VCN_MES_SCRATCH_DATA +#define VCN_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define VCN_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//VCN_MES_INSTR_PNTR +#define VCN_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define VCN_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//VCN_MES_MSCRATCH_HI +#define VCN_MES_MSCRATCH_HI__DATA__SHIFT 0x0 +#define VCN_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL +//VCN_MES_MSCRATCH_LO +#define VCN_MES_MSCRATCH_LO__DATA__SHIFT 0x0 +#define VCN_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL +//VCN_MES_MSTATUS_LO +#define VCN_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 +#define VCN_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL +//VCN_MES_MSTATUS_HI +#define VCN_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 +#define VCN_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL +//VCN_MES_MEPC_LO +#define VCN_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 +#define VCN_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL +//VCN_MES_MEPC_HI +#define VCN_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 +#define VCN_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL +//VCN_MES_MCAUSE_LO +#define VCN_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 +#define VCN_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL +//VCN_MES_MCAUSE_HI +#define VCN_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 +#define VCN_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL +//VCN_MES_MBADADDR_LO +#define VCN_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 +#define VCN_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//VCN_MES_MBADADDR_HI +#define VCN_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 +#define VCN_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//VCN_MES_MIP_LO +#define VCN_MES_MIP_LO__MIP_LO__SHIFT 0x0 +#define VCN_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//VCN_MES_MIP_HI +#define VCN_MES_MIP_HI__MIP_HI__SHIFT 0x0 +#define VCN_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//VCN_MES_IC_OP_CNTL +#define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define VCN_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define VCN_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define VCN_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define VCN_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//VCN_MES_MCYCLE_LO +#define VCN_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 +#define VCN_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL +//VCN_MES_MCYCLE_HI +#define VCN_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 +#define VCN_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL +//VCN_MES_MTIME_LO +#define VCN_MES_MTIME_LO__TIME_LO__SHIFT 0x0 +#define VCN_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL +//VCN_MES_MTIME_HI +#define VCN_MES_MTIME_HI__TIME_HI__SHIFT 0x0 +#define VCN_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL +//VCN_MES_MINSTRET_LO +#define VCN_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 +#define VCN_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL +//VCN_MES_MINSTRET_HI +#define VCN_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 +#define VCN_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL +//VCN_MES_MISA_LO +#define VCN_MES_MISA_LO__MISA_LO__SHIFT 0x0 +#define VCN_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL +//VCN_MES_MISA_HI +#define VCN_MES_MISA_HI__MISA_HI__SHIFT 0x0 +#define VCN_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL +//VCN_MES_MVENDORID_LO +#define VCN_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 +#define VCN_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL +//VCN_MES_MVENDORID_HI +#define VCN_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 +#define VCN_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL +//VCN_MES_MARCHID_LO +#define VCN_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 +#define VCN_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL +//VCN_MES_MARCHID_HI +#define VCN_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 +#define VCN_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL +//VCN_MES_MIMPID_LO +#define VCN_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 +#define VCN_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL +//VCN_MES_MIMPID_HI +#define VCN_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 +#define VCN_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL +//VCN_MES_MHARTID_LO +#define VCN_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 +#define VCN_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL +//VCN_MES_MHARTID_HI +#define VCN_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 +#define VCN_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL +//VCN_MES_DC_BASE_CNTL +#define VCN_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define VCN_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//VCN_MES_DC_OP_CNTL +#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define VCN_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define VCN_MES_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 +#define VCN_MES_DC_OP_CNTL__DEPRACATED__SHIFT 0x4 +#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define VCN_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define VCN_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +#define VCN_MES_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L +#define VCN_MES_DC_OP_CNTL__DEPRACATED_MASK 0x00000010L +//VCN_MES_MTIMECMP_LO +#define VCN_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define VCN_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//VCN_MES_MTIMECMP_HI +#define VCN_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define VCN_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//VCN_MES_GP0_LO +#define VCN_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define VCN_MES_GP0_LO__DATA__SHIFT 0x1 +#define VCN_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define VCN_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL +//VCN_MES_GP0_HI +#define VCN_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define VCN_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//VCN_MES_GP1_LO +#define VCN_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define VCN_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//VCN_MES_GP1_HI +#define VCN_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define VCN_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//VCN_MES_GP2_LO +#define VCN_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define VCN_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//VCN_MES_GP2_HI +#define VCN_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define VCN_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//VCN_MES_GP3_LO +#define VCN_MES_GP3_LO__DATA__SHIFT 0x0 +#define VCN_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP3_HI +#define VCN_MES_GP3_HI__DATA__SHIFT 0x0 +#define VCN_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP4_LO +#define VCN_MES_GP4_LO__DATA__SHIFT 0x0 +#define VCN_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP4_HI +#define VCN_MES_GP4_HI__DATA__SHIFT 0x0 +#define VCN_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP5_LO +#define VCN_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define VCN_MES_GP5_LO__DATA__SHIFT 0x1 +#define VCN_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define VCN_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL +//VCN_MES_GP5_HI +#define VCN_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define VCN_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//VCN_MES_GP6_LO +#define VCN_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define VCN_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//VCN_MES_GP6_HI +#define VCN_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define VCN_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//VCN_MES_GP7_LO +#define VCN_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define VCN_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//VCN_MES_GP7_HI +#define VCN_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define VCN_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//VCN_MES_GP8_LO +#define VCN_MES_GP8_LO__DATA__SHIFT 0x0 +#define VCN_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP8_HI +#define VCN_MES_GP8_HI__DATA__SHIFT 0x0 +#define VCN_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP9_LO +#define VCN_MES_GP9_LO__DATA__SHIFT 0x0 +#define VCN_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL +//VCN_MES_GP9_HI +#define VCN_MES_GP9_HI__DATA__SHIFT 0x0 +#define VCN_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL +//VCN_MES_DM_INDEX_ADDR +#define VCN_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define VCN_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//VCN_MES_DM_INDEX_DATA +#define VCN_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define VCN_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//VCN_MES_LOCAL_BASE0_LO +#define VCN_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define VCN_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//VCN_MES_LOCAL_BASE0_HI +#define VCN_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define VCN_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//VCN_MES_LOCAL_MASK0_LO +#define VCN_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define VCN_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//VCN_MES_LOCAL_MASK0_HI +#define VCN_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define VCN_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//VCN_MES_LOCAL_APERTURE +#define VCN_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define VCN_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +//VCN_MES_LOCAL_INSTR_BASE_LO +#define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define VCN_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//VCN_MES_LOCAL_INSTR_BASE_HI +#define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define VCN_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//VCN_MES_LOCAL_INSTR_MASK_LO +#define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define VCN_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//VCN_MES_LOCAL_INSTR_MASK_HI +#define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define VCN_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//VCN_MES_LOCAL_INSTR_APERTURE +#define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define VCN_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +//VCN_MES_LOCAL_SCRATCH_APERTURE +#define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define VCN_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//VCN_MES_LOCAL_SCRATCH_BASE_LO +#define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define VCN_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//VCN_MES_LOCAL_SCRATCH_BASE_HI +#define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define VCN_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//VCN_MES_PERFCOUNT_CNTL +#define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define VCN_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//VCN_MES_PENDING_INTERRUPT +#define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define VCN_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//VCN_MES_PRGRM_CNTR_START_HI +#define VCN_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define VCN_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//VCN_MES_INTERRUPT_DATA_16 +#define VCN_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_17 +#define VCN_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_18 +#define VCN_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_19 +#define VCN_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_20 +#define VCN_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_21 +#define VCN_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_22 +#define VCN_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_23 +#define VCN_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_24 +#define VCN_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_25 +#define VCN_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_26 +#define VCN_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_27 +#define VCN_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_28 +#define VCN_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_29 +#define VCN_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_30 +#define VCN_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//VCN_MES_INTERRUPT_DATA_31 +#define VCN_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define VCN_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE0_BASE +#define VCN_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE0_MASK +#define VCN_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE0_CNTL +#define VCN_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE1_BASE +#define VCN_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE1_MASK +#define VCN_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE1_CNTL +#define VCN_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE2_BASE +#define VCN_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE2_MASK +#define VCN_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE2_CNTL +#define VCN_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE3_BASE +#define VCN_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE3_MASK +#define VCN_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE3_CNTL +#define VCN_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE4_BASE +#define VCN_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE4_MASK +#define VCN_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE4_CNTL +#define VCN_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE5_BASE +#define VCN_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE5_MASK +#define VCN_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE5_CNTL +#define VCN_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE6_BASE +#define VCN_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE6_MASK +#define VCN_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE6_CNTL +#define VCN_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE7_BASE +#define VCN_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE7_MASK +#define VCN_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE7_CNTL +#define VCN_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE8_BASE +#define VCN_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE8_MASK +#define VCN_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE8_CNTL +#define VCN_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE9_BASE +#define VCN_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE9_MASK +#define VCN_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE9_CNTL +#define VCN_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE10_BASE +#define VCN_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE10_MASK +#define VCN_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE10_CNTL +#define VCN_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE11_BASE +#define VCN_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE11_MASK +#define VCN_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE11_CNTL +#define VCN_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE12_BASE +#define VCN_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE12_MASK +#define VCN_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE12_CNTL +#define VCN_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE13_BASE +#define VCN_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE13_MASK +#define VCN_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE13_CNTL +#define VCN_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE14_BASE +#define VCN_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE14_MASK +#define VCN_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE14_CNTL +#define VCN_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L +//VCN_MES_DC_APERTURE15_BASE +#define VCN_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 +#define VCN_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE15_MASK +#define VCN_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 +#define VCN_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL +//VCN_MES_DC_APERTURE15_CNTL +#define VCN_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 +#define VCN_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L + + +// addressBlock: uvd_vcn_hypdec +//VCN_MES_IC_BASE_LO +#define VCN_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define VCN_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//VCN_MES_MIBASE_LO +#define VCN_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc +#define VCN_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//VCN_MES_IC_BASE_HI +#define VCN_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define VCN_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//VCN_MES_MIBASE_HI +#define VCN_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 +#define VCN_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//VCN_MES_IC_BASE_CNTL +#define VCN_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define VCN_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define VCN_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define VCN_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define VCN_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define VCN_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//VCN_MES_DC_BASE_LO +#define VCN_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define VCN_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//VCN_MES_MDBASE_LO +#define VCN_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define VCN_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//VCN_MES_DC_BASE_HI +#define VCN_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define VCN_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL +//VCN_MES_MDBASE_HI +#define VCN_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define VCN_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL +//VCN_MES_MIBOUND_LO +#define VCN_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define VCN_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//VCN_MES_MIBOUND_HI +#define VCN_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define VCN_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//VCN_MES_MDBOUND_LO +#define VCN_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define VCN_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//VCN_MES_MDBOUND_HI +#define VCN_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define VCN_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL + + +// addressBlock: uvd_slmi_adpdec +//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL +//UVD_LMI_MMSCH_NC_VMID +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L +#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L +//UVD_LMI_MMSCH_CTRL +#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 +#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 +#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH__SHIFT 0x2 +#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 +#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc +#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L +#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L +#define UVD_LMI_MMSCH_CTRL__PRIV_CLIENT_MMSCH_MASK 0x00000004L +#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L +#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L +#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L +#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L +//UVD_MMSCH_LMI_STATUS +#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT__SHIFT 0x0 +#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT__SHIFT 0x1 +#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN__SHIFT 0x2 +#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN__SHIFT 0x4 +#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS__SHIFT 0x8 +#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE__SHIFT 0xc +#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN__SHIFT 0xd +#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN__SHIFT 0xe +#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_LEN_INT_MASK 0x00000001L +#define UVD_MMSCH_LMI_STATUS__LMI_AXI_MMSCH_UNSUPPORTED_ADR_ALIGN_INT_MASK 0x00000002L +#define UVD_MMSCH_LMI_STATUS__MMSCH_LMI_WRITE_CLEAN_MASK 0x00000004L +#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_LEN_MASK 0x000000F0L +#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_ADDR_LSBS_MASK 0x00000700L +#define UVD_MMSCH_LMI_STATUS__AXI_MMSCH_ERR_AWRITE_MASK 0x00001000L +#define UVD_MMSCH_LMI_STATUS__MMSCH_RD_CLEAN_MASK 0x00002000L +#define UVD_MMSCH_LMI_STATUS__MMSCH_WR_CLEAN_MASK 0x00004000L +//UMSCH_IOV_ACTIVE_FCN_ID +#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 +#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f +#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000003FL +#define UMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L +//UVD_UMSCH_LMI_STATUS +#define UVD_UMSCH_LMI_STATUS__UMSCHIC_RD_CLEAN__SHIFT 0x0 +#define UVD_UMSCH_LMI_STATUS__UMSCHDC_RD_CLEAN__SHIFT 0x1 +#define UVD_UMSCH_LMI_STATUS__UMSCHDC_WR_CLEAN__SHIFT 0x2 +#define UVD_UMSCH_LMI_STATUS__UMSCHIC_RD_CLEAN_MASK 0x00000001L +#define UVD_UMSCH_LMI_STATUS__UMSCHDC_RD_CLEAN_MASK 0x00000002L +#define UVD_UMSCH_LMI_STATUS__UMSCHDC_WR_CLEAN_MASK 0x00000004L + + +#endif diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 3d083010e734a..62f7ed0b20667 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -879,6 +879,7 @@ enum atom_connector_caps_def { ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq + ATOM_CONNECTOR_CAP_DP_PLUS_PLUS_TYPE2_ONLY = 0x10, //a cap bit that indicates connector with DP_PLUS_PLUS_TYPE2_ONLY }; struct atom_disp_connector_caps_record @@ -1694,7 +1695,9 @@ struct atom_integrated_system_info_v2_3 { uint8_t gpu_package_id; struct edp_info_table edp1_info; struct edp_info_table edp2_info; - uint32_t reserved2[8]; + uint32_t cpuid; + uint32_t vram_bit_width; + uint32_t reserved2[6]; struct atom_external_display_connection_info extdispconninfo; uint8_t UMACarveoutVersion; uint8_t UMACarveoutIndexMax; @@ -1769,6 +1772,7 @@ enum atom_dmi_t17_mem_type_def{ Hbm2MemType, ///< Assign 33 to HBM2 Ddr5MemType, ///< Assign 34 to DDR5 LpDdr5MemType, ///< Assign 35 to LPDDR5 + LpDdr5xMemType, ///< Assign 36 to LPDDR5x }; diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index 710e328fad48f..76c9f951bc1c8 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -64,6 +64,19 @@ typedef struct binary_header table_info table_list[TOTAL_TABLES]; } binary_header; +typedef struct binary_header_v2 +{ + /* psp structure should go at the top of this structure */ + uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ + uint16_t version_major; /* 0x02 */ + uint16_t version_minor; + uint16_t binary_checksum; /* Byte sum of the binary after this field */ + uint16_t binary_size; /* Binary Size*/ + uint16_t num_tables; + uint16_t padding; + table_info table_list[] __counted_by(num_tables); +} binary_header_v2; + typedef struct die_info { uint16_t die_id; diff --git a/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h new file mode 100644 index 0000000000000..9fe5466e94183 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/gfx/irqsrcs_gfx_12_1_0.h @@ -0,0 +1,136 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __IRQSRCS_GFX_12_1_0_H__ +#define __IRQSRCS_GFX_12_1_0_H__ + +/* 0x0 UTCL2 has encountered a fault scenario */ +#define GFX_12_1_0__SRCID__UTCL2_FAULT 0 +/* 0x1 UTCL2 has encountered a retry scenario */ +#define GFX_12_1_0__SRCID__UTCL2_RETRY 1 +/* 0x2 UTCL2 for data poisoning */ +#define GFX_12_1_0__SRCID__UTCL2_DATA_POISONING 2 +/* 0x30 SDMA atomic*_rtn ops complete */ +#define GFX_12_1_0__SRCID__SDMA_ATOMIC_RTN_DONE 48 +/* 0x31 Trap */ +#define GFX_12_1_0__SRCID__SDMA_TRAP 49 +/* 0x32 SRBM write Protection */ +#define GFX_12_1_0__SRCID__SDMA_SRBMWRITE 50 +/* 0x33 Context Empty */ +#define GFX_12_1_0__SRCID__SDMA_CTXEMPTY 51 +/* 0x34 SDMA New Run List */ +#define GFX_12_1_0__SRCID__SDMA_PREEMPT 52 +/* 0x35 sdma mid - command buffer preempt interrupt */ +#define GFX_12_1_0__SRCID__SDMA_IB_PREEMPT 53 +/* 0x36 Doorbell BE invalid */ +#define GFX_12_1_0__SRCID__SDMA_DOORBELL_INVALID 54 +/* 0x37 Queue hang or Command timeout */ +#define GFX_12_1_0__SRCID__SDMA_QUEUE_HANG 55 +/* 0x38 SDMA atomic CMPSWAP loop timeout */ +#define GFX_12_1_0__SRCID__SDMA_ATOMIC_TIMEOUT 56 +/* 0x39 SRBM read poll timeout */ +#define GFX_12_1_0__SRCID__SDMA_POLL_TIMEOUT 57 +/* 0x3A Page retry timeout after UTCL2 return nack = 1 */ +#define GFX_12_1_0__SRCID__SDMA_PAGE_TIMEOUT 58 +/* 0x3B Page Null from UTCL2 when nack = 2 */ +#define GFX_12_1_0__SRCID__SDMA_PAGE_NULL 59 +/* 0x3C Page Fault Error from UTCL2 when nack = 3 */ +#define GFX_12_1_0__SRCID__SDMA_PAGE_FAULT 60 +/* 0x3D MC or SEM address in VM hole */ +#define GFX_12_1_0__SRCID__SDMA_INVALID_ADDR 61 +/* 0x3E ECC Error */ +#define GFX_12_1_0__SRCID__SDMA_ECC 62 +/* 0x3F SDMA Frozen */ +#define GFX_12_1_0__SRCID__SDMA_FROZEN 63 +/* 0x40 SRAM ECC Error */ +#define GFX_12_1_0__SRCID__SDMA_SRAM_ECC 64 +/* 0x41 GPF(Sem incomplete timeout) */ +#define GFX_12_1_0__SRCID__SDMA_SEM_INCOMPLETE_TIMEOUT 65 +/* 0x42 Semaphore wait fail timeout */ +#define GFX_12_1_0__SRCID__SDMA_SEM_WAIT_FAIL_TIMEOUT 66 +/* 0x43 Wptr less than Rptr in active queue */ +#define GFX_12_1_0__SRCID__SDMA_INVALID_RB_PTR 67 +/* 0x44 BE command exception */ +#define GFX_12_1_0__SRCID__SDMA_BE_EXCEPTION 68 +/* 0x46 User fence. inherit from gfx v12_0 for gfx user queue */ +#define GFX_12_1_0__SRCID__SDMA_FENCE 70 +/* 0xB0 CP_INTERRUPT pkt in RB */ +#define GFX_12_1_0__SRCID__CP_RB_INT_PKT 176 +/* 0xB1 CP_INTERRUPT pkt in IB1 */ +#define GFX_12_1_0__SRCID__CP_IB1_INT_PKT 177 +/* 0xB2 CP_INTERRUPT pkt in IB2 */ +#define GFX_12_1_0__SRCID__CP_IB2_INT_PKT 178 +/* 0xB3 DMA Watch Interrupt */ +#define GFX_12_1_0__SRCID__CP_DMA_WATCH_INTERRUPT 179 +/* 0xB4 PM4 Pkt Rsvd Bits Error */ +#define GFX_12_1_0__SRCID__CP_PM4_PKT_RSVD_BIT_ERROR 180 +/* 0xB5 End-of-Pipe Interrupt */ +#define GFX_12_1_0__SRCID__CP_EOP_INTERRUPT 181 +/* 0xB7 Bad Opcode Error */ +#define GFX_12_1_0__SRCID__CP_BAD_OPCODE_ERROR 183 +/* 0xB8 Privileged Register Fault */ +#define GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT 184 +/* 0xB9 Privileged Instr Fault */ +#define GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT 185 +/* 0xBA Wait Memory Semaphore Fault (Sync Object Fault) */ +#define GFX_12_1_0__SRCID__CP_WAIT_MEM_SEM_FAULT 186 +/* 0xBB Context Empty Interrupt */ +#define GFX_12_1_0__SRCID__CP_CTX_EMPTY_INTERRUPT 187 +/* 0xBC Context Busy Interrupt */ +#define GFX_12_1_0__SRCID__CP_CTX_BUSY_INTERRUPT 188 +/* 0xC0 CP.ME Wait_Reg_Mem Poll Timeout */ +#define GFX_12_1_0__SRCID__CP_ME_WAIT_REG_MEM_POLL_TIMEOUT 192 +/* 0xC1 Surface Probe Fault Signal Incomplete */ +#define GFX_12_1_0__SRCID__CP_SIG_INCOMPLETE 193 +/* 0xC2 Preemption Ack-wledge */ +#define GFX_12_1_0__SRCID__CP_PREEMPT_ACK 194 +/* 0xC3 General Protection Fault (GPF) */ +#define GFX_12_1_0__SRCID__CP_GPF 195 +/* 0xC4 GDS Alloc Error */ +#define GFX_12_1_0__SRCID__CP_GDS_ALLOC_ERROR 196 +/* 0xC5 ECC Error */ +#define GFX_12_1_0__SRCID__CP_ECC_ERROR 197 +/* 0xC8 Unattached VM Doorbell Received */ +#define GFX_12_1_0__SRCID__CP_VM_DOORBELL 200 +/* 0xC9 ECC FUE Error */ +#define GFX_12_1_0__SRCID__CP_FUE_ERROR 201 +/* 0xCA Suspend Completion Interrupt */ +#define GFX_12_1_0__SRCID__CP_SUSPEAND_REQ_INTERRUPT 202 +/* 0xCB Resume Completion Interrupt */ +#define GFX_12_1_0__SRCID__CP_RESUME_REQ_INTERRUPT 203 +/* 0xCA RLC Streaming Perf Monitor Interrupt + * ContextID[15:0] each bit indicates poison is seen on respecive indexed VMID + * Ex: ContextID[3] == 1 means VMID-3 encountered poison consumption + * ContextID[16] == 1 indicates that complete VF need to reset with FLR */ +#define GFX_12_1_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT 202 +/* 0xCB RLC Poison Interrupt */ +#define GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT 203 +/* 0xE7 High on ContextID[0] - nHT Error; ContextID[1] - illegal Opcode Error */ +#define GFX_12_1_0__SRCID__PMR_EA_ERROR_INTERRUPT 231 +/* 0xE8 CRead timeout error */ +#define GFX_12_1_0__SRCID__GRBM_RD_TIMEOUT_ERROR 232 +/* 0xE9 Register GUI Idle */ +#define GFX_12_1_0__SRCID__GRBM_REG_GUI_IDLE 233 +/* 0xEF SQ Interrupt (ttrace wrap, errors) */ +#define GFX_12_1_0__SRCID__SQ_INTERRUPT_ID 239 + +#endif diff --git a/drivers/gpu/drm/amd/include/ivsrcid/vmc/irqsrcs_vmc_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/vmc/irqsrcs_vmc_1_0.h index d130936c99890..22075805e95c4 100644 --- a/drivers/gpu/drm/amd/include/ivsrcid/vmc/irqsrcs_vmc_1_0.h +++ b/drivers/gpu/drm/amd/include/ivsrcid/vmc/irqsrcs_vmc_1_0.h @@ -28,10 +28,12 @@ #define VMC_1_0__SRCID__VM_FAULT 0 +#define VMC_1_0__SRCID__VM_RETRY 1 #define VMC_1_0__SRCID__VM_CONTEXT0_ALL 256 #define VMC_1_0__SRCID__VM_CONTEXT1_ALL 257 #define UTCL2_1_0__SRCID__FAULT 0 /* UTC L2 has encountered a fault or retry scenario */ +#define UTCL2_1_0__SRCID__RETRY 1 /* UTC L2 has encountered a retry scenario (GFX12.1) */ #endif /* __IRQSRCS_VMC_1_0_H__ */ diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 9aba8596faa7e..df5b578a5e6b1 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -31,6 +31,8 @@ #include #include #include +#include + #include "amdgpu_irq.h" #include "amdgpu_gfx.h" @@ -204,6 +206,11 @@ struct tile_config { * IH ring entry. This function allows the KFD ISR to get the VMID * from the fault status register as early as possible. * + * @get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values + * + * @build_grace_period_packet_info: build a IQ_WAUT_TIME2 reg value with an + * updated grace period value. + * * @get_cu_occupancy: Function pointer that returns to caller the number * of wave fronts that are in flight for all of the queues of a process * as identified by its pasid. It is important to note that the value @@ -333,6 +340,21 @@ struct kfd2kgd_calls { uint32_t inst, unsigned int utimeout); uint32_t (*hqd_sdma_get_doorbell)(struct amdgpu_device *adev, int engine, int queue); + uint32_t (*trigger_pc_sample_trap)(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); + void (*override_core_cg)(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); + uint32_t (*setup_stoch_sampling)(struct amdgpu_device *adev, + uint32_t compute_vmid_bitmap, + bool enable, + enum kfd_ioctl_pc_sample_type type, + uint64_t intval, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 2366e68262e68..2e931aa89726d 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -29,6 +29,7 @@ extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; +extern const struct amdgpu_ip_block_version smu_v15_0_ip_block; enum smu_temp_metric_type { SMU_TEMP_METRIC_BASEBOARD, @@ -118,6 +119,7 @@ enum pp_clock_type { PP_ISPXCLK, OD_SCLK, OD_MCLK, + OD_FCLK, OD_VDDC_CURVE, OD_RANGE, OD_VDDGFX_OFFSET, @@ -136,7 +138,6 @@ enum amd_pp_sensors { AMDGPU_PP_SENSOR_CPU_CLK, AMDGPU_PP_SENSOR_VDDNB, AMDGPU_PP_SENSOR_VDDGFX, - AMDGPU_PP_SENSOR_VDDBOARD, AMDGPU_PP_SENSOR_UVD_VCLK, AMDGPU_PP_SENSOR_UVD_DCLK, AMDGPU_PP_SENSOR_VCE_ECCLK, @@ -162,10 +163,13 @@ enum amd_pp_sensors { AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, AMDGPU_PP_SENSOR_VCN_LOAD, + AMDGPU_PP_SENSOR_VDDBOARD, AMDGPU_PP_SENSOR_NODEPOWERLIMIT, AMDGPU_PP_SENSOR_NODEPOWER, AMDGPU_PP_SENSOR_GPPTRESIDENCY, AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, + AMDGPU_PP_SENSOR_UBB_POWER, + AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, }; enum amd_pp_task { @@ -205,6 +209,7 @@ enum { enum PP_OD_DPM_TABLE_COMMAND { PP_OD_EDIT_SCLK_VDDC_TABLE, PP_OD_EDIT_MCLK_VDDC_TABLE, + PP_OD_EDIT_FCLK_TABLE, PP_OD_EDIT_CCLK_VDDC_TABLE, PP_OD_EDIT_VDDC_CURVE, PP_OD_RESTORE_DEFAULT_TABLE, @@ -309,6 +314,15 @@ enum pp_policy_soc_pstate { #define PP_POLICY_MAX_LEVELS 5 +enum pp_pm_phase_det_param_id { + PP_PM_PHASE_DET_LO_FREQ = 0, + PP_PM_PHASE_DET_HI_FREQ = 1, + PP_PM_PHASE_DET_THRESH = 2, + PP_PM_PHASE_DET_ALPHA = 3, + PP_PM_PHASE_DET_HYST = 4, + PP_PM_PHASE_DET_ALL = 5, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 @@ -581,6 +595,62 @@ enum amdgpu_metrics_attr_id { AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HBM, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MID, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_AID, + AMDGPU_METRICS_ATTR_ID_TEMPERATURE_XCD, + AMDGPU_METRICS_ATTR_ID_LABEL_VERSION, + AMDGPU_METRICS_ATTR_ID_NODE_ID, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_RETIMER, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_IBC_2, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_VDD18_VR, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_B_VR, + AMDGPU_METRICS_ATTR_ID_NODE_TEMP_04_HBM_D_VR, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_SOCIO_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X0, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_X1, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_04_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_B, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_HBM_D, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_11_GTA_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075_GTA_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDCR_075_UCIE, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAA, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_A, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDIO_065_UCIEAM_C, + AMDGPU_METRICS_ATTR_ID_VR_TEMP_VDDAN_075, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FRONT, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_BACK, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM7, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_IBC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_UFPGA, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_OAM1, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_2_3_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_6_7_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_0V72_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_UBB_FPGA_3V3_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_0_1_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_4_5_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_2_3_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_RETIMER_6_7_0V9_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC_HSC, + AMDGPU_METRICS_ATTR_ID_SYSTEM_TEMP_IBC, AMDGPU_METRICS_ATTR_ID_MAX, }; @@ -1826,4 +1896,23 @@ struct amdgpu_partition_metrics_v1_1 { struct gpu_metrics_attr metrics_attrs[]; }; +enum amdgpu_xgmi_link_status { + AMDGPU_XGMI_LINK_INACTIVE = 0, + AMDGPU_XGMI_LINK_ACTIVE = 1, + /* Status not available */ + AMDGPU_XGMI_LINK_NA = 2, +}; + +struct amdgpu_gpuboard_temp_metrics_v1_1 { + struct metrics_table_header common_header; + int attr_count; + struct gpu_metrics_attr metrics_attrs[]; +}; + +struct amdgpu_baseboard_temp_metrics_v1_1 { + struct metrics_table_header common_header; + int attr_count; + struct gpu_metrics_attr metrics_attrs[]; +}; + #endif diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h index 2f12cba4eb662..e541a43714a10 100644 --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h @@ -71,6 +71,13 @@ enum MES_SCH_API_OPCODE { MES_SCH_API_MAX = 0xFF }; +enum MES_RRMT_MODE { + MES_RRMT_MODE_LOCAL_XCD, + MES_RRMT_MODE_LOCAL_REMOTE_AID, + MES_RRMT_MODE_REMOTE_XCD, + MES_RRMT_MODE_REMOTE_MID +}; + union MES_API_HEADER { struct { uint32_t type : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */ @@ -310,7 +317,8 @@ union MESAPI_SET_HW_RESOURCES_1 { union { struct { uint32_t enable_mes_debug_ctx : 1; - uint32_t reserved : 31; + uint32_t mes_coop_mode : 1; /* 0: non-coop; 1: coop */ + uint32_t reserved : 30; }; uint32_t uint32_all; }; @@ -318,7 +326,8 @@ union MESAPI_SET_HW_RESOURCES_1 { uint32_t mes_debug_ctx_size; /* unit is 100ms */ uint32_t mes_kiq_unmap_timeout; - uint64_t reserved1; + /* shared buffer of master/slaves, valid if mes_coop_mode=1 */ + uint64_t coop_sch_shared_mc_addr; uint64_t cleaner_shader_fence_mc_addr; }; @@ -383,6 +392,7 @@ union MESAPI__ADD_QUEUE { uint32_t pipe_id; //used for mapping legacy kernel queue uint32_t queue_id; uint32_t alignment_mode_setting; + uint32_t full_sh_mem_config_data; }; uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; @@ -482,8 +492,10 @@ union MESAPI__SUSPEND { union MES_API_HEADER header; /* false - suspend all gangs; true - specific gang */ struct { - uint32_t suspend_all_gangs : 1; - uint32_t reserved : 31; + uint32_t suspend_all_gangs : 1; // suspend all compute gangs (can be set together with suspend_all_sdma_gangs) + uint32_t query_status : 1; + uint32_t suspend_all_sdma_gangs : 1; // suspend all sdma gangs (can be set together with suspend_all_gangs) + uint32_t reserved : 29; }; /* gang_context_addr is valid only if suspend_all = false */ @@ -553,7 +565,26 @@ union MESAPI__RESET { /* valid only if reset_queue_only = true */ uint32_t doorbell_offset; - /* valid only if hang_detect_then_reset = true */ + /* + * valid only if hang_detect_then_reset or hang_detect_only = true + * doorbell_offset_addr will store the structure as follows + * struct + * { + * uint32_t db_offset[list_size]; + * uint32_t hqd_id[list_size]; + * } + * The hqd_id has following defines : + * struct + * { + * uint32 queue_type : 3; Type of the queue + * uint32 pipe_index : 4; pipe Index + * uint32 hqd_index : 8; This is queue_index within the pipe + * uint32 reserved : 17; + * }; + * The list_size is the total queue numbers that been managed by mes. + * It can be calculated from all hqd_masks(including gfX, compute and sdma) + * on set_hw_resource API + */ uint64_t doorbell_offset_addr; enum MES_QUEUE_TYPE queue_type; @@ -672,6 +703,7 @@ union MESAPI__SET_DEBUG_VMID { uint32_t process_context_array_index; uint32_t alignment_mode_setting; + uint32_t full_sh_mem_config_data; }; uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS]; @@ -696,9 +728,26 @@ enum MESAPI_MISC_OPCODE { enum {MISC_DATA_MAX_SIZE_IN_DWORDS = 20}; +/* + * RRMT(Register Remapping Table), allow the firmware to modify the upper + * address to correctly steer the register transaction to expected DIE + */ +struct RRMT_OPTION { + union { + struct { + uint32_t mode : 4; + uint32_t mid_die_id : 4; + uint32_t xcd_die_id : 4; + }; + uint32_t all; + }; +}; + + struct WRITE_REG { - uint32_t reg_offset; - uint32_t reg_value; + uint32_t reg_offset; + uint32_t reg_value; + struct RRMT_OPTION rrmt_opt; }; struct READ_REG { @@ -711,6 +760,7 @@ struct READ_REG { } bits; uint32_t all; } option; + struct RRMT_OPTION rrmt_opt; }; struct INV_GART { @@ -736,6 +786,8 @@ struct WAIT_REG_MEM { uint32_t mask; uint32_t reg_offset1; uint32_t reg_offset2; + struct RRMT_OPTION rrmt_opt1; /* for reg1 */ + struct RRMT_OPTION rrmt_opt2; /* for reg2 */ }; struct SET_SHADER_DEBUGGER { @@ -744,7 +796,8 @@ struct SET_SHADER_DEBUGGER { struct { uint32_t single_memop : 1; // SQ_DEBUG.single_memop uint32_t single_alu_op : 1; // SQ_DEBUG.single_alu_op - uint32_t reserved : 30; + uint32_t lds_oor_reporting : 1; /* SQ_DEBUG.ADDR_OUT_OF_RANGE_REPORTING */ + uint32_t reserved : 29; }; uint32_t u32all; } flags; diff --git a/drivers/gpu/drm/amd/include/soc15_hw_ip.h b/drivers/gpu/drm/amd/include/soc15_hw_ip.h index dad83037793aa..a20e59584dde7 100644 --- a/drivers/gpu/drm/amd/include/soc15_hw_ip.h +++ b/drivers/gpu/drm/amd/include/soc15_hw_ip.h @@ -100,5 +100,7 @@ #define XGMI_HWID 200 #define XGBE_HWID 216 #define MP0_HWID 255 +#define ATU_HWID 294 +#define AIGC_HWID 295 #endif diff --git a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h index e1948613cc1b7..d249b8407259f 100644 --- a/drivers/gpu/drm/amd/include/soc15_ih_clientid.h +++ b/drivers/gpu/drm/amd/include/soc15_ih_clientid.h @@ -103,6 +103,7 @@ enum soc21_ih_clientid { SOC21_IH_CLIENTID_VPE = 0x18, SOC21_IH_CLIENTID_PWR = 0x19, SOC21_IH_CLIENTID_LSDMA = 0x1a, + SOC21_IH_CLIENTID_UTCL2 = 0x1b, SOC21_IH_CLIENTID_MP0 = 0x1e, SOC21_IH_CLIENTID_MP1 = 0x1f, SOC21_IH_CLIENTID_MAX, diff --git a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h new file mode 100644 index 0000000000000..2a910785334db --- /dev/null +++ b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h @@ -0,0 +1,38 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SOC_V1_0_ENUM_H__ +#define __SOC_V1_0_ENUM_H__ + +typedef enum MTYPE { + MTYPE_NC = 0x00000000, + MTYPE_RESERVED_1 = 0x00000001, + MTYPE_RW = 0x00000002, + MTYPE_UC = 0x00000003, +} MTYPE; + +typedef enum SH_MEM_ALIGNMENT_MODE { + SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000, + SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000001, +} SH_MEM_ALIGNMENT_MODE; + +#endif diff --git a/drivers/gpu/drm/amd/include/soc_v1_0_ih_clientid.h b/drivers/gpu/drm/amd/include/soc_v1_0_ih_clientid.h new file mode 100644 index 0000000000000..11ab4b7d61e10 --- /dev/null +++ b/drivers/gpu/drm/amd/include/soc_v1_0_ih_clientid.h @@ -0,0 +1,52 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SOC_V1_0_IH_CLIENTID_H__ +#define __SOC_V1_0_IH_CLIENTID_H__ + +extern const char *soc_v1_0_ih_clientid_name[]; + +enum soc_v1_0_ih_clientid { + SOC_V1_0_IH_CLIENTID_IH = 0x00, + SOC_V1_0_IH_CLIENTID_ATHUB = 0x02, + SOC_V1_0_IH_CLIENTID_BIF = 0x03, + SOC_V1_0_IH_CLIENTID_RLC = 0x07, + SOC_V1_0_IH_CLIENTID_GFX = 0x0a, + SOC_V1_0_IH_CLIENTID_IMU = 0x0b, + SOC_V1_0_IH_CLIENTID_VCN1 = 0x0e, + SOC_V1_0_IH_CLIENTID_THM = 0x0f, + SOC_V1_0_IH_CLIENTID_VCN = 0x10, + SOC_V1_0_IH_CLIENTID_VMC = 0x12, + SOC_V1_0_IH_CLIENTID_GRBM_CP = 0x14, + SOC_V1_0_IH_CLIENTID_GC_AID = 0x15, + SOC_V1_0_IH_CLIENTID_ROM_SMUIO = 0x16, + SOC_V1_0_IH_CLIENTID_DF = 0x17, + SOC_V1_0_IH_CLIENTID_PWR = 0x19, + SOC_V1_0_IH_CLIENTID_LSDMA = 0x1a, + SOC_V1_0_IH_CLIENTID_GC_UTCL2 = 0x1b, + SOC_V1_0_IH_CLIENTID_nHT = 0X1c, + SOC_V1_0_IH_CLIENTID_MP0 = 0x1e, + SOC_V1_0_IH_CLIENTID_MP1 = 0x1f, + SOC_V1_0_IH_CLIENTID_MAX, +}; + +#endif diff --git a/drivers/gpu/drm/amd/include/v12_structs.h b/drivers/gpu/drm/amd/include/v12_structs.h index 03a35f8a65b08..28f4b01326811 100644 --- a/drivers/gpu/drm/amd/include/v12_structs.h +++ b/drivers/gpu/drm/amd/include/v12_structs.h @@ -1186,4 +1186,2058 @@ struct v12_compute_mqd { uint32_t gws_63_val; // offset: 511 (0x1FF) }; +struct v12_1_compute_mqd { + uint32_t header; // offset: 0 (0x0) + uint32_t compute_dispatch_initiator; // offset: 1 (0x1) + uint32_t compute_dim_x; // offset: 2 (0x2) + uint32_t compute_dim_y; // offset: 3 (0x3) + uint32_t compute_dim_z; // offset: 4 (0x4) + uint32_t compute_start_x; // offset: 5 (0x5) + uint32_t compute_start_y; // offset: 6 (0x6) + uint32_t compute_start_z; // offset: 7 (0x7) + uint32_t compute_num_thread_x; // offset: 8 (0x8) + uint32_t compute_num_thread_y; // offset: 9 (0x9) + uint32_t compute_num_thread_z; // offset: 10 (0xA) + uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) + uint32_t compute_perfcount_enable; // offset: 12 (0xC) + uint32_t compute_pgm_lo; // offset: 13 (0xD) + uint32_t compute_pgm_hi; // offset: 14 (0xE) + uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) + uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) + uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) + uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) + uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) + uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) + uint32_t compute_vmid; // offset: 21 (0x15) + uint32_t compute_resource_limits; // offset: 22 (0x16) + uint32_t compute_tmpring_size; // offset: 23 (0x17) + uint32_t compute_restart_x; // offset: 24 (0x18) + uint32_t compute_restart_y; // offset: 25 (0x19) + uint32_t compute_restart_z; // offset: 26 (0x1A) + uint32_t compute_thread_trace_enable; // offset: 27 (0x1B) + uint32_t compute_misc_reserved; // offset: 28 (0x1C) + uint32_t compute_dispatch_id; // offset: 29 (0x1D) + uint32_t compute_threadgroup_id; // offset: 30 (0x1E) + uint32_t compute_req_ctrl; // offset: 31 (0x1F) + uint32_t compute_user_accum_0; // offset: 32 (0x20) + uint32_t compute_user_accum_1; // offset: 33 (0x21) + uint32_t compute_user_accum_2; // offset: 34 (0x22) + uint32_t compute_user_accum_3; // offset: 35 (0x23) + uint32_t compute_pgm_rsrc3; // offset: 36 (0x24) + uint32_t compute_ddid_index; // offset: 37 (0x25) + uint32_t compute_shader_chksum; // offset: 38 (0x26) + uint32_t compute_dispatch_interleave; // offset: 39 (0x27) + uint32_t compute_current_logical_xcc_id; // offset: 40 (0x28) + uint32_t compute_restart_cg_tg_id; // offset: 41 (0x29) + uint32_t compute_tg_chunk_size; // offset: 42 (0x2A) + uint32_t compute_restore_tg_chunk_size; // offset: 43 (0x2B) + uint32_t reserved_44; // offset: 44 (0x2C) + uint32_t reserved_45; // offset: 45 (0x2D) + uint32_t compute_prescaled_dim_x; // offset: 46 (0x2E) + uint32_t compute_prescaled_dim_y; // offset: 47 (0x2F) + uint32_t compute_prescaled_dim_z; // offset: 48 (0x30) + uint32_t compute_static_thread_mgmt_se0; // offset: 49 (0x31) + uint32_t compute_static_thread_mgmt_se1; // offset: 50 (0x32) + uint32_t compute_static_thread_mgmt_se2; // offset: 51 (0x33) + uint32_t compute_static_thread_mgmt_se3; // offset: 52 (0x34) + uint32_t compute_static_thread_mgmt_se4; // offset: 53 (0x35) + uint32_t compute_static_thread_mgmt_se5; // offset: 54 (0x36) + uint32_t compute_static_thread_mgmt_se6; // offset: 55 (0x37) + uint32_t compute_static_thread_mgmt_se7; // offset: 56 (0x38) + uint32_t compute_static_thread_mgmt_se8; // offset: 57 (0x39) + uint32_t reserved_58; // offset: 58 (0x3A) + uint32_t reserved_59; // offset: 59 (0x3B) + uint32_t reserved_60; // offset: 60 (0x3C) + uint32_t reserved_61; // offset: 61 (0x3D) + uint32_t reserved_62; // offset: 62 (0x3E) + uint32_t reserved_63; // offset: 63 (0x3F) + uint32_t tg_counter_id; // offset: 64 (0x40) + uint32_t compute_user_data_0; // offset: 65 (0x41) + uint32_t compute_user_data_1; // offset: 66 (0x42) + uint32_t compute_user_data_2; // offset: 67 (0x43) + uint32_t compute_user_data_3; // offset: 68 (0x44) + uint32_t compute_user_data_4; // offset: 69 (0x45) + uint32_t compute_user_data_5; // offset: 70 (0x46) + uint32_t compute_user_data_6; // offset: 71 (0x47) + uint32_t compute_user_data_7; // offset: 72 (0x48) + uint32_t compute_user_data_8; // offset: 73 (0x49) + uint32_t compute_user_data_9; // offset: 74 (0x4A) + uint32_t compute_user_data_10; // offset: 75 (0x4B) + uint32_t compute_user_data_11; // offset: 76 (0x4C) + uint32_t compute_user_data_12; // offset: 77 (0x4D) + uint32_t compute_user_data_13; // offset: 78 (0x4E) + uint32_t compute_user_data_14; // offset: 79 (0x4F) + uint32_t compute_user_data_15; // offset: 80 (0x50) + uint32_t compute_user_data_16; // offset: 81 (0x51) + uint32_t compute_user_data_17; // offset: 82 (0x52) + uint32_t compute_user_data_18; // offset: 83 (0x53) + uint32_t compute_user_data_19; // offset: 84 (0x54) + uint32_t compute_user_data_20; // offset: 85 (0x55) + uint32_t compute_user_data_21; // offset: 86 (0x56) + uint32_t compute_user_data_22; // offset: 87 (0x57) + uint32_t compute_user_data_23; // offset: 88 (0x58) + uint32_t compute_user_data_24; // offset: 89 (0x59) + uint32_t compute_user_data_25; // offset: 90 (0x5A) + uint32_t compute_user_data_26; // offset: 91 (0x5B) + uint32_t compute_user_data_27; // offset: 92 (0x5C) + uint32_t compute_user_data_28; // offset: 93 (0x5D) + uint32_t compute_user_data_29; // offset: 94 (0x5E) + uint32_t compute_user_data_30; // offset: 95 (0x5F) + uint32_t compute_user_data_31; // offset: 96 (0x60) + uint32_t cp_compute_csinvoc_count_lo; // offset: 97 (0x61) + uint32_t cp_compute_csinvoc_count_hi; // offset: 98 (0x62) + uint32_t reserved_99; // offset: 99 (0x63) + uint32_t reserved_100; // offset: 100 (0x64) + uint32_t reserved_101; // offset: 101 (0x65) + uint32_t reserved_102; // offset: 102 (0x66) + uint32_t reserved_103; // offset: 103 (0x67) + uint32_t reserved_104; // offset: 104 (0x68) + uint32_t reserved_105; // offset: 105 (0x69) + uint32_t reserved_106; // offset: 106 (0x6A) + uint32_t reserved_107; // offset: 107 (0x6B) + uint32_t reserved_108; // offset: 108 (0x6C) + uint32_t reserved_109; // offset: 109 (0x6D) + uint32_t compute_relaunch; // offset: 110 (0x6E) + uint32_t compute_wave_restore_addr_lo; // offset: 111 (0x6F) + uint32_t compute_wave_restore_addr_hi; // offset: 112 (0x70) + uint32_t compute_relaunch2; // offset: 113 (0x71) + uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) + uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) + uint32_t cp_packet_id_lo; // offset: 116 (0x74) + uint32_t cp_packet_id_hi; // offset: 117 (0x75) + uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) + uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) + uint32_t reserved_120; // offset: 120 (0x78) + uint32_t reserved_121; // offset: 121 (0x79) + uint32_t reserved_122; // offset: 122 (0x7A) + uint32_t reserved_123; // offset: 123 (0x7B) + uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) + uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) + uint32_t reserved_126; // offset: 126 (0x7E) + uint32_t reserved_127; // offset: 127 (0x7F) + uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) + uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) + uint32_t cp_hqd_active; // offset: 130 (0x82) + uint32_t cp_hqd_vmid; // offset: 131 (0x83) + uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) + uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) + uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) + uint32_t cp_hqd_quantum; // offset: 135 (0x87) + uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) + uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) + uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) + uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) + uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) + uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) + uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) + uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) + uint32_t reserved_144; // offset: 144 (0x90) + uint32_t cp_hqd_pq_control; // offset: 145 (0x91) + uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) + uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) + uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) + uint32_t cp_hqd_ib_control; // offset: 149 (0x95) + uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) + uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) + uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) + uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) + uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) + uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) + uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) + uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) + uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) + uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) + uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) + uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) + uint32_t cp_mqd_control; // offset: 162 (0xA2) + uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) + uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) + uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) + uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) + uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) + uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) + uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) + uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) + uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) + uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) + uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) + uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) + uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) + uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) + uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) + uint32_t reserved_178; // offset: 178 (0xB2) + uint32_t cp_hqd_error; // offset: 179 (0xB3) + uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) + uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) + uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) + uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) + uint32_t cp_hqd_suspend_cntl_stack_offset; // offset: 184 (0xB8) + uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; // offset: 185 (0xB9) + uint32_t cp_hqd_suspend_wg_state_offset; // offset: 186 (0xBA) + uint32_t cp_hqd_ddid_rptr; // offset: 187 (0xBB) + uint32_t cp_hqd_ddid_wptr; // offset: 188 (0xBC) + uint32_t cp_hqd_ddid_inflight_count; // offset: 189 (0xBD) + uint32_t cp_hqd_ddid_delta_rpt_count; // offset: 190 (0xBE) + uint32_t cp_hqd_dequeue_status; // offset: 191 (0xBF) + uint32_t cp_hqd_aql_control_1; // offset: 192 (0xC0) + uint32_t cp_hqd_aql_dispatch_id; // offset: 193 (0xC1) + uint32_t cp_hqd_aql_dispatch_id_hi; // offset: 194 (0xC2) + uint32_t cp_hqd_kd_base; // offset: 195 (0xC3) + uint32_t cp_hqd_kd_base_hi; // offset: 196 (0xC4) + uint32_t cp_hqd_kd_cntl; // offset: 197 (0xC5) + uint32_t reserved_198; // offset: 198 (0xC6) + uint32_t reserved_199; // offset: 199 (0xC7) + uint32_t reserved_200; // offset: 200 (0xC8) + uint32_t reserved_201; // offset: 201 (0xC9) + uint32_t reserved_202; // offset: 202 (0xCA) + uint32_t reserved_203; // offset: 203 (0xCB) + uint32_t reserved_204; // offset: 204 (0xCC) + uint32_t reserved_205; // offset: 205 (0xCD) + uint32_t reserved_206; // offset: 206 (0xCE) + uint32_t reserved_207; // offset: 207 (0xCF) + uint32_t reserved_208; // offset: 208 (0xD0) + uint32_t reserved_209; // offset: 209 (0xD1) + uint32_t reserved_210; // offset: 210 (0xD2) + uint32_t reserved_211; // offset: 211 (0xD3) + uint32_t reserved_212; // offset: 212 (0xD4) + uint32_t reserved_213; // offset: 213 (0xD5) + uint32_t reserved_214; // offset: 214 (0xD6) + uint32_t reserved_215; // offset: 215 (0xD7) + uint32_t reserved_216; // offset: 216 (0xD8) + uint32_t reserved_217; // offset: 217 (0xD9) + uint32_t reserved_218; // offset: 218 (0xDA) + uint32_t reserved_219; // offset: 219 (0xDB) + uint32_t reserved_220; // offset: 220 (0xDC) + uint32_t reserved_221; // offset: 221 (0xDD) + uint32_t reserved_222; // offset: 222 (0xDE) + uint32_t reserved_223; // offset: 223 (0xDF) + uint32_t reserved_224; // offset: 224 (0xE0) + uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1) + uint32_t cp_mqd_stride_size; // offset: 226 (0xE2) + uint32_t xcc_sync_counter; // offset: 227 (0xE3) + uint32_t set_resources_header; // offset: 228 (0xE4) + uint32_t set_resources_dw1; // offset: 229 (0xE5) + uint32_t set_resources_dw2; // offset: 230 (0xE6) + uint32_t set_resources_dw3; // offset: 231 (0xE7) + uint32_t set_resources_dw4; // offset: 232 (0xE8) + uint32_t set_resources_dw5; // offset: 233 (0xE9) + uint32_t set_resources_dw6; // offset: 234 (0xEA) + uint32_t set_resources_dw7; // offset: 235 (0xEB) + uint32_t reserved_236; // offset: 236 (0xEC) + uint32_t reserved_237; // offset: 237 (0xED) + uint32_t reserved_238; // offset: 238 (0xEE) + uint32_t reserved_239; // offset: 239 (0xEF) + uint32_t reserved_240; // offset: 240 (0xF0) + uint32_t reserved_241; // offset: 241 (0xF1) + uint32_t reserved_242; // offset: 242 (0xF2) + uint32_t reserved_243; // offset: 243 (0xF3) + uint32_t reserved_244; // offset: 244 (0xF4) + uint32_t reserved_245; // offset: 245 (0xF5) + uint32_t reserved_246; // offset: 246 (0xF6) + uint32_t reserved_247; // offset: 247 (0xF7) + uint32_t reserved_248; // offset: 248 (0xF8) + uint32_t reserved_249; // offset: 249 (0xF9) + uint32_t reserved_250; // offset: 250 (0xFA) + uint32_t reserved_251; // offset: 251 (0xFB) + uint32_t reserved_252; // offset: 252 (0xFC) + uint32_t reserved_253; // offset: 253 (0xFD) + uint32_t reserved_254; // offset: 254 (0xFE) + uint32_t reserved_255; // offset: 255 (0xFF) + uint32_t control_buf_addr_lo; // offset: 256 (0x100) + uint32_t control_buf_addr_hi; // offset: 257 (0x101) + uint32_t control_buf_wptr_lo; // offset: 258 (0x102) + uint32_t control_buf_wptr_hi; // offset: 259 (0x103) + uint32_t control_buf_dptr_lo; // offset: 260 (0x104) + uint32_t control_buf_dptr_hi; // offset: 261 (0x105) + uint32_t draw_ring_addr_lo; // offset: 262 (0x106) + uint32_t draw_ring_addr_hi; // offset: 263 (0x107) + uint32_t control_buf_num_entries; // offset: 264 (0x108) + uint32_t reserved_265; // offset: 265 (0x109) + uint32_t reserved_266; // offset: 266 (0x10A) + uint32_t reserved_267; // offset: 267 (0x10B) + uint32_t reserved_268; // offset: 268 (0x10C) + uint32_t reserved_269; // offset: 269 (0x10D) + uint32_t reserved_270; // offset: 270 (0x10E) + uint32_t reserved_271; // offset: 271 (0x10F) + uint32_t dfwx_flags; // offset: 272 (0x110) + uint32_t dfwx_slot; // offset: 273 (0x111) + uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) + uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) + uint32_t dfwx_queue_connect_addr_lo; // offset: 276 (0x114) + uint32_t dfwx_queue_connect_addr_hi; // offset: 277 (0x115) + uint32_t reserved_278; // offset: 278 (0x116) + uint32_t reserved_279; // offset: 279 (0x117) + uint32_t reserved_280; // offset: 280 (0x118) + uint32_t reserved_281; // offset: 281 (0x119) + uint32_t reserved_282; // offset: 282 (0x11A) + uint32_t reserved_283; // offset: 283 (0x11B) + uint32_t reserved_284; // offset: 284 (0x11C) + uint32_t reserved_285; // offset: 285 (0x11D) + uint32_t reserved_286; // offset: 286 (0x11E) + uint32_t reserved_287; // offset: 287 (0x11F) + uint32_t cp_mqd_query_time_lo; // offset: 288 (0x120) + uint32_t cp_mqd_query_time_hi; // offset: 289 (0x121) + uint32_t cp_mqd_connect_start_time_lo; // offset: 290 (0x122) + uint32_t cp_mqd_connect_start_time_hi; // offset: 291 (0x123) + uint32_t cp_mqd_connect_end_time_lo; // offset: 292 (0x124) + uint32_t cp_mqd_connect_end_time_hi; // offset: 293 (0x125) + uint32_t cp_mqd_connect_end_wf_count; // offset: 294 (0x126) + uint32_t cp_mqd_connect_end_pq_rptr; // offset: 295 (0x127) + uint32_t cp_mqd_connect_end_pq_wptr; // offset: 296 (0x128) + uint32_t cp_mqd_connect_end_ib_rptr; // offset: 297 (0x129) + uint32_t cp_mqd_readindex_lo; // offset: 298 (0x12A) + uint32_t cp_mqd_readindex_hi; // offset: 299 (0x12B) + uint32_t cp_mqd_save_start_time_lo; // offset: 300 (0x12C) + uint32_t cp_mqd_save_start_time_hi; // offset: 301 (0x12D) + uint32_t cp_mqd_save_end_time_lo; // offset: 302 (0x12E) + uint32_t cp_mqd_save_end_time_hi; // offset: 303 (0x12F) + uint32_t cp_mqd_restore_start_time_lo; // offset: 304 (0x130) + uint32_t cp_mqd_restore_start_time_hi; // offset: 305 (0x131) + uint32_t cp_mqd_restore_end_time_lo; // offset: 306 (0x132) + uint32_t cp_mqd_restore_end_time_hi; // offset: 307 (0x133) + uint32_t disable_queue; // offset: 308 (0x134) + uint32_t reserved_309; // offset: 309 (0x135) + uint32_t reserved_310; // offset: 310 (0x136) + uint32_t reserved_311; // offset: 311 (0x137) + uint32_t reserved_312; // offset: 312 (0x138) + uint32_t reserved_313; // offset: 313 (0x139) + uint32_t reserved_314; // offset: 314 (0x13A) + uint32_t reserved_315; // offset: 315 (0x13B) + uint32_t reserved_316; // offset: 316 (0x13C) + uint32_t reserved_317; // offset: 317 (0x13D) + uint32_t reserved_318; // offset: 318 (0x13E) + uint32_t reserved_319; // offset: 319 (0x13F) + uint32_t reserved_320; // offset: 320 (0x140) + uint32_t reserved_321; // offset: 321 (0x141) + uint32_t reserved_322; // offset: 322 (0x142) + uint32_t reserved_323; // offset: 323 (0x143) + uint32_t reserved_324; // offset: 324 (0x144) + uint32_t reserved_325; // offset: 325 (0x145) + uint32_t reserved_326; // offset: 326 (0x146) + uint32_t reserved_327; // offset: 327 (0x147) + uint32_t reserved_328; // offset: 328 (0x148) + uint32_t reserved_329; // offset: 329 (0x149) + uint32_t reserved_330; // offset: 330 (0x14A) + uint32_t reserved_331; // offset: 331 (0x14B) + uint32_t reserved_332; // offset: 332 (0x14C) + uint32_t reserved_333; // offset: 333 (0x14D) + uint32_t reserved_334; // offset: 334 (0x14E) + uint32_t reserved_335; // offset: 335 (0x14F) + uint32_t reserved_336; // offset: 336 (0x150) + uint32_t reserved_337; // offset: 337 (0x151) + uint32_t reserved_338; // offset: 338 (0x152) + uint32_t reserved_339; // offset: 339 (0x153) + uint32_t reserved_340; // offset: 340 (0x154) + uint32_t reserved_341; // offset: 341 (0x155) + uint32_t reserved_342; // offset: 342 (0x156) + uint32_t reserved_343; // offset: 343 (0x157) + uint32_t reserved_344; // offset: 344 (0x158) + uint32_t reserved_345; // offset: 345 (0x159) + uint32_t reserved_346; // offset: 346 (0x15A) + uint32_t reserved_347; // offset: 347 (0x15B) + uint32_t reserved_348; // offset: 348 (0x15C) + uint32_t reserved_349; // offset: 349 (0x15D) + uint32_t reserved_350; // offset: 350 (0x15E) + uint32_t reserved_351; // offset: 351 (0x15F) + uint32_t reserved_352; // offset: 352 (0x160) + uint32_t reserved_353; // offset: 353 (0x161) + uint32_t reserved_354; // offset: 354 (0x162) + uint32_t reserved_355; // offset: 355 (0x163) + uint32_t reserved_356; // offset: 356 (0x164) + uint32_t reserved_357; // offset: 357 (0x165) + uint32_t reserved_358; // offset: 358 (0x166) + uint32_t reserved_359; // offset: 359 (0x167) + uint32_t reserved_360; // offset: 360 (0x168) + uint32_t reserved_361; // offset: 361 (0x169) + uint32_t reserved_362; // offset: 362 (0x16A) + uint32_t reserved_363; // offset: 363 (0x16B) + uint32_t reserved_364; // offset: 364 (0x16C) + uint32_t reserved_365; // offset: 365 (0x16D) + uint32_t reserved_366; // offset: 366 (0x16E) + uint32_t reserved_367; // offset: 367 (0x16F) + uint32_t reserved_368; // offset: 368 (0x170) + uint32_t reserved_369; // offset: 369 (0x171) + uint32_t reserved_370; // offset: 370 (0x172) + uint32_t reserved_371; // offset: 371 (0x173) + uint32_t reserved_372; // offset: 372 (0x174) + uint32_t reserved_373; // offset: 373 (0x175) + uint32_t reserved_374; // offset: 374 (0x176) + uint32_t reserved_375; // offset: 375 (0x177) + uint32_t reserved_376; // offset: 376 (0x178) + uint32_t reserved_377; // offset: 377 (0x179) + uint32_t reserved_378; // offset: 378 (0x17A) + uint32_t reserved_379; // offset: 379 (0x17B) + uint32_t reserved_380; // offset: 380 (0x17C) + uint32_t reserved_381; // offset: 381 (0x17D) + uint32_t reserved_382; // offset: 382 (0x17E) + uint32_t reserved_383; // offset: 383 (0x17F) + uint32_t iqtimer_pkt_header; // offset: 384 (0x180) + uint32_t iqtimer_pkt_dw0; // offset: 385 (0x181) + uint32_t iqtimer_pkt_dw1; // offset: 386 (0x182) + uint32_t iqtimer_pkt_dw2; // offset: 387 (0x183) + uint32_t iqtimer_pkt_dw3; // offset: 388 (0x184) + uint32_t iqtimer_pkt_dw4; // offset: 389 (0x185) + uint32_t iqtimer_pkt_dw5; // offset: 390 (0x186) + uint32_t iqtimer_pkt_dw6; // offset: 391 (0x187) + uint32_t iqtimer_pkt_dw7; // offset: 392 (0x188) + uint32_t iqtimer_pkt_dw8; // offset: 393 (0x189) + uint32_t iqtimer_pkt_dw9; // offset: 394 (0x18A) + uint32_t iqtimer_pkt_dw10; // offset: 395 (0x18B) + uint32_t iqtimer_pkt_dw11; // offset: 396 (0x18C) + uint32_t iqtimer_pkt_dw12; // offset: 397 (0x18D) + uint32_t iqtimer_pkt_dw13; // offset: 398 (0x18E) + uint32_t iqtimer_pkt_dw14; // offset: 399 (0x18F) + uint32_t iqtimer_pkt_dw15; // offset: 400 (0x190) + uint32_t iqtimer_pkt_dw16; // offset: 401 (0x191) + uint32_t iqtimer_pkt_dw17; // offset: 402 (0x192) + uint32_t iqtimer_pkt_dw18; // offset: 403 (0x193) + uint32_t iqtimer_pkt_dw19; // offset: 404 (0x194) + uint32_t iqtimer_pkt_dw20; // offset: 405 (0x195) + uint32_t iqtimer_pkt_dw21; // offset: 406 (0x196) + uint32_t iqtimer_pkt_dw22; // offset: 407 (0x197) + uint32_t iqtimer_pkt_dw23; // offset: 408 (0x198) + uint32_t iqtimer_pkt_dw24; // offset: 409 (0x199) + uint32_t iqtimer_pkt_dw25; // offset: 410 (0x19A) + uint32_t iqtimer_pkt_dw26; // offset: 411 (0x19B) + uint32_t iqtimer_pkt_dw27; // offset: 412 (0x19C) + uint32_t iqtimer_pkt_dw28; // offset: 413 (0x19D) + uint32_t iqtimer_pkt_dw29; // offset: 414 (0x19E) + uint32_t iqtimer_pkt_dw30; // offset: 415 (0x19F) + uint32_t iqtimer_pkt_dw31; // offset: 416 (0x1A0) + uint32_t reserved_417; // offset: 417 (0x1A1) + uint32_t reserved_418; // offset: 418 (0x1A2) + uint32_t reserved_419; // offset: 419 (0x1A3) + uint32_t reserved_420; // offset: 420 (0x1A4) + uint32_t reserved_421; // offset: 421 (0x1A5) + uint32_t reserved_422; // offset: 422 (0x1A6) + uint32_t reserved_423; // offset: 423 (0x1A7) + uint32_t reserved_424; // offset: 424 (0x1A8) + uint32_t reserved_425; // offset: 425 (0x1A9) + uint32_t reserved_426; // offset: 426 (0x1AA) + uint32_t reserved_427; // offset: 427 (0x1AB) + uint32_t reserved_428; // offset: 428 (0x1AC) + uint32_t reserved_429; // offset: 429 (0x1AD) + uint32_t reserved_430; // offset: 430 (0x1AE) + uint32_t reserved_431; // offset: 431 (0x1AF) + uint32_t reserved_432; // offset: 432 (0x1B0) + uint32_t reserved_433; // offset: 433 (0x1B1) + uint32_t reserved_434; // offset: 434 (0x1B2) + uint32_t reserved_435; // offset: 435 (0x1B3) + uint32_t reserved_436; // offset: 436 (0x1B4) + uint32_t reserved_437; // offset: 437 (0x1B5) + uint32_t reserved_438; // offset: 438 (0x1B6) + uint32_t reserved_439; // offset: 439 (0x1B7) + uint32_t reserved_440; // offset: 440 (0x1B8) + uint32_t reserved_441; // offset: 441 (0x1B9) + uint32_t reserved_442; // offset: 442 (0x1BA) + uint32_t reserved_443; // offset: 443 (0x1BB) + uint32_t reserved_444; // offset: 444 (0x1BC) + uint32_t reserved_445; // offset: 445 (0x1BD) + uint32_t reserved_446; // offset: 446 (0x1BE) + uint32_t reserved_447; // offset: 447 (0x1BF) + uint32_t reserved_448; // offset: 448 (0x1C0) + uint32_t reserved_449; // offset: 449 (0x1C1) + uint32_t reserved_450; // offset: 450 (0x1C2) + uint32_t reserved_451; // offset: 451 (0x1C3) + uint32_t reserved_452; // offset: 452 (0x1C4) + uint32_t reserved_453; // offset: 453 (0x1C5) + uint32_t reserved_454; // offset: 454 (0x1C6) + uint32_t reserved_455; // offset: 455 (0x1C7) + uint32_t reserved_456; // offset: 456 (0x1C8) + uint32_t reserved_457; // offset: 457 (0x1C9) + uint32_t reserved_458; // offset: 458 (0x1CA) + uint32_t reserved_459; // offset: 459 (0x1CB) + uint32_t reserved_460; // offset: 460 (0x1CC) + uint32_t reserved_461; // offset: 461 (0x1CD) + uint32_t reserved_462; // offset: 462 (0x1CE) + uint32_t reserved_463; // offset: 463 (0x1CF) + uint32_t reserved_464; // offset: 464 (0x1D0) + uint32_t reserved_465; // offset: 465 (0x1D1) + uint32_t reserved_466; // offset: 466 (0x1D2) + uint32_t reserved_467; // offset: 467 (0x1D3) + uint32_t reserved_468; // offset: 468 (0x1D4) + uint32_t reserved_469; // offset: 469 (0x1D5) + uint32_t reserved_470; // offset: 470 (0x1D6) + uint32_t reserved_471; // offset: 471 (0x1D7) + uint32_t reserved_472; // offset: 472 (0x1D8) + uint32_t reserved_473; // offset: 473 (0x1D9) + uint32_t reserved_474; // offset: 474 (0x1DA) + uint32_t reserved_475; // offset: 475 (0x1DB) + uint32_t reserved_476; // offset: 476 (0x1DC) + uint32_t reserved_477; // offset: 477 (0x1DD) + uint32_t reserved_478; // offset: 478 (0x1DE) + uint32_t reserved_479; // offset: 479 (0x1DF) + uint32_t reserved_480; // offset: 480 (0x1E0) + uint32_t reserved_481; // offset: 481 (0x1E1) + uint32_t reserved_482; // offset: 482 (0x1E2) + uint32_t reserved_483; // offset: 483 (0x1E3) + uint32_t reserved_484; // offset: 484 (0x1E4) + uint32_t reserved_485; // offset: 485 (0x1E5) + uint32_t reserved_486; // offset: 486 (0x1E6) + uint32_t reserved_487; // offset: 487 (0x1E7) + uint32_t reserved_488; // offset: 488 (0x1E8) + uint32_t reserved_489; // offset: 489 (0x1E9) + uint32_t reserved_490; // offset: 490 (0x1EA) + uint32_t reserved_491; // offset: 491 (0x1EB) + uint32_t reserved_492; // offset: 492 (0x1EC) + uint32_t reserved_493; // offset: 493 (0x1ED) + uint32_t reserved_494; // offset: 494 (0x1EE) + uint32_t reserved_495; // offset: 495 (0x1EF) + uint32_t reserved_496; // offset: 496 (0x1F0) + uint32_t reserved_497; // offset: 497 (0x1F1) + uint32_t reserved_498; // offset: 498 (0x1F2) + uint32_t reserved_499; // offset: 499 (0x1F3) + uint32_t reserved_500; // offset: 500 (0x1F4) + uint32_t reserved_501; // offset: 501 (0x1F5) + uint32_t reserved_502; // offset: 502 (0x1F6) + uint32_t reserved_503; // offset: 503 (0x1F7) + uint32_t reserved_504; // offset: 504 (0x1F8) + uint32_t reserved_505; // offset: 505 (0x1F9) + uint32_t reserved_506; // offset: 506 (0x1FA) + uint32_t reserved_507; // offset: 507 (0x1FB) + uint32_t reserved_508; // offset: 508 (0x1FC) + uint32_t reserved_509; // offset: 509 (0x1FD) + uint32_t reserved_510; // offset: 510 (0x1FE) + uint32_t reserved_511; // offset: 511 (0x1FF) + uint32_t reserved_512; // offset: 512 (0x200) + uint32_t reserved_513; // offset: 513 (0x201) + uint32_t reserved_514; // offset: 514 (0x202) + uint32_t reserved_515; // offset: 515 (0x203) + uint32_t reserved_516; // offset: 516 (0x204) + uint32_t reserved_517; // offset: 517 (0x205) + uint32_t reserved_518; // offset: 518 (0x206) + uint32_t reserved_519; // offset: 519 (0x207) + uint32_t reserved_520; // offset: 520 (0x208) + uint32_t reserved_521; // offset: 521 (0x209) + uint32_t reserved_522; // offset: 522 (0x20A) + uint32_t reserved_523; // offset: 523 (0x20B) + uint32_t reserved_524; // offset: 524 (0x20C) + uint32_t reserved_525; // offset: 525 (0x20D) + uint32_t reserved_526; // offset: 526 (0x20E) + uint32_t reserved_527; // offset: 527 (0x20F) + uint32_t reserved_528; // offset: 528 (0x210) + uint32_t reserved_529; // offset: 529 (0x211) + uint32_t reserved_530; // offset: 530 (0x212) + uint32_t reserved_531; // offset: 531 (0x213) + uint32_t reserved_532; // offset: 532 (0x214) + uint32_t reserved_533; // offset: 533 (0x215) + uint32_t reserved_534; // offset: 534 (0x216) + uint32_t reserved_535; // offset: 535 (0x217) + uint32_t reserved_536; // offset: 536 (0x218) + uint32_t reserved_537; // offset: 537 (0x219) + uint32_t reserved_538; // offset: 538 (0x21A) + uint32_t reserved_539; // offset: 539 (0x21B) + uint32_t reserved_540; // offset: 540 (0x21C) + uint32_t reserved_541; // offset: 541 (0x21D) + uint32_t reserved_542; // offset: 542 (0x21E) + uint32_t reserved_543; // offset: 543 (0x21F) + uint32_t reserved_544; // offset: 544 (0x220) + uint32_t reserved_545; // offset: 545 (0x221) + uint32_t reserved_546; // offset: 546 (0x222) + uint32_t reserved_547; // offset: 547 (0x223) + uint32_t reserved_548; // offset: 548 (0x224) + uint32_t reserved_549; // offset: 549 (0x225) + uint32_t reserved_550; // offset: 550 (0x226) + uint32_t reserved_551; // offset: 551 (0x227) + uint32_t reserved_552; // offset: 552 (0x228) + uint32_t reserved_553; // offset: 553 (0x229) + uint32_t reserved_554; // offset: 554 (0x22A) + uint32_t reserved_555; // offset: 555 (0x22B) + uint32_t reserved_556; // offset: 556 (0x22C) + uint32_t reserved_557; // offset: 557 (0x22D) + uint32_t reserved_558; // offset: 558 (0x22E) + uint32_t reserved_559; // offset: 559 (0x22F) + uint32_t reserved_560; // offset: 560 (0x230) + uint32_t reserved_561; // offset: 561 (0x231) + uint32_t reserved_562; // offset: 562 (0x232) + uint32_t reserved_563; // offset: 563 (0x233) + uint32_t reserved_564; // offset: 564 (0x234) + uint32_t reserved_565; // offset: 565 (0x235) + uint32_t reserved_566; // offset: 566 (0x236) + uint32_t reserved_567; // offset: 567 (0x237) + uint32_t reserved_568; // offset: 568 (0x238) + uint32_t reserved_569; // offset: 569 (0x239) + uint32_t reserved_570; // offset: 570 (0x23A) + uint32_t reserved_571; // offset: 571 (0x23B) + uint32_t reserved_572; // offset: 572 (0x23C) + uint32_t reserved_573; // offset: 573 (0x23D) + uint32_t reserved_574; // offset: 574 (0x23E) + uint32_t reserved_575; // offset: 575 (0x23F) + uint32_t reserved_576; // offset: 576 (0x240) + uint32_t reserved_577; // offset: 577 (0x241) + uint32_t reserved_578; // offset: 578 (0x242) + uint32_t reserved_579; // offset: 579 (0x243) + uint32_t reserved_580; // offset: 580 (0x244) + uint32_t reserved_581; // offset: 581 (0x245) + uint32_t reserved_582; // offset: 582 (0x246) + uint32_t reserved_583; // offset: 583 (0x247) + uint32_t reserved_584; // offset: 584 (0x248) + uint32_t reserved_585; // offset: 585 (0x249) + uint32_t reserved_586; // offset: 586 (0x24A) + uint32_t reserved_587; // offset: 587 (0x24B) + uint32_t reserved_588; // offset: 588 (0x24C) + uint32_t reserved_589; // offset: 589 (0x24D) + uint32_t reserved_590; // offset: 590 (0x24E) + uint32_t reserved_591; // offset: 591 (0x24F) + uint32_t reserved_592; // offset: 592 (0x250) + uint32_t reserved_593; // offset: 593 (0x251) + uint32_t reserved_594; // offset: 594 (0x252) + uint32_t reserved_595; // offset: 595 (0x253) + uint32_t reserved_596; // offset: 596 (0x254) + uint32_t reserved_597; // offset: 597 (0x255) + uint32_t reserved_598; // offset: 598 (0x256) + uint32_t reserved_599; // offset: 599 (0x257) + uint32_t reserved_600; // offset: 600 (0x258) + uint32_t reserved_601; // offset: 601 (0x259) + uint32_t reserved_602; // offset: 602 (0x25A) + uint32_t reserved_603; // offset: 603 (0x25B) + uint32_t reserved_604; // offset: 604 (0x25C) + uint32_t reserved_605; // offset: 605 (0x25D) + uint32_t reserved_606; // offset: 606 (0x25E) + uint32_t reserved_607; // offset: 607 (0x25F) + uint32_t reserved_608; // offset: 608 (0x260) + uint32_t reserved_609; // offset: 609 (0x261) + uint32_t reserved_610; // offset: 610 (0x262) + uint32_t reserved_611; // offset: 611 (0x263) + uint32_t reserved_612; // offset: 612 (0x264) + uint32_t reserved_613; // offset: 613 (0x265) + uint32_t reserved_614; // offset: 614 (0x266) + uint32_t reserved_615; // offset: 615 (0x267) + uint32_t reserved_616; // offset: 616 (0x268) + uint32_t reserved_617; // offset: 617 (0x269) + uint32_t reserved_618; // offset: 618 (0x26A) + uint32_t reserved_619; // offset: 619 (0x26B) + uint32_t reserved_620; // offset: 620 (0x26C) + uint32_t reserved_621; // offset: 621 (0x26D) + uint32_t reserved_622; // offset: 622 (0x26E) + uint32_t reserved_623; // offset: 623 (0x26F) + uint32_t reserved_624; // offset: 624 (0x270) + uint32_t reserved_625; // offset: 625 (0x271) + uint32_t reserved_626; // offset: 626 (0x272) + uint32_t reserved_627; // offset: 627 (0x273) + uint32_t reserved_628; // offset: 628 (0x274) + uint32_t reserved_629; // offset: 629 (0x275) + uint32_t reserved_630; // offset: 630 (0x276) + uint32_t reserved_631; // offset: 631 (0x277) + uint32_t reserved_632; // offset: 632 (0x278) + uint32_t reserved_633; // offset: 633 (0x279) + uint32_t reserved_634; // offset: 634 (0x27A) + uint32_t reserved_635; // offset: 635 (0x27B) + uint32_t reserved_636; // offset: 636 (0x27C) + uint32_t reserved_637; // offset: 637 (0x27D) + uint32_t reserved_638; // offset: 638 (0x27E) + uint32_t reserved_639; // offset: 639 (0x27F) + uint32_t reserved_640; // offset: 640 (0x280) + uint32_t reserved_641; // offset: 641 (0x281) + uint32_t reserved_642; // offset: 642 (0x282) + uint32_t reserved_643; // offset: 643 (0x283) + uint32_t reserved_644; // offset: 644 (0x284) + uint32_t reserved_645; // offset: 645 (0x285) + uint32_t reserved_646; // offset: 646 (0x286) + uint32_t reserved_647; // offset: 647 (0x287) + uint32_t reserved_648; // offset: 648 (0x288) + uint32_t reserved_649; // offset: 649 (0x289) + uint32_t reserved_650; // offset: 650 (0x28A) + uint32_t reserved_651; // offset: 651 (0x28B) + uint32_t reserved_652; // offset: 652 (0x28C) + uint32_t reserved_653; // offset: 653 (0x28D) + uint32_t reserved_654; // offset: 654 (0x28E) + uint32_t reserved_655; // offset: 655 (0x28F) + uint32_t reserved_656; // offset: 656 (0x290) + uint32_t reserved_657; // offset: 657 (0x291) + uint32_t reserved_658; // offset: 658 (0x292) + uint32_t reserved_659; // offset: 659 (0x293) + uint32_t reserved_660; // offset: 660 (0x294) + uint32_t reserved_661; // offset: 661 (0x295) + uint32_t reserved_662; // offset: 662 (0x296) + uint32_t reserved_663; // offset: 663 (0x297) + uint32_t reserved_664; // offset: 664 (0x298) + uint32_t reserved_665; // offset: 665 (0x299) + uint32_t reserved_666; // offset: 666 (0x29A) + uint32_t reserved_667; // offset: 667 (0x29B) + uint32_t reserved_668; // offset: 668 (0x29C) + uint32_t reserved_669; // offset: 669 (0x29D) + uint32_t reserved_670; // offset: 670 (0x29E) + uint32_t reserved_671; // offset: 671 (0x29F) + uint32_t reserved_672; // offset: 672 (0x2A0) + uint32_t reserved_673; // offset: 673 (0x2A1) + uint32_t reserved_674; // offset: 674 (0x2A2) + uint32_t reserved_675; // offset: 675 (0x2A3) + uint32_t reserved_676; // offset: 676 (0x2A4) + uint32_t reserved_677; // offset: 677 (0x2A5) + uint32_t reserved_678; // offset: 678 (0x2A6) + uint32_t reserved_679; // offset: 679 (0x2A7) + uint32_t reserved_680; // offset: 680 (0x2A8) + uint32_t reserved_681; // offset: 681 (0x2A9) + uint32_t reserved_682; // offset: 682 (0x2AA) + uint32_t reserved_683; // offset: 683 (0x2AB) + uint32_t reserved_684; // offset: 684 (0x2AC) + uint32_t reserved_685; // offset: 685 (0x2AD) + uint32_t reserved_686; // offset: 686 (0x2AE) + uint32_t reserved_687; // offset: 687 (0x2AF) + uint32_t reserved_688; // offset: 688 (0x2B0) + uint32_t reserved_689; // offset: 689 (0x2B1) + uint32_t reserved_690; // offset: 690 (0x2B2) + uint32_t reserved_691; // offset: 691 (0x2B3) + uint32_t reserved_692; // offset: 692 (0x2B4) + uint32_t reserved_693; // offset: 693 (0x2B5) + uint32_t reserved_694; // offset: 694 (0x2B6) + uint32_t reserved_695; // offset: 695 (0x2B7) + uint32_t reserved_696; // offset: 696 (0x2B8) + uint32_t reserved_697; // offset: 697 (0x2B9) + uint32_t reserved_698; // offset: 698 (0x2BA) + uint32_t reserved_699; // offset: 699 (0x2BB) + uint32_t reserved_700; // offset: 700 (0x2BC) + uint32_t reserved_701; // offset: 701 (0x2BD) + uint32_t reserved_702; // offset: 702 (0x2BE) + uint32_t reserved_703; // offset: 703 (0x2BF) + uint32_t reserved_704; // offset: 704 (0x2C0) + uint32_t reserved_705; // offset: 705 (0x2C1) + uint32_t reserved_706; // offset: 706 (0x2C2) + uint32_t reserved_707; // offset: 707 (0x2C3) + uint32_t reserved_708; // offset: 708 (0x2C4) + uint32_t reserved_709; // offset: 709 (0x2C5) + uint32_t reserved_710; // offset: 710 (0x2C6) + uint32_t reserved_711; // offset: 711 (0x2C7) + uint32_t reserved_712; // offset: 712 (0x2C8) + uint32_t reserved_713; // offset: 713 (0x2C9) + uint32_t reserved_714; // offset: 714 (0x2CA) + uint32_t reserved_715; // offset: 715 (0x2CB) + uint32_t reserved_716; // offset: 716 (0x2CC) + uint32_t reserved_717; // offset: 717 (0x2CD) + uint32_t reserved_718; // offset: 718 (0x2CE) + uint32_t reserved_719; // offset: 719 (0x2CF) + uint32_t reserved_720; // offset: 720 (0x2D0) + uint32_t reserved_721; // offset: 721 (0x2D1) + uint32_t reserved_722; // offset: 722 (0x2D2) + uint32_t reserved_723; // offset: 723 (0x2D3) + uint32_t reserved_724; // offset: 724 (0x2D4) + uint32_t reserved_725; // offset: 725 (0x2D5) + uint32_t reserved_726; // offset: 726 (0x2D6) + uint32_t reserved_727; // offset: 727 (0x2D7) + uint32_t reserved_728; // offset: 728 (0x2D8) + uint32_t reserved_729; // offset: 729 (0x2D9) + uint32_t reserved_730; // offset: 730 (0x2DA) + uint32_t reserved_731; // offset: 731 (0x2DB) + uint32_t reserved_732; // offset: 732 (0x2DC) + uint32_t reserved_733; // offset: 733 (0x2DD) + uint32_t reserved_734; // offset: 734 (0x2DE) + uint32_t reserved_735; // offset: 735 (0x2DF) + uint32_t reserved_736; // offset: 736 (0x2E0) + uint32_t reserved_737; // offset: 737 (0x2E1) + uint32_t reserved_738; // offset: 738 (0x2E2) + uint32_t reserved_739; // offset: 739 (0x2E3) + uint32_t reserved_740; // offset: 740 (0x2E4) + uint32_t reserved_741; // offset: 741 (0x2E5) + uint32_t reserved_742; // offset: 742 (0x2E6) + uint32_t reserved_743; // offset: 743 (0x2E7) + uint32_t reserved_744; // offset: 744 (0x2E8) + uint32_t reserved_745; // offset: 745 (0x2E9) + uint32_t reserved_746; // offset: 746 (0x2EA) + uint32_t reserved_747; // offset: 747 (0x2EB) + uint32_t reserved_748; // offset: 748 (0x2EC) + uint32_t reserved_749; // offset: 749 (0x2ED) + uint32_t reserved_750; // offset: 750 (0x2EE) + uint32_t reserved_751; // offset: 751 (0x2EF) + uint32_t reserved_752; // offset: 752 (0x2F0) + uint32_t reserved_753; // offset: 753 (0x2F1) + uint32_t reserved_754; // offset: 754 (0x2F2) + uint32_t reserved_755; // offset: 755 (0x2F3) + uint32_t reserved_756; // offset: 756 (0x2F4) + uint32_t reserved_757; // offset: 757 (0x2F5) + uint32_t reserved_758; // offset: 758 (0x2F6) + uint32_t reserved_759; // offset: 759 (0x2F7) + uint32_t reserved_760; // offset: 760 (0x2F8) + uint32_t reserved_761; // offset: 761 (0x2F9) + uint32_t reserved_762; // offset: 762 (0x2FA) + uint32_t reserved_763; // offset: 763 (0x2FB) + uint32_t reserved_764; // offset: 764 (0x2FC) + uint32_t reserved_765; // offset: 765 (0x2FD) + uint32_t reserved_766; // offset: 766 (0x2FE) + uint32_t reserved_767; // offset: 767 (0x2FF) + uint32_t reserved_768; // offset: 768 (0x300) + uint32_t reserved_769; // offset: 769 (0x301) + uint32_t reserved_770; // offset: 770 (0x302) + uint32_t reserved_771; // offset: 771 (0x303) + uint32_t reserved_772; // offset: 772 (0x304) + uint32_t reserved_773; // offset: 773 (0x305) + uint32_t reserved_774; // offset: 774 (0x306) + uint32_t reserved_775; // offset: 775 (0x307) + uint32_t reserved_776; // offset: 776 (0x308) + uint32_t reserved_777; // offset: 777 (0x309) + uint32_t reserved_778; // offset: 778 (0x30A) + uint32_t reserved_779; // offset: 779 (0x30B) + uint32_t reserved_780; // offset: 780 (0x30C) + uint32_t reserved_781; // offset: 781 (0x30D) + uint32_t reserved_782; // offset: 782 (0x30E) + uint32_t reserved_783; // offset: 783 (0x30F) + uint32_t reserved_784; // offset: 784 (0x310) + uint32_t reserved_785; // offset: 785 (0x311) + uint32_t reserved_786; // offset: 786 (0x312) + uint32_t reserved_787; // offset: 787 (0x313) + uint32_t reserved_788; // offset: 788 (0x314) + uint32_t reserved_789; // offset: 789 (0x315) + uint32_t reserved_790; // offset: 790 (0x316) + uint32_t reserved_791; // offset: 791 (0x317) + uint32_t reserved_792; // offset: 792 (0x318) + uint32_t reserved_793; // offset: 793 (0x319) + uint32_t reserved_794; // offset: 794 (0x31A) + uint32_t reserved_795; // offset: 795 (0x31B) + uint32_t reserved_796; // offset: 796 (0x31C) + uint32_t reserved_797; // offset: 797 (0x31D) + uint32_t reserved_798; // offset: 798 (0x31E) + uint32_t reserved_799; // offset: 799 (0x31F) + uint32_t reserved_800; // offset: 800 (0x320) + uint32_t reserved_801; // offset: 801 (0x321) + uint32_t reserved_802; // offset: 802 (0x322) + uint32_t reserved_803; // offset: 803 (0x323) + uint32_t reserved_804; // offset: 804 (0x324) + uint32_t reserved_805; // offset: 805 (0x325) + uint32_t reserved_806; // offset: 806 (0x326) + uint32_t reserved_807; // offset: 807 (0x327) + uint32_t reserved_808; // offset: 808 (0x328) + uint32_t reserved_809; // offset: 809 (0x329) + uint32_t reserved_810; // offset: 810 (0x32A) + uint32_t reserved_811; // offset: 811 (0x32B) + uint32_t reserved_812; // offset: 812 (0x32C) + uint32_t reserved_813; // offset: 813 (0x32D) + uint32_t reserved_814; // offset: 814 (0x32E) + uint32_t reserved_815; // offset: 815 (0x32F) + uint32_t reserved_816; // offset: 816 (0x330) + uint32_t reserved_817; // offset: 817 (0x331) + uint32_t reserved_818; // offset: 818 (0x332) + uint32_t reserved_819; // offset: 819 (0x333) + uint32_t reserved_820; // offset: 820 (0x334) + uint32_t reserved_821; // offset: 821 (0x335) + uint32_t reserved_822; // offset: 822 (0x336) + uint32_t reserved_823; // offset: 823 (0x337) + uint32_t reserved_824; // offset: 824 (0x338) + uint32_t reserved_825; // offset: 825 (0x339) + uint32_t reserved_826; // offset: 826 (0x33A) + uint32_t reserved_827; // offset: 827 (0x33B) + uint32_t reserved_828; // offset: 828 (0x33C) + uint32_t reserved_829; // offset: 829 (0x33D) + uint32_t reserved_830; // offset: 830 (0x33E) + uint32_t reserved_831; // offset: 831 (0x33F) + uint32_t reserved_832; // offset: 832 (0x340) + uint32_t reserved_833; // offset: 833 (0x341) + uint32_t reserved_834; // offset: 834 (0x342) + uint32_t reserved_835; // offset: 835 (0x343) + uint32_t reserved_836; // offset: 836 (0x344) + uint32_t reserved_837; // offset: 837 (0x345) + uint32_t reserved_838; // offset: 838 (0x346) + uint32_t reserved_839; // offset: 839 (0x347) + uint32_t reserved_840; // offset: 840 (0x348) + uint32_t reserved_841; // offset: 841 (0x349) + uint32_t reserved_842; // offset: 842 (0x34A) + uint32_t reserved_843; // offset: 843 (0x34B) + uint32_t reserved_844; // offset: 844 (0x34C) + uint32_t reserved_845; // offset: 845 (0x34D) + uint32_t reserved_846; // offset: 846 (0x34E) + uint32_t reserved_847; // offset: 847 (0x34F) + uint32_t reserved_848; // offset: 848 (0x350) + uint32_t reserved_849; // offset: 849 (0x351) + uint32_t reserved_850; // offset: 850 (0x352) + uint32_t reserved_851; // offset: 851 (0x353) + uint32_t reserved_852; // offset: 852 (0x354) + uint32_t reserved_853; // offset: 853 (0x355) + uint32_t reserved_854; // offset: 854 (0x356) + uint32_t reserved_855; // offset: 855 (0x357) + uint32_t reserved_856; // offset: 856 (0x358) + uint32_t reserved_857; // offset: 857 (0x359) + uint32_t reserved_858; // offset: 858 (0x35A) + uint32_t reserved_859; // offset: 859 (0x35B) + uint32_t reserved_860; // offset: 860 (0x35C) + uint32_t reserved_861; // offset: 861 (0x35D) + uint32_t reserved_862; // offset: 862 (0x35E) + uint32_t reserved_863; // offset: 863 (0x35F) + uint32_t reserved_864; // offset: 864 (0x360) + uint32_t reserved_865; // offset: 865 (0x361) + uint32_t reserved_866; // offset: 866 (0x362) + uint32_t reserved_867; // offset: 867 (0x363) + uint32_t reserved_868; // offset: 868 (0x364) + uint32_t reserved_869; // offset: 869 (0x365) + uint32_t reserved_870; // offset: 870 (0x366) + uint32_t reserved_871; // offset: 871 (0x367) + uint32_t reserved_872; // offset: 872 (0x368) + uint32_t reserved_873; // offset: 873 (0x369) + uint32_t reserved_874; // offset: 874 (0x36A) + uint32_t reserved_875; // offset: 875 (0x36B) + uint32_t reserved_876; // offset: 876 (0x36C) + uint32_t reserved_877; // offset: 877 (0x36D) + uint32_t reserved_878; // offset: 878 (0x36E) + uint32_t reserved_879; // offset: 879 (0x36F) + uint32_t reserved_880; // offset: 880 (0x370) + uint32_t reserved_881; // offset: 881 (0x371) + uint32_t reserved_882; // offset: 882 (0x372) + uint32_t reserved_883; // offset: 883 (0x373) + uint32_t reserved_884; // offset: 884 (0x374) + uint32_t reserved_885; // offset: 885 (0x375) + uint32_t reserved_886; // offset: 886 (0x376) + uint32_t reserved_887; // offset: 887 (0x377) + uint32_t reserved_888; // offset: 888 (0x378) + uint32_t reserved_889; // offset: 889 (0x379) + uint32_t reserved_890; // offset: 890 (0x37A) + uint32_t reserved_891; // offset: 891 (0x37B) + uint32_t reserved_892; // offset: 892 (0x37C) + uint32_t reserved_893; // offset: 893 (0x37D) + uint32_t reserved_894; // offset: 894 (0x37E) + uint32_t reserved_895; // offset: 895 (0x37F) + uint32_t reserved_896; // offset: 896 (0x380) + uint32_t reserved_897; // offset: 897 (0x381) + uint32_t reserved_898; // offset: 898 (0x382) + uint32_t reserved_899; // offset: 899 (0x383) + uint32_t reserved_900; // offset: 900 (0x384) + uint32_t reserved_901; // offset: 901 (0x385) + uint32_t reserved_902; // offset: 902 (0x386) + uint32_t reserved_903; // offset: 903 (0x387) + uint32_t reserved_904; // offset: 904 (0x388) + uint32_t reserved_905; // offset: 905 (0x389) + uint32_t reserved_906; // offset: 906 (0x38A) + uint32_t reserved_907; // offset: 907 (0x38B) + uint32_t reserved_908; // offset: 908 (0x38C) + uint32_t reserved_909; // offset: 909 (0x38D) + uint32_t reserved_910; // offset: 910 (0x38E) + uint32_t reserved_911; // offset: 911 (0x38F) + uint32_t reserved_912; // offset: 912 (0x390) + uint32_t reserved_913; // offset: 913 (0x391) + uint32_t reserved_914; // offset: 914 (0x392) + uint32_t reserved_915; // offset: 915 (0x393) + uint32_t reserved_916; // offset: 916 (0x394) + uint32_t reserved_917; // offset: 917 (0x395) + uint32_t reserved_918; // offset: 918 (0x396) + uint32_t reserved_919; // offset: 919 (0x397) + uint32_t reserved_920; // offset: 920 (0x398) + uint32_t reserved_921; // offset: 921 (0x399) + uint32_t reserved_922; // offset: 922 (0x39A) + uint32_t reserved_923; // offset: 923 (0x39B) + uint32_t reserved_924; // offset: 924 (0x39C) + uint32_t reserved_925; // offset: 925 (0x39D) + uint32_t reserved_926; // offset: 926 (0x39E) + uint32_t reserved_927; // offset: 927 (0x39F) + uint32_t reserved_928; // offset: 928 (0x3A0) + uint32_t reserved_929; // offset: 929 (0x3A1) + uint32_t reserved_930; // offset: 930 (0x3A2) + uint32_t reserved_931; // offset: 931 (0x3A3) + uint32_t reserved_932; // offset: 932 (0x3A4) + uint32_t reserved_933; // offset: 933 (0x3A5) + uint32_t reserved_934; // offset: 934 (0x3A6) + uint32_t reserved_935; // offset: 935 (0x3A7) + uint32_t reserved_936; // offset: 936 (0x3A8) + uint32_t reserved_937; // offset: 937 (0x3A9) + uint32_t reserved_938; // offset: 938 (0x3AA) + uint32_t reserved_939; // offset: 939 (0x3AB) + uint32_t reserved_940; // offset: 940 (0x3AC) + uint32_t reserved_941; // offset: 941 (0x3AD) + uint32_t reserved_942; // offset: 942 (0x3AE) + uint32_t reserved_943; // offset: 943 (0x3AF) + uint32_t reserved_944; // offset: 944 (0x3B0) + uint32_t reserved_945; // offset: 945 (0x3B1) + uint32_t reserved_946; // offset: 946 (0x3B2) + uint32_t reserved_947; // offset: 947 (0x3B3) + uint32_t reserved_948; // offset: 948 (0x3B4) + uint32_t reserved_949; // offset: 949 (0x3B5) + uint32_t reserved_950; // offset: 950 (0x3B6) + uint32_t reserved_951; // offset: 951 (0x3B7) + uint32_t reserved_952; // offset: 952 (0x3B8) + uint32_t reserved_953; // offset: 953 (0x3B9) + uint32_t reserved_954; // offset: 954 (0x3BA) + uint32_t reserved_955; // offset: 955 (0x3BB) + uint32_t reserved_956; // offset: 956 (0x3BC) + uint32_t reserved_957; // offset: 957 (0x3BD) + uint32_t reserved_958; // offset: 958 (0x3BE) + uint32_t reserved_959; // offset: 959 (0x3BF) + uint32_t reserved_960; // offset: 960 (0x3C0) + uint32_t reserved_961; // offset: 961 (0x3C1) + uint32_t reserved_962; // offset: 962 (0x3C2) + uint32_t reserved_963; // offset: 963 (0x3C3) + uint32_t reserved_964; // offset: 964 (0x3C4) + uint32_t reserved_965; // offset: 965 (0x3C5) + uint32_t reserved_966; // offset: 966 (0x3C6) + uint32_t reserved_967; // offset: 967 (0x3C7) + uint32_t reserved_968; // offset: 968 (0x3C8) + uint32_t reserved_969; // offset: 969 (0x3C9) + uint32_t reserved_970; // offset: 970 (0x3CA) + uint32_t reserved_971; // offset: 971 (0x3CB) + uint32_t reserved_972; // offset: 972 (0x3CC) + uint32_t reserved_973; // offset: 973 (0x3CD) + uint32_t reserved_974; // offset: 974 (0x3CE) + uint32_t reserved_975; // offset: 975 (0x3CF) + uint32_t reserved_976; // offset: 976 (0x3D0) + uint32_t reserved_977; // offset: 977 (0x3D1) + uint32_t reserved_978; // offset: 978 (0x3D2) + uint32_t reserved_979; // offset: 979 (0x3D3) + uint32_t reserved_980; // offset: 980 (0x3D4) + uint32_t reserved_981; // offset: 981 (0x3D5) + uint32_t reserved_982; // offset: 982 (0x3D6) + uint32_t reserved_983; // offset: 983 (0x3D7) + uint32_t reserved_984; // offset: 984 (0x3D8) + uint32_t reserved_985; // offset: 985 (0x3D9) + uint32_t reserved_986; // offset: 986 (0x3DA) + uint32_t reserved_987; // offset: 987 (0x3DB) + uint32_t reserved_988; // offset: 988 (0x3DC) + uint32_t reserved_989; // offset: 989 (0x3DD) + uint32_t reserved_990; // offset: 990 (0x3DE) + uint32_t reserved_991; // offset: 991 (0x3DF) + uint32_t reserved_992; // offset: 992 (0x3E0) + uint32_t reserved_993; // offset: 993 (0x3E1) + uint32_t reserved_994; // offset: 994 (0x3E2) + uint32_t reserved_995; // offset: 995 (0x3E3) + uint32_t reserved_996; // offset: 996 (0x3E4) + uint32_t reserved_997; // offset: 997 (0x3E5) + uint32_t reserved_998; // offset: 998 (0x3E6) + uint32_t reserved_999; // offset: 999 (0x3E7) + uint32_t reserved_1000; // offset: 1000 (0x3E8) + uint32_t reserved_1001; // offset: 1001 (0x3E9) + uint32_t reserved_1002; // offset: 1002 (0x3EA) + uint32_t reserved_1003; // offset: 1003 (0x3EB) + uint32_t reserved_1004; // offset: 1004 (0x3EC) + uint32_t reserved_1005; // offset: 1005 (0x3ED) + uint32_t reserved_1006; // offset: 1006 (0x3EE) + uint32_t reserved_1007; // offset: 1007 (0x3EF) + uint32_t reserved_1008; // offset: 1008 (0x3F0) + uint32_t reserved_1009; // offset: 1009 (0x3F1) + uint32_t reserved_1010; // offset: 1010 (0x3F2) + uint32_t reserved_1011; // offset: 1011 (0x3F3) + uint32_t reserved_1012; // offset: 1012 (0x3F4) + uint32_t reserved_1013; // offset: 1013 (0x3F5) + uint32_t reserved_1014; // offset: 1014 (0x3F6) + uint32_t reserved_1015; // offset: 1015 (0x3F7) + uint32_t reserved_1016; // offset: 1016 (0x3F8) + uint32_t reserved_1017; // offset: 1017 (0x3F9) + uint32_t reserved_1018; // offset: 1018 (0x3FA) + uint32_t reserved_1019; // offset: 1019 (0x3FB) + uint32_t reserved_1020; // offset: 1020 (0x3FC) + uint32_t reserved_1021; // offset: 1021 (0x3FD) + uint32_t reserved_1022; // offset: 1022 (0x3FE) + uint32_t reserved_1023; // offset: 1023 (0x3FF) +}; + +struct v12_1_mes_mqd { + uint32_t header; // offset: 0 (0x0) + uint32_t compute_dispatch_initiator; // offset: 1 (0x1) + uint32_t compute_dim_x; // offset: 2 (0x2) + uint32_t compute_dim_y; // offset: 3 (0x3) + uint32_t compute_dim_z; // offset: 4 (0x4) + uint32_t compute_start_x; // offset: 5 (0x5) + uint32_t compute_start_y; // offset: 6 (0x6) + uint32_t compute_start_z; // offset: 7 (0x7) + uint32_t compute_num_thread_x; // offset: 8 (0x8) + uint32_t compute_num_thread_y; // offset: 9 (0x9) + uint32_t compute_num_thread_z; // offset: 10 (0xA) + uint32_t compute_pipelinestat_enable; // offset: 11 (0xB) + uint32_t compute_perfcount_enable; // offset: 12 (0xC) + uint32_t compute_pgm_lo; // offset: 13 (0xD) + uint32_t compute_pgm_hi; // offset: 14 (0xE) + uint32_t compute_dispatch_pkt_addr_lo; // offset: 15 (0xF) + uint32_t compute_dispatch_pkt_addr_hi; // offset: 16 (0x10) + uint32_t compute_dispatch_scratch_base_lo; // offset: 17 (0x11) + uint32_t compute_dispatch_scratch_base_hi; // offset: 18 (0x12) + uint32_t compute_pgm_rsrc1; // offset: 19 (0x13) + uint32_t compute_pgm_rsrc2; // offset: 20 (0x14) + uint32_t compute_vmid; // offset: 21 (0x15) + uint32_t compute_resource_limits; // offset: 22 (0x16) + uint32_t compute_tmpring_size; // offset: 23 (0x17) + uint32_t compute_restart_x; // offset: 24 (0x18) + uint32_t compute_restart_y; // offset: 25 (0x19) + uint32_t compute_restart_z; // offset: 26 (0x1A) + uint32_t compute_thread_trace_enable; // offset: 27 (0x1B) + uint32_t compute_misc_reserved; // offset: 28 (0x1C) + uint32_t compute_dispatch_id; // offset: 29 (0x1D) + uint32_t compute_threadgroup_id; // offset: 30 (0x1E) + uint32_t compute_req_ctrl; // offset: 31 (0x1F) + uint32_t compute_user_accum_0; // offset: 32 (0x20) + uint32_t compute_user_accum_1; // offset: 33 (0x21) + uint32_t compute_user_accum_2; // offset: 34 (0x22) + uint32_t compute_user_accum_3; // offset: 35 (0x23) + uint32_t compute_pgm_rsrc3; // offset: 36 (0x24) + uint32_t compute_ddid_index; // offset: 37 (0x25) + uint32_t compute_shader_chksum; // offset: 38 (0x26) + uint32_t compute_dispatch_interleave; // offset: 39 (0x27) + uint32_t compute_current_logical_xcc_id; // offset: 40 (0x28) + uint32_t compute_restart_cg_tg_id; // offset: 41 (0x29) + uint32_t compute_tg_chunk_size; // offset: 42 (0x2A) + uint32_t compute_restore_tg_chunk_size; // offset: 43 (0x2B) + uint32_t compute_start_total_lo; // offset: 44 (0x2C) + uint32_t compute_start_total_hi; // offset: 45 (0x2D) + uint32_t compute_prescaled_dim_x; // offset: 46 (0x2E) + uint32_t compute_prescaled_dim_y; // offset: 47 (0x2F) + uint32_t compute_prescaled_dim_z; // offset: 48 (0x30) + uint32_t compute_static_thread_mgmt_se0; // offset: 49 (0x31) + uint32_t compute_static_thread_mgmt_se1; // offset: 50 (0x32) + uint32_t compute_static_thread_mgmt_se2; // offset: 51 (0x33) + uint32_t compute_static_thread_mgmt_se3; // offset: 52 (0x34) + uint32_t compute_static_thread_mgmt_se4; // offset: 53 (0x35) + uint32_t compute_static_thread_mgmt_se5; // offset: 54 (0x36) + uint32_t compute_static_thread_mgmt_se6; // offset: 55 (0x37) + uint32_t compute_static_thread_mgmt_se7; // offset: 56 (0x38) + uint32_t compute_static_thread_mgmt_se8; // offset: 57 (0x39) + uint32_t reserved_58; // offset: 58 (0x3A) + uint32_t reserved_59; // offset: 59 (0x3B) + uint32_t reserved_60; // offset: 60 (0x3C) + uint32_t reserved_61; // offset: 61 (0x3D) + uint32_t reserved_62; // offset: 62 (0x3E) + uint32_t reserved_63; // offset: 63 (0x3F) + uint32_t reserved_64; // offset: 64 (0x40) + uint32_t compute_user_data_0; // offset: 65 (0x41) + uint32_t compute_user_data_1; // offset: 66 (0x42) + uint32_t compute_user_data_2; // offset: 67 (0x43) + uint32_t compute_user_data_3; // offset: 68 (0x44) + uint32_t compute_user_data_4; // offset: 69 (0x45) + uint32_t compute_user_data_5; // offset: 70 (0x46) + uint32_t compute_user_data_6; // offset: 71 (0x47) + uint32_t compute_user_data_7; // offset: 72 (0x48) + uint32_t compute_user_data_8; // offset: 73 (0x49) + uint32_t compute_user_data_9; // offset: 74 (0x4A) + uint32_t compute_user_data_10; // offset: 75 (0x4B) + uint32_t compute_user_data_11; // offset: 76 (0x4C) + uint32_t compute_user_data_12; // offset: 77 (0x4D) + uint32_t compute_user_data_13; // offset: 78 (0x4E) + uint32_t compute_user_data_14; // offset: 79 (0x4F) + uint32_t compute_user_data_15; // offset: 80 (0x50) + uint32_t compute_user_data_16; // offset: 81 (0x51) + uint32_t compute_user_data_17; // offset: 82 (0x52) + uint32_t compute_user_data_18; // offset: 83 (0x53) + uint32_t compute_user_data_19; // offset: 84 (0x54) + uint32_t compute_user_data_20; // offset: 85 (0x55) + uint32_t compute_user_data_21; // offset: 86 (0x56) + uint32_t compute_user_data_22; // offset: 87 (0x57) + uint32_t compute_user_data_23; // offset: 88 (0x58) + uint32_t compute_user_data_24; // offset: 89 (0x59) + uint32_t compute_user_data_25; // offset: 90 (0x5A) + uint32_t compute_user_data_26; // offset: 91 (0x5B) + uint32_t compute_user_data_27; // offset: 92 (0x5C) + uint32_t compute_user_data_28; // offset: 93 (0x5D) + uint32_t compute_user_data_29; // offset: 94 (0x5E) + uint32_t compute_user_data_30; // offset: 95 (0x5F) + uint32_t compute_user_data_31; // offset: 96 (0x60) + uint32_t reserved_97; // offset: 97 (0x61) + uint32_t reserved_98; // offset: 98 (0x62) + uint32_t reserved_99; // offset: 99 (0x63) + uint32_t reserved_100; // offset: 100 (0x64) + uint32_t reserved_101; // offset: 101 (0x65) + uint32_t reserved_102; // offset: 102 (0x66) + uint32_t reserved_103; // offset: 103 (0x67) + uint32_t reserved_104; // offset: 104 (0x68) + uint32_t reserved_105; // offset: 105 (0x69) + uint32_t reserved_106; // offset: 106 (0x6A) + uint32_t reserved_107; // offset: 107 (0x6B) + uint32_t reserved_108; // offset: 108 (0x6C) + uint32_t reserved_109; // offset: 109 (0x6D) + uint32_t compute_relaunch; // offset: 110 (0x6E) + uint32_t compute_wave_restore_addr_lo; // offset: 111 (0x6F) + uint32_t compute_wave_restore_addr_hi; // offset: 112 (0x70) + uint32_t compute_relaunch2; // offset: 113 (0x71) + uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72) + uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73) + uint32_t cp_packet_id_lo; // offset: 116 (0x74) + uint32_t cp_packet_id_hi; // offset: 117 (0x75) + uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76) + uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77) + uint32_t reserved_120; // offset: 120 (0x78) + uint32_t reserved_121; // offset: 121 (0x79) + uint32_t reserved_122; // offset: 122 (0x7A) + uint32_t reserved_123; // offset: 123 (0x7B) + uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C) + uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D) + uint32_t reserved_126; // offset: 126 (0x7E) + uint32_t reserved_127; // offset: 127 (0x7F) + uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80) + uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81) + uint32_t cp_hqd_active; // offset: 130 (0x82) + uint32_t cp_hqd_vmid; // offset: 131 (0x83) + uint32_t cp_hqd_persistent_state; // offset: 132 (0x84) + uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85) + uint32_t cp_hqd_queue_priority; // offset: 134 (0x86) + uint32_t cp_hqd_quantum; // offset: 135 (0x87) + uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88) + uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89) + uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A) + uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B) + uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C) + uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D) + uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E) + uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F) + uint32_t reserved_144; // offset: 144 (0x90) + uint32_t cp_hqd_pq_control; // offset: 145 (0x91) + uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92) + uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93) + uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94) + uint32_t cp_hqd_ib_control; // offset: 149 (0x95) + uint32_t cp_hqd_iq_timer; // offset: 150 (0x96) + uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97) + uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98) + uint32_t cp_hqd_dma_offload; // offset: 153 (0x99) + uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A) + uint32_t cp_hqd_msg_type; // offset: 155 (0x9B) + uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C) + uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D) + uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E) + uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F) + uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0) + uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1) + uint32_t cp_mqd_control; // offset: 162 (0xA2) + uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3) + uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4) + uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5) + uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6) + uint32_t cp_hqd_eop_control; // offset: 167 (0xA7) + uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8) + uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9) + uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA) + uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB) + uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC) + uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD) + uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE) + uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF) + uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0) + uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1) + uint32_t reserved_178; // offset: 178 (0xB2) + uint32_t cp_hqd_error; // offset: 179 (0xB3) + uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4) + uint32_t cp_hqd_aql_control; // offset: 181 (0xB5) + uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6) + uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7) + uint32_t cp_hqd_gfx_control; // offset: 184 (0xB8) + uint32_t cp_hqd_suspend_cntl_stack_dw_cnt; // offset: 185 (0xB9) + uint32_t cp_hqd_suspend_wg_state_offset; // offset: 186 (0xBA) + uint32_t cp_hqd_ddid_rptr; // offset: 187 (0xBB) + uint32_t cp_hqd_ddid_wptr; // offset: 188 (0xBC) + uint32_t cp_hqd_ddid_inflight_count; // offset: 189 (0xBD) + uint32_t cp_hqd_ddid_delta_rpt_count; // offset: 190 (0xBE) + uint32_t cp_hqd_dequeue_status; // offset: 191 (0xBF) + uint32_t cp_hqd_aql_control_1; // offset: 192 (0xC0) + uint32_t cp_hqd_aql_dispatch_id; // offset: 193 (0xC1) + uint32_t cp_hqd_aql_dispatch_id_hi; // offset: 194 (0xC2) + uint32_t cp_hqd_kd_base; // offset: 195 (0xC3) + uint32_t cp_hqd_kd_base_hi; // offset: 196 (0xC4) + uint32_t cp_hqd_kd_cntl; // offset: 197 (0xC5) + uint32_t reserved_198; // offset: 198 (0xC6) + uint32_t reserved_199; // offset: 199 (0xC7) + uint32_t reserved_200; // offset: 200 (0xC8) + uint32_t reserved_201; // offset: 201 (0xC9) + uint32_t reserved_202; // offset: 202 (0xCA) + uint32_t reserved_203; // offset: 203 (0xCB) + uint32_t reserved_204; // offset: 204 (0xCC) + uint32_t reserved_205; // offset: 205 (0xCD) + uint32_t reserved_206; // offset: 206 (0xCE) + uint32_t reserved_207; // offset: 207 (0xCF) + uint32_t reserved_208; // offset: 208 (0xD0) + uint32_t reserved_209; // offset: 209 (0xD1) + uint32_t reserved_210; // offset: 210 (0xD2) + uint32_t reserved_211; // offset: 211 (0xD3) + uint32_t reserved_212; // offset: 212 (0xD4) + uint32_t reserved_213; // offset: 213 (0xD5) + uint32_t reserved_214; // offset: 214 (0xD6) + uint32_t reserved_215; // offset: 215 (0xD7) + uint32_t reserved_216; // offset: 216 (0xD8) + uint32_t reserved_217; // offset: 217 (0xD9) + uint32_t reserved_218; // offset: 218 (0xDA) + uint32_t reserved_219; // offset: 219 (0xDB) + uint32_t reserved_220; // offset: 220 (0xDC) + uint32_t reserved_221; // offset: 221 (0xDD) + uint32_t reserved_222; // offset: 222 (0xDE) + uint32_t reserved_223; // offset: 223 (0xDF) + uint32_t reserved_224; // offset: 224 (0xE0) + uint32_t pm4_target_xcc_in_xcp; // offset: 225 (0xE1) + uint32_t cp_mqd_stride_size; // offset: 226 (0xE2) + uint32_t xcc_sync_counter; // offset: 227 (0xE3) + uint32_t set_resources_header; // offset: 228 (0xE4) + uint32_t set_resources_dw1; // offset: 229 (0xE5) + uint32_t set_resources_dw2; // offset: 230 (0xE6) + uint32_t set_resources_dw3; // offset: 231 (0xE7) + uint32_t set_resources_dw4; // offset: 232 (0xE8) + uint32_t set_resources_dw5; // offset: 233 (0xE9) + uint32_t set_resources_dw6; // offset: 234 (0xEA) + uint32_t set_resources_dw7; // offset: 235 (0xEB) + uint32_t reserved_236; // offset: 236 (0xEC) + uint32_t reserved_237; // offset: 237 (0xED) + uint32_t reserved_238; // offset: 238 (0xEE) + uint32_t reserved_239; // offset: 239 (0xEF) + uint32_t reserved_240; // offset: 240 (0xF0) + uint32_t reserved_241; // offset: 241 (0xF1) + uint32_t reserved_242; // offset: 242 (0xF2) + uint32_t reserved_243; // offset: 243 (0xF3) + uint32_t reserved_244; // offset: 244 (0xF4) + uint32_t reserved_245; // offset: 245 (0xF5) + uint32_t reserved_246; // offset: 246 (0xF6) + uint32_t reserved_247; // offset: 247 (0xF7) + uint32_t reserved_248; // offset: 248 (0xF8) + uint32_t reserved_249; // offset: 249 (0xF9) + uint32_t reserved_250; // offset: 250 (0xFA) + uint32_t reserved_251; // offset: 251 (0xFB) + uint32_t reserved_252; // offset: 252 (0xFC) + uint32_t reserved_253; // offset: 253 (0xFD) + uint32_t reserved_254; // offset: 254 (0xFE) + uint32_t reserved_255; // offset: 255 (0xFF) + uint32_t control_buf_addr_lo; // offset: 256 (0x100) + uint32_t control_buf_addr_hi; // offset: 257 (0x101) + uint32_t control_buf_wptr_lo; // offset: 258 (0x102) + uint32_t control_buf_wptr_hi; // offset: 259 (0x103) + uint32_t control_buf_dptr_lo; // offset: 260 (0x104) + uint32_t control_buf_dptr_hi; // offset: 261 (0x105) + uint32_t draw_ring_addr_lo; // offset: 262 (0x106) + uint32_t draw_ring_addr_hi; // offset: 263 (0x107) + uint32_t control_buf_num_entries; // offset: 264 (0x108) + uint32_t reserved_265; // offset: 265 (0x109) + uint32_t reserved_266; // offset: 266 (0x10A) + uint32_t reserved_267; // offset: 267 (0x10B) + uint32_t reserved_268; // offset: 268 (0x10C) + uint32_t reserved_269; // offset: 269 (0x10D) + uint32_t reserved_270; // offset: 270 (0x10E) + uint32_t reserved_271; // offset: 271 (0x10F) + uint32_t dfwx_flags; // offset: 272 (0x110) + uint32_t dfwx_slot; // offset: 273 (0x111) + uint32_t dfwx_client_data_addr_lo; // offset: 274 (0x112) + uint32_t dfwx_client_data_addr_hi; // offset: 275 (0x113) + uint32_t dfwx_queue_connect_addr_lo; // offset: 276 (0x114) + uint32_t dfwx_queue_connect_addr_hi; // offset: 277 (0x115) + uint32_t reserved_278; // offset: 278 (0x116) + uint32_t reserved_279; // offset: 279 (0x117) + uint32_t reserved_280; // offset: 280 (0x118) + uint32_t reserved_281; // offset: 281 (0x119) + uint32_t reserved_282; // offset: 282 (0x11A) + uint32_t reserved_283; // offset: 283 (0x11B) + uint32_t reserved_284; // offset: 284 (0x11C) + uint32_t reserved_285; // offset: 285 (0x11D) + uint32_t reserved_286; // offset: 286 (0x11E) + uint32_t reserved_287; // offset: 287 (0x11F) + uint32_t cp_mqd_query_time_lo; // offset: 288 (0x120) + uint32_t cp_mqd_query_time_hi; // offset: 289 (0x121) + uint32_t cp_mqd_connect_start_time_lo; // offset: 290 (0x122) + uint32_t cp_mqd_connect_start_time_hi; // offset: 291 (0x123) + uint32_t cp_mqd_connect_end_time_lo; // offset: 292 (0x124) + uint32_t cp_mqd_connect_end_time_hi; // offset: 293 (0x125) + uint32_t cp_mqd_connect_end_wf_count; // offset: 294 (0x126) + uint32_t cp_mqd_connect_end_pq_rptr; // offset: 295 (0x127) + uint32_t cp_mqd_connect_end_pq_wptr; // offset: 296 (0x128) + uint32_t cp_mqd_connect_end_ib_rptr; // offset: 297 (0x129) + uint32_t cp_mqd_readindex_lo; // offset: 298 (0x12A) + uint32_t cp_mqd_readindex_hi; // offset: 299 (0x12B) + uint32_t cp_mqd_save_start_time_lo; // offset: 300 (0x12C) + uint32_t cp_mqd_save_start_time_hi; // offset: 301 (0x12D) + uint32_t cp_mqd_save_end_time_lo; // offset: 302 (0x12E) + uint32_t cp_mqd_save_end_time_hi; // offset: 303 (0x12F) + uint32_t cp_mqd_restore_start_time_lo; // offset: 304 (0x130) + uint32_t cp_mqd_restore_start_time_hi; // offset: 305 (0x131) + uint32_t cp_mqd_restore_end_time_lo; // offset: 306 (0x132) + uint32_t cp_mqd_restore_end_time_hi; // offset: 307 (0x133) + uint32_t disable_queue; // offset: 308 (0x134) + uint32_t reserved_309; // offset: 309 (0x135) + uint32_t reserved_310; // offset: 310 (0x136) + uint32_t reserved_311; // offset: 311 (0x137) + uint32_t reserved_312; // offset: 312 (0x138) + uint32_t reserved_313; // offset: 313 (0x139) + uint32_t reserved_314; // offset: 314 (0x13A) + uint32_t reserved_315; // offset: 315 (0x13B) + uint32_t reserved_316; // offset: 316 (0x13C) + uint32_t reserved_317; // offset: 317 (0x13D) + uint32_t tg_counter_id; // offset: 318 (0x13E) + uint32_t cp_compute_csinvoc_count_lo; // offset: 319 (0x13F) + uint32_t cp_compute_csinvoc_count_hi; // offset: 320 (0x140) + uint32_t reserved_321; // offset: 321 (0x141) + uint32_t reserved_322; // offset: 322 (0x142) + uint32_t reserved_323; // offset: 323 (0x143) + uint32_t reserved_324; // offset: 324 (0x144) + uint32_t reserved_325; // offset: 325 (0x145) + uint32_t reserved_326; // offset: 326 (0x146) + uint32_t reserved_327; // offset: 327 (0x147) + uint32_t reserved_328; // offset: 328 (0x148) + uint32_t reserved_329; // offset: 329 (0x149) + uint32_t reserved_330; // offset: 330 (0x14A) + uint32_t reserved_331; // offset: 331 (0x14B) + uint32_t reserved_332; // offset: 332 (0x14C) + uint32_t reserved_333; // offset: 333 (0x14D) + uint32_t reserved_334; // offset: 334 (0x14E) + uint32_t reserved_335; // offset: 335 (0x14F) + uint32_t reserved_336; // offset: 336 (0x150) + uint32_t reserved_337; // offset: 337 (0x151) + uint32_t reserved_338; // offset: 338 (0x152) + uint32_t reserved_339; // offset: 339 (0x153) + uint32_t reserved_340; // offset: 340 (0x154) + uint32_t reserved_341; // offset: 341 (0x155) + uint32_t reserved_342; // offset: 342 (0x156) + uint32_t reserved_343; // offset: 343 (0x157) + uint32_t reserved_344; // offset: 344 (0x158) + uint32_t reserved_345; // offset: 345 (0x159) + uint32_t reserved_346; // offset: 346 (0x15A) + uint32_t reserved_347; // offset: 347 (0x15B) + uint32_t reserved_348; // offset: 348 (0x15C) + uint32_t reserved_349; // offset: 349 (0x15D) + uint32_t reserved_350; // offset: 350 (0x15E) + uint32_t reserved_351; // offset: 351 (0x15F) + uint32_t reserved_352; // offset: 352 (0x160) + uint32_t reserved_353; // offset: 353 (0x161) + uint32_t reserved_354; // offset: 354 (0x162) + uint32_t reserved_355; // offset: 355 (0x163) + uint32_t reserved_356; // offset: 356 (0x164) + uint32_t reserved_357; // offset: 357 (0x165) + uint32_t reserved_358; // offset: 358 (0x166) + uint32_t reserved_359; // offset: 359 (0x167) + uint32_t reserved_360; // offset: 360 (0x168) + uint32_t reserved_361; // offset: 361 (0x169) + uint32_t reserved_362; // offset: 362 (0x16A) + uint32_t reserved_363; // offset: 363 (0x16B) + uint32_t reserved_364; // offset: 364 (0x16C) + uint32_t reserved_365; // offset: 365 (0x16D) + uint32_t reserved_366; // offset: 366 (0x16E) + uint32_t reserved_367; // offset: 367 (0x16F) + uint32_t reserved_368; // offset: 368 (0x170) + uint32_t reserved_369; // offset: 369 (0x171) + uint32_t reserved_370; // offset: 370 (0x172) + uint32_t reserved_371; // offset: 371 (0x173) + uint32_t reserved_372; // offset: 372 (0x174) + uint32_t reserved_373; // offset: 373 (0x175) + uint32_t reserved_374; // offset: 374 (0x176) + uint32_t reserved_375; // offset: 375 (0x177) + uint32_t reserved_376; // offset: 376 (0x178) + uint32_t reserved_377; // offset: 377 (0x179) + uint32_t reserved_378; // offset: 378 (0x17A) + uint32_t reserved_379; // offset: 379 (0x17B) + uint32_t reserved_380; // offset: 380 (0x17C) + uint32_t reserved_381; // offset: 381 (0x17D) + uint32_t reserved_382; // offset: 382 (0x17E) + uint32_t reserved_383; // offset: 383 (0x17F) + uint32_t iqtimer_pkt_header; // offset: 384 (0x180) + uint32_t iqtimer_pkt_dw0; // offset: 385 (0x181) + uint32_t iqtimer_pkt_dw1; // offset: 386 (0x182) + uint32_t iqtimer_pkt_dw2; // offset: 387 (0x183) + uint32_t iqtimer_pkt_dw3; // offset: 388 (0x184) + uint32_t iqtimer_pkt_dw4; // offset: 389 (0x185) + uint32_t iqtimer_pkt_dw5; // offset: 390 (0x186) + uint32_t iqtimer_pkt_dw6; // offset: 391 (0x187) + uint32_t iqtimer_pkt_dw7; // offset: 392 (0x188) + uint32_t iqtimer_pkt_dw8; // offset: 393 (0x189) + uint32_t iqtimer_pkt_dw9; // offset: 394 (0x18A) + uint32_t iqtimer_pkt_dw10; // offset: 395 (0x18B) + uint32_t iqtimer_pkt_dw11; // offset: 396 (0x18C) + uint32_t iqtimer_pkt_dw12; // offset: 397 (0x18D) + uint32_t iqtimer_pkt_dw13; // offset: 398 (0x18E) + uint32_t iqtimer_pkt_dw14; // offset: 399 (0x18F) + uint32_t iqtimer_pkt_dw15; // offset: 400 (0x190) + uint32_t iqtimer_pkt_dw16; // offset: 401 (0x191) + uint32_t iqtimer_pkt_dw17; // offset: 402 (0x192) + uint32_t iqtimer_pkt_dw18; // offset: 403 (0x193) + uint32_t iqtimer_pkt_dw19; // offset: 404 (0x194) + uint32_t iqtimer_pkt_dw20; // offset: 405 (0x195) + uint32_t iqtimer_pkt_dw21; // offset: 406 (0x196) + uint32_t iqtimer_pkt_dw22; // offset: 407 (0x197) + uint32_t iqtimer_pkt_dw23; // offset: 408 (0x198) + uint32_t iqtimer_pkt_dw24; // offset: 409 (0x199) + uint32_t iqtimer_pkt_dw25; // offset: 410 (0x19A) + uint32_t iqtimer_pkt_dw26; // offset: 411 (0x19B) + uint32_t iqtimer_pkt_dw27; // offset: 412 (0x19C) + uint32_t iqtimer_pkt_dw28; // offset: 413 (0x19D) + uint32_t iqtimer_pkt_dw29; // offset: 414 (0x19E) + uint32_t iqtimer_pkt_dw30; // offset: 415 (0x19F) + uint32_t iqtimer_pkt_dw31; // offset: 416 (0x1A0) + uint32_t reserved_417; // offset: 417 (0x1A1) + uint32_t reserved_418; // offset: 418 (0x1A2) + uint32_t reserved_419; // offset: 419 (0x1A3) + uint32_t reserved_420; // offset: 420 (0x1A4) + uint32_t reserved_421; // offset: 421 (0x1A5) + uint32_t reserved_422; // offset: 422 (0x1A6) + uint32_t reserved_423; // offset: 423 (0x1A7) + uint32_t reserved_424; // offset: 424 (0x1A8) + uint32_t reserved_425; // offset: 425 (0x1A9) + uint32_t reserved_426; // offset: 426 (0x1AA) + uint32_t reserved_427; // offset: 427 (0x1AB) + uint32_t reserved_428; // offset: 428 (0x1AC) + uint32_t reserved_429; // offset: 429 (0x1AD) + uint32_t reserved_430; // offset: 430 (0x1AE) + uint32_t reserved_431; // offset: 431 (0x1AF) + uint32_t reserved_432; // offset: 432 (0x1B0) + uint32_t reserved_433; // offset: 433 (0x1B1) + uint32_t reserved_434; // offset: 434 (0x1B2) + uint32_t reserved_435; // offset: 435 (0x1B3) + uint32_t reserved_436; // offset: 436 (0x1B4) + uint32_t reserved_437; // offset: 437 (0x1B5) + uint32_t reserved_438; // offset: 438 (0x1B6) + uint32_t reserved_439; // offset: 439 (0x1B7) + uint32_t reserved_440; // offset: 440 (0x1B8) + uint32_t reserved_441; // offset: 441 (0x1B9) + uint32_t reserved_442; // offset: 442 (0x1BA) + uint32_t reserved_443; // offset: 443 (0x1BB) + uint32_t reserved_444; // offset: 444 (0x1BC) + uint32_t reserved_445; // offset: 445 (0x1BD) + uint32_t reserved_446; // offset: 446 (0x1BE) + uint32_t reserved_447; // offset: 447 (0x1BF) + uint32_t reserved_448; // offset: 448 (0x1C0) + uint32_t reserved_449; // offset: 449 (0x1C1) + uint32_t reserved_450; // offset: 450 (0x1C2) + uint32_t reserved_451; // offset: 451 (0x1C3) + uint32_t reserved_452; // offset: 452 (0x1C4) + uint32_t reserved_453; // offset: 453 (0x1C5) + uint32_t reserved_454; // offset: 454 (0x1C6) + uint32_t reserved_455; // offset: 455 (0x1C7) + uint32_t reserved_456; // offset: 456 (0x1C8) + uint32_t reserved_457; // offset: 457 (0x1C9) + uint32_t reserved_458; // offset: 458 (0x1CA) + uint32_t reserved_459; // offset: 459 (0x1CB) + uint32_t reserved_460; // offset: 460 (0x1CC) + uint32_t reserved_461; // offset: 461 (0x1CD) + uint32_t reserved_462; // offset: 462 (0x1CE) + uint32_t reserved_463; // offset: 463 (0x1CF) + uint32_t reserved_464; // offset: 464 (0x1D0) + uint32_t reserved_465; // offset: 465 (0x1D1) + uint32_t reserved_466; // offset: 466 (0x1D2) + uint32_t reserved_467; // offset: 467 (0x1D3) + uint32_t reserved_468; // offset: 468 (0x1D4) + uint32_t reserved_469; // offset: 469 (0x1D5) + uint32_t reserved_470; // offset: 470 (0x1D6) + uint32_t reserved_471; // offset: 471 (0x1D7) + uint32_t reserved_472; // offset: 472 (0x1D8) + uint32_t reserved_473; // offset: 473 (0x1D9) + uint32_t reserved_474; // offset: 474 (0x1DA) + uint32_t reserved_475; // offset: 475 (0x1DB) + uint32_t reserved_476; // offset: 476 (0x1DC) + uint32_t reserved_477; // offset: 477 (0x1DD) + uint32_t reserved_478; // offset: 478 (0x1DE) + uint32_t reserved_479; // offset: 479 (0x1DF) + uint32_t reserved_480; // offset: 480 (0x1E0) + uint32_t reserved_481; // offset: 481 (0x1E1) + uint32_t reserved_482; // offset: 482 (0x1E2) + uint32_t reserved_483; // offset: 483 (0x1E3) + uint32_t reserved_484; // offset: 484 (0x1E4) + uint32_t reserved_485; // offset: 485 (0x1E5) + uint32_t reserved_486; // offset: 486 (0x1E6) + uint32_t reserved_487; // offset: 487 (0x1E7) + uint32_t reserved_488; // offset: 488 (0x1E8) + uint32_t reserved_489; // offset: 489 (0x1E9) + uint32_t reserved_490; // offset: 490 (0x1EA) + uint32_t reserved_491; // offset: 491 (0x1EB) + uint32_t reserved_492; // offset: 492 (0x1EC) + uint32_t reserved_493; // offset: 493 (0x1ED) + uint32_t reserved_494; // offset: 494 (0x1EE) + uint32_t reserved_495; // offset: 495 (0x1EF) + uint32_t reserved_496; // offset: 496 (0x1F0) + uint32_t reserved_497; // offset: 497 (0x1F1) + uint32_t reserved_498; // offset: 498 (0x1F2) + uint32_t reserved_499; // offset: 499 (0x1F3) + uint32_t reserved_500; // offset: 500 (0x1F4) + uint32_t reserved_501; // offset: 501 (0x1F5) + uint32_t reserved_502; // offset: 502 (0x1F6) + uint32_t reserved_503; // offset: 503 (0x1F7) + uint32_t reserved_504; // offset: 504 (0x1F8) + uint32_t reserved_505; // offset: 505 (0x1F9) + uint32_t reserved_506; // offset: 506 (0x1FA) + uint32_t reserved_507; // offset: 507 (0x1FB) + uint32_t reserved_508; // offset: 508 (0x1FC) + uint32_t reserved_509; // offset: 509 (0x1FD) + uint32_t reserved_510; // offset: 510 (0x1FE) + uint32_t reserved_511; // offset: 511 (0x1FF) + uint32_t reserved_512; // offset: 512 (0x200) + uint32_t reserved_513; // offset: 513 (0x201) + uint32_t reserved_514; // offset: 514 (0x202) + uint32_t reserved_515; // offset: 515 (0x203) + uint32_t reserved_516; // offset: 516 (0x204) + uint32_t reserved_517; // offset: 517 (0x205) + uint32_t reserved_518; // offset: 518 (0x206) + uint32_t reserved_519; // offset: 519 (0x207) + uint32_t reserved_520; // offset: 520 (0x208) + uint32_t reserved_521; // offset: 521 (0x209) + uint32_t reserved_522; // offset: 522 (0x20A) + uint32_t reserved_523; // offset: 523 (0x20B) + uint32_t reserved_524; // offset: 524 (0x20C) + uint32_t reserved_525; // offset: 525 (0x20D) + uint32_t reserved_526; // offset: 526 (0x20E) + uint32_t reserved_527; // offset: 527 (0x20F) + uint32_t reserved_528; // offset: 528 (0x210) + uint32_t reserved_529; // offset: 529 (0x211) + uint32_t reserved_530; // offset: 530 (0x212) + uint32_t reserved_531; // offset: 531 (0x213) + uint32_t reserved_532; // offset: 532 (0x214) + uint32_t reserved_533; // offset: 533 (0x215) + uint32_t reserved_534; // offset: 534 (0x216) + uint32_t reserved_535; // offset: 535 (0x217) + uint32_t reserved_536; // offset: 536 (0x218) + uint32_t reserved_537; // offset: 537 (0x219) + uint32_t reserved_538; // offset: 538 (0x21A) + uint32_t reserved_539; // offset: 539 (0x21B) + uint32_t reserved_540; // offset: 540 (0x21C) + uint32_t reserved_541; // offset: 541 (0x21D) + uint32_t reserved_542; // offset: 542 (0x21E) + uint32_t reserved_543; // offset: 543 (0x21F) + uint32_t reserved_544; // offset: 544 (0x220) + uint32_t reserved_545; // offset: 545 (0x221) + uint32_t reserved_546; // offset: 546 (0x222) + uint32_t reserved_547; // offset: 547 (0x223) + uint32_t reserved_548; // offset: 548 (0x224) + uint32_t reserved_549; // offset: 549 (0x225) + uint32_t reserved_550; // offset: 550 (0x226) + uint32_t reserved_551; // offset: 551 (0x227) + uint32_t reserved_552; // offset: 552 (0x228) + uint32_t reserved_553; // offset: 553 (0x229) + uint32_t reserved_554; // offset: 554 (0x22A) + uint32_t reserved_555; // offset: 555 (0x22B) + uint32_t reserved_556; // offset: 556 (0x22C) + uint32_t reserved_557; // offset: 557 (0x22D) + uint32_t reserved_558; // offset: 558 (0x22E) + uint32_t reserved_559; // offset: 559 (0x22F) + uint32_t reserved_560; // offset: 560 (0x230) + uint32_t reserved_561; // offset: 561 (0x231) + uint32_t reserved_562; // offset: 562 (0x232) + uint32_t reserved_563; // offset: 563 (0x233) + uint32_t reserved_564; // offset: 564 (0x234) + uint32_t reserved_565; // offset: 565 (0x235) + uint32_t reserved_566; // offset: 566 (0x236) + uint32_t reserved_567; // offset: 567 (0x237) + uint32_t reserved_568; // offset: 568 (0x238) + uint32_t reserved_569; // offset: 569 (0x239) + uint32_t reserved_570; // offset: 570 (0x23A) + uint32_t reserved_571; // offset: 571 (0x23B) + uint32_t reserved_572; // offset: 572 (0x23C) + uint32_t reserved_573; // offset: 573 (0x23D) + uint32_t reserved_574; // offset: 574 (0x23E) + uint32_t reserved_575; // offset: 575 (0x23F) + uint32_t reserved_576; // offset: 576 (0x240) + uint32_t reserved_577; // offset: 577 (0x241) + uint32_t reserved_578; // offset: 578 (0x242) + uint32_t reserved_579; // offset: 579 (0x243) + uint32_t reserved_580; // offset: 580 (0x244) + uint32_t reserved_581; // offset: 581 (0x245) + uint32_t reserved_582; // offset: 582 (0x246) + uint32_t reserved_583; // offset: 583 (0x247) + uint32_t reserved_584; // offset: 584 (0x248) + uint32_t reserved_585; // offset: 585 (0x249) + uint32_t reserved_586; // offset: 586 (0x24A) + uint32_t reserved_587; // offset: 587 (0x24B) + uint32_t reserved_588; // offset: 588 (0x24C) + uint32_t reserved_589; // offset: 589 (0x24D) + uint32_t reserved_590; // offset: 590 (0x24E) + uint32_t reserved_591; // offset: 591 (0x24F) + uint32_t reserved_592; // offset: 592 (0x250) + uint32_t reserved_593; // offset: 593 (0x251) + uint32_t reserved_594; // offset: 594 (0x252) + uint32_t reserved_595; // offset: 595 (0x253) + uint32_t reserved_596; // offset: 596 (0x254) + uint32_t reserved_597; // offset: 597 (0x255) + uint32_t reserved_598; // offset: 598 (0x256) + uint32_t reserved_599; // offset: 599 (0x257) + uint32_t reserved_600; // offset: 600 (0x258) + uint32_t reserved_601; // offset: 601 (0x259) + uint32_t reserved_602; // offset: 602 (0x25A) + uint32_t reserved_603; // offset: 603 (0x25B) + uint32_t reserved_604; // offset: 604 (0x25C) + uint32_t reserved_605; // offset: 605 (0x25D) + uint32_t reserved_606; // offset: 606 (0x25E) + uint32_t reserved_607; // offset: 607 (0x25F) + uint32_t reserved_608; // offset: 608 (0x260) + uint32_t reserved_609; // offset: 609 (0x261) + uint32_t reserved_610; // offset: 610 (0x262) + uint32_t reserved_611; // offset: 611 (0x263) + uint32_t reserved_612; // offset: 612 (0x264) + uint32_t reserved_613; // offset: 613 (0x265) + uint32_t reserved_614; // offset: 614 (0x266) + uint32_t reserved_615; // offset: 615 (0x267) + uint32_t reserved_616; // offset: 616 (0x268) + uint32_t reserved_617; // offset: 617 (0x269) + uint32_t reserved_618; // offset: 618 (0x26A) + uint32_t reserved_619; // offset: 619 (0x26B) + uint32_t reserved_620; // offset: 620 (0x26C) + uint32_t reserved_621; // offset: 621 (0x26D) + uint32_t reserved_622; // offset: 622 (0x26E) + uint32_t reserved_623; // offset: 623 (0x26F) + uint32_t reserved_624; // offset: 624 (0x270) + uint32_t reserved_625; // offset: 625 (0x271) + uint32_t reserved_626; // offset: 626 (0x272) + uint32_t reserved_627; // offset: 627 (0x273) + uint32_t reserved_628; // offset: 628 (0x274) + uint32_t reserved_629; // offset: 629 (0x275) + uint32_t reserved_630; // offset: 630 (0x276) + uint32_t reserved_631; // offset: 631 (0x277) + uint32_t reserved_632; // offset: 632 (0x278) + uint32_t reserved_633; // offset: 633 (0x279) + uint32_t reserved_634; // offset: 634 (0x27A) + uint32_t reserved_635; // offset: 635 (0x27B) + uint32_t reserved_636; // offset: 636 (0x27C) + uint32_t reserved_637; // offset: 637 (0x27D) + uint32_t reserved_638; // offset: 638 (0x27E) + uint32_t reserved_639; // offset: 639 (0x27F) + uint32_t reserved_640; // offset: 640 (0x280) + uint32_t reserved_641; // offset: 641 (0x281) + uint32_t reserved_642; // offset: 642 (0x282) + uint32_t reserved_643; // offset: 643 (0x283) + uint32_t reserved_644; // offset: 644 (0x284) + uint32_t reserved_645; // offset: 645 (0x285) + uint32_t reserved_646; // offset: 646 (0x286) + uint32_t reserved_647; // offset: 647 (0x287) + uint32_t reserved_648; // offset: 648 (0x288) + uint32_t reserved_649; // offset: 649 (0x289) + uint32_t reserved_650; // offset: 650 (0x28A) + uint32_t reserved_651; // offset: 651 (0x28B) + uint32_t reserved_652; // offset: 652 (0x28C) + uint32_t reserved_653; // offset: 653 (0x28D) + uint32_t reserved_654; // offset: 654 (0x28E) + uint32_t reserved_655; // offset: 655 (0x28F) + uint32_t reserved_656; // offset: 656 (0x290) + uint32_t reserved_657; // offset: 657 (0x291) + uint32_t reserved_658; // offset: 658 (0x292) + uint32_t reserved_659; // offset: 659 (0x293) + uint32_t reserved_660; // offset: 660 (0x294) + uint32_t reserved_661; // offset: 661 (0x295) + uint32_t reserved_662; // offset: 662 (0x296) + uint32_t reserved_663; // offset: 663 (0x297) + uint32_t reserved_664; // offset: 664 (0x298) + uint32_t reserved_665; // offset: 665 (0x299) + uint32_t reserved_666; // offset: 666 (0x29A) + uint32_t reserved_667; // offset: 667 (0x29B) + uint32_t reserved_668; // offset: 668 (0x29C) + uint32_t reserved_669; // offset: 669 (0x29D) + uint32_t reserved_670; // offset: 670 (0x29E) + uint32_t reserved_671; // offset: 671 (0x29F) + uint32_t reserved_672; // offset: 672 (0x2A0) + uint32_t reserved_673; // offset: 673 (0x2A1) + uint32_t reserved_674; // offset: 674 (0x2A2) + uint32_t reserved_675; // offset: 675 (0x2A3) + uint32_t reserved_676; // offset: 676 (0x2A4) + uint32_t reserved_677; // offset: 677 (0x2A5) + uint32_t reserved_678; // offset: 678 (0x2A6) + uint32_t reserved_679; // offset: 679 (0x2A7) + uint32_t reserved_680; // offset: 680 (0x2A8) + uint32_t reserved_681; // offset: 681 (0x2A9) + uint32_t reserved_682; // offset: 682 (0x2AA) + uint32_t reserved_683; // offset: 683 (0x2AB) + uint32_t reserved_684; // offset: 684 (0x2AC) + uint32_t reserved_685; // offset: 685 (0x2AD) + uint32_t reserved_686; // offset: 686 (0x2AE) + uint32_t reserved_687; // offset: 687 (0x2AF) + uint32_t reserved_688; // offset: 688 (0x2B0) + uint32_t reserved_689; // offset: 689 (0x2B1) + uint32_t reserved_690; // offset: 690 (0x2B2) + uint32_t reserved_691; // offset: 691 (0x2B3) + uint32_t reserved_692; // offset: 692 (0x2B4) + uint32_t reserved_693; // offset: 693 (0x2B5) + uint32_t reserved_694; // offset: 694 (0x2B6) + uint32_t reserved_695; // offset: 695 (0x2B7) + uint32_t reserved_696; // offset: 696 (0x2B8) + uint32_t reserved_697; // offset: 697 (0x2B9) + uint32_t reserved_698; // offset: 698 (0x2BA) + uint32_t reserved_699; // offset: 699 (0x2BB) + uint32_t reserved_700; // offset: 700 (0x2BC) + uint32_t reserved_701; // offset: 701 (0x2BD) + uint32_t reserved_702; // offset: 702 (0x2BE) + uint32_t reserved_703; // offset: 703 (0x2BF) + uint32_t reserved_704; // offset: 704 (0x2C0) + uint32_t reserved_705; // offset: 705 (0x2C1) + uint32_t reserved_706; // offset: 706 (0x2C2) + uint32_t reserved_707; // offset: 707 (0x2C3) + uint32_t reserved_708; // offset: 708 (0x2C4) + uint32_t reserved_709; // offset: 709 (0x2C5) + uint32_t reserved_710; // offset: 710 (0x2C6) + uint32_t reserved_711; // offset: 711 (0x2C7) + uint32_t reserved_712; // offset: 712 (0x2C8) + uint32_t reserved_713; // offset: 713 (0x2C9) + uint32_t reserved_714; // offset: 714 (0x2CA) + uint32_t reserved_715; // offset: 715 (0x2CB) + uint32_t reserved_716; // offset: 716 (0x2CC) + uint32_t reserved_717; // offset: 717 (0x2CD) + uint32_t reserved_718; // offset: 718 (0x2CE) + uint32_t reserved_719; // offset: 719 (0x2CF) + uint32_t reserved_720; // offset: 720 (0x2D0) + uint32_t reserved_721; // offset: 721 (0x2D1) + uint32_t reserved_722; // offset: 722 (0x2D2) + uint32_t reserved_723; // offset: 723 (0x2D3) + uint32_t reserved_724; // offset: 724 (0x2D4) + uint32_t reserved_725; // offset: 725 (0x2D5) + uint32_t reserved_726; // offset: 726 (0x2D6) + uint32_t reserved_727; // offset: 727 (0x2D7) + uint32_t reserved_728; // offset: 728 (0x2D8) + uint32_t reserved_729; // offset: 729 (0x2D9) + uint32_t reserved_730; // offset: 730 (0x2DA) + uint32_t reserved_731; // offset: 731 (0x2DB) + uint32_t reserved_732; // offset: 732 (0x2DC) + uint32_t reserved_733; // offset: 733 (0x2DD) + uint32_t reserved_734; // offset: 734 (0x2DE) + uint32_t reserved_735; // offset: 735 (0x2DF) + uint32_t reserved_736; // offset: 736 (0x2E0) + uint32_t reserved_737; // offset: 737 (0x2E1) + uint32_t reserved_738; // offset: 738 (0x2E2) + uint32_t reserved_739; // offset: 739 (0x2E3) + uint32_t reserved_740; // offset: 740 (0x2E4) + uint32_t reserved_741; // offset: 741 (0x2E5) + uint32_t reserved_742; // offset: 742 (0x2E6) + uint32_t reserved_743; // offset: 743 (0x2E7) + uint32_t reserved_744; // offset: 744 (0x2E8) + uint32_t reserved_745; // offset: 745 (0x2E9) + uint32_t reserved_746; // offset: 746 (0x2EA) + uint32_t reserved_747; // offset: 747 (0x2EB) + uint32_t reserved_748; // offset: 748 (0x2EC) + uint32_t reserved_749; // offset: 749 (0x2ED) + uint32_t reserved_750; // offset: 750 (0x2EE) + uint32_t reserved_751; // offset: 751 (0x2EF) + uint32_t reserved_752; // offset: 752 (0x2F0) + uint32_t reserved_753; // offset: 753 (0x2F1) + uint32_t reserved_754; // offset: 754 (0x2F2) + uint32_t reserved_755; // offset: 755 (0x2F3) + uint32_t reserved_756; // offset: 756 (0x2F4) + uint32_t reserved_757; // offset: 757 (0x2F5) + uint32_t reserved_758; // offset: 758 (0x2F6) + uint32_t reserved_759; // offset: 759 (0x2F7) + uint32_t reserved_760; // offset: 760 (0x2F8) + uint32_t reserved_761; // offset: 761 (0x2F9) + uint32_t reserved_762; // offset: 762 (0x2FA) + uint32_t reserved_763; // offset: 763 (0x2FB) + uint32_t reserved_764; // offset: 764 (0x2FC) + uint32_t reserved_765; // offset: 765 (0x2FD) + uint32_t reserved_766; // offset: 766 (0x2FE) + uint32_t reserved_767; // offset: 767 (0x2FF) + uint32_t reserved_768; // offset: 768 (0x300) + uint32_t reserved_769; // offset: 769 (0x301) + uint32_t reserved_770; // offset: 770 (0x302) + uint32_t reserved_771; // offset: 771 (0x303) + uint32_t reserved_772; // offset: 772 (0x304) + uint32_t reserved_773; // offset: 773 (0x305) + uint32_t reserved_774; // offset: 774 (0x306) + uint32_t reserved_775; // offset: 775 (0x307) + uint32_t reserved_776; // offset: 776 (0x308) + uint32_t reserved_777; // offset: 777 (0x309) + uint32_t reserved_778; // offset: 778 (0x30A) + uint32_t reserved_779; // offset: 779 (0x30B) + uint32_t reserved_780; // offset: 780 (0x30C) + uint32_t reserved_781; // offset: 781 (0x30D) + uint32_t reserved_782; // offset: 782 (0x30E) + uint32_t reserved_783; // offset: 783 (0x30F) + uint32_t reserved_784; // offset: 784 (0x310) + uint32_t reserved_785; // offset: 785 (0x311) + uint32_t reserved_786; // offset: 786 (0x312) + uint32_t reserved_787; // offset: 787 (0x313) + uint32_t reserved_788; // offset: 788 (0x314) + uint32_t reserved_789; // offset: 789 (0x315) + uint32_t reserved_790; // offset: 790 (0x316) + uint32_t reserved_791; // offset: 791 (0x317) + uint32_t reserved_792; // offset: 792 (0x318) + uint32_t reserved_793; // offset: 793 (0x319) + uint32_t reserved_794; // offset: 794 (0x31A) + uint32_t reserved_795; // offset: 795 (0x31B) + uint32_t reserved_796; // offset: 796 (0x31C) + uint32_t reserved_797; // offset: 797 (0x31D) + uint32_t reserved_798; // offset: 798 (0x31E) + uint32_t reserved_799; // offset: 799 (0x31F) + uint32_t reserved_800; // offset: 800 (0x320) + uint32_t reserved_801; // offset: 801 (0x321) + uint32_t reserved_802; // offset: 802 (0x322) + uint32_t reserved_803; // offset: 803 (0x323) + uint32_t reserved_804; // offset: 804 (0x324) + uint32_t reserved_805; // offset: 805 (0x325) + uint32_t reserved_806; // offset: 806 (0x326) + uint32_t reserved_807; // offset: 807 (0x327) + uint32_t reserved_808; // offset: 808 (0x328) + uint32_t reserved_809; // offset: 809 (0x329) + uint32_t reserved_810; // offset: 810 (0x32A) + uint32_t reserved_811; // offset: 811 (0x32B) + uint32_t reserved_812; // offset: 812 (0x32C) + uint32_t reserved_813; // offset: 813 (0x32D) + uint32_t reserved_814; // offset: 814 (0x32E) + uint32_t reserved_815; // offset: 815 (0x32F) + uint32_t reserved_816; // offset: 816 (0x330) + uint32_t reserved_817; // offset: 817 (0x331) + uint32_t reserved_818; // offset: 818 (0x332) + uint32_t reserved_819; // offset: 819 (0x333) + uint32_t reserved_820; // offset: 820 (0x334) + uint32_t reserved_821; // offset: 821 (0x335) + uint32_t reserved_822; // offset: 822 (0x336) + uint32_t reserved_823; // offset: 823 (0x337) + uint32_t reserved_824; // offset: 824 (0x338) + uint32_t reserved_825; // offset: 825 (0x339) + uint32_t reserved_826; // offset: 826 (0x33A) + uint32_t reserved_827; // offset: 827 (0x33B) + uint32_t reserved_828; // offset: 828 (0x33C) + uint32_t reserved_829; // offset: 829 (0x33D) + uint32_t reserved_830; // offset: 830 (0x33E) + uint32_t reserved_831; // offset: 831 (0x33F) + uint32_t reserved_832; // offset: 832 (0x340) + uint32_t reserved_833; // offset: 833 (0x341) + uint32_t reserved_834; // offset: 834 (0x342) + uint32_t reserved_835; // offset: 835 (0x343) + uint32_t reserved_836; // offset: 836 (0x344) + uint32_t reserved_837; // offset: 837 (0x345) + uint32_t reserved_838; // offset: 838 (0x346) + uint32_t reserved_839; // offset: 839 (0x347) + uint32_t reserved_840; // offset: 840 (0x348) + uint32_t reserved_841; // offset: 841 (0x349) + uint32_t reserved_842; // offset: 842 (0x34A) + uint32_t reserved_843; // offset: 843 (0x34B) + uint32_t reserved_844; // offset: 844 (0x34C) + uint32_t reserved_845; // offset: 845 (0x34D) + uint32_t reserved_846; // offset: 846 (0x34E) + uint32_t reserved_847; // offset: 847 (0x34F) + uint32_t reserved_848; // offset: 848 (0x350) + uint32_t reserved_849; // offset: 849 (0x351) + uint32_t reserved_850; // offset: 850 (0x352) + uint32_t reserved_851; // offset: 851 (0x353) + uint32_t reserved_852; // offset: 852 (0x354) + uint32_t reserved_853; // offset: 853 (0x355) + uint32_t reserved_854; // offset: 854 (0x356) + uint32_t reserved_855; // offset: 855 (0x357) + uint32_t reserved_856; // offset: 856 (0x358) + uint32_t reserved_857; // offset: 857 (0x359) + uint32_t reserved_858; // offset: 858 (0x35A) + uint32_t reserved_859; // offset: 859 (0x35B) + uint32_t reserved_860; // offset: 860 (0x35C) + uint32_t reserved_861; // offset: 861 (0x35D) + uint32_t reserved_862; // offset: 862 (0x35E) + uint32_t reserved_863; // offset: 863 (0x35F) + uint32_t reserved_864; // offset: 864 (0x360) + uint32_t reserved_865; // offset: 865 (0x361) + uint32_t reserved_866; // offset: 866 (0x362) + uint32_t reserved_867; // offset: 867 (0x363) + uint32_t reserved_868; // offset: 868 (0x364) + uint32_t reserved_869; // offset: 869 (0x365) + uint32_t reserved_870; // offset: 870 (0x366) + uint32_t reserved_871; // offset: 871 (0x367) + uint32_t reserved_872; // offset: 872 (0x368) + uint32_t reserved_873; // offset: 873 (0x369) + uint32_t reserved_874; // offset: 874 (0x36A) + uint32_t reserved_875; // offset: 875 (0x36B) + uint32_t reserved_876; // offset: 876 (0x36C) + uint32_t reserved_877; // offset: 877 (0x36D) + uint32_t reserved_878; // offset: 878 (0x36E) + uint32_t reserved_879; // offset: 879 (0x36F) + uint32_t reserved_880; // offset: 880 (0x370) + uint32_t reserved_881; // offset: 881 (0x371) + uint32_t reserved_882; // offset: 882 (0x372) + uint32_t reserved_883; // offset: 883 (0x373) + uint32_t reserved_884; // offset: 884 (0x374) + uint32_t reserved_885; // offset: 885 (0x375) + uint32_t reserved_886; // offset: 886 (0x376) + uint32_t reserved_887; // offset: 887 (0x377) + uint32_t reserved_888; // offset: 888 (0x378) + uint32_t reserved_889; // offset: 889 (0x379) + uint32_t reserved_890; // offset: 890 (0x37A) + uint32_t reserved_891; // offset: 891 (0x37B) + uint32_t reserved_892; // offset: 892 (0x37C) + uint32_t reserved_893; // offset: 893 (0x37D) + uint32_t reserved_894; // offset: 894 (0x37E) + uint32_t reserved_895; // offset: 895 (0x37F) + uint32_t reserved_896; // offset: 896 (0x380) + uint32_t reserved_897; // offset: 897 (0x381) + uint32_t reserved_898; // offset: 898 (0x382) + uint32_t reserved_899; // offset: 899 (0x383) + uint32_t reserved_900; // offset: 900 (0x384) + uint32_t reserved_901; // offset: 901 (0x385) + uint32_t reserved_902; // offset: 902 (0x386) + uint32_t reserved_903; // offset: 903 (0x387) + uint32_t reserved_904; // offset: 904 (0x388) + uint32_t reserved_905; // offset: 905 (0x389) + uint32_t reserved_906; // offset: 906 (0x38A) + uint32_t reserved_907; // offset: 907 (0x38B) + uint32_t reserved_908; // offset: 908 (0x38C) + uint32_t reserved_909; // offset: 909 (0x38D) + uint32_t reserved_910; // offset: 910 (0x38E) + uint32_t reserved_911; // offset: 911 (0x38F) + uint32_t reserved_912; // offset: 912 (0x390) + uint32_t reserved_913; // offset: 913 (0x391) + uint32_t reserved_914; // offset: 914 (0x392) + uint32_t reserved_915; // offset: 915 (0x393) + uint32_t reserved_916; // offset: 916 (0x394) + uint32_t reserved_917; // offset: 917 (0x395) + uint32_t reserved_918; // offset: 918 (0x396) + uint32_t reserved_919; // offset: 919 (0x397) + uint32_t reserved_920; // offset: 920 (0x398) + uint32_t reserved_921; // offset: 921 (0x399) + uint32_t reserved_922; // offset: 922 (0x39A) + uint32_t reserved_923; // offset: 923 (0x39B) + uint32_t reserved_924; // offset: 924 (0x39C) + uint32_t reserved_925; // offset: 925 (0x39D) + uint32_t reserved_926; // offset: 926 (0x39E) + uint32_t reserved_927; // offset: 927 (0x39F) + uint32_t reserved_928; // offset: 928 (0x3A0) + uint32_t reserved_929; // offset: 929 (0x3A1) + uint32_t reserved_930; // offset: 930 (0x3A2) + uint32_t reserved_931; // offset: 931 (0x3A3) + uint32_t reserved_932; // offset: 932 (0x3A4) + uint32_t reserved_933; // offset: 933 (0x3A5) + uint32_t reserved_934; // offset: 934 (0x3A6) + uint32_t reserved_935; // offset: 935 (0x3A7) + uint32_t reserved_936; // offset: 936 (0x3A8) + uint32_t reserved_937; // offset: 937 (0x3A9) + uint32_t reserved_938; // offset: 938 (0x3AA) + uint32_t reserved_939; // offset: 939 (0x3AB) + uint32_t reserved_940; // offset: 940 (0x3AC) + uint32_t reserved_941; // offset: 941 (0x3AD) + uint32_t reserved_942; // offset: 942 (0x3AE) + uint32_t reserved_943; // offset: 943 (0x3AF) + uint32_t reserved_944; // offset: 944 (0x3B0) + uint32_t reserved_945; // offset: 945 (0x3B1) + uint32_t reserved_946; // offset: 946 (0x3B2) + uint32_t reserved_947; // offset: 947 (0x3B3) + uint32_t reserved_948; // offset: 948 (0x3B4) + uint32_t reserved_949; // offset: 949 (0x3B5) + uint32_t reserved_950; // offset: 950 (0x3B6) + uint32_t reserved_951; // offset: 951 (0x3B7) + uint32_t reserved_952; // offset: 952 (0x3B8) + uint32_t reserved_953; // offset: 953 (0x3B9) + uint32_t reserved_954; // offset: 954 (0x3BA) + uint32_t reserved_955; // offset: 955 (0x3BB) + uint32_t reserved_956; // offset: 956 (0x3BC) + uint32_t reserved_957; // offset: 957 (0x3BD) + uint32_t reserved_958; // offset: 958 (0x3BE) + uint32_t reserved_959; // offset: 959 (0x3BF) + uint32_t reserved_960; // offset: 960 (0x3C0) + uint32_t reserved_961; // offset: 961 (0x3C1) + uint32_t reserved_962; // offset: 962 (0x3C2) + uint32_t reserved_963; // offset: 963 (0x3C3) + uint32_t reserved_964; // offset: 964 (0x3C4) + uint32_t reserved_965; // offset: 965 (0x3C5) + uint32_t reserved_966; // offset: 966 (0x3C6) + uint32_t reserved_967; // offset: 967 (0x3C7) + uint32_t reserved_968; // offset: 968 (0x3C8) + uint32_t reserved_969; // offset: 969 (0x3C9) + uint32_t reserved_970; // offset: 970 (0x3CA) + uint32_t reserved_971; // offset: 971 (0x3CB) + uint32_t reserved_972; // offset: 972 (0x3CC) + uint32_t reserved_973; // offset: 973 (0x3CD) + uint32_t reserved_974; // offset: 974 (0x3CE) + uint32_t reserved_975; // offset: 975 (0x3CF) + uint32_t reserved_976; // offset: 976 (0x3D0) + uint32_t reserved_977; // offset: 977 (0x3D1) + uint32_t reserved_978; // offset: 978 (0x3D2) + uint32_t reserved_979; // offset: 979 (0x3D3) + uint32_t reserved_980; // offset: 980 (0x3D4) + uint32_t reserved_981; // offset: 981 (0x3D5) + uint32_t reserved_982; // offset: 982 (0x3D6) + uint32_t reserved_983; // offset: 983 (0x3D7) + uint32_t reserved_984; // offset: 984 (0x3D8) + uint32_t reserved_985; // offset: 985 (0x3D9) + uint32_t reserved_986; // offset: 986 (0x3DA) + uint32_t reserved_987; // offset: 987 (0x3DB) + uint32_t reserved_988; // offset: 988 (0x3DC) + uint32_t reserved_989; // offset: 989 (0x3DD) + uint32_t reserved_990; // offset: 990 (0x3DE) + uint32_t reserved_991; // offset: 991 (0x3DF) + uint32_t reserved_992; // offset: 992 (0x3E0) + uint32_t reserved_993; // offset: 993 (0x3E1) + uint32_t reserved_994; // offset: 994 (0x3E2) + uint32_t reserved_995; // offset: 995 (0x3E3) + uint32_t reserved_996; // offset: 996 (0x3E4) + uint32_t reserved_997; // offset: 997 (0x3E5) + uint32_t reserved_998; // offset: 998 (0x3E6) + uint32_t reserved_999; // offset: 999 (0x3E7) + uint32_t reserved_1000; // offset: 1000 (0x3E8) + uint32_t reserved_1001; // offset: 1001 (0x3E9) + uint32_t reserved_1002; // offset: 1002 (0x3EA) + uint32_t reserved_1003; // offset: 1003 (0x3EB) + uint32_t reserved_1004; // offset: 1004 (0x3EC) + uint32_t reserved_1005; // offset: 1005 (0x3ED) + uint32_t reserved_1006; // offset: 1006 (0x3EE) + uint32_t reserved_1007; // offset: 1007 (0x3EF) + uint32_t reserved_1008; // offset: 1008 (0x3F0) + uint32_t reserved_1009; // offset: 1009 (0x3F1) + uint32_t reserved_1010; // offset: 1010 (0x3F2) + uint32_t reserved_1011; // offset: 1011 (0x3F3) + uint32_t reserved_1012; // offset: 1012 (0x3F4) + uint32_t reserved_1013; // offset: 1013 (0x3F5) + uint32_t reserved_1014; // offset: 1014 (0x3F6) + uint32_t reserved_1015; // offset: 1015 (0x3F7) + uint32_t reserved_1016; // offset: 1016 (0x3F8) + uint32_t reserved_1017; // offset: 1017 (0x3F9) + uint32_t reserved_1018; // offset: 1018 (0x3FA) + uint32_t reserved_1019; // offset: 1019 (0x3FB) + uint32_t reserved_1020; // offset: 1020 (0x3FC) + uint32_t reserved_1021; // offset: 1021 (0x3FD) + uint32_t reserved_1022; // offset: 1022 (0x3FE) + uint32_t reserved_1023; // offset: 1023 (0x3FF) +}; + #endif /* V11_STRUCTS_H_ */ diff --git a/drivers/gpu/drm/amd/pm/Makefile b/drivers/gpu/drm/amd/pm/Makefile index ebbf188f625c1..a4dde44f7a44d 100644 --- a/drivers/gpu/drm/amd/pm/Makefile +++ b/drivers/gpu/drm/amd/pm/Makefile @@ -31,6 +31,7 @@ subdir-ccflags-y += \ -I$(FULL_AMD_PATH)/pm/swsmu/smu12 \ -I$(FULL_AMD_PATH)/pm/swsmu/smu13 \ -I$(FULL_AMD_PATH)/pm/swsmu/smu14 \ + -I$(FULL_AMD_PATH)/pm/swsmu/smu15 \ -I$(FULL_AMD_PATH)/pm/powerplay/inc \ -I$(FULL_AMD_PATH)/pm/powerplay/smumgr\ -I$(FULL_AMD_PATH)/pm/powerplay/hwmgr \ diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 302af1fb6901e..930c99e212fc2 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -608,8 +608,8 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable, 0); if (ret) - DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", - enable ? "enable" : "disable", ret); + drm_err(adev_to_drm(adev), "DPM %s uvd failed, ret = %d.\n", + enable ? "enable" : "disable", ret); } void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst) @@ -618,8 +618,8 @@ void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst) ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCN, !enable, inst); if (ret) - DRM_ERROR("Dpm %s uvd failed, ret = %d. \n", - enable ? "enable" : "disable", ret); + drm_err(adev_to_drm(adev), "DPM %s vcn failed, ret = %d.\n", + enable ? "enable" : "disable", ret); } void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) @@ -643,8 +643,8 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable, 0); if (ret) - DRM_ERROR("Dpm %s vce failed, ret = %d. \n", - enable ? "enable" : "disable", ret); + drm_err(adev_to_drm(adev), "DPM %s vce failed, ret = %d.\n", + enable ? "enable" : "disable", ret); } void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) @@ -653,8 +653,8 @@ void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable, 0); if (ret) - DRM_ERROR("Dpm %s jpeg failed, ret = %d. \n", - enable ? "enable" : "disable", ret); + drm_err(adev_to_drm(adev), "Dpm %s jpeg failed, ret = %d.\n", + enable ? "enable" : "disable", ret); } void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) @@ -663,8 +663,8 @@ void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable, 0); if (ret) - DRM_ERROR("Dpm %s vpe failed, ret = %d.\n", - enable ? "enable" : "disable", ret); + drm_err(adev_to_drm(adev), "DPM %s vpe failed, ret = %d.\n", + enable ? "enable" : "disable", ret); } int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) @@ -1244,25 +1244,6 @@ int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, return ret; } -int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, - enum pp_clock_type type, - char *buf) -{ - const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; - int ret = 0; - - if (!pp_funcs->print_clock_levels) - return 0; - - mutex_lock(&adev->pm.mutex); - ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, - type, - buf); - mutex_unlock(&adev->pm.mutex); - - return ret; -} - int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, enum pp_clock_type type, char *buf, @@ -1589,7 +1570,7 @@ int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, int ret = 0; if (!pp_funcs->get_power_limit) - return -ENODATA; + return -EOPNOTSUPP; mutex_lock(&adev->pm.mutex); ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, @@ -2130,6 +2111,14 @@ ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id, return ret; } +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev) +{ + if (!is_support_sw_smu(adev)) + return; + + amdgpu_smu_phase_det_debugfs_init(adev); +} + const struct ras_smu_drv *amdgpu_dpm_get_ras_smu_driver(struct amdgpu_device *adev) { void *pp_handle = adev->powerplay.pp_handle; diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 65296a819e6a1..74d29075765a6 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -243,11 +243,11 @@ static ssize_t amdgpu_set_power_dpm_state(struct device *dev, enum amd_pm_state_type state; int ret; - if (strncmp("battery", buf, strlen("battery")) == 0) + if (sysfs_streq(buf, "battery")) state = POWER_STATE_TYPE_BATTERY; - else if (strncmp("balanced", buf, strlen("balanced")) == 0) + else if (sysfs_streq(buf, "balanced")) state = POWER_STATE_TYPE_BALANCED; - else if (strncmp("performance", buf, strlen("performance")) == 0) + else if (sysfs_streq(buf, "performance")) state = POWER_STATE_TYPE_PERFORMANCE; else return -EINVAL; @@ -363,29 +363,28 @@ static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev, enum amd_dpm_forced_level level; int ret = 0; - if (strncmp("low", buf, strlen("low")) == 0) { + if (sysfs_streq(buf, "low")) level = AMD_DPM_FORCED_LEVEL_LOW; - } else if (strncmp("high", buf, strlen("high")) == 0) { + else if (sysfs_streq(buf, "high")) level = AMD_DPM_FORCED_LEVEL_HIGH; - } else if (strncmp("auto", buf, strlen("auto")) == 0) { + else if (sysfs_streq(buf, "auto")) level = AMD_DPM_FORCED_LEVEL_AUTO; - } else if (strncmp("manual", buf, strlen("manual")) == 0) { + else if (sysfs_streq(buf, "manual")) level = AMD_DPM_FORCED_LEVEL_MANUAL; - } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { + else if (sysfs_streq(buf, "profile_exit")) level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; - } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { + else if (sysfs_streq(buf, "profile_standard")) level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; - } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { + else if (sysfs_streq(buf, "profile_min_sclk")) level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; - } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { + else if (sysfs_streq(buf, "profile_min_mclk")) level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; - } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { + else if (sysfs_streq(buf, "profile_peak")) level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; - } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) { + else if (sysfs_streq(buf, "perf_determinism")) level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM; - } else { + else return -EINVAL; - } ret = amdgpu_pm_get_access(adev); if (ret < 0) @@ -681,6 +680,8 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, * - minimum(not available for Vega20 and Navi1x) and maximum memory * clock labeled OD_MCLK * + * - minimum and maximum fabric clock labeled OD_FCLK (SMU13) + * * - three points labeled OD_VDDC_CURVE. * They can be used to calibrate the sclk voltage curve. This is * available for Vega20 and NV1X. @@ -716,10 +717,11 @@ static ssize_t amdgpu_set_pp_table(struct device *dev, * - First select manual using power_dpm_force_performance_level * * - For clock frequency setting, enter a new value by writing a - * string that contains "s/m index clock" to the file. The index + * string that contains "s/m/f index clock" to the file. The index * should be 0 if to set minimum clock. And 1 if to set maximum * clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz. - * "m 1 800" will update maximum mclk to be 800Mhz. For core + * "m 1 800" will update maximum mclk to be 800Mhz. "f 1 1600" will + * update maximum fabric clock to be 1600Mhz. For core * clocks on VanGogh, the string contains "p core index clock". * E.g., "p 2 0 800" would set the minimum core clock on core * 2 to 800Mhz. @@ -769,6 +771,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, type = PP_OD_EDIT_CCLK_VDDC_TABLE; else if (*buf == 'm') type = PP_OD_EDIT_MCLK_VDDC_TABLE; + else if (*buf == 'f') + type = PP_OD_EDIT_FCLK_TABLE; else if (*buf == 'r') type = PP_OD_RESTORE_DEFAULT_TABLE; else if (*buf == 'c') @@ -844,9 +848,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, struct amdgpu_device *adev = drm_to_adev(ddev); int size = 0; int ret; - enum pp_clock_type od_clocks[6] = { + enum pp_clock_type od_clocks[] = { OD_SCLK, OD_MCLK, + OD_FCLK, OD_VDDC_CURVE, OD_RANGE, OD_VDDGFX_OFFSET, @@ -858,18 +863,8 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, if (ret) return ret; - for (clk_index = 0 ; clk_index < 6 ; clk_index++) { - ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); - if (ret) - break; - } - if (ret == -ENOENT) { - size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); - size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); - size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); - size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); - size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); - size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); + for (clk_index = 0 ; clk_index < ARRAY_SIZE(od_clocks) ; clk_index++) { + amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size); } if (size == 0) @@ -999,8 +994,8 @@ static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev, return ret; ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size); - if (ret == -ENOENT) - size = amdgpu_dpm_print_clock_levels(adev, type, buf); + if (ret) + return ret; if (size == 0) size = sysfs_emit(buf, "\n"); @@ -1919,8 +1914,6 @@ static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr, uint32_t mask, enum amdgpu_device_attr_states *states) { - uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0); - *states = ATTR_STATE_SUPPORTED; if (!amdgpu_dpm_is_overdrive_supported(adev)) { @@ -1928,10 +1921,8 @@ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdg return 0; } - /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0 SRIOV/BM support */ - if (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0)) { + /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0, 12.1.0 SRIOV/BM support */ + if (amdgpu_is_multi_aid(adev)) { if (amdgpu_sriov_multi_vf_mode(adev)) *states = ATTR_STATE_UNSUPPORTED; return 0; @@ -2009,9 +2000,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd gc_ver == IP_VERSION(11, 5, 0) || gc_ver == IP_VERSION(11, 0, 2) || gc_ver == IP_VERSION(11, 0, 3) || - gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) + amdgpu_is_multi_aid(adev))) *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) { if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2032,9 +2021,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd gc_ver == IP_VERSION(11, 5, 0) || gc_ver == IP_VERSION(11, 0, 2) || gc_ver == IP_VERSION(11, 0, 3) || - gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) + amdgpu_is_multi_aid(adev))) *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) { if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2044,9 +2031,7 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd *states = ATTR_STATE_UNSUPPORTED; } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) { if (gc_ver == IP_VERSION(9, 4, 2) || - gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0)) + amdgpu_is_multi_aid(adev)) *states = ATTR_STATE_UNSUPPORTED; } @@ -2081,9 +2066,10 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd * for user application to monitor various board reated attributes. * * The amdgpu driver provides a sysfs API for reporting board attributes. Presently, - * seven types of attributes are reported. Baseboard temperature and + * nine types of attributes are reported. Baseboard temperature and * gpu board temperature are reported as binary files. Npm status, current node power limit, - * max node power limit, node power and global ppt residency is reported as ASCII text file. + * max node power limit, node power, global ppt residency, baseboard_power, baseboard_power_limit + * is reported as ASCII text file. * * * .. code-block:: console * @@ -2100,6 +2086,10 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd * hexdump /sys/bus/pci/devices/.../board/node_power * * hexdump /sys/bus/pci/devices/.../board/global_ppt_resid + * + * hexdump /sys/bus/pci/devices/.../board/baseboard_power + * + * hexdump /sys/bus/pci/devices/.../board/baseboard_power_limit */ /** @@ -2294,6 +2284,52 @@ static ssize_t amdgpu_show_max_node_power_limit(struct device *dev, return sysfs_emit(buf, "%u\n", max_nplimit); } +/** + * DOC: baseboard_power + * + * The amdgpu driver provides a sysfs API for retrieving current ubb power in watts. + * The file baseboard_power is used for this. + */ +static ssize_t amdgpu_show_baseboard_power(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 ubbpower; + int r; + + /* get the ubb power */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_UBB_POWER, + (void *)&ubbpower); + if (r) + return r; + + return sysfs_emit(buf, "%u\n", ubbpower); +} + +/** + * DOC: baseboard_power_limit + * + * The amdgpu driver provides a sysfs API for retrieving threshold ubb power in watts. + * The file baseboard_power_limit is used for this. + */ +static ssize_t amdgpu_show_baseboard_power_limit(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + u32 ubbpowerlimit; + int r; + + /* get the ubb power limit */ + r = amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, + (void *)&ubbpowerlimit); + if (r) + return r; + + return sysfs_emit(buf, "%u\n", ubbpowerlimit); +} + static DEVICE_ATTR(baseboard_temp, 0444, amdgpu_get_baseboard_temp_metrics, NULL); static DEVICE_ATTR(gpuboard_temp, 0444, amdgpu_get_gpuboard_temp_metrics, NULL); static DEVICE_ATTR(cur_node_power_limit, 0444, amdgpu_show_cur_node_power_limit, NULL); @@ -2301,6 +2337,8 @@ static DEVICE_ATTR(node_power, 0444, amdgpu_show_node_power, NULL); static DEVICE_ATTR(global_ppt_resid, 0444, amdgpu_show_global_ppt_resid, NULL); static DEVICE_ATTR(max_node_power_limit, 0444, amdgpu_show_max_node_power_limit, NULL); static DEVICE_ATTR(npm_status, 0444, amdgpu_show_npm_status, NULL); +static DEVICE_ATTR(baseboard_power, 0444, amdgpu_show_baseboard_power, NULL); +static DEVICE_ATTR(baseboard_power_limit, 0444, amdgpu_show_baseboard_power_limit, NULL); static struct attribute *board_attrs[] = { &dev_attr_baseboard_temp.attr, @@ -2607,6 +2645,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ case IP_VERSION(11, 0, 3): case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): + case IP_VERSION(12, 1, 0): *states = ATTR_STATE_SUPPORTED; break; default: @@ -3688,8 +3727,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, /* Skip crit temp on APU */ if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) || - (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) && + amdgpu_is_multi_aid(adev)) && (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)) return 0; @@ -3771,18 +3809,14 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */ adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */ - (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) && + amdgpu_is_multi_aid(adev)) && (attr == &sensor_dev_attr_in0_input.dev_attr.attr || attr == &sensor_dev_attr_in0_label.dev_attr.attr)) return 0; /* only APUs other than gc 9,4,3 have vddnb */ if ((!(adev->flags & AMD_IS_APU) || - (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0))) && + amdgpu_is_multi_aid(adev)) && (attr == &sensor_dev_attr_in1_input.dev_attr.attr || attr == &sensor_dev_attr_in1_label.dev_attr.attr)) return 0; @@ -3811,9 +3845,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, return 0; /* hotspot temperature for gc 9,4,3*/ - if (gc_ver == IP_VERSION(9, 4, 3) || - gc_ver == IP_VERSION(9, 4, 4) || - gc_ver == IP_VERSION(9, 5, 0)) { + if (amdgpu_is_multi_aid(adev)) { if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr || attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || attr == &sensor_dev_attr_temp1_label.dev_attr.attr) @@ -3833,7 +3865,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)) return 0; - /* only Vangogh has fast PPT limit and power labels */ + /* only a few GPUs have fast PPT limit and power labels */ if ((attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || attr == &sensor_dev_attr_power2_cap.dev_attr.attr || @@ -3868,7 +3900,9 @@ static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev, if (ret) return ret; - size = amdgpu_dpm_print_clock_levels(adev, od_type, buf); + ret = amdgpu_dpm_emit_clock_levels(adev, od_type, buf, &size); + if (ret) + return ret; if (size == 0) size = sysfs_emit(buf, "\n"); @@ -4728,6 +4762,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) dev_info(adev->dev, "overdrive feature is not supported\n"); } +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) != -EOPNOTSUPP) { ret = devm_device_add_group(adev->dev, @@ -4735,6 +4770,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) if (ret) goto err_out1; } +#endif if (amdgpu_dpm_is_temp_metrics_supported(adev, SMU_TEMP_METRIC_GPUBOARD)) { ret = devm_device_add_group(adev->dev, @@ -4756,6 +4792,14 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_npm_status.attr, amdgpu_board_attr_group.name); } + if (amdgpu_pm_get_sensor_generic(adev, AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, + (void *)&tmp) != -EOPNOTSUPP) { + sysfs_add_file_to_group(&adev->dev->kobj, + &dev_attr_baseboard_power_limit.attr, + amdgpu_board_attr_group.name); + sysfs_add_file_to_group(&adev->dev->kobj, &dev_attr_baseboard_power.attr, + amdgpu_board_attr_group.name); + } } adev->pm.sysfs_initialized = true; @@ -5051,5 +5095,6 @@ void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) adev->pm.smu_prv_buffer_size); amdgpu_dpm_stb_debug_fs_init(adev); + amdgpu_dpm_phase_det_debugfs_init(adev); #endif } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index aa3f427819a09..6a73df27088e4 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -608,6 +608,7 @@ ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf); int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev); +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev); int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask); bool amdgpu_dpm_reset_vcn_is_supported(struct amdgpu_device *adev); bool amdgpu_dpm_is_temp_metrics_supported(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 695432d3045ff..b75a6031c68a5 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -3454,9 +3454,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, if (adev->asic_type == CHIP_HAINAN) { if ((adev->pdev->revision == 0x81) || (adev->pdev->revision == 0xC3) || + (adev->pdev->device == 0x6660) || (adev->pdev->device == 0x6664) || (adev->pdev->device == 0x6665) || - (adev->pdev->device == 0x6667)) { + (adev->pdev->device == 0x6667) || + (adev->pdev->device == 0x666F)) { max_sclk = 75000; } if ((adev->pdev->revision == 0xC3) || @@ -3464,6 +3466,11 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev, max_sclk = 60000; max_mclk = 80000; } + if ((adev->pdev->device == 0x666f) && + (adev->pdev->revision == 0x00)) { + max_sclk = 80000; + max_mclk = 95000; + } } else if (adev->asic_type == CHIP_OLAND) { if ((adev->pdev->revision == 0xC7) || (adev->pdev->revision == 0x80) || @@ -7801,13 +7808,12 @@ static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev); - DRM_INFO("amdgpu: dpm initialized\n"); - + drm_info(adev_to_drm(adev), "si dpm initialized\n"); return 0; dpm_failed: si_dpm_fini(adev); - DRM_ERROR("amdgpu: dpm initialization failed\n"); + drm_err(adev_to_drm(adev), "dpm initialization failed\n"); return ret; } diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c index 281a5e377aee4..e1c509bfc3902 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_smc.c @@ -65,7 +65,7 @@ int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, addr = smc_start_address; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); while (byte_count >= 4) { /* SMC address space is BE */ data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; @@ -109,7 +109,7 @@ int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, } done: - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return ret; } @@ -252,7 +252,7 @@ int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) if (ucode_size & 3) return -EINVAL; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); WREG32(mmSMC_IND_INDEX_0, ucode_start_address); WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); while (ucode_size >= 4) { @@ -265,7 +265,7 @@ int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit) ucode_size -= 4; } WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return 0; } @@ -276,11 +276,11 @@ int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, unsigned long flags; int ret; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); ret = si_set_smc_sram_address(adev, smc_address, limit); if (ret == 0) *value = RREG32(mmSMC_IND_DATA_0); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return ret; } @@ -291,11 +291,11 @@ int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, unsigned long flags; int ret; - spin_lock_irqsave(&adev->smc_idx_lock, flags); + spin_lock_irqsave(&adev->reg.smc.lock, flags); ret = si_set_smc_sram_address(adev, smc_address, limit); if (ret == 0) WREG32(mmSMC_IND_DATA_0, value); - spin_unlock_irqrestore(&adev->smc_idx_lock, flags); + spin_unlock_irqrestore(&adev->reg.smc.lock, flags); return ret; } diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 3aaf3dd71868c..0bbb89788335e 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -198,7 +198,7 @@ static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) &adev->pm.smu_prv_buffer, &gpu_addr, &cpu_ptr)) { - DRM_ERROR("amdgpu: failed to create smu prv buffer\n"); + drm_err(adev_to_drm(adev), "failed to create smu prv buffer\n"); return; } @@ -213,7 +213,7 @@ static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) if (r) { amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); adev->pm.smu_prv_buffer = NULL; - DRM_ERROR("amdgpu: failed to notify SMU buffer address\n"); + drm_err(adev_to_drm(adev), "failed to notify SMU buffer address\n"); } } @@ -724,21 +724,6 @@ static int pp_dpm_emit_clock_levels(void *handle, return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset); } -static int pp_dpm_print_clock_levels(void *handle, - enum pp_clock_type type, char *buf) -{ - struct pp_hwmgr *hwmgr = handle; - - if (!hwmgr || !hwmgr->pm_en) - return -EINVAL; - - if (hwmgr->hwmgr_func->print_clock_levels == NULL) { - pr_info_ratelimited("%s was not implemented.\n", __func__); - return 0; - } - return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf); -} - static int pp_dpm_get_sclk_od(void *handle) { struct pp_hwmgr *hwmgr = handle; @@ -1068,7 +1053,8 @@ static int pp_get_current_clocks(void *handle, &hw_clocks, PHM_PerformanceLevelDesignation_Activity); if (ret) { - pr_debug("Error in phm_get_clock_info \n"); + drm_err(adev_to_drm(hwmgr->adev), + "Error in phm_get_clock_info\n"); return -EINVAL; } @@ -1582,7 +1568,6 @@ static const struct amd_pm_funcs pp_dpm_funcs = { .set_pp_table = pp_dpm_set_pp_table, .force_clock_level = pp_dpm_force_clock_level, .emit_clock_levels = pp_dpm_emit_clock_levels, - .print_clock_levels = pp_dpm_print_clock_levels, .get_sclk_od = pp_dpm_get_sclk_od, .set_sclk_od = pp_dpm_set_sclk_od, .get_mclk_od = pp_dpm_get_mclk_od, diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c index 14ccd743ca1d0..8de8d66df95f4 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c @@ -1024,13 +1024,14 @@ static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, return 0; } -static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) +static int smu10_emit_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf, + int *offset) { struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); struct smu10_voltage_dependency_table *mclk_table = data->clock_vol_info.vdd_dep_on_fclk; - uint32_t i, now, size = 0; + uint32_t i, now, size = *offset; uint32_t min_freq, max_freq = 0; int ret = 0; @@ -1048,15 +1049,15 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, else i = 1; - size += sprintf(buf + size, "0: %uMhz %s\n", - data->gfx_min_freq_limit/100, - i == 0 ? "*" : ""); - size += sprintf(buf + size, "1: %uMhz %s\n", - i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK, - i == 1 ? "*" : ""); - size += sprintf(buf + size, "2: %uMhz %s\n", - data->gfx_max_freq_limit/100, - i == 2 ? "*" : ""); + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", + data->gfx_min_freq_limit / 100, + i == 0 ? "*" : ""); + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", + i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK, + i == 1 ? "*" : ""); + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", + data->gfx_max_freq_limit / 100, + i == 2 ? "*" : ""); break; case PP_MCLK: ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); @@ -1064,11 +1065,12 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, return ret; for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, - mclk_table->entries[i].clk / 100, - ((mclk_table->entries[i].clk / 100) - == now) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + mclk_table->entries[i].clk / 100, + ((mclk_table->entries[i].clk / 100) == now) ? + "*" : + ""); break; case OD_SCLK: if (hwmgr->od_enabled) { @@ -1079,11 +1081,17 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, if (ret) return ret; - size += sprintf(buf + size, "%s:\n", "OD_SCLK"); - size += sprintf(buf + size, "0: %10uMhz\n", - (data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq); - size += sprintf(buf + size, "1: %10uMhz\n", - (data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); + size += sysfs_emit_at( + buf, size, "0: %10uMhz\n", + (data->gfx_actual_soft_min_freq > 0) ? + data->gfx_actual_soft_min_freq : + min_freq); + size += sysfs_emit_at( + buf, size, "1: %10uMhz\n", + (data->gfx_actual_soft_max_freq > 0) ? + data->gfx_actual_soft_max_freq : + max_freq); } break; case OD_RANGE: @@ -1095,16 +1103,19 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr, if (ret) return ret; - size += sprintf(buf + size, "%s:\n", "OD_RANGE"); - size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", - min_freq, max_freq); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); + size += sysfs_emit_at(buf, size, + "SCLK: %7uMHz %10uMHz\n", + min_freq, max_freq); } break; default: break; } - return size; + *offset = size; + + return 0; } static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, @@ -1652,7 +1663,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = { .set_cpu_power_state = smu10_set_cpu_power_state, .store_cc6_data = smu10_store_cc6_data, .force_clock_level = smu10_force_clock_level, - .print_clock_levels = smu10_print_clock_levels, + .emit_clock_levels = smu10_emit_clock_levels, .get_dal_power_level = smu10_get_dal_power_level, .get_performance_level = smu10_get_performance_level, .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks, diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h index 42adc2a3dcbc1..ec6cec793c25c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h @@ -192,7 +192,11 @@ struct smu10_clock_voltage_dependency_record { struct smu10_voltage_dependency_table { uint32_t count; - struct smu10_clock_voltage_dependency_record entries[] __counted_by(count); + struct smu10_clock_voltage_dependency_record entries[] +#ifdef __counted_by + __counted_by(count) +#endif + ; }; struct smu10_clock_voltage_information { diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c index 9b28c07282699..2be584aefd0ad 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c @@ -4961,8 +4961,9 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, return 0; } -static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) +static int smu7_emit_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf, + int *offset) { struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); @@ -4971,7 +4972,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); - int size = 0, ret = 0; + int size = *offset, ret = 0; uint32_t i, now, clock, pcie_speed; switch (type) { @@ -4987,9 +4988,10 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, now = i; for (i = 0; i < sclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, sclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, + sclk_table->dpm_levels[i].value / + 100, + (i == now) ? "*" : ""); break; case PP_MCLK: ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency, &clock); @@ -5003,9 +5005,10 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, now = i; for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, mclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, + mclk_table->dpm_levels[i].value / + 100, + (i == now) ? "*" : ""); break; case PP_PCIE: pcie_speed = smu7_get_current_pcie_speed(hwmgr); @@ -5017,48 +5020,68 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, now = i; for (i = 0; i < pcie_table->count; i++) - size += sprintf(buf + size, "%d: %s %s\n", i, - (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : - (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : - (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", - (i == now) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %s %s\n", i, + (pcie_table->dpm_levels[i].value == 0) ? + "2.5GT/s, x8" : + (pcie_table->dpm_levels[i].value == 1) ? + "5.0GT/s, x16" : + (pcie_table->dpm_levels[i].value == 2) ? + "8.0GT/s, x16" : + "", + (i == now) ? "*" : ""); break; case OD_SCLK: if (hwmgr->od_enabled) { - size += sprintf(buf + size, "%s:\n", "OD_SCLK"); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); for (i = 0; i < odn_sclk_table->num_of_pl; i++) - size += sprintf(buf + size, "%d: %10uMHz %10umV\n", - i, odn_sclk_table->entries[i].clock/100, + size += sysfs_emit_at( + buf, size, "%d: %10uMHz %10umV\n", i, + odn_sclk_table->entries[i].clock / 100, odn_sclk_table->entries[i].vddc); } break; case OD_MCLK: if (hwmgr->od_enabled) { - size += sprintf(buf + size, "%s:\n", "OD_MCLK"); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); for (i = 0; i < odn_mclk_table->num_of_pl; i++) - size += sprintf(buf + size, "%d: %10uMHz %10umV\n", - i, odn_mclk_table->entries[i].clock/100, + size += sysfs_emit_at( + buf, size, "%d: %10uMHz %10umV\n", i, + odn_mclk_table->entries[i].clock / 100, odn_mclk_table->entries[i].vddc); } break; case OD_RANGE: if (hwmgr->od_enabled) { - size += sprintf(buf + size, "%s:\n", "OD_RANGE"); - size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.engineClock/100); - size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); - size += sprintf(buf + size, "VDDC: %7umV %11umV\n", - data->odn_dpm_table.min_vddc, - data->odn_dpm_table.max_vddc); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); + size += sysfs_emit_at( + buf, size, "SCLK: %7uMHz %10uMHz\n", + data->golden_dpm_table.sclk_table.dpm_levels[0] + .value / + 100, + hwmgr->platform_descriptor.overdriveLimit + .engineClock / + 100); + size += sysfs_emit_at( + buf, size, "MCLK: %7uMHz %10uMHz\n", + data->golden_dpm_table.mclk_table.dpm_levels[0] + .value / + 100, + hwmgr->platform_descriptor.overdriveLimit + .memoryClock / + 100); + size += sysfs_emit_at(buf, size, "VDDC: %7umV %11umV\n", + data->odn_dpm_table.min_vddc, + data->odn_dpm_table.max_vddc); } break; default: break; } - return size; + + *offset = size; + + return 0; } static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) @@ -5775,7 +5798,7 @@ static const struct pp_hwmgr_func smu7_hwmgr_funcs = { .set_fan_control_mode = smu7_set_fan_control_mode, .get_fan_control_mode = smu7_get_fan_control_mode, .force_clock_level = smu7_force_clock_level, - .print_clock_levels = smu7_print_clock_levels, + .emit_clock_levels = smu7_emit_clock_levels, .powergate_gfx = smu7_powergate_gfx, .get_sclk_od = smu7_get_sclk_od, .set_sclk_od = smu7_set_sclk_od, diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c index 9b20076e26c0f..736e5a8af4779 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c @@ -1564,14 +1564,15 @@ static int smu8_force_clock_level(struct pp_hwmgr *hwmgr, return 0; } -static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) +static int smu8_emit_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf, + int *offset) { struct smu8_hwmgr *data = hwmgr->backend; struct phm_clock_voltage_dependency_table *sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; uint32_t i, now; - int size = 0; + int size = *offset; switch (type) { case PP_SCLK: @@ -1582,9 +1583,9 @@ static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, CURR_SCLK_INDEX); for (i = 0; i < sclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, sclk_table->entries[i].clk / 100, - (i == now) ? "*" : ""); + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, + sclk_table->entries[i].clk / 100, + (i == now) ? "*" : ""); break; case PP_MCLK: now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, @@ -1594,14 +1595,20 @@ static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr, CURR_MCLK_INDEX); for (i = SMU8_NUM_NBPMEMORYCLOCK; i > 0; i--) - size += sprintf(buf + size, "%d: %uMhz %s\n", - SMU8_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100, - (SMU8_NUM_NBPMEMORYCLOCK-i == now) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", + SMU8_NUM_NBPMEMORYCLOCK - i, + data->sys_info.nbp_memory_clock[i - 1] / 100, + (SMU8_NUM_NBPMEMORYCLOCK - i == now) ? "*" : + ""); break; default: break; } - return size; + + *offset = size; + + return 0; } static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, @@ -2055,7 +2062,7 @@ static const struct pp_hwmgr_func smu8_hwmgr_funcs = { .set_cpu_power_state = smu8_set_cpu_power_state, .store_cc6_data = smu8_store_cc6_data, .force_clock_level = smu8_force_clock_level, - .print_clock_levels = smu8_print_clock_levels, + .emit_clock_levels = smu8_emit_clock_levels, .get_dal_power_level = smu8_get_dal_power_level, .get_performance_level = smu8_get_performance_level, .get_current_shallow_sleep_clocks = smu8_get_current_shallow_sleep_clocks, diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c index 9ace863792d48..1b8a57d987597 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c @@ -4825,146 +4825,6 @@ static int vega10_emit_clock_levels(struct pp_hwmgr *hwmgr, return ret; } -static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) -{ - struct vega10_hwmgr *data = hwmgr->backend; - struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); - struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); - struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table); - struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table); - struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL; - uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; - PPTable_t *pptable = &(data->smc_state_table.pp_table); - - int i, ret, now, size = 0, count = 0; - - switch (type) { - case PP_SCLK: - if (data->registry_data.sclk_dpm_key_disabled) - break; - - ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex, &now); - if (ret) - break; - - if (hwmgr->pp_one_vf && - (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) - count = 5; - else - count = sclk_table->count; - for (i = 0; i < count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, sclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_MCLK: - if (data->registry_data.mclk_dpm_key_disabled) - break; - - ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex, &now); - if (ret) - break; - - for (i = 0; i < mclk_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, mclk_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_SOCCLK: - if (data->registry_data.socclk_dpm_key_disabled) - break; - - ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex, &now); - if (ret) - break; - - for (i = 0; i < soc_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, soc_table->dpm_levels[i].value / 100, - (i == now) ? "*" : ""); - break; - case PP_DCEFCLK: - if (data->registry_data.dcefclk_dpm_key_disabled) - break; - - ret = smum_send_msg_to_smc_with_parameter(hwmgr, - PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK, &now); - if (ret) - break; - - for (i = 0; i < dcef_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, dcef_table->dpm_levels[i].value / 100, - (dcef_table->dpm_levels[i].value / 100 == now) ? - "*" : ""); - break; - case PP_PCIE: - current_gen_speed = - vega10_get_current_pcie_link_speed_level(hwmgr); - current_lane_width = - vega10_get_current_pcie_link_width_level(hwmgr); - for (i = 0; i < NUM_LINK_LEVELS; i++) { - gen_speed = pptable->PcieGenSpeed[i]; - lane_width = pptable->PcieLaneCount[i]; - - size += sprintf(buf + size, "%d: %s %s %s\n", i, - (gen_speed == 0) ? "2.5GT/s," : - (gen_speed == 1) ? "5.0GT/s," : - (gen_speed == 2) ? "8.0GT/s," : - (gen_speed == 3) ? "16.0GT/s," : "", - (lane_width == 1) ? "x1" : - (lane_width == 2) ? "x2" : - (lane_width == 3) ? "x4" : - (lane_width == 4) ? "x8" : - (lane_width == 5) ? "x12" : - (lane_width == 6) ? "x16" : "", - (current_gen_speed == gen_speed) && - (current_lane_width == lane_width) ? - "*" : ""); - } - break; - - case OD_SCLK: - if (hwmgr->od_enabled) { - size += sprintf(buf + size, "%s:\n", "OD_SCLK"); - podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_sclk; - for (i = 0; i < podn_vdd_dep->count; i++) - size += sprintf(buf + size, "%d: %10uMhz %10umV\n", - i, podn_vdd_dep->entries[i].clk / 100, - podn_vdd_dep->entries[i].vddc); - } - break; - case OD_MCLK: - if (hwmgr->od_enabled) { - size += sprintf(buf + size, "%s:\n", "OD_MCLK"); - podn_vdd_dep = &data->odn_dpm_table.vdd_dep_on_mclk; - for (i = 0; i < podn_vdd_dep->count; i++) - size += sprintf(buf + size, "%d: %10uMhz %10umV\n", - i, podn_vdd_dep->entries[i].clk/100, - podn_vdd_dep->entries[i].vddc); - } - break; - case OD_RANGE: - if (hwmgr->od_enabled) { - size += sprintf(buf + size, "%s:\n", "OD_RANGE"); - size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.gfx_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.engineClock/100); - size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", - data->golden_dpm_table.mem_table.dpm_levels[0].value/100, - hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); - size += sprintf(buf + size, "VDDC: %7umV %11umV\n", - data->odn_dpm_table.min_vddc, - data->odn_dpm_table.max_vddc); - } - break; - default: - break; - } - return size; -} - static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { struct vega10_hwmgr *data = hwmgr->backend; @@ -5792,7 +5652,6 @@ static const struct pp_hwmgr_func vega10_hwmgr_funcs = { .display_clock_voltage_request = vega10_display_clock_voltage_request, .force_clock_level = vega10_force_clock_level, .emit_clock_levels = vega10_emit_clock_levels, - .print_clock_levels = vega10_print_clock_levels, .display_config_changed = vega10_display_configuration_changed_task, .powergate_uvd = vega10_power_gate_uvd, .powergate_vce = vega10_power_gate_vce, diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c index 10fd4e9f016cd..5a987a535e73e 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c @@ -2271,11 +2271,12 @@ static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) return link_speed[speed_level]; } -static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) +static int vega12_emit_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf, + int *offset) { - int i, now, size = 0; struct pp_clock_levels_with_latency clocks; + int i, now, size = *offset; switch (type) { case PP_SCLK: @@ -2289,9 +2290,13 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, "Attempt to get gfx clk levels Failed!", return -1); for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz / 1000 == + now / 100) ? + "*" : + ""); break; case PP_MCLK: @@ -2305,9 +2310,13 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, "Attempt to get memory clk levels Failed!", return -1); for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz / 1000 == + now / 100) ? + "*" : + ""); break; case PP_SOCCLK: @@ -2323,9 +2332,12 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, "Attempt to get soc clk levels Failed!", return -1); for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz / 1000 == now) ? + "*" : + ""); break; case PP_DCEFCLK: @@ -2341,9 +2353,12 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, "Attempt to get dcef clk levels Failed!", return -1); for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz / 1000 == now) ? + "*" : + ""); break; case PP_PCIE: @@ -2352,7 +2367,10 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, default: break; } - return size; + + *offset = size; + + return 0; } static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) @@ -2951,7 +2969,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = { .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges, .display_clock_voltage_request = vega12_display_clock_voltage_request, .force_clock_level = vega12_force_clock_level, - .print_clock_levels = vega12_print_clock_levels, + .emit_clock_levels = vega12_emit_clock_levels, .apply_clocks_adjust_rules = vega12_apply_clocks_adjust_rules, .pre_display_config_changed = diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c index baf251fe5d828..5193b7d0e11be 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c @@ -3362,8 +3362,9 @@ static int vega20_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) return link_speed[speed_level]; } -static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, - enum pp_clock_type type, char *buf) +static int vega20_emit_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf, + int *offset) { struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); @@ -3375,7 +3376,7 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency clocks; struct vega20_single_dpm_table *fclk_dpm_table = &(data->dpm_table.fclk_table); - int i, now, size = 0; + int i, now, size = *offset; int ret = 0; uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; @@ -3387,15 +3388,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, return ret); if (vega20_get_sclks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); + size += sysfs_emit_at(buf, size, + "0: %uMhz * (DPM disabled)\n", + now / 100); break; } for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz == now * 10) ? + "*" : + ""); break; case PP_MCLK: @@ -3405,15 +3410,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, return ret); if (vega20_get_memclocks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); + size += sysfs_emit_at(buf, size, + "0: %uMhz * (DPM disabled)\n", + now / 100); break; } for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz == now * 10) ? + "*" : + ""); break; case PP_SOCCLK: @@ -3423,15 +3432,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, return ret); if (vega20_get_socclocks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); + size += sysfs_emit_at(buf, size, + "0: %uMhz * (DPM disabled)\n", + now / 100); break; } for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz == now * 10) ? + "*" : + ""); break; case PP_FCLK: @@ -3441,9 +3454,13 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, return ret); for (i = 0; i < fclk_dpm_table->count; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, fclk_dpm_table->dpm_levels[i].value, - fclk_dpm_table->dpm_levels[i].value == (now / 100) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + fclk_dpm_table->dpm_levels[i].value, + fclk_dpm_table->dpm_levels[i].value == + (now / 100) ? + "*" : + ""); break; case PP_DCEFCLK: @@ -3453,15 +3470,19 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, return ret); if (vega20_get_dcefclocks(hwmgr, &clocks)) { - size += sprintf(buf + size, "0: %uMhz * (DPM disabled)\n", - now / 100); + size += sysfs_emit_at(buf, size, + "0: %uMhz * (DPM disabled)\n", + now / 100); break; } for (i = 0; i < clocks.num_levels; i++) - size += sprintf(buf + size, "%d: %uMhz %s\n", - i, clocks.data[i].clocks_in_khz / 1000, - (clocks.data[i].clocks_in_khz == now * 10) ? "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", i, + clocks.data[i].clocks_in_khz / 1000, + (clocks.data[i].clocks_in_khz == now * 10) ? + "*" : + ""); break; case PP_PCIE: @@ -3473,40 +3494,45 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, gen_speed = pptable->PcieGenSpeed[i]; lane_width = pptable->PcieLaneCount[i]; - size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i, - (gen_speed == 0) ? "2.5GT/s," : - (gen_speed == 1) ? "5.0GT/s," : - (gen_speed == 2) ? "8.0GT/s," : - (gen_speed == 3) ? "16.0GT/s," : "", - (lane_width == 1) ? "x1" : - (lane_width == 2) ? "x2" : - (lane_width == 3) ? "x4" : - (lane_width == 4) ? "x8" : - (lane_width == 5) ? "x12" : - (lane_width == 6) ? "x16" : "", - pptable->LclkFreq[i], - (current_gen_speed == gen_speed) && - (current_lane_width == lane_width) ? - "*" : ""); + size += sysfs_emit_at( + buf, size, "%d: %s %s %dMhz %s\n", i, + (gen_speed == 0) ? "2.5GT/s," : + (gen_speed == 1) ? "5.0GT/s," : + (gen_speed == 2) ? "8.0GT/s," : + (gen_speed == 3) ? "16.0GT/s," : + "", + (lane_width == 1) ? "x1" : + (lane_width == 2) ? "x2" : + (lane_width == 3) ? "x4" : + (lane_width == 4) ? "x8" : + (lane_width == 5) ? "x12" : + (lane_width == 6) ? "x16" : + "", + pptable->LclkFreq[i], + (current_gen_speed == gen_speed) && + (current_lane_width == + lane_width) ? + "*" : + ""); } break; case OD_SCLK: if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { - size += sprintf(buf + size, "%s:\n", "OD_SCLK"); - size += sprintf(buf + size, "0: %10uMhz\n", - od_table->GfxclkFmin); - size += sprintf(buf + size, "1: %10uMhz\n", - od_table->GfxclkFmax); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); + size += sysfs_emit_at(buf, size, "0: %10uMhz\n", + od_table->GfxclkFmin); + size += sysfs_emit_at(buf, size, "1: %10uMhz\n", + od_table->GfxclkFmax); } break; case OD_MCLK: if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { - size += sprintf(buf + size, "%s:\n", "OD_MCLK"); - size += sprintf(buf + size, "1: %10uMhz\n", - od_table->UclkFmax); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); + size += sysfs_emit_at(buf, size, "1: %10uMhz\n", + od_table->UclkFmax); } break; @@ -3518,32 +3544,38 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { - size += sprintf(buf + size, "%s:\n", "OD_VDDC_CURVE"); - size += sprintf(buf + size, "0: %10uMhz %10dmV\n", - od_table->GfxclkFreq1, - od_table->GfxclkVolt1 / VOLTAGE_SCALE); - size += sprintf(buf + size, "1: %10uMhz %10dmV\n", - od_table->GfxclkFreq2, - od_table->GfxclkVolt2 / VOLTAGE_SCALE); - size += sprintf(buf + size, "2: %10uMhz %10dmV\n", - od_table->GfxclkFreq3, - od_table->GfxclkVolt3 / VOLTAGE_SCALE); + size += sysfs_emit_at(buf, size, "%s:\n", + "OD_VDDC_CURVE"); + size += sysfs_emit_at(buf, size, "0: %10uMhz %10dmV\n", + od_table->GfxclkFreq1, + od_table->GfxclkVolt1 / + VOLTAGE_SCALE); + size += sysfs_emit_at(buf, size, "1: %10uMhz %10dmV\n", + od_table->GfxclkFreq2, + od_table->GfxclkVolt2 / + VOLTAGE_SCALE); + size += sysfs_emit_at(buf, size, "2: %10uMhz %10dmV\n", + od_table->GfxclkFreq3, + od_table->GfxclkVolt3 / + VOLTAGE_SCALE); } break; case OD_RANGE: - size += sprintf(buf + size, "%s:\n", "OD_RANGE"); + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id && od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) { - size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n", + size += sysfs_emit_at( + buf, size, "SCLK: %7uMhz %10uMhz\n", od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value, od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value); } if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) { - size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n", + size += sysfs_emit_at( + buf, size, "MCLK: %7uMhz %10uMhz\n", od8_settings[OD8_SETTING_UCLK_FMAX].min_value, od8_settings[OD8_SETTING_UCLK_FMAX].max_value); } @@ -3554,31 +3586,52 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr, od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id && od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id && od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) { - size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", + size += sysfs_emit_at( + buf, size, + "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value, - od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value); - size += sprintf(buf + size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value, - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value); - size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", + od8_settings[OD8_SETTING_GFXCLK_FREQ1] + .max_value); + size += sysfs_emit_at( + buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", + od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1] + .min_value, + od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1] + .max_value); + size += sysfs_emit_at( + buf, size, + "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value, - od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value); - size += sprintf(buf + size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value, - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value); - size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", + od8_settings[OD8_SETTING_GFXCLK_FREQ2] + .max_value); + size += sysfs_emit_at( + buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", + od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2] + .min_value, + od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2] + .max_value); + size += sysfs_emit_at( + buf, size, + "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value, - od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value); - size += sprintf(buf + size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value, - od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value); + od8_settings[OD8_SETTING_GFXCLK_FREQ3] + .max_value); + size += sysfs_emit_at( + buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", + od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3] + .min_value, + od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3] + .max_value); } break; default: break; } - return size; + + *offset = size; + + return 0; } static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, @@ -4412,7 +4465,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = { .odn_edit_dpm_table = vega20_odn_edit_dpm_table, /* for sysfs to retrive/set gfxclk/memclk */ .force_clock_level = vega20_force_clock_level, - .print_clock_levels = vega20_print_clock_levels, + .emit_clock_levels = vega20_emit_clock_levels, .read_sensor = vega20_read_sensor, .get_ppfeature_status = vega20_get_ppfeature_status, .set_ppfeature_status = vega20_set_ppfeature_status, diff --git a/drivers/gpu/drm/amd/pm/swsmu/Makefile b/drivers/gpu/drm/amd/pm/swsmu/Makefile index e5fdda49c96ce..178b102a8845d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/Makefile +++ b/drivers/gpu/drm/amd/pm/swsmu/Makefile @@ -22,7 +22,7 @@ AMD_SWSMU_PATH = ../pm/swsmu -SWSMU_LIBS = smu11 smu12 smu13 smu14 +SWSMU_LIBS = smu11 smu12 smu13 smu14 smu15 AMD_SWSMU = $(addsuffix /Makefile,$(addprefix $(FULL_AMD_PATH)/pm/swsmu/,$(SWSMU_LIBS))) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index f51fa265230b3..4a69f2c0d1dde 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -46,6 +46,8 @@ #include "smu_v13_0_7_ppt.h" #include "smu_v14_0_0_ppt.h" #include "smu_v14_0_2_ppt.h" +#include "smu_v15_0_0_ppt.h" +#include "smu_v15_0_8_ppt.h" #include "amd_pcie.h" /* @@ -618,12 +620,27 @@ int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type ms struct smu_context *smu = adev->powerplay.pp_handle; int ret = -EOPNOTSUPP; + if (!smu) + return ret; + if (smu->ppt_funcs && smu->ppt_funcs->ras_send_msg) ret = smu->ppt_funcs->ras_send_msg(smu, msg, param, read_arg); return ret; } +int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, + enum smu_feature_mask mask) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + int ret = 0; + + if (smu->ppt_funcs && smu->ppt_funcs->feature_is_enabled) + ret = smu->ppt_funcs->feature_is_enabled(smu, mask); + + return ret; +} + static int smu_sys_get_pp_table(void *handle, char **table) { @@ -687,12 +704,8 @@ static int smu_sys_set_pp_table(void *handle, return ret; } -static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) +static int smu_init_driver_allowed_feature_mask(struct smu_context *smu) { - struct smu_feature *feature = &smu->smu_feature; - uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32]; - int ret = 0; - /* * With SCPM enabled, the allowed featuremasks setting(via * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted. @@ -701,22 +714,13 @@ static int smu_get_driver_allowed_feature_mask(struct smu_context *smu) * such scenario. */ if (smu->adev->scpm_enabled) { - bitmap_fill(feature->allowed, SMU_FEATURE_MAX); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } - bitmap_zero(feature->allowed, SMU_FEATURE_MAX); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); - ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask, - SMU_FEATURE_MAX/32); - if (ret) - return ret; - - bitmap_or(feature->allowed, feature->allowed, - (unsigned long *)allowed_feature_mask, - feature->feature_num); - - return ret; + return smu_init_allowed_features(smu); } static int smu_set_funcs(struct amdgpu_device *adev) @@ -796,6 +800,13 @@ static int smu_set_funcs(struct amdgpu_device *adev) case IP_VERSION(14, 0, 3): smu_v14_0_2_set_ppt_funcs(smu); break; + case IP_VERSION(15, 0, 0): + smu_v15_0_0_set_ppt_funcs(smu); + break; + case IP_VERSION(15, 0, 8): + smu_v15_0_8_set_ppt_funcs(smu); + smu->od_enabled = true; + break; default: return -EINVAL; } @@ -816,14 +827,12 @@ static int smu_early_init(struct amdgpu_ip_block *ip_block) smu->adev = adev; smu->pm_enabled = !!amdgpu_dpm; smu->is_apu = false; - smu->smu_baco.state = SMU_BACO_STATE_NONE; + smu->smu_baco.state = SMU_BACO_STATE_EXIT; smu->smu_baco.platform_support = false; smu->smu_baco.maco_support = false; smu->user_dpm_profile.fan_mode = -1; smu->power_profile_mode = PP_SMC_POWER_PROFILE_UNKNOWN; - mutex_init(&smu->message_lock); - adev->powerplay.pp_handle = smu; adev->powerplay.pp_funcs = &swsmu_pm_funcs; @@ -1326,7 +1335,7 @@ static void smu_init_power_profile(struct smu_context *smu) if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_UNKNOWN) smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; - smu_power_profile_mode_get(smu, smu->power_profile_mode); + } void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id) @@ -1363,9 +1372,7 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) int i, ret; smu->pool_size = adev->pm.smu_prv_buffer_size; - smu->smu_feature.feature_num = SMU_FEATURE_MAX; - bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX); - bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX); + smu_feature_init(smu, SMU_FEATURE_NUM_DEFAULT); INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn); INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn); @@ -1654,10 +1661,9 @@ static void smu_wbrf_fini(struct smu_context *smu) static int smu_smc_hw_setup(struct smu_context *smu) { - struct smu_feature *feature = &smu->smu_feature; struct amdgpu_device *adev = smu->adev; uint8_t pcie_gen = 0, pcie_width = 0; - uint64_t features_supported; + struct smu_feature_bits features_supported; int ret = 0; switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { @@ -1817,9 +1823,8 @@ static int smu_smc_hw_setup(struct smu_context *smu) dev_err(adev->dev, "Failed to retrieve supported dpm features!\n"); return ret; } - bitmap_copy(feature->supported, - (unsigned long *)&features_supported, - feature->feature_num); + smu_feature_list_set_bits(smu, SMU_FEATURE_LIST_SUPPORTED, + features_supported.bits); if (!smu_is_dpm_running(smu)) dev_info(adev->dev, "dpm has been disabled\n"); @@ -1950,7 +1955,7 @@ static int smu_hw_init(struct amdgpu_ip_block *ip_block) if (!smu->pm_enabled) return 0; - ret = smu_get_driver_allowed_feature_mask(smu); + ret = smu_init_driver_allowed_feature_mask(smu); if (ret) return ret; @@ -2132,9 +2137,8 @@ static int smu_reset_mp1_state(struct smu_context *smu) int ret = 0; if ((!adev->in_runpm) && (!adev->in_suspend) && - (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == - IP_VERSION(13, 0, 10) && - !amdgpu_device_has_display_hardware(adev)) + (!amdgpu_in_reset(adev)) && !smu->is_apu && + amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(13, 0, 0)) ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD); return ret; @@ -2806,6 +2810,14 @@ const struct amdgpu_ip_block_version smu_v14_0_ip_block = { .funcs = &smu_ip_funcs, }; +const struct amdgpu_ip_block_version smu_v15_0_ip_block = { + .type = AMD_IP_BLOCK_TYPE_SMC, + .major = 15, + .minor = 0, + .rev = 0, + .funcs = &smu_ip_funcs, +}; + const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle) { struct smu_context *smu = (struct smu_context *)handle; @@ -2958,6 +2970,7 @@ int smu_get_power_limit(void *handle, case IP_VERSION(11, 0, 11): case IP_VERSION(11, 0, 12): case IP_VERSION(11, 0, 13): + case IP_VERSION(15, 0, 8): ret = smu_get_asic_power_limits(smu, &smu->current_power_limit, NULL, NULL, NULL); @@ -3014,19 +3027,6 @@ static int smu_set_power_limit(void *handle, uint32_t limit_type, uint32_t limit return 0; } -static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) -{ - int ret = 0; - - if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) - return -EOPNOTSUPP; - - if (smu->ppt_funcs->print_clk_levels) - ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf); - - return ret; -} - static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) { enum smu_clk_type clk_type; @@ -3062,6 +3062,8 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) clk_type = SMU_OD_SCLK; break; case OD_MCLK: clk_type = SMU_OD_MCLK; break; + case OD_FCLK: + clk_type = SMU_OD_FCLK; break; case OD_VDDC_CURVE: clk_type = SMU_OD_VDDC_CURVE; break; case OD_RANGE: @@ -3091,20 +3093,6 @@ static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type) return clk_type; } -static int smu_print_ppclk_levels(void *handle, - enum pp_clock_type type, - char *buf) -{ - struct smu_context *smu = handle; - enum smu_clk_type clk_type; - - clk_type = smu_convert_to_smuclk(type); - if (clk_type == SMU_CLK_COUNT) - return -EINVAL; - - return smu_print_smuclk_levels(smu, clk_type, buf); -} - static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset) { struct smu_context *smu = handle; @@ -3183,10 +3171,19 @@ static int smu_read_sensor(void *handle, *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100; *size = 4; break; - case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: - ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data); + case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK: { + struct smu_feature_bits feature_mask; + uint32_t features[2]; + + /* TBD: need to handle for > 64 bits */ + ret = smu_feature_get_enabled_mask(smu, &feature_mask); + if (!ret) { + smu_feature_bits_to_arr32(&feature_mask, features, 64); + *(uint64_t *)data = *(uint64_t *)features; + } *size = 8; break; + } case AMDGPU_PP_SENSOR_UVD_POWER: *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0; *size = 4; @@ -3686,6 +3683,9 @@ static int smu_get_dpm_clock_table(void *handle, static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) { struct smu_context *smu = handle; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_driver_table *driver_tables = smu_table->driver_tables; + struct smu_driver_table *gpu_metrics_table; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; @@ -3693,6 +3693,14 @@ static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table) if (!smu->ppt_funcs->get_gpu_metrics) return -EOPNOTSUPP; + gpu_metrics_table = &driver_tables[SMU_DRIVER_TABLE_GPU_METRICS]; + + /* If cached table is valid, return it */ + if (smu_driver_table_is_valid(gpu_metrics_table)) { + *table = gpu_metrics_table->cache.buffer; + return gpu_metrics_table->cache.size; + } + return smu->ppt_funcs->get_gpu_metrics(smu, table); } @@ -3880,8 +3888,9 @@ static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type { struct smu_context *smu = handle; struct smu_table_context *smu_table = &smu->smu_table; - struct smu_table *tables = smu_table->tables; - enum smu_table_id table_id; + struct smu_driver_table *driver_tables = smu_table->driver_tables; + enum smu_driver_table_id table_id; + struct smu_driver_table *temp_table; if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) return -EOPNOTSUPP; @@ -3891,17 +3900,18 @@ static ssize_t smu_sys_get_temp_metrics(void *handle, enum smu_temp_metric_type table_id = smu_metrics_get_temp_table_id(type); - if (table_id == SMU_TABLE_COUNT) + if (table_id == SMU_DRIVER_TABLE_COUNT) return -EINVAL; + temp_table = &driver_tables[table_id]; + /* If the request is to get size alone, return the cached table size */ - if (!table && tables[table_id].cache.size) - return tables[table_id].cache.size; + if (!table && temp_table->cache.size) + return temp_table->cache.size; - if (smu_table_cache_is_valid(&tables[table_id])) { - memcpy(table, tables[table_id].cache.buffer, - tables[table_id].cache.size); - return tables[table_id].cache.size; + if (smu_driver_table_is_valid(temp_table)) { + memcpy(table, temp_table->cache.buffer, temp_table->cache.size); + return temp_table->cache.size; } return smu->smu_temp.temp_funcs->get_temp_metrics(smu, type, table); @@ -3941,7 +3951,6 @@ static const struct amd_pm_funcs swsmu_pm_funcs = { .set_fan_speed_pwm = smu_set_fan_speed_pwm, .get_fan_speed_pwm = smu_get_fan_speed_pwm, .force_clock_level = smu_force_ppclk_levels, - .print_clock_levels = smu_print_ppclk_levels, .emit_clock_levels = smu_emit_ppclk_levels, .force_performance_level = smu_force_performance_level, .read_sensor = smu_read_sensor, @@ -4175,3 +4184,191 @@ int smu_reset_vcn(struct smu_context *smu, uint32_t inst_mask) return 0; } + +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->set) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->set(smu, id, val); +} + +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get) + return -EOPNOTSUPP; + + return pd_ctl->ops->get(smu, id, val); +} + +int smu_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->enable) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->enable(smu, enable); +} + +static int smu_phase_det_get_residency(struct smu_context *smu, uint32_t *res) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get_residency) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->get_residency(smu, res); +} + +#if defined(CONFIG_DEBUG_FS) + +static int smu_phase_det_debugfs_get_residency(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + uint32_t res; + int r; + + r = smu_phase_det_get_residency(smu, &res); + if (r) + return r; + *val = res; + + return 0; +} + +static int smu_phase_det_debugfs_status(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + + *val = pd_ctl->status; + + return 0; +} + +static int smu_phase_det_debugfs_enable(void *data, u64 val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct amdgpu_device *adev = smu->adev; + + if (amdgpu_in_reset(adev) || adev->in_suspend) + return -EPERM; + + return smu_phase_det_enable(smu, !!val); +} + +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") + +DEBUGFS_PHASE_DET_FOPS(LO_FREQ); +DEBUGFS_PHASE_DET_FOPS(HI_FREQ); +DEBUGFS_PHASE_DET_FOPS(THRESH); +DEBUGFS_PHASE_DET_FOPS(ALPHA); +DEBUGFS_PHASE_DET_FOPS(HYST); + +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); + +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); + +#define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ + debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) + +#define AMDGPU_SMU_PHASE_DET "smu_phase_detect" +#endif + +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + + struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + struct dentry *dir; + + pd_ctl = dpm_ctxt->pd_ctl; + + if (!smu || !pd_ctl) + return; + + dir = debugfs_create_dir(AMDGPU_SMU_PHASE_DET, + adev_to_drm(adev)->primary->debugfs_root); + + debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + + if (pd_ctl->ops->get_residency) + debugfs_create_file("residency", 0444, dir, smu, + &smu_phase_det_fops_res); + + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); + DEBUGFS_CREATE_PHASE_DET_ATTR(alpha, ALPHA); + DEBUGFS_CREATE_PHASE_DET_ATTR(hyst, HYST); + +#endif +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 8815fc70b63b0..6eed4d6cc1d4a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -41,6 +41,8 @@ #define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1) #define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2) +#define SMU_GPU_METRICS_CACHE_INTERVAL 5 + // Power Throttlers #define SMU_THROTTLER_PPT0_BIT 0 #define SMU_THROTTLER_PPT1_BIT 1 @@ -269,6 +271,18 @@ struct smu_table { struct smu_table_cache cache; }; +enum smu_driver_table_id { + SMU_DRIVER_TABLE_GPU_METRICS = 0, + SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS, + SMU_DRIVER_TABLE_COUNT, +}; + +struct smu_driver_table { + enum smu_driver_table_id id; + struct smu_table_cache cache; +}; + enum smu_perf_level_designation { PERF_LEVEL_ACTIVITY, PERF_LEVEL_POWER_CONTAINMENT, @@ -292,6 +306,37 @@ struct smu_clock_info { uint32_t max_bus_bandwidth; }; +#define SMU_MAX_DPM_LEVELS 16 + +struct smu_dpm_clk_level { + bool enabled; + uint32_t value; +}; + +#define SMU_DPM_TABLE_FINE_GRAINED BIT(0) + +struct smu_dpm_table { + enum smu_clk_type clk_type; + uint32_t count; + uint32_t flags; + struct smu_dpm_clk_level dpm_levels[SMU_MAX_DPM_LEVELS]; +}; + +#define SMU_DPM_TABLE_MIN(table) \ + ((table)->count > 0 ? (table)->dpm_levels[0].value : 0) + +#define SMU_DPM_TABLE_MAX(table) \ + ((table)->count > 0 ? (table)->dpm_levels[(table)->count - 1].value : 0) + +#define SMU_MAX_PCIE_LEVELS 3 + +struct smu_pcie_table { + uint8_t pcie_gen[SMU_MAX_PCIE_LEVELS]; + uint8_t pcie_lane[SMU_MAX_PCIE_LEVELS]; + uint16_t lclk_freq[SMU_MAX_PCIE_LEVELS]; + uint32_t lclk_levels; +}; + struct smu_bios_boot_up_values { uint32_t revision; uint32_t gfxclk; @@ -332,8 +377,6 @@ enum smu_table_id { SMU_TABLE_ECCINFO, SMU_TABLE_COMBO_PPTABLE, SMU_TABLE_WIFIBAND, - SMU_TABLE_GPUBOARD_TEMP_METRICS, - SMU_TABLE_BASEBOARD_TEMP_METRICS, SMU_TABLE_PMFW_SYSTEM_METRICS, SMU_TABLE_COUNT, }; @@ -346,6 +389,7 @@ struct smu_table_context { void *metrics_table; void *clocks_table; void *watermarks_table; + struct mutex metrics_lock; void *max_sustainable_clocks; struct smu_bios_boot_up_values boot_values; @@ -371,8 +415,7 @@ struct smu_table_context { void *boot_overdrive_table; void *user_overdrive_table; - uint32_t gpu_metrics_table_size; - void *gpu_metrics_table; + struct smu_driver_table driver_tables[SMU_DRIVER_TABLE_COUNT]; }; struct smu_context; @@ -396,6 +439,36 @@ struct smu_dpm_policy_ctxt { unsigned long policy_mask; }; +struct smu_phase_det_params { + uint32_t freq_hi; + uint32_t freq_lo; + uint32_t thresh; + uint32_t hyst; + uint32_t alpha; +}; + +struct smu_phase_det_ops { + int (*set)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t val); + int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t *val); + int (*enable)(struct smu_context *smu, bool enable); + int (*get_residency)(struct smu_context *smu, uint32_t *res); +}; + +enum phase_det_state { + SMU_PHASE_DET_OFF = 0, + SMU_PHASE_DET_ON = 1, + SMU_PHASE_DET_DISABLED = -1, +}; + +struct smu_phase_det_ctl { + struct smu_phase_det_params params; + struct smu_phase_det_ops *ops; + enum phase_det_state status; + uint32_t residency; +}; + struct smu_dpm_context { uint32_t dpm_context_size; void *dpm_context; @@ -407,6 +480,7 @@ struct smu_dpm_context { struct smu_power_state *dpm_current_power_state; struct mclock_latency_table *mclk_latency_table; struct smu_dpm_policy_ctxt *dpm_policies; + struct smu_phase_det_ctl *pd_ctl; }; struct smu_temp_context { @@ -429,11 +503,39 @@ struct smu_power_context { struct smu_power_gate power_gate; }; -#define SMU_FEATURE_MAX (64) +#define SMU_FEATURE_NUM_DEFAULT (64) +#define SMU_FEATURE_MAX (128) + +struct smu_feature_bits { + DECLARE_BITMAP(bits, SMU_FEATURE_MAX); +}; + +/* + * Helpers for initializing smu_feature_bits statically. + * Use SMU_FEATURE_BIT_INIT() which automatically handles array indexing: + * static const struct smu_feature_bits example = { + * .bits = { + * SMU_FEATURE_BIT_INIT(5), + * SMU_FEATURE_BIT_INIT(10), + * SMU_FEATURE_BIT_INIT(65), + * SMU_FEATURE_BIT_INIT(100) + * } + * }; + */ +#define SMU_FEATURE_BITS_ELEM(bit) ((bit) / BITS_PER_LONG) +#define SMU_FEATURE_BITS_POS(bit) ((bit) % BITS_PER_LONG) +#define SMU_FEATURE_BIT_INIT(bit) \ + [SMU_FEATURE_BITS_ELEM(bit)] = (1UL << SMU_FEATURE_BITS_POS(bit)) + +enum smu_feature_list { + SMU_FEATURE_LIST_SUPPORTED, + SMU_FEATURE_LIST_ALLOWED, + SMU_FEATURE_LIST_MAX, +}; + struct smu_feature { uint32_t feature_num; - DECLARE_BITMAP(supported, SMU_FEATURE_MAX); - DECLARE_BITMAP(allowed, SMU_FEATURE_MAX); + struct smu_feature_bits bits[SMU_FEATURE_LIST_MAX]; }; struct smu_clocks { @@ -466,7 +568,6 @@ enum smu_reset_mode { enum smu_baco_state { SMU_BACO_STATE_ENTER = 0, SMU_BACO_STATE_EXIT, - SMU_BACO_STATE_NONE, }; struct smu_baco_context { @@ -509,6 +610,86 @@ struct cmn2asic_mapping { int map_to; }; +#define SMU_MSG_MAX_ARGS 4 + +/* Message flags for smu_msg_args */ +#define SMU_MSG_FLAG_ASYNC BIT(0) /* Async send - skip post-poll */ +#define SMU_MSG_FLAG_LOCK_HELD BIT(1) /* Caller holds ctl->lock */ + +/* smu_msg_ctl flags */ +#define SMU_MSG_CTL_DEBUG_MAILBOX BIT(0) /* Debug mailbox supported */ + +struct smu_msg_ctl; +/** + * struct smu_msg_config - IP-level register configuration + * @msg_reg: Message register offset + * @resp_reg: Response register offset + * @arg_regs: Argument register offsets (up to SMU_MSG_MAX_ARGS) + * @num_arg_regs: Number of argument registers available + * @debug_msg_reg: Debug message register offset + * @debug_resp_reg: Debug response register offset + * @debug_param_reg: Debug parameter register offset + */ +struct smu_msg_config { + u32 msg_reg; + u32 resp_reg; + u32 arg_regs[SMU_MSG_MAX_ARGS]; + int num_arg_regs; + u32 debug_msg_reg; + u32 debug_resp_reg; + u32 debug_param_reg; +}; + +/** + * struct smu_msg_args - Per-call message arguments + * @msg: Common message type (enum smu_message_type) + * @args: Input arguments + * @num_args: Number of input arguments + * @out_args: Output arguments (filled after successful send) + * @num_out_args: Number of output arguments to read + * @flags: Message flags (SMU_MSG_FLAG_*) + * @timeout: Per-message timeout in us (0 = use default) + */ +struct smu_msg_args { + enum smu_message_type msg; + u32 args[SMU_MSG_MAX_ARGS]; + int num_args; + u32 out_args[SMU_MSG_MAX_ARGS]; + int num_out_args; + u32 flags; + u32 timeout; +}; + +/** + * struct smu_msg_ops - IP-level protocol operations + * @send_msg: send message protocol + * @wait_response: wait for response (for split send/wait cases) + * @decode_response: Convert response register value to errno + * @send_debug_msg: send debug message + */ +struct smu_msg_ops { + int (*send_msg)(struct smu_msg_ctl *ctl, struct smu_msg_args *args); + int (*wait_response)(struct smu_msg_ctl *ctl, u32 timeout_us); + int (*decode_response)(u32 resp); + int (*send_debug_msg)(struct smu_msg_ctl *ctl, u32 msg, u32 param); +}; + +/** + * struct smu_msg_ctl - Per-device message control block + * This is a standalone control block that encapsulates everything + * needed for SMU messaging. The ops->send_msg implements the complete + * protocol including all filtering and error handling. + */ +struct smu_msg_ctl { + struct smu_context *smu; + struct mutex lock; + struct smu_msg_config config; + const struct smu_msg_ops *ops; + const struct cmn2asic_msg_mapping *message_map; + u32 default_timeout; + u32 flags; +}; + struct stb_context { uint32_t stb_buf_size; bool enabled; @@ -545,13 +726,11 @@ struct smu_context { struct amdgpu_irq_src irq_source; const struct pptable_funcs *ppt_funcs; - const struct cmn2asic_msg_mapping *message_map; const struct cmn2asic_mapping *clock_map; const struct cmn2asic_mapping *feature_map; const struct cmn2asic_mapping *table_map; const struct cmn2asic_mapping *pwr_src_map; const struct cmn2asic_mapping *workload_map; - struct mutex message_lock; uint64_t pool_size; struct smu_table_context smu_table; @@ -635,20 +814,15 @@ struct smu_context { struct firmware pptable_firmware; - u32 param_reg; - u32 msg_reg; - u32 resp_reg; - - u32 debug_param_reg; - u32 debug_msg_reg; - u32 debug_resp_reg; - struct delayed_work swctf_delayed_work; /* data structures for wbrf feature support */ bool wbrf_supported; struct notifier_block wbrf_notifier; struct delayed_work wbrf_delayed_work; + + /* SMU message control block */ + struct smu_msg_ctl msg_ctl; }; struct i2c_adapter; @@ -687,11 +861,10 @@ struct pptable_funcs { int (*run_btc)(struct smu_context *smu); /** - * @get_allowed_feature_mask: Get allowed feature mask. - * &feature_mask: Array to store feature mask. - * &num: Elements in &feature_mask. + * @init_allowed_features: Initialize allowed features bitmap. + * Directly sets allowed features using smu_feature wrapper functions. */ - int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); + int (*init_allowed_features)(struct smu_context *smu); /** * @get_current_power_state: Get the current power state. @@ -714,15 +887,6 @@ struct pptable_funcs { */ int (*populate_umd_state_clk)(struct smu_context *smu); - /** - * @print_clk_levels: Print DPM clock levels for a clock domain - * to buffer. Star current level. - * - * Used for sysfs interfaces. - * Return: Number of characters written to the buffer - */ - int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); - /** * @emit_clk_levels: Print DPM clock levels for a clock domain * to buffer using sysfs_emit_at. Star current level. @@ -1080,24 +1244,6 @@ struct pptable_funcs { */ int (*system_features_control)(struct smu_context *smu, bool en); - /** - * @send_smc_msg_with_param: Send a message with a parameter to the SMU. - * &msg: Type of message. - * ¶m: Message parameter. - * &read_arg: SMU response (optional). - */ - int (*send_smc_msg_with_param)(struct smu_context *smu, - enum smu_message_type msg, uint32_t param, uint32_t *read_arg); - - /** - * @send_smc_msg: Send a message to the SMU. - * &msg: Type of message. - * &read_arg: SMU response (optional). - */ - int (*send_smc_msg)(struct smu_context *smu, - enum smu_message_type msg, - uint32_t *read_arg); - /** * @init_display_count: Notify the SMU of the number of display * components in current display configuration. @@ -1115,7 +1261,8 @@ struct pptable_funcs { * on the SMU. * &feature_mask: Enabled feature mask. */ - int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask); + int (*get_enabled_mask)(struct smu_context *smu, + struct smu_feature_bits *feature_mask); /** * @feature_is_enabled: Test if a feature is enabled. @@ -1590,6 +1737,7 @@ typedef enum { METRICS_THROTTLER_RESIDENCY_THM_CORE, METRICS_THROTTLER_RESIDENCY_THM_GFX, METRICS_THROTTLER_RESIDENCY_THM_SOC, + METRICS_AVERAGE_NPUCLK, } MetricsMember_t; enum smu_cmn2asic_mapping_type { @@ -1680,19 +1828,19 @@ typedef struct { struct smu_dpm_policy *smu_get_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type); -static inline enum smu_table_id +static inline enum smu_driver_table_id smu_metrics_get_temp_table_id(enum smu_temp_metric_type type) { switch (type) { case SMU_TEMP_METRIC_BASEBOARD: - return SMU_TABLE_BASEBOARD_TEMP_METRICS; + return SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS; case SMU_TEMP_METRIC_GPUBOARD: - return SMU_TABLE_GPUBOARD_TEMP_METRICS; + return SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS; default: - return SMU_TABLE_COUNT; + return SMU_DRIVER_TABLE_COUNT; } - return SMU_TABLE_COUNT; + return SMU_DRIVER_TABLE_COUNT; } static inline void smu_table_cache_update_time(struct smu_table *table, @@ -1745,6 +1893,82 @@ static inline void smu_table_cache_fini(struct smu_context *smu, } } +static inline int smu_driver_table_init(struct smu_context *smu, + enum smu_driver_table_id table_id, + size_t size, uint32_t cache_interval) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_driver_table *driver_tables = smu_table->driver_tables; + + if (table_id >= SMU_DRIVER_TABLE_COUNT) + return -EINVAL; + + driver_tables[table_id].id = table_id; + driver_tables[table_id].cache.buffer = kzalloc(size, GFP_KERNEL); + if (!driver_tables[table_id].cache.buffer) + return -ENOMEM; + + driver_tables[table_id].cache.last_cache_time = 0; + driver_tables[table_id].cache.interval = cache_interval; + driver_tables[table_id].cache.size = size; + + return 0; +} + +static inline void smu_driver_table_fini(struct smu_context *smu, + enum smu_driver_table_id table_id) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_driver_table *driver_tables = smu_table->driver_tables; + + if (table_id >= SMU_DRIVER_TABLE_COUNT) + return; + + if (driver_tables[table_id].cache.buffer) { + kfree(driver_tables[table_id].cache.buffer); + driver_tables[table_id].cache.buffer = NULL; + driver_tables[table_id].cache.last_cache_time = 0; + driver_tables[table_id].cache.interval = 0; + } +} + +static inline bool smu_driver_table_is_valid(struct smu_driver_table *table) +{ + if (!table->cache.buffer || !table->cache.last_cache_time || + !table->cache.interval || !table->cache.size || + time_after(jiffies, + table->cache.last_cache_time + + msecs_to_jiffies(table->cache.interval))) + return false; + + return true; +} + +static inline void *smu_driver_table_ptr(struct smu_context *smu, + enum smu_driver_table_id table_id) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_driver_table *driver_tables = smu_table->driver_tables; + + if (table_id >= SMU_DRIVER_TABLE_COUNT) + return NULL; + + return driver_tables[table_id].cache.buffer; +} + +static inline void +smu_driver_table_update_cache_time(struct smu_context *smu, + enum smu_driver_table_id table_id) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_driver_table *driver_tables = smu_table->driver_tables; + + if (table_id >= SMU_DRIVER_TABLE_COUNT) + return; + + driver_tables[table_id].cache.last_cache_time = jiffies; +} + #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4) int smu_get_power_limit(void *handle, uint32_t *limit, @@ -1803,10 +2027,179 @@ ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); const struct ras_smu_drv *smu_get_ras_smu_driver(void *handle); +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val); +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val); +int smu_phase_det_enable(struct smu_context *smu, bool enable); +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); + int amdgpu_smu_ras_send_msg(struct amdgpu_device *adev, enum smu_message_type msg, uint32_t param, uint32_t *readarg); +int amdgpu_smu_ras_feature_is_enabled(struct amdgpu_device *adev, + enum smu_feature_mask mask); #endif void smu_feature_cap_set(struct smu_context *smu, enum smu_feature_cap_id fea_id); bool smu_feature_cap_test(struct smu_context *smu, enum smu_feature_cap_id fea_id); + +static inline bool smu_feature_bits_is_set(const struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit >= SMU_FEATURE_MAX) + return false; + + return test_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_set_bit(struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit < SMU_FEATURE_MAX) + __set_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_clear_bit(struct smu_feature_bits *bits, + unsigned int bit) +{ + if (bit < SMU_FEATURE_MAX) + __clear_bit(bit, bits->bits); +} + +static inline void smu_feature_bits_clearall(struct smu_feature_bits *bits) +{ + bitmap_zero(bits->bits, SMU_FEATURE_MAX); +} + +static inline void smu_feature_bits_fill(struct smu_feature_bits *bits) +{ + bitmap_fill(bits->bits, SMU_FEATURE_MAX); +} + +static inline bool +smu_feature_bits_test_mask(const struct smu_feature_bits *bits, + const unsigned long *mask) +{ + return bitmap_intersects(bits->bits, mask, SMU_FEATURE_MAX); +} + +static inline void smu_feature_bits_from_arr32(struct smu_feature_bits *bits, + const uint32_t *arr, + unsigned int nbits) +{ + bitmap_from_arr32(bits->bits, arr, nbits); +} + +static inline void +smu_feature_bits_to_arr32(const struct smu_feature_bits *bits, uint32_t *arr, + unsigned int nbits) +{ + bitmap_to_arr32(arr, bits->bits, nbits); +} + +static inline bool smu_feature_bits_empty(const struct smu_feature_bits *bits, + unsigned int nbits) +{ + return bitmap_empty(bits->bits, nbits); +} + +static inline bool smu_feature_bits_full(const struct smu_feature_bits *bits, + unsigned int nbits) +{ + return bitmap_full(bits->bits, nbits); +} + +static inline void smu_feature_bits_copy(struct smu_feature_bits *dst, + const unsigned long *src, + unsigned int nbits) +{ + bitmap_copy(dst->bits, src, nbits); +} + +static inline struct smu_feature_bits * +__smu_feature_get_list(struct smu_context *smu, enum smu_feature_list list) +{ + if (unlikely(list >= SMU_FEATURE_LIST_MAX)) { + dev_warn(smu->adev->dev, "Invalid feature list: %d\n", list); + return &smu->smu_feature.bits[SMU_FEATURE_LIST_SUPPORTED]; + } + + return &smu->smu_feature.bits[list]; +} + +static inline bool smu_feature_list_is_set(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return false; + + return smu_feature_bits_is_set(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_set_bit(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return; + + smu_feature_bits_set_bit(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_clear_bit(struct smu_context *smu, + enum smu_feature_list list, + unsigned int bit) +{ + if (bit >= smu->smu_feature.feature_num) + return; + + smu_feature_bits_clear_bit(__smu_feature_get_list(smu, list), bit); +} + +static inline void smu_feature_list_set_all(struct smu_context *smu, + enum smu_feature_list list) +{ + smu_feature_bits_fill(__smu_feature_get_list(smu, list)); +} + +static inline void smu_feature_list_clear_all(struct smu_context *smu, + enum smu_feature_list list) +{ + smu_feature_bits_clearall(__smu_feature_get_list(smu, list)); +} + +static inline bool smu_feature_list_is_empty(struct smu_context *smu, + enum smu_feature_list list) +{ + return smu_feature_bits_empty(__smu_feature_get_list(smu, list), + smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_set_bits(struct smu_context *smu, + enum smu_feature_list dst_list, + const unsigned long *src) +{ + smu_feature_bits_copy(__smu_feature_get_list(smu, dst_list), src, + smu->smu_feature.feature_num); +} + +static inline void smu_feature_list_to_arr32(struct smu_context *smu, + enum smu_feature_list list, + uint32_t *arr) +{ + smu_feature_bits_to_arr32(__smu_feature_get_list(smu, list), arr, + smu->smu_feature.feature_num); +} + +static inline void smu_feature_init(struct smu_context *smu, int feature_num) +{ + if (!feature_num || smu->smu_feature.feature_num != 0) + return; + + smu->smu_feature.feature_num = feature_num; + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_SUPPORTED); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); +} + #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h new file mode 100644 index 0000000000000..47ddf533b08f3 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu15_driver_if_v15_0_0.h @@ -0,0 +1,231 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef SMU15_DRIVER_IF_V15_0_0_H +#define SMU15_DRIVER_IF_V15_0_0_H + +typedef struct { + int32_t value; + uint32_t numFractionalBits; +} FloatInIntFormat_t; + +typedef enum { + DSPCLK_DCFCLK = 0, + DSPCLK_DISPCLK, + DSPCLK_PIXCLK, + DSPCLK_PHYCLK, + DSPCLK_COUNT, +} DSPCLK_e; + +typedef struct { + uint16_t Freq; // in MHz + uint16_t Vid; // min voltage in SVI3 VID +} DisplayClockTable_t; + +typedef struct { + uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) + uint16_t MinMclk; + uint16_t MaxMclk; + + uint8_t WmSetting; + uint8_t WmType; // Used for normal pstate change or memory retraining + uint8_t Padding[2]; +} WatermarkRowGeneric_t; + +#define NUM_WM_RANGES 4 +#define WM_PSTATE_CHG 0 +#define WM_RETRAINING 1 + +typedef enum { + WM_SOCCLK = 0, + WM_DCFCLK, + WM_COUNT, +} WM_CLOCK_e; + +typedef struct { + // Watermarks + WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES]; + + uint32_t MmHubPadding[7]; // SMU internal use +} Watermarks_t; + +typedef enum { + CUSTOM_DPM_SETTING_GFXCLK, + CUSTOM_DPM_SETTING_CCLK, + CUSTOM_DPM_SETTING_FCLK_CCX, + CUSTOM_DPM_SETTING_FCLK_GFX, + CUSTOM_DPM_SETTING_FCLK_STALLS, + CUSTOM_DPM_SETTING_LCLK, + CUSTOM_DPM_SETTING_COUNT, +} CUSTOM_DPM_SETTING_e; + +typedef struct { + uint8_t ActiveHystLimit; + uint8_t IdleHystLimit; + uint8_t FPS; + uint8_t MinActiveFreqType; + FloatInIntFormat_t MinActiveFreq; + FloatInIntFormat_t PD_Data_limit; + FloatInIntFormat_t PD_Data_time_constant; + FloatInIntFormat_t PD_Data_error_coeff; + FloatInIntFormat_t PD_Data_error_rate_coeff; +} DpmActivityMonitorCoeffExt_t; + +typedef struct { + DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT]; +} CustomDpmSettings_t; + +#define NUM_DCFCLK_DPM_LEVELS 8 +#define NUM_DISPCLK_DPM_LEVELS 8 +#define NUM_DPPCLK_DPM_LEVELS 8 +#define NUM_SOCCLK_DPM_LEVELS 8 +#define NUM_VCN_DPM_LEVELS 8 +#define NUM_SOC_VOLTAGE_LEVELS 8 +#define NUM_VPE_DPM_LEVELS 8 +#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_MEM_PSTATE_LEVELS 4 + + +typedef struct { + uint32_t UClk; + uint32_t MemClk; + uint32_t Voltage; + uint8_t WckRatio; + uint8_t Spare[3]; +} MemPstateTable_t; + +//Freq in MHz +//Voltage in milli volts with 2 fractional bits +typedef struct { + uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS]; + uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS]; + uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS]; + uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS]; + uint32_t VClocks[NUM_VCN_DPM_LEVELS]; + uint32_t DClocks[NUM_VCN_DPM_LEVELS]; + uint32_t VPEClocks[NUM_VPE_DPM_LEVELS]; + uint32_t FclkClocks_Freq[NUM_FCLK_DPM_LEVELS]; + uint32_t FclkClocks_Voltage[NUM_FCLK_DPM_LEVELS]; + uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS]; + MemPstateTable_t MemPstateTable[NUM_MEM_PSTATE_LEVELS]; + + uint8_t NumDcfClkLevelsEnabled; + uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk + uint8_t NumSocClkLevelsEnabled; + uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk + + uint8_t VpeClkLevelsEnabled; + uint8_t NumMemPstatesEnabled; + uint8_t NumFclkLevelsEnabled; + uint8_t spare; + + uint32_t MinGfxClk; + uint32_t MaxGfxClk; +} DpmClocks_t; + +typedef struct { + uint16_t CoreFrequency[16]; //Target core frequency [MHz] + uint16_t CorePower[16]; //CAC calculated core power [mW] + uint16_t CoreTemperature[16]; //TSEN measured core temperature [centi-C] + uint16_t GfxTemperature; //TSEN measured GFX temperature [centi-C] + uint16_t SocTemperature; //TSEN measured SOC temperature [centi-C] + uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW] + uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW] + uint16_t InfrastructureCpuMaxFreq; //CCLK frequency limit enforced on classic cores [MHz] + uint16_t InfrastructureGfxMaxFreq; //GFXCLK frequency limit enforced on GFX [MHz] + uint16_t SkinTemp; //Maximum skin temperature reported by APU and HS2 chassis sensors [centi-C] + uint16_t GfxclkFrequency; //Time filtered target GFXCLK frequency [MHz] + uint16_t FclkFrequency; //Time filtered target FCLK frequency [MHz] + uint16_t GfxActivity; //Time filtered GFX busy % [0-100] + uint16_t SocclkFrequency; //Time filtered target SOCCLK frequency [MHz] + uint16_t VclkFrequency; //Time filtered target VCLK frequency [MHz] + uint16_t VcnActivity; //Time filtered VCN busy % [0-100] + uint16_t VpeclkFrequency; //Time filtered target VPECLK frequency [MHz] + uint16_t NpuclkFrequency; //Time filtered target NPUCLK frequency [MHz] + uint16_t NpuBusy[8]; //Time filtered NPU per-column busy % [0-100] + uint16_t DRAMReads; //Time filtered DRAM read bandwidth [MB/sec] + uint16_t DRAMWrites; //Time filtered DRAM write bandwidth [MB/sec] + uint16_t CoreC0Residency[16]; //Time filtered per-core C0 residency % [0-100] + uint16_t NpuPower; //Time filtered NPU power [mW] + uint32_t ApuPower; //Time filtered APU power [mW] + uint32_t GfxPower; //Time filtered GFX power [mW] + uint32_t dGpuPower; //Time filtered dGPU power [mW] + uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW] + uint32_t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW] + uint32_t FilterAlphaValue; //Metrics table alpha filter time constant [us] + uint32_t MetricsCounter; //Counter that is incremented on every metrics table update [PM_TIMER cycles] + uint16_t MemclkFrequency; //Time filtered target MEMCLK frequency [MHz] + uint16_t AieclkFrequency; //Time filtered target AIECLK frequency [MHz] + uint16_t NpuReads; //Time filtered NPU read bandwidth [MB/sec] + uint16_t NpuWrites; //Time filtered NPU write bandwidth [MB/sec] + uint32_t ThrottleResidency_PROCHOT; //Counter that is incremented on every metrics table update when PROCHOT was engaged [PM_TIMER cycles] + uint32_t ThrottleResidency_SPL; //Counter that is incremented on every metrics table update when SPL was engaged [PM_TIMER cycles] + uint32_t ThrottleResidency_FPPT; //Counter that is incremented on every metrics table update when fast PPT was engaged [PM_TIMER cycles] + uint32_t ThrottleResidency_SPPT; //Counter that is incremented on every metrics table update when slow PPT was engaged [PM_TIMER cycles] + uint32_t ThrottleResidency_THM_VDD; //Counter that is incremented on every metrics table update when VDD thermal throttling was engaged [PM_TIMER cycles] + uint32_t ThrottleResidency_THM_SOC; //Counter that is incremented on every metrics table update when SOC thermal throttling was engaged [PM_TIMER cycles] + uint16_t Psys; //Time filtered Psys power [mW] + uint16_t spare1; + uint32_t spare[6]; +} SmuMetrics_t; + +//ISP tile definitions +typedef enum { + TILE_XTILE = 0, //ONO0 + TILE_MTILE, //ONO1 + TILE_PDP, //ONO2 + TILE_CSTAT, //ONO2 + TILE_LME, //ONO3 + TILE_BYRP, //ONO4 + TILE_GRBP, //ONO4 + TILE_MCFP, //ONO4 + TILE_YUVP, //ONO4 + TILE_MCSC, //ONO4 + TILE_GDC, //ONO5 + TILE_MAX +} TILE_NUM_e; + +// Tile Selection (Based on arguments) +#define ISP_TILE_SEL(tile) (1<smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -273,11 +272,12 @@ static int arcturus_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) { + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) { kfree(smu_table->metrics_table); - return -ENOMEM; + return ret; } return 0; @@ -346,14 +346,9 @@ static int arcturus_init_smc_tables(struct smu_context *smu) } static int -arcturus_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +arcturus_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -362,79 +357,75 @@ static int arcturus_set_default_dpm_table(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; PPTable_t *driver_ppt = smu->smu_table.driver_pptable; - struct smu_11_0_dpm_table *dpm_table = NULL; + struct smu_dpm_table *dpm_table = NULL; int ret = 0; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_SOCCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_GFXCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* memclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_UCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* fclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_FCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* XGMI PLPD is supported by 54.23.0 and onwards */ @@ -572,23 +563,20 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_11_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_11_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; - pstate_table->gfxclk_pstate.min = gfx_table->min; - pstate_table->gfxclk_pstate.peak = gfx_table->max; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL && mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL && @@ -611,29 +599,6 @@ static int arcturus_populate_umd_state_clk(struct smu_context *smu) return 0; } -static void arcturus_get_clk_table(struct smu_context *smu, - struct pp_clock_levels_with_latency *clocks, - struct smu_11_0_dpm_table *dpm_table) -{ - uint32_t i; - - clocks->num_levels = min_t(uint32_t, - dpm_table->count, - (uint32_t)PP_MAX_CLOCK_LEVELS); - - for (i = 0; i < clocks->num_levels; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = 0; - } -} - -static int arcturus_freqs_in_same_level(int32_t frequency1, - int32_t frequency2) -{ - return (abs(frequency1 - frequency2) <= EPSILON); -} - static int arcturus_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) @@ -800,15 +765,12 @@ static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu, static int arcturus_emit_clk_levels(struct smu_context *smu, enum smu_clk_type type, char *buf, int *offset) { - int ret = 0; - struct pp_clock_levels_with_latency clocks; - struct smu_11_0_dpm_table *single_dpm_table; - struct smu_dpm_context *smu_dpm = &smu->smu_dpm; - struct smu_11_0_dpm_context *dpm_context = NULL; + struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_dpm_table *single_dpm_table; + struct smu_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - uint32_t i, cur_value = 0; - bool freq_match; - unsigned int clock_mhz; + uint32_t cur_value = 0; + int ret = 0; static const char attempt_string[] = "Attempt to get current"; if (amdgpu_ras_intr_triggered()) { @@ -816,8 +778,6 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, return -EBUSY; } - dpm_context = smu_dpm->dpm_context; - switch (type) { case SMU_SCLK: ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value); @@ -825,10 +785,11 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string); return ret; } - single_dpm_table = &(dpm_context->dpm_tables.gfx_table); - arcturus_get_clk_table(smu, &clocks, single_dpm_table); - + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + if (ret < 0) + return ret; break; case SMU_MCLK: @@ -837,10 +798,11 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string); return ret; } - single_dpm_table = &(dpm_context->dpm_tables.uclk_table); - arcturus_get_clk_table(smu, &clocks, single_dpm_table); - + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + if (ret < 0) + return ret; break; case SMU_SOCCLK: @@ -849,10 +811,11 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string); return ret; } - single_dpm_table = &(dpm_context->dpm_tables.soc_table); - arcturus_get_clk_table(smu, &clocks, single_dpm_table); - + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + if (ret < 0) + return ret; break; case SMU_FCLK: @@ -861,10 +824,11 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string); return ret; } - single_dpm_table = &(dpm_context->dpm_tables.fclk_table); - arcturus_get_clk_table(smu, &clocks, single_dpm_table); - + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + if (ret < 0) + return ret; break; case SMU_VCLK: @@ -873,10 +837,11 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string); return ret; } - single_dpm_table = &(dpm_context->dpm_tables.vclk_table); - arcturus_get_clk_table(smu, &clocks, single_dpm_table); - + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + if (ret < 0) + return ret; break; case SMU_DCLK: @@ -885,56 +850,27 @@ static int arcturus_emit_clk_levels(struct smu_context *smu, dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string); return ret; } - single_dpm_table = &(dpm_context->dpm_tables.dclk_table); - arcturus_get_clk_table(smu, &clocks, single_dpm_table); - + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + if (ret < 0) + return ret; break; case SMU_PCIE: gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); - break; - - default: - return -EINVAL; - } - - switch (type) { - case SMU_SCLK: - case SMU_MCLK: - case SMU_SOCCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_DCLK: - /* - * For DPM disabled case, there will be only one clock level. - * And it's safe to assume that is always the current clock. - */ - for (i = 0; i < clocks.num_levels; i++) { - clock_mhz = clocks.data[i].clocks_in_khz / 1000; - freq_match = arcturus_freqs_in_same_level(clock_mhz, cur_value); - freq_match |= (clocks.num_levels == 1); - - *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", - i, clock_mhz, - freq_match ? "*" : ""); - } - break; - - case SMU_PCIE: - *offset += sysfs_emit_at(buf, *offset, "0: %s %s %dMhz *\n", - (gen_speed == 0) ? "2.5GT/s," : - (gen_speed == 1) ? "5.0GT/s," : - (gen_speed == 2) ? "8.0GT/s," : - (gen_speed == 3) ? "16.0GT/s," : "", - (lane_width == 1) ? "x1" : - (lane_width == 2) ? "x2" : - (lane_width == 3) ? "x4" : - (lane_width == 4) ? "x8" : - (lane_width == 5) ? "x12" : - (lane_width == 6) ? "x16" : "", - smu->smu_table.boot_values.lclk / 100); + pcie_table = &(dpm_context->dpm_tables.pcie_table); + /* Populate with current state - arcturus only has boot level lclk */ + pcie_table->lclk_levels = 1; + pcie_table->pcie_gen[0] = gen_speed; + pcie_table->pcie_lane[0] = lane_width; + pcie_table->lclk_freq[0] = + smu->smu_table.boot_values.lclk / 100; + ret = smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed, + lane_width, buf, offset); + if (ret < 0) + return ret; break; default: @@ -1003,7 +939,7 @@ static int arcturus_force_clk_levels(struct smu_context *smu, enum smu_clk_type type, uint32_t mask) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_dpm_table *single_dpm_table = NULL; + struct smu_dpm_table *single_dpm_table = NULL; uint32_t soft_min_level, soft_max_level; int ret = 0; @@ -1591,13 +1527,14 @@ static int arcturus_set_performance_level(struct smu_context *smu, static bool arcturus_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + arcturus_dpm_features.bits); } static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, @@ -1874,9 +1811,9 @@ static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu) static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -1930,12 +1867,14 @@ static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } static const struct pptable_funcs arcturus_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = arcturus_get_allowed_feature_mask, + .init_allowed_features = arcturus_init_allowed_features, /* btc */ .run_btc = arcturus_run_btc, /* dpm/clk tables */ @@ -1973,8 +1912,6 @@ static const struct pptable_funcs arcturus_ppt_funcs = { .set_tool_table_location = smu_v11_0_set_tool_table_location, .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, .system_features_control = smu_v11_0_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .init_display_count = NULL, .set_allowed_mask = smu_v11_0_set_allowed_mask, .get_enabled_mask = smu_cmn_get_enabled_mask, @@ -2017,11 +1954,10 @@ static const struct pptable_funcs arcturus_ppt_funcs = { void arcturus_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &arcturus_ppt_funcs; - smu->message_map = arcturus_message_map; smu->clock_map = arcturus_clk_map; smu->feature_map = arcturus_feature_mask_map; smu->table_map = arcturus_table_map; smu->pwr_src_map = arcturus_pwr_src_map; smu->workload_map = arcturus_workload_map; - smu_v11_0_set_smu_mailbox_registers(smu); + smu_v11_0_init_msg_ctl(smu, arcturus_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c index 55401e6b2b0be..87953a4d0a433 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c @@ -60,11 +60,13 @@ static struct gfx_user_settings { static uint32_t cyan_skillfish_sclk_default; -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOC_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits cyan_skillfish_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOC_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping cyan_skillfish_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), @@ -88,6 +90,7 @@ static int cyan_skillfish_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), @@ -98,9 +101,10 @@ static int cyan_skillfish_tables_init(struct smu_context *smu) if (!smu_table->metrics_table) goto err0_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v2_2), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->metrics_time = 0; @@ -108,7 +112,6 @@ static int cyan_skillfish_tables_init(struct smu_context *smu) return 0; err1_out: - smu_table->gpu_metrics_table_size = 0; kfree(smu_table->metrics_table); err0_out: return -ENOMEM; @@ -287,17 +290,14 @@ static int cyan_skillfish_get_current_clk_freq(struct smu_context *smu, return cyan_skillfish_get_smu_metrics_data(smu, member_type, value); } -static int cyan_skillfish_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, - char *buf) +static int cyan_skillfish_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { - int ret = 0, size = 0, start_offset = 0; + int ret = 0, size = *offset, start_offset = *offset; uint32_t cur_value = 0; int i; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: ret = cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK, &cur_value); @@ -354,14 +354,16 @@ static int cyan_skillfish_print_clk_levels(struct smu_context *smu, return ret; } - return size - start_offset; + *offset += size - start_offset; + + return 0; } static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; /* we need to re-init after suspend so return false */ if (adev->in_suspend) @@ -378,15 +380,16 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu) cyan_skillfish_get_smu_metrics_data(smu, METRICS_CURR_GFXCLK, &cyan_skillfish_sclk_default); - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + cyan_skillfish_dpm_features.bits); } static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_2 *gpu_metrics = - (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_2 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int i, ret = 0; @@ -433,6 +436,8 @@ static ssize_t cyan_skillfish_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_2); } @@ -563,12 +568,13 @@ static int cyan_skillfish_get_dpm_ultimate_freq(struct smu_context *smu, return 0; } -static int cyan_skillfish_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) +static int +cyan_skillfish_get_enabled_mask(struct smu_context *smu, + struct smu_feature_bits *feature_mask) { if (!feature_mask) return -EINVAL; - memset(feature_mask, 0xff, sizeof(*feature_mask)); + smu_feature_bits_fill(feature_mask); return 0; } @@ -582,7 +588,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs = { .init_smc_tables = cyan_skillfish_init_smc_tables, .fini_smc_tables = smu_v11_0_fini_smc_tables, .read_sensor = cyan_skillfish_read_sensor, - .print_clk_levels = cyan_skillfish_print_clk_levels, + .emit_clk_levels = cyan_skillfish_emit_clk_levels, .get_enabled_mask = cyan_skillfish_get_enabled_mask, .is_dpm_running = cyan_skillfish_is_dpm_running, .get_gpu_metrics = cyan_skillfish_get_gpu_metrics, @@ -590,8 +596,6 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs = { .get_dpm_ultimate_freq = cyan_skillfish_get_dpm_ultimate_freq, .register_irq_handler = smu_v11_0_register_irq_handler, .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .set_driver_table_location = smu_v11_0_set_driver_table_location, .interrupt_work = smu_v11_0_interrupt_work, }; @@ -599,8 +603,7 @@ static const struct pptable_funcs cyan_skillfish_ppt_funcs = { void cyan_skillfish_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &cyan_skillfish_ppt_funcs; - smu->message_map = cyan_skillfish_message_map; smu->table_map = cyan_skillfish_table_map; smu->is_apu = true; - smu_v11_0_set_smu_mailbox_registers(smu); + smu_v11_0_init_msg_ctl(smu, cyan_skillfish_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index c4966dcc68756..737bfdfb814c5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -58,16 +58,18 @@ #undef pr_info #undef pr_debug -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)) +static const struct smu_feature_bits navi10_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFX_PACE_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT) + } +}; #define SMU_11_0_GFX_BUSY_THRESHOLD 15 @@ -275,89 +277,83 @@ static bool is_asic_secure(struct smu_context *smu) } static int -navi10_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +navi10_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) - | FEATURE_MASK(FEATURE_PPT_BIT) - | FEATURE_MASK(FEATURE_TDC_BIT) - | FEATURE_MASK(FEATURE_GFX_EDC_BIT) - | FEATURE_MASK(FEATURE_APCC_PLUS_BIT) - | FEATURE_MASK(FEATURE_VR0HOT_BIT) - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) - | FEATURE_MASK(FEATURE_THERMAL_BIT) - | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) - | FEATURE_MASK(FEATURE_DS_LCLK_BIT) - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) - | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT) - | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_EDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_PLUS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_LED_DISPLAY_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TEMP_DEPENDENT_VMIN_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VCN_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_JPEG_PG_BIT); if (smu->dc_controlled_by_gpio) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); - /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ if (!(is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) && - (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); + } - /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ if (is_asic_secure(smu) && (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) - *(uint64_t *)feature_mask &= - ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); return 0; } @@ -495,8 +491,8 @@ static int navi10_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; - struct smu_table *dummy_read_1_table = - &smu_table->dummy_read_1_table; + struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -526,9 +522,10 @@ static int navi10_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); @@ -545,7 +542,7 @@ static int navi10_tables_init(struct smu_context *smu) err3_out: kfree(smu_table->watermarks_table); err2_out: - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); err1_out: kfree(smu_table->metrics_table); err0_out: @@ -967,169 +964,160 @@ static int navi10_set_default_dpm_table(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; PPTable_t *driver_ppt = smu->smu_table.driver_pptable; - struct smu_11_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; int ret = 0; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_SOCCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_GFXCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* uclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_UCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* vclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = SMU_VCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_VCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = SMU_DCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_DCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dcefclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dcef_table; + dpm_table->clk_type = SMU_DCEFCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_DCEFCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* pixelclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.pixel_table; + dpm_table->clk_type = SMU_PIXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_PIXCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* displayclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.display_table; + dpm_table->clk_type = SMU_DISPCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_DISPCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* phyclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.phy_table; + dpm_table->clk_type = SMU_PHYCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_PHYCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete; + if (!driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } return 0; @@ -1261,104 +1249,48 @@ static int navi10_emit_clk_levels(struct smu_context *smu, { uint16_t *curve_settings; int ret = 0; - uint32_t cur_value = 0, value = 0; - uint32_t freq_values[3] = {0}; - uint32_t i, levels, mark_index = 0, count = 0; + uint32_t cur_value = 0; + uint32_t i; struct smu_table_context *table_context = &smu->smu_table; uint32_t gen_speed, lane_width; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; - PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; struct smu_11_0_overdrive_table *od_settings = smu->od_settings; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_pcie_table *pcie_table; uint32_t min_value, max_value; switch (clk_type) { case SMU_GFXCLK: case SMU_SCLK: + single_dpm_table = &(dpm_context->dpm_tables.gfx_table); + break; + /* FCLK and SOC CLK mapped to SOCCLK in clock map table */ case SMU_SOCCLK: + case SMU_FCLK: + single_dpm_table = &(dpm_context->dpm_tables.soc_table); + break; case SMU_MCLK: case SMU_UCLK: - case SMU_FCLK: + single_dpm_table = &(dpm_context->dpm_tables.uclk_table); + break; case SMU_VCLK: + single_dpm_table = &(dpm_context->dpm_tables.vclk_table); + break; case SMU_DCLK: + single_dpm_table = &(dpm_context->dpm_tables.dclk_table); + break; case SMU_DCEFCLK: - ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); - if (ret) - return ret; - - ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); - if (ret) - return ret; - - ret = navi10_is_support_fine_grained_dpm(smu, clk_type); - if (ret < 0) - return ret; - - if (!ret) { - for (i = 0; i < count; i++) { - ret = smu_v11_0_get_dpm_freq_by_index(smu, - clk_type, i, &value); - if (ret) - return ret; - - *offset += sysfs_emit_at(buf, *offset, - "%d: %uMhz %s\n", - i, value, - cur_value == value ? "*" : ""); - } - } else { - ret = smu_v11_0_get_dpm_freq_by_index(smu, - clk_type, 0, &freq_values[0]); - if (ret) - return ret; - ret = smu_v11_0_get_dpm_freq_by_index(smu, - clk_type, - count - 1, - &freq_values[2]); - if (ret) - return ret; - - freq_values[1] = cur_value; - mark_index = cur_value == freq_values[0] ? 0 : - cur_value == freq_values[2] ? 2 : 1; - - levels = 3; - if (mark_index != 1) { - levels = 2; - freq_values[1] = freq_values[2]; - } - - for (i = 0; i < levels; i++) { - *offset += sysfs_emit_at(buf, *offset, - "%d: %uMhz %s\n", - i, freq_values[i], - i == mark_index ? "*" : ""); - } - } + single_dpm_table = &(dpm_context->dpm_tables.dcef_table); break; case SMU_PCIE: gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); - for (i = 0; i < NUM_LINK_LEVELS; i++) { - *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i, - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", - pptable->LclkFreq[i], - (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && - (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? - "*" : ""); - } - break; + pcie_table = &dpm_context->dpm_tables.pcie_table; + return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed, + lane_width, buf, offset); case SMU_OD_SCLK: if (!smu->od_enabled || !od_table || !od_settings) return -EOPNOTSUPP; @@ -1462,199 +1394,16 @@ static int navi10_emit_clk_levels(struct smu_context *smu, break; } - return 0; -} - -static int navi10_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) -{ - uint16_t *curve_settings; - int i, levels, size = 0, ret = 0, start_offset = 0; - uint32_t cur_value = 0, value = 0, count = 0; - uint32_t freq_values[3] = {0}; - uint32_t mark_index = 0; - struct smu_table_context *table_context = &smu->smu_table; - uint32_t gen_speed, lane_width; - struct smu_dpm_context *smu_dpm = &smu->smu_dpm; - struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; - PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; - OverDriveTable_t *od_table = - (OverDriveTable_t *)table_context->overdrive_table; - struct smu_11_0_overdrive_table *od_settings = smu->od_settings; - uint32_t min_value, max_value; - - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - - switch (clk_type) { - case SMU_GFXCLK: - case SMU_SCLK: - case SMU_SOCCLK: - case SMU_MCLK: - case SMU_UCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_DCLK: - case SMU_DCEFCLK: - ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value); + if (single_dpm_table) { + ret = navi10_get_current_clk_freq_by_table(smu, clk_type, + &cur_value); if (ret) - return size - start_offset; - - ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); - if (ret) - return size - start_offset; - - ret = navi10_is_support_fine_grained_dpm(smu, clk_type); - if (ret < 0) return ret; - - if (!ret) { - for (i = 0; i < count; i++) { - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); - if (ret) - return size - start_offset; - - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, - cur_value == value ? "*" : ""); - } - } else { - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); - if (ret) - return size - start_offset; - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); - if (ret) - return size - start_offset; - - freq_values[1] = cur_value; - mark_index = cur_value == freq_values[0] ? 0 : - cur_value == freq_values[2] ? 2 : 1; - - levels = 3; - if (mark_index != 1) { - levels = 2; - freq_values[1] = freq_values[2]; - } - - for (i = 0; i < levels; i++) { - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], - i == mark_index ? "*" : ""); - } - } - break; - case SMU_PCIE: - gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); - lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); - for (i = 0; i < NUM_LINK_LEVELS; i++) - size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", - pptable->LclkFreq[i], - (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && - (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? - "*" : ""); - break; - case SMU_OD_SCLK: - if (!smu->od_enabled || !od_table || !od_settings) - break; - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) - break; - size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); - size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", - od_table->GfxclkFmin, od_table->GfxclkFmax); - break; - case SMU_OD_MCLK: - if (!smu->od_enabled || !od_table || !od_settings) - break; - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) - break; - size += sysfs_emit_at(buf, size, "OD_MCLK:\n"); - size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax); - break; - case SMU_OD_VDDC_CURVE: - if (!smu->od_enabled || !od_table || !od_settings) - break; - if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) - break; - size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n"); - for (i = 0; i < 3; i++) { - switch (i) { - case 0: - curve_settings = &od_table->GfxclkFreq1; - break; - case 1: - curve_settings = &od_table->GfxclkFreq2; - break; - case 2: - curve_settings = &od_table->GfxclkFreq3; - break; - } - size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n", - i, curve_settings[0], - curve_settings[1] / NAVI10_VOLTAGE_SCALE); - } - break; - case SMU_OD_RANGE: - if (!smu->od_enabled || !od_table || !od_settings) - break; - size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); - - if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) { - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN, - &min_value, NULL); - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX, - NULL, &max_value); - size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", - min_value, max_value); - } - - if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) { - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n", - min_value, max_value); - } - - if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) { - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n", - min_value, max_value); - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n", - min_value, max_value); - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n", - min_value, max_value); - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n", - min_value, max_value); - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n", - min_value, max_value); - navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3, - &min_value, &max_value); - size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n", - min_value, max_value); - } - - break; - default: - break; + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); } - return size - start_offset; + return 0; } static int navi10_force_clk_levels(struct smu_context *smu, @@ -1711,18 +1460,15 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_11_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_11_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; uint32_t sclk_freq; - pstate_table->gfxclk_pstate.min = gfx_table->min; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(11, 0, 0): switch (adev->pdev->revision) { @@ -1771,15 +1517,15 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) } pstate_table->gfxclk_pstate.peak = sclk_freq; - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); - if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && - mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && - soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { + if (SMU_DPM_TABLE_MAX(gfx_table) > NAVI10_UMD_PSTATE_PROFILING_GFXCLK && + SMU_DPM_TABLE_MAX(mem_table) > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && + SMU_DPM_TABLE_MAX(soc_table) > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) { pstate_table->gfxclk_pstate.standard = NAVI10_UMD_PSTATE_PROFILING_GFXCLK; pstate_table->uclk_pstate.standard = @@ -1875,13 +1621,14 @@ static int navi10_display_config_changed(struct smu_context *smu) static bool navi10_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + navi10_dpm_features.bits); } static int navi10_get_fan_speed_rpm(struct smu_context *smu, @@ -2449,10 +2196,13 @@ static int navi10_update_pcie_parameters(struct smu_context *smu, int i; /* lclk dpm table setup */ - for (i = 0; i < MAX_PCIE_CONF; i++) { + for (i = 0; i < NUM_LINK_LEVELS; i++) { dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i]; dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i]; + dpm_context->dpm_tables.pcie_table.lclk_freq[i] = + pptable->LclkFreq[i]; } + dpm_context->dpm_tables.pcie_table.lclk_levels = NUM_LINK_LEVELS; for (i = 0; i < NUM_LINK_LEVELS; i++) { dpm_context->dpm_tables.pcie_table.pcie_gen[i] = @@ -2961,7 +2711,8 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, { struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_legacy_t metrics; int ret = 0; @@ -3023,6 +2774,8 @@ static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -3169,7 +2922,8 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, { struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -3233,6 +2987,8 @@ static ssize_t navi10_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -3241,7 +2997,8 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, { struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_NV12_legacy_t metrics; int ret = 0; @@ -3308,6 +3065,8 @@ static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -3316,7 +3075,8 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, { struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_NV12_t metrics; int ret = 0; @@ -3385,6 +3145,8 @@ static ssize_t navi12_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -3512,13 +3274,12 @@ static int navi10_set_config_table(struct smu_context *smu, } static const struct pptable_funcs navi10_ppt_funcs = { - .get_allowed_feature_mask = navi10_get_allowed_feature_mask, + .init_allowed_features = navi10_init_allowed_features, .set_default_dpm_table = navi10_set_default_dpm_table, .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable, .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable, .i2c_init = navi10_i2c_control_init, .i2c_fini = navi10_i2c_control_fini, - .print_clk_levels = navi10_print_clk_levels, .emit_clk_levels = navi10_emit_clk_levels, .force_clk_levels = navi10_force_clk_levels, .populate_umd_state_clk = navi10_populate_umd_state_clk, @@ -3555,8 +3316,6 @@ static const struct pptable_funcs navi10_ppt_funcs = { .set_tool_table_location = smu_v11_0_set_tool_table_location, .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, .system_features_control = smu_v11_0_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .init_display_count = smu_v11_0_init_display_count, .set_allowed_mask = smu_v11_0_set_allowed_mask, .get_enabled_mask = smu_cmn_get_enabled_mask, @@ -3605,11 +3364,10 @@ static const struct pptable_funcs navi10_ppt_funcs = { void navi10_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &navi10_ppt_funcs; - smu->message_map = navi10_message_map; smu->clock_map = navi10_clk_map; smu->feature_map = navi10_feature_mask_map; smu->table_map = navi10_table_map; smu->pwr_src_map = navi10_pwr_src_map; smu->workload_map = navi10_workload_map; - smu_v11_0_set_smu_mailbox_registers(smu); + smu_v11_0_init_msg_ctl(smu, navi10_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 774283ac78277..c7b7179a38eff 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -60,16 +60,18 @@ #undef pr_info #undef pr_debug -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) +static const struct smu_feature_bits sienna_cichlid_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_PREFETCHER_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_DCEFCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) + } +}; #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15 @@ -250,7 +252,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; @@ -276,85 +278,82 @@ static const uint8_t sienna_cichlid_throttler_map[] = { }; static int -sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +sienna_cichlid_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) - | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) - | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) - | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) - | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_DS_FCLK_BIT) - | FEATURE_MASK(FEATURE_DS_UCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) - | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) - | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) - | FEATURE_MASK(FEATURE_GFX_SS_BIT) - | FEATURE_MASK(FEATURE_VR0HOT_BIT) - | FEATURE_MASK(FEATURE_PPT_BIT) - | FEATURE_MASK(FEATURE_TDC_BIT) - | FEATURE_MASK(FEATURE_BACO_BIT) - | FEATURE_MASK(FEATURE_APCC_DFLL_BIT) - | FEATURE_MASK(FEATURE_FW_CTF_BIT) - | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT) - | FEATURE_MASK(FEATURE_THERMAL_BIT) - | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT); + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_PREFETCHER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_RSMU_SMN_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_SS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_PPT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_TDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_APCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THERMAL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_OUT_OF_BAND_MONITOR_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_GPO_BIT); } if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) && (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && !(adev->flags & AMD_IS_APU)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_DCS_BIT); - if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) - | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT) - | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT); + if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_VDDCI_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_MVDD_SCALING_BIT); + } if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCEFCLK_BIT); if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MMHUB_PG_BIT); if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN || smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_PG_BIT); if (smu->dc_controlled_by_gpio) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ACDC_BIT); if (amdgpu_device_should_use_aspm(adev)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); return 0; } @@ -533,6 +532,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; int table_size; + int ret; table_size = get_table_size(smu); SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size, @@ -560,9 +560,10 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); @@ -585,7 +586,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) err3_out: kfree(smu_table->watermarks_table); err2_out: - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); err1_out: kfree(smu_table->metrics_table); err0_out: @@ -954,13 +955,15 @@ static int sienna_cichlid_init_smc_tables(struct smu_context *smu) static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; struct amdgpu_device *adev = smu->adev; int i, ret = 0; DpmDescriptor_t *table_member; + uint16_t *lclk_freq; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; GET_PPTABLE_MEMBER(DpmDescriptor, &table_member); if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, @@ -968,68 +971,63 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_SOCCLK].SnapToDiscrete; + if (!table_member[PPCLK_SOCCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_GFXCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_GFXCLK].SnapToDiscrete; + if (!table_member[PPCLK_GFXCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* uclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_UCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_UCLK].SnapToDiscrete; + if (!table_member[PPCLK_UCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* fclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_FCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_FCLK].SnapToDiscrete; + if (!table_member[PPCLK_FCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* vclk0/1 dpm table setup */ @@ -1038,20 +1036,20 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) continue; dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = i ? SMU_VCLK1 : SMU_VCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, i ? SMU_VCLK1 : SMU_VCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0].SnapToDiscrete; + if (!table_member[i ? PPCLK_VCLK_1 : PPCLK_VCLK_0] + .SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } } @@ -1060,95 +1058,96 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu) if (adev->vcn.harvest_config & (1 << i)) continue; dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = i ? SMU_DCLK1 : SMU_DCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, i ? SMU_DCLK1 : SMU_DCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0].SnapToDiscrete; + if (!table_member[i ? PPCLK_DCLK_1 : PPCLK_DCLK_0] + .SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } } /* dcefclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dcef_table; + dpm_table->clk_type = SMU_DCEFCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_DCEFCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_DCEFCLK].SnapToDiscrete; + if (!table_member[PPCLK_DCEFCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* pixelclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.pixel_table; + dpm_table->clk_type = SMU_PIXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_PIXCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_PIXCLK].SnapToDiscrete; + if (!table_member[PPCLK_PIXCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* displayclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.display_table; + dpm_table->clk_type = SMU_DISPCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_DISPCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_DISPCLK].SnapToDiscrete; + if (!table_member[PPCLK_DISPCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* phyclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.phy_table; + dpm_table->clk_type = SMU_PHYCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { ret = smu_v11_0_set_single_dpm_table(smu, SMU_PHYCLK, dpm_table); if (ret) return ret; - dpm_table->is_fine_grained = - !table_member[PPCLK_PHYCLK].SnapToDiscrete; + if (!table_member[PPCLK_PHYCLK].SnapToDiscrete) + dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } + GET_PPTABLE_MEMBER(LclkFreq, &lclk_freq); + for (i = 0; i < NUM_LINK_LEVELS; i++) + dpm_context->dpm_tables.pcie_table.lclk_freq[i] = lclk_freq[i]; + dpm_context->dpm_tables.pcie_table.lclk_levels = NUM_LINK_LEVELS; + return 0; } @@ -1269,103 +1268,56 @@ static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_tabl *max = od_table->max[setting]; } -static int sienna_cichlid_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int sienna_cichlid_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { struct amdgpu_device *adev = smu->adev; struct smu_table_context *table_context = &smu->smu_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context; - uint16_t *table_member; - struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; OverDriveTable_t *od_table = (OverDriveTable_t *)table_context->overdrive_table; - int i, size = 0, ret = 0, start_offset = 0; - uint32_t cur_value = 0, value = 0, count = 0; - uint32_t freq_values[3] = {0}; - uint32_t mark_index = 0; + int size = *offset, ret = 0, start_offset = *offset; + uint32_t cur_value = 0; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_pcie_table *pcie_table; uint32_t gen_speed, lane_width; uint32_t min_value, max_value; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_GFXCLK: case SMU_SCLK: + single_dpm_table = &(dpm_context->dpm_tables.gfx_table); + break; case SMU_SOCCLK: + single_dpm_table = &(dpm_context->dpm_tables.soc_table); + break; case SMU_MCLK: case SMU_UCLK: + single_dpm_table = &(dpm_context->dpm_tables.uclk_table); + break; case SMU_FCLK: + single_dpm_table = &(dpm_context->dpm_tables.fclk_table); + break; case SMU_VCLK: case SMU_VCLK1: + single_dpm_table = &(dpm_context->dpm_tables.vclk_table); + break; case SMU_DCLK: case SMU_DCLK1: + single_dpm_table = &(dpm_context->dpm_tables.dclk_table); + break; case SMU_DCEFCLK: - ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value); - if (ret) - goto print_clk_out; - - ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count); - if (ret) - goto print_clk_out; - - if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) { - for (i = 0; i < count; i++) { - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); - if (ret) - goto print_clk_out; - - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, - cur_value == value ? "*" : ""); - } - } else { - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]); - if (ret) - goto print_clk_out; - ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]); - if (ret) - goto print_clk_out; - - freq_values[1] = cur_value; - mark_index = cur_value == freq_values[0] ? 0 : - cur_value == freq_values[2] ? 2 : 1; - - count = 3; - if (mark_index != 1) { - count = 2; - freq_values[1] = freq_values[2]; - } - - for (i = 0; i < count; i++) { - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i], - cur_value == freq_values[i] ? "*" : ""); - } - - } + single_dpm_table = &(dpm_context->dpm_tables.dcef_table); break; case SMU_PCIE: gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu); lane_width = smu_v11_0_get_current_pcie_link_width_level(smu); - GET_PPTABLE_MEMBER(LclkFreq, &table_member); - for (i = 0; i < NUM_LINK_LEVELS; i++) - size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," : - (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "", - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" : - (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "", - table_member[i], - (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) && - (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ? - "*" : ""); - break; + pcie_table = &dpm_context->dpm_tables.pcie_table; + return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed, + lane_width, buf, offset); case SMU_OD_SCLK: if (!smu->od_enabled || !od_table || !od_settings) break; @@ -1434,8 +1386,18 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu, break; } -print_clk_out: - return size - start_offset; + if (single_dpm_table) { + ret = sienna_cichlid_get_current_clk_freq_by_table( + smu, clk_type, &cur_value); + if (ret) + return ret; + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); + } + + *offset += size - start_offset; + + return 0; } static int sienna_cichlid_force_clk_levels(struct smu_context *smu, @@ -1487,24 +1449,21 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_11_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_11_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; - pstate_table->gfxclk_pstate.min = gfx_table->min; - pstate_table->gfxclk_pstate.peak = gfx_table->max; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(11, 0, 7): @@ -1577,13 +1536,14 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu) static bool sienna_cichlid_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + sienna_cichlid_dpm_features.bits); } static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu, @@ -2141,7 +2101,7 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, uint8_t pcie_width_cap) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; + struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; uint8_t *table_member1, *table_member2; uint8_t min_gen_speed, max_gen_speed; uint8_t min_lane_width, max_lane_width; @@ -2674,9 +2634,9 @@ static void sienna_cichlid_i2c_control_fini(struct smu_context *smu) static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetricsExternal_t metrics_external; SmuMetrics_t *metrics = &(metrics_external.SmuMetrics); @@ -2825,6 +2785,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -3081,21 +3043,21 @@ static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu, static int sienna_cichlid_mode2_reset(struct smu_context *smu) { - int ret = 0, index; + struct smu_msg_ctl *ctl = &smu->msg_ctl; struct amdgpu_device *adev = smu->adev; + int ret = 0; int timeout = 100; - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, - SMU_MSG_DriverMode2Reset); - - mutex_lock(&smu->message_lock); + mutex_lock(&ctl->lock); - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, - SMU_RESET_MODE_2); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_DriverMode2Reset, + SMU_RESET_MODE_2); + if (ret) + goto out; - ret = smu_cmn_wait_for_response(smu); + ret = smu_msg_wait_response(ctl, 0); while (ret != 0 && timeout) { - ret = smu_cmn_wait_for_response(smu); + ret = smu_msg_wait_response(ctl, 0); /* Wait a bit more time for getting ACK */ if (ret != 0) { --timeout; @@ -3113,23 +3075,23 @@ static int sienna_cichlid_mode2_reset(struct smu_context *smu) goto out; } - dev_info(smu->adev->dev, "restore config space...\n"); + dev_info(adev->dev, "restore config space...\n"); /* Restore the config space saved during init */ amdgpu_device_load_pci_state(adev->pdev); out: - mutex_unlock(&smu->message_lock); + mutex_unlock(&ctl->lock); return ret; } static const struct pptable_funcs sienna_cichlid_ppt_funcs = { - .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, + .init_allowed_features = sienna_cichlid_init_allowed_features, .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable, .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable, .i2c_init = sienna_cichlid_i2c_control_init, .i2c_fini = sienna_cichlid_i2c_control_fini, - .print_clk_levels = sienna_cichlid_print_clk_levels, + .emit_clk_levels = sienna_cichlid_emit_clk_levels, .force_clk_levels = sienna_cichlid_force_clk_levels, .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk, .pre_display_config_changed = sienna_cichlid_pre_display_config_changed, @@ -3164,8 +3126,6 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .set_tool_table_location = smu_v11_0_set_tool_table_location, .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, .system_features_control = sienna_cichlid_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .init_display_count = NULL, .set_allowed_mask = smu_v11_0_set_allowed_mask, .get_enabled_mask = smu_cmn_get_enabled_mask, @@ -3220,11 +3180,10 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { void sienna_cichlid_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &sienna_cichlid_ppt_funcs; - smu->message_map = sienna_cichlid_message_map; smu->clock_map = sienna_cichlid_clk_map; smu->feature_map = sienna_cichlid_feature_mask_map; smu->table_map = sienna_cichlid_table_map; smu->pwr_src_map = sienna_cichlid_pwr_src_map; smu->workload_map = sienna_cichlid_workload_map; - smu_v11_0_set_smu_mailbox_registers(smu); + smu_v11_0_init_msg_ctl(smu, sienna_cichlid_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index b0d6487171d70..1eec1a88e05f8 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -262,7 +262,6 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(smu->adev->dev, "SMU driver if version not matched\n"); } return ret; @@ -428,14 +427,13 @@ int smu_v11_0_fini_smc_tables(struct smu_context *smu) struct smu_table_context *smu_table = &smu->smu_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); kfree(smu_table->user_overdrive_table); kfree(smu_table->boot_overdrive_table); kfree(smu_table->overdrive_table); kfree(smu_table->max_sustainable_clocks); kfree(smu_table->driver_pptable); kfree(smu_table->clocks_table); - smu_table->gpu_metrics_table = NULL; smu_table->user_overdrive_table = NULL; smu_table->boot_overdrive_table = NULL; smu_table->overdrive_table = NULL; @@ -751,12 +749,13 @@ int smu_v11_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) { + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) { ret = -EINVAL; goto failed; } - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); @@ -1859,12 +1858,9 @@ int smu_v11_0_set_performance_level(struct smu_context *smu, { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_11_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_11_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_11_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; @@ -1876,22 +1872,22 @@ int smu_v11_0_set_performance_level(struct smu_context *smu, switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: - sclk_min = sclk_max = gfx_table->max; - mclk_min = mclk_max = mem_table->max; - socclk_min = socclk_max = soc_table->max; + sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); break; case AMD_DPM_FORCED_LEVEL_LOW: - sclk_min = sclk_max = gfx_table->min; - mclk_min = mclk_max = mem_table->min; - socclk_min = socclk_max = soc_table->min; + sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); break; case AMD_DPM_FORCED_LEVEL_AUTO: - sclk_min = gfx_table->min; - sclk_max = gfx_table->max; - mclk_min = mem_table->min; - mclk_max = mem_table->max; - socclk_min = soc_table->min; - socclk_max = soc_table->max; + sclk_min = SMU_DPM_TABLE_MIN(gfx_table); + sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = SMU_DPM_TABLE_MIN(mem_table); + mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = SMU_DPM_TABLE_MIN(soc_table); + socclk_max = SMU_DPM_TABLE_MAX(soc_table); auto_level = true; break; case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: @@ -2028,7 +2024,7 @@ int smu_v11_0_get_dpm_level_count(struct smu_context *smu, int smu_v11_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, - struct smu_11_0_dpm_table *single_dpm_table) + struct smu_dpm_table *single_dpm_table) { int ret = 0; uint32_t clk; @@ -2054,11 +2050,6 @@ int smu_v11_0_set_single_dpm_table(struct smu_context *smu, single_dpm_table->dpm_levels[i].value = clk; single_dpm_table->dpm_levels[i].enabled = true; - - if (i == 0) - single_dpm_table->min = clk; - else if (i == single_dpm_table->count - 1) - single_dpm_table->max = clk; } return 0; @@ -2177,11 +2168,19 @@ int smu_v11_0_restore_user_od_settings(struct smu_context *smu) return ret; } -void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu) +void smu_v11_0_init_msg_ctl(struct smu_context *smu, + const struct cmn2asic_msg_mapping *message_map) { struct amdgpu_device *adev = smu->adev; - - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = message_map; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 9626da2dba584..f4d4918e54b78 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -58,17 +58,19 @@ #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits vangogh_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), @@ -225,6 +227,7 @@ static int vangogh_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -242,11 +245,12 @@ static int vangogh_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); - smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_3)); - smu_table->gpu_metrics_table_size = max(smu_table->gpu_metrics_table_size, sizeof(struct gpu_metrics_v2_4)); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + max3(sizeof(struct gpu_metrics_v2_2), + sizeof(struct gpu_metrics_v2_3), + sizeof(struct gpu_metrics_v2_4)), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); @@ -262,7 +266,7 @@ static int vangogh_tables_init(struct smu_context *smu) err3_out: kfree(smu_table->watermarks_table); err2_out: - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); err1_out: kfree(smu_table->metrics_table); err0_out: @@ -453,7 +457,11 @@ static int vangogh_init_smc_tables(struct smu_context *smu) #ifdef CONFIG_X86 /* AMD x86 APU only */ +#ifdef HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE smu->cpu_core_num = topology_num_cores_per_package(); +#else + smu->cpu_core_num = boot_cpu_data.x86_max_cores; +#endif #else smu->cpu_core_num = 4; #endif @@ -502,7 +510,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; /* we need to re-init after suspend so return false */ if (adev->in_suspend) @@ -513,7 +521,8 @@ static bool vangogh_is_dpm_running(struct smu_context *smu) if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + vangogh_dpm_features.bits); } static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type, @@ -559,13 +568,14 @@ static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_typ return 0; } -static int vangogh_print_legacy_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int vangogh_emit_legacy_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { + int i, idx, size = *offset, ret = 0, start_offset = *offset; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_legacy_t metrics; struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm); - int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; bool cur_value_match_level = false; @@ -575,9 +585,6 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu, if (ret) return ret; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { @@ -659,15 +666,18 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + *offset += size - start_offset; + + return 0; } -static int vangogh_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int vangogh_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { + int i, idx, size = *offset, ret = 0, start_offset = *offset; DpmClocks_t *clk_table = smu->smu_table.clocks_table; SmuMetrics_t metrics; - int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0; bool cur_value_match_level = false; uint32_t min, max; @@ -678,9 +688,6 @@ static int vangogh_print_clk_levels(struct smu_context *smu, if (ret) return ret; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); @@ -781,18 +788,21 @@ static int vangogh_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + *offset += size - start_offset; + + return 0; } -static int vangogh_common_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int vangogh_common_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { int ret = 0; if (smu->smc_fw_if_version < 0x3) - ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf); + ret = vangogh_emit_legacy_clk_levels(smu, clk_type, buf, offset); else - ret = vangogh_print_clk_levels(smu, clk_type, buf); + ret = vangogh_emit_clk_levels(smu, clk_type, buf, offset); return ret; } @@ -1652,9 +1662,9 @@ static int vangogh_set_watermarks_table(struct smu_context *smu, static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_3 *gpu_metrics = - (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_legacy_t metrics; int ret = 0; @@ -1703,15 +1713,17 @@ static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_3); } static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_2 *gpu_metrics = - (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_2 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_legacy_t metrics; int ret = 0; @@ -1760,15 +1772,17 @@ static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_2); } static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_3 *gpu_metrics = - (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -1831,6 +1845,8 @@ static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_3); } @@ -1838,9 +1854,9 @@ static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu, void **table) { SmuMetrics_t metrics; - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_4 *gpu_metrics = - (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_4 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); int ret = 0; ret = smu_cmn_get_metrics_table(smu, &metrics, true); @@ -1911,15 +1927,17 @@ static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_4); } static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_2 *gpu_metrics = - (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_2 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -1975,6 +1993,8 @@ static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_2); } @@ -2259,18 +2279,12 @@ static int vangogh_post_smu_init(struct smu_context *smu) static int vangogh_mode_reset(struct smu_context *smu, int type) { - int ret = 0, index = 0; - - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, - SMU_MSG_GfxDeviceDriverReset); - if (index < 0) - return index == -EACCES ? 0 : index; - - mutex_lock(&smu->message_lock); - - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type); + struct smu_msg_ctl *ctl = &smu->msg_ctl; + int ret; - mutex_unlock(&smu->message_lock); + mutex_lock(&ctl->lock); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, type); + mutex_unlock(&ctl->lock); mdelay(10); @@ -2509,8 +2523,6 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .fini_power = smu_v11_0_fini_power, .register_irq_handler = smu_v11_0_register_irq_handler, .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable, .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable, .is_dpm_running = vangogh_is_dpm_running, @@ -2524,7 +2536,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .interrupt_work = smu_v11_0_interrupt_work, .get_gpu_metrics = vangogh_common_get_gpu_metrics, .od_edit_dpm_table = vangogh_od_edit_dpm_table, - .print_clk_levels = vangogh_common_print_clk_levels, + .emit_clk_levels = vangogh_common_emit_clk_levels, .set_default_dpm_table = vangogh_set_default_dpm_tables, .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, .notify_rlc_state = vangogh_notify_rlc_state, @@ -2550,10 +2562,9 @@ static const struct pptable_funcs vangogh_ppt_funcs = { void vangogh_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &vangogh_ppt_funcs; - smu->message_map = vangogh_message_map; smu->feature_map = vangogh_feature_mask_map; smu->table_map = vangogh_table_map; smu->workload_map = vangogh_workload_map; smu->is_apu = true; - smu_v11_0_set_smu_mailbox_registers(smu); + smu_v11_0_init_msg_ctl(smu, vangogh_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index eaa9ea162f169..31e21ff8859a5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -41,15 +41,6 @@ #undef pr_info #undef pr_debug -#define mmMP1_SMN_C2PMSG_66 0x0282 -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_82 0x0292 -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_90 0x029a -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 - static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), @@ -157,6 +148,7 @@ static int renoir_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -178,9 +170,10 @@ static int renoir_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v2_2), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err3_out; return 0; @@ -491,11 +484,12 @@ static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) return 0; } -static int renoir_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int renoir_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { - int i, idx, size = 0, ret = 0, start_offset = 0; uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0; + int i, idx, size = *offset, ret = 0, start_offset = *offset; SmuMetrics_t metrics; bool cur_value_match_level = false; @@ -505,9 +499,6 @@ static int renoir_print_clk_levels(struct smu_context *smu, if (ret) return ret; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_RANGE: ret = smu_cmn_send_smc_msg_with_param(smu, @@ -534,24 +525,24 @@ static int renoir_print_clk_levels(struct smu_context *smu, /* retirve table returned paramters unit is MHz */ cur_value = metrics.ClockFrequency[CLOCK_GFXCLK]; ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max); - if (!ret) { - /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ - if (cur_value == max) - i = 2; - else if (cur_value == min) - i = 0; - else - i = 1; - - size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, - i == 0 ? "*" : ""); - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", - i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK, - i == 1 ? "*" : ""); - size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, - i == 2 ? "*" : ""); - } - return size - start_offset; + if (ret) + return ret; + /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ + if (cur_value == max) + i = 2; + else if (cur_value == min) + i = 0; + else + i = 1; + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, + i == 0 ? "*" : ""); + size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", + i == 1 ? cur_value : + RENOIR_UMD_PSTATE_GFXCLK, + i == 1 ? "*" : ""); + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, + i == 2 ? "*" : ""); + break; case SMU_SOCCLK: count = NUM_SOCCLK_DPM_LEVELS; cur_value = metrics.ClockFrequency[CLOCK_SOCCLK]; @@ -608,7 +599,9 @@ static int renoir_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + *offset += size - start_offset; + + return 0; } static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu) @@ -1371,9 +1364,9 @@ static bool renoir_is_dpm_running(struct smu_context *smu) static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_2 *gpu_metrics = - (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_2 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -1429,6 +1422,8 @@ static ssize_t renoir_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_2); } @@ -1439,18 +1434,18 @@ static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state) } static int renoir_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { if (!feature_mask) return -EINVAL; - memset(feature_mask, 0xff, sizeof(*feature_mask)); + smu_feature_bits_fill(feature_mask); return 0; } static const struct pptable_funcs renoir_ppt_funcs = { .set_power_state = NULL, - .print_clk_levels = renoir_print_clk_levels, + .emit_clk_levels = renoir_emit_clk_levels, .get_current_power_state = renoir_get_current_power_state, .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable, .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable, @@ -1464,8 +1459,6 @@ static const struct pptable_funcs renoir_ppt_funcs = { .check_fw_status = smu_v12_0_check_fw_status, .check_fw_version = smu_v12_0_check_fw_version, .powergate_sdma = smu_v12_0_powergate_sdma, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg, .gfx_off_control = smu_v12_0_gfx_off_control, .get_gfx_off_status = smu_v12_0_get_gfxoff_status, @@ -1491,16 +1484,11 @@ static const struct pptable_funcs renoir_ppt_funcs = { void renoir_set_ppt_funcs(struct smu_context *smu) { - struct amdgpu_device *adev = smu->adev; - smu->ppt_funcs = &renoir_ppt_funcs; - smu->message_map = renoir_message_map; smu->clock_map = renoir_clk_map; smu->table_map = renoir_table_map; smu->workload_map = renoir_workload_map; smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION; smu->is_apu = true; - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + smu_v12_0_init_msg_ctl(smu, renoir_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c index 3d3cd546f0adc..ac5e44dff6c97 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/smu_v12_0.c @@ -101,7 +101,6 @@ int smu_v12_0_check_fw_version(struct smu_context *smu) "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(smu->adev->dev, "SMU driver if version not matched\n"); } return ret; @@ -192,8 +191,7 @@ int smu_v12_0_fini_smc_tables(struct smu_context *smu) kfree(smu_table->watermarks_table); smu_table->watermarks_table = NULL; - kfree(smu_table->gpu_metrics_table); - smu_table->gpu_metrics_table = NULL; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); return 0; } @@ -406,3 +404,20 @@ int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu) return 0; } + +void smu_v12_0_init_msg_ctl(struct smu_context *smu, + const struct cmn2asic_msg_mapping *message_map) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = message_map; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c index 18d5d07045098..259e5a13c1bd2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c @@ -61,18 +61,18 @@ [smu_feature] = {1, (aldebaran_feature)} #define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_XGMI_BIT) | \ - FEATURE_MASK(FEATURE_DPM_VCN_BIT)) - -/* possible frequency drift (1Mhz) */ -#define EPSILON 1 +static const struct smu_feature_bits aldebaran_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATIONS), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN_BIT) + } +}; #define smnPCIE_ESM_CTRL 0x111003D0 @@ -228,6 +228,7 @@ static int aldebaran_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -249,17 +250,18 @@ static int aldebaran_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) { + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) { kfree(smu_table->metrics_table); - return -ENOMEM; + return ret; } smu_table->ecc_table = kzalloc(tables[SMU_TABLE_ECCINFO].size, GFP_KERNEL); if (!smu_table->ecc_table) { kfree(smu_table->metrics_table); - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); return -ENOMEM; } @@ -330,14 +332,9 @@ static int aldebaran_init_smc_tables(struct smu_context *smu) return smu_v13_0_init_smc_tables(smu); } -static int aldebaran_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +static int aldebaran_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -347,7 +344,7 @@ static int aldebaran_get_dpm_ultimate_freq(struct smu_context *smu, uint32_t *min, uint32_t *max) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; uint32_t min_clk, max_clk; if (amdgpu_sriov_vf(smu->adev)) { @@ -376,8 +373,8 @@ static int aldebaran_get_dpm_ultimate_freq(struct smu_context *smu, return -EINVAL; } - min_clk = dpm_table->min; - max_clk = dpm_table->max; + min_clk = SMU_DPM_TABLE_MIN(dpm_table); + max_clk = SMU_DPM_TABLE_MAX(dpm_table); if (min) { if (!min_clk) @@ -400,12 +397,13 @@ static int aldebaran_get_dpm_ultimate_freq(struct smu_context *smu, static int aldebaran_set_default_dpm_table(struct smu_context *smu) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *dpm_table = NULL; + struct smu_dpm_table *dpm_table = NULL; PPTable_t *pptable = smu->smu_table.driver_pptable; int ret = 0; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_SOCCLK, @@ -416,12 +414,11 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { /* in the case of gfxclk, only fine-grained dpm is honored */ dpm_table->count = 2; @@ -429,18 +426,15 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu) dpm_table->dpm_levels[0].enabled = true; dpm_table->dpm_levels[1].value = pptable->GfxclkFmax; dpm_table->dpm_levels[1].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[1].value; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* memclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_UCLK, @@ -451,12 +445,11 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* fclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_FCLK, @@ -467,8 +460,6 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } return 0; @@ -593,29 +584,26 @@ static int aldebaran_populate_umd_state_clk(struct smu_context *smu) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_13_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_13_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; - pstate_table->gfxclk_pstate.min = gfx_table->min; - pstate_table->gfxclk_pstate.peak = gfx_table->max; - pstate_table->gfxclk_pstate.curr.min = gfx_table->min; - pstate_table->gfxclk_pstate.curr.max = gfx_table->max; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); + pstate_table->gfxclk_pstate.curr.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = SMU_DPM_TABLE_MAX(gfx_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; - pstate_table->uclk_pstate.curr.min = mem_table->min; - pstate_table->uclk_pstate.curr.max = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); + pstate_table->uclk_pstate.curr.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.curr.max = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; - pstate_table->socclk_pstate.curr.min = soc_table->min; - pstate_table->socclk_pstate.curr.max = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); + pstate_table->socclk_pstate.curr.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.curr.max = SMU_DPM_TABLE_MAX(soc_table); if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL && mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && @@ -638,30 +626,6 @@ static int aldebaran_populate_umd_state_clk(struct smu_context *smu) return 0; } -static void aldebaran_get_clk_table(struct smu_context *smu, - struct pp_clock_levels_with_latency *clocks, - struct smu_13_0_dpm_table *dpm_table) -{ - uint32_t i; - - clocks->num_levels = min_t(uint32_t, - dpm_table->count, - (uint32_t)PP_MAX_CLOCK_LEVELS); - - for (i = 0; i < clocks->num_levels; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = 0; - } - -} - -static int aldebaran_freqs_in_same_level(int32_t frequency1, - int32_t frequency2) -{ - return (abs(frequency1 - frequency2) <= EPSILON); -} - static int aldebaran_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) @@ -828,16 +792,10 @@ static int aldebaran_emit_clk_levels(struct smu_context *smu, { int ret = 0; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; - struct pp_clock_levels_with_latency clocks; - struct smu_13_0_dpm_table *single_dpm_table; + struct smu_dpm_table *single_dpm_table = NULL; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = NULL; - uint32_t i; - int display_levels; - uint32_t freq_values[3] = {0}; - uint32_t min_clk, max_clk, cur_value = 0; - bool freq_match; - unsigned int clock_mhz; + uint32_t cur_value = 0; static const char attempt_string[] = "Attempt to get current"; if (amdgpu_ras_intr_triggered()) { @@ -848,134 +806,50 @@ static int aldebaran_emit_clk_levels(struct smu_context *smu, dpm_context = smu_dpm->dpm_context; switch (type) { - case SMU_OD_SCLK: *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_SCLK"); *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n", - pstate_table->gfxclk_pstate.curr.min, - pstate_table->gfxclk_pstate.curr.max); + pstate_table->gfxclk_pstate.curr.min, + pstate_table->gfxclk_pstate.curr.max); return 0; - case SMU_SCLK: - ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &cur_value); - if (ret) { - dev_err(smu->adev->dev, "%s gfx clk Failed!", attempt_string); - return ret; - } - - single_dpm_table = &(dpm_context->dpm_tables.gfx_table); - aldebaran_get_clk_table(smu, &clocks, single_dpm_table); - - display_levels = (clocks.num_levels == 1) ? 1 : 2; - - min_clk = pstate_table->gfxclk_pstate.curr.min; - max_clk = pstate_table->gfxclk_pstate.curr.max; - - freq_values[0] = min_clk; - freq_values[1] = max_clk; - - /* fine-grained dpm has only 2 levels */ - if (cur_value > min_clk && cur_value < max_clk) { - display_levels++; - freq_values[2] = max_clk; - freq_values[1] = cur_value; - } - break; - case SMU_OD_MCLK: *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_MCLK"); *offset += sysfs_emit_at(buf, *offset, "0: %uMhz\n1: %uMhz\n", - pstate_table->uclk_pstate.curr.min, - pstate_table->uclk_pstate.curr.max); + pstate_table->uclk_pstate.curr.min, + pstate_table->uclk_pstate.curr.max); return 0; - case SMU_MCLK: - ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &cur_value); - if (ret) { - dev_err(smu->adev->dev, "%s mclk Failed!", attempt_string); - return ret; - } + case SMU_SCLK: + single_dpm_table = &(dpm_context->dpm_tables.gfx_table); + break; + case SMU_MCLK: single_dpm_table = &(dpm_context->dpm_tables.uclk_table); - aldebaran_get_clk_table(smu, &clocks, single_dpm_table); break; - case SMU_SOCCLK: - ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &cur_value); - if (ret) { - dev_err(smu->adev->dev, "%s socclk Failed!", attempt_string); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.soc_table); - aldebaran_get_clk_table(smu, &clocks, single_dpm_table); break; - case SMU_FCLK: - ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &cur_value); - if (ret) { - dev_err(smu->adev->dev, "%s fclk Failed!", attempt_string); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.fclk_table); - aldebaran_get_clk_table(smu, &clocks, single_dpm_table); break; - case SMU_VCLK: - ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &cur_value); - if (ret) { - dev_err(smu->adev->dev, "%s vclk Failed!", attempt_string); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.vclk_table); - aldebaran_get_clk_table(smu, &clocks, single_dpm_table); break; - case SMU_DCLK: - ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &cur_value); - if (ret) { - dev_err(smu->adev->dev, "%s dclk Failed!", attempt_string); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.dclk_table); - aldebaran_get_clk_table(smu, &clocks, single_dpm_table); break; - default: return -EINVAL; } - switch (type) { - case SMU_SCLK: - for (i = 0; i < display_levels; i++) { - clock_mhz = freq_values[i]; - freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value); - freq_match |= (display_levels == 1); - - *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", i, - clock_mhz, - (freq_match) ? "*" : ""); - } - break; - - case SMU_MCLK: - case SMU_SOCCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_DCLK: - for (i = 0; i < clocks.num_levels; i++) { - clock_mhz = clocks.data[i].clocks_in_khz / 1000; - freq_match = aldebaran_freqs_in_same_level(clock_mhz, cur_value); - freq_match |= (clocks.num_levels == 1); - - *offset += sysfs_emit_at(buf, *offset, "%d: %uMhz %s\n", - i, clock_mhz, - (freq_match) ? "*" : ""); + if (single_dpm_table) { + ret = aldebaran_get_current_clk_freq_by_table(smu, type, + &cur_value); + if (ret) { + dev_err(smu->adev->dev, "%s Failed!", attempt_string); + return ret; } - break; - default: - return -EINVAL; + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + cur_value, buf, offset); } return 0; @@ -1040,7 +914,7 @@ static int aldebaran_force_clk_levels(struct smu_context *smu, enum smu_clk_type type, uint32_t mask) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *single_dpm_table = NULL; + struct smu_dpm_table *single_dpm_table = NULL; uint32_t soft_min_level, soft_max_level; int ret = 0; @@ -1322,8 +1196,7 @@ static int aldebaran_set_performance_level(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; int r; @@ -1331,7 +1204,8 @@ static int aldebaran_set_performance_level(struct smu_context *smu, if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); - pstate_table->gfxclk_pstate.curr.max = gfx_table->max; + pstate_table->gfxclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(gfx_table); } switch (level) { @@ -1372,7 +1246,8 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) return -EINVAL; - + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) return -EINVAL; @@ -1399,16 +1274,13 @@ static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu, } if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { - if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || - (max > dpm_context->dpm_tables.gfx_table.max)) { + if (!max || (max < min_clk) || (max > max_clk)) { dev_warn(adev->dev, "Invalid max frequency %d MHz specified for determinism\n", max); return -EINVAL; } /* Restore default min/max clocks and enable determinism */ - min_clk = dpm_context->dpm_tables.gfx_table.min; - max_clk = dpm_context->dpm_tables.gfx_table.max; ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk, false); if (!ret) { usleep_range(500, 1000); @@ -1449,11 +1321,14 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ dev_err(smu->adev->dev, "Input parameter number not correct\n"); return -EINVAL; } - + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); if (input[0] == 0) { - if (input[1] < dpm_context->dpm_tables.gfx_table.min) { - dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", - input[1], dpm_context->dpm_tables.gfx_table.min); + if (input[1] < min_clk) { + dev_warn( + smu->adev->dev, + "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", + input[1], min_clk); pstate_table->gfxclk_pstate.custom.min = pstate_table->gfxclk_pstate.curr.min; return -EINVAL; @@ -1461,9 +1336,11 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ pstate_table->gfxclk_pstate.custom.min = input[1]; } else if (input[0] == 1) { - if (input[1] > dpm_context->dpm_tables.gfx_table.max) { - dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", - input[1], dpm_context->dpm_tables.gfx_table.max); + if (input[1] > max_clk) { + dev_warn( + smu->adev->dev, + "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); pstate_table->gfxclk_pstate.custom.max = pstate_table->gfxclk_pstate.curr.max; return -EINVAL; @@ -1480,8 +1357,10 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ return -EINVAL; } else { /* Use the default frequencies for manual and determinism mode */ - min_clk = dpm_context->dpm_tables.gfx_table.min; - max_clk = dpm_context->dpm_tables.gfx_table.max; + min_clk = SMU_DPM_TABLE_MIN( + &dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX( + &dpm_context->dpm_tables.gfx_table); ret = aldebaran_set_soft_freq_limited_range( smu, SMU_GFXCLK, min_clk, max_clk, false); @@ -1519,12 +1398,13 @@ static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_ static bool aldebaran_is_dpm_running(struct smu_context *smu) { int ret; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + aldebaran_dpm_features.bits); } static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap, @@ -1762,9 +1642,9 @@ static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu) static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int i, ret = 0; @@ -1836,6 +1716,8 @@ static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -1945,26 +1827,28 @@ static int aldebaran_mode1_reset(struct smu_context *smu) static int aldebaran_mode2_reset(struct smu_context *smu) { - int ret = 0, index; + struct smu_msg_ctl *ctl = &smu->msg_ctl; struct amdgpu_device *adev = smu->adev; + int ret = 0; int timeout = 10; - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, - SMU_MSG_GfxDeviceDriverReset); - if (index < 0 ) - return -EINVAL; - mutex_lock(&smu->message_lock); + mutex_lock(&ctl->lock); + if (smu->smc_fw_version >= 0x00441400) { - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, + SMU_RESET_MODE_2); + if (ret) + goto out; + /* This is similar to FLR, wait till max FLR timeout */ msleep(100); - dev_dbg(smu->adev->dev, "restore config space...\n"); + dev_dbg(adev->dev, "restore config space...\n"); /* Restore the config space saved during init */ amdgpu_device_load_pci_state(adev->pdev); - dev_dbg(smu->adev->dev, "wait for reset ack\n"); + dev_dbg(adev->dev, "wait for reset ack\n"); while (ret == -ETIME && timeout) { - ret = smu_cmn_wait_for_response(smu); + ret = smu_msg_wait_response(ctl, 0); /* Wait a bit more time for getting ACK */ if (ret == -ETIME) { --timeout; @@ -1987,7 +1871,7 @@ static int aldebaran_mode2_reset(struct smu_context *smu) if (ret == 1) ret = 0; out: - mutex_unlock(&smu->message_lock); + mutex_unlock(&ctl->lock); return ret; } @@ -2082,7 +1966,7 @@ static int aldebaran_send_hbm_bad_channel_flag(struct smu_context *smu, static const struct pptable_funcs aldebaran_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask, + .init_allowed_features = aldebaran_init_allowed_features, /* dpm/clk tables */ .set_default_dpm_table = aldebaran_set_default_dpm_table, .populate_umd_state_clk = aldebaran_populate_umd_state_clk, @@ -2105,14 +1989,12 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { /* pptable related */ .setup_pptable = aldebaran_setup_pptable, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .write_pptable = smu_cmn_write_pptable, .set_driver_table_location = smu_v13_0_set_driver_table_location, .set_tool_table_location = smu_v13_0_set_tool_table_location, .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, .system_features_control = aldebaran_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .get_enabled_mask = smu_cmn_get_enabled_mask, .feature_is_enabled = smu_cmn_feature_is_enabled, .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception, @@ -2149,10 +2031,9 @@ static const struct pptable_funcs aldebaran_ppt_funcs = { void aldebaran_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &aldebaran_ppt_funcs; - smu->message_map = aldebaran_message_map; smu->clock_map = aldebaran_clk_map; smu->feature_map = aldebaran_feature_mask_map; smu->table_map = aldebaran_table_map; smu->smc_driver_if_version = SMU13_DRIVER_IF_VERSION_ALDE; - smu_v13_0_set_smu_mailbox_registers(smu); + smu_v13_0_init_msg_ctl(smu, aldebaran_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 2efd914d81e5b..99b8aae1bede1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -258,48 +258,6 @@ int smu_v13_0_check_fw_status(struct smu_context *smu) return -EIO; } -int smu_v13_0_check_fw_version(struct smu_context *smu) -{ - struct amdgpu_device *adev = smu->adev; - uint32_t if_version = 0xff, smu_version = 0xff; - uint8_t smu_program, smu_major, smu_minor, smu_debug; - int ret = 0; - - ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); - if (ret) - return ret; - - smu_program = (smu_version >> 24) & 0xff; - smu_major = (smu_version >> 16) & 0xff; - smu_minor = (smu_version >> 8) & 0xff; - smu_debug = (smu_version >> 0) & 0xff; - adev->pm.fw_version = smu_version; - - /* only for dGPU w/ SMU13*/ - if (adev->pm.fw) - dev_dbg(smu->adev->dev, "smu fw reported program %d, version = 0x%08x (%d.%d.%d)\n", - smu_program, smu_version, smu_major, smu_minor, smu_debug); - - /* - * 1. if_version mismatch is not critical as our fw is designed - * to be backward compatible. - * 2. New fw usually brings some optimizations. But that's visible - * only on the paired driver. - * Considering above, we just leave user a verbal message instead - * of halt driver loading. - */ - if (smu->smc_driver_if_version != SMU_IGNORE_IF_VERSION && - if_version != smu->smc_driver_if_version) { - dev_info(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " - "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", - smu->smc_driver_if_version, if_version, - smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(adev->dev, "SMU driver if version not matched\n"); - } - - return ret; -} - static int smu_v13_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) { struct amdgpu_device *adev = smu->adev; @@ -507,14 +465,13 @@ int smu_v13_0_fini_smc_tables(struct smu_context *smu) struct smu_table_context *smu_table = &smu->smu_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); kfree(smu_table->combo_pptable); kfree(smu_table->user_overdrive_table); kfree(smu_table->boot_overdrive_table); kfree(smu_table->overdrive_table); kfree(smu_table->max_sustainable_clocks); kfree(smu_table->driver_pptable); - smu_table->gpu_metrics_table = NULL; smu_table->combo_pptable = NULL; smu_table->user_overdrive_table = NULL; smu_table->boot_overdrive_table = NULL; @@ -532,6 +489,7 @@ int smu_v13_0_fini_smc_tables(struct smu_context *smu) smu_table->watermarks_table = NULL; smu_table->metrics_time = 0; + kfree(smu_dpm->pd_ctl); kfree(smu_dpm->dpm_policies); kfree(smu_dpm->dpm_context); kfree(smu_dpm->golden_dpm_context); @@ -762,11 +720,11 @@ int smu_v13_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || - feature->feature_num < 64) + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); @@ -1003,8 +961,7 @@ static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) { int ret = 0; - if (smu->dc_controlled_by_gpio && - smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) ret = smu_v13_0_allow_ih_interrupt(smu); return ret; @@ -1586,18 +1543,12 @@ int smu_v13_0_set_performance_level(struct smu_context *smu, { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_13_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_13_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; - struct smu_13_0_dpm_table *vclk_table = - &dpm_context->dpm_tables.vclk_table; - struct smu_13_0_dpm_table *dclk_table = - &dpm_context->dpm_tables.dclk_table; - struct smu_13_0_dpm_table *fclk_table = - &dpm_context->dpm_tables.fclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; @@ -1612,34 +1563,34 @@ int smu_v13_0_set_performance_level(struct smu_context *smu, switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: - sclk_min = sclk_max = gfx_table->max; - mclk_min = mclk_max = mem_table->max; - socclk_min = socclk_max = soc_table->max; - vclk_min = vclk_max = vclk_table->max; - dclk_min = dclk_max = dclk_table->max; - fclk_min = fclk_max = fclk_table->max; + sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table); break; case AMD_DPM_FORCED_LEVEL_LOW: - sclk_min = sclk_max = gfx_table->min; - mclk_min = mclk_max = mem_table->min; - socclk_min = socclk_max = soc_table->min; - vclk_min = vclk_max = vclk_table->min; - dclk_min = dclk_max = dclk_table->min; - fclk_min = fclk_max = fclk_table->min; + sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table); break; case AMD_DPM_FORCED_LEVEL_AUTO: - sclk_min = gfx_table->min; - sclk_max = gfx_table->max; - mclk_min = mem_table->min; - mclk_max = mem_table->max; - socclk_min = soc_table->min; - socclk_max = soc_table->max; - vclk_min = vclk_table->min; - vclk_max = vclk_table->max; - dclk_min = dclk_table->min; - dclk_max = dclk_table->max; - fclk_min = fclk_table->min; - fclk_max = fclk_table->max; + sclk_min = SMU_DPM_TABLE_MIN(gfx_table); + sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = SMU_DPM_TABLE_MIN(mem_table); + mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = SMU_DPM_TABLE_MIN(soc_table); + socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = SMU_DPM_TABLE_MIN(vclk_table); + vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = SMU_DPM_TABLE_MIN(dclk_table); + dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = SMU_DPM_TABLE_MIN(fclk_table); + fclk_max = SMU_DPM_TABLE_MAX(fclk_table); auto_level = true; break; case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: @@ -1910,11 +1861,12 @@ static int smu_v13_0_get_fine_grained_status(struct smu_context *smu, int smu_v13_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, - struct smu_13_0_dpm_table *single_dpm_table) + struct smu_dpm_table *single_dpm_table) { int ret = 0; uint32_t clk; int i; + bool is_fine_grained; ret = smu_v13_0_get_dpm_level_count(smu, clk_type, @@ -1925,13 +1877,14 @@ int smu_v13_0_set_single_dpm_table(struct smu_context *smu, } if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) { - ret = smu_v13_0_get_fine_grained_status(smu, - clk_type, - &single_dpm_table->is_fine_grained); + ret = smu_v13_0_get_fine_grained_status(smu, clk_type, + &is_fine_grained); if (ret) { dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); return ret; } + if (is_fine_grained) + single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; } for (i = 0; i < single_dpm_table->count; i++) { @@ -1946,11 +1899,6 @@ int smu_v13_0_set_single_dpm_table(struct smu_context *smu, single_dpm_table->dpm_levels[i].value = clk; single_dpm_table->dpm_levels[i].enabled = true; - - if (i == 0) - single_dpm_table->min = clk; - else if (i == single_dpm_table->count - 1) - single_dpm_table->max = clk; } return 0; @@ -2255,18 +2203,21 @@ int smu_v13_0_baco_exit(struct smu_context *smu) int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) { - uint16_t index; + struct smu_msg_ctl *ctl = &smu->msg_ctl; struct amdgpu_device *adev = smu->adev; + int ret; if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); } - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, - SMU_MSG_EnableGfxImu); - return smu_cmn_send_msg_without_waiting(smu, index, - ENABLE_IMU_ARG_GFXOFF_ENABLE); + mutex_lock(&ctl->lock); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, + ENABLE_IMU_ARG_GFXOFF_ENABLE); + mutex_unlock(&ctl->lock); + + return ret; } int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, @@ -2359,13 +2310,22 @@ int smu_v13_0_set_default_dpm_tables(struct smu_context *smu) smu_table->clocks_table, false); } -void smu_v13_0_set_smu_mailbox_registers(struct smu_context *smu) +void smu_v13_0_init_msg_ctl(struct smu_context *smu, + const struct cmn2asic_msg_mapping *message_map) { struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = message_map; + ctl->flags = 0; } int smu_v13_0_mode1_reset(struct smu_context *smu) @@ -2384,9 +2344,8 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu, uint8_t pcie_width_cap) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_pcie_table *pcie_table = - &dpm_context->dpm_tables.pcie_table; - int num_of_levels = pcie_table->num_of_link_levels; + struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; + int num_of_levels = pcie_table->lclk_levels; uint32_t smu_pcie_arg; int ret = 0; int i; @@ -2508,4 +2467,6 @@ void smu_v13_0_reset_custom_level(struct smu_context *smu) pstate_table->uclk_pstate.custom.max = 0; pstate_table->gfxclk_pstate.custom.min = 0; pstate_table->gfxclk_pstate.custom.max = 0; + pstate_table->fclk_pstate.custom.min = 0; + pstate_table->fclk_pstate.custom.max = 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index eaeff6a9bc50f..4ccaff09ad8a7 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -59,26 +59,23 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) +static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, + int od_feature_bit, + int32_t *min, int32_t *max); + +static const struct smu_feature_bits smu_v13_0_0_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) + } +}; #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 -#define mmMP1_SMN_C2PMSG_66 0x0282 -#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_82 0x0292 -#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 - -#define mmMP1_SMN_C2PMSG_90 0x029a -#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 - #define mmMP1_SMN_C2PMSG_75 0x028b #define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 @@ -296,49 +293,44 @@ static const uint8_t smu_v13_0_0_throttler_map[] = { }; static int -smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +smu_v13_0_0_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0xff, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); } if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); - /* PMFW 78.58 contains a critical fix for gfxoff feature */ if ((smu->smc_fw_version < 0x004e3a00) || !(adev->pm.pp_feature & PP_GFXOFF_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); } if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); } if (!(adev->pm.pp_feature & PP_ULV_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); + smu_feature_list_clear_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); return 0; } @@ -482,6 +474,7 @@ static int smu_v13_0_0_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -511,9 +504,10 @@ static int smu_v13_0_0_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); @@ -529,7 +523,7 @@ static int smu_v13_0_0_tables_init(struct smu_context *smu) err3_out: kfree(smu_table->watermarks_table); err2_out: - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); err1_out: kfree(smu_table->metrics_table); err0_out: @@ -571,11 +565,12 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) struct smu_table_context *table_context = &smu->smu_table; PPTable_t *pptable = table_context->driver_pptable; SkuTable_t *skutable = &pptable->SkuTable; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; int ret = 0; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_SOCCLK, @@ -586,12 +581,11 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_GFXCLK, @@ -613,18 +607,16 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) skutable->DriverReportedClocks.GameClockAc)) { dpm_table->dpm_levels[dpm_table->count - 1].value = skutable->DriverReportedClocks.GameClockAc; - dpm_table->max = skutable->DriverReportedClocks.GameClockAc; } } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* uclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_UCLK, @@ -635,12 +627,11 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* fclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_FCLK, @@ -651,12 +642,11 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* vclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = SMU_VCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_VCLK, @@ -667,12 +657,11 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = SMU_DCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_DCLK, @@ -683,12 +672,11 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dcefclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dcef_table; + dpm_table->clk_type = SMU_DCEFCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_DCEFCLK, @@ -699,8 +687,6 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } return 0; @@ -709,13 +695,14 @@ static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_0_dpm_features.bits); } static int smu_v13_0_0_system_features_control(struct smu_context *smu, @@ -876,7 +863,7 @@ static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu, { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; switch (clk_type) { case SMU_MCLK: @@ -913,9 +900,9 @@ static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu, } if (min) - *min = dpm_table->min; + *min = SMU_DPM_TABLE_MIN(dpm_table); if (max) - *max = dpm_table->max; + *max = SMU_DPM_TABLE_MAX(dpm_table); return 0; } @@ -1061,8 +1048,35 @@ static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu, PPTable_t *pptable = smu->smu_table.driver_pptable; const OverDriveLimits_t * const overdrive_upperlimits = &pptable->SkuTable.OverDriveLimitsBasicMax; + int32_t min_value, max_value; + bool feature_enabled; + + switch (od_feature_bit) { + case PP_OD_FEATURE_FAN_CURVE_BIT: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + if (feature_enabled) { + smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); + smu_v13_0_0_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + } + break; + default: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + break; + } + +out: + return feature_enabled; } static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, @@ -1184,27 +1198,24 @@ static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu, return ret; } -static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, - char *buf) +static int smu_v13_0_0_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; OverDriveTableExternal_t *od_table = (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; - struct smu_13_0_dpm_table *single_dpm_table; - struct smu_13_0_pcie_table *pcie_table; + int i, curr_freq, size = *offset, start_offset = *offset; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - int i, curr_freq, size = 0, start_offset = 0; int32_t min_value, max_value; int ret = 0; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - if (amdgpu_ras_intr_triggered()) { - size += sysfs_emit_at(buf, size, "unavailable\n"); - return size - start_offset; + sysfs_emit_at(buf, size, "unavailable\n"); + return -EBUSY; } switch (clk_type) { @@ -1231,61 +1242,6 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, case SMU_DCEFCLK: single_dpm_table = &(dpm_context->dpm_tables.dcef_table); break; - default: - break; - } - - switch (clk_type) { - case SMU_SCLK: - case SMU_MCLK: - case SMU_SOCCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_VCLK1: - case SMU_DCLK: - case SMU_DCLK1: - case SMU_DCEFCLK: - ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); - if (ret) { - dev_err(smu->adev->dev, "Failed to get current clock freq!"); - return ret; - } - - if (single_dpm_table->is_fine_grained) { - /* - * For fine grained dpms, there are only two dpm levels: - * - level 0 -> min clock freq - * - level 1 -> max clock freq - * And the current clock frequency can be any value between them. - * So, if the current clock frequency is not at level 0 or level 1, - * we will fake it as three dpm levels: - * - level 0 -> min clock freq - * - level 1 -> current actual clock freq - * - level 2 -> max clock freq - */ - if ((single_dpm_table->dpm_levels[0].value != curr_freq) && - (single_dpm_table->dpm_levels[1].value != curr_freq)) { - size += sysfs_emit_at(buf, size, "0: %uMhz\n", - single_dpm_table->dpm_levels[0].value); - size += sysfs_emit_at(buf, size, "1: %uMhz *\n", - curr_freq); - size += sysfs_emit_at(buf, size, "2: %uMhz\n", - single_dpm_table->dpm_levels[1].value); - } else { - size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", - single_dpm_table->dpm_levels[0].value, - single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", - single_dpm_table->dpm_levels[1].value, - single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); - } - } else { - for (i = 0; i < single_dpm_table->count; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", - i, single_dpm_table->dpm_levels[i].value, - single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); - } - break; case SMU_PCIE: ret = smu_v13_0_0_get_smu_metrics_data(smu, METRICS_PCIE_RATE, @@ -1300,24 +1256,10 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, return ret; pcie_table = &(dpm_context->dpm_tables.pcie_table); - for (i = 0; i < pcie_table->num_of_link_levels; i++) - size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : - (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", - (pcie_table->pcie_lane[i] == 1) ? "x1" : - (pcie_table->pcie_lane[i] == 2) ? "x2" : - (pcie_table->pcie_lane[i] == 3) ? "x4" : - (pcie_table->pcie_lane[i] == 4) ? "x8" : - (pcie_table->pcie_lane[i] == 5) ? "x12" : - (pcie_table->pcie_lane[i] == 6) ? "x16" : "", - pcie_table->clk_freq[i], - (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && - (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? - "*" : ""); - break; - + return smu_cmn_print_pcie_levels(smu, pcie_table, + SMU_DPM_PCIE_GEN_IDX(gen_speed), + SMU_DPM_PCIE_WIDTH_IDX(lane_width), + buf, offset); case SMU_OD_SCLK: if (!smu_v13_0_0_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) @@ -1535,7 +1477,21 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + if (single_dpm_table) { + ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, + &curr_freq); + if (ret) { + dev_err(smu->adev->dev, + "Failed to get current clock freq!"); + return ret; + } + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + curr_freq, buf, offset); + } + + *offset += size - start_offset; + + return 0; } @@ -1989,7 +1945,7 @@ static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; - struct smu_13_0_dpm_table *single_dpm_table; + struct smu_dpm_table *single_dpm_table; uint32_t soft_min_level, soft_max_level; uint32_t min_freq, max_freq; int ret = 0; @@ -2035,7 +1991,7 @@ static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, case SMU_VCLK1: case SMU_DCLK: case SMU_DCLK1: - if (single_dpm_table->is_fine_grained) { + if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) { /* There is only 2 levels for fine grained DPM */ soft_max_level = (soft_max_level >= 1 ? 1 : 0); soft_min_level = (soft_min_level >= 1 ? 1 : 0); @@ -2105,11 +2061,12 @@ static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetricsExternal_t metrics_ext; SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; + uint32_t mp1_ver = amdgpu_ip_version(smu->adev, MP1_HWIP, 0); int ret = 0; ret = smu_cmn_get_metrics_table(smu, @@ -2134,7 +2091,12 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, metrics->Vcn1ActivityPercentage); gpu_metrics->average_socket_power = metrics->AverageSocketPower; - gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; + + if ((mp1_ver == IP_VERSION(13, 0, 0) && smu->smc_fw_version <= 0x004e1e00) || + (mp1_ver == IP_VERSION(13, 0, 10) && smu->smc_fw_version <= 0x00500800)) + gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; + else + gpu_metrics->energy_accumulator = UINT_MAX; if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD) gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; @@ -2181,6 +2143,8 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -2290,7 +2254,8 @@ static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu) user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | BIT(PP_OD_FEATURE_UCLK_BIT) | BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); res = smu_v13_0_0_upload_overdrive_table(smu, user_od_table); user_od_table->OverDriveTable.FeatureCtrlMask = 0; if (res == 0) @@ -2303,18 +2268,12 @@ static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_13_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_13_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; - struct smu_13_0_dpm_table *vclk_table = - &dpm_context->dpm_tables.vclk_table; - struct smu_13_0_dpm_table *dclk_table = - &dpm_context->dpm_tables.dclk_table; - struct smu_13_0_dpm_table *fclk_table = - &dpm_context->dpm_tables.fclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct smu_table_context *table_context = &smu->smu_table; @@ -2322,38 +2281,39 @@ static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) DriverReportedClocks_t driver_clocks = pptable->SkuTable.DriverReportedClocks; - pstate_table->gfxclk_pstate.min = gfx_table->min; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); if (driver_clocks.GameClockAc && - (driver_clocks.GameClockAc < gfx_table->max)) + (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table))) pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; else - pstate_table->gfxclk_pstate.peak = gfx_table->max; + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); - pstate_table->vclk_pstate.min = vclk_table->min; - pstate_table->vclk_pstate.peak = vclk_table->max; + pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table); + pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table); - pstate_table->dclk_pstate.min = dclk_table->min; - pstate_table->dclk_pstate.peak = dclk_table->max; + pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table); + pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table); - pstate_table->fclk_pstate.min = fclk_table->min; - pstate_table->fclk_pstate.peak = fclk_table->max; + pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table); if (driver_clocks.BaseClockAc && - driver_clocks.BaseClockAc < gfx_table->max) + driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table)) pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; else - pstate_table->gfxclk_pstate.standard = gfx_table->max; - pstate_table->uclk_pstate.standard = mem_table->max; - pstate_table->socclk_pstate.standard = soc_table->min; - pstate_table->vclk_pstate.standard = vclk_table->min; - pstate_table->dclk_pstate.standard = dclk_table->min; - pstate_table->fclk_pstate.standard = fclk_table->min; + pstate_table->gfxclk_pstate.standard = + SMU_DPM_TABLE_MAX(gfx_table); + pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table); + pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table); + pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table); + pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table); return 0; } @@ -2693,21 +2653,11 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - u32 smu_version; - int ret; /* SRIOV does not support SMU mode1 reset */ if (amdgpu_sriov_vf(adev)) return false; - /* PMFW support is available since 78.41 */ - ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); - if (ret) - return false; - - if (smu_version < 0x004e2900) - return false; - return true; } @@ -2856,13 +2806,7 @@ static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, switch (mp1_state) { case PP_MP1_STATE_UNLOAD: - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_PrepareMp1ForUnload, - 0x55, NULL); - - if (!ret && smu->smu_baco.state == SMU_BACO_STATE_EXIT) - ret = smu_v13_0_disable_pmfw_state(smu); - + ret = smu_cmn_set_mp1_state(smu, mp1_state); break; default: /* Ignore others */ @@ -2906,8 +2850,9 @@ static int smu_v13_0_0_mode1_reset(struct smu_context *smu) /* SMU 13_0_0 PMFW supports RAS fatal error reset from 78.77 */ smu_v13_0_0_set_mode1_reset_param(smu, 0x004e4d00, ¶m); - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_Mode1Reset, param, NULL); + ret = smu_cmn_send_debug_smc_msg_with_param(smu, + DEBUGSMC_MSG_Mode1Reset, param); + break; case IP_VERSION(13, 0, 10): @@ -2958,17 +2903,18 @@ static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu) return -EOPNOTSUPP; } -static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) +static void smu_v13_0_0_init_msg_ctl(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map); - smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); - smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); - smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); + /* Set up debug mailbox registers */ + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; } static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, @@ -3126,8 +3072,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, uint8_t pcie_width_cap) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_pcie_table *pcie_table = - &dpm_context->dpm_tables.pcie_table; + struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; int num_of_levels; uint32_t smu_pcie_arg; uint32_t link_level; @@ -3137,7 +3082,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, int ret = 0; int i; - pcie_table->num_of_link_levels = 0; + pcie_table->lclk_levels = 0; for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { if (!skutable->PcieGenSpeed[link_level] && @@ -3145,16 +3090,16 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, !skutable->LclkFreq[link_level]) continue; - pcie_table->pcie_gen[pcie_table->num_of_link_levels] = - skutable->PcieGenSpeed[link_level]; - pcie_table->pcie_lane[pcie_table->num_of_link_levels] = - skutable->PcieLaneCount[link_level]; - pcie_table->clk_freq[pcie_table->num_of_link_levels] = - skutable->LclkFreq[link_level]; - pcie_table->num_of_link_levels++; + pcie_table->pcie_gen[pcie_table->lclk_levels] = + skutable->PcieGenSpeed[link_level]; + pcie_table->pcie_lane[pcie_table->lclk_levels] = + skutable->PcieLaneCount[link_level]; + pcie_table->lclk_freq[pcie_table->lclk_levels] = + skutable->LclkFreq[link_level]; + pcie_table->lclk_levels++; } - num_of_levels = pcie_table->num_of_link_levels; + num_of_levels = pcie_table->lclk_levels; if (!num_of_levels) return 0; @@ -3206,7 +3151,7 @@ static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu, } static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { - .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_0_init_allowed_features, .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table, .i2c_init = smu_v13_0_0_i2c_control_init, .i2c_fini = smu_v13_0_0_i2c_control_fini, @@ -3220,7 +3165,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .fini_power = smu_v13_0_fini_power, .check_fw_status = smu_v13_0_check_fw_status, .setup_pptable = smu_v13_0_0_setup_pptable, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .write_pptable = smu_cmn_write_pptable, .set_driver_table_location = smu_v13_0_set_driver_table_location, .system_features_control = smu_v13_0_0_system_features_control, @@ -3232,7 +3177,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, .read_sensor = smu_v13_0_0_read_sensor, .feature_is_enabled = smu_cmn_feature_is_enabled, - .print_clk_levels = smu_v13_0_0_print_clk_levels, + .emit_clk_levels = smu_v13_0_0_emit_clk_levels, .force_clk_levels = smu_v13_0_0_force_clk_levels, .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters, .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range, @@ -3259,7 +3204,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, .get_power_limit = smu_v13_0_0_get_power_limit, .set_power_limit = smu_v13_0_0_set_power_limit, - .set_power_source = smu_v13_0_set_power_source, .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, .run_btc = smu_v13_0_run_btc, @@ -3291,14 +3235,13 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &smu_v13_0_0_ppt_funcs; - smu->message_map = smu_v13_0_0_message_map; smu->clock_map = smu_v13_0_0_clk_map; smu->feature_map = smu_v13_0_0_feature_mask_map; smu->table_map = smu_v13_0_0_table_map; smu->pwr_src_map = smu_v13_0_0_pwr_src_map; smu->workload_map = smu_v13_0_0_workload_map; smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION; - smu_v13_0_0_set_smu_mailbox_registers(smu); + smu_v13_0_0_init_msg_ctl(smu); if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c index 9e635f733fbfd..67cd186bd2632 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c @@ -49,13 +49,23 @@ #undef pr_info #undef pr_debug +#define hbm_stack_mask_valid(umc_mask) \ + (((umc_mask) & 0x3) == 0x3) + +#define for_each_hbm_stack(stack_idx, umc_mask) \ + for ((stack_idx) = 0; (umc_mask); \ + (umc_mask) >>= 2, (stack_idx)++) \ + #define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \ [smu_feature] = { 1, (smu_13_0_12_feature) } -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE \ - (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK)) +static const struct smu_feature_bits smu_v13_0_12_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK) + } +}; #define NUM_JPEG_RINGS_FW 10 #define NUM_JPEG_RINGS_GPU_METRICS(gpu_metrics) \ @@ -156,9 +166,6 @@ int smu_v13_0_12_tables_init(struct smu_context *smu) { struct amdgpu_baseboard_temp_metrics_v1_0 *baseboard_temp_metrics; struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; - struct smu_table_context *smu_table = &smu->smu_table; - struct smu_table *tables = smu_table->tables; - struct smu_table_cache *cache; int ret; ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, @@ -167,25 +174,28 @@ int smu_v13_0_12_tables_init(struct smu_context *smu) if (ret) return ret; - ret = smu_table_cache_init(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS, - sizeof(*baseboard_temp_metrics), 50); + ret = smu_driver_table_init(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS, + sizeof(*baseboard_temp_metrics), 50); if (ret) return ret; /* Initialize base board temperature metrics */ - cache = &(tables[SMU_TABLE_BASEBOARD_TEMP_METRICS].cache); - baseboard_temp_metrics = - (struct amdgpu_baseboard_temp_metrics_v1_0 *) cache->buffer; + baseboard_temp_metrics = (struct amdgpu_baseboard_temp_metrics_v1_0 *) + smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); smu_cmn_init_baseboard_temp_metrics(baseboard_temp_metrics, 1, 0); /* Initialize GPU board temperature metrics */ - ret = smu_table_cache_init(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS, - sizeof(*gpuboard_temp_metrics), 50); + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, + sizeof(*gpuboard_temp_metrics), 50); if (ret) { smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); - smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); + smu_driver_table_fini(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); return ret; } - cache = &(tables[SMU_TABLE_GPUBOARD_TEMP_METRICS].cache); - gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *)cache->buffer; + gpuboard_temp_metrics = (struct amdgpu_gpuboard_temp_metrics_v1_0 *) + smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); smu_cmn_init_gpuboard_temp_metrics(gpuboard_temp_metrics, 1, 0); return 0; @@ -193,20 +203,20 @@ int smu_v13_0_12_tables_init(struct smu_context *smu) void smu_v13_0_12_tables_fini(struct smu_context *smu) { - smu_table_cache_fini(smu, SMU_TABLE_BASEBOARD_TEMP_METRICS); - smu_table_cache_fini(smu, SMU_TABLE_GPUBOARD_TEMP_METRICS); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); } static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { int ret; ret = smu_cmn_get_enabled_mask(smu, feature_mask); if (ret == -EIO) { - *feature_mask = 0; + smu_feature_bits_clearall(feature_mask); ret = 0; } @@ -259,8 +269,9 @@ static void smu_v13_0_12_init_xgmi_data(struct smu_context *smu, int ret; if (smu_table->tables[SMU_TABLE_SMU_METRICS].version >= 0x13) { - max_width = (uint8_t)static_metrics->MaxXgmiWidth; - max_speed = (uint16_t)static_metrics->MaxXgmiBitrate; + max_width = (uint8_t)SMUQ10_ROUND(static_metrics->MaxXgmiWidth); + max_speed = + (uint16_t)SMUQ10_ROUND(static_metrics->MaxXgmiBitrate); ret = 0; } else { MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table; @@ -372,14 +383,15 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu) bool smu_v13_0_12_is_dpm_running(struct smu_context *smu) { int ret; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_12_dpm_features.bits); } int smu_v13_0_12_get_smu_metrics_data(struct smu_context *smu, @@ -601,6 +613,40 @@ static bool smu_v13_0_12_is_temp_metrics_supported(struct smu_context *smu, return false; } +int smu_v13_0_12_get_system_power(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + int ret; + + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SYSTEM_POWER_METRICS))) + return -EOPNOTSUPP; + + ret = smu_v13_0_12_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + + switch (sensor) { + case AMDGPU_PP_SENSOR_UBB_POWER: + *value = metrics->SystemPower[SYSTEM_POWER_UBB_POWER]; + break; + case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT: + *value = metrics->SystemPower[SYSTEM_POWER_UBB_POWER_THRESHOLD]; + break; + default: + return -EINVAL; + } + + return ret; +} + int smu_v13_0_12_get_npm_data(struct smu_context *smu, enum amd_pp_sensors sensor, uint32_t *value) @@ -652,39 +698,28 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, struct amdgpu_gpuboard_temp_metrics_v1_0 *gpuboard_temp_metrics; struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + enum smu_driver_table_id table_id; SystemMetricsTable_t *metrics; - struct smu_table *data_table; struct smu_table *sys_table; int ret, sensor_type; u32 idx, sensors; ssize_t size; - if (type == SMU_TEMP_METRIC_BASEBOARD) { - /* Initialize base board temperature metrics */ - data_table = - &smu->smu_table.tables[SMU_TABLE_BASEBOARD_TEMP_METRICS]; - baseboard_temp_metrics = - (struct amdgpu_baseboard_temp_metrics_v1_0 *) - data_table->cache.buffer; - size = sizeof(*baseboard_temp_metrics); - } else { - data_table = - &smu->smu_table.tables[SMU_TABLE_GPUBOARD_TEMP_METRICS]; - gpuboard_temp_metrics = - (struct amdgpu_gpuboard_temp_metrics_v1_0 *) - data_table->cache.buffer; - size = sizeof(*baseboard_temp_metrics); - } - ret = smu_v13_0_12_get_system_metrics_table(smu); if (ret) return ret; sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; - smu_table_cache_update_time(data_table, jiffies); - if (type == SMU_TEMP_METRIC_GPUBOARD) { + switch (type) { + case SMU_TEMP_METRIC_GPUBOARD: + table_id = SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS; + gpuboard_temp_metrics = + (struct amdgpu_gpuboard_temp_metrics_v1_0 *) + smu_driver_table_ptr(smu, table_id); + size = sizeof(*gpuboard_temp_metrics); + gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; gpuboard_temp_metrics->label_version = metrics->LabelVersion; gpuboard_temp_metrics->node_id = metrics->NodeIdentifier; @@ -711,7 +746,15 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, idx++; } } - } else if (type == SMU_TEMP_METRIC_BASEBOARD) { + memcpy(table, gpuboard_temp_metrics, size); + break; + case SMU_TEMP_METRIC_BASEBOARD: + table_id = SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS; + baseboard_temp_metrics = + (struct amdgpu_baseboard_temp_metrics_v1_0 *) + smu_driver_table_ptr(smu, table_id); + size = sizeof(*baseboard_temp_metrics); + baseboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; baseboard_temp_metrics->label_version = metrics->LabelVersion; baseboard_temp_metrics->node_id = metrics->NodeIdentifier; @@ -726,9 +769,12 @@ static ssize_t smu_v13_0_12_get_temp_metrics(struct smu_context *smu, idx++; } } + memcpy(table, baseboard_temp_metrics, size); + break; + default: + return -EINVAL; } - - memcpy(table, data_table->cache.buffer, size); + smu_driver_table_update_cache_time(smu, table_id); return size; } @@ -785,6 +831,9 @@ ssize_t smu_v13_0_12_get_xcp_metrics(struct smu_context *smu, struct amdgpu_xcp idx++; } + xcp_metrics->accumulation_counter = metrics->AccumulationCounter; + xcp_metrics->firmware_timestamp = metrics->Timestamp; + return sizeof(*xcp_metrics); } @@ -793,7 +842,7 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, struct smu_v13_0_6_gpu_metrics *gpu_metrics) { struct amdgpu_device *adev = smu->adev; - int ret = 0, xcc_id, inst, i, j; + int ret = 0, xcc_id, inst, i, j, idx; u8 num_jpeg_rings_gpu_metrics; MetricsTable_t *metrics; @@ -808,6 +857,31 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, gpu_metrics->temperature_vrsoc = SMUQ10_ROUND(metrics->MaxVrTemperature); + if (smu_v13_0_6_cap_supported(smu, + SMU_CAP(TEMP_AID_XCD_HBM))) { + if (adev->umc.active_mask) { + u64 mask = adev->umc.active_mask; + int out_idx = 0; + int stack_idx; + + if (unlikely(hweight64(mask) / 2 > SMU_13_0_6_MAX_HBM_STACKS)) { + dev_warn(adev->dev, "Invalid umc mask %lld\n", mask); + } else { + for_each_hbm_stack(stack_idx, mask) { + if (!hbm_stack_mask_valid(mask)) + continue; + gpu_metrics->temperature_hbm[out_idx++] = + metrics->HbmTemperature[stack_idx]; + } + } + } + idx = 0; + for_each_inst(i, adev->aid_mask) { + gpu_metrics->temperature_aid[idx] = metrics->AidTemperature[i]; + idx++; + } + } + gpu_metrics->average_gfx_activity = SMUQ10_ROUND(metrics->SocketGfxBusy); gpu_metrics->average_umc_activity = @@ -922,7 +996,10 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, gpu_metrics->gfx_below_host_limit_total_acc [i] = SMUQ10_ROUND( metrics->GfxclkBelowHostLimitTotalAcc[inst]); - }; + } + if (smu_v13_0_6_cap_supported(smu, + SMU_CAP(TEMP_AID_XCD_HBM))) + gpu_metrics->temperature_xcd[i] = metrics->XcdTemperature[inst]; } gpu_metrics->xgmi_link_width = metrics->XgmiWidth; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 6908f9930f169..167b3499f7f1b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -52,24 +52,25 @@ #define mmMP1_SMN_C2PMSG_90 0x029a #define mmMP1_SMN_C2PMSG_90_BASE_IDX 1 -#define FEATURE_MASK(feature) (1ULL << feature) - #define SMU_13_0_4_UMD_PSTATE_GFXCLK 938 #define SMU_13_0_4_UMD_PSTATE_SOCCLK 938 #define SMU_13_0_4_UMD_PSTATE_FCLK 1875 -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \ - FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits smu_v13_0_4_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), @@ -151,6 +152,7 @@ static int smu_v13_0_4_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -172,9 +174,10 @@ static int smu_v13_0_4_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v2_1), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err3_out; return 0; @@ -202,8 +205,7 @@ static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) kfree(smu_table->watermarks_table); smu_table->watermarks_table = NULL; - kfree(smu_table->gpu_metrics_table); - smu_table->gpu_metrics_table = NULL; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); return 0; } @@ -211,14 +213,15 @@ static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu) static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_4_dpm_features.bits); } static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) @@ -247,9 +250,9 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en) static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_1 *gpu_metrics = - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_1 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -294,6 +297,8 @@ static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_1); } @@ -494,16 +499,14 @@ static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu, return 0; } -static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int smu_v13_0_4_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { - int i, idx, size = 0, ret = 0, start_offset = 0; + int i, idx, size = *offset, ret = 0, start_offset = *offset; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min, max; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); @@ -525,17 +528,17 @@ static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, case SMU_FCLK: ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - break; + return ret; ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count); if (ret) - break; + return ret; for (i = 0; i < count; i++) { idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value); if (ret) - break; + return ret; size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); @@ -545,7 +548,7 @@ static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, case SMU_SCLK: ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - break; + return ret; min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; if (cur_value == max) @@ -566,7 +569,9 @@ static int smu_v13_0_4_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + *offset += size - start_offset; + + return 0; } static int smu_v13_0_4_read_sensor(struct smu_context *smu, @@ -1093,13 +1098,11 @@ static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *sm static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { .check_fw_status = smu_v13_0_check_fw_status, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = smu_v13_0_4_init_smc_tables, .fini_smc_tables = smu_v13_0_4_fini_smc_tables, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, .system_features_control = smu_v13_0_4_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable, .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable, .set_default_dpm_table = smu_v13_0_set_default_dpm_tables, @@ -1114,20 +1117,27 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { .mode2_reset = smu_v13_0_4_mode2_reset, .get_dpm_ultimate_freq = smu_v13_0_4_get_dpm_ultimate_freq, .od_edit_dpm_table = smu_v13_0_od_edit_dpm_table, - .print_clk_levels = smu_v13_0_4_print_clk_levels, + .emit_clk_levels = smu_v13_0_4_emit_clk_levels, .force_clk_levels = smu_v13_0_4_force_clk_levels, .set_performance_level = smu_v13_0_4_set_performance_level, .set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters, .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, }; -static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu) +static void smu_v13_0_4_init_msg_ctl(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = smu_v13_0_4_message_map; } void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) @@ -1135,14 +1145,13 @@ void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; smu->ppt_funcs = &smu_v13_0_4_ppt_funcs; - smu->message_map = smu_v13_0_4_message_map; smu->feature_map = smu_v13_0_4_feature_mask_map; smu->table_map = smu_v13_0_4_table_map; smu->smc_driver_if_version = SMU13_0_4_DRIVER_IF_VERSION; smu->is_apu = true; if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 4)) - smu_v13_0_4_set_smu_mailbox_registers(smu); + smu_v13_0_4_init_msg_ctl(smu); else - smu_v13_0_set_smu_mailbox_registers(smu); + smu_v13_0_init_msg_ctl(smu, smu_v13_0_4_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c index 4576bf008b22d..141e778333c50 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c @@ -51,17 +51,19 @@ #define mmMP1_C2PMSG_33 (0xbee261 + 0xb00000 / 4) #define mmMP1_C2PMSG_33_BASE_IDX 0 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)) +static const struct smu_feature_bits smu_v13_0_5_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping smu_v13_0_5_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), @@ -125,6 +127,7 @@ static int smu_v13_0_5_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -146,9 +149,10 @@ static int smu_v13_0_5_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v2_1), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err3_out; return 0; @@ -176,8 +180,7 @@ static int smu_v13_0_5_fini_smc_tables(struct smu_context *smu) kfree(smu_table->watermarks_table); smu_table->watermarks_table = NULL; - kfree(smu_table->gpu_metrics_table); - smu_table->gpu_metrics_table = NULL; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); return 0; } @@ -229,14 +232,15 @@ static int smu_v13_0_5_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) static bool smu_v13_0_5_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_5_dpm_features.bits); } static int smu_v13_0_5_mode_reset(struct smu_context *smu, int type) @@ -466,11 +470,11 @@ static int smu_v13_0_5_set_watermarks_table(struct smu_context *smu, } static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu, - void **table) + void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_1 *gpu_metrics = - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_1 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -500,6 +504,8 @@ static ssize_t smu_v13_0_5_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_1); } @@ -858,16 +864,14 @@ static int smu_v13_0_5_set_soft_freq_limited_range(struct smu_context *smu, return ret; } -static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int smu_v13_0_5_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { - int i, idx, size = 0, ret = 0, start_offset = 0; + int i, idx, size = *offset, ret = 0, start_offset = *offset; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min = 0, max = 0; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); @@ -887,17 +891,17 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, case SMU_MCLK: ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - goto print_clk_out; + return ret; ret = smu_v13_0_5_get_dpm_level_count(smu, clk_type, &count); if (ret) - goto print_clk_out; + return ret; for (i = 0; i < count; i++) { idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i; ret = smu_v13_0_5_get_dpm_freq_by_index(smu, clk_type, idx, &value); if (ret) - goto print_clk_out; + return ret; size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); @@ -907,7 +911,7 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, case SMU_SCLK: ret = smu_v13_0_5_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - goto print_clk_out; + return ret; min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; if (cur_value == max) @@ -928,8 +932,9 @@ static int smu_v13_0_5_print_clk_levels(struct smu_context *smu, break; } -print_clk_out: - return size - start_offset; + *offset += size - start_offset; + + return 0; } @@ -1097,13 +1102,11 @@ static int smu_v13_0_5_set_fine_grain_gfx_freq_parameters(struct smu_context *sm static const struct pptable_funcs smu_v13_0_5_ppt_funcs = { .check_fw_status = smu_v13_0_check_fw_status, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = smu_v13_0_5_init_smc_tables, .fini_smc_tables = smu_v13_0_5_fini_smc_tables, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, .system_features_control = smu_v13_0_5_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .dpm_set_vcn_enable = smu_v13_0_5_dpm_set_vcn_enable, .dpm_set_jpeg_enable = smu_v13_0_5_dpm_set_jpeg_enable, .set_default_dpm_table = smu_v13_0_5_set_default_dpm_tables, @@ -1118,23 +1121,34 @@ static const struct pptable_funcs smu_v13_0_5_ppt_funcs = { .mode2_reset = smu_v13_0_5_mode2_reset, .get_dpm_ultimate_freq = smu_v13_0_5_get_dpm_ultimate_freq, .od_edit_dpm_table = smu_v13_0_5_od_edit_dpm_table, - .print_clk_levels = smu_v13_0_5_print_clk_levels, + .emit_clk_levels = smu_v13_0_5_emit_clk_levels, .force_clk_levels = smu_v13_0_5_force_clk_levels, .set_performance_level = smu_v13_0_5_set_performance_level, .set_fine_grain_gfx_freq_parameters = smu_v13_0_5_set_fine_grain_gfx_freq_parameters, }; -void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) +static void smu_v13_0_5_init_msg_ctl(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = smu_v13_0_5_message_map; +} +void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu) +{ smu->ppt_funcs = &smu_v13_0_5_ppt_funcs; - smu->message_map = smu_v13_0_5_message_map; smu->feature_map = smu_v13_0_5_feature_mask_map; smu->table_map = smu_v13_0_5_table_map; smu->is_apu = true; smu->smc_driver_if_version = SMU13_0_5_DRIVER_IF_VERSION; - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_34); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_2); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_C2PMSG_33); + smu_v13_0_5_init_msg_ctl(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 44e1cd821eec9..367a0b7dc4c08 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -76,15 +76,18 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin"); [smu_feature] = { 1, (smu_13_0_6_feature) } #define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE \ - (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \ - FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_UCLK) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK) | FEATURE_MASK(FEATURE_DPM_FCLK) | \ - FEATURE_MASK(FEATURE_DPM_LCLK) | FEATURE_MASK(FEATURE_DPM_XGMI) | \ - FEATURE_MASK(FEATURE_DPM_VCN)) - -/* possible frequency drift (1Mhz) */ -#define EPSILON 1 +static const struct smu_feature_bits smu_v13_0_6_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN) + } +}; #define smnPCIE_ESM_CTRL 0x93D0 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288 @@ -95,9 +98,7 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin"); #define smnPCIE_LC_SPEED_CNTL 0x1a340290 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5 -#define LINK_SPEED_MAX 4 -#define SMU_13_0_6_DSCLK_THRESHOLD 140 - +#define LINK_SPEED_MAX 4 #define MCA_BANK_IPID(_ip, _hwid, _type) \ [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, } @@ -178,6 +179,13 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), + MSG_MAP(SetPhsDetWRbwThreshold, PPSMC_MSG_SetPhsDetWRbwThreshold, 0), + MSG_MAP(SetPhsDetWRbwFreqHigh, PPSMC_MSG_SetPhsDetWRbwFreqHigh, 0), + MSG_MAP(SetPhsDetWRbwFreqLow, PPSMC_MSG_SetPhsDetWRbwFreqLow, 0), + MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), + MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), + MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), + MSG_MAP(GetPhsDetResidency, PPSMC_MSG_GetPhsDetResidency, 0), }; // clang-format on @@ -251,7 +259,7 @@ static const uint8_t smu_v13_0_6_throttler_map[] = { struct smu_v13_0_6_dpm_map { enum smu_clk_type clk_type; uint32_t feature_num; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; uint32_t *freq_table; }; @@ -356,8 +364,11 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) if (fw_ver > 0x04560900) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); - if (fw_ver >= 0x04560D00) + if (fw_ver >= 0x04560D00) { smu_v13_0_6_cap_set(smu, SMU_CAP(FAST_PPT)); + if (smu->adev->gmc.xgmi.physical_node_id == 0) + smu_v13_0_6_cap_set(smu, SMU_CAP(SYSTEM_POWER_METRICS)); + } if (fw_ver >= 0x04560700) { if (fw_ver >= 0x04560900) { @@ -369,6 +380,9 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu) } else { smu_v13_0_12_tables_fini(smu); } + + if (fw_ver >= 0x04561000) + smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_AID_XCD_HBM)); } static void smu_v13_0_6_init_caps(struct smu_context *smu) @@ -454,6 +468,7 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu) smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET)); if ((pgm == 0 && fw_ver >= 0x00558200) || + (pgm == 4 && fw_ver >= 0x04557100) || (pgm == 7 && fw_ver >= 0x07551400)) smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET)); } @@ -474,7 +489,7 @@ static int smu_v13_0_6_check_fw_version(struct smu_context *smu) { int r; - r = smu_v13_0_check_fw_version(smu); + r = smu_cmn_check_fw_version(smu); /* Initialize caps flags once fw version is fetched */ if (!r) smu_v13_0_x_init_caps(smu); @@ -586,20 +601,22 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) if (!driver_pptable) return -ENOMEM; - ret = smu_table_cache_init(smu, SMU_TABLE_SMU_METRICS, - sizeof(struct smu_v13_0_6_gpu_metrics), 1); + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct smu_v13_0_6_gpu_metrics), + SMU_GPU_METRICS_CACHE_INTERVAL); if (ret) return ret; - gpu_metrics = (struct smu_v13_0_6_gpu_metrics - *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); + gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); smu_v13_0_6_gpu_metrics_init(gpu_metrics, 1, 9); if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) { ret = smu_v13_0_12_tables_init(smu); if (ret) { - smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS); + smu_driver_table_fini(smu, + SMU_DRIVER_TABLE_GPU_METRICS); return ret; } } @@ -678,6 +695,132 @@ static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level) return ret; } +static int smu_v13_0_6_phase_det_set(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + uint32_t *param; + int r, msg_id; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqLow; + param = &pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqHigh; + param = &pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + msg_id = SMU_MSG_SetPhsDetWRbwThreshold; + param = &pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + msg_id = SMU_MSG_SetPhsDetWRbwAlpha; + param = &pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + msg_id = SMU_MSG_SetPhsDetWRbwHystDown; + param = &pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + r = smu_cmn_send_smc_msg_with_param(smu, msg_id, val, NULL); + if (!r) + *param = val; + + return r; +} + +static int smu_v13_0_6_phase_det_get(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t *val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl || !val) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + *val = pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + *val = pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + *val = pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + *val = pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + *val = pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + int r; + + pd_ctl = smu_dpm->pd_ctl; + r = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPhsDetOnOff, enable, + NULL); + + if (!r) { + pd_ctl->status = enable ? SMU_PHASE_DET_ON : SMU_PHASE_DET_OFF; + } else { + dev_warn(smu->adev->dev, "Phase detect %s failed", + enable ? "enable" : "disable"); + pd_ctl->status = SMU_PHASE_DET_DISABLED; + } + + return r; +} + +static int smu_v13_0_6_phase_det_get_residency(struct smu_context *smu, + uint32_t *res) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + + if (!res) + return -EINVAL; + + if (pd_ctl->status != SMU_PHASE_DET_ON) { + *res = 0; + return 0; + } + + return smu_cmn_send_smc_msg(smu, SMU_MSG_GetPhsDetResidency, res); +} + +static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { + .set = smu_v13_0_6_phase_det_set, + .get = smu_v13_0_6_phase_det_get, + .enable = smu_v13_0_6_phase_det_enable, + .get_residency = smu_v13_0_6_phase_det_get_residency, +}; + static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -696,6 +839,22 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) && + !(smu->adev->flags & AMD_IS_APU)) { + smu_dpm->pd_ctl = + kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, + sizeof(struct smu_phase_det_params)); + } if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -739,19 +898,12 @@ static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu) { if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) smu_v13_0_12_tables_fini(smu); - smu_table_cache_fini(smu, SMU_TABLE_SMU_METRICS); return smu_v13_0_fini_smc_tables(smu); } -static int smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, - uint32_t num) +static int smu_v13_0_6_init_allowed_features(struct smu_context *smu) { - if (num > 2) - return -EINVAL; - - /* pptable will handle the features to enable */ - memset(feature_mask, 0xFF, sizeof(uint32_t) * num); + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -777,6 +929,10 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table, amdgpu_hdp_invalidate(smu->adev, NULL); memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + if (!memchr_inv(smu_table->metrics_table, 0xff, + min(16, table_size))) + return -EHWPOISON; + smu_table->metrics_time = jiffies; } @@ -984,7 +1140,7 @@ static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu, struct smu_table_context *smu_table = &smu->smu_table; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; uint32_t min_clk, max_clk, param; int ret = 0, clk_id = 0; @@ -1015,9 +1171,8 @@ static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu, return -EINVAL; } - min_clk = dpm_table->min; - max_clk = dpm_table->max; - + min_clk = SMU_DPM_TABLE_MIN(dpm_table); + max_clk = SMU_DPM_TABLE_MAX(dpm_table); if (min) *min = min_clk; if (max) @@ -1087,7 +1242,8 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; struct smu_table_context *smu_table = &smu->smu_table; - struct smu_13_0_dpm_table *dpm_table = NULL; + struct smu_dpm_table *dpm_table = NULL; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; uint32_t gfxclkmin, gfxclkmax, levels; @@ -1120,9 +1276,19 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556E00)) { + kfree(smu_dpm->pd_ctl); + smu_dpm->pd_ctl = NULL; + } + + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556F78)) + smu_dpm->pd_ctl->ops->get_residency = NULL; + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { /* In the case of gfxclk, only fine-grained dpm is honored. * Get min/max values from FW. @@ -1131,20 +1297,15 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) &gfxclkmin, &gfxclkmax); if (ret) return ret; - dpm_table->count = 2; dpm_table->dpm_levels[0].value = gfxclkmin; dpm_table->dpm_levels[0].enabled = true; dpm_table->dpm_levels[1].value = gfxclkmax; dpm_table->dpm_levels[1].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[1].value; } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } for (j = 0; j < ARRAY_SIZE(dpm_map); j++) { @@ -1157,15 +1318,12 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) return ret; } dpm_table->count = levels; + dpm_table->clk_type = dpm_map[j].clk_type; for (i = 0; i < dpm_table->count; ++i) { dpm_table->dpm_levels[i].value = dpm_map[j].freq_table[i]; dpm_table->dpm_levels[i].enabled = true; - } - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[levels - 1].value; - } return 0; @@ -1202,28 +1360,32 @@ static int smu_v13_0_6_check_fw_status(struct smu_context *smu) static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_13_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_13_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; - pstate_table->gfxclk_pstate.min = gfx_table->min; - pstate_table->gfxclk_pstate.peak = gfx_table->max; - pstate_table->gfxclk_pstate.curr.min = gfx_table->min; - pstate_table->gfxclk_pstate.curr.max = gfx_table->max; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); + pstate_table->gfxclk_pstate.curr.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = SMU_DPM_TABLE_MAX(gfx_table); + + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); + pstate_table->uclk_pstate.curr.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.curr.max = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; - pstate_table->uclk_pstate.curr.min = mem_table->min; - pstate_table->uclk_pstate.curr.max = mem_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); + pstate_table->socclk_pstate.curr.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.curr.max = SMU_DPM_TABLE_MAX(soc_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; - pstate_table->socclk_pstate.curr.min = soc_table->min; - pstate_table->socclk_pstate.curr.max = soc_table->max; + pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table); + pstate_table->fclk_pstate.curr.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.curr.max = SMU_DPM_TABLE_MAX(fclk_table); + pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table); if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL && mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL && @@ -1246,31 +1408,6 @@ static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu) return 0; } -static int smu_v13_0_6_get_clk_table(struct smu_context *smu, - struct pp_clock_levels_with_latency *clocks, - struct smu_13_0_dpm_table *dpm_table) -{ - int i, count; - - count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : - dpm_table->count; - clocks->num_levels = count; - - for (i = 0; i < count; i++) { - clocks->data[i].clocks_in_khz = - dpm_table->dpm_levels[i].value * 1000; - clocks->data[i].latency_in_us = 0; - } - - return 0; -} - -static int smu_v13_0_6_freqs_in_same_level(int32_t frequency1, - int32_t frequency2) -{ - return (abs(frequency1 - frequency2) <= EPSILON); -} - static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu) { struct smu_power_context *smu_power = &smu->smu_power; @@ -1375,9 +1512,11 @@ static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu, switch (clk_type) { case SMU_GFXCLK: + case SMU_SCLK: member_type = METRICS_CURR_GFXCLK; break; case SMU_UCLK: + case SMU_MCLK: member_type = METRICS_CURR_UCLK; break; case SMU_SOCCLK: @@ -1399,74 +1538,20 @@ static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu, return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value); } -static int smu_v13_0_6_print_clks(struct smu_context *smu, char *buf, int size, - struct smu_13_0_dpm_table *single_dpm_table, - uint32_t curr_clk, const char *clk_name) +static int smu_v13_0_6_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type type, char *buf, + int *offset) { - struct pp_clock_levels_with_latency clocks; - int i, ret, level = -1; - uint32_t clk1, clk2; - - ret = smu_v13_0_6_get_clk_table(smu, &clocks, single_dpm_table); - if (ret) { - dev_err(smu->adev->dev, "Attempt to get %s clk levels failed!", - clk_name); - return ret; - } - - if (!clocks.num_levels) - return -EINVAL; - - if (curr_clk < SMU_13_0_6_DSCLK_THRESHOLD) { - size += sysfs_emit_at(buf, size, "S: %uMhz *\n", curr_clk); - for (i = 0; i < clocks.num_levels; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz\n", i, - clocks.data[i].clocks_in_khz / - 1000); - - } else { - if ((clocks.num_levels == 1) || - (curr_clk < (clocks.data[0].clocks_in_khz / 1000))) - level = 0; - for (i = 0; i < clocks.num_levels; i++) { - clk1 = clocks.data[i].clocks_in_khz / 1000; - - if (i < (clocks.num_levels - 1)) - clk2 = clocks.data[i + 1].clocks_in_khz / 1000; - - if (curr_clk == clk1) { - level = i; - } else if (curr_clk >= clk1 && curr_clk < clk2) { - level = (curr_clk - clk1) <= (clk2 - curr_clk) ? - i : - i + 1; - } - - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, - clk1, (level == i) ? "*" : ""); - } - } - - return size; -} - -static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, - enum smu_clk_type type, char *buf) -{ - int now, size = 0, start_offset = 0; + int now, size = *offset, start_offset = *offset; int ret = 0; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; - struct smu_13_0_dpm_table *single_dpm_table; + struct smu_dpm_table *single_dpm_table = NULL; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = NULL; - uint32_t min_clk, max_clk; - - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; if (amdgpu_ras_intr_triggered()) { - size += sysfs_emit_at(buf, size, "unavailable\n"); - return size - start_offset; + sysfs_emit_at(buf, size, "unavailable\n"); + return -EBUSY; } dpm_context = smu_dpm->dpm_context; @@ -1478,150 +1563,63 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu, pstate_table->gfxclk_pstate.curr.min, pstate_table->gfxclk_pstate.curr.max); break; - case SMU_SCLK: - ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_GFXCLK, - &now); - if (ret) { - dev_err(smu->adev->dev, - "Attempt to get current gfx clk Failed!"); - return ret; - } - - single_dpm_table = &(dpm_context->dpm_tables.gfx_table); - min_clk = single_dpm_table->min; - max_clk = single_dpm_table->max; - - if (now < SMU_13_0_6_DSCLK_THRESHOLD) { - size += sysfs_emit_at(buf, size, "S: %uMhz *\n", - now); - size += sysfs_emit_at(buf, size, "0: %uMhz\n", - min_clk); - size += sysfs_emit_at(buf, size, "1: %uMhz\n", - max_clk); - - } else if (!smu_v13_0_6_freqs_in_same_level(now, min_clk) && - !smu_v13_0_6_freqs_in_same_level(now, max_clk)) { - size += sysfs_emit_at(buf, size, "0: %uMhz\n", - min_clk); - size += sysfs_emit_at(buf, size, "1: %uMhz *\n", - now); - size += sysfs_emit_at(buf, size, "2: %uMhz\n", - max_clk); - } else { - size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", - min_clk, - smu_v13_0_6_freqs_in_same_level(now, min_clk) ? "*" : ""); - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", - max_clk, - smu_v13_0_6_freqs_in_same_level(now, max_clk) ? "*" : ""); - } - - break; - case SMU_OD_MCLK: if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX))) - return 0; + return -EOPNOTSUPP; size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", pstate_table->uclk_pstate.curr.min, pstate_table->uclk_pstate.curr.max); break; - case SMU_MCLK: - ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_UCLK, - &now); - if (ret) { - dev_err(smu->adev->dev, - "Attempt to get current mclk Failed!"); - return ret; - } + case SMU_OD_FCLK: + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) + return -EOPNOTSUPP; + size += sysfs_emit_at(buf, size, "%s:\n", "OD_FCLK"); + size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", + pstate_table->fclk_pstate.curr.min, + pstate_table->fclk_pstate.curr.max); + break; + case SMU_SCLK: + case SMU_GFXCLK: + single_dpm_table = &(dpm_context->dpm_tables.gfx_table); + break; + case SMU_MCLK: + case SMU_UCLK: single_dpm_table = &(dpm_context->dpm_tables.uclk_table); - - ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "mclk"); - if (ret < 0) - return ret; - - size += ret; break; case SMU_SOCCLK: - ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_SOCCLK, - &now); - if (ret) { - dev_err(smu->adev->dev, - "Attempt to get current socclk Failed!"); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.soc_table); - - ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "socclk"); - if (ret < 0) - return ret; - - size += ret; break; case SMU_FCLK: - ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_FCLK, - &now); - if (ret) { - dev_err(smu->adev->dev, - "Attempt to get current fclk Failed!"); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.fclk_table); - - ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "fclk"); - if (ret < 0) - return ret; - - size += ret; break; case SMU_VCLK: - ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_VCLK, - &now); - if (ret) { - dev_err(smu->adev->dev, - "Attempt to get current vclk Failed!"); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.vclk_table); - - ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "vclk"); - if (ret < 0) - return ret; - - size += ret; break; case SMU_DCLK: - ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, SMU_DCLK, - &now); - if (ret) { - dev_err(smu->adev->dev, - "Attempt to get current dclk Failed!"); - return ret; - } - single_dpm_table = &(dpm_context->dpm_tables.dclk_table); - - ret = smu_v13_0_6_print_clks(smu, buf, size, single_dpm_table, - now, "dclk"); - if (ret < 0) - return ret; - - size += ret; break; default: break; } - return size - start_offset; + if (single_dpm_table) { + ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, type, + &now); + if (ret) { + dev_err(smu->adev->dev, + "Attempt to get current clk Failed!"); + return ret; + } + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, now, + buf, offset); + } + + *offset += size - start_offset; + + return 0; } static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max, @@ -1687,7 +1685,7 @@ static int smu_v13_0_6_force_clk_levels(struct smu_context *smu, enum smu_clk_type type, uint32_t mask) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *single_dpm_table = NULL; + struct smu_dpm_table *single_dpm_table = NULL; uint32_t soft_min_level, soft_max_level; int ret = 0; @@ -1860,6 +1858,13 @@ static int smu_v13_0_6_read_sensor(struct smu_context *smu, return ret; *size = 4; break; + case AMDGPU_PP_SENSOR_UBB_POWER: + case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT: + ret = smu_v13_0_12_get_system_power(smu, sensor, (uint32_t *)data); + if (ret) + return ret; + *size = 4; + break; case AMDGPU_PP_SENSOR_GPU_AVG_POWER: default: ret = -EOPNOTSUPP; @@ -2146,10 +2151,8 @@ static int smu_v13_0_6_set_performance_level(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_13_0_dpm_table *uclk_table = - &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; int ret; @@ -2157,7 +2160,8 @@ static int smu_v13_0_6_set_performance_level(struct smu_context *smu, if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) { smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL); - pstate_table->gfxclk_pstate.curr.max = gfx_table->max; + pstate_table->gfxclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(gfx_table); } switch (level) { @@ -2165,24 +2169,32 @@ static int smu_v13_0_6_set_performance_level(struct smu_context *smu, return 0; case AMD_DPM_FORCED_LEVEL_AUTO: - if ((gfx_table->min != pstate_table->gfxclk_pstate.curr.min) || - (gfx_table->max != pstate_table->gfxclk_pstate.curr.max)) { + if ((SMU_DPM_TABLE_MIN(gfx_table) != + pstate_table->gfxclk_pstate.curr.min) || + (SMU_DPM_TABLE_MAX(gfx_table) != + pstate_table->gfxclk_pstate.curr.max)) { ret = smu_v13_0_6_set_gfx_soft_freq_limited_range( - smu, gfx_table->min, gfx_table->max); + smu, SMU_DPM_TABLE_MIN(gfx_table), + SMU_DPM_TABLE_MAX(gfx_table)); if (ret) return ret; - pstate_table->gfxclk_pstate.curr.min = gfx_table->min; - pstate_table->gfxclk_pstate.curr.max = gfx_table->max; + pstate_table->gfxclk_pstate.curr.min = + SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(gfx_table); } - if (uclk_table->max != pstate_table->uclk_pstate.curr.max) { + if (SMU_DPM_TABLE_MAX(uclk_table) != + pstate_table->uclk_pstate.curr.max) { /* Min UCLK is not expected to be changed */ ret = smu_v13_0_set_soft_freq_limited_range( - smu, SMU_UCLK, 0, uclk_table->max, false); + smu, SMU_UCLK, 0, SMU_DPM_TABLE_MAX(uclk_table), + false); if (ret) return ret; - pstate_table->uclk_pstate.curr.max = uclk_table->max; + pstate_table->uclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(uclk_table); } smu_v13_0_reset_custom_level(smu); @@ -2210,7 +2222,7 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, int ret = 0; if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK && - clk_type != SMU_UCLK) + clk_type != SMU_UCLK && clk_type != SMU_FCLK) return -EINVAL; if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) && @@ -2251,12 +2263,22 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, pstate_table->uclk_pstate.curr.max = max; } + if (clk_type == SMU_FCLK) { + if (max == pstate_table->fclk_pstate.curr.max) + return 0; + + ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_FCLK, 0, max, false); + if (!ret) + pstate_table->fclk_pstate.curr.max = max; + } + return ret; } if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { - if (!max || (max < dpm_context->dpm_tables.gfx_table.min) || - (max > dpm_context->dpm_tables.gfx_table.max)) { + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); + if (!max || (max < min_clk) || (max > max_clk)) { dev_warn( adev->dev, "Invalid max frequency %d MHz specified for determinism\n", @@ -2265,10 +2287,8 @@ static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu, } /* Restore default min/max clocks and enable determinism */ - min_clk = dpm_context->dpm_tables.gfx_table.min; - max_clk = dpm_context->dpm_tables.gfx_table.max; ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk, - max_clk); + max_clk); if (!ret) { usleep_range(500, 1000); ret = smu_cmn_send_smc_msg_with_param( @@ -2293,6 +2313,8 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; uint32_t min_clk; uint32_t max_clk; @@ -2310,14 +2332,14 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, "Input parameter number not correct\n"); return -EINVAL; } - + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); if (input[0] == 0) { - if (input[1] < dpm_context->dpm_tables.gfx_table.min) { + if (input[1] < min_clk) { dev_warn( smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", - input[1], - dpm_context->dpm_tables.gfx_table.min); + input[1], min_clk); pstate_table->gfxclk_pstate.custom.min = pstate_table->gfxclk_pstate.curr.min; return -EINVAL; @@ -2325,12 +2347,11 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, pstate_table->gfxclk_pstate.custom.min = input[1]; } else if (input[0] == 1) { - if (input[1] > dpm_context->dpm_tables.gfx_table.max) { + if (input[1] > max_clk) { dev_warn( smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", - input[1], - dpm_context->dpm_tables.gfx_table.max); + input[1], max_clk); pstate_table->gfxclk_pstate.custom.max = pstate_table->gfxclk_pstate.curr.max; return -EINVAL; @@ -2354,18 +2375,18 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, "UCLK_LIMITS setting not supported!\n"); return -EOPNOTSUPP; } - + max_clk = + SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); if (input[0] == 0) { dev_info(smu->adev->dev, "Setting min UCLK level is not supported"); return -EINVAL; } else if (input[0] == 1) { - if (input[1] > dpm_context->dpm_tables.uclk_table.max) { + if (input[1] > max_clk) { dev_warn( smu->adev->dev, "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", - input[1], - dpm_context->dpm_tables.uclk_table.max); + input[1], max_clk); pstate_table->uclk_pstate.custom.max = pstate_table->uclk_pstate.curr.max; return -EINVAL; @@ -2374,6 +2395,40 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, pstate_table->uclk_pstate.custom.max = input[1]; } break; + case PP_OD_EDIT_FCLK_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + if (!smu_cmn_feature_is_enabled(smu, + SMU_FEATURE_DPM_FCLK_BIT)) { + dev_warn(smu->adev->dev, + "FCLK limits setting not supported!\n"); + return -EOPNOTSUPP; + } + + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table); + if (input[0] == 0) { + dev_info(smu->adev->dev, + "Setting min FCLK level is not supported\n"); + return -EOPNOTSUPP; + } else if (input[0] == 1) { + if (input[1] > max_clk) { + dev_warn(smu->adev->dev, + "Maximum FCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); + pstate_table->fclk_pstate.custom.max = + pstate_table->fclk_pstate.curr.max; + return -EINVAL; + } + + pstate_table->fclk_pstate.custom.max = input[1]; + } else { + return -EINVAL; + } + break; case PP_OD_RESTORE_DEFAULT_TABLE: if (size != 0) { @@ -2382,8 +2437,10 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, return -EINVAL; } else { /* Use the default frequencies for manual and determinism mode */ - min_clk = dpm_context->dpm_tables.gfx_table.min; - max_clk = dpm_context->dpm_tables.gfx_table.max; + min_clk = SMU_DPM_TABLE_MIN( + &dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX( + &dpm_context->dpm_tables.gfx_table); ret = smu_v13_0_6_set_soft_freq_limited_range( smu, SMU_GFXCLK, min_clk, max_clk, false); @@ -2391,12 +2448,27 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, if (ret) return ret; - min_clk = dpm_context->dpm_tables.uclk_table.min; - max_clk = dpm_context->dpm_tables.uclk_table.max; - ret = smu_v13_0_6_set_soft_freq_limited_range( - smu, SMU_UCLK, min_clk, max_clk, false); - if (ret) - return ret; + if (SMU_DPM_TABLE_MAX(uclk_table) != + pstate_table->uclk_pstate.curr.max) { + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, + SMU_UCLK, min_clk, + max_clk, false); + if (ret) + return ret; + } + + if (SMU_DPM_TABLE_MAX(fclk_table) != + pstate_table->fclk_pstate.curr.max) { + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table); + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.fclk_table); + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, + SMU_FCLK, min_clk, + max_clk, false); + if (ret) + return ret; + } smu_v13_0_reset_custom_level(smu); } break; @@ -2423,6 +2495,16 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, if (ret) return ret; + if (pstate_table->fclk_pstate.custom.max) { + min_clk = pstate_table->fclk_pstate.curr.min; + max_clk = pstate_table->fclk_pstate.custom.max; + ret = smu_v13_0_6_set_soft_freq_limited_range(smu, + SMU_FCLK, min_clk, + max_clk, false); + if (ret) + return ret; + } + if (!pstate_table->uclk_pstate.custom.max) return 0; @@ -2440,14 +2522,14 @@ static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu, } static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { int ret; ret = smu_cmn_get_enabled_mask(smu, feature_mask); if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) { - *feature_mask = 0; + smu_feature_bits_clearall(feature_mask); ret = 0; } @@ -2457,7 +2539,7 @@ static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu, static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) { int ret; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) return smu_v13_0_12_is_dpm_running(smu); @@ -2467,7 +2549,8 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu) if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_6_dpm_features.bits); } static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu, @@ -2731,9 +2814,10 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3; int version = smu_v13_0_6_get_metrics_version(smu); struct smu_v13_0_6_partition_metrics *xcp_metrics; - MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; + struct smu_table_context *smu_table = &smu->smu_table; struct amdgpu_device *adev = smu->adev; int ret, inst, i, j, k, idx; + MetricsTableV0_t *metrics_v0; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; struct amdgpu_xcp *xcp; @@ -2753,22 +2837,20 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table; smu_v13_0_6_partition_metrics_init(xcp_metrics, 1, 1); - metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); - if (!metrics_v0) - return -ENOMEM; - - ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); + ret = smu_v13_0_6_get_metrics_table(smu, NULL, false); if (ret) return ret; + metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table; + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) return smu_v13_0_12_get_xcp_metrics(smu, xcp, table, metrics_v0); - metrics_v1 = (MetricsTableV1_t *)metrics_v0; - metrics_v2 = (MetricsTableV2_t *)metrics_v0; + metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table; + metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table; per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS)); @@ -2836,33 +2918,33 @@ static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id, idx++; } } + xcp_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version); + xcp_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); return sizeof(*xcp_metrics); } static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; - struct smu_table *tables = smu_table->tables; struct smu_v13_0_6_gpu_metrics *gpu_metrics; int version = smu_v13_0_6_get_metrics_version(smu); - MetricsTableV0_t *metrics_v0 __free(kfree) = NULL; + struct smu_table_context *smu_table = &smu->smu_table; struct amdgpu_device *adev = smu->adev; int ret = 0, xcc_id, inst, i, j; + MetricsTableV0_t *metrics_v0; MetricsTableV1_t *metrics_v1; MetricsTableV2_t *metrics_v2; u16 link_width_level; u8 num_jpeg_rings; bool per_inst; - metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL); - ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false); + ret = smu_v13_0_6_get_metrics_table(smu, NULL, false); if (ret) return ret; - metrics_v2 = (MetricsTableV2_t *)metrics_v0; - gpu_metrics = (struct smu_v13_0_6_gpu_metrics - *)(tables[SMU_TABLE_SMU_METRICS].cache.buffer); + metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table; + gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) && smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) { @@ -2871,8 +2953,8 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table goto fill; } - metrics_v1 = (MetricsTableV1_t *)metrics_v0; - metrics_v2 = (MetricsTableV2_t *)metrics_v0; + metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table; + metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table; gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)); @@ -3047,7 +3129,9 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version); fill: - *table = tables[SMU_TABLE_SMU_METRICS].cache.buffer; + *table = gpu_metrics; + + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); return sizeof(*gpu_metrics); } @@ -3065,24 +3149,22 @@ static void smu_v13_0_6_restore_pci_config(struct smu_context *smu) static int smu_v13_0_6_mode2_reset(struct smu_context *smu) { - int ret = 0, index; + struct smu_msg_ctl *ctl = &smu->msg_ctl; struct amdgpu_device *adev = smu->adev; + int ret = 0; int timeout = 10; - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, - SMU_MSG_GfxDeviceDriverReset); - if (index < 0) - return index; - - mutex_lock(&smu->message_lock); + mutex_lock(&ctl->lock); - ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, - SMU_RESET_MODE_2); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, + SMU_RESET_MODE_2); + if (ret) + goto out; /* Reset takes a bit longer, wait for 200ms. */ msleep(200); - dev_dbg(smu->adev->dev, "restore config space...\n"); + dev_dbg(adev->dev, "restore config space...\n"); /* Restore the config space saved during init */ amdgpu_device_load_pci_state(adev->pdev); @@ -3100,9 +3182,9 @@ static int smu_v13_0_6_mode2_reset(struct smu_context *smu) if (!(adev->flags & AMD_IS_APU)) smu_v13_0_6_restore_pci_config(smu); - dev_dbg(smu->adev->dev, "wait for reset ack\n"); + dev_dbg(adev->dev, "wait for reset ack\n"); do { - ret = smu_cmn_wait_for_response(smu); + ret = smu_msg_wait_response(ctl, 0); /* Wait a bit more time for getting ACK */ if (ret == -ETIME) { --timeout; @@ -3116,7 +3198,7 @@ static int smu_v13_0_6_mode2_reset(struct smu_context *smu) } while (ret == -ETIME && timeout); out: - mutex_unlock(&smu->message_lock); + mutex_unlock(&ctl->lock); if (ret) dev_err(adev->dev, "failed to send mode2 reset, error code %d", @@ -3314,6 +3396,32 @@ static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu) return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET)); } +static int smu_v13_0_6_post_init(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + bool enable; + + if (smu_v13_0_6_is_link_reset_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET); + + if (smu_v13_0_6_reset_sdma_is_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); + + if (smu_v13_0_6_reset_vcn_is_supported(smu)) + smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET); + + pd_ctl = smu_dpm->pd_ctl; + + if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) + return 0; + + enable = (pd_ctl->status == SMU_PHASE_DET_ON) ? true : false; + smu_v13_0_6_phase_det_enable(smu, enable); + + return 0; +} + static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) { int ret = 0; @@ -3328,14 +3436,25 @@ static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask) static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg) { + struct amdgpu_device *adev = smu->adev; int ret; + if (amdgpu_sriov_vf(adev)) + return -EOPNOTSUPP; + switch (msg) { case SMU_MSG_QueryValidMcaCount: case SMU_MSG_QueryValidMcaCeCount: case SMU_MSG_McaBankDumpDW: case SMU_MSG_McaBankCeDumpDW: case SMU_MSG_ClearMcaOnRead: + case SMU_MSG_GetRASTableVersion: + case SMU_MSG_GetBadPageCount: + case SMU_MSG_GetBadPageMcaAddr: + case SMU_MSG_SetTimestamp: + case SMU_MSG_GetTimestamp: + case SMU_MSG_GetBadPageIpid: + case SMU_MSG_EraseRasTable: ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg); break; default: @@ -3345,20 +3464,6 @@ static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_ty return ret; } -static int smu_v13_0_6_post_init(struct smu_context *smu) -{ - if (smu_v13_0_6_is_link_reset_supported(smu)) - smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET); - - if (smu_v13_0_6_reset_sdma_is_supported(smu)) - smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET); - - if (smu_v13_0_6_reset_vcn_is_supported(smu)) - smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET); - - return 0; -} - static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) { struct smu_context *smu = adev->powerplay.pp_handle; @@ -4006,11 +4111,11 @@ static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { /* init dpm */ - .get_allowed_feature_mask = smu_v13_0_6_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_6_init_allowed_features, /* dpm/clk tables */ .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table, .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk, - .print_clk_levels = smu_v13_0_6_print_clk_levels, + .emit_clk_levels = smu_v13_0_6_emit_clk_levels, .force_clk_levels = smu_v13_0_6_force_clk_levels, .read_sensor = smu_v13_0_6_read_sensor, .set_performance_level = smu_v13_0_6_set_performance_level, @@ -4030,8 +4135,6 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .set_tool_table_location = smu_v13_0_set_tool_table_location, .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location, .system_features_control = smu_v13_0_6_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .get_enabled_mask = smu_v13_0_6_get_enabled_mask, .feature_is_enabled = smu_cmn_feature_is_enabled, .set_power_limit = smu_v13_0_6_set_power_limit, @@ -4069,8 +4172,10 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) { + const struct cmn2asic_msg_mapping *message_map; + smu->ppt_funcs = &smu_v13_0_6_ppt_funcs; - smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? + message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? smu_v13_0_12_message_map : smu_v13_0_6_message_map; smu->clock_map = smu_v13_0_6_clk_map; smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? @@ -4078,7 +4183,7 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) smu->table_map = smu_v13_0_6_table_map; smu->smc_driver_if_version = SMU_IGNORE_IF_VERSION; smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI; - smu_v13_0_set_smu_mailbox_registers(smu); + smu_v13_0_init_msg_ctl(smu, message_map); smu_v13_0_6_set_temp_funcs(smu); amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs); amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h index 6cbdd7c5ded9b..a150fc88902c4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h @@ -77,6 +77,8 @@ enum smu_v13_0_6_caps { SMU_CAP(NPM_METRICS), SMU_CAP(RAS_EEPROM), SMU_CAP(FAST_PPT), + SMU_CAP(SYSTEM_POWER_METRICS), + SMU_CAP(TEMP_AID_XCD_HBM), SMU_CAP(ALL), }; @@ -86,6 +88,8 @@ enum smu_v13_0_6_caps { #define SMU_13_0_6_MAX_XCC 8 #define SMU_13_0_6_MAX_VCN 4 #define SMU_13_0_6_MAX_JPEG 40 +#define SMU_13_0_6_MAX_AID 4 +#define SMU_13_0_6_MAX_HBM_STACKS 8 extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu); bool smu_v13_0_6_cap_supported(struct smu_context *smu, enum smu_v13_0_6_caps cap); @@ -107,6 +111,9 @@ void smu_v13_0_12_tables_fini(struct smu_context *smu); int smu_v13_0_12_get_npm_data(struct smu_context *smu, enum amd_pp_sensors sensor, uint32_t *value); +int smu_v13_0_12_get_system_power(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value); extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[]; extern const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[]; extern const struct smu_temp_funcs smu_v13_0_12_temp_funcs; @@ -136,7 +143,7 @@ extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ SMU_MTYPE(U64), system_clock_counter); \ SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ - SMU_MTYPE(U32), accumulation_counter); \ + SMU_MTYPE(U64), accumulation_counter); \ SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ SMU_MTYPE(U32), prochot_residency_acc); \ SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ @@ -218,7 +225,15 @@ extern const struct ras_smu_drv smu_v13_0_12_ras_smu_drv; SMU_13_0_6_MAX_XCC); \ SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ - SMU_13_0_6_MAX_XCC); + SMU_13_0_6_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_HBM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hbm, \ + SMU_13_0_6_MAX_HBM_STACKS); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_AID), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_aid, SMU_13_0_6_MAX_AID); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_XCD), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_xcd, SMU_13_0_6_MAX_XCC); \ + DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_gpu_metrics, SMU_13_0_6_METRICS_FIELDS); void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, @@ -255,7 +270,11 @@ void smu_v13_0_12_get_gpu_metrics(struct smu_context *smu, void **table, SMU_13_0_6_MAX_XCC); \ SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ - SMU_13_0_6_MAX_XCC); + SMU_13_0_6_MAX_XCC); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); DECLARE_SMU_METRICS_CLASS(smu_v13_0_6_partition_metrics, SMU_13_0_6_PARTITION_METRICS_FIELDS); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index a3fc35b9011e4..3ad756e141740 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -59,19 +59,36 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)) +static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu, + int od_feature_bit, + int32_t *min, int32_t *max); + +static const struct smu_feature_bits smu_v13_0_7_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_MP0CLK_BIT) + } +}; #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 +#define mmMP1_SMN_C2PMSG_75 0x028b +#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_53 0x0275 +#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 + +#define mmMP1_SMN_C2PMSG_54 0x0276 +#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 + +#define DEBUGSMC_MSG_Mode1Reset 2 + #define PP_OD_FEATURE_GFXCLK_FMIN 0 #define PP_OD_FEATURE_GFXCLK_FMAX 1 #define PP_OD_FEATURE_UCLK_FMIN 2 @@ -265,71 +282,67 @@ static const uint8_t smu_v13_0_7_throttler_map[] = { }; static int -smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +smu_v13_0_7_init_allowed_features(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - if (num > 2) - return -EINVAL; + smu_feature_list_clear_all(smu, SMU_FEATURE_LIST_ALLOWED); - memset(feature_mask, 0, sizeof(uint32_t) * num); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DATA_READ_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_IMU_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); } if (adev->pm.pp_feature & PP_GFXOFF_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXOFF_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_UCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VMEMP_SCALING_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VDDIO_MEM_SCALING_BIT); } - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_SOCCLK_BIT); if (adev->pm.pp_feature & PP_PCIE_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_LINK_BIT); if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_GFXCLK_BIT); if (adev->pm.pp_feature & PP_ULV_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); - - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_ULV_BIT); + + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_LCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_MP0CLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MM_DPM_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_VCN_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_FCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DF_CSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_THROTTLERS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_VR0HOT_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_CTF_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FAN_CONTROL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DS_SOCCLK_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_MEM_TEMP_READ_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_FW_DSTATE_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_MPCLK_DS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_MPCLK_DS_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_GFX_PCC_DFLL_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_SOC_CG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_BACO_BIT); if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_DPM_DCN_BIT); if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) && (adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); + smu_feature_list_set_bit(smu, SMU_FEATURE_LIST_ALLOWED, FEATURE_ATHUB_MMHUB_PG_BIT); return 0; } @@ -497,6 +510,7 @@ static int smu_v13_0_7_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -525,9 +539,10 @@ static int smu_v13_0_7_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); @@ -537,7 +552,7 @@ static int smu_v13_0_7_tables_init(struct smu_context *smu) return 0; err2_out: - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); err1_out: kfree(smu_table->metrics_table); err0_out: @@ -578,11 +593,12 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; PPTable_t *driver_ppt = smu->smu_table.driver_pptable; SkuTable_t *skutable = &driver_ppt->SkuTable; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; int ret = 0; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_SOCCLK, @@ -593,12 +609,11 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_GFXCLK, @@ -611,18 +626,16 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) skutable->DriverReportedClocks.GameClockAc)) { dpm_table->dpm_levels[dpm_table->count - 1].value = skutable->DriverReportedClocks.GameClockAc; - dpm_table->max = skutable->DriverReportedClocks.GameClockAc; } } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* uclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_UCLK, @@ -633,12 +646,11 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* fclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_FCLK, @@ -649,12 +661,11 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* vclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = SMU_VCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_VCLK, @@ -665,12 +676,11 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = SMU_DCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_DCLK, @@ -681,12 +691,11 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dcefclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dcef_table; + dpm_table->clk_type = SMU_DCEFCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) { ret = smu_v13_0_set_single_dpm_table(smu, SMU_DCEFCLK, @@ -697,8 +706,6 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } return 0; @@ -707,13 +714,14 @@ static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu) static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v13_0_7_dpm_features.bits); } static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics) @@ -865,7 +873,7 @@ static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu, { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; switch (clk_type) { case SMU_MCLK: @@ -902,9 +910,9 @@ static int smu_v13_0_7_get_dpm_ultimate_freq(struct smu_context *smu, } if (min) - *min = dpm_table->min; + *min = SMU_DPM_TABLE_MIN(dpm_table); if (max) - *max = dpm_table->max; + *max = SMU_DPM_TABLE_MAX(dpm_table); return 0; } @@ -1050,8 +1058,35 @@ static bool smu_v13_0_7_is_od_feature_supported(struct smu_context *smu, PPTable_t *pptable = smu->smu_table.driver_pptable; const OverDriveLimits_t * const overdrive_upperlimits = &pptable->SkuTable.OverDriveLimitsBasicMax; + int32_t min_value, max_value; + bool feature_enabled; + + switch (od_feature_bit) { + case PP_OD_FEATURE_FAN_CURVE_BIT: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + if (feature_enabled) { + smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + + smu_v13_0_7_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + } + break; + default: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + break; + } - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); +out: + return feature_enabled; } static void smu_v13_0_7_get_od_setting_limits(struct smu_context *smu, @@ -1173,27 +1208,24 @@ static int smu_v13_0_7_upload_overdrive_table(struct smu_context *smu, return ret; } -static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, - char *buf) +static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; OverDriveTableExternal_t *od_table = (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; - struct smu_13_0_dpm_table *single_dpm_table; - struct smu_13_0_pcie_table *pcie_table; + int i, curr_freq, size = *offset, start_offset = *offset; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - int i, curr_freq, size = 0, start_offset = 0; int32_t min_value, max_value; int ret = 0; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - if (amdgpu_ras_intr_triggered()) { - size += sysfs_emit_at(buf, size, "unavailable\n"); - return size - start_offset; + sysfs_emit_at(buf, size, "unavailable\n"); + return -EBUSY; } switch (clk_type) { @@ -1220,61 +1252,6 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, case SMU_DCEFCLK: single_dpm_table = &(dpm_context->dpm_tables.dcef_table); break; - default: - break; - } - - switch (clk_type) { - case SMU_SCLK: - case SMU_MCLK: - case SMU_SOCCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_VCLK1: - case SMU_DCLK: - case SMU_DCLK1: - case SMU_DCEFCLK: - ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); - if (ret) { - dev_err(smu->adev->dev, "Failed to get current clock freq!"); - return ret; - } - - if (single_dpm_table->is_fine_grained) { - /* - * For fine grained dpms, there are only two dpm levels: - * - level 0 -> min clock freq - * - level 1 -> max clock freq - * And the current clock frequency can be any value between them. - * So, if the current clock frequency is not at level 0 or level 1, - * we will fake it as three dpm levels: - * - level 0 -> min clock freq - * - level 1 -> current actual clock freq - * - level 2 -> max clock freq - */ - if ((single_dpm_table->dpm_levels[0].value != curr_freq) && - (single_dpm_table->dpm_levels[1].value != curr_freq)) { - size += sysfs_emit_at(buf, size, "0: %uMhz\n", - single_dpm_table->dpm_levels[0].value); - size += sysfs_emit_at(buf, size, "1: %uMhz *\n", - curr_freq); - size += sysfs_emit_at(buf, size, "2: %uMhz\n", - single_dpm_table->dpm_levels[1].value); - } else { - size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", - single_dpm_table->dpm_levels[0].value, - single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", - single_dpm_table->dpm_levels[1].value, - single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); - } - } else { - for (i = 0; i < single_dpm_table->count; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", - i, single_dpm_table->dpm_levels[i].value, - single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); - } - break; case SMU_PCIE: ret = smu_v13_0_7_get_smu_metrics_data(smu, METRICS_PCIE_RATE, @@ -1289,24 +1266,10 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, return ret; pcie_table = &(dpm_context->dpm_tables.pcie_table); - for (i = 0; i < pcie_table->num_of_link_levels; i++) - size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : - (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", - (pcie_table->pcie_lane[i] == 1) ? "x1" : - (pcie_table->pcie_lane[i] == 2) ? "x2" : - (pcie_table->pcie_lane[i] == 3) ? "x4" : - (pcie_table->pcie_lane[i] == 4) ? "x8" : - (pcie_table->pcie_lane[i] == 5) ? "x12" : - (pcie_table->pcie_lane[i] == 6) ? "x16" : "", - pcie_table->clk_freq[i], - (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && - (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? - "*" : ""); - break; - + return smu_cmn_print_pcie_levels(smu, pcie_table, + SMU_DPM_PCIE_GEN_IDX(gen_speed), + SMU_DPM_PCIE_WIDTH_IDX(lane_width), + buf, offset); case SMU_OD_SCLK: if (!smu_v13_0_7_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT)) @@ -1524,7 +1487,21 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + if (single_dpm_table) { + ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, + &curr_freq); + if (ret) { + dev_err(smu->adev->dev, + "Failed to get current clock freq!"); + return ret; + } + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + curr_freq, buf, offset); + } + + *offset += size - start_offset; + + return 0; } static int smu_v13_0_7_od_restore_table_single(struct smu_context *smu, long input) @@ -1978,7 +1955,7 @@ static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context; - struct smu_13_0_dpm_table *single_dpm_table; + struct smu_dpm_table *single_dpm_table; uint32_t soft_min_level, soft_max_level; uint32_t min_freq, max_freq; int ret = 0; @@ -2024,7 +2001,7 @@ static int smu_v13_0_7_force_clk_levels(struct smu_context *smu, case SMU_VCLK1: case SMU_DCLK: case SMU_DCLK1: - if (single_dpm_table->is_fine_grained) { + if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) { /* There is only 2 levels for fine grained DPM */ soft_max_level = (soft_max_level >= 1 ? 1 : 0); soft_min_level = (soft_min_level >= 1 ? 1 : 0); @@ -2091,9 +2068,9 @@ static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu, static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetricsExternal_t metrics_ext; SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; int ret = 0; @@ -2120,7 +2097,8 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, metrics->Vcn1ActivityPercentage); gpu_metrics->average_socket_power = metrics->AverageSocketPower; - gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; + gpu_metrics->energy_accumulator = smu->smc_fw_version <= 0x00521400 ? + metrics->EnergyAccumulator : UINT_MAX; if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD) gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; @@ -2167,6 +2145,8 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -2276,7 +2256,8 @@ static int smu_v13_0_7_restore_user_od_settings(struct smu_context *smu) user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | BIT(PP_OD_FEATURE_UCLK_BIT) | BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); res = smu_v13_0_7_upload_overdrive_table(smu, user_od_table); user_od_table->OverDriveTable.FeatureCtrlMask = 0; if (res == 0) @@ -2289,18 +2270,12 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_13_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_13_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; - struct smu_13_0_dpm_table *vclk_table = - &dpm_context->dpm_tables.vclk_table; - struct smu_13_0_dpm_table *dclk_table = - &dpm_context->dpm_tables.dclk_table; - struct smu_13_0_dpm_table *fclk_table = - &dpm_context->dpm_tables.fclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct smu_table_context *table_context = &smu->smu_table; @@ -2308,38 +2283,39 @@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu) DriverReportedClocks_t driver_clocks = pptable->SkuTable.DriverReportedClocks; - pstate_table->gfxclk_pstate.min = gfx_table->min; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); if (driver_clocks.GameClockAc && - (driver_clocks.GameClockAc < gfx_table->max)) + (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table))) pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; else - pstate_table->gfxclk_pstate.peak = gfx_table->max; + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); - pstate_table->vclk_pstate.min = vclk_table->min; - pstate_table->vclk_pstate.peak = vclk_table->max; + pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table); + pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table); - pstate_table->dclk_pstate.min = dclk_table->min; - pstate_table->dclk_pstate.peak = dclk_table->max; + pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table); + pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table); - pstate_table->fclk_pstate.min = fclk_table->min; - pstate_table->fclk_pstate.peak = fclk_table->max; + pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table); if (driver_clocks.BaseClockAc && - driver_clocks.BaseClockAc < gfx_table->max) + driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table)) pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; else - pstate_table->gfxclk_pstate.standard = gfx_table->max; - pstate_table->uclk_pstate.standard = mem_table->max; - pstate_table->socclk_pstate.standard = soc_table->min; - pstate_table->vclk_pstate.standard = vclk_table->min; - pstate_table->dclk_pstate.standard = dclk_table->min; - pstate_table->fclk_pstate.standard = fclk_table->min; + pstate_table->gfxclk_pstate.standard = + SMU_DPM_TABLE_MAX(gfx_table); + pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table); + pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table); + pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table); + pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table); return 0; } @@ -2725,8 +2701,7 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, uint8_t pcie_width_cap) { struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_13_0_pcie_table *pcie_table = - &dpm_context->dpm_tables.pcie_table; + struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; int num_of_levels; int link_level; uint32_t smu_pcie_arg; @@ -2736,23 +2711,23 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, int ret = 0; int i; - pcie_table->num_of_link_levels = 0; + pcie_table->lclk_levels = 0; for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { if (!skutable->PcieGenSpeed[link_level] && !skutable->PcieLaneCount[link_level] && !skutable->LclkFreq[link_level]) continue; - pcie_table->pcie_gen[pcie_table->num_of_link_levels] = - skutable->PcieGenSpeed[link_level]; - pcie_table->pcie_lane[pcie_table->num_of_link_levels] = - skutable->PcieLaneCount[link_level]; - pcie_table->clk_freq[pcie_table->num_of_link_levels] = - skutable->LclkFreq[link_level]; - pcie_table->num_of_link_levels++; + pcie_table->pcie_gen[pcie_table->lclk_levels] = + skutable->PcieGenSpeed[link_level]; + pcie_table->pcie_lane[pcie_table->lclk_levels] = + skutable->PcieLaneCount[link_level]; + pcie_table->lclk_freq[pcie_table->lclk_levels] = + skutable->LclkFreq[link_level]; + pcie_table->lclk_levels++; } - num_of_levels = pcie_table->num_of_link_levels; + num_of_levels = pcie_table->lclk_levels; if (!num_of_levels) return 0; @@ -2803,8 +2778,38 @@ static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu, return ret; } +static int smu_v13_0_7_mode1_reset(struct smu_context *smu) +{ + int ret; + + ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); + if (!ret) { + /* disable mmio access while doing mode 1 reset*/ + smu->adev->no_hw_access = true; + /* ensure no_hw_access is globally visible before any MMIO */ + smp_mb(); + msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); + } + + return ret; +} + +static void smu_v13_0_7_init_msg_ctl(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + smu_v13_0_init_msg_ctl(smu, smu_v13_0_7_message_map); + + /* Set up debug mailbox registers */ + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53); + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75); + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54); + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; +} + static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { - .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask, + .init_allowed_features = smu_v13_0_7_init_allowed_features, .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table, .is_dpm_running = smu_v13_0_7_is_dpm_running, .init_microcode = smu_v13_0_init_microcode, @@ -2816,7 +2821,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .fini_power = smu_v13_0_fini_power, .check_fw_status = smu_v13_0_7_check_fw_status, .setup_pptable = smu_v13_0_7_setup_pptable, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .write_pptable = smu_cmn_write_pptable, .set_driver_table_location = smu_v13_0_set_driver_table_location, .system_features_control = smu_v13_0_system_features_control, @@ -2830,7 +2835,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, .read_sensor = smu_v13_0_7_read_sensor, .feature_is_enabled = smu_cmn_feature_is_enabled, - .print_clk_levels = smu_v13_0_7_print_clk_levels, + .emit_clk_levels = smu_v13_0_7_emit_clk_levels, .force_clk_levels = smu_v13_0_7_force_clk_levels, .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters, .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range, @@ -2864,7 +2869,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { .baco_enter = smu_v13_0_baco_enter, .baco_exit = smu_v13_0_baco_exit, .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported, - .mode1_reset = smu_v13_0_mode1_reset, + .mode1_reset = smu_v13_0_7_mode1_reset, .set_mp1_state = smu_v13_0_7_set_mp1_state, .set_df_cstate = smu_v13_0_7_set_df_cstate, .gpo_control = smu_v13_0_gpo_control, @@ -2877,12 +2882,11 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = { void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &smu_v13_0_7_ppt_funcs; - smu->message_map = smu_v13_0_7_message_map; smu->clock_map = smu_v13_0_7_clk_map; smu->feature_map = smu_v13_0_7_feature_mask_map; smu->table_map = smu_v13_0_7_table_map; smu->pwr_src_map = smu_v13_0_7_pwr_src_map; smu->workload_map = smu_v13_0_7_workload_map; smu->smc_driver_if_version = SMU13_0_7_DRIVER_IF_VERSION; - smu_v13_0_set_smu_mailbox_registers(smu); + smu_v13_0_7_init_msg_ctl(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 5d7e671fa3c3a..748b5b074fff6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -55,17 +55,19 @@ #define SMU_13_0_1_UMD_PSTATE_SOCCLK 678 #define SMU_13_0_1_UMD_PSTATE_FCLK 1800 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT)) +static const struct smu_feature_bits yellow_carp_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT) + } +}; static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), @@ -152,6 +154,7 @@ static int yellow_carp_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -173,9 +176,10 @@ static int yellow_carp_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v2_1), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err3_out; return 0; @@ -203,8 +207,7 @@ static int yellow_carp_fini_smc_tables(struct smu_context *smu) kfree(smu_table->watermarks_table); smu_table->watermarks_table = NULL; - kfree(smu_table->gpu_metrics_table); - smu_table->gpu_metrics_table = NULL; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); return 0; } @@ -256,14 +259,15 @@ static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable) static bool yellow_carp_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + yellow_carp_dpm_features.bits); } static int yellow_carp_post_smu_init(struct smu_context *smu) @@ -557,11 +561,11 @@ static int yellow_carp_set_watermarks_table(struct smu_context *smu, } static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu, - void **table) + void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v2_1 *gpu_metrics = - (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v2_1 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -606,6 +610,8 @@ static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v2_1); } @@ -1038,17 +1044,15 @@ static uint32_t yellow_carp_get_umd_pstate_clk_default(struct smu_context *smu, return clk_limit; } -static int yellow_carp_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int yellow_carp_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { - int i, idx, size = 0, ret = 0, start_offset = 0; + int i, idx, size = *offset, ret = 0, start_offset = *offset; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min, max; uint32_t clk_limit = 0; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); @@ -1069,17 +1073,17 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu, case SMU_FCLK: ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - goto print_clk_out; + return ret; ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count); if (ret) - goto print_clk_out; + return ret; for (i = 0; i < count; i++) { idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, idx, &value); if (ret) - goto print_clk_out; + return ret; size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); @@ -1090,7 +1094,7 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu, clk_limit = yellow_carp_get_umd_pstate_clk_default(smu, clk_type); ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - goto print_clk_out; + return ret; min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; if (cur_value == max) @@ -1111,8 +1115,9 @@ static int yellow_carp_print_clk_levels(struct smu_context *smu, break; } -print_clk_out: - return size - start_offset; + *offset += size - start_offset; + + return 0; } static int yellow_carp_force_clk_levels(struct smu_context *smu, @@ -1326,13 +1331,11 @@ static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *sm static const struct pptable_funcs yellow_carp_ppt_funcs = { .check_fw_status = smu_v13_0_check_fw_status, - .check_fw_version = smu_v13_0_check_fw_version, + .check_fw_version = smu_cmn_check_fw_version, .init_smc_tables = yellow_carp_init_smc_tables, .fini_smc_tables = yellow_carp_fini_smc_tables, .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values, .system_features_control = yellow_carp_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable, .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable, .set_default_dpm_table = yellow_carp_set_default_dpm_tables, @@ -1349,7 +1352,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = { .mode2_reset = yellow_carp_mode2_reset, .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq, .od_edit_dpm_table = yellow_carp_od_edit_dpm_table, - .print_clk_levels = yellow_carp_print_clk_levels, + .emit_clk_levels = yellow_carp_emit_clk_levels, .force_clk_levels = yellow_carp_force_clk_levels, .set_performance_level = yellow_carp_set_performance_level, .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters, @@ -1358,10 +1361,9 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = { void yellow_carp_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &yellow_carp_ppt_funcs; - smu->message_map = yellow_carp_message_map; smu->feature_map = yellow_carp_feature_mask_map; smu->table_map = yellow_carp_table_map; smu->is_apu = true; smu->smc_driver_if_version = SMU13_YELLOW_CARP_DRIVER_IF_VERSION; - smu_v13_0_set_smu_mailbox_registers(smu); + smu_v13_0_init_msg_ctl(smu, yellow_carp_message_map); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index 06a81533759cd..9f01bed3970ee 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -284,7 +284,6 @@ int smu_v14_0_check_fw_version(struct smu_context *smu) "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", smu->smc_driver_if_version, if_version, smu_program, smu_version, smu_major, smu_minor, smu_debug); - dev_info(adev->dev, "SMU driver if version not matched\n"); } return ret; @@ -496,13 +495,12 @@ int smu_v14_0_fini_smc_tables(struct smu_context *smu) struct smu_table_context *smu_table = &smu->smu_table; struct smu_dpm_context *smu_dpm = &smu->smu_dpm; - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); kfree(smu_table->combo_pptable); kfree(smu_table->boot_overdrive_table); kfree(smu_table->overdrive_table); kfree(smu_table->max_sustainable_clocks); kfree(smu_table->driver_pptable); - smu_table->gpu_metrics_table = NULL; smu_table->combo_pptable = NULL; smu_table->boot_overdrive_table = NULL; smu_table->overdrive_table = NULL; @@ -747,11 +745,11 @@ int smu_v14_0_set_allowed_mask(struct smu_context *smu) int ret = 0; uint32_t feature_mask[2]; - if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || - feature->feature_num < 64) + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) return -EINVAL; - bitmap_to_arr32(feature_mask, feature->allowed, 64); + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, feature_mask[1], NULL); @@ -1248,18 +1246,12 @@ int smu_v14_0_set_performance_level(struct smu_context *smu, { struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_14_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_14_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_14_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; - struct smu_14_0_dpm_table *vclk_table = - &dpm_context->dpm_tables.vclk_table; - struct smu_14_0_dpm_table *dclk_table = - &dpm_context->dpm_tables.dclk_table; - struct smu_14_0_dpm_table *fclk_table = - &dpm_context->dpm_tables.fclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct amdgpu_device *adev = smu->adev; @@ -1274,34 +1266,34 @@ int smu_v14_0_set_performance_level(struct smu_context *smu, switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: - sclk_min = sclk_max = gfx_table->max; - mclk_min = mclk_max = mem_table->max; - socclk_min = socclk_max = soc_table->max; - vclk_min = vclk_max = vclk_table->max; - dclk_min = dclk_max = dclk_table->max; - fclk_min = fclk_max = fclk_table->max; + sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table); break; case AMD_DPM_FORCED_LEVEL_LOW: - sclk_min = sclk_max = gfx_table->min; - mclk_min = mclk_max = mem_table->min; - socclk_min = socclk_max = soc_table->min; - vclk_min = vclk_max = vclk_table->min; - dclk_min = dclk_max = dclk_table->min; - fclk_min = fclk_max = fclk_table->min; + sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table); break; case AMD_DPM_FORCED_LEVEL_AUTO: - sclk_min = gfx_table->min; - sclk_max = gfx_table->max; - mclk_min = mem_table->min; - mclk_max = mem_table->max; - socclk_min = soc_table->min; - socclk_max = soc_table->max; - vclk_min = vclk_table->min; - vclk_max = vclk_table->max; - dclk_min = dclk_table->min; - dclk_max = dclk_table->max; - fclk_min = fclk_table->min; - fclk_max = fclk_table->max; + sclk_min = SMU_DPM_TABLE_MIN(gfx_table); + sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = SMU_DPM_TABLE_MIN(mem_table); + mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = SMU_DPM_TABLE_MIN(soc_table); + socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = SMU_DPM_TABLE_MIN(vclk_table); + vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = SMU_DPM_TABLE_MIN(dclk_table); + dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = SMU_DPM_TABLE_MIN(fclk_table); + fclk_max = SMU_DPM_TABLE_MAX(fclk_table); auto_level = true; break; case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: @@ -1523,11 +1515,12 @@ static int smu_v14_0_get_fine_grained_status(struct smu_context *smu, int smu_v14_0_set_single_dpm_table(struct smu_context *smu, enum smu_clk_type clk_type, - struct smu_14_0_dpm_table *single_dpm_table) + struct smu_dpm_table *single_dpm_table) { int ret = 0; uint32_t clk; int i; + bool is_fine_grained; ret = smu_v14_0_get_dpm_level_count(smu, clk_type, @@ -1537,13 +1530,14 @@ int smu_v14_0_set_single_dpm_table(struct smu_context *smu, return ret; } - ret = smu_v14_0_get_fine_grained_status(smu, - clk_type, - &single_dpm_table->is_fine_grained); + ret = smu_v14_0_get_fine_grained_status(smu, clk_type, + &is_fine_grained); if (ret) { dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); return ret; } + if (is_fine_grained) + single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; for (i = 0; i < single_dpm_table->count; i++) { ret = smu_v14_0_get_dpm_freq_by_index(smu, @@ -1557,11 +1551,6 @@ int smu_v14_0_set_single_dpm_table(struct smu_context *smu, single_dpm_table->dpm_levels[i].value = clk; single_dpm_table->dpm_levels[i].enabled = true; - - if (i == 0) - single_dpm_table->min = clk; - else if (i == single_dpm_table->count - 1) - single_dpm_table->max = clk; } return 0; @@ -1845,17 +1834,21 @@ int smu_v14_0_baco_exit(struct smu_context *smu) int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu) { - uint16_t index; + struct smu_msg_ctl *ctl = &smu->msg_ctl; struct amdgpu_device *adev = smu->adev; + int ret; if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); } - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, - SMU_MSG_EnableGfxImu); - return smu_cmn_send_msg_without_waiting(smu, index, ENABLE_IMU_ARG_GFXOFF_ENABLE); + mutex_lock(&ctl->lock); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, + ENABLE_IMU_ARG_GFXOFF_ENABLE); + mutex_unlock(&ctl->lock); + + return ret; } int smu_v14_0_set_default_dpm_tables(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c index 97414bc397641..dbdf7653cc534 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c @@ -72,19 +72,21 @@ #define SMU_14_0_4_UMD_PSTATE_GFXCLK 938 #define SMU_14_0_4_UMD_PSTATE_SOCCLK 938 -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \ - FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \ - FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \ - FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \ - FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \ - FEATURE_MASK(FEATURE_GFX_DPM_BIT) | \ - FEATURE_MASK(FEATURE_VPE_DPM_BIT)) +static const struct smu_feature_bits smu_v14_0_0_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_IPU_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT) + } +}; enum smu_mall_pg_config { SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0, @@ -186,6 +188,7 @@ static int smu_v14_0_0_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -207,9 +210,10 @@ static int smu_v14_0_0_init_smc_tables(struct smu_context *smu) if (!smu_table->watermarks_table) goto err2_out; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v3_0); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v3_0), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err3_out; return 0; @@ -237,8 +241,7 @@ static int smu_v14_0_0_fini_smc_tables(struct smu_context *smu) kfree(smu_table->watermarks_table); smu_table->watermarks_table = NULL; - kfree(smu_table->gpu_metrics_table); - smu_table->gpu_metrics_table = NULL; + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); return 0; } @@ -469,14 +472,15 @@ static int smu_v14_0_0_read_sensor(struct smu_context *smu, static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v14_0_0_dpm_features.bits); } static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu, @@ -538,11 +542,11 @@ static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu, } static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu, - void **table) + void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v3_0 *gpu_metrics = - (struct gpu_metrics_v3_0 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v3_0 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetrics_t metrics; int ret = 0; @@ -611,6 +615,8 @@ static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v3_0); } @@ -1129,16 +1135,14 @@ static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu, return 0; } -static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, char *buf) +static int smu_v14_0_0_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { - int i, idx, ret = 0, size = 0, start_offset = 0; + int i, idx, ret = 0, size = *offset, start_offset = *offset; uint32_t cur_value = 0, value = 0, count = 0; uint32_t min, max; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - switch (clk_type) { case SMU_OD_SCLK: size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); @@ -1162,17 +1166,17 @@ static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, case SMU_FCLK: ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - break; + return ret; ret = smu_v14_0_common_get_dpm_level_count(smu, clk_type, &count); if (ret) - break; + return ret; for (i = 0; i < count; i++) { idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i; ret = smu_v14_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value); if (ret) - break; + return ret; size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value, cur_value == value ? "*" : ""); @@ -1182,7 +1186,7 @@ static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, case SMU_SCLK: ret = smu_v14_0_0_get_current_clk_freq(smu, clk_type, &cur_value); if (ret) - break; + return ret; min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; if (cur_value == max) @@ -1203,7 +1207,9 @@ static int smu_v14_0_0_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + *offset += size - start_offset; + + return 0; } static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu, @@ -1698,8 +1704,6 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = { .fini_smc_tables = smu_v14_0_0_fini_smc_tables, .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values, .system_features_control = smu_v14_0_0_system_features_control, - .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, - .send_smc_msg = smu_cmn_send_smc_msg, .dpm_set_vcn_enable = smu_v14_0_set_vcn_enable, .dpm_set_jpeg_enable = smu_v14_0_set_jpeg_enable, .set_default_dpm_table = smu_v14_0_set_default_dpm_tables, @@ -1716,7 +1720,7 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = { .set_soft_freq_limited_range = smu_v14_0_0_set_soft_freq_limited_range, .restore_user_od_settings = smu_v14_0_0_restore_user_od_settings, .od_edit_dpm_table = smu_v14_0_od_edit_dpm_table, - .print_clk_levels = smu_v14_0_0_print_clk_levels, + .emit_clk_levels = smu_v14_0_0_emit_clk_levels, .force_clk_levels = smu_v14_0_0_force_clk_levels, .set_performance_level = smu_v14_0_common_set_performance_level, .set_fine_grain_gfx_freq_parameters = smu_v14_0_common_set_fine_grain_gfx_freq_parameters, @@ -1728,23 +1732,28 @@ static const struct pptable_funcs smu_v14_0_0_ppt_funcs = { .set_mall_enable = smu_v14_0_common_set_mall_enable, }; -static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu) +static void smu_v14_0_0_init_msg_ctl(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = smu_v14_0_0_message_map; } void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu) { - smu->ppt_funcs = &smu_v14_0_0_ppt_funcs; - smu->message_map = smu_v14_0_0_message_map; smu->feature_map = smu_v14_0_0_feature_mask_map; smu->table_map = smu_v14_0_0_table_map; smu->is_apu = true; - smu_v14_0_0_set_smu_mailbox_registers(smu); + smu_v14_0_0_init_msg_ctl(smu); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index d7642d388bc38..baf6866477e7c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -56,13 +56,17 @@ #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) -#define FEATURE_MASK(feature) (1ULL << feature) -#define SMC_DPM_FEATURE ( \ - FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \ - FEATURE_MASK(FEATURE_DPM_FCLK_BIT)) +static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, + int od_feature_bit, + int32_t *min, int32_t *max); + +static const struct smu_feature_bits smu_v14_0_2_dpm_features = { + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_LINK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK_BIT) } +}; #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000 #define DEBUGSMC_MSG_Mode1Reset 2 @@ -264,53 +268,9 @@ static const uint8_t smu_v14_0_2_throttler_map[] = { [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT), }; -static int -smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu, - uint32_t *feature_mask, uint32_t num) +static int smu_v14_0_2_init_allowed_features(struct smu_context *smu) { - struct amdgpu_device *adev = smu->adev; - /*u32 smu_version;*/ - - if (num > 2) - return -EINVAL; - - memset(feature_mask, 0xff, sizeof(uint32_t) * num); - - if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) { - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); - *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); - } -#if 0 - if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) || - !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); - - if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); - - /* PMFW 78.58 contains a critical fix for gfxoff feature */ - smu_cmn_get_smc_version(smu, NULL, &smu_version); - if ((smu_version < 0x004e3a00) || - !(adev->pm.pp_feature & PP_GFXOFF_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); - - if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT); - } - - if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); - - if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT); - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT); - } - - if (!(adev->pm.pp_feature & PP_ULV_MASK)) - *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT); -#endif + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); return 0; } @@ -415,6 +375,7 @@ static int smu_v14_0_2_tables_init(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; struct smu_table *tables = smu_table->tables; + int ret; SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -441,9 +402,10 @@ static int smu_v14_0_2_tables_init(struct smu_context *smu) goto err0_out; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3); - smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); - if (!smu_table->gpu_metrics_table) + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v1_3), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) goto err1_out; smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); @@ -459,7 +421,7 @@ static int smu_v14_0_2_tables_init(struct smu_context *smu) err3_out: kfree(smu_table->watermarks_table); err2_out: - kfree(smu_table->gpu_metrics_table); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); err1_out: kfree(smu_table->metrics_table); err0_out: @@ -501,11 +463,12 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) struct smu_table_context *table_context = &smu->smu_table; PPTable_t *pptable = table_context->driver_pptable; SkuTable_t *skutable = &pptable->SkuTable; - struct smu_14_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; int ret = 0; /* socclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_SOCCLK, @@ -516,12 +479,11 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_GFXCLK, @@ -543,18 +505,16 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) skutable->DriverReportedClocks.GameClockAc)) { dpm_table->dpm_levels[dpm_table->count - 1].value = skutable->DriverReportedClocks.GameClockAc; - dpm_table->max = skutable->DriverReportedClocks.GameClockAc; } } else { dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* uclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_UCLK, @@ -565,12 +525,11 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* fclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_FCLK, @@ -581,12 +540,11 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* vclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = SMU_VCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_VCLK, @@ -597,12 +555,11 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = SMU_DCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_DCLK, @@ -613,12 +570,11 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } /* dcefclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.dcef_table; + dpm_table->clk_type = SMU_DCEFCLK; if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCN_BIT)) { ret = smu_v14_0_set_single_dpm_table(smu, SMU_DCEFCLK, @@ -629,8 +585,6 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) dpm_table->count = 1; dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; dpm_table->dpm_levels[0].enabled = true; - dpm_table->min = dpm_table->dpm_levels[0].value; - dpm_table->max = dpm_table->dpm_levels[0].value; } return 0; @@ -639,13 +593,14 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) static bool smu_v14_0_2_is_dpm_running(struct smu_context *smu) { int ret = 0; - uint64_t feature_enabled; + struct smu_feature_bits feature_enabled; ret = smu_cmn_get_enabled_mask(smu, &feature_enabled); if (ret) return false; - return !!(feature_enabled & SMC_DPM_FEATURE); + return smu_feature_bits_test_mask(&feature_enabled, + smu_v14_0_2_dpm_features.bits); } static uint32_t smu_v14_0_2_get_throttler_status(SmuMetrics_t *metrics) @@ -794,7 +749,7 @@ static int smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context *smu, { struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_14_0_dpm_table *dpm_table; + struct smu_dpm_table *dpm_table; switch (clk_type) { case SMU_MCLK: @@ -831,9 +786,9 @@ static int smu_v14_0_2_get_dpm_ultimate_freq(struct smu_context *smu, } if (min) - *min = dpm_table->min; + *min = SMU_DPM_TABLE_MIN(dpm_table); if (max) - *max = dpm_table->max; + *max = SMU_DPM_TABLE_MAX(dpm_table); return 0; } @@ -972,8 +927,35 @@ static bool smu_v14_0_2_is_od_feature_supported(struct smu_context *smu, PPTable_t *pptable = smu->smu_table.driver_pptable; const OverDriveLimits_t * const overdrive_upperlimits = &pptable->SkuTable.OverDriveLimitsBasicMax; + int32_t min_value, max_value; + bool feature_enabled; - return overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit); + switch (od_feature_bit) { + case PP_OD_FEATURE_FAN_CURVE_BIT: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + if (feature_enabled) { + smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_TEMP, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + + smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_FAN_CURVE_PWM, + &min_value, &max_value); + if (!min_value && !max_value) { + feature_enabled = false; + goto out; + } + } + break; + default: + feature_enabled = !!(overdrive_upperlimits->FeatureCtrlMask & (1U << od_feature_bit)); + break; + } + +out: + return feature_enabled; } static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, @@ -1045,27 +1027,24 @@ static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, *max = od_max_setting; } -static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, - enum smu_clk_type clk_type, - char *buf) +static int smu_v14_0_2_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context; OverDriveTableExternal_t *od_table = (OverDriveTableExternal_t *)smu->smu_table.overdrive_table; - struct smu_14_0_dpm_table *single_dpm_table; - struct smu_14_0_pcie_table *pcie_table; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_pcie_table *pcie_table; uint32_t gen_speed, lane_width; - int i, curr_freq, size = 0, start_offset = 0; + int i, curr_freq, size = *offset, start_offset = *offset; int32_t min_value, max_value; int ret = 0; - smu_cmn_get_sysfs_buf(&buf, &size); - start_offset = size; - if (amdgpu_ras_intr_triggered()) { - size += sysfs_emit_at(buf, size, "unavailable\n"); - return size - start_offset; + sysfs_emit_at(buf, size, "unavailable\n"); + return -EBUSY; } switch (clk_type) { @@ -1092,61 +1071,6 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, case SMU_DCEFCLK: single_dpm_table = &(dpm_context->dpm_tables.dcef_table); break; - default: - break; - } - - switch (clk_type) { - case SMU_SCLK: - case SMU_MCLK: - case SMU_SOCCLK: - case SMU_FCLK: - case SMU_VCLK: - case SMU_VCLK1: - case SMU_DCLK: - case SMU_DCLK1: - case SMU_DCEFCLK: - ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type, &curr_freq); - if (ret) { - dev_err(smu->adev->dev, "Failed to get current clock freq!"); - return ret; - } - - if (single_dpm_table->is_fine_grained) { - /* - * For fine grained dpms, there are only two dpm levels: - * - level 0 -> min clock freq - * - level 1 -> max clock freq - * And the current clock frequency can be any value between them. - * So, if the current clock frequency is not at level 0 or level 1, - * we will fake it as three dpm levels: - * - level 0 -> min clock freq - * - level 1 -> current actual clock freq - * - level 2 -> max clock freq - */ - if ((single_dpm_table->dpm_levels[0].value != curr_freq) && - (single_dpm_table->dpm_levels[1].value != curr_freq)) { - size += sysfs_emit_at(buf, size, "0: %uMhz\n", - single_dpm_table->dpm_levels[0].value); - size += sysfs_emit_at(buf, size, "1: %uMhz *\n", - curr_freq); - size += sysfs_emit_at(buf, size, "2: %uMhz\n", - single_dpm_table->dpm_levels[1].value); - } else { - size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", - single_dpm_table->dpm_levels[0].value, - single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : ""); - size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", - single_dpm_table->dpm_levels[1].value, - single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : ""); - } - } else { - for (i = 0; i < single_dpm_table->count; i++) - size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", - i, single_dpm_table->dpm_levels[i].value, - single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : ""); - } - break; case SMU_PCIE: ret = smu_v14_0_2_get_smu_metrics_data(smu, METRICS_PCIE_RATE, @@ -1161,25 +1085,10 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, return ret; pcie_table = &(dpm_context->dpm_tables.pcie_table); - for (i = 0; i < pcie_table->num_of_link_levels; i++) - size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, - (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : - (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : - (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : - (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : - (pcie_table->pcie_gen[i] == 4) ? "32.0GT/s," : "", - (pcie_table->pcie_lane[i] == 1) ? "x1" : - (pcie_table->pcie_lane[i] == 2) ? "x2" : - (pcie_table->pcie_lane[i] == 3) ? "x4" : - (pcie_table->pcie_lane[i] == 4) ? "x8" : - (pcie_table->pcie_lane[i] == 5) ? "x12" : - (pcie_table->pcie_lane[i] == 6) ? "x16" : - (pcie_table->pcie_lane[i] == 7) ? "x32" : "", - pcie_table->clk_freq[i], - (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && - (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? - "*" : ""); - break; + return smu_cmn_print_pcie_levels(smu, pcie_table, + SMU_DPM_PCIE_GEN_IDX(gen_speed), + SMU_DPM_PCIE_WIDTH_IDX(lane_width), + buf, offset); case SMU_OD_SCLK: if (!smu_v14_0_2_is_od_feature_supported(smu, @@ -1375,7 +1284,21 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, break; } - return size - start_offset; + if (single_dpm_table) { + ret = smu_v14_0_2_get_current_clk_freq_by_table(smu, clk_type, + &curr_freq); + if (ret) { + dev_err(smu->adev->dev, + "Failed to get current clock freq!"); + return ret; + } + return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, + curr_freq, buf, offset); + } + + *offset += size - start_offset; + + return 0; } static int smu_v14_0_2_force_clk_levels(struct smu_context *smu, @@ -1384,7 +1307,7 @@ static int smu_v14_0_2_force_clk_levels(struct smu_context *smu, { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context; - struct smu_14_0_dpm_table *single_dpm_table; + struct smu_dpm_table *single_dpm_table; uint32_t soft_min_level, soft_max_level; uint32_t min_freq, max_freq; int ret = 0; @@ -1430,7 +1353,7 @@ static int smu_v14_0_2_force_clk_levels(struct smu_context *smu, case SMU_VCLK1: case SMU_DCLK: case SMU_DCLK1: - if (single_dpm_table->is_fine_grained) { + if (single_dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED) { /* There is only 2 levels for fine grained DPM */ soft_max_level = (soft_max_level >= 1 ? 1 : 0); soft_min_level = (soft_min_level >= 1 ? 1 : 0); @@ -1463,9 +1386,9 @@ static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu, uint8_t pcie_width_cap) { struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_14_0_pcie_table *pcie_table = + struct smu_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; - int num_of_levels; + int lclk_levels; uint32_t smu_pcie_arg; uint32_t link_level; struct smu_table_context *table_context = &smu->smu_table; @@ -1474,34 +1397,34 @@ static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu, int ret = 0; int i; - pcie_table->num_of_link_levels = 0; + pcie_table->lclk_levels = 0; for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { if (!skutable->PcieGenSpeed[link_level] && !skutable->PcieLaneCount[link_level] && !skutable->LclkFreq[link_level]) continue; - pcie_table->pcie_gen[pcie_table->num_of_link_levels] = + pcie_table->pcie_gen[pcie_table->lclk_levels] = skutable->PcieGenSpeed[link_level]; - pcie_table->pcie_lane[pcie_table->num_of_link_levels] = + pcie_table->pcie_lane[pcie_table->lclk_levels] = skutable->PcieLaneCount[link_level]; - pcie_table->clk_freq[pcie_table->num_of_link_levels] = + pcie_table->lclk_freq[pcie_table->lclk_levels] = skutable->LclkFreq[link_level]; - pcie_table->num_of_link_levels++; + pcie_table->lclk_levels++; } - num_of_levels = pcie_table->num_of_link_levels; - if (!num_of_levels) + lclk_levels = pcie_table->lclk_levels; + if (!lclk_levels) return 0; if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) { - if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap) - pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1]; + if (pcie_table->pcie_gen[lclk_levels - 1] < pcie_gen_cap) + pcie_gen_cap = pcie_table->pcie_gen[lclk_levels - 1]; - if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap) - pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1]; + if (pcie_table->pcie_lane[lclk_levels - 1] < pcie_width_cap) + pcie_width_cap = pcie_table->pcie_lane[lclk_levels - 1]; /* Force all levels to use the same settings */ - for (i = 0; i < num_of_levels; i++) { + for (i = 0; i < lclk_levels; i++) { pcie_table->pcie_gen[i] = pcie_gen_cap; pcie_table->pcie_lane[i] = pcie_width_cap; smu_pcie_arg = i << 16; @@ -1516,7 +1439,7 @@ static int smu_v14_0_2_update_pcie_parameters(struct smu_context *smu, break; } } else { - for (i = 0; i < num_of_levels; i++) { + for (i = 0; i < lclk_levels; i++) { if (pcie_table->pcie_gen[i] > pcie_gen_cap || pcie_table->pcie_lane[i] > pcie_width_cap) { pcie_table->pcie_gen[i] = pcie_table->pcie_gen[i] > pcie_gen_cap ? @@ -1583,18 +1506,12 @@ static int smu_v14_0_2_populate_umd_state_clk(struct smu_context *smu) { struct smu_14_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; - struct smu_14_0_dpm_table *gfx_table = - &dpm_context->dpm_tables.gfx_table; - struct smu_14_0_dpm_table *mem_table = - &dpm_context->dpm_tables.uclk_table; - struct smu_14_0_dpm_table *soc_table = - &dpm_context->dpm_tables.soc_table; - struct smu_14_0_dpm_table *vclk_table = - &dpm_context->dpm_tables.vclk_table; - struct smu_14_0_dpm_table *dclk_table = - &dpm_context->dpm_tables.dclk_table; - struct smu_14_0_dpm_table *fclk_table = - &dpm_context->dpm_tables.fclk_table; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; struct smu_table_context *table_context = &smu->smu_table; @@ -1602,38 +1519,39 @@ static int smu_v14_0_2_populate_umd_state_clk(struct smu_context *smu) DriverReportedClocks_t driver_clocks = pptable->SkuTable.DriverReportedClocks; - pstate_table->gfxclk_pstate.min = gfx_table->min; + pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table); if (driver_clocks.GameClockAc && - (driver_clocks.GameClockAc < gfx_table->max)) + (driver_clocks.GameClockAc < SMU_DPM_TABLE_MAX(gfx_table))) pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc; else - pstate_table->gfxclk_pstate.peak = gfx_table->max; + pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table); - pstate_table->uclk_pstate.min = mem_table->min; - pstate_table->uclk_pstate.peak = mem_table->max; + pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table); - pstate_table->socclk_pstate.min = soc_table->min; - pstate_table->socclk_pstate.peak = soc_table->max; + pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table); - pstate_table->vclk_pstate.min = vclk_table->min; - pstate_table->vclk_pstate.peak = vclk_table->max; + pstate_table->vclk_pstate.min = SMU_DPM_TABLE_MIN(vclk_table); + pstate_table->vclk_pstate.peak = SMU_DPM_TABLE_MAX(vclk_table); - pstate_table->dclk_pstate.min = dclk_table->min; - pstate_table->dclk_pstate.peak = dclk_table->max; + pstate_table->dclk_pstate.min = SMU_DPM_TABLE_MIN(dclk_table); + pstate_table->dclk_pstate.peak = SMU_DPM_TABLE_MAX(dclk_table); - pstate_table->fclk_pstate.min = fclk_table->min; - pstate_table->fclk_pstate.peak = fclk_table->max; + pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table); + pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table); if (driver_clocks.BaseClockAc && - driver_clocks.BaseClockAc < gfx_table->max) + driver_clocks.BaseClockAc < SMU_DPM_TABLE_MAX(gfx_table)) pstate_table->gfxclk_pstate.standard = driver_clocks.BaseClockAc; else - pstate_table->gfxclk_pstate.standard = gfx_table->max; - pstate_table->uclk_pstate.standard = mem_table->max; - pstate_table->socclk_pstate.standard = soc_table->min; - pstate_table->vclk_pstate.standard = vclk_table->min; - pstate_table->dclk_pstate.standard = dclk_table->min; - pstate_table->fclk_pstate.standard = fclk_table->min; + pstate_table->gfxclk_pstate.standard = + SMU_DPM_TABLE_MAX(gfx_table); + pstate_table->uclk_pstate.standard = SMU_DPM_TABLE_MAX(mem_table); + pstate_table->socclk_pstate.standard = SMU_DPM_TABLE_MIN(soc_table); + pstate_table->vclk_pstate.standard = SMU_DPM_TABLE_MIN(vclk_table); + pstate_table->dclk_pstate.standard = SMU_DPM_TABLE_MIN(dclk_table); + pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table); return 0; } @@ -2178,25 +2096,35 @@ static int smu_v14_0_2_enable_gfx_features(struct smu_context *smu) return -EOPNOTSUPP; } -static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu) +static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; - - smu->param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82); - smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66); - smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90); - - smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53); - smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75); - smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_66); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_90); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_82); + ctl->config.num_arg_regs = 1; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = smu_v14_0_2_message_map; + ctl->flags = 0; + + /* Set up debug mailbox registers */ + ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53); + ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75); + ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); + ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX; } static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu, void **table) { - struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_3 *gpu_metrics = - (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table; + (struct gpu_metrics_v1_3 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); SmuMetricsExternal_t metrics_ext; SmuMetrics_t *metrics = &metrics_ext.SmuMetrics; int ret = 0; @@ -2270,6 +2198,8 @@ static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu, *table = (void *)gpu_metrics; + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + return sizeof(struct gpu_metrics_v1_3); } @@ -2413,7 +2343,8 @@ static int smu_v14_0_2_restore_user_od_settings(struct smu_context *smu) user_od_table->OverDriveTable.FeatureCtrlMask = BIT(PP_OD_FEATURE_GFXCLK_BIT) | BIT(PP_OD_FEATURE_UCLK_BIT) | BIT(PP_OD_FEATURE_GFX_VF_CURVE_BIT) | - BIT(PP_OD_FEATURE_FAN_CURVE_BIT); + BIT(PP_OD_FEATURE_FAN_CURVE_BIT) | + BIT(PP_OD_FEATURE_ZERO_FAN_BIT); res = smu_v14_0_2_upload_overdrive_table(smu, user_od_table); user_od_table->OverDriveTable.FeatureCtrlMask = 0; if (res == 0) @@ -2854,7 +2785,7 @@ static int smu_v14_0_2_set_power_limit(struct smu_context *smu, } static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { - .get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask, + .init_allowed_features = smu_v14_0_2_init_allowed_features, .set_default_dpm_table = smu_v14_0_2_set_default_dpm_table, .i2c_init = smu_v14_0_2_i2c_control_init, .i2c_fini = smu_v14_0_2_i2c_control_fini, @@ -2879,7 +2810,7 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { .get_vbios_bootup_values = smu_v14_0_get_vbios_bootup_values, .read_sensor = smu_v14_0_2_read_sensor, .feature_is_enabled = smu_cmn_feature_is_enabled, - .print_clk_levels = smu_v14_0_2_print_clk_levels, + .emit_clk_levels = smu_v14_0_2_emit_clk_levels, .force_clk_levels = smu_v14_0_2_force_clk_levels, .update_pcie_parameters = smu_v14_0_2_update_pcie_parameters, .get_thermal_temperature_range = smu_v14_0_2_get_thermal_temperature_range, @@ -2928,11 +2859,10 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu) { smu->ppt_funcs = &smu_v14_0_2_ppt_funcs; - smu->message_map = smu_v14_0_2_message_map; smu->clock_map = smu_v14_0_2_clk_map; smu->feature_map = smu_v14_0_2_feature_mask_map; smu->table_map = smu_v14_0_2_table_map; smu->pwr_src_map = smu_v14_0_2_pwr_src_map; smu->workload_map = smu_v14_0_2_workload_map; - smu_v14_0_2_set_smu_mailbox_registers(smu); + smu_v14_0_2_init_msg_ctl(smu); } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile similarity index 75% rename from drivers/gpu/drm/amd/display/dc/virtual/Makefile rename to drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile index 931facd4dab5d..fa083ad46c0fd 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/Makefile +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2017 Advanced Micro Devices, Inc. +# Copyright 2025 Advanced Micro Devices, Inc. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -20,11 +20,11 @@ # OTHER DEALINGS IN THE SOFTWARE. # # -# Makefile for the virtual sub-component of DAL. -# It provides the control and status of HW CRTC block. +# Makefile for the 'smu manager' sub-component of powerplay. +# It provides the smu management services for the driver. -VIRTUAL = virtual_link_encoder.o virtual_stream_encoder.o virtual_link_hwss.o +SMU15_MGR = smu_v15_0.o smu_v15_0_0_ppt.o smu_v15_0_8_ppt.o -AMD_DAL_VIRTUAL = $(addprefix $(AMDDALPATH)/dc/virtual/,$(VIRTUAL)) +AMD_SWSMU_SMU15MGR = $(addprefix $(AMD_SWSMU_PATH)/smu15/,$(SMU15_MGR)) -AMD_DISPLAY_FILES += $(AMD_DAL_VIRTUAL) +AMD_POWERPLAY_FILES += $(AMD_SWSMU_SMU15MGR) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c new file mode 100644 index 0000000000000..5649f2e71ac6e --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0.c @@ -0,0 +1,1760 @@ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#define SWSMU_CODE_LAYER_L3 + +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "atomfirmware.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_atombios.h" +#include "smu_v15_0.h" +#include "soc15_common.h" +#include "atom.h" +#include "amdgpu_ras.h" +#include "smu_cmn.h" + +#include "asic_reg/thm/thm_15_0_0_offset.h" +#include "asic_reg/thm/thm_15_0_0_sh_mask.h" +#include "asic_reg/mp/mp_15_0_0_offset.h" +#include "asic_reg/mp/mp_15_0_0_sh_mask.h" + +#define regMP1_SMN_IH_SW_INT_mp1_15_0_0 0x0341 +#define regMP1_SMN_IH_SW_INT_mp1_15_0_0_BASE_IDX 0 +#define regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0 0x0342 +#define regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0_BASE_IDX 0 + +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +#define ENABLE_IMU_ARG_GFXOFF_ENABLE 1 + +int smu_v15_0_init_microcode(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + char ucode_prefix[15]; + int err = 0; + const struct smc_firmware_header_v1_0 *hdr; + const struct common_firmware_header *header; + struct amdgpu_firmware_info *ucode = NULL; + + /* doesn't need to load smu firmware in IOV mode */ + if (amdgpu_sriov_vf(adev)) + return 0; + + amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); + err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, + "amdgpu/%s.bin", ucode_prefix); + if (err) + goto out; + + hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; + amdgpu_ucode_print_smc_hdr(&hdr->header); + adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; + ucode->ucode_id = AMDGPU_UCODE_ID_SMC; + ucode->fw = adev->pm.fw; + header = (const struct common_firmware_header *)ucode->fw->data; + adev->firmware.fw_size += + ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); + } + +out: + if (err) + amdgpu_ucode_release(&adev->pm.fw); + return err; +} + +void smu_v15_0_fini_microcode(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + + amdgpu_ucode_release(&adev->pm.fw); + adev->pm.fw_version = 0; +} + +int smu_v15_0_load_microcode(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + const uint32_t *src; + const struct smc_firmware_header_v1_0 *hdr; + uint32_t addr_start = MP1_SRAM; + uint32_t i; + uint32_t smc_fw_size; + uint32_t mp1_fw_flags; + + hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; + src = (const uint32_t *)(adev->pm.fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + smc_fw_size = hdr->header.ucode_size_bytes; + + for (i = 1; i < smc_fw_size/4 - 1; i++) { + WREG32_PCIE(addr_start, src[i]); + addr_start += 4; + } + + + for (i = 0; i < adev->usec_timeout; i++) { + if (smu->is_apu) + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + + if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + break; + udelay(1); + } + + if (i == adev->usec_timeout) + return -ETIME; + + return 0; +} + +int smu_v15_0_init_pptable_microcode(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct amdgpu_firmware_info *ucode = NULL; + uint32_t size = 0, pptable_id = 0; + int ret = 0; + void *table; + + /* doesn't need to load smu firmware in IOV mode */ + if (amdgpu_sriov_vf(adev)) + return 0; + + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) + return 0; + + if (!adev->scpm_enabled) + return 0; + + /* override pptable_id from driver parameter */ + if (amdgpu_smu_pptable_id >= 0) { + pptable_id = amdgpu_smu_pptable_id; + dev_info(adev->dev, "override pptable id %d\n", pptable_id); + } else { + pptable_id = smu->smu_table.boot_values.pp_table_id; + } + + /* "pptable_id == 0" means vbios carries the pptable. */ + if (!pptable_id) + return 0; + + ret = smu_v15_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); + if (ret) + return ret; + + smu->pptable_firmware.data = table; + smu->pptable_firmware.size = size; + + ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_PPTABLE]; + ucode->ucode_id = AMDGPU_UCODE_ID_PPTABLE; + ucode->fw = &smu->pptable_firmware; + adev->firmware.fw_size += + ALIGN(smu->pptable_firmware.size, PAGE_SIZE); + + return 0; +} + +int smu_v15_0_check_fw_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t mp1_fw_flags = 0; + + if (smu->is_apu) + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); + + + if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return 0; + + return -EIO; +} + +static int smu_v15_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t ppt_offset_bytes; + const struct smc_firmware_header_v2_0 *v2; + + v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; + + ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes); + *size = le32_to_cpu(v2->ppt_size_bytes); + *table = (uint8_t *)v2 + ppt_offset_bytes; + + return 0; +} + +static int smu_v15_0_set_pptable_v2_1(struct smu_context *smu, void **table, + uint32_t *size, uint32_t pptable_id) +{ + struct amdgpu_device *adev = smu->adev; + const struct smc_firmware_header_v2_1 *v2_1; + struct smc_soft_pptable_entry *entries; + uint32_t pptable_count = 0; + int i = 0; + + v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; + entries = (struct smc_soft_pptable_entry *) + ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)); + pptable_count = le32_to_cpu(v2_1->pptable_count); + for (i = 0; i < pptable_count; i++) { + if (le32_to_cpu(entries[i].id) == pptable_id) { + *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)); + *size = le32_to_cpu(entries[i].ppt_size_bytes); + break; + } + } + + if (i == pptable_count) + return -EINVAL; + + return 0; +} + +static int smu_v15_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size) +{ + struct amdgpu_device *adev = smu->adev; + uint16_t atom_table_size; + uint8_t frev, crev; + int ret, index; + + dev_info(adev->dev, "use vbios provided pptable\n"); + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + powerplayinfo); + + ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, + (uint8_t **)table); + if (ret) + return ret; + + if (size) + *size = atom_table_size; + + return 0; +} + +int smu_v15_0_get_pptable_from_firmware(struct smu_context *smu, + void **table, + uint32_t *size, + uint32_t pptable_id) +{ + const struct smc_firmware_header_v1_0 *hdr; + struct amdgpu_device *adev = smu->adev; + uint16_t version_major, version_minor; + int ret; + + hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; + if (!hdr) + return -EINVAL; + + dev_info(adev->dev, "use driver provided pptable %d\n", pptable_id); + + version_major = le16_to_cpu(hdr->header.header_version_major); + version_minor = le16_to_cpu(hdr->header.header_version_minor); + if (version_major != 2) { + dev_err(adev->dev, "Unsupported smu firmware version %d.%d\n", + version_major, version_minor); + return -EINVAL; + } + + switch (version_minor) { + case 0: + ret = smu_v15_0_set_pptable_v2_0(smu, table, size); + break; + case 1: + ret = smu_v15_0_set_pptable_v2_1(smu, table, size, pptable_id); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +int smu_v15_0_setup_pptable(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t size = 0, pptable_id = 0; + void *table; + int ret = 0; + + /* override pptable_id from driver parameter */ + if (amdgpu_smu_pptable_id >= 0) { + pptable_id = amdgpu_smu_pptable_id; + dev_info(adev->dev, "override pptable id %d\n", pptable_id); + } else { + pptable_id = smu->smu_table.boot_values.pp_table_id; + } + + /* force using vbios pptable in sriov mode */ + if ((amdgpu_sriov_vf(adev) || !pptable_id) && (amdgpu_emu_mode != 1)) + ret = smu_v15_0_get_pptable_from_vbios(smu, &table, &size); + else + ret = smu_v15_0_get_pptable_from_firmware(smu, &table, &size, pptable_id); + + if (ret) + return ret; + + if (!smu->smu_table.power_play_table) + smu->smu_table.power_play_table = table; + if (!smu->smu_table.power_play_table_size) + smu->smu_table.power_play_table_size = size; + + return 0; +} + +int smu_v15_0_init_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + int ret = 0; + + smu_table->driver_pptable = + kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL); + if (!smu_table->driver_pptable) { + ret = -ENOMEM; + goto err0_out; + } + + smu_table->max_sustainable_clocks = + kzalloc(sizeof(struct smu_15_0_max_sustainable_clocks), GFP_KERNEL); + if (!smu_table->max_sustainable_clocks) { + ret = -ENOMEM; + goto err1_out; + } + + if (tables[SMU_TABLE_OVERDRIVE].size) { + smu_table->overdrive_table = + kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); + if (!smu_table->overdrive_table) { + ret = -ENOMEM; + goto err2_out; + } + + smu_table->boot_overdrive_table = + kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); + if (!smu_table->boot_overdrive_table) { + ret = -ENOMEM; + goto err3_out; + } + + smu_table->user_overdrive_table = + kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL); + if (!smu_table->user_overdrive_table) { + ret = -ENOMEM; + goto err4_out; + } + } + + smu_table->combo_pptable = + kzalloc(tables[SMU_TABLE_COMBO_PPTABLE].size, GFP_KERNEL); + if (!smu_table->combo_pptable) { + ret = -ENOMEM; + goto err5_out; + } + + return 0; + +err5_out: + kfree(smu_table->user_overdrive_table); +err4_out: + kfree(smu_table->boot_overdrive_table); +err3_out: + kfree(smu_table->overdrive_table); +err2_out: + kfree(smu_table->max_sustainable_clocks); +err1_out: + kfree(smu_table->driver_pptable); +err0_out: + return ret; +} + +int smu_v15_0_fini_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); + kfree(smu_table->combo_pptable); + kfree(smu_table->boot_overdrive_table); + kfree(smu_table->overdrive_table); + kfree(smu_table->max_sustainable_clocks); + kfree(smu_table->driver_pptable); + smu_table->combo_pptable = NULL; + smu_table->boot_overdrive_table = NULL; + smu_table->overdrive_table = NULL; + smu_table->max_sustainable_clocks = NULL; + smu_table->driver_pptable = NULL; + kfree(smu_table->hardcode_pptable); + smu_table->hardcode_pptable = NULL; + + kfree(smu_table->ecc_table); + kfree(smu_table->metrics_table); + kfree(smu_table->watermarks_table); + smu_table->ecc_table = NULL; + smu_table->metrics_table = NULL; + smu_table->watermarks_table = NULL; + smu_table->metrics_time = 0; + + kfree(smu_dpm->dpm_context); + kfree(smu_dpm->golden_dpm_context); + kfree(smu_dpm->dpm_current_power_state); + kfree(smu_dpm->dpm_request_power_state); + smu_dpm->dpm_context = NULL; + smu_dpm->golden_dpm_context = NULL; + smu_dpm->dpm_context_size = 0; + smu_dpm->dpm_current_power_state = NULL; + smu_dpm->dpm_request_power_state = NULL; + + return 0; +} + +int smu_v15_0_init_power(struct smu_context *smu) +{ + struct smu_power_context *smu_power = &smu->smu_power; + + if (smu_power->power_context || smu_power->power_context_size != 0) + return -EINVAL; + + smu_power->power_context = kzalloc(sizeof(struct smu_15_0_dpm_context), + GFP_KERNEL); + if (!smu_power->power_context) + return -ENOMEM; + smu_power->power_context_size = sizeof(struct smu_15_0_dpm_context); + + return 0; +} + +int smu_v15_0_fini_power(struct smu_context *smu) +{ + struct smu_power_context *smu_power = &smu->smu_power; + + if (!smu_power->power_context || smu_power->power_context_size == 0) + return -EINVAL; + + kfree(smu_power->power_context); + smu_power->power_context = NULL; + smu_power->power_context_size = 0; + + return 0; +} + +int smu_v15_0_get_vbios_bootup_values(struct smu_context *smu) +{ + int ret, index; + uint16_t size; + uint8_t frev, crev; + struct atom_common_table_header *header; + struct atom_firmware_info_v3_4 *v_3_4; + struct atom_firmware_info_v3_3 *v_3_3; + struct atom_firmware_info_v3_1 *v_3_1; + struct atom_smu_info_v3_6 *smu_info_v3_6; + struct atom_smu_info_v4_0 *smu_info_v4_0; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + firmwareinfo); + + ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, + (uint8_t **)&header); + if (ret) + return ret; + + if (header->format_revision != 3) { + dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu15\n"); + return -EINVAL; + } + + switch (header->content_revision) { + case 0: + case 1: + case 2: + v_3_1 = (struct atom_firmware_info_v3_1 *)header; + smu->smu_table.boot_values.revision = v_3_1->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; + smu->smu_table.boot_values.pp_table_id = 0; + break; + case 3: + v_3_3 = (struct atom_firmware_info_v3_3 *)header; + smu->smu_table.boot_values.revision = v_3_3->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; + smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; + break; + case 4: + default: + v_3_4 = (struct atom_firmware_info_v3_4 *)header; + smu->smu_table.boot_values.revision = v_3_4->firmware_revision; + smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz; + smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; + smu->smu_table.boot_values.socclk = 0; + smu->smu_table.boot_values.dcefclk = 0; + smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv; + smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv; + smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv; + smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv; + smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id; + smu->smu_table.boot_values.pp_table_id = v_3_4->pplib_pptable_id; + break; + } + + smu->smu_table.boot_values.format_revision = header->format_revision; + smu->smu_table.boot_values.content_revision = header->content_revision; + + index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1, + smu_info); + if (!amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, + (uint8_t **)&header)) { + + if ((frev == 3) && (crev == 6)) { + smu_info_v3_6 = (struct atom_smu_info_v3_6 *)header; + + smu->smu_table.boot_values.socclk = smu_info_v3_6->bootup_socclk_10khz; + smu->smu_table.boot_values.vclk = smu_info_v3_6->bootup_vclk_10khz; + smu->smu_table.boot_values.dclk = smu_info_v3_6->bootup_dclk_10khz; + smu->smu_table.boot_values.fclk = smu_info_v3_6->bootup_fclk_10khz; + } else if ((frev == 3) && (crev == 1)) { + return 0; + } else if ((frev == 4) && (crev == 0)) { + smu_info_v4_0 = (struct atom_smu_info_v4_0 *)header; + + smu->smu_table.boot_values.socclk = smu_info_v4_0->bootup_socclk_10khz; + smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; + smu->smu_table.boot_values.vclk = smu_info_v4_0->bootup_vclk0_10khz; + smu->smu_table.boot_values.dclk = smu_info_v4_0->bootup_dclk0_10khz; + smu->smu_table.boot_values.fclk = smu_info_v4_0->bootup_fclk_10khz; + } else { + dev_warn(smu->adev->dev, "Unexpected and unhandled version: %d.%d\n", + (uint32_t)frev, (uint32_t)crev); + } + } + + return 0; +} + + +int smu_v15_0_notify_memory_pool_location(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *memory_pool = &smu_table->memory_pool; + struct smu_msg_args args = { + .msg = SMU_MSG_DramLogSetDramAddr, + .num_args = 3, + .num_out_args = 0, + }; + + if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL) + return 0; + + /* SMU_MSG_DramLogSetDramAddr: ARG0=low, ARG1=high, ARG2=size */ + args.args[0] = lower_32_bits(memory_pool->mc_address); + args.args[1] = upper_32_bits(memory_pool->mc_address); + args.args[2] = (u32)memory_pool->size; + + return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); +} + +int smu_v15_0_set_driver_table_location(struct smu_context *smu) +{ + struct smu_table *driver_table = &smu->smu_table.driver_table; + struct smu_msg_args args = { + .msg = SMU_MSG_SetDriverDramAddr, + .num_args = 2, + .num_out_args = 0, + }; + + args.args[0] = lower_32_bits(driver_table->mc_address); + args.args[1] = upper_32_bits(driver_table->mc_address); + + return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); +} + +int smu_v15_0_set_tool_table_location(struct smu_context *smu) +{ + struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; + struct smu_msg_args args = { + .msg = SMU_MSG_SetToolsDramAddr, + .num_args = 2, + .num_out_args = 0, + }; + + /* SMU_MSG_SetToolsDramAddr: ARG0=low, ARG1=high */ + args.args[0] = lower_32_bits(tool_table->mc_address); + args.args[1] = upper_32_bits(tool_table->mc_address); + + return smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); +} + +int smu_v15_0_set_allowed_mask(struct smu_context *smu) +{ + struct smu_feature *feature = &smu->smu_feature; + int ret = 0; + uint32_t feature_mask[2]; + + if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) || + feature->feature_num < SMU_FEATURE_NUM_DEFAULT) + return -EINVAL; + + smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask); + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, + feature_mask[1], NULL); + if (ret) + return ret; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetAllowedFeaturesMaskLow, + feature_mask[0], + NULL); +} + +int smu_v15_0_gfx_off_control(struct smu_context *smu, bool enable) +{ + int ret = 0; + struct amdgpu_device *adev = smu->adev; + + switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { + case IP_VERSION(15, 0, 0): + if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) + return 0; + if (enable) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL); + else + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL); + break; + default: + break; + } + + return ret; +} + +int smu_v15_0_system_features_control(struct smu_context *smu, bool en) +{ + return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : + SMU_MSG_DisableAllSmuFeatures), NULL); +} + +int smu_v15_0_notify_display_change(struct smu_context *smu) +{ + int ret = 0; + + if (!smu->pm_enabled) + return ret; + + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && + smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); + + return ret; +} + +int smu_v15_0_get_current_power_limit(struct smu_context *smu, + uint32_t *power_limit) +{ + int power_src; + int ret = 0; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) + return -EINVAL; + + power_src = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_PWR, + smu->adev->pm.ac_power ? + SMU_POWER_SOURCE_AC : + SMU_POWER_SOURCE_DC); + if (power_src < 0) + return -EINVAL; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetPptLimit, + power_src << 16, + power_limit); + if (ret) + dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); + + return ret; +} + +int smu_v15_0_set_power_limit(struct smu_context *smu, + enum smu_ppt_limit_type limit_type, + uint32_t limit) +{ + int ret = 0; + + if (limit_type != SMU_DEFAULT_PPT_LIMIT) + return -EINVAL; + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { + dev_err(smu->adev->dev, "Setting new power limit is not supported!\n"); + return -EOPNOTSUPP; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit, NULL); + if (ret) { + dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); + return ret; + } + + smu->current_power_limit = limit; + + return 0; +} + +static int smu_v15_0_set_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned tyep, + enum amdgpu_interrupt_state state) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + uint32_t val = 0; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + + /* For MP1 SW irqs */ + if (smu->is_apu) { + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0, val); + } else { + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + } + + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* For MP1 SW irqs */ + if (smu->is_apu) { + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_15_0_0, val); + + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_15_0_0, val); + } else { + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); + + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + } + + break; + default: + break; + } + + return 0; +} + +#define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ +#define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ + +static int smu_v15_0_irq_process(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + uint32_t client_id = entry->client_id; + uint32_t src_id = entry->src_id; + + if (client_id == SOC15_IH_CLIENTID_THM) { + switch (src_id) { + case THM_11_0__SRCID__THM_DIG_THERM_L2H: + schedule_delayed_work(&smu->swctf_delayed_work, + msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY)); + break; + case THM_11_0__SRCID__THM_DIG_THERM_H2L: + dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n"); + break; + default: + dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n", + src_id); + break; + } + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs smu_v15_0_irq_funcs = { + .set = smu_v15_0_set_irq_state, + .process = smu_v15_0_irq_process, +}; + +int smu_v15_0_register_irq_handler(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct amdgpu_irq_src *irq_src = &smu->irq_source; + int ret = 0; + + if (amdgpu_sriov_vf(adev)) + return 0; + + irq_src->num_types = 1; + irq_src->funcs = &smu_v15_0_irq_funcs; + + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, + THM_11_0__SRCID__THM_DIG_THERM_L2H, + irq_src); + if (ret) + return ret; + + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, + THM_11_0__SRCID__THM_DIG_THERM_H2L, + irq_src); + if (ret) + return ret; + + ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, + SMU_IH_INTERRUPT_ID_TO_DRIVER, + irq_src); + if (ret) + return ret; + + return ret; +} + +static int smu_v15_0_wait_for_reset_complete(struct smu_context *smu, + uint64_t event_arg) +{ + int ret = 0; + + dev_dbg(smu->adev->dev, "waiting for smu reset complete\n"); + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GfxDriverResetRecovery, NULL); + + return ret; +} + +int smu_v15_0_wait_for_event(struct smu_context *smu, + enum smu_event_type event, + uint64_t event_arg) +{ + int ret = -EINVAL; + + switch (event) { + case SMU_EVENT_RESET_COMPLETE: + ret = smu_v15_0_wait_for_reset_complete(smu, event_arg); + break; + default: + break; + } + + return ret; +} + +int smu_v15_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, + uint32_t *min, uint32_t *max) +{ + int ret = 0, clk_id = 0; + uint32_t param = 0; + uint32_t clock_limit; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + clock_limit = smu->smu_table.boot_values.uclk; + break; + case SMU_GFXCLK: + case SMU_SCLK: + clock_limit = smu->smu_table.boot_values.gfxclk; + break; + case SMU_SOCCLK: + clock_limit = smu->smu_table.boot_values.socclk; + break; + default: + clock_limit = 0; + break; + } + + /* clock in Mhz unit */ + if (min) + *min = clock_limit / 100; + if (max) + *max = clock_limit / 100; + + return 0; + } + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) { + ret = -EINVAL; + goto failed; + } + param = (clk_id & 0xffff) << 16; + + if (max) { + if (smu->adev->pm.ac_power) + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetMaxDpmFreq, + param, + max); + else + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetDcModeMaxDpmFreq, + param, + max); + if (ret) + goto failed; + } + + if (min) { + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); + if (ret) + goto failed; + } + +failed: + return ret; +} + +int smu_v15_0_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max, + bool automatic) +{ + int ret = 0, clk_id = 0; + uint32_t param; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + if (max > 0) { + if (automatic) + param = (uint32_t)((clk_id << 16) | 0xffff); + else + param = (uint32_t)((clk_id << 16) | (max & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, + param, NULL); + if (ret) + goto out; + } + + if (min > 0) { + if (automatic) + param = (uint32_t)((clk_id << 16) | 0); + else + param = (uint32_t)((clk_id << 16) | (min & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, + param, NULL); + if (ret) + goto out; + } + +out: + return ret; +} + +int smu_v15_0_set_hard_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max) +{ + int ret = 0, clk_id = 0; + uint32_t param; + + if (min <= 0 && max <= 0) + return -EINVAL; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + if (max > 0) { + param = (uint32_t)((clk_id << 16) | (max & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, + param, NULL); + if (ret) + return ret; + } + + if (min > 0) { + param = (uint32_t)((clk_id << 16) | (min & 0xffff)); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, + param, NULL); + if (ret) + return ret; + } + + return ret; +} + +int smu_v15_0_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct smu_15_0_dpm_context *dpm_context = + smu->smu_dpm.dpm_context; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table; + struct smu_dpm_table *vclk_table = &dpm_context->dpm_tables.vclk_table; + struct smu_dpm_table *dclk_table = &dpm_context->dpm_tables.dclk_table; + struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table; + struct smu_umd_pstate_table *pstate_table = + &smu->pstate_table; + struct amdgpu_device *adev = smu->adev; + uint32_t sclk_min = 0, sclk_max = 0; + uint32_t mclk_min = 0, mclk_max = 0; + uint32_t socclk_min = 0, socclk_max = 0; + uint32_t vclk_min = 0, vclk_max = 0; + uint32_t dclk_min = 0, dclk_max = 0; + uint32_t fclk_min = 0, fclk_max = 0; + int ret = 0, i; + bool auto_level = false; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MAX(fclk_table); + break; + case AMD_DPM_FORCED_LEVEL_LOW: + sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table); + mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table); + socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table); + vclk_min = vclk_max = SMU_DPM_TABLE_MIN(vclk_table); + dclk_min = dclk_max = SMU_DPM_TABLE_MIN(dclk_table); + fclk_min = fclk_max = SMU_DPM_TABLE_MIN(fclk_table); + break; + case AMD_DPM_FORCED_LEVEL_AUTO: + sclk_min = SMU_DPM_TABLE_MIN(gfx_table); + sclk_max = SMU_DPM_TABLE_MAX(gfx_table); + mclk_min = SMU_DPM_TABLE_MIN(mem_table); + mclk_max = SMU_DPM_TABLE_MAX(mem_table); + socclk_min = SMU_DPM_TABLE_MIN(soc_table); + socclk_max = SMU_DPM_TABLE_MAX(soc_table); + vclk_min = SMU_DPM_TABLE_MIN(vclk_table); + vclk_max = SMU_DPM_TABLE_MAX(vclk_table); + dclk_min = SMU_DPM_TABLE_MIN(dclk_table); + dclk_max = SMU_DPM_TABLE_MAX(dclk_table); + fclk_min = SMU_DPM_TABLE_MIN(fclk_table); + fclk_max = SMU_DPM_TABLE_MAX(fclk_table); + auto_level = true; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: + sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; + mclk_min = mclk_max = pstate_table->uclk_pstate.standard; + socclk_min = socclk_max = pstate_table->socclk_pstate.standard; + vclk_min = vclk_max = pstate_table->vclk_pstate.standard; + dclk_min = dclk_max = pstate_table->dclk_pstate.standard; + fclk_min = fclk_max = pstate_table->fclk_pstate.standard; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: + sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: + mclk_min = mclk_max = pstate_table->uclk_pstate.min; + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: + sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; + mclk_min = mclk_max = pstate_table->uclk_pstate.peak; + socclk_min = socclk_max = pstate_table->socclk_pstate.peak; + vclk_min = vclk_max = pstate_table->vclk_pstate.peak; + dclk_min = dclk_max = pstate_table->dclk_pstate.peak; + fclk_min = fclk_max = pstate_table->fclk_pstate.peak; + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: + return 0; + default: + dev_err(adev->dev, "Invalid performance level %d\n", level); + return -EINVAL; + } + + if (sclk_min && sclk_max) { + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_GFXCLK, + sclk_min, + sclk_max, + auto_level); + if (ret) + return ret; + + pstate_table->gfxclk_pstate.curr.min = sclk_min; + pstate_table->gfxclk_pstate.curr.max = sclk_max; + } + + if (mclk_min && mclk_max) { + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_MCLK, + mclk_min, + mclk_max, + auto_level); + if (ret) + return ret; + + pstate_table->uclk_pstate.curr.min = mclk_min; + pstate_table->uclk_pstate.curr.max = mclk_max; + } + + if (socclk_min && socclk_max) { + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_SOCCLK, + socclk_min, + socclk_max, + auto_level); + if (ret) + return ret; + + pstate_table->socclk_pstate.curr.min = socclk_min; + pstate_table->socclk_pstate.curr.max = socclk_max; + } + + if (vclk_min && vclk_max) { + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + ret = smu_v15_0_set_soft_freq_limited_range(smu, + i ? SMU_VCLK1 : SMU_VCLK, + vclk_min, + vclk_max, + auto_level); + if (ret) + return ret; + } + pstate_table->vclk_pstate.curr.min = vclk_min; + pstate_table->vclk_pstate.curr.max = vclk_max; + } + + if (dclk_min && dclk_max) { + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + ret = smu_v15_0_set_soft_freq_limited_range(smu, + i ? SMU_DCLK1 : SMU_DCLK, + dclk_min, + dclk_max, + auto_level); + if (ret) + return ret; + } + pstate_table->dclk_pstate.curr.min = dclk_min; + pstate_table->dclk_pstate.curr.max = dclk_max; + } + + if (fclk_min && fclk_max) { + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_FCLK, + fclk_min, + fclk_max, + auto_level); + if (ret) + return ret; + + pstate_table->fclk_pstate.curr.min = fclk_min; + pstate_table->fclk_pstate.curr.max = fclk_max; + } + + return ret; +} + +int smu_v15_0_set_power_source(struct smu_context *smu, + enum smu_power_src_type power_src) +{ + int pwr_source; + + pwr_source = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_PWR, + (uint32_t)power_src); + if (pwr_source < 0) + return -EINVAL; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_NotifyPowerSource, + pwr_source, + NULL); +} + +static int smu_v15_0_get_dpm_freq_by_index(struct smu_context *smu, + enum smu_clk_type clk_type, + uint16_t level, + uint32_t *value) +{ + int ret = 0, clk_id = 0; + uint32_t param; + + if (!value) + return -EINVAL; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetDpmFreqByIndex, + param, + value); + if (ret) + return ret; + + *value = *value & 0x7fffffff; + + return ret; +} + +static int smu_v15_0_get_dpm_level_count(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + int ret; + + ret = smu_v15_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value); + + return ret; +} + +static int smu_v15_0_get_fine_grained_status(struct smu_context *smu, + enum smu_clk_type clk_type, + bool *is_fine_grained_dpm) +{ + int ret = 0, clk_id = 0; + uint32_t param; + uint32_t value; + + if (!is_fine_grained_dpm) + return -EINVAL; + + if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) + return 0; + + clk_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_CLK, + clk_type); + if (clk_id < 0) + return clk_id; + + param = (uint32_t)(((clk_id & 0xffff) << 16) | 0xff); + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_GetDpmFreqByIndex, + param, + &value); + if (ret) + return ret; + + /* + * BIT31: 1 - Fine grained DPM, 0 - Dicrete DPM + * now, we un-support it + */ + *is_fine_grained_dpm = value & 0x80000000; + + return 0; +} + +int smu_v15_0_set_single_dpm_table(struct smu_context *smu, + enum smu_clk_type clk_type, + struct smu_dpm_table *single_dpm_table) +{ + int ret = 0; + uint32_t clk; + bool is_fine_grained; + int i; + + ret = smu_v15_0_get_dpm_level_count(smu, + clk_type, + &single_dpm_table->count); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__); + return ret; + } + + ret = smu_v15_0_get_fine_grained_status(smu, + clk_type, + &is_fine_grained); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get fine grained status!\n", __func__); + return ret; + } + + if (is_fine_grained) + single_dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED; + + for (i = 0; i < single_dpm_table->count; i++) { + ret = smu_v15_0_get_dpm_freq_by_index(smu, + clk_type, + i, + &clk); + if (ret) { + dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__); + return ret; + } + + single_dpm_table->dpm_levels[i].value = clk; + single_dpm_table->dpm_levels[i].enabled = true; + } + + return 0; +} + +int smu_v15_0_set_vcn_enable(struct smu_context *smu, + bool enable, + int inst) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (adev->vcn.harvest_config & (1 << inst)) + return ret; + + if (smu->is_apu) { + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? + SMU_MSG_PowerUpVcn : SMU_MSG_PowerDownVcn, + inst << 16U, NULL); + } + + return ret; +} + +int smu_v15_0_set_jpeg_enable(struct smu_context *smu, + bool enable) +{ + struct amdgpu_device *adev = smu->adev; + int i, ret = 0; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { + if (adev->jpeg.harvest_config & (1 << i)) + continue; + + if (smu->is_apu) { + ret = smu_cmn_send_smc_msg_with_param(smu, enable ? + SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg, + i << 16U, NULL); + } + + if (ret) + return ret; + } + + return ret; +} + +int smu_v15_0_run_btc(struct smu_context *smu) +{ + int res; + + res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); + if (res) + dev_err(smu->adev->dev, "RunDcBtc failed!\n"); + + return res; +} + +int smu_v15_0_gpo_control(struct smu_context *smu, + bool enablement) +{ + int res; + + res = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_AllowGpo, + enablement ? 1 : 0, + NULL); + if (res) + dev_err(smu->adev->dev, "SetGpoAllow %d failed!\n", enablement); + + return res; +} + +int smu_v15_0_deep_sleep_control(struct smu_context *smu, + bool enablement) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + return ret; +} + +int smu_v15_0_gfx_ulv_control(struct smu_context *smu, + bool enablement) +{ + int ret = 0; + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); + + return ret; +} + +int smu_v15_0_baco_set_armd3_sequence(struct smu_context *smu, + enum smu_baco_seq baco_seq) +{ + struct smu_baco_context *smu_baco = &smu->smu_baco; + int ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_ArmD3, + baco_seq, + NULL); + if (ret) + return ret; + + if (baco_seq == BACO_SEQ_BAMACO || + baco_seq == BACO_SEQ_BACO) + smu_baco->state = SMU_BACO_STATE_ENTER; + else + smu_baco->state = SMU_BACO_STATE_EXIT; + + return 0; +} + +int smu_v15_0_get_bamaco_support(struct smu_context *smu) +{ + struct smu_baco_context *smu_baco = &smu->smu_baco; + int bamaco_support = 0; + + if (amdgpu_sriov_vf(smu->adev) || + !smu_baco->platform_support) + return 0; + + if (smu_baco->maco_support) + bamaco_support |= MACO_SUPPORT; + + /* return true if ASIC is in BACO state already */ + if (smu_v15_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER) + return (bamaco_support |= BACO_SUPPORT); + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && + !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) + return 0; + + return (bamaco_support |= BACO_SUPPORT); +} + +enum smu_baco_state smu_v15_0_baco_get_state(struct smu_context *smu) +{ + struct smu_baco_context *smu_baco = &smu->smu_baco; + + return smu_baco->state; +} + +int smu_v15_0_baco_set_state(struct smu_context *smu, + enum smu_baco_state state) +{ + struct smu_baco_context *smu_baco = &smu->smu_baco; + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (smu_v15_0_baco_get_state(smu) == state) + return 0; + + if (state == SMU_BACO_STATE_ENTER) { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_EnterBaco, + (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO) ? + BACO_SEQ_BAMACO : BACO_SEQ_BACO, + NULL); + } else { + ret = smu_cmn_send_smc_msg(smu, + SMU_MSG_ExitBaco, + NULL); + if (ret) + return ret; + + /* clear vbios scratch 6 and 7 for coming asic reinit */ + WREG32(adev->bios_scratch_reg_offset + 6, 0); + WREG32(adev->bios_scratch_reg_offset + 7, 0); + } + + if (!ret) + smu_baco->state = state; + + return ret; +} + +int smu_v15_0_baco_enter(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_v15_0_baco_set_state(smu, + SMU_BACO_STATE_ENTER); + if (ret) + return ret; + + msleep(10); + + return ret; +} + +int smu_v15_0_baco_exit(struct smu_context *smu) +{ + return smu_v15_0_baco_set_state(smu, + SMU_BACO_STATE_EXIT); +} + +int smu_v15_0_set_gfx_power_up_by_imu(struct smu_context *smu) +{ + struct smu_msg_ctl *ctl = &smu->msg_ctl; + struct amdgpu_device *adev = smu->adev; + int ret; + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnableGfxImu, + ENABLE_IMU_ARG_GFXOFF_ENABLE, NULL); + } + + mutex_lock(&ctl->lock); + ret = smu_msg_send_async_locked(ctl, SMU_MSG_EnableGfxImu, + ENABLE_IMU_ARG_GFXOFF_ENABLE); + mutex_unlock(&ctl->lock); + + return ret; +} + +int smu_v15_0_od_edit_dpm_table(struct smu_context *smu, + enum PP_OD_DPM_TABLE_COMMAND type, + long input[], uint32_t size) +{ + struct smu_dpm_context *smu_dpm = &(smu->smu_dpm); + int ret = 0; + + /* Only allowed in manual mode */ + if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_OD_EDIT_SCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } + + if (input[0] == 0) { + if (input[1] < smu->gfx_default_hard_min_freq) { + dev_warn(smu->adev->dev, + "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", + input[1], smu->gfx_default_hard_min_freq); + return -EINVAL; + } + smu->gfx_actual_hard_min_freq = input[1]; + } else if (input[0] == 1) { + if (input[1] > smu->gfx_default_soft_max_freq) { + dev_warn(smu->adev->dev, + "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", + input[1], smu->gfx_default_soft_max_freq); + return -EINVAL; + } + smu->gfx_actual_soft_max_freq = input[1]; + } else { + return -EINVAL; + } + break; + case PP_OD_RESTORE_DEFAULT_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } + smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq; + smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq; + break; + case PP_OD_COMMIT_DPM_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, "Input parameter number not correct\n"); + return -EINVAL; + } + if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) { + dev_err(smu->adev->dev, + "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", + smu->gfx_actual_hard_min_freq, + smu->gfx_actual_soft_max_freq); + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk, + smu->gfx_actual_hard_min_freq, + NULL); + if (ret) { + dev_err(smu->adev->dev, "Set hard min sclk failed!"); + return ret; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, + smu->gfx_actual_soft_max_freq, + NULL); + if (ret) { + dev_err(smu->adev->dev, "Set soft max sclk failed!"); + return ret; + } + break; + default: + return -ENOSYS; + } + + return ret; +} + +static int smu_v15_0_allow_ih_interrupt(struct smu_context *smu) +{ + return smu_cmn_send_smc_msg(smu, + SMU_MSG_AllowIHHostInterrupt, + NULL); +} + +int smu_v15_0_enable_thermal_alert(struct smu_context *smu) +{ + int ret = 0; + + if (!smu->irq_source.num_types) + return 0; + + ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); + if (ret) + return ret; + + return smu_v15_0_allow_ih_interrupt(smu); +} + +int smu_v15_0_disable_thermal_alert(struct smu_context *smu) +{ + if (!smu->irq_source.num_types) + return 0; + + return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c new file mode 100644 index 0000000000000..9a4a5f482e75c --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.c @@ -0,0 +1,1474 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "smu_types.h" +#define SWSMU_CODE_LAYER_L2 + +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "smu_v15_0.h" +#include "smu15_driver_if_v15_0_0.h" +#include "smu_v15_0_0_ppt.h" +#include "smu_v15_0_0_ppsmc.h" +#include "smu_v15_0_0_pmfw.h" +#include "smu_cmn.h" + +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +#define mmMP1_SMN_C2PMSG_30 0x005e +#define mmMP1_SMN_C2PMSG_30_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_31 0x005f +#define mmMP1_SMN_C2PMSG_31_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_32 0x0060 +#define mmMP1_SMN_C2PMSG_32_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_33 0x0061 +#define mmMP1_SMN_C2PMSG_33_BASE_IDX 1 + +#define mmMP1_SMN_C2PMSG_34 0x0062 +#define mmMP1_SMN_C2PMSG_34_BASE_IDX 1 + +#define SMU_15_0_UMD_PSTATE_GFXCLK 700 +#define SMU_15_0_UMD_PSTATE_SOCCLK 678 +#define SMU_15_0_UMD_PSTATE_FCLK 1800 + + +static const struct smu_feature_bits smu_v15_0_0_dpm_features = { + .bits = { + SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_ISP_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_NPU_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT), + SMU_FEATURE_BIT_INIT(FEATURE_VPE_DPM_BIT) + } +}; + +enum smu_mall_pg_config { + SMU_MALL_PG_CONFIG_PMFW_CONTROL = 0, + SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_ON = 1, + SMU_MALL_PG_CONFIG_DRIVER_CONTROL_ALWAYS_OFF = 2, +}; + +static struct cmn2asic_msg_mapping smu_v15_0_0_message_map[SMU_MSG_MAX_COUNT] = { + MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1), + MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1), + MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), + MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1), + MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1), + MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 1), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1), + MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1), + MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1), + MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), + MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 1), + MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1), + MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1), + MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1), + MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1), + MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), + MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1), + MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1), + MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1), + MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1), + MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1), + MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1), + MSG_MAP(AllowZstates, PPSMC_MSG_AllowZstates, 1), + MSG_MAP(GetSmartShiftStatus, PPSMC_MSG_GetSmartShiftStatus, 1), + MSG_MAP(PowerUpUmsch, PPSMC_MSG_PowerUpUmsch, 1), + MSG_MAP(PowerDownUmsch, PPSMC_MSG_PowerDownUmsch, 1), + MSG_MAP(PowerUpVpe, PPSMC_MSG_PowerUpVpe, 1), + MSG_MAP(PowerDownVpe, PPSMC_MSG_PowerDownVpe, 1), + MSG_MAP(EnableLSdma, PPSMC_MSG_EnableLSdma, 1), + MSG_MAP(DisableLSdma, PPSMC_MSG_DisableLSdma, 1), + MSG_MAP(SetSoftMaxVpe, PPSMC_MSG_SetSoftMaxVpe, 1), + MSG_MAP(SetSoftMinVpe, PPSMC_MSG_SetSoftMinVpe, 1), +}; + +static struct cmn2asic_mapping smu_v15_0_0_feature_mask_map[SMU_FEATURE_COUNT] = { + FEA_MAP(CCLK_DPM), + FEA_MAP(FAN_CONTROLLER), + FEA_MAP(PPT), + FEA_MAP(TDC), + FEA_MAP(THERMAL), + FEA_MAP(VCN_DPM), + FEA_MAP_REVERSE(FCLK), + FEA_MAP_REVERSE(SOCCLK), + FEA_MAP(LCLK_DPM), + FEA_MAP(SHUBCLK_DPM), + FEA_MAP(DCFCLK_DPM), + FEA_MAP_HALF_REVERSE(GFX), + FEA_MAP(DS_GFXCLK), + FEA_MAP(DS_SOCCLK), + FEA_MAP(DS_LCLK), + FEA_MAP(LOW_POWER_DCNCLKS), + FEA_MAP(DS_FCLK), + FEA_MAP(DS_MP1CLK), + FEA_MAP(PSI), + FEA_MAP(PROCHOT), + FEA_MAP(CPUOFF), + FEA_MAP(STAPM), + FEA_MAP(S0I3), + FEA_MAP(PERF_LIMIT), + FEA_MAP(CORE_DLDO), + FEA_MAP(DS_VCN), + FEA_MAP(CPPC), + FEA_MAP(DF_CSTATES), + FEA_MAP(ATHUB_PG), +}; + +static struct cmn2asic_mapping smu_v15_0_0_table_map[SMU_TABLE_COUNT] = { + TAB_MAP_VALID(WATERMARKS), + TAB_MAP_VALID(SMU_METRICS), + TAB_MAP_VALID(CUSTOM_DPM), + TAB_MAP_VALID(DPMCLOCKS), +}; + +static int smu_v15_0_0_init_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + int ret; + + SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); + if (!smu_table->metrics_table) + goto err0_out; + smu_table->metrics_time = 0; + + smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL); + if (!smu_table->clocks_table) + goto err1_out; + + smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL); + if (!smu_table->watermarks_table) + goto err2_out; + + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct gpu_metrics_v3_0), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) + goto err3_out; + + return 0; + +err3_out: + kfree(smu_table->watermarks_table); +err2_out: + kfree(smu_table->clocks_table); +err1_out: + kfree(smu_table->metrics_table); +err0_out: + return -ENOMEM; +} + +static int smu_v15_0_0_fini_smc_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + kfree(smu_table->clocks_table); + smu_table->clocks_table = NULL; + + kfree(smu_table->metrics_table); + smu_table->metrics_table = NULL; + + kfree(smu_table->watermarks_table); + smu_table->watermarks_table = NULL; + + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS); + + return 0; +} + +static int smu_v15_0_0_system_features_control(struct smu_context *smu, bool en) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (!en && !adev->in_s0ix) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); + + return ret; +} + +static int smu_v15_0_0_update_table(struct smu_context *smu, + enum smu_table_id table_index, + int argument, + void *table_data, + bool drv2smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct amdgpu_device *adev = smu->adev; + struct smu_table *table = &smu_table->driver_table; + int table_id = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_TABLE, + table_index); + uint64_t address; + uint32_t table_size; + int ret; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + if (!table_data || table_index >= SMU_TABLE_COUNT || table_id < 0) + return -EINVAL; + + table_size = smu_table->tables[table_index].size; + + if (drv2smu) { + memcpy(table->cpu_addr, table_data, table_size); + /* + * Flush hdp cache: to guard the content seen by + * GPU is consitent with CPU. + */ + amdgpu_hdp_flush(adev, NULL); + } + + address = table->mc_address; + + struct smu_msg_args args = { + .msg = drv2smu ? + SMU_MSG_TransferTableDram2Smu : + SMU_MSG_TransferTableSmu2Dram, + .num_args = 3, + .num_out_args = 0, + }; + + args.args[0] = table_id; + args.args[1] = (uint32_t)lower_32_bits(address); + args.args[2] = (uint32_t)upper_32_bits(address); + + ret = ctl->ops->send_msg(ctl, &args); + + if (ret) + return ret; + + if (!drv2smu) { + amdgpu_hdp_invalidate(adev, NULL); + memcpy(table_data, table->cpu_addr, table_size); + } + + return 0; +} + +static int smu_v15_0_0_set_default_dpm_tables(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + return smu_v15_0_0_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, + smu_table->clocks_table, false); +} + +static int smu_v15_0_0_get_metrics_table(struct smu_context *smu, + void *metrics_table, + bool bypass_cache) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = + smu_table->tables[SMU_TABLE_SMU_METRICS].size; + int ret; + + if (bypass_cache || + !smu_table->metrics_time || + time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) { + ret = smu_v15_0_0_update_table(smu, + SMU_TABLE_SMU_METRICS, + 0, + smu_table->metrics_table, + false); + if (ret) { + dev_info(smu->adev->dev, "Failed to export SMU15_0_0 metrics table!\n"); + return ret; + } + smu_table->metrics_time = jiffies; + } + + if (metrics_table) + memcpy(metrics_table, smu_table->metrics_table, table_size); + + return 0; +} + +static int smu_v15_0_0_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; + int ret = 0; + + ret = smu_v15_0_0_get_metrics_table(smu, NULL, false); + if (ret) + return ret; + + switch (member) { + case METRICS_AVERAGE_GFXCLK: + *value = metrics->GfxclkFrequency; + break; + case METRICS_AVERAGE_SOCCLK: + *value = metrics->SocclkFrequency; + break; + case METRICS_AVERAGE_VCLK: + *value = metrics->VclkFrequency; + break; + case METRICS_AVERAGE_DCLK: + *value = 0; + break; + case METRICS_AVERAGE_UCLK: + *value = metrics->MemclkFrequency; + break; + case METRICS_AVERAGE_FCLK: + *value = metrics->FclkFrequency; + break; + case METRICS_AVERAGE_VPECLK: + *value = metrics->VpeclkFrequency; + break; + case METRICS_AVERAGE_NPUCLK: + *value = metrics->NpuclkFrequency; + break; + case METRICS_AVERAGE_GFXACTIVITY: + if ((smu->smc_fw_version > 0x5d4600)) + *value = metrics->GfxActivity; + else + *value = metrics->GfxActivity / 100; + break; + case METRICS_AVERAGE_VCNACTIVITY: + *value = metrics->VcnActivity / 100; + break; + case METRICS_AVERAGE_SOCKETPOWER: + case METRICS_CURR_SOCKETPOWER: + *value = (metrics->SocketPower / 1000 << 8) + + (metrics->SocketPower % 1000 / 10); + break; + case METRICS_TEMPERATURE_EDGE: + *value = metrics->GfxTemperature / 100 * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = metrics->SocTemperature / 100 * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_THROTTLER_RESIDENCY_PROCHOT: + *value = metrics->ThrottleResidency_PROCHOT; + break; + case METRICS_THROTTLER_RESIDENCY_SPL: + *value = metrics->ThrottleResidency_SPL; + break; + case METRICS_THROTTLER_RESIDENCY_FPPT: + *value = metrics->ThrottleResidency_FPPT; + break; + case METRICS_THROTTLER_RESIDENCY_SPPT: + *value = metrics->ThrottleResidency_SPPT; + break; + case METRICS_THROTTLER_RESIDENCY_THM_SOC: + *value = metrics->ThrottleResidency_THM_SOC; + break; + case METRICS_VOLTAGE_VDDGFX: + *value = 0; + break; + case METRICS_VOLTAGE_VDDSOC: + *value = 0; + break; + case METRICS_SS_APU_SHARE: + /* return the percentage of APU power with respect to APU's power limit. + * percentage is reported, this isn't boost value. Smartshift power + * boost/shift is only when the percentage is more than 100. + */ + if (metrics->StapmOpnLimit > 0) + *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit; + else + *value = 0; + break; + case METRICS_SS_DGPU_SHARE: + /* return the percentage of dGPU power with respect to dGPU's power limit. + * percentage is reported, this isn't boost value. Smartshift power + * boost/shift is only when the percentage is more than 100. + */ + if ((metrics->dGpuPower > 0) && + (metrics->StapmCurrentLimit > metrics->StapmOpnLimit)) + *value = (metrics->dGpuPower * 100) / + (metrics->StapmCurrentLimit - metrics->StapmOpnLimit); + else + *value = 0; + break; + default: + *value = UINT_MAX; + break; + } + + return ret; +} + +static int smu_v15_0_0_read_sensor(struct smu_context *smu, + enum amd_pp_sensors sensor, + void *data, uint32_t *size) +{ + int ret = 0; + + if (!data || !size) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXACTIVITY, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_VCN_LOAD: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_AVERAGE_VCNACTIVITY, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_AVG_POWER: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_AVERAGE_SOCKETPOWER, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_CURR_SOCKETPOWER, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_EDGE_TEMP: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_EDGE, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_HOTSPOT, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_AVERAGE_UCLK, + (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_SCLK: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXCLK, + (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDGFX: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_VOLTAGE_VDDGFX, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDNB: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_VOLTAGE_VDDSOC, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_SS_APU_SHARE: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_SS_APU_SHARE, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_SS_DGPU_SHARE: + ret = smu_v15_0_0_get_smu_metrics_data(smu, + METRICS_SS_DGPU_SHARE, + (uint32_t *)data); + *size = 4; + break; + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu, + struct smu_feature_bits *feature_mask) +{ + int ret; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + if (!feature_mask) + return -EINVAL; + + struct smu_msg_args args = { + .msg = SMU_MSG_GetEnabledSmuFeatures, + .num_args = 0, + .num_out_args = 2, + }; + + ret = ctl->ops->send_msg(ctl, &args); + + if (!ret) + smu_feature_bits_from_arr32(feature_mask, args.out_args, + SMU_FEATURE_NUM_DEFAULT); + + return ret; +} + +static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu) +{ + int ret = 0; + struct smu_feature_bits feature_enabled; + + ret = smu_v15_0_0_get_enabled_mask(smu, &feature_enabled); + + if (ret) + return false; + + return smu_feature_bits_test_mask(&feature_enabled, + smu_v15_0_0_dpm_features.bits); +} + +static int smu_v15_0_0_set_watermarks_table(struct smu_context *smu, + struct pp_smu_wm_range_sets *clock_ranges) +{ + int i; + int ret = 0; + Watermarks_t *table = smu->smu_table.watermarks_table; + + if (!table || !clock_ranges) + return -EINVAL; + + if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES || + clock_ranges->num_writer_wm_sets > NUM_WM_RANGES) + return -EINVAL; + + for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) { + table->WatermarkRow[WM_DCFCLK][i].MinClock = + clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; + table->WatermarkRow[WM_DCFCLK][i].MaxClock = + clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; + table->WatermarkRow[WM_DCFCLK][i].MinMclk = + clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; + table->WatermarkRow[WM_DCFCLK][i].MaxMclk = + clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; + + table->WatermarkRow[WM_DCFCLK][i].WmSetting = + clock_ranges->reader_wm_sets[i].wm_inst; + } + + for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) { + table->WatermarkRow[WM_SOCCLK][i].MinClock = + clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; + table->WatermarkRow[WM_SOCCLK][i].MaxClock = + clock_ranges->writer_wm_sets[i].max_fill_clk_mhz; + table->WatermarkRow[WM_SOCCLK][i].MinMclk = + clock_ranges->writer_wm_sets[i].min_drain_clk_mhz; + table->WatermarkRow[WM_SOCCLK][i].MaxMclk = + clock_ranges->writer_wm_sets[i].max_drain_clk_mhz; + + table->WatermarkRow[WM_SOCCLK][i].WmSetting = + clock_ranges->writer_wm_sets[i].wm_inst; + } + + smu->watermarks_bitmap |= WATERMARKS_EXIST; + + /* pass data to smu controller */ + if ((smu->watermarks_bitmap & WATERMARKS_EXIST) && + !(smu->watermarks_bitmap & WATERMARKS_LOADED)) { + ret = smu_cmn_write_watermarks_table(smu); + if (ret) { + dev_err(smu->adev->dev, "Failed to update WMTABLE!"); + return ret; + } + smu->watermarks_bitmap |= WATERMARKS_LOADED; + } + + return 0; +} + +static ssize_t smu_v15_0_0_get_gpu_metrics(struct smu_context *smu, + void **table) +{ + struct gpu_metrics_v3_0 *gpu_metrics = + (struct gpu_metrics_v3_0 *)smu_driver_table_ptr( + smu, SMU_DRIVER_TABLE_GPU_METRICS); + SmuMetrics_t metrics; + int ret = 0; + + ret = smu_v15_0_0_get_metrics_table(smu, &metrics, false); + if (ret) + return ret; + + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 3, 0); + + gpu_metrics->temperature_gfx = metrics.GfxTemperature; + gpu_metrics->temperature_soc = metrics.SocTemperature; + memcpy(&gpu_metrics->temperature_core[0], + &metrics.CoreTemperature[0], + sizeof(uint16_t) * 16); + gpu_metrics->temperature_skin = metrics.SkinTemp; + + gpu_metrics->average_gfx_activity = metrics.GfxActivity; + gpu_metrics->average_vcn_activity = metrics.VcnActivity; + + memcpy(&gpu_metrics->average_core_c0_activity[0], + &metrics.CoreC0Residency[0], + sizeof(uint16_t) * 16); + gpu_metrics->average_dram_reads = metrics.DRAMReads; + gpu_metrics->average_dram_writes = metrics.DRAMWrites; + + gpu_metrics->average_socket_power = metrics.SocketPower; + gpu_metrics->average_apu_power = metrics.ApuPower; + gpu_metrics->average_gfx_power = metrics.GfxPower; + gpu_metrics->average_dgpu_power = metrics.dGpuPower; + gpu_metrics->average_all_core_power = metrics.AllCorePower; + gpu_metrics->average_sys_power = metrics.Psys; + memcpy(&gpu_metrics->average_core_power[0], + &metrics.CorePower[0], + sizeof(uint16_t) * 16); + + gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency; + gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency; + gpu_metrics->average_vpeclk_frequency = metrics.VpeclkFrequency; + gpu_metrics->average_fclk_frequency = metrics.FclkFrequency; + gpu_metrics->average_vclk_frequency = metrics.VclkFrequency; + gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency; + + memcpy(&gpu_metrics->current_coreclk[0], + &metrics.CoreFrequency[0], + sizeof(uint16_t) * 16); + gpu_metrics->current_core_maxfreq = metrics.InfrastructureCpuMaxFreq; + gpu_metrics->current_gfx_maxfreq = metrics.InfrastructureGfxMaxFreq; + + gpu_metrics->throttle_residency_prochot = metrics.ThrottleResidency_PROCHOT; + gpu_metrics->throttle_residency_spl = metrics.ThrottleResidency_SPL; + gpu_metrics->throttle_residency_fppt = metrics.ThrottleResidency_FPPT; + gpu_metrics->throttle_residency_sppt = metrics.ThrottleResidency_SPPT; + gpu_metrics->throttle_residency_thm_soc = metrics.ThrottleResidency_THM_SOC; + + gpu_metrics->time_filter_alphavalue = metrics.FilterAlphaValue; + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + *table = (void *)gpu_metrics; + + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + + return sizeof(struct gpu_metrics_v3_0); +} + +static int smu_v15_0_0_mode2_reset(struct smu_context *smu) +{ + int ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset, + SMU_RESET_MODE_2, NULL); + + if (ret) + dev_err(smu->adev->dev, "Failed to mode2 reset!\n"); + + return ret; +} + +static int smu_v15_0_0_get_dpm_freq_by_index(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t dpm_level, + uint32_t *freq) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + + if (!clk_table || clk_type >= SMU_CLK_COUNT) + return -EINVAL; + + switch (clk_type) { + case SMU_SOCCLK: + if (dpm_level >= clk_table->NumSocClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->SocClocks[dpm_level]; + break; + case SMU_VCLK: + if (dpm_level >= clk_table->VcnClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->VClocks[dpm_level]; + break; + case SMU_DCLK: + if (dpm_level >= clk_table->VcnClkLevelsEnabled) + return -EINVAL; + *freq = clk_table->DClocks[dpm_level]; + break; + case SMU_UCLK: + case SMU_MCLK: + if (dpm_level >= clk_table->NumMemPstatesEnabled) + return -EINVAL; + *freq = clk_table->MemPstateTable[dpm_level].MemClk; + break; + case SMU_FCLK: + if (dpm_level >= clk_table->NumFclkLevelsEnabled) + return -EINVAL; + *freq = clk_table->FclkClocks_Freq[dpm_level]; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int smu_v15_0_common_get_dpm_freq_by_index(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t dpm_level, + uint32_t *freq) +{ + smu_v15_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq); + + return 0; +} + +static bool smu_v15_0_0_clk_dpm_is_enabled(struct smu_context *smu, + enum smu_clk_type clk_type) +{ + enum smu_feature_mask feature_id = 0; + + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + case SMU_FCLK: + feature_id = SMU_FEATURE_DPM_FCLK_BIT; + break; + case SMU_GFXCLK: + case SMU_SCLK: + feature_id = SMU_FEATURE_DPM_GFXCLK_BIT; + break; + case SMU_SOCCLK: + feature_id = SMU_FEATURE_DPM_SOCCLK_BIT; + break; + case SMU_VCLK: + case SMU_DCLK: + case SMU_VCLK1: + case SMU_DCLK1: + feature_id = SMU_FEATURE_VCN_DPM_BIT; + break; + default: + return true; + } + + return smu_cmn_feature_is_enabled(smu, feature_id); +} + +static int smu_v15_0_0_get_dpm_ultimate_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min, + uint32_t *max) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + uint32_t clock_limit; + uint32_t max_dpm_level, min_dpm_level; + int ret = 0; + + if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type)) { + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + clock_limit = smu->smu_table.boot_values.uclk; + break; + case SMU_FCLK: + clock_limit = smu->smu_table.boot_values.fclk; + break; + case SMU_GFXCLK: + case SMU_SCLK: + clock_limit = smu->smu_table.boot_values.gfxclk; + break; + case SMU_SOCCLK: + clock_limit = smu->smu_table.boot_values.socclk; + break; + case SMU_VCLK: + clock_limit = smu->smu_table.boot_values.vclk; + break; + case SMU_DCLK: + clock_limit = smu->smu_table.boot_values.dclk; + break; + default: + clock_limit = 0; + break; + } + + /* clock in Mhz unit */ + if (min) + *min = clock_limit / 100; + if (max) + *max = clock_limit / 100; + + return 0; + } + + if (max) { + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + *max = clk_table->MaxGfxClk; + break; + case SMU_MCLK: + case SMU_UCLK: + max_dpm_level = 0; + break; + case SMU_FCLK: + max_dpm_level = clk_table->NumFclkLevelsEnabled - 1; + break; + case SMU_SOCCLK: + max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1; + break; + case SMU_VCLK: + case SMU_DCLK: + max_dpm_level = clk_table->VcnClkLevelsEnabled - 1; + break; + default: + ret = -EINVAL; + goto failed; + } + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { + ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max); + if (ret) + goto failed; + } + } + + if (min) { + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + *min = clk_table->MinGfxClk; + break; + case SMU_MCLK: + case SMU_UCLK: + min_dpm_level = clk_table->NumMemPstatesEnabled - 1; + break; + case SMU_FCLK: + min_dpm_level = 0; + break; + case SMU_SOCCLK: + min_dpm_level = 0; + break; + case SMU_VCLK: + case SMU_DCLK: + min_dpm_level = 0; + break; + default: + ret = -EINVAL; + goto failed; + } + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { + ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min); + if (ret) + goto failed; + } + } + +failed: + return ret; +} + +static int smu_v15_0_common_get_dpm_ultimate_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min, + uint32_t *max) +{ + if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1) + smu_v15_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max); + + return 0; +} + +static int smu_v15_0_0_get_current_clk_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + MetricsMember_t member_type; + + switch (clk_type) { + case SMU_SOCCLK: + member_type = METRICS_AVERAGE_SOCCLK; + break; + case SMU_VCLK: + member_type = METRICS_AVERAGE_VCLK; + break; + case SMU_VCLK1: + member_type = METRICS_AVERAGE_VCLK1; + break; + case SMU_DCLK: + member_type = METRICS_AVERAGE_DCLK; + break; + case SMU_DCLK1: + member_type = METRICS_AVERAGE_DCLK1; + break; + case SMU_MCLK: + member_type = METRICS_AVERAGE_UCLK; + break; + case SMU_FCLK: + member_type = METRICS_AVERAGE_FCLK; + break; + case SMU_GFXCLK: + case SMU_SCLK: + member_type = METRICS_AVERAGE_GFXCLK; + break; + default: + return -EINVAL; + } + + return smu_v15_0_0_get_smu_metrics_data(smu, member_type, value); +} + +static int smu_v15_0_0_get_dpm_level_count(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *count) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + + switch (clk_type) { + case SMU_SOCCLK: + *count = clk_table->NumSocClkLevelsEnabled; + break; + case SMU_VCLK: + *count = clk_table->VcnClkLevelsEnabled; + break; + case SMU_DCLK: + *count = clk_table->VcnClkLevelsEnabled; + break; + case SMU_MCLK: + *count = clk_table->NumMemPstatesEnabled; + break; + case SMU_FCLK: + *count = clk_table->NumFclkLevelsEnabled; + break; + default: + break; + } + + return 0; +} + +static int smu_v15_0_common_get_dpm_level_count(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *count) +{ + if (clk_type != SMU_VCLK1 && clk_type != SMU_DCLK1) + smu_v15_0_0_get_dpm_level_count(smu, clk_type, count); + + return 0; +} + +static int smu_v15_0_0_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, char *buf, + int *offset) +{ + int i, idx, ret = 0, size = *offset; + uint32_t cur_value = 0, value = 0, count = 0; + uint32_t min, max; + + switch (clk_type) { + case SMU_OD_SCLK: + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); + size += sysfs_emit_at(buf, size, "0: %10uMhz\n", + (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq); + size += sysfs_emit_at(buf, size, "1: %10uMhz\n", + (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq); + break; + case SMU_OD_RANGE: + size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); + size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", + smu->gfx_default_hard_min_freq, + smu->gfx_default_soft_max_freq); + break; + case SMU_SOCCLK: + case SMU_VCLK: + case SMU_DCLK: + case SMU_VCLK1: + case SMU_DCLK1: + case SMU_MCLK: + case SMU_FCLK: + ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value); + if (ret) + return ret; + + ret = smu_v15_0_common_get_dpm_level_count(smu, clk_type, &count); + if (ret) + return ret; + + for (i = 0; i < count; i++) { + idx = (clk_type == SMU_MCLK) ? (count - i - 1) : i; + ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, idx, &value); + if (ret) + return ret; + + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, + value, + cur_value == value ? "*" : ""); + } + break; + case SMU_GFXCLK: + case SMU_SCLK: + ret = smu_v15_0_0_get_current_clk_freq(smu, clk_type, &cur_value); + if (ret) + return ret; + min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq; + max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq; + if (cur_value == max) + i = 2; + else if (cur_value == min) + i = 0; + else + i = 1; + size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min, + i == 0 ? "*" : ""); + size += sysfs_emit_at( + buf, size, "1: %uMhz %s\n", + i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */ + i == 1 ? "*" : ""); + size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max, + i == 2 ? "*" : ""); + break; + default: + break; + } + + *offset = size; + + return 0; +} + +static int smu_v15_0_0_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, + uint32_t max) +{ + enum smu_message_type msg_set_min, msg_set_max; + int ret = 0; + + if (!smu_v15_0_0_clk_dpm_is_enabled(smu, clk_type)) + return -EINVAL; + + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + msg_set_min = SMU_MSG_SetSoftMinGfxclk; + msg_set_max = SMU_MSG_SetSoftMaxGfxClk; + break; + case SMU_FCLK: + msg_set_min = SMU_MSG_SetSoftMinFclk; + msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq; + break; + case SMU_SOCCLK: + msg_set_min = SMU_MSG_SetSoftMinSocclkByFreq; + msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq; + break; + case SMU_VCLK: + case SMU_DCLK: + msg_set_min = SMU_MSG_SetSoftMinVcn; + msg_set_max = SMU_MSG_SetSoftMaxVcn; + break; + default: + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL); + if (ret) + return ret; + + return smu_cmn_send_smc_msg_with_param(smu, msg_set_max, + max, NULL); +} + +static int smu_v15_0_0_force_clk_levels(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t mask) +{ + uint32_t soft_min_level = 0, soft_max_level = 0; + uint32_t min_freq = 0, max_freq = 0; + int ret = 0; + + soft_min_level = mask ? (ffs(mask) - 1) : 0; + soft_max_level = mask ? (fls(mask) - 1) : 0; + + switch (clk_type) { + case SMU_SOCCLK: + case SMU_FCLK: + case SMU_VCLK: + case SMU_DCLK: + case SMU_VCLK1: + case SMU_DCLK1: + ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq); + if (ret) + break; + + ret = smu_v15_0_common_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq); + if (ret) + break; + + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int smu_v15_0_common_get_dpm_profile_freq(struct smu_context *smu, + enum amd_dpm_forced_level level, + enum smu_clk_type clk_type, + uint32_t *min_clk, + uint32_t *max_clk) +{ + uint32_t clk_limit = 0; + int ret = 0; + + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + clk_limit = SMU_15_0_UMD_PSTATE_GFXCLK; + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit); + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL); + break; + case SMU_SOCCLK: + clk_limit = SMU_15_0_UMD_PSTATE_SOCCLK; + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit); + break; + case SMU_FCLK: + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(15, 0, 0)) + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit); + else + clk_limit = SMU_15_0_UMD_PSTATE_FCLK; + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit); + else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL); + break; + case SMU_VCLK: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit); + break; + case SMU_VCLK1: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &clk_limit); + break; + case SMU_DCLK: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit); + break; + case SMU_DCLK1: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &clk_limit); + break; + default: + ret = -EINVAL; + break; + } + *min_clk = *max_clk = clk_limit; + return ret; +} + +static int smu_v15_0_common_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t sclk_min = 0, sclk_max = 0; + uint32_t fclk_min = 0, fclk_max = 0; + uint32_t socclk_min = 0, socclk_max = 0; + uint32_t vclk_min = 0, vclk_max = 0; + uint32_t dclk_min = 0, dclk_max = 0; + uint32_t vclk1_min = 0, vclk1_max = 0; + uint32_t dclk1_min = 0, dclk1_max = 0; + int ret = 0; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, NULL, &vclk1_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, NULL, &dclk1_max); + sclk_min = sclk_max; + fclk_min = fclk_max; + socclk_min = socclk_max; + vclk_min = vclk_max; + dclk_min = dclk_max; + vclk1_min = vclk1_max; + dclk1_min = dclk1_max; + break; + case AMD_DPM_FORCED_LEVEL_LOW: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, NULL); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, NULL); + sclk_max = sclk_min; + fclk_max = fclk_min; + socclk_max = socclk_min; + vclk_max = vclk_min; + dclk_max = dclk_min; + vclk1_max = vclk1_min; + dclk1_max = dclk1_min; + break; + case AMD_DPM_FORCED_LEVEL_AUTO: + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_VCLK1, &vclk1_min, &vclk1_max); + smu_v15_0_common_get_dpm_ultimate_freq(smu, SMU_DCLK1, &dclk1_min, &dclk1_max); + break; + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max); + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max); + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max); + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max); + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max); + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_VCLK1, &vclk1_min, &vclk1_max); + smu_v15_0_common_get_dpm_profile_freq(smu, level, SMU_DCLK1, &dclk1_min, &dclk1_max); + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: + return 0; + default: + dev_err(adev->dev, "Invalid performance level %d\n", level); + return -EINVAL; + } + + if (sclk_min && sclk_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_SCLK, + sclk_min, + sclk_max); + if (ret) + return ret; + + smu->gfx_actual_hard_min_freq = sclk_min; + smu->gfx_actual_soft_max_freq = sclk_max; + } + + if (fclk_min && fclk_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_FCLK, + fclk_min, + fclk_max); + if (ret) + return ret; + } + + if (socclk_min && socclk_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_SOCCLK, + socclk_min, + socclk_max); + if (ret) + return ret; + } + + if (vclk_min && vclk_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_VCLK, + vclk_min, + vclk_max); + if (ret) + return ret; + } + + if (vclk1_min && vclk1_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_VCLK1, + vclk1_min, + vclk1_max); + if (ret) + return ret; + } + + if (dclk_min && dclk_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_DCLK, + dclk_min, + dclk_max); + if (ret) + return ret; + } + + if (dclk1_min && dclk1_max) { + ret = smu_v15_0_0_set_soft_freq_limited_range(smu, + SMU_DCLK1, + dclk1_min, + dclk1_max); + if (ret) + return ret; + } + + return ret; +} + +static int smu_v15_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + + smu->gfx_default_hard_min_freq = clk_table->MinGfxClk; + smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk; + smu->gfx_actual_hard_min_freq = 0; + smu->gfx_actual_soft_max_freq = 0; + + return 0; +} + +static int smu_v15_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) +{ + smu_v15_0_0_set_fine_grain_gfx_freq_parameters(smu); + + return 0; +} + +static int smu_v15_0_0_set_vpe_enable(struct smu_context *smu, + bool enable) +{ + return smu_cmn_send_smc_msg_with_param(smu, enable ? + SMU_MSG_PowerUpVpe : SMU_MSG_PowerDownVpe, + 0, NULL); +} + +static int smu_v15_0_0_set_umsch_mm_enable(struct smu_context *smu, + bool enable) +{ + return smu_cmn_send_smc_msg_with_param(smu, enable ? + SMU_MSG_PowerUpUmsch : SMU_MSG_PowerDownUmsch, + 0, NULL); +} + +static int smu_v15_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) +{ + DpmClocks_t *clk_table = smu->smu_table.clocks_table; + uint8_t idx; + + /* Only the Clock information of SOC and VPE is copied to provide VPE DPM settings for use. */ + for (idx = 0; idx < NUM_SOCCLK_DPM_LEVELS; idx++) { + clock_table->SocClocks[idx].Freq = (idx < clk_table->NumSocClkLevelsEnabled) ? clk_table->SocClocks[idx]:0; + clock_table->SocClocks[idx].Vol = 0; + } + + for (idx = 0; idx < NUM_VPE_DPM_LEVELS; idx++) { + clock_table->VPEClocks[idx].Freq = (idx < clk_table->VpeClkLevelsEnabled) ? clk_table->VPEClocks[idx]:0; + clock_table->VPEClocks[idx].Vol = 0; + } + + return 0; +} + +static int smu_v15_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table) +{ + smu_v15_0_0_get_dpm_table(smu, clock_table); + + return 0; +} + +static const struct pptable_funcs smu_v15_0_0_ppt_funcs = { + .check_fw_status = smu_v15_0_check_fw_status, + .check_fw_version = smu_cmn_check_fw_version, + .init_smc_tables = smu_v15_0_0_init_smc_tables, + .fini_smc_tables = smu_v15_0_0_fini_smc_tables, + .get_vbios_bootup_values = smu_v15_0_get_vbios_bootup_values, + .system_features_control = smu_v15_0_0_system_features_control, + .dpm_set_vcn_enable = smu_v15_0_set_vcn_enable, + .dpm_set_jpeg_enable = smu_v15_0_set_jpeg_enable, + .set_default_dpm_table = smu_v15_0_0_set_default_dpm_tables, + .read_sensor = smu_v15_0_0_read_sensor, + .is_dpm_running = smu_v15_0_0_is_dpm_running, + .set_watermarks_table = smu_v15_0_0_set_watermarks_table, + .get_gpu_metrics = smu_v15_0_0_get_gpu_metrics, + .get_enabled_mask = smu_v15_0_0_get_enabled_mask, + .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, + .gfx_off_control = smu_v15_0_gfx_off_control, + .mode2_reset = smu_v15_0_0_mode2_reset, + .get_dpm_ultimate_freq = smu_v15_0_common_get_dpm_ultimate_freq, + .od_edit_dpm_table = smu_v15_0_od_edit_dpm_table, + .emit_clk_levels = smu_v15_0_0_emit_clk_levels, + .force_clk_levels = smu_v15_0_0_force_clk_levels, + .set_performance_level = smu_v15_0_common_set_performance_level, + .set_fine_grain_gfx_freq_parameters = smu_v15_0_common_set_fine_grain_gfx_freq_parameters, + .set_gfx_power_up_by_imu = smu_v15_0_set_gfx_power_up_by_imu, + .dpm_set_vpe_enable = smu_v15_0_0_set_vpe_enable, + .dpm_set_umsch_mm_enable = smu_v15_0_0_set_umsch_mm_enable, + .get_dpm_clock_table = smu_v15_0_common_get_dpm_table, +}; + +static void smu_v15_0_0_init_msg_ctl(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_30); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_31); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_32); + ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_33); + ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_34); + ctl->config.num_arg_regs = 3; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = smu_v15_0_0_message_map; +} + +void smu_v15_0_0_set_ppt_funcs(struct smu_context *smu) +{ + smu->ppt_funcs = &smu_v15_0_0_ppt_funcs; + smu->feature_map = smu_v15_0_0_feature_mask_map; + smu->table_map = smu_v15_0_0_table_map; + smu->is_apu = true; + smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0; + + smu_v15_0_0_init_msg_ctl(smu); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.h new file mode 100644 index 0000000000000..8365b9fea77ea --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_0_ppt.h @@ -0,0 +1,28 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU_V15_0_0_PPT_H__ +#define __SMU_V15_0_0_PPT_H__ + +extern void smu_v15_0_0_set_ppt_funcs(struct smu_context *smu); + +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c new file mode 100644 index 0000000000000..cc2babc6a341a --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c @@ -0,0 +1,2270 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#define SWSMU_CODE_LAYER_L2 + +#include +#include "amdgpu.h" +#include "amdgpu_smu.h" +#include "smu_v15_0_8_pmfw.h" +#include "smu15_driver_if_v15_0_8.h" +#include "smu_v15_0_8_ppsmc.h" +#include "smu_v15_0_8_ppt.h" +#include +#include "smu_cmn.h" +#include "mp/mp_15_0_8_offset.h" +#include "mp/mp_15_0_8_sh_mask.h" +#include "smu_v15_0.h" +#include "amdgpu_fru_eeprom.h" + +#undef MP1_Public + +/* address block */ +#define MP1_Public 0x03b00000 +#define smnMP1_FIRMWARE_FLAGS_15_0_8 0x3010024 +/* + * DO NOT use these for err/warn/info/debug messages. + * Use dev_err, dev_warn, dev_info and dev_dbg instead. + * They are more MGPU friendly. + */ +#undef pr_err +#undef pr_warn +#undef pr_info +#undef pr_debug + +#define SMUQ10_TO_UINT(x) ((x) >> 10) +#define SMUQ10_FRAC(x) ((x) & 0x3ff) +#define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) + +#define hbm_stack_mask_valid(umc_mask) \ + (((umc_mask) & 0xF) == 0xF) + +#define for_each_hbm_stack(stack_idx, umc_mask) \ + for ((stack_idx) = 0; (umc_mask); \ + (umc_mask) >>= 4, (stack_idx)++) \ + +#define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c)) + +#define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature) \ + [smu_feature] = { 1, (smu_15_0_8_feature) } + +#define FEATURE_MASK(feature) (1ULL << feature) + +static const struct smu_feature_bits smu_v15_0_8_dpm_features = { + .bits = { SMU_FEATURE_BIT_INIT(FEATURE_ID_DATA_CALCULATION), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_GFXCLK), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_UCLK), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_FCLK), + SMU_FEATURE_BIT_INIT(FEATURE_ID_DPM_GL2CLK) } +}; + +static const struct cmn2asic_msg_mapping smu_v15_0_8_message_map[SMU_MSG_MAX_COUNT] = { + MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0), + MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1), + MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK), + MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1), + MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0), + MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1), + MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1), + MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1), + MSG_MAP(SetDriverDramAddr, PPSMC_MSG_SetDriverDramAddr, 1), + MSG_MAP(SetToolsDramAddr, PPSMC_MSG_SetToolsDramAddr, 0), + MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1), + MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0), + MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1), + MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0), + MSG_MAP(HeavySBR, PPSMC_MSG_HeavySBR, 0), + MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0), + MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0), + MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1), + MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1), + MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0), + MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI), + MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI), + MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0), + MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI), + MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI), + MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0), + MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0), + MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0), + MSG_MAP(GetRASTableVersion, PPSMC_MSG_GetRasTableVersion, 0), + MSG_MAP(SetTimestamp, PPSMC_MSG_SetTimestamp, 0), + MSG_MAP(GetTimestamp, PPSMC_MSG_GetTimestamp, 0), + MSG_MAP(GetBadPageIpid, PPSMC_MSG_GetBadPageIpIdLoHi, 0), + MSG_MAP(EraseRasTable, PPSMC_MSG_EraseRasTable, 0), + MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1), + MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1), + MSG_MAP(GetSystemMetricsVersion, PPSMC_MSG_GetSystemMetricsVersion, 0), + MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0), + MSG_MAP(SetFastPptLimit, PPSMC_MSG_SetFastPptLimit, 0), + MSG_MAP(GetFastPptLimit, PPSMC_MSG_GetFastPptLimit, 0), + MSG_MAP(SetSoftMinGl2clk, PPSMC_MSG_SetSoftMinGl2clk, 0), + MSG_MAP(SetSoftMaxGl2clk, PPSMC_MSG_SetSoftMaxGl2clk, 0), + MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0), + MSG_MAP(SetSoftMaxFclk, PPSMC_MSG_SetSoftMaxFclk, 0), +}; + +/* TODO: Update the clk map once enum PPCLK is updated in smu15_driver_if_v15_0_8.h */ +static struct cmn2asic_mapping smu_v15_0_8_clk_map[SMU_CLK_COUNT] = { + CLK_MAP(UCLK, PPCLK_UCLK), +}; + +static const struct cmn2asic_mapping smu_v15_0_8_feature_mask_map[SMU_FEATURE_COUNT] = { + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_ID_DATA_CALCULATION), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_ID_DPM_GFXCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_ID_DPM_UCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_ID_DPM_FCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DPM_GL2CLK_BIT, FEATURE_ID_DPM_GL2CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_ID_DS_GFXCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_ID_DS_SOCCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_ID_DS_LCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_ID_DS_FCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_DMABECLK_BIT, FEATURE_ID_DS_DMABECLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPIFOECLK_BIT, FEATURE_ID_DS_MPIFOECLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPRASCLK_BIT, FEATURE_ID_DS_MPRASCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPNHTCLK_BIT, FEATURE_ID_DS_MPNHTCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_FIOCLK_BIT, FEATURE_ID_DS_FIOCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_DXIOCLK_BIT, FEATURE_ID_DS_DXIOCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_GL2CLK_BIT, FEATURE_ID_DS_GL2CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_ID_PPT), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_ID_TDC), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_ID_SMU_CG), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_ID_FW_CTF), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_ID_THERMAL), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, FEATURE_ID_SOC_PCC), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_ID_XGMI_PER_LINK_PWR_DOWN), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_ID_DS_VCN), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_ID_DS_MP1CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_ID_DS_MPIOCLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_ID_DS_MP0CLK), + SMU_15_0_8_FEA_MAP(SMU_FEATURE_PIT_BIT, FEATURE_ID_PIT), +}; + +#define TABLE_PMSTATUSLOG 0 +#define TABLE_SMU_METRICS 1 +#define TABLE_I2C_COMMANDS 2 +#define TABLE_COUNT 3 + +static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = { + TAB_MAP(PMSTATUSLOG), + TAB_MAP(SMU_METRICS), + TAB_MAP(I2C_COMMANDS), +}; + +static size_t smu_v15_0_8_get_system_metrics_size(void) +{ + return sizeof(SystemMetricsTable_t); +} + +static int smu_v15_0_8_tables_init(struct smu_context *smu) +{ + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics; + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; + struct smu_table_context *smu_table = &smu->smu_table; + int ret, gpu_metrcs_size = sizeof(MetricsTable_t); + struct smu_table *tables = smu_table->tables; + struct smu_v15_0_8_gpu_metrics *gpu_metrics; + void *driver_pptable __free(kfree) = NULL; + void *metrics_table __free(kfree) = NULL; + + SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU15_TOOL_SIZE, + PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); + + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, + gpu_metrcs_size, + PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); + SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS, + smu_v15_0_8_get_system_metrics_size(), PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT); + + metrics_table = kzalloc(gpu_metrcs_size, GFP_KERNEL); + if (!metrics_table) + return -ENOMEM; + + smu_table->metrics_time = 0; + + driver_pptable = kzalloc(sizeof(PPTable_t), GFP_KERNEL); + if (!driver_pptable) + return -ENOMEM; + + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS, + sizeof(struct smu_v15_0_8_gpu_metrics), + SMU_GPU_METRICS_CACHE_INTERVAL); + if (ret) + return ret; + + gpu_metrics = (struct smu_v15_0_8_gpu_metrics *)smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPU_METRICS); + smu_v15_0_8_gpu_metrics_init(gpu_metrics, 1, 9); + + ret = smu_table_cache_init(smu, SMU_TABLE_PMFW_SYSTEM_METRICS, + smu_v15_0_8_get_system_metrics_size(), 5); + + if (ret) + return ret; + + /* Initialize base board temperature metrics */ + ret = smu_driver_table_init(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS, + sizeof(*baseboard_temp_metrics), 50); + if (ret) + return ret; + baseboard_temp_metrics = (struct smu_v15_0_8_baseboard_temp_metrics *) + smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_v15_0_8_baseboard_temp_metrics_init(baseboard_temp_metrics, 1, 1); + /* Initialize GPU board temperature metrics */ + ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS, + sizeof(*gpuboard_temp_metrics), 50); + if (ret) { + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); + smu_driver_table_fini(smu, + SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + return ret; + } + gpuboard_temp_metrics = (struct smu_v15_0_8_gpuboard_temp_metrics *) + smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_v15_0_8_gpuboard_temp_metrics_init(gpuboard_temp_metrics, 1, 1); + + smu_table->metrics_table = no_free_ptr(metrics_table); + smu_table->driver_pptable = no_free_ptr(driver_pptable); + + mutex_init(&smu_table->metrics_lock); + + return 0; +} + +static int smu_v15_0_8_allocate_dpm_context(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + + smu_dpm->dpm_context = + kzalloc(sizeof(struct smu_15_0_dpm_context), GFP_KERNEL); + if (!smu_dpm->dpm_context) + return -ENOMEM; + smu_dpm->dpm_context_size = sizeof(struct smu_15_0_dpm_context); + + smu_dpm->dpm_policies = + kzalloc(sizeof(struct smu_dpm_policy_ctxt), GFP_KERNEL); + if (!smu_dpm->dpm_policies) { + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + + return 0; +} + +static int smu_v15_0_8_init_smc_tables(struct smu_context *smu) +{ + int ret = 0; + + ret = smu_v15_0_8_tables_init(smu); + if (ret) + return ret; + + ret = smu_v15_0_8_allocate_dpm_context(smu); + + return ret; +} + +static int smu_v15_0_8_tables_fini(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_table_cache_fini(smu, SMU_TABLE_PMFW_SYSTEM_METRICS); + mutex_destroy(&smu_table->metrics_lock); + + return 0; +} + +static int smu_v15_0_8_fini_smc_tables(struct smu_context *smu) +{ + int ret; + + ret = smu_v15_0_8_tables_fini(smu); + if (ret) + return ret; + + ret = smu_v15_0_fini_smc_tables(smu); + if (ret) + return ret; + + return ret; +} + +static int smu_v15_0_8_init_allowed_features(struct smu_context *smu) +{ + /* pptable will handle the features to enable */ + smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED); + + return 0; +} + +static int smu_v15_0_8_get_metrics_table_internal(struct smu_context *smu, uint32_t tmo, void *data) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + struct smu_table *table = &smu_table->driver_table; + struct amdgpu_device *adev = smu->adev; + + mutex_lock(&smu_table->metrics_lock); + + if (!tmo || !smu_table->metrics_time || + time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(tmo))) { + int ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL); + if (ret) { + dev_info(adev->dev, + "Failed to export SMU metrics table!\n"); + mutex_unlock(&smu_table->metrics_lock); + return ret; + } + + amdgpu_device_invalidate_hdp(smu->adev, NULL); + memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + + smu_table->metrics_time = jiffies; + } + + if (data) + memcpy(data, smu_table->metrics_table, table_size); + mutex_unlock(&smu_table->metrics_lock); + return 0; +} + +static int smu_v15_0_8_get_smu_metrics_data(struct smu_context *smu, + MetricsMember_t member, uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + MetricsTable_t *metrics = (MetricsTable_t *)smu_table->metrics_table; + struct amdgpu_device *adev = smu->adev; + int ret, xcc_id; + + ret = smu_v15_0_8_get_metrics_table_internal(smu, 10, NULL); + if (ret) + return ret; + + switch (member) { + case METRICS_CURR_GFXCLK: + case METRICS_AVERAGE_GFXCLK: + xcc_id = GET_INST(GC, 0); + *value = SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); + break; + case METRICS_CURR_SOCCLK: + case METRICS_AVERAGE_SOCCLK: + *value = SMUQ10_ROUND(metrics->SocclkFrequency[0]); + break; + case METRICS_CURR_UCLK: + case METRICS_AVERAGE_UCLK: + *value = SMUQ10_ROUND(metrics->UclkFrequency[0]); + break; + case METRICS_CURR_VCLK: + *value = SMUQ10_ROUND(metrics->VclkFrequency[0]); + break; + case METRICS_CURR_DCLK: + *value = SMUQ10_ROUND(metrics->DclkFrequency[0]); + break; + case METRICS_CURR_FCLK: + *value = SMUQ10_ROUND(metrics->FclkFrequency[0]); + break; + case METRICS_AVERAGE_GFXACTIVITY: + *value = SMUQ10_ROUND(metrics->SocketGfxBusy); + break; + case METRICS_AVERAGE_MEMACTIVITY: + *value = SMUQ10_ROUND(metrics->DramBandwidthUtilization); + break; + case METRICS_CURR_SOCKETPOWER: + *value = SMUQ10_ROUND(metrics->SocketPower) << 8; + break; + case METRICS_TEMPERATURE_HOTSPOT: + *value = SMUQ10_ROUND(metrics->MaxSocketTemperature) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + case METRICS_TEMPERATURE_MEM: + { + struct amdgpu_device *adev = smu->adev; + u32 max_hbm_temp = 0; + + /* Find max temperature across all HBM stacks */ + if (adev->umc.active_mask) { + u64 mask = adev->umc.active_mask; + int stack_idx; + + for_each_hbm_stack(stack_idx, mask) { + u32 temp; + + if (!hbm_stack_mask_valid(mask)) + continue; + + temp = SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + if (temp > max_hbm_temp) + max_hbm_temp = temp; + } + } + *value = max_hbm_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + } + /* This is the max of all VRs and not just SOC VR. + */ + case METRICS_TEMPERATURE_VRSOC: + *value = SMUQ10_ROUND(metrics->MaxVrTemperature) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + break; + default: + *value = UINT_MAX; + break; + } + + return 0; +} + +static int smu_v15_0_8_get_current_clk_freq_by_table(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *value) +{ + MetricsMember_t member_type; + + if (!value) + return -EINVAL; + + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + member_type = METRICS_CURR_GFXCLK; + break; + case SMU_UCLK: + case SMU_MCLK: + member_type = METRICS_CURR_UCLK; + break; + case SMU_SOCCLK: + member_type = METRICS_CURR_SOCCLK; + break; + case SMU_VCLK: + member_type = METRICS_CURR_VCLK; + break; + case SMU_DCLK: + member_type = METRICS_CURR_DCLK; + break; + case SMU_FCLK: + member_type = METRICS_CURR_FCLK; + break; + default: + return -EINVAL; + } + + return smu_v15_0_8_get_smu_metrics_data(smu, member_type, value); +} + +static int smu_v15_0_8_get_current_activity_percent(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + int ret = 0; + + if (!value) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_AVERAGE_GFXACTIVITY, value); + break; + case AMDGPU_PP_SENSOR_MEM_LOAD: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_AVERAGE_MEMACTIVITY, value); + break; + default: + dev_err(smu->adev->dev, + "Invalid sensor for retrieving clock activity\n"); + return -EINVAL; + } + + return ret; +} + +static int smu_v15_0_8_thermal_get_temperature(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + int ret = 0; + + if (!value) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_HOTSPOT, value); + break; + case AMDGPU_PP_SENSOR_MEM_TEMP: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_TEMPERATURE_MEM, value); + break; + default: + dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n"); + return -EINVAL; + } + + return ret; +} + +static int smu_v15_0_8_get_system_metrics_table(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *table = &smu_table->driver_table; + struct smu_table *tables = smu_table->tables; + struct smu_table *sys_table; + int ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + if (smu_table_cache_is_valid(sys_table)) + return 0; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSystemMetricsTable, NULL); + if (ret) { + dev_info(smu->adev->dev, + "Failed to export system metrics table!\n"); + return ret; + } + + amdgpu_hdp_invalidate(smu->adev, NULL); + smu_table_cache_update_time(sys_table, jiffies); + memcpy(sys_table->cache.buffer, table->cpu_addr, + sizeof(SystemMetricsTable_t)); + + return 0; +} + +static int smu_v15_0_8_get_npm_data(struct smu_context *smu, + enum amd_pp_sensors sensor, + uint32_t *value) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + int ret; + + if (sensor == AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT) { + /*TBD as of now put 0 */ + *value = 0; + return 0; + } + + ret = smu_v15_0_8_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + + switch (sensor) { + case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: + *value = SMUQ10_ROUND(metrics->NodePowerLimit); + break; + case AMDGPU_PP_SENSOR_NODEPOWER: + *value = SMUQ10_ROUND(metrics->NodePower); + break; + case AMDGPU_PP_SENSOR_GPPTRESIDENCY: + *value = SMUQ10_ROUND(metrics->GlobalPPTResidencyAcc); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int smu_v15_0_8_read_sensor(struct smu_context *smu, + enum amd_pp_sensors sensor, void *data, + uint32_t *size) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + int ret = 0; + + if (amdgpu_ras_intr_triggered()) + return 0; + + if (!data || !size) + return -EINVAL; + + switch (sensor) { + case AMDGPU_PP_SENSOR_MEM_LOAD: + case AMDGPU_PP_SENSOR_GPU_LOAD: + ret = smu_v15_0_8_get_current_activity_percent(smu, sensor, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_INPUT_POWER: + ret = smu_v15_0_8_get_smu_metrics_data(smu, + METRICS_CURR_SOCKETPOWER, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_HOTSPOT_TEMP: + case AMDGPU_PP_SENSOR_MEM_TEMP: + ret = smu_v15_0_8_thermal_get_temperature(smu, sensor, + (uint32_t *)data); + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_MCLK: + ret = smu_v15_0_8_get_current_clk_freq_by_table(smu, + SMU_UCLK, (uint32_t *)data); + /* the output clock frequency in 10K unit */ + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GFX_SCLK: + ret = smu_v15_0_8_get_current_clk_freq_by_table(smu, + SMU_GFXCLK, (uint32_t *)data); + *(uint32_t *)data *= 100; + *size = 4; + break; + case AMDGPU_PP_SENSOR_VDDBOARD: + *(uint32_t *)data = dpm_context->board_volt; + *size = 4; + break; + case AMDGPU_PP_SENSOR_NODEPOWERLIMIT: + case AMDGPU_PP_SENSOR_NODEPOWER: + case AMDGPU_PP_SENSOR_GPPTRESIDENCY: + case AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT: + ret = smu_v15_0_8_get_npm_data(smu, sensor, (uint32_t *)data); + if (ret) + return ret; + *size = 4; + break; + case AMDGPU_PP_SENSOR_GPU_AVG_POWER: + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int smu_v15_0_8_emit_clk_levels(struct smu_context *smu, + enum smu_clk_type type, char *buf, + int *offset) +{ + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + struct smu_15_0_dpm_context *dpm_context; + struct smu_dpm_table *single_dpm_table = NULL; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + int ret, now, size = *offset; + + if (amdgpu_ras_intr_triggered()) { + sysfs_emit_at(buf, size, "unavailable\n"); + return -EBUSY; + } + + dpm_context = smu_dpm->dpm_context; + + switch (type) { + case SMU_OD_SCLK: + size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); + size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", + pstate_table->gfxclk_pstate.curr.min, + pstate_table->gfxclk_pstate.curr.max); + break; + case SMU_OD_MCLK: + size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK"); + size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", + pstate_table->uclk_pstate.curr.min, + pstate_table->uclk_pstate.curr.max); + break; + case SMU_SCLK: + case SMU_GFXCLK: + single_dpm_table = &dpm_context->dpm_tables.gfx_table; + break; + case SMU_MCLK: + case SMU_UCLK: + single_dpm_table = &dpm_context->dpm_tables.uclk_table; + break; + case SMU_SOCCLK: + single_dpm_table = &dpm_context->dpm_tables.soc_table; + break; + case SMU_FCLK: + single_dpm_table = &dpm_context->dpm_tables.fclk_table; + break; + case SMU_VCLK: + single_dpm_table = &dpm_context->dpm_tables.vclk_table; + break; + case SMU_DCLK: + single_dpm_table = &dpm_context->dpm_tables.dclk_table; + break; + default: + break; + } + + if (single_dpm_table) { + ret = smu_v15_0_8_get_current_clk_freq_by_table(smu, type, &now); + if (ret) { + dev_err(smu->adev->dev, + "Attempt to get current clk Failed!"); + return ret; + } + ret = smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, now, + buf, offset); + if (ret < 0) + return ret; + + return 0; + } + + *offset = size; + + return 0; +} + +static int smu_v15_0_8_get_dpm_ultimate_freq(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t *min, uint32_t *max) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + struct smu_dpm_table *dpm_table; + uint32_t min_clk = 0, max_clk = 0; + + if (!pptable->init) + return -EINVAL; + + /* Try cached DPM tables first */ + if (dpm_context) { + switch (clk_type) { + case SMU_MCLK: + case SMU_UCLK: + dpm_table = &dpm_context->dpm_tables.uclk_table; + break; + case SMU_GFXCLK: + case SMU_SCLK: + dpm_table = &dpm_context->dpm_tables.gfx_table; + break; + case SMU_SOCCLK: + dpm_table = &dpm_context->dpm_tables.soc_table; + break; + case SMU_FCLK: + dpm_table = &dpm_context->dpm_tables.fclk_table; + break; + case SMU_GL2CLK: + dpm_table = &dpm_context->dpm_tables.gl2_table; + break; + case SMU_VCLK: + dpm_table = &dpm_context->dpm_tables.vclk_table; + break; + case SMU_DCLK: + dpm_table = &dpm_context->dpm_tables.dclk_table; + break; + default: + dpm_table = NULL; + break; + } + + if (dpm_table && dpm_table->count > 0) { + min_clk = SMU_DPM_TABLE_MIN(dpm_table); + max_clk = SMU_DPM_TABLE_MAX(dpm_table); + + if (min_clk && max_clk) { + if (min) + *min = min_clk; + if (max) + *max = max_clk; + return 0; + } + } + } + + /* Fall back to pptable */ + switch (clk_type) { + case SMU_GFXCLK: + case SMU_SCLK: + min_clk = pptable->MinGfxclkFrequency; + max_clk = pptable->MaxGfxclkFrequency; + break; + case SMU_FCLK: + min_clk = pptable->MinFclkFrequency; + max_clk = pptable->MaxFclkFrequency; + break; + case SMU_GL2CLK: + min_clk = pptable->MinGl2clkFrequency; + max_clk = pptable->MaxGl2clkFrequency; + break; + case SMU_MCLK: + case SMU_UCLK: + min_clk = pptable->UclkFrequencyTable[0]; + max_clk = pptable->UclkFrequencyTable[ARRAY_SIZE(pptable->UclkFrequencyTable) - 1]; + break; + case SMU_SOCCLK: + min_clk = pptable->SocclkFrequency; + max_clk = pptable->SocclkFrequency; + break; + case SMU_VCLK: + min_clk = pptable->VclkFrequency; + max_clk = pptable->VclkFrequency; + break; + case SMU_DCLK: + min_clk = pptable->DclkFrequency; + max_clk = pptable->DclkFrequency; + break; + default: + return -EINVAL; + } + + if (min) + *min = min_clk; + if (max) + *max = max_clk; + + return 0; +} + +static int smu_v15_0_8_set_dpm_table(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_dpm_table *dpm_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int i, ret; + uint32_t gfxclkmin, gfxclkmax; + + /* gfxclk dpm table setup - fine-grained */ + dpm_table = &dpm_context->dpm_tables.gfx_table; + dpm_table->clk_type = SMU_GFXCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { + ret = smu_v15_0_8_get_dpm_ultimate_freq(smu, SMU_GFXCLK, + &gfxclkmin, &gfxclkmax); + if (ret) + return ret; + + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = gfxclkmin; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = gfxclkmax; + dpm_table->dpm_levels[1].enabled = true; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + } + + /* fclk dpm table setup - fine-grained */ + dpm_table = &dpm_context->dpm_tables.fclk_table; + dpm_table->clk_type = SMU_FCLK; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) { + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = pptable->MinFclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = pptable->MaxFclkFrequency; + dpm_table->dpm_levels[1].enabled = true; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->MinFclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + } + + /* gl2clk dpm table setup - fine-grained */ + dpm_table = &dpm_context->dpm_tables.gl2_table; + dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GL2CLK_BIT)) { + dpm_table->count = 2; + dpm_table->dpm_levels[0].value = pptable->MinGl2clkFrequency; + dpm_table->dpm_levels[0].enabled = true; + dpm_table->dpm_levels[1].value = pptable->MaxGl2clkFrequency; + dpm_table->dpm_levels[1].enabled = true; + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->MinGl2clkFrequency; + dpm_table->dpm_levels[0].enabled = true; + } + + /* uclk dpm table setup - discrete levels */ + dpm_table = &dpm_context->dpm_tables.uclk_table; + dpm_table->clk_type = SMU_UCLK; + dpm_table->flags = 0; + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + dpm_table->count = ARRAY_SIZE(pptable->UclkFrequencyTable); + for (i = 0; i < dpm_table->count; ++i) { + dpm_table->dpm_levels[i].value = pptable->UclkFrequencyTable[i]; + dpm_table->dpm_levels[i].enabled = true; + } + } else { + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->UclkFrequencyTable[0]; + dpm_table->dpm_levels[0].enabled = true; + } + + /* socclk dpm table setup - single boot-time value */ + dpm_table = &dpm_context->dpm_tables.soc_table; + dpm_table->clk_type = SMU_SOCCLK; + dpm_table->flags = 0; + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->SocclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + + /* vclk dpm table setup - single boot-time value */ + dpm_table = &dpm_context->dpm_tables.vclk_table; + dpm_table->clk_type = SMU_VCLK; + dpm_table->flags = 0; + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->VclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + + /* dclk dpm table setup - single boot-time value */ + dpm_table = &dpm_context->dpm_tables.dclk_table; + dpm_table->clk_type = SMU_DCLK; + dpm_table->flags = 0; + dpm_table->count = 1; + dpm_table->dpm_levels[0].value = pptable->DclkFrequency; + dpm_table->dpm_levels[0].enabled = true; + + return 0; +} + +static int smu_v15_0_8_setup_pptable(struct smu_context *smu) +{ + struct smu_table_context *table_context = &smu->smu_table; + + /* TODO: PPTable is not available. + * 1) Find an alternate way to get 'PPTable values' here. + * 2) Check if there is SW CTF + */ + table_context->thermal_controller_type = 0; + + return 0; +} + +static int smu_v15_0_8_check_fw_status(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t mp1_fw_flags; + + mp1_fw_flags = RREG32_PCIE(MP1_Public | + (smnMP1_FIRMWARE_FLAGS_15_0_8 & 0xffffffff)); + + if ((mp1_fw_flags & MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> + MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) + return 0; + + return -EIO; +} + +static int smu_v15_0_8_get_static_metrics_table(struct smu_context *smu) +{ + struct smu_table_context *smu_table = &smu->smu_table; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + struct smu_table *table = &smu_table->driver_table; + int ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL); + if (ret) { + dev_err(smu->adev->dev, + "Failed to export static metrics table!\n"); + return ret; + } + + amdgpu_hdp_invalidate(smu->adev, NULL); + memcpy(smu_table->metrics_table, table->cpu_addr, table_size); + + return 0; +} + +static int smu_v15_0_8_fru_get_product_info(struct smu_context *smu, + StaticMetricsTable_t *static_metrics) +{ + struct amdgpu_fru_info *fru_info; + struct amdgpu_device *adev = smu->adev; + + if (!adev->fru_info) { + adev->fru_info = kzalloc(sizeof(*adev->fru_info), GFP_KERNEL); + if (!adev->fru_info) + return -ENOMEM; + } + + fru_info = adev->fru_info; + strscpy(fru_info->product_number, static_metrics->ProductInfo.ModelNumber, + sizeof(fru_info->product_number)); + strscpy(fru_info->product_name, static_metrics->ProductInfo.Name, + sizeof(fru_info->product_name)); + strscpy(fru_info->serial, static_metrics->ProductInfo.Serial, + sizeof(fru_info->serial)); + strscpy(fru_info->manufacturer_name, static_metrics->ProductInfo.ManufacturerName, + sizeof(fru_info->manufacturer_name)); + strscpy(fru_info->fru_id, static_metrics->ProductInfo.FruId, + sizeof(fru_info->fru_id)); + + return 0; +} + +static void smu_v15_0_8_init_xgmi_data(struct smu_context *smu, + StaticMetricsTable_t *static_metrics) +{ + uint16_t max_speed; + uint8_t max_width; + + max_width = (uint8_t)static_metrics->MaxXgmiWidth; + max_speed = (uint16_t)static_metrics->MaxXgmiBitrate; + amgpu_xgmi_set_max_speed_width(smu->adev, max_speed, max_width); +} + +static int smu_v15_0_8_set_driver_pptable(struct smu_context *smu) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_table_context *smu_table = &smu->smu_table; + StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int ret, i, n; + uint32_t table_version; + + if (!pptable->init) { + ret = smu_v15_0_8_get_static_metrics_table(smu); + if (ret) + return ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion, + &table_version); + if (ret) + return ret; + smu_table->tables[SMU_TABLE_SMU_METRICS].version = + table_version; + + pptable->MaxSocketPowerLimit = + SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit); + pptable->MaxGfxclkFrequency = + SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency); + pptable->MinGfxclkFrequency = + SMUQ10_ROUND(static_metrics->MinGfxclkFrequency); + pptable->MaxFclkFrequency = + SMUQ10_ROUND(static_metrics->MaxFclkFrequency); + pptable->MinFclkFrequency = + SMUQ10_ROUND(static_metrics->MinFclkFrequency); + pptable->MaxGl2clkFrequency = + SMUQ10_ROUND(static_metrics->MaxGl2clkFrequency); + pptable->MinGl2clkFrequency = + SMUQ10_ROUND(static_metrics->MinGl2clkFrequency); + + for (i = 0; i < ARRAY_SIZE(static_metrics->UclkFrequencyTable); ++i) + pptable->UclkFrequencyTable[i] = + SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]); + + pptable->SocclkFrequency = SMUQ10_ROUND(static_metrics->SocclkFrequency); + pptable->LclkFrequency = SMUQ10_ROUND(static_metrics->LclkFrequency); + pptable->VclkFrequency = SMUQ10_ROUND(static_metrics->VclkFrequency); + pptable->DclkFrequency = SMUQ10_ROUND(static_metrics->DclkFrequency); + + pptable->CTFLimitMID = SMUQ10_ROUND(static_metrics->CTFLimit_MID); + pptable->CTFLimitAID = SMUQ10_ROUND(static_metrics->CTFLimit_AID); + pptable->CTFLimitXCD = SMUQ10_ROUND(static_metrics->CTFLimit_XCD); + pptable->CTFLimitHBM = SMUQ10_ROUND(static_metrics->CTFLimit_HBM); + pptable->ThermalLimitMID = SMUQ10_ROUND(static_metrics->ThermalLimit_MID); + pptable->ThermalLimitAID = SMUQ10_ROUND(static_metrics->ThermalLimit_AID); + pptable->ThermalLimitXCD = SMUQ10_ROUND(static_metrics->ThermalLimit_XCD); + pptable->ThermalLimitHBM = SMUQ10_ROUND(static_metrics->ThermalLimit_HBM); + + /* use MID0 serial number by default */ + pptable->PublicSerialNumberMID = + static_metrics->PublicSerialNumber_MID[0]; + + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC, + 0, pptable->PublicSerialNumberMID); + pptable->PublicSerialNumberAID = + static_metrics->PublicSerialNumber_AID[0]; + pptable->PublicSerialNumberXCD = + static_metrics->PublicSerialNumber_XCD[0]; + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_MID); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_MID, i, + static_metrics->PublicSerialNumber_MID[i]); + } + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_AID); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i, + static_metrics->PublicSerialNumber_AID[i]); + } + n = ARRAY_SIZE(static_metrics->PublicSerialNumber_XCD); + for (i = 0; i < n; i++) { + amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i, + static_metrics->PublicSerialNumber_XCD[i]); + } + + ret = smu_v15_0_8_fru_get_product_info(smu, static_metrics); + if (ret) + return ret; + pptable->PPT1Max = static_metrics->PPT1Max; + pptable->PPT1Min = static_metrics->PPT1Min; + pptable->PPT1Default = static_metrics->PPT1Default; + + if (static_metrics->pldmVersion[0] != 0xFFFFFFFF) + smu->adev->firmware.pldm_version = + static_metrics->pldmVersion[0]; + dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV; + smu_v15_0_8_init_xgmi_data(smu, static_metrics); + pptable->init = true; + } + + return 0; +} + +static int smu_v15_0_8_set_default_dpm_table(struct smu_context *smu) +{ + int ret; + + ret = smu_v15_0_8_set_driver_pptable(smu); + if (ret) + return ret; + + ret = smu_v15_0_8_set_dpm_table(smu); + if (ret) + return ret; + + return 0; +} + +static int smu_v15_0_8_irq_process(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_power_context *smu_power = &smu->smu_power; + struct smu_15_0_power_context *power_context = smu_power->power_context; + uint32_t client_id = entry->client_id; + uint32_t ctxid = entry->src_data[0]; + uint32_t src_id = entry->src_id; + uint32_t data; + + if (client_id == SOC_V1_0_IH_CLIENTID_MP1) { + if (src_id == IH_INTERRUPT_ID_TO_DRIVER) { + /* ACK SMUToHost interrupt */ + data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); + /* + * ctxid is used to distinguish different events for SMCToHost + * interrupt. + */ + switch (ctxid) { + case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING: + /* + * Increment the throttle interrupt counter + */ + atomic64_inc(&smu->throttle_int_counter); + + if (!atomic_read(&adev->throttling_logging_enabled)) + return 0; + + /* This uses the new method which fixes the + * incorrect throttling status reporting + * through metrics table. For older FWs, + * it will be ignored. + */ + if (__ratelimit(&adev->throttling_logging_rs)) { + atomic_set( + &power_context->throttle_status, + entry->src_data[1]); + schedule_work(&smu->throttling_logging_work); + } + break; + default: + dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n", + ctxid, client_id); + break; + } + } + } + + return 0; +} + +static int smu_v15_0_8_set_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + uint32_t val = 0; + + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* For MP1 SW irqs */ + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* For MP1 SW irqs */ + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); + + val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); + val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0); + WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); + + break; + default: + break; + } + + return 0; +} + +static const struct amdgpu_irq_src_funcs smu_v15_0_8_irq_funcs = { + .set = smu_v15_0_8_set_irq_state, + .process = smu_v15_0_8_irq_process, +}; + +static int smu_v15_0_8_register_irq_handler(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct amdgpu_irq_src *irq_src = &smu->irq_source; + int ret = 0; + + if (amdgpu_sriov_vf(adev)) + return 0; + + irq_src->num_types = 1; + irq_src->funcs = &smu_v15_0_8_irq_funcs; + + ret = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_MP1, + IH_INTERRUPT_ID_TO_DRIVER, + irq_src); + if (ret) + return ret; + + return ret; +} + +static int smu_v15_0_8_notify_unload(struct smu_context *smu) +{ + if (amdgpu_in_reset(smu->adev)) + return 0; + + dev_dbg(smu->adev->dev, "Notify PMFW about driver unload"); + /* Ignore return, just intimate FW that driver is not going to be there */ + smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL); + + return 0; +} + + +static int smu_v15_0_8_system_features_control(struct smu_context *smu, + bool enable) +{ + struct amdgpu_device *adev = smu->adev; + int ret = 0; + + if (amdgpu_sriov_vf(adev)) + return 0; + + if (enable) + ret = smu_v15_0_system_features_control(smu, enable); + else + smu_v15_0_8_notify_unload(smu); + + return ret; +} + +/** + * smu_v15_0_8_get_enabled_mask - Get enabled SMU features (128-bit) + * @smu: SMU context + * @feature_mask: feature mask structure + * + * SMU 15 returns all 128 feature bits in a single message via out_args[0..3]. + * For backward compatibility, this function returns only the first 64 bits. + * + * Return: 0 on success, negative errno on failure + */ +static int smu_v15_0_8_get_enabled_mask(struct smu_context *smu, + struct smu_feature_bits *feature_mask) +{ + struct smu_msg_args args = { + .msg = SMU_MSG_GetEnabledSmuFeatures, + .num_args = 0, + .num_out_args = 2, + }; + int ret; + + if (!feature_mask) + return -EINVAL; + + ret = smu->msg_ctl.ops->send_msg(&smu->msg_ctl, &args); + + if (ret) + return ret; + + smu_feature_bits_from_arr32(feature_mask, args.out_args, + SMU_FEATURE_NUM_DEFAULT); + + return 0; +} + +static bool smu_v15_0_8_is_dpm_running(struct smu_context *smu) +{ + int ret = 0; + struct smu_feature_bits feature_enabled; + + ret = smu_v15_0_8_get_enabled_mask(smu, &feature_enabled); + if (ret) + return false; + + return smu_feature_bits_test_mask(&feature_enabled, + smu_v15_0_8_dpm_features.bits); +} + +static ssize_t smu_v15_0_8_get_pm_metrics(struct smu_context *smu, + void *metrics, size_t max_size) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct amdgpu_pm_metrics *pm_metrics = (struct amdgpu_pm_metrics *)metrics; + uint32_t table_version = smu_table->tables[SMU_TABLE_SMU_METRICS].version; + uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size; + uint32_t pmfw_version; + int ret; + + if (!pm_metrics || !max_size) + return -EINVAL; + + if (max_size < (table_size + sizeof(pm_metrics->common_header))) + return -EOVERFLOW; + + /* Don't use cached metrics data */ + ret = smu_v15_0_8_get_metrics_table_internal(smu, 0, pm_metrics->data); + if (ret) + return ret; + + smu_cmn_get_smc_version(smu, NULL, &pmfw_version); + memset(&pm_metrics->common_header, 0, sizeof(pm_metrics->common_header)); + pm_metrics->common_header.mp1_ip_discovery_version = + amdgpu_ip_version(smu->adev, MP1_HWIP, 0); + pm_metrics->common_header.pmfw_version = pmfw_version; + pm_metrics->common_header.pmmetrics_version = table_version; + pm_metrics->common_header.structure_size = + sizeof(pm_metrics->common_header) + table_size; + + return pm_metrics->common_header.structure_size; +} + +static int smu_v15_0_8_mode2_reset(struct smu_context *smu) +{ + struct smu_msg_ctl *ctl = &smu->msg_ctl; + struct amdgpu_device *adev = smu->adev; + int timeout = 10; + int ret = 0; + + mutex_lock(&ctl->lock); + + ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, + SMU_RESET_MODE_2); + + if (ret) + goto out; + + /* Reset takes a bit longer, wait for 200ms. */ + msleep(200); + + dev_dbg(adev->dev, "wait for reset ack\n"); + do { + ret = smu_msg_wait_response(ctl, 0); + /* Wait a bit more time for getting ACK */ + if (ret == -ETIME) { + --timeout; + usleep_range(500, 1000); + continue; + } + + if (ret) + goto out; + + } while (ret == -ETIME && timeout); + +out: + mutex_unlock(&ctl->lock); + + if (ret) + dev_err(adev->dev, "failed to send mode2 reset, error code %d", + ret); + + return ret; +} + +static bool smu_v15_0_8_is_temp_metrics_supported(struct smu_context *smu, + enum smu_temp_metric_type type) +{ + switch (type) { + case SMU_TEMP_METRIC_BASEBOARD: + if (smu->adev->gmc.xgmi.physical_node_id == 0) + return true; + return false; + case SMU_TEMP_METRIC_GPUBOARD: + return true; + default: + return false; + } +} + +static void smu_v15_0_8_fill_baseboard_temp_metrics( + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics, + const SystemMetricsTable_t *metrics) +{ + baseboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; + baseboard_temp_metrics->label_version = metrics->LabelVersion; + baseboard_temp_metrics->node_id = metrics->NodeIdentifier; + + baseboard_temp_metrics->system_temp_ubb_fpga = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA]; + baseboard_temp_metrics->system_temp_ubb_front = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FRONT]; + baseboard_temp_metrics->system_temp_ubb_back = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_BACK]; + baseboard_temp_metrics->system_temp_ubb_oam7 = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_OAM7]; + baseboard_temp_metrics->system_temp_ubb_ibc = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_IBC]; + baseboard_temp_metrics->system_temp_ubb_ufpga = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_UFPGA]; + baseboard_temp_metrics->system_temp_ubb_oam1 = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_OAM1]; + baseboard_temp_metrics->system_temp_oam_0_1_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_0_1_HSC]; + baseboard_temp_metrics->system_temp_oam_2_3_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_2_3_HSC]; + baseboard_temp_metrics->system_temp_oam_4_5_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_4_5_HSC]; + baseboard_temp_metrics->system_temp_oam_6_7_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_6_7_HSC]; + baseboard_temp_metrics->system_temp_ubb_fpga_0v72_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA_0V72_VR]; + baseboard_temp_metrics->system_temp_ubb_fpga_3v3_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_UBB_FPGA_3V3_VR]; + baseboard_temp_metrics->system_temp_retimer_0_1_2_3_1v2_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR]; + baseboard_temp_metrics->system_temp_retimer_4_5_6_7_1v2_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR]; + baseboard_temp_metrics->system_temp_retimer_0_1_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_0_1_0V9_VR]; + baseboard_temp_metrics->system_temp_retimer_4_5_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_4_5_0V9_VR]; + baseboard_temp_metrics->system_temp_retimer_2_3_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_2_3_0V9_VR]; + baseboard_temp_metrics->system_temp_retimer_6_7_0v9_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_RETIMER_6_7_0V9_VR]; + baseboard_temp_metrics->system_temp_oam_0_1_2_3_3v3_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR]; + baseboard_temp_metrics->system_temp_oam_4_5_6_7_3v3_vr = + metrics->SystemTemperatures[SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR]; + baseboard_temp_metrics->system_temp_ibc_hsc = + metrics->SystemTemperatures[SYSTEM_TEMP_IBC_HSC]; + baseboard_temp_metrics->system_temp_ibc = + metrics->SystemTemperatures[SYSTEM_TEMP_IBC]; +} + +static void smu_v15_0_8_fill_gpuboard_temp_metrics( + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics, + const SystemMetricsTable_t *metrics) +{ + gpuboard_temp_metrics->accumulation_counter = metrics->AccumulationCounter; + gpuboard_temp_metrics->label_version = metrics->LabelVersion; + gpuboard_temp_metrics->node_id = metrics->NodeIdentifier; + + gpuboard_temp_metrics->node_temp_retimer = + metrics->NodeTemperatures[NODE_TEMP_RETIMER]; + gpuboard_temp_metrics->node_temp_ibc = + metrics->NodeTemperatures[NODE_TEMP_IBC_TEMP]; + gpuboard_temp_metrics->node_temp_ibc_2 = + metrics->NodeTemperatures[NODE_TEMP_IBC_2_TEMP]; + gpuboard_temp_metrics->node_temp_vdd18_vr = + metrics->NodeTemperatures[NODE_TEMP_VDD18_VR_TEMP]; + gpuboard_temp_metrics->node_temp_04_hbm_b_vr = + metrics->NodeTemperatures[NODE_TEMP_04_HBM_B_VR_TEMP]; + gpuboard_temp_metrics->node_temp_04_hbm_d_vr = + metrics->NodeTemperatures[NODE_TEMP_04_HBM_D_VR_TEMP]; + + gpuboard_temp_metrics->vr_temp_vddcr_socio_a = + metrics->VrTemperatures[SVI_PLANE_VDDCR_SOCIO_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_socio_c = + metrics->VrTemperatures[SVI_PLANE_VDDCR_SOCIO_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_x0 = + metrics->VrTemperatures[SVI_PLANE_VDDCR_X0_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_x1 = + metrics->VrTemperatures[SVI_PLANE_VDDCR_X1_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDIO_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDIO_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_04_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDIO_04_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_04_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDIO_04_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDCR_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDCR_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_075_hbm_b = + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_HBM_B_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_075_hbm_d = + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_HBM_D_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_11_gta_a = + metrics->VrTemperatures[SVI_PLANE_VDDIO_11_GTA_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_11_gta_c = + metrics->VrTemperatures[SVI_PLANE_VDDIO_11_GTA_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddan_075_gta_a = + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_GTA_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddan_075_gta_c = + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_GTA_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddcr_075_ucie = + metrics->VrTemperatures[SVI_PLANE_VDDCR_075_UCIE_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_065_ucieaa = + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAA_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_065_ucieam_a = + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAM_A_TEMP]; + gpuboard_temp_metrics->vr_temp_vddio_065_ucieam_c = + metrics->VrTemperatures[SVI_PLANE_VDDIO_065_UCIEAM_C_TEMP]; + gpuboard_temp_metrics->vr_temp_vddan_075 = + metrics->VrTemperatures[SVI_PLANE_VDDAN_075_TEMP]; +} + +static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu, + enum smu_temp_metric_type type, + void *table) +{ + struct smu_v15_0_8_baseboard_temp_metrics *baseboard_temp_metrics; + struct smu_v15_0_8_gpuboard_temp_metrics *gpuboard_temp_metrics; + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_table *tables = smu_table->tables; + SystemMetricsTable_t *metrics; + struct smu_table *sys_table; + int ret; + + ret = smu_v15_0_8_get_system_metrics_table(smu); + if (ret) + return ret; + + sys_table = &tables[SMU_TABLE_PMFW_SYSTEM_METRICS]; + metrics = (SystemMetricsTable_t *)sys_table->cache.buffer; + + switch (type) { + case SMU_TEMP_METRIC_GPUBOARD: + gpuboard_temp_metrics = + (struct smu_v15_0_8_gpuboard_temp_metrics *) + smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPUBOARD_TEMP_METRICS); + smu_v15_0_8_fill_gpuboard_temp_metrics(gpuboard_temp_metrics, + metrics); + memcpy(table, gpuboard_temp_metrics, sizeof(*gpuboard_temp_metrics)); + return sizeof(*gpuboard_temp_metrics); + case SMU_TEMP_METRIC_BASEBOARD: + baseboard_temp_metrics = + (struct smu_v15_0_8_baseboard_temp_metrics *) + smu_driver_table_ptr(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_BASEBOARD_TEMP_METRICS); + smu_v15_0_8_fill_baseboard_temp_metrics(baseboard_temp_metrics, + metrics); + memcpy(table, baseboard_temp_metrics, sizeof(*baseboard_temp_metrics)); + return sizeof(*baseboard_temp_metrics); + default: + return -EINVAL; + } +} + +static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table) +{ + struct smu_table_context *smu_table = &smu->smu_table; + struct smu_v15_0_8_gpu_metrics *gpu_metrics; + struct amdgpu_device *adev = smu->adev; + int ret = 0, xcc_id, inst, i, j, idx; + uint32_t aid_mask = adev->aid_mask; + uint32_t mid_mask = adev->aid_mask; + MetricsTable_t *metrics; + + metrics = kzalloc(sizeof(MetricsTable_t), GFP_KERNEL); + + ret = smu_v15_0_8_get_metrics_table_internal(smu, 1, NULL); + if (ret) + return ret; + + metrics = (MetricsTable_t *)smu_table->metrics_table; + gpu_metrics = (struct smu_v15_0_8_gpu_metrics *)smu_driver_table_ptr(smu, + SMU_DRIVER_TABLE_GPU_METRICS); + + gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); + + gpu_metrics->temperature_hotspot = SMUQ10_ROUND(metrics->MaxSocketTemperature); + + /* Per-HBM stack temperatures */ + if (adev->umc.active_mask) { + u64 mask = adev->umc.active_mask; + int out_idx = 0; + int stack_idx; + + if (unlikely(hweight64(mask)/4 > SMU_15_0_8_MAX_HBM_STACKS)) + dev_warn(adev->dev, "Invalid umc mask %lld\n", mask); + else { + for_each_hbm_stack(stack_idx, mask) { + if (!hbm_stack_mask_valid(mask)) + continue; + gpu_metrics->temperature_hbm[out_idx++] = + SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]); + } + } + } + + /* Reports max temperature of all voltage rails */ + gpu_metrics->temperature_vrsoc = SMUQ10_ROUND(metrics->MaxVrTemperature); + /* MID, AID, XCD temperatures */ + idx = 0; + for_each_inst(i, mid_mask) { + gpu_metrics->temperature_mid[idx] = SMUQ10_ROUND(metrics->MidTemperature[i]); + idx++; + } + + idx = 0; + for_each_inst(i, aid_mask) { + gpu_metrics->temperature_aid[idx] = SMUQ10_ROUND(metrics->AidTemperature[i]); + idx++; + } + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + xcc_id = GET_INST(GC, i); + if (xcc_id >= 0) + gpu_metrics->temperature_xcd[i] = SMUQ10_ROUND(metrics->XcdTemperature[xcc_id]); + } + /* Power */ + gpu_metrics->curr_socket_power = SMUQ10_ROUND(metrics->SocketPower); + + gpu_metrics->average_gfx_activity = SMUQ10_ROUND(metrics->SocketGfxBusy); + gpu_metrics->average_umc_activity = SMUQ10_ROUND(metrics->DramBandwidthUtilization); + gpu_metrics->mem_max_bandwidth = SMUQ10_ROUND(metrics->MaxDramBandwidth); + + /* Energy counter reported in 15.259uJ (2^-16) units */ + gpu_metrics->energy_accumulator = metrics->SocketEnergyAcc; + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + xcc_id = GET_INST(GC, i); + if (xcc_id >= 0) { + gpu_metrics->current_gfxclk[i] = + SMUQ10_ROUND(metrics->GfxclkFrequency[xcc_id]); + } + } + + /* Per-MID clocks */ + idx = 0; + for_each_inst(i, mid_mask) { + gpu_metrics->current_socclk[idx] = SMUQ10_ROUND(metrics->SocclkFrequency[i]); + idx++; + } + + /* Per-VCN clocks */ + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + inst = GET_INST(VCN, i); + if (inst >= 0) { + gpu_metrics->current_vclk0[i] = SMUQ10_ROUND(metrics->VclkFrequency[inst]); + gpu_metrics->current_dclk0[i] = SMUQ10_ROUND(metrics->DclkFrequency[inst]); + } + } + + /* Per-AID clocks */ + idx = 0; + for_each_inst(i, aid_mask) { + gpu_metrics->current_uclk[idx] = SMUQ10_ROUND(metrics->UclkFrequency[i]); + idx++; + } + + /* Total accumulated cycle counter */ + gpu_metrics->accumulation_counter = metrics->AccumulationCounter; + + /* Accumulated throttler residencies */ + gpu_metrics->prochot_residency_acc = metrics->ProchotResidencyAcc; + gpu_metrics->ppt_residency_acc = metrics->PptResidencyAcc; + gpu_metrics->socket_thm_residency_acc = metrics->SocketThmResidencyAcc; + gpu_metrics->vr_thm_residency_acc = metrics->VrThmResidencyAcc; + gpu_metrics->hbm_thm_residency_acc = metrics->HbmThmResidencyAcc; + + gpu_metrics->gfx_activity_acc = SMUQ10_ROUND(metrics->SocketGfxBusyAcc); + gpu_metrics->mem_activity_acc = SMUQ10_ROUND(metrics->DramBandwidthUtilizationAcc); + + for (i = 0; i < NUM_XGMI_LINKS; i++) { + j = amdgpu_xgmi_get_ext_link(adev, i); + if (j < 0 || j >= NUM_XGMI_LINKS) + continue; + ret = amdgpu_get_xgmi_link_status(adev, i); + if (ret >= 0) + gpu_metrics->xgmi_link_status[j] = ret; + } + + gpu_metrics->xgmi_read_data_acc = SMUQ10_ROUND(metrics->XgmiReadBandwidthAcc); + gpu_metrics->xgmi_write_data_acc = SMUQ10_ROUND(metrics->XgmiWriteBandwidthAcc); + + for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) { + inst = GET_INST(GC, i); + gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND(metrics->GfxBusy[inst]); + gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]); + gpu_metrics->gfx_below_host_limit_ppt_acc[i] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]); + gpu_metrics->gfx_below_host_limit_thm_acc[i] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]); + gpu_metrics->gfx_low_utilization_acc[i] = + SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]); + gpu_metrics->gfx_below_host_limit_total_acc[i] = + SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]); + } + + gpu_metrics->xgmi_link_width = metrics->XgmiWidth; + gpu_metrics->xgmi_link_speed = metrics->XgmiBitrate; + + gpu_metrics->firmware_timestamp = metrics->Timestamp; + + *table = gpu_metrics; + + smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS); + + return sizeof(*gpu_metrics); +} + +static void smu_v15_0_8_get_unique_id(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + + adev->unique_id = pptable->PublicSerialNumberMID; +} + +static int smu_v15_0_8_get_power_limit(struct smu_context *smu, + uint32_t *current_power_limit, + uint32_t *default_power_limit, + uint32_t *max_power_limit, + uint32_t *min_power_limit) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + uint32_t power_limit = 0; + int ret; + + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit); + if (ret) { + dev_err(smu->adev->dev, "Couldn't get PPT limit"); + return -EINVAL; + } + + if (current_power_limit) + *current_power_limit = power_limit; + + if (default_power_limit) + *max_power_limit = pptable->MaxSocketPowerLimit; + + if (max_power_limit) + *max_power_limit = pptable->MaxSocketPowerLimit; + + if (min_power_limit) + *min_power_limit = 0; + + return 0; +} + +static int smu_v15_0_8_populate_umd_state_clk(struct smu_context *smu) +{ + struct smu_15_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + + pstate_table->gfxclk_pstate.curr.min = SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = SMU_DPM_TABLE_MAX(gfx_table); + + pstate_table->uclk_pstate.curr.min = SMU_DPM_TABLE_MIN(mem_table); + pstate_table->uclk_pstate.curr.max = SMU_DPM_TABLE_MAX(mem_table); + return 0; +} + +static int smu_v15_0_8_set_gfx_soft_freq_limited_range(struct smu_context *smu, + uint32_t min, + uint32_t max) +{ + int ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk, + max & 0xffff, NULL); + if (ret) + return ret; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk, + min & 0xffff, NULL); + + return ret; +} + +static int smu_v15_0_8_set_performance_level(struct smu_context *smu, + enum amd_dpm_forced_level level) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_15_0_dpm_context *dpm_context = smu_dpm->dpm_context; + struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table; + struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + int ret; + + switch (level) { + case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM: + /* Determinism not supported on SMU v15.0.8 */ + ret = -EOPNOTSUPP; + break; + + case AMD_DPM_FORCED_LEVEL_AUTO: + /* Restore GFXCLK to default range */ + if ((SMU_DPM_TABLE_MIN(gfx_table) != + pstate_table->gfxclk_pstate.curr.min) || + (SMU_DPM_TABLE_MAX(gfx_table) != + pstate_table->gfxclk_pstate.curr.max)) { + ret = smu_v15_0_8_set_gfx_soft_freq_limited_range( + smu, SMU_DPM_TABLE_MIN(gfx_table), + SMU_DPM_TABLE_MAX(gfx_table)); + if (ret) + goto out; + + pstate_table->gfxclk_pstate.curr.min = + SMU_DPM_TABLE_MIN(gfx_table); + pstate_table->gfxclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(gfx_table); + } + + /* Restore UCLK to default max */ + if (SMU_DPM_TABLE_MAX(uclk_table) != + pstate_table->uclk_pstate.curr.max) { + /* Min UCLK is not expected to be changed */ + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_UCLK, 0, + SMU_DPM_TABLE_MAX(uclk_table), + false); + if (ret) + goto out; + + pstate_table->uclk_pstate.curr.max = + SMU_DPM_TABLE_MAX(uclk_table); + } + + if (ret) + goto out; + + smu_cmn_reset_custom_level(smu); + + break; + case AMD_DPM_FORCED_LEVEL_MANUAL: + ret = 0; + break; + default: + ret = -EOPNOTSUPP; + break; + } + +out: + return ret; +} + +static int smu_v15_0_8_set_soft_freq_limited_range(struct smu_context *smu, + enum smu_clk_type clk_type, + uint32_t min, uint32_t max, + bool automatic) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + int ret = 0; + + if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK && + clk_type != SMU_UCLK) + return -EINVAL; + + if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) { + if (min >= max) { + dev_err(smu->adev->dev, + "Minimum clk should be less than the maximum allowed clock\n"); + return -EINVAL; + } + + if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) { + if ((min == pstate_table->gfxclk_pstate.curr.min) && + (max == pstate_table->gfxclk_pstate.curr.max)) + return 0; + + ret = smu_v15_0_8_set_gfx_soft_freq_limited_range(smu, + min, max); + if (!ret) { + pstate_table->gfxclk_pstate.curr.min = min; + pstate_table->gfxclk_pstate.curr.max = max; + } + } + + if (clk_type == SMU_UCLK) { + if (max == pstate_table->uclk_pstate.curr.max) + return 0; + + ret = smu_v15_0_set_soft_freq_limited_range(smu, + SMU_UCLK, + 0, max, + false); + if (!ret) + pstate_table->uclk_pstate.curr.max = max; + } + + return ret; + } + + return 0; +} + +static int smu_v15_0_8_od_edit_dpm_table(struct smu_context *smu, + enum PP_OD_DPM_TABLE_COMMAND type, + long input[], uint32_t size) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + struct smu_15_0_dpm_context *dpm_context = smu_dpm->dpm_context; + uint32_t min_clk, max_clk; + int ret; + + /* Only allowed in manual mode */ + if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_OD_EDIT_SCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); + if (input[0] == 0) { + if (input[1] < min_clk) { + dev_warn(smu->adev->dev, + "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n", + input[1], min_clk); + pstate_table->gfxclk_pstate.custom.min = + pstate_table->gfxclk_pstate.curr.min; + return -EINVAL; + } + + pstate_table->gfxclk_pstate.custom.min = input[1]; + } else if (input[0] == 1) { + if (input[1] > max_clk) { + dev_warn(smu->adev->dev, + "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); + pstate_table->gfxclk_pstate.custom.max = + pstate_table->gfxclk_pstate.curr.max; + return -EINVAL; + } + + pstate_table->gfxclk_pstate.custom.max = input[1]; + } else { + return -EINVAL; + } + break; + case PP_OD_EDIT_MCLK_VDDC_TABLE: + if (size != 2) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + dev_warn(smu->adev->dev, + "UCLK_LIMITS setting not supported!\n"); + return -EOPNOTSUPP; + } + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + if (input[0] == 0) { + dev_info(smu->adev->dev, + "Setting min UCLK level is not supported"); + return -EINVAL; + } else if (input[0] == 1) { + if (input[1] > max_clk) { + dev_warn(smu->adev->dev, + "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n", + input[1], max_clk); + pstate_table->uclk_pstate.custom.max = + pstate_table->uclk_pstate.curr.max; + + return -EINVAL; + } + + pstate_table->uclk_pstate.custom.max = input[1]; + } + break; + case PP_OD_RESTORE_DEFAULT_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + /* Use the default frequencies for manual mode */ + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table); + + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_GFXCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + + min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table); + max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table); + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_UCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + + smu_cmn_reset_custom_level(smu); + break; + case PP_OD_COMMIT_DPM_TABLE: + if (size != 0) { + dev_err(smu->adev->dev, + "Input parameter number not correct\n"); + return -EINVAL; + } + + if (!pstate_table->gfxclk_pstate.custom.min) + pstate_table->gfxclk_pstate.custom.min = + pstate_table->gfxclk_pstate.curr.min; + + if (!pstate_table->gfxclk_pstate.custom.max) + pstate_table->gfxclk_pstate.custom.max = + pstate_table->gfxclk_pstate.curr.max; + + min_clk = pstate_table->gfxclk_pstate.custom.min; + max_clk = pstate_table->gfxclk_pstate.custom.max; + + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_GFXCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + + /* Commit UCLK custom range (only max supported) */ + if (pstate_table->uclk_pstate.custom.max) { + min_clk = pstate_table->uclk_pstate.curr.min; + max_clk = pstate_table->uclk_pstate.custom.max; + ret = smu_v15_0_8_set_soft_freq_limited_range(smu, + SMU_UCLK, + min_clk, max_clk, + false); + if (ret) + return ret; + } + + break; + default: + return -ENOSYS; + } + + return 0; +} + +static int smu_v15_0_8_get_thermal_temperature_range(struct smu_context *smu, + struct smu_temperature_range *range) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + uint32_t max_ctf, max_thm; + + if (amdgpu_sriov_multi_vf_mode(smu->adev)) + return 0; + + if (!range) + return -EINVAL; + + /* CTF (Critical Temperature Fault) limits */ + max_ctf = max3(pptable->CTFLimitMID, pptable->CTFLimitXCD, + pptable->CTFLimitAID); + range->hotspot_emergency_max = max_ctf * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + range->mem_emergency_max = pptable->CTFLimitHBM * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + /* Thermal throttling limits */ + max_thm = max3(pptable->ThermalLimitMID, pptable->ThermalLimitXCD, + pptable->ThermalLimitAID); + range->hotspot_crit_max = max_thm * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + range->mem_crit_max = pptable->ThermalLimitHBM * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + + return 0; +} + +static int smu_v15_0_8_set_power_limit(struct smu_context *smu, + enum smu_ppt_limit_type limit_type, + uint32_t limit) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int ret; + + if (limit_type == SMU_FAST_PPT_LIMIT) { + if (!pptable->PPT1Max) + return -EOPNOTSUPP; + + if (limit > pptable->PPT1Max || limit < pptable->PPT1Min) { + dev_err(smu->adev->dev, + "New PPT1 limit (%d) should be between min %d and max %d\n", + limit, pptable->PPT1Min, pptable->PPT1Max); + return -EINVAL; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetFastPptLimit, + limit, NULL); + if (ret) + dev_err(smu->adev->dev, "Set fast PPT limit failed!\n"); + + return ret; + } + + return smu_v15_0_set_power_limit(smu, limit_type, limit); +} + +static int smu_v15_0_8_get_ppt_limit(struct smu_context *smu, + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) +{ + struct smu_table_context *smu_table = &smu->smu_table; + PPTable_t *pptable = (PPTable_t *)smu_table->driver_pptable; + int ret = 0; + + if (!ppt_limit) + return -EINVAL; + + if (type == SMU_FAST_PPT_LIMIT) { + if (!pptable->PPT1Max) + return -EOPNOTSUPP; + + switch (level) { + case SMU_PPT_LIMIT_MAX: + *ppt_limit = pptable->PPT1Max; + break; + case SMU_PPT_LIMIT_CURRENT: + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPptLimit, + ppt_limit); + if (ret) + dev_err(smu->adev->dev, + "Get fast PPT limit failed!\n"); + break; + case SMU_PPT_LIMIT_DEFAULT: + *ppt_limit = pptable->PPT1Default; + break; + case SMU_PPT_LIMIT_MIN: + *ppt_limit = pptable->PPT1Min; + break; + default: + return -EOPNOTSUPP; + } + return ret; + } + + return -EOPNOTSUPP; +} + +static const struct pptable_funcs smu_v15_0_8_ppt_funcs = { + .init_allowed_features = smu_v15_0_8_init_allowed_features, + .set_default_dpm_table = smu_v15_0_8_set_default_dpm_table, + .is_dpm_running = smu_v15_0_8_is_dpm_running, + .init_smc_tables = smu_v15_0_8_init_smc_tables, + .fini_smc_tables = smu_v15_0_8_fini_smc_tables, + .init_power = smu_v15_0_init_power, + .fini_power = smu_v15_0_fini_power, + .check_fw_status = smu_v15_0_8_check_fw_status, + .check_fw_version = smu_cmn_check_fw_version, + .set_driver_table_location = smu_v15_0_set_driver_table_location, + .set_tool_table_location = smu_v15_0_set_tool_table_location, + .notify_memory_pool_location = smu_v15_0_notify_memory_pool_location, + .system_features_control = smu_v15_0_8_system_features_control, + .get_enabled_mask = smu_v15_0_8_get_enabled_mask, + .feature_is_enabled = smu_cmn_feature_is_enabled, + .register_irq_handler = smu_v15_0_8_register_irq_handler, + .setup_pptable = smu_v15_0_8_setup_pptable, + .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, + .wait_for_event = smu_v15_0_wait_for_event, + .get_pm_metrics = smu_v15_0_8_get_pm_metrics, + .mode2_reset = smu_v15_0_8_mode2_reset, + .get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq, + .get_gpu_metrics = smu_v15_0_8_get_gpu_metrics, + .get_unique_id = smu_v15_0_8_get_unique_id, + .get_power_limit = smu_v15_0_8_get_power_limit, + .set_power_limit = smu_v15_0_8_set_power_limit, + .get_ppt_limit = smu_v15_0_8_get_ppt_limit, + .emit_clk_levels = smu_v15_0_8_emit_clk_levels, + .read_sensor = smu_v15_0_8_read_sensor, + .populate_umd_state_clk = smu_v15_0_8_populate_umd_state_clk, + .set_performance_level = smu_v15_0_8_set_performance_level, + .od_edit_dpm_table = smu_v15_0_8_od_edit_dpm_table, + .get_thermal_temperature_range = smu_v15_0_8_get_thermal_temperature_range, +}; + +static void smu_v15_0_8_init_msg_ctl(struct smu_context *smu, + const struct cmn2asic_msg_mapping *message_map) +{ + struct amdgpu_device *adev = smu->adev; + struct smu_msg_ctl *ctl = &smu->msg_ctl; + + ctl->smu = smu; + mutex_init(&ctl->lock); + ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_40); + ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_41); + ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_42); + ctl->config.arg_regs[1] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_43); + ctl->config.arg_regs[2] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_44); + ctl->config.arg_regs[3] = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_45); + ctl->config.num_arg_regs = 4; + ctl->ops = &smu_msg_v1_ops; + ctl->default_timeout = adev->usec_timeout * 20; + ctl->message_map = message_map; +} + +static const struct smu_temp_funcs smu_v15_0_8_temp_funcs = { + .temp_metrics_is_supported = smu_v15_0_8_is_temp_metrics_supported, + .get_temp_metrics = smu_v15_0_8_get_temp_metrics, +}; + +void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu) +{ + smu->ppt_funcs = &smu_v15_0_8_ppt_funcs; + smu->clock_map = smu_v15_0_8_clk_map; + smu->feature_map = smu_v15_0_8_feature_mask_map; + smu->table_map = smu_v15_0_8_table_map; + smu_v15_0_8_init_msg_ctl(smu, smu_v15_0_8_message_map); + smu->smu_temp.temp_funcs = &smu_v15_0_8_temp_funcs; + smu->smc_driver_if_version = SMU15_DRIVER_IF_VERSION_SMU_V15_0_8; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h new file mode 100644 index 0000000000000..398ce44821741 --- /dev/null +++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h @@ -0,0 +1,313 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __SMU_15_0_8_PPT_H__ +#define __SMU_15_0_8_PPT_H__ + +#define SMU_15_0_8_NUM_XGMI_LINKS 8 +#define SMU_15_0_8_MAX_GFX_CLKS 8 +#define SMU_15_0_8_MAX_CLKS 4 +#define SMU_15_0_8_MAX_XCC 8 +#define SMU_15_0_8_MAX_VCN 4 +#define SMU_15_0_8_MAX_JPEG 40 +#define SMU_15_0_8_MAX_AID 2 +#define SMU_15_0_8_MAX_MID 2 +#define SMU_15_0_8_MAX_HBM_STACKS 12 +extern void smu_v15_0_8_set_ppt_funcs(struct smu_context *smu); + +typedef struct { + uint32_t MaxSocketPowerLimit; + uint32_t MaxGfxclkFrequency; + uint32_t MinGfxclkFrequency; + uint32_t MaxFclkFrequency; + uint32_t MinFclkFrequency; + uint32_t MaxGl2clkFrequency; + uint32_t MinGl2clkFrequency; + uint32_t UclkFrequencyTable[4]; + uint32_t SocclkFrequency; + uint32_t LclkFrequency; + uint32_t VclkFrequency; + uint32_t DclkFrequency; + uint32_t CTFLimitMID; + uint32_t CTFLimitAID; + uint32_t CTFLimitXCD; + uint32_t CTFLimitHBM; + uint32_t ThermalLimitMID; + uint32_t ThermalLimitAID; + uint32_t ThermalLimitXCD; + uint32_t ThermalLimitHBM; + uint64_t PublicSerialNumberMID; + uint64_t PublicSerialNumberAID; + uint64_t PublicSerialNumberXCD; + uint32_t PPT1Max; + uint32_t PPT1Min; + uint32_t PPT1Default; + bool init; +} PPTable_t; + +#if defined(SWSMU_CODE_LAYER_L2) +#include "smu_cmn.h" + +/* SMUv 15.0.8 GPU metrics*/ +#define SMU_15_0_8_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_HOTSPOT), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hotspot); \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_MEM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_mem); \ + SMU_SCALAR(SMU_MATTR(TEMPERATURE_VRSOC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_vrsoc); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_HBM), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_hbm, \ + SMU_15_0_8_MAX_HBM_STACKS); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_MID), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_mid, SMU_15_0_8_MAX_MID); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_AID), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_aid, SMU_15_0_8_MAX_AID); \ + SMU_ARRAY(SMU_MATTR(TEMPERATURE_XCD), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(U16), temperature_xcd, SMU_15_0_8_MAX_XCC); \ + SMU_SCALAR(SMU_MATTR(CURR_SOCKET_POWER), SMU_MUNIT(POWER_1), \ + SMU_MTYPE(U16), curr_socket_power); \ + SMU_SCALAR(SMU_MATTR(AVERAGE_GFX_ACTIVITY), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U16), average_gfx_activity); \ + SMU_SCALAR(SMU_MATTR(AVERAGE_UMC_ACTIVITY), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U16), average_umc_activity); \ + SMU_SCALAR(SMU_MATTR(MEM_MAX_BANDWIDTH), SMU_MUNIT(BW_1), \ + SMU_MTYPE(U64), mem_max_bandwidth); \ + SMU_SCALAR(SMU_MATTR(ENERGY_ACCUMULATOR), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), energy_accumulator); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_CLOCK_COUNTER), SMU_MUNIT(TIME_1), \ + SMU_MTYPE(U64), system_clock_counter); \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(PROCHOT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), prochot_residency_acc); \ + SMU_SCALAR(SMU_MATTR(PPT_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), ppt_residency_acc); \ + SMU_SCALAR(SMU_MATTR(SOCKET_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), socket_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(VR_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), vr_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(HBM_THM_RESIDENCY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), hbm_thm_residency_acc); \ + SMU_SCALAR(SMU_MATTR(GFXCLK_LOCK_STATUS), SMU_MUNIT(NONE), \ + SMU_MTYPE(U32), gfxclk_lock_status); \ + SMU_SCALAR(SMU_MATTR(PCIE_LINK_WIDTH), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), pcie_link_width); \ + SMU_SCALAR(SMU_MATTR(PCIE_LINK_SPEED), SMU_MUNIT(SPEED_2), \ + SMU_MTYPE(U16), pcie_link_speed); \ + SMU_SCALAR(SMU_MATTR(XGMI_LINK_WIDTH), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), xgmi_link_width); \ + SMU_SCALAR(SMU_MATTR(XGMI_LINK_SPEED), SMU_MUNIT(SPEED_1), \ + SMU_MTYPE(U16), xgmi_link_speed); \ + SMU_SCALAR(SMU_MATTR(GFX_ACTIVITY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_activity_acc); \ + SMU_SCALAR(SMU_MATTR(MEM_ACTIVITY_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), mem_activity_acc); \ + SMU_ARRAY(SMU_MATTR(PCIE_BANDWIDTH_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_bandwidth_acc, SMU_15_0_8_MAX_MID); \ + SMU_ARRAY(SMU_MATTR(PCIE_BANDWIDTH_INST), SMU_MUNIT(BW_1), \ + SMU_MTYPE(U32), pcie_bandwidth_inst, SMU_15_0_8_MAX_MID); \ + SMU_SCALAR(SMU_MATTR(PCIE_L0_TO_RECOV_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_l0_to_recov_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_replay_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_REPLAY_ROVER_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_replay_rover_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_NAK_SENT_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_nak_sent_count_acc); \ + SMU_SCALAR(SMU_MATTR(PCIE_NAK_RCVD_COUNT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), pcie_nak_rcvd_count_acc); \ + SMU_ARRAY(SMU_MATTR(XGMI_LINK_STATUS), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), xgmi_link_status, \ + SMU_15_0_8_NUM_XGMI_LINKS); \ + SMU_SCALAR(SMU_MATTR(XGMI_READ_DATA_ACC), SMU_MUNIT(DATA_1), \ + SMU_MTYPE(U64), xgmi_read_data_acc); \ + SMU_SCALAR(SMU_MATTR(XGMI_WRITE_DATA_ACC), SMU_MUNIT(DATA_1), \ + SMU_MTYPE(U64), xgmi_write_data_acc); \ + SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2), \ + SMU_MTYPE(U64), firmware_timestamp); \ + SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_gfxclk, SMU_15_0_8_MAX_GFX_CLKS); \ + SMU_ARRAY(SMU_MATTR(CURRENT_SOCCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_socclk, SMU_15_0_8_MAX_MID); \ + SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_vclk0, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_dclk0, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(CURRENT_UCLK), SMU_MUNIT(CLOCK_1), \ + SMU_MTYPE(U16), current_uclk, SMU_15_0_8_MAX_AID); \ + SMU_SCALAR(SMU_MATTR(PCIE_LC_PERF_OTHER_END_RECOVERY), \ + SMU_MUNIT(NONE), SMU_MTYPE(U64), \ + pcie_lc_perf_other_end_recovery); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT), \ + SMU_MTYPE(U32), gfx_busy_inst, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + jpeg_busy, SMU_15_0_8_MAX_JPEG); \ + SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U16), \ + vcn_busy, SMU_15_0_8_MAX_VCN); \ + SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(NONE), SMU_MTYPE(U64), \ + gfx_busy_acc, SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_thm_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_low_utilization_acc, \ + SMU_15_0_8_MAX_XCC); \ + SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), gfx_below_host_limit_total_acc, \ + SMU_15_0_8_MAX_XCC); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpu_metrics, SMU_15_0_8_METRICS_FIELDS); + +/* Maximum temperature sensor counts for system metrics */ +#define SMU_15_0_8_MAX_SYSTEM_TEMP_ENTRIES 32 +#define SMU_15_0_8_MAX_NODE_TEMP_ENTRIES 12 +#define SMU_15_0_8_MAX_VR_TEMP_ENTRIES 22 + +/* SMUv 15.0.8 GPU board temperature metrics */ +#define SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(LABEL_VERSION), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), label_version); \ + SMU_SCALAR(SMU_MATTR(NODE_ID), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), node_id); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_RETIMER), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_retimer); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_IBC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_ibc); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_IBC_2), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_ibc_2); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_VDD18_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_vdd18_vr); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_04_HBM_B_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_04_hbm_b_vr); \ + SMU_SCALAR(SMU_MATTR(NODE_TEMP_04_HBM_D_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), node_temp_04_hbm_d_vr); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_SOCIO_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_socio_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_SOCIO_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_socio_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_X0), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_x0); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_X1), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_x1); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_04_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_04_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_04_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_04_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_HBM_B), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_075_hbm_b); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_HBM_D), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_075_hbm_d); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_11_GTA_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_11_gta_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_11_GTA_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_11_gta_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075_GTA_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddan_075_gta_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075_GTA_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddan_075_gta_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDCR_075_UCIE), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddcr_075_ucie); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAA), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_065_ucieaa); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAM_A), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_065_ucieam_a); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDIO_065_UCIEAM_C), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddio_065_ucieam_c); \ + SMU_SCALAR(SMU_MATTR(VR_TEMP_VDDAN_075), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), vr_temp_vddan_075); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics, + SMU_15_0_8_GPUBOARD_TEMP_METRICS_FIELDS); + +/* SMUv 15.0.8 Baseboard temperature metrics - ID-based approach */ +#define SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY) \ + SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE), \ + SMU_MTYPE(U64), accumulation_counter); \ + SMU_SCALAR(SMU_MATTR(LABEL_VERSION), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), label_version); \ + SMU_SCALAR(SMU_MATTR(NODE_ID), SMU_MUNIT(NONE), \ + SMU_MTYPE(U16), node_id); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_fpga); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FRONT), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_front); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_BACK), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_back); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_OAM7), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_oam7); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_IBC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_ibc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_UFPGA), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_ufpga); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_OAM1), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_oam1); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_0_1_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_0_1_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_2_3_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_2_3_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_4_5_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_4_5_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_6_7_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_6_7_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA_0V72_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_fpga_0v72_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_UBB_FPGA_3V3_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ubb_fpga_3v3_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_0_1_2_3_1V2_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_0_1_2_3_1v2_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_4_5_6_7_1V2_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_4_5_6_7_1v2_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_0_1_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_0_1_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_4_5_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_4_5_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_2_3_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_2_3_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_RETIMER_6_7_0V9_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_retimer_6_7_0v9_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_0_1_2_3_3V3_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_0_1_2_3_3v3_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_OAM_4_5_6_7_3V3_VR), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_oam_4_5_6_7_3v3_vr); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_IBC_HSC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ibc_hsc); \ + SMU_SCALAR(SMU_MATTR(SYSTEM_TEMP_IBC), SMU_MUNIT(TEMP_1), \ + SMU_MTYPE(S16), system_temp_ibc); + +DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_baseboard_temp_metrics, + SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS); +#endif +#endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 4040ff926544f..59e746e571ff1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -53,6 +53,9 @@ static const char * const __smu_message_names[] = { -ENOTSUPP) : \ -EINVAL) +#define SMU_MSG_V1_DEFAULT_RATELIMIT_INTERVAL (5 * HZ) +#define SMU_MSG_V1_DEFAULT_RATELIMIT_BURST 10 + static const char *smu_get_message_name(struct smu_context *smu, enum smu_message_type type) { @@ -62,14 +65,6 @@ static const char *smu_get_message_name(struct smu_context *smu, return __smu_message_names[type]; } -static void smu_cmn_read_arg(struct smu_context *smu, - uint32_t *arg) -{ - struct amdgpu_device *adev = smu->adev; - - *arg = RREG32(smu->param_reg); -} - /* Redefine the SMU error codes here. * * Note that these definitions are redundant and should be removed @@ -87,117 +82,134 @@ static void smu_cmn_read_arg(struct smu_context *smu, #define SMU_RESP_DEBUG_END 0xFB #define SMU_RESP_UNEXP (~0U) + +static int smu_msg_v1_send_debug_msg(struct smu_msg_ctl *ctl, u32 msg, u32 param) +{ + struct amdgpu_device *adev = ctl->smu->adev; + struct smu_msg_config *cfg = &ctl->config; + + if (!(ctl->flags & SMU_MSG_CTL_DEBUG_MAILBOX)) + return -EOPNOTSUPP; + + mutex_lock(&ctl->lock); + + WREG32(cfg->debug_param_reg, param); + WREG32(cfg->debug_msg_reg, msg); + WREG32(cfg->debug_resp_reg, 0); + + mutex_unlock(&ctl->lock); + + return 0; +} + +static int __smu_cmn_send_debug_msg(struct smu_msg_ctl *ctl, + u32 msg, + u32 param) +{ + if (!ctl->ops || !ctl->ops->send_debug_msg) + return -EOPNOTSUPP; + + return ctl->ops->send_debug_msg(ctl, msg, param); +} + /** - * __smu_cmn_poll_stat -- poll for a status from the SMU - * @smu: a pointer to SMU context + * smu_cmn_wait_for_response -- wait for response from the SMU + * @smu: pointer to an SMU context * - * Returns the status of the SMU, which could be, - * 0, the SMU is busy with your command; - * 1, execution status: success, execution result: success; - * 0xFF, execution status: success, execution result: failure; - * 0xFE, unknown command; - * 0xFD, valid command, but bad (command) prerequisites; - * 0xFC, the command was rejected as the SMU is busy; - * 0xFB, "SMC_Result_DebugDataDumpEnd". + * Wait for status from the SMU. * - * The values here are not defined by macros, because I'd rather we - * include a single header file which defines them, which is - * maintained by the SMU FW team, so that we're impervious to firmware - * changes. At the moment those values are defined in various header - * files, one for each ASIC, yet here we're a single ASIC-agnostic - * interface. Such a change can be followed-up by a subsequent patch. + * Return 0 on success, -errno on error, indicating the execution + * status and result of the message being waited for. See + * smu_msg_v1_decode_response() for details of the -errno. */ -static u32 __smu_cmn_poll_stat(struct smu_context *smu) +int smu_cmn_wait_for_response(struct smu_context *smu) { - struct amdgpu_device *adev = smu->adev; - int timeout = adev->usec_timeout * 20; - u32 reg; + return smu_msg_wait_response(&smu->msg_ctl, 0); +} - for ( ; timeout > 0; timeout--) { - reg = RREG32(smu->resp_reg); - if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) - break; +/** + * smu_cmn_send_smc_msg_with_param -- send a message with parameter + * @smu: pointer to an SMU context + * @msg: message to send + * @param: parameter to send to the SMU + * @read_arg: pointer to u32 to return a value from the SMU back + * to the caller + * + * Send the message @msg with parameter @param to the SMU, wait for + * completion of the command, and return back a value from the SMU in + * @read_arg pointer. + * + * Return 0 on success, -errno when a problem is encountered sending + * message or receiving reply. If there is a PCI bus recovery or + * the destination is a virtual GPU which does not allow this message + * type, the message is simply dropped and success is also returned. + * See smu_msg_v1_decode_response() for details of the -errno. + * + * If we weren't able to send the message to the SMU, we also print + * the error to the standard log. + * + * Command completion status is printed only if the -errno is + * -EREMOTEIO, indicating that the SMU returned back an + * undefined/unknown/unspecified result. All other cases are + * well-defined, not printed, but instead given back to the client to + * decide what further to do. + * + * The return value, @read_arg is read back regardless, to give back + * more information to the client, which on error would most likely be + * @param, but we can't assume that. This also eliminates more + * conditionals. + */ +int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, + enum smu_message_type msg, + uint32_t param, + uint32_t *read_arg) +{ + struct smu_msg_ctl *ctl = &smu->msg_ctl; + struct smu_msg_args args = { + .msg = msg, + .args[0] = param, + .num_args = 1, + .num_out_args = read_arg ? 1 : 0, + .flags = 0, + .timeout = 0, + }; + int ret; - udelay(1); - } + ret = ctl->ops->send_msg(ctl, &args); - return reg; + if (read_arg) + *read_arg = args.out_args[0]; + + return ret; } -static void __smu_cmn_reg_print_error(struct smu_context *smu, - u32 reg_c2pmsg_90, - int msg_index, - u32 param, - enum smu_message_type msg) +int smu_cmn_send_smc_msg(struct smu_context *smu, + enum smu_message_type msg, + uint32_t *read_arg) { - struct amdgpu_device *adev = smu->adev; - const char *message = smu_get_message_name(smu, msg); - u32 msg_idx, prm; - - switch (reg_c2pmsg_90) { - case SMU_RESP_NONE: { - msg_idx = RREG32(smu->msg_reg); - prm = RREG32(smu->param_reg); - dev_err_ratelimited(adev->dev, - "SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X", - msg_idx, prm); - } - break; - case SMU_RESP_OK: - /* The SMU executed the command. It completed with a - * successful result. - */ - break; - case SMU_RESP_CMD_FAIL: - /* The SMU executed the command. It completed with an - * unsuccessful result. - */ - break; - case SMU_RESP_CMD_UNKNOWN: - dev_err_ratelimited(adev->dev, - "SMU: unknown command: index:%d param:0x%08X message:%s", - msg_index, param, message); - break; - case SMU_RESP_CMD_BAD_PREREQ: - dev_err_ratelimited(adev->dev, - "SMU: valid command, bad prerequisites: index:%d param:0x%08X message:%s", - msg_index, param, message); - break; - case SMU_RESP_BUSY_OTHER: - /* It is normal for SMU_MSG_GetBadPageCount to return busy - * so don't print error at this case. - */ - if (msg != SMU_MSG_GetBadPageCount) - dev_err_ratelimited(adev->dev, - "SMU: I'm very busy for your command: index:%d param:0x%08X message:%s", - msg_index, param, message); - break; - case SMU_RESP_DEBUG_END: - dev_err_ratelimited(adev->dev, - "SMU: I'm debugging!"); - break; - case SMU_RESP_UNEXP: - if (amdgpu_device_bus_status_check(smu->adev)) { - /* print error immediately if device is off the bus */ - dev_err(adev->dev, - "SMU: response:0x%08X for index:%d param:0x%08X message:%s?", - reg_c2pmsg_90, msg_index, param, message); - break; - } - fallthrough; - default: - dev_err_ratelimited(adev->dev, - "SMU: response:0x%08X for index:%d param:0x%08X message:%s?", - reg_c2pmsg_90, msg_index, param, message); - break; - } + return smu_cmn_send_smc_msg_with_param(smu, + msg, + 0, + read_arg); +} + +int smu_cmn_send_debug_smc_msg(struct smu_context *smu, + uint32_t msg) +{ + return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, 0); +} + +int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, + uint32_t msg, uint32_t param) +{ + return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, param); } -static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90) +static int smu_msg_v1_decode_response(u32 resp) { int res; - switch (reg_c2pmsg_90) { + switch (resp) { case SMU_RESP_NONE: /* The SMU is busy--still executing your command. */ @@ -238,281 +250,345 @@ static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90) return res; } -static void __smu_cmn_send_msg(struct smu_context *smu, - u16 msg, - u32 param) +static u32 __smu_msg_v1_poll_stat(struct smu_msg_ctl *ctl, u32 timeout_us) { - struct amdgpu_device *adev = smu->adev; + struct amdgpu_device *adev = ctl->smu->adev; + struct smu_msg_config *cfg = &ctl->config; + u32 timeout = timeout_us ? timeout_us : ctl->default_timeout; + u32 reg; + + for (; timeout > 0; timeout--) { + reg = RREG32(cfg->resp_reg); + if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0) + break; + udelay(1); + } - WREG32(smu->resp_reg, 0); - WREG32(smu->param_reg, param); - WREG32(smu->msg_reg, msg); + return reg; } -static inline uint32_t __smu_cmn_get_msg_flags(struct smu_context *smu, - enum smu_message_type msg) +static void __smu_msg_v1_send(struct smu_msg_ctl *ctl, u16 index, + struct smu_msg_args *args) { - return smu->message_map[msg].flags; + struct amdgpu_device *adev = ctl->smu->adev; + struct smu_msg_config *cfg = &ctl->config; + int i; + + WREG32(cfg->resp_reg, 0); + for (i = 0; i < args->num_args; i++) + WREG32(cfg->arg_regs[i], args->args[i]); + WREG32(cfg->msg_reg, index); } -static int __smu_cmn_ras_filter_msg(struct smu_context *smu, - enum smu_message_type msg, bool *poll) +static void __smu_msg_v1_read_out_args(struct smu_msg_ctl *ctl, + struct smu_msg_args *args) { - struct amdgpu_device *adev = smu->adev; - uint32_t flags, resp; - bool fed_status, pri; + struct amdgpu_device *adev = ctl->smu->adev; + int i; - flags = __smu_cmn_get_msg_flags(smu, msg); - *poll = true; + for (i = 0; i < args->num_out_args; i++) + args->out_args[i] = RREG32(ctl->config.arg_regs[i]); +} - pri = !!(flags & SMU_MSG_NO_PRECHECK); - /* When there is RAS fatal error, FW won't process non-RAS priority - * messages. Don't allow any messages other than RAS priority messages. - */ - fed_status = amdgpu_ras_get_fed_status(adev); - if (fed_status) { - if (!(flags & SMU_MSG_RAS_PRI)) { - dev_dbg(adev->dev, - "RAS error detected, skip sending %s", - smu_get_message_name(smu, msg)); - return -EACCES; - } - } +static void __smu_msg_v1_print_err_limited(struct smu_msg_ctl *ctl, + struct smu_msg_args *args, + char *err_msg) +{ + static DEFINE_RATELIMIT_STATE(_rs, + SMU_MSG_V1_DEFAULT_RATELIMIT_INTERVAL, + SMU_MSG_V1_DEFAULT_RATELIMIT_BURST); + struct smu_context *smu = ctl->smu; + struct amdgpu_device *adev = smu->adev; - if (pri || fed_status) { - /* FW will ignore non-priority messages when a RAS fatal error - * or reset condition is detected. Hence it is possible that a - * previous message wouldn't have got response. Allow to - * continue without polling for response status for priority - * messages. - */ - resp = RREG32(smu->resp_reg); - dev_dbg(adev->dev, - "Sending priority message %s response status: %x", - smu_get_message_name(smu, msg), resp); - if (resp == 0) - *poll = false; + if (__ratelimit(&_rs)) { + u32 in[SMU_MSG_MAX_ARGS]; + int i; + + dev_err(adev->dev, "%s msg_reg: %x resp_reg: %x", err_msg, + RREG32(ctl->config.msg_reg), + RREG32(ctl->config.resp_reg)); + if (args->num_args > 0) { + for (i = 0; i < args->num_args; i++) + in[i] = RREG32(ctl->config.arg_regs[i]); + print_hex_dump(KERN_ERR, "in params:", DUMP_PREFIX_NONE, + 16, 4, in, args->num_args * sizeof(u32), + false); + } } - - return 0; } -static int __smu_cmn_send_debug_msg(struct smu_context *smu, - u32 msg, - u32 param) +static void __smu_msg_v1_print_error(struct smu_msg_ctl *ctl, + u32 resp, + struct smu_msg_args *args) { + struct smu_context *smu = ctl->smu; struct amdgpu_device *adev = smu->adev; + int index = ctl->message_map[args->msg].map_to; - WREG32(smu->debug_param_reg, param); - WREG32(smu->debug_msg_reg, msg); - WREG32(smu->debug_resp_reg, 0); - - return 0; + switch (resp) { + case SMU_RESP_NONE: + __smu_msg_v1_print_err_limited(ctl, args, "SMU: No response"); + break; + case SMU_RESP_OK: + break; + case SMU_RESP_CMD_FAIL: + break; + case SMU_RESP_CMD_UNKNOWN: + __smu_msg_v1_print_err_limited(ctl, args, + "SMU: unknown command"); + break; + case SMU_RESP_CMD_BAD_PREREQ: + __smu_msg_v1_print_err_limited( + ctl, args, "SMU: valid command, bad prerequisites"); + break; + case SMU_RESP_BUSY_OTHER: + if (args->msg != SMU_MSG_GetBadPageCount) + __smu_msg_v1_print_err_limited(ctl, args, + "SMU: I'm very busy"); + break; + case SMU_RESP_DEBUG_END: + __smu_msg_v1_print_err_limited(ctl, args, "SMU: Debug Err"); + break; + case SMU_RESP_UNEXP: + if (amdgpu_device_bus_status_check(adev)) { + dev_err(adev->dev, + "SMU: bus error for message: %s(%d) response:0x%08X ", + smu_get_message_name(smu, args->msg), index, + resp); + if (args->num_args > 0) + print_hex_dump(KERN_ERR, + "in params:", DUMP_PREFIX_NONE, + 16, 4, args->args, + args->num_args * sizeof(u32), + false); + } + break; + default: + __smu_msg_v1_print_err_limited(ctl, args, + "SMU: unknown response"); + break; + } } -/** - * smu_cmn_send_msg_without_waiting -- send the message; don't wait for status - * @smu: pointer to an SMU context - * @msg_index: message index - * @param: message parameter to send to the SMU - * - * Send a message to the SMU with the parameter passed. Do not wait - * for status/result of the message, thus the "without_waiting". - * - * Return 0 on success, -errno on error if we weren't able to _send_ - * the message for some reason. See __smu_cmn_reg2errno() for details - * of the -errno. - */ -int smu_cmn_send_msg_without_waiting(struct smu_context *smu, - uint16_t msg_index, - uint32_t param) + +static int __smu_msg_v1_ras_filter(struct smu_msg_ctl *ctl, + enum smu_message_type msg, u32 msg_flags, + bool *skip_pre_poll) { + struct smu_context *smu = ctl->smu; struct amdgpu_device *adev = smu->adev; + bool fed_status; u32 reg; - int res; - if (adev->no_hw_access) + if (!(smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI)) return 0; - if (smu->smc_fw_state == SMU_FW_HANG) { - dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n"); - res = -EREMOTEIO; - goto Out; - } + fed_status = amdgpu_ras_get_fed_status(adev); - if (smu->smc_fw_state == SMU_FW_INIT) { - smu->smc_fw_state = SMU_FW_RUNTIME; - } else { - reg = __smu_cmn_poll_stat(smu); - res = __smu_cmn_reg2errno(smu, reg); - if (reg == SMU_RESP_NONE || res == -EREMOTEIO) - goto Out; + /* Block non-RAS-priority messages during RAS error */ + if (fed_status && !(msg_flags & SMU_MSG_RAS_PRI)) { + dev_dbg(adev->dev, "RAS error detected, skip sending %s", + smu_get_message_name(smu, msg)); + return -EACCES; } - __smu_cmn_send_msg(smu, msg_index, param); - res = 0; -Out: - if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && - res && (res != -ETIME)) { - amdgpu_device_halt(adev); - WARN_ON(1); + /* Skip pre-poll for priority messages or during RAS error */ + if ((msg_flags & SMU_MSG_NO_PRECHECK) || fed_status) { + reg = RREG32(ctl->config.resp_reg); + dev_dbg(adev->dev, + "Sending priority message %s response status: %x", + smu_get_message_name(smu, msg), reg); + if (reg == 0) + *skip_pre_poll = true; } - return res; + return 0; } /** - * smu_cmn_wait_for_response -- wait for response from the SMU - * @smu: pointer to an SMU context - * - * Wait for status from the SMU. + * smu_msg_v1_send_msg - Complete V1 protocol with all filtering + * @ctl: Message control block + * @args: Message arguments * - * Return 0 on success, -errno on error, indicating the execution - * status and result of the message being waited for. See - * __smu_cmn_reg2errno() for details of the -errno. + * Return: 0 on success, negative errno on failure */ -int smu_cmn_wait_for_response(struct smu_context *smu) +static int smu_msg_v1_send_msg(struct smu_msg_ctl *ctl, + struct smu_msg_args *args) { - u32 reg; - int res; + struct smu_context *smu = ctl->smu; + struct amdgpu_device *adev = smu->adev; + const struct cmn2asic_msg_mapping *mapping; + u32 reg, msg_flags; + int ret, index; + bool skip_pre_poll = false; + bool lock_held = args->flags & SMU_MSG_FLAG_LOCK_HELD; - reg = __smu_cmn_poll_stat(smu); - res = __smu_cmn_reg2errno(smu, reg); + /* Early exit if no HW access */ + if (adev->no_hw_access) + return 0; - if (res == -EREMOTEIO) - smu->smc_fw_state = SMU_FW_HANG; + /* Message index translation */ + if (args->msg >= SMU_MSG_MAX_COUNT || !ctl->message_map) + return -EINVAL; - if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && - res && (res != -ETIME)) { - amdgpu_device_halt(smu->adev); - WARN_ON(1); - } + if (args->num_args > ctl->config.num_arg_regs || + args->num_out_args > ctl->config.num_arg_regs) + return -EINVAL; - return res; -} + mapping = &ctl->message_map[args->msg]; + if (!mapping->valid_mapping) + return -EINVAL; -/** - * smu_cmn_send_smc_msg_with_param -- send a message with parameter - * @smu: pointer to an SMU context - * @msg: message to send - * @param: parameter to send to the SMU - * @read_arg: pointer to u32 to return a value from the SMU back - * to the caller - * - * Send the message @msg with parameter @param to the SMU, wait for - * completion of the command, and return back a value from the SMU in - * @read_arg pointer. - * - * Return 0 on success, -errno when a problem is encountered sending - * message or receiving reply. If there is a PCI bus recovery or - * the destination is a virtual GPU which does not allow this message - * type, the message is simply dropped and success is also returned. - * See __smu_cmn_reg2errno() for details of the -errno. - * - * If we weren't able to send the message to the SMU, we also print - * the error to the standard log. - * - * Command completion status is printed only if the -errno is - * -EREMOTEIO, indicating that the SMU returned back an - * undefined/unknown/unspecified result. All other cases are - * well-defined, not printed, but instead given back to the client to - * decide what further to do. - * - * The return value, @read_arg is read back regardless, to give back - * more information to the client, which on error would most likely be - * @param, but we can't assume that. This also eliminates more - * conditionals. - */ -int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, - enum smu_message_type msg, - uint32_t param, - uint32_t *read_arg) -{ - struct amdgpu_device *adev = smu->adev; - int res, index; - bool poll = true; - u32 reg; + msg_flags = mapping->flags; + index = mapping->map_to; - if (adev->no_hw_access) + /* VF filter - skip messages not valid for VF */ + if (amdgpu_sriov_vf(adev) && !(msg_flags & SMU_MSG_VF_FLAG)) return 0; - index = smu_cmn_to_asic_specific_index(smu, - CMN2ASIC_MAPPING_MSG, - msg); - if (index < 0) - return index == -EACCES ? 0 : index; - - mutex_lock(&smu->message_lock); + if (!lock_held) + mutex_lock(&ctl->lock); - if (smu->smc_fw_caps & SMU_FW_CAP_RAS_PRI) { - res = __smu_cmn_ras_filter_msg(smu, msg, &poll); - if (res) - goto Out; - } + /* RAS priority filter */ + ret = __smu_msg_v1_ras_filter(ctl, args->msg, msg_flags, + &skip_pre_poll); + if (ret) + goto out; + /* FW state checks */ if (smu->smc_fw_state == SMU_FW_HANG) { - dev_err(adev->dev, "SMU is in hanged state, failed to send smu message!\n"); - res = -EREMOTEIO; - goto Out; + dev_err(adev->dev, + "SMU is in hanged state, failed to send smu message!\n"); + ret = -EREMOTEIO; + goto out; } else if (smu->smc_fw_state == SMU_FW_INIT) { - /* Ignore initial smu response register value */ - poll = false; + skip_pre_poll = true; smu->smc_fw_state = SMU_FW_RUNTIME; } - if (poll) { - reg = __smu_cmn_poll_stat(smu); - res = __smu_cmn_reg2errno(smu, reg); - if (reg == SMU_RESP_NONE || res == -EREMOTEIO) { - __smu_cmn_reg_print_error(smu, reg, index, param, msg); - goto Out; + /* Pre-poll: ensure previous message completed */ + if (!skip_pre_poll) { + reg = __smu_msg_v1_poll_stat(ctl, args->timeout); + ret = smu_msg_v1_decode_response(reg); + if (reg == SMU_RESP_NONE || ret == -EREMOTEIO) { + __smu_msg_v1_print_error(ctl, reg, args); + goto out; } } - __smu_cmn_send_msg(smu, (uint16_t) index, param); - reg = __smu_cmn_poll_stat(smu); - res = __smu_cmn_reg2errno(smu, reg); - if (res != 0) { - if (res == -EREMOTEIO) - smu->smc_fw_state = SMU_FW_HANG; - __smu_cmn_reg_print_error(smu, reg, index, param, msg); + + /* Send message */ + __smu_msg_v1_send(ctl, (u16)index, args); + + /* Post-poll (skip if ASYNC) */ + if (args->flags & SMU_MSG_FLAG_ASYNC) { + ret = 0; + goto out; + } + + reg = __smu_msg_v1_poll_stat(ctl, args->timeout); + ret = smu_msg_v1_decode_response(reg); + + /* FW state update on fatal error */ + if (ret == -EREMOTEIO) { + smu->smc_fw_state = SMU_FW_HANG; + __smu_msg_v1_print_error(ctl, reg, args); + } else if (ret != 0) { + __smu_msg_v1_print_error(ctl, reg, args); } - if (read_arg) { - smu_cmn_read_arg(smu, read_arg); - dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x, readval: 0x%08x\n", - smu_get_message_name(smu, msg), index, param, reg, *read_arg); + + /* Read output args */ + if (ret == 0 && args->num_out_args > 0) { + __smu_msg_v1_read_out_args(ctl, args); + dev_dbg(adev->dev, "smu send message: %s(%d) resp : 0x%08x", + smu_get_message_name(smu, args->msg), index, reg); + if (args->num_args > 0) + print_hex_dump_debug("in params:", DUMP_PREFIX_NONE, 16, + 4, args->args, + args->num_args * sizeof(u32), + false); + print_hex_dump_debug("out params:", DUMP_PREFIX_NONE, 16, 4, + args->out_args, + args->num_out_args * sizeof(u32), false); } else { - dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, resp: 0x%08x\n", - smu_get_message_name(smu, msg), index, param, reg); + dev_dbg(adev->dev, "smu send message: %s(%d), resp: 0x%08x\n", + smu_get_message_name(smu, args->msg), index, reg); + if (args->num_args > 0) + print_hex_dump_debug("in params:", DUMP_PREFIX_NONE, 16, + 4, args->args, + args->num_args * sizeof(u32), + false); } -Out: - if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) { + +out: + /* Debug halt on error */ + if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && + ret) { amdgpu_device_halt(adev); WARN_ON(1); } - mutex_unlock(&smu->message_lock); - return res; + if (!lock_held) + mutex_unlock(&ctl->lock); + return ret; } -int smu_cmn_send_smc_msg(struct smu_context *smu, - enum smu_message_type msg, - uint32_t *read_arg) +static int smu_msg_v1_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us) { - return smu_cmn_send_smc_msg_with_param(smu, - msg, - 0, - read_arg); + struct smu_context *smu = ctl->smu; + struct amdgpu_device *adev = smu->adev; + u32 reg; + int ret; + + reg = __smu_msg_v1_poll_stat(ctl, timeout_us); + ret = smu_msg_v1_decode_response(reg); + + if (ret == -EREMOTEIO) + smu->smc_fw_state = SMU_FW_HANG; + + if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && + ret && (ret != -ETIME)) { + amdgpu_device_halt(adev); + WARN_ON(1); + } + + return ret; } -int smu_cmn_send_debug_smc_msg(struct smu_context *smu, - uint32_t msg) +const struct smu_msg_ops smu_msg_v1_ops = { + .send_msg = smu_msg_v1_send_msg, + .wait_response = smu_msg_v1_wait_response, + .decode_response = smu_msg_v1_decode_response, + .send_debug_msg = smu_msg_v1_send_debug_msg, +}; + +int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us) { - return __smu_cmn_send_debug_msg(smu, msg, 0); + return ctl->ops->wait_response(ctl, timeout_us); } -int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, - uint32_t msg, uint32_t param) +/** + * smu_msg_send_async_locked - Send message asynchronously, caller holds lock + * @ctl: Message control block + * @msg: Message type + * @param: Message parameter + * + * Send an SMU message without waiting for response. Caller must hold ctl->lock + * and call smu_msg_wait_response() later to get the result. + * + * Return: 0 on success, negative errno on failure + */ +int smu_msg_send_async_locked(struct smu_msg_ctl *ctl, + enum smu_message_type msg, u32 param) { - return __smu_cmn_send_debug_msg(smu, msg, param); + struct smu_msg_args args = { + .msg = msg, + .args[0] = param, + .num_args = 1, + .num_out_args = 0, + .flags = SMU_MSG_FLAG_ASYNC | SMU_MSG_FLAG_LOCK_HELD, + .timeout = 0, + }; + + return ctl->ops->send_msg(ctl, &args); } int smu_cmn_to_asic_specific_index(struct smu_context *smu, @@ -525,10 +601,10 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu, switch (type) { case CMN2ASIC_MAPPING_MSG: if (index >= SMU_MSG_MAX_COUNT || - !smu->message_map) + !smu->msg_ctl.message_map) return -EINVAL; - msg_mapping = smu->message_map[index]; + msg_mapping = smu->msg_ctl.message_map[index]; if (!msg_mapping.valid_mapping) return -EINVAL; @@ -601,7 +677,6 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu, int smu_cmn_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask) { - struct smu_feature *feature = &smu->smu_feature; int feature_id; feature_id = smu_cmn_to_asic_specific_index(smu, @@ -610,13 +685,12 @@ int smu_cmn_feature_is_supported(struct smu_context *smu, if (feature_id < 0) return 0; - WARN_ON(feature_id > feature->feature_num); - - return test_bit(feature_id, feature->supported); + return smu_feature_list_is_set(smu, SMU_FEATURE_LIST_SUPPORTED, + feature_id); } static int __smu_get_enabled_features(struct smu_context *smu, - uint64_t *enabled_features) + struct smu_feature_bits *enabled_features) { return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features); } @@ -625,7 +699,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu, enum smu_feature_mask mask) { struct amdgpu_device *adev = smu->adev; - uint64_t enabled_features; + struct smu_feature_bits enabled_features; int feature_id; if (__smu_get_enabled_features(smu, &enabled_features)) { @@ -638,7 +712,8 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu, * enabled. Also considering they have no feature_map available, the * check here can avoid unwanted feature_map check below. */ - if (enabled_features == ULLONG_MAX) + if (smu_feature_bits_full(&enabled_features, + smu->smu_feature.feature_num)) return 1; feature_id = smu_cmn_to_asic_specific_index(smu, @@ -647,7 +722,7 @@ int smu_cmn_feature_is_enabled(struct smu_context *smu, if (feature_id < 0) return 0; - return test_bit(feature_id, (unsigned long *)&enabled_features); + return smu_feature_bits_is_set(&enabled_features, feature_id); } bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, @@ -689,45 +764,39 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, } int smu_cmn_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask) + struct smu_feature_bits *feature_mask) { - uint32_t *feature_mask_high; - uint32_t *feature_mask_low; + uint32_t features[2]; int ret = 0, index = 0; if (!feature_mask) return -EINVAL; - feature_mask_low = &((uint32_t *)feature_mask)[0]; - feature_mask_high = &((uint32_t *)feature_mask)[1]; - index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetEnabledSmuFeatures); if (index > 0) { - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_GetEnabledSmuFeatures, - 0, - feature_mask_low); + ret = smu_cmn_send_smc_msg_with_param( + smu, SMU_MSG_GetEnabledSmuFeatures, 0, &features[0]); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_GetEnabledSmuFeatures, - 1, - feature_mask_high); + ret = smu_cmn_send_smc_msg_with_param( + smu, SMU_MSG_GetEnabledSmuFeatures, 1, &features[1]); } else { - ret = smu_cmn_send_smc_msg(smu, - SMU_MSG_GetEnabledSmuFeaturesHigh, - feature_mask_high); + ret = smu_cmn_send_smc_msg( + smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &features[1]); if (ret) return ret; - ret = smu_cmn_send_smc_msg(smu, - SMU_MSG_GetEnabledSmuFeaturesLow, - feature_mask_low); + ret = smu_cmn_send_smc_msg( + smu, SMU_MSG_GetEnabledSmuFeaturesLow, &features[0]); } + if (!ret) + smu_feature_bits_from_arr32(feature_mask, features, + SMU_FEATURE_NUM_DEFAULT); + return ret; } @@ -811,8 +880,13 @@ static const char *smu_get_feature_name(struct smu_context *smu, size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, char *buf) { - int8_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; - uint64_t feature_mask; +#ifdef MAX + int16_t sort_feature[MAX(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; +#else + int16_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)]; +#endif + struct smu_feature_bits feature_mask; + uint32_t features[2]; int i, feature_index; uint32_t count = 0; size_t size = 0; @@ -820,8 +894,10 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, if (__smu_get_enabled_features(smu, &feature_mask)) return 0; - size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", - upper_32_bits(feature_mask), lower_32_bits(feature_mask)); + /* TBD: Need to handle for > 64 bits */ + smu_feature_bits_to_arr32(&feature_mask, features, 64); + size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n", + features[1], features[0]); memset(sort_feature, -1, sizeof(sort_feature)); @@ -838,16 +914,18 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n", "No", "Feature", "Bit", "State"); - for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) { + for (feature_index = 0; feature_index < smu->smu_feature.feature_num; + feature_index++) { if (sort_feature[feature_index] < 0) continue; - size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n", - count++, - smu_get_feature_name(smu, sort_feature[feature_index]), - feature_index, - !!test_bit(feature_index, (unsigned long *)&feature_mask) ? - "enabled" : "disabled"); + size += sysfs_emit_at( + buf, size, "%02d. %-20s (%2d) : %s\n", count++, + smu_get_feature_name(smu, sort_feature[feature_index]), + feature_index, + smu_feature_bits_is_set(&feature_mask, feature_index) ? + "enabled" : + "disabled"); } return size; @@ -857,7 +935,8 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask) { int ret = 0; - uint64_t feature_mask; + struct smu_feature_bits feature_mask; + uint64_t feature_mask_u64; uint64_t feature_2_enabled = 0; uint64_t feature_2_disabled = 0; @@ -865,8 +944,9 @@ int smu_cmn_set_pp_feature_mask(struct smu_context *smu, if (ret) return ret; - feature_2_enabled = ~feature_mask & new_mask; - feature_2_disabled = feature_mask & ~new_mask; + feature_mask_u64 = *(uint64_t *)feature_mask.bits; + feature_2_enabled = ~feature_mask_u64 & new_mask; + feature_2_disabled = feature_mask_u64 & ~new_mask; if (feature_2_enabled) { ret = smu_cmn_feature_update_enable_state(smu, @@ -959,6 +1039,31 @@ int smu_cmn_get_smc_version(struct smu_context *smu, return ret; } +int smu_cmn_check_fw_version(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t if_version = 0xff, smu_version = 0xff; + uint8_t smu_program, smu_major, smu_minor, smu_debug; + int ret; + + ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); + if (ret) + return ret; + + smu_program = (smu_version >> 24) & 0xff; + smu_major = (smu_version >> 16) & 0xff; + smu_minor = (smu_version >> 8) & 0xff; + smu_debug = (smu_version >> 0) & 0xff; + adev->pm.fw_version = smu_version; + + dev_info_once(adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, " + "smu fw program = %d, smu fw version = 0x%08x (%d.%d.%d)\n", + smu->smc_driver_if_version, if_version, + smu_program, smu_version, smu_major, smu_minor, smu_debug); + + return 0; +} + int smu_cmn_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument, @@ -1199,3 +1304,182 @@ void smu_cmn_get_backend_workload_mask(struct smu_context *smu, *backend_workload_mask |= 1 << workload_type; } } + +void smu_cmn_reset_custom_level(struct smu_context *smu) +{ + struct smu_umd_pstate_table *pstate_table = &smu->pstate_table; + + pstate_table->gfxclk_pstate.custom.min = 0; + pstate_table->gfxclk_pstate.custom.max = 0; + pstate_table->uclk_pstate.custom.min = 0; + pstate_table->uclk_pstate.custom.max = 0; +} + +static inline bool smu_cmn_freqs_match(uint32_t freq1, uint32_t freq2) +{ + /* Frequencies within 25 MHz are considered equal */ + return (abs((int)freq1 - (int)freq2) <= 25); +} + +int smu_cmn_print_dpm_clk_levels(struct smu_context *smu, + struct smu_dpm_table *dpm_table, + uint32_t cur_clk, char *buf, int *offset) +{ + uint32_t min_clk, max_clk, level_index, count; + uint32_t freq_values[3]; + int size, lvl, i; + bool is_fine_grained; + bool is_deep_sleep; + bool freq_match; + + if (!dpm_table || !buf) + return -EINVAL; + + level_index = 0; + size = *offset; + count = dpm_table->count; + is_fine_grained = dpm_table->flags & SMU_DPM_TABLE_FINE_GRAINED; + min_clk = SMU_DPM_TABLE_MIN(dpm_table); + max_clk = SMU_DPM_TABLE_MAX(dpm_table); + + /* Deep sleep - current clock < min_clock/2, TBD: cur_clk = 0 as GFXOFF */ + is_deep_sleep = cur_clk < min_clk / 2; + if (is_deep_sleep) { + size += sysfs_emit_at(buf, size, "S: %uMhz *\n", cur_clk); + level_index = 1; + } + + if (!is_fine_grained || count == 1) { + for (i = 0; i < count; i++) { + freq_match = !is_deep_sleep && + smu_cmn_freqs_match( + cur_clk, + dpm_table->dpm_levels[i].value); + size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", + level_index + i, + dpm_table->dpm_levels[i].value, + freq_match ? "*" : ""); + } + } else { + count = 2; + freq_values[0] = min_clk; + freq_values[1] = max_clk; + + if (!is_deep_sleep) { + if (smu_cmn_freqs_match(cur_clk, min_clk)) { + lvl = 0; + } else if (smu_cmn_freqs_match(cur_clk, max_clk)) { + lvl = 1; + } else { + /* NOTE: use index '1' to show current clock value */ + lvl = 1; + count = 3; + freq_values[1] = cur_clk; + freq_values[2] = max_clk; + } + } + + for (i = 0; i < count; i++) { + size += sysfs_emit_at( + buf, size, "%d: %uMhz %s\n", level_index + i, + freq_values[i], + (!is_deep_sleep && i == lvl) ? "*" : ""); + } + } + + *offset = size; + + return 0; +} + +int smu_cmn_print_pcie_levels(struct smu_context *smu, + struct smu_pcie_table *pcie_table, + uint32_t cur_gen, uint32_t cur_lane, char *buf, + int *offset) +{ + int size, i; + + if (!pcie_table || !buf) + return -EINVAL; + + size = *offset; + + for (i = 0; i < pcie_table->lclk_levels; i++) { + size += sysfs_emit_at( + buf, size, "%d: %s %s %dMhz %s\n", i, + (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : + (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : + (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : + (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : + (pcie_table->pcie_gen[i] == 4) ? "32.0GT/s," : + (pcie_table->pcie_gen[i] == 5) ? "64.0GT/s," : + "", + (pcie_table->pcie_lane[i] == 1) ? "x1" : + (pcie_table->pcie_lane[i] == 2) ? "x2" : + (pcie_table->pcie_lane[i] == 3) ? "x4" : + (pcie_table->pcie_lane[i] == 4) ? "x8" : + (pcie_table->pcie_lane[i] == 5) ? "x12" : + (pcie_table->pcie_lane[i] == 6) ? "x16" : + (pcie_table->pcie_lane[i] == 7) ? "x32" : + "", + pcie_table->lclk_freq[i], + (cur_gen == pcie_table->pcie_gen[i]) && + (cur_lane == pcie_table->pcie_lane[i]) ? + "*" : + ""); + } + + *offset = size; + + return 0; +} + +int smu_cmn_dpm_pcie_gen_idx(int gen) +{ + int ret; + + switch (gen) { + case 1 ... 5: + ret = gen - 1; + break; + default: + ret = -1; + break; + } + + return ret; +} + +int smu_cmn_dpm_pcie_width_idx(int width) +{ + int ret; + + switch (width) { + case 1: + ret = 1; + break; + case 2: + ret = 2; + break; + case 4: + ret = 3; + break; + case 8: + ret = 4; + break; + case 12: + ret = 5; + break; + case 16: + ret = 6; + break; + case 32: + ret = 7; + break; + default: + ret = -1; + break; + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h index 8d7c4814c68f0..b76e86df5da78 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h @@ -25,6 +25,12 @@ #include "amdgpu_smu.h" +extern const struct smu_msg_ops smu_msg_v1_ops; + +int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us); +int smu_msg_send_async_locked(struct smu_msg_ctl *ctl, + enum smu_message_type msg, u32 param); + #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4) #define FDO_PWM_MODE_STATIC 1 @@ -93,6 +99,9 @@ header->structure_size = sizeof(*tmp); \ } while (0) +#define SMU_DPM_PCIE_GEN_IDX(gen) smu_cmn_dpm_pcie_gen_idx((gen)) +#define SMU_DPM_PCIE_WIDTH_IDX(width) smu_cmn_dpm_pcie_width_idx((width)) + extern const int link_speed[]; /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */ @@ -101,9 +110,6 @@ static inline int pcie_gen_to_speed(uint32_t gen) return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]); } -int smu_cmn_send_msg_without_waiting(struct smu_context *smu, - uint16_t msg_index, - uint32_t param); int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, enum smu_message_type msg, uint32_t param, @@ -135,7 +141,7 @@ bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type); int smu_cmn_get_enabled_mask(struct smu_context *smu, - uint64_t *feature_mask); + struct smu_feature_bits *feature_mask); uint64_t smu_cmn_get_indep_throttler_status( const unsigned long dep_status, @@ -181,19 +187,6 @@ int smu_cmn_get_combo_pptable(struct smu_context *smu); int smu_cmn_set_mp1_state(struct smu_context *smu, enum pp_mp1_state mp1_state); -/* - * Helper function to make sysfs_emit_at() happy. Align buf to - * the current page boundary and record the offset. - */ -static inline void smu_cmn_get_sysfs_buf(char **buf, int *offset) -{ - if (!*buf || !offset) - return; - - *offset = offset_in_page(*buf); - *buf -= *offset; -} - bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev); void smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy *policy); void smu_cmn_generic_plpd_policy_desc(struct smu_dpm_policy *policy); @@ -202,6 +195,21 @@ void smu_cmn_get_backend_workload_mask(struct smu_context *smu, u32 workload_mask, u32 *backend_workload_mask); +int smu_cmn_print_dpm_clk_levels(struct smu_context *smu, + struct smu_dpm_table *dpm_table, + uint32_t cur_clk, + char *buf, int *offset); + +int smu_cmn_print_pcie_levels(struct smu_context *smu, + struct smu_pcie_table *pcie_table, + uint32_t cur_gen, uint32_t cur_lane, + char *buf, int *offset); +void smu_cmn_reset_custom_level(struct smu_context *smu); + +int smu_cmn_dpm_pcie_gen_idx(int gen); +int smu_cmn_dpm_pcie_width_idx(int width); +int smu_cmn_check_fw_version(struct smu_context *smu); + /*SMU gpu metrics */ /* Attribute ID mapping */ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h index 34f6b4b1c3ba0..24848da902343 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_internal.h @@ -54,8 +54,6 @@ #define smu_system_features_control(smu, en) smu_ppt_funcs(system_features_control, 0, smu, en) #define smu_init_max_sustainable_clocks(smu) smu_ppt_funcs(init_max_sustainable_clocks, 0, smu) #define smu_set_default_od_settings(smu) smu_ppt_funcs(set_default_od_settings, 0, smu) -#define smu_send_smc_msg_with_param(smu, msg, param, read_arg) smu_ppt_funcs(send_smc_msg_with_param, 0, smu, msg, param, read_arg) -#define smu_send_smc_msg(smu, msg, read_arg) smu_ppt_funcs(send_smc_msg, 0, smu, msg, read_arg) #define smu_init_display_count(smu, count) smu_ppt_funcs(init_display_count, 0, smu, count) #define smu_feature_set_allowed_mask(smu) smu_ppt_funcs(set_allowed_mask, 0, smu) #define smu_feature_get_enabled_mask(smu, mask) smu_ppt_funcs(get_enabled_mask, -EOPNOTSUPP, smu, mask) @@ -72,7 +70,7 @@ #define smu_apply_clocks_adjust_rules(smu) smu_ppt_funcs(apply_clocks_adjust_rules, 0, smu) #define smu_notify_smc_display_config(smu) smu_ppt_funcs(notify_smc_display_config, 0, smu) #define smu_run_btc(smu) smu_ppt_funcs(run_btc, 0, smu) -#define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num) +#define smu_init_allowed_features(smu) smu_ppt_funcs(init_allowed_features, 0, smu) #define smu_set_watermarks_table(smu, clock_ranges) smu_ppt_funcs(set_watermarks_table, 0, smu, clock_ranges) #define smu_thermal_temperature_range_update(smu, range, rw) smu_ppt_funcs(thermal_temperature_range_update, 0, smu, range, rw) #define smu_register_irq_handler(smu) smu_ppt_funcs(register_irq_handler, 0, smu) diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile index 5e5a2cfa40688..6759635aadc26 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/Makefile +++ b/drivers/gpu/drm/amd/ras/ras_mgr/Makefile @@ -23,6 +23,7 @@ RAS_MGR_FILES = amdgpu_ras_sys.o \ amdgpu_ras_eeprom_i2c.o \ amdgpu_ras_mp1_v13_0.o \ amdgpu_ras_cmd.o \ + amdgpu_virt_ras_cmd.o \ amdgpu_ras_process.o \ amdgpu_ras_nbio_v7_9.o diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c index 78419b7f7729a..cb6498c308345 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c @@ -28,6 +28,7 @@ #include "ras_sys.h" #include "amdgpu_ras_cmd.h" #include "amdgpu_ras_mgr.h" +#include "amdgpu_virt_ras_cmd.h" /* inject address is 52 bits */ #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) @@ -252,6 +253,7 @@ int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd) { + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; struct ras_core_context *cmd_core = ras_core; int timeout = 60; int res; @@ -259,6 +261,9 @@ int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx cmd->cmd_res = RAS_CMD__ERROR_INVALID_CMD; cmd->output_size = 0; + if (amdgpu_sriov_vf(adev)) + return amdgpu_virt_ras_handle_cmd(cmd_core, cmd); + if (!ras_core_is_enabled(cmd_core)) return RAS_CMD__ERROR_ACCESS_DENIED; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c index afe8135b62586..861b1f2904754 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c @@ -27,6 +27,7 @@ #include "ras_sys.h" #include "amdgpu_ras_mgr.h" #include "amdgpu_ras_cmd.h" +#include "amdgpu_virt_ras_cmd.h" #include "amdgpu_ras_process.h" #include "amdgpu_ras_eeprom_i2c.h" #include "amdgpu_ras_mp1_v13_0.h" @@ -215,6 +216,7 @@ static int amdgpu_ras_mgr_get_ras_ta_init_param(struct ras_core_context *ras_cor ras_ta_param->channel_dis_num = hweight32(adev->gmc.m_half_use) * 2; ras_ta_param->active_umc_mask = adev->umc.active_mask; + ras_ta_param->vram_type = (uint8_t)adev->gmc.vram_type; if (!amdgpu_ras_mgr_get_curr_nps_mode(adev, &nps_mode)) ras_ta_param->nps_mode = nps_mode; @@ -316,6 +318,16 @@ static int amdgpu_ras_mgr_sw_init(struct amdgpu_ip_block *ip_block) amdgpu_ras_process_init(adev); ras_core_sw_init(ras_mgr->ras_core); amdgpu_ras_mgr_init_event_mgr(ras_mgr->ras_core); + + if (amdgpu_sriov_vf(adev)) { + ret = amdgpu_virt_ras_sw_init(adev); + if (ret) { + RAS_DEV_ERR(adev, + "Virt ras sw_init failed! ret:%d\n", ret); + goto err; + } + } + return 0; err: @@ -335,6 +347,9 @@ static int amdgpu_ras_mgr_sw_fini(struct amdgpu_ip_block *ip_block) if (!ras_mgr) return 0; + if (amdgpu_sriov_vf(adev)) + amdgpu_virt_ras_sw_fini(adev); + amdgpu_ras_process_fini(adev); ras_core_sw_fini(ras_mgr->ras_core); ras_core_destroy(ras_mgr->ras_core); @@ -359,9 +374,13 @@ static int amdgpu_ras_mgr_hw_init(struct amdgpu_ip_block *ip_block) if (!ras_mgr || !ras_mgr->ras_core) return -EINVAL; - ret = ras_core_hw_init(ras_mgr->ras_core); + if (amdgpu_sriov_vf(adev)) + ret = amdgpu_virt_ras_hw_init(adev); + else + ret = ras_core_hw_init(ras_mgr->ras_core); + if (ret) { - RAS_DEV_ERR(adev, "Failed to initialize ras core!\n"); + RAS_DEV_ERR(adev, "Failed to initialize hw_init!, ret:%d\n", ret); return ret; } @@ -385,7 +404,10 @@ static int amdgpu_ras_mgr_hw_fini(struct amdgpu_ip_block *ip_block) if (!ras_mgr || !ras_mgr->ras_core) return -EINVAL; - ras_core_hw_fini(ras_mgr->ras_core); + if (amdgpu_sriov_vf(adev)) + amdgpu_virt_ras_hw_fini(adev); + else + ras_core_hw_fini(ras_mgr->ras_core); ras_mgr->ras_is_ready = false; @@ -423,9 +445,6 @@ int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable) if (!ras_mgr || !ras_mgr->ras_core) return -EPERM; - if (amdgpu_sriov_vf(adev)) - return -EPERM; - RAS_DEV_INFO(adev, "Enable amdgpu unified ras!"); return ras_core_set_status(ras_mgr->ras_core, enable); } @@ -434,10 +453,10 @@ bool amdgpu_uniras_enabled(struct amdgpu_device *adev) { struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); - if (!ras_mgr || !ras_mgr->ras_core) - return false; - if (amdgpu_sriov_vf(adev)) + return amdgpu_virt_ras_remote_uniras_enabled(adev); + + if (!ras_mgr || !ras_mgr->ras_core) return false; return ras_core_is_enabled(ras_mgr->ras_core); @@ -516,6 +535,37 @@ int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void return ret; } +int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + uint64_t seq_no = 0; + int ret = 0; + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + if (!ih_info) + return 0; + + if (ih_info->block == RAS_BLOCK_ID__UMC) { + if (ras_mgr->ras_core->poison_supported) { + seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_DE); + RAS_DEV_INFO(adev, + "{%llu} RAS poison is created, no user action is needed.\n", + seq_no); + } + + ret = amdgpu_ras_process_handle_umc_interrupt(adev, ih_info); + } else if (ras_mgr->ras_core->poison_supported) { + ret = amdgpu_ras_process_handle_consumption_interrupt(adev, ih_info); + } else { + RAS_DEV_WARN(adev, + "No RAS interrupt handler for non-UMC block with poison disabled.\n"); + } + + return ret; +} + int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data) { if (!amdgpu_ras_mgr_is_ready(adev)) @@ -552,6 +602,9 @@ bool amdgpu_ras_mgr_check_eeprom_safety_watermark(struct amdgpu_device *adev) if (!amdgpu_ras_mgr_is_ready(adev)) return false; + if (ras_fw_eeprom_supported(ras_mgr->ras_core)) + return ras_fw_eeprom_check_safety_watermark(ras_mgr->ras_core); + return ras_eeprom_check_safety_watermark(ras_mgr->ras_core); } @@ -603,7 +656,7 @@ int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, uint32_t ctx_buf_size = PAGE_SIZE; int ret; - if (!amdgpu_ras_mgr_is_ready(adev)) + if (!amdgpu_sriov_vf(adev) && !amdgpu_ras_mgr_is_ready(adev)) return -EPERM; cmd_ctx = kzalloc(ctx_buf_size, GFP_KERNEL); @@ -627,6 +680,9 @@ int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev) { + if (amdgpu_sriov_vf(adev)) + return amdgpu_virt_ras_pre_reset(adev); + if (!amdgpu_ras_mgr_is_ready(adev)) { RAS_DEV_ERR(adev, "Invalid ras suspend!\n"); return -EPERM; @@ -638,6 +694,9 @@ int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev) int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev) { + if (amdgpu_sriov_vf(adev)) + return amdgpu_virt_ras_post_reset(adev); + if (!amdgpu_ras_mgr_is_ready(adev)) { RAS_DEV_ERR(adev, "Invalid ras resume!\n"); return -EPERM; @@ -646,3 +705,18 @@ int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev) amdgpu_ras_process_post_reset(adev); return 0; } + +int amdgpu_ras_mgr_lookup_bad_pages_in_a_row(struct amdgpu_device *adev, + uint64_t addr, uint64_t *nps_page_addr, uint32_t max_page_count) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + + if (!amdgpu_ras_mgr_is_ready(adev)) + return -EPERM; + + if (!nps_page_addr || !max_page_count) + return -EINVAL; + + return ras_core_convert_soc_pa_to_cur_nps_pages(ras_mgr->ras_core, + addr, nps_page_addr, max_page_count); +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h index 8fb7eb4b8f132..4f44a917d48be 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h @@ -50,6 +50,7 @@ struct amdgpu_ras_mgr { struct ras_core_context *ras_core; struct delayed_work retire_page_dwork; struct ras_event_manager ras_event_mgr; + void *virt_ras_cmd; uint64_t last_poison_consumption_seqno; bool ras_is_ready; @@ -66,6 +67,7 @@ bool amdgpu_uniras_enabled(struct amdgpu_device *adev); int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data); int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data); +int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info); int amdgpu_ras_mgr_update_ras_ecc(struct amdgpu_device *adev); int amdgpu_ras_mgr_reset_gpu(struct amdgpu_device *adev, uint32_t flags); uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev, @@ -80,4 +82,6 @@ int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev, void *output, uint32_t out_size); int amdgpu_ras_mgr_pre_reset(struct amdgpu_device *adev); int amdgpu_ras_mgr_post_reset(struct amdgpu_device *adev); +int amdgpu_ras_mgr_lookup_bad_pages_in_a_row(struct amdgpu_device *adev, + uint64_t addr, uint64_t *nps_page_addr, uint32_t max_page_count); #endif diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c index 79a51b1603ac1..2098f24d4940c 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mp1_v13_0.c @@ -28,6 +28,16 @@ #define RAS_MP1_MSG_QueryValidMcaCeCount 0x3A #define RAS_MP1_MSG_McaBankCeDumpDW 0x3B +static const enum smu_message_type pmfw_eeprom_msgs[] = { + [RAS_SMU_GetRASTableVersion] = SMU_MSG_GetRASTableVersion, + [RAS_SMU_GetBadPageCount] = SMU_MSG_GetBadPageCount, + [RAS_SMU_SetTimestamp] = SMU_MSG_SetTimestamp, + [RAS_SMU_GetTimestamp] = SMU_MSG_GetTimestamp, + [RAS_SMU_GetBadPageIpid] = SMU_MSG_GetBadPageIpid, + [RAS_SMU_EraseRasTable] = SMU_MSG_EraseRasTable, + [RAS_SMU_GetBadPageMcaAddr] = SMU_MSG_GetBadPageMcaAddr, +}; + static int mp1_v13_0_get_valid_bank_count(struct ras_core_context *ras_core, u32 msg, u32 *count) { @@ -87,8 +97,44 @@ static int mp1_v13_0_dump_valid_bank(struct ras_core_context *ras_core, return ret; } +static int mp1_v13_0_eeprom_send_msg(struct ras_core_context *ras_core, + enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret = 0; + + if (down_read_trylock(&adev->reset_domain->sem)) { + ret = amdgpu_smu_ras_send_msg(adev, + pmfw_eeprom_msgs[index], param, read_arg); + up_read(&adev->reset_domain->sem); + } else { + ret = -RAS_CORE_GPU_IN_MODE1_RESET; + } + + return ret; +} + +static int mp1_v13_0_get_ras_enabled_mask(struct ras_core_context *ras_core, + uint64_t *enabled_mask) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev; + int ret = 0; + + if (down_read_trylock(&adev->reset_domain->sem)) { + if (amdgpu_smu_ras_feature_is_enabled(adev, SMU_FEATURE_HROM_EN_BIT)) + *enabled_mask |= RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM; + up_read(&adev->reset_domain->sem); + } else { + ret = -RAS_CORE_GPU_IN_MODE1_RESET; + } + + return ret; +} + const struct ras_mp1_sys_func amdgpu_ras_mp1_sys_func_v13_0 = { .mp1_get_valid_bank_count = mp1_v13_0_get_valid_bank_count, .mp1_dump_valid_bank = mp1_v13_0_dump_valid_bank, + .mp1_send_eeprom_msg = mp1_v13_0_eeprom_send_msg, + .mp1_get_ras_enabled_mask = mp1_v13_0_get_ras_enabled_mask, }; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c index 5782c007de71c..285d81a85a99d 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_process.c @@ -103,6 +103,16 @@ int amdgpu_ras_process_handle_consumption_interrupt(struct amdgpu_device *adev, if (!ih_info) return -EINVAL; + if (amdgpu_sriov_vf(adev)) { + if (adev->virt.ops && adev->virt.ops->ras_poison_handler) + adev->virt.ops->ras_poison_handler(adev, ih_info->block); + else + dev_warn(adev->dev, + "No ras_poison_handler interface in SRIOV for block[%d]!\n", + ih_info->block); + return 0; + } + memset(&req, 0, sizeof(req)); req.block = ih_info->block; req.data = ih_info->data; diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c index 45ed8c3b5563b..7d728e5236042 100644 --- a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_sys.c @@ -137,7 +137,8 @@ static int amdgpu_ras_sys_event_notifier(struct ras_core_context *ras_core, break; case RAS_EVENT_ID__DEVICE_RMA: ras_log_ring_add_log_event(ras_core, RAS_LOG_EVENT_RMA, NULL, NULL); - ret = amdgpu_dpm_send_rma_reason(ras_core->dev); + if (!ras_fw_eeprom_supported(ras_core)) + ret = amdgpu_dpm_send_rma_reason(ras_core->dev); break; case RAS_EVENT_ID__RESET_GPU: ret = amdgpu_ras_mgr_reset_gpu(ras_core->dev, *(uint32_t *)data); diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c new file mode 100644 index 0000000000000..81553230dca44 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include "amdgpu.h" +#include "amdgpu_ras.h" +#include "ras_sys.h" +#include "amdgpu_ras_cmd.h" +#include "amdgpu_virt_ras_cmd.h" +#include "amdgpu_ras_mgr.h" + +static int amdgpu_virt_ras_get_cmd_shared_mem(struct ras_core_context *ras_core, + uint32_t cmd, uint32_t mem_size, struct amdgpu_virt_shared_mem *shared_mem) +{ + struct amdgpu_device *adev = ras_core->dev; + struct amdsriov_ras_telemetry *ras_telemetry_cpu; + struct amdsriov_ras_telemetry *ras_telemetry_gpu; + uint64_t fw_vram_usage_start_offset = 0; + uint64_t ras_telemetry_offset = 0; + + if (!adev->virt.fw_reserve.ras_telemetry) + return -EINVAL; + + if (adev->mman.fw_vram_usage_va && + adev->mman.fw_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { + fw_vram_usage_start_offset = adev->mman.fw_vram_usage_start_offset; + ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - + (uintptr_t)adev->mman.fw_vram_usage_va; + } else if (adev->mman.drv_vram_usage_va && + adev->mman.drv_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { + fw_vram_usage_start_offset = adev->mman.drv_vram_usage_start_offset; + ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - + (uintptr_t)adev->mman.drv_vram_usage_va; + } else { + return -EINVAL; + } + + ras_telemetry_cpu = + (struct amdsriov_ras_telemetry *)adev->virt.fw_reserve.ras_telemetry; + ras_telemetry_gpu = + (struct amdsriov_ras_telemetry *)(uintptr_t)(fw_vram_usage_start_offset + + ras_telemetry_offset); + + if (cmd == RAS_CMD__GET_ALL_BLOCK_ECC_STATUS) { + if (mem_size > AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE) + return -ENOMEM; + + shared_mem->cpu_addr = ras_telemetry_cpu->uniras_shared_mem.blocks_ecc_buf; + shared_mem->gpa = + (uintptr_t)ras_telemetry_gpu->uniras_shared_mem.blocks_ecc_buf - + adev->gmc.vram_start; + shared_mem->size = mem_size; + } else { + if (mem_size > AMD_SRIOV_UNIRAS_CMD_MAX_SIZE) + return -ENOMEM; + + shared_mem->cpu_addr = ras_telemetry_cpu->uniras_shared_mem.cmd_buf; + shared_mem->gpa = + (uintptr_t)ras_telemetry_gpu->uniras_shared_mem.cmd_buf - + adev->gmc.vram_start; + shared_mem->size = mem_size; + } + + return 0; +} + +static int amdgpu_virt_ras_remote_ioctl_cmd(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd, void *output_data, uint32_t output_size) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(ras_core->dev); + struct amdgpu_virt_ras_cmd *virt_ras = ras_mgr->virt_ras_cmd; + uint32_t mem_len = ALIGN(sizeof(*cmd) + output_size, AMDGPU_GPU_PAGE_SIZE); + struct ras_cmd_ctx *rcmd; + struct amdgpu_virt_shared_mem shared_mem = {0}; + int ret = 0; + + mutex_lock(&virt_ras->remote_access_lock); + + ret = amdgpu_virt_ras_get_cmd_shared_mem(ras_core, cmd->cmd_id, mem_len, &shared_mem); + if (ret) + goto out; + + rcmd = (struct ras_cmd_ctx *)shared_mem.cpu_addr; + memset(rcmd, 0, mem_len); + memcpy(rcmd, cmd, sizeof(*cmd)); + + ret = amdgpu_virt_send_remote_ras_cmd(ras_core->dev, + shared_mem.gpa, mem_len); + if (!ret) { + if (rcmd->cmd_res) { + ret = rcmd->cmd_res; + goto out; + } + + cmd->cmd_res = rcmd->cmd_res; + cmd->output_size = rcmd->output_size; + if (rcmd->output_size && (rcmd->output_size <= output_size) && output_data) + memcpy(output_data, rcmd->output_buff_raw, rcmd->output_size); + } + +out: + mutex_unlock(&virt_ras->remote_access_lock); + return ret; +} + +static int amdgpu_virt_ras_send_remote_cmd(struct ras_core_context *ras_core, + uint32_t cmd_id, void *input_data, uint32_t input_size, + void *output_data, uint32_t output_size) +{ + struct ras_cmd_ctx rcmd = {0}; + int ret; + + if (input_size > RAS_CMD_MAX_IN_SIZE) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + rcmd.cmd_id = cmd_id; + rcmd.input_size = input_size; + memcpy(rcmd.input_buff_raw, input_data, input_size); + + ret = amdgpu_virt_ras_remote_ioctl_cmd(ras_core, + &rcmd, output_data, output_size); + if (!ret) { + if (rcmd.output_size != output_size) + return RAS_CMD__ERROR_GENERIC; + } + + return ret; +} + +static int amdgpu_virt_ras_get_batch_trace_overview(struct ras_core_context *ras_core, + struct ras_log_batch_overview *overview) +{ + struct ras_cmd_batch_trace_snapshot_req req = {0}; + struct ras_cmd_batch_trace_snapshot_rsp rsp = {0}; + int ret; + + ret = amdgpu_virt_ras_send_remote_cmd(ras_core, RAS_CMD__GET_BATCH_TRACE_SNAPSHOT, + &req, sizeof(req), &rsp, sizeof(rsp)); + if (ret) + return ret; + + overview->first_batch_id = rsp.start_batch_id; + overview->last_batch_id = rsp.latest_batch_id; + overview->logged_batch_count = rsp.total_batch_num; + + return RAS_CMD__SUCCESS; +} + +static int amdgpu_virt_ras_get_cper_snapshot(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(ras_core->dev); + struct amdgpu_virt_ras_cmd *virt_ras = + (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + int ret; + + if (cmd->input_size != sizeof(struct ras_cmd_cper_snapshot_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + ret = amdgpu_virt_ras_send_remote_cmd(ras_core, cmd->cmd_id, + cmd->input_buff_raw, cmd->input_size, + cmd->output_buff_raw, sizeof(struct ras_cmd_cper_snapshot_rsp)); + if (ret) + return ret; + + memset(&virt_ras->batch_mgr, 0, sizeof(virt_ras->batch_mgr)); + amdgpu_virt_ras_get_batch_trace_overview(ras_core, + &virt_ras->batch_mgr.batch_overview); + + cmd->output_size = sizeof(struct ras_cmd_cper_snapshot_rsp); + return RAS_CMD__SUCCESS; +} + +static int amdgpu_virt_ras_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_id, + struct ras_log_info **trace_arr, uint32_t arr_num, + struct ras_cmd_batch_trace_record_rsp *rsp_cache) +{ + struct ras_cmd_batch_trace_record_req req = { + .start_batch_id = batch_id, + .batch_num = RAS_CMD_MAX_BATCH_NUM, + }; + struct ras_cmd_batch_trace_record_rsp *rsp = rsp_cache; + struct batch_ras_trace_info *batch; + int ret = 0; + uint32_t i; + + if (!rsp->real_batch_num || (batch_id < rsp->start_batch_id) || + (batch_id >= (rsp->start_batch_id + rsp->real_batch_num))) { + + memset(rsp, 0, sizeof(*rsp)); + ret = amdgpu_virt_ras_send_remote_cmd(ras_core, RAS_CMD__GET_BATCH_TRACE_RECORD, + &req, sizeof(req), rsp, sizeof(*rsp)); + if (ret) + return -EPIPE; + } + + batch = &rsp->batchs[batch_id - rsp->start_batch_id]; + if (batch_id != batch->batch_id) + return -ENODATA; + + for (i = 0; i < batch->trace_num; i++) { + if (i >= arr_num) + break; + trace_arr[i] = &rsp->records[batch->offset + i]; + } + + return i; +} + +static int amdgpu_virt_ras_get_cper_records(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd, void *data) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(ras_core->dev); + struct amdgpu_virt_ras_cmd *virt_ras = + (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + struct ras_cmd_cper_record_req *req = + (struct ras_cmd_cper_record_req *)cmd->input_buff_raw; + struct ras_cmd_cper_record_rsp *rsp = + (struct ras_cmd_cper_record_rsp *)cmd->output_buff_raw; + struct ras_log_batch_overview *overview = &virt_ras->batch_mgr.batch_overview; + struct ras_cmd_batch_trace_record_rsp *rsp_cache = &virt_ras->batch_mgr.batch_trace; + struct ras_log_info **trace; + uint32_t offset = 0, real_data_len = 0; + uint64_t batch_id; + uint8_t *out_buf; + int ret = 0, i, count; + + if (cmd->input_size != sizeof(struct ras_cmd_cper_record_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if (!req->buf_size || !req->buf_ptr || !req->cper_num) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + trace = kcalloc(MAX_RECORD_PER_BATCH, sizeof(*trace), GFP_KERNEL); + if (!trace) + return RAS_CMD__ERROR_GENERIC; + + out_buf = kzalloc(req->buf_size, GFP_KERNEL); + if (!out_buf) { + kfree(trace); + return RAS_CMD__ERROR_GENERIC; + } + + memset(out_buf, 0, req->buf_size); + + for (i = 0; i < req->cper_num; i++) { + batch_id = req->cper_start_id + i; + if (batch_id >= overview->last_batch_id) + break; + count = amdgpu_virt_ras_get_batch_records(ras_core, batch_id, + trace, MAX_RECORD_PER_BATCH, + rsp_cache); + if (count > 0) { + ret = ras_cper_generate_cper(ras_core, trace, count, + &out_buf[offset], req->buf_size - offset, &real_data_len); + if (ret) + break; + + offset += real_data_len; + } + } + + if ((ret && (ret != -ENOMEM)) || + copy_to_user(u64_to_user_ptr(req->buf_ptr), out_buf, offset)) { + kfree(out_buf); + kfree(trace); + return RAS_CMD__ERROR_GENERIC; + } + + rsp->real_data_size = offset; + rsp->real_cper_num = i; + rsp->remain_num = (ret == -ENOMEM) ? (req->cper_num - i) : 0; + rsp->version = 0; + + cmd->output_size = sizeof(struct ras_cmd_cper_record_rsp); + + kfree(out_buf); + kfree(trace); + + return RAS_CMD__SUCCESS; +} + +static int __fill_get_blocks_ecc_cmd(struct amdgpu_device *adev, + struct vram_blocks_ecc *blks_ecc) +{ + struct ras_cmd_ctx *rcmd; + + if (!blks_ecc || !blks_ecc->shared_mem.cpu_addr) + return -EINVAL; + + rcmd = (struct ras_cmd_ctx *)blks_ecc->shared_mem.cpu_addr; + + rcmd->cmd_id = RAS_CMD__GET_ALL_BLOCK_ECC_STATUS; + rcmd->input_size = sizeof(struct ras_cmd_blocks_ecc_req); + rcmd->output_buf_size = blks_ecc->shared_mem.size - sizeof(*rcmd); + + return 0; +} + +static int __set_cmd_auto_update(struct amdgpu_device *adev, + enum ras_cmd_id cmd_id, uint64_t gpa_addr, uint32_t len, bool reg) +{ + struct ras_cmd_auto_update_req req = {0}; + struct ras_cmd_auto_update_rsp rsp = {0}; + int ret; + + req.mode = reg ? 1 : 0; + req.cmd_id = cmd_id; + req.addr = gpa_addr; + req.len = len; + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__SET_CMD_AUTO_UPDATE, + &req, sizeof(req), &rsp, sizeof(rsp)); + + return ret; +} + +static int amdgpu_virt_ras_get_block_ecc(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd, void *data) +{ + struct amdgpu_device *adev = ras_core->dev; + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras = + (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + struct vram_blocks_ecc *blks_ecc = &virt_ras->blocks_ecc; + struct ras_cmd_ctx *blks_ecc_cmd_ctx; + struct ras_cmd_blocks_ecc_rsp *blks_ecc_rsp; + struct ras_cmd_block_ecc_info_req *input_data = + (struct ras_cmd_block_ecc_info_req *)cmd->input_buff_raw; + struct ras_cmd_block_ecc_info_rsp *output_data = + (struct ras_cmd_block_ecc_info_rsp *)cmd->output_buff_raw; + int ret = 0; + + if (cmd->input_size != sizeof(struct ras_cmd_block_ecc_info_req)) + return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + + if (input_data->block_id >= MAX_RAS_BLOCK_NUM) + return RAS_CMD__ERROR_INVALID_INPUT_DATA; + + if (__fill_get_blocks_ecc_cmd(adev, blks_ecc)) + return RAS_CMD__ERROR_GENERIC; + + if (!virt_ras->blocks_ecc.auto_update_actived) { + ret = __set_cmd_auto_update(adev, RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, + blks_ecc->shared_mem.gpa, + blks_ecc->shared_mem.size, true); + if (ret) + return ret; + + blks_ecc->auto_update_actived = true; + } + + blks_ecc_cmd_ctx = blks_ecc->shared_mem.cpu_addr; + blks_ecc_rsp = (struct ras_cmd_blocks_ecc_rsp *)blks_ecc_cmd_ctx->output_buff_raw; + + output_data->ce_count = blks_ecc_rsp->blocks[input_data->block_id].ce_count; + output_data->ue_count = blks_ecc_rsp->blocks[input_data->block_id].ue_count; + output_data->de_count = blks_ecc_rsp->blocks[input_data->block_id].de_count; + + cmd->output_size = sizeof(struct ras_cmd_block_ecc_info_rsp); + return RAS_CMD__SUCCESS; +} + +int amdgpu_virt_ras_check_address_validity(struct amdgpu_device *adev, + uint64_t address, bool *hit) +{ + struct ras_cmd_address_check_req req = {0}; + struct ras_cmd_address_check_rsp rsp = {0}; + int ret = 0; + + req.address = address; + + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CHECK_ADDRESS_VALIDITY, + &req, sizeof(req), &rsp, sizeof(rsp)); + + if (ret) + return RAS_CMD__ERROR_GENERIC; + + *hit = rsp.result ? true : false; + + return RAS_CMD__SUCCESS; +} + +int amdgpu_virt_ras_convert_retired_address(struct amdgpu_device *adev, + uint64_t address, uint64_t *pfn, uint32_t max_pfn_sz) +{ + struct ras_cmd_convert_retired_address_req req = {0}; + struct ras_cmd_convert_retired_address_rsp rsp = {0}; + int ret = 0, i; + int retired_page_count; + + if (!pfn || !max_pfn_sz) + return -EINVAL; + + req.address = address; + + ret = amdgpu_ras_mgr_handle_ras_cmd(adev, RAS_CMD__CONVERT_RETIRED_ADDRESS, + &req, sizeof(req), &rsp, sizeof(rsp)); + + if (ret || rsp.retired_count == 0) + return -EINVAL; + + retired_page_count = rsp.retired_count > max_pfn_sz ? max_pfn_sz : rsp.retired_count; + + for (i = 0; i < retired_page_count; i++) + pfn[i] = rsp.retired_addr[i] >> AMDGPU_GPU_PAGE_SHIFT; + + return retired_page_count; +} + +static struct ras_cmd_func_map amdgpu_virt_ras_cmd_maps[] = { + {RAS_CMD__GET_CPER_SNAPSHOT, amdgpu_virt_ras_get_cper_snapshot}, + {RAS_CMD__GET_CPER_RECORD, amdgpu_virt_ras_get_cper_records}, + {RAS_CMD__GET_BLOCK_ECC_STATUS, amdgpu_virt_ras_get_block_ecc}, +}; + +int amdgpu_virt_ras_handle_cmd(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd) +{ + struct ras_cmd_func_map *ras_cmd = NULL; + int i, res; + + for (i = 0; i < ARRAY_SIZE(amdgpu_virt_ras_cmd_maps); i++) { + if (cmd->cmd_id == amdgpu_virt_ras_cmd_maps[i].cmd_id) { + ras_cmd = &amdgpu_virt_ras_cmd_maps[i]; + break; + } + } + + if (ras_cmd) + res = ras_cmd->func(ras_core, cmd, NULL); + else + res = amdgpu_virt_ras_remote_ioctl_cmd(ras_core, cmd, + cmd->output_buff_raw, cmd->output_buf_size); + + cmd->cmd_res = res; + + if (cmd->output_size > cmd->output_buf_size) { + RAS_DEV_ERR(ras_core->dev, + "Output data size 0x%x exceeds buffer size 0x%x!\n", + cmd->output_size, cmd->output_buf_size); + return RAS_CMD__SUCCESS_EXEED_BUFFER; + } + + return RAS_CMD__SUCCESS; +} + +int amdgpu_virt_ras_sw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras_cmd; + + ras_mgr->virt_ras_cmd = kzalloc(sizeof(struct amdgpu_virt_ras_cmd), GFP_KERNEL); + if (!ras_mgr->virt_ras_cmd) + return -ENOMEM; + + virt_ras_cmd = ras_mgr->virt_ras_cmd; + mutex_init(&virt_ras_cmd->remote_access_lock); + + return 0; +} + +int amdgpu_virt_ras_sw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras_cmd = ras_mgr->virt_ras_cmd; + + mutex_destroy(&virt_ras_cmd->remote_access_lock); + kfree(ras_mgr->virt_ras_cmd); + ras_mgr->virt_ras_cmd = NULL; + + return 0; +} + +int amdgpu_virt_ras_hw_init(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras = + (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + struct vram_blocks_ecc *blks_ecc = &virt_ras->blocks_ecc; + + amdgpu_virt_get_ras_capability(adev); + + memset(blks_ecc, 0, sizeof(*blks_ecc)); + if (amdgpu_virt_ras_get_cmd_shared_mem(ras_mgr->ras_core, + RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, + AMD_SRIOV_UNIRAS_BLOCKS_BUF_SIZE, &blks_ecc->shared_mem)) + return -ENOMEM; + + return 0; +} + +int amdgpu_virt_ras_hw_fini(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras = + (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + struct vram_blocks_ecc *blks_ecc = &virt_ras->blocks_ecc; + + if (blks_ecc->shared_mem.cpu_addr) { + __set_cmd_auto_update(adev, + RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, + blks_ecc->shared_mem.gpa, + blks_ecc->shared_mem.size, false); + + memset(blks_ecc->shared_mem.cpu_addr, 0, blks_ecc->shared_mem.size); + } + memset(blks_ecc, 0, sizeof(*blks_ecc)); + + return 0; +} + +int amdgpu_virt_ras_pre_reset(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras = + (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + + virt_ras->blocks_ecc.auto_update_actived = false; + return 0; +} + +int amdgpu_virt_ras_post_reset(struct amdgpu_device *adev) +{ + return 0; +} + +void amdgpu_virt_ras_set_remote_uniras(struct amdgpu_device *adev, bool en) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras; + + if (!ras_mgr || !ras_mgr->virt_ras_cmd) + return; + + virt_ras = (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + virt_ras->remote_uniras_supported = en; +} + +bool amdgpu_virt_ras_remote_uniras_enabled(struct amdgpu_device *adev) +{ + struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev); + struct amdgpu_virt_ras_cmd *virt_ras; + + if (amdgpu_in_reset(adev)) + return false; + + if (!ras_mgr || !ras_mgr->virt_ras_cmd) + return false; + + virt_ras = (struct amdgpu_virt_ras_cmd *)ras_mgr->virt_ras_cmd; + + return virt_ras->remote_uniras_supported; +} diff --git a/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h new file mode 100644 index 0000000000000..3000c354b76fd --- /dev/null +++ b/drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMDGPU_VIRT_RAS_CMD_H__ +#define __AMDGPU_VIRT_RAS_CMD_H__ +#include "ras.h" + +struct remote_batch_trace_mgr { + struct ras_log_batch_overview batch_overview; + struct ras_cmd_batch_trace_record_rsp batch_trace; +}; + +struct amdgpu_virt_shared_mem { + uint64_t gpa; + void *cpu_addr; + uint32_t size; +}; + +struct vram_blocks_ecc { + struct amdgpu_virt_shared_mem shared_mem; + bool auto_update_actived; +}; + +struct amdgpu_virt_ras_cmd { + bool remote_uniras_supported; + struct remote_batch_trace_mgr batch_mgr; + struct vram_blocks_ecc blocks_ecc; + struct mutex remote_access_lock; +}; + +int amdgpu_virt_ras_sw_init(struct amdgpu_device *adev); +int amdgpu_virt_ras_sw_fini(struct amdgpu_device *adev); +int amdgpu_virt_ras_hw_init(struct amdgpu_device *adev); +int amdgpu_virt_ras_hw_fini(struct amdgpu_device *adev); +int amdgpu_virt_ras_handle_cmd(struct ras_core_context *ras_core, + struct ras_cmd_ctx *cmd); +int amdgpu_virt_ras_pre_reset(struct amdgpu_device *adev); +int amdgpu_virt_ras_post_reset(struct amdgpu_device *adev); +void amdgpu_virt_ras_set_remote_uniras(struct amdgpu_device *adev, bool en); +bool amdgpu_virt_ras_remote_uniras_enabled(struct amdgpu_device *adev); +int amdgpu_virt_ras_check_address_validity(struct amdgpu_device *adev, + uint64_t address, bool *hit); +int amdgpu_virt_ras_convert_retired_address(struct amdgpu_device *adev, + uint64_t address, uint64_t *pfn, uint32_t max_pfn_sz); +#endif diff --git a/drivers/gpu/drm/amd/ras/rascore/Makefile b/drivers/gpu/drm/amd/ras/rascore/Makefile index e826a1f86424c..06b265ec1cde8 100644 --- a/drivers/gpu/drm/amd/ras/rascore/Makefile +++ b/drivers/gpu/drm/amd/ras/rascore/Makefile @@ -36,7 +36,8 @@ RAS_CORE_FILES = ras_core.o \ ras_log_ring.o \ ras_cper.o \ ras_psp.o \ - ras_psp_v13_0.o + ras_psp_v13_0.o \ + ras_eeprom_fw.o RAS_CORE = $(addprefix $(AMD_GPU_RAS_PATH)/rascore/,$(RAS_CORE_FILES)) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras.h b/drivers/gpu/drm/amd/ras/rascore/ras.h index 3396b2e0949df..6449d7b8627d6 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras.h @@ -36,6 +36,7 @@ #include "ras_mp1.h" #include "ras_psp.h" #include "ras_log_ring.h" +#include "ras_eeprom_fw.h" #define RAS_HW_ERR "[Hardware Error]: " @@ -49,6 +50,17 @@ #define GPU_RESET_CAUSE_FATAL (RAS_CORE_RESET_GPU | 0x0002) #define GPU_RESET_CAUSE_RMA (RAS_CORE_RESET_GPU | 0x0004) +enum ras_gpu_health_status { + RAS_GPU_HEALTH_NONE = 0, + RAS_GPU_HEALTH_USABLE = 1, + RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2, + RAS_GPU_IN_BAD_STATUS = 3, +}; + +enum ras_core_fw_feature_flags { + RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM = BIT_ULL(0), +}; + enum ras_block_id { RAS_BLOCK_ID__UMC = 0, RAS_BLOCK_ID__SDMA, @@ -127,6 +139,16 @@ enum ras_gpu_status { RAS_GPU_STATUS__IS_VF = 0x8, }; +enum ras_fw_eeprom_cmd { + RAS_SMU_GetRASTableVersion = 0, + RAS_SMU_GetBadPageCount, + RAS_SMU_SetTimestamp, + RAS_SMU_GetTimestamp, + RAS_SMU_GetBadPageIpid, + RAS_SMU_EraseRasTable, + RAS_SMU_GetBadPageMcaAddr, +}; + struct ras_core_context; struct ras_bank_ecc; struct ras_umc; @@ -141,6 +163,10 @@ struct ras_mp1_sys_func { u32 msg, u32 *count); int (*mp1_dump_valid_bank)(struct ras_core_context *ras_core, u32 msg, u32 idx, u32 reg_idx, u64 *val); + int (*mp1_send_eeprom_msg)(struct ras_core_context *ras_core, + enum ras_fw_eeprom_cmd index, uint32_t param, uint32_t *read_arg); + int (*mp1_get_ras_enabled_mask)(struct ras_core_context *ras_core, + uint64_t *enabled_mask); }; struct ras_eeprom_sys_func { @@ -222,6 +248,7 @@ struct ras_bank_ecc { uint64_t status; uint64_t ipid; uint64_t addr; + uint64_t ts; }; struct ras_bank_ecc_node { @@ -294,6 +321,7 @@ struct ras_core_context { bool ras_eeprom_supported; struct ras_eeprom_control ras_eeprom; + struct ras_fw_eeprom_control ras_fw_eeprom; struct ras_psp ras_psp; struct ras_umc ras_umc; @@ -317,6 +345,8 @@ struct ras_core_context { spinlock_t seqno_lock; bool ras_core_enabled; + + u64 ras_fw_features; }; struct ras_core_context *ras_core_create(struct ras_core_config *init_config); @@ -367,4 +397,6 @@ int ras_core_event_notify(struct ras_core_context *ras_core, enum ras_notify_event event_id, void *data); int ras_core_get_device_system_info(struct ras_core_context *ras_core, struct device_system_info *dev_info); +int ras_core_convert_soc_pa_to_cur_nps_pages(struct ras_core_context *ras_core, + uint64_t soc_pa, uint64_t *page_pfn, uint32_t max_pages); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c index e433c70d29891..67a35409ff0e9 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca.c @@ -234,16 +234,27 @@ static int aca_log_bad_bank(struct ras_core_context *ras_core, bank_ecc->de_count) { struct ras_bank_ecc ras_ecc = {0}; - ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); - ras_ecc.addr = bank_ecc->bank_info.addr; - ras_ecc.ipid = bank_ecc->bank_info.ipid; - ras_ecc.status = bank_ecc->bank_info.status; - ras_ecc.seq_no = bank->seq_no; - - if (ras_core_gpu_in_reset(ras_core)) - ras_umc_log_bad_bank_pending(ras_core, &ras_ecc); - else - ras_umc_log_bad_bank(ras_core, &ras_ecc); + if (ras_fw_eeprom_supported(ras_core)) { + ret = ras_fw_eeprom_update_record(ras_core, &ras_ecc); + if (!ret) { + ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); + ras_ecc.status = bank_ecc->bank_info.status; + ras_ecc.seq_no = bank->seq_no; + } + } else { + ras_ecc.nps = ras_core_get_curr_nps_mode(ras_core); + ras_ecc.addr = bank_ecc->bank_info.addr; + ras_ecc.ipid = bank_ecc->bank_info.ipid; + ras_ecc.status = bank_ecc->bank_info.status; + ras_ecc.seq_no = bank->seq_no; + } + + if (!ret) { + if (ras_core_gpu_in_reset(ras_core)) + ras_umc_log_bad_bank_pending(ras_core, &ras_ecc); + else + ras_umc_log_bad_bank(ras_core, &ras_ecc); + } } aca_report_ecc_info(ras_core, diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c index 29df98948703b..210fbd8851a6d 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_aca_v1_0.c @@ -299,7 +299,7 @@ static int aca_parse_xgmi_bank(struct ras_core_context *ras_core, count = ACA_REG_MISC0_ERRCNT(bank->regs[ACA_REG_IDX__MISC0]); if (bank->ecc_type == RAS_ERR_TYPE__UE) { - if (ext_error_code != 0 && ext_error_code != 9) + if (ext_error_code != 0 && ext_error_code != 1 && ext_error_code != 9) count = 0ULL; ecc->ue_count = count; } else if (bank->ecc_type == RAS_ERR_TYPE__CE) { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c index 94e6d7420d94e..4f89810d85a15 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.c @@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core, if (cmd->input_size != sizeof(struct ras_cmd_dev_handle)) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; - if (ras_eeprom_reset_table(ras_core)) - return RAS_CMD__ERROR_GENERIC; + if (ras_fw_eeprom_supported(ras_core)) { + if (ras_fw_eeprom_reset_table(ras_core)) + return RAS_CMD__ERROR_GENERIC; + } else { + if (ras_eeprom_reset_table(ras_core)) + return RAS_CMD__ERROR_GENERIC; + } if (ras_umc_clean_badpage_data(ras_core)) return RAS_CMD__ERROR_GENERIC; diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h index 48a0715eb8218..7ea35a0289874 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_cmd.h @@ -75,6 +75,10 @@ enum ras_cmd_id { RAS_CMD__GET_CPER_RECORD, RAS_CMD__GET_BATCH_TRACE_SNAPSHOT, RAS_CMD__GET_BATCH_TRACE_RECORD, + RAS_CMD__GET_ALL_BLOCK_ECC_STATUS, + RAS_CMD__SET_CMD_AUTO_UPDATE, + RAS_CMD__CHECK_ADDRESS_VALIDITY, + RAS_CMD__CONVERT_RETIRED_ADDRESS, RAS_CMD__SUPPORTED_MAX = RAS_CMD_ID_COMMON_END, }; @@ -411,6 +415,64 @@ struct ras_cmd_batch_trace_record_rsp { struct ras_log_info records[RAS_CMD_MAX_TRACE_NUM]; }; +struct ras_cmd_auto_update_req { + struct ras_cmd_dev_handle dev; + uint32_t mode; + uint32_t cmd_id; + uint64_t addr; + uint32_t len; + uint32_t reserved[5]; +}; + +struct ras_cmd_auto_update_rsp { + uint32_t version; + uint32_t reserved[4]; +}; + +struct ras_cmd_address_check_req { + struct ras_cmd_dev_handle dev; + uint64_t address; + uint32_t flags; + uint32_t vf_idx; + uint32_t reserved[4]; +}; + +struct ras_cmd_address_check_rsp { + uint32_t version; + uint32_t result; + uint32_t reserved[6]; +}; + +struct ras_cmd_convert_retired_address_req { + struct ras_cmd_dev_handle dev; + uint64_t address; + uint32_t reserved[6]; +}; + +#define RAS_CMD_MAX_RETIRED_ADDR_COUNT 32 +struct ras_cmd_convert_retired_address_rsp { + uint32_t version; + uint32_t retired_count; + uint64_t retired_addr[RAS_CMD_MAX_RETIRED_ADDR_COUNT]; +}; + +struct ras_cmd_blocks_ecc_req { + struct ras_cmd_dev_handle dev; +}; + +struct ras_cmd_block_ecc { + uint32_t ce_count; + uint32_t ue_count; + uint32_t de_count; +}; + +#define MAX_RAS_BLOCK_NUM 20 +struct ras_cmd_blocks_ecc_rsp { + uint32_t version; + uint32_t reserved[5]; + struct ras_cmd_block_ecc blocks[MAX_RAS_BLOCK_NUM]; +}; + #pragma pack(pop) int ras_cmd_init(struct ras_core_context *ras_core); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_core.c b/drivers/gpu/drm/amd/ras/rascore/ras_core.c index 01122b55c98ab..29b1b8f0cc263 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_core.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_core.c @@ -62,14 +62,19 @@ int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core, uint64_t timestamp, struct ras_time *tm) { int days_in_month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; - uint64_t month = 0, day = 0, hour = 0, minute = 0, second = 0; + uint64_t month = 0, day = 0, hour = 0, minute = 0, second = 0, remainder; uint32_t year = 0; int seconds_per_day = 24 * 60 * 60; int seconds_per_hour = 60 * 60; int seconds_per_minute = 60; int days, remaining_seconds; - days = div64_u64_rem(timestamp, seconds_per_day, (uint64_t *)&remaining_seconds); + if (!tm) + return -EINVAL; + + days = div64_u64_rem(timestamp, seconds_per_day, &remainder); + /* remainder will always be less than seconds_per_day. */ + remaining_seconds = remainder; /* utc_timestamp follows the Unix epoch */ year = 1970; @@ -114,6 +119,9 @@ bool ras_core_gpu_in_reset(struct ras_core_context *ras_core) { uint32_t status = 0; + if (!ras_core) + return false; + if (ras_core->sys_fn && ras_core->sys_fn->check_gpu_status) ras_core->sys_fn->check_gpu_status(ras_core, &status); @@ -125,6 +133,9 @@ bool ras_core_gpu_is_vf(struct ras_core_context *ras_core) { uint32_t status = 0; + if (!ras_core) + return false; + if (ras_core->sys_fn && ras_core->sys_fn->check_gpu_status) ras_core->sys_fn->check_gpu_status(ras_core, &status); @@ -239,7 +250,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core) int count; int ret; - count = ras_eeprom_get_record_count(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + count = ras_fw_eeprom_get_record_count(ras_core); + else + count = ras_eeprom_get_record_count(ras_core); if (!count) return 0; @@ -253,7 +267,10 @@ static int ras_core_eeprom_recovery(struct ras_core_context *ras_core) return ret; } - ras_eeprom_sync_info(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ras_fw_eeprom_sync_info(ras_core); + else + ras_eeprom_sync_info(ras_core); return ret; } @@ -263,6 +280,9 @@ struct ras_core_context *ras_core_create(struct ras_core_config *init_config) struct ras_core_context *ras_core; struct ras_core_config *config; + if (!init_config) + return NULL; + ras_core = kzalloc(sizeof(*ras_core), GFP_KERNEL); if (!ras_core) return NULL; @@ -382,7 +402,12 @@ int ras_core_hw_init(struct ras_core_context *ras_core) if (ret) goto init_err5; - ret = ras_eeprom_hw_init(ras_core); + ras_fw_init_feature_flags(ras_core); + + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_hw_init(ras_core); + else + ret = ras_eeprom_hw_init(ras_core); if (ret) goto init_err6; @@ -393,7 +418,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core) goto init_err6; } - ret = ras_eeprom_check_storage_status(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_check_storage_status(ras_core); + else + ret = ras_eeprom_check_storage_status(ras_core); if (ret) goto init_err6; @@ -406,7 +434,10 @@ int ras_core_hw_init(struct ras_core_context *ras_core) return 0; init_err7: - ras_eeprom_hw_fini(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ras_fw_eeprom_hw_fini(ras_core); + else + ras_eeprom_hw_fini(ras_core); init_err6: ras_gfx_hw_fini(ras_core); init_err5: @@ -427,7 +458,10 @@ int ras_core_hw_fini(struct ras_core_context *ras_core) ras_core->is_initialized = false; ras_process_fini(ras_core); - ras_eeprom_hw_fini(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + ras_fw_eeprom_hw_fini(ras_core); + else + ras_eeprom_hw_fini(ras_core); ras_gfx_hw_fini(ras_core); ras_nbio_hw_fini(ras_core); ras_umc_hw_fini(ras_core); @@ -457,6 +491,9 @@ int ras_core_handle_fatal_error(struct ras_core_context *ras_core) uint32_t ras_core_get_curr_nps_mode(struct ras_core_context *ras_core) { + if (!ras_core) + return 0; + if (ras_core->ras_nbio.ip_func && ras_core->ras_nbio.ip_func->get_memory_partition_mode) return ras_core->ras_nbio.ip_func->get_memory_partition_mode(ras_core); @@ -505,8 +542,11 @@ bool ras_core_is_enabled(struct ras_core_context *ras_core) uint64_t ras_core_get_utc_second_timestamp(struct ras_core_context *ras_core) { - if (ras_core && ras_core->sys_fn && - ras_core->sys_fn->get_utc_second_timestamp) + if (!ras_core) + return 0; + + if (ras_core->sys_fn && + ras_core->sys_fn->get_utc_second_timestamp) return ras_core->sys_fn->get_utc_second_timestamp(ras_core); RAS_DEV_ERR(ras_core->dev, "Failed to get system timestamp!\n"); @@ -528,13 +568,17 @@ bool ras_core_ras_interrupt_detected(struct ras_core_context *ras_core) ras_core->sys_fn->detect_ras_interrupt) return ras_core->sys_fn->detect_ras_interrupt(ras_core); - RAS_DEV_ERR(ras_core->dev, "Failed to detect ras interrupt!\n"); + if (ras_core && ras_core->dev) + RAS_DEV_ERR(ras_core->dev, "Failed to detect ras interrupt!\n"); + return false; } int ras_core_get_gpu_mem(struct ras_core_context *ras_core, enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) { + if (!ras_core || !gpu_mem) + return -EINVAL; if (ras_core->sys_fn && ras_core->sys_fn->get_gpu_mem) return ras_core->sys_fn->get_gpu_mem(ras_core, mem_type, gpu_mem); @@ -545,6 +589,8 @@ int ras_core_get_gpu_mem(struct ras_core_context *ras_core, int ras_core_put_gpu_mem(struct ras_core_context *ras_core, enum gpu_mem_type mem_type, struct gpu_mem_block *gpu_mem) { + if (!ras_core || !gpu_mem) + return -EINVAL; if (ras_core->sys_fn && ras_core->sys_fn->put_gpu_mem) return ras_core->sys_fn->put_gpu_mem(ras_core, mem_type, gpu_mem); @@ -559,6 +605,9 @@ bool ras_core_is_ready(struct ras_core_context *ras_core) bool ras_core_check_safety_watermark(struct ras_core_context *ras_core) { + if (ras_fw_eeprom_supported(ras_core)) + return ras_fw_eeprom_check_safety_watermark(ras_core); + return ras_eeprom_check_safety_watermark(ras_core); } @@ -595,9 +644,35 @@ int ras_core_event_notify(struct ras_core_context *ras_core, int ras_core_get_device_system_info(struct ras_core_context *ras_core, struct device_system_info *dev_info) { + if (!dev_info) + return -EINVAL; + if (ras_core && ras_core->sys_fn && ras_core->sys_fn->get_device_system_info) return ras_core->sys_fn->get_device_system_info(ras_core, dev_info); return -RAS_CORE_NOT_SUPPORTED; } + +int ras_core_convert_soc_pa_to_cur_nps_pages(struct ras_core_context *ras_core, + uint64_t soc_pa, uint64_t *page_pfn, uint32_t max_pages) +{ + struct eeprom_umc_record record; + uint32_t cur_nps_mode; + int count = 0; + + if (!ras_core || !page_pfn || !max_pages) + return -EINVAL; + + cur_nps_mode = ras_core_get_curr_nps_mode(ras_core); + if (!cur_nps_mode || cur_nps_mode > UMC_MEMORY_PARTITION_MODE_NPS8) + return -EINVAL; + + memset(&record, 0, sizeof(record)); + record.cur_nps_retired_row_pfn = RAS_ADDR_TO_PFN(soc_pa); + + count = ras_umc_convert_record_to_nps_pages(ras_core, + &record, cur_nps_mode, page_pfn, max_pages); + + return count; +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c index cd6b057bdaf3b..65c1812a10fb1 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c @@ -829,8 +829,8 @@ static int ras_eeprom_update_header(struct ras_eeprom_control *control) } /** - * ras_core_eeprom_append -- append records to the EEPROM RAS table - * @control: pointer to control structure + * ras_eeprom_append -- append records to the EEPROM RAS table + * @ras_core: pointer to ras core context * @record: array of records to append * @num: number of records in @record array * diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h index 2abe566c18b67..f2c001ef64e1f 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom.h @@ -57,13 +57,6 @@ do { \ (RECORD)->retired_row_pfn = tmp; \ } while (0) -enum ras_gpu_health_status { - RAS_GPU_HEALTH_NONE = 0, - RAS_GPU_HEALTH_USABLE = 1, - RAS_GPU_RETIRED__ECC_REACH_THRESHOLD = 2, - RAS_GPU_IN_BAD_STATUS = 3, -}; - enum ras_eeprom_err_type { RAS_EEPROM_ERR_NA, RAS_EEPROM_ERR_RECOVERABLE, diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c new file mode 100644 index 0000000000000..29001e606d1bc --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "ras.h" + +#define RAS_SMU_MESSAGE_TIMEOUT_MS 1000 /* 1s */ + +void ras_fw_init_feature_flags(struct ras_core_context *ras_core) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint64_t flags = 0ULL; + + if (!sys_func || !sys_func->mp1_get_ras_enabled_mask) + return; + + if (!sys_func->mp1_get_ras_enabled_mask(ras_core, &flags)) + ras_core->ras_fw_features = flags; +} + +bool ras_fw_eeprom_supported(struct ras_core_context *ras_core) +{ + return !!(ras_core->ras_fw_features & RAS_CORE_FW_FEATURE_BIT__RAS_EEPROM); +} + +int ras_fw_get_table_version(struct ras_core_context *ras_core, + uint32_t *table_version) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + + return sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetRASTableVersion, 0, table_version); +} + +int ras_fw_get_badpage_count(struct ras_core_context *ras_core, + uint32_t *count, uint32_t timeout) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint64_t end, now; + int ret = 0; + + now = (uint64_t)ktime_to_ms(ktime_get()); + end = now + timeout; + + do { + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageCount, 0, count); + /* eeprom is not ready */ + if (ret != -EBUSY) + return ret; + + mdelay(10); + now = (uint64_t)ktime_to_ms(ktime_get()); + } while (now < end); + + RAS_DEV_ERR(ras_core->dev, + "smu get bad page count timeout!\n"); + return ret; +} + +int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core, + uint16_t index, uint64_t *mca_addr) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t temp_arg, temp_addr_lo, temp_addr_high; + int ret; + + temp_arg = index | (1 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_lo); + if (ret) + return ret; + + temp_arg = index | (2 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageMcaAddr, temp_arg, &temp_addr_high); + + if (!ret) + *mca_addr = (uint64_t)temp_addr_high << 32 | temp_addr_lo; + + return ret; +} + +int ras_fw_set_timestamp(struct ras_core_context *ras_core, + uint64_t timestamp) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + + return sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_SetTimestamp, (uint32_t)timestamp, 0); +} + +int ras_fw_get_timestamp(struct ras_core_context *ras_core, + uint16_t index, uint64_t *timestamp) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t temp = 0; + int ret; + + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetTimestamp, index, &temp); + if (!ret) + *timestamp = temp; + + return ret; +} + +int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, + uint16_t index, uint64_t *ipid) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + uint32_t temp_arg, temp_ipid_lo, temp_ipid_high; + int ret; + + temp_arg = index | (1 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_lo); + if (ret) + return ret; + + temp_arg = index | (2 << 16); + ret = sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_GetBadPageIpid, temp_arg, &temp_ipid_high); + if (!ret) + *ipid = (uint64_t)temp_ipid_high << 32 | temp_ipid_lo; + + return ret; +} + +int ras_fw_erase_ras_table(struct ras_core_context *ras_core, + uint32_t *result) +{ + struct ras_mp1 *mp1 = &ras_core->ras_mp1; + const struct ras_mp1_sys_func *sys_func = mp1->sys_func; + + return sys_func->mp1_send_eeprom_msg(ras_core, + RAS_SMU_EraseRasTable, 0, result); +} + +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + u32 erase_res = 0; + int res; + + mutex_lock(&control->ras_tbl_mutex); + + res = ras_fw_erase_ras_table(ras_core, &erase_res); + if (res || erase_res) { + RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d", + res, erase_res); + if (!res) + res = -EIO; + } + + control->ras_num_recs = 0; + control->bad_channel_bitmap = 0; + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + &control->ras_num_recs); + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + &control->bad_channel_bitmap); + control->update_channel_flag = false; + + mutex_unlock(&control->ras_tbl_mutex); + + return res; +} + +bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + bool ret = false; + int bad_page_count; + + if (!control->record_threshold_config) + return false; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + + if (bad_page_count > control->record_threshold_count) + RAS_DEV_WARN(ras_core->dev, "RAS records:%d exceed threshold:%d", + bad_page_count, control->record_threshold_count); + + if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || + (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { + RAS_DEV_WARN(ras_core->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures.\n"); + ret = false; + } else { + ras_core->is_rma = true; + RAS_DEV_WARN(ras_core->dev, + "Please consider adjusting the customized threshold.\n"); + ret = true; + } + + return ret; +} + +int ras_fw_eeprom_append(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, const u32 num) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int threshold_config = control->record_threshold_config; + int i, bad_page_count; + + mutex_lock(&control->ras_tbl_mutex); + + for (i = 0; i < num; i++) { + /* update bad channel bitmap */ + if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && + !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { + control->bad_channel_bitmap |= 1 << record[i].mem_channel; + control->update_channel_flag = true; + } + } + control->ras_num_recs += num; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + + if (threshold_config != 0 && + bad_page_count > control->record_threshold_count) { + RAS_DEV_WARN(ras_core->dev, + "Saved bad pages %d reaches threshold value %d\n", + bad_page_count, control->record_threshold_count); + + if ((threshold_config != WARN_NONSTOP_OVER_THRESHOLD) && + (threshold_config != NONSTOP_OVER_THRESHOLD)) + ras_core->is_rma = true; + + /* ignore the -ENOTSUPP return value */ + ras_core_event_notify(ras_core, RAS_EVENT_ID__DEVICE_RMA, NULL); + } + + mutex_unlock(&control->ras_tbl_mutex); + return 0; +} + +int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, + struct eeprom_umc_record *record_umc, + struct ras_bank_ecc *ras_ecc, + u32 rec_idx, const u32 num) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int i, ret, end_idx; + u64 mca, ipid, ts; + + if (!ras_core->ras_umc.ip_func || + !ras_core->ras_umc.ip_func->mca_ipid_parse) + return -EOPNOTSUPP; + + mutex_lock(&control->ras_tbl_mutex); + + end_idx = rec_idx + num; + for (i = rec_idx; i < end_idx; i++) { + ret = ras_fw_get_badpage_mca_addr(ras_core, i, &mca); + if (ret) + goto out; + + ret = ras_fw_get_badpage_ipid(ras_core, i, &ipid); + if (ret) + goto out; + + ret = ras_fw_get_timestamp(ras_core, i, &ts); + if (ret) + goto out; + + if (record_umc) { + record_umc[i - rec_idx].address = mca; + /* retired_page (pa) is unused now */ + record_umc[i - rec_idx].retired_row_pfn = 0x1ULL; + record_umc[i - rec_idx].ts = ts; + record_umc[i - rec_idx].err_type = RAS_EEPROM_ERR_NON_RECOVERABLE; + + ras_core->ras_umc.ip_func->mca_ipid_parse(ras_core, ipid, + (uint32_t *)&(record_umc[i - rec_idx].cu), + (uint32_t *)&(record_umc[i - rec_idx].mem_channel), + (uint32_t *)&(record_umc[i - rec_idx].mcumc_id), NULL); + + /* update bad channel bitmap */ + if ((record_umc[i - rec_idx].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && + !(control->bad_channel_bitmap & (1 << record_umc[i - rec_idx].mem_channel))) { + control->bad_channel_bitmap |= 1 << record_umc[i - rec_idx].mem_channel; + control->update_channel_flag = true; + } + } + + if (ras_ecc) { + ras_ecc[i - rec_idx].addr = mca; + ras_ecc[i - rec_idx].ipid = ipid; + ras_ecc[i - rec_idx].ts = ts; + } + + } + +out: + mutex_unlock(&control->ras_tbl_mutex); + return ret; +} + +uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core) +{ + if (!ras_core) + return 0; + + return ras_core->ras_fw_eeprom.ras_num_recs; +} + +int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, + struct ras_bank_ecc *ras_ecc) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int ret, retry = 20; + u32 recs_num_new = control->ras_num_recs; + + do { + /* 1000ms timeout is long enough, smu_get_badpage_count won't + * return -EBUSY before timeout. + */ + ret = ras_fw_get_badpage_count(ras_core, + &recs_num_new, RAS_SMU_MESSAGE_TIMEOUT_MS); + if (!ret && + (recs_num_new == control->ras_num_recs)) { + /* record number update in PMFW needs some time, + * smu_get_badpage_count may return immediately without + * count update, sleep for a while and retry again. + */ + msleep(50); + retry--; + } else { + break; + } + } while (retry); + + if (ret) + return ret; + + if (recs_num_new > control->ras_num_recs) + ret = ras_fw_eeprom_read_idx(ras_core, 0, + ras_ecc, control->ras_num_recs, 1); + else + ret = -EINVAL; + + return ret; +} + +static int __check_ras_fw_table_status(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + uint64_t local_time; + int res; + + mutex_init(&control->ras_tbl_mutex); + + res = ras_fw_get_table_version(ras_core, &(control->version)); + if (res) + return res; + + res = ras_fw_get_badpage_count(ras_core, &(control->ras_num_recs), 100); + if (res) + return res; + + local_time = (uint64_t)ktime_get_real_seconds(); + res = ras_fw_set_timestamp(ras_core, local_time); + if (res) + return res; + + control->ras_max_record_count = 4000; + + + if (control->ras_num_recs > control->ras_max_record_count) { + RAS_DEV_ERR(ras_core->dev, + "RAS header invalid, records in header: %u max allowed :%u", + control->ras_num_recs, control->ras_max_record_count); + return -EINVAL; + } + + return 0; +} + +int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control; + struct ras_eeprom_config *eeprom_cfg; + struct ras_mp1 *mp1; + const struct ras_mp1_sys_func *sys_func; + + if (!ras_core) + return -EINVAL; + + mp1 = &ras_core->ras_mp1; + sys_func = mp1->sys_func; + + if (!sys_func || !sys_func->mp1_send_eeprom_msg) + return -EINVAL; + + ras_core->is_rma = false; + + control = &ras_core->ras_fw_eeprom; + + memset(control, 0, sizeof(*control)); + + eeprom_cfg = &ras_core->config->eeprom_cfg; + control->record_threshold_config = + eeprom_cfg->eeprom_record_threshold_config; + + control->record_threshold_count = 4000; + if (eeprom_cfg->eeprom_record_threshold_count < + control->record_threshold_count) + control->record_threshold_count = + eeprom_cfg->eeprom_record_threshold_count; + + control->update_channel_flag = false; + + return __check_ras_fw_table_status(ras_core); +} + +int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control; + + if (!ras_core) + return -EINVAL; + + control = &ras_core->ras_fw_eeprom; + mutex_destroy(&control->ras_tbl_mutex); + + return 0; +} + +int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + int bad_page_count; + + bad_page_count = ras_umc_get_badpage_count(ras_core); + + if ((control->record_threshold_count < bad_page_count) && + (control->record_threshold_config != 0)) { + RAS_DEV_ERR(ras_core->dev, "RAS records:%d exceed threshold:%d", + bad_page_count, control->record_threshold_count); + if ((control->record_threshold_config == WARN_NONSTOP_OVER_THRESHOLD) || + (control->record_threshold_config == NONSTOP_OVER_THRESHOLD)) { + RAS_DEV_WARN(ras_core->dev, + "Please consult AMD Service Action Guide (SAG) for appropriate service procedures\n"); + } else { + ras_core->is_rma = true; + RAS_DEV_ERR(ras_core->dev, + "User defined threshold is set, runtime service will be halt when threshold is reached\n"); + } + return 0; + } + + RAS_DEV_INFO(ras_core->dev, + "Found existing EEPROM table with %d records\n", + bad_page_count); + /* Warn if we are at 90% of the threshold or above + */ + if (10 * bad_page_count >= 9 * control->record_threshold_count) + RAS_DEV_WARN(ras_core->dev, + "RAS records:%u exceeds 90%% of threshold:%d\n", + bad_page_count, + control->record_threshold_count); + + return 0; +} + +enum ras_gpu_health_status + ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom; + + if (!control->record_threshold_config) + return RAS_GPU_HEALTH_NONE; + + if (ras_core->is_rma) + return RAS_GPU_RETIRED__ECC_REACH_THRESHOLD; + + return RAS_GPU_HEALTH_USABLE; +} + +void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core) +{ + struct ras_fw_eeprom_control *control; + + if (!ras_core) + return; + + control = &ras_core->ras_fw_eeprom; + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM, + &control->ras_num_recs); + ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP, + &control->bad_channel_bitmap); +} diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h new file mode 100644 index 0000000000000..762345be075c2 --- /dev/null +++ b/drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2026 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __RAS_EEPROM_FW_H__ +#define __RAS_EEPROM_FW_H__ + +struct ras_fw_eeprom_control { + uint32_t version; + /* record threshold */ + int record_threshold_config; + uint32_t record_threshold_count; + bool update_channel_flag; + + /* Number of records in the table. + */ + u32 ras_num_recs; + + /* Maximum possible number of records + * we could store, i.e. the maximum capacity + * of the table. + */ + u32 ras_max_record_count; + + /* Protect table access via this mutex. + */ + struct mutex ras_tbl_mutex; + + /* Record channel info which occurred bad pages + */ + u32 bad_channel_bitmap; +}; + +void ras_fw_init_feature_flags(struct ras_core_context *ras_core); +bool ras_fw_eeprom_supported(struct ras_core_context *ras_core); +int ras_fw_get_table_version(struct ras_core_context *ras_core, + uint32_t *table_version); +int ras_fw_get_badpage_count(struct ras_core_context *ras_core, + uint32_t *count, uint32_t timeout); +int ras_fw_get_badpage_mca_addr(struct ras_core_context *ras_core, + uint16_t index, uint64_t *mca_addr); +int ras_fw_set_timestamp(struct ras_core_context *ras_core, + uint64_t timestamp); +int ras_fw_get_timestamp(struct ras_core_context *ras_core, + uint16_t index, uint64_t *timestamp); +int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, + uint16_t index, uint64_t *ipid); +int ras_fw_erase_ras_table(struct ras_core_context *ras_core, + uint32_t *result); +int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core); +bool ras_fw_eeprom_check_safety_watermark(struct ras_core_context *ras_core); +int ras_fw_eeprom_append(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, const u32 num); +int ras_fw_eeprom_read_idx(struct ras_core_context *ras_core, + struct eeprom_umc_record *record_umc, + struct ras_bank_ecc *ras_ecc, + u32 rec_idx, const u32 num); +uint32_t ras_fw_eeprom_get_record_count(struct ras_core_context *ras_core); +int ras_fw_eeprom_update_record(struct ras_core_context *ras_core, + struct ras_bank_ecc *ras_ecc); +int ras_fw_eeprom_hw_init(struct ras_core_context *ras_core); +int ras_fw_eeprom_hw_fini(struct ras_core_context *ras_core); +int ras_fw_eeprom_check_storage_status(struct ras_core_context *ras_core); +enum ras_gpu_health_status + ras_fw_eeprom_check_gpu_status(struct ras_core_context *ras_core); +void ras_fw_eeprom_sync_info(struct ras_core_context *ras_core); + +#endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c index ccdb42d2dd605..5d556e2a7000c 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_psp.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp.c @@ -507,6 +507,7 @@ static int send_load_ta_fw_cmd(struct ras_core_context *ras_core, ta_init_flags->channel_dis_num = ta_ctx->init_param.channel_dis_num; ta_init_flags->nps_mode = ta_ctx->init_param.nps_mode; ta_init_flags->active_umc_mask = ta_ctx->init_param.active_umc_mask; + ta_init_flags->vram_type = ta_ctx->init_param.vram_type; /* Setup load ras ta command */ memset(&psp_load_ta_cmd, 0, sizeof(psp_load_ta_cmd)); diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_psp.h b/drivers/gpu/drm/amd/ras/rascore/ras_psp.h index 71776fecfd664..347f5334c3f34 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_psp.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_psp.h @@ -51,6 +51,7 @@ struct ras_ta_init_param { uint8_t channel_dis_num; uint8_t nps_mode; uint32_t active_umc_mask; + uint8_t vram_type; }; struct gpu_mem_block { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h b/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h index 0921e36d3274e..e910a75b30229 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_ta_if.h @@ -167,6 +167,7 @@ struct ras_ta_init_flags { uint8_t channel_dis_num; uint8_t nps_mode; uint32_t active_umc_mask; + uint8_t vram_type; }; struct ras_ta_mca_addr { diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c index 4dae64c424a24..d4072350f48fe 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.c @@ -154,22 +154,36 @@ int ras_umc_clear_logged_ecc(struct ras_core_context *ras_core) return 0; } +int ras_umc_convert_record_to_nps_pages(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps, + uint64_t *page_pfn, uint32_t max_pages) +{ + int count = 0; + struct ras_umc *ras_umc = &ras_core->ras_umc; + + if (!page_pfn || !max_pages) + return -EINVAL; + + if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) + count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, + record, nps, page_pfn, max_pages); + + return count; +} + static void ras_umc_reserve_eeprom_record(struct ras_core_context *ras_core, struct eeprom_umc_record *record) { - struct ras_umc *ras_umc = &ras_core->ras_umc; uint64_t page_pfn[16]; int count = 0, i; memset(page_pfn, 0, sizeof(page_pfn)); - if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) { - count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, + count = ras_umc_convert_record_to_nps_pages(ras_core, record, record->cur_nps, page_pfn, ARRAY_SIZE(page_pfn)); - if (count <= 0) { - RAS_DEV_ERR(ras_core->dev, - "Fail to convert error address! count:%d\n", count); - return; - } + if (count <= 0) { + RAS_DEV_ERR(ras_core->dev, + "Fail to convert error address! count:%d\n", count); + return; } /* Reserve memory */ @@ -208,7 +222,7 @@ int ras_umc_log_pending_bad_bank(struct ras_core_context *ras_core) mutex_lock(&ras_umc->pending_ecc_lock); list_for_each_entry_safe(ecc_node, tmp, &ras_umc->pending_ecc_list, node){ - if (ecc_node && !ras_umc_log_bad_bank(ras_core, &ecc_node->ecc)) { + if (!ras_umc_log_bad_bank(ras_core, &ecc_node->ecc)) { list_del(&ecc_node->node); kfree(ecc_node); } @@ -367,10 +381,8 @@ static int ras_umc_update_eeprom_ram_data(struct ras_core_context *ras_core, } memset(page_pfn, 0, sizeof(page_pfn)); - if (ras_umc->ip_func && ras_umc->ip_func->eeprom_record_to_nps_pages) - count = ras_umc->ip_func->eeprom_record_to_nps_pages(ras_core, + count = ras_umc_convert_record_to_nps_pages(ras_core, bps, bps->cur_nps, page_pfn, ARRAY_SIZE(page_pfn)); - if (count > 0) { for (j = 0; j < count; j++) { bps->cur_nps_retired_row_pfn = page_pfn[j]; @@ -436,17 +448,27 @@ int ras_umc_load_bad_pages(struct ras_core_context *ras_core) uint32_t ras_num_recs; int ret; - ras_num_recs = ras_eeprom_get_record_count(ras_core); - /* no bad page record, skip eeprom access */ - if (!ras_num_recs || - ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) - return 0; + if (ras_fw_eeprom_supported(ras_core)) { + ras_num_recs = ras_fw_eeprom_get_record_count(ras_core); + /* no bad page record, skip eeprom access */ + if (!ras_num_recs || + ras_core->ras_fw_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) + return 0; + } else { + ras_num_recs = ras_eeprom_get_record_count(ras_core); + if (!ras_num_recs || + ras_core->ras_eeprom.record_threshold_config == DISABLE_RETIRE_PAGE) + return 0; + } bps = kcalloc(ras_num_recs, sizeof(*bps), GFP_KERNEL); if (!bps) return -ENOMEM; - ret = ras_eeprom_read(ras_core, bps, ras_num_recs); + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_read_idx(ras_core, bps, 0, 0, ras_num_recs); + else + ret = ras_eeprom_read(ras_core, bps, ras_num_recs); if (ret) { RAS_DEV_ERR(ras_core->dev, "Failed to load EEPROM table records!"); } else { @@ -474,14 +496,21 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core) if (!data->bps) return 0; - eeprom_record_num = ras_eeprom_get_record_count(ras_core); + if (ras_fw_eeprom_supported(ras_core)) + eeprom_record_num = ras_fw_eeprom_get_record_count(ras_core); + else + eeprom_record_num = ras_eeprom_get_record_count(ras_core); mutex_lock(&ras_umc->umc_lock); save_count = data->count - eeprom_record_num; /* only new entries are saved */ if (save_count > 0) { - if (ras_eeprom_append(ras_core, - &data->bps[eeprom_record_num], - save_count)) { + if (ras_fw_eeprom_supported(ras_core)) + ret = ras_fw_eeprom_append(ras_core, &data->bps[eeprom_record_num], + save_count); + else + ret = ras_eeprom_append(ras_core, &data->bps[eeprom_record_num], + save_count); + if (ret) { RAS_DEV_ERR(ras_core->dev, "Failed to save EEPROM table data!"); ret = -EIO; goto exit; @@ -497,27 +526,40 @@ static int ras_umc_save_bad_pages(struct ras_core_context *ras_core) int ras_umc_handle_bad_pages(struct ras_core_context *ras_core, void *data) { - struct eeprom_umc_record records[MAX_ECC_NUM_PER_RETIREMENT]; + struct eeprom_umc_record *records; int count, ret; - memset(records, 0, sizeof(records)); - count = ras_umc_get_new_records(ras_core, records, ARRAY_SIZE(records)); - if (count <= 0) - return -ENODATA; + records = kcalloc(MAX_ECC_NUM_PER_RETIREMENT, + sizeof(*records), GFP_KERNEL); + if (!records) + return -ENOMEM; + + count = ras_umc_get_new_records(ras_core, records, + MAX_ECC_NUM_PER_RETIREMENT); + if (count <= 0) { + ret = -ENODATA; + goto out; + } ret = ras_umc_add_bad_pages(ras_core, records, count, false); if (ret) { RAS_DEV_ERR(ras_core->dev, "Failed to add ras bad page!\n"); - return -EINVAL; + ret = -EINVAL; + goto out; } ret = ras_umc_save_bad_pages(ras_core); if (ret) { RAS_DEV_ERR(ras_core->dev, "Failed to save ras bad page\n"); - return -EINVAL; + ret = -EINVAL; + goto out; } - return 0; + ret = 0; + +out: + kfree(records); + return ret; } int ras_umc_sw_init(struct ras_core_context *ras_core) diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h index 7d9e779d8c4c6..1d3026be509b8 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc.h +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc.h @@ -108,6 +108,8 @@ struct ras_umc_ip_func { struct umc_bank_addr bank_addr, uint64_t *soc_pa); int (*soc_pa_to_bank)(struct ras_core_context *ras_core, uint64_t soc_pa, struct umc_bank_addr *bank_addr); + void (*mca_ipid_parse)(struct ras_core_context *ras_core, uint64_t ipid, + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid); }; struct eeprom_store_record { @@ -163,4 +165,7 @@ int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index bool ras_umc_check_retired_addr(struct ras_core_context *ras_core, uint64_t addr); int ras_umc_translate_soc_pa_and_bank(struct ras_core_context *ras_core, uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa); +int ras_umc_convert_record_to_nps_pages(struct ras_core_context *ras_core, + struct eeprom_umc_record *record, uint32_t nps, + uint64_t *page_pfn, uint32_t max_pages); #endif diff --git a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c index 5d9a11c17a864..b809a2f21d731 100644 --- a/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c +++ b/drivers/gpu/drm/amd/ras/rascore/ras_umc_v12_0.c @@ -373,6 +373,9 @@ static int umc_v12_0_bank_to_eeprom_record(struct ras_core_context *ras_core, ACA_ADDR_2_ERR_ADDR(bank->addr), ACA_IPID_2_UMC_INST(bank->ipid), &nps_addr, bank->nps, record); + if (ras_fw_eeprom_supported(ras_core) && bank->ts) + record->ts = bank->ts; + lookup_bad_pages_in_a_row(ras_core, record, bank->nps, NULL, 0, bank->seq_no, true); @@ -413,7 +416,7 @@ static int umc_v12_0_eeprom_record_to_nps_record(struct ras_core_context *ras_co uint64_t pa = 0; int ret = 0; - if (nps == EEPROM_RECORD_UMC_NPS_MODE(record)) { + if (nps == EEPROM_RECORD_UMC_NPS_MODE(record) && !ras_fw_eeprom_supported(ras_core)) { record->cur_nps_retired_row_pfn = EEPROM_RECORD_UMC_ADDR_PFN(record); } else { ret = convert_eeprom_record_to_nps_addr(ras_core, @@ -501,11 +504,25 @@ static int umc_12_0_bank_to_soc_pa(struct ras_core_context *ras_core, return 0; } +static void umc_v12_0_mca_ipid_parse(struct ras_core_context *ras_core, uint64_t ipid, + uint32_t *did, uint32_t *ch, uint32_t *umc_inst, uint32_t *sid) +{ + if (did) + *did = ACA_IPID_2_DIE_ID(ipid); + if (ch) + *ch = ACA_IPID_2_UMC_CH(ipid); + if (umc_inst) + *umc_inst = ACA_IPID_2_UMC_INST(ipid); + if (sid) + *sid = ACA_IPID_2_SOCKET_ID(ipid); +} + const struct ras_umc_ip_func ras_umc_func_v12_0 = { .bank_to_eeprom_record = umc_v12_0_bank_to_eeprom_record, .eeprom_record_to_nps_record = umc_v12_0_eeprom_record_to_nps_record, .eeprom_record_to_nps_pages = umc_v12_0_eeprom_record_to_nps_pages, .bank_to_soc_pa = umc_12_0_bank_to_soc_pa, .soc_pa_to_bank = umc_12_0_soc_pa_to_bank, + .mca_ipid_parse = umc_v12_0_mca_ipid_parse, }; diff --git a/drivers/gpu/drm/ast/ast_cursor.c b/drivers/gpu/drm/ast/ast_cursor.c index 2d3ad7610c2e9..3fa8e75db9c05 100644 --- a/drivers/gpu/drm/ast/ast_cursor.c +++ b/drivers/gpu/drm/ast/ast_cursor.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "ast_drv.h" @@ -92,12 +93,17 @@ static void ast_set_cursor_image(struct ast_device *ast, const u8 *src, unsigned int width, unsigned int height) { u8 __iomem *dst = ast_plane_vaddr(&ast->cursor_plane.base); - u32 csum; - - csum = ast_cursor_calculate_checksum(src, width, height); + u32 csum = ast_cursor_calculate_checksum(src, width, height); /* write pixel data */ +#if defined(__BIG_ENDIAN) + unsigned int i; + + for (i = 0; i < AST_HWC_SIZE; i += 2) + writew(swab16(*(const __u16 *)&src[i]), &dst[i]); +#else memcpy_toio(dst, src, AST_HWC_SIZE); +#endif /* write checksum + signature */ dst += AST_HWC_SIZE; @@ -181,6 +187,62 @@ static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, return 0; } +static const u8 *ast_cursor_plane_get_argb4444(struct ast_cursor_plane *ast_cursor_plane, + struct drm_shadow_plane_state *shadow_plane_state, + const struct drm_rect *clip) +{ + struct drm_plane_state *plane_state = &shadow_plane_state->base; + struct drm_framebuffer *fb = plane_state->fb; + u8 *argb4444 = NULL; + + if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE) == 0) { + switch (fb->format->format) { + case DRM_FORMAT_ARGB4444: + if (shadow_plane_state->data[0].is_iomem) { + struct iosys_map argb4444_dst[DRM_FORMAT_MAX_PLANES] = { + IOSYS_MAP_INIT_VADDR(ast_cursor_plane->argb4444), + }; + unsigned int argb4444_dst_pitch[DRM_FORMAT_MAX_PLANES] = { + AST_HWC_PITCH, + }; + + drm_fb_memcpy(argb4444_dst, argb4444_dst_pitch, + shadow_plane_state->data, fb, clip); + argb4444 = argb4444_dst[0].vaddr; + } else { + argb4444 = shadow_plane_state->data[0].vaddr; + } + break; + case DRM_FORMAT_ARGB8888: + { + struct iosys_map argb4444_dst[DRM_FORMAT_MAX_PLANES] = { + IOSYS_MAP_INIT_VADDR(ast_cursor_plane->argb4444), + }; + unsigned int argb4444_dst_pitch[DRM_FORMAT_MAX_PLANES] = { + AST_HWC_PITCH, + }; + + drm_fb_argb8888_to_argb4444(argb4444_dst, argb4444_dst_pitch, + shadow_plane_state->data, fb, clip, + &shadow_plane_state->fmtcnv_state); + argb4444 = argb4444_dst[0].vaddr; + } + break; + } + + drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); + } else { + /* + * Fall back to white square if GEM object is not ready. Gives + * the user an indication where the cursor is located. + */ + memset(ast_cursor_plane->argb4444, 0xff, sizeof(ast_cursor_plane->argb4444)); + argb4444 = ast_cursor_plane->argb4444; + } + + return argb4444; +} + static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -205,29 +267,13 @@ static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, */ if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) { - u8 *argb4444; + const u8 *argb4444 = ast_cursor_plane_get_argb4444(ast_cursor_plane, + shadow_plane_state, + &damage); - switch (fb->format->format) { - case DRM_FORMAT_ARGB4444: - argb4444 = shadow_plane_state->data[0].vaddr; - break; - default: - argb4444 = ast_cursor_plane->argb4444; - { - struct iosys_map argb4444_dst[DRM_FORMAT_MAX_PLANES] = { - IOSYS_MAP_INIT_VADDR(argb4444), - }; - unsigned int argb4444_dst_pitch[DRM_FORMAT_MAX_PLANES] = { - AST_HWC_PITCH, - }; + if (argb4444) + ast_set_cursor_image(ast, argb4444, fb->width, fb->height); - drm_fb_argb8888_to_argb4444(argb4444_dst, argb4444_dst_pitch, - shadow_plane_state->data, fb, &damage, - &shadow_plane_state->fmtcnv_state); - } - break; - } - ast_set_cursor_image(ast, argb4444, fb->width, fb->height); ast_set_cursor_base(ast, dst_off); } diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c index cd08990a10f93..57c6fbc3232b0 100644 --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c @@ -526,12 +526,18 @@ static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, static void ast_handle_damage(struct ast_plane *ast_plane, struct iosys_map *src, struct drm_framebuffer *fb, - const struct drm_rect *clip) + const struct drm_rect *clip, + struct drm_format_conv_state *fmtcnv_state) { struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(ast_plane_vaddr(ast_plane)); iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip)); + +#if defined(__BIG_ENDIAN) + drm_fb_swab(&dst, fb->pitches, src, fb, clip, !src[0].is_iomem, fmtcnv_state); +#else drm_fb_memcpy(&dst, fb->pitches, src, fb, clip); +#endif } static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, @@ -561,7 +567,8 @@ static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, if (drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE) == 0) { drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); drm_atomic_for_each_plane_damage(&iter, &damage) { - ast_handle_damage(ast_plane, shadow_plane_state->data, fb, &damage); + ast_handle_damage(ast_plane, shadow_plane_state->data, fb, &damage, + &shadow_plane_state->fmtcnv_state); } drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index e0efc7309b1b2..b075f291847f9 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -509,14 +509,6 @@ static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = { .atomic_disable = atmel_hlcdc_crtc_atomic_disable, }; -static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c) -{ - struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); - - drm_crtc_cleanup(c); - kfree(crtc); -} - static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc) { struct drm_device *dev = crtc->base.dev; @@ -607,7 +599,6 @@ static void atmel_hlcdc_crtc_disable_vblank(struct drm_crtc *c) static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = { .page_flip = drm_atomic_helper_page_flip, .set_config = drm_atomic_helper_set_config, - .destroy = atmel_hlcdc_crtc_destroy, .reset = atmel_hlcdc_crtc_reset, .atomic_duplicate_state = atmel_hlcdc_crtc_duplicate_state, .atomic_destroy_state = atmel_hlcdc_crtc_destroy_state, @@ -620,15 +611,8 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) struct atmel_hlcdc_plane *primary = NULL, *cursor = NULL; struct atmel_hlcdc_dc *dc = dev->dev_private; struct atmel_hlcdc_crtc *crtc; - int ret; int i; - crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); - if (!crtc) - return -ENOMEM; - - crtc->dc = dc; - for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) { if (!dc->layers[i]) continue; @@ -646,13 +630,13 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) break; } } + crtc = drmm_crtc_alloc_with_planes(dev, struct atmel_hlcdc_crtc, base, + &primary->base, &cursor->base, &atmel_hlcdc_crtc_funcs, + NULL); + if (IS_ERR(crtc)) + return PTR_ERR(crtc); - ret = drm_crtc_init_with_planes(dev, &crtc->base, &primary->base, - &cursor->base, &atmel_hlcdc_crtc_funcs, - NULL); - if (ret < 0) - goto fail; - + crtc->dc = dc; crtc->id = drm_crtc_index(&crtc->base); for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) { @@ -674,8 +658,4 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev) dc->crtc = &crtc->base; return 0; - -fail: - atmel_hlcdc_crtc_destroy(&crtc->base); - return ret; } diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index dd70894c8f38e..d1f5451ebfeaf 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -723,12 +723,6 @@ static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) drm_mode_config_init(dev); - ret = atmel_hlcdc_create_outputs(dev); - if (ret) { - drm_err(dev, "failed to create HLCDC outputs: %d\n", ret); - return ret; - } - ret = atmel_hlcdc_create_planes(dev); if (ret) { drm_err(dev, "failed to create planes: %d\n", ret); @@ -741,6 +735,12 @@ static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) return ret; } + ret = atmel_hlcdc_create_outputs(dev); + if (ret) { + drm_err(dev, "failed to create HLCDC outputs: %d\n", ret); + return ret; + } + dev->mode_config.min_width = dc->desc->min_width; dev->mode_config.min_height = dc->desc->min_height; dev->mode_config.max_width = dc->desc->max_width; @@ -751,11 +751,16 @@ static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev) return 0; } +static struct atmel_hlcdc_dc *atmel_hlcdc_dc_of_dev(struct drm_device *dev) +{ + return container_of(dev, struct atmel_hlcdc_dc, dev); +} + static int atmel_hlcdc_dc_load(struct drm_device *dev) { struct platform_device *pdev = to_platform_device(dev->dev); const struct of_device_id *match; - struct atmel_hlcdc_dc *dc; + struct atmel_hlcdc_dc *dc = atmel_hlcdc_dc_of_dev(dev); int ret; match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node); @@ -769,10 +774,6 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev) return -EINVAL; } - dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL); - if (!dc) - return -ENOMEM; - dc->desc = match->data; dc->hlcdc = dev_get_drvdata(dev->dev->parent); dev->dev_private = dc; @@ -853,16 +854,21 @@ static const struct drm_driver atmel_hlcdc_dc_driver = { static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev) { + struct atmel_hlcdc_dc *dc; struct drm_device *ddev; int ret; - ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev); - if (IS_ERR(ddev)) - return PTR_ERR(ddev); + if (drm_firmware_drivers_only()) + return -ENODEV; + + dc = devm_drm_dev_alloc(&pdev->dev, &atmel_hlcdc_dc_driver, struct atmel_hlcdc_dc, dev); + if (IS_ERR(dc)) + return PTR_ERR(dc); + ddev = &dc->dev; ret = atmel_hlcdc_dc_load(ddev); if (ret) - goto err_put; + return ret; ret = drm_dev_register(ddev, 0); if (ret) @@ -875,9 +881,6 @@ static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev) err_unload: atmel_hlcdc_dc_unload(ddev); -err_put: - drm_dev_put(ddev); - return ret; } @@ -887,7 +890,6 @@ static void atmel_hlcdc_dc_drm_remove(struct platform_device *pdev) drm_dev_unregister(ddev); atmel_hlcdc_dc_unload(ddev); - drm_dev_put(ddev); } static void atmel_hlcdc_dc_drm_shutdown(struct platform_device *pdev) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 53d47f01db0bd..26b26185cf34a 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -350,6 +350,7 @@ struct atmel_hlcdc_dc { struct dma_pool *dscrpool; struct atmel_hlcdc *hlcdc; struct drm_crtc *crtc; + struct drm_device dev; struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; struct { u32 imr; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c index 0b8a86afb0965..e8aea905fb10d 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_output.c @@ -69,27 +69,24 @@ static int atmel_hlcdc_attach_endpoint(struct drm_device *dev, int endpoint) { struct atmel_hlcdc_rgb_output *output; struct device_node *ep; - struct drm_panel *panel; struct drm_bridge *bridge; - int ret; + struct atmel_hlcdc_dc *dc = dev->dev_private; + struct drm_crtc *crtc = dc->crtc; + int ret = 0; + + bridge = devm_drm_of_get_bridge(dev->dev, dev->dev->of_node, 0, endpoint); + if (IS_ERR(bridge)) + return PTR_ERR(bridge); + + output = drmm_simple_encoder_alloc(dev, struct atmel_hlcdc_rgb_output, + encoder, DRM_MODE_ENCODER_NONE); + if (IS_ERR(output)) + return PTR_ERR(output); ep = of_graph_get_endpoint_by_regs(dev->dev->of_node, 0, endpoint); if (!ep) return -ENODEV; - ret = drm_of_find_panel_or_bridge(dev->dev->of_node, 0, endpoint, - &panel, &bridge); - if (ret) { - of_node_put(ep); - return ret; - } - - output = devm_kzalloc(dev->dev, sizeof(*output), GFP_KERNEL); - if (!output) { - of_node_put(ep); - return -ENOMEM; - } - output->bus_fmt = atmel_hlcdc_of_bus_fmt(ep); of_node_put(ep); if (output->bus_fmt < 0) { @@ -97,30 +94,11 @@ static int atmel_hlcdc_attach_endpoint(struct drm_device *dev, int endpoint) return -EINVAL; } - ret = drm_simple_encoder_init(dev, &output->encoder, - DRM_MODE_ENCODER_NONE); - if (ret) - return ret; - output->encoder.possible_crtcs = 0x1; - - if (panel) { - bridge = drm_panel_bridge_add_typed(panel, - DRM_MODE_CONNECTOR_Unknown); - if (IS_ERR(bridge)) - return PTR_ERR(bridge); - } + output->encoder.possible_crtcs = drm_crtc_mask(crtc); - if (bridge) { + if (bridge) ret = drm_bridge_attach(&output->encoder, bridge, NULL, 0); - if (!ret) - return 0; - - if (panel) - drm_panel_bridge_remove(bridge); - } - - drm_encoder_cleanup(&output->encoder); return ret; } diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index 92132be9823f1..c52da47982ee5 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -79,8 +79,6 @@ drm_plane_state_to_atmel_hlcdc_plane_state(struct drm_plane_state *s) return container_of(s, struct atmel_hlcdc_plane_state, base); } -#define SUBPIXEL_MASK 0xffff - static uint32_t rgb_formats[] = { DRM_FORMAT_C8, DRM_FORMAT_XRGB4444, @@ -745,24 +743,15 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, if (ret || !s->visible) return ret; - hstate->src_x = s->src.x1; - hstate->src_y = s->src.y1; - hstate->src_w = drm_rect_width(&s->src); - hstate->src_h = drm_rect_height(&s->src); + hstate->src_x = s->src.x1 >> 16; + hstate->src_y = s->src.y1 >> 16; + hstate->src_w = drm_rect_width(&s->src) >> 16; + hstate->src_h = drm_rect_height(&s->src) >> 16; hstate->crtc_x = s->dst.x1; hstate->crtc_y = s->dst.y1; hstate->crtc_w = drm_rect_width(&s->dst); hstate->crtc_h = drm_rect_height(&s->dst); - if ((hstate->src_x | hstate->src_y | hstate->src_w | hstate->src_h) & - SUBPIXEL_MASK) - return -EINVAL; - - hstate->src_x >>= 16; - hstate->src_y >>= 16; - hstate->src_w >>= 16; - hstate->src_h >>= 16; - hstate->nplanes = fb->format->num_planes; if (hstate->nplanes > ATMEL_HLCDC_LAYER_MAX_PLANES) return -EINVAL; @@ -1155,32 +1144,6 @@ static int atmel_hlcdc_plane_alloc_dscrs(struct drm_plane *p, return -ENOMEM; } -static void atmel_hlcdc_plane_reset(struct drm_plane *p) -{ - struct atmel_hlcdc_plane_state *state; - - if (p->state) { - state = drm_plane_state_to_atmel_hlcdc_plane_state(p->state); - - if (state->base.fb) - drm_framebuffer_put(state->base.fb); - - kfree(state); - p->state = NULL; - } - - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state) { - if (atmel_hlcdc_plane_alloc_dscrs(p, state)) { - kfree(state); - drm_err(p->dev, - "Failed to allocate initial plane state\n"); - return; - } - __drm_atomic_helper_plane_reset(p, &state->base); - } -} - static struct drm_plane_state * atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p) { @@ -1197,8 +1160,7 @@ atmel_hlcdc_plane_atomic_duplicate_state(struct drm_plane *p) return NULL; } - if (copy->base.fb) - drm_framebuffer_get(copy->base.fb); + __drm_atomic_helper_plane_duplicate_state(p, ©->base); return ©->base; } @@ -1216,16 +1178,40 @@ static void atmel_hlcdc_plane_atomic_destroy_state(struct drm_plane *p, state->dscrs[i]->self); } - if (s->fb) - drm_framebuffer_put(s->fb); + __drm_atomic_helper_plane_destroy_state(s); kfree(state); } +static void atmel_hlcdc_plane_reset(struct drm_plane *p) +{ + struct atmel_hlcdc_plane_state *state; + struct atmel_hlcdc_dc *dc = p->dev->dev_private; + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); + + if (p->state) { + atmel_hlcdc_plane_atomic_destroy_state(p, p->state); + p->state = NULL; + } + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state) { + if (atmel_hlcdc_plane_alloc_dscrs(p, state)) { + kfree(state); + drm_err(p->dev, + "Failed to allocate initial plane state\n"); + return; + } + __drm_atomic_helper_plane_reset(p, &state->base); + } + + if (plane->layer.desc->layout.csc) + dc->desc->ops->lcdc_csc_init(plane, plane->layer.desc); +} + static const struct drm_plane_funcs layer_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, - .destroy = drm_plane_cleanup, .reset = atmel_hlcdc_plane_reset, .atomic_duplicate_state = atmel_hlcdc_plane_atomic_duplicate_state, .atomic_destroy_state = atmel_hlcdc_plane_atomic_destroy_state, @@ -1239,12 +1225,6 @@ static int atmel_hlcdc_plane_create(struct drm_device *dev, enum drm_plane_type type; int ret; - plane = devm_kzalloc(dev->dev, sizeof(*plane), GFP_KERNEL); - if (!plane) - return -ENOMEM; - - atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap); - if (desc->type == ATMEL_HLCDC_BASE_LAYER) type = DRM_PLANE_TYPE_PRIMARY; else if (desc->type == ATMEL_HLCDC_CURSOR_LAYER) @@ -1252,13 +1232,13 @@ static int atmel_hlcdc_plane_create(struct drm_device *dev, else type = DRM_PLANE_TYPE_OVERLAY; - ret = drm_universal_plane_init(dev, &plane->base, 0, - &layer_plane_funcs, - desc->formats->formats, - desc->formats->nformats, - NULL, type, NULL); - if (ret) - return ret; + plane = drmm_universal_plane_alloc(dev, struct atmel_hlcdc_plane, base, 0, + &layer_plane_funcs, desc->formats->formats, + desc->formats->nformats, NULL, type, NULL); + if (IS_ERR(plane)) + return PTR_ERR(plane); + + atmel_hlcdc_layer_init(&plane->layer, desc, dc->hlcdc->regmap); drm_plane_helper_add(&plane->base, &atmel_hlcdc_layer_plane_helper_funcs); diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index a250afd8d6622..39385deafc68e 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -100,6 +100,13 @@ config DRM_I2C_NXP_TDA998X help Support for NXP Semiconductors TDA998X HDMI encoders. +config DRM_INNO_HDMI + tristate + select DRM_BRIDGE_CONNECTOR + select DRM_DISPLAY_HDMI_HELPER + select DRM_DISPLAY_HELPER + select DRM_KMS_HELPER + config DRM_ITE_IT6263 tristate "ITE IT6263 LVDS/HDMI bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index c7dc03182e592..909c21cc3acd3 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o tda998x-y := tda998x_drv.o obj-$(CONFIG_DRM_I2C_NXP_TDA998X) += tda998x.o +obj-$(CONFIG_DRM_INNO_HDMI) += inno-hdmi.o obj-$(CONFIG_DRM_ITE_IT6263) += ite-it6263.o obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index b9be865413075..1050bb62280bb 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -887,88 +887,111 @@ static const struct drm_edid *adv7511_bridge_edid_read(struct drm_bridge *bridge return adv7511_edid_read(adv, connector); } -static int adv7511_bridge_hdmi_clear_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type) +static int adv7511_bridge_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) { struct adv7511 *adv7511 = bridge_to_adv7511(bridge); - switch (type) { - case HDMI_INFOFRAME_TYPE_AUDIO: - adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME); - break; - case HDMI_INFOFRAME_TYPE_AVI: - adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME); - break; - case HDMI_INFOFRAME_TYPE_SPD: - adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPD); - break; - case HDMI_INFOFRAME_TYPE_VENDOR: - adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPARE1); - break; - default: - drm_dbg_driver(adv7511->bridge.dev, "Unsupported HDMI InfoFrame %x\n", type); - break; - } + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME); return 0; } -static int adv7511_bridge_hdmi_write_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) +static int adv7511_bridge_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) { struct adv7511 *adv7511 = bridge_to_adv7511(bridge); - switch (type) { - case HDMI_INFOFRAME_TYPE_AUDIO: - /* send current Audio infoframe values while updating */ - regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, - BIT(5), BIT(5)); - - /* The Audio infoframe id is not configurable */ - regmap_bulk_write(adv7511->regmap, ADV7511_REG_AUDIO_INFOFRAME_VERSION, - buffer + 1, len - 1); - - /* use Audio infoframe updated info */ - regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, - BIT(5), 0); - - adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME); - break; - case HDMI_INFOFRAME_TYPE_AVI: - /* send current AVI infoframe values while updating */ - regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, - BIT(6), BIT(6)); - - /* The AVI infoframe id is not configurable */ - regmap_bulk_write(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME_VERSION, - buffer + 1, len - 1); - - regmap_write(adv7511->regmap, ADV7511_REG_AUDIO_INFOFRAME_LENGTH, 0x2); - regmap_write(adv7511->regmap, ADV7511_REG_AUDIO_INFOFRAME(1), 0x1); - - /* use AVI infoframe updated info */ - regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, - BIT(6), 0); - - adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME); - break; - case HDMI_INFOFRAME_TYPE_SPD: - adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPD); - regmap_bulk_write(adv7511->regmap_packet, ADV7511_PACKET_SPD(0), - buffer, len); - adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_SPD); - break; - case HDMI_INFOFRAME_TYPE_VENDOR: - adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPARE1); - regmap_bulk_write(adv7511->regmap_packet, ADV7511_PACKET_SPARE1(0), - buffer, len); - adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_SPARE1); - break; - default: - drm_dbg_driver(adv7511->bridge.dev, "Unsupported HDMI InfoFrame %x\n", type); - break; - } + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME); + + return 0; +} + +static int adv7511_bridge_hdmi_clear_spd_infoframe(struct drm_bridge *bridge) +{ + struct adv7511 *adv7511 = bridge_to_adv7511(bridge); + + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPD); + + return 0; +} + +static int adv7511_bridge_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + struct adv7511 *adv7511 = bridge_to_adv7511(bridge); + + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPARE1); + + return 0; +} + +static int adv7511_bridge_hdmi_write_audio_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct adv7511 *adv7511 = bridge_to_adv7511(bridge); + + /* send current Audio infoframe values while updating */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, + BIT(5), BIT(5)); + + /* The Audio infoframe id is not configurable */ + regmap_bulk_write(adv7511->regmap, ADV7511_REG_AUDIO_INFOFRAME_VERSION, + buffer + 1, len - 1); + + /* use Audio infoframe updated info */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, + BIT(5), 0); + + adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AUDIO_INFOFRAME); + + return 0; +} + +static int adv7511_bridge_hdmi_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct adv7511 *adv7511 = bridge_to_adv7511(bridge); + + /* send current AVI infoframe values while updating */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, + BIT(6), BIT(6)); + + /* The AVI infoframe id is not configurable */ + regmap_bulk_write(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME_VERSION, + buffer + 1, len - 1); + + regmap_write(adv7511->regmap, ADV7511_REG_AUDIO_INFOFRAME_LENGTH, 0x2); + regmap_write(adv7511->regmap, ADV7511_REG_AUDIO_INFOFRAME(1), 0x1); + + /* use AVI infoframe updated info */ + regmap_update_bits(adv7511->regmap, ADV7511_REG_INFOFRAME_UPDATE, + BIT(6), 0); + + adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME); + + return 0; +} + +static int adv7511_bridge_hdmi_write_spd_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct adv7511 *adv7511 = bridge_to_adv7511(bridge); + + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPD); + regmap_bulk_write(adv7511->regmap_packet, ADV7511_PACKET_SPD(0), + buffer, len); + adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_SPD); + + return 0; +} + +static int adv7511_bridge_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct adv7511 *adv7511 = bridge_to_adv7511(bridge); + + adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_SPARE1); + regmap_bulk_write(adv7511->regmap_packet, ADV7511_PACKET_SPARE1(0), + buffer, len); + adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_SPARE1); return 0; } @@ -986,8 +1009,14 @@ static const struct drm_bridge_funcs adv7511_bridge_funcs = { .atomic_reset = drm_atomic_helper_bridge_reset, .hdmi_tmds_char_rate_valid = adv7511_bridge_hdmi_tmds_char_rate_valid, - .hdmi_clear_infoframe = adv7511_bridge_hdmi_clear_infoframe, - .hdmi_write_infoframe = adv7511_bridge_hdmi_write_infoframe, + .hdmi_clear_audio_infoframe = adv7511_bridge_hdmi_clear_audio_infoframe, + .hdmi_write_audio_infoframe = adv7511_bridge_hdmi_write_audio_infoframe, + .hdmi_clear_avi_infoframe = adv7511_bridge_hdmi_clear_avi_infoframe, + .hdmi_write_avi_infoframe = adv7511_bridge_hdmi_write_avi_infoframe, + .hdmi_clear_spd_infoframe = adv7511_bridge_hdmi_clear_spd_infoframe, + .hdmi_write_spd_infoframe = adv7511_bridge_hdmi_write_spd_infoframe, + .hdmi_clear_hdmi_infoframe = adv7511_bridge_hdmi_clear_hdmi_infoframe, + .hdmi_write_hdmi_infoframe = adv7511_bridge_hdmi_write_hdmi_infoframe, .hdmi_audio_startup = adv7511_hdmi_audio_startup, .hdmi_audio_prepare = adv7511_hdmi_audio_prepare, @@ -1322,7 +1351,8 @@ static int adv7511_probe(struct i2c_client *i2c) adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | - DRM_BRIDGE_OP_HDMI; + DRM_BRIDGE_OP_HDMI | + DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME; if (adv7511->i2c_main->irq) adv7511->bridge.ops |= DRM_BRIDGE_OP_HPD; diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 6f3fdcb6afdb9..4e49e4f28d552 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -1801,7 +1801,7 @@ static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx) return NULL; } - ctx->cached_drm_edid = drm_edid_alloc(edid_buf, FOUR_BLOCK_SIZE); + ctx->cached_drm_edid = drm_edid_alloc(edid_buf, edid_num * ONE_BLOCK_SIZE); kfree(edid_buf); out: diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c index 3a6f8587a257c..15fbb1be07cdf 100644 --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c @@ -29,7 +29,6 @@ struct imx8mp_hdmi_pvi { struct drm_bridge bridge; struct device *dev; - struct drm_bridge *next_bridge; void __iomem *regs; }; @@ -45,7 +44,7 @@ static int imx8mp_hdmi_pvi_bridge_attach(struct drm_bridge *bridge, { struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); - return drm_bridge_attach(encoder, pvi->next_bridge, + return drm_bridge_attach(encoder, pvi->bridge.next_bridge, bridge, flags); } @@ -78,8 +77,8 @@ static void imx8mp_hdmi_pvi_bridge_enable(struct drm_bridge *bridge, if (mode->flags & DRM_MODE_FLAG_PHSYNC) val |= PVI_CTRL_OP_HSYNC_POL | PVI_CTRL_INP_HSYNC_POL; - if (pvi->next_bridge->timings) - bus_flags = pvi->next_bridge->timings->input_bus_flags; + if (pvi->bridge.next_bridge->timings) + bus_flags = pvi->bridge.next_bridge->timings->input_bus_flags; else if (bridge_state) bus_flags = bridge_state->input_bus_cfg.flags; @@ -108,7 +107,7 @@ imx8mp_hdmi_pvi_bridge_get_input_bus_fmts(struct drm_bridge *bridge, unsigned int *num_input_fmts) { struct imx8mp_hdmi_pvi *pvi = to_imx8mp_hdmi_pvi(bridge); - struct drm_bridge *next_bridge = pvi->next_bridge; + struct drm_bridge *next_bridge = pvi->bridge.next_bridge; struct drm_bridge_state *next_state; if (!next_bridge->funcs->atomic_get_input_bus_fmts) @@ -157,10 +156,10 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev) if (!remote) return -EINVAL; - pvi->next_bridge = of_drm_find_bridge(remote); + pvi->bridge.next_bridge = of_drm_find_and_get_bridge(remote); of_node_put(remote); - if (!pvi->next_bridge) + if (!pvi->bridge.next_bridge) return dev_err_probe(&pdev->dev, -EPROBE_DEFER, "could not find next bridge\n"); @@ -168,7 +167,7 @@ static int imx8mp_hdmi_pvi_probe(struct platform_device *pdev) /* Register the bridge. */ pvi->bridge.of_node = pdev->dev.of_node; - pvi->bridge.timings = pvi->next_bridge->timings; + pvi->bridge.timings = pvi->bridge.next_bridge->timings; drm_bridge_add(&pvi->bridge); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c index 1225029689271..f27ca5f08ce0a 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-ldb.c @@ -62,6 +62,18 @@ static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) return container_of(base, struct imx8qxp_ldb, base); } +static void imx8qxp_ldb_bridge_destroy(struct drm_bridge *bridge) +{ + struct ldb_channel *ldb_ch = bridge->driver_private; + struct imx8qxp_ldb *imx8qxp_ldb; + + if (!ldb_ch) + return; + + imx8qxp_ldb = base_to_imx8qxp_ldb(ldb_ch->ldb); + drm_bridge_put(imx8qxp_ldb->companion); +} + static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb, unsigned long di_clk, bool is_split, struct phy_configure_opts_lvds *phy_cfg) @@ -391,6 +403,7 @@ imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge, } static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = { + .destroy = imx8qxp_ldb_bridge_destroy, .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, @@ -552,7 +565,7 @@ static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) goto out; } - imx8qxp_ldb->companion = of_drm_find_bridge(companion_port); + imx8qxp_ldb->companion = of_drm_find_and_get_bridge(companion_port); if (!imx8qxp_ldb->companion) { ret = -EPROBE_DEFER; DRM_DEV_DEBUG_DRIVER(dev, diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c index 8517b1c953d4e..74eda8b540236 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-combiner.c @@ -60,7 +60,6 @@ enum imx8qxp_pc_pix_data_format { struct imx8qxp_pc_channel { struct drm_bridge bridge; - struct drm_bridge *next_bridge; struct imx8qxp_pc *pc; unsigned int stream_id; }; @@ -120,7 +119,7 @@ static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge, } return drm_bridge_attach(encoder, - ch->next_bridge, bridge, + ch->bridge.next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); } @@ -326,8 +325,8 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev) goto free_child; } - ch->next_bridge = of_drm_find_bridge(remote); - if (!ch->next_bridge) { + ch->bridge.next_bridge = of_drm_find_and_get_bridge(remote); + if (!ch->bridge.next_bridge) { of_node_put(remote); ret = -EPROBE_DEFER; DRM_DEV_DEBUG_DRIVER(dev, @@ -349,7 +348,7 @@ static int imx8qxp_pc_bridge_probe(struct platform_device *pdev) free_child: of_node_put(child); - if (i == 1 && pc->ch[0]->next_bridge) + if (i == 1 && pc->ch[0]->bridge.next_bridge) drm_bridge_remove(&pc->ch[0]->bridge); pm_runtime_disable(dev); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c index e5943506981df..433c080197a22 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -374,13 +374,8 @@ static int imx8qxp_pixel_link_bridge_probe(struct platform_device *pdev) return ret; pl->next_bridge = imx8qxp_pixel_link_find_next_bridge(pl); - if (IS_ERR(pl->next_bridge)) { - ret = PTR_ERR(pl->next_bridge); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", - ret); - return ret; - } + if (IS_ERR(pl->next_bridge)) + return PTR_ERR(pl->next_bridge); platform_set_drvdata(pdev, pl); diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c index 111310acab2ce..d5de39b5710ba 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pxl2dpi.c @@ -35,7 +35,6 @@ struct imx8qxp_pxl2dpi { struct regmap *regmap; struct drm_bridge bridge; - struct drm_bridge *next_bridge; struct drm_bridge *companion; struct device *dev; struct imx_sc_ipc *ipc_handle; @@ -60,10 +59,20 @@ static int imx8qxp_pxl2dpi_bridge_attach(struct drm_bridge *bridge, } return drm_bridge_attach(encoder, - p2d->next_bridge, bridge, + p2d->bridge.next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); } +static void imx8qxp_pxl2dpi_bridge_destroy(struct drm_bridge *bridge) +{ + struct imx8qxp_pxl2dpi *p2d = bridge->driver_private; + + if (!p2d) + return; + + drm_bridge_put(p2d->companion); +} + static int imx8qxp_pxl2dpi_bridge_atomic_check(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, @@ -206,6 +215,7 @@ static const struct drm_bridge_funcs imx8qxp_pxl2dpi_bridge_funcs = { .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, .attach = imx8qxp_pxl2dpi_bridge_attach, + .destroy = imx8qxp_pxl2dpi_bridge_destroy, .atomic_check = imx8qxp_pxl2dpi_bridge_atomic_check, .mode_set = imx8qxp_pxl2dpi_bridge_mode_set, .atomic_disable = imx8qxp_pxl2dpi_bridge_atomic_disable, @@ -255,40 +265,27 @@ imx8qxp_pxl2dpi_get_available_ep_from_port(struct imx8qxp_pxl2dpi *p2d, return ep; } -static struct drm_bridge * -imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d) +static int imx8qxp_pxl2dpi_find_next_bridge(struct imx8qxp_pxl2dpi *p2d) { - struct device_node *ep, *remote; - struct drm_bridge *next_bridge; - int ret; - - ep = imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1); - if (IS_ERR(ep)) { - ret = PTR_ERR(ep); - return ERR_PTR(ret); - } + struct device_node *ep __free(device_node) = + imx8qxp_pxl2dpi_get_available_ep_from_port(p2d, 1); + if (IS_ERR(ep)) + return PTR_ERR(ep); - remote = of_graph_get_remote_port_parent(ep); + struct device_node *remote __free(device_node) = of_graph_get_remote_port_parent(ep); if (!remote || !of_device_is_available(remote)) { DRM_DEV_ERROR(p2d->dev, "no available remote\n"); - next_bridge = ERR_PTR(-ENODEV); - goto out; + return -ENODEV; } else if (!of_device_is_available(remote->parent)) { DRM_DEV_ERROR(p2d->dev, "remote parent is not available\n"); - next_bridge = ERR_PTR(-ENODEV); - goto out; + return -ENODEV; } - next_bridge = of_drm_find_bridge(remote); - if (!next_bridge) { - next_bridge = ERR_PTR(-EPROBE_DEFER); - goto out; - } -out: - of_node_put(remote); - of_node_put(ep); + p2d->bridge.next_bridge = of_drm_find_and_get_bridge(remote); + if (!p2d->bridge.next_bridge) + return -EPROBE_DEFER; - return next_bridge; + return 0; } static int imx8qxp_pxl2dpi_set_pixel_link_sel(struct imx8qxp_pxl2dpi *p2d) @@ -347,7 +344,7 @@ static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d) goto out; } - p2d->companion = of_drm_find_bridge(companion); + p2d->companion = of_drm_find_and_get_bridge(companion); if (!p2d->companion) { ret = -EPROBE_DEFER; DRM_DEV_DEBUG_DRIVER(p2d->dev, @@ -364,8 +361,8 @@ static int imx8qxp_pxl2dpi_parse_dt_companion(struct imx8qxp_pxl2dpi *p2d) * the next bridges are connected to. If they are marked as expecting * even pixels and odd pixels than we need to use the companion PXL2DPI. */ - port1 = of_graph_get_port_by_id(p2d->next_bridge->of_node, 1); - port2 = of_graph_get_port_by_id(companion_p2d->next_bridge->of_node, 1); + port1 = of_graph_get_port_by_id(p2d->bridge.next_bridge->of_node, 1); + port2 = of_graph_get_port_by_id(companion_p2d->bridge.next_bridge->of_node, 1); dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); of_node_put(port1); of_node_put(port2); @@ -421,14 +418,9 @@ static int imx8qxp_pxl2dpi_bridge_probe(struct platform_device *pdev) return ret; } - p2d->next_bridge = imx8qxp_pxl2dpi_find_next_bridge(p2d); - if (IS_ERR(p2d->next_bridge)) { - ret = PTR_ERR(p2d->next_bridge); - if (ret != -EPROBE_DEFER) - DRM_DEV_ERROR(dev, "failed to find next bridge: %d\n", - ret); + ret = imx8qxp_pxl2dpi_find_next_bridge(p2d); + if (ret) return ret; - } ret = imx8qxp_pxl2dpi_set_pixel_link_sel(p2d); if (ret) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/bridge/inno-hdmi.c similarity index 69% rename from drivers/gpu/drm/rockchip/inno_hdmi.c rename to drivers/gpu/drm/bridge/inno-hdmi.c index 9f7a8cf0ab444..a26b99b101c4a 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/bridge/inno-hdmi.c @@ -3,14 +3,15 @@ * Copyright (C) Rockchip Electronics Co., Ltd. * Zheng Yang * Yakir Yang + * Andy Yan */ #include #include #include #include +#include #include -#include #include #include #include @@ -18,6 +19,7 @@ #include #include +#include #include #include #include @@ -29,8 +31,6 @@ #include #include -#include "rockchip_drm_drv.h" - #define INNO_HDMI_MIN_TMDS_CLOCK 25000000U #define DDC_SEGMENT_ADDR 0x30 @@ -384,27 +384,6 @@ enum { #define HDMI_CEC_BUSFREETIME_H 0xdd #define HDMI_CEC_LOGICADDR 0xde -#define RK3036_GRF_SOC_CON2 0x148 -#define RK3036_HDMI_PHSYNC BIT(4) -#define RK3036_HDMI_PVSYNC BIT(5) - -enum inno_hdmi_dev_type { - RK3036_HDMI, - RK3128_HDMI, -}; - -struct inno_hdmi_phy_config { - unsigned long pixelclock; - u8 pre_emphasis; - u8 voltage_level_control; -}; - -struct inno_hdmi_variant { - enum inno_hdmi_dev_type dev_type; - struct inno_hdmi_phy_config *phy_configs; - struct inno_hdmi_phy_config *default_phy_config; -}; - struct inno_hdmi_i2c { struct i2c_adapter adap; @@ -417,41 +396,17 @@ struct inno_hdmi_i2c { struct inno_hdmi { struct device *dev; - + struct drm_bridge bridge; struct clk *pclk; struct clk *refclk; void __iomem *regs; struct regmap *grf; - struct drm_connector connector; - struct rockchip_encoder encoder; - struct inno_hdmi_i2c *i2c; struct i2c_adapter *ddc; - - const struct inno_hdmi_variant *variant; -}; - -struct inno_hdmi_connector_state { - struct drm_connector_state base; - unsigned int colorimetry; + const struct inno_hdmi_plat_data *plat_data; }; -static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder) -{ - struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - - return container_of(rkencoder, struct inno_hdmi, encoder); -} - -static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector) -{ - return container_of(connector, struct inno_hdmi, connector); -} - -#define to_inno_hdmi_conn_state(conn_state) \ - container_of_const(conn_state, struct inno_hdmi_connector_state, base) - enum { CSC_RGB_0_255_TO_ITU601_16_235_8BIT, CSC_RGB_0_255_TO_ITU709_16_235_8BIT, @@ -494,23 +449,15 @@ static const char coeff_csc[][24] = { }, }; -static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = { - { 74250000, 0x3f, 0xbb }, - { 165000000, 0x6f, 0xbb }, - { ~0UL, 0x00, 0x00 } -}; - -static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = { - { 74250000, 0x3f, 0xaa }, - { 165000000, 0x5f, 0xaa }, - { ~0UL, 0x00, 0x00 } -}; +static struct inno_hdmi *bridge_to_inno_hdmi(struct drm_bridge *bridge) +{ + return container_of(bridge, struct inno_hdmi, bridge); +} static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi, unsigned long pixelclk) { - const struct inno_hdmi_phy_config *phy_configs = - hdmi->variant->phy_configs; + const struct inno_hdmi_phy_config *phy_configs = hdmi->plat_data->phy_configs; int i; for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) { @@ -582,12 +529,12 @@ static void inno_hdmi_power_up(struct inno_hdmi *hdmi, int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock); if (ret < 0) { - phy_config = hdmi->variant->default_phy_config; + phy_config = hdmi->plat_data->default_phy_config; DRM_DEV_ERROR(hdmi->dev, "Using default phy configuration for TMDS rate %lu", mpixelclock); } else { - phy_config = &hdmi->variant->phy_configs[ret]; + phy_config = &hdmi->plat_data->phy_configs[ret]; } inno_hdmi_sys_power(hdmi, false); @@ -637,36 +584,22 @@ static void inno_hdmi_init_hw(struct inno_hdmi *hdmi) hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); } -static int inno_hdmi_disable_frame(struct drm_connector *connector, - enum hdmi_infoframe_type type) +static int inno_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge) { - struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - - if (type != HDMI_INFOFRAME_TYPE_AVI) { - drm_err(connector->dev, - "Unsupported infoframe type: %u\n", type); - return 0; - } + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI); return 0; } -static int inno_hdmi_upload_frame(struct drm_connector *connector, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) +static int inno_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) { - struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); ssize_t i; - if (type != HDMI_INFOFRAME_TYPE_AVI) { - drm_err(connector->dev, - "Unsupported infoframe type: %u\n", type); - return 0; - } - - inno_hdmi_disable_frame(connector, type); + inno_hdmi_bridge_clear_avi_infoframe(bridge); for (i = 0; i < len; i++) hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, buffer[i]); @@ -674,23 +607,41 @@ static int inno_hdmi_upload_frame(struct drm_connector *connector, return 0; } -static const struct drm_connector_hdmi_funcs inno_hdmi_hdmi_connector_funcs = { - .clear_infoframe = inno_hdmi_disable_frame, - .write_infoframe = inno_hdmi_upload_frame, -}; +static int inno_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + drm_warn_once(bridge->encoder->dev, "HDMI VSI not implemented\n"); -static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) + return 0; +} + +static int inno_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + drm_warn_once(bridge->encoder->dev, "HDMI VSI not implemented\n"); + + return 0; +} + +static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi, + struct drm_connector *connector, + struct drm_display_mode *mode) { - struct drm_connector *connector = &hdmi->connector; struct drm_connector_state *conn_state = connector->state; - struct inno_hdmi_connector_state *inno_conn_state = - to_inno_hdmi_conn_state(conn_state); int c0_c2_change = 0; int csc_enable = 0; int csc_mode = 0; int auto_csc = 0; int value; int i; + int colorimetry; + u8 vic = drm_match_cea_mode(mode); + + if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || + vic == 2 || vic == 3 || vic == 17 || vic == 18) + colorimetry = HDMI_COLORIMETRY_ITU_601; + else + colorimetry = HDMI_COLORIMETRY_ITU_709; + /* Input video mode is SDR RGB24bit, data enable signal from external */ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL | @@ -720,7 +671,7 @@ static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) return 0; } } else { - if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) { + if (colorimetry == HDMI_COLORIMETRY_ITU_601) { if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) { csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT; auto_csc = AUTO_CSC_DISABLE; @@ -738,8 +689,7 @@ static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) } for (i = 0; i < 24; i++) - hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, - coeff_csc[csc_mode][i]); + hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, coeff_csc[csc_mode][i]); value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); @@ -753,15 +703,11 @@ static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi) static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, struct drm_display_mode *mode) { - int value, psync; - - if (hdmi->variant->dev_type == RK3036_HDMI) { - psync = mode->flags & DRM_MODE_FLAG_PHSYNC ? 1 : 0; - value = FIELD_PREP_WM16(RK3036_HDMI_PHSYNC, psync); - psync = mode->flags & DRM_MODE_FLAG_PVSYNC ? 1 : 0; - value |= FIELD_PREP_WM16(RK3036_HDMI_PVSYNC, psync); - regmap_write(hdmi->grf, RK3036_GRF_SOC_CON2, value); - } + const struct inno_hdmi_plat_ops *plat_ops = hdmi->plat_data->ops; + u32 value; + + if (plat_ops && plat_ops->enable) + plat_ops->enable(hdmi->dev, mode); /* Set detail external video timing polarity and interlace mode */ value = v_EXTERANL_VIDEO(1); @@ -810,14 +756,16 @@ static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, return 0; } -static int inno_hdmi_setup(struct inno_hdmi *hdmi, - struct drm_atomic_state *state) +static int inno_hdmi_setup(struct inno_hdmi *hdmi, struct drm_atomic_state *state) { - struct drm_connector *connector = &hdmi->connector; - struct drm_display_info *display = &connector->display_info; + struct drm_bridge *bridge = &hdmi->bridge; + struct drm_connector *connector; + struct drm_display_info *info; struct drm_connector_state *new_conn_state; struct drm_crtc_state *new_crtc_state; + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); + new_conn_state = drm_atomic_get_new_connector_state(state, connector); if (WARN_ON(!new_conn_state)) return -EINVAL; @@ -826,17 +774,18 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi, if (WARN_ON(!new_crtc_state)) return -EINVAL; + info = &connector->display_info; + /* Mute video and audio output */ hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); /* Set HDMI Mode */ - hdmi_writeb(hdmi, HDMI_HDCP_CTRL, - v_HDMI_DVI(display->is_hdmi)); + hdmi_writeb(hdmi, HDMI_HDCP_CTRL, v_HDMI_DVI(info->is_hdmi)); inno_hdmi_config_video_timing(hdmi, &new_crtc_state->adjusted_mode); - inno_hdmi_config_video_csc(hdmi); + inno_hdmi_config_video_csc(hdmi, connector, &new_crtc_state->adjusted_mode); drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); @@ -857,9 +806,11 @@ static int inno_hdmi_setup(struct inno_hdmi *hdmi, return 0; } -static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi, - const struct drm_display_mode *mode) +static enum drm_mode_status inno_hdmi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); unsigned long mpixelclk, max_tolerance; long rounded_refclk; @@ -889,189 +840,59 @@ static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi, return MODE_OK; } -static void inno_hdmi_encoder_enable(struct drm_encoder *encoder, - struct drm_atomic_state *state) -{ - struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_setup(hdmi, state); -} - -static void inno_hdmi_encoder_disable(struct drm_encoder *encoder, - struct drm_atomic_state *state) -{ - struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder); - - inno_hdmi_standby(hdmi); -} - -static int -inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); - struct drm_display_mode *mode = &crtc_state->adjusted_mode; - u8 vic = drm_match_cea_mode(mode); - struct inno_hdmi_connector_state *inno_conn_state = - to_inno_hdmi_conn_state(conn_state); - - s->output_mode = ROCKCHIP_OUT_MODE_P888; - s->output_type = DRM_MODE_CONNECTOR_HDMIA; - - if (vic == 6 || vic == 7 || - vic == 21 || vic == 22 || - vic == 2 || vic == 3 || - vic == 17 || vic == 18) - inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601; - else - inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709; - - return 0; -} - -static const struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = { - .atomic_check = inno_hdmi_encoder_atomic_check, - .atomic_enable = inno_hdmi_encoder_enable, - .atomic_disable = inno_hdmi_encoder_disable, -}; - static enum drm_connector_status -inno_hdmi_connector_detect(struct drm_connector *connector, bool force) +inno_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) { - struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? connector_status_connected : connector_status_disconnected; } -static int inno_hdmi_connector_get_modes(struct drm_connector *connector) +static const struct drm_edid * +inno_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) { - struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); const struct drm_edid *drm_edid; - int ret = 0; - - if (!hdmi->ddc) - return 0; - - drm_edid = drm_edid_read_ddc(connector, hdmi->ddc); - drm_edid_connector_update(connector, drm_edid); - ret = drm_edid_connector_add_modes(connector); - drm_edid_free(drm_edid); - - return ret; -} - -static enum drm_mode_status -inno_hdmi_connector_mode_valid(struct drm_connector *connector, - const struct drm_display_mode *mode) -{ - struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector); - - return inno_hdmi_display_mode_valid(hdmi, mode); -} -static void -inno_hdmi_connector_destroy_state(struct drm_connector *connector, - struct drm_connector_state *state) -{ - struct inno_hdmi_connector_state *inno_conn_state = - to_inno_hdmi_conn_state(state); + drm_edid = drm_edid_read_ddc(connector, bridge->ddc); + if (!drm_edid) + dev_dbg(hdmi->dev, "failed to get edid\n"); - __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base); - kfree(inno_conn_state); + return drm_edid; } -static void inno_hdmi_connector_reset(struct drm_connector *connector) +static void inno_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { - struct inno_hdmi_connector_state *inno_conn_state; - - if (connector->state) { - inno_hdmi_connector_destroy_state(connector, connector->state); - connector->state = NULL; - } - - inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL); - if (!inno_conn_state) - return; - - __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base); - __drm_atomic_helper_connector_hdmi_reset(connector, connector->state); + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); - inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709; + inno_hdmi_setup(hdmi, state); } -static struct drm_connector_state * -inno_hdmi_connector_duplicate_state(struct drm_connector *connector) +static void inno_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) { - struct inno_hdmi_connector_state *inno_conn_state; - - if (WARN_ON(!connector->state)) - return NULL; - - inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state), - sizeof(*inno_conn_state), GFP_KERNEL); - - if (!inno_conn_state) - return NULL; - - __drm_atomic_helper_connector_duplicate_state(connector, - &inno_conn_state->base); + struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); - return &inno_conn_state->base; + inno_hdmi_standby(hdmi); } -static const struct drm_connector_funcs inno_hdmi_connector_funcs = { - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = inno_hdmi_connector_detect, - .reset = inno_hdmi_connector_reset, - .atomic_duplicate_state = inno_hdmi_connector_duplicate_state, - .atomic_destroy_state = inno_hdmi_connector_destroy_state, -}; - -static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = { - .atomic_check = drm_atomic_helper_connector_hdmi_check, - .get_modes = inno_hdmi_connector_get_modes, - .mode_valid = inno_hdmi_connector_mode_valid, +static const struct drm_bridge_funcs inno_hdmi_bridge_funcs = { + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_enable = inno_hdmi_bridge_atomic_enable, + .atomic_disable = inno_hdmi_bridge_atomic_disable, + .detect = inno_hdmi_bridge_detect, + .edid_read = inno_hdmi_bridge_edid_read, + .hdmi_clear_avi_infoframe = inno_hdmi_bridge_clear_avi_infoframe, + .hdmi_write_avi_infoframe = inno_hdmi_bridge_write_avi_infoframe, + .hdmi_clear_hdmi_infoframe = inno_hdmi_bridge_clear_hdmi_infoframe, + .hdmi_write_hdmi_infoframe = inno_hdmi_bridge_write_hdmi_infoframe, + .mode_valid = inno_hdmi_bridge_mode_valid, }; -static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi) -{ - struct drm_encoder *encoder = &hdmi->encoder.encoder; - struct device *dev = hdmi->dev; - - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); - - /* - * If we failed to find the CRTC(s) which this encoder is - * supposed to be connected to, it's because the CRTC has - * not been registered yet. Defer probing, and hope that - * the required CRTC is added later. - */ - if (encoder->possible_crtcs == 0) - return -EPROBE_DEFER; - - drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs); - drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); - - hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; - - drm_connector_helper_add(&hdmi->connector, - &inno_hdmi_connector_helper_funcs); - drmm_connector_hdmi_init(drm, &hdmi->connector, - "Rockchip", "Inno HDMI", - &inno_hdmi_connector_funcs, - &inno_hdmi_hdmi_connector_funcs, - DRM_MODE_CONNECTOR_HDMIA, - hdmi->ddc, - BIT(HDMI_COLORSPACE_RGB), - 8); - - drm_connector_attach_encoder(&hdmi->connector, encoder); - - return 0; -} - static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi) { struct inno_hdmi_i2c *i2c = hdmi->i2c; @@ -1111,7 +932,7 @@ static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) { struct inno_hdmi *hdmi = dev_id; - drm_helper_hpd_irq_event(hdmi->connector.dev); + drm_helper_hpd_irq_event(hdmi->bridge.dev); return IRQ_HANDLED; } @@ -1243,128 +1064,80 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) return adap; } -static int inno_hdmi_bind(struct device *dev, struct device *master, - void *data) +struct inno_hdmi *inno_hdmi_bind(struct device *dev, + struct drm_encoder *encoder, + const struct inno_hdmi_plat_data *plat_data) { struct platform_device *pdev = to_platform_device(dev); - struct drm_device *drm = data; struct inno_hdmi *hdmi; - const struct inno_hdmi_variant *variant; int irq; int ret; - hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); - if (!hdmi) - return -ENOMEM; - - hdmi->dev = dev; + if (!plat_data->phy_configs || !plat_data->default_phy_config) { + dev_err(dev, "Missing platform PHY ops\n"); + return ERR_PTR(-ENODEV); + } - variant = of_device_get_match_data(hdmi->dev); - if (!variant) - return -EINVAL; + hdmi = devm_drm_bridge_alloc(dev, struct inno_hdmi, bridge, &inno_hdmi_bridge_funcs); + if (IS_ERR(hdmi)) + return ERR_CAST(hdmi); - hdmi->variant = variant; + hdmi->dev = dev; + hdmi->plat_data = plat_data; hdmi->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hdmi->regs)) - return PTR_ERR(hdmi->regs); + return ERR_CAST(hdmi->regs); hdmi->pclk = devm_clk_get_enabled(hdmi->dev, "pclk"); - if (IS_ERR(hdmi->pclk)) - return dev_err_probe(dev, PTR_ERR(hdmi->pclk), "Unable to get HDMI pclk\n"); + if (IS_ERR(hdmi->pclk)) { + dev_err_probe(dev, PTR_ERR(hdmi->pclk), "Unable to get HDMI pclk\n"); + return ERR_CAST(hdmi->pclk); + } hdmi->refclk = devm_clk_get_optional_enabled(hdmi->dev, "ref"); - if (IS_ERR(hdmi->refclk)) - return dev_err_probe(dev, PTR_ERR(hdmi->refclk), "Unable to get HDMI refclk\n"); - - if (hdmi->variant->dev_type == RK3036_HDMI) { - hdmi->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); - if (IS_ERR(hdmi->grf)) - return dev_err_probe(dev, - PTR_ERR(hdmi->grf), "Unable to get rockchip,grf\n"); + if (IS_ERR(hdmi->refclk)) { + dev_err_probe(dev, PTR_ERR(hdmi->refclk), "Unable to get HDMI refclk\n"); + return ERR_CAST(hdmi->refclk); } - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - inno_hdmi_init_hw(hdmi); - hdmi->ddc = inno_hdmi_i2c_adapter(hdmi); - if (IS_ERR(hdmi->ddc)) - return PTR_ERR(hdmi->ddc); - - ret = inno_hdmi_register(drm, hdmi); - if (ret) - return ret; - - dev_set_drvdata(dev, hdmi); + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return ERR_PTR(irq); ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq, inno_hdmi_irq, IRQF_SHARED, dev_name(dev), hdmi); - if (ret < 0) - goto err_cleanup_hdmi; - - return 0; -err_cleanup_hdmi: - hdmi->connector.funcs->destroy(&hdmi->connector); - hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); - return ret; -} - -static void inno_hdmi_unbind(struct device *dev, struct device *master, - void *data) -{ - struct inno_hdmi *hdmi = dev_get_drvdata(dev); - - hdmi->connector.funcs->destroy(&hdmi->connector); - hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder); -} + if (ret) + return ERR_PTR(ret); -static const struct component_ops inno_hdmi_ops = { - .bind = inno_hdmi_bind, - .unbind = inno_hdmi_unbind, -}; + hdmi->bridge.driver_private = hdmi; + hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | + DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HDMI | + DRM_BRIDGE_OP_HPD; + hdmi->bridge.of_node = pdev->dev.of_node; + hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + hdmi->bridge.vendor = "Inno"; + hdmi->bridge.product = "Inno HDMI"; + + hdmi->bridge.ddc = inno_hdmi_i2c_adapter(hdmi); + if (IS_ERR(hdmi->bridge.ddc)) + return ERR_CAST(hdmi->bridge.ddc); + + ret = devm_drm_bridge_add(dev, &hdmi->bridge); + if (ret) + return ERR_PTR(ret); -static int inno_hdmi_probe(struct platform_device *pdev) -{ - return component_add(&pdev->dev, &inno_hdmi_ops); -} + ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) + return ERR_PTR(ret); -static void inno_hdmi_remove(struct platform_device *pdev) -{ - component_del(&pdev->dev, &inno_hdmi_ops); + return hdmi; } - -static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = { - .dev_type = RK3036_HDMI, - .phy_configs = rk3036_hdmi_phy_configs, - .default_phy_config = &rk3036_hdmi_phy_configs[1], -}; - -static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = { - .dev_type = RK3128_HDMI, - .phy_configs = rk3128_hdmi_phy_configs, - .default_phy_config = &rk3128_hdmi_phy_configs[1], -}; - -static const struct of_device_id inno_hdmi_dt_ids[] = { - { .compatible = "rockchip,rk3036-inno-hdmi", - .data = &rk3036_inno_hdmi_variant, - }, - { .compatible = "rockchip,rk3128-inno-hdmi", - .data = &rk3128_inno_hdmi_variant, - }, - {}, -}; -MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids); - -struct platform_driver inno_hdmi_driver = { - .probe = inno_hdmi_probe, - .remove = inno_hdmi_remove, - .driver = { - .name = "innohdmi-rockchip", - .of_match_table = inno_hdmi_dt_ids, - }, -}; +EXPORT_SYMBOL_GPL(inno_hdmi_bind); +MODULE_AUTHOR("Andy Yan "); +MODULE_DESCRIPTION("INNOSILICON HDMI transmitter library"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/bridge/ite-it6263.c b/drivers/gpu/drm/bridge/ite-it6263.c index 2eb8fba7016cb..3991fb76143c9 100644 --- a/drivers/gpu/drm/bridge/ite-it6263.c +++ b/drivers/gpu/drm/bridge/ite-it6263.c @@ -759,61 +759,62 @@ it6263_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, return MODE_OK; } -static int it6263_hdmi_clear_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type) +static int it6263_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) { struct it6263 *it = bridge_to_it6263(bridge); - switch (type) { - case HDMI_INFOFRAME_TYPE_AVI: - regmap_write(it->hdmi_regmap, HDMI_REG_AVI_INFOFRM_CTRL, 0); - break; - case HDMI_INFOFRAME_TYPE_VENDOR: - regmap_write(it->hdmi_regmap, HDMI_REG_PKT_NULL_CTRL, 0); - break; - default: - dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type); - } + regmap_write(it->hdmi_regmap, HDMI_REG_AVI_INFOFRM_CTRL, 0); + + return 0; +} + +static int it6263_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + struct it6263 *it = bridge_to_it6263(bridge); + + regmap_write(it->hdmi_regmap, HDMI_REG_PKT_NULL_CTRL, 0); return 0; } -static int it6263_hdmi_write_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) +static int it6263_hdmi_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) { struct it6263 *it = bridge_to_it6263(bridge); struct regmap *regmap = it->hdmi_regmap; - switch (type) { - case HDMI_INFOFRAME_TYPE_AVI: - /* write the first AVI infoframe data byte chunk(DB1-DB5) */ - regmap_bulk_write(regmap, HDMI_REG_AVI_DB1, - &buffer[HDMI_INFOFRAME_HEADER_SIZE], - HDMI_AVI_DB_CHUNK1_SIZE); - - /* write the second AVI infoframe data byte chunk(DB6-DB13) */ - regmap_bulk_write(regmap, HDMI_REG_AVI_DB6, - &buffer[HDMI_INFOFRAME_HEADER_SIZE + - HDMI_AVI_DB_CHUNK1_SIZE], - HDMI_AVI_DB_CHUNK2_SIZE); - - /* write checksum */ - regmap_write(regmap, HDMI_REG_AVI_CSUM, buffer[3]); - - regmap_write(regmap, HDMI_REG_AVI_INFOFRM_CTRL, - ENABLE_PKT | REPEAT_PKT); - break; - case HDMI_INFOFRAME_TYPE_VENDOR: - /* write header and payload */ - regmap_bulk_write(regmap, HDMI_REG_PKT_HB(0), buffer, len); - - regmap_write(regmap, HDMI_REG_PKT_NULL_CTRL, - ENABLE_PKT | REPEAT_PKT); - break; - default: - dev_dbg(it->dev, "unsupported HDMI infoframe 0x%x\n", type); - } + /* write the first AVI infoframe data byte chunk(DB1-DB5) */ + regmap_bulk_write(regmap, HDMI_REG_AVI_DB1, + &buffer[HDMI_INFOFRAME_HEADER_SIZE], + HDMI_AVI_DB_CHUNK1_SIZE); + + /* write the second AVI infoframe data byte chunk(DB6-DB13) */ + regmap_bulk_write(regmap, HDMI_REG_AVI_DB6, + &buffer[HDMI_INFOFRAME_HEADER_SIZE + + HDMI_AVI_DB_CHUNK1_SIZE], + HDMI_AVI_DB_CHUNK2_SIZE); + + /* write checksum */ + regmap_write(regmap, HDMI_REG_AVI_CSUM, buffer[3]); + + regmap_write(regmap, HDMI_REG_AVI_INFOFRM_CTRL, + ENABLE_PKT | REPEAT_PKT); + + return 0; +} + +static int it6263_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct it6263 *it = bridge_to_it6263(bridge); + struct regmap *regmap = it->hdmi_regmap; + + /* write header and payload */ + regmap_bulk_write(regmap, HDMI_REG_PKT_HB(0), buffer, len); + + regmap_write(regmap, HDMI_REG_PKT_NULL_CTRL, + ENABLE_PKT | REPEAT_PKT); + return 0; } @@ -830,8 +831,10 @@ static const struct drm_bridge_funcs it6263_bridge_funcs = { .edid_read = it6263_bridge_edid_read, .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts, .hdmi_tmds_char_rate_valid = it6263_hdmi_tmds_char_rate_valid, - .hdmi_clear_infoframe = it6263_hdmi_clear_infoframe, - .hdmi_write_infoframe = it6263_hdmi_write_infoframe, + .hdmi_clear_avi_infoframe = it6263_hdmi_clear_avi_infoframe, + .hdmi_write_avi_infoframe = it6263_hdmi_write_avi_infoframe, + .hdmi_clear_hdmi_infoframe = it6263_hdmi_clear_hdmi_infoframe, + .hdmi_write_hdmi_infoframe = it6263_hdmi_write_hdmi_infoframe, }; static int it6263_probe(struct i2c_client *client) diff --git a/drivers/gpu/drm/bridge/ite-it66121.c b/drivers/gpu/drm/bridge/ite-it66121.c index 0185f61e6e59a..9246e9c15a6ef 100644 --- a/drivers/gpu/drm/bridge/ite-it66121.c +++ b/drivers/gpu/drm/bridge/ite-it66121.c @@ -298,7 +298,6 @@ struct it66121_chip_info { struct it66121_ctx { struct regmap *regmap; struct drm_bridge bridge; - struct drm_bridge *next_bridge; struct drm_connector *connector; struct device *dev; struct gpio_desc *gpio_reset; @@ -596,7 +595,7 @@ static int it66121_bridge_attach(struct drm_bridge *bridge, if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) return -EINVAL; - ret = drm_bridge_attach(encoder, ctx->next_bridge, bridge, flags); + ret = drm_bridge_attach(encoder, ctx->bridge.next_bridge, bridge, flags); if (ret) return ret; @@ -1543,9 +1542,9 @@ static int it66121_probe(struct i2c_client *client) return -EINVAL; } - ctx->next_bridge = of_drm_find_bridge(ep); + ctx->bridge.next_bridge = of_drm_find_and_get_bridge(ep); of_node_put(ep); - if (!ctx->next_bridge) { + if (!ctx->bridge.next_bridge) { dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n"); return -EPROBE_DEFER; } diff --git a/drivers/gpu/drm/bridge/lontium-lt8912b.c b/drivers/gpu/drm/bridge/lontium-lt8912b.c index 342374cb8fc6b..8a0b48efca580 100644 --- a/drivers/gpu/drm/bridge/lontium-lt8912b.c +++ b/drivers/gpu/drm/bridge/lontium-lt8912b.c @@ -35,7 +35,6 @@ struct lt8912 { struct regmap *regmap[I2C_MAX_IDX]; struct device_node *host_node; - struct drm_bridge *hdmi_port; struct mipi_dsi_device *dsi; @@ -407,8 +406,8 @@ lt8912_connector_detect(struct drm_connector *connector, bool force) { struct lt8912 *lt = connector_to_lt8912(connector); - if (lt->hdmi_port->ops & DRM_BRIDGE_OP_DETECT) - return drm_bridge_detect(lt->hdmi_port, connector); + if (lt->bridge.next_bridge->ops & DRM_BRIDGE_OP_DETECT) + return drm_bridge_detect(lt->bridge.next_bridge, connector); return lt8912_check_cable_status(lt); } @@ -429,7 +428,7 @@ static int lt8912_connector_get_modes(struct drm_connector *connector) u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; int ret, num; - drm_edid = drm_bridge_edid_read(lt->hdmi_port, connector); + drm_edid = drm_bridge_edid_read(lt->bridge.next_bridge, connector); drm_edid_connector_update(connector, drm_edid); if (!drm_edid) return 0; @@ -519,8 +518,8 @@ static int lt8912_bridge_connector_init(struct drm_bridge *bridge) struct lt8912 *lt = bridge_to_lt8912(bridge); struct drm_connector *connector = <->connector; - if (lt->hdmi_port->ops & DRM_BRIDGE_OP_HPD) { - drm_bridge_hpd_enable(lt->hdmi_port, lt8912_bridge_hpd_cb, lt); + if (lt->bridge.next_bridge->ops & DRM_BRIDGE_OP_HPD) { + drm_bridge_hpd_enable(lt->bridge.next_bridge, lt8912_bridge_hpd_cb, lt); connector->polled = DRM_CONNECTOR_POLL_HPD; } else { connector->polled = DRM_CONNECTOR_POLL_CONNECT | @@ -529,7 +528,7 @@ static int lt8912_bridge_connector_init(struct drm_bridge *bridge) ret = drm_connector_init(bridge->dev, connector, <8912_connector_funcs, - lt->hdmi_port->type); + lt->bridge.next_bridge->type); if (ret) goto exit; @@ -549,7 +548,7 @@ static int lt8912_bridge_attach(struct drm_bridge *bridge, struct lt8912 *lt = bridge_to_lt8912(bridge); int ret; - ret = drm_bridge_attach(encoder, lt->hdmi_port, bridge, + ret = drm_bridge_attach(encoder, lt->bridge.next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret < 0) { dev_err(lt->dev, "Failed to attach next bridge (%d)\n", ret); @@ -585,8 +584,8 @@ static void lt8912_bridge_detach(struct drm_bridge *bridge) lt8912_hard_power_off(lt); - if (lt->connector.dev && lt->hdmi_port->ops & DRM_BRIDGE_OP_HPD) - drm_bridge_hpd_disable(lt->hdmi_port); + if (lt->connector.dev && lt->bridge.next_bridge->ops & DRM_BRIDGE_OP_HPD) + drm_bridge_hpd_disable(lt->bridge.next_bridge); } static enum drm_mode_status @@ -611,8 +610,8 @@ lt8912_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) { struct lt8912 *lt = bridge_to_lt8912(bridge); - if (lt->hdmi_port->ops & DRM_BRIDGE_OP_DETECT) - return drm_bridge_detect(lt->hdmi_port, connector); + if (lt->bridge.next_bridge->ops & DRM_BRIDGE_OP_DETECT) + return drm_bridge_detect(lt->bridge.next_bridge, connector); return lt8912_check_cable_status(lt); } @@ -626,8 +625,8 @@ static const struct drm_edid *lt8912_bridge_edid_read(struct drm_bridge *bridge, * edid must be read through the ddc bus but it must be * given to the hdmi connector node. */ - if (lt->hdmi_port->ops & DRM_BRIDGE_OP_EDID) - return drm_bridge_edid_read(lt->hdmi_port, connector); + if (lt->bridge.next_bridge->ops & DRM_BRIDGE_OP_EDID) + return drm_bridge_edid_read(lt->bridge.next_bridge, connector); dev_warn(lt->dev, "The connected bridge does not supports DRM_BRIDGE_OP_EDID\n"); return NULL; @@ -723,8 +722,8 @@ static int lt8912_parse_dt(struct lt8912 *lt) goto err_free_host_node; } - lt->hdmi_port = of_drm_find_bridge(port_node); - if (!lt->hdmi_port) { + lt->bridge.next_bridge = of_drm_find_and_get_bridge(port_node); + if (!lt->bridge.next_bridge) { ret = -EPROBE_DEFER; dev_err_probe(lt->dev, ret, "%s: Failed to get hdmi port\n", __func__); goto err_free_host_node; diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c index a2d032ee47447..0628d8e737abb 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611.c @@ -843,84 +843,96 @@ lt9611_atomic_get_input_bus_fmts(struct drm_bridge *bridge, #define LT9611_INFOFRAME_AUDIO 0x02 #define LT9611_INFOFRAME_AVI 0x08 #define LT9611_INFOFRAME_SPD 0x10 -#define LT9611_INFOFRAME_VENDOR 0x20 +#define LT9611_INFOFRAME_HDMI 0x20 -static int lt9611_hdmi_clear_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type) +static int lt9611_hdmi_clear_audio_infoframe(struct drm_bridge *bridge) { struct lt9611 *lt9611 = bridge_to_lt9611(bridge); - unsigned int mask; - switch (type) { - case HDMI_INFOFRAME_TYPE_AUDIO: - mask = LT9611_INFOFRAME_AUDIO; - break; + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, 0); - case HDMI_INFOFRAME_TYPE_AVI: - mask = LT9611_INFOFRAME_AVI; - break; + return 0; +} - case HDMI_INFOFRAME_TYPE_SPD: - mask = LT9611_INFOFRAME_SPD; - break; +static int lt9611_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) +{ + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); - case HDMI_INFOFRAME_TYPE_VENDOR: - mask = LT9611_INFOFRAME_VENDOR; - break; + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AVI, 0); - default: - drm_dbg_driver(lt9611->bridge.dev, "Unsupported HDMI InfoFrame %x\n", type); - mask = 0; - break; - } + return 0; +} + +static int lt9611_hdmi_clear_spd_infoframe(struct drm_bridge *bridge) +{ + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); - if (mask) - regmap_update_bits(lt9611->regmap, 0x843d, mask, 0); + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_SPD, 0); return 0; } -static int lt9611_hdmi_write_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) +static int lt9611_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); + + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_HDMI, 0); + + return 0; +} + +static int lt9611_hdmi_write_audio_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) { struct lt9611 *lt9611 = bridge_to_lt9611(bridge); - unsigned int mask, addr; int i; - switch (type) { - case HDMI_INFOFRAME_TYPE_AUDIO: - mask = LT9611_INFOFRAME_AUDIO; - addr = 0x84b2; - break; - - case HDMI_INFOFRAME_TYPE_AVI: - mask = LT9611_INFOFRAME_AVI; - addr = 0x8440; - break; - - case HDMI_INFOFRAME_TYPE_SPD: - mask = LT9611_INFOFRAME_SPD; - addr = 0x8493; - break; - - case HDMI_INFOFRAME_TYPE_VENDOR: - mask = LT9611_INFOFRAME_VENDOR; - addr = 0x8474; - break; - - default: - drm_dbg_driver(lt9611->bridge.dev, "Unsupported HDMI InfoFrame %x\n", type); - mask = 0; - break; - } + for (i = 0; i < len; i++) + regmap_write(lt9611->regmap, 0x84b2 + i, buffer[i]); - if (mask) { - for (i = 0; i < len; i++) - regmap_write(lt9611->regmap, addr + i, buffer[i]); + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AUDIO, LT9611_INFOFRAME_AUDIO); - regmap_update_bits(lt9611->regmap, 0x843d, mask, mask); - } + return 0; +} + +static int lt9611_hdmi_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); + int i; + + for (i = 0; i < len; i++) + regmap_write(lt9611->regmap, 0x8440 + i, buffer[i]); + + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_AVI, LT9611_INFOFRAME_AVI); + + return 0; +} + +static int lt9611_hdmi_write_spd_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); + int i; + + for (i = 0; i < len; i++) + regmap_write(lt9611->regmap, 0x8493 + i, buffer[i]); + + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_SPD, LT9611_INFOFRAME_SPD); + + return 0; +} + +static int lt9611_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct lt9611 *lt9611 = bridge_to_lt9611(bridge); + int i; + + for (i = 0; i < len; i++) + regmap_write(lt9611->regmap, 0x8474 + i, buffer[i]); + + regmap_update_bits(lt9611->regmap, 0x843d, LT9611_INFOFRAME_HDMI, LT9611_INFOFRAME_HDMI); return 0; } @@ -1003,8 +1015,14 @@ static const struct drm_bridge_funcs lt9611_bridge_funcs = { .atomic_get_input_bus_fmts = lt9611_atomic_get_input_bus_fmts, .hdmi_tmds_char_rate_valid = lt9611_hdmi_tmds_char_rate_valid, - .hdmi_write_infoframe = lt9611_hdmi_write_infoframe, - .hdmi_clear_infoframe = lt9611_hdmi_clear_infoframe, + .hdmi_write_audio_infoframe = lt9611_hdmi_write_audio_infoframe, + .hdmi_clear_audio_infoframe = lt9611_hdmi_clear_audio_infoframe, + .hdmi_write_avi_infoframe = lt9611_hdmi_write_avi_infoframe, + .hdmi_clear_avi_infoframe = lt9611_hdmi_clear_avi_infoframe, + .hdmi_write_spd_infoframe = lt9611_hdmi_write_spd_infoframe, + .hdmi_clear_spd_infoframe = lt9611_hdmi_clear_spd_infoframe, + .hdmi_write_hdmi_infoframe = lt9611_hdmi_write_hdmi_infoframe, + .hdmi_clear_hdmi_infoframe = lt9611_hdmi_clear_hdmi_infoframe, .hdmi_audio_startup = lt9611_hdmi_audio_startup, .hdmi_audio_prepare = lt9611_hdmi_audio_prepare, @@ -1132,7 +1150,8 @@ static int lt9611_probe(struct i2c_client *client) lt9611->bridge.of_node = client->dev.of_node; lt9611->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_MODES | - DRM_BRIDGE_OP_HDMI | DRM_BRIDGE_OP_HDMI_AUDIO; + DRM_BRIDGE_OP_HDMI | DRM_BRIDGE_OP_HDMI_AUDIO | + DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME; lt9611->bridge.type = DRM_MODE_CONNECTOR_HDMIA; lt9611->bridge.vendor = "Lontium"; lt9611->bridge.product = "LT9611"; diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index 38fb8776c0f44..11aab07d88df6 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -17,8 +17,6 @@ #include #include -#include - #include #include #include @@ -27,6 +25,8 @@ #include #include +#include + #define EDID_BLOCK_SIZE 128 #define EDID_NUM_BLOCKS 2 @@ -48,7 +48,6 @@ struct lt9611uxc { struct device_node *dsi1_node; struct mipi_dsi_device *dsi0; struct mipi_dsi_device *dsi1; - struct platform_device *audio_pdev; struct gpio_desc *reset_gpio; struct gpio_desc *enable_gpio; @@ -429,12 +428,52 @@ static const struct drm_edid *lt9611uxc_bridge_edid_read(struct drm_bridge *brid return drm_edid_read_custom(connector, lt9611uxc_get_edid_block, lt9611uxc); } +static void lt9611uxc_bridge_hpd_notify(struct drm_bridge *bridge, + struct drm_connector *connector, + enum drm_connector_status status) +{ + const struct drm_edid *drm_edid; + + if (status == connector_status_disconnected) { + drm_connector_hdmi_audio_plugged_notify(connector, false); + drm_edid_connector_update(connector, NULL); + return; + } + + drm_edid = lt9611uxc_bridge_edid_read(bridge, connector); + drm_edid_connector_update(connector, drm_edid); + drm_edid_free(drm_edid); + + if (status == connector_status_connected) + drm_connector_hdmi_audio_plugged_notify(connector, true); +} + +static int lt9611uxc_hdmi_audio_prepare(struct drm_bridge *bridge, + struct drm_connector *connector, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms) +{ + /* + * LT9611UXC will automatically detect rate and sample size, so no need + * to setup anything here. + */ + return 0; +} + +static void lt9611uxc_hdmi_audio_shutdown(struct drm_bridge *bridge, + struct drm_connector *connector) +{ +} + static const struct drm_bridge_funcs lt9611uxc_bridge_funcs = { .attach = lt9611uxc_bridge_attach, .mode_valid = lt9611uxc_bridge_mode_valid, .mode_set = lt9611uxc_bridge_mode_set, .detect = lt9611uxc_bridge_detect, .edid_read = lt9611uxc_bridge_edid_read, + .hpd_notify = lt9611uxc_bridge_hpd_notify, + .hdmi_audio_prepare = lt9611uxc_hdmi_audio_prepare, + .hdmi_audio_shutdown = lt9611uxc_hdmi_audio_shutdown, }; static int lt9611uxc_parse_dt(struct device *dev, @@ -508,73 +547,6 @@ static int lt9611uxc_read_version(struct lt9611uxc *lt9611uxc) return ret < 0 ? ret : rev; } -static int lt9611uxc_hdmi_hw_params(struct device *dev, void *data, - struct hdmi_codec_daifmt *fmt, - struct hdmi_codec_params *hparms) -{ - /* - * LT9611UXC will automatically detect rate and sample size, so no need - * to setup anything here. - */ - return 0; -} - -static void lt9611uxc_audio_shutdown(struct device *dev, void *data) -{ -} - -static int lt9611uxc_hdmi_i2s_get_dai_id(struct snd_soc_component *component, - struct device_node *endpoint, - void *data) -{ - struct of_endpoint of_ep; - int ret; - - ret = of_graph_parse_endpoint(endpoint, &of_ep); - if (ret < 0) - return ret; - - /* - * HDMI sound should be located as reg = <2> - * Then, it is sound port 0 - */ - if (of_ep.port == 2) - return 0; - - return -EINVAL; -} - -static const struct hdmi_codec_ops lt9611uxc_codec_ops = { - .hw_params = lt9611uxc_hdmi_hw_params, - .audio_shutdown = lt9611uxc_audio_shutdown, - .get_dai_id = lt9611uxc_hdmi_i2s_get_dai_id, -}; - -static int lt9611uxc_audio_init(struct device *dev, struct lt9611uxc *lt9611uxc) -{ - struct hdmi_codec_pdata codec_data = { - .ops = <9611uxc_codec_ops, - .max_i2s_channels = 2, - .i2s = 1, - .data = lt9611uxc, - }; - - lt9611uxc->audio_pdev = - platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, - PLATFORM_DEVID_AUTO, - &codec_data, sizeof(codec_data)); - - return PTR_ERR_OR_ZERO(lt9611uxc->audio_pdev); -} - -static void lt9611uxc_audio_exit(struct lt9611uxc *lt9611uxc) -{ - if (lt9611uxc->audio_pdev) { - platform_device_unregister(lt9611uxc->audio_pdev); - lt9611uxc->audio_pdev = NULL; - } -} - #define LT9611UXC_FW_PAGE_SIZE 32 static void lt9611uxc_firmware_write_page(struct lt9611uxc *lt9611uxc, u16 addr, const u8 *buf) { @@ -858,11 +830,17 @@ static int lt9611uxc_probe(struct i2c_client *client) i2c_set_clientdata(client, lt9611uxc); lt9611uxc->bridge.of_node = client->dev.of_node; - lt9611uxc->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; + lt9611uxc->bridge.ops = DRM_BRIDGE_OP_DETECT | + DRM_BRIDGE_OP_EDID | + DRM_BRIDGE_OP_HDMI_AUDIO; if (lt9611uxc->hpd_supported) lt9611uxc->bridge.ops |= DRM_BRIDGE_OP_HPD; lt9611uxc->bridge.type = DRM_MODE_CONNECTOR_HDMIA; + lt9611uxc->bridge.hdmi_audio_dev = dev; + lt9611uxc->bridge.hdmi_audio_max_i2s_playback_channels = 2; + lt9611uxc->bridge.hdmi_audio_dai_port = 2; + drm_bridge_add(<9611uxc->bridge); /* Attach primary DSI */ @@ -881,10 +859,6 @@ static int lt9611uxc_probe(struct i2c_client *client) } } - ret = lt9611uxc_audio_init(dev, lt9611uxc); - if (ret) - goto err_remove_bridge; - return 0; err_remove_bridge: @@ -908,7 +882,6 @@ static void lt9611uxc_remove(struct i2c_client *client) free_irq(client->irq, lt9611uxc); cancel_work_sync(<9611uxc->work); - lt9611uxc_audio_exit(lt9611uxc); drm_bridge_remove(<9611uxc->bridge); mutex_destroy(<9611uxc->ocm_lock); diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index eabc4c32f6ab4..1d85e706c74b9 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -1828,7 +1828,7 @@ static int samsung_dsim_attach(struct drm_bridge *bridge, { struct samsung_dsim *dsi = bridge_to_dsi(bridge); - return drm_bridge_attach(encoder, dsi->out_bridge, bridge, + return drm_bridge_attach(encoder, dsi->bridge.next_bridge, bridge, flags); } @@ -1886,11 +1886,12 @@ static int samsung_dsim_host_attach(struct mipi_dsi_host *host, { struct samsung_dsim *dsi = host_to_dsi(host); const struct samsung_dsim_plat_data *pdata = dsi->plat_data; + struct drm_bridge *next_bridge __free(drm_bridge_put) = NULL; struct device *dev = dsi->dev; struct device_node *np = dev->of_node; struct device_node *remote; struct drm_panel *panel; - int ret; + int ret = 0; /* * Devices can also be child nodes when we also control that device @@ -1924,17 +1925,22 @@ static int samsung_dsim_host_attach(struct mipi_dsi_host *host, panel = of_drm_find_panel(remote); if (!IS_ERR(panel)) { - dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); + next_bridge = devm_drm_panel_bridge_add(dev, panel); + if (IS_ERR(next_bridge)) { + ret = PTR_ERR(next_bridge); + next_bridge = NULL; // Inhibit the cleanup action on an ERR_PTR + } else { + drm_bridge_get(next_bridge); + } } else { - dsi->out_bridge = of_drm_find_bridge(remote); - if (!dsi->out_bridge) - dsi->out_bridge = ERR_PTR(-EINVAL); + next_bridge = of_drm_find_and_get_bridge(remote); + if (!next_bridge) + ret = -EINVAL; } of_node_put(remote); - if (IS_ERR(dsi->out_bridge)) { - ret = PTR_ERR(dsi->out_bridge); + if (ret) { DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); return ret; } @@ -1958,10 +1964,13 @@ static int samsung_dsim_host_attach(struct mipi_dsi_host *host, return ret; } + // The next bridge can be used by host_ops->attach + dsi->bridge.next_bridge = drm_bridge_get(next_bridge); + if (pdata->host_ops && pdata->host_ops->attach) { ret = pdata->host_ops->attach(dsi, device); if (ret) - return ret; + goto err_release_next_bridge; } dsi->lanes = device->lanes; @@ -1969,6 +1978,11 @@ static int samsung_dsim_host_attach(struct mipi_dsi_host *host, dsi->mode_flags = device->mode_flags; return 0; + +err_release_next_bridge: + drm_bridge_put(dsi->bridge.next_bridge); + dsi->bridge.next_bridge = NULL; + return ret; } static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi) @@ -1985,11 +1999,12 @@ static int samsung_dsim_host_detach(struct mipi_dsi_host *host, struct samsung_dsim *dsi = host_to_dsi(host); const struct samsung_dsim_plat_data *pdata = dsi->plat_data; - dsi->out_bridge = NULL; - if (pdata->host_ops && pdata->host_ops->detach) pdata->host_ops->detach(dsi, device); + drm_bridge_put(dsi->bridge.next_bridge); + dsi->bridge.next_bridge = NULL; + samsung_dsim_unregister_te_irq(dsi); drm_bridge_remove(&dsi->bridge); diff --git a/drivers/gpu/drm/bridge/sii902x.c b/drivers/gpu/drm/bridge/sii902x.c index 1f0aba28ad1e1..12497f5ce4ff5 100644 --- a/drivers/gpu/drm/bridge/sii902x.c +++ b/drivers/gpu/drm/bridge/sii902x.c @@ -175,7 +175,6 @@ struct sii902x { struct i2c_client *i2c; struct regmap *regmap; struct drm_bridge bridge; - struct drm_bridge *next_bridge; struct drm_connector connector; struct gpio_desc *reset_gpio; struct i2c_mux_core *i2cmux; @@ -421,7 +420,7 @@ static int sii902x_bridge_attach(struct drm_bridge *bridge, int ret; if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) - return drm_bridge_attach(encoder, sii902x->next_bridge, + return drm_bridge_attach(encoder, sii902x->bridge.next_bridge, bridge, flags); drm_connector_helper_add(&sii902x->connector, @@ -1204,9 +1203,9 @@ static int sii902x_probe(struct i2c_client *client) return -ENODEV; } - sii902x->next_bridge = of_drm_find_bridge(remote); + sii902x->bridge.next_bridge = of_drm_find_and_get_bridge(remote); of_node_put(remote); - if (!sii902x->next_bridge) + if (!sii902x->bridge.next_bridge) return dev_err_probe(dev, -EPROBE_DEFER, "Failed to find remote bridge\n"); } diff --git a/drivers/gpu/drm/bridge/simple-bridge.c b/drivers/gpu/drm/bridge/simple-bridge.c index 2cd1847ba7760..8aa31ca3c72d4 100644 --- a/drivers/gpu/drm/bridge/simple-bridge.c +++ b/drivers/gpu/drm/bridge/simple-bridge.c @@ -31,7 +31,6 @@ struct simple_bridge { const struct simple_bridge_info *info; - struct drm_bridge *next_bridge; struct regulator *vdd; struct gpio_desc *enable; }; @@ -54,8 +53,8 @@ static int simple_bridge_get_modes(struct drm_connector *connector) const struct drm_edid *drm_edid; int ret; - if (sbridge->next_bridge->ops & DRM_BRIDGE_OP_EDID) { - drm_edid = drm_bridge_edid_read(sbridge->next_bridge, connector); + if (sbridge->bridge.next_bridge->ops & DRM_BRIDGE_OP_EDID) { + drm_edid = drm_bridge_edid_read(sbridge->bridge.next_bridge, connector); if (!drm_edid) DRM_INFO("EDID read failed. Fallback to standard modes\n"); } else { @@ -90,7 +89,7 @@ simple_bridge_connector_detect(struct drm_connector *connector, bool force) { struct simple_bridge *sbridge = drm_connector_to_simple_bridge(connector); - return drm_bridge_detect(sbridge->next_bridge, connector); + return drm_bridge_detect(sbridge->bridge.next_bridge, connector); } static const struct drm_connector_funcs simple_bridge_con_funcs = { @@ -109,7 +108,7 @@ static int simple_bridge_attach(struct drm_bridge *bridge, struct simple_bridge *sbridge = drm_bridge_to_simple_bridge(bridge); int ret; - ret = drm_bridge_attach(encoder, sbridge->next_bridge, bridge, + ret = drm_bridge_attach(encoder, sbridge->bridge.next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret < 0) return ret; @@ -122,7 +121,7 @@ static int simple_bridge_attach(struct drm_bridge *bridge, ret = drm_connector_init_with_ddc(bridge->dev, &sbridge->connector, &simple_bridge_con_funcs, sbridge->info->connector_type, - sbridge->next_bridge->ddc); + sbridge->bridge.next_bridge->ddc); if (ret) { DRM_ERROR("Failed to initialize connector\n"); return ret; @@ -180,10 +179,10 @@ static int simple_bridge_probe(struct platform_device *pdev) if (!remote) return -EINVAL; - sbridge->next_bridge = of_drm_find_bridge(remote); + sbridge->bridge.next_bridge = of_drm_find_and_get_bridge(remote); of_node_put(remote); - if (!sbridge->next_bridge) { + if (!sbridge->bridge.next_bridge) { dev_dbg(&pdev->dev, "Next bridge not found, deferring probe\n"); return -EPROBE_DEFER; } @@ -261,6 +260,11 @@ static const struct of_device_id simple_bridge_match[] = { .timings = &default_bridge_timings, .connector_type = DRM_MODE_CONNECTOR_VGA, }, + }, { + .compatible = "algoltek,ag6311", + .data = &(const struct simple_bridge_info) { + .connector_type = DRM_MODE_CONNECTOR_HDMIA, + }, }, { .compatible = "asl-tek,cs5263", .data = &(const struct simple_bridge_info) { diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c index 60166919c5b54..ab7fed6214e06 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -26,6 +26,7 @@ #include #include #include +#include #include @@ -166,6 +167,7 @@ struct dw_hdmi_qp { int main_irq; unsigned long tmds_char_rate; + bool no_hpd; }; static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val, @@ -556,14 +558,22 @@ static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi, stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); if (!stat) { - dev_err(hdmi->dev, "i2c read timed out\n"); + if (hdmi->no_hpd) + dev_dbg_ratelimited(hdmi->dev, + "i2c read timed out\n"); + else + dev_err(hdmi->dev, "i2c read timed out\n"); dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); return -EAGAIN; } /* Check for error condition on the bus */ if (i2c->stat & I2CM_NACK_RCVD_IRQ) { - dev_err(hdmi->dev, "i2c read error\n"); + if (hdmi->no_hpd) + dev_dbg_ratelimited(hdmi->dev, + "i2c read error\n"); + else + dev_err(hdmi->dev, "i2c read error\n"); dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); return -EIO; } @@ -901,6 +911,15 @@ static enum drm_connector_status dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) { struct dw_hdmi_qp *hdmi = bridge->driver_private; + const struct drm_edid *drm_edid; + + if (hdmi->no_hpd) { + drm_edid = drm_edid_read_ddc(connector, bridge->ddc); + if (drm_edid) + return connector_status_connected; + else + return connector_status_disconnected; + } return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); } @@ -926,6 +945,11 @@ dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, { struct dw_hdmi_qp *hdmi = bridge->driver_private; + /* + * TODO: when hdmi->no_hpd is 1 we must not support modes that + * require scrambling, including every mode with a clock above + * HDMI14_MAX_TMDSCLK. + */ if (rate > HDMI14_MAX_TMDSCLK) { dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate); return MODE_CLOCK_HIGH; @@ -934,57 +958,85 @@ dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, return MODE_OK; } -static int dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type) +static int dw_hdmi_qp_bridge_clear_avi_infoframe(struct drm_bridge *bridge) { struct dw_hdmi_qp *hdmi = bridge->driver_private; - switch (type) { - case HDMI_INFOFRAME_TYPE_AVI: - dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, - PKTSCHED_PKT_EN); - break; + dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, + PKTSCHED_PKT_EN); - case HDMI_INFOFRAME_TYPE_DRM: - dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); - break; + return 0; +} - case HDMI_INFOFRAME_TYPE_AUDIO: - dw_hdmi_qp_mod(hdmi, 0, - PKTSCHED_ACR_TX_EN | - PKTSCHED_AUDS_TX_EN | - PKTSCHED_AUDI_TX_EN, - PKTSCHED_PKT_EN); - break; - default: - dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type); - } +static int dw_hdmi_qp_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) +{ + /* FIXME: add support for this InfoFrame */ + + drm_warn_once(bridge->encoder->dev, "HDMI VSI not supported\n"); return 0; } -static int dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge *bridge, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) +static int dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(struct drm_bridge *bridge) { struct dw_hdmi_qp *hdmi = bridge->driver_private; - dw_hdmi_qp_bridge_clear_infoframe(bridge, type); + dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); - switch (type) { - case HDMI_INFOFRAME_TYPE_AVI: - return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len); + return 0; +} - case HDMI_INFOFRAME_TYPE_DRM: - return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len); +static int dw_hdmi_qp_bridge_clear_audio_infoframe(struct drm_bridge *bridge) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; - case HDMI_INFOFRAME_TYPE_AUDIO: - return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len); + dw_hdmi_qp_mod(hdmi, 0, + PKTSCHED_ACR_TX_EN | + PKTSCHED_AUDS_TX_EN | + PKTSCHED_AUDI_TX_EN, + PKTSCHED_PKT_EN); - default: - dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type); - return 0; - } + return 0; +} + +static int dw_hdmi_qp_bridge_write_avi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + + dw_hdmi_qp_bridge_clear_avi_infoframe(bridge); + + return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len); +} + +static int dw_hdmi_qp_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + dw_hdmi_qp_bridge_clear_hdmi_infoframe(bridge); + + /* FIXME: add support for the HDMI VSI */ + + return 0; +} + +static int dw_hdmi_qp_bridge_write_hdr_drm_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + + dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(bridge); + + return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len); +} + +static int dw_hdmi_qp_bridge_write_audio_infoframe(struct drm_bridge *bridge, + const u8 *buffer, size_t len) +{ + struct dw_hdmi_qp *hdmi = bridge->driver_private; + + dw_hdmi_qp_bridge_clear_audio_infoframe(bridge); + + return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len); } #ifdef CONFIG_DRM_DW_HDMI_QP_CEC @@ -1169,8 +1221,14 @@ static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = { .detect = dw_hdmi_qp_bridge_detect, .edid_read = dw_hdmi_qp_bridge_edid_read, .hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid, - .hdmi_clear_infoframe = dw_hdmi_qp_bridge_clear_infoframe, - .hdmi_write_infoframe = dw_hdmi_qp_bridge_write_infoframe, + .hdmi_clear_avi_infoframe = dw_hdmi_qp_bridge_clear_avi_infoframe, + .hdmi_write_avi_infoframe = dw_hdmi_qp_bridge_write_avi_infoframe, + .hdmi_clear_hdmi_infoframe = dw_hdmi_qp_bridge_clear_hdmi_infoframe, + .hdmi_write_hdmi_infoframe = dw_hdmi_qp_bridge_write_hdmi_infoframe, + .hdmi_clear_hdr_drm_infoframe = dw_hdmi_qp_bridge_clear_hdr_drm_infoframe, + .hdmi_write_hdr_drm_infoframe = dw_hdmi_qp_bridge_write_hdr_drm_infoframe, + .hdmi_clear_audio_infoframe = dw_hdmi_qp_bridge_clear_audio_infoframe, + .hdmi_write_audio_infoframe = dw_hdmi_qp_bridge_write_audio_infoframe, .hdmi_audio_startup = dw_hdmi_qp_audio_enable, .hdmi_audio_shutdown = dw_hdmi_qp_audio_disable, .hdmi_audio_prepare = dw_hdmi_qp_audio_prepare, @@ -1279,12 +1337,16 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, if (ret) return ERR_PTR(ret); + hdmi->no_hpd = device_property_read_bool(dev, "no-hpd"); + hdmi->bridge.driver_private = hdmi; hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HDMI | DRM_BRIDGE_OP_HDMI_AUDIO | - DRM_BRIDGE_OP_HPD; + DRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME; + if (!hdmi->no_hpd) + hdmi->bridge.ops |= DRM_BRIDGE_OP_HPD; hdmi->bridge.of_node = pdev->dev.of_node; hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; hdmi->bridge.vendor = "Synopsys"; diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 3b77e73ac0eaa..ee88c0e793b04 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -132,7 +132,6 @@ struct dw_hdmi_phy_data { struct dw_hdmi { struct drm_connector connector; struct drm_bridge bridge; - struct drm_bridge *next_bridge; unsigned int version; @@ -2912,7 +2911,7 @@ static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) - return drm_bridge_attach(encoder, hdmi->next_bridge, + return drm_bridge_attach(encoder, hdmi->bridge.next_bridge, bridge, flags); return dw_hdmi_connector_create(hdmi); @@ -3318,9 +3317,9 @@ static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) if (!remote) return -ENODEV; - hdmi->next_bridge = of_drm_find_bridge(remote); + hdmi->bridge.next_bridge = of_drm_find_and_get_bridge(remote); of_node_put(remote); - if (!hdmi->next_bridge) + if (!hdmi->bridge.next_bridge) return -EPROBE_DEFER; return 0; diff --git a/drivers/gpu/drm/bridge/thc63lvd1024.c b/drivers/gpu/drm/bridge/thc63lvd1024.c index 2cb7cd0c06082..c804222846c38 100644 --- a/drivers/gpu/drm/bridge/thc63lvd1024.c +++ b/drivers/gpu/drm/bridge/thc63lvd1024.c @@ -32,7 +32,6 @@ struct thc63_dev { struct gpio_desc *oe; struct drm_bridge bridge; - struct drm_bridge *next; struct drm_bridge_timings timings; }; @@ -48,7 +47,7 @@ static int thc63_attach(struct drm_bridge *bridge, { struct thc63_dev *thc63 = to_thc63(bridge); - return drm_bridge_attach(encoder, thc63->next, bridge, flags); + return drm_bridge_attach(encoder, thc63->bridge.next_bridge, bridge, flags); } static enum drm_mode_status thc63_mode_valid(struct drm_bridge *bridge, @@ -132,9 +131,9 @@ static int thc63_parse_dt(struct thc63_dev *thc63) return -ENODEV; } - thc63->next = of_drm_find_bridge(remote); + thc63->bridge.next_bridge = of_drm_find_and_get_bridge(remote); of_node_put(remote); - if (!thc63->next) + if (!thc63->bridge.next_bridge) return -EPROBE_DEFER; endpoint = of_graph_get_endpoint_by_regs(thc63->dev->of_node, diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index fffb47b62f437..f6736b4457bb9 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -406,6 +406,10 @@ static void sn65dsi83_reset_work(struct work_struct *ws) { struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work); int ret; + int idx; + + if (!drm_bridge_enter(&ctx->bridge, &idx)) + return; /* Reset the pipe */ ret = sn65dsi83_reset_pipe(ctx); @@ -415,12 +419,18 @@ static void sn65dsi83_reset_work(struct work_struct *ws) } if (ctx->irq) enable_irq(ctx->irq); + + drm_bridge_exit(idx); } static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) { unsigned int irq_stat; int ret; + int idx; + + if (!drm_bridge_enter(&ctx->bridge, &idx)) + return; /* * Schedule a reset in case of: @@ -448,6 +458,8 @@ static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) schedule_work(&ctx->reset_work); } + + drm_bridge_exit(idx); } static void sn65dsi83_monitor_work(struct work_struct *work) @@ -470,6 +482,37 @@ static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx) cancel_delayed_work_sync(&ctx->monitor_work); } +/* + * Release resources taken by sn65dsi83_atomic_pre_enable(). + * + * Invoked by sn65dsi83_atomic_disable() normally, or by devres after + * sn65dsi83_remove() in case this happens befora atomic_disable. + */ +static void sn65dsi83_release_resources(void *data) +{ + struct sn65dsi83 *ctx = (struct sn65dsi83 *)data; + int ret; + + if (ctx->irq) { + /* Disable irq */ + regmap_write(ctx->regmap, REG_IRQ_EN, 0x0); + regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0); + } else { + /* Stop the polling task */ + sn65dsi83_monitor_stop(ctx); + } + + /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ + gpiod_set_value_cansleep(ctx->enable_gpio, 0); + usleep_range(10000, 11000); + + ret = regulator_disable(ctx->vcc); + if (ret) + dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); + + regcache_mark_dirty(ctx->regmap); +} + static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) { @@ -485,11 +528,15 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, __le16 le16val; u16 val; int ret; + int idx; + + if (!drm_bridge_enter(bridge, &idx)) + return; ret = regulator_enable(ctx->vcc); if (ret) { dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); - return; + goto err_exit; } /* Deassert reset */ @@ -632,7 +679,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); /* On failure, disable PLL again and exit. */ regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); - return; + goto err_add_action; } /* Trigger reset after CSR register update. */ @@ -640,6 +687,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, /* Wait for 10ms after soft reset as specified in datasheet */ usleep_range(10000, 12000); + +err_add_action: + devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx); +err_exit: + drm_bridge_exit(idx); } static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, @@ -647,6 +699,10 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, { struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); unsigned int pval; + int idx; + + if (!drm_bridge_enter(bridge, &idx)) + return; /* Clear all errors that got asserted during initialization. */ regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); @@ -666,32 +722,22 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, /* Use the polling task */ sn65dsi83_monitor_start(ctx); } + + drm_bridge_exit(idx); } static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, struct drm_atomic_state *state) { struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); - int ret; + int idx; - if (ctx->irq) { - /* Disable irq */ - regmap_write(ctx->regmap, REG_IRQ_EN, 0x0); - regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0); - } else { - /* Stop the polling task */ - sn65dsi83_monitor_stop(ctx); - } - - /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ - gpiod_set_value_cansleep(ctx->enable_gpio, 0); - usleep_range(10000, 11000); + if (!drm_bridge_enter(bridge, &idx)) + return; - ret = regulator_disable(ctx->vcc); - if (ret) - dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); + devm_release_action(ctx->dev, sn65dsi83_release_resources, ctx); - regcache_mark_dirty(ctx->regmap); + drm_bridge_exit(idx); } static enum drm_mode_status @@ -1012,7 +1058,7 @@ static void sn65dsi83_remove(struct i2c_client *client) { struct sn65dsi83 *ctx = i2c_get_clientdata(client); - drm_bridge_remove(&ctx->bridge); + drm_bridge_unplug(&ctx->bridge); } static const struct i2c_device_id sn65dsi83_id[] = { diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c b/drivers/gpu/drm/bridge/ti-tfp410.c index b80ee089f8801..11b5bb50e9f42 100644 --- a/drivers/gpu/drm/bridge/ti-tfp410.c +++ b/drivers/gpu/drm/bridge/ti-tfp410.c @@ -30,7 +30,6 @@ struct tfp410 { struct gpio_desc *powerdown; struct drm_bridge_timings timings; - struct drm_bridge *next_bridge; struct device *dev; }; @@ -53,8 +52,8 @@ static int tfp410_get_modes(struct drm_connector *connector) const struct drm_edid *drm_edid; int ret; - if (dvi->next_bridge->ops & DRM_BRIDGE_OP_EDID) { - drm_edid = drm_bridge_edid_read(dvi->next_bridge, connector); + if (dvi->bridge.next_bridge->ops & DRM_BRIDGE_OP_EDID) { + drm_edid = drm_bridge_edid_read(dvi->bridge.next_bridge, connector); if (!drm_edid) DRM_INFO("EDID read failed. Fallback to standard modes\n"); } else { @@ -89,7 +88,7 @@ tfp410_connector_detect(struct drm_connector *connector, bool force) { struct tfp410 *dvi = drm_connector_to_tfp410(connector); - return drm_bridge_detect(dvi->next_bridge, connector); + return drm_bridge_detect(dvi->bridge.next_bridge, connector); } static const struct drm_connector_funcs tfp410_con_funcs = { @@ -126,7 +125,7 @@ static int tfp410_attach(struct drm_bridge *bridge, struct tfp410 *dvi = drm_bridge_to_tfp410(bridge); int ret; - ret = drm_bridge_attach(encoder, dvi->next_bridge, bridge, + ret = drm_bridge_attach(encoder, dvi->bridge.next_bridge, bridge, DRM_BRIDGE_ATTACH_NO_CONNECTOR); if (ret < 0) return ret; @@ -134,14 +133,14 @@ static int tfp410_attach(struct drm_bridge *bridge, if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) return 0; - if (dvi->next_bridge->ops & DRM_BRIDGE_OP_DETECT) + if (dvi->bridge.next_bridge->ops & DRM_BRIDGE_OP_DETECT) dvi->connector.polled = DRM_CONNECTOR_POLL_HPD; else dvi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; - if (dvi->next_bridge->ops & DRM_BRIDGE_OP_HPD) { + if (dvi->bridge.next_bridge->ops & DRM_BRIDGE_OP_HPD) { INIT_DELAYED_WORK(&dvi->hpd_work, tfp410_hpd_work_func); - drm_bridge_hpd_enable(dvi->next_bridge, tfp410_hpd_callback, + drm_bridge_hpd_enable(dvi->bridge.next_bridge, tfp410_hpd_callback, dvi); } @@ -149,8 +148,8 @@ static int tfp410_attach(struct drm_bridge *bridge, &tfp410_con_helper_funcs); ret = drm_connector_init_with_ddc(bridge->dev, &dvi->connector, &tfp410_con_funcs, - dvi->next_bridge->type, - dvi->next_bridge->ddc); + dvi->bridge.next_bridge->type, + dvi->bridge.next_bridge->ddc); if (ret) { dev_err(dvi->dev, "drm_connector_init_with_ddc() failed: %d\n", ret); @@ -169,8 +168,8 @@ static void tfp410_detach(struct drm_bridge *bridge) { struct tfp410 *dvi = drm_bridge_to_tfp410(bridge); - if (dvi->connector.dev && dvi->next_bridge->ops & DRM_BRIDGE_OP_HPD) { - drm_bridge_hpd_disable(dvi->next_bridge); + if (dvi->connector.dev && dvi->bridge.next_bridge->ops & DRM_BRIDGE_OP_HPD) { + drm_bridge_hpd_disable(dvi->bridge.next_bridge); cancel_delayed_work_sync(&dvi->hpd_work); } } @@ -362,10 +361,10 @@ static int tfp410_init(struct device *dev, bool i2c) if (!node) return -ENODEV; - dvi->next_bridge = of_drm_find_bridge(node); + dvi->bridge.next_bridge = of_drm_find_and_get_bridge(node); of_node_put(node); - if (!dvi->next_bridge) + if (!dvi->bridge.next_bridge) return -EPROBE_DEFER; /* Get the powerdown GPIO. */ diff --git a/drivers/gpu/drm/bridge/ti-tpd12s015.c b/drivers/gpu/drm/bridge/ti-tpd12s015.c index dcf686c4e73d4..136e47ad1a10d 100644 --- a/drivers/gpu/drm/bridge/ti-tpd12s015.c +++ b/drivers/gpu/drm/bridge/ti-tpd12s015.c @@ -28,8 +28,6 @@ struct tpd12s015_device { struct gpio_desc *ls_oe_gpio; struct gpio_desc *hpd_gpio; int hpd_irq; - - struct drm_bridge *next_bridge; }; static inline struct tpd12s015_device *to_tpd12s015(struct drm_bridge *bridge) @@ -47,7 +45,7 @@ static int tpd12s015_attach(struct drm_bridge *bridge, if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) return -EINVAL; - ret = drm_bridge_attach(encoder, tpd->next_bridge, + ret = drm_bridge_attach(encoder, tpd->bridge.next_bridge, bridge, flags); if (ret < 0) return ret; @@ -138,10 +136,10 @@ static int tpd12s015_probe(struct platform_device *pdev) if (!node) return -ENODEV; - tpd->next_bridge = of_drm_find_bridge(node); + tpd->bridge.next_bridge = of_drm_find_and_get_bridge(node); of_node_put(node); - if (!tpd->next_bridge) + if (!tpd->bridge.next_bridge) return -EPROBE_DEFER; /* Get the control and HPD GPIOs. */ diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt index e4a8f8352cd65..ae36a39619c69 100644 --- a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt +++ b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-kingoftown-fails.txt @@ -6,12 +6,16 @@ kms_color@ctm-green-to-red,Fail kms_color@ctm-negative,Fail kms_color@ctm-red-to-blue,Fail kms_color@ctm-signed,Fail +kms_color@gamma,Fail +kms_color@legacy-gamma,Fail kms_cursor_legacy@cursor-vs-flip-toggle,Fail kms_cursor_legacy@cursor-vs-flip-varying-size,Fail kms_flip@flip-vs-modeset-vs-hang,Fail kms_flip@flip-vs-panning-vs-hang,Fail kms_lease@lease-uevent,Fail kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail +kms_plane@pixel-format,Fail +kms_plane@pixel-format-source-clamping,Fail kms_plane_alpha_blend@alpha-7efc,Fail kms_plane_alpha_blend@coverage-7efc,Fail kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt index e4a8f8352cd65..ae36a39619c69 100644 --- a/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt +++ b/drivers/gpu/drm/ci/xfails/msm-sc7180-trogdor-lazor-limozeen-fails.txt @@ -6,12 +6,16 @@ kms_color@ctm-green-to-red,Fail kms_color@ctm-negative,Fail kms_color@ctm-red-to-blue,Fail kms_color@ctm-signed,Fail +kms_color@gamma,Fail +kms_color@legacy-gamma,Fail kms_cursor_legacy@cursor-vs-flip-toggle,Fail kms_cursor_legacy@cursor-vs-flip-varying-size,Fail kms_flip@flip-vs-modeset-vs-hang,Fail kms_flip@flip-vs-panning-vs-hang,Fail kms_lease@lease-uevent,Fail kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail +kms_plane@pixel-format,Fail +kms_plane@pixel-format-source-clamping,Fail kms_plane_alpha_blend@alpha-7efc,Fail kms_plane_alpha_blend@coverage-7efc,Fail kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail diff --git a/drivers/gpu/drm/clients/drm_log.c b/drivers/gpu/drm/clients/drm_log.c index 4d3005273b278..2bd5189c967e1 100644 --- a/drivers/gpu/drm/clients/drm_log.c +++ b/drivers/gpu/drm/clients/drm_log.c @@ -182,7 +182,7 @@ static u32 drm_log_find_usable_format(struct drm_plane *plane) int i; for (i = 0; i < plane->format_count; i++) - if (drm_draw_color_from_xrgb8888(0xffffff, plane->format_types[i]) != 0) + if (drm_draw_can_convert_from_xrgb8888(plane->format_types[i])) return plane->format_types[i]; return DRM_FORMAT_INVALID; } diff --git a/drivers/gpu/drm/display/drm_bridge_connector.c b/drivers/gpu/drm/display/drm_bridge_connector.c index a2d30cf9e06df..258132c6b8b56 100644 --- a/drivers/gpu/drm/display/drm_bridge_connector.c +++ b/drivers/gpu/drm/display/drm_bridge_connector.c @@ -123,6 +123,14 @@ struct drm_bridge_connector { * DRM_BRIDGE_OP_HDMI_CEC_NOTIFIER). */ struct drm_bridge *bridge_hdmi_cec; + + /** + * @hdmi_funcs: + * + * The particular &drm_connector_hdmi_funcs implementation for this + * bridge connector. + */ + struct drm_connector_hdmi_funcs hdmi_funcs; }; #define to_drm_bridge_connector(x) \ @@ -141,7 +149,7 @@ static void drm_bridge_connector_hpd_notify(struct drm_connector *connector, /* Notify all bridges in the pipeline of hotplug events. */ drm_for_each_bridge_in_chain_scoped(bridge_connector->encoder, bridge) { if (bridge->funcs->hpd_notify) - bridge->funcs->hpd_notify(bridge, status); + bridge->funcs->hpd_notify(bridge, connector, status); } } @@ -401,8 +409,102 @@ drm_bridge_connector_tmds_char_rate_valid(const struct drm_connector *connector, return MODE_OK; } -static int drm_bridge_connector_clear_infoframe(struct drm_connector *connector, - enum hdmi_infoframe_type type) +static int drm_bridge_connector_clear_avi_infoframe(struct drm_connector *connector) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_clear_avi_infoframe(bridge); +} + +static int drm_bridge_connector_write_avi_infoframe(struct drm_connector *connector, + const u8 *buffer, size_t len) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_write_avi_infoframe(bridge, buffer, len); +} + +static int drm_bridge_connector_clear_hdmi_infoframe(struct drm_connector *connector) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_clear_hdmi_infoframe(bridge); +} + +static int drm_bridge_connector_write_hdmi_infoframe(struct drm_connector *connector, + const u8 *buffer, size_t len) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_write_hdmi_infoframe(bridge, buffer, len); +} + +static int drm_bridge_connector_clear_audio_infoframe(struct drm_connector *connector) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_clear_audio_infoframe(bridge); +} + +static int drm_bridge_connector_write_audio_infoframe(struct drm_connector *connector, + const u8 *buffer, size_t len) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_write_audio_infoframe(bridge, buffer, len); +} + +static int drm_bridge_connector_clear_hdr_drm_infoframe(struct drm_connector *connector) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_clear_hdr_drm_infoframe(bridge); +} + +static int drm_bridge_connector_write_hdr_drm_infoframe(struct drm_connector *connector, + const u8 *buffer, size_t len) { struct drm_bridge_connector *bridge_connector = to_drm_bridge_connector(connector); @@ -412,12 +514,10 @@ static int drm_bridge_connector_clear_infoframe(struct drm_connector *connector, if (!bridge) return -EINVAL; - return bridge->funcs->hdmi_clear_infoframe(bridge, type); + return bridge->funcs->hdmi_write_hdr_drm_infoframe(bridge, buffer, len); } -static int drm_bridge_connector_write_infoframe(struct drm_connector *connector, - enum hdmi_infoframe_type type, - const u8 *buffer, size_t len) +static int drm_bridge_connector_clear_spd_infoframe(struct drm_connector *connector) { struct drm_bridge_connector *bridge_connector = to_drm_bridge_connector(connector); @@ -427,7 +527,21 @@ static int drm_bridge_connector_write_infoframe(struct drm_connector *connector, if (!bridge) return -EINVAL; - return bridge->funcs->hdmi_write_infoframe(bridge, type, buffer, len); + return bridge->funcs->hdmi_clear_spd_infoframe(bridge); +} + +static int drm_bridge_connector_write_spd_infoframe(struct drm_connector *connector, + const u8 *buffer, size_t len) +{ + struct drm_bridge_connector *bridge_connector = + to_drm_bridge_connector(connector); + struct drm_bridge *bridge; + + bridge = bridge_connector->bridge_hdmi; + if (!bridge) + return -EINVAL; + + return bridge->funcs->hdmi_write_spd_infoframe(bridge, buffer, len); } static const struct drm_edid * @@ -446,9 +560,31 @@ drm_bridge_connector_read_edid(struct drm_connector *connector) static const struct drm_connector_hdmi_funcs drm_bridge_connector_hdmi_funcs = { .tmds_char_rate_valid = drm_bridge_connector_tmds_char_rate_valid, - .clear_infoframe = drm_bridge_connector_clear_infoframe, - .write_infoframe = drm_bridge_connector_write_infoframe, .read_edid = drm_bridge_connector_read_edid, + .avi = { + .clear_infoframe = drm_bridge_connector_clear_avi_infoframe, + .write_infoframe = drm_bridge_connector_write_avi_infoframe, + }, + .hdmi = { + .clear_infoframe = drm_bridge_connector_clear_hdmi_infoframe, + .write_infoframe = drm_bridge_connector_write_hdmi_infoframe, + }, + /* audio, hdr_drm and spd are set dynamically during init */ +}; + +static const struct drm_connector_infoframe_funcs drm_bridge_connector_hdmi_audio_infoframe = { + .clear_infoframe = drm_bridge_connector_clear_audio_infoframe, + .write_infoframe = drm_bridge_connector_write_audio_infoframe, +}; + +static const struct drm_connector_infoframe_funcs drm_bridge_connector_hdmi_hdr_drm_infoframe = { + .clear_infoframe = drm_bridge_connector_clear_hdr_drm_infoframe, + .write_infoframe = drm_bridge_connector_write_hdr_drm_infoframe, +}; + +static const struct drm_connector_infoframe_funcs drm_bridge_connector_hdmi_spd_infoframe = { + .clear_infoframe = drm_bridge_connector_clear_spd_infoframe, + .write_infoframe = drm_bridge_connector_write_spd_infoframe, }; static int drm_bridge_connector_audio_startup(struct drm_connector *connector) @@ -709,8 +845,25 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, if (bridge->ops & DRM_BRIDGE_OP_HDMI) { if (bridge_connector->bridge_hdmi) return ERR_PTR(-EBUSY); - if (!bridge->funcs->hdmi_write_infoframe || - !bridge->funcs->hdmi_clear_infoframe) + if (!bridge->funcs->hdmi_write_avi_infoframe || + !bridge->funcs->hdmi_clear_avi_infoframe || + !bridge->funcs->hdmi_write_hdmi_infoframe || + !bridge->funcs->hdmi_clear_hdmi_infoframe) + return ERR_PTR(-EINVAL); + + if (bridge->ops & DRM_BRIDGE_OP_HDMI_AUDIO && + (!bridge->funcs->hdmi_write_audio_infoframe || + !bridge->funcs->hdmi_clear_audio_infoframe)) + return ERR_PTR(-EINVAL); + + if (bridge->ops & DRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME && + (!bridge->funcs->hdmi_write_hdr_drm_infoframe || + !bridge->funcs->hdmi_clear_hdr_drm_infoframe)) + return ERR_PTR(-EINVAL); + + if (bridge->ops & DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME && + (!bridge->funcs->hdmi_write_spd_infoframe || + !bridge->funcs->hdmi_clear_spd_infoframe)) return ERR_PTR(-EINVAL); bridge_connector->bridge_hdmi = drm_bridge_get(bridge); @@ -803,11 +956,25 @@ struct drm_connector *drm_bridge_connector_init(struct drm_device *drm, if (!connector->ycbcr_420_allowed) supported_formats &= ~BIT(HDMI_COLORSPACE_YUV420); + bridge_connector->hdmi_funcs = drm_bridge_connector_hdmi_funcs; + + if (bridge_connector->bridge_hdmi->ops & DRM_BRIDGE_OP_HDMI_AUDIO) + bridge_connector->hdmi_funcs.audio = + drm_bridge_connector_hdmi_audio_infoframe; + + if (bridge_connector->bridge_hdmi->ops & DRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME) + bridge_connector->hdmi_funcs.hdr_drm = + drm_bridge_connector_hdmi_hdr_drm_infoframe; + + if (bridge_connector->bridge_hdmi->ops & DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME) + bridge_connector->hdmi_funcs.spd = + drm_bridge_connector_hdmi_spd_infoframe; + ret = drmm_connector_hdmi_init(drm, connector, bridge_connector->bridge_hdmi->vendor, bridge_connector->bridge_hdmi->product, &drm_bridge_connector_funcs, - &drm_bridge_connector_hdmi_funcs, + &bridge_connector->hdmi_funcs, connector_type, ddc, supported_formats, max_bpc); diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c index f9fdf19de74a9..a697cc227e289 100644 --- a/drivers/gpu/drm/display/drm_dp_helper.c +++ b/drivers/gpu/drm/display/drm_dp_helper.c @@ -2704,6 +2704,71 @@ u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) } EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); +/** + * drm_dp_dsc_slice_count_to_mask() - Convert a slice count to a slice count mask + * @slice_count: slice count + * + * Convert @slice_count to a slice count mask. + * + * Returns the slice count mask. + */ +u32 drm_dp_dsc_slice_count_to_mask(int slice_count) +{ + return BIT(slice_count - 1); +} +EXPORT_SYMBOL(drm_dp_dsc_slice_count_to_mask); + +/** + * drm_dp_dsc_sink_slice_count_mask() - Get the mask of valid DSC sink slice counts + * @dsc_dpcd: the sink's DSC DPCD capabilities + * @is_edp: %true for an eDP sink + * + * Get the mask of supported slice counts from the sink's DSC DPCD register. + * + * Returns: + * Mask of slice counts supported by the DSC sink: + * - > 0: bit#0,1,3,5..,23 set if the sink supports 1,2,4,6..,24 slices + * - 0: if the sink doesn't support any slices + */ +u32 drm_dp_dsc_sink_slice_count_mask(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], + bool is_edp) +{ + u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; + u32 mask = 0; + + if (!is_edp) { + /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ + u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; + + if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(24); + if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(20); + if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(16); + } + + /* DP, eDP v1.5+ */ + if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(12); + if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(10); + if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(8); + if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(6); + /* DP, eDP v1.4+ */ + if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(4); + if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(2); + if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) + mask |= drm_dp_dsc_slice_count_to_mask(1); + + return mask; +} +EXPORT_SYMBOL(drm_dp_dsc_sink_slice_count_mask); + /** * drm_dp_dsc_sink_max_slice_count() - Get the max slice count * supported by the DSC sink. @@ -2723,43 +2788,7 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], bool is_edp) { - u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; - - if (is_edp) { - /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ - if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) - return 4; - if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) - return 2; - if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) - return 1; - } else { - /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ - u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; - - if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) - return 24; - if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) - return 20; - if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) - return 16; - if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) - return 12; - if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) - return 10; - if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) - return 8; - if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) - return 6; - if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) - return 4; - if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) - return 2; - if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) - return 1; - } - - return 0; + return fls(drm_dp_dsc_sink_slice_count_mask(dsc_dpcd, is_edp)); } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index 64e5c176d5cce..be749dcad3b58 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -4572,7 +4572,8 @@ int drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, if (!payload->delete) { payload->pbn = 0; payload->delete = true; - topology_state->payload_mask &= ~BIT(payload->vcpi - 1); + if (payload->vcpi > 0) + topology_state->payload_mask &= ~BIT(payload->vcpi - 1); } return 0; diff --git a/drivers/gpu/drm/display/drm_hdmi_state_helper.c b/drivers/gpu/drm/display/drm_hdmi_state_helper.c index a561f124be99a..a1d16762ac7a9 100644 --- a/drivers/gpu/drm/display/drm_hdmi_state_helper.c +++ b/drivers/gpu/drm/display/drm_hdmi_state_helper.c @@ -718,6 +718,9 @@ static int hdmi_generate_spd_infoframe(const struct drm_connector *connector, infoframe->set = false; + if (!connector->hdmi.funcs->spd.write_infoframe) + return 0; + ret = hdmi_spd_infoframe_init(frame, connector->hdmi.vendor, connector->hdmi.product); @@ -742,6 +745,9 @@ static int hdmi_generate_hdr_infoframe(const struct drm_connector *connector, infoframe->set = false; + if (!connector->hdmi.funcs->hdr_drm.write_infoframe) + return 0; + if (connector->max_bpc < 10) return 0; @@ -891,21 +897,21 @@ drm_hdmi_connector_mode_valid(struct drm_connector *connector, } EXPORT_SYMBOL(drm_hdmi_connector_mode_valid); -static int clear_device_infoframe(struct drm_connector *connector, - enum hdmi_infoframe_type type) +static int clear_infoframe(struct drm_connector *connector, + const struct drm_connector_infoframe_funcs *funcs, + const char *type) { - const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; struct drm_device *dev = connector->dev; int ret; - drm_dbg_kms(dev, "Clearing infoframe type 0x%x\n", type); + drm_dbg_kms(dev, "Clearing %s InfoFrame\n", type); - if (!funcs || !funcs->clear_infoframe) { + if (!funcs->clear_infoframe) { drm_dbg_kms(dev, "Function not implemented, bailing.\n"); - return 0; + return -EOPNOTSUPP; } - ret = funcs->clear_infoframe(connector, type); + ret = funcs->clear_infoframe(connector); if (ret) { drm_dbg_kms(dev, "Call failed: %d\n", ret); return ret; @@ -914,39 +920,28 @@ static int clear_device_infoframe(struct drm_connector *connector, return 0; } -static int clear_infoframe(struct drm_connector *connector, - struct drm_connector_hdmi_infoframe *old_frame) -{ - int ret; - - ret = clear_device_infoframe(connector, old_frame->data.any.type); - if (ret) - return ret; - - return 0; -} - -static int write_device_infoframe(struct drm_connector *connector, - union hdmi_infoframe *frame) +static int write_infoframe(struct drm_connector *connector, + const struct drm_connector_infoframe_funcs *funcs, + const char *type, + struct drm_connector_hdmi_infoframe *new_frame) { - const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; struct drm_device *dev = connector->dev; u8 buffer[HDMI_INFOFRAME_SIZE(MAX)]; int ret; int len; - drm_dbg_kms(dev, "Writing infoframe type %x\n", frame->any.type); + drm_dbg_kms(dev, "Writing %s InfoFrame\n", type); - if (!funcs || !funcs->write_infoframe) { + if (!funcs->write_infoframe) { drm_dbg_kms(dev, "Function not implemented, bailing.\n"); - return -EINVAL; + return -EOPNOTSUPP; } - len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); + len = hdmi_infoframe_pack(&new_frame->data, buffer, sizeof(buffer)); if (len < 0) return len; - ret = funcs->write_infoframe(connector, frame->any.type, buffer, len); + ret = funcs->write_infoframe(connector, buffer, len); if (ret) { drm_dbg_kms(dev, "Call failed: %d\n", ret); return ret; @@ -955,27 +950,17 @@ static int write_device_infoframe(struct drm_connector *connector, return 0; } -static int write_infoframe(struct drm_connector *connector, - struct drm_connector_hdmi_infoframe *new_frame) -{ - int ret; - - ret = write_device_infoframe(connector, &new_frame->data); - if (ret) - return ret; - - return 0; -} - static int write_or_clear_infoframe(struct drm_connector *connector, + const struct drm_connector_infoframe_funcs *funcs, + const char *type, struct drm_connector_hdmi_infoframe *old_frame, struct drm_connector_hdmi_infoframe *new_frame) { if (new_frame->set) - return write_infoframe(connector, new_frame); + return write_infoframe(connector, funcs, type, new_frame); if (old_frame->set && !new_frame->set) - return clear_infoframe(connector, old_frame); + return clear_infoframe(connector, funcs, type); return 0; } @@ -995,6 +980,7 @@ static int write_or_clear_infoframe(struct drm_connector *connector, int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *connector, struct drm_atomic_state *state) { + const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; struct drm_connector_state *old_conn_state = drm_atomic_get_old_connector_state(state, connector); struct drm_connector_state *new_conn_state = @@ -1005,9 +991,15 @@ int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *con if (!info->is_hdmi) return 0; + if (!funcs) { + drm_dbg_kms(connector->dev, "Function not implemented, bailing.\n"); + return -EINVAL; + } + mutex_lock(&connector->hdmi.infoframes.lock); ret = write_or_clear_infoframe(connector, + &funcs->avi, "AVI", &old_conn_state->hdmi.infoframes.avi, &new_conn_state->hdmi.infoframes.avi); if (ret) @@ -1015,18 +1007,21 @@ int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *con if (connector->hdmi.infoframes.audio.set) { ret = write_infoframe(connector, + &funcs->audio, "Audio", &connector->hdmi.infoframes.audio); if (ret) goto out; } ret = write_or_clear_infoframe(connector, + &funcs->hdr_drm, "HDR DRM", &old_conn_state->hdmi.infoframes.hdr_drm, &new_conn_state->hdmi.infoframes.hdr_drm); if (ret) goto out; ret = write_or_clear_infoframe(connector, + &funcs->spd, "SPD", &old_conn_state->hdmi.infoframes.spd, &new_conn_state->hdmi.infoframes.spd); if (ret) @@ -1034,6 +1029,7 @@ int drm_atomic_helper_connector_hdmi_update_infoframes(struct drm_connector *con if (info->has_hdmi_infoframe) { ret = write_or_clear_infoframe(connector, + &funcs->hdmi, "HDMI-VS", &old_conn_state->hdmi.infoframes.hdmi, &new_conn_state->hdmi.infoframes.hdmi); if (ret) @@ -1062,6 +1058,7 @@ int drm_atomic_helper_connector_hdmi_update_audio_infoframe(struct drm_connector *connector, struct hdmi_audio_infoframe *frame) { + const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; struct drm_connector_hdmi_infoframe *infoframe = &connector->hdmi.infoframes.audio; struct drm_display_info *info = &connector->display_info; @@ -1070,12 +1067,17 @@ drm_atomic_helper_connector_hdmi_update_audio_infoframe(struct drm_connector *co if (!info->is_hdmi) return 0; + if (!funcs || !funcs->audio.write_infoframe) { + drm_dbg_kms(connector->dev, "Function not implemented, bailing.\n"); + return -EINVAL; + } + mutex_lock(&connector->hdmi.infoframes.lock); memcpy(&infoframe->data, frame, sizeof(infoframe->data)); infoframe->set = true; - ret = write_infoframe(connector, infoframe); + ret = write_infoframe(connector, &funcs->audio, "Audio", infoframe); mutex_unlock(&connector->hdmi.infoframes.lock); @@ -1097,6 +1099,7 @@ EXPORT_SYMBOL(drm_atomic_helper_connector_hdmi_update_audio_infoframe); int drm_atomic_helper_connector_hdmi_clear_audio_infoframe(struct drm_connector *connector) { + const struct drm_connector_hdmi_funcs *funcs = connector->hdmi.funcs; struct drm_connector_hdmi_infoframe *infoframe = &connector->hdmi.infoframes.audio; struct drm_display_info *info = &connector->display_info; @@ -1105,11 +1108,16 @@ drm_atomic_helper_connector_hdmi_clear_audio_infoframe(struct drm_connector *con if (!info->is_hdmi) return 0; + if (!funcs || !funcs->audio.write_infoframe) { + drm_dbg_kms(connector->dev, "Function not implemented, bailing.\n"); + return -EINVAL; + } + mutex_lock(&connector->hdmi.infoframes.lock); infoframe->set = false; - ret = clear_infoframe(connector, infoframe); + ret = clear_infoframe(connector, &funcs->audio, "Audio"); memset(&infoframe->data, 0, sizeof(infoframe->data)); diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 67e095e398a34..52738b80ddbeb 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -641,6 +641,38 @@ drm_atomic_get_colorop_state(struct drm_atomic_state *state, } EXPORT_SYMBOL(drm_atomic_get_colorop_state); +/** + * drm_atomic_get_old_colorop_state - get colorop state, if it exists + * @state: global atomic state object + * @colorop: colorop to grab + * + * This function returns the old colorop state for the given colorop, or + * NULL if the colorop is not part of the global atomic state. + */ +struct drm_colorop_state * +drm_atomic_get_old_colorop_state(struct drm_atomic_state *state, + struct drm_colorop *colorop) +{ + return state->colorops[drm_colorop_index(colorop)].old_state; +} +EXPORT_SYMBOL(drm_atomic_get_old_colorop_state); + +/** + * drm_atomic_get_new_colorop_state - get colorop state, if it exists + * @state: global atomic state object + * @colorop: colorop to grab + * + * This function returns the new colorop state for the given colorop, or + * NULL if the colorop is not part of the global atomic state. + */ +struct drm_colorop_state * +drm_atomic_get_new_colorop_state(struct drm_atomic_state *state, + struct drm_colorop *colorop) +{ + return state->colorops[drm_colorop_index(colorop)].new_state; +} +EXPORT_SYMBOL(drm_atomic_get_new_colorop_state); + static bool plane_switching_crtc(const struct drm_plane_state *old_plane_state, const struct drm_plane_state *new_plane_state) @@ -906,6 +938,7 @@ drm_atomic_private_obj_init(struct drm_device *dev, drm_modeset_lock_init(&obj->lock); + obj->dev = dev; obj->state = state; obj->funcs = funcs; list_add_tail(&obj->head, &dev->mode_config.privobj_list); diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 5beea645035f2..cc1f0c102414f 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c index 7320db4b8489f..dc013a22bf265 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -413,10 +413,19 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, } else if (property == config->prop_vrr_enabled) { state->vrr_enabled = val; } else if (property == config->degamma_lut_property) { + const size_t elem_size = sizeof(struct drm_color_lut); + u64 lut_size; + + ret = drm_object_immutable_property_get_value(&crtc->base, + config->degamma_lut_size_property, + &lut_size); + if (ret) + return ret; + ret = drm_property_replace_blob_from_id(dev, &state->degamma_lut, val, - -1, sizeof(struct drm_color_lut), + elem_size * lut_size, -1, elem_size, &replaced); state->color_mgmt_changed |= replaced; return ret; @@ -424,15 +433,24 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, ret = drm_property_replace_blob_from_id(dev, &state->ctm, val, - sizeof(struct drm_color_ctm), -1, + -1, sizeof(struct drm_color_ctm), -1, &replaced); state->color_mgmt_changed |= replaced; return ret; } else if (property == config->gamma_lut_property) { + const size_t elem_size = sizeof(struct drm_color_lut); + u64 lut_size; + + ret = drm_object_immutable_property_get_value(&crtc->base, + config->gamma_lut_size_property, + &lut_size); + if (ret) + return ret; + ret = drm_property_replace_blob_from_id(dev, &state->gamma_lut, val, - -1, sizeof(struct drm_color_lut), + elem_size * lut_size, -1, elem_size, &replaced); state->color_mgmt_changed |= replaced; return ret; @@ -587,8 +605,7 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, ret = drm_property_replace_blob_from_id(dev, &state->fb_damage_clips, val, - -1, - sizeof(struct drm_mode_rect), + -1, -1, sizeof(struct drm_mode_rect), &replaced); return ret; } else if (property == plane->scaling_filter_property) { @@ -717,8 +734,7 @@ static int drm_atomic_color_set_data_property(struct drm_colorop *colorop, return drm_property_replace_blob_from_id(colorop->dev, &state->data, val, - size, - elem_size, + -1, size, elem_size, &replaced); } @@ -876,7 +892,7 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, ret = drm_property_replace_blob_from_id(dev, &state->hdr_output_metadata, val, - sizeof(struct hdr_output_metadata), -1, + -1, sizeof(struct hdr_output_metadata), -1, &replaced); return ret; } else if (property == config->aspect_ratio_property) { diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 8f355df883d8a..3b165a0d1e779 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -202,6 +203,67 @@ static DEFINE_MUTEX(bridge_lock); static LIST_HEAD(bridge_list); static LIST_HEAD(bridge_lingering_list); +DEFINE_STATIC_SRCU(drm_bridge_unplug_srcu); + +/** + * drm_bridge_enter - Enter DRM bridge critical section + * @bridge: DRM bridge + * @idx: Pointer to index that will be passed to the matching drm_bridge_exit() + * + * This function marks and protects the beginning of a section that should not + * be entered after the bridge has been unplugged. The section end is marked + * with drm_bridge_exit(). Calls to this function can be nested. + * + * Returns: + * True if it is OK to enter the section, false otherwise. + */ +bool drm_bridge_enter(struct drm_bridge *bridge, int *idx) +{ + *idx = srcu_read_lock(&drm_bridge_unplug_srcu); + + if (bridge->unplugged) { + srcu_read_unlock(&drm_bridge_unplug_srcu, *idx); + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_bridge_enter); + +/** + * drm_bridge_exit - Exit DRM bridge critical section + * @idx: index returned by drm_bridge_enter() + * + * This function marks the end of a section that should not be entered after + * the bridge has been unplugged. + */ +void drm_bridge_exit(int idx) +{ + srcu_read_unlock(&drm_bridge_unplug_srcu, idx); +} +EXPORT_SYMBOL(drm_bridge_exit); + +/** + * drm_bridge_unplug - declare a DRM bridge was unplugged and remove it + * @bridge: DRM bridge + * + * This tells the bridge has been physically unplugged and no operations on + * device resources must be done anymore. Entry-points can use + * drm_bridge_enter() and drm_bridge_exit() to protect device resources in + * a race free manner. + * + * Also unregisters the bridge. + */ +void drm_bridge_unplug(struct drm_bridge *bridge) +{ + bridge->unplugged = true; + + synchronize_srcu(&drm_bridge_unplug_srcu); + + drm_bridge_remove(bridge); +} +EXPORT_SYMBOL(drm_bridge_unplug); + static void __drm_bridge_free(struct kref *kref) { struct drm_bridge *bridge = container_of(kref, struct drm_bridge, refcount); @@ -213,6 +275,8 @@ static void __drm_bridge_free(struct kref *kref) if (bridge->funcs->destroy) bridge->funcs->destroy(bridge); + drm_bridge_put(bridge->next_bridge); + kfree(bridge->container); } @@ -299,7 +363,7 @@ EXPORT_SYMBOL(__devm_drm_bridge_alloc); * @bridge: bridge control structure * * Add the given bridge to the global list of bridges, where they can be - * found by users via of_drm_find_bridge(). + * found by users via of_drm_find_and_get_bridge(). * * The bridge to be added must have been allocated by * devm_drm_bridge_alloc(). @@ -360,9 +424,9 @@ EXPORT_SYMBOL(devm_drm_bridge_add); * @bridge: bridge control structure * * Remove the given bridge from the global list of registered bridges, so - * it won't be found by users via of_drm_find_bridge(), and add it to the - * lingering bridge list, to keep track of it until its allocated memory is - * eventually freed. + * it won't be found by users via of_drm_find_and_get_bridge(), and add it + * to the lingering bridge list, to keep track of it until its allocated + * memory is eventually freed. */ void drm_bridge_remove(struct drm_bridge *bridge) { @@ -1417,30 +1481,70 @@ void drm_bridge_hpd_notify(struct drm_bridge *bridge, EXPORT_SYMBOL_GPL(drm_bridge_hpd_notify); #ifdef CONFIG_OF +/** + * of_drm_find_and_get_bridge - find the bridge corresponding to the device + * node in the global bridge list + * @np: device node + * + * The refcount of the returned bridge is incremented. Use drm_bridge_put() + * when done with it. + * + * RETURNS: + * drm_bridge control struct on success, NULL on failure + */ +struct drm_bridge *of_drm_find_and_get_bridge(struct device_node *np) +{ + struct drm_bridge *bridge; + + scoped_guard(mutex, &bridge_lock) { + list_for_each_entry(bridge, &bridge_list, list) + if (bridge->of_node == np) + return drm_bridge_get(bridge); + } + + return NULL; +} +EXPORT_SYMBOL(of_drm_find_and_get_bridge); + /** * of_drm_find_bridge - find the bridge corresponding to the device node in * the global bridge list * * @np: device node * + * This function is deprecated. Convert to of_drm_find_and_get_bridge() + * instead for proper refcounting. + * + * The bridge returned by this function is not refcounted. This is + * dangerous because the bridge might be deallocated even before the caller + * has a chance to use it. To use this function you have to do one of: + * + * - get a reference with drm_bridge_get() as soon as possible to + * minimize the race window, and then drm_bridge_put() when no longer + * using the pointer + * + * - not call drm_bridge_get() or drm_bridge_put() at all, which used to + * be the correct practice before dynamic bridge lifetime was introduced + * + * - again, convert to of_drm_find_and_get_bridge(), which is the only safe + * thing to do + * * RETURNS: * drm_bridge control struct on success, NULL on failure */ struct drm_bridge *of_drm_find_bridge(struct device_node *np) { - struct drm_bridge *bridge; - - mutex_lock(&bridge_lock); + struct drm_bridge *bridge = of_drm_find_and_get_bridge(np); - list_for_each_entry(bridge, &bridge_list, list) { - if (bridge->of_node == np) { - mutex_unlock(&bridge_lock); - return bridge; - } - } + /* + * We need to emulate the original semantics of + * of_drm_find_bridge(), which was not getting any bridge + * reference. Being now based on of_drm_find_and_get_bridge() which + * gets a reference, put it before returning. + */ + drm_bridge_put(bridge); - mutex_unlock(&bridge_lock); - return NULL; + return bridge; } EXPORT_SYMBOL(of_drm_find_bridge); #endif diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index 2f279b46bd2cf..fd34d3755f7c5 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -420,6 +420,7 @@ void drm_buddy_fini(struct drm_buddy *mm) for_each_free_tree(i) kfree(mm->free_trees[i]); + kfree(mm->free_trees); kfree(mm->roots); } EXPORT_SYMBOL(drm_buddy_fini); @@ -1155,6 +1156,15 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, order = fls(pages) - 1; min_order = ilog2(min_block_size) - ilog2(mm->chunk_size); + if (order > mm->max_order || size > mm->size) { + if ((flags & DRM_BUDDY_CONTIGUOUS_ALLOCATION) && + !(flags & DRM_BUDDY_RANGE_ALLOCATION)) + return __alloc_contig_try_harder(mm, original_size, + original_min_size, blocks); + + return -EINVAL; + } + do { order = min(order, (unsigned int)fls(pages) - 1); BUG_ON(order > mm->max_order); diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 4d6dc9ebfdb5b..aec05adbc8894 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -600,6 +600,12 @@ int drmm_connector_hdmi_init(struct drm_device *dev, if (!(max_bpc == 8 || max_bpc == 10 || max_bpc == 12)) return -EINVAL; + if (!hdmi_funcs->avi.clear_infoframe || + !hdmi_funcs->avi.write_infoframe || + !hdmi_funcs->hdmi.clear_infoframe || + !hdmi_funcs->hdmi.write_infoframe) + return -EINVAL; + ret = drmm_connector_init(dev, connector, funcs, connector_type, ddc); if (ret) return ret; @@ -1167,6 +1173,11 @@ static const struct drm_prop_enum_list drm_link_status_enum_list[] = { { DRM_MODE_LINK_STATUS_BAD, "Bad" }, }; +static const struct drm_prop_enum_list drm_panel_type_enum_list[] = { + { DRM_MODE_PANEL_TYPE_UNKNOWN, "unknown" }, + { DRM_MODE_PANEL_TYPE_OLED, "OLED" }, +}; + /** * drm_display_info_set_bus_formats - set the supported bus formats * @info: display info to store bus formats in @@ -1495,6 +1506,9 @@ EXPORT_SYMBOL(drm_hdmi_connector_get_output_format_name); * Summarizing: Only set "DPMS" when the connector is known to be enabled, * assume that a successful SETCONFIG call also sets "DPMS" to on, and * never read back the value of "DPMS" because it can be incorrect. + * panel_type: + * Immutable enum property to indicate the type of connected panel. + * Possible values are "unknown" (default) and "OLED". * PATH: * Connector path property to identify how this sink is physically * connected. Used by DP MST. This should be set by calling @@ -1845,6 +1859,13 @@ int drm_connector_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.link_status_property = prop; + prop = drm_property_create_enum(dev, DRM_MODE_PROP_IMMUTABLE, "panel_type", + drm_panel_type_enum_list, + ARRAY_SIZE(drm_panel_type_enum_list)); + if (!prop) + return -ENOMEM; + dev->mode_config.panel_type_property = prop; + prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop"); if (!prop) return -ENOMEM; @@ -3620,3 +3641,21 @@ struct drm_tile_group *drm_mode_create_tile_group(struct drm_device *dev, return tg; } EXPORT_SYMBOL(drm_mode_create_tile_group); + +/** + * drm_connector_attach_panel_type_property - attaches panel type property + * @connector: connector to attach the property on. + * + * This is used to add support for panel type detection. + */ +void drm_connector_attach_panel_type_property(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.panel_type_property; + + if (!prop) + return; + + drm_object_attach_property(&connector->base, prop, DRM_MODE_PANEL_TYPE_UNKNOWN); +} +EXPORT_SYMBOL(drm_connector_attach_panel_type_property); diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c index 365cf337529fa..ae1c6126c2c59 100644 --- a/drivers/gpu/drm/drm_debugfs.c +++ b/drivers/gpu/drm/drm_debugfs.c @@ -672,6 +672,10 @@ static int create_hdmi_audio_infoframe_file(struct drm_connector *connector, { struct dentry *file; + if (!connector->hdmi.funcs || + !connector->hdmi.funcs->audio.write_infoframe) + return 0; + file = debugfs_create_file("audio", 0400, parent, connector, &audio_infoframe_fops); if (IS_ERR(file)) return PTR_ERR(file); @@ -726,6 +730,9 @@ static int create_hdmi_## _f ## _infoframe_file(struct drm_connector *connector, { \ struct dentry *file; \ \ + if (!connector->hdmi.funcs || \ + !connector->hdmi.funcs->_f.write_infoframe) \ + return 0; \ file = debugfs_create_file(#_f, 0400, parent, connector, &_f ## _infoframe_fops); \ if (IS_ERR(file)) \ return PTR_ERR(file); \ diff --git a/drivers/gpu/drm/drm_draw.c b/drivers/gpu/drm/drm_draw.c index 5b956229c82fb..5043baf901b82 100644 --- a/drivers/gpu/drm/drm_draw.c +++ b/drivers/gpu/drm/drm_draw.c @@ -15,6 +15,35 @@ #include "drm_draw_internal.h" #include "drm_format_internal.h" +/** + * drm_draw_can_convert_from_xrgb8888 - check if xrgb8888 can be converted to the desired format + * @format: format + * + * Returns: + * True if XRGB8888 can be converted to the specified format, false otherwise. + */ +bool drm_draw_can_convert_from_xrgb8888(u32 format) +{ + switch (format) { + case DRM_FORMAT_RGB565: + case DRM_FORMAT_RGBA5551: + case DRM_FORMAT_XRGB1555: + case DRM_FORMAT_ARGB1555: + case DRM_FORMAT_RGB888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_ABGR2101010: + return true; + default: + return false; + } +} +EXPORT_SYMBOL(drm_draw_can_convert_from_xrgb8888); + /** * drm_draw_color_from_xrgb8888 - convert one pixel from xrgb8888 to the desired format * @color: input color, in xrgb8888 format diff --git a/drivers/gpu/drm/drm_draw_internal.h b/drivers/gpu/drm/drm_draw_internal.h index 20cb404e23ea6..2619671456359 100644 --- a/drivers/gpu/drm/drm_draw_internal.h +++ b/drivers/gpu/drm/drm_draw_internal.h @@ -24,6 +24,8 @@ static inline const u8 *drm_draw_get_char_bitmap(const struct font_desc *font, return font->data + (c * font->height) * font_pitch; } +bool drm_draw_can_convert_from_xrgb8888(u32 format); + u32 drm_draw_color_from_xrgb8888(u32 color, u32 format); void drm_draw_blit16(struct iosys_map *dmap, unsigned int dpitch, diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c index 8d06014001828..1f485faeb69ac 100644 --- a/drivers/gpu/drm/drm_exec.c +++ b/drivers/gpu/drm/drm_exec.c @@ -6,6 +6,10 @@ #include #include +#ifndef amdkcl_gem_resvp +#define amdkcl_gem_resvp(obj) ((obj)->resv) +#endif + /** * DOC: Overview * @@ -59,7 +63,7 @@ static void drm_exec_unlock_all(struct drm_exec *exec) unsigned long index; drm_exec_for_each_locked_object_reverse(exec, index, obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); drm_gem_object_put(obj); } @@ -172,12 +176,12 @@ static int drm_exec_lock_contended(struct drm_exec *exec) /* Always cleanup the contention so that error handling can kick in */ exec->contended = NULL; if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { - ret = dma_resv_lock_slow_interruptible(obj->resv, + ret = dma_resv_lock_slow_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret)) goto error_dropref; } else { - dma_resv_lock_slow(obj->resv, &exec->ticket); + dma_resv_lock_slow(amdkcl_gem_resvp(obj), &exec->ticket); } ret = drm_exec_obj_locked(exec, obj); @@ -188,7 +192,7 @@ static int drm_exec_lock_contended(struct drm_exec *exec) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); error_dropref: drm_gem_object_put(obj); @@ -221,9 +225,9 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) } if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) - ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + ret = dma_resv_lock_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); else - ret = dma_resv_lock(obj->resv, &exec->ticket); + ret = dma_resv_lock(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret == -EDEADLK)) { drm_gem_object_get(obj); @@ -245,7 +249,7 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); return ret; } EXPORT_SYMBOL(drm_exec_lock_obj); @@ -265,7 +269,7 @@ void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) for (i = exec->num_objects; i--;) { if (exec->objects[i] == obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); for (++i; i < exec->num_objects; ++i) exec->objects[i - 1] = exec->objects[i]; --exec->num_objects; @@ -297,7 +301,7 @@ int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, if (ret) return ret; - ret = dma_resv_reserve_fences(obj->resv, num_fences); + ret = dma_resv_reserve_fences(amdkcl_gem_resvp(obj), num_fences); if (ret) { drm_exec_unlock_obj(exec, obj); return ret; diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 4b47aa0dab35a..e5321b2896d96 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -75,9 +76,6 @@ MODULE_PARM_DESC(drm_leak_fbdev_smem, "Allow unsafe leaking fbdev physical smem address [default=false]"); #endif -static LIST_HEAD(kernel_fb_helper_list); -static DEFINE_MUTEX(kernel_fb_helper_lock); - /** * DOC: fbdev helpers * @@ -115,101 +113,6 @@ static DEFINE_MUTEX(kernel_fb_helper_lock); * mmap page writes. */ -static void drm_fb_helper_restore_lut_atomic(struct drm_crtc *crtc) -{ - uint16_t *r_base, *g_base, *b_base; - - if (crtc->funcs->gamma_set == NULL) - return; - - r_base = crtc->gamma_store; - g_base = r_base + crtc->gamma_size; - b_base = g_base + crtc->gamma_size; - - crtc->funcs->gamma_set(crtc, r_base, g_base, b_base, - crtc->gamma_size, NULL); -} - -/** - * drm_fb_helper_debug_enter - implementation for &fb_ops.fb_debug_enter - * @info: fbdev registered by the helper - */ -int drm_fb_helper_debug_enter(struct fb_info *info) -{ - struct drm_fb_helper *helper = info->par; - const struct drm_crtc_helper_funcs *funcs; - struct drm_mode_set *mode_set; - - list_for_each_entry(helper, &kernel_fb_helper_list, kernel_fb_list) { - mutex_lock(&helper->client.modeset_mutex); - drm_client_for_each_modeset(mode_set, &helper->client) { - if (!mode_set->crtc->enabled) - continue; - - funcs = mode_set->crtc->helper_private; - if (funcs->mode_set_base_atomic == NULL) - continue; - - if (drm_drv_uses_atomic_modeset(mode_set->crtc->dev)) - continue; - - funcs->mode_set_base_atomic(mode_set->crtc, - mode_set->fb, - mode_set->x, - mode_set->y, - ENTER_ATOMIC_MODE_SET); - } - mutex_unlock(&helper->client.modeset_mutex); - } - - return 0; -} -EXPORT_SYMBOL(drm_fb_helper_debug_enter); - -/** - * drm_fb_helper_debug_leave - implementation for &fb_ops.fb_debug_leave - * @info: fbdev registered by the helper - */ -int drm_fb_helper_debug_leave(struct fb_info *info) -{ - struct drm_fb_helper *helper = info->par; - struct drm_client_dev *client = &helper->client; - struct drm_device *dev = helper->dev; - struct drm_crtc *crtc; - const struct drm_crtc_helper_funcs *funcs; - struct drm_mode_set *mode_set; - struct drm_framebuffer *fb; - - mutex_lock(&client->modeset_mutex); - drm_client_for_each_modeset(mode_set, client) { - crtc = mode_set->crtc; - if (drm_drv_uses_atomic_modeset(crtc->dev)) - continue; - - funcs = crtc->helper_private; - fb = crtc->primary->fb; - - if (!crtc->enabled) - continue; - - if (!fb) { - drm_err(dev, "no fb to restore?\n"); - continue; - } - - if (funcs->mode_set_base_atomic == NULL) - continue; - - drm_fb_helper_restore_lut_atomic(mode_set->crtc); - funcs->mode_set_base_atomic(mode_set->crtc, fb, crtc->x, - crtc->y, LEAVE_ATOMIC_MODE_SET); - } - mutex_unlock(&client->modeset_mutex); - - return 0; -} -EXPORT_SYMBOL(drm_fb_helper_debug_leave); - static int __drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper *fb_helper, bool force) @@ -400,7 +303,6 @@ void drm_fb_helper_prepare(struct drm_device *dev, struct drm_fb_helper *helper, if (!preferred_bpp) preferred_bpp = 32; - INIT_LIST_HEAD(&helper->kernel_fb_list); spin_lock_init(&helper->damage_lock); INIT_WORK(&helper->resume_work, drm_fb_helper_resume_worker); INIT_WORK(&helper->damage_work, drm_fb_helper_damage_work); @@ -537,11 +439,6 @@ void drm_fb_helper_fini(struct drm_fb_helper *fb_helper) drm_fb_helper_release_info(fb_helper); - mutex_lock(&kernel_fb_helper_lock); - if (!list_empty(&fb_helper->kernel_fb_list)) - list_del(&fb_helper->kernel_fb_list); - mutex_unlock(&kernel_fb_helper_lock); - if (!fb_helper->client.funcs) drm_client_release(&fb_helper->client); } @@ -1776,10 +1673,6 @@ __drm_fb_helper_initial_config_and_unlock(struct drm_fb_helper *fb_helper) drm_info(dev, "fb%d: %s frame buffer device\n", info->node, info->fix.id); - mutex_lock(&kernel_fb_helper_lock); - list_add(&fb_helper->kernel_fb_list, &kernel_fb_helper_list); - mutex_unlock(&kernel_fb_helper_lock); - return 0; err_drm_fb_helper_release_info: @@ -1894,3 +1787,31 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper) return 0; } EXPORT_SYMBOL(drm_fb_helper_hotplug_event); + +/** + * drm_fb_helper_gem_is_fb - Tests if GEM object is framebuffer + * @fb_helper: fb_helper instance, can be NULL + * @obj: The GEM object to test, can be NULL + * + * Call drm_fb_helper_gem_is_fb to test is a DRM device's fbdev emulation + * uses the specified GEM object for its framebuffer. The result is always + * false if either poiner is NULL. + * + * Returns: + * True if fbdev emulation uses the provided GEM object, or false otherwise. + */ +bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper, + const struct drm_gem_object *obj) +{ + const struct drm_gem_object *gem = NULL; + + if (!fb_helper || !obj) + return false; + if (fb_helper->buffer && fb_helper->buffer->gem) + gem = fb_helper->buffer->gem; + else if (fb_helper->fb) + gem = drm_gem_fb_get_obj(fb_helper->fb, 0); + + return gem == obj; +} +EXPORT_SYMBOL_GPL(drm_fb_helper_gem_is_fb); diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 25f68fed9b482..3985def993af0 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -29,6 +29,9 @@ #include #include #include +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +#include +#endif #include #include #include @@ -36,6 +39,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +85,60 @@ * up at a later date, and as our interface with shmfs for memory allocation. */ +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +static void drm_gem_huge_mnt_free(struct drm_device *dev, void *data) +{ + kern_unmount(dev->huge_mnt); +} + +/** + * drm_gem_huge_mnt_create - Create, mount and use a huge tmpfs mountpoint + * @dev: DRM device that will use the huge tmpfs mountpoint + * @value: huge tmpfs mount option value + * + * This function creates and mounts a dedicated huge tmpfs mountpoint for the + * lifetime of the DRM device @dev which is used at GEM object initialization + * with drm_gem_object_init(). + * + * The most common option for @value is "within_size" which only allocates huge + * pages if the page will be fully within the GEM object size. "always", + * "advise" and "never" are supported too but the latter would just create a + * mountpoint similar to the default one (`shm_mnt`). See shmemfs and + * Transparent Hugepage for more information. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int drm_gem_huge_mnt_create(struct drm_device *dev, const char *value) +{ + struct file_system_type *type; + struct fs_context *fc; + int ret; + + if (unlikely(drm_gem_get_huge_mnt(dev))) + return 0; + + type = get_fs_type("tmpfs"); + if (unlikely(!type)) + return -EOPNOTSUPP; + fc = fs_context_for_mount(type, SB_KERNMOUNT); + if (IS_ERR(fc)) + return PTR_ERR(fc); + ret = vfs_parse_fs_string(fc, "source", "tmpfs"); + if (unlikely(ret)) + return -ENOPARAM; + ret = vfs_parse_fs_string(fc, "huge", value); + if (unlikely(ret)) + return -ENOPARAM; + + dev->huge_mnt = fc_mount_longterm(fc); + put_fs_context(fc); + + return drmm_add_action_or_reset(dev, drm_gem_huge_mnt_free, NULL); +} +EXPORT_SYMBOL_GPL(drm_gem_huge_mnt_create); +#endif + static void drm_gem_init_release(struct drm_device *dev, void *ptr) { @@ -113,29 +171,28 @@ drm_gem_init(struct drm_device *dev) } /** - * drm_gem_object_init_with_mnt - initialize an allocated shmem-backed GEM - * object in a given shmfs mountpoint + * drm_gem_object_init - initialize an allocated shmem-backed GEM object * * @dev: drm_device the object should be initialized for * @obj: drm_gem_object to initialize * @size: object size - * @gemfs: tmpfs mount where the GEM object will be created. If NULL, use - * the usual tmpfs mountpoint (`shm_mnt`). * * Initialize an already allocated GEM object of the specified size with - * shmfs backing store. + * shmfs backing store. A huge mountpoint can be used by calling + * drm_gem_huge_mnt_create() beforehand. */ -int drm_gem_object_init_with_mnt(struct drm_device *dev, - struct drm_gem_object *obj, size_t size, - struct vfsmount *gemfs) +int drm_gem_object_init(struct drm_device *dev, struct drm_gem_object *obj, + size_t size) { + struct vfsmount *huge_mnt; struct file *filp; drm_gem_private_object_init(dev, obj, size); - if (gemfs) - filp = shmem_file_setup_with_mnt(gemfs, "drm mm object", size, - VM_NORESERVE); + huge_mnt = drm_gem_get_huge_mnt(dev); + if (huge_mnt) + filp = shmem_file_setup_with_mnt(huge_mnt, "drm mm object", + size, VM_NORESERVE); else filp = shmem_file_setup("drm mm object", size, VM_NORESERVE); @@ -146,22 +203,6 @@ int drm_gem_object_init_with_mnt(struct drm_device *dev, return 0; } -EXPORT_SYMBOL(drm_gem_object_init_with_mnt); - -/** - * drm_gem_object_init - initialize an allocated shmem-backed GEM object - * @dev: drm_device the object should be initialized for - * @obj: drm_gem_object to initialize - * @size: object size - * - * Initialize an already allocated GEM object of the specified size with - * shmfs backing store. - */ -int drm_gem_object_init(struct drm_device *dev, struct drm_gem_object *obj, - size_t size) -{ - return drm_gem_object_init_with_mnt(dev, obj, size, NULL); -} EXPORT_SYMBOL(drm_gem_object_init); /** @@ -742,7 +783,7 @@ EXPORT_SYMBOL(drm_gem_put_pages); static int objects_lookup(struct drm_file *filp, u32 *handle, int count, struct drm_gem_object **objs) { - int i, ret = 0; + int i; struct drm_gem_object *obj; spin_lock(&filp->table_lock); @@ -750,16 +791,23 @@ static int objects_lookup(struct drm_file *filp, u32 *handle, int count, for (i = 0; i < count; i++) { /* Check if we currently have a reference on the object */ obj = idr_find(&filp->object_idr, handle[i]); - if (!obj) { - ret = -ENOENT; - break; - } + if (!obj) + goto err; + drm_gem_object_get(obj); objs[i] = obj; } + spin_unlock(&filp->table_lock); + return 0; - return ret; +err: + spin_unlock(&filp->table_lock); + + while (i--) + drm_gem_object_put(objs[i]); + + return -ENOENT; } /** @@ -787,24 +835,34 @@ int drm_gem_objects_lookup(struct drm_file *filp, void __user *bo_handles, u32 *handles; int ret; + *objs_out = NULL; + if (!count) return 0; - objs = kvmalloc_array(count, sizeof(struct drm_gem_object *), - GFP_KERNEL | __GFP_ZERO); + objs = kvmalloc_array(count, sizeof(*objs), GFP_KERNEL); if (!objs) return -ENOMEM; - *objs_out = objs; - handles = vmemdup_array_user(bo_handles, count, sizeof(u32)); - if (IS_ERR(handles)) - return PTR_ERR(handles); + if (IS_ERR(handles)) { + ret = PTR_ERR(handles); + goto err_free_objs; + } ret = objects_lookup(filp, handles, count, objs); + if (ret) + goto err_free_handles; + kvfree(handles); - return ret; + *objs_out = objs; + return 0; +err_free_handles: + kvfree(handles); +err_free_objs: + kvfree(objs); + return ret; } EXPORT_SYMBOL(drm_gem_objects_lookup); @@ -1187,36 +1245,27 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, } EXPORT_SYMBOL(drm_gem_mmap_obj); -/** - * drm_gem_mmap - memory map routine for GEM objects - * @filp: DRM file pointer - * @vma: VMA for the area to be mapped - * - * If a driver supports GEM object mapping, mmap calls on the DRM file - * descriptor will end up here. - * - * Look up the GEM object based on the offset passed in (vma->vm_pgoff will - * contain the fake offset we created when the GTT map ioctl was called on - * the object) and map it with a call to drm_gem_mmap_obj(). - * - * If the caller is not granted access to the buffer object, the mmap will fail - * with EACCES. Please see the vma manager for more information. +/* + * Look up a GEM object in offset space based on the exact start address. The + * caller must be granted access to the object. Returns a GEM object on success + * or a negative error code on failure. The returned GEM object needs to be + * released with drm_gem_object_put(). */ -int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) +static struct drm_gem_object * +drm_gem_object_lookup_at_offset(struct file *filp, unsigned long start, + unsigned long pages) { struct drm_file *priv = filp->private_data; struct drm_device *dev = priv->minor->dev; struct drm_gem_object *obj = NULL; struct drm_vma_offset_node *node; - int ret; if (drm_dev_is_unplugged(dev)) - return -ENODEV; + return ERR_PTR(-ENODEV); drm_vma_offset_lock_lookup(dev->vma_offset_manager); node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, - vma->vm_pgoff, - vma_pages(vma)); + start, pages); if (likely(node)) { obj = container_of(node, struct drm_gem_object, vma_node); /* @@ -1235,14 +1284,89 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) drm_vma_offset_unlock_lookup(dev->vma_offset_manager); if (!obj) - return -EINVAL; + return ERR_PTR(-EINVAL); if (!drm_vma_node_is_allowed(node, priv)) { drm_gem_object_put(obj); - return -EACCES; + return ERR_PTR(-EACCES); } - ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, + return obj; +} + +#ifdef CONFIG_MMU +/** + * drm_gem_get_unmapped_area - get memory mapping region routine for GEM objects + * @filp: DRM file pointer + * @uaddr: User address hint + * @len: Mapping length + * @pgoff: Offset (in pages) + * @flags: Mapping flags + * + * If a driver supports GEM object mapping, before ending up in drm_gem_mmap(), + * mmap calls on the DRM file descriptor will first try to find a free linear + * address space large enough for a mapping. Since GEM objects are backed by + * shmem buffers, this should preferably be handled by the shmem virtual memory + * filesystem which can appropriately align addresses to huge page sizes when + * needed. + * + * Look up the GEM object based on the offset passed in (vma->vm_pgoff will + * contain the fake offset we created) and call shmem_get_unmapped_area() with + * the right file pointer. + * + * If a GEM object is not available at the given offset or if the caller is not + * granted access to it, fall back to mm_get_unmapped_area(). + */ +unsigned long drm_gem_get_unmapped_area(struct file *filp, unsigned long uaddr, + unsigned long len, unsigned long pgoff, + unsigned long flags) +{ + struct drm_gem_object *obj; + unsigned long ret; + + obj = drm_gem_object_lookup_at_offset(filp, pgoff, len >> PAGE_SHIFT); + if (IS_ERR(obj)) + obj = NULL; + + if (!obj || !obj->filp || !obj->filp->f_op->get_unmapped_area) + ret = mm_get_unmapped_area(filp, uaddr, len, 0, flags); + else + ret = obj->filp->f_op->get_unmapped_area(obj->filp, uaddr, len, 0, flags); + + drm_gem_object_put(obj); + + return ret; +} +EXPORT_SYMBOL_GPL(drm_gem_get_unmapped_area); +#endif + +/** + * drm_gem_mmap - memory map routine for GEM objects + * @filp: DRM file pointer + * @vma: VMA for the area to be mapped + * + * If a driver supports GEM object mapping, mmap calls on the DRM file + * descriptor will end up here. + * + * Look up the GEM object based on the offset passed in (vma->vm_pgoff will + * contain the fake offset we created) and map it with a call to + * drm_gem_mmap_obj(). + * + * If the caller is not granted access to the buffer object, the mmap will fail + * with EACCES. Please see the vma manager for more information. + */ +int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_gem_object *obj; + int ret; + + obj = drm_gem_object_lookup_at_offset(filp, vma->vm_pgoff, + vma_pages(vma)); + if (IS_ERR(obj)) + return PTR_ERR(obj); + + ret = drm_gem_mmap_obj(obj, + drm_vma_node_size(&obj->vma_node) << PAGE_SHIFT, vma); drm_gem_object_put(obj); diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index f13eb5f36e8a9..3871a6d92f776 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -15,6 +15,8 @@ #include #endif +#include + #include #include #include @@ -50,7 +52,7 @@ static const struct drm_gem_object_funcs drm_gem_shmem_funcs = { }; static int __drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_object *shmem, - size_t size, bool private, struct vfsmount *gemfs) + size_t size, bool private) { struct drm_gem_object *obj = &shmem->base; int ret = 0; @@ -62,7 +64,7 @@ static int __drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_obj drm_gem_private_object_init(dev, obj, size); shmem->map_wc = false; /* dma-buf mappings use always writecombine */ } else { - ret = drm_gem_object_init_with_mnt(dev, obj, size, gemfs); + ret = drm_gem_object_init(dev, obj, size); } if (ret) { drm_gem_private_object_fini(obj); @@ -96,21 +98,22 @@ static int __drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_obj /** * drm_gem_shmem_init - Initialize an allocated object. * @dev: DRM device - * @shmem: The allocated shmem GEM object. + * @shmem: shmem GEM object to initialize * @size: Buffer size in bytes * + * This function initializes an allocated shmem GEM object. + * * Returns: * 0 on success, or a negative error code on failure. */ int drm_gem_shmem_init(struct drm_device *dev, struct drm_gem_shmem_object *shmem, size_t size) { - return __drm_gem_shmem_init(dev, shmem, size, false, NULL); + return __drm_gem_shmem_init(dev, shmem, size, false); } EXPORT_SYMBOL_GPL(drm_gem_shmem_init); static struct drm_gem_shmem_object * -__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private, - struct vfsmount *gemfs) +__drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private) { struct drm_gem_shmem_object *shmem; struct drm_gem_object *obj; @@ -130,7 +133,7 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private, obj = &shmem->base; } - ret = __drm_gem_shmem_init(dev, shmem, size, private, gemfs); + ret = __drm_gem_shmem_init(dev, shmem, size, private); if (ret) { kfree(obj); return ERR_PTR(ret); @@ -151,31 +154,10 @@ __drm_gem_shmem_create(struct drm_device *dev, size_t size, bool private, */ struct drm_gem_shmem_object *drm_gem_shmem_create(struct drm_device *dev, size_t size) { - return __drm_gem_shmem_create(dev, size, false, NULL); + return __drm_gem_shmem_create(dev, size, false); } EXPORT_SYMBOL_GPL(drm_gem_shmem_create); -/** - * drm_gem_shmem_create_with_mnt - Allocate an object with the given size in a - * given mountpoint - * @dev: DRM device - * @size: Size of the object to allocate - * @gemfs: tmpfs mount where the GEM object will be created - * - * This function creates a shmem GEM object in a given tmpfs mountpoint. - * - * Returns: - * A struct drm_gem_shmem_object * on success or an ERR_PTR()-encoded negative - * error code on failure. - */ -struct drm_gem_shmem_object *drm_gem_shmem_create_with_mnt(struct drm_device *dev, - size_t size, - struct vfsmount *gemfs) -{ - return __drm_gem_shmem_create(dev, size, false, gemfs); -} -EXPORT_SYMBOL_GPL(drm_gem_shmem_create_with_mnt); - /** * drm_gem_shmem_release - Release resources associated with a shmem GEM object. * @shmem: shmem GEM object @@ -568,6 +550,26 @@ int drm_gem_shmem_dumb_create(struct drm_file *file, struct drm_device *dev, } EXPORT_SYMBOL_GPL(drm_gem_shmem_dumb_create); +static bool drm_gem_shmem_try_map_pmd(struct vm_fault *vmf, unsigned long addr, + struct page *page) +{ +#ifdef CONFIG_ARCH_SUPPORTS_PMD_PFNMAP + unsigned long pfn = page_to_pfn(page); + unsigned long paddr = pfn << PAGE_SHIFT; + bool aligned = (addr & ~PMD_MASK) == (paddr & ~PMD_MASK); + + if (aligned && + pmd_none(*vmf->pmd) && + folio_test_pmd_mappable(page_folio(page))) { + pfn &= PMD_MASK >> PAGE_SHIFT; + if (vmf_insert_pfn_pmd(vmf, pfn, false) == VM_FAULT_NOPAGE) + return true; + } +#endif + + return false; +} + static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; @@ -575,11 +577,12 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) struct drm_gem_shmem_object *shmem = to_drm_gem_shmem_obj(obj); loff_t num_pages = obj->size >> PAGE_SHIFT; vm_fault_t ret; - struct page *page; + struct page **pages = shmem->pages; pgoff_t page_offset; + unsigned long pfn; - /* We don't use vmf->pgoff since that has the fake offset */ - page_offset = (vmf->address - vma->vm_start) >> PAGE_SHIFT; + /* Offset to faulty address in the VMA. */ + page_offset = vmf->pgoff - vma->vm_pgoff; dma_resv_lock(shmem->base.resv, NULL); @@ -587,12 +590,18 @@ static vm_fault_t drm_gem_shmem_fault(struct vm_fault *vmf) drm_WARN_ON_ONCE(obj->dev, !shmem->pages) || shmem->madv < 0) { ret = VM_FAULT_SIGBUS; - } else { - page = shmem->pages[page_offset]; + goto out; + } - ret = vmf_insert_pfn(vma, vmf->address, page_to_pfn(page)); + if (drm_gem_shmem_try_map_pmd(vmf, vmf->address, pages[page_offset])) { + ret = VM_FAULT_NOPAGE; + goto out; } + pfn = page_to_pfn(pages[page_offset]); + ret = vmf_insert_pfn(vma, vmf->address, pfn); + + out: dma_resv_unlock(shmem->base.resv); return ret; @@ -825,7 +834,7 @@ drm_gem_shmem_prime_import_sg_table(struct drm_device *dev, size_t size = PAGE_ALIGN(attach->dmabuf->size); struct drm_gem_shmem_object *shmem; - shmem = __drm_gem_shmem_create(dev, size, true, NULL); + shmem = __drm_gem_shmem_create(dev, size, true); if (IS_ERR(shmem)) return ERR_CAST(shmem); @@ -873,7 +882,7 @@ struct drm_gem_object *drm_gem_shmem_prime_import_no_map(struct drm_device *dev, size = PAGE_ALIGN(attach->dmabuf->size); - shmem = __drm_gem_shmem_create(dev, size, true, NULL); + shmem = __drm_gem_shmem_create(dev, size, true); if (IS_ERR(shmem)) { ret = PTR_ERR(shmem); goto fail_detach; @@ -894,6 +903,67 @@ struct drm_gem_object *drm_gem_shmem_prime_import_no_map(struct drm_device *dev, } EXPORT_SYMBOL_GPL(drm_gem_shmem_prime_import_no_map); +/* + * Kunit helpers + */ + +#if IS_ENABLED(CONFIG_KUNIT) +int drm_gem_shmem_vmap(struct drm_gem_shmem_object *shmem, struct iosys_map *map) +{ + struct drm_gem_object *obj = &shmem->base; + int ret; + + ret = dma_resv_lock_interruptible(obj->resv, NULL); + if (ret) + return ret; + ret = drm_gem_shmem_vmap_locked(shmem, map); + dma_resv_unlock(obj->resv); + + return ret; +} +EXPORT_SYMBOL_IF_KUNIT(drm_gem_shmem_vmap); + +void drm_gem_shmem_vunmap(struct drm_gem_shmem_object *shmem, struct iosys_map *map) +{ + struct drm_gem_object *obj = &shmem->base; + + dma_resv_lock_interruptible(obj->resv, NULL); + drm_gem_shmem_vunmap_locked(shmem, map); + dma_resv_unlock(obj->resv); +} +EXPORT_SYMBOL_IF_KUNIT(drm_gem_shmem_vunmap); + +int drm_gem_shmem_madvise(struct drm_gem_shmem_object *shmem, int madv) +{ + struct drm_gem_object *obj = &shmem->base; + int ret; + + ret = dma_resv_lock_interruptible(obj->resv, NULL); + if (ret) + return ret; + ret = drm_gem_shmem_madvise_locked(shmem, madv); + dma_resv_unlock(obj->resv); + + return ret; +} +EXPORT_SYMBOL_IF_KUNIT(drm_gem_shmem_madvise); + +int drm_gem_shmem_purge(struct drm_gem_shmem_object *shmem) +{ + struct drm_gem_object *obj = &shmem->base; + int ret; + + ret = dma_resv_lock_interruptible(obj->resv, NULL); + if (ret) + return ret; + drm_gem_shmem_purge_locked(shmem); + dma_resv_unlock(obj->resv); + + return 0; +} +EXPORT_SYMBOL_IF_KUNIT(drm_gem_shmem_purge); +#endif + MODULE_DESCRIPTION("DRM SHMEM memory-management helpers"); MODULE_IMPORT_NS("DMA_BUF"); MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/drm_gpusvm.c b/drivers/gpu/drm/drm_gpusvm.c index 73e550c8ff8c9..aa9a0b60e727e 100644 --- a/drivers/gpu/drm/drm_gpusvm.c +++ b/drivers/gpu/drm/drm_gpusvm.c @@ -743,6 +743,127 @@ static bool drm_gpusvm_check_pages(struct drm_gpusvm *gpusvm, return err ? false : true; } +/** + * drm_gpusvm_scan_mm() - Check the migration state of a drm_gpusvm_range + * @range: Pointer to the struct drm_gpusvm_range to check. + * @dev_private_owner: The struct dev_private_owner to use to determine + * compatible device-private pages. + * @pagemap: The struct dev_pagemap pointer to use for pagemap-specific + * checks. + * + * Scan the CPU address space corresponding to @range and return the + * current migration state. Note that the result may be invalid as + * soon as the function returns. It's an advisory check. + * + * TODO: Bail early and call hmm_range_fault() for subranges. + * + * Return: See &enum drm_gpusvm_scan_result. + */ +enum drm_gpusvm_scan_result drm_gpusvm_scan_mm(struct drm_gpusvm_range *range, + void *dev_private_owner, + const struct dev_pagemap *pagemap) +{ + struct mmu_interval_notifier *notifier = &range->notifier->notifier; + unsigned long start = drm_gpusvm_range_start(range); + unsigned long end = drm_gpusvm_range_end(range); + struct hmm_range hmm_range = { + .default_flags = 0, + .notifier = notifier, + .start = start, + .end = end, + .dev_private_owner = dev_private_owner, + }; + unsigned long timeout = + jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT); + enum drm_gpusvm_scan_result state = DRM_GPUSVM_SCAN_UNPOPULATED, new_state; + unsigned long *pfns; + unsigned long npages = npages_in_range(start, end); + const struct dev_pagemap *other = NULL; + int err, i; + + pfns = kvmalloc_array(npages, sizeof(*pfns), GFP_KERNEL); + if (!pfns) + return DRM_GPUSVM_SCAN_UNPOPULATED; + + hmm_range.hmm_pfns = pfns; + +retry: + hmm_range.notifier_seq = mmu_interval_read_begin(notifier); + mmap_read_lock(range->gpusvm->mm); + + while (true) { + err = hmm_range_fault(&hmm_range); + if (err == -EBUSY) { + if (time_after(jiffies, timeout)) + break; + + hmm_range.notifier_seq = + mmu_interval_read_begin(notifier); + continue; + } + break; + } + mmap_read_unlock(range->gpusvm->mm); + if (err) + goto err_free; + + drm_gpusvm_notifier_lock(range->gpusvm); + if (mmu_interval_read_retry(notifier, hmm_range.notifier_seq)) { + drm_gpusvm_notifier_unlock(range->gpusvm); + goto retry; + } + + for (i = 0; i < npages;) { + struct page *page; + const struct dev_pagemap *cur = NULL; + + if (!(pfns[i] & HMM_PFN_VALID)) { + state = DRM_GPUSVM_SCAN_UNPOPULATED; + goto err_free; + } + + page = hmm_pfn_to_page(pfns[i]); + if (is_device_private_page(page) || + is_device_coherent_page(page)) + cur = page_pgmap(page); + + if (cur == pagemap) { + new_state = DRM_GPUSVM_SCAN_EQUAL; + } else if (cur && (cur == other || !other)) { + new_state = DRM_GPUSVM_SCAN_OTHER; + other = cur; + } else if (cur) { + new_state = DRM_GPUSVM_SCAN_MIXED_DEVICE; + } else { + new_state = DRM_GPUSVM_SCAN_SYSTEM; + } + + /* + * TODO: Could use an array for state + * transitions, and caller might want it + * to bail early for some results. + */ + if (state == DRM_GPUSVM_SCAN_UNPOPULATED) { + state = new_state; + } else if (state != new_state) { + if (new_state == DRM_GPUSVM_SCAN_SYSTEM || + state == DRM_GPUSVM_SCAN_SYSTEM) + state = DRM_GPUSVM_SCAN_MIXED; + else if (state != DRM_GPUSVM_SCAN_MIXED) + state = DRM_GPUSVM_SCAN_MIXED_DEVICE; + } + + i += 1ul << drm_gpusvm_hmm_pfn_to_order(pfns[i], i, npages); + } + +err_free: + drm_gpusvm_notifier_unlock(range->gpusvm); + + kvfree(pfns); + return state; +} +EXPORT_SYMBOL(drm_gpusvm_scan_mm); + /** * drm_gpusvm_range_chunk_size() - Determine chunk size for GPU SVM range * @gpusvm: Pointer to the GPU SVM structure @@ -1038,6 +1159,7 @@ static void __drm_gpusvm_unmap_pages(struct drm_gpusvm *gpusvm, flags.has_dma_mapping = false; WRITE_ONCE(svm_pages->flags.__flags, flags.__flags); + drm_pagemap_put(svm_pages->dpagemap); svm_pages->dpagemap = NULL; } } @@ -1288,6 +1410,9 @@ int drm_gpusvm_get_pages(struct drm_gpusvm *gpusvm, DMA_BIDIRECTIONAL; retry: + if (time_after(jiffies, timeout)) + return -EBUSY; + hmm_range.notifier_seq = mmu_interval_read_begin(notifier); if (drm_gpusvm_pages_valid_unlocked(gpusvm, svm_pages)) goto set_seqno; @@ -1431,6 +1556,8 @@ int drm_gpusvm_get_pages(struct drm_gpusvm *gpusvm, if (pagemap) { flags.has_devmem_pages = true; + drm_pagemap_get(dpagemap); + drm_pagemap_put(svm_pages->dpagemap); svm_pages->dpagemap = dpagemap; } diff --git a/drivers/gpu/drm/drm_gpuvm.c b/drivers/gpu/drm/drm_gpuvm.c index 0de47e83d84df..14469765a7801 100644 --- a/drivers/gpu/drm/drm_gpuvm.c +++ b/drivers/gpu/drm/drm_gpuvm.c @@ -1834,8 +1834,8 @@ drm_gpuvm_bo_find(struct drm_gpuvm *gpuvm, EXPORT_SYMBOL_GPL(drm_gpuvm_bo_find); /** - * drm_gpuvm_bo_obtain() - obtains an instance of the &drm_gpuvm_bo for the - * given &drm_gpuvm and &drm_gem_object + * drm_gpuvm_bo_obtain_locked() - obtains an instance of the &drm_gpuvm_bo for + * the given &drm_gpuvm and &drm_gem_object * @gpuvm: The &drm_gpuvm the @obj is mapped in. * @obj: The &drm_gem_object being mapped in the @gpuvm. * @@ -1844,16 +1844,26 @@ EXPORT_SYMBOL_GPL(drm_gpuvm_bo_find); * count of the &drm_gpuvm_bo accordingly. If not found, allocates a new * &drm_gpuvm_bo. * + * Requires the lock for the GEMs gpuva list. + * * A new &drm_gpuvm_bo is added to the GEMs gpuva list. * * Returns: a pointer to the &drm_gpuvm_bo on success, an ERR_PTR on failure */ struct drm_gpuvm_bo * -drm_gpuvm_bo_obtain(struct drm_gpuvm *gpuvm, - struct drm_gem_object *obj) +drm_gpuvm_bo_obtain_locked(struct drm_gpuvm *gpuvm, + struct drm_gem_object *obj) { struct drm_gpuvm_bo *vm_bo; + /* + * In immediate mode this would require the caller to hold the GEMs + * gpuva mutex, but it's not okay to allocate while holding that lock, + * and this method allocates. Immediate mode drivers should use + * drm_gpuvm_bo_obtain_prealloc() instead. + */ + drm_WARN_ON(gpuvm->drm, drm_gpuvm_immediate_mode(gpuvm)); + vm_bo = drm_gpuvm_bo_find(gpuvm, obj); if (vm_bo) return vm_bo; @@ -1867,7 +1877,7 @@ drm_gpuvm_bo_obtain(struct drm_gpuvm *gpuvm, return vm_bo; } -EXPORT_SYMBOL_GPL(drm_gpuvm_bo_obtain); +EXPORT_SYMBOL_GPL(drm_gpuvm_bo_obtain_locked); /** * drm_gpuvm_bo_obtain_prealloc() - obtains an instance of the &drm_gpuvm_bo @@ -2285,7 +2295,7 @@ EXPORT_SYMBOL_GPL(drm_gpuvm_interval_empty); void drm_gpuva_map(struct drm_gpuvm *gpuvm, struct drm_gpuva *va, - struct drm_gpuva_op_map *op) + const struct drm_gpuva_op_map *op) { drm_gpuva_init_from_op(va, op); drm_gpuva_insert(gpuvm, va); @@ -2305,7 +2315,7 @@ EXPORT_SYMBOL_GPL(drm_gpuva_map); void drm_gpuva_remap(struct drm_gpuva *prev, struct drm_gpuva *next, - struct drm_gpuva_op_remap *op) + const struct drm_gpuva_op_remap *op) { struct drm_gpuva *va = op->unmap->va; struct drm_gpuvm *gpuvm = va->vm; @@ -2332,7 +2342,7 @@ EXPORT_SYMBOL_GPL(drm_gpuva_remap); * Removes the &drm_gpuva associated with the &drm_gpuva_op_unmap. */ void -drm_gpuva_unmap(struct drm_gpuva_op_unmap *op) +drm_gpuva_unmap(const struct drm_gpuva_op_unmap *op) { drm_gpuva_remove(op->va); } diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c index b45d501b10c86..2d943a610b88b 100644 --- a/drivers/gpu/drm/drm_mode_object.c +++ b/drivers/gpu/drm/drm_mode_object.c @@ -385,6 +385,31 @@ int drm_object_property_get_default_value(struct drm_mode_object *obj, } EXPORT_SYMBOL(drm_object_property_get_default_value); +/** + * drm_object_immutable_property_get_value - retrieve the value of a property + * @obj: drm mode object to get property value from + * @property: property to retrieve + * @val: storage for the property value + * + * This function retrieves the software state of the given immutable property + * for the given mode object. + * + * This function can be called by both atomic and non-atomic drivers. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_object_immutable_property_get_value(struct drm_mode_object *obj, + struct drm_property *property, + uint64_t *val) +{ + if (drm_WARN_ON(property->dev, !(property->flags & DRM_MODE_PROP_IMMUTABLE))) + return -EINVAL; + + return __drm_object_property_get_prop_value(obj, property, val); +} +EXPORT_SYMBOL(drm_object_immutable_property_get_value); + /* helper for getconnector and getproperties ioctls */ int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomic, bool plane_color_pipeline, diff --git a/drivers/gpu/drm/drm_pagemap.c b/drivers/gpu/drm/drm_pagemap.c index 704f2f9450190..38eca94f01a11 100644 --- a/drivers/gpu/drm/drm_pagemap.c +++ b/drivers/gpu/drm/drm_pagemap.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include /** * DOC: Overview @@ -63,7 +65,7 @@ * * @refcount: Reference count for the zdd * @devmem_allocation: device memory allocation - * @device_private_page_owner: Device private pages owner + * @dpagemap: Refcounted pointer to the underlying struct drm_pagemap. * * This structure serves as a generic wrapper installed in * page->zone_device_data. It provides infrastructure for looking up a device @@ -75,12 +77,12 @@ struct drm_pagemap_zdd { struct kref refcount; struct drm_pagemap_devmem *devmem_allocation; - void *device_private_page_owner; + struct drm_pagemap *dpagemap; }; /** * drm_pagemap_zdd_alloc() - Allocate a zdd structure. - * @device_private_page_owner: Device private pages owner + * @dpagemap: Pointer to the underlying struct drm_pagemap. * * This function allocates and initializes a new zdd structure. It sets up the * reference count and initializes the destroy work. @@ -88,7 +90,7 @@ struct drm_pagemap_zdd { * Return: Pointer to the allocated zdd on success, ERR_PTR() on failure. */ static struct drm_pagemap_zdd * -drm_pagemap_zdd_alloc(void *device_private_page_owner) +drm_pagemap_zdd_alloc(struct drm_pagemap *dpagemap) { struct drm_pagemap_zdd *zdd; @@ -98,7 +100,7 @@ drm_pagemap_zdd_alloc(void *device_private_page_owner) kref_init(&zdd->refcount); zdd->devmem_allocation = NULL; - zdd->device_private_page_owner = device_private_page_owner; + zdd->dpagemap = drm_pagemap_get(dpagemap); return zdd; } @@ -128,6 +130,7 @@ static void drm_pagemap_zdd_destroy(struct kref *ref) struct drm_pagemap_zdd *zdd = container_of(ref, struct drm_pagemap_zdd, refcount); struct drm_pagemap_devmem *devmem = zdd->devmem_allocation; + struct drm_pagemap *dpagemap = zdd->dpagemap; if (devmem) { complete_all(&devmem->detached); @@ -135,6 +138,7 @@ static void drm_pagemap_zdd_destroy(struct kref *ref) devmem->ops->devmem_release(devmem); } kfree(zdd); + drm_pagemap_put(dpagemap); } /** @@ -202,11 +206,13 @@ static void drm_pagemap_get_devmem_page(struct page *page, /** * drm_pagemap_migrate_map_pages() - Map migration pages for GPU SVM migration - * @dev: The device for which the pages are being mapped - * @pagemap_addr: Array to store DMA information corresponding to mapped pages - * @migrate_pfn: Array of migrate page frame numbers to map - * @npages: Number of pages to map + * @dev: The device performing the migration. + * @local_dpagemap: The drm_pagemap local to the migrating device. + * @pagemap_addr: Array to store DMA information corresponding to mapped pages. + * @migrate_pfn: Array of page frame numbers of system pages or peer pages to map. + * @npages: Number of system pages or peer pages to map. * @dir: Direction of data transfer (e.g., DMA_BIDIRECTIONAL) + * @mdetails: Details governing the migration behaviour. * * This function maps pages of memory for migration usage in GPU SVM. It * iterates over each page frame number provided in @migrate_pfn, maps the @@ -216,12 +222,14 @@ static void drm_pagemap_get_devmem_page(struct page *page, * Returns: 0 on success, -EFAULT if an error occurs during mapping. */ static int drm_pagemap_migrate_map_pages(struct device *dev, + struct drm_pagemap *local_dpagemap, struct drm_pagemap_addr *pagemap_addr, unsigned long *migrate_pfn, unsigned long npages, - enum dma_data_direction dir) + enum dma_data_direction dir, + const struct drm_pagemap_migrate_details *mdetails) { - unsigned long i; + unsigned long num_peer_pages = 0, num_local_pages = 0, i; for (i = 0; i < npages;) { struct page *page = migrate_pfn_to_page(migrate_pfn[i]); @@ -232,31 +240,58 @@ static int drm_pagemap_migrate_map_pages(struct device *dev, if (!page) goto next; - if (WARN_ON_ONCE(is_zone_device_page(page))) - return -EFAULT; - folio = page_folio(page); order = folio_order(folio); - dma_addr = dma_map_page(dev, page, 0, page_size(page), dir); - if (dma_mapping_error(dev, dma_addr)) - return -EFAULT; - - pagemap_addr[i] = - drm_pagemap_addr_encode(dma_addr, - DRM_INTERCONNECT_SYSTEM, - order, dir); + if (is_device_private_page(page)) { + struct drm_pagemap_zdd *zdd = page->zone_device_data; + struct drm_pagemap *dpagemap = zdd->dpagemap; + struct drm_pagemap_addr addr; + + if (dpagemap == local_dpagemap) { + if (!mdetails->can_migrate_same_pagemap) + goto next; + + num_local_pages += NR_PAGES(order); + } else { + num_peer_pages += NR_PAGES(order); + } + + addr = dpagemap->ops->device_map(dpagemap, dev, page, order, dir); + if (dma_mapping_error(dev, addr.addr)) + return -EFAULT; + + pagemap_addr[i] = addr; + } else { + dma_addr = dma_map_page(dev, page, 0, page_size(page), dir); + if (dma_mapping_error(dev, dma_addr)) + return -EFAULT; + + pagemap_addr[i] = + drm_pagemap_addr_encode(dma_addr, + DRM_INTERCONNECT_SYSTEM, + order, dir); + } next: i += NR_PAGES(order); } + if (num_peer_pages) + drm_dbg(local_dpagemap->drm, "Migrating %lu peer pages over interconnect.\n", + num_peer_pages); + if (num_local_pages) + drm_dbg(local_dpagemap->drm, "Migrating %lu local pages over interconnect.\n", + num_local_pages); + return 0; } /** * drm_pagemap_migrate_unmap_pages() - Unmap pages previously mapped for GPU SVM migration * @dev: The device for which the pages were mapped + * @migrate_pfn: Array of migrate pfns set up for the mapped pages. Used to + * determine the drm_pagemap of a peer device private page. * @pagemap_addr: Array of DMA information corresponding to mapped pages * @npages: Number of pages to unmap * @dir: Direction of data transfer (e.g., DMA_BIDIRECTIONAL) @@ -267,16 +302,27 @@ static int drm_pagemap_migrate_map_pages(struct device *dev, */ static void drm_pagemap_migrate_unmap_pages(struct device *dev, struct drm_pagemap_addr *pagemap_addr, + unsigned long *migrate_pfn, unsigned long npages, enum dma_data_direction dir) { unsigned long i; for (i = 0; i < npages;) { - if (!pagemap_addr[i].addr || dma_mapping_error(dev, pagemap_addr[i].addr)) + struct page *page = migrate_pfn_to_page(migrate_pfn[i]); + + if (!page || !pagemap_addr[i].addr || dma_mapping_error(dev, pagemap_addr[i].addr)) goto next; - dma_unmap_page(dev, pagemap_addr[i].addr, PAGE_SIZE << pagemap_addr[i].order, dir); + if (is_zone_device_page(page)) { + struct drm_pagemap_zdd *zdd = page->zone_device_data; + struct drm_pagemap *dpagemap = zdd->dpagemap; + + dpagemap->ops->device_unmap(dpagemap, dev, pagemap_addr[i]); + } else { + dma_unmap_page(dev, pagemap_addr[i].addr, + PAGE_SIZE << pagemap_addr[i].order, dir); + } next: i += NR_PAGES(pagemap_addr[i].order); @@ -289,18 +335,125 @@ npages_in_range(unsigned long start, unsigned long end) return (end - start) >> PAGE_SHIFT; } +static int +drm_pagemap_migrate_remote_to_local(struct drm_pagemap_devmem *devmem, + struct device *remote_device, + struct drm_pagemap *remote_dpagemap, + unsigned long local_pfns[], + struct page *remote_pages[], + struct drm_pagemap_addr pagemap_addr[], + unsigned long npages, + const struct drm_pagemap_devmem_ops *ops, + const struct drm_pagemap_migrate_details *mdetails) + +{ + int err = drm_pagemap_migrate_map_pages(remote_device, remote_dpagemap, + pagemap_addr, local_pfns, + npages, DMA_FROM_DEVICE, mdetails); + + if (err) + goto out; + + err = ops->copy_to_ram(remote_pages, pagemap_addr, npages, + devmem->pre_migrate_fence); +out: + drm_pagemap_migrate_unmap_pages(remote_device, pagemap_addr, local_pfns, + npages, DMA_FROM_DEVICE); + return err; +} + +static int +drm_pagemap_migrate_sys_to_dev(struct drm_pagemap_devmem *devmem, + unsigned long sys_pfns[], + struct page *local_pages[], + struct drm_pagemap_addr pagemap_addr[], + unsigned long npages, + const struct drm_pagemap_devmem_ops *ops, + const struct drm_pagemap_migrate_details *mdetails) +{ + int err = drm_pagemap_migrate_map_pages(devmem->dev, devmem->dpagemap, + pagemap_addr, sys_pfns, npages, + DMA_TO_DEVICE, mdetails); + + if (err) + goto out; + + err = ops->copy_to_devmem(local_pages, pagemap_addr, npages, + devmem->pre_migrate_fence); +out: + drm_pagemap_migrate_unmap_pages(devmem->dev, pagemap_addr, sys_pfns, npages, + DMA_TO_DEVICE); + return err; +} + +/** + * struct migrate_range_loc - Cursor into the loop over migrate_pfns for migrating to + * device. + * @start: The current loop index. + * @device: migrating device. + * @dpagemap: Pointer to struct drm_pagemap used by the migrating device. + * @ops: The copy ops to be used for the migrating device. + */ +struct migrate_range_loc { + unsigned long start; + struct device *device; + struct drm_pagemap *dpagemap; + const struct drm_pagemap_devmem_ops *ops; +}; + +static int drm_pagemap_migrate_range(struct drm_pagemap_devmem *devmem, + unsigned long src_pfns[], + unsigned long dst_pfns[], + struct page *pages[], + struct drm_pagemap_addr pagemap_addr[], + struct migrate_range_loc *last, + const struct migrate_range_loc *cur, + const struct drm_pagemap_migrate_details *mdetails) +{ + int ret = 0; + + if (cur->start == 0) + goto out; + + if (cur->start <= last->start) + return 0; + + if (cur->dpagemap == last->dpagemap && cur->ops == last->ops) + return 0; + + if (last->dpagemap) + ret = drm_pagemap_migrate_remote_to_local(devmem, + last->device, + last->dpagemap, + &dst_pfns[last->start], + &pages[last->start], + &pagemap_addr[last->start], + cur->start - last->start, + last->ops, mdetails); + + else + ret = drm_pagemap_migrate_sys_to_dev(devmem, + &src_pfns[last->start], + &pages[last->start], + &pagemap_addr[last->start], + cur->start - last->start, + last->ops, mdetails); + +out: + *last = *cur; + return ret; +} + /** * drm_pagemap_migrate_to_devmem() - Migrate a struct mm_struct range to device memory * @devmem_allocation: The device memory allocation to migrate to. * The caller should hold a reference to the device memory allocation, - * and the reference is consumed by this function unless it returns with + * and the reference is consumed by this function even if it returns with * an error. * @mm: Pointer to the struct mm_struct. * @start: Start of the virtual address range to migrate. * @end: End of the virtual address range to migrate. - * @timeslice_ms: The time requested for the migrated pagemap pages to - * be present in @mm before being allowed to be migrated back. - * @pgmap_owner: Not used currently, since only system memory is considered. + * @mdetails: Details to govern the migration. * * This function migrates the specified virtual address range to device memory. * It performs the necessary setup and invokes the driver-specific operations for @@ -318,17 +471,31 @@ npages_in_range(unsigned long start, unsigned long end) int drm_pagemap_migrate_to_devmem(struct drm_pagemap_devmem *devmem_allocation, struct mm_struct *mm, unsigned long start, unsigned long end, - unsigned long timeslice_ms, - void *pgmap_owner) + const struct drm_pagemap_migrate_details *mdetails) { const struct drm_pagemap_devmem_ops *ops = devmem_allocation->ops; + struct drm_pagemap *dpagemap = devmem_allocation->dpagemap; + struct dev_pagemap *pagemap = dpagemap->pagemap; struct migrate_vma migrate = { .start = start, .end = end, - .pgmap_owner = pgmap_owner, - .flags = MIGRATE_VMA_SELECT_SYSTEM, + .pgmap_owner = pagemap->owner, + /* + * FIXME: MIGRATE_VMA_SELECT_DEVICE_PRIVATE intermittently + * causes 'xe_exec_system_allocator --r *race*no*' to trigger aa + * engine reset and a hard hang due to getting stuck on a folio + * lock. This should work and needs to be root-caused. The only + * downside of not selecting MIGRATE_VMA_SELECT_DEVICE_PRIVATE + * is that device-to-device migrations won’t work; instead, + * memory will bounce through system memory. This path should be + * rare and only occur when the madvise attributes of memory are + * changed or atomics are being used. + */ + .flags = MIGRATE_VMA_SELECT_SYSTEM | MIGRATE_VMA_SELECT_DEVICE_COHERENT, }; unsigned long i, npages = npages_in_range(start, end); + unsigned long own_pages = 0, migrated_pages = 0; + struct migrate_range_loc cur, last = {.device = dpagemap->drm->dev, .ops = ops}; struct vm_area_struct *vas; struct drm_pagemap_zdd *zdd = NULL; struct page **pages; @@ -367,11 +534,13 @@ int drm_pagemap_migrate_to_devmem(struct drm_pagemap_devmem *devmem_allocation, pagemap_addr = buf + (2 * sizeof(*migrate.src) * npages); pages = buf + (2 * sizeof(*migrate.src) + sizeof(*pagemap_addr)) * npages; - zdd = drm_pagemap_zdd_alloc(pgmap_owner); + zdd = drm_pagemap_zdd_alloc(dpagemap); if (!zdd) { err = -ENOMEM; - goto err_free; + kvfree(buf); + goto err_out; } + zdd->devmem_allocation = devmem_allocation; /* Owns ref */ migrate.vma = vas; migrate.src = buf; @@ -382,58 +551,136 @@ int drm_pagemap_migrate_to_devmem(struct drm_pagemap_devmem *devmem_allocation, goto err_free; if (!migrate.cpages) { - err = -EFAULT; + /* No pages to migrate. Raced or unknown device pages. */ + err = -EBUSY; goto err_free; } if (migrate.cpages != npages) { + /* + * Some pages to migrate. But we want to migrate all or + * nothing. Raced or unknown device pages. + */ err = -EBUSY; - goto err_finalize; + goto err_aborted_migration; } - err = ops->populate_devmem_pfn(devmem_allocation, npages, migrate.dst); - if (err) - goto err_finalize; + /* Count device-private pages to migrate */ + for (i = 0; i < npages;) { + struct page *src_page = migrate_pfn_to_page(migrate.src[i]); + unsigned long nr_pages = src_page ? NR_PAGES(folio_order(page_folio(src_page))) : 1; - err = drm_pagemap_migrate_map_pages(devmem_allocation->dev, pagemap_addr, - migrate.src, npages, DMA_TO_DEVICE); + if (src_page && is_zone_device_page(src_page)) { + if (page_pgmap(src_page) == pagemap) + own_pages += nr_pages; + } + + i += nr_pages; + } + drm_dbg(dpagemap->drm, "Total pages %lu; Own pages: %lu.\n", + npages, own_pages); + if (own_pages == npages) { + err = 0; + drm_dbg(dpagemap->drm, "Migration wasn't necessary.\n"); + goto err_aborted_migration; + } else if (own_pages && !mdetails->can_migrate_same_pagemap) { + err = -EBUSY; + drm_dbg(dpagemap->drm, "Migration aborted due to fragmentation.\n"); + goto err_aborted_migration; + } + + err = ops->populate_devmem_pfn(devmem_allocation, npages, migrate.dst); if (err) - goto err_finalize; + goto err_aborted_migration; + + own_pages = 0; for (i = 0; i < npages; ++i) { struct page *page = pfn_to_page(migrate.dst[i]); + struct page *src_page = migrate_pfn_to_page(migrate.src[i]); + cur.start = i; - pages[i] = page; + pages[i] = NULL; + if (src_page && is_device_private_page(src_page)) { + struct drm_pagemap_zdd *src_zdd = src_page->zone_device_data; + + if (page_pgmap(src_page) == pagemap && + !mdetails->can_migrate_same_pagemap) { + migrate.dst[i] = 0; + own_pages++; + continue; + } + if (mdetails->source_peer_migrates) { + cur.dpagemap = src_zdd->dpagemap; + cur.ops = src_zdd->devmem_allocation->ops; + cur.device = cur.dpagemap->drm->dev; + pages[i] = src_page; + } + } + if (!pages[i]) { + cur.dpagemap = NULL; + cur.ops = ops; + cur.device = dpagemap->drm->dev; + pages[i] = page; + } migrate.dst[i] = migrate_pfn(migrate.dst[i]); drm_pagemap_get_devmem_page(page, zdd); - } - err = ops->copy_to_devmem(pages, pagemap_addr, npages, - devmem_allocation->pre_migrate_fence); + /* If we switched the migrating drm_pagemap, migrate previous pages now */ + err = drm_pagemap_migrate_range(devmem_allocation, migrate.src, migrate.dst, + pages, pagemap_addr, &last, &cur, + mdetails); + if (err) { + npages = i + 1; + goto err_finalize; + } + } + cur.start = npages; + cur.ops = NULL; /* Force migration */ + err = drm_pagemap_migrate_range(devmem_allocation, migrate.src, migrate.dst, + pages, pagemap_addr, &last, &cur, mdetails); if (err) goto err_finalize; + drm_WARN_ON(dpagemap->drm, !!own_pages); + dma_fence_put(devmem_allocation->pre_migrate_fence); devmem_allocation->pre_migrate_fence = NULL; /* Upon success bind devmem allocation to range and zdd */ devmem_allocation->timeslice_expiration = get_jiffies_64() + - msecs_to_jiffies(timeslice_ms); - zdd->devmem_allocation = devmem_allocation; /* Owns ref */ + msecs_to_jiffies(mdetails->timeslice_ms); err_finalize: if (err) drm_pagemap_migration_unlock_put_pages(npages, migrate.dst); +err_aborted_migration: migrate_vma_pages(&migrate); + + for (i = 0; !err && i < npages;) { + struct page *page = migrate_pfn_to_page(migrate.src[i]); + unsigned long nr_pages = page ? NR_PAGES(folio_order(page_folio(page))) : 1; + + if (migrate.src[i] & MIGRATE_PFN_MIGRATE) + migrated_pages += nr_pages; + + i += nr_pages; + } + + if (!err && migrated_pages < npages - own_pages) { + drm_dbg(dpagemap->drm, "Raced while finalizing migration.\n"); + err = -EBUSY; + } + migrate_vma_finalize(&migrate); - drm_pagemap_migrate_unmap_pages(devmem_allocation->dev, pagemap_addr, npages, - DMA_TO_DEVICE); err_free: - if (zdd) - drm_pagemap_zdd_put(zdd); + drm_pagemap_zdd_put(zdd); kvfree(buf); + return err; + err_out: + devmem_allocation->ops->devmem_release(devmem_allocation); return err; } EXPORT_SYMBOL_GPL(drm_pagemap_migrate_to_devmem); @@ -543,6 +790,157 @@ static int drm_pagemap_migrate_populate_ram_pfn(struct vm_area_struct *vas, return -ENOMEM; } +static void drm_pagemap_dev_unhold_work(struct work_struct *work); +static LLIST_HEAD(drm_pagemap_unhold_list); +static DECLARE_WORK(drm_pagemap_work, drm_pagemap_dev_unhold_work); + +/** + * struct drm_pagemap_dev_hold - Struct to aid in drm_device release. + * @link: Link into drm_pagemap_unhold_list for deferred reference releases. + * @drm: drm device to put. + * + * When a struct drm_pagemap is released, we also need to release the + * reference it holds on the drm device. However, typically that needs + * to be done separately from a system-wide workqueue. + * Each time a struct drm_pagemap is initialized + * (or re-initialized if cached) therefore allocate a separate + * drm_pagemap_dev_hold item, from which we put the drm device and + * associated module. + */ +struct drm_pagemap_dev_hold { + struct llist_node link; + struct drm_device *drm; +}; + +static void drm_pagemap_release(struct kref *ref) +{ + struct drm_pagemap *dpagemap = container_of(ref, typeof(*dpagemap), ref); + struct drm_pagemap_dev_hold *dev_hold = dpagemap->dev_hold; + + /* + * We know the pagemap provider is alive at this point, since + * the struct drm_pagemap_dev_hold holds a reference to the + * pagemap provider drm_device and its module. + */ + dpagemap->dev_hold = NULL; + drm_pagemap_shrinker_add(dpagemap); + llist_add(&dev_hold->link, &drm_pagemap_unhold_list); + schedule_work(&drm_pagemap_work); + /* + * Here, either the provider device is still alive, since if called from + * page_free(), the caller is holding a reference on the dev_pagemap, + * or if called from drm_pagemap_put(), the direct caller is still alive. + * This ensures we can't race with THIS module unload. + */ +} + +static void drm_pagemap_dev_unhold_work(struct work_struct *work) +{ + struct llist_node *node = llist_del_all(&drm_pagemap_unhold_list); + struct drm_pagemap_dev_hold *dev_hold, *next; + + /* + * Deferred release of drm_pagemap provider device and module. + * THIS module is kept alive during the release by the + * flush_work() in the drm_pagemap_exit() function. + */ + llist_for_each_entry_safe(dev_hold, next, node, link) { + struct drm_device *drm = dev_hold->drm; + struct module *module = drm->driver->fops->owner; + + drm_dbg(drm, "Releasing reference on provider device and module.\n"); + drm_dev_put(drm); + module_put(module); + kfree(dev_hold); + } +} + +static struct drm_pagemap_dev_hold * +drm_pagemap_dev_hold(struct drm_pagemap *dpagemap) +{ + struct drm_pagemap_dev_hold *dev_hold; + struct drm_device *drm = dpagemap->drm; + + dev_hold = kzalloc(sizeof(*dev_hold), GFP_KERNEL); + if (!dev_hold) + return ERR_PTR(-ENOMEM); + + init_llist_node(&dev_hold->link); + dev_hold->drm = drm; + (void)try_module_get(drm->driver->fops->owner); + drm_dev_get(drm); + + return dev_hold; +} + +/** + * drm_pagemap_reinit() - Reinitialize a drm_pagemap + * @dpagemap: The drm_pagemap to reinitialize + * + * Reinitialize a drm_pagemap, for which drm_pagemap_release + * has already been called. This interface is intended for the + * situation where the driver caches a destroyed drm_pagemap. + * + * Return: 0 on success, negative error code on failure. + */ +int drm_pagemap_reinit(struct drm_pagemap *dpagemap) +{ + dpagemap->dev_hold = drm_pagemap_dev_hold(dpagemap); + if (IS_ERR(dpagemap->dev_hold)) + return PTR_ERR(dpagemap->dev_hold); + + kref_init(&dpagemap->ref); + return 0; +} +EXPORT_SYMBOL(drm_pagemap_reinit); + +/** + * drm_pagemap_init() - Initialize a pre-allocated drm_pagemap + * @dpagemap: The drm_pagemap to initialize. + * @pagemap: The associated dev_pagemap providing the device + * private pages. + * @drm: The drm device. The drm_pagemap holds a reference on the + * drm_device and the module owning the drm_device until + * drm_pagemap_release(). This facilitates drm_pagemap exporting. + * @ops: The drm_pagemap ops. + * + * Initialize and take an initial reference on a drm_pagemap. + * After successful return, use drm_pagemap_put() to destroy. + * + ** Return: 0 on success, negative error code on error. + */ +int drm_pagemap_init(struct drm_pagemap *dpagemap, + struct dev_pagemap *pagemap, + struct drm_device *drm, + const struct drm_pagemap_ops *ops) +{ + kref_init(&dpagemap->ref); + dpagemap->ops = ops; + dpagemap->pagemap = pagemap; + dpagemap->drm = drm; + dpagemap->cache = NULL; + INIT_LIST_HEAD(&dpagemap->shrink_link); + + return drm_pagemap_reinit(dpagemap); +} +EXPORT_SYMBOL(drm_pagemap_init); + +/** + * drm_pagemap_put() - Put a struct drm_pagemap reference + * @dpagemap: Pointer to a struct drm_pagemap object. + * + * Puts a struct drm_pagemap reference and frees the drm_pagemap object + * if the refount reaches zero. + */ +void drm_pagemap_put(struct drm_pagemap *dpagemap) +{ + if (likely(dpagemap)) { + drm_pagemap_shrinker_might_lock(dpagemap); + kref_put(&dpagemap->ref, drm_pagemap_release); + } +} +EXPORT_SYMBOL(drm_pagemap_put); + /** * drm_pagemap_evict_to_ram() - Evict GPU SVM range to RAM * @devmem_allocation: Pointer to the device memory allocation @@ -555,6 +953,7 @@ static int drm_pagemap_migrate_populate_ram_pfn(struct vm_area_struct *vas, int drm_pagemap_evict_to_ram(struct drm_pagemap_devmem *devmem_allocation) { const struct drm_pagemap_devmem_ops *ops = devmem_allocation->ops; + struct drm_pagemap_migrate_details mdetails = {}; unsigned long npages, mpages = 0; struct page **pages; unsigned long *src, *dst; @@ -593,8 +992,10 @@ int drm_pagemap_evict_to_ram(struct drm_pagemap_devmem *devmem_allocation) if (err || !mpages) goto err_finalize; - err = drm_pagemap_migrate_map_pages(devmem_allocation->dev, pagemap_addr, - dst, npages, DMA_FROM_DEVICE); + err = drm_pagemap_migrate_map_pages(devmem_allocation->dev, + devmem_allocation->dpagemap, pagemap_addr, + dst, npages, DMA_FROM_DEVICE, + &mdetails); if (err) goto err_finalize; @@ -610,8 +1011,9 @@ int drm_pagemap_evict_to_ram(struct drm_pagemap_devmem *devmem_allocation) drm_pagemap_migration_unlock_put_pages(npages, dst); migrate_device_pages(src, dst, npages); migrate_device_finalize(src, dst, npages); - drm_pagemap_migrate_unmap_pages(devmem_allocation->dev, pagemap_addr, npages, + drm_pagemap_migrate_unmap_pages(devmem_allocation->dev, pagemap_addr, dst, npages, DMA_FROM_DEVICE); + err_free: kvfree(buf); err_out: @@ -632,8 +1034,7 @@ EXPORT_SYMBOL_GPL(drm_pagemap_evict_to_ram); /** * __drm_pagemap_migrate_to_ram() - Migrate GPU SVM range to RAM (internal) * @vas: Pointer to the VM area structure - * @device_private_page_owner: Device private pages owner - * @page: Pointer to the page for fault handling (can be NULL) + * @page: Pointer to the page for fault handling. * @fault_addr: Fault address * @size: Size of migration * @@ -644,18 +1045,18 @@ EXPORT_SYMBOL_GPL(drm_pagemap_evict_to_ram); * Return: 0 on success, negative error code on failure. */ static int __drm_pagemap_migrate_to_ram(struct vm_area_struct *vas, - void *device_private_page_owner, struct page *page, unsigned long fault_addr, unsigned long size) { struct migrate_vma migrate = { .vma = vas, - .pgmap_owner = device_private_page_owner, + .pgmap_owner = page_pgmap(page)->owner, .flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE | MIGRATE_VMA_SELECT_DEVICE_COHERENT, .fault_page = page, }; + struct drm_pagemap_migrate_details mdetails = {}; struct drm_pagemap_zdd *zdd; const struct drm_pagemap_devmem_ops *ops; struct device *dev = NULL; @@ -666,12 +1067,9 @@ static int __drm_pagemap_migrate_to_ram(struct vm_area_struct *vas, void *buf; int i, err = 0; - if (page) { - zdd = page->zone_device_data; - if (time_before64(get_jiffies_64(), - zdd->devmem_allocation->timeslice_expiration)) - return 0; - } + zdd = page->zone_device_data; + if (time_before64(get_jiffies_64(), zdd->devmem_allocation->timeslice_expiration)) + return 0; start = ALIGN_DOWN(fault_addr, size); end = ALIGN(fault_addr + 1, size); @@ -707,19 +1105,6 @@ static int __drm_pagemap_migrate_to_ram(struct vm_area_struct *vas, if (!migrate.cpages) goto err_free; - if (!page) { - for (i = 0; i < npages; ++i) { - if (!(migrate.src[i] & MIGRATE_PFN_MIGRATE)) - continue; - - page = migrate_pfn_to_page(migrate.src[i]); - break; - } - - if (!page) - goto err_finalize; - } - zdd = page->zone_device_data; ops = zdd->devmem_allocation->ops; dev = zdd->devmem_allocation->dev; @@ -729,8 +1114,8 @@ static int __drm_pagemap_migrate_to_ram(struct vm_area_struct *vas, if (err) goto err_finalize; - err = drm_pagemap_migrate_map_pages(dev, pagemap_addr, migrate.dst, npages, - DMA_FROM_DEVICE); + err = drm_pagemap_migrate_map_pages(dev, zdd->dpagemap, pagemap_addr, migrate.dst, npages, + DMA_FROM_DEVICE, &mdetails); if (err) goto err_finalize; @@ -747,8 +1132,8 @@ static int __drm_pagemap_migrate_to_ram(struct vm_area_struct *vas, migrate_vma_pages(&migrate); migrate_vma_finalize(&migrate); if (dev) - drm_pagemap_migrate_unmap_pages(dev, pagemap_addr, npages, - DMA_FROM_DEVICE); + drm_pagemap_migrate_unmap_pages(dev, pagemap_addr, migrate.dst, + npages, DMA_FROM_DEVICE); err_free: kvfree(buf); err_out: @@ -785,7 +1170,6 @@ static vm_fault_t drm_pagemap_migrate_to_ram(struct vm_fault *vmf) int err; err = __drm_pagemap_migrate_to_ram(vmf->vma, - zdd->device_private_page_owner, vmf->page, vmf->address, zdd->devmem_allocation->size); @@ -889,3 +1273,19 @@ int drm_pagemap_populate_mm(struct drm_pagemap *dpagemap, return err; } EXPORT_SYMBOL(drm_pagemap_populate_mm); + +void drm_pagemap_destroy(struct drm_pagemap *dpagemap, bool is_atomic_or_reclaim) +{ + if (dpagemap->ops->destroy) + dpagemap->ops->destroy(dpagemap, is_atomic_or_reclaim); + else + kfree(dpagemap); +} + +static void drm_pagemap_exit(void) +{ + flush_work(&drm_pagemap_work); + if (WARN_ON(!llist_empty(&drm_pagemap_unhold_list))) + disable_work_sync(&drm_pagemap_work); +} +module_exit(drm_pagemap_exit); diff --git a/drivers/gpu/drm/drm_pagemap_util.c b/drivers/gpu/drm/drm_pagemap_util.c new file mode 100644 index 0000000000000..c6ae3357c7fb7 --- /dev/null +++ b/drivers/gpu/drm/drm_pagemap_util.c @@ -0,0 +1,568 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright © 2025 Intel Corporation + */ + +#include + +#include +#include +#include +#include +#include + +/** + * struct drm_pagemap_cache - Lookup structure for pagemaps + * + * Structure to keep track of active (refcount > 1) and inactive + * (refcount == 0) pagemaps. Inactive pagemaps can be made active + * again by waiting for the @queued completion (indicating that the + * pagemap has been put on the @shrinker's list of shrinkable + * pagemaps, and then successfully removing it from @shrinker's + * list. The latter may fail if the shrinker is already in the + * process of freeing the pagemap. A struct drm_pagemap_cache can + * hold a single struct drm_pagemap. + */ +struct drm_pagemap_cache { + /** @lookup_mutex: Mutex making the lookup process atomic */ + struct mutex lookup_mutex; + /** @lock: Lock protecting the @dpagemap pointer */ + spinlock_t lock; + /** @shrinker: Pointer to the shrinker used for this cache. Immutable. */ + struct drm_pagemap_shrinker *shrinker; + /** @dpagemap: Non-refcounted pointer to the drm_pagemap */ + struct drm_pagemap *dpagemap; + /** + * @queued: Signals when an inactive drm_pagemap has been put on + * @shrinker's list. + */ + struct completion queued; +}; + +/** + * struct drm_pagemap_shrinker - Shrinker to remove unused pagemaps + */ +struct drm_pagemap_shrinker { + /** @drm: Pointer to the drm device. */ + struct drm_device *drm; + /** @lock: Spinlock to protect the @dpagemaps list. */ + spinlock_t lock; + /** @dpagemaps: List of unused dpagemaps. */ + struct list_head dpagemaps; + /** @num_dpagemaps: Number of unused dpagemaps in @dpagemaps. */ + atomic_t num_dpagemaps; + /** @shrink: Pointer to the struct shrinker. */ + struct shrinker *shrink; +}; + +static bool drm_pagemap_shrinker_cancel(struct drm_pagemap *dpagemap); + +static void drm_pagemap_cache_fini(void *arg) +{ + struct drm_pagemap_cache *cache = arg; + struct drm_pagemap *dpagemap; + + drm_dbg(cache->shrinker->drm, "Destroying dpagemap cache.\n"); + spin_lock(&cache->lock); + dpagemap = cache->dpagemap; + if (!dpagemap) { + spin_unlock(&cache->lock); + goto out; + } + + if (drm_pagemap_shrinker_cancel(dpagemap)) { + cache->dpagemap = NULL; + spin_unlock(&cache->lock); + drm_pagemap_destroy(dpagemap, false); + } + +out: + mutex_destroy(&cache->lookup_mutex); + kfree(cache); +} + +/** + * drm_pagemap_cache_create_devm() - Create a drm_pagemap_cache + * @shrinker: Pointer to a struct drm_pagemap_shrinker. + * + * Create a device-managed drm_pagemap cache. The cache is automatically + * destroyed on struct device removal, at which point any *inactive* + * drm_pagemap's are destroyed. + * + * Return: Pointer to a struct drm_pagemap_cache on success. Error pointer + * on failure. + */ +struct drm_pagemap_cache *drm_pagemap_cache_create_devm(struct drm_pagemap_shrinker *shrinker) +{ + struct drm_pagemap_cache *cache = kzalloc(sizeof(*cache), GFP_KERNEL); + int err; + + if (!cache) + return ERR_PTR(-ENOMEM); + + mutex_init(&cache->lookup_mutex); + spin_lock_init(&cache->lock); + cache->shrinker = shrinker; + init_completion(&cache->queued); + err = devm_add_action_or_reset(shrinker->drm->dev, drm_pagemap_cache_fini, cache); + if (err) + return ERR_PTR(err); + + return cache; +} +EXPORT_SYMBOL(drm_pagemap_cache_create_devm); + +/** + * DOC: Cache lookup + * + * Cache lookup should be done under a locked mutex, so that a + * failed drm_pagemap_get_from_cache() and a following + * drm_pagemap_cache_setpagemap() are carried out as an atomic + * operation WRT other lookups. Otherwise, racing lookups may + * unnecessarily concurrently create pagemaps to fulfill a + * failed lookup. The API provides two functions to perform this lock, + * drm_pagemap_lock_lookup() and drm_pagemap_unlock_lookup() and they + * should be used in the following way: + * + * .. code-block:: c + * + * drm_pagemap_lock_lookup(cache); + * dpagemap = drm_pagemap_get_from_cache(cache); + * if (dpagemap) + * goto out_unlock; + * + * dpagemap = driver_create_new_dpagemap(); + * if (!IS_ERR(dpagemap)) + * drm_pagemap_cache_set_pagemap(cache, dpagemap); + * + * out_unlock: + * drm_pagemap_unlock_lookup(cache); + */ + +/** + * drm_pagemap_cache_lock_lookup() - Lock a drm_pagemap_cache for lookup. + * @cache: The drm_pagemap_cache to lock. + * + * Return: %-EINTR if interrupted while blocking. %0 otherwise. + */ +int drm_pagemap_cache_lock_lookup(struct drm_pagemap_cache *cache) +{ + return mutex_lock_interruptible(&cache->lookup_mutex); +} +EXPORT_SYMBOL(drm_pagemap_cache_lock_lookup); + +/** + * drm_pagemap_cache_unlock_lookup() - Unlock a drm_pagemap_cache after lookup. + * @cache: The drm_pagemap_cache to unlock. + */ +void drm_pagemap_cache_unlock_lookup(struct drm_pagemap_cache *cache) +{ + mutex_unlock(&cache->lookup_mutex); +} +EXPORT_SYMBOL(drm_pagemap_cache_unlock_lookup); + +/** + * drm_pagemap_get_from_cache() - Lookup of drm_pagemaps. + * @cache: The cache used for lookup. + * + * If an active pagemap is present in the cache, it is immediately returned. + * If an inactive pagemap is present, it's removed from the shrinker list and + * an attempt is made to make it active. + * If no pagemap present or the attempt to make it active failed, %NULL is returned + * to indicate to the caller to create a new drm_pagemap and insert it into + * the cache. + * + * Return: A reference-counted pointer to a drm_pagemap if successful. An error + * pointer if an error occurred, or %NULL if no drm_pagemap was found and + * the caller should insert a new one. + */ +struct drm_pagemap *drm_pagemap_get_from_cache(struct drm_pagemap_cache *cache) +{ + struct drm_pagemap *dpagemap; + int err; + + lockdep_assert_held(&cache->lookup_mutex); +retry: + spin_lock(&cache->lock); + dpagemap = cache->dpagemap; + if (drm_pagemap_get_unless_zero(dpagemap)) { + spin_unlock(&cache->lock); + return dpagemap; + } + + if (!dpagemap) { + spin_unlock(&cache->lock); + return NULL; + } + + if (!try_wait_for_completion(&cache->queued)) { + spin_unlock(&cache->lock); + err = wait_for_completion_interruptible(&cache->queued); + if (err) + return ERR_PTR(err); + goto retry; + } + + if (drm_pagemap_shrinker_cancel(dpagemap)) { + cache->dpagemap = NULL; + spin_unlock(&cache->lock); + err = drm_pagemap_reinit(dpagemap); + if (err) { + drm_pagemap_destroy(dpagemap, false); + return ERR_PTR(err); + } + drm_pagemap_cache_set_pagemap(cache, dpagemap); + } else { + cache->dpagemap = NULL; + spin_unlock(&cache->lock); + dpagemap = NULL; + } + + return dpagemap; +} +EXPORT_SYMBOL(drm_pagemap_get_from_cache); + +/** + * drm_pagemap_cache_set_pagemap() - Assign a drm_pagemap to a drm_pagemap_cache + * @cache: The cache to assign the drm_pagemap to. + * @dpagemap: The drm_pagemap to assign. + * + * The function must be called to populate a drm_pagemap_cache only + * after a call to drm_pagemap_get_from_cache() returns NULL. + */ +void drm_pagemap_cache_set_pagemap(struct drm_pagemap_cache *cache, struct drm_pagemap *dpagemap) +{ + struct drm_device *drm = dpagemap->drm; + + lockdep_assert_held(&cache->lookup_mutex); + spin_lock(&cache->lock); + dpagemap->cache = cache; + swap(cache->dpagemap, dpagemap); + reinit_completion(&cache->queued); + spin_unlock(&cache->lock); + drm_WARN_ON(drm, !!dpagemap); +} +EXPORT_SYMBOL(drm_pagemap_cache_set_pagemap); + +/** + * drm_pagemap_get_from_cache_if_active() - Quick lookup of active drm_pagemaps + * @cache: The cache to lookup from. + * + * Function that should be used to lookup a drm_pagemap that is already active. + * (refcount > 0). + * + * Return: A pointer to the cache's drm_pagemap if it's active; %NULL otherwise. + */ +struct drm_pagemap *drm_pagemap_get_from_cache_if_active(struct drm_pagemap_cache *cache) +{ + struct drm_pagemap *dpagemap; + + spin_lock(&cache->lock); + dpagemap = drm_pagemap_get_unless_zero(cache->dpagemap); + spin_unlock(&cache->lock); + + return dpagemap; +} +EXPORT_SYMBOL(drm_pagemap_get_from_cache_if_active); + +static bool drm_pagemap_shrinker_cancel(struct drm_pagemap *dpagemap) +{ + struct drm_pagemap_cache *cache = dpagemap->cache; + struct drm_pagemap_shrinker *shrinker = cache->shrinker; + + spin_lock(&shrinker->lock); + if (list_empty(&dpagemap->shrink_link)) { + spin_unlock(&shrinker->lock); + return false; + } + + list_del_init(&dpagemap->shrink_link); + atomic_dec(&shrinker->num_dpagemaps); + spin_unlock(&shrinker->lock); + return true; +} + +#ifdef CONFIG_PROVE_LOCKING +/** + * drm_pagemap_shrinker_might_lock() - lockdep test for drm_pagemap_shrinker_add() + * @dpagemap: The drm pagemap. + * + * The drm_pagemap_shrinker_add() function performs some locking. + * This function can be called in code-paths that might + * call drm_pagemap_shrinker_add() to detect any lockdep problems early. + */ +void drm_pagemap_shrinker_might_lock(struct drm_pagemap *dpagemap) +{ + int idx; + + if (drm_dev_enter(dpagemap->drm, &idx)) { + struct drm_pagemap_cache *cache = dpagemap->cache; + + if (cache) + might_lock(&cache->shrinker->lock); + + drm_dev_exit(idx); + } +} +#endif + +/** + * drm_pagemap_shrinker_add() - Add a drm_pagemap to the shrinker list or destroy + * @dpagemap: The drm_pagemap. + * + * If @dpagemap is associated with a &struct drm_pagemap_cache AND the + * struct device backing the drm device is still alive, add @dpagemap to + * the &struct drm_pagemap_shrinker list of shrinkable drm_pagemaps. + * + * Otherwise destroy the pagemap directly using drm_pagemap_destroy(). + * + * This is an internal function which is not intended to be exposed to drivers. + */ +void drm_pagemap_shrinker_add(struct drm_pagemap *dpagemap) +{ + struct drm_pagemap_cache *cache; + struct drm_pagemap_shrinker *shrinker; + int idx; + + /* + * The pagemap cache and shrinker are disabled at + * pci device remove time. After that, dpagemaps + * are freed directly. + */ + if (!drm_dev_enter(dpagemap->drm, &idx)) + goto out_no_cache; + + cache = dpagemap->cache; + if (!cache) { + drm_dev_exit(idx); + goto out_no_cache; + } + + shrinker = cache->shrinker; + spin_lock(&shrinker->lock); + list_add_tail(&dpagemap->shrink_link, &shrinker->dpagemaps); + atomic_inc(&shrinker->num_dpagemaps); + spin_unlock(&shrinker->lock); + complete_all(&cache->queued); + drm_dev_exit(idx); + return; + +out_no_cache: + drm_pagemap_destroy(dpagemap, true); +} + +static unsigned long +drm_pagemap_shrinker_count(struct shrinker *shrink, struct shrink_control *sc) +{ + struct drm_pagemap_shrinker *shrinker = shrink->private_data; + unsigned long count = atomic_read(&shrinker->num_dpagemaps); + + return count ? : SHRINK_EMPTY; +} + +static unsigned long +drm_pagemap_shrinker_scan(struct shrinker *shrink, struct shrink_control *sc) +{ + struct drm_pagemap_shrinker *shrinker = shrink->private_data; + struct drm_pagemap *dpagemap; + struct drm_pagemap_cache *cache; + unsigned long nr_freed = 0; + + sc->nr_scanned = 0; + spin_lock(&shrinker->lock); + do { + dpagemap = list_first_entry_or_null(&shrinker->dpagemaps, typeof(*dpagemap), + shrink_link); + if (!dpagemap) + break; + + atomic_dec(&shrinker->num_dpagemaps); + list_del_init(&dpagemap->shrink_link); + spin_unlock(&shrinker->lock); + + sc->nr_scanned++; + nr_freed++; + + cache = dpagemap->cache; + spin_lock(&cache->lock); + cache->dpagemap = NULL; + spin_unlock(&cache->lock); + + drm_dbg(dpagemap->drm, "Shrinking dpagemap %p.\n", dpagemap); + drm_pagemap_destroy(dpagemap, true); + spin_lock(&shrinker->lock); + } while (sc->nr_scanned < sc->nr_to_scan); + spin_unlock(&shrinker->lock); + + return sc->nr_scanned ? nr_freed : SHRINK_STOP; +} + +static void drm_pagemap_shrinker_fini(void *arg) +{ + struct drm_pagemap_shrinker *shrinker = arg; + + drm_dbg(shrinker->drm, "Destroying dpagemap shrinker.\n"); + drm_WARN_ON(shrinker->drm, !!atomic_read(&shrinker->num_dpagemaps)); + shrinker_free(shrinker->shrink); + kfree(shrinker); +} + +/** + * drm_pagemap_shrinker_create_devm() - Create and register a pagemap shrinker + * @drm: The drm device + * + * Create and register a pagemap shrinker that shrinks unused pagemaps + * and thereby reduces memory footprint. + * The shrinker is drm_device managed and unregisters itself when + * the drm device is removed. + * + * Return: %0 on success, negative error code on failure. + */ +struct drm_pagemap_shrinker *drm_pagemap_shrinker_create_devm(struct drm_device *drm) +{ + struct drm_pagemap_shrinker *shrinker; + struct shrinker *shrink; + int err; + + shrinker = kzalloc(sizeof(*shrinker), GFP_KERNEL); + if (!shrinker) + return ERR_PTR(-ENOMEM); + + shrink = shrinker_alloc(0, "drm-drm_pagemap:%s", drm->unique); + if (!shrink) { + kfree(shrinker); + return ERR_PTR(-ENOMEM); + } + + spin_lock_init(&shrinker->lock); + INIT_LIST_HEAD(&shrinker->dpagemaps); + shrinker->drm = drm; + shrinker->shrink = shrink; + shrink->count_objects = drm_pagemap_shrinker_count; + shrink->scan_objects = drm_pagemap_shrinker_scan; + shrink->private_data = shrinker; + shrinker_register(shrink); + + err = devm_add_action_or_reset(drm->dev, drm_pagemap_shrinker_fini, shrinker); + if (err) + return ERR_PTR(err); + + return shrinker; +} +EXPORT_SYMBOL(drm_pagemap_shrinker_create_devm); + +/** + * struct drm_pagemap_owner - Device interconnect group + * @kref: Reference count. + * + * A struct drm_pagemap_owner identifies a device interconnect group. + */ +struct drm_pagemap_owner { + struct kref kref; +}; + +static void drm_pagemap_owner_release(struct kref *kref) +{ + kfree(container_of(kref, struct drm_pagemap_owner, kref)); +} + +/** + * drm_pagemap_release_owner() - Stop participating in an interconnect group + * @peer: Pointer to the struct drm_pagemap_peer used when joining the group + * + * Stop participating in an interconnect group. This function is typically + * called when a pagemap is removed to indicate that it doesn't need to + * be taken into account. + */ +void drm_pagemap_release_owner(struct drm_pagemap_peer *peer) +{ + struct drm_pagemap_owner_list *owner_list = peer->list; + + if (!owner_list) + return; + + mutex_lock(&owner_list->lock); + list_del(&peer->link); + kref_put(&peer->owner->kref, drm_pagemap_owner_release); + peer->owner = NULL; + mutex_unlock(&owner_list->lock); +} +EXPORT_SYMBOL(drm_pagemap_release_owner); + +/** + * typedef interconnect_fn - Callback function to identify fast interconnects + * @peer1: First endpoint. + * @peer2: Second endpont. + * + * The function returns %true iff @peer1 and @peer2 have a fast interconnect. + * Note that this is symmetrical. The function has no notion of client and provider, + * which may not be sufficient in some cases. However, since the callback is intended + * to guide in providing common pagemap owners, the notion of a common owner to + * indicate fast interconnects would then have to change as well. + * + * Return: %true iff @peer1 and @peer2 have a fast interconnect. Otherwise @false. + */ +typedef bool (*interconnect_fn)(struct drm_pagemap_peer *peer1, struct drm_pagemap_peer *peer2); + +/** + * drm_pagemap_acquire_owner() - Join an interconnect group + * @peer: A struct drm_pagemap_peer keeping track of the device interconnect + * @owner_list: Pointer to the owner_list, keeping track of all interconnects + * @has_interconnect: Callback function to determine whether two peers have a + * fast local interconnect. + * + * Repeatedly calls @has_interconnect for @peer and other peers on @owner_list to + * determine a set of peers for which @peer has a fast interconnect. That set will + * have common &struct drm_pagemap_owner, and upon successful return, @peer::owner + * will point to that struct, holding a reference, and @peer will be registered in + * @owner_list. If @peer doesn't have any fast interconnects to other @peers, a + * new unique &struct drm_pagemap_owner will be allocated for it, and that + * may be shared with other peers that, at a later point, are determined to have + * a fast interconnect with @peer. + * + * When @peer no longer participates in an interconnect group, + * drm_pagemap_release_owner() should be called to drop the reference on the + * struct drm_pagemap_owner. + * + * Return: %0 on success, negative error code on failure. + */ +int drm_pagemap_acquire_owner(struct drm_pagemap_peer *peer, + struct drm_pagemap_owner_list *owner_list, + interconnect_fn has_interconnect) +{ + struct drm_pagemap_peer *cur_peer; + struct drm_pagemap_owner *owner = NULL; + bool interconnect = false; + + mutex_lock(&owner_list->lock); + might_alloc(GFP_KERNEL); + list_for_each_entry(cur_peer, &owner_list->peers, link) { + if (cur_peer->owner != owner) { + if (owner && interconnect) + break; + owner = cur_peer->owner; + interconnect = true; + } + if (interconnect && !has_interconnect(peer, cur_peer)) + interconnect = false; + } + + if (!interconnect) { + owner = kmalloc(sizeof(*owner), GFP_KERNEL); + if (!owner) { + mutex_unlock(&owner_list->lock); + return -ENOMEM; + } + kref_init(&owner->kref); + list_add_tail(&peer->link, &owner_list->peers); + } else { + kref_get(&owner->kref); + list_add_tail(&peer->link, &cur_peer->link); + } + peer->owner = owner; + peer->list = owner_list; + mutex_unlock(&owner_list->lock); + + return 0; +} +EXPORT_SYMBOL(drm_pagemap_acquire_owner); diff --git a/drivers/gpu/drm/drm_panic.c b/drivers/gpu/drm/drm_panic.c index d4b6ea42db0fe..d6d3b8d85dea2 100644 --- a/drivers/gpu/drm/drm_panic.c +++ b/drivers/gpu/drm/drm_panic.c @@ -39,12 +39,6 @@ MODULE_AUTHOR("Jocelyn Falempe"); MODULE_DESCRIPTION("DRM panic handler"); MODULE_LICENSE("GPL"); -static char drm_panic_screen[16] = CONFIG_DRM_PANIC_SCREEN; -module_param_string(panic_screen, drm_panic_screen, sizeof(drm_panic_screen), 0644); -MODULE_PARM_DESC(panic_screen, - "Choose what will be displayed by drm_panic, 'user' or 'kmsg' [default=" - CONFIG_DRM_PANIC_SCREEN "]"); - /** * DOC: overview * @@ -482,7 +476,7 @@ static void drm_panic_logo_draw(struct drm_scanout_buffer *sb, struct drm_rect * fg_color); } -static void draw_panic_static_user(struct drm_scanout_buffer *sb) +static void draw_panic_screen_user(struct drm_scanout_buffer *sb) { u32 fg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_FOREGROUND_COLOR, sb->format->format); @@ -551,7 +545,7 @@ static int draw_line_with_wrap(struct drm_scanout_buffer *sb, const struct font_ * Draw the kmsg buffer to the screen, starting from the youngest message at the bottom, * and going up until reaching the top of the screen. */ -static void draw_panic_static_kmsg(struct drm_scanout_buffer *sb) +static void draw_panic_screen_kmsg(struct drm_scanout_buffer *sb) { u32 fg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_FOREGROUND_COLOR, sb->format->format); @@ -739,7 +733,7 @@ static int drm_panic_get_qr_code(u8 **qr_image) /* * Draw the panic message at the center of the screen, with a QR Code */ -static int _draw_panic_static_qr_code(struct drm_scanout_buffer *sb) +static int _draw_panic_screen_qr_code(struct drm_scanout_buffer *sb) { u32 fg_color = drm_draw_color_from_xrgb8888(CONFIG_DRM_PANIC_FOREGROUND_COLOR, sb->format->format); @@ -807,20 +801,65 @@ static int _draw_panic_static_qr_code(struct drm_scanout_buffer *sb) return 0; } -static void draw_panic_static_qr_code(struct drm_scanout_buffer *sb) +static void draw_panic_screen_qr_code(struct drm_scanout_buffer *sb) { - if (_draw_panic_static_qr_code(sb)) - draw_panic_static_user(sb); + if (_draw_panic_screen_qr_code(sb)) + draw_panic_screen_user(sb); } #else -static void draw_panic_static_qr_code(struct drm_scanout_buffer *sb) +static void drm_panic_qr_init(void) {}; +static void drm_panic_qr_exit(void) {}; +#endif + +enum drm_panic_type { + DRM_PANIC_TYPE_KMSG, + DRM_PANIC_TYPE_USER, + DRM_PANIC_TYPE_QR, +}; + +static enum drm_panic_type drm_panic_type = -1; + +static const char *drm_panic_type_map[] = { + [DRM_PANIC_TYPE_KMSG] = "kmsg", + [DRM_PANIC_TYPE_USER] = "user", +#if IS_ENABLED(CONFIG_DRM_PANIC_SCREEN_QR_CODE) + [DRM_PANIC_TYPE_QR] = "qr_code", +#endif +}; + +static int drm_panic_type_set(const char *val, const struct kernel_param *kp) { - draw_panic_static_user(sb); + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(drm_panic_type_map); i++) { + if (!strcmp(val, drm_panic_type_map[i])) { + drm_panic_type = i; + return 0; + } + } + + return -EINVAL; } -static void drm_panic_qr_init(void) {}; -static void drm_panic_qr_exit(void) {}; +static int drm_panic_type_get(char *buffer, const struct kernel_param *kp) +{ + return scnprintf(buffer, PAGE_SIZE, "%s\n", + drm_panic_type_map[drm_panic_type]); +} + +static const struct kernel_param_ops drm_panic_ops = { + .set = drm_panic_type_set, + .get = drm_panic_type_get, +}; + +module_param_cb(panic_screen, &drm_panic_ops, NULL, 0644); +MODULE_PARM_DESC(panic_screen, +#if IS_ENABLED(CONFIG_DRM_PANIC_SCREEN_QR_CODE) + "Choose what will be displayed by drm_panic, 'user', 'kmsg' or 'qr_code' [default=" +#else + "Choose what will be displayed by drm_panic, 'user' or 'kmsg' [default=" #endif + CONFIG_DRM_PANIC_SCREEN "]"); /* * drm_panic_is_format_supported() @@ -833,17 +872,25 @@ static bool drm_panic_is_format_supported(const struct drm_format_info *format) { if (format->num_planes != 1) return false; - return drm_draw_color_from_xrgb8888(0xffffff, format->format) != 0; + return drm_draw_can_convert_from_xrgb8888(format->format); } static void draw_panic_dispatch(struct drm_scanout_buffer *sb) { - if (!strcmp(drm_panic_screen, "kmsg")) { - draw_panic_static_kmsg(sb); - } else if (!strcmp(drm_panic_screen, "qr_code")) { - draw_panic_static_qr_code(sb); - } else { - draw_panic_static_user(sb); + switch (drm_panic_type) { + case DRM_PANIC_TYPE_KMSG: + draw_panic_screen_kmsg(sb); + break; + +#if IS_ENABLED(CONFIG_DRM_PANIC_SCREEN_QR_CODE) + case DRM_PANIC_TYPE_QR: + draw_panic_screen_qr_code(sb); + break; +#endif + + case DRM_PANIC_TYPE_USER: + default: + draw_panic_screen_user(sb); } } @@ -1025,6 +1072,11 @@ void drm_panic_unregister(struct drm_device *dev) */ void __init drm_panic_init(void) { + if (drm_panic_type == -1 && drm_panic_type_set(CONFIG_DRM_PANIC_SCREEN, NULL)) { + pr_warn("Unsupported value for CONFIG_DRM_PANIC_SCREEN ('%s'), falling back to 'user'...\n", + CONFIG_DRM_PANIC_SCREEN); + drm_panic_type = DRM_PANIC_TYPE_USER; + } drm_panic_qr_init(); } @@ -1035,3 +1087,7 @@ void drm_panic_exit(void) { drm_panic_qr_exit(); } + +#ifdef CONFIG_DRM_KUNIT_TEST +#include "tests/drm_panic_test.c" +#endif diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index b143589717e64..bed2562bf911b 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -1867,9 +1867,9 @@ int drm_plane_create_color_pipeline_property(struct drm_plane *plane, prop = drm_property_create_enum(plane->dev, DRM_MODE_PROP_ATOMIC, "COLOR_PIPELINE", all_pipelines, len); - if (IS_ERR(prop)) { + if (!prop) { kfree(all_pipelines); - return PTR_ERR(prop); + return -ENOMEM; } drm_object_attach_property(&plane->base, prop, 0); diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c index 596272149a359..540cd41d8368f 100644 --- a/drivers/gpu/drm/drm_property.c +++ b/drivers/gpu/drm/drm_property.c @@ -562,7 +562,7 @@ drm_property_create_blob(struct drm_device *dev, size_t length, if (!length || length > INT_MAX - sizeof(struct drm_property_blob)) return ERR_PTR(-EINVAL); - blob = kvzalloc(sizeof(struct drm_property_blob)+length, GFP_KERNEL); + blob = kvzalloc(sizeof(struct drm_property_blob) + length, GFP_KERNEL_ACCOUNT); if (!blob) return ERR_PTR(-ENOMEM); @@ -757,6 +757,7 @@ EXPORT_SYMBOL(drm_property_replace_blob); * @dev: DRM device * @blob: a pointer to the member blob to be replaced * @blob_id: the id of the new blob to replace with + * @max_size: the maximum size of the blob property for variable-size blobs * @expected_size: expected size of the blob property * @expected_elem_size: expected size of an element in the blob property * @replaced: if the blob was in fact replaced @@ -771,6 +772,7 @@ EXPORT_SYMBOL(drm_property_replace_blob); int drm_property_replace_blob_from_id(struct drm_device *dev, struct drm_property_blob **blob, uint64_t blob_id, + ssize_t max_size, ssize_t expected_size, ssize_t expected_elem_size, bool *replaced) @@ -785,6 +787,15 @@ int drm_property_replace_blob_from_id(struct drm_device *dev, return -EINVAL; } + if (max_size > 0 && + new_blob->length > max_size) { + drm_dbg_atomic(dev, + "[BLOB:%d] length %zu greater than max %zu\n", + new_blob->base.id, new_blob->length, max_size); + drm_property_blob_put(new_blob); + return -EINVAL; + } + if (expected_size > 0 && new_blob->length != expected_size) { drm_dbg_atomic(dev, diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c index e1b0fa4000cdd..2d4ab745fdad9 100644 --- a/drivers/gpu/drm/drm_syncobj.c +++ b/drivers/gpu/drm/drm_syncobj.c @@ -250,14 +250,14 @@ struct drm_syncobj *drm_syncobj_find(struct drm_file *file_private, { struct drm_syncobj *syncobj; - spin_lock(&file_private->syncobj_table_lock); + xa_lock(&file_private->syncobj_xa); /* Check if we currently have a reference on the object */ - syncobj = idr_find(&file_private->syncobj_idr, handle); + syncobj = xa_load(&file_private->syncobj_xa, handle); if (syncobj) drm_syncobj_get(syncobj); - spin_unlock(&file_private->syncobj_table_lock); + xa_unlock(&file_private->syncobj_xa); return syncobj; } @@ -598,23 +598,15 @@ int drm_syncobj_get_handle(struct drm_file *file_private, { int ret; - /* take a reference to put in the idr */ + /* take a reference to put in the xarray */ drm_syncobj_get(syncobj); - idr_preload(GFP_KERNEL); - spin_lock(&file_private->syncobj_table_lock); - ret = idr_alloc(&file_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT); - spin_unlock(&file_private->syncobj_table_lock); - - idr_preload_end(); - - if (ret < 0) { + ret = xa_alloc(&file_private->syncobj_xa, handle, syncobj, xa_limit_32b, + GFP_NOWAIT); + if (ret) drm_syncobj_put(syncobj); - return ret; - } - *handle = ret; - return 0; + return ret; } EXPORT_SYMBOL(drm_syncobj_get_handle); @@ -638,10 +630,7 @@ static int drm_syncobj_destroy(struct drm_file *file_private, { struct drm_syncobj *syncobj; - spin_lock(&file_private->syncobj_table_lock); - syncobj = idr_remove(&file_private->syncobj_idr, handle); - spin_unlock(&file_private->syncobj_table_lock); - + syncobj = xa_erase(&file_private->syncobj_xa, handle); if (!syncobj) return -EINVAL; @@ -722,20 +711,13 @@ static int drm_syncobj_fd_to_handle(struct drm_file *file_private, if (fd_file(f)->f_op != &drm_syncobj_file_fops) return -EINVAL; - /* take a reference to put in the idr */ + /* take a reference to put in the xarray */ syncobj = fd_file(f)->private_data; drm_syncobj_get(syncobj); - idr_preload(GFP_KERNEL); - spin_lock(&file_private->syncobj_table_lock); - ret = idr_alloc(&file_private->syncobj_idr, syncobj, 1, 0, GFP_NOWAIT); - spin_unlock(&file_private->syncobj_table_lock); - idr_preload_end(); - - if (ret > 0) { - *handle = ret; - ret = 0; - } else + ret = xa_alloc(&file_private->syncobj_xa, handle, syncobj, xa_limit_32b, + GFP_NOWAIT); + if (ret) drm_syncobj_put(syncobj); return ret; @@ -814,17 +796,7 @@ static int drm_syncobj_export_sync_file(struct drm_file *file_private, void drm_syncobj_open(struct drm_file *file_private) { - idr_init_base(&file_private->syncobj_idr, 1); - spin_lock_init(&file_private->syncobj_table_lock); -} - -static int -drm_syncobj_release_handle(int id, void *ptr, void *data) -{ - struct drm_syncobj *syncobj = ptr; - - drm_syncobj_put(syncobj); - return 0; + xa_init_flags(&file_private->syncobj_xa, XA_FLAGS_ALLOC1); } /** @@ -838,9 +810,12 @@ drm_syncobj_release_handle(int id, void *ptr, void *data) void drm_syncobj_release(struct drm_file *file_private) { - idr_for_each(&file_private->syncobj_idr, - &drm_syncobj_release_handle, file_private); - idr_destroy(&file_private->syncobj_idr); + struct drm_syncobj *syncobj; + unsigned long handle; + + xa_for_each(&file_private->syncobj_xa, handle, syncobj) + drm_syncobj_put(syncobj); + xa_destroy(&file_private->syncobj_xa); } int diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index 5c14140cd0c20..42fe11cc139b9 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -551,7 +551,7 @@ int drm_vblank_init(struct drm_device *dev, unsigned int num_crtcs) dev->num_crtcs = num_crtcs; for (i = 0; i < num_crtcs; i++) { - struct drm_vblank_crtc *vblank = &dev->vblank[i]; + struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, i); vblank->dev = dev; vblank->pipe = i; @@ -605,7 +605,9 @@ EXPORT_SYMBOL(drm_dev_has_vblank); */ wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc) { - return &crtc->dev->vblank[drm_crtc_index(crtc)].queue; + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); + + return &vblank->queue; } EXPORT_SYMBOL(drm_crtc_vblank_waitqueue); @@ -710,7 +712,6 @@ drm_crtc_vblank_helper_get_vblank_timestamp_internal( { struct drm_device *dev = crtc->dev; unsigned int pipe = crtc->index; - struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; struct timespec64 ts_etime, ts_vblank_time; ktime_t stime, etime; bool vbl_status; @@ -729,10 +730,13 @@ drm_crtc_vblank_helper_get_vblank_timestamp_internal( return false; } - if (drm_drv_uses_atomic_modeset(dev)) + if (drm_drv_uses_atomic_modeset(dev)) { + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); + mode = &vblank->hwmode; - else + } else { mode = &crtc->hwmode; + } /* If mode timing undefined, just return as no-op: * Happens during initial modesetting of a crtc. @@ -1285,29 +1289,27 @@ void drm_crtc_vblank_put(struct drm_crtc *crtc) EXPORT_SYMBOL(drm_crtc_vblank_put); /** - * drm_wait_one_vblank - wait for one vblank - * @dev: DRM device - * @pipe: CRTC index + * drm_crtc_wait_one_vblank - wait for one vblank + * @crtc: DRM crtc * - * This waits for one vblank to pass on @pipe, using the irq driver interfaces. - * It is a failure to call this when the vblank irq for @pipe is disabled, e.g. + * This waits for one vblank to pass on @crtc, using the irq driver interfaces. + * It is a failure to call this when the vblank irq for @crtc is disabled, e.g. * due to lack of driver support or because the crtc is off. * - * This is the legacy version of drm_crtc_wait_one_vblank(). + * Returns: 0 on success, negative error on failures. */ -void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe) +int drm_crtc_wait_one_vblank(struct drm_crtc *crtc) { - struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe); + struct drm_device *dev = crtc->dev; + int pipe = drm_crtc_index(crtc); + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); int ret; u64 last; - if (drm_WARN_ON(dev, pipe >= dev->num_crtcs)) - return; - ret = drm_vblank_get(dev, pipe); if (drm_WARN(dev, ret, "vblank not available on crtc %i, ret=%i\n", pipe, ret)) - return; + return ret; last = drm_vblank_count(dev, pipe); @@ -1318,20 +1320,8 @@ void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe) drm_WARN(dev, ret == 0, "vblank wait timed out on crtc %i\n", pipe); drm_vblank_put(dev, pipe); -} -EXPORT_SYMBOL(drm_wait_one_vblank); -/** - * drm_crtc_wait_one_vblank - wait for one vblank - * @crtc: DRM crtc - * - * This waits for one vblank to pass on @crtc, using the irq driver interfaces. - * It is a failure to call this when the vblank irq for @crtc is disabled, e.g. - * due to lack of driver support or because the crtc is off. - */ -void drm_crtc_wait_one_vblank(struct drm_crtc *crtc) -{ - drm_wait_one_vblank(crtc->dev, drm_crtc_index(crtc)); + return ret ? 0 : -ETIMEDOUT; } EXPORT_SYMBOL(drm_crtc_wait_one_vblank); @@ -1794,7 +1784,7 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void *data, if (pipe >= dev->num_crtcs) return -EINVAL; - vblank = &dev->vblank[pipe]; + vblank = drm_vblank_crtc(dev, pipe); /* If the counter is currently enabled and accurate, short-circuit * queries to return the cached timestamp of the last vblank. diff --git a/drivers/gpu/drm/etnaviv/Makefile b/drivers/gpu/drm/etnaviv/Makefile index 46e5ffad69a6d..903101e8751a1 100644 --- a/drivers/gpu/drm/etnaviv/Makefile +++ b/drivers/gpu/drm/etnaviv/Makefile @@ -14,6 +14,7 @@ etnaviv-y := \ etnaviv_iommu.o \ etnaviv_mmu.o \ etnaviv_perfmon.o \ + etnaviv_flop_reset.o \ etnaviv_sched.o obj-$(CONFIG_DRM_ETNAVIV) += etnaviv.o diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c index ad5e6f7b23f95..03b2576af67fd 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c @@ -10,6 +10,7 @@ #include "etnaviv_gpu.h" #include "etnaviv_gem.h" #include "etnaviv_mmu.h" +#include "etnaviv_buffer.h" #include "common.xml.h" #include "state.xml.h" @@ -18,75 +19,7 @@ #include "state_3d.xml.h" #include "cmdstream.xml.h" -/* - * Command Buffer helper: - */ - - -static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data) -{ - u32 *vaddr = (u32 *)buffer->vaddr; - - BUG_ON(buffer->user_size >= buffer->size); - - vaddr[buffer->user_size / 4] = data; - buffer->user_size += 4; -} - -static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer, - u32 reg, u32 value) -{ - u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR; - - buffer->user_size = ALIGN(buffer->user_size, 8); - - /* write a register via cmd stream */ - OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE | - VIV_FE_LOAD_STATE_HEADER_COUNT(1) | - VIV_FE_LOAD_STATE_HEADER_OFFSET(index)); - OUT(buffer, value); -} - -static inline void CMD_END(struct etnaviv_cmdbuf *buffer) -{ - buffer->user_size = ALIGN(buffer->user_size, 8); - - OUT(buffer, VIV_FE_END_HEADER_OP_END); -} - -static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer, - unsigned int waitcycles) -{ - buffer->user_size = ALIGN(buffer->user_size, 8); - - OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | waitcycles); -} - -static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer, - u16 prefetch, u32 address) -{ - buffer->user_size = ALIGN(buffer->user_size, 8); - - OUT(buffer, VIV_FE_LINK_HEADER_OP_LINK | - VIV_FE_LINK_HEADER_PREFETCH(prefetch)); - OUT(buffer, address); -} - -static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer, - u32 from, u32 to) -{ - buffer->user_size = ALIGN(buffer->user_size, 8); - - OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL); - OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to)); -} - -static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to) -{ - CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN, - VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | - VIVS_GL_SEMAPHORE_TOKEN_TO(to)); -} +#include "etnaviv_flop_reset.h" static void etnaviv_cmd_select_pipe(struct etnaviv_gpu *gpu, struct etnaviv_cmdbuf *buffer, u8 pipe) @@ -170,6 +103,10 @@ u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu) /* initialize buffer */ buffer->user_size = 0; + /* Queue in PPU flop reset */ + if (etnaviv_flop_reset_ppu_require(&gpu->identity)) + etnaviv_flop_reset_ppu_run(gpu); + CMD_WAIT(buffer, gpu->fe_waitcycles); CMD_LINK(buffer, 2, etnaviv_cmdbuf_get_va(buffer, &gpu->mmu_context->cmdbuf_mapping) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.h b/drivers/gpu/drm/etnaviv/etnaviv_buffer.h new file mode 100644 index 0000000000000..4331ca8aac47d --- /dev/null +++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.h @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2014-2025 Etnaviv Project + */ + +#ifndef __ETNAVIV_BUFFER_H__ +#define __ETNAVIV_BUFFER_H__ + +#include "etnaviv_cmdbuf.h" +#include "etnaviv_gpu.h" +#include "etnaviv_gem.h" +#include "etnaviv_mmu.h" + +#include "common.xml.h" +#include "linux/printk.h" +#include "state.xml.h" +#include "state_blt.xml.h" +#include "state_hi.xml.h" +#include "state_3d.xml.h" +#include "cmdstream.xml.h" + +static inline void OUT(struct etnaviv_cmdbuf *buffer, u32 data) +{ + u32 *vaddr = (u32 *)buffer->vaddr; + + BUG_ON(buffer->user_size >= buffer->size); + + vaddr[buffer->user_size / 4] = data; + buffer->user_size += 4; +} + +static inline void CMD_LOAD_STATE(struct etnaviv_cmdbuf *buffer, u32 reg, + u32 value) +{ + u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR; + + buffer->user_size = ALIGN(buffer->user_size, 8); + + /* write a register via cmd stream */ + OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE | + VIV_FE_LOAD_STATE_HEADER_COUNT(1) | + VIV_FE_LOAD_STATE_HEADER_OFFSET(index)); + OUT(buffer, value); +} + +static inline void CMD_LOAD_STATES_START(struct etnaviv_cmdbuf *buffer, u32 reg, + u32 nvalues) +{ + u32 index = reg >> VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR; + + buffer->user_size = ALIGN(buffer->user_size, 8); + + /* write a register via cmd stream */ + OUT(buffer, VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE | + VIV_FE_LOAD_STATE_HEADER_OFFSET(index) | + VIV_FE_LOAD_STATE_HEADER_COUNT(nvalues)); +} + +static inline void CMD_END(struct etnaviv_cmdbuf *buffer) +{ + buffer->user_size = ALIGN(buffer->user_size, 8); + + OUT(buffer, VIV_FE_END_HEADER_OP_END); +} + +static inline void CMD_WAIT(struct etnaviv_cmdbuf *buffer, + unsigned int waitcycles) +{ + buffer->user_size = ALIGN(buffer->user_size, 8); + + OUT(buffer, VIV_FE_WAIT_HEADER_OP_WAIT | waitcycles); +} + +static inline void CMD_LINK(struct etnaviv_cmdbuf *buffer, u16 prefetch, + u32 address) +{ + buffer->user_size = ALIGN(buffer->user_size, 8); + + OUT(buffer, + VIV_FE_LINK_HEADER_OP_LINK | VIV_FE_LINK_HEADER_PREFETCH(prefetch)); + OUT(buffer, address); +} + +static inline void CMD_STALL(struct etnaviv_cmdbuf *buffer, u32 from, u32 to) +{ + buffer->user_size = ALIGN(buffer->user_size, 8); + + OUT(buffer, VIV_FE_STALL_HEADER_OP_STALL); + OUT(buffer, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to)); +} + +static inline void CMD_SEM(struct etnaviv_cmdbuf *buffer, u32 from, u32 to) +{ + CMD_LOAD_STATE(buffer, VIVS_GL_SEMAPHORE_TOKEN, + VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | + VIVS_GL_SEMAPHORE_TOKEN_TO(to)); +} + +#endif /* __ETNAVIV_BUFFER_H__ */ diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 54ceae87b4015..bb1b84eecec8d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -601,6 +601,9 @@ static void etnaviv_unbind(struct device *dev) component_unbind_all(dev, drm); + etnaviv_cmdbuf_free(priv->flop_reset_data_ppu); + kfree(priv->flop_reset_data_ppu); + etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); xa_destroy(&priv->active_contexts); diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h index b3eb1662e90c8..20dad16fd5542 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h @@ -48,6 +48,9 @@ struct etnaviv_drm_private { /* list of GEM objects: */ struct mutex gem_lock; struct list_head gem_list; + + /* ppu flop reset data */ + struct etnaviv_cmdbuf *flop_reset_data_ppu; }; int etnaviv_ioctl_gem_submit(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c new file mode 100644 index 0000000000000..58d957ee861d7 --- /dev/null +++ b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Etnaviv Project + */ + +#include +#include +#include +#include + +#include "etnaviv_buffer.h" +#include "etnaviv_cmdbuf.h" +#include "etnaviv_gpu.h" +#include "state_3d.xml.h" + +#include "etnaviv_flop_reset.h" + +static int etnaviv_force_flop_reset; +module_param_named(force_flop_reset, etnaviv_force_flop_reset, int, 0); + +#define PPU_IMAGE_STRIDE 64 +#define PPU_IMAGE_XSIZE 64 +#define PPU_IMAGE_YSIZE 6 + +#define PPU_FLOP_RESET_INSTR_DWORD_COUNT 16 + +static void etnaviv_emit_flop_reset_state_ppu(struct etnaviv_cmdbuf *cmdbuf, + u32 buffer_base, u32 input_offset, + u32 output_offset, + u32 shader_offset, + u32 shader_size, + u32 shader_register_count) +{ + CMD_LOAD_STATE(cmdbuf, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL); + CMD_SEM(cmdbuf, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); + CMD_STALL(cmdbuf, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); + + CMD_LOAD_STATES_START(cmdbuf, VIVS_SH_HALTI5_UNIFORMS(0), 4); + + OUT(cmdbuf, buffer_base + input_offset); + OUT(cmdbuf, PPU_IMAGE_STRIDE); + OUT(cmdbuf, PPU_IMAGE_XSIZE | (PPU_IMAGE_YSIZE << 16)); + OUT(cmdbuf, 0x444051f0); + OUT(cmdbuf, 0xffffffff); + + CMD_LOAD_STATES_START(cmdbuf, VIVS_SH_HALTI5_UNIFORMS(4), 4); + OUT(cmdbuf, buffer_base + output_offset); + OUT(cmdbuf, PPU_IMAGE_STRIDE); + OUT(cmdbuf, PPU_IMAGE_XSIZE | (PPU_IMAGE_YSIZE << 16)); + OUT(cmdbuf, 0x444051f0); + OUT(cmdbuf, 0xffffffff); + + CMD_LOAD_STATE(cmdbuf, VIVS_CL_CONFIG, + VIVS_CL_CONFIG_DIMENSIONS(2) | + VIVS_CL_CONFIG_VALUE_ORDER(3)); + CMD_LOAD_STATE(cmdbuf, VIVS_VS_ICACHE_INVALIDATE, 0x1f); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_VARYING_NUM_COMPONENTS(0), 0); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_TEMP_REGISTER_CONTROL, + shader_register_count); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_SAMPLER_BASE, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_UNIFORM_BASE, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_NEWRANGE_LOW, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_NEWRANGE_HIGH, shader_size / 16); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_INST_ADDR, buffer_base + shader_offset); + CMD_LOAD_STATE(cmdbuf, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING); + CMD_LOAD_STATE(cmdbuf, VIVS_VS_ICACHE_CONTROL, + VIVS_VS_ICACHE_CONTROL_ENABLE); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_ICACHE_COUNT, shader_size / 16 - 1); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_INPUT_COUNT, 0x1f01); + CMD_LOAD_STATE(cmdbuf, VIVS_VS_HALTI5_UNK008A0, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_PA_VS_OUTPUT_COUNT, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_GL_VARYING_TOTAL_COMPONENTS, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_CONTROL_EXT, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_VS_OUTPUT_COUNT, 0x1); + CMD_LOAD_STATE(cmdbuf, VIVS_GL_HALTI5_SH_SPECIALS, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_PS_ICACHE_PREFETCH, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_CL_UNK00924, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_CL_THREAD_ALLOCATION, 0x1); + + CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_X, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_Y, 0x0); + CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_Z, 0x0); + + CMD_LOAD_STATES_START(cmdbuf, VIVS_CL_WORKGROUP_COUNT_X, 9); + OUT(cmdbuf, 0xf); + OUT(cmdbuf, 0x5); + OUT(cmdbuf, 0xffffffff); + OUT(cmdbuf, 0x0); + OUT(cmdbuf, 0x0); + OUT(cmdbuf, 0x3ff); + OUT(cmdbuf, 0x0); + OUT(cmdbuf, 0x4); + OUT(cmdbuf, 0x1); + OUT(cmdbuf, 0x0); + + CMD_LOAD_STATE(cmdbuf, VIVS_CL_KICKER, 0xbadabeeb); + CMD_LOAD_STATE(cmdbuf, VIVS_GL_FLUSH_CACHE, + VIVS_GL_FLUSH_CACHE_SHADER_L1 | + VIVS_GL_FLUSH_CACHE_UNK10 | + VIVS_GL_FLUSH_CACHE_UNK11); +} + +static void etnaviv_flop_reset_ppu_fill_input(u32 *buffer, u32 size) +{ + memset32(buffer, 0x01010101, size / 4); +} + +static void etnaviv_flop_reset_ppu_set_shader(u8 *dest) +{ + static const u32 inst[PPU_FLOP_RESET_INSTR_DWORD_COUNT] = { + /* img_load.u8 r1, c0, r0.xy */ + 0x78011779, + 0x39000804, + 0x00A90050, + 0x00000000, + /* img_load.u8 r2, c0, r0.xy */ + 0x78021779, + 0x39000804, + 0x00A90050, + 0x00000000, + /* dp2x8 r1, r1, r2, c3_512 */ + 0xB8017145, + 0x390018FC, + 0x01C90140, + 0x40390028, + /* img_store.u8 r1, c2, r0.xy, r1 */ + 0x380007BA, + 0x39001804, + 0x00A90050, + 0x00390018, + }; + memcpy(dest, inst, sizeof(inst)); +} + +static const struct etnaviv_flop_reset_entry { + u16 chip_model; + u16 revision; + u32 flags; +} etnaviv_flop_reset_db[] = { + { + .chip_model = 0x8000, + .revision = 0x6205, + }, +}; + +bool etnaviv_flop_reset_ppu_require(const struct etnaviv_chip_identity *chip_id) +{ + const struct etnaviv_flop_reset_entry *e = etnaviv_flop_reset_db; + + for (int i = 0; i < ARRAY_SIZE(etnaviv_flop_reset_db); ++i, ++e) { + if (chip_id->model == e->chip_model && + chip_id->revision == e->revision) + return true; + } + + if (etnaviv_force_flop_reset) { + if (!(chip_id->features & chipFeatures_PIPE_3D)) { + pr_warn("Etnaviv: model: 0x%04x, revision: 0x%04x does not support PIPE_3D\n", + chip_id->model, chip_id->revision); + pr_warn("Request to force PPU flop reset ignored.\n"); + return false; + } + + pr_info("Force PPU flop reset for model: 0x%04x, revision: 0x%04x\n", + chip_id->model, chip_id->revision); + return true; + } + + return false; +} + +static const u32 image_data_size = PPU_IMAGE_STRIDE * PPU_IMAGE_YSIZE; +static const u32 output_offset = ALIGN(image_data_size, 64); +static const u32 shader_offset = ALIGN(output_offset + image_data_size, 64); +static const u32 shader_size = PPU_FLOP_RESET_INSTR_DWORD_COUNT * sizeof(u32); +static const u32 shader_register_count = 3; +static const u32 buffer_size = shader_offset + shader_size; + +int etnaviv_flop_reset_ppu_init(struct etnaviv_drm_private *priv) +{ + /* Get some space from the ring buffer to put the payload + * (input and output image, and shader), we keep this buffer + * for the whole life time the driver is bound + */ + priv->flop_reset_data_ppu = + kzalloc(sizeof(*priv->flop_reset_data_ppu), GFP_KERNEL); + + if (!priv->flop_reset_data_ppu) + return -ENOMEM; + + int ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, + priv->flop_reset_data_ppu, buffer_size); + if (ret) { + kfree(priv->flop_reset_data_ppu); + return ret; + } + + void *buffer_base = priv->flop_reset_data_ppu->vaddr; + u32 *input_data = (u32 *)buffer_base; + u8 *shader_data = (u8 *)buffer_base + shader_offset; + + etnaviv_flop_reset_ppu_fill_input(input_data, image_data_size); + etnaviv_flop_reset_ppu_set_shader(shader_data); + + return 0; +} + +void etnaviv_flop_reset_ppu_run(struct etnaviv_gpu *gpu) +{ + struct etnaviv_drm_private *priv = gpu->drm->dev_private; + + if (!priv->flop_reset_data_ppu) { + dev_err(gpu->dev, + "Oops: Flop reset data was not initialized, skipping\n"); + return; + } + + u32 buffer_base = etnaviv_cmdbuf_get_va(priv->flop_reset_data_ppu, + &gpu->mmu_context->cmdbuf_mapping); + + etnaviv_emit_flop_reset_state_ppu(&gpu->buffer, buffer_base, 0, + output_offset, shader_offset, + shader_size, shader_register_count); +} diff --git a/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.h b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.h new file mode 100644 index 0000000000000..e6dee1db788f6 --- /dev/null +++ b/drivers/gpu/drm/etnaviv/etnaviv_flop_reset.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2025 Etnaviv Project + */ + +#ifndef _ETNAVIV_FLOP_RESET_H_ +#define _ETNAVIV_FLOP_RESET_H_ + +#include + +struct etnaviv_chip_identity; +struct etnaviv_drm_private; +struct etnaviv_gpu; + +bool etnaviv_flop_reset_ppu_require(const struct etnaviv_chip_identity *chip_id); + +int etnaviv_flop_reset_ppu_init(struct etnaviv_drm_private *priv); + +void etnaviv_flop_reset_ppu_run(struct etnaviv_gpu *gpu); + +#endif diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index ca0be293f5fee..94326dddaf6fb 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -20,6 +20,7 @@ #include "etnaviv_cmdbuf.h" #include "etnaviv_dump.h" +#include "etnaviv_flop_reset.h" #include "etnaviv_gpu.h" #include "etnaviv_gem.h" #include "etnaviv_mmu.h" @@ -839,6 +840,16 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) goto fail; } + if (etnaviv_flop_reset_ppu_require(&gpu->identity) && + !priv->flop_reset_data_ppu) { + ret = etnaviv_flop_reset_ppu_init(priv); + if (ret) { + dev_err(gpu->dev, + "Unable to initialize PPU flop reset data\n"); + goto fail; + } + } + if (gpu->identity.nn_core_count > 0) dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " "for which the UAPI is still experimental\n"); diff --git a/drivers/gpu/drm/etnaviv/state_3d.xml.h b/drivers/gpu/drm/etnaviv/state_3d.xml.h index ebbd4fcf3096b..a654c05414eca 100644 --- a/drivers/gpu/drm/etnaviv/state_3d.xml.h +++ b/drivers/gpu/drm/etnaviv/state_3d.xml.h @@ -4,6 +4,101 @@ /* This is a cut-down version of the state_3d.xml.h file */ +#define VIVS_CL_CONFIG 0x00000900 +#define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 +#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 +#define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) +#define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK 0x00000070 +#define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT 4 +#define VIVS_CL_CONFIG_TRAVERSE_ORDER(x) (((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK) +#define VIVS_CL_CONFIG_ENABLE_SWATH_X 0x00000100 +#define VIVS_CL_CONFIG_ENABLE_SWATH_Y 0x00000200 +#define VIVS_CL_CONFIG_ENABLE_SWATH_Z 0x00000400 +#define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK 0x0000f000 +#define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT 12 +#define VIVS_CL_CONFIG_SWATH_SIZE_X(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK) +#define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK 0x000f0000 +#define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT 16 +#define VIVS_CL_CONFIG_SWATH_SIZE_Y(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK) +#define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK 0x00f00000 +#define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT 20 +#define VIVS_CL_CONFIG_SWATH_SIZE_Z(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK) + +#define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 +#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 +#define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) + +#define VIVS_CL_CONFIG_VALUE_ORDER__MASK 0x07000000 +#define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT 24 +#define VIVS_CL_CONFIG_VALUE_ORDER(x) (((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK) + +#define VIVS_CL_GLOBAL_WORK_OFFSET_X 0x0000092c +#define VIVS_CL_GLOBAL_WORK_OFFSET_Y 0x00000934 +#define VIVS_CL_GLOBAL_WORK_OFFSET_Z 0x0000093c + +#define VIVS_CL_KICKER 0x00000920 +#define VIVS_CL_THREAD_ALLOCATION 0x0000091c +#define VIVS_CL_UNK00924 0x00000924 + +#define VIVS_CL_WORKGROUP_COUNT_X 0x00000940 +#define VIVS_CL_WORKGROUP_COUNT_Y 0x00000944 +#define VIVS_CL_WORKGROUP_COUNT_Z 0x00000948 +#define VIVS_CL_WORKGROUP_SIZE_X 0x0000094c +#define VIVS_CL_WORKGROUP_SIZE_Y 0x00000950 +#define VIVS_CL_WORKGROUP_SIZE_Z 0x00000954 + +#define VIVS_CL_GLOBAL_SCALE_X 0x00000958 +#define VIVS_CL_GLOBAL_SCALE_Y 0x0000095c +#define VIVS_CL_GLOBAL_SCALE_Z 0x00000960 + +#define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8 +#define VIVS_PS_CONTROL_EXT 0x00001030 +#define VIVS_PS_ICACHE_COUNT 0x00001094 +#define VIVS_PS_ICACHE_PREFETCH 0x00001048 + +#define VIVS_PS_INPUT_COUNT 0x00001008 +#define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000001f +#define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0 +#define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK) + +#define VIVS_PS_NEWRANGE_LOW 0x0000087c +#define VIVS_PS_NEWRANGE_HIGH 0x00001090 +#define VIVS_PS_SAMPLER_BASE 0x00001058 + +#define VIVS_PS_UNIFORM_BASE 0x00001024 +#define VIVS_PS_INST_ADDR 0x00001028 + +#define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c +#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f +#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 +#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) + +#define VIVS_PS_VARYING_NUM_COMPONENTS(i0) (0x00001080 + 0x4*(i0)) +#define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE 0x00000004 +#define VIVS_PS_VARYING_NUM_COMPONENTS__LEN 0x00000004 + +#define VIVS_SH_CONFIG 0x00015600 +#define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002 + +#define VIVS_SH_HALTI5_UNIFORMS(i0) (0x00036000 + 0x4*(i0)) +#define VIVS_SH_HALTI5_UNIFORMS__ESIZE 0x00000004 +#define VIVS_SH_HALTI5_UNIFORMS__LEN 0x00000800 + +#define VIVS_VS_HALTI5_UNK008A0 0x000008a0 +#define VIVS_VS_HALTI5_UNK008A0_A__MASK 0x0000003f +#define VIVS_VS_HALTI5_UNK008A0_A__SHIFT 0 +#define VIVS_VS_HALTI5_UNK008A0_A(x) (((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK) + +#define VIVS_VS_ICACHE_CONTROL 0x00000868 +#define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001 + +#define VIVS_VS_ICACHE_INVALIDATE 0x000008b0 + +#define VIVS_VS_OUTPUT_COUNT 0x00000804 +#define VIVS_VS_OUTPUT_COUNT_COUNT__MASK 0x000000ff +#define VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT 0 +#define VIVS_VS_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_OUTPUT_COUNT_COUNT__MASK) + #define VIVS_TS_FLUSH_CACHE 0x00001650 #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 8e76ac8ee4e24..09b2cabb236f3 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1779,7 +1779,7 @@ static int hdmi_bridge_init(struct hdmi_context *hdata) return -EINVAL; } - hdata->bridge = of_drm_find_bridge(np); + hdata->bridge = of_drm_find_and_get_bridge(np); of_node_put(np); if (!hdata->bridge) @@ -2096,6 +2096,8 @@ static void hdmi_remove(struct platform_device *pdev) put_device(&hdata->ddc_adpt->dev); + drm_bridge_put(hdata->bridge); + mutex_destroy(&hdata->mutex); } diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h index 4add05c7f161a..f9ee7ebfec55c 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -40,6 +40,10 @@ struct hibmc_dp_dev { struct mutex lock; /* protects concurrent RW in hibmc_dp_reg_write_field() */ struct hibmc_dp_link link; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; + struct drm_dp_desc desc; + bool is_branch; + int hpd_status; void __iomem *serdes_base; }; diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h index 08f9e1caf7fcb..efb30a7584758 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_config.h @@ -17,5 +17,7 @@ #define HIBMC_DP_LINK_RATE_CAL 27 #define HIBMC_DP_SYNC_DELAY(lanes) ((lanes) == 0x2 ? 86 : 46) #define HIBMC_DP_INT_ENABLE 0xc +/* HIBMC_DP_LINK_RATE_CAL * 10000 * 80% = 216000 */ +#define DP_MODE_VALI_CAL 216000 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c index 8f0daec7d1749..d5bd3c45649b2 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -2,6 +2,7 @@ // Copyright (c) 2024 Hisilicon Limited. #include +#include #include #include "dp_config.h" #include "dp_comm.h" @@ -176,13 +177,18 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) dp_dev->link.cap.lanes = 0x2; dp_dev->link.cap.link_rate = DP_LINK_BW_8_1; - /* hdcp data */ - writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); /* int init */ writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); + /* clr colorbar */ + writel(0, dp_dev->base + HIBMC_DP_COLOR_BAR_CTRL); /* rst */ + writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + usleep_range(30, 50); + /* de-rst */ writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); + /* hdcp data */ + writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); /* clock enable */ writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); @@ -263,6 +269,16 @@ void hibmc_dp_reset_link(struct hibmc_dp *dp) dp->dp_dev->link.status.channel_equalized = false; } +u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.link_rate; +} + +u8 hibmc_dp_get_lanes(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.lanes; +} + static const struct hibmc_dp_color_raw g_rgb_raw[] = { {CBAR_COLOR_BAR, 0x000, 0x000, 0x000}, {CBAR_WHITE, 0xfff, 0xfff, 0xfff}, @@ -305,3 +321,21 @@ void hibmc_dp_set_cbar(struct hibmc_dp *dp, const struct hibmc_dp_cbar_cfg *cfg) hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(0), cfg->enable); writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL); } + +bool hibmc_dp_check_hpd_status(struct hibmc_dp *dp, int exp_status) +{ + u32 status; + int ret; + + ret = readl_poll_timeout(dp->dp_dev->base + HIBMC_DP_HPD_STATUS, status, + FIELD_GET(HIBMC_DP_HPD_CUR_STATE, status) == exp_status, + 1000, 100000); /* DP spec says 100ms */ + if (ret) { + drm_dbg_dp(dp->drm_dev, "wait hpd status timeout"); + return false; + } + + dp->dp_dev->hpd_status = exp_status; + + return true; +} diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h index 665f5b166dfb5..31316fe1ea8db 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -14,6 +14,11 @@ struct hibmc_dp_dev; +enum hibmc_hpd_status { + HIBMC_HPD_OUT, + HIBMC_HPD_IN, +}; + enum hibmc_dp_cbar_pattern { CBAR_COLOR_BAR, CBAR_WHITE, @@ -60,5 +65,8 @@ void hibmc_dp_reset_link(struct hibmc_dp *dp); void hibmc_dp_hpd_cfg(struct hibmc_dp *dp); void hibmc_dp_enable_int(struct hibmc_dp *dp); void hibmc_dp_disable_int(struct hibmc_dp *dp); +bool hibmc_dp_check_hpd_status(struct hibmc_dp *dp, int exp_status); +u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp); +u8 hibmc_dp_get_lanes(struct hibmc_dp *dp); #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h index 394b1e933c3ae..64306abcd9866 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h @@ -24,6 +24,9 @@ #define HIBMC_DP_CFG_AUX_READY_DATA_BYTE GENMASK(16, 12) #define HIBMC_DP_CFG_AUX GENMASK(24, 17) +#define HIBMC_DP_HPD_STATUS 0x98 +#define HIBMC_DP_HPD_CUR_STATE GENMASK(7, 4) + #define HIBMC_DP_PHYIF_CTRL0 0xa0 #define HIBMC_DP_CFG_SCRAMBLE_EN BIT(0) #define HIBMC_DP_CFG_PAT_SEL GENMASK(7, 4) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c index d06832e62e966..616821e3c933b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -12,6 +12,8 @@ #include "hibmc_drm_drv.h" #include "dp/dp_hw.h" +#include "dp/dp_comm.h" +#include "dp/dp_config.h" #define DP_MASKED_SINK_HPD_PLUG_INT BIT(2) @@ -31,17 +33,76 @@ static int hibmc_dp_connector_get_modes(struct drm_connector *connector) return count; } +static bool hibmc_dp_get_dpcd(struct hibmc_dp_dev *dp_dev) +{ + int ret; + + ret = drm_dp_read_dpcd_caps(dp_dev->aux, dp_dev->dpcd); + if (ret) + return false; + + dp_dev->is_branch = drm_dp_is_branch(dp_dev->dpcd); + + ret = drm_dp_read_desc(dp_dev->aux, &dp_dev->desc, dp_dev->is_branch); + if (ret) + return false; + + ret = drm_dp_read_downstream_info(dp_dev->aux, dp_dev->dpcd, dp_dev->downstream_ports); + if (ret) + return false; + + return true; +} + static int hibmc_dp_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, bool force) { - mdelay(200); + struct hibmc_dp *dp = to_hibmc_dp(connector); + struct hibmc_dp_dev *dp_dev = dp->dp_dev; + int ret; + + if (dp->irq_status) { + if (dp_dev->hpd_status != HIBMC_HPD_IN) + return connector_status_disconnected; + } + + if (!hibmc_dp_get_dpcd(dp_dev)) + return connector_status_disconnected; + + if (!dp_dev->is_branch) + return connector_status_connected; + + if (drm_dp_read_sink_count_cap(connector, dp_dev->dpcd, &dp_dev->desc) && + dp_dev->downstream_ports[0] & DP_DS_PORT_HPD) { + ret = drm_dp_read_sink_count(dp_dev->aux); + if (ret > 0) + return connector_status_connected; + } + + return connector_status_disconnected; +} + +static int hibmc_dp_mode_valid(struct drm_connector *connector, + const struct drm_display_mode *mode, + struct drm_modeset_acquire_ctx *ctx, + enum drm_mode_status *status) +{ + struct hibmc_dp *dp = to_hibmc_dp(connector); + u64 cur_val, max_val; - return drm_connector_helper_detect_from_ddc(connector, ctx, force); + /* check DP link BW */ + cur_val = (u64)mode->clock * HIBMC_DP_BPP; + max_val = (u64)hibmc_dp_get_link_rate(dp) * DP_MODE_VALI_CAL * hibmc_dp_get_lanes(dp); + + *status = cur_val > max_val ? MODE_CLOCK_HIGH : MODE_OK; + + return 0; } static const struct drm_connector_helper_funcs hibmc_dp_conn_helper_funcs = { .get_modes = hibmc_dp_connector_get_modes, .detect_ctx = hibmc_dp_detect, + .mode_valid_ctx = hibmc_dp_mode_valid, }; static int hibmc_dp_late_register(struct drm_connector *connector) @@ -115,7 +176,7 @@ irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg) { struct drm_device *dev = (struct drm_device *)arg; struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); - int idx; + int idx, exp_status; if (!drm_dev_enter(dev, &idx)) return -ENODEV; @@ -123,12 +184,14 @@ irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg) if (priv->dp.irq_status & DP_MASKED_SINK_HPD_PLUG_INT) { drm_dbg_dp(&priv->dev, "HPD IN isr occur!\n"); hibmc_dp_hpd_cfg(&priv->dp); + exp_status = HIBMC_HPD_IN; } else { drm_dbg_dp(&priv->dev, "HPD OUT isr occur!\n"); hibmc_dp_reset_link(&priv->dp); + exp_status = HIBMC_HPD_OUT; } - if (dev->registered) + if (hibmc_dp_check_hpd_status(&priv->dp, exp_status)) drm_connector_helper_hpd_irq_event(&priv->dp.connector); drm_dev_exit(idx); diff --git a/drivers/gpu/drm/hyperv/Kconfig b/drivers/gpu/drm/hyperv/Kconfig new file mode 100644 index 0000000000000..86234f6a73f2a --- /dev/null +++ b/drivers/gpu/drm/hyperv/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config DRM_HYPERV + tristate "DRM Support for Hyper-V synthetic video device" + depends on DRM && PCI && HYPERV_VMBUS + select DRM_CLIENT_SELECTION + select DRM_KMS_HELPER + select DRM_GEM_SHMEM_HELPER + help + This is a KMS driver for Hyper-V synthetic video device. Choose this + option if you would like to enable drm driver for Hyper-V virtual + machine. Unselect Hyper-V framebuffer driver (CONFIG_FB_HYPERV) so + that DRM driver is used by default. + + If M is selected the module will be called hyperv_drm. diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 4db24050edb0e..241b1d2e2603f 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -27,7 +27,10 @@ i915-y += \ i915_config.o \ i915_driver.o \ i915_drm_client.o \ + i915_edram.o \ + i915_freq.o \ i915_getparam.o \ + i915_gmch.o \ i915_ioctl.o \ i915_irq.o \ i915_mitigations.o \ @@ -54,12 +57,6 @@ i915-y += \ vlv_iosf_sb.o \ vlv_suspend.o -# core peripheral code -i915-y += \ - soc/intel_dram.o \ - soc/intel_gmch.o \ - soc/intel_rom.o - # core library code i915-y += \ i915_memcpy.o \ @@ -77,6 +74,13 @@ i915-$(CONFIG_DEBUG_FS) += \ i915-$(CONFIG_PERF_EVENTS) += \ i915_pmu.o +# core display adaptation +i915-y += \ + i915_display_pc8.o \ + i915_hdcp_gsc.o \ + i915_initial_plane.o \ + i915_panic.o + # "Graphics Technology" (aka we talk to the gpu) gt-y += \ gt/gen2_engine_cs.o \ @@ -170,8 +174,7 @@ gem-y += \ gem/i915_gem_ttm_move.o \ gem/i915_gem_ttm_pm.o \ gem/i915_gem_userptr.o \ - gem/i915_gem_wait.o \ - gem/i915_gemfs.o + gem/i915_gem_wait.o i915-y += \ $(gem-y) \ i915_active.o \ @@ -268,6 +271,7 @@ i915-y += \ display/intel_dpll_mgr.o \ display/intel_dpt.o \ display/intel_dpt_common.o \ + display/intel_dram.o \ display/intel_drrs.o \ display/intel_dsb.o \ display/intel_dsb_buffer.o \ @@ -281,11 +285,11 @@ i915-y += \ display/intel_frontbuffer.o \ display/intel_global_state.o \ display/intel_hdcp.o \ - display/intel_hdcp_gsc.o \ display/intel_hdcp_gsc_message.o \ display/intel_hotplug.o \ display/intel_hotplug_irq.o \ display/intel_hti.o \ + display/intel_initial_plane.o \ display/intel_link_bw.o \ display/intel_load_detect.o \ display/intel_lpe_audio.o \ @@ -293,15 +297,15 @@ i915-y += \ display/intel_modeset_setup.o \ display/intel_modeset_verify.o \ display/intel_overlay.o \ - display/intel_panic.o \ + display/intel_parent.o \ display/intel_pch.o \ display/intel_pch_display.o \ display/intel_pch_refclk.o \ display/intel_plane.o \ - display/intel_plane_initial.o \ display/intel_pmdemand.o \ display/intel_psr.o \ display/intel_quirks.o \ + display/intel_rom.o \ display/intel_sbi.o \ display/intel_sprite.o \ display/intel_sprite_uapi.o \ @@ -378,6 +382,9 @@ i915-y += \ i915-$(CONFIG_DRM_I915_DP_TUNNEL) += \ display/intel_dp_tunnel.o +i915-$(CONFIG_DRM_I915_GVT) += \ + display/intel_gvt_api.o + i915-y += \ i915_perf.o diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index a3ff21b2f69fe..4cb753177fd8e 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -302,7 +302,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; wakeref = intel_display_power_get_if_enabled(display, @@ -684,12 +684,11 @@ static void intel_enable_dp(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(state); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); u32 dp_reg = intel_de_read(display, intel_dp->output_reg); - intel_wakeref_t wakeref; if (drm_WARN_ON(display->drm, dp_reg & DP_PORT_EN)) return; - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { if (display->platform.valleyview || display->platform.cherryview) vlv_pps_port_enable_unlocked(encoder, pipe_config); diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c index f6e2d1ed56397..8b22447e8e234 100644 --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c @@ -68,7 +68,7 @@ static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; wakeref = intel_display_power_get_if_enabled(display, diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 51ccc6bd5f215..b1fecf1789061 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -22,7 +22,6 @@ #include "intel_fb.h" #include "intel_fbc.h" #include "intel_frontbuffer.h" -#include "intel_panic.h" #include "intel_plane.h" #include "intel_sprite.h" @@ -134,7 +133,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display, enum i9xx_plane_id i9xx_plane) { if (i9xx_plane_has_fbc(display, i9xx_plane)) - return display->fbc[INTEL_FBC_A]; + return display->fbc.instances[INTEL_FBC_A]; else return NULL; } @@ -724,7 +723,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; u32 val; @@ -819,7 +818,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); - if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) + if (intel_plane_can_async_flip(plane, fb->format, fb->modifier)) return 256 * 1024; /* FIXME undocumented so not sure what's actually needed */ @@ -843,7 +842,7 @@ static unsigned int g4x_primary_min_alignment(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); - if (intel_plane_can_async_flip(plane, fb->format->format, fb->modifier)) + if (intel_plane_can_async_flip(plane, fb->format, fb->modifier)) return 256 * 1024; if (intel_scanout_needs_vtd_wa(display)) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 01f3803fa09f1..39dfceb438ae4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -7,9 +7,6 @@ #include -#include "soc/intel_dram.h" - -#include "i915_drv.h" #include "i915_reg.h" #include "i9xx_wm.h" #include "i9xx_wm_regs.h" @@ -19,6 +16,8 @@ #include "intel_display.h" #include "intel_display_regs.h" #include "intel_display_trace.h" +#include "intel_display_utils.h" +#include "intel_dram.h" #include "intel_fb.h" #include "intel_mchbar_regs.h" #include "intel_wm.h" @@ -91,7 +90,7 @@ static const struct cxsr_latency cxsr_latency_table[] = { static const struct cxsr_latency *pnv_get_cxsr_latency(struct intel_display *display) { - const struct dram_info *dram_info = intel_dram_info(display->drm); + const struct dram_info *dram_info = intel_dram_info(display); bool is_ddr3 = dram_info->type == INTEL_DRAM_DDR3; int i; @@ -1864,8 +1863,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_uncore *uncore = &dev_priv->uncore; + struct intel_uncore *uncore = to_intel_uncore(display->drm); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct vlv_fifo_state *fifo_state = @@ -2744,12 +2742,12 @@ static void ilk_compute_wm_level(struct intel_display *display, static void hsw_read_wm_latency(struct intel_display *display, u16 wm[]) { - struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_uncore *uncore = to_intel_uncore(display->drm); u64 sskpd; display->wm.num_levels = 5; - sskpd = intel_uncore_read64(&i915->uncore, MCH_SSKPD); + sskpd = intel_uncore_read64(uncore, MCH_SSKPD); wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd); if (wm[0] == 0) @@ -2762,12 +2760,12 @@ static void hsw_read_wm_latency(struct intel_display *display, u16 wm[]) static void snb_read_wm_latency(struct intel_display *display, u16 wm[]) { - struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 sskpd; display->wm.num_levels = 4; - sskpd = intel_uncore_read(&i915->uncore, MCH_SSKPD); + sskpd = intel_uncore_read(uncore, MCH_SSKPD); wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd); wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd); @@ -2777,12 +2775,12 @@ static void snb_read_wm_latency(struct intel_display *display, u16 wm[]) static void ilk_read_wm_latency(struct intel_display *display, u16 wm[]) { - struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 mltr; display->wm.num_levels = 3; - mltr = intel_uncore_read(&i915->uncore, MLTR_ILK); + mltr = intel_uncore_read(uncore, MLTR_ILK); /* ILK primary LP0 latency is 700 ns */ wm[0] = 7; diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 9230792960f29..dac781f546617 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1411,7 +1411,7 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); intel_display_power_put(display, @@ -1722,7 +1722,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum transcoder dsi_trans; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; enum port port; bool ret = false; u32 tmp; diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 6372f533f65b5..7ce8c674bb030 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -326,11 +326,9 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, if (intel_dp->as_sdp_supported) { u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1; - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & - DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP) + if (crtc_state->link_off_after_as_sdp_when_pr_active) pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU; - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & - DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR)) + if (crtc_state->disable_as_sdp_when_pr_active) pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE; intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder), diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index 53599b464deaa..c6a4ec5b9561f 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -1,5 +1,5 @@ -/* SPDX-License-Identifier: MIT - * +/* SPDX-License-Identifier: MIT */ +/* * Copyright © 2024 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 5bdaef38f13d6..5f3c175afdd27 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -1042,10 +1042,10 @@ int intel_audio_min_cdclk(const struct intel_crtc_state *crtc_state) static unsigned long intel_audio_component_get_power(struct device *kdev) { struct intel_display *display = to_intel_display(kdev); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; /* Catch potential impedance mismatches before they occur! */ - BUILD_BUG_ON(sizeof(intel_wakeref_t) > sizeof(unsigned long)); + BUILD_BUG_ON(sizeof(wakeref) > sizeof(unsigned long)); wakeref = intel_display_power_get(display, POWER_DOMAIN_AUDIO_PLAYBACK); @@ -1074,7 +1074,7 @@ static void intel_audio_component_put_power(struct device *kdev, unsigned long cookie) { struct intel_display *display = to_intel_display(kdev); - intel_wakeref_t wakeref = (intel_wakeref_t)cookie; + struct ref_tracker *wakeref = (struct ref_tracker *)cookie; /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ if (--display->audio.power_refcount == 0) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 4b41068e9e35f..ae0b922d5bc3d 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -34,14 +34,13 @@ #include #include -#include "soc/intel_rom.h" - #include "intel_display.h" #include "intel_display_core.h" #include "intel_display_rpm.h" #include "intel_display_types.h" #include "intel_display_utils.h" #include "intel_gmbus.h" +#include "intel_rom.h" #define _INTEL_BIOS_PRIVATE #include "intel_vbt_defs.h" @@ -2529,6 +2528,54 @@ intel_bios_encoder_reject_edp_rate(const struct intel_bios_encoder_data *devdata return devdata->child.edp_data_rate_override & edp_rate_override_mask(rate); } +static void sanitize_dedicated_external(struct intel_bios_encoder_data *devdata, + enum port port) +{ + struct intel_display *display = devdata->display; + + if (!intel_bios_encoder_is_dedicated_external(devdata)) + return; + + /* + * Since dedicated_external is for ports connected to PHYs outside of + * the Type-C subsystem, clear bits that would only make sense for ports + * with PHYs in the Type-C subsystem. + */ + + /* + * Bit dp_usb_type_c is marked as "don't care" in Bspec when + * dedicated_external is set. + */ + if (devdata->child.dp_usb_type_c) { + drm_dbg_kms(display->drm, + "VBT claims Port %c supports USB Type-C, but the port is dedicated external, ignoring\n", + port_name(port)); + devdata->child.dp_usb_type_c = 0; + } + + /* + * Bit tbt is marked as "don't care" in Bspec when dedicated_external is + * set. + */ + if (devdata->child.tbt) { + drm_dbg_kms(display->drm, + "VBT claims Port %c supports TBT, but the port is dedicated external, ignoring\n", + port_name(port)); + devdata->child.tbt = 0; + } + + /* + * DDI allocation for TC capable ports only make sense for PHYs in the + * Type-C subsystem. + */ + if (devdata->child.dyn_port_over_tc) { + drm_dbg_kms(display->drm, + "VBT claims Port %c supports dynamic DDI allocation in TCSS, but the port is dedicated external, ignoring\n", + port_name(port)); + devdata->child.dyn_port_over_tc = 0; + } +} + static void sanitize_device_type(struct intel_bios_encoder_data *devdata, enum port port) { @@ -2693,6 +2740,16 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata) supports_typec_usb, supports_tbt, devdata->dsc != NULL); + if (intel_bios_encoder_is_dedicated_external(devdata)) + drm_dbg_kms(display->drm, + "Port %c is dedicated external\n", + port_name(port)); + + if (intel_bios_encoder_supports_dyn_port_over_tc(devdata)) + drm_dbg_kms(display->drm, + "Port %c supports dynamic DDI allocation in TCSS\n", + port_name(port)); + hdmi_level_shift = intel_bios_hdmi_level_shift(devdata); if (hdmi_level_shift >= 0) { drm_dbg_kms(display->drm, @@ -2750,6 +2807,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata) return; } + sanitize_dedicated_external(devdata, port); sanitize_device_type(devdata, port); sanitize_hdmi_level_shift(devdata, port); } @@ -2777,7 +2835,7 @@ static int child_device_expected_size(u16 version) { BUILD_BUG_ON(sizeof(struct child_device_config) < 40); - if (version > 263) + if (version > 264) return -ENOENT; else if (version >= 263) return 44; @@ -3721,6 +3779,18 @@ bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devda return devdata->display->vbt.version >= 209 && devdata->child.tbt; } +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata) +{ + return devdata->display->vbt.version >= 264 && + devdata->child.dedicated_external; +} + +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata) +{ + return devdata->display->vbt.version >= 264 && + devdata->child.dyn_port_over_tc; +} + bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata) { return devdata && devdata->child.lane_reversal; diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index f9e438b2787bd..75dff27b42289 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata); bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata); bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata); +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata); +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata); bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata); bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata); bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata); diff --git a/drivers/gpu/drm/i915/display/intel_bo.c b/drivers/gpu/drm/i915/display/intel_bo.c index f3687eb634671..8f372b33d48bf 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.c +++ b/drivers/gpu/drm/i915/display/intel_bo.c @@ -6,6 +6,7 @@ #include "gem/i915_gem_mman.h" #include "gem/i915_gem_object.h" #include "gem/i915_gem_object_frontbuffer.h" +#include "pxp/intel_pxp.h" #include "i915_debugfs.h" #include "intel_bo.h" @@ -29,6 +30,11 @@ bool intel_bo_is_protected(struct drm_gem_object *obj) return i915_gem_object_is_protected(to_intel_bo(obj)); } +int intel_bo_key_check(struct drm_gem_object *obj) +{ + return intel_pxp_key_check(obj, false); +} + int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { return i915_gem_fb_mmap(to_intel_bo(obj), vma); diff --git a/drivers/gpu/drm/i915/display/intel_bo.h b/drivers/gpu/drm/i915/display/intel_bo.h index fc05f680dc76b..516a3836a6bc0 100644 --- a/drivers/gpu/drm/i915/display/intel_bo.h +++ b/drivers/gpu/drm/i915/display/intel_bo.h @@ -16,6 +16,7 @@ bool intel_bo_is_tiled(struct drm_gem_object *obj); bool intel_bo_is_userptr(struct drm_gem_object *obj); bool intel_bo_is_shmem(struct drm_gem_object *obj); bool intel_bo_is_protected(struct drm_gem_object *obj); +int intel_bo_key_check(struct drm_gem_object *obj); int intel_bo_fb_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); int intel_bo_read_from_page(struct drm_gem_object *obj, u64 offset, void *dst, int size); diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 1f6461be50efb..4ee3f5172f4e0 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -6,9 +6,6 @@ #include #include -#include "soc/intel_dram.h" - -#include "i915_drv.h" #include "i915_reg.h" #include "intel_bw.h" #include "intel_crtc.h" @@ -16,6 +13,7 @@ #include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_display_utils.h" +#include "intel_dram.h" #include "intel_mchbar_regs.h" #include "intel_pcode.h" #include "intel_uncore.h" @@ -76,11 +74,11 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, struct intel_qgv_point *sp, int point) { - struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 dclk_ratio, dclk_reference; u32 val; - val = intel_uncore_read(&i915->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); + val = intel_uncore_read(uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val); if (val & DG1_QCLK_REFERENCE) dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */ @@ -88,18 +86,18 @@ static int dg1_mchbar_read_qgv_point_info(struct intel_display *display, dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */ sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); - val = intel_uncore_read(&i915->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); + val = intel_uncore_read(uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); if (val & DG1_GEAR_TYPE) sp->dclk *= 2; if (sp->dclk == 0) return -EINVAL; - val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); + val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); - val = intel_uncore_read(&i915->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); + val = intel_uncore_read(uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); @@ -213,14 +211,12 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display, static int mtl_read_qgv_point_info(struct intel_display *display, struct intel_qgv_point *sp, int point) { - struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val, val2; u16 dclk; - val = intel_uncore_read(&i915->uncore, - MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); - val2 = intel_uncore_read(&i915->uncore, - MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); + val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); + val2 = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); @@ -800,7 +796,7 @@ static unsigned int icl_qgv_bw(struct intel_display *display, void intel_bw_init_hw(struct intel_display *display) { - const struct dram_info *dram_info = intel_dram_info(display->drm); + const struct dram_info *dram_info = intel_dram_info(display); if (!HAS_DISPLAY(display)) return; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 37801c744b053..9bfbfbf34dc0c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -28,10 +28,7 @@ #include #include -#include "soc/intel_dram.h" - #include "hsw_ips.h" -#include "i915_drv.h" #include "i915_reg.h" #include "intel_atomic.h" #include "intel_audio.h" @@ -42,11 +39,14 @@ #include "intel_display_regs.h" #include "intel_display_types.h" #include "intel_display_utils.h" +#include "intel_display_wa.h" +#include "intel_dram.h" #include "intel_mchbar_regs.h" #include "intel_pci_config.h" #include "intel_pcode.h" #include "intel_plane.h" #include "intel_psr.h" +#include "intel_step.h" #include "intel_vdsc.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" @@ -668,7 +668,7 @@ static void vlv_set_cdclk(struct intel_display *display, { int cdclk = cdclk_config->cdclk; u32 val, cmd = cdclk_config->voltage_level; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int ret; switch (cdclk) { @@ -758,7 +758,7 @@ static void chv_set_cdclk(struct intel_display *display, { int cdclk = cdclk_config->cdclk; u32 val, cmd = cdclk_config->voltage_level; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int ret; switch (cdclk) { @@ -1859,6 +1859,20 @@ static void bxt_de_pll_enable(struct intel_display *display, int vco) static void icl_cdclk_pll_disable(struct intel_display *display) { + /* + * Wa_13012396614: + * Fixes: A sporadic race condition between MDCLK selection and PLL + * enabling. + * Workaround: + * Change programming of MDCLK source selection in CDCLK_CTL: + * - When disabling the CDCLK PLL, first set MDCLK source to be CD2XCLK. + * - When enabling the CDCLK PLL, update MDCLK source selection only + * after the PLL is enabled (which is already done as part of the + * normal flow of _bxt_set_cdclk()). + */ + if (intel_display_wa(display, 13012396614)) + intel_de_rmw(display, CDCLK_CTL, MDCLK_SOURCE_SEL_MASK, MDCLK_SOURCE_SEL_CD2XCLK); + intel_de_rmw(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE, 0); @@ -1934,6 +1948,8 @@ static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, int cdclk, int vco, u16 waveform) { + u32 ret; + /* cdclk = vco / 2 / div{1,1.5,2,4} */ switch (cdclk_divider(cdclk, vco, waveform)) { default: @@ -1942,14 +1958,27 @@ static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, drm_WARN_ON(display->drm, vco != 0); fallthrough; case 2: - return BXT_CDCLK_CD2X_DIV_SEL_1; + ret = BXT_CDCLK_CD2X_DIV_SEL_1; + break; case 3: - return BXT_CDCLK_CD2X_DIV_SEL_1_5; + ret = BXT_CDCLK_CD2X_DIV_SEL_1_5; + break; case 4: - return BXT_CDCLK_CD2X_DIV_SEL_2; + ret = BXT_CDCLK_CD2X_DIV_SEL_2; + break; case 8: - return BXT_CDCLK_CD2X_DIV_SEL_4; + ret = BXT_CDCLK_CD2X_DIV_SEL_4; + break; } + + /* + * On Xe3_LPD onward, the expectation is to always have + * BXT_CDCLK_CD2X_DIV_SEL_1 as the default. + */ + if (DISPLAY_VER(display) >= 30) + drm_WARN_ON(display->drm, ret != BXT_CDCLK_CD2X_DIV_SEL_1); + + return ret; } static u16 cdclk_squash_waveform(struct intel_display *display, @@ -2137,8 +2166,10 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, waveform = cdclk_squash_waveform(display, cdclk); - val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | - bxt_cdclk_cd2x_pipe(display, pipe); + val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform); + + if (DISPLAY_VER(display) < 30) + val |= bxt_cdclk_cd2x_pipe(display, pipe); /* * Disable SSA Precharge when CD clock frequency < 500 MHz, @@ -2148,10 +2179,20 @@ static u32 bxt_cdclk_ctl(struct intel_display *display, cdclk >= 500000) val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; - if (DISPLAY_VER(display) >= 20) - val |= xe2lpd_mdclk_source_sel(display); - else + if (DISPLAY_VER(display) >= 20) { + /* + * Wa_13012396614 requires selecting CD2XCLK as MDCLK source + * prior to disabling the PLL, which is already handled by + * icl_cdclk_pll_disable(). Here we are just making sure + * we keep the expected value. + */ + if (intel_display_wa(display, 13012396614) && vco == 0) + val |= MDCLK_SOURCE_SEL_CD2XCLK; + else + val |= xe2lpd_mdclk_source_sel(display); + } else { val |= skl_cdclk_decimal(cdclk); + } return val; } @@ -3738,10 +3779,8 @@ static int pch_rawclk(struct intel_display *display) static int i9xx_hrawclk(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - /* hrawclock is 1/4 the FSB frequency */ - return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4); + return DIV_ROUND_CLOSEST(intel_fsb_freq(display), 4); } /** diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c index 165138b95cb2f..e1fdc6fe9762a 100644 --- a/drivers/gpu/drm/i915/display/intel_cmtg.c +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c @@ -85,7 +85,6 @@ static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display, enum transcoder trans) { enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; u32 val = 0; if (!HAS_TRANSCODER(display, trans)) @@ -93,7 +92,7 @@ static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display, power_domain = POWER_DOMAIN_TRANSCODER(trans); - with_intel_display_power_if_enabled(display, power_domain, wakeref) + with_intel_display_power_if_enabled(display, power_domain) val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); return val & CMTG_SECONDARY_MODE; diff --git a/drivers/gpu/drm/i915/display/intel_colorop.c b/drivers/gpu/drm/i915/display/intel_colorop.c index f2fc0d8780cee..1d84933f05aa9 100644 --- a/drivers/gpu/drm/i915/display/intel_colorop.c +++ b/drivers/gpu/drm/i915/display/intel_colorop.c @@ -2,7 +2,9 @@ /* * Copyright © 2025 Intel Corporation */ + #include "intel_colorop.h" +#include "intel_display_types.h" struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop) { diff --git a/drivers/gpu/drm/i915/display/intel_colorop.h b/drivers/gpu/drm/i915/display/intel_colorop.h index 21d58eb9f3d0f..9276eee6e75a3 100644 --- a/drivers/gpu/drm/i915/display/intel_colorop.h +++ b/drivers/gpu/drm/i915/display/intel_colorop.h @@ -6,7 +6,9 @@ #ifndef __INTEL_COLOROP_H__ #define __INTEL_COLOROP_H__ -#include "intel_display_types.h" +enum intel_color_block; +struct drm_colorop; +struct intel_colorop; struct intel_colorop *to_intel_colorop(struct drm_colorop *colorop); struct intel_colorop *intel_colorop_alloc(void); diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c index 913d90a7a5083..682bf1be350da 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c @@ -31,8 +31,6 @@ #include #include -#include "i915_drv.h" -#include "i915_utils.h" /* for i915_inject_probe_failure() */ #include "intel_connector.h" #include "intel_display_core.h" #include "intel_display_debugfs.h" @@ -156,27 +154,17 @@ void intel_connector_destroy(struct drm_connector *connector) int intel_connector_register(struct drm_connector *_connector) { struct intel_connector *connector = to_intel_connector(_connector); - struct drm_i915_private *i915 = to_i915(_connector->dev); int ret; ret = intel_panel_register(connector); if (ret) - goto err; - - if (i915_inject_probe_failure(i915)) { - ret = -EFAULT; - goto err_panel; - } + return ret; intel_connector_debugfs_add(connector); return 0; - -err_panel: - intel_panel_unregister(connector); -err: - return ret; } +ALLOW_ERROR_INJECTION(intel_connector_register, ERRNO); void intel_connector_unregister(struct drm_connector *_connector) { diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 82e89cdbe5a56..5f9a03877ea90 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -109,7 +109,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_crt *crt = intel_encoder_to_crt(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; wakeref = intel_display_power_get_if_enabled(display, @@ -847,7 +847,7 @@ intel_crt_detect(struct drm_connector *connector, struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); struct intel_encoder *encoder = &crt->base; struct drm_atomic_state *state; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int status; drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", @@ -936,7 +936,7 @@ static int intel_crt_get_modes(struct drm_connector *connector) struct intel_display *display = to_intel_display(connector->dev); struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); struct intel_encoder *encoder = &crt->base; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; struct i2c_adapter *ddc; int ret; diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 9d2a23c96c61b..778ebc5095c38 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -13,8 +13,6 @@ #include #include -#include "i915_drv.h" -#include "i915_vgpu.h" #include "i9xx_plane.h" #include "icl_dsi.h" #include "intel_atomic.h" @@ -28,6 +26,7 @@ #include "intel_drrs.h" #include "intel_dsi.h" #include "intel_fifo_underrun.h" +#include "intel_parent.h" #include "intel_pipe_crc.h" #include "intel_plane.h" #include "intel_psr.h" @@ -309,7 +308,7 @@ static const struct drm_crtc_funcs i8xx_crtc_funcs = { .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; -int intel_crtc_init(struct intel_display *display, enum pipe pipe) +static int __intel_crtc_init(struct intel_display *display, enum pipe pipe) { struct intel_plane *primary, *cursor; const struct drm_crtc_funcs *funcs; @@ -396,7 +395,7 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) drm_WARN_ON(display->drm, drm_crtc_index(&crtc->base) != crtc->pipe); - if (HAS_CASF(display)) + if (HAS_CASF(display) && crtc->num_scalers >= 2) drm_crtc_create_sharpness_strength_property(&crtc->base); return 0; @@ -407,6 +406,23 @@ int intel_crtc_init(struct intel_display *display, enum pipe pipe) return ret; } +int intel_crtc_init(struct intel_display *display) +{ + enum pipe pipe; + int ret; + + drm_dbg_kms(display->drm, "%d display pipe%s available.\n", + INTEL_NUM_PIPES(display), str_plural(INTEL_NUM_PIPES(display))); + + for_each_pipe(display, pipe) { + ret = __intel_crtc_init(display, pipe); + if (ret) + return ret; + } + + return 0; +} + int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { @@ -553,7 +569,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state, for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { - if (old_plane_state->uapi.crtc == &crtc->base) + if (old_plane_state->hw.crtc == &crtc->base) intel_plane_init_cursor_vblank_work(old_plane_state, new_plane_state); } @@ -671,7 +687,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state, int scanline_end = intel_get_crtc_scanline(crtc); u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); ktime_t end_vbl_time = ktime_get(); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); drm_WARN_ON(display->drm, new_crtc_state->use_dsb); @@ -706,7 +721,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state, int i; for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { - if (old_plane_state->uapi.crtc == &crtc->base && + if (old_plane_state->hw.crtc == &crtc->base && old_plane_state->unpin_work.vblank) { drm_vblank_work_schedule(&old_plane_state->unpin_work, drm_crtc_accurate_vblank_count(&crtc->base) + 1, @@ -737,7 +752,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state, local_irq_enable(); - if (intel_vgpu_active(dev_priv)) + if (intel_parent_vgpu_active(display)) goto out; if (crtc->debug.start_vbl_count && diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h index 07917e8a9ae33..12507b51ee77e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.h +++ b/drivers/gpu/drm/i915/display/intel_crtc.h @@ -37,7 +37,7 @@ void intel_crtc_arm_vblank_event(struct intel_crtc_state *crtc_state); void intel_crtc_prepare_vblank_event(struct intel_crtc_state *crtc_state, struct drm_pending_vblank_event **event); u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state); -int intel_crtc_init(struct intel_display *display, enum pipe pipe); +int intel_crtc_init(struct intel_display *display); int intel_crtc_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index c2a6217c22622..234843b8f83a4 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -303,6 +303,14 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n", intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config), intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config)); + drm_printf(&p, "vrr: dc balance: %s, vmin: %d vmax: %d guardband: %d, slope: %d max increase: %d max decrease: %d vblank target: %d\n", + str_yes_no(pipe_config->vrr.dc_balance.enable), + pipe_config->vrr.dc_balance.vmin, pipe_config->vrr.dc_balance.vmax, + pipe_config->vrr.dc_balance.guardband, + pipe_config->vrr.dc_balance.slope, + pipe_config->vrr.dc_balance.max_increase, + pipe_config->vrr.dc_balance.max_decrease, + pipe_config->vrr.dc_balance.vblank_target); drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(&pipe_config->hw.mode)); diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index a10b2425b94d2..2c5d917fbd7e9 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -324,7 +324,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(PIPE_A); @@ -727,7 +727,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; u32 val; @@ -974,6 +974,7 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = intel_cursor_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static void intel_cursor_add_size_hints_property(struct intel_plane *plane) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index d98b4cf6b60e0..7288065d24619 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -11,6 +11,7 @@ #include "intel_alpm.h" #include "intel_cx0_phy.h" #include "intel_cx0_phy_regs.h" +#include "intel_display_regs.h" #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" @@ -104,11 +105,11 @@ static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder) * We also do the msgbus timer programming here to ensure that the timer * is already programmed before any access to the msgbus. */ -static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) +static struct ref_tracker *intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; intel_psr_pause(intel_dp); wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); @@ -117,7 +118,7 @@ static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *enc return wakeref; } -static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) +static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, struct ref_tracker *wakeref) { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -444,13 +445,38 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state) } } +static void intel_c10_msgbus_access_begin(struct intel_encoder *encoder, + u8 lane_mask) +{ + if (!intel_encoder_is_c10phy(encoder)) + return; + + intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1), + 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); +} + +static void intel_c10_msgbus_access_commit(struct intel_encoder *encoder, + u8 lane_mask, bool master_lane) +{ + u8 val = C10_VDR_CTRL_UPDATE_CFG; + + if (!intel_encoder_is_c10phy(encoder)) + return; + + if (master_lane) + val |= C10_VDR_CTRL_MASTER_LANE; + + intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1), + 0, val, MB_WRITE_COMMITTED); +} + void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; u8 owned_lane_mask; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int n_entries, ln; struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -467,9 +493,9 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, return; } + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); + if (intel_encoder_is_c10phy(encoder)) { - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), - 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), C10_CMN3_TXVBOOST_MASK, C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), @@ -508,9 +534,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, MB_WRITE_COMMITTED); - if (intel_encoder_is_c10phy(encoder)) - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), - 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); + intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false); intel_cx0_phy_transaction_end(encoder, wakeref); } @@ -2005,7 +2029,7 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = { }; static const struct intel_c10pll_state * const * -intel_c10pll_tables_get(struct intel_crtc_state *crtc_state, +intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { if (intel_crtc_has_dp_encoder(crtc_state)) { @@ -2035,6 +2059,15 @@ static void intel_cx0pll_update_ssc(struct intel_encoder *encoder, } } +#define C10_PLL_SSC_REG_START_IDX 4 +#define C10_PLL_SSC_REG_COUNT 5 + +static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state *pll_state) +{ + return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX], + 0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT); +} + static void intel_c10pll_update_pll(struct intel_encoder *encoder, struct intel_cx0pll_state *pll_state) { @@ -2044,16 +2077,42 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder, if (pll_state->ssc_enabled) return; - drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); - for (i = 4; i < 9; i++) + drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < + C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT); + for (i = C10_PLL_SSC_REG_START_IDX; + i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT; + i++) pll_state->c10.pll[i] = 0; } +static bool c10pll_state_is_dp(const struct intel_c10pll_state *pll_state) +{ + return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); +} + +static bool c20pll_state_is_dp(const struct intel_c20pll_state *pll_state) +{ + return pll_state->vdr.serdes_rate & PHY_C20_IS_DP; +} + +static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state) +{ + if (pll_state->use_c10) + return c10pll_state_is_dp(&pll_state->c10); + + return c20pll_state_is_dp(&pll_state->c20); +} + +/* + * TODO: Convert the following to align with intel_c20pll_find_table() and + * intel_c20pll_calc_state_from_table(). + */ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder, const struct intel_c10pll_state * const *tables, - bool is_dp, int port_clock, + bool is_dp, int port_clock, int lane_count, struct intel_cx0pll_state *pll_state) { + struct intel_display *display = to_intel_display(encoder); int i; for (i = 0; tables[i]; i++) { @@ -2061,7 +2120,11 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder, pll_state->c10 = *tables[i]; intel_cx0pll_update_ssc(encoder, pll_state, is_dp); intel_c10pll_update_pll(encoder, pll_state); + pll_state->use_c10 = true; + pll_state->lane_count = lane_count; + + drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10)); return 0; } @@ -2070,9 +2133,12 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder, return -EINVAL; } -static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder) +static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder, + struct intel_dpll_hw_state *hw_state) { + struct intel_display *display = to_intel_display(encoder); + bool is_dp = intel_crtc_has_dp_encoder(crtc_state); const struct intel_c10pll_state * const *tables; int err; @@ -2080,43 +2146,126 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, if (!tables) return -EINVAL; - err = intel_c10pll_calc_state_from_table(encoder, tables, - intel_crtc_has_dp_encoder(crtc_state), - crtc_state->port_clock, - &crtc_state->dpll_hw_state.cx0pll); + err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp, + crtc_state->port_clock, crtc_state->lane_count, + &hw_state->cx0pll); if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return err; /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */ - intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10, + intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10, crtc_state->port_clock); - intel_c10pll_update_pll(encoder, - &crtc_state->dpll_hw_state.cx0pll); - crtc_state->dpll_hw_state.cx0pll.use_c10 = true; + intel_c10pll_update_pll(encoder, &hw_state->cx0pll); + + hw_state->cx0pll.use_c10 = true; + hw_state->cx0pll.lane_count = crtc_state->lane_count; + + drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&hw_state->cx0pll.c10)); return 0; } static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, - const struct intel_c10pll_state *pll_state); + const struct intel_c10pll_state *pll_state) +{ + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; + unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; + int tmpclk = 0; + + if (pll_state->pll[0] & C10_PLL0_FRACEN) { + frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; + frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; + frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; + } + + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | + pll_state->pll[2]) / 2 + 16; + + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); + hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); + + tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + + DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), + 10 << (tx_clk_div + 16)); + tmpclk *= (hdmi_div ? 2 : 1); + + return tmpclk; +} + +static int readout_enabled_lane_count(struct intel_encoder *encoder) +{ + struct intel_display *display = to_intel_display(encoder); + u8 enabled_tx_lane_count = 0; + int max_tx_lane_count = 4; + bool lane_reversal; + int tx_lane; + + lane_reversal = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, encoder->port)) & + XELPDP_PORT_REVERSAL; + + /* + * TODO: also check inactive TX lanes in all PHY lanes owned by the + * display. For now checking only those PHY lane(s) which are owned + * based on the active TX lane count (i.e. + * 1,2 active TX lanes -> PHY lane#0 + * 3,4 active TX lanes -> PHY lane#0 and PHY lane#1). + * + * In case of lane reversal for 1, 2 active TX lanes, only PHY + * lane#1 is used. This is only possible in TypeC legacy mode or if + * the port is connected to a non-TC PHY. In both of these cases both + * PHY lane#0 and #1 are owned by display, so check all 4 TX lanes in + * both PHY lanes in those cases. + */ + if (!lane_reversal) + max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, + DDI_BUF_CTL(encoder->port))); + + if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0)) + max_tx_lane_count = round_up(max_tx_lane_count, 2); + + for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) { + u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; + int tx = tx_lane % 2 + 1; + u8 val; + + val = intel_cx0_read(encoder, phy_lane_mask, PHY_CX0_TX_CONTROL(tx, 2)); + if (!(val & CONTROL2_DISABLE_SINGLE_TX)) + enabled_tx_lane_count++; + } + + return enabled_tx_lane_count; +} + +static bool readout_ssc_state(struct intel_encoder *encoder, bool is_mpll_b) +{ + struct intel_display *display = to_intel_display(encoder); + + return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) & + (is_mpll_b ? XELPDP_SSC_ENABLE_PLLB : XELPDP_SSC_ENABLE_PLLA); +} static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, - struct intel_c10pll_state *pll_state) + struct intel_cx0pll_state *cx0pll_state) { + struct intel_c10pll_state *pll_state = &cx0pll_state->c10; + struct intel_display *display = to_intel_display(encoder); + enum phy phy = intel_encoder_to_phy(encoder); u8 lane = INTEL_CX0_LANE0; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int i; + cx0pll_state->use_c10 = true; + wakeref = intel_cx0_phy_transaction_begin(encoder); /* * According to C10 VDR Register programming Sequence we need * to do this to read PHY internal registers from MsgBus. */ - intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1), - 0, C10_VDR_CTRL_MSGBUS_ACCESS, - MB_WRITE_COMMITTED); + intel_c10_msgbus_access_begin(encoder, lane); + + cx0pll_state->lane_count = readout_enabled_lane_count(encoder); for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); @@ -2127,6 +2276,15 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, intel_cx0_phy_transaction_end(encoder, wakeref); pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state); + + cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true); + + if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state)) + drm_dbg_kms(display->drm, + "PHY %c: SSC state mismatch: port SSC is %s, PLL SSC is %s\n", + phy_name(phy), + str_enabled_disabled(cx0pll_state->ssc_enabled), + str_enabled_disabled(intel_c10pll_ssc_enabled(pll_state))); } static void intel_c10_pll_program(struct intel_display *display, @@ -2135,9 +2293,7 @@ static void intel_c10_pll_program(struct intel_display *display, { int i; - intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), - 0, C10_VDR_CTRL_MSGBUS_ACCESS, - MB_WRITE_COMMITTED); + intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES); /* Program the pll values only for the master lane */ for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) @@ -2152,12 +2308,11 @@ static void intel_c10_pll_program(struct intel_display *display, intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10, MB_WRITE_COMMITTED); - intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), - 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, - MB_WRITE_COMMITTED); + + intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true); } -static void intel_c10pll_dump_hw_state(struct intel_display *display, +static void intel_c10pll_dump_hw_state(struct drm_printer *p, const struct intel_c10pll_state *hw_state) { bool fracen; @@ -2166,33 +2321,32 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display, unsigned int multiplier, tx_clk_div; fracen = hw_state->pll[0] & C10_PLL0_FRACEN; - drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ", - str_yes_no(fracen)); + drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ", + hw_state->clock, str_yes_no(fracen)); if (fracen) { frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; - drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n", - frac_quot, frac_rem, frac_den); + drm_printf(p, "quot: %u, rem: %u, den: %u,\n", + frac_quot, frac_rem, frac_den); } multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | hw_state->pll[2]) / 2 + 16; tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); - drm_dbg_kms(display->drm, - "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); + drm_printf(p, + "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div); - drm_dbg_kms(display->drm, "c10pll_rawhw_state:"); - drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, - hw_state->cmn); + drm_printf(p, "c10pll_rawhw_state:"); + drm_printf(p, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) - drm_dbg_kms(display->drm, - "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", - i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], - i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); + drm_printf(p, + "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", + i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], + i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); } /* @@ -2210,7 +2364,7 @@ static bool is_arrowlake_s_by_host_bridge(void) return pdev && IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id); } -static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state) +static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); u16 tx_misc; @@ -2234,9 +2388,9 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state) C20_PHY_TX_DCC_BYPASS | C20_PHY_TX_TERM_CTL(tx_term_ctrl)); } -static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) +static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_state, + struct intel_c20pll_state *pll_state) { - struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; u64 datarate; u64 mpll_tx_clk_div; u64 vco_freq_shift; @@ -2304,7 +2458,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state) } static const struct intel_c20pll_state * const * -intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, +intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(crtc_state); @@ -2332,42 +2486,223 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, return NULL; } -static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder) +static u8 intel_c20_get_dp_rate(u32 clock) { - const struct intel_c20pll_state * const *tables; - int i; + switch (clock) { + case 162000: /* 1.62 Gbps DP1.4 */ + return 0; + case 270000: /* 2.7 Gbps DP1.4 */ + return 1; + case 540000: /* 5.4 Gbps DP 1.4 */ + return 2; + case 810000: /* 8.1 Gbps DP1.4 */ + return 3; + case 216000: /* 2.16 Gbps eDP */ + return 4; + case 243000: /* 2.43 Gbps eDP */ + return 5; + case 324000: /* 3.24 Gbps eDP */ + return 6; + case 432000: /* 4.32 Gbps eDP */ + return 7; + case 1000000: /* 10 Gbps DP2.0 */ + return 8; + case 1350000: /* 13.5 Gbps DP2.0 */ + return 9; + case 2000000: /* 20 Gbps DP2.0 */ + return 10; + case 648000: /* 6.48 Gbps eDP*/ + return 11; + case 675000: /* 6.75 Gbps eDP*/ + return 12; + default: + MISSING_CASE(clock); + return 0; + } +} - /* try computed C20 HDMI tables before using consolidated tables */ - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { - if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) - return 0; +static u8 intel_c20_get_hdmi_rate(u32 clock) +{ + if (clock >= 25175 && clock <= 600000) + return 0; + + switch (clock) { + case 300000: /* 3 Gbps */ + case 600000: /* 6 Gbps */ + case 1200000: /* 12 Gbps */ + return 1; + case 800000: /* 8 Gbps */ + return 2; + case 1000000: /* 10 Gbps */ + return 3; + default: + MISSING_CASE(clock); + return 0; + } +} + +static bool is_dp2(u32 clock) +{ + /* DP2.0 clock rates */ + if (clock == 1000000 || clock == 1350000 || clock == 2000000) + return true; + + return false; +} + +static int intel_get_c20_custom_width(u32 clock, bool dp) +{ + if (dp && is_dp2(clock)) + return 2; + else if (intel_hdmi_is_frl(clock)) + return 1; + else + return 0; +} + +static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool is_dp, + int port_clock) +{ + vdr->custom_width = intel_get_c20_custom_width(port_clock, is_dp); + + vdr->serdes_rate = 0; + vdr->hdmi_rate = 0; + + if (is_dp) { + vdr->serdes_rate = PHY_C20_IS_DP | + PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)); + } else { + if (intel_hdmi_is_frl(port_clock)) + vdr->serdes_rate = PHY_C20_IS_HDMI_FRL; + + vdr->hdmi_rate = intel_c20_get_hdmi_rate(port_clock); } +} + +#define PHY_C20_SERDES_RATE_MASK (PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL) + +static void intel_c20_readout_vdr_params(struct intel_encoder *encoder, + struct intel_c20pll_vdr_state *vdr, bool *cntx) +{ + u8 serdes; + + serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE); + *cntx = serdes & PHY_C20_CONTEXT_TOGGLE; + + vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) & + PHY_C20_CUSTOM_WIDTH_MASK; + + vdr->serdes_rate = serdes & PHY_C20_SERDES_RATE_MASK; + if (!(vdr->serdes_rate & PHY_C20_IS_DP)) + vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) & + PHY_C20_HDMI_RATE_MASK; + else + vdr->hdmi_rate = 0; +} + +static void intel_c20_program_vdr_params(struct intel_encoder *encoder, + const struct intel_c20pll_vdr_state *vdr, + u8 owned_lane_mask) +{ + struct intel_display *display = to_intel_display(encoder); + + drm_WARN_ON(display->drm, vdr->custom_width & ~PHY_C20_CUSTOM_WIDTH_MASK); + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, + PHY_C20_CUSTOM_WIDTH_MASK, vdr->custom_width, + MB_WRITE_COMMITTED); + + drm_WARN_ON(display->drm, vdr->serdes_rate & ~PHY_C20_SERDES_RATE_MASK); + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, + PHY_C20_SERDES_RATE_MASK, vdr->serdes_rate, + MB_WRITE_COMMITTED); + + if (vdr->serdes_rate & PHY_C20_IS_DP) + return; + + drm_WARN_ON(display->drm, vdr->hdmi_rate & ~PHY_C20_HDMI_RATE_MASK); + intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, + PHY_C20_HDMI_RATE_MASK, vdr->hdmi_rate, + MB_WRITE_COMMITTED); +} + +static const struct intel_c20pll_state * +intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder) +{ + const struct intel_c20pll_state * const *tables; + int i; tables = intel_c20_pll_tables_get(crtc_state, encoder); if (!tables) + return NULL; + + for (i = 0; tables[i]; i++) + if (crtc_state->port_clock == tables[i]->clock) + return tables[i]; + + return NULL; +} + +static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder, + struct intel_cx0pll_state *pll_state) +{ + const struct intel_c20pll_state *table; + + table = intel_c20_pll_find_table(crtc_state, encoder); + if (!table) return -EINVAL; - for (i = 0; tables[i]; i++) { - if (crtc_state->port_clock == tables[i]->clock) { - crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; - intel_cx0pll_update_ssc(encoder, - &crtc_state->dpll_hw_state.cx0pll, - intel_crtc_has_dp_encoder(crtc_state)); - crtc_state->dpll_hw_state.cx0pll.use_c10 = false; - return 0; - } - } + pll_state->c20 = *table; - return -EINVAL; + intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state)); + + return 0; } -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, - struct intel_encoder *encoder) +static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder, + struct intel_dpll_hw_state *hw_state) { + struct intel_display *display = to_intel_display(encoder); + bool is_dp = intel_crtc_has_dp_encoder(crtc_state); + int err = -ENOENT; + + hw_state->cx0pll.use_c10 = false; + hw_state->cx0pll.lane_count = crtc_state->lane_count; + + /* + * Try the ideal C20 HDMI tables before computing them, since the calculated + * values, although correct, may not be optimal. + */ + if (err) + err = intel_c20pll_calc_state_from_table(crtc_state, encoder, + &hw_state->cx0pll); + + /* TODO: Update SSC state for HDMI as well */ + if (!is_dp && err) + err = intel_c20_compute_hdmi_tmds_pll(crtc_state, &hw_state->cx0pll.c20); + + if (err) + return err; + + intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr, + is_dp, crtc_state->port_clock); + + drm_WARN_ON(display->drm, is_dp != c20pll_state_is_dp(&hw_state->cx0pll.c20)); + + return 0; +} + +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder, + struct intel_dpll_hw_state *hw_state) +{ + memset(hw_state, 0, sizeof(*hw_state)); + if (intel_encoder_is_c10phy(encoder)) - return intel_c10pll_calc_state(crtc_state, encoder); - return intel_c20pll_calc_state(crtc_state, encoder); + return intel_c10pll_calc_state(crtc_state, encoder, hw_state); + return intel_c20pll_calc_state(crtc_state, encoder, hw_state); } static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) @@ -2421,17 +2756,22 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, } static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, - struct intel_c20pll_state *pll_state) + struct intel_cx0pll_state *cx0pll_state) { + struct intel_c20pll_state *pll_state = &cx0pll_state->c20; struct intel_display *display = to_intel_display(encoder); bool cntx; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int i; + cx0pll_state->use_c10 = false; + wakeref = intel_cx0_phy_transaction_begin(encoder); - /* 1. Read current context selection */ - cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE; + cx0pll_state->lane_count = readout_enabled_lane_count(encoder); + + /* 1. Read VDR params and current context selection */ + intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx); /* Read Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { @@ -2486,103 +2826,52 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); intel_cx0_phy_transaction_end(encoder, wakeref); + + cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state)); } -static void intel_c20pll_dump_hw_state(struct intel_display *display, +static void intel_c20pll_dump_hw_state(struct drm_printer *p, const struct intel_c20pll_state *hw_state) { int i; - drm_dbg_kms(display->drm, "c20pll_hw_state:\n"); - drm_dbg_kms(display->drm, - "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", - hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); - drm_dbg_kms(display->drm, - "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", - hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); + drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock); + drm_printf(p, + "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); + drm_printf(p, + "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); if (intel_c20phy_use_mpllb(hw_state)) { for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) - drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, - hw_state->mpllb[i]); + drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); } else { for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) - drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i, - hw_state->mplla[i]); - } -} - -void intel_cx0pll_dump_hw_state(struct intel_display *display, - const struct intel_cx0pll_state *hw_state) -{ - if (hw_state->use_c10) - intel_c10pll_dump_hw_state(display, &hw_state->c10); - else - intel_c20pll_dump_hw_state(display, &hw_state->c20); -} + drm_printf(p, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); -static u8 intel_c20_get_dp_rate(u32 clock) -{ - switch (clock) { - case 162000: /* 1.62 Gbps DP1.4 */ - return 0; - case 270000: /* 2.7 Gbps DP1.4 */ - return 1; - case 540000: /* 5.4 Gbps DP 1.4 */ - return 2; - case 810000: /* 8.1 Gbps DP1.4 */ - return 3; - case 216000: /* 2.16 Gbps eDP */ - return 4; - case 243000: /* 2.43 Gbps eDP */ - return 5; - case 324000: /* 3.24 Gbps eDP */ - return 6; - case 432000: /* 4.32 Gbps eDP */ - return 7; - case 1000000: /* 10 Gbps DP2.0 */ - return 8; - case 1350000: /* 13.5 Gbps DP2.0 */ - return 9; - case 2000000: /* 20 Gbps DP2.0 */ - return 10; - case 648000: /* 6.48 Gbps eDP*/ - return 11; - case 675000: /* 6.75 Gbps eDP*/ - return 12; - default: - MISSING_CASE(clock); - return 0; + /* For full coverage, also print the additional PLL B entry. */ + BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb)); + drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); } -} -static u8 intel_c20_get_hdmi_rate(u32 clock) -{ - if (clock >= 25175 && clock <= 600000) - return 0; - - switch (clock) { - case 300000: /* 3 Gbps */ - case 600000: /* 6 Gbps */ - case 1200000: /* 12 Gbps */ - return 1; - case 800000: /* 8 Gbps */ - return 2; - case 1000000: /* 10 Gbps */ - return 3; - default: - MISSING_CASE(clock); - return 0; - } + drm_printf(p, + "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n", + hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate); } -static bool is_dp2(u32 clock) +void intel_cx0pll_dump_hw_state(struct drm_printer *p, + const struct intel_cx0pll_state *hw_state) { - /* DP2.0 clock rates */ - if (clock == 1000000 || clock == 1350000 || clock == 2000000) - return true; + drm_printf(p, + "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n", + hw_state->lane_count, str_yes_no(hw_state->ssc_enabled), + str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode)); - return false; + if (hw_state->use_c10) + intel_c10pll_dump_hw_state(p, &hw_state->c10); + else + intel_c20pll_dump_hw_state(p, &hw_state->c20); } static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) @@ -2594,23 +2883,11 @@ static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) return intel_tc_port_in_legacy_mode(intel_dig_port); } -static int intel_get_c20_custom_width(u32 clock, bool dp) -{ - if (dp && is_dp2(clock)) - return 2; - else if (intel_hdmi_is_frl(clock)) - return 1; - else - return 0; -} - static void intel_c20_pll_program(struct intel_display *display, struct intel_encoder *encoder, - const struct intel_c20pll_state *pll_state, - bool is_dp, int port_clock) + const struct intel_c20pll_state *pll_state) { u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); - u8 serdes; bool cntx; int i; @@ -2679,30 +2956,11 @@ static void intel_c20_pll_program(struct intel_display *display, } } - /* 4. Program custom width to match the link protocol */ - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, - PHY_C20_CUSTOM_WIDTH_MASK, - PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)), - MB_WRITE_COMMITTED); - - /* 5. For DP or 6. For HDMI */ - serdes = 0; - if (is_dp) - serdes = PHY_C20_IS_DP | - PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock)); - else if (intel_hdmi_is_frl(port_clock)) - serdes = PHY_C20_IS_HDMI_FRL; - - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, - PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL, - serdes, - MB_WRITE_COMMITTED); - - if (!is_dp) - intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE, - PHY_C20_HDMI_RATE_MASK, - intel_c20_get_hdmi_rate(port_clock), - MB_WRITE_COMMITTED); + /* + * 4. Program custom width to match the link protocol. + * 5. For DP or 6. For HDMI + */ + intel_c20_program_vdr_params(encoder, &pll_state->vdr, owned_lane_mask); /* * 7. Write Vendor specific registers to toggle context setting to load @@ -2713,39 +2971,13 @@ static void intel_c20_pll_program(struct intel_display *display, MB_WRITE_COMMITTED); } -static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, - const struct intel_c10pll_state *pll_state) -{ - unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; - unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400; - int tmpclk = 0; - - if (pll_state->pll[0] & C10_PLL0_FRACEN) { - frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; - frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; - frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; - } - - multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | - pll_state->pll[2]) / 2 + 16; - - tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); - hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); - - tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) + - DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den), - 10 << (tx_clk_div + 16)); - tmpclk *= (hdmi_div ? 2 : 1); - - return tmpclk; -} - static void intel_program_port_clock_ctl(struct intel_encoder *encoder, const struct intel_cx0pll_state *pll_state, - bool is_dp, int port_clock, + int port_clock, bool lane_reversal) { struct intel_display *display = to_intel_display(encoder); + bool is_dp = cx0pll_state_is_dp(pll_state); u32 val = 0; intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), @@ -2830,7 +3062,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder, intel_cx0_get_powerdown_update(lane_mask), XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS)) drm_warn(display->drm, - "PHY %c failed to bring out of lane reset\n", + "PHY %c failed to change powerdown state\n", phy_name(phy)); } @@ -2938,11 +3170,7 @@ static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_c bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); - if (intel_encoder_is_c10phy(encoder)) - intel_cx0_rmw(encoder, owned_lane_mask, - PHY_C10_VDR_CONTROL(1), 0, - C10_VDR_CTRL_MSGBUS_ACCESS, - MB_WRITE_COMMITTED); + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); if (lane_reversal) disables = REG_GENMASK8(3, 0) >> lane_count; @@ -2967,11 +3195,7 @@ static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_c MB_WRITE_COMMITTED); } - if (intel_encoder_is_c10phy(encoder)) - intel_cx0_rmw(encoder, owned_lane_mask, - PHY_C10_VDR_CONTROL(1), 0, - C10_VDR_CTRL_UPDATE_CFG, - MB_WRITE_COMMITTED); + intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false); } static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) @@ -2996,23 +3220,30 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask) return val; } -static void __intel_cx0pll_enable(struct intel_encoder *encoder, - const struct intel_cx0pll_state *pll_state, - bool is_dp, int port_clock, int lane_count) +static void intel_cx0pll_enable(struct intel_encoder *encoder, + const struct intel_cx0pll_state *pll_state) { + int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock; struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool lane_reversal = dig_port->lane_reversal; u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 : INTEL_CX0_LANE0; - intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); + struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder); + + /* + * Lane reversal is never used in DP-alt mode, in that case the + * corresponding lane swapping (based on the TypeC cable flip state + * for instance) is handled automatically by the HW via a TCSS mux. + */ + drm_WARN_ON(display->drm, lane_reversal && intel_tc_port_in_dp_alt_mode(dig_port)); /* * 1. Program PORT_CLOCK_CTL REGISTER to configure * clock muxes, gating and SSC */ - intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal); + intel_program_port_clock_ctl(encoder, pll_state, port_clock, lane_reversal); /* 2. Bring PHY out of reset. */ intel_cx0_phy_lane_reset(encoder, lane_reversal); @@ -3034,13 +3265,13 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder, if (intel_encoder_is_c10phy(encoder)) intel_c10_pll_program(display, encoder, &pll_state->c10); else - intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock); + intel_c20_pll_program(display, encoder, &pll_state->c20); /* * 6. Program the enabled and disabled owned PHY lane * transmitters over message bus */ - intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal); + intel_cx0_program_phy_lane(encoder, pll_state->lane_count, lane_reversal); /* * 7. Follow the Display Voltage Frequency Switching - Sequence @@ -3074,16 +3305,40 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder, * Frequency Change. We handle this step in bxt_set_cdclk(). */ - /* TODO: enable TBT-ALT mode */ + /* + * 12. Toggle powerdown if HDMI is enabled on C10 PHY. + * + * Wa_13013502646: + * Fixes: HDMI lane to lane skew violations on C10 display PHYs. + * Workaround: Toggle powerdown value by setting first to P0 and then to P2, for both + * PHY lanes. + */ + if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) { + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, + XELPDP_P0_STATE_ACTIVE); + intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, + XELPDP_P2_STATE_READY); + } + intel_cx0_phy_transaction_end(encoder, wakeref); } -static void intel_cx0pll_enable(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state) { - __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, - intel_crtc_has_dp_encoder(crtc_state), - crtc_state->port_clock, crtc_state->lane_count); + memset(hw_state, 0, sizeof(*hw_state)); + + hw_state->cx0pll.tbt_mode = true; +} + +bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, + struct intel_dpll *pll, + struct intel_dpll_hw_state *hw_state) +{ + memset(hw_state, 0, sizeof(*hw_state)); + + hw_state->cx0pll.tbt_mode = true; + + return true; } int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) @@ -3148,8 +3403,7 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display, } } -void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) +void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -3163,7 +3417,7 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, mask = XELPDP_DDI_CLOCK_SELECT_MASK(display); val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, - intel_mtl_tbt_clock_select(display, crtc_state->port_clock)); + intel_mtl_tbt_clock_select(display, port_clock)); mask |= XELPDP_FORWARD_CLOCK_UNGATE; val |= XELPDP_FORWARD_CLOCK_UNGATE; @@ -3201,18 +3455,23 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder, * clock frequency. */ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), - crtc_state->port_clock); + port_clock); } void intel_mtl_pll_enable(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state) + struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) +{ + intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll); +} + +void intel_mtl_pll_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); if (intel_tc_port_in_tbt_alt_mode(dig_port)) - intel_mtl_tbt_pll_enable(encoder, crtc_state); - else - intel_cx0pll_enable(encoder, crtc_state); + intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); } /* @@ -3224,7 +3483,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int i; u8 owned_lane_mask; @@ -3236,9 +3495,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, wakeref = intel_cx0_phy_transaction_begin(encoder); - if (intel_encoder_is_c10phy(encoder)) - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0, - C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); for (i = 0; i < 4; i++) { int tx = i % 2 + 1; @@ -3273,7 +3530,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); - intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); + struct ref_tracker *wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Change owned PHY lane power to Disable state. */ intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, @@ -3329,7 +3586,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder) intel_cx0_get_pclk_pll_request(lane); } -void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) +void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); @@ -3368,13 +3625,16 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder) } void intel_mtl_pll_disable(struct intel_encoder *encoder) +{ + intel_cx0pll_disable(encoder); +} + +void intel_mtl_pll_disable_clock(struct intel_encoder *encoder) { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); if (intel_tc_port_in_tbt_alt_mode(dig_port)) - intel_mtl_tbt_pll_disable(encoder); - else - intel_cx0pll_disable(encoder); + intel_mtl_tbt_pll_disable_clock(encoder); } enum icl_port_dpll_id @@ -3398,50 +3658,20 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder, return ICL_PORT_DPLL_DEFAULT; } -static void intel_c10pll_state_verify(const struct intel_crtc_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder, - struct intel_c10pll_state *mpllb_hw_state) -{ - struct intel_display *display = to_intel_display(state); - const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; - int i; - - for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { - u8 expected = mpllb_sw_state->pll[i]; - - INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected, - "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", - crtc->base.base.id, crtc->base.name, i, - expected, mpllb_hw_state->pll[i]); - } - - INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx, - "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", - crtc->base.base.id, crtc->base.name, - mpllb_sw_state->tx, mpllb_hw_state->tx); - - INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn, - "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", - crtc->base.base.id, crtc->base.name, - mpllb_sw_state->cmn, mpllb_hw_state->cmn); -} - -void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, struct intel_cx0pll_state *pll_state) { - pll_state->use_c10 = false; + memset(pll_state, 0, sizeof(*pll_state)); - pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); - if (pll_state->tbt_mode) - return; + if (!intel_cx0_pll_is_enabled(encoder)) + return false; - if (intel_encoder_is_c10phy(encoder)) { - intel_c10pll_readout_hw_state(encoder, &pll_state->c10); - pll_state->use_c10 = true; - } else { - intel_c20pll_readout_hw_state(encoder, &pll_state->c20); - } + if (intel_encoder_is_c10phy(encoder)) + intel_c10pll_readout_hw_state(encoder, pll_state); + else + intel_c20pll_readout_hw_state(encoder, pll_state); + + return true; } static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a, @@ -3505,91 +3735,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); } -static void intel_c20pll_state_verify(const struct intel_crtc_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder, - struct intel_c20pll_state *mpll_hw_state) -{ - struct intel_display *display = to_intel_display(state); - const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; - bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state); - bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state); - int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state); - int i; - - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock, - "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", - crtc->base.base.id, crtc->base.name, - mpll_sw_state->clock, mpll_hw_state->clock); - - INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb, - "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)", - crtc->base.base.id, crtc->base.name, - sw_use_mpllb, hw_use_mpllb); - - if (hw_use_mpllb) { - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], - "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)", - crtc->base.base.id, crtc->base.name, i, - mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); - } - } else { - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], - "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)", - crtc->base.base.id, crtc->base.name, i, - mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); - } - } - - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], - "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)", - crtc->base.base.id, crtc->base.name, i, - mpll_sw_state->tx[i], mpll_hw_state->tx[i]); - } - - for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { - INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], - "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)", - crtc->base.base.id, crtc->base.name, i, - mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); - } -} - -void intel_cx0pll_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc) -{ - struct intel_display *display = to_intel_display(state); - const struct intel_crtc_state *new_crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); - struct intel_encoder *encoder; - struct intel_cx0pll_state mpll_hw_state = {}; - - if (!IS_DISPLAY_VER(display, 14, 30)) - return; - - if (!new_crtc_state->hw.active) - return; - - /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ - if (!intel_crtc_needs_modeset(new_crtc_state) && - !intel_crtc_needs_fastset(new_crtc_state)) - return; - - encoder = intel_get_crtc_new_encoder(state, new_crtc_state); - intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state); - - if (mpll_hw_state.tbt_mode) - return; - - if (intel_encoder_is_c10phy(encoder)) - intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10); - else - intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20); -} - /* * WA 14022081154 * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle @@ -3613,6 +3758,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display) for_each_intel_encoder(display->drm, encoder) { struct intel_cx0pll_state pll_state = {}; int port_clock = 162000; + int lane_count = 4; if (!intel_encoder_is_dig_port(encoder)) continue; @@ -3625,7 +3771,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display) if (intel_c10pll_calc_state_from_table(encoder, mtl_c10_edp_tables, - true, port_clock, + true, port_clock, lane_count, &pll_state) < 0) { drm_WARN_ON(display->drm, "Unable to calc C10 state from the tables\n"); @@ -3636,7 +3782,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display) "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n", encoder->base.base.id, encoder->base.name); - __intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4); + intel_cx0pll_enable(encoder, &pll_state); intel_cx0pll_disable(encoder); } } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 84d334b865f77..ae98ac23ea222 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: MIT +/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ @@ -11,6 +11,7 @@ #define MB_WRITE_COMMITTED true #define MB_WRITE_UNCOMMITTED false +struct drm_printer; enum icl_port_dpll_id; struct intel_atomic_state; struct intel_c10pll_state; @@ -19,6 +20,8 @@ struct intel_crtc; struct intel_crtc_state; struct intel_cx0pll_state; struct intel_display; +struct intel_dpll; +struct intel_dpll_hw_state; struct intel_encoder; struct intel_hdmi; @@ -26,22 +29,30 @@ void intel_clear_response_ready_flag(struct intel_encoder *encoder, int lane); bool intel_encoder_is_c10phy(struct intel_encoder *encoder); void intel_mtl_pll_enable(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state); + struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state); void intel_mtl_pll_disable(struct intel_encoder *encoder); enum icl_port_dpll_id intel_mtl_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); +void intel_mtl_pll_enable_clock(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state); +void intel_mtl_pll_disable_clock(struct intel_encoder *encoder); +void intel_mtl_pll_disable_clock(struct intel_encoder *encoder); +void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, + int port_clock); +void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder); -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder); -void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state, + struct intel_encoder *encoder, + struct intel_dpll_hw_state *hw_state); +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, struct intel_cx0pll_state *pll_state); int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, const struct intel_cx0pll_state *pll_state); -void intel_cx0pll_dump_hw_state(struct intel_display *display, +void intel_cx0pll_dump_hw_state(struct drm_printer *p, const struct intel_cx0pll_state *hw_state); -void intel_cx0pll_state_verify(struct intel_atomic_state *state, - struct intel_crtc *crtc); bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, const struct intel_cx0pll_state *b); void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, @@ -59,7 +70,13 @@ void intel_cx0_write(struct intel_encoder *encoder, int intel_cx0_wait_for_ack(struct intel_encoder *encoder, int command, int lane, u32 *val); void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane); + +void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state); +bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display, + struct intel_dpll *pll, + struct intel_dpll_hw_state *hw_state); int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder); + void intel_cx0_pll_power_save_wa(struct intel_display *display); void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index 8df5cd5ce4188..658890f735153 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -1,5 +1,5 @@ -/* SPDX-License-Identifier: MIT - * +/* SPDX-License-Identifier: MIT */ +/* * Copyright © 2023 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 002ccd47856d0..cb91d07cdaa60 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -89,6 +89,8 @@ #include "skl_scaler.h" #include "skl_universal_plane.h" +struct intel_dpll; + static const u8 index_to_dp_signal_levels[] = { [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0, [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1, @@ -726,7 +728,7 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, bool enable, u32 hdcp_mask) { struct intel_display *display = to_intel_display(intel_encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int ret = 0; wakeref = intel_display_power_get_if_enabled(display, @@ -747,7 +749,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) int type = intel_connector->base.connector_type; enum port port = encoder->port; enum transcoder cpu_transcoder; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; enum pipe pipe = 0; u32 ddi_mode; bool ret; @@ -803,7 +805,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); enum port port = encoder->port; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; enum pipe p; u32 tmp; u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0; @@ -846,7 +848,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, for_each_pipe(display, p) { enum transcoder cpu_transcoder = (enum transcoder)p; u32 port_mask, ddi_select, ddi_mode; - intel_wakeref_t trans_wakeref; + struct ref_tracker *trans_wakeref; trans_wakeref = intel_display_power_get_if_enabled(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder)); @@ -1000,7 +1002,7 @@ main_link_aux_power_domain_put(struct intel_digital_port *dig_port, struct intel_display *display = to_intel_display(dig_port); enum intel_display_power_domain domain = intel_ddi_main_link_aux_domain(dig_port, crtc_state); - intel_wakeref_t wf; + struct ref_tracker *wf; wf = fetch_and_zero(&dig_port->aux_wakeref); if (!wf) @@ -2446,7 +2448,7 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, return; } - drm_err(display->drm, "Failed to enable FEC after retries\n"); + drm_dbg_kms(display->drm, "Failed to enable FEC after retries\n"); } static void intel_ddi_disable_fec(struct intel_encoder *encoder, @@ -3128,7 +3130,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &dig_port->dp; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool is_mst = intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST); @@ -3196,7 +3198,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, struct intel_display *display = to_intel_display(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &dig_port->hdmi; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; dig_port->set_infoframes(encoder, false, old_crtc_state, old_conn_state); @@ -3667,8 +3669,8 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc *pipe_crtc; - /* FIXME: Add MTL pll_mgr */ - if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder)) + /* FIXME: Add NVL+ and DG2 pll_mgr */ + if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr) return; for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, @@ -3963,7 +3965,7 @@ static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) { enum intel_display_power_domain power_domain; - intel_wakeref_t trans_wakeref; + struct ref_tracker *trans_wakeref; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); trans_wakeref = intel_display_power_get_if_enabled(display, @@ -4255,19 +4257,70 @@ static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, intel_ddi_get_config(encoder, crtc_state); } -static void mtl_ddi_get_config(struct intel_encoder *encoder, - struct intel_crtc_state *crtc_state) +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) { - intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); + return pll->info->id == DPLL_ID_ICL_TBTPLL; +} - if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) +static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + enum icl_port_dpll_id port_dpll_id, + enum intel_dpll_id pll_id) +{ + struct intel_display *display = to_intel_display(encoder); + struct icl_port_dpll *port_dpll; + struct intel_dpll *pll; + bool pll_active; + + port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; + pll = intel_get_dpll_by_id(display, pll_id); + + if (drm_WARN_ON(display->drm, !pll)) + return; + + port_dpll->pll = pll; + pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state); + drm_WARN_ON(display->drm, !pll_active); + + icl_set_active_port_dpll(crtc_state, port_dpll_id); + + if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll)) crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); else - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); + crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll, + &crtc_state->dpll_hw_state); intel_ddi_get_config(encoder, crtc_state); } +/* + * Get the configuration for either a port using a C10 PHY PLL, or a port using a + * C20 PHY PLL in the cases of: + * - BMG port A/B + * - PTL port B eDP over TypeC PHY + */ +static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(encoder); + + mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, + mtl_port_to_pll_id(display, encoder->port)); +} + +static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(encoder); + + if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) + mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT, + DPLL_ID_ICL_TBTPLL); + else + mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY, + mtl_port_to_pll_id(display, encoder->port)); +} + static void dg2_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -4305,11 +4358,6 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder, intel_ddi_get_config(encoder, crtc_state); } -static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) -{ - return pll->info->id == DPLL_ID_ICL_TBTPLL; -} - static enum icl_port_dpll_id icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) @@ -5100,7 +5148,7 @@ static const char *intel_ddi_encoder_name(struct intel_display *display, port_name(port - PORT_D_XELPD + PORT_D), phy_name(phy)); } else if (DISPLAY_VER(display) >= 12) { - enum tc_port tc_port = intel_port_to_tc(display, port); + enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); seq_buf_printf(s, "DDI %s%c/PHY %s%c", port >= PORT_TC1 ? "TC" : "", @@ -5108,7 +5156,7 @@ static const char *intel_ddi_encoder_name(struct intel_display *display, tc_port != TC_PORT_NONE ? "TC" : "", tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy)); } else if (DISPLAY_VER(display) >= 11) { - enum tc_port tc_port = intel_port_to_tc(display, port); + enum tc_port tc_port = intel_tc_phy_port_to_tc(display, port); seq_buf_printf(s, "DDI %c%s/PHY %s%c", port_name(port), @@ -5252,10 +5300,13 @@ void intel_ddi_init(struct intel_display *display, encoder->port_pll_type = intel_mtl_port_pll_type; encoder->get_config = xe3plpd_ddi_get_config; } else if (DISPLAY_VER(display) >= 14) { - encoder->enable_clock = intel_mtl_pll_enable; - encoder->disable_clock = intel_mtl_pll_disable; - encoder->port_pll_type = intel_mtl_port_pll_type; - encoder->get_config = mtl_ddi_get_config; + encoder->enable_clock = intel_mtl_pll_enable_clock; + encoder->disable_clock = intel_mtl_pll_disable_clock; + encoder->port_pll_type = icl_ddi_tc_port_pll_type; + if (intel_encoder_is_tc(encoder)) + encoder->get_config = mtl_ddi_tc_phy_get_config; + else + encoder->get_config = mtl_ddi_non_tc_phy_get_config; } else if (display->platform.dg2) { encoder->enable_clock = intel_mpllb_enable; encoder->disable_clock = intel_mpllb_disable; @@ -5372,6 +5423,17 @@ void intel_ddi_init(struct intel_display *display, goto err; } + /* + * FIXME: We currently need to store dedicated_external because devdata + * does not live long enough for when intel_encoder_is_tc() is called on + * the unbind path. This needs to be fixed by making sure that the VBT + * data is kept long enough, so that + * intel_bios_encoder_is_dedicated_external() can be called directly + * from intel_encoder_is_tc(). + */ + if (intel_bios_encoder_is_dedicated_external(devdata)) + dig_port->dedicated_external = true; + if (intel_encoder_is_tc(encoder)) { bool is_legacy = !intel_bios_encoder_supports_typec_usb(devdata) && diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 095a319f8bc90..81b3a6692ca20 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -50,7 +50,6 @@ #include "g4x_hdmi.h" #include "hsw_ips.h" #include "i915_config.h" -#include "i915_drv.h" #include "i915_reg.h" #include "i9xx_plane.h" #include "i9xx_plane_regs.h" @@ -100,6 +99,7 @@ #include "intel_frontbuffer.h" #include "intel_hdmi.h" #include "intel_hotplug.h" +#include "intel_initial_plane.h" #include "intel_link_bw.h" #include "intel_lt_phy.h" #include "intel_lvds.h" @@ -113,7 +113,6 @@ #include "intel_pfit.h" #include "intel_pipe_crc.h" #include "intel_plane.h" -#include "intel_plane_initial.h" #include "intel_pmdemand.h" #include "intel_pps.h" #include "intel_psr.h" @@ -372,7 +371,7 @@ void assert_transcoder(struct intel_display *display, { bool cur_state; enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; /* we keep both pipes enabled on 830 */ if (display->platform.i830) @@ -639,7 +638,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc, if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 && hsw_ips_disable(crtc_state)) { crtc_state->ips_enabled = false; - intel_plane_initial_vblank_wait(crtc); + intel_initial_plane_vblank_wait(crtc); } /* @@ -653,7 +652,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc, */ if (HAS_GMCH(display) && intel_set_memory_cxsr(display, false)) - intel_plane_initial_vblank_wait(crtc); + intel_initial_plane_vblank_wait(crtc); /* * Gen2 reports pipe underruns whenever all planes are disabled. @@ -663,7 +662,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc, intel_set_cpu_fifo_underrun_reporting(display, crtc->pipe, false); intel_plane_disable_arm(NULL, plane, crtc_state); - intel_plane_initial_vblank_wait(crtc); + intel_initial_plane_vblank_wait(crtc); } unsigned int @@ -1158,6 +1157,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, if (intel_crtc_vrr_disabling(state, crtc)) { intel_vrr_disable(old_crtc_state); + intel_vrr_dcb_reset(old_crtc_state, crtc); intel_crtc_update_active_timings(old_crtc_state, false); } @@ -1810,7 +1810,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy) return false; } -/* Prefer intel_encoder_is_tc() */ +/* + * This function returns true if the DDI port respective to the PHY enumeration + * is a Type-C capable port. + * + * Depending on the VBT, the port might be configured + * as a "dedicated external" port, meaning that actual physical PHY is outside + * of the Type-C subsystem and, as such, not really a "Type-C PHY". + * + * Prefer intel_encoder_is_tc(), especially if you really need to know if we + * are dealing with Type-C connections. + */ bool intel_phy_is_tc(struct intel_display *display, enum phy phy) { /* @@ -1859,17 +1869,32 @@ enum phy intel_port_to_phy(struct intel_display *display, enum port port) } /* Prefer intel_encoder_to_tc() */ +/* + * Return TC_PORT_1..I915_MAX_TC_PORTS for any TypeC DDI port. The function + * can be also called for TypeC DDI ports not connected to a TypeC PHY such as + * the PORT_TC1..4 ports on RKL/ADLS/BMG. + */ enum tc_port intel_port_to_tc(struct intel_display *display, enum port port) { - if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) - return TC_PORT_NONE; - if (DISPLAY_VER(display) >= 12) return TC_PORT_1 + port - PORT_TC1; else return TC_PORT_1 + port - PORT_C; } +/* + * Return TC_PORT_1..I915_MAX_TC_PORTS for TypeC DDI ports connected to a TypeC PHY. + * Note that on RKL, ADLS, BMG the PORT_TC1..4 ports are connected to a non-TypeC + * PHY, so on those platforms the function returns TC_PORT_NONE. + */ +enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port) +{ + if (!intel_phy_is_tc(display, intel_port_to_phy(display, port))) + return TC_PORT_NONE; + + return intel_port_to_tc(display, port); +} + enum phy intel_encoder_to_phy(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); @@ -1894,6 +1919,10 @@ bool intel_encoder_is_snps(struct intel_encoder *encoder) bool intel_encoder_is_tc(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + if (dig_port && dig_port->dedicated_external) + return false; return intel_phy_is_tc(display, intel_encoder_to_phy(encoder)); } @@ -1902,7 +1931,7 @@ enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); - return intel_port_to_tc(display, encoder->port); + return intel_tc_phy_port_to_tc(display, encoder->port); } enum intel_display_power_domain @@ -3020,7 +3049,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, struct intel_display *display = to_intel_display(crtc); enum intel_display_power_domain power_domain; enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret = false; u32 tmp; @@ -3364,7 +3393,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, struct intel_display *display = to_intel_display(crtc); enum intel_display_power_domain power_domain; enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret = false; u32 tmp; @@ -3454,12 +3483,11 @@ static bool transcoder_ddi_func_is_enabled(struct intel_display *display, enum transcoder cpu_transcoder) { enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; u32 tmp = 0; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - with_intel_display_power_if_enabled(display, power_domain, wakeref) + with_intel_display_power_if_enabled(display, power_domain) tmp = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); @@ -3481,10 +3509,9 @@ static void enabled_uncompressed_joiner_pipes(struct intel_display *display, joiner_pipes(display)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; - intel_wakeref_t wakeref; power_domain = POWER_DOMAIN_PIPE(pipe); - with_intel_display_power_if_enabled(display, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (tmp & UNCOMPRESSED_JOINER_PRIMARY) @@ -3510,10 +3537,9 @@ static void enabled_bigjoiner_pipes(struct intel_display *display, joiner_pipes(display)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; - intel_wakeref_t wakeref; power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); - with_intel_display_power_if_enabled(display, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (!(tmp & BIG_JOINER_ENABLE)) @@ -3580,10 +3606,9 @@ static void enabled_ultrajoiner_pipes(struct intel_display *display, joiner_pipes(display)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; - intel_wakeref_t wakeref; power_domain = intel_dsc_power_domain(crtc, (enum transcoder)pipe); - with_intel_display_power_if_enabled(display, power_domain, wakeref) { + with_intel_display_power_if_enabled(display, power_domain) { u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe)); if (!(tmp & ULTRA_JOINER_ENABLE)) @@ -3741,12 +3766,11 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) for_each_cpu_transcoder_masked(display, cpu_transcoder, panel_transcoder_mask) { enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; enum pipe trans_pipe; u32 tmp = 0; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - with_intel_display_power_if_enabled(display, power_domain, wakeref) + with_intel_display_power_if_enabled(display, power_domain) tmp = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)); @@ -4977,24 +5001,6 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, intel_dpll_dump_hw_state(display, p, b); } -static void -pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, - const struct intel_crtc *crtc, - const char *name, - const struct intel_cx0pll_state *a, - const struct intel_cx0pll_state *b) -{ - struct intel_display *display = to_intel_display(crtc); - char *chipname = a->use_c10 ? "C10" : "C20"; - - pipe_config_mismatch(p, fastset, crtc, name, chipname); - - drm_printf(p, "expected:\n"); - intel_cx0pll_dump_hw_state(display, a); - drm_printf(p, "found:\n"); - intel_cx0pll_dump_hw_state(display, b); -} - static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(old_crtc_state); @@ -5146,16 +5152,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) -#define PIPE_CONF_CHECK_PLL_CX0(name) do { \ - if (!intel_cx0pll_compare_hw_state(¤t_config->name, \ - &pipe_config->name)) { \ - pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \ - ¤t_config->name, \ - &pipe_config->name); \ - ret = false; \ - } \ -} while (0) - #define PIPE_CONF_CHECK_PLL_LT(name) do { \ if (!intel_lt_phy_pll_compare_hw_state(¤t_config->name, \ &pipe_config->name)) { \ @@ -5395,8 +5391,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, /* FIXME convert MTL+ platforms over to dpll_mgr */ if (HAS_LT_PHY(display)) PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll); - else if (DISPLAY_VER(display) >= 14) - PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div); @@ -5482,6 +5476,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); PIPE_CONF_CHECK_BOOL(cmrr.enable); + PIPE_CONF_CHECK_I(vrr.dc_balance.vmin); + PIPE_CONF_CHECK_I(vrr.dc_balance.vmax); + PIPE_CONF_CHECK_I(vrr.dc_balance.guardband); + PIPE_CONF_CHECK_I(vrr.dc_balance.slope); + PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase); + PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease); + PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target); } if (!fastset || intel_vrr_always_use_vrr_tg(display)) { @@ -6032,14 +6033,6 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, return -EINVAL; } - /* FIXME: selective fetch should be disabled for async flips */ - if (new_crtc_state->enable_psr2_sel_fetch) { - drm_dbg_kms(display->drm, - "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n", - crtc->base.base.id, crtc->base.name); - return -EINVAL; - } - for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { if (plane->pipe != crtc->pipe) @@ -6130,7 +6123,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in if (!plane->async_flip) continue; - if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format->format, + if (!intel_plane_can_async_flip(plane, new_plane_state->hw.fb->format, new_plane_state->hw.fb->modifier)) { drm_dbg_kms(display->drm, "[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n", @@ -6870,6 +6863,9 @@ static void intel_update_crtc(struct intel_atomic_state *state, intel_crtc_update_active_timings(new_crtc_state, new_crtc_state->vrr.enable); + if (new_crtc_state->vrr.dc_balance.enable) + intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); + /* * We usually enable FIFO underrun interrupts as part of the * CRTC enable sequence during modesets. But when we inherit a @@ -7168,7 +7164,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) { - struct drm_i915_private *i915 = to_i915(intel_state->base.dev); struct drm_plane *plane; struct drm_plane_state *new_plane_state; long ret; @@ -7177,7 +7172,7 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) { if (new_plane_state->fence) { ret = dma_fence_wait_timeout(new_plane_state->fence, false, - i915_fence_timeout(i915)); + i915_fence_timeout()); if (ret <= 0) break; @@ -7333,6 +7328,21 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, if (new_crtc_state->use_flipq) intel_flipq_wait_dmc_halt(new_crtc_state->dsb_commit, crtc); + if (new_crtc_state->vrr.dc_balance.enable) { + /* + * Pause the DMC DC balancing for the remainder of + * the commit so that vmin/vmax won't change after + * we've baked them into the DSB vblank evasion + * commands. + * + * FIXME maybe need a small delay here to make sure + * DMC has finished updating the values? Or we need + * a better DMC<->driver protocol that gives is real + * guarantees about that... + */ + intel_pipedmc_dcb_disable(NULL, crtc); + } + if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_noarm(new_crtc_state->dsb_commit, new_crtc_state); @@ -7386,6 +7396,10 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); + + if (new_crtc_state->vrr.dc_balance.enable) + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); + intel_dsb_interrupt(new_crtc_state->dsb_commit); } @@ -7395,11 +7409,11 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, static void intel_atomic_commit_tail(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); + struct intel_uncore *uncore = to_intel_uncore(display->drm); struct intel_crtc_state *new_crtc_state, *old_crtc_state; struct intel_crtc *crtc; struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {}; - intel_wakeref_t wakeref = NULL; + struct ref_tracker *wakeref = NULL; int i; for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) @@ -7605,7 +7619,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) * so enable debugging for the next modeset - and hope we catch * the culprit. */ - intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); + intel_uncore_arm_unclaimed_mmio_detection(uncore); } /* * Delay re-enabling DC states by 17 ms to avoid the off->on->off diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index bcc6ccb69d2b5..f8e6e4e827222 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -451,6 +451,7 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy); bool intel_phy_is_tc(struct intel_display *display, enum phy phy); bool intel_phy_is_snps(struct intel_display *display, enum phy phy); enum tc_port intel_port_to_tc(struct intel_display *display, enum port port); +enum tc_port intel_tc_phy_port_to_tc(struct intel_display *display, enum port port); enum phy intel_encoder_to_phy(struct intel_encoder *encoder); bool intel_encoder_is_combo(struct intel_encoder *encoder); diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 9b8414b77c158..d708d322aa85a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -386,7 +386,7 @@ struct intel_display { struct { struct intel_dmc *dmc; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; } dmc; struct { @@ -394,6 +394,21 @@ struct intel_display { u32 mmio_base; } dsi; + struct { + const struct dram_info *info; + } dram; + + struct { + struct intel_fbc *instances[I915_MAX_FBCS]; + + /* xe3p_lpd+: FBC instance utilizing the system cache */ + struct sys_cache_cfg { + /* Protect concurrecnt access to system cache configuration */ + struct mutex lock; + enum intel_fbc_id id; + } sys_cache; + } fbc; + struct { /* list of fbdev register on this device */ struct intel_fbdev *fbdev; @@ -611,7 +626,6 @@ struct intel_display { struct drm_dp_tunnel_mgr *dp_tunnel_mgr; struct intel_audio audio; struct intel_dpll_global dpll; - struct intel_fbc *fbc[I915_MAX_FBCS]; struct intel_frontbuffer_tracking fb_tracking; struct intel_hotplug hotplug; struct intel_opregion *opregion; diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 9bbfdae8d024b..aba13e8a90518 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -86,7 +86,7 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) static int i915_sr_status(struct seq_file *m, void *unused) { struct intel_display *display = node_to_intel_display(m->private); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool sr_enabled = false; wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 1170afaa8680f..471f236c9ddf8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1420,6 +1420,10 @@ static const struct platform_desc ptl_desc = { } }; +static const struct platform_desc nvl_desc = { + PLATFORM(novalake), +}; + __diag_pop(); /* @@ -1495,6 +1499,7 @@ static const struct { INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc), + INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc), }; static const struct { diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index b559ef43d5470..6c74d6b0cc48d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -103,7 +103,9 @@ struct pci_dev; func(battlemage) \ /* Display ver 30 (based on GMD ID) */ \ func(pantherlake) \ - func(pantherlake_wildcatlake) + func(pantherlake_wildcatlake) \ + /* Display ver 35 (based on GMD ID) */ \ + func(novalake) #define __MEMBER(name) unsigned long name:1; @@ -147,7 +149,7 @@ struct intel_display_platforms { #define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14) #define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5) #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13) -#define HAS_AUX_CCS(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) +#define HAS_AUX_DIST(__display) (IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake) #define HAS_BIGJOINER(__display) (DISPLAY_VER(__display) >= 11 && HAS_DSC(__display)) #define HAS_CASF(__display) (DISPLAY_VER(__display) >= 20) #define HAS_CDCLK_CRAWL(__display) (DISPLAY_INFO(__display)->has_cdclk_crawl) @@ -173,6 +175,7 @@ struct intel_display_platforms { #define HAS_DSC_MST(__display) (DISPLAY_VER(__display) >= 12 && HAS_DSC(__display)) #define HAS_FBC(__display) (DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0) #define HAS_FBC_DIRTY_RECT(__display) (DISPLAY_VER(__display) >= 30) +#define HAS_FBC_SYS_CACHE(__display) (DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx) #define HAS_FPGA_DBG_UNCLAIMED(__display) (DISPLAY_INFO(__display)->has_fpga_dbg) #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3) #define HAS_GMBUS_BURST_READ(__display) (DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake) @@ -185,6 +188,7 @@ struct intel_display_platforms { #define HAS_IPS(__display) ((__display)->platform.haswell_ult || (__display)->platform.broadwell) #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12) #define HAS_LSPCON(__display) (IS_DISPLAY_VER(__display, 9, 10)) +#define HAS_LT_PHY(__display) ((__display)->platform.novalake) #define HAS_MBUS_JOINING(__display) ((__display)->platform.alderlake_p || DISPLAY_VER(__display) >= 14) #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12) #define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay) @@ -197,9 +201,11 @@ struct intel_display_platforms { #define HAS_TRANSCODER(__display, trans) ((DISPLAY_RUNTIME_INFO(__display)->cpu_transcoder_mask & \ BIT(trans)) != 0) #define HAS_UNCOMPRESSED_JOINER(__display) (DISPLAY_VER(__display) >= 13) +#define HAS_UNDERRUN_DBG_INFO(__display) (DISPLAY_VER(__display) >= 35) #define HAS_ULTRAJOINER(__display) (((__display)->platform.dgfx && \ DISPLAY_VER(__display) == 14) && HAS_DSC(__display)) #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11) +#define HAS_VRR_DC_BALANCE(__display) (DISPLAY_VER(__display) >= 30) #define INTEL_NUM_PIPES(__display) (hweight8(DISPLAY_RUNTIME_INFO(__display)->pipe_mask)) #define OVERLAY_NEEDS_PHYSICAL(__display) (DISPLAY_INFO(__display)->overlay_needs_physical) #define SUPPORTS_TV(__display) (DISPLAY_INFO(__display)->supports_tv) @@ -255,6 +261,23 @@ struct intel_display_platforms { ((id) == ARLS_HOST_BRIDGE_PCI_ID3) || \ ((id) == ARLS_HOST_BRIDGE_PCI_ID4)) +#define INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe) \ + (DISPLAY_INFO((display))->pipe_offsets[(pipe)] - \ + DISPLAY_INFO((display))->pipe_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE((display))) + +#define INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans) \ + (DISPLAY_INFO((display))->trans_offsets[(trans)] - \ + DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \ + DISPLAY_MMIO_BASE((display))) + +#define INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe) \ + (DISPLAY_INFO((display))->cursor_offsets[(pipe)] - \ + DISPLAY_INFO((display))->cursor_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE((display))) + +#define DISPLAY_MMIO_BASE(display) (DISPLAY_INFO((display))->mmio_offset) + struct intel_display_runtime_info { struct intel_display_ip_ver { u16 ver; diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 7e000ba3e08bf..268b1de45b813 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -18,8 +18,6 @@ #include #include -#include "i915_drv.h" -#include "i915_utils.h" /* for i915_inject_probe_failure() */ #include "i9xx_wm.h" #include "intel_acpi.h" #include "intel_atomic.h" @@ -54,11 +52,11 @@ #include "intel_hdcp.h" #include "intel_hotplug.h" #include "intel_hti.h" +#include "intel_initial_plane.h" #include "intel_modeset_lock.h" #include "intel_modeset_setup.h" #include "intel_opregion.h" #include "intel_overlay.h" -#include "intel_plane_initial.h" #include "intel_pmdemand.h" #include "intel_pps.h" #include "intel_psr.h" @@ -199,12 +197,8 @@ void intel_display_driver_early_probe(struct intel_display *display) /* part #1: call before irq install */ int intel_display_driver_probe_noirq(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); int ret; - if (i915_inject_probe_failure(i915)) - return -ENODEV; - if (HAS_DISPLAY(display)) { ret = drm_vblank_init(display->drm, INTEL_NUM_PIPES(display)); @@ -317,6 +311,7 @@ int intel_display_driver_probe_noirq(struct intel_display *display) return ret; } +ALLOW_ERROR_INJECTION(intel_display_driver_probe_noirq, ERRNO); static void set_display_access(struct intel_display *display, bool any_task_allowed, @@ -452,7 +447,6 @@ bool intel_display_driver_check_access(struct intel_display *display) /* part #2: call after irq install, but before gem init */ int intel_display_driver_probe_nogem(struct intel_display *display) { - enum pipe pipe; int ret; if (!HAS_DISPLAY(display)) @@ -466,15 +460,9 @@ int intel_display_driver_probe_nogem(struct intel_display *display) intel_gmbus_setup(display); - drm_dbg_kms(display->drm, "%d display pipe%s available.\n", - INTEL_NUM_PIPES(display), - INTEL_NUM_PIPES(display) > 1 ? "s" : ""); - - for_each_pipe(display, pipe) { - ret = intel_crtc_init(display, pipe); - if (ret) - goto err_mode_config; - } + ret = intel_crtc_init(display); + if (ret) + goto err_mode_config; intel_plane_possible_crtcs_init(display); intel_dpll_init(display); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 43b27deb4a26d..9adeebb376b18 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -6,8 +6,6 @@ #include #include -#include "i915_drv.h" -#include "i915_irq.h" #include "i915_reg.h" #include "icl_dsi_regs.h" #include "intel_crtc.h" @@ -19,57 +17,83 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_dmc.h" -#include "intel_dmc_wl.h" #include "intel_dp_aux.h" #include "intel_dsb.h" #include "intel_fdi_regs.h" #include "intel_fifo_underrun.h" #include "intel_gmbus.h" #include "intel_hotplug_irq.h" +#include "intel_parent.h" #include "intel_pipe_crc_regs.h" #include "intel_plane.h" #include "intel_pmdemand.h" #include "intel_psr.h" #include "intel_psr_regs.h" -#include "intel_uncore.h" -static void -intel_display_irq_regs_init(struct intel_display *display, struct i915_irq_regs regs, - u32 imr_val, u32 ier_val) +static void irq_reset(struct intel_display *display, struct i915_irq_regs regs) { - intel_dmc_wl_get(display, regs.imr); - intel_dmc_wl_get(display, regs.ier); - intel_dmc_wl_get(display, regs.iir); + intel_de_write(display, regs.imr, 0xffffffff); + intel_de_posting_read(display, regs.imr); - gen2_irq_init(to_intel_uncore(display->drm), regs, imr_val, ier_val); + intel_de_write(display, regs.ier, 0); - intel_dmc_wl_put(display, regs.iir); - intel_dmc_wl_put(display, regs.ier); - intel_dmc_wl_put(display, regs.imr); + /* IIR can theoretically queue up two events. Be paranoid. */ + intel_de_write(display, regs.iir, 0xffffffff); + intel_de_posting_read(display, regs.iir); + intel_de_write(display, regs.iir, 0xffffffff); + intel_de_posting_read(display, regs.iir); } -static void -intel_display_irq_regs_reset(struct intel_display *display, struct i915_irq_regs regs) +/* + * We should clear IMR at preinstall/uninstall, and just check at postinstall. + */ +static void assert_iir_is_zero(struct intel_display *display, i915_reg_t reg) { - intel_dmc_wl_get(display, regs.imr); - intel_dmc_wl_get(display, regs.ier); - intel_dmc_wl_get(display, regs.iir); + u32 val = intel_de_read(display, reg); - gen2_irq_reset(to_intel_uncore(display->drm), regs); + if (val == 0) + return; - intel_dmc_wl_put(display, regs.iir); - intel_dmc_wl_put(display, regs.ier); - intel_dmc_wl_put(display, regs.imr); + drm_WARN(display->drm, 1, + "Interrupt register 0x%x is not zero: 0x%08x\n", + i915_mmio_reg_offset(reg), val); + intel_de_write(display, reg, 0xffffffff); + intel_de_posting_read(display, reg); + intel_de_write(display, reg, 0xffffffff); + intel_de_posting_read(display, reg); } -static void -intel_display_irq_regs_assert_irr_is_zero(struct intel_display *display, i915_reg_t reg) +static void irq_init(struct intel_display *display, struct i915_irq_regs regs, + u32 imr_val, u32 ier_val) { - intel_dmc_wl_get(display, reg); + assert_iir_is_zero(display, regs.iir); + + intel_de_write(display, regs.ier, ier_val); + intel_de_write(display, regs.imr, imr_val); + intel_de_posting_read(display, regs.imr); +} - gen2_assert_iir_is_zero(to_intel_uncore(display->drm), reg); +static void error_reset(struct intel_display *display, struct i915_error_regs regs) +{ + intel_de_write(display, regs.emr, 0xffffffff); + intel_de_posting_read(display, regs.emr); - intel_dmc_wl_put(display, reg); + intel_de_write(display, regs.eir, 0xffffffff); + intel_de_posting_read(display, regs.eir); + intel_de_write(display, regs.eir, 0xffffffff); + intel_de_posting_read(display, regs.eir); +} + +static void error_init(struct intel_display *display, struct i915_error_regs regs, + u32 emr_val) +{ + intel_de_write(display, regs.eir, 0xffffffff); + intel_de_posting_read(display, regs.eir); + intel_de_write(display, regs.eir, 0xffffffff); + intel_de_posting_read(display, regs.eir); + + intel_de_write(display, regs.emr, emr_val); + intel_de_posting_read(display, regs.emr); } struct pipe_fault_handler { @@ -135,7 +159,6 @@ intel_handle_vblank(struct intel_display *display, enum pipe pipe) void ilk_update_display_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 new_val; lockdep_assert_held(&display->irq.lock); @@ -146,7 +169,7 @@ void ilk_update_display_irq(struct intel_display *display, new_val |= (~enabled_irq_mask & interrupt_mask); if (new_val != display->irq.ilk_de_imr_mask && - !drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) { + !drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) { display->irq.ilk_de_imr_mask = new_val; intel_de_write(display, DEIMR, display->irq.ilk_de_imr_mask); intel_de_posting_read(display, DEIMR); @@ -172,7 +195,6 @@ void ilk_disable_display_irq(struct intel_display *display, u32 bits) void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 new_val; u32 old_val; @@ -180,7 +202,7 @@ void bdw_update_port_irq(struct intel_display *display, drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); - if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) + if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) return; old_val = intel_de_read(display, GEN8_DE_PORT_IMR); @@ -206,14 +228,13 @@ static void bdw_update_pipe_irq(struct intel_display *display, enum pipe pipe, u32 interrupt_mask, u32 enabled_irq_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 new_val; lockdep_assert_held(&display->irq.lock); drm_WARN_ON(display->drm, enabled_irq_mask & ~interrupt_mask); - if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) + if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) return; new_val = display->irq.de_pipe_imr_mask[pipe]; @@ -249,7 +270,6 @@ void ibx_display_interrupt_update(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 sdeimr = intel_de_read(display, SDEIMR); sdeimr &= ~interrupt_mask; @@ -259,7 +279,7 @@ void ibx_display_interrupt_update(struct intel_display *display, lockdep_assert_held(&display->irq.lock); - if (drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv))) + if (drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display))) return; intel_de_write(display, SDEIMR, sdeimr); @@ -323,7 +343,6 @@ u32 i915_pipestat_enable_mask(struct intel_display *display, void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); i915_reg_t reg = PIPESTAT(display, pipe); u32 enable_mask; @@ -332,7 +351,7 @@ void i915_enable_pipestat(struct intel_display *display, pipe_name(pipe), status_mask); lockdep_assert_held(&display->irq.lock); - drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); + drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)); if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) return; @@ -347,7 +366,6 @@ void i915_enable_pipestat(struct intel_display *display, void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); i915_reg_t reg = PIPESTAT(display, pipe); u32 enable_mask; @@ -356,7 +374,7 @@ void i915_disable_pipestat(struct intel_display *display, pipe_name(pipe), status_mask); lockdep_assert_held(&display->irq.lock); - drm_WARN_ON(display->drm, !intel_irqs_enabled(dev_priv)); + drm_WARN_ON(display->drm, !intel_parent_irq_enabled(display)); if ((display->irq.pipestat_irq_mask[pipe] & status_mask) == 0) return; @@ -1918,15 +1936,14 @@ static void _vlv_display_irq_reset(struct intel_display *display) else intel_de_write(display, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); - gen2_error_reset(to_intel_uncore(display->drm), - VLV_ERROR_REGS); + error_reset(display, VLV_ERROR_REGS); i915_hotplug_interrupt_update_locked(display, 0xffffffff, 0); intel_de_rmw(display, PORT_HOTPLUG_STAT(display), 0, 0); i9xx_pipestat_irq_reset(display); - intel_display_irq_regs_reset(display, VLV_IRQ_REGS); + irq_reset(display, VLV_IRQ_REGS); display->irq.vlv_imr_mask = ~0u; } @@ -2014,8 +2031,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display) DPINVGTT_STATUS_MASK_VLV | DPINVGTT_EN_MASK_VLV); - gen2_error_init(to_intel_uncore(display->drm), - VLV_ERROR_REGS, ~vlv_error_mask()); + error_init(display, VLV_ERROR_REGS, ~vlv_error_mask()); pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS; @@ -2038,7 +2054,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display) display->irq.vlv_imr_mask = ~enable_mask; - intel_display_irq_regs_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); + irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); } void vlv_display_irq_postinstall(struct intel_display *display) @@ -2054,7 +2070,7 @@ static void ibx_display_irq_reset(struct intel_display *display) if (HAS_PCH_NOP(display)) return; - gen2_irq_reset(to_intel_uncore(display->drm), SDE_IRQ_REGS); + irq_reset(display, SDE_IRQ_REGS); if (HAS_PCH_CPT(display) || HAS_PCH_LPT(display)) intel_de_write(display, SERR_INT, 0xffffffff); @@ -2062,9 +2078,7 @@ static void ibx_display_irq_reset(struct intel_display *display) void ilk_display_irq_reset(struct intel_display *display) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); - - gen2_irq_reset(uncore, DE_IRQ_REGS); + irq_reset(display, DE_IRQ_REGS); display->irq.ilk_de_imr_mask = ~0u; if (DISPLAY_VER(display) == 7) @@ -2091,10 +2105,10 @@ void gen8_display_irq_reset(struct intel_display *display) for_each_pipe(display, pipe) if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); + irq_reset(display, GEN8_DE_PORT_IRQ_REGS); + irq_reset(display, GEN8_DE_MISC_IRQ_REGS); if (HAS_PCH_SPLIT(display)) ibx_display_irq_reset(display); @@ -2136,39 +2150,38 @@ void gen11_display_irq_reset(struct intel_display *display) for_each_pipe(display, pipe) if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); - intel_display_irq_regs_reset(display, GEN8_DE_PORT_IRQ_REGS); - intel_display_irq_regs_reset(display, GEN8_DE_MISC_IRQ_REGS); + irq_reset(display, GEN8_DE_PORT_IRQ_REGS); + irq_reset(display, GEN8_DE_MISC_IRQ_REGS); if (DISPLAY_VER(display) >= 14) - intel_display_irq_regs_reset(display, PICAINTERRUPT_IRQ_REGS); + irq_reset(display, PICAINTERRUPT_IRQ_REGS); else - intel_display_irq_regs_reset(display, GEN11_DE_HPD_IRQ_REGS); + irq_reset(display, GEN11_DE_HPD_IRQ_REGS); if (INTEL_PCH_TYPE(display) >= PCH_ICP) - intel_display_irq_regs_reset(display, SDE_IRQ_REGS); + irq_reset(display, SDE_IRQ_REGS); } void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN | gen8_de_pipe_flip_done_mask(display); enum pipe pipe; spin_lock_irq(&display->irq.lock); - if (!intel_irqs_enabled(dev_priv)) { + if (!intel_parent_irq_enabled(display)) { spin_unlock_irq(&display->irq.lock); return; } for_each_pipe_masked(display, pipe, pipe_mask) - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), - display->irq.de_pipe_imr_mask[pipe], - ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); + irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), + display->irq.de_pipe_imr_mask[pipe], + ~display->irq.de_pipe_imr_mask[pipe] | extra_ier); spin_unlock_irq(&display->irq.lock); } @@ -2176,23 +2189,22 @@ void gen8_irq_power_well_post_enable(struct intel_display *display, void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask) { - struct drm_i915_private *dev_priv = to_i915(display->drm); enum pipe pipe; spin_lock_irq(&display->irq.lock); - if (!intel_irqs_enabled(dev_priv)) { + if (!intel_parent_irq_enabled(display)) { spin_unlock_irq(&display->irq.lock); return; } for_each_pipe_masked(display, pipe, pipe_mask) - intel_display_irq_regs_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); + irq_reset(display, GEN8_DE_PIPE_IRQ_REGS(pipe)); spin_unlock_irq(&display->irq.lock); /* make sure we're done processing display irqs */ - intel_synchronize_irq(dev_priv); + intel_parent_irq_synchronize(display); } /* @@ -2220,13 +2232,11 @@ static void ibx_irq_postinstall(struct intel_display *display) else mask = SDE_GMBUS_CPT; - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); + irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); } void valleyview_enable_display_irqs(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - spin_lock_irq(&display->irq.lock); if (display->irq.vlv_display_irqs_enabled) @@ -2234,7 +2244,7 @@ void valleyview_enable_display_irqs(struct intel_display *display) display->irq.vlv_display_irqs_enabled = true; - if (intel_irqs_enabled(dev_priv)) { + if (intel_parent_irq_enabled(display)) { _vlv_display_irq_reset(display); _vlv_display_irq_postinstall(display); } @@ -2245,8 +2255,6 @@ void valleyview_enable_display_irqs(struct intel_display *display) void valleyview_disable_display_irqs(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - spin_lock_irq(&display->irq.lock); if (!display->irq.vlv_display_irqs_enabled) @@ -2254,7 +2262,7 @@ void valleyview_disable_display_irqs(struct intel_display *display) display->irq.vlv_display_irqs_enabled = false; - if (intel_irqs_enabled(dev_priv)) + if (intel_parent_irq_enabled(display)) _vlv_display_irq_reset(display); out: spin_unlock_irq(&display->irq.lock); @@ -2286,7 +2294,7 @@ void ilk_de_irq_postinstall(struct intel_display *display) } if (display->platform.haswell) { - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); + assert_iir_is_zero(display, EDP_PSR_IIR); display_mask |= DE_EDP_PSR_INT_HSW; } @@ -2297,8 +2305,8 @@ void ilk_de_irq_postinstall(struct intel_display *display) ibx_irq_postinstall(display); - intel_display_irq_regs_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, - display_mask | extra_mask); + irq_init(display, DE_IRQ_REGS, display->irq.ilk_de_imr_mask, + display_mask | extra_mask); } static void mtp_irq_postinstall(struct intel_display *display); @@ -2374,11 +2382,10 @@ void gen8_de_irq_postinstall(struct intel_display *display) if (!intel_display_power_is_enabled(display, domain)) continue; - intel_display_irq_regs_assert_irr_is_zero(display, - TRANS_PSR_IIR(display, trans)); + assert_iir_is_zero(display, TRANS_PSR_IIR(display, trans)); } } else { - intel_display_irq_regs_assert_irr_is_zero(display, EDP_PSR_IIR); + assert_iir_is_zero(display, EDP_PSR_IIR); } for_each_pipe(display, pipe) { @@ -2386,44 +2393,50 @@ void gen8_de_irq_postinstall(struct intel_display *display) if (intel_display_power_is_enabled(display, POWER_DOMAIN_PIPE(pipe))) - intel_display_irq_regs_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), - display->irq.de_pipe_imr_mask[pipe], - de_pipe_enables); + irq_init(display, GEN8_DE_PIPE_IRQ_REGS(pipe), + display->irq.de_pipe_imr_mask[pipe], + de_pipe_enables); } - intel_display_irq_regs_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, - de_port_enables); - intel_display_irq_regs_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, - de_misc_masked); + irq_init(display, GEN8_DE_PORT_IRQ_REGS, ~de_port_masked, de_port_enables); + irq_init(display, GEN8_DE_MISC_IRQ_REGS, ~de_misc_masked, de_misc_masked); if (IS_DISPLAY_VER(display, 11, 13)) { u32 de_hpd_masked = 0; u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; - intel_display_irq_regs_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, - de_hpd_enables); + irq_init(display, GEN11_DE_HPD_IRQ_REGS, ~de_hpd_masked, de_hpd_enables); } } +u32 xelpdp_pica_aux_mask(struct intel_display *display) +{ + u32 mask = XELPDP_AUX_TC_MASK; + + if (DISPLAY_VER(display) >= 20) + mask |= XE2LPD_AUX_DDI_MASK; + + return mask; +} + static void mtp_irq_postinstall(struct intel_display *display) { u32 sde_mask = SDE_GMBUS_ICP | SDE_PICAINTERRUPT; - u32 de_hpd_mask = XELPDP_AUX_TC_MASK; + u32 de_hpd_mask = xelpdp_pica_aux_mask(display); u32 de_hpd_enables = de_hpd_mask | XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK; - intel_display_irq_regs_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, - de_hpd_enables); + irq_init(display, PICAINTERRUPT_IRQ_REGS, ~de_hpd_mask, de_hpd_enables); - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); + irq_init(display, SDE_IRQ_REGS, ~sde_mask, 0xffffffff); } static void icp_irq_postinstall(struct intel_display *display) { u32 mask = SDE_GMBUS_ICP; - intel_display_irq_regs_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); + irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); } void gen11_de_irq_postinstall(struct intel_display *display) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index 84acd31948cfc..b25d180254d75 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -16,6 +16,8 @@ struct drm_printer; struct intel_display; struct intel_display_irq_snapshot; +u32 xelpdp_pica_aux_mask(struct intel_display *display); + void valleyview_enable_display_irqs(struct intel_display *display); void valleyview_disable_display_irqs(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index b01bc5700c52d..b95ecf728daab 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: MIT +/* SPDX-License-Identifier: MIT */ /* * Copyright © 2023 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 2a4cc1dcc293b..d27397f438633 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -8,10 +8,6 @@ #include -#include "soc/intel_dram.h" - -#include "i915_drv.h" -#include "i915_irq.h" #include "i915_reg.h" #include "intel_backlight_regs.h" #include "intel_cdclk.h" @@ -26,12 +22,15 @@ #include "intel_display_types.h" #include "intel_display_utils.h" #include "intel_dmc.h" +#include "intel_dram.h" #include "intel_mchbar_regs.h" +#include "intel_parent.h" #include "intel_pch_refclk.h" #include "intel_pcode.h" #include "intel_pmdemand.h" #include "intel_pps_regs.h" #include "intel_snps_phy.h" +#include "intel_step.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" #include "vlv_sideband.h" @@ -545,8 +544,8 @@ __intel_display_power_get_domain(struct intel_display *display, * Any power domain reference obtained by this function must have a symmetric * call to intel_display_power_put() to release the reference again. */ -intel_wakeref_t intel_display_power_get(struct intel_display *display, - enum intel_display_power_domain domain) +struct ref_tracker *intel_display_power_get(struct intel_display *display, + enum intel_display_power_domain domain) { struct i915_power_domains *power_domains = &display->power.domains; struct ref_tracker *wakeref; @@ -572,7 +571,7 @@ intel_wakeref_t intel_display_power_get(struct intel_display *display, * Any power domain reference obtained by this function must have a symmetric * call to intel_display_power_put() to release the reference again. */ -intel_wakeref_t +struct ref_tracker * intel_display_power_get_if_enabled(struct intel_display *display, enum intel_display_power_domain domain) { @@ -639,7 +638,7 @@ static void __intel_display_power_put(struct intel_display *display, static void queue_async_put_domains_work(struct i915_power_domains *power_domains, - intel_wakeref_t wakeref, + struct ref_tracker *wakeref, int delay_ms) { struct intel_display *display = container_of(power_domains, @@ -741,7 +740,7 @@ intel_display_power_put_async_work(struct work_struct *work) */ void __intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref, + struct ref_tracker *wakeref, int delay_ms) { struct i915_power_domains *power_domains = &display->power.domains; @@ -800,7 +799,7 @@ void intel_display_power_flush_work(struct intel_display *display) { struct i915_power_domains *power_domains = &display->power.domains; struct intel_power_domain_mask async_put_mask; - intel_wakeref_t work_wakeref; + struct ref_tracker *work_wakeref; mutex_lock(&power_domains->lock); @@ -854,7 +853,7 @@ intel_display_power_flush_work_sync(struct intel_display *display) */ void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref) + struct ref_tracker *wakeref) { __intel_display_power_put(display, domain); intel_display_rpm_put(display, wakeref); @@ -886,7 +885,7 @@ intel_display_power_get_in_set(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain) { - intel_wakeref_t __maybe_unused wf; + struct ref_tracker *__maybe_unused wf; drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); @@ -902,7 +901,7 @@ intel_display_power_get_in_set_if_enabled(struct intel_display *display, struct intel_display_power_domain_set *power_domain_set, enum intel_display_power_domain domain) { - intel_wakeref_t wf; + struct ref_tracker *wf; drm_WARN_ON(display->drm, test_bit(domain, power_domain_set->mask.bits)); @@ -929,7 +928,7 @@ intel_display_power_put_mask_in_set(struct intel_display *display, !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM)); for_each_power_domain(domain, mask) { - intel_wakeref_t __maybe_unused wf = INTEL_WAKEREF_DEF; + struct ref_tracker *__maybe_unused wf = INTEL_WAKEREF_DEF; #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) wf = fetch_and_zero(&power_domain_set->wakerefs[domain]); @@ -1202,7 +1201,6 @@ static void hsw_assert_cdclk(struct intel_display *display) static void assert_can_disable_lcpll(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc *crtc; for_each_intel_crtc(display->drm, crtc) @@ -1247,7 +1245,7 @@ static void assert_can_disable_lcpll(struct intel_display *display) * gen-specific and since we only disable LCPLL after we fully disable * the interrupts, the check below should be enough. */ - INTEL_DISPLAY_STATE_WARN(display, intel_irqs_enabled(dev_priv), + INTEL_DISPLAY_STATE_WARN(display, intel_parent_irq_enabled(display), "IRQs enabled\n"); } @@ -1330,7 +1328,6 @@ static void hsw_disable_lcpll(struct intel_display *display, */ static void hsw_restore_lcpll(struct intel_display *display) { - struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); u32 val; int ret; @@ -1341,10 +1338,10 @@ static void hsw_restore_lcpll(struct intel_display *display) return; /* - * Make sure we're not on PC8 state before disabling PC8, otherwise - * we'll hang the machine. To prevent PC8 state, just enable force_wake. + * Make sure we're not on PC8 state before disabling + * PC8, otherwise we'll hang the machine. */ - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL); + intel_parent_pc8_block(display); if (val & LCPLL_POWER_DOWN_ALLOW) { val &= ~LCPLL_POWER_DOWN_ALLOW; @@ -1374,7 +1371,7 @@ static void hsw_restore_lcpll(struct intel_display *display) "Switching back to LCPLL failed\n"); } - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); + intel_parent_pc8_unblock(display); intel_update_cdclk(display); intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); @@ -1417,8 +1414,6 @@ static void hsw_enable_pc8(struct intel_display *display) static void hsw_disable_pc8(struct intel_display *display) { - struct drm_i915_private __maybe_unused *dev_priv = to_i915(display->drm); - drm_dbg_kms(display->drm, "Disabling package C8+\n"); hsw_restore_lcpll(display); @@ -1426,7 +1421,7 @@ static void hsw_disable_pc8(struct intel_display *display) /* Many display registers don't survive PC8+ */ #ifdef I915 /* FIXME */ - intel_clock_gating_init(dev_priv); + intel_clock_gating_init(display->drm); #endif } @@ -1618,7 +1613,7 @@ static const struct buddy_page_mask wa_1409767108_buddy_page_masks[] = { static void tgl_bw_buddy_init(struct intel_display *display) { - const struct dram_info *dram_info = intel_dram_info(display->drm); + const struct dram_info *dram_info = intel_dram_info(display); const struct buddy_page_mask *table; unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask; int config, i; @@ -2006,7 +2001,7 @@ void intel_power_domains_init_hw(struct intel_display *display, bool resume) */ void intel_power_domains_driver_remove(struct intel_display *display) { - intel_wakeref_t wakeref __maybe_unused = + struct ref_tracker *wakeref __maybe_unused = fetch_and_zero(&display->power.domains.init_wakeref); /* Remove the refcount we took to keep power well support disabled. */ @@ -2067,7 +2062,7 @@ void intel_power_domains_sanitize_state(struct intel_display *display) */ void intel_power_domains_enable(struct intel_display *display) { - intel_wakeref_t wakeref __maybe_unused = + struct ref_tracker *wakeref __maybe_unused = fetch_and_zero(&display->power.domains.init_wakeref); intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); @@ -2106,7 +2101,7 @@ void intel_power_domains_disable(struct intel_display *display) void intel_power_domains_suspend(struct intel_display *display, bool s2idle) { struct i915_power_domains *power_domains = &display->power.domains; - intel_wakeref_t wakeref __maybe_unused = + struct ref_tracker *wakeref __maybe_unused = fetch_and_zero(&power_domains->init_wakeref); intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index f8813b0e16dfb..d616d5d09cbed 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -9,15 +9,17 @@ #include #include -#include "intel_wakeref.h" - enum aux_ch; enum port; struct i915_power_well; struct intel_display; struct intel_encoder; +struct ref_tracker; struct seq_file; +/* -ENOENT means we got the ref, but there's no tracking */ +#define INTEL_WAKEREF_DEF ERR_PTR(-ENOENT) + /* * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances * consecutive, so that the pipe,transcoder,port -> power domain macros @@ -142,14 +144,14 @@ struct i915_power_domains { u32 target_dc_state; u32 allowed_dc_mask; - intel_wakeref_t init_wakeref; - intel_wakeref_t disable_wakeref; + struct ref_tracker *init_wakeref; + struct ref_tracker *disable_wakeref; struct mutex lock; int domain_use_count[POWER_DOMAIN_NUM]; struct delayed_work async_put_work; - intel_wakeref_t async_put_wakeref; + struct ref_tracker *async_put_wakeref; struct intel_power_domain_mask async_put_domains[2]; int async_put_next_delay; @@ -159,7 +161,7 @@ struct i915_power_domains { struct intel_display_power_domain_set { struct intel_power_domain_mask mask; #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM - intel_wakeref_t wakerefs[POWER_DOMAIN_NUM]; + struct ref_tracker *wakerefs[POWER_DOMAIN_NUM]; #endif }; @@ -187,24 +189,24 @@ u32 intel_display_power_get_current_dc_state(struct intel_display *display); bool intel_display_power_is_enabled(struct intel_display *display, enum intel_display_power_domain domain); -intel_wakeref_t intel_display_power_get(struct intel_display *display, - enum intel_display_power_domain domain); -intel_wakeref_t +struct ref_tracker *intel_display_power_get(struct intel_display *display, + enum intel_display_power_domain domain); +struct ref_tracker * intel_display_power_get_if_enabled(struct intel_display *display, enum intel_display_power_domain domain); void __intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref, + struct ref_tracker *wakeref, int delay_ms); void intel_display_power_flush_work(struct intel_display *display); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref); + struct ref_tracker *wakeref); static inline void intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref) + struct ref_tracker *wakeref) { __intel_display_power_put_async(display, domain, wakeref, -1); } @@ -212,7 +214,7 @@ intel_display_power_put_async(struct intel_display *display, static inline void intel_display_power_put_async_delay(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref, + struct ref_tracker *wakeref, int delay_ms) { __intel_display_power_put_async(display, domain, wakeref, delay_ms); @@ -224,7 +226,7 @@ void intel_display_power_put_unchecked(struct intel_display *display, static inline void intel_display_power_put(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref) + struct ref_tracker *wakeref) { intel_display_power_put_unchecked(display, domain); } @@ -232,7 +234,7 @@ intel_display_power_put(struct intel_display *display, static inline void intel_display_power_put_async(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref) + struct ref_tracker *wakeref) { __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, -1); } @@ -240,7 +242,7 @@ intel_display_power_put_async(struct intel_display *display, static inline void intel_display_power_put_async_delay(struct intel_display *display, enum intel_display_power_domain domain, - intel_wakeref_t wakeref, + struct ref_tracker *wakeref, int delay_ms) { __intel_display_power_put_async(display, domain, INTEL_WAKEREF_DEF, delay_ms); @@ -297,12 +299,18 @@ enum dbuf_slice { void gen9_dbuf_slices_update(struct intel_display *display, u8 req_slices); -#define with_intel_display_power(display, domain, wf) \ - for ((wf) = intel_display_power_get((display), (domain)); (wf); \ +#define __with_intel_display_power(display, domain, wf) \ + for (struct ref_tracker *(wf) = intel_display_power_get((display), (domain)); (wf); \ intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) -#define with_intel_display_power_if_enabled(display, domain, wf) \ - for ((wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ +#define with_intel_display_power(display, domain) \ + __with_intel_display_power(display, domain, __UNIQUE_ID(wakeref)) + +#define __with_intel_display_power_if_enabled(display, domain, wf) \ + for (struct ref_tracker *(wf) = intel_display_power_get_if_enabled((display), (domain)); (wf); \ intel_display_power_put_async((display), (domain), (wf)), (wf) = NULL) +#define with_intel_display_power_if_enabled(display, domain) \ + __with_intel_display_power_if_enabled(display, domain, __UNIQUE_ID(wakeref)) + #endif /* __INTEL_DISPLAY_POWER_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index f4f7e73acc874..db185a8591339 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -7,8 +7,6 @@ #include -#include "i915_drv.h" -#include "i915_irq.h" #include "i915_reg.h" #include "intel_backlight_regs.h" #include "intel_combo_phy.h" @@ -28,6 +26,7 @@ #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_hotplug.h" +#include "intel_parent.h" #include "intel_pcode.h" #include "intel_pps.h" #include "intel_psr.h" @@ -258,8 +257,9 @@ aux_ch_to_digital_port(struct intel_display *display, return NULL; } -static enum phy icl_aux_pw_to_phy(struct intel_display *display, - const struct i915_power_well *power_well) +static struct intel_encoder * +icl_aux_pw_to_encoder(struct intel_display *display, + const struct i915_power_well *power_well) { enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well); struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch); @@ -271,7 +271,23 @@ static enum phy icl_aux_pw_to_phy(struct intel_display *display, * as HDMI-only and routed to a combo PHY, the encoder either won't be * present at all or it will not have an aux_ch assigned. */ - return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE; + return dig_port ? &dig_port->base : NULL; +} + +static enum phy icl_aux_pw_to_phy(struct intel_display *display, + const struct i915_power_well *power_well) +{ + struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); + + return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE; +} + +static bool icl_aux_pw_is_tc_phy(struct intel_display *display, + const struct i915_power_well *power_well) +{ + struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well); + + return encoder && intel_encoder_is_tc(encoder); } static void hsw_wait_for_power_well_enable(struct intel_display *display, @@ -570,9 +586,7 @@ static void icl_aux_power_well_enable(struct intel_display *display, struct i915_power_well *power_well) { - enum phy phy = icl_aux_pw_to_phy(display, power_well); - - if (intel_phy_is_tc(display, phy)) + if (icl_aux_pw_is_tc_phy(display, power_well)) return icl_tc_phy_aux_power_well_enable(display, power_well); else if (display->platform.icelake) return icl_combo_phy_aux_power_well_enable(display, @@ -585,9 +599,7 @@ static void icl_aux_power_well_disable(struct intel_display *display, struct i915_power_well *power_well) { - enum phy phy = icl_aux_pw_to_phy(display, power_well); - - if (intel_phy_is_tc(display, phy)) + if (icl_aux_pw_is_tc_phy(display, power_well)) return hsw_power_well_disable(display, power_well); else if (display->platform.icelake) return icl_combo_phy_aux_power_well_disable(display, @@ -628,8 +640,6 @@ static bool hsw_power_well_enabled(struct intel_display *display, static void assert_can_enable_dc9(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - drm_WARN_ONCE(display->drm, (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), "DC9 already programmed to be enabled.\n"); @@ -641,7 +651,7 @@ static void assert_can_enable_dc9(struct intel_display *display) intel_de_read(display, HSW_PWR_WELL_CTL2) & HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), "Power well 2 on.\n"); - drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), + drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), "Interrupts not disabled yet.\n"); /* @@ -655,9 +665,7 @@ static void assert_can_enable_dc9(struct intel_display *display) static void assert_can_disable_dc9(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - - drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), + drm_WARN_ONCE(display->drm, intel_parent_irq_enabled(display), "Interrupts not disabled yet.\n"); drm_WARN_ONCE(display->drm, intel_de_read(display, DC_STATE_EN) & @@ -1281,12 +1289,10 @@ static void vlv_display_power_well_init(struct intel_display *display) static void vlv_display_power_well_deinit(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - valleyview_disable_display_irqs(display); /* make sure we're done processing display irqs */ - intel_synchronize_irq(dev_priv); + intel_parent_irq_synchronize(display); vlv_pps_reset_all(display); @@ -1852,7 +1858,7 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display, enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch; enum phy phy = icl_aux_pw_to_phy(display, power_well); - if (intel_phy_is_tc(display, phy)) + if (icl_aux_pw_is_tc_phy(display, power_well)) icl_tc_port_assert_ref_held(display, power_well, aux_ch_to_digital_port(display, aux_ch)); @@ -1860,19 +1866,19 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display, XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, XELPDP_DP_AUX_CH_CTL_POWER_REQUEST); - /* - * The power status flag cannot be used to determine whether aux - * power wells have finished powering up. Instead we're - * expected to just wait a fixed 600us after raising the request - * bit. - */ - if (DISPLAY_VER(display) >= 35) { + if (HAS_LT_PHY(display)) { if (intel_de_wait_for_set_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 2)) drm_warn(display->drm, "Timeout waiting for PHY %c AUX channel power to be up\n", phy_name(phy)); } else { + /* + * The power status flag cannot be used to determine whether aux + * power wells have finished powering up. Instead we're + * expected to just wait a fixed 600us after raising the request + * bit. + */ usleep_range(600, 1200); } } @@ -1887,7 +1893,7 @@ static void xelpdp_aux_power_well_disable(struct intel_display *display, XELPDP_DP_AUX_CH_CTL_POWER_REQUEST, 0); - if (DISPLAY_VER(display) >= 35) { + if (HAS_LT_PHY(display)) { if (intel_de_wait_for_clear_ms(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1)) drm_warn(display->drm, diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index b83ad06f2ea7a..175334b41bba2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -8,8 +8,6 @@ #include "i915_reg_defs.h" -#define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset) - #define VLV_DISPLAY_BASE 0x180000 /* @@ -36,14 +34,9 @@ * Device info offset array based helpers for groups of registers with unevenly * spaced base offsets. */ -#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \ - DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \ - DISPLAY_MMIO_BASE(display) + (reg)) -#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ - DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \ - DISPLAY_MMIO_BASE(display) + (reg)) -#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \ - DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \ - DISPLAY_MMIO_BASE(display) + (reg)) + +#define _MMIO_PIPE2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_PIPE_OFFSET((display), (pipe)) + (reg)) +#define _MMIO_TRANS2(display, trans, reg) _MMIO(INTEL_DISPLAY_DEVICE_TRANS_OFFSET((display), (trans)) + (reg)) +#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(INTEL_DISPLAY_DEVICE_CURSOR_OFFSET((display), (pipe)) + (reg)) #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 9d71e26a4fa27..9e0d853f4b61a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -882,6 +882,21 @@ #define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */ #define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id)) +#define _UNDERRUN_DBG1_A 0x70064 +#define _UNDERRUN_DBG1_B 0x71064 +#define UNDERRUN_DBG1(pipe) _MMIO_PIPE(pipe, _UNDERRUN_DBG1_A, _UNDERRUN_DBG1_B) +#define UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK REG_GENMASK(29, 24) +#define UNDERRUN_DDB_EMPTY_MASK REG_GENMASK(21, 16) +#define UNDERRUN_DBUF_NOT_FILLED_MASK REG_GENMASK(13, 8) +#define UNDERRUN_BELOW_WM0_MASK REG_GENMASK(5, 0) + +#define _UNDERRUN_DBG2_A 0x70068 +#define _UNDERRUN_DBG2_B 0x71068 +#define UNDERRUN_DBG2(pipe) _MMIO_PIPE(pipe, _UNDERRUN_DBG2_A, _UNDERRUN_DBG2_B) +#define UNDERRUN_FRAME_LINE_COUNTERS_FROZEN REG_BIT(31) +#define UNDERRUN_PIPE_FRAME_COUNT_MASK REG_GENMASK(30, 20) +#define UNDERRUN_LINE_COUNT_MASK REG_GENMASK(19, 0) + #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */ #define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16) #define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16) @@ -1416,6 +1431,7 @@ #define GEN12_DCPR_STATUS_1 _MMIO(0x46440) #define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26) +#define XE3P_UNDERRUN_PKGC REG_BIT(21) #define FUSE_STRAP _MMIO(0x42014) #define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31) @@ -2349,8 +2365,13 @@ enum skl_power_gate { #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) #define DDI_A_4_LANES REG_BIT(4) #define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) +#define DDI_PORT_WIDTH_ENCODE(width) ((width) == 3 ? 4 : (width) - 1) +#define DDI_PORT_WIDTH_DECODE(regval) ((regval) == 4 ? 3 : (regval) + 1) #define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ - ((width) == 3 ? 4 : (width) - 1)) + DDI_PORT_WIDTH_ENCODE(width)) +#define DDI_PORT_WIDTH_GET(regval) DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \ + (regval))) + #define DDI_PORT_WIDTH_SHIFT 1 #define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) diff --git a/drivers/gpu/drm/i915/display/intel_display_reset.c b/drivers/gpu/drm/i915/display/intel_display_reset.c index 03e8c68d29133..d00ef5bdcbda9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reset.c +++ b/drivers/gpu/drm/i915/display/intel_display_reset.c @@ -6,13 +6,13 @@ #include #include -#include "i915_drv.h" #include "intel_clock_gating.h" #include "intel_cx0_phy.h" #include "intel_display_core.h" #include "intel_display_driver.h" #include "intel_display_reset.h" #include "intel_display_types.h" +#include "intel_display_utils.h" #include "intel_hotplug.h" #include "intel_pps.h" @@ -79,7 +79,6 @@ bool intel_display_reset_prepare(struct intel_display *display, void intel_display_reset_finish(struct intel_display *display, bool test_only) { - struct drm_i915_private *i915 = to_i915(display->drm); struct drm_modeset_acquire_ctx *ctx = &display->restore.reset_ctx; struct drm_atomic_state *state; int ret; @@ -107,7 +106,7 @@ void intel_display_reset_finish(struct intel_display *display, bool test_only) */ intel_pps_unlock_regs_wa(display); intel_display_driver_init_hw(display); - intel_clock_gating_init(i915); + intel_clock_gating_init(display->drm); intel_cx0_pll_power_save_wa(display); intel_hpd_init(display); diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c index 82ea1ec482e41..e77811396474f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rps.c +++ b/drivers/gpu/drm/i915/display/intel_display_rps.c @@ -3,38 +3,39 @@ * Copyright © 2023 Intel Corporation */ +#include + #include #include -#include "gt/intel_rps.h" -#include "i915_drv.h" #include "i915_reg.h" #include "intel_display_core.h" #include "intel_display_irq.h" #include "intel_display_rps.h" #include "intel_display_types.h" +#include "intel_parent.h" struct wait_rps_boost { struct wait_queue_entry wait; struct drm_crtc *crtc; - struct i915_request *request; + struct dma_fence *fence; }; static int do_rps_boost(struct wait_queue_entry *_wait, unsigned mode, int sync, void *key) { struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait); - struct i915_request *rq = wait->request; + struct intel_display *display = to_intel_display(wait->crtc->dev); /* * If we missed the vblank, but the request is already running it * is reasonable to assume that it will complete before the next - * vblank without our intervention, so leave RPS alone. + * vblank without our intervention, so leave RPS alone if not started. */ - if (!i915_request_started(rq)) - intel_rps_boost(rq); - i915_request_put(rq); + intel_parent_rps_boost_if_not_started(display, wait->fence); + + dma_fence_put(wait->fence); drm_crtc_vblank_put(wait->crtc); @@ -49,7 +50,7 @@ void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, struct intel_display *display = to_intel_display(crtc->dev); struct wait_rps_boost *wait; - if (!dma_fence_is_i915(fence)) + if (!intel_parent_rps_available(display)) return; if (DISPLAY_VER(display) < 6) @@ -64,7 +65,7 @@ void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, return; } - wait->request = to_request(dma_fence_get(fence)); + wait->fence = dma_fence_get(fence); wait->crtc = crtc; wait->wait.func = do_rps_boost; @@ -77,12 +78,14 @@ void intel_display_rps_mark_interactive(struct intel_display *display, struct intel_atomic_state *state, bool interactive) { - struct drm_i915_private *i915 = to_i915(display->drm); + if (!intel_parent_rps_available(display)) + return; if (state->rps_interactive == interactive) return; - intel_rps_mark_interactive(&to_gt(i915)->rps, interactive); + intel_parent_rps_mark_interactive(display, interactive); + state->rps_interactive = interactive; } @@ -102,7 +105,5 @@ void ilk_display_rps_disable(struct intel_display *display) void ilk_display_rps_irq_handler(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - - gen5_rps_irq_handler(&to_gt(i915)->rps); + intel_parent_rps_ilk_irq_handler(display); } diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.h b/drivers/gpu/drm/i915/display/intel_display_rps.h index 183d154f2c7cf..96b1fd00ead45 100644 --- a/drivers/gpu/drm/i915/display/intel_display_rps.h +++ b/drivers/gpu/drm/i915/display/intel_display_rps.h @@ -13,7 +13,6 @@ struct drm_crtc; struct intel_atomic_state; struct intel_display; -#ifdef I915 void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, struct dma_fence *fence); void intel_display_rps_mark_interactive(struct intel_display *display, @@ -22,25 +21,5 @@ void intel_display_rps_mark_interactive(struct intel_display *display, void ilk_display_rps_enable(struct intel_display *display); void ilk_display_rps_disable(struct intel_display *display); void ilk_display_rps_irq_handler(struct intel_display *display); -#else -static inline void intel_display_rps_boost_after_vblank(struct drm_crtc *crtc, - struct dma_fence *fence) -{ -} -static inline void intel_display_rps_mark_interactive(struct intel_display *display, - struct intel_atomic_state *state, - bool interactive) -{ -} -static inline void ilk_display_rps_enable(struct intel_display *display) -{ -} -static inline void ilk_display_rps_disable(struct intel_display *display) -{ -} -static inline void ilk_display_rps_irq_handler(struct intel_display *display) -{ -} -#endif #endif /* __INTEL_DISPLAY_RPS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 06bf8f7c0989b..6b92f333e18bc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -509,6 +510,12 @@ struct intel_hdcp { bool force_hdcp14; }; +enum intel_panel_replay_dsc_support { + INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED, + INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY, + INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE, +}; + struct intel_connector { struct drm_connector base; /* @@ -561,6 +568,30 @@ struct intel_connector { } overall_throughput; int max_line_width; } dsc_branch_caps; + + struct { + u8 dpcd[DP_PANEL_REPLAY_CAP_SIZE]; +#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT) + + bool support; + bool su_support; + enum intel_panel_replay_dsc_support dsc_support; + + u16 su_w_granularity; + u16 su_y_granularity; + } panel_replay_caps; + + struct { + u8 dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; + + bool support; + bool su_support; + + u16 su_w_granularity; + u16 su_y_granularity; + + u8 sync_latency; + } psr_caps; } dp; struct { @@ -955,12 +986,6 @@ struct intel_csc_matrix { u16 postoff[3]; }; -enum intel_panel_replay_dsc_support { - INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED, - INTEL_DP_PANEL_REPLAY_DSC_FULL_FRAME_ONLY, - INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE, -}; - struct scaler_filter_coeff { u16 sign; u16 exp; @@ -1152,6 +1177,8 @@ struct intel_crtc_state { bool enable_psr2_su_region_et; bool req_psr2_sdp_prior_scanline; bool has_panel_replay; + bool link_off_after_as_sdp_when_pr_active; + bool disable_as_sdp_when_pr_active; bool wm_level_disabled; bool pkg_c_latency_used; /* Only used for state verification. */ @@ -1358,6 +1385,13 @@ struct intel_crtc_state { u8 pipeline_full; u16 flipline, vmin, vmax, guardband; u32 vsync_end, vsync_start; + struct { + bool enable; + u16 vmin, vmax; + u16 guardband, slope; + u16 max_increase, max_decrease; + u16 vblank_target; + } dc_balance; } vrr; /* Content Match Refresh Rate state */ @@ -1498,6 +1532,10 @@ struct intel_crtc { struct intel_link_m_n m_n, m2_n2; } drrs; + struct { + u64 flip_count; + } dc_balance; + int scanline_offset; struct { @@ -1662,7 +1700,7 @@ struct intel_pps { unsigned long last_power_on; unsigned long last_backlight_off; ktime_t panel_power_off_time; - intel_wakeref_t vdd_wakeref; + struct ref_tracker *vdd_wakeref; union { /* @@ -1716,14 +1754,12 @@ struct intel_psr { bool active; struct work_struct work; unsigned int busy_frontbuffer_bits; - bool sink_psr2_support; bool link_standby; bool sel_update_enabled; bool psr2_sel_fetch_enabled; bool psr2_sel_fetch_cff_enabled; bool su_region_et_enabled; bool req_psr2_sdp_prior_scanline; - u8 sink_sync_latency; ktime_t last_entry_attempt; ktime_t last_exit; bool sink_not_reliable; @@ -1732,8 +1768,6 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; - bool sink_panel_replay_su_support; - enum intel_panel_replay_dsc_support sink_panel_replay_dsc_support; bool panel_replay_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; @@ -1760,9 +1794,6 @@ struct intel_dp { bool needs_modeset_retry; bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; - u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; - u8 pr_dpcd[DP_PANEL_REPLAY_CAP_SIZE]; -#define INTEL_PR_DPCD_INDEX(pr_dpcd_register) ((pr_dpcd_register) - DP_PANEL_REPLAY_CAP_SUPPORT) u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; @@ -1940,12 +1971,13 @@ struct intel_digital_port { bool lane_reversal; bool ddi_a_4_lanes; bool release_cl2_override; + bool dedicated_external; u8 max_lanes; /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */ enum aux_ch aux_ch; enum intel_display_power_domain ddi_io_power_domain; - intel_wakeref_t ddi_io_wakeref; - intel_wakeref_t aux_wakeref; + struct ref_tracker *ddi_io_wakeref; + struct ref_tracker *aux_wakeref; struct intel_tc_port *tc; diff --git a/drivers/gpu/drm/i915/display/intel_display_utils.h b/drivers/gpu/drm/i915/display/intel_display_utils.h index 2a18f160320cb..affa3179f52c7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_utils.h +++ b/drivers/gpu/drm/i915/display/intel_display_utils.h @@ -9,18 +9,14 @@ struct intel_display; -#ifndef MISSING_CASE #define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \ __stringify(x), (long)(x)) -#endif -#ifndef fetch_and_zero #define fetch_and_zero(ptr) ({ \ typeof(*ptr) __T = *(ptr); \ *(ptr) = (typeof(*ptr))0; \ __T; \ }) -#endif #define KHz(x) (1000 * (x)) #define MHz(x) KHz(1000 * (x)) diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c index e38e5e87877c2..581d943b9bdc3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.c +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -62,12 +62,18 @@ static bool intel_display_needs_wa_16025573575(struct intel_display *display) bool __intel_display_wa(struct intel_display *display, enum intel_display_wa wa, const char *name) { switch (wa) { + case INTEL_DISPLAY_WA_13012396614: + return DISPLAY_VERx100(display) == 3000; + case INTEL_DISPLAY_WA_14011503117: + return DISPLAY_VER(display) == 13; + case INTEL_DISPLAY_WA_14025769978: + return DISPLAY_VER(display) == 35; + case INTEL_DISPLAY_WA_15018326506: + return display->platform.battlemage; case INTEL_DISPLAY_WA_16023588340: return intel_display_needs_wa_16023588340(display); case INTEL_DISPLAY_WA_16025573575: return intel_display_needs_wa_16025573575(display); - case INTEL_DISPLAY_WA_14011503117: - return DISPLAY_VER(display) == 13; case INTEL_DISPLAY_WA_22014263786: return IS_DISPLAY_VERx100(display, 1100, 1400); default: diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h index 3644e8e2b7245..40f989f19df17 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.h +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h @@ -21,10 +21,18 @@ static inline bool intel_display_needs_wa_16023588340(struct intel_display *disp bool intel_display_needs_wa_16023588340(struct intel_display *display); #endif +/* + * This enum lists display workarounds; each entry here must have a + * corresponding case in __intel_display_wa(). Keep both sorted by lineage + * number. + */ enum intel_display_wa { + INTEL_DISPLAY_WA_13012396614, + INTEL_DISPLAY_WA_14011503117, + INTEL_DISPLAY_WA_14025769978, + INTEL_DISPLAY_WA_15018326506, INTEL_DISPLAY_WA_16023588340, INTEL_DISPLAY_WA_16025573575, - INTEL_DISPLAY_WA_14011503117, INTEL_DISPLAY_WA_22014263786, }; diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 6ebbd97e6351b..1182bc9a2e6dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -859,6 +859,14 @@ static void dmc_configure_event(struct intel_display *display, dmc_id, num_handlers, event_id); } +void intel_dmc_configure_dc_balance_event(struct intel_display *display, + enum pipe pipe, bool enable) +{ + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); + + dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); +} + /** * intel_dmc_block_pkgc() - block PKG C-state * @display: display instance @@ -1322,7 +1330,7 @@ static void intel_dmc_runtime_pm_get(struct intel_display *display) static void intel_dmc_runtime_pm_put(struct intel_display *display) { - intel_wakeref_t wakeref __maybe_unused = + struct ref_tracker *wakeref __maybe_unused = fetch_and_zero(&display->dmc.wakeref); intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref); @@ -1755,3 +1763,20 @@ u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc) return dmc ? dmc->dmc_info[dmc_id].start_mmioaddr : 0; } + +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + enum pipe pipe = crtc->pipe; + + intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), + PIPEDMC_ADAPTIVE_DCB_ENABLE); +} + +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + enum pipe pipe = crtc->pipe; + + intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(pipe), 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index 40e9dcb033cc6..3d8a9a593319b 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -15,6 +15,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_display; struct intel_dmc_snapshot; +struct intel_dsb; void intel_dmc_init(struct intel_display *display); void intel_dmc_load_program(struct intel_display *display); @@ -24,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state); void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state); void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, bool block); +void intel_dmc_configure_dc_balance_event(struct intel_display *display, + enum pipe pipe, bool enable); void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, enum pipe pipe, bool enable); void intel_dmc_fini(struct intel_display *display); @@ -39,6 +42,8 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star void assert_main_dmc_loaded(struct intel_display *display); void intel_pipedmc_irq_handler(struct intel_display *display, enum pipe pipe); +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc); +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc); u32 intel_pipedmc_start_mmioaddr(struct intel_crtc *crtc); void intel_pipedmc_enable_event(struct intel_crtc *crtc, diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index c5aa49921cb9f..38e342b45af06 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -584,4 +584,64 @@ enum pipedmc_event_id { #define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8) #define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0) +#define _PIPEDMC_DCB_CTL_A 0x5f1a0 +#define _PIPEDMC_DCB_CTL_B 0x5f5a0 +#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\ + _PIPEDMC_DCB_CTL_B) +#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31) + +#define _PIPEDMC_DCB_VBLANK_A 0x5f1bc +#define _PIPEDMC_DCB_VBLANK_B 0x5f5bc +#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\ + _PIPEDMC_DCB_VBLANK_B) + +#define _PIPEDMC_DCB_SLOPE_A 0x5f1b8 +#define _PIPEDMC_DCB_SLOPE_B 0x5f5b8 +#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\ + _PIPEDMC_DCB_SLOPE_B) + +#define _PIPEDMC_DCB_GUARDBAND_A 0x5f1b4 +#define _PIPEDMC_DCB_GUARDBAND_B 0x5f5b4 +#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\ + _PIPEDMC_DCB_GUARDBAND_B) + +#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5f1ac +#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5f5ac +#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\ + _PIPEDMC_DCB_MAX_INCREASE_B) + +#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5f1b0 +#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5f5b0 +#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\ + _PIPEDMC_DCB_MAX_DECREASE_B) + +#define _PIPEDMC_DCB_VMIN_A 0x5f1a4 +#define _PIPEDMC_DCB_VMIN_B 0x5f5a4 +#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\ + _PIPEDMC_DCB_VMIN_B) + +#define _PIPEDMC_DCB_VMAX_A 0x5f1a8 +#define _PIPEDMC_DCB_VMAX_B 0x5f5a8 +#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\ + _PIPEDMC_DCB_VMAX_B) + +#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0 +#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0 +#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\ + _PIPEDMC_DCB_DEBUG_B) + +#define _PIPEDMC_EVT_CTL_3_A 0x5f040 +#define _PIPEDMC_EVT_CTL_3_B 0x5f440 +#define PIPEDMC_EVT_CTL_3(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\ + _PIPEDMC_EVT_CTL_3_B) + +#define _PIPEDMC_DCB_FLIP_COUNT_A 0x906a4 +#define _PIPEDMC_DCB_FLIP_COUNT_B 0x986a4 +#define PIPEDMC_DCB_FLIP_COUNT(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_FLIP_COUNT_A,\ + _PIPEDMC_DCB_FLIP_COUNT_B) + +#define _PIPEDMC_DCB_BALANCE_RESET_A 0x906a8 +#define _PIPEDMC_DCB_BALANCE_RESET_B 0x986a8 +#define PIPEDMC_DCB_BALANCE_RESET(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_BALANCE_RESET_A,\ + _PIPEDMC_DCB_BALANCE_RESET_B) #endif /* __INTEL_DMC_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0ec82fcbcf48e..7e022c47e8ac2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -424,18 +424,44 @@ static int intel_dp_min_lane_count(struct intel_dp *intel_dp) return 1; } +int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, + int dsc_slice_count, int bpp_x16, unsigned long flags) +{ + int overhead; + + WARN_ON(flags & ~(DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK | + DRM_DP_BW_OVERHEAD_FEC)); + + if (drm_dp_is_uhbr_rate(link_clock)) + flags |= DRM_DP_BW_OVERHEAD_UHBR; + + if (dsc_slice_count) + flags |= DRM_DP_BW_OVERHEAD_DSC; + + overhead = drm_dp_bw_overhead(lane_count, hdisplay, + dsc_slice_count, + bpp_x16, + flags); + + /* + * TODO: clarify whether a minimum required by the fixed FEC overhead + * in the bspec audio programming sequence is required here. + */ + return max(overhead, intel_dp_bw_fec_overhead(flags & DRM_DP_BW_OVERHEAD_FEC)); +} + /* * The required data bandwidth for a mode with given pixel clock and bpp. This * is the required net bandwidth independent of the data bandwidth efficiency. - * - * TODO: check if callers of this functions should use - * intel_dp_effective_data_rate() instead. */ -int -intel_dp_link_required(int pixel_clock, int bpp) +int intel_dp_link_required(int link_clock, int lane_count, + int mode_clock, int mode_hdisplay, + int link_bpp_x16, unsigned long bw_overhead_flags) { - /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ - return DIV_ROUND_UP(pixel_clock * bpp, 8); + int bw_overhead = intel_dp_link_bw_overhead(link_clock, lane_count, mode_hdisplay, + 0, link_bpp_x16, bw_overhead_flags); + + return intel_dp_effective_data_rate(mode_clock, link_bpp_x16, bw_overhead); } /** @@ -520,7 +546,8 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) struct intel_display *display = to_intel_display(intel_dp); struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; - if (intel_encoder_is_c10phy(encoder)) + if (intel_encoder_is_c10phy(encoder) || + display->platform.pantherlake_wildcatlake) return 810000; if (DISPLAY_VERx100(display) == 1401) @@ -841,50 +868,32 @@ small_joiner_ram_size_bits(struct intel_display *display) return 6144 * 8; } -static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp) +static int align_min_vesa_compressed_bpp_x16(int min_link_bpp_x16) { - u32 bits_per_pixel = bpp; int i; - /* Error out if the max bpp is less than smallest allowed valid bpp */ - if (bits_per_pixel < valid_dsc_bpp[0]) { - drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n", - bits_per_pixel, valid_dsc_bpp[0]); - return 0; + for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { + int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]); + + if (vesa_bpp_x16 >= min_link_bpp_x16) + return vesa_bpp_x16; } - /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ - if (DISPLAY_VER(display) >= 13) { - bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); + return 0; +} - /* - * According to BSpec, 27 is the max DSC output bpp, - * 8 is the min DSC output bpp. - * While we can still clamp higher bpp values to 27, saving bandwidth, - * if it is required to oompress up to bpp < 8, means we can't do - * that and probably means we can't fit the required mode, even with - * DSC enabled. - */ - if (bits_per_pixel < 8) { - drm_dbg_kms(display->drm, - "Unsupported BPP %u, min 8\n", - bits_per_pixel); - return 0; - } - bits_per_pixel = min_t(u32, bits_per_pixel, 27); - } else { - /* Find the nearest match in the array of known BPPs from VESA */ - for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { - if (bits_per_pixel < valid_dsc_bpp[i + 1]) - break; - } - drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n", - bits_per_pixel, valid_dsc_bpp[i]); +static int align_max_vesa_compressed_bpp_x16(int max_link_bpp_x16) +{ + int i; + + for (i = ARRAY_SIZE(valid_dsc_bpp) - 1; i >= 0; i--) { + int vesa_bpp_x16 = fxp_q4_from_int(valid_dsc_bpp[i]); - bits_per_pixel = valid_dsc_bpp[i]; + if (vesa_bpp_x16 <= max_link_bpp_x16) + return vesa_bpp_x16; } - return bits_per_pixel; + return 0; } static int bigjoiner_interface_bits(struct intel_display *display) @@ -950,69 +959,13 @@ u32 get_max_compressed_bpp_with_joiner(struct intel_display *display, return max_bpp; } -/* TODO: return a bpp_x16 value */ -u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - int num_joined_pipes, - enum intel_output_format output_format, - u32 pipe_bpp, - u32 timeslots) -{ - u32 bits_per_pixel, joiner_max_bpp; - - /* - * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* - * (LinkSymbolClock)* 8 * (TimeSlots / 64) - * for SST -> TimeSlots is 64(i.e all TimeSlots that are available) - * for MST -> TimeSlots has to be calculated, based on mode requirements - * - * Due to FEC overhead, the available bw is reduced to 97.2261%. - * To support the given mode: - * Bandwidth required should be <= Available link Bandwidth * FEC Overhead - * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead - * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock - * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) / - * (ModeClock / FEC Overhead) - * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) / - * (ModeClock / FEC Overhead * 8) - */ - bits_per_pixel = ((link_clock * lane_count) * timeslots) / - (intel_dp_mode_to_fec_clock(mode_clock) * 8); - - /* Bandwidth required for 420 is half, that of 444 format */ - if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) - bits_per_pixel *= 2; - - /* - * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum - * supported PPS value can be 63.9375 and with the further - * mention that for 420, 422 formats, bpp should be programmed double - * the target bpp restricting our target bpp to be 31.9375 at max. - */ - if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) - bits_per_pixel = min_t(u32, bits_per_pixel, 31); - - drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots " - "total bw %u pixel clock %u\n", - bits_per_pixel, timeslots, - (link_clock * lane_count * 8), - intel_dp_mode_to_fec_clock(mode_clock)); - - joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock, - mode_hdisplay, num_joined_pipes); - bits_per_pixel = min(bits_per_pixel, joiner_max_bpp); - - bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp); - - return bits_per_pixel; -} - u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, int num_joined_pipes) { struct intel_display *display = to_intel_display(connector); + u32 sink_slice_count_mask = + drm_dp_dsc_sink_slice_count_mask(connector->dp.dsc_dpcd, false); u8 min_slice_count, i; int max_slice_width; int tp_rgb_yuv444; @@ -1084,9 +1037,9 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4)) continue; - if (test_slice_count > - drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) - break; + if (!(drm_dp_dsc_slice_count_to_mask(test_slice_count) & + sink_slice_count_mask)) + continue; /* * Bigjoiner needs small joiner to be enabled. @@ -1103,8 +1056,14 @@ u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, return test_slice_count; } - drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n", - min_slice_count); + /* Print slice count 1,2,4,..24 if bit#0,1,3,..23 is set in the mask. */ + sink_slice_count_mask <<= 1; + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] Unsupported slice count (min: %d, sink supported: %*pbl)\n", + connector->base.base.id, connector->base.name, + min_slice_count, + (int)BITS_PER_TYPE(sink_slice_count_mask), &sink_slice_count_mask); + return 0; } @@ -1226,7 +1185,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format) return 8 * 3; } -int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) +int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, int pipe_bpp) { /* * bpp value was assumed to RGB format. And YCbCr 4:2:0 output @@ -1234,9 +1193,9 @@ int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) * of bytes of RGB pixel. */ if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) - bpp /= 2; + pipe_bpp /= 2; - return bpp; + return fxp_q4_from_int(pipe_bpp); } static enum intel_output_format @@ -1252,8 +1211,8 @@ intel_dp_sink_format(struct intel_connector *connector, } static int -intel_dp_mode_min_output_bpp(struct intel_connector *connector, - const struct drm_display_mode *mode) +intel_dp_mode_min_link_bpp_x16(struct intel_connector *connector, + const struct drm_display_mode *mode) { enum intel_output_format output_format, sink_format; @@ -1261,7 +1220,8 @@ intel_dp_mode_min_output_bpp(struct intel_connector *connector, output_format = intel_dp_output_format(connector, sink_format); - return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); + return intel_dp_output_format_link_bpp_x16(output_format, + intel_dp_min_bpp(output_format)); } static bool intel_dp_hdisplay_bad(struct intel_display *display, @@ -1333,11 +1293,11 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { + int link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); int target_bw; int max_frl_bw; - int bpp = intel_dp_mode_min_output_bpp(connector, mode); - target_bw = bpp * target_clock; + target_bw = fxp_q4_to_int_roundup(link_bpp_x16) * target_clock; max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; @@ -1452,6 +1412,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, enum drm_mode_status status; bool dsc = false; int num_joined_pipes; + int link_bpp_x16; status = intel_cpu_transcoder_mode_valid(display, mode); if (status != MODE_OK) @@ -1494,8 +1455,10 @@ intel_dp_mode_valid(struct drm_connector *_connector, max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); - mode_rate = intel_dp_link_required(target_clock, - intel_dp_mode_min_output_bpp(connector, mode)); + link_bpp_x16 = intel_dp_mode_min_link_bpp_x16(connector, mode); + mode_rate = intel_dp_link_required(max_link_clock, max_lanes, + target_clock, mode->hdisplay, + link_bpp_x16, 0); if (intel_dp_has_dsc(connector)) { int pipe_bpp; @@ -1516,24 +1479,20 @@ intel_dp_mode_valid(struct drm_connector *_connector, dsc_slice_count = drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, true); + dsc = dsc_max_compressed_bpp && dsc_slice_count; } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { - dsc_max_compressed_bpp = - intel_dp_dsc_get_max_compressed_bpp(display, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - num_joined_pipes, - output_format, - pipe_bpp, 64); - dsc_slice_count = - intel_dp_dsc_get_slice_count(connector, - target_clock, - mode->hdisplay, - num_joined_pipes); - } + unsigned long bw_overhead_flags = 0; - dsc = dsc_max_compressed_bpp && dsc_slice_count; + if (!drm_dp_is_uhbr_rate(max_link_clock)) + bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC; + + dsc = intel_dp_mode_valid_with_dsc(connector, + max_link_clock, max_lanes, + target_clock, mode->hdisplay, + num_joined_pipes, + output_format, pipe_bpp, + bw_overhead_flags); + } } if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) @@ -1802,14 +1761,13 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, const struct link_config_limits *limits) { int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state); - int mode_rate, link_rate, link_avail; + int link_rate, link_avail; for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); bpp >= fxp_q4_to_int(limits->link.min_bpp_x16); bpp -= 2 * 3) { - int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); - - mode_rate = intel_dp_link_required(clock, link_bpp); + int link_bpp_x16 = + intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp); for (i = 0; i < intel_dp->num_common_rates; i++) { link_rate = intel_dp_common_rate(intel_dp, i); @@ -1820,11 +1778,17 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, for (lane_count = limits->min_lane_count; lane_count <= limits->max_lane_count; lane_count <<= 1) { + const struct drm_display_mode *adjusted_mode = + &pipe_config->hw.adjusted_mode; + int mode_rate = + intel_dp_link_required(link_rate, lane_count, + clock, adjusted_mode->hdisplay, + link_bpp_x16, 0); + link_avail = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); - if (mode_rate <= link_avail) { pipe_config->lane_count = lane_count; pipe_config->pipe_bpp = bpp; @@ -1850,12 +1814,44 @@ int intel_dp_dsc_max_src_input_bpc(struct intel_display *display) return intel_dp_dsc_min_src_input_bpc(); } +static int align_min_sink_dsc_input_bpp(const struct intel_connector *connector, + int min_pipe_bpp) +{ + u8 dsc_bpc[3]; + int num_bpc; + int i; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, + dsc_bpc); + for (i = num_bpc - 1; i >= 0; i--) { + if (dsc_bpc[i] * 3 >= min_pipe_bpp) + return dsc_bpc[i] * 3; + } + + return 0; +} + +static int align_max_sink_dsc_input_bpp(const struct intel_connector *connector, + int max_pipe_bpp) +{ + u8 dsc_bpc[3]; + int num_bpc; + int i; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (dsc_bpc[i] * 3 <= max_pipe_bpp) + return dsc_bpc[i] * 3; + } + + return 0; +} + int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, u8 max_req_bpc) { struct intel_display *display = to_intel_display(connector); - int i, num_bpc; - u8 dsc_bpc[3] = {}; int dsc_max_bpc; dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); @@ -1865,14 +1861,7 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, dsc_max_bpc = min(dsc_max_bpc, max_req_bpc); - num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, - dsc_bpc); - for (i = 0; i < num_bpc; i++) { - if (dsc_max_bpc >= dsc_bpc[i]) - return dsc_bpc[i] * 3; - } - - return 0; + return align_max_sink_dsc_input_bpp(connector, dsc_max_bpc * 3); } static int intel_dp_source_dsc_version_minor(struct intel_display *display) @@ -1982,25 +1971,28 @@ static bool intel_dp_dsc_supports_format(const struct intel_connector *connector return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); } -static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock, - u32 lane_count, u32 mode_clock, - enum intel_output_format output_format, - int timeslots) +static bool is_bw_sufficient_for_dsc_config(struct intel_dp *intel_dp, + int link_clock, int lane_count, + int mode_clock, int mode_hdisplay, + int dsc_slice_count, int link_bpp_x16, + unsigned long bw_overhead_flags) { - u32 available_bw, required_bw; + int available_bw; + int required_bw; - available_bw = (link_clock * lane_count * timeslots * 16) / 8; - required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock)); + available_bw = intel_dp_max_link_data_rate(intel_dp, link_clock, lane_count); + required_bw = intel_dp_link_required(link_clock, lane_count, + mode_clock, mode_hdisplay, + link_bpp_x16, bw_overhead_flags); - return available_bw > required_bw; + return available_bw >= required_bw; } static int dsc_compute_link_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, const struct link_config_limits *limits, - int dsc_bpp_x16, - int timeslots) + int dsc_bpp_x16) { const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int link_rate, lane_count; @@ -2038,10 +2030,16 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, if (ret) continue; } else { - if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate, - lane_count, adjusted_mode->clock, - pipe_config->output_format, - timeslots)) + unsigned long bw_overhead_flags = + pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; + + if (!is_bw_sufficient_for_dsc_config(intel_dp, + link_rate, lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->hdisplay, + pipe_config->dsc.slice_count, + dsc_bpp_x16, + bw_overhead_flags)) continue; } @@ -2054,7 +2052,7 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, static u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, - const struct intel_crtc_state *pipe_config, + enum intel_output_format output_format, int bpc) { u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); @@ -2065,43 +2063,43 @@ u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connec * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate * values as given in spec Table 2-157 DP v2.0 */ - switch (pipe_config->output_format) { + switch (output_format) { case INTEL_OUTPUT_FORMAT_RGB: case INTEL_OUTPUT_FORMAT_YCBCR444: return (3 * bpc) << 4; case INTEL_OUTPUT_FORMAT_YCBCR420: return (3 * (bpc / 2)) << 4; default: - MISSING_CASE(pipe_config->output_format); + MISSING_CASE(output_format); break; } return 0; } -int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config) +static int intel_dp_dsc_sink_min_compressed_bpp(enum intel_output_format output_format) { /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */ - switch (pipe_config->output_format) { + switch (output_format) { case INTEL_OUTPUT_FORMAT_RGB: case INTEL_OUTPUT_FORMAT_YCBCR444: return 8; case INTEL_OUTPUT_FORMAT_YCBCR420: return 6; default: - MISSING_CASE(pipe_config->output_format); + MISSING_CASE(output_format); break; } return 0; } -int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, - const struct intel_crtc_state *pipe_config, - int bpc) +static int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, + enum intel_output_format output_format, + int bpc) { return intel_dp_dsc_max_sink_compressed_bppx16(connector, - pipe_config, bpc) >> 4; + output_format, bpc) >> 4; } int intel_dp_dsc_min_src_compressed_bpp(void) @@ -2159,7 +2157,6 @@ int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) { struct intel_display *display = to_intel_display(intel_dp); - int i; if (DISPLAY_VER(display) >= 13) { if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16)) @@ -2171,12 +2168,41 @@ bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16) if (fxp_q4_to_frac(bpp_x16)) return false; - for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) { - if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i]) - return true; + return align_max_vesa_compressed_bpp_x16(bpp_x16) == bpp_x16; +} + +static int align_min_compressed_bpp_x16(const struct intel_connector *connector, int min_bpp_x16) +{ + struct intel_display *display = to_intel_display(connector); + + if (DISPLAY_VER(display) >= 13) { + int bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); + + drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); + + return round_up(min_bpp_x16, bpp_step_x16); + } else { + return align_min_vesa_compressed_bpp_x16(min_bpp_x16); } +} - return false; +static int align_max_compressed_bpp_x16(const struct intel_connector *connector, + enum intel_output_format output_format, + int pipe_bpp, int max_bpp_x16) +{ + struct intel_display *display = to_intel_display(connector); + int link_bpp_x16 = intel_dp_output_format_link_bpp_x16(output_format, pipe_bpp); + int bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); + + max_bpp_x16 = min(max_bpp_x16, link_bpp_x16 - bpp_step_x16); + + if (DISPLAY_VER(display) >= 13) { + drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); + + return round_down(max_bpp_x16, bpp_step_x16); + } else { + return align_max_vesa_compressed_bpp_x16(max_bpp_x16); + } } /* @@ -2187,33 +2213,28 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, const struct link_config_limits *limits, - int pipe_bpp, - int timeslots) + int pipe_bpp) { struct intel_display *display = to_intel_display(intel_dp); const struct intel_connector *connector = to_intel_connector(conn_state->connector); - const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; - int output_bpp; int min_bpp_x16, max_bpp_x16, bpp_step_x16; - int dsc_joiner_max_bpp; - int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config); int bpp_x16; int ret; - dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock, - adjusted_mode->hdisplay, - num_joined_pipes); - max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16); - + min_bpp_x16 = limits->link.min_bpp_x16; + max_bpp_x16 = limits->link.max_bpp_x16; bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); - /* Compressed BPP should be less than the Input DSC bpp */ - output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); - max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); + max_bpp_x16 = align_max_compressed_bpp_x16(connector, pipe_config->output_format, + pipe_bpp, max_bpp_x16); + if (intel_dp_is_edp(intel_dp)) { + pipe_config->port_clock = limits->max_rate; + pipe_config->lane_count = limits->max_lane_count; - drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); - min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16); - max_bpp_x16 = round_down(max_bpp_x16, bpp_step_x16); + pipe_config->dsc.compressed_bpp_x16 = max_bpp_x16; + + return 0; + } for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16)) @@ -2223,8 +2244,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, pipe_config, conn_state, limits, - bpp_x16, - timeslots); + bpp_x16); if (ret == 0) { pipe_config->dsc.compressed_bpp_x16 = bpp_x16; if (intel_dp->force_dsc_fractional_bpp_en && @@ -2281,86 +2301,21 @@ int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp, static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, - const struct link_config_limits *limits, - int timeslots) + const struct link_config_limits *limits) { - const struct intel_connector *connector = - to_intel_connector(conn_state->connector); - u8 dsc_bpc[3] = {}; int forced_bpp, pipe_bpp; - int num_bpc, i, ret; - - forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); - - if (forced_bpp) { - ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, - limits, forced_bpp, timeslots); - if (ret == 0) { - pipe_config->pipe_bpp = forced_bpp; - return 0; - } - } - - /* - * Get the maximum DSC bpc that will be supported by any valid - * link configuration and compressed bpp. - */ - num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); - for (i = 0; i < num_bpc; i++) { - pipe_bpp = dsc_bpc[i] * 3; - if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp) - continue; - - ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, - limits, pipe_bpp, timeslots); - if (ret == 0) { - pipe_config->pipe_bpp = pipe_bpp; - return 0; - } - } - - return -EINVAL; -} - -static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - const struct link_config_limits *limits) -{ - struct intel_display *display = to_intel_display(intel_dp); - struct intel_connector *connector = - to_intel_connector(conn_state->connector); - int pipe_bpp, forced_bpp; - int dsc_min_bpp; - int dsc_max_bpp; + int ret; forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); - - if (forced_bpp) { + if (forced_bpp) pipe_bpp = forced_bpp; - } else { - int max_bpc = limits->pipe.max_bpp / 3; - - /* For eDP use max bpp that can be supported with DSC. */ - pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); - if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { - drm_dbg_kms(display->drm, - "Computed BPC is not in DSC BPC limits\n"); - return -EINVAL; - } - } - pipe_config->port_clock = limits->max_rate; - pipe_config->lane_count = limits->max_lane_count; - - dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16); - - dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); - - /* Compressed BPP should be less than the Input DSC bpp */ - dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1); + else + pipe_bpp = limits->pipe.max_bpp; - pipe_config->dsc.compressed_bpp_x16 = - fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp)); + ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state, + limits, pipe_bpp); + if (ret) + return -EINVAL; pipe_config->pipe_bpp = pipe_bpp; @@ -2418,12 +2373,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * figured out for DP MST DSC. */ if (!is_mst) { - if (intel_dp_is_edp(intel_dp)) - ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config, - conn_state, limits); - else - ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, - conn_state, limits, timeslots); + ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config, + conn_state, limits); if (ret) { drm_dbg_kms(display->drm, "No Valid pipe bpp for given mode ret = %d\n", ret); @@ -2496,11 +2447,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, static int dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector, - const struct intel_crtc_state *crtc_state) + int mode_clock) { - const struct drm_display_mode *adjusted_mode = - &crtc_state->hw.adjusted_mode; - if (!connector->dp.dsc_throughput_quirk) return INT_MAX; @@ -2520,7 +2468,7 @@ dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector, * smaller than the YUV422/420 value, but let's not depend on this * assumption. */ - if (adjusted_mode->crtc_clock < + if (mode_clock < min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444, connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2) return INT_MAX; @@ -2528,18 +2476,106 @@ dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector, return fxp_q4_from_int(12); } +static int compute_min_compressed_bpp_x16(struct intel_connector *connector, + enum intel_output_format output_format) +{ + int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; + int min_bpp_x16; + + dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp(); + dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(output_format); + dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); + + min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); + + min_bpp_x16 = align_min_compressed_bpp_x16(connector, min_bpp_x16); + + return min_bpp_x16; +} + +static int compute_max_compressed_bpp_x16(struct intel_connector *connector, + int mode_clock, int mode_hdisplay, + int num_joined_pipes, + enum intel_output_format output_format, + int pipe_max_bpp, int max_link_bpp_x16) +{ + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); + int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; + int throughput_max_bpp_x16; + int joiner_max_bpp; + + dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); + joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, + mode_clock, + mode_hdisplay, + num_joined_pipes); + dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, + output_format, + pipe_max_bpp / 3); + dsc_max_bpp = min(dsc_sink_max_bpp, dsc_src_max_bpp); + dsc_max_bpp = min(dsc_max_bpp, joiner_max_bpp); + + max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); + + throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, + mode_clock); + if (throughput_max_bpp_x16 < max_link_bpp_x16) { + max_link_bpp_x16 = throughput_max_bpp_x16; + + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n", + connector->base.base.id, connector->base.name, + FXP_Q4_ARGS(max_link_bpp_x16)); + } + + max_link_bpp_x16 = align_max_compressed_bpp_x16(connector, output_format, + pipe_max_bpp, max_link_bpp_x16); + + return max_link_bpp_x16; +} + +bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, + int link_clock, int lane_count, + int mode_clock, int mode_hdisplay, + int num_joined_pipes, + enum intel_output_format output_format, + int pipe_bpp, unsigned long bw_overhead_flags) +{ + struct intel_dp *intel_dp = intel_attached_dp(connector); + int min_bpp_x16 = compute_min_compressed_bpp_x16(connector, output_format); + int max_bpp_x16 = compute_max_compressed_bpp_x16(connector, + mode_clock, mode_hdisplay, + num_joined_pipes, + output_format, + pipe_bpp, INT_MAX); + int dsc_slice_count = intel_dp_dsc_get_slice_count(connector, + mode_clock, + mode_hdisplay, + num_joined_pipes); + + if (min_bpp_x16 <= 0 || min_bpp_x16 > max_bpp_x16) + return false; + + return is_bw_sufficient_for_dsc_config(intel_dp, + link_clock, lane_count, + mode_clock, mode_hdisplay, + dsc_slice_count, min_bpp_x16, + bw_overhead_flags); +} + /* * Calculate the output link min, max bpp values in limits based on the pipe bpp * range, crtc_state and dsc mode. Return true on success. */ static bool -intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, - const struct intel_connector *connector, +intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector, const struct intel_crtc_state *crtc_state, bool dsc, struct link_config_limits *limits) { - struct intel_display *display = to_intel_display(intel_dp); + struct intel_display *display = to_intel_display(connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -2557,42 +2593,23 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp); } else { - int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; - int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; - int throughput_max_bpp_x16; - - dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp(); - dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state); - dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp); - limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp); - - dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); - dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, - crtc_state, - limits->pipe.max_bpp / 3); - dsc_max_bpp = dsc_sink_max_bpp ? - min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; - - max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp)); - - throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, crtc_state); - throughput_max_bpp_x16 = clamp(throughput_max_bpp_x16, - limits->link.min_bpp_x16, max_link_bpp_x16); - if (throughput_max_bpp_x16 < max_link_bpp_x16) { - max_link_bpp_x16 = throughput_max_bpp_x16; + limits->link.min_bpp_x16 = + compute_min_compressed_bpp_x16(connector, crtc_state->output_format); - drm_dbg_kms(display->drm, - "[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n", - crtc->base.base.id, crtc->base.name, - connector->base.base.id, connector->base.name, - FXP_Q4_ARGS(max_link_bpp_x16)); - } + max_link_bpp_x16 = + compute_max_compressed_bpp_x16(connector, + adjusted_mode->crtc_clock, + adjusted_mode->hdisplay, + intel_crtc_num_joined_pipes(crtc_state), + crtc_state->output_format, + limits->pipe.max_bpp, + max_link_bpp_x16); } limits->link.max_bpp_x16 = max_link_bpp_x16; drm_dbg_kms(display->drm, - "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n", + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n", encoder->base.base.id, encoder->base.name, crtc->base.base.id, crtc->base.name, adjusted_mode->crtc_clock, @@ -2600,21 +2617,44 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, limits->max_lane_count, limits->max_rate, limits->pipe.max_bpp, + FXP_Q4_ARGS(limits->link.min_bpp_x16), FXP_Q4_ARGS(limits->link.max_bpp_x16)); + if (limits->link.min_bpp_x16 <= 0 || + limits->link.min_bpp_x16 > limits->link.max_bpp_x16) + return false; + return true; } -static void -intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp, +static bool +intel_dp_dsc_compute_pipe_bpp_limits(struct intel_connector *connector, struct link_config_limits *limits) { - struct intel_display *display = to_intel_display(intel_dp); + struct intel_display *display = to_intel_display(connector); + const struct link_config_limits orig_limits = *limits; int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(); int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display); - limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); - limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3); + limits->pipe.min_bpp = max(limits->pipe.min_bpp, dsc_min_bpc * 3); + limits->pipe.min_bpp = align_min_sink_dsc_input_bpp(connector, limits->pipe.min_bpp); + + limits->pipe.max_bpp = min(limits->pipe.max_bpp, dsc_max_bpc * 3); + limits->pipe.max_bpp = align_max_sink_dsc_input_bpp(connector, limits->pipe.max_bpp); + + if (limits->pipe.min_bpp <= 0 || + limits->pipe.min_bpp > limits->pipe.max_bpp) { + drm_dbg_kms(display->drm, + "[CONNECTOR:%d:%s] Invalid DSC src/sink input BPP (src:%d-%d pipe:%d-%d sink-align:%d-%d)\n", + connector->base.base.id, connector->base.name, + dsc_min_bpc * 3, dsc_max_bpc * 3, + orig_limits.pipe.min_bpp, orig_limits.pipe.max_bpp, + limits->pipe.min_bpp, limits->pipe.max_bpp); + + return false; + } + + return true; } bool @@ -2654,8 +2694,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, respect_downstream_limits); } - if (dsc) - intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits); + if (dsc && !intel_dp_dsc_compute_pipe_bpp_limits(connector, limits)) + return false; if (is_mst || intel_dp->use_max_params) { /* @@ -2675,8 +2715,7 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, intel_dp_test_compute_config(intel_dp, crtc_state, limits); - return intel_dp_compute_config_link_bpp_limits(intel_dp, - connector, + return intel_dp_compute_config_link_bpp_limits(connector, crtc_state, dsc, limits); @@ -2686,11 +2725,13 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - int bpp = crtc_state->dsc.compression_enable ? - fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) : - crtc_state->pipe_bpp; + int link_bpp_x16 = crtc_state->dsc.compression_enable ? + crtc_state->dsc.compressed_bpp_x16 : + fxp_q4_from_int(crtc_state->pipe_bpp); - return intel_dp_link_required(adjusted_mode->crtc_clock, bpp); + return intel_dp_link_required(crtc_state->port_clock, crtc_state->lane_count, + adjusted_mode->crtc_clock, adjusted_mode->hdisplay, + link_bpp_x16, 0); } bool intel_dp_joiner_needs_dsc(struct intel_display *display, @@ -3259,8 +3300,8 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, if (crtc_state->dsc.compression_enable) link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; else - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, - crtc_state->pipe_bpp)); + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(crtc_state->output_format, + crtc_state->pipe_bpp); /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ hactive_sym_cycles = drm_dp_link_symbol_cycles(max_lane_count, @@ -3370,8 +3411,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, if (pipe_config->dsc.compression_enable) link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16; else - link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format, - pipe_config->pipe_bpp)); + link_bpp_x16 = intel_dp_output_format_link_bpp_x16(pipe_config->output_format, + pipe_config->pipe_bpp); if (intel_dp->mso_link_count) { int n = intel_dp->mso_link_count; @@ -4562,7 +4603,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector * This has to be called after intel_dp->edp_dpcd is filled, PSR checks * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] */ - intel_psr_init_dpcd(intel_dp); + intel_psr_init_dpcd(intel_dp, connector); intel_edp_set_sink_rates(intel_dp); intel_dp_set_max_sink_lane_count(intel_dp); @@ -5791,9 +5832,8 @@ bool intel_digital_port_connected_locked(struct intel_encoder *encoder) struct intel_digital_port *dig_port = enc_to_dig_port(encoder); bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port); bool is_connected = false; - intel_wakeref_t wakeref; - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { poll_timeout_us(is_connected = dig_port->connected(encoder), is_connected || is_glitch_free, 30, 4000, false); @@ -6049,10 +6089,19 @@ intel_dp_detect(struct drm_connector *_connector, if (status == connector_status_disconnected) { intel_dp_test_reset(intel_dp); + /* + * FIXME: Resetting these caps here cause + * state computation fail if the connector need to be + * modeset after sink disconnect. Move resetting them + * to where new sink is connected. + */ memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); + memset(connector->dp.panel_replay_caps.dpcd, 0, + sizeof(connector->dp.panel_replay_caps.dpcd)); intel_dp->psr.sink_panel_replay_support = false; - intel_dp->psr.sink_panel_replay_su_support = false; - intel_dp->psr.sink_panel_replay_dsc_support = + connector->dp.panel_replay_caps.support = false; + connector->dp.panel_replay_caps.su_support = false; + connector->dp.panel_replay_caps.dsc_support = INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED; intel_dp_mst_disconnect(intel_dp); @@ -6075,7 +6124,7 @@ intel_dp_detect(struct drm_connector *_connector, connector->base.epoch_counter++; if (!intel_dp_is_edp(intel_dp)) - intel_psr_init_dpcd(intel_dp); + intel_psr_init_dpcd(intel_dp, connector); intel_dp_detect_dsc_caps(intel_dp, connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 200a8b267f647..25bfbfd291b0a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -117,7 +117,11 @@ void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, bool intel_dp_source_supports_tps3(struct intel_display *display); bool intel_dp_source_supports_tps4(struct intel_display *display); -int intel_dp_link_required(int pixel_clock, int bpp); +int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay, + int dsc_slice_count, int bpp_x16, unsigned long flags); +int intel_dp_link_required(int link_clock, int lane_count, + int mode_clock, int mode_hdisplay, + int link_bpp_x16, unsigned long bw_overhead_flags); int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, int bw_overhead); int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, @@ -139,17 +143,12 @@ bool intel_digital_port_connected(struct intel_encoder *encoder); bool intel_digital_port_connected_locked(struct intel_encoder *encoder); int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, u8 dsc_max_bpc); -u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - int num_joined_pipes, - enum intel_output_format output_format, - u32 pipe_bpp, - u32 timeslots); -int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config); -int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, - const struct intel_crtc_state *pipe_config, - int bpc); +bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector, + int link_clock, int lane_count, + int mode_clock, int mode_hdisplay, + int num_joined_pipes, + enum intel_output_format output_format, + int pipe_bpp, unsigned long bw_overhead_flags); bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16); u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, @@ -193,7 +192,8 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); void intel_dp_wait_source_oui(struct intel_dp *intel_dp); -int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); +int intel_dp_output_format_link_bpp_x16(enum intel_output_format output_format, + int pipe_bpp); bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, struct drm_connector_state *conn_state, diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index 809799f63e326..b20ec3e589fad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -6,6 +6,7 @@ #include #include "intel_de.h" +#include "intel_display_jiffies.h" #include "intel_display_types.h" #include "intel_display_utils.h" #include "intel_dp.h" @@ -60,16 +61,17 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); const unsigned int timeout_ms = 10; u32 status; - int ret; + bool done; - ret = intel_de_wait_ms(display, ch_ctl, - DP_AUX_CH_CTL_SEND_BUSY, 0, - timeout_ms, &status); +#define C (((status = intel_de_read_notrace(display, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) + done = wait_event_timeout(display->gmbus.wait_queue, C, + msecs_to_jiffies_timeout(timeout_ms)); - if (ret == -ETIMEDOUT) + if (!done) drm_err(display->drm, "%s: did not complete or timeout within %ums (status 0x%08x)\n", intel_dp->aux.name, timeout_ms, status); +#undef C return status; } @@ -245,8 +247,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, i915_reg_t ch_ctl, ch_data[5]; u32 aux_clock_divider; enum intel_display_power_domain aux_domain; - intel_wakeref_t aux_wakeref; - intel_wakeref_t pps_wakeref = NULL; + struct ref_tracker *aux_wakeref; + struct ref_tracker *pps_wakeref = NULL; int i, ret, recv_bytes; int try, clock = 0; u32 status; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index aad5fe14962f9..54c585c59b900 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1195,7 +1195,9 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, intel_panel_preferred_fixed_mode(intel_dp->attached_connector); int mode_rate, max_rate; - mode_rate = intel_dp_link_required(fixed_mode->clock, 18); + mode_rate = intel_dp_link_required(link_rate, lane_count, + fixed_mode->clock, fixed_mode->hdisplay, + fxp_q4_from_int(18), 0); max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); if (mode_rate > max_rate) return false; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 4c0b943fe86f1..24f8e60df9ac1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -180,26 +180,16 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; unsigned long flags = DRM_DP_BW_OVERHEAD_MST; - int overhead; - flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0; flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0; flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0; - if (dsc_slice_count) - flags |= DRM_DP_BW_OVERHEAD_DSC; - - overhead = drm_dp_bw_overhead(crtc_state->lane_count, - adjusted_mode->hdisplay, - dsc_slice_count, - bpp_x16, - flags); - - /* - * TODO: clarify whether a minimum required by the fixed FEC overhead - * in the bspec audio programming sequence is required here. - */ - return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable)); + return intel_dp_link_bw_overhead(crtc_state->port_clock, + crtc_state->lane_count, + adjusted_mode->hdisplay, + dsc_slice_count, + bpp_x16, + flags); } static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state, @@ -344,8 +334,8 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, } link_bpp_x16 = dsc ? bpp_x16 : - fxp_q4_from_int(intel_dp_output_bpp(crtc_state->output_format, - fxp_q4_to_int(bpp_x16))); + intel_dp_output_format_link_bpp_x16(crtc_state->output_format, + fxp_q4_to_int(bpp_x16)); local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, false, dsc_slice_count, link_bpp_x16); @@ -473,57 +463,21 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp, { struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = to_intel_connector(conn_state->connector); - int num_bpc; - u8 dsc_bpc[3] = {}; - int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; - int min_compressed_bpp_x16, max_compressed_bpp_x16; - int bpp_step_x16; - - max_bpp = limits->pipe.max_bpp; - min_bpp = limits->pipe.min_bpp; - - num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, - dsc_bpc); - - drm_dbg_kms(display->drm, "DSC Source supported min bpp %d max bpp %d\n", - min_bpp, max_bpp); - - sink_min_bpp = min_array(dsc_bpc, num_bpc) * 3; - sink_max_bpp = max_array(dsc_bpc, num_bpc) * 3; - - drm_dbg_kms(display->drm, "DSC Sink supported min bpp %d max bpp %d\n", - sink_min_bpp, sink_max_bpp); - if (min_bpp < sink_min_bpp) - min_bpp = sink_min_bpp; - - if (max_bpp > sink_max_bpp) - max_bpp = sink_max_bpp; - - crtc_state->pipe_bpp = max_bpp; - - min_compressed_bpp_x16 = limits->link.min_bpp_x16; - max_compressed_bpp_x16 = limits->link.max_bpp_x16; + crtc_state->pipe_bpp = limits->pipe.max_bpp; drm_dbg_kms(display->drm, "DSC Sink supported compressed min bpp " FXP_Q4_FMT " compressed max bpp " FXP_Q4_FMT "\n", - FXP_Q4_ARGS(min_compressed_bpp_x16), FXP_Q4_ARGS(max_compressed_bpp_x16)); - - bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector); - - max_compressed_bpp_x16 = min(max_compressed_bpp_x16, fxp_q4_from_int(crtc_state->pipe_bpp) - bpp_step_x16); - - drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16)); - min_compressed_bpp_x16 = round_up(min_compressed_bpp_x16, bpp_step_x16); - max_compressed_bpp_x16 = round_down(max_compressed_bpp_x16, bpp_step_x16); + FXP_Q4_ARGS(limits->link.min_bpp_x16), FXP_Q4_ARGS(limits->link.max_bpp_x16)); crtc_state->lane_count = limits->max_lane_count; crtc_state->port_clock = limits->max_rate; return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state, - min_compressed_bpp_x16, - max_compressed_bpp_x16, - bpp_step_x16, true); + limits->link.min_bpp_x16, + limits->link.max_bpp_x16, + intel_dp_dsc_bpp_step_x16(connector), + true); } static int mode_hblank_period_ns(const struct drm_display_mode *mode) @@ -1468,10 +1422,10 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, const int min_bpp = 18; int max_dotclk = display->cdclk.max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; + unsigned long bw_overhead_flags = + DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK; int ret; bool dsc = false; - u16 dsc_max_compressed_bpp = 0; - u8 dsc_slice_count = 0; int target_clock = mode->clock; int num_joined_pipes; @@ -1499,7 +1453,10 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes); - mode_rate = intel_dp_link_required(mode->clock, min_bpp); + mode_rate = intel_dp_link_required(max_link_clock, max_lanes, + mode->clock, mode->hdisplay, + fxp_q4_from_int(min_bpp), + bw_overhead_flags); /* * TODO: @@ -1527,31 +1484,22 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector, return 0; } - if (intel_dp_has_dsc(connector)) { + if (intel_dp_has_dsc(connector) && drm_dp_sink_supports_fec(connector->dp.fec_capability)) { /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ int pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); - if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { - dsc_max_compressed_bpp = - intel_dp_dsc_get_max_compressed_bpp(display, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - num_joined_pipes, - INTEL_OUTPUT_FORMAT_RGB, - pipe_bpp, 64); - dsc_slice_count = - intel_dp_dsc_get_slice_count(connector, - target_clock, - mode->hdisplay, - num_joined_pipes); - } + if (!drm_dp_is_uhbr_rate(max_link_clock)) + bw_overhead_flags |= DRM_DP_BW_OVERHEAD_FEC; - dsc = dsc_max_compressed_bpp && dsc_slice_count; + dsc = intel_dp_mode_valid_with_dsc(connector, + max_link_clock, max_lanes, + target_clock, mode->hdisplay, + num_joined_pipes, + INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, + bw_overhead_flags); } if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) { diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 4f1db8493a2e8..a4f372c9e6fca 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -1212,27 +1212,6 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state, return 0; } -static int mtl_crtc_compute_clock(struct intel_atomic_state *state, - struct intel_crtc *crtc) -{ - struct intel_crtc_state *crtc_state = - intel_atomic_get_new_crtc_state(state, crtc); - struct intel_encoder *encoder = - intel_get_crtc_new_encoder(state, crtc_state); - int ret; - - ret = intel_cx0pll_calc_state(crtc_state, encoder); - if (ret) - return ret; - - /* TODO: Do the readback via intel_dpll_compute() */ - crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); - - crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); - - return 0; -} - static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1719,7 +1698,8 @@ static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = { }; static const struct intel_dpll_global_funcs mtl_dpll_funcs = { - .crtc_compute_clock = mtl_crtc_compute_clock, + .crtc_compute_clock = hsw_crtc_compute_clock, + .crtc_get_dpll = hsw_crtc_get_dpll, }; static const struct intel_dpll_global_funcs dg2_dpll_funcs = { diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 9c7cf03cf022e..9aa84a430f098 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -203,6 +203,22 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port) return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1; } +enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port) +{ + if (port >= PORT_TC1) + return icl_tc_port_to_pll_id(intel_port_to_tc(display, port)); + + switch (port) { + case PORT_A: + return DPLL_ID_ICL_DPLL0; + case PORT_B: + return DPLL_ID_ICL_DPLL1; + default: + MISSING_CASE(port); + return DPLL_ID_ICL_DPLL0; + } +} + static i915_reg_t intel_combo_pll_enable_reg(struct intel_display *display, struct intel_dpll *pll) @@ -531,7 +547,7 @@ static bool ibx_pch_dpll_get_hw_state(struct intel_display *display, { struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; const enum intel_dpll_id id = pll->info->id; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u32 val; wakeref = intel_display_power_get_if_enabled(display, @@ -752,7 +768,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display, { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; const enum intel_dpll_id id = pll->info->id; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u32 val; wakeref = intel_display_power_get_if_enabled(display, @@ -773,7 +789,7 @@ static bool hsw_ddi_spll_get_hw_state(struct intel_display *display, struct intel_dpll_hw_state *dpll_hw_state) { struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u32 val; wakeref = intel_display_power_get_if_enabled(display, @@ -1431,7 +1447,7 @@ static bool skl_ddi_pll_get_hw_state(struct intel_display *display, struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; u32 val; @@ -1469,7 +1485,7 @@ static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display, struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl; const struct skl_dpll_regs *regs = skl_dpll_regs; const enum intel_dpll_id id = pll->info->id; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u32 val; bool ret; @@ -2172,7 +2188,7 @@ static bool bxt_ddi_pll_get_hw_state(struct intel_display *display, { struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt; enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; enum dpio_phy phy; enum dpio_channel ch; u32 val; @@ -3490,6 +3506,37 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state, return ret; } +/* + * Get the PLL for either a port using a C10 PHY PLL, or for a port using a + * C20 PHY PLL in the cases of: + * - BMG port A/B + * - PTL port B eDP over TypeC PHY + */ +static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct icl_port_dpll *port_dpll = + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; + enum intel_dpll_id pll_id = mtl_port_to_pll_id(display, encoder->port); + + port_dpll->pll = intel_find_dpll(state, crtc, + &port_dpll->hw_state, + BIT(pll_id)); + if (!port_dpll->pll) + return -EINVAL; + + intel_reference_dpll(state, crtc, + port_dpll->pll, &port_dpll->hw_state); + + icl_update_active_dpll(state, crtc, encoder); + + return 0; +} + static int icl_compute_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) @@ -3551,7 +3598,7 @@ static bool mg_pll_get_hw_state(struct intel_display *display, struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret = false; u32 val; @@ -3618,7 +3665,7 @@ static bool dkl_pll_get_hw_state(struct intel_display *display, struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; enum tc_port tc_port = icl_pll_id_to_tc_port(id); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret = false; u32 val; @@ -3690,7 +3737,7 @@ static bool icl_pll_get_hw_state(struct intel_display *display, { struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; const enum intel_dpll_id id = pll->info->id; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret = false; u32 val; @@ -3753,9 +3800,9 @@ static bool combo_pll_get_hw_state(struct intel_display *display, return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg); } -static bool tbt_pll_get_hw_state(struct intel_display *display, - struct intel_dpll *pll, - struct intel_dpll_hw_state *dpll_hw_state) +static bool icl_tbt_pll_get_hw_state(struct intel_display *display, + struct intel_dpll *pll, + struct intel_dpll_hw_state *dpll_hw_state) { return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE); } @@ -3984,9 +4031,9 @@ static void combo_pll_enable(struct intel_display *display, /* DVFS post sequence would be here. See the comment above. */ } -static void tbt_pll_enable(struct intel_display *display, - struct intel_dpll *pll, - const struct intel_dpll_hw_state *dpll_hw_state) +static void icl_tbt_pll_enable(struct intel_display *display, + struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) { const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl; @@ -4069,8 +4116,8 @@ static void combo_pll_disable(struct intel_display *display, icl_pll_disable(display, pll, enable_reg); } -static void tbt_pll_disable(struct intel_display *display, - struct intel_dpll *pll) +static void icl_tbt_pll_disable(struct intel_display *display, + struct intel_dpll *pll) { icl_pll_disable(display, pll, TBT_PLL_ENABLE); } @@ -4142,10 +4189,10 @@ static const struct intel_dpll_funcs combo_pll_funcs = { .get_freq = icl_ddi_combo_pll_get_freq, }; -static const struct intel_dpll_funcs tbt_pll_funcs = { - .enable = tbt_pll_enable, - .disable = tbt_pll_disable, - .get_hw_state = tbt_pll_get_hw_state, +static const struct intel_dpll_funcs icl_tbt_pll_funcs = { + .enable = icl_tbt_pll_enable, + .disable = icl_tbt_pll_disable, + .get_hw_state = icl_tbt_pll_get_hw_state, .get_freq = icl_ddi_tbt_pll_get_freq, }; @@ -4159,7 +4206,7 @@ static const struct intel_dpll_funcs mg_pll_funcs = { static const struct dpll_info icl_plls[] = { { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, + { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, .is_alt_port_dpll = true, }, { .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, { .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, @@ -4207,7 +4254,7 @@ static const struct intel_dpll_funcs dkl_pll_funcs = { static const struct dpll_info tgl_plls[] = { { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, + { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, .is_alt_port_dpll = true, }, { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, @@ -4285,7 +4332,7 @@ static const struct intel_dpll_mgr adls_pll_mgr = { static const struct dpll_info adlp_plls[] = { { .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, { .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, - { .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, + { .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, .is_alt_port_dpll = true, }, { .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, { .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, @@ -4305,6 +4352,224 @@ static const struct intel_dpll_mgr adlp_pll_mgr = { .compare_hw_state = icl_compare_hw_state, }; +static struct intel_encoder *get_intel_encoder(struct intel_display *display, + const struct intel_dpll *pll) +{ + struct intel_encoder *encoder; + enum intel_dpll_id mtl_id; + + for_each_intel_encoder(display->drm, encoder) { + mtl_id = mtl_port_to_pll_id(display, encoder->port); + + if (mtl_id == pll->info->id) + return encoder; + } + + return NULL; +} + +static bool mtl_pll_get_hw_state(struct intel_display *display, + struct intel_dpll *pll, + struct intel_dpll_hw_state *dpll_hw_state) +{ + struct intel_encoder *encoder = get_intel_encoder(display, pll); + + if (!encoder) + return false; + + return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll); +} + +static int mtl_pll_get_freq(struct intel_display *display, + const struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) +{ + struct intel_encoder *encoder = get_intel_encoder(display, pll); + + if (drm_WARN_ON(display->drm, !encoder)) + return -EINVAL; + + return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll); +} + +static void mtl_pll_enable(struct intel_display *display, + struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) +{ + struct intel_encoder *encoder = get_intel_encoder(display, pll); + + if (drm_WARN_ON(display->drm, !encoder)) + return; + + intel_mtl_pll_enable(encoder, pll, dpll_hw_state); +} + +static void mtl_pll_disable(struct intel_display *display, + struct intel_dpll *pll) +{ + struct intel_encoder *encoder = get_intel_encoder(display, pll); + + if (drm_WARN_ON(display->drm, !encoder)) + return; + + intel_mtl_pll_disable(encoder); +} + +static const struct intel_dpll_funcs mtl_pll_funcs = { + .enable = mtl_pll_enable, + .disable = mtl_pll_disable, + .get_hw_state = mtl_pll_get_hw_state, + .get_freq = mtl_pll_get_freq, +}; + +static void mtl_tbt_pll_enable(struct intel_display *display, + struct intel_dpll *pll, + const struct intel_dpll_hw_state *hw_state) +{ +} + +static void mtl_tbt_pll_disable(struct intel_display *display, + struct intel_dpll *pll) +{ +} + +static int mtl_tbt_pll_get_freq(struct intel_display *display, + const struct intel_dpll *pll, + const struct intel_dpll_hw_state *dpll_hw_state) +{ + /* + * The PLL outputs multiple frequencies at the same time, selection is + * made at DDI clock mux level. + */ + drm_WARN_ON(display->drm, 1); + + return 0; +} + +static const struct intel_dpll_funcs mtl_tbt_pll_funcs = { + .enable = mtl_tbt_pll_enable, + .disable = mtl_tbt_pll_disable, + .get_hw_state = intel_mtl_tbt_pll_readout_hw_state, + .get_freq = mtl_tbt_pll_get_freq, +}; + +static const struct dpll_info mtl_plls[] = { + { .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, }, + { .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, }, + { .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL, + .is_alt_port_dpll = true, .always_on = true }, + { .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, }, + { .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, }, + { .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, }, + { .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, }, + {} +}; + +/* + * Compute the state for either a C10 PHY PLL, or in the case of the PTL port B, + * eDP on TypeC PHY case for a C20 PHY PLL. + */ +static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) +{ + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + struct icl_port_dpll *port_dpll = + &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; + int ret; + + ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state); + if (ret) + return ret; + + /* this is mainly for the fastset check */ + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); + + crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, + &port_dpll->hw_state.cx0pll); + + return 0; +} + +static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) +{ + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + struct icl_port_dpll *port_dpll; + int ret; + + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; + intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state); + + port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; + ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state); + if (ret) + return ret; + + /* this is mainly for the fastset check */ + if (old_crtc_state->intel_dpll && + old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL) + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); + else + icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY); + + crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, + &port_dpll->hw_state.cx0pll); + + return 0; +} + +static int mtl_compute_dplls(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) +{ + if (intel_encoder_is_tc(encoder)) + return mtl_compute_tc_phy_dplls(state, crtc, encoder); + else + return mtl_compute_non_tc_phy_dpll(state, crtc, encoder); +} + +static int mtl_get_dplls(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder) +{ + if (intel_encoder_is_tc(encoder)) + return icl_get_tc_phy_dplls(state, crtc, encoder); + else + return mtl_get_non_tc_phy_dpll(state, crtc, encoder); +} + +static void mtl_dump_hw_state(struct drm_printer *p, + const struct intel_dpll_hw_state *dpll_hw_state) +{ + intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll); +} + +static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a, + const struct intel_dpll_hw_state *_b) +{ + const struct intel_cx0pll_state *a = &_a->cx0pll; + const struct intel_cx0pll_state *b = &_b->cx0pll; + + return intel_cx0pll_compare_hw_state(a, b); +} + +static const struct intel_dpll_mgr mtl_pll_mgr = { + .dpll_info = mtl_plls, + .compute_dplls = mtl_compute_dplls, + .get_dplls = mtl_get_dplls, + .put_dplls = icl_put_dplls, + .update_active_dpll = icl_update_active_dpll, + .update_ref_clks = icl_update_dpll_ref_clks, + .dump_hw_state = mtl_dump_hw_state, + .compare_hw_state = mtl_compare_hw_state, +}; + /** * intel_dpll_init - Initialize DPLLs * @display: intel_display device @@ -4319,9 +4584,11 @@ void intel_dpll_init(struct intel_display *display) mutex_init(&display->dpll.lock); - if (DISPLAY_VER(display) >= 14 || display->platform.dg2) - /* No shared DPLLs on DG2; port PLLs are part of the PHY */ + if (DISPLAY_VER(display) >= 35 || display->platform.dg2) + /* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */ dpll_mgr = NULL; + else if (DISPLAY_VER(display) >= 14) + dpll_mgr = &mtl_pll_mgr; else if (display->platform.alderlake_p) dpll_mgr = &adlp_pll_mgr; else if (display->platform.alderlake_s) @@ -4675,11 +4942,18 @@ verify_single_dpll_state(struct intel_display *display, "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n", pll->info->name, pipe_mask, pll->state.pipe_mask); - INTEL_DISPLAY_STATE_WARN(display, - pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, - sizeof(dpll_hw_state)), - "%s: pll hw state mismatch\n", - pll->info->name); + if (INTEL_DISPLAY_STATE_WARN(display, + pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state, + sizeof(dpll_hw_state)), + "%s: pll hw state mismatch\n", + pll->info->name)) { + struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); + + drm_printf(&p, "PLL %s HW state:\n", pll->info->name); + intel_dpll_dump_hw_state(display, &p, &dpll_hw_state); + drm_printf(&p, "PLL %s SW state:\n", pll->info->name); + intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state); + } } static bool has_alt_port_dpll(const struct intel_dpll *old_pll, diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 6183da90b28d3..5b71c860515fc 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -28,7 +28,6 @@ #include #include "intel_display_power.h" -#include "intel_wakeref.h" #define for_each_dpll(__display, __pll, __i) \ for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \ @@ -42,6 +41,7 @@ struct intel_crtc_state; struct intel_dpll_funcs; struct intel_encoder; struct intel_shared_dpll; +struct ref_tracker; /** * enum intel_dpll_id - possible DPLL ids @@ -255,6 +255,11 @@ struct intel_c20pll_state { u16 mplla[10]; u16 mpllb[11]; }; + struct intel_c20pll_vdr_state { + u8 custom_width; + u8 serdes_rate; + u8 hdmi_rate; + } vdr; }; struct intel_cx0pll_state { @@ -262,6 +267,7 @@ struct intel_cx0pll_state { struct intel_c10pll_state c10; struct intel_c20pll_state c20; }; + int lane_count; bool ssc_enabled; bool use_c10; bool tbt_mode; @@ -390,7 +396,7 @@ struct intel_dpll { * @wakeref: In some platforms a device-level runtime pm reference may * need to be grabbed to disable DC states while this DPLL is enabled */ - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; }; #define SKL_DPLL0 0 @@ -444,6 +450,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display, const struct intel_dpll_hw_state *a, const struct intel_dpll_hw_state *b); enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); +enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port); bool intel_dpll_is_combophy(enum intel_dpll_id id); void intel_dpll_state_verify(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c similarity index 53% rename from drivers/gpu/drm/i915/soc/intel_dram.c rename to drivers/gpu/drm/i915/display/intel_dram.c index 3e588762709af..170de304fe96d 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/display/intel_dram.c @@ -8,11 +8,9 @@ #include #include -#include "../display/intel_display_core.h" /* FIXME */ - -#include "i915_drv.h" #include "i915_reg.h" -#include "i915_utils.h" +#include "intel_display_core.h" +#include "intel_display_utils.h" #include "intel_dram.h" #include "intel_mchbar_regs.h" #include "intel_pcode.h" @@ -57,17 +55,20 @@ const char *intel_dram_type_str(enum intel_dram_type type) #undef DRAM_TYPE_STR -static enum intel_dram_type pnv_dram_type(struct drm_i915_private *i915) +static enum intel_dram_type pnv_dram_type(struct intel_display *display) { - return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ? + struct intel_uncore *uncore = to_intel_uncore(display->drm); + + return intel_uncore_read(uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3 ? INTEL_DRAM_DDR3 : INTEL_DRAM_DDR2; } -static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) +static unsigned int pnv_mem_freq(struct intel_display *display) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 tmp; - tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); + tmp = intel_uncore_read(uncore, CLKCFG); switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: @@ -81,11 +82,12 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) return 0; } -static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) +static unsigned int ilk_mem_freq(struct intel_display *display) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); u16 ddrpll; - ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); + ddrpll = intel_uncore_read16(uncore, DDRMPLL1); switch (ddrpll & 0xff) { case 0xc: return 800000; @@ -96,19 +98,19 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) case 0x18: return 1600000; default: - drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", - ddrpll & 0xff); + drm_dbg_kms(display->drm, "unknown memory frequency 0x%02x\n", + ddrpll & 0xff); return 0; } } -static unsigned int chv_mem_freq(struct drm_i915_private *i915) +static unsigned int chv_mem_freq(struct intel_display *display) { u32 val; - vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_CCK)); - val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG); - vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_CCK)); + vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_CCK)); + val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_CCK, CCK_FUSE_REG); + vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_CCK)); switch ((val >> 2) & 0x7) { case 3: @@ -118,13 +120,13 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915) } } -static unsigned int vlv_mem_freq(struct drm_i915_private *i915) +static unsigned int vlv_mem_freq(struct intel_display *display) { u32 val; - vlv_iosf_sb_get(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); - val = vlv_iosf_sb_read(&i915->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); - vlv_iosf_sb_put(&i915->drm, BIT(VLV_IOSF_SB_PUNIT)); + vlv_iosf_sb_get(display->drm, BIT(VLV_IOSF_SB_PUNIT)); + val = vlv_iosf_sb_read(display->drm, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); + vlv_iosf_sb_put(display->drm, BIT(VLV_IOSF_SB_PUNIT)); switch ((val >> 6) & 3) { case 0: @@ -139,22 +141,23 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915) return 0; } -unsigned int intel_mem_freq(struct drm_i915_private *i915) +unsigned int intel_mem_freq(struct intel_display *display) { - if (IS_PINEVIEW(i915)) - return pnv_mem_freq(i915); - else if (GRAPHICS_VER(i915) == 5) - return ilk_mem_freq(i915); - else if (IS_CHERRYVIEW(i915)) - return chv_mem_freq(i915); - else if (IS_VALLEYVIEW(i915)) - return vlv_mem_freq(i915); + if (display->platform.pineview) + return pnv_mem_freq(display); + else if (DISPLAY_VER(display) == 5) + return ilk_mem_freq(display); + else if (display->platform.cherryview) + return chv_mem_freq(display); + else if (display->platform.valleyview) + return vlv_mem_freq(display); else return 0; } -static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) +static unsigned int i9xx_fsb_freq(struct intel_display *display) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 fsb; /* @@ -165,9 +168,9 @@ static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) * don't know which registers have that information, * and all the relevant docs have gone to bit heaven :( */ - fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; + fsb = intel_uncore_read(uncore, CLKCFG) & CLKCFG_FSB_MASK; - if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { + if (display->platform.pineview || display->platform.mobile) { switch (fsb) { case CLKCFG_FSB_400: return 400000; @@ -208,11 +211,12 @@ static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) } } -static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) +static unsigned int ilk_fsb_freq(struct intel_display *display) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); u16 fsb; - fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff; + fsb = intel_uncore_read16(uncore, CSIPLL0) & 0x3ff; switch (fsb) { case 0x00c: @@ -230,33 +234,33 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) case 0x018: return 6400000; default: - drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); + drm_dbg_kms(display->drm, "unknown fsb frequency 0x%04x\n", fsb); return 0; } } -unsigned int intel_fsb_freq(struct drm_i915_private *i915) +unsigned int intel_fsb_freq(struct intel_display *display) { - if (GRAPHICS_VER(i915) == 5) - return ilk_fsb_freq(i915); - else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4) - return i9xx_fsb_freq(i915); + if (DISPLAY_VER(display) == 5) + return ilk_fsb_freq(display); + else if (IS_DISPLAY_VER(display, 3, 4)) + return i9xx_fsb_freq(display); else return 0; } -static int i915_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) +static int i915_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { - dram_info->fsb_freq = intel_fsb_freq(i915); + dram_info->fsb_freq = intel_fsb_freq(display); if (dram_info->fsb_freq) - drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq); + drm_dbg_kms(display->drm, "FSB frequency: %d kHz\n", dram_info->fsb_freq); - dram_info->mem_freq = intel_mem_freq(i915); + dram_info->mem_freq = intel_mem_freq(display); if (dram_info->mem_freq) - drm_dbg(&i915->drm, "DDR speed: %d kHz\n", dram_info->mem_freq); + drm_dbg_kms(display->drm, "DDR speed: %d kHz\n", dram_info->mem_freq); - if (IS_PINEVIEW(i915)) - dram_info->type = pnv_dram_type(i915); + if (display->platform.pineview) + dram_info->type = pnv_dram_type(display); return 0; } @@ -267,69 +271,121 @@ static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) } /* Returns total Gb for the whole DIMM */ -static int skl_get_dimm_size(u16 val) +static int skl_get_dimm_s_size(u32 val) +{ + return REG_FIELD_GET(SKL_DIMM_S_SIZE_MASK, val) * 8; +} + +static int skl_get_dimm_l_size(u32 val) { - return (val & SKL_DRAM_SIZE_MASK) * 8; + return REG_FIELD_GET(SKL_DIMM_L_SIZE_MASK, val) * 8; } -static int skl_get_dimm_width(u16 val) +static int skl_get_dimm_s_width(u32 val) { - if (skl_get_dimm_size(val) == 0) + if (skl_get_dimm_s_size(val) == 0) return 0; - switch (val & SKL_DRAM_WIDTH_MASK) { - case SKL_DRAM_WIDTH_X8: - case SKL_DRAM_WIDTH_X16: - case SKL_DRAM_WIDTH_X32: - val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT; - return 8 << val; + switch (val & SKL_DIMM_S_WIDTH_MASK) { + case SKL_DIMM_S_WIDTH_X8: + case SKL_DIMM_S_WIDTH_X16: + case SKL_DIMM_S_WIDTH_X32: + return 8 << REG_FIELD_GET(SKL_DIMM_S_WIDTH_MASK, val); default: MISSING_CASE(val); return 0; } } -static int skl_get_dimm_ranks(u16 val) +static int skl_get_dimm_l_width(u32 val) { - if (skl_get_dimm_size(val) == 0) + if (skl_get_dimm_l_size(val) == 0) return 0; - val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT; + switch (val & SKL_DIMM_L_WIDTH_MASK) { + case SKL_DIMM_L_WIDTH_X8: + case SKL_DIMM_L_WIDTH_X16: + case SKL_DIMM_L_WIDTH_X32: + return 8 << REG_FIELD_GET(SKL_DIMM_L_WIDTH_MASK, val); + default: + MISSING_CASE(val); + return 0; + } +} + +static int skl_get_dimm_s_ranks(u32 val) +{ + if (skl_get_dimm_s_size(val) == 0) + return 0; + + return REG_FIELD_GET(SKL_DIMM_S_RANK_MASK, val) + 1; +} + +static int skl_get_dimm_l_ranks(u32 val) +{ + if (skl_get_dimm_l_size(val) == 0) + return 0; - return val + 1; + return REG_FIELD_GET(SKL_DIMM_L_RANK_MASK, val) + 1; } /* Returns total Gb for the whole DIMM */ -static int icl_get_dimm_size(u16 val) +static int icl_get_dimm_s_size(u32 val) { - return (val & ICL_DRAM_SIZE_MASK) * 8 / 2; + return REG_FIELD_GET(ICL_DIMM_S_SIZE_MASK, val) * 8 / 2; } -static int icl_get_dimm_width(u16 val) +static int icl_get_dimm_l_size(u32 val) { - if (icl_get_dimm_size(val) == 0) + return REG_FIELD_GET(ICL_DIMM_L_SIZE_MASK, val) * 8 / 2; +} + +static int icl_get_dimm_s_width(u32 val) +{ + if (icl_get_dimm_s_size(val) == 0) return 0; - switch (val & ICL_DRAM_WIDTH_MASK) { - case ICL_DRAM_WIDTH_X8: - case ICL_DRAM_WIDTH_X16: - case ICL_DRAM_WIDTH_X32: - val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT; - return 8 << val; + switch (val & ICL_DIMM_S_WIDTH_MASK) { + case ICL_DIMM_S_WIDTH_X8: + case ICL_DIMM_S_WIDTH_X16: + case ICL_DIMM_S_WIDTH_X32: + return 8 << REG_FIELD_GET(ICL_DIMM_S_WIDTH_MASK, val); default: MISSING_CASE(val); return 0; } } -static int icl_get_dimm_ranks(u16 val) +static int icl_get_dimm_l_width(u32 val) { - if (icl_get_dimm_size(val) == 0) + if (icl_get_dimm_l_size(val) == 0) return 0; - val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT; + switch (val & ICL_DIMM_L_WIDTH_MASK) { + case ICL_DIMM_L_WIDTH_X8: + case ICL_DIMM_L_WIDTH_X16: + case ICL_DIMM_L_WIDTH_X32: + return 8 << REG_FIELD_GET(ICL_DIMM_L_WIDTH_MASK, val); + default: + MISSING_CASE(val); + return 0; + } +} + +static int icl_get_dimm_s_ranks(u32 val) +{ + if (icl_get_dimm_s_size(val) == 0) + return 0; + + return REG_FIELD_GET(ICL_DIMM_S_RANK_MASK, val) + 1; +} + +static int icl_get_dimm_l_ranks(u32 val) +{ + if (icl_get_dimm_l_size(val) == 0) + return 0; - return val + 1; + return REG_FIELD_GET(ICL_DIMM_L_RANK_MASK, val) + 1; } static bool @@ -340,38 +396,62 @@ skl_is_16gb_dimm(const struct dram_dimm_info *dimm) } static void -skl_dram_get_dimm_info(struct drm_i915_private *i915, - struct dram_dimm_info *dimm, - int channel, char dimm_name, u16 val) -{ - if (GRAPHICS_VER(i915) >= 11) { - dimm->size = icl_get_dimm_size(val); - dimm->width = icl_get_dimm_width(val); - dimm->ranks = icl_get_dimm_ranks(val); - } else { - dimm->size = skl_get_dimm_size(val); - dimm->width = skl_get_dimm_width(val); - dimm->ranks = skl_get_dimm_ranks(val); - } - - drm_dbg_kms(&i915->drm, +skl_dram_print_dimm_info(struct intel_display *display, + struct dram_dimm_info *dimm, + int channel, char dimm_name) +{ + drm_dbg_kms(display->drm, "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb+ DIMMs: %s\n", channel, dimm_name, dimm->size, dimm->width, dimm->ranks, str_yes_no(skl_is_16gb_dimm(dimm))); } +static void +skl_dram_get_dimm_l_info(struct intel_display *display, + struct dram_dimm_info *dimm, + int channel, u32 val) +{ + if (DISPLAY_VER(display) >= 11) { + dimm->size = icl_get_dimm_l_size(val); + dimm->width = icl_get_dimm_l_width(val); + dimm->ranks = icl_get_dimm_l_ranks(val); + } else { + dimm->size = skl_get_dimm_l_size(val); + dimm->width = skl_get_dimm_l_width(val); + dimm->ranks = skl_get_dimm_l_ranks(val); + } + + skl_dram_print_dimm_info(display, dimm, channel, 'L'); +} + +static void +skl_dram_get_dimm_s_info(struct intel_display *display, + struct dram_dimm_info *dimm, + int channel, u32 val) +{ + if (DISPLAY_VER(display) >= 11) { + dimm->size = icl_get_dimm_s_size(val); + dimm->width = icl_get_dimm_s_width(val); + dimm->ranks = icl_get_dimm_s_ranks(val); + } else { + dimm->size = skl_get_dimm_s_size(val); + dimm->width = skl_get_dimm_s_width(val); + dimm->ranks = skl_get_dimm_s_ranks(val); + } + + skl_dram_print_dimm_info(display, dimm, channel, 'S'); +} + static int -skl_dram_get_channel_info(struct drm_i915_private *i915, +skl_dram_get_channel_info(struct intel_display *display, struct dram_channel_info *ch, int channel, u32 val) { - skl_dram_get_dimm_info(i915, &ch->dimm_l, - channel, 'L', val & 0xffff); - skl_dram_get_dimm_info(i915, &ch->dimm_s, - channel, 'S', val >> 16); + skl_dram_get_dimm_l_info(display, &ch->dimm_l, channel, val); + skl_dram_get_dimm_s_info(display, &ch->dimm_s, channel, val); if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) { - drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel); + drm_dbg_kms(display->drm, "CH%u not populated\n", channel); return -EINVAL; } @@ -385,7 +465,7 @@ skl_dram_get_channel_info(struct drm_i915_private *i915, ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) || skl_is_16gb_dimm(&ch->dimm_s); - drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n", + drm_dbg_kms(display->drm, "CH%u ranks: %u, 16Gb+ DIMMs: %s\n", channel, ch->ranks, str_yes_no(ch->is_16gb_dimm)); return 0; @@ -401,8 +481,9 @@ intel_is_dram_symmetric(const struct dram_channel_info *ch0, } static int -skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram_info) +skl_dram_get_channels_info(struct intel_display *display, struct dram_info *dram_info) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); struct dram_channel_info ch0 = {}, ch1 = {}; u32 val; int ret; @@ -410,25 +491,23 @@ skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram /* Assume 16Gb+ DIMMs are present until proven otherwise */ dram_info->has_16gb_dimms = true; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); - ret = skl_dram_get_channel_info(i915, &ch0, 0, val); + val = intel_uncore_read(uncore, SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN); + ret = skl_dram_get_channel_info(display, &ch0, 0, val); if (ret == 0) dram_info->num_channels++; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); - ret = skl_dram_get_channel_info(i915, &ch1, 1, val); + val = intel_uncore_read(uncore, SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN); + ret = skl_dram_get_channel_info(display, &ch1, 1, val); if (ret == 0) dram_info->num_channels++; if (dram_info->num_channels == 0) { - drm_info(&i915->drm, "Number of memory channels is zero\n"); + drm_info(display->drm, "Number of memory channels is zero\n"); return -EINVAL; } if (ch0.ranks == 0 && ch1.ranks == 0) { - drm_info(&i915->drm, "couldn't get memory rank information\n"); + drm_info(display->drm, "couldn't get memory rank information\n"); return -EINVAL; } @@ -436,22 +515,22 @@ skl_dram_get_channels_info(struct drm_i915_private *i915, struct dram_info *dram dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); - drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n", + drm_dbg_kms(display->drm, "Memory configuration is symmetric? %s\n", str_yes_no(dram_info->symmetric_memory)); - drm_dbg_kms(&i915->drm, "16Gb+ DIMMs: %s\n", + drm_dbg_kms(display->drm, "16Gb+ DIMMs: %s\n", str_yes_no(dram_info->has_16gb_dimms)); return 0; } static enum intel_dram_type -skl_get_dram_type(struct drm_i915_private *i915) +skl_get_dram_type(struct intel_display *display) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val; - val = intel_uncore_read(&i915->uncore, - SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); + val = intel_uncore_read(uncore, SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN); switch (val & SKL_DRAM_DDR_TYPE_MASK) { case SKL_DRAM_DDR_TYPE_DDR3: @@ -469,13 +548,13 @@ skl_get_dram_type(struct drm_i915_private *i915) } static int -skl_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) +skl_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { int ret; - dram_info->type = skl_get_dram_type(i915); + dram_info->type = skl_get_dram_type(display); - ret = skl_dram_get_channels_info(i915, dram_info); + ret = skl_dram_get_channels_info(display, dram_info); if (ret) return ret; @@ -560,8 +639,9 @@ static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val) dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm); } -static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) +static int bxt_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { + struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val; u8 valid_ranks = 0; int i; @@ -573,7 +653,7 @@ static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dr struct dram_dimm_info dimm; enum intel_dram_type type; - val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i)); + val = intel_uncore_read(uncore, BXT_D_CR_DRP0_DUNIT(i)); if (val == 0xFFFFFFFF) continue; @@ -582,11 +662,11 @@ static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dr bxt_get_dimm_info(&dimm, val); type = bxt_get_dimm_type(val); - drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN && + drm_WARN_ON(display->drm, type != INTEL_DRAM_UNKNOWN && dram_info->type != INTEL_DRAM_UNKNOWN && dram_info->type != type); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "CH%u DIMM size: %u Gb, width: X%u, ranks: %u\n", i - BXT_D_CR_DRP0_DUNIT_START, dimm.size, dimm.width, dimm.ranks); @@ -599,25 +679,25 @@ static int bxt_get_dram_info(struct drm_i915_private *i915, struct dram_info *dr } if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) { - drm_info(&i915->drm, "couldn't get memory information\n"); + drm_info(display->drm, "couldn't get memory information\n"); return -EINVAL; } return 0; } -static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, +static int icl_pcode_read_mem_global_info(struct intel_display *display, struct dram_info *dram_info) { u32 val = 0; int ret; - ret = intel_pcode_read(&dev_priv->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | + ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL); if (ret) return ret; - if (GRAPHICS_VER(dev_priv) == 12) { + if (DISPLAY_VER(display) >= 12) { switch (val & 0xf) { case 0: dram_info->type = INTEL_DRAM_DDR4; @@ -668,26 +748,26 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, return 0; } -static int gen11_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) +static int gen11_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { int ret; - ret = skl_dram_get_channels_info(i915, dram_info); + ret = skl_dram_get_channels_info(display, dram_info); if (ret) return ret; - return icl_pcode_read_mem_global_info(i915, dram_info); + return icl_pcode_read_mem_global_info(display, dram_info); } -static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) +static int gen12_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { - return icl_pcode_read_mem_global_info(i915, dram_info); + return icl_pcode_read_mem_global_info(display, dram_info); } -static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info) +static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { - struct intel_display *display = i915->display; - u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); + struct intel_uncore *uncore = to_intel_uncore(display->drm); + u32 val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_GLOBAL); switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { case 0: @@ -709,11 +789,11 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info dram_info->type = INTEL_DRAM_LPDDR3; break; case 8: - drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); + drm_WARN_ON(display->drm, !display->platform.dgfx); dram_info->type = INTEL_DRAM_GDDR; break; case 9: - drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); + drm_WARN_ON(display->drm, !display->platform.dgfx); dram_info->type = INTEL_DRAM_GDDR_ECC; break; default: @@ -731,41 +811,40 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info return 0; } -int intel_dram_detect(struct drm_i915_private *i915) +int intel_dram_detect(struct intel_display *display) { - struct intel_display *display = i915->display; struct dram_info *dram_info; int ret; - if (IS_DG2(i915) || !intel_display_device_present(display)) + if (display->platform.dg2 || !HAS_DISPLAY(display)) return 0; - dram_info = drmm_kzalloc(&i915->drm, sizeof(*dram_info), GFP_KERNEL); + dram_info = drmm_kzalloc(display->drm, sizeof(*dram_info), GFP_KERNEL); if (!dram_info) return -ENOMEM; - i915->dram_info = dram_info; + display->dram.info = dram_info; if (DISPLAY_VER(display) >= 14) - ret = xelpdp_get_dram_info(i915, dram_info); - else if (GRAPHICS_VER(i915) >= 12) - ret = gen12_get_dram_info(i915, dram_info); - else if (GRAPHICS_VER(i915) >= 11) - ret = gen11_get_dram_info(i915, dram_info); - else if (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) - ret = bxt_get_dram_info(i915, dram_info); - else if (GRAPHICS_VER(i915) >= 9) - ret = skl_get_dram_info(i915, dram_info); + ret = xelpdp_get_dram_info(display, dram_info); + else if (DISPLAY_VER(display) >= 12) + ret = gen12_get_dram_info(display, dram_info); + else if (DISPLAY_VER(display) >= 11) + ret = gen11_get_dram_info(display, dram_info); + else if (display->platform.broxton || display->platform.geminilake) + ret = bxt_get_dram_info(display, dram_info); + else if (DISPLAY_VER(display) >= 9) + ret = skl_get_dram_info(display, dram_info); else - ret = i915_get_dram_info(i915, dram_info); + ret = i915_get_dram_info(display, dram_info); - drm_dbg_kms(&i915->drm, "DRAM type: %s\n", + drm_dbg_kms(display->drm, "DRAM type: %s\n", intel_dram_type_str(dram_info->type)); - drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels); + drm_dbg_kms(display->drm, "DRAM channels: %u\n", dram_info->num_channels); - drm_dbg_kms(&i915->drm, "Num QGV points %u\n", dram_info->num_qgv_points); - drm_dbg_kms(&i915->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points); + drm_dbg_kms(display->drm, "Num QGV points %u\n", dram_info->num_qgv_points); + drm_dbg_kms(display->drm, "Num PSF GV points %u\n", dram_info->num_psf_gv_points); /* TODO: Do we want to abort probe on dram detection failures? */ if (ret) @@ -779,45 +858,7 @@ int intel_dram_detect(struct drm_i915_private *i915) * checks, and prefer not dereferencing on platforms that shouldn't look at dram * info, to catch accidental and incorrect dram info checks. */ -const struct dram_info *intel_dram_info(struct drm_device *drm) +const struct dram_info *intel_dram_info(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(drm); - - return i915->dram_info; -} - -static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap) -{ - static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 }; - static const u8 sets[4] = { 1, 1, 2, 2 }; - - return EDRAM_NUM_BANKS(cap) * - ways[EDRAM_WAYS_IDX(cap)] * - sets[EDRAM_SETS_IDX(cap)]; -} - -void intel_dram_edram_detect(struct drm_i915_private *i915) -{ - u32 edram_cap = 0; - - if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9)) - return; - - edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP); - - /* NB: We can't write IDICR yet because we don't have gt funcs set up */ - - if (!(edram_cap & EDRAM_ENABLED)) - return; - - /* - * The needed capability bits for size calculation are not there with - * pre gen9 so return 128MB always. - */ - if (GRAPHICS_VER(i915) < 9) - i915->edram_size_mb = 128; - else - i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap); - - drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb); + return display->dram.info; } diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/display/intel_dram.h similarity index 68% rename from drivers/gpu/drm/i915/soc/intel_dram.h rename to drivers/gpu/drm/i915/display/intel_dram.h index 8475ee379daab..5800b7b4e6146 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.h +++ b/drivers/gpu/drm/i915/display/intel_dram.h @@ -8,8 +8,7 @@ #include -struct drm_i915_private; -struct drm_device; +struct intel_display; struct dram_info { enum intel_dram_type { @@ -35,11 +34,10 @@ struct dram_info { bool has_16gb_dimms; }; -void intel_dram_edram_detect(struct drm_i915_private *i915); -int intel_dram_detect(struct drm_i915_private *i915); -unsigned int intel_fsb_freq(struct drm_i915_private *i915); -unsigned int intel_mem_freq(struct drm_i915_private *i915); -const struct dram_info *intel_dram_info(struct drm_device *drm); +int intel_dram_detect(struct intel_display *display); +unsigned int intel_fsb_freq(struct intel_display *display); +unsigned int intel_mem_freq(struct intel_display *display); +const struct dram_info *intel_dram_info(struct intel_display *display); const char *intel_dram_type_str(enum intel_dram_type type); #endif /* __INTEL_DRAM_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 4ad4efbf9253b..91060e2a57624 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -26,7 +26,7 @@ struct intel_dsb { enum intel_dsb_id id; - struct intel_dsb_buffer dsb_buf; + struct intel_dsb_buffer *dsb_buf; struct intel_crtc *crtc; /* @@ -211,10 +211,10 @@ static void intel_dsb_dump(struct intel_dsb *dsb) for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4) drm_dbg_kms(display->drm, " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", i * 4, - intel_dsb_buffer_read(&dsb->dsb_buf, i), - intel_dsb_buffer_read(&dsb->dsb_buf, i + 1), - intel_dsb_buffer_read(&dsb->dsb_buf, i + 2), - intel_dsb_buffer_read(&dsb->dsb_buf, i + 3)); + intel_dsb_buffer_read(dsb->dsb_buf, i), + intel_dsb_buffer_read(dsb->dsb_buf, i + 1), + intel_dsb_buffer_read(dsb->dsb_buf, i + 2), + intel_dsb_buffer_read(dsb->dsb_buf, i + 3)); drm_dbg_kms(display->drm, "}\n"); } @@ -231,12 +231,12 @@ unsigned int intel_dsb_size(struct intel_dsb *dsb) unsigned int intel_dsb_head(struct intel_dsb *dsb) { - return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); + return intel_dsb_buffer_ggtt_offset(dsb->dsb_buf); } static unsigned int intel_dsb_tail(struct intel_dsb *dsb) { - return intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf) + intel_dsb_size(dsb); + return intel_dsb_buffer_ggtt_offset(dsb->dsb_buf) + intel_dsb_size(dsb); } static void intel_dsb_ins_align(struct intel_dsb *dsb) @@ -263,8 +263,8 @@ static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) dsb->ins[0] = ldw; dsb->ins[1] = udw; - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]); - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]); + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, dsb->ins[0]); + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, dsb->ins[1]); } static bool intel_dsb_prev_ins_is_write(struct intel_dsb *dsb, @@ -335,13 +335,13 @@ void intel_dsb_reg_write_indexed(struct intel_dsb *dsb, /* Update the count */ dsb->ins[0]++; - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->ins_start_offset + 0, + intel_dsb_buffer_write(dsb->dsb_buf, dsb->ins_start_offset + 0, dsb->ins[0]); - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos++, val); + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos++, val); /* if number of data words is odd, then the last dword should be 0.*/ if (dsb->free_pos & 0x1) - intel_dsb_buffer_write(&dsb->dsb_buf, dsb->free_pos, 0); + intel_dsb_buffer_write(dsb->dsb_buf, dsb->free_pos, 0); } void intel_dsb_reg_write(struct intel_dsb *dsb, @@ -521,7 +521,7 @@ static void intel_dsb_align_tail(struct intel_dsb *dsb) aligned_tail = ALIGN(tail, CACHELINE_BYTES); if (aligned_tail > tail) - intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, + intel_dsb_buffer_memset(dsb->dsb_buf, dsb->free_pos, 0, aligned_tail - tail); dsb->free_pos = aligned_tail / 4; @@ -541,7 +541,7 @@ static void intel_dsb_gosub_align(struct intel_dsb *dsb) * "Ensure GOSUB is not placed in cacheline QW slot 6 or 7 (numbered 0-7)" */ if (aligned_tail - tail <= 2 * 8) - intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0, + intel_dsb_buffer_memset(dsb->dsb_buf, dsb->free_pos, 0, aligned_tail - tail); dsb->free_pos = aligned_tail / 4; @@ -606,14 +606,14 @@ void intel_dsb_gosub_finish(struct intel_dsb *dsb) */ intel_dsb_noop(dsb, 8); - intel_dsb_buffer_flush_map(&dsb->dsb_buf); + intel_dsb_buffer_flush_map(dsb->dsb_buf); } void intel_dsb_finish(struct intel_dsb *dsb) { intel_dsb_align_tail(dsb); - intel_dsb_buffer_flush_map(&dsb->dsb_buf); + intel_dsb_buffer_flush_map(dsb->dsb_buf); } static u32 dsb_error_int_status(struct intel_display *display) @@ -704,7 +704,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, if (crtc_state->has_psr) intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0); - if (pre_commit_is_vrr_active(state, crtc)) { + if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance.enable) { + int vblank_delay = crtc_state->set_context_latency; + int vmin_vblank_start, vmax_vblank_start; + + vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state); + + if (vmin_vblank_start >= 0) { + end = vmin_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + } + + vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state); + + if (vmax_vblank_start >= 0) { + end = vmax_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + } + + vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state); + end = vmin_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + + vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state); + end = vmax_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + } else if (pre_commit_is_vrr_active(state, crtc)) { int vblank_delay = crtc_state->set_context_latency; end = intel_vrr_vmin_vblank_start(crtc_state); @@ -888,7 +917,7 @@ void intel_dsb_wait(struct intel_dsb *dsb) !is_busy, 100, 1000, false); if (ret) { - u32 offset = intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf); + u32 offset = intel_dsb_buffer_ggtt_offset(dsb->dsb_buf); intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), DSB_ENABLE | DSB_HALT); @@ -934,6 +963,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, unsigned int max_cmds) { struct intel_display *display = to_intel_display(state); + struct intel_dsb_buffer *dsb_buf; struct ref_tracker *wakeref; struct intel_dsb *dsb; unsigned int size; @@ -953,9 +983,12 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, /* ~1 qword per instruction, full cachelines */ size = ALIGN(max_cmds * 8, CACHELINE_BYTES); - if (!intel_dsb_buffer_create(crtc, &dsb->dsb_buf, size)) + dsb_buf = intel_dsb_buffer_create(display->drm, size); + if (IS_ERR(dsb_buf)) goto out_put_rpm; + dsb->dsb_buf = dsb_buf; + intel_display_rpm_put(display, wakeref); dsb->id = dsb_id; @@ -988,7 +1021,7 @@ struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state, */ void intel_dsb_cleanup(struct intel_dsb *dsb) { - intel_dsb_buffer_cleanup(&dsb->dsb_buf); + intel_dsb_buffer_cleanup(dsb->dsb_buf); kfree(dsb); } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 2f31f2c1d0c54..386a5a942572e 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -1,5 +1,5 @@ -/* SPDX-License-Identifier: MIT - * +/* SPDX-License-Identifier: MIT */ +/* * Copyright © 2019 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/display/intel_dsb_buffer.c b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c index c77d48bda26ac..50faf3869b6c0 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_buffer.c +++ b/drivers/gpu/drm/i915/display/intel_dsb_buffer.c @@ -7,9 +7,14 @@ #include "gem/i915_gem_lmem.h" #include "i915_drv.h" #include "i915_vma.h" -#include "intel_display_types.h" #include "intel_dsb_buffer.h" +struct intel_dsb_buffer { + u32 *cmd_buf; + struct i915_vma *vma; + size_t buf_size; +}; + u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf) { return i915_ggtt_offset(dsb_buf->vma); @@ -32,48 +37,66 @@ void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, memset(&dsb_buf->cmd_buf[idx], val, size); } -bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size) +struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(drm); + struct intel_dsb_buffer *dsb_buf; struct drm_i915_gem_object *obj; struct i915_vma *vma; u32 *buf; + int ret; + + dsb_buf = kzalloc(sizeof(*dsb_buf), GFP_KERNEL); + if (!dsb_buf) + return ERR_PTR(-ENOMEM); if (HAS_LMEM(i915)) { obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size), I915_BO_ALLOC_CONTIGUOUS); - if (IS_ERR(obj)) - return false; + if (IS_ERR(obj)) { + ret = PTR_ERR(obj); + goto err; + } } else { obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); - if (IS_ERR(obj)) - return false; + if (IS_ERR(obj)) { + ret = PTR_ERR(obj); + goto err; + } i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); } vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { + ret = PTR_ERR(vma); i915_gem_object_put(obj); - return false; + goto err; } buf = i915_gem_object_pin_map_unlocked(vma->obj, I915_MAP_WC); if (IS_ERR(buf)) { + ret = PTR_ERR(buf); i915_vma_unpin_and_release(&vma, I915_VMA_RELEASE_MAP); - return false; + goto err; } dsb_buf->vma = vma; dsb_buf->cmd_buf = buf; dsb_buf->buf_size = size; - return true; + return dsb_buf; + +err: + kfree(dsb_buf); + + return ERR_PTR(ret); } void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf) { i915_vma_unpin_and_release(&dsb_buf->vma, I915_VMA_RELEASE_MAP); + kfree(dsb_buf); } void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf) diff --git a/drivers/gpu/drm/i915/display/intel_dsb_buffer.h b/drivers/gpu/drm/i915/display/intel_dsb_buffer.h index 425acd3939059..f4577d1f25cd9 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb_buffer.h +++ b/drivers/gpu/drm/i915/display/intel_dsb_buffer.h @@ -1,5 +1,5 @@ -/* SPDX-License-Identifier: MIT - * +/* SPDX-License-Identifier: MIT */ +/* * Copyright © 2023 Intel Corporation */ @@ -8,21 +8,14 @@ #include -struct intel_crtc; -struct i915_vma; - -struct intel_dsb_buffer { - u32 *cmd_buf; - struct i915_vma *vma; - size_t buf_size; -}; +struct drm_device; +struct intel_dsb_buffer; u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf); void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val); u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx); void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size); -bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, - size_t size); +struct intel_dsb_buffer *intel_dsb_buffer_create(struct drm_device *drm, size_t size); void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf); void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf); diff --git a/drivers/gpu/drm/i915/display/intel_dsi.h b/drivers/gpu/drm/i915/display/intel_dsi.h index 89c7166a3860b..489d26ffd2354 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi.h +++ b/drivers/gpu/drm/i915/display/intel_dsi.h @@ -29,6 +29,9 @@ #include "intel_display_types.h" +struct intel_dsi_host; +struct ref_tracker; + #define INTEL_DSI_VIDEO_MODE 0 #define INTEL_DSI_COMMAND_MODE 1 @@ -37,13 +40,11 @@ #define DSI_DUAL_LINK_FRONT_BACK 1 #define DSI_DUAL_LINK_PIXEL_ALT 2 -struct intel_dsi_host; - struct intel_dsi { struct intel_encoder base; struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS]; - intel_wakeref_t io_wakeref[I915_MAX_PORTS]; + struct ref_tracker *io_wakeref[I915_MAX_PORTS]; /* GPIO Desc for panel and backlight control */ struct gpio_desc *gpio_panel; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index b34b4961fe1c5..b9bd9b6dfe947 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -20,7 +20,7 @@ #include "intel_fb.h" #include "intel_fb_bo.h" #include "intel_frontbuffer.h" -#include "intel_panic.h" +#include "intel_parent.h" #include "intel_plane.h" #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) @@ -558,7 +558,7 @@ static bool plane_has_modifier(struct intel_display *display, * where supported. */ if (intel_fb_is_ccs_modifier(md->modifier) && - HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes) + intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes) return false; if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && @@ -2216,7 +2216,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, int ret; int i; - intel_fb->panic = intel_panic_alloc(); + intel_fb->panic = intel_parent_panic_alloc(display); if (!intel_fb->panic) return -ENOMEM; diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 437d2fda20a7e..1f3f5237a1c20 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -45,12 +45,6 @@ #include #include -#include "gem/i915_gem_stolen.h" - -#include "gt/intel_gt_types.h" - -#include "i915_drv.h" -#include "i915_vgpu.h" #include "i915_vma.h" #include "i9xx_plane_regs.h" #include "intel_de.h" @@ -64,6 +58,8 @@ #include "intel_fbc.h" #include "intel_fbc_regs.h" #include "intel_frontbuffer.h" +#include "intel_parent.h" +#include "intel_step.h" #define for_each_fbc_id(__display, __fbc_id) \ for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ @@ -71,7 +67,9 @@ #define for_each_intel_fbc(__display, __fbc, __fbc_id) \ for_each_fbc_id((__display), (__fbc_id)) \ - for_each_if((__fbc) = (__display)->fbc[(__fbc_id)]) + for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)]) + +#define FBC_SYS_CACHE_ID_NONE I915_MAX_FBCS struct intel_fbc_funcs { void (*activate)(struct intel_fbc *fbc); @@ -129,6 +127,19 @@ struct intel_fbc { const char *no_fbc_reason; }; +static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe) +{ + struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); + struct intel_plane *primary = NULL; + + primary = to_intel_plane(crtc->base.primary); + + if (drm_WARN_ON(display->drm, !primary)) + return NULL; + + return primary->fbc; +} + /* plane stride in pixels */ static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state) { @@ -204,7 +215,7 @@ static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; unsigned int cpp = intel_fbc_cfb_cpp(plane_state); @@ -235,7 +246,7 @@ static unsigned int _intel_fbc_cfb_size(struct intel_display *display, static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16; return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); @@ -243,7 +254,7 @@ static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_sta static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -267,9 +278,7 @@ static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_s static bool intel_fbc_has_fences(struct intel_display *display) { - struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm); - - return intel_gt_support_legacy_fencing(to_gt(i915)); + return intel_parent_has_fenced_regions(display); } static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) @@ -382,17 +391,17 @@ static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) struct intel_display *display = fbc->display; drm_WARN_ON(display->drm, - range_end_overflows_t(u64, i915_gem_stolen_area_address(display->drm), - i915_gem_stolen_node_offset(fbc->compressed_fb), + range_end_overflows_t(u64, intel_parent_stolen_area_address(display), + intel_parent_stolen_node_offset(display, fbc->compressed_fb), U32_MAX)); drm_WARN_ON(display->drm, - range_end_overflows_t(u64, i915_gem_stolen_area_address(display->drm), - i915_gem_stolen_node_offset(fbc->compressed_llb), + range_end_overflows_t(u64, intel_parent_stolen_area_address(display), + intel_parent_stolen_node_offset(display, fbc->compressed_llb), U32_MAX)); intel_de_write(display, FBC_CFB_BASE, - i915_gem_stolen_node_address(fbc->compressed_fb)); + intel_parent_stolen_node_address(display, fbc->compressed_fb)); intel_de_write(display, FBC_LL_BASE, - i915_gem_stolen_node_address(fbc->compressed_llb)); + intel_parent_stolen_node_address(display, fbc->compressed_llb)); } static const struct intel_fbc_funcs i8xx_fbc_funcs = { @@ -500,7 +509,7 @@ static void g4x_fbc_program_cfb(struct intel_fbc *fbc) struct intel_display *display = fbc->display; intel_de_write(display, DPFC_CB_BASE, - i915_gem_stolen_node_offset(fbc->compressed_fb)); + intel_parent_stolen_node_offset(display, fbc->compressed_fb)); } static const struct intel_fbc_funcs g4x_fbc_funcs = { @@ -569,7 +578,7 @@ static void ilk_fbc_program_cfb(struct intel_fbc *fbc) struct intel_display *display = fbc->display; intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), - i915_gem_stolen_node_offset(fbc->compressed_fb)); + intel_parent_stolen_node_offset(display, fbc->compressed_fb)); } static const struct intel_fbc_funcs ilk_fbc_funcs = { @@ -800,19 +809,32 @@ static u64 intel_fbc_cfb_base_max(struct intel_display *display) static u64 intel_fbc_stolen_end(struct intel_display *display) { - u64 end; + u64 end = intel_fbc_cfb_base_max(display); - /* The FBC hardware for BDW/SKL doesn't have access to the stolen + /* + * The FBC hardware for BDW/SKL doesn't have access to the stolen * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO - * underruns, even if that range is not reserved by the BIOS. */ + * underruns, even if that range is not reserved by the BIOS. + */ if (display->platform.broadwell || - (DISPLAY_VER(display) == 9 && !display->platform.broxton)) - end = i915_gem_stolen_area_size(display->drm) - 8 * 1024 * 1024; - else - end = U64_MAX; + (DISPLAY_VER(display) == 9 && !display->platform.broxton)) { + u64 stolen_area_size = intel_parent_stolen_area_size(display); + + /* + * If stolen_area_size is less than SZ_8M, use + * intel_fbc_cfb_base_max instead. This should not happen, + * so warn if it does. + */ + if (drm_WARN_ON(display->drm, + check_sub_overflow(stolen_area_size, + SZ_8M, &stolen_area_size))) + return end; + + return min(end, stolen_area_size); + } - return min(end, intel_fbc_cfb_base_max(display)); + return end; } static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) @@ -843,14 +865,14 @@ static int find_compression_limit(struct intel_fbc *fbc, size /= limit; /* Try to over-allocate to reduce reallocations and fragmentation. */ - ret = i915_gem_stolen_insert_node_in_range(fbc->compressed_fb, - size <<= 1, 4096, 0, end); + ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, + size <<= 1, 4096, 0, end); if (ret == 0) return limit; for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { - ret = i915_gem_stolen_insert_node_in_range(fbc->compressed_fb, - size >>= 1, 4096, 0, end); + ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, + size >>= 1, 4096, 0, end); if (ret == 0) return limit; } @@ -865,12 +887,12 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, int ret; drm_WARN_ON(display->drm, - i915_gem_stolen_node_allocated(fbc->compressed_fb)); + intel_parent_stolen_node_allocated(display, fbc->compressed_fb)); drm_WARN_ON(display->drm, - i915_gem_stolen_node_allocated(fbc->compressed_llb)); + intel_parent_stolen_node_allocated(display, fbc->compressed_llb)); if (DISPLAY_VER(display) < 5 && !display->platform.g4x) { - ret = i915_gem_stolen_insert_node(fbc->compressed_llb, 4096, 4096); + ret = intel_parent_stolen_insert_node(display, fbc->compressed_llb, 4096, 4096); if (ret) goto err; } @@ -886,14 +908,14 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, drm_dbg_kms(display->drm, "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", - i915_gem_stolen_node_size(fbc->compressed_fb), fbc->limit); + intel_parent_stolen_node_size(display, fbc->compressed_fb), fbc->limit); return 0; err_llb: - if (i915_gem_stolen_node_allocated(fbc->compressed_llb)) - i915_gem_stolen_remove_node(fbc->compressed_llb); + if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) + intel_parent_stolen_remove_node(display, fbc->compressed_llb); err: - if (i915_gem_stolen_initialized(display->drm)) + if (intel_parent_stolen_initialized(display)) drm_info_once(display->drm, "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); return -ENOSPC; @@ -945,15 +967,83 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc) fbc_compressor_clkgate_disable_wa(fbc, true); } +static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg, + enum intel_fbc_id id) +{ + if (!HAS_FBC_SYS_CACHE(display)) + return; + + lockdep_assert_held(&display->fbc.sys_cache.lock); + + /* + * Wa_14025769978: + * Fixes: SoC hardware issue in read caching + * Workaround: disable cache read setting which is enabled by default. + */ + if (!intel_display_wa(display, 14025769978)) + /* Cache read enable is set by default */ + reg |= FBC_SYS_CACHE_READ_ENABLE; + + intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg); + + display->fbc.sys_cache.id = id; +} + +static void fbc_sys_cache_disable(const struct intel_fbc *fbc) +{ + struct intel_display *display = fbc->display; + struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; + + mutex_lock(&sys_cache->lock); + /* clear only if "fbc" reserved the cache */ + if (sys_cache->id == fbc->id) + fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); + mutex_unlock(&sys_cache->lock); +} + +static int fbc_sys_cache_limit(struct intel_display *display) +{ + if (DISPLAY_VER(display) == 35) + return 2 * 1024 * 1024; + + return 0; +} + +static void fbc_sys_cache_enable(const struct intel_fbc *fbc) +{ + struct intel_display *display = fbc->display; + struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; + int range, offset; + u32 cfg; + + if (!HAS_FBC_SYS_CACHE(display)) + return; + + range = fbc_sys_cache_limit(display) / (64 * 1024); + + offset = intel_parent_stolen_node_offset(display, fbc->compressed_fb) / (4 * 1024); + + cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE | FBC_SYS_CACHEABLE_RANGE(range) | + FBC_SYS_CACHE_START_BASE(offset); + + mutex_lock(&sys_cache->lock); + /* update sys cache config only if sys cache is unassigned */ + if (sys_cache->id == FBC_SYS_CACHE_ID_NONE) + fbc_sys_cache_update_config(display, cfg, fbc->id); + mutex_unlock(&sys_cache->lock); +} + static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) { + struct intel_display *display = fbc->display; + if (WARN_ON(intel_fbc_hw_is_active(fbc))) return; - if (i915_gem_stolen_node_allocated(fbc->compressed_llb)) - i915_gem_stolen_remove_node(fbc->compressed_llb); - if (i915_gem_stolen_node_allocated(fbc->compressed_fb)) - i915_gem_stolen_remove_node(fbc->compressed_fb); + if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) + intel_parent_stolen_remove_node(display, fbc->compressed_llb); + if (intel_parent_stolen_node_allocated(display, fbc->compressed_fb)) + intel_parent_stolen_remove_node(display, fbc->compressed_fb); } void intel_fbc_cleanup(struct intel_display *display) @@ -966,11 +1056,16 @@ void intel_fbc_cleanup(struct intel_display *display) __intel_fbc_cleanup_cfb(fbc); mutex_unlock(&fbc->lock); - i915_gem_stolen_node_free(fbc->compressed_fb); - i915_gem_stolen_node_free(fbc->compressed_llb); + intel_parent_stolen_node_free(display, fbc->compressed_fb); + intel_parent_stolen_node_free(display, fbc->compressed_llb); kfree(fbc); } + + mutex_lock(&display->fbc.sys_cache.lock); + drm_WARN_ON(display->drm, + display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE); + mutex_unlock(&display->fbc.sys_cache.lock); } static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state) @@ -1016,7 +1111,7 @@ static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) static bool stride_is_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); if (DISPLAY_VER(display) >= 11) return icl_fbc_stride_is_valid(plane_state); @@ -1032,7 +1127,7 @@ static bool stride_is_valid(const struct intel_plane_state *plane_state) static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; switch (fb->format->format) { @@ -1052,7 +1147,7 @@ static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; switch (fb->format->format) { @@ -1131,7 +1226,7 @@ intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); if (DISPLAY_VER(display) >= 35) return xe3p_lpd_fbc_pixel_format_is_valid(plane_state); @@ -1167,7 +1262,7 @@ static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_stat static bool rotation_is_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); if (DISPLAY_VER(display) >= 9) return skl_fbc_rotation_is_valid(plane_state); @@ -1206,7 +1301,7 @@ static void intel_fbc_max_surface_size(struct intel_display *display, */ static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int effective_w, effective_h, max_w, max_h; intel_fbc_max_surface_size(display, &max_w, &max_h); @@ -1239,7 +1334,7 @@ static void intel_fbc_max_plane_size(struct intel_display *display, static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); unsigned int w, h, max_w, max_h; intel_fbc_max_plane_size(display, &max_w, &max_h); @@ -1264,7 +1359,7 @@ static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state) static bool tiling_is_valid(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); if (DISPLAY_VER(display) >= 9) return skl_fbc_tiling_valid(plane_state); @@ -1344,7 +1439,7 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) { - struct intel_display *display = to_intel_display(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); const struct intel_plane_state *plane_state = @@ -1377,7 +1472,7 @@ static void intel_fbc_update_state(struct intel_atomic_state *state, static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); + struct intel_display *display = to_intel_display(plane_state); /* * The use of a CPU fence is one of two ways to detect writes by the @@ -1398,12 +1493,13 @@ static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct intel_fbc *fbc = plane->fbc; return intel_fbc_min_limit(plane_state) <= fbc->limit && intel_fbc_cfb_size(plane_state) <= fbc->limit * - i915_gem_stolen_node_size(fbc->compressed_fb); + intel_parent_stolen_node_size(display, fbc->compressed_fb); } static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) @@ -1484,8 +1580,7 @@ static int _intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_fbc_check_plane(struct intel_atomic_state *state, struct intel_plane *plane) { - struct intel_display *display = to_intel_display(state->base.dev); - struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_display *display = to_intel_display(state); struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -1496,12 +1591,12 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, if (!fbc) return 0; - if (!i915_gem_stolen_initialized(display->drm)) { + if (!intel_parent_stolen_initialized(display)) { plane_state->no_fbc_reason = "stolen memory not initialised"; return 0; } - if (intel_vgpu_active(i915)) { + if (intel_parent_vgpu_active(display)) { plane_state->no_fbc_reason = "VGPU active"; return 0; } @@ -1521,6 +1616,16 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } + /* + * Wa_15018326506: + * Fixes: Underrun during media decode + * Workaround: Do not enable FBC + */ + if (intel_display_wa(display, 15018326506)) { + plane_state->no_fbc_reason = "Wa_15018326506"; + return 0; + } + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ if (intel_display_vtd_active(display) && (display->platform.skylake || display->platform.broxton)) { @@ -1702,7 +1807,7 @@ static bool __intel_fbc_pre_update(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) { - struct intel_display *display = to_intel_display(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_fbc *fbc = plane->fbc; bool need_vblank_wait = false; @@ -1775,6 +1880,8 @@ static void __intel_fbc_disable(struct intel_fbc *fbc) __intel_fbc_cleanup_cfb(fbc); + fbc_sys_cache_disable(fbc); + /* wa_18038517565 Enable DPFC clock gating after FBC disable */ if (display->platform.dg2 || DISPLAY_VER(display) >= 14) fbc_compressor_clkgate_disable_wa(fbc, false); @@ -1915,7 +2022,7 @@ static void __intel_fbc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_plane *plane) { - struct intel_display *display = to_intel_display(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); struct intel_fbc *fbc = plane->fbc; @@ -1967,6 +2074,8 @@ static void __intel_fbc_enable(struct intel_atomic_state *state, intel_fbc_program_workarounds(fbc); intel_fbc_program_cfb(fbc); + + fbc_sys_cache_enable(fbc); } /** @@ -1977,7 +2086,7 @@ static void __intel_fbc_enable(struct intel_atomic_state *state, */ void intel_fbc_disable(struct intel_crtc *crtc) { - struct intel_display *display = to_intel_display(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane; for_each_intel_plane(display->drm, plane) { @@ -2119,6 +2228,37 @@ void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) __intel_fbc_handle_fifo_underrun_irq(fbc); } +/** + * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info + * @display: display device instance + * @pipe: the pipe possibly containing the FBC + * @log: log the info? + * + * If @pipe does not contain an FBC instance, this function bails early. + * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log + * is true, printed with error level. + */ +void intel_fbc_read_underrun_dbg_info(struct intel_display *display, + enum pipe pipe, bool log) +{ + struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe); + u32 val; + + if (!fbc) + return; + + val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id)); + if (!(val & FBC_UNDERRUN_DECMPR)) + return; + + intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR); + + if (log) + drm_err(display->drm, + "Pipe %c FIFO underrun info: FBC decompressing\n", + pipe_name(pipe)); +} + /* * The DDX driver changes its behavior depending on the value it reads from * i915.enable_fbc, so sanitize it by translating the default value into either @@ -2156,10 +2296,10 @@ static struct intel_fbc *intel_fbc_create(struct intel_display *display, if (!fbc) return NULL; - fbc->compressed_fb = i915_gem_stolen_node_alloc(display->drm); + fbc->compressed_fb = intel_parent_stolen_node_alloc(display); if (!fbc->compressed_fb) goto err; - fbc->compressed_llb = i915_gem_stolen_node_alloc(display->drm); + fbc->compressed_llb = intel_parent_stolen_node_alloc(display); if (!fbc->compressed_llb) goto err; @@ -2184,8 +2324,8 @@ static struct intel_fbc *intel_fbc_create(struct intel_display *display, return fbc; err: - i915_gem_stolen_node_free(fbc->compressed_llb); - i915_gem_stolen_node_free(fbc->compressed_fb); + intel_parent_stolen_node_free(display, fbc->compressed_llb); + intel_parent_stolen_node_free(display, fbc->compressed_fb); kfree(fbc); return NULL; @@ -2206,7 +2346,10 @@ void intel_fbc_init(struct intel_display *display) display->params.enable_fbc); for_each_fbc_id(display, fbc_id) - display->fbc[fbc_id] = intel_fbc_create(display, fbc_id); + display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id); + + mutex_init(&display->fbc.sys_cache.lock); + display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE; } /** @@ -2226,6 +2369,11 @@ void intel_fbc_sanitize(struct intel_display *display) if (intel_fbc_hw_is_active(fbc)) intel_fbc_hw_deactivate(fbc); } + + /* Ensure the sys cache usage config is clear as well */ + mutex_lock(&display->fbc.sys_cache.lock); + fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); + mutex_unlock(&display->fbc.sys_cache.lock); } static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) @@ -2244,6 +2392,11 @@ static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) seq_puts(m, "FBC enabled\n"); seq_printf(m, "Compressing: %s\n", str_yes_no(intel_fbc_is_compressing(fbc))); + + mutex_lock(&display->fbc.sys_cache.lock); + seq_printf(m, "Using system cache: %s\n", + str_yes_no(display->fbc.sys_cache.id == fbc->id)); + mutex_unlock(&display->fbc.sys_cache.lock); } else { seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); } @@ -2325,7 +2478,7 @@ void intel_fbc_debugfs_register(struct intel_display *display) { struct intel_fbc *fbc; - fbc = display->fbc[INTEL_FBC_A]; + fbc = display->fbc.instances[INTEL_FBC_A]; if (fbc) intel_fbc_debugfs_add(fbc, display->drm->debugfs_root); } diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index 91424563206a3..f0255ddae2b60 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -9,6 +9,7 @@ #include enum fb_op_origin; +enum pipe; struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; @@ -46,6 +47,8 @@ void intel_fbc_flush(struct intel_display *display, unsigned int frontbuffer_bits, enum fb_op_origin origin); void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane); void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display); +void intel_fbc_read_underrun_dbg_info(struct intel_display *display, + enum pipe, bool log); void intel_fbc_reset_underrun(struct intel_display *display); void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc); void intel_fbc_debugfs_register(struct intel_display *display); diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h index b1d0161a31968..4178e602d7d76 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -88,6 +88,8 @@ #define DPFC_FENCE_YOFF _MMIO(0x3218) #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) #define DPFC_CHICKEN _MMIO(0x3224) +#define FBC_DEBUG_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43220, 0x43260) +#define FBC_UNDERRUN_DECMPR REG_BIT(27) #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ #define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ @@ -126,4 +128,14 @@ #define FBC_REND_NUKE REG_BIT(2) #define FBC_REND_CACHE_CLEAN REG_BIT(1) +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG _MMIO(0x1344E0) +#define FBC_SYS_CACHE_START_BASE_MASK REG_GENMASK(31, 16) +#define FBC_SYS_CACHE_START_BASE(base) REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base)) +#define FBC_SYS_CACHEABLE_RANGE_MASK REG_GENMASK(15, 4) +#define FBC_SYS_CACHEABLE_RANGE(range) REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range)) +#define FBC_SYS_CACHE_TAG_MASK REG_GENMASK(3, 2) +#define FBC_SYS_CACHE_TAG_DONT_CACHE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0) +#define FBC_SYS_CACHE_TAG_USE_RES_SPACE REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3) +#define FBC_SYS_CACHE_READ_ENABLE REG_BIT(0) + #endif /* __INTEL_FBC_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index c2ce8461ac9e7..b413b3e871d82 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -25,6 +25,8 @@ * */ +#include + #include #include "i915_reg.h" @@ -57,6 +59,100 @@ * The code also supports underrun detection on the PCH transcoder. */ +#define UNDERRUN_DBG1_NUM_PLANES 6 + +static void log_underrun_dbg1(struct intel_display *display, enum pipe pipe, + unsigned long plane_mask, const char *info) +{ + DECLARE_SEQ_BUF(planes_desc, 32); + unsigned int i; + + if (!plane_mask) + return; + + for_each_set_bit(i, &plane_mask, UNDERRUN_DBG1_NUM_PLANES) { + if (i == 0) + seq_buf_puts(&planes_desc, "[C]"); + else + seq_buf_printf(&planes_desc, "[%d]", i); + } + + drm_err(display->drm, "Pipe %c FIFO underrun info: %s on planes: %s\n", + pipe_name(pipe), info, seq_buf_str(&planes_desc)); + + drm_WARN_ON(display->drm, seq_buf_has_overflowed(&planes_desc)); +} + +static void read_underrun_dbg1(struct intel_display *display, enum pipe pipe, bool log) +{ + u32 val = intel_de_read(display, UNDERRUN_DBG1(pipe)); + + if (!val) + return; + + intel_de_write(display, UNDERRUN_DBG1(pipe), val); + + if (!log) + return; + + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK, val), + "DBUF block not valid"); + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DDB_EMPTY_MASK, val), + "DDB empty"); + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_DBUF_NOT_FILLED_MASK, val), + "DBUF not completely filled"); + log_underrun_dbg1(display, pipe, REG_FIELD_GET(UNDERRUN_BELOW_WM0_MASK, val), + "DBUF below WM0"); +} + +static void read_underrun_dbg2(struct intel_display *display, enum pipe pipe, bool log) +{ + u32 val = intel_de_read(display, UNDERRUN_DBG2(pipe)); + + if (!(val & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN)) + return; + + intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN); + + if (log) + drm_err(display->drm, + "Pipe %c FIFO underrun info: frame count: %u, line count: %u\n", + pipe_name(pipe), + REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, val), + REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, val)); +} + +static void read_underrun_dbg_pkgc(struct intel_display *display, bool log) +{ + u32 val = intel_de_read(display, GEN12_DCPR_STATUS_1); + + if (!(val & XE3P_UNDERRUN_PKGC)) + return; + + /* + * Note: If there are multiple pipes enabled, only one of them will see + * XE3P_UNDERRUN_PKGC set. + */ + intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC); + + if (log) + drm_err(display->drm, + "General FIFO underrun info: Package C-state blocking memory\n"); +} + +static void read_underrun_dbg_info(struct intel_display *display, + enum pipe pipe, + bool log) +{ + if (!HAS_UNDERRUN_DBG_INFO(display)) + return; + + read_underrun_dbg1(display, pipe, log); + read_underrun_dbg2(display, pipe, log); + intel_fbc_read_underrun_dbg_info(display, pipe, log); + read_underrun_dbg_pkgc(display, log); +} + static bool ivb_can_enable_err_int(struct intel_display *display) { struct intel_crtc *crtc; @@ -262,6 +358,17 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct intel_display *displa old = !crtc->cpu_fifo_underrun_disabled; crtc->cpu_fifo_underrun_disabled = !enable; + /* + * The debug bits get latched at the time of the FIFO underrun ISR bit + * getting set. That means that any non-zero debug bit that is read when + * handling a FIFO underrun interrupt has the potential to belong to + * another underrun event (past or future). To alleviate this problem, + * let's clear existing bits before enabling the interrupt, so that at + * least we don't get information that is too out-of-date. + */ + if (enable && !old) + read_underrun_dbg_info(display, pipe, false); + if (HAS_GMCH(display)) i9xx_set_fifo_underrun_reporting(display, pipe, enable, old); else if (display->platform.ironlake || display->platform.sandybridge) @@ -379,6 +486,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display, trace_intel_cpu_fifo_underrun(display, pipe); drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); + + read_underrun_dbg_info(display, pipe, true); } intel_fbc_handle_fifo_underrun_irq(display); diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 795012d7c24c2..2caff677600ca 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -35,8 +35,6 @@ #include #include -#include "i915_drv.h" -#include "i915_irq.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_display_regs.h" @@ -44,6 +42,7 @@ #include "intel_display_wa.h" #include "intel_gmbus.h" #include "intel_gmbus_regs.h" +#include "intel_parent.h" struct intel_gmbus { struct i2c_adapter adapter; @@ -391,12 +390,11 @@ intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) static bool has_gmbus_irq(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); /* * encoder->shutdown() may want to use GMBUS * after irqs have already been disabled. */ - return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915); + return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display); } static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) @@ -791,7 +789,7 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) { struct intel_gmbus *bus = to_intel_gmbus(adapter); struct intel_display *display = bus->display; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int ret; wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); @@ -831,7 +829,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) .buf = buf, } }; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int ret; wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); diff --git a/drivers/gpu/drm/i915/display/intel_gvt_api.c b/drivers/gpu/drm/i915/display/intel_gvt_api.c new file mode 100644 index 0000000000000..a69e249395aea --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_gvt_api.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2025 Intel Corporation + */ + +#include + +#include "intel_display_core.h" +#include "intel_display_regs.h" +#include "intel_gvt_api.h" + +u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe) +{ + return INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe); +} +EXPORT_SYMBOL_NS_GPL(intel_display_device_pipe_offset, "I915_GVT"); + +u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans) +{ + return INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans); +} +EXPORT_SYMBOL_NS_GPL(intel_display_device_trans_offset, "I915_GVT"); + +u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe) +{ + return INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe); +} +EXPORT_SYMBOL_NS_GPL(intel_display_device_cursor_offset, "I915_GVT"); + +u32 intel_display_device_mmio_base(struct intel_display *display) +{ + return DISPLAY_MMIO_BASE(display); +} +EXPORT_SYMBOL_NS_GPL(intel_display_device_mmio_base, "I915_GVT"); + +bool intel_display_device_pipe_valid(struct intel_display *display, enum pipe pipe) +{ + if (pipe < PIPE_A || pipe >= I915_MAX_PIPES) + return false; + + return DISPLAY_RUNTIME_INFO(display)->pipe_mask & BIT(pipe); +} +EXPORT_SYMBOL_NS_GPL(intel_display_device_pipe_valid, "I915_GVT"); diff --git a/drivers/gpu/drm/i915/display/intel_gvt_api.h b/drivers/gpu/drm/i915/display/intel_gvt_api.h new file mode 100644 index 0000000000000..ce3b744142a5a --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_gvt_api.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef __INTEL_GVT_API_H__ +#define __INTEL_GVT_API_H__ + +#include + +enum pipe; +enum transcoder; +struct intel_display; + +u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe); +u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans); +u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe); +u32 intel_display_device_mmio_base(struct intel_display *display); +bool intel_display_device_pipe_valid(struct intel_display *display, enum pipe pipe); + +#endif /* __INTEL_GVT_API_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 5e1a96223a9ce..7114fc405c291 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -29,10 +29,10 @@ #include "intel_display_types.h" #include "intel_dp_mst.h" #include "intel_hdcp.h" -#include "intel_hdcp_gsc.h" #include "intel_hdcp_gsc_message.h" #include "intel_hdcp_regs.h" #include "intel_hdcp_shim.h" +#include "intel_parent.h" #include "intel_pcode.h" #include "intel_step.h" @@ -258,7 +258,7 @@ static bool intel_hdcp2_prerequisite(struct intel_connector *connector) /* If MTL+ make sure gsc is loaded and proxy is setup */ if (USE_HDCP_GSC(display)) { - if (!intel_hdcp_gsc_check_status(display->drm)) + if (!intel_parent_hdcp_gsc_check_status(display)) return false; } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h deleted file mode 100644 index 9305c14aaffeb..0000000000000 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#ifndef __INTEL_HDCP_GSC_H__ -#define __INTEL_HDCP_GSC_H__ - -#include - -struct drm_device; -struct intel_hdcp_gsc_context; - -ssize_t intel_hdcp_gsc_msg_send(struct intel_hdcp_gsc_context *gsc_context, - void *msg_in, size_t msg_in_len, - void *msg_out, size_t msg_out_len); -bool intel_hdcp_gsc_check_status(struct drm_device *drm); - -struct intel_hdcp_gsc_context *intel_hdcp_gsc_context_alloc(struct drm_device *drm); -void intel_hdcp_gsc_context_free(struct intel_hdcp_gsc_context *gsc_context); - -#endif /* __INTEL_HDCP_GCS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c index 98967bb148e38..781667b710b4d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c @@ -10,8 +10,8 @@ #include "intel_display_core.h" #include "intel_display_types.h" -#include "intel_hdcp_gsc.h" #include "intel_hdcp_gsc_message.h" +#include "intel_parent.h" static int intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, @@ -44,10 +44,9 @@ intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, session_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; session_init_in.protocol = data->protocol; - byte = intel_hdcp_gsc_msg_send(gsc_context, &session_init_in, - sizeof(session_init_in), - &session_init_out, - sizeof(session_init_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &session_init_in, sizeof(session_init_in), + &session_init_out, sizeof(session_init_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -106,10 +105,9 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, memcpy(verify_rxcert_in.r_rx, &rx_cert->r_rx, HDCP_2_2_RRX_LEN); memcpy(verify_rxcert_in.rx_caps, rx_cert->rx_caps, HDCP_2_2_RXCAPS_LEN); - byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_rxcert_in, - sizeof(verify_rxcert_in), - &verify_rxcert_out, - sizeof(verify_rxcert_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &verify_rxcert_in, sizeof(verify_rxcert_in), + &verify_rxcert_out, sizeof(verify_rxcert_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed: %zd\n", byte); return byte; @@ -169,10 +167,9 @@ intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, memcpy(send_hprime_in.h_prime, rx_hprime->h_prime, HDCP_2_2_H_PRIME_LEN); - byte = intel_hdcp_gsc_msg_send(gsc_context, &send_hprime_in, - sizeof(send_hprime_in), - &send_hprime_out, - sizeof(send_hprime_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &send_hprime_in, sizeof(send_hprime_in), + &send_hprime_out, sizeof(send_hprime_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -220,10 +217,9 @@ intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *dat memcpy(pairing_info_in.e_kh_km, pairing_info->e_kh_km, HDCP_2_2_E_KH_KM_LEN); - byte = intel_hdcp_gsc_msg_send(gsc_context, &pairing_info_in, - sizeof(pairing_info_in), - &pairing_info_out, - sizeof(pairing_info_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &pairing_info_in, sizeof(pairing_info_in), + &pairing_info_out, sizeof(pairing_info_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -269,8 +265,9 @@ intel_hdcp_gsc_initiate_locality_check(struct device *dev, lc_init_in.port.physical_port = (u8)data->hdcp_ddi; lc_init_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - byte = intel_hdcp_gsc_msg_send(gsc_context, &lc_init_in, sizeof(lc_init_in), - &lc_init_out, sizeof(lc_init_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &lc_init_in, sizeof(lc_init_in), + &lc_init_out, sizeof(lc_init_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -321,10 +318,9 @@ intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, memcpy(verify_lprime_in.l_prime, rx_lprime->l_prime, HDCP_2_2_L_PRIME_LEN); - byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_lprime_in, - sizeof(verify_lprime_in), - &verify_lprime_out, - sizeof(verify_lprime_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &verify_lprime_in, sizeof(verify_lprime_in), + &verify_lprime_out, sizeof(verify_lprime_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -370,8 +366,9 @@ intel_hdcp_gsc_get_session_key(struct device *dev, get_skey_in.port.physical_port = (u8)data->hdcp_ddi; get_skey_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - byte = intel_hdcp_gsc_msg_send(gsc_context, &get_skey_in, sizeof(get_skey_in), - &get_skey_out, sizeof(get_skey_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &get_skey_in, sizeof(get_skey_in), + &get_skey_out, sizeof(get_skey_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -434,10 +431,9 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, memcpy(verify_repeater_in.receiver_ids, rep_topology->receiver_ids, HDCP_2_2_RECEIVER_IDS_MAX_LEN); - byte = intel_hdcp_gsc_msg_send(gsc_context, &verify_repeater_in, - sizeof(verify_repeater_in), - &verify_repeater_out, - sizeof(verify_repeater_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &verify_repeater_in, sizeof(verify_repeater_in), + &verify_repeater_out, sizeof(verify_repeater_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -504,9 +500,9 @@ intel_hdcp_gsc_verify_mprime(struct device *dev, verify_mprime_in->k = cpu_to_be16(data->k); - byte = intel_hdcp_gsc_msg_send(gsc_context, verify_mprime_in, cmd_size, - &verify_mprime_out, - sizeof(verify_mprime_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + verify_mprime_in, cmd_size, + &verify_mprime_out, sizeof(verify_mprime_out)); kfree(verify_mprime_in); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); @@ -552,10 +548,9 @@ static int intel_hdcp_gsc_enable_authentication(struct device *dev, enable_auth_in.port.attached_transcoder = (u8)data->hdcp_transcoder; enable_auth_in.stream_type = data->streams[0].stream_type; - byte = intel_hdcp_gsc_msg_send(gsc_context, &enable_auth_in, - sizeof(enable_auth_in), - &enable_auth_out, - sizeof(enable_auth_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &enable_auth_in, sizeof(enable_auth_in), + &enable_auth_out, sizeof(enable_auth_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -599,10 +594,9 @@ intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) session_close_in.port.physical_port = (u8)data->hdcp_ddi; session_close_in.port.attached_transcoder = (u8)data->hdcp_transcoder; - byte = intel_hdcp_gsc_msg_send(gsc_context, &session_close_in, - sizeof(session_close_in), - &session_close_out, - sizeof(session_close_out)); + byte = intel_parent_hdcp_gsc_msg_send(display, gsc_context, + &session_close_in, sizeof(session_close_in), + &session_close_out, sizeof(session_close_out)); if (byte < 0) { drm_dbg_kms(display->drm, "intel_hdcp_gsc_msg_send failed. %zd\n", byte); return byte; @@ -645,7 +639,7 @@ int intel_hdcp_gsc_init(struct intel_display *display) mutex_lock(&display->hdcp.hdcp_mutex); - gsc_context = intel_hdcp_gsc_context_alloc(display->drm); + gsc_context = intel_parent_hdcp_gsc_context_alloc(display); if (IS_ERR(gsc_context)) { ret = PTR_ERR(gsc_context); kfree(arbiter); @@ -665,7 +659,7 @@ int intel_hdcp_gsc_init(struct intel_display *display) void intel_hdcp_gsc_fini(struct intel_display *display) { - intel_hdcp_gsc_context_free(display->hdcp.gsc_context); + intel_parent_hdcp_gsc_context_free(display, display->hdcp.gsc_context); display->hdcp.gsc_context = NULL; kfree(display->hdcp.arbiter); display->hdcp.arbiter = NULL; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 908faf17f93d3..055e68810d0d6 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2518,7 +2518,7 @@ intel_hdmi_set_edid(struct drm_connector *_connector) struct intel_display *display = to_intel_display(connector); struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); struct i2c_adapter *ddc = connector->base.ddc; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; const struct drm_edid *drm_edid; bool connected = false; @@ -2561,7 +2561,7 @@ intel_hdmi_detect(struct drm_connector *_connector, bool force) enum drm_connector_status status = connector_status_disconnected; struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", connector->base.base.id, connector->base.name); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 235706229ffbb..970aa95ee344a 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -27,8 +27,6 @@ #include #include -#include "i915_drv.h" -#include "i915_irq.h" #include "intel_connector.h" #include "intel_display_core.h" #include "intel_display_power.h" @@ -39,6 +37,7 @@ #include "intel_hdcp.h" #include "intel_hotplug.h" #include "intel_hotplug_irq.h" +#include "intel_parent.h" /** * DOC: Hotplug @@ -786,7 +785,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work) container_of(work, typeof(*display), hotplug.poll_init_work); struct drm_connector_list_iter conn_iter; struct intel_connector *connector; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool enabled; mutex_lock(&display->drm->mode_config.mutex); @@ -1177,13 +1176,12 @@ bool intel_hpd_schedule_detection(struct intel_display *display) static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) { struct intel_display *display = m->private; - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_hotplug *hotplug = &display->hotplug; /* Synchronize with everything first in case there's been an HPD * storm, but we haven't finished handling it in the kernel yet */ - intel_synchronize_irq(dev_priv); + intel_parent_irq_synchronize(display); flush_work(&display->hotplug.dig_port_work); flush_delayed_work(&display->hotplug.hotplug_work); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index 46c47b3d6f428..82c39e4ffa371 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -519,12 +519,9 @@ void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir) { enum hpd_pin pin; u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); - u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; + u32 trigger_aux = iir & xelpdp_pica_aux_mask(display); u32 pin_mask = 0, long_mask = 0; - if (DISPLAY_VER(display) >= 20) - trigger_aux |= iir & XE2LPD_AUX_DDI_MASK; - for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { u32 val; diff --git a/drivers/gpu/drm/i915/display/intel_initial_plane.c b/drivers/gpu/drm/i915/display/intel_initial_plane.c new file mode 100644 index 0000000000000..ee545c033da68 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_initial_plane.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: MIT +/* Copyright © 2025 Intel Corporation */ + +#include +#include + +#include "intel_display_core.h" +#include "intel_display_types.h" +#include "intel_fb.h" +#include "intel_frontbuffer.h" +#include "intel_initial_plane.h" +#include "intel_plane.h" + +void intel_initial_plane_vblank_wait(struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + + display->parent->initial_plane->vblank_wait(&crtc->base); +} + +static const struct intel_plane_state * +intel_reuse_initial_plane_obj(struct intel_crtc *this, + const struct intel_initial_plane_config plane_configs[]) +{ + struct intel_display *display = to_intel_display(this); + struct intel_crtc *crtc; + + for_each_intel_crtc(display->drm, crtc) { + struct intel_plane *plane = + to_intel_plane(crtc->base.primary); + const struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + + if (!crtc_state->hw.active) + continue; + + if (!plane_state->ggtt_vma) + continue; + + if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) + return plane_state; + } + + return NULL; +} + +static struct drm_gem_object * +intel_alloc_initial_plane_obj(struct intel_display *display, + struct intel_initial_plane_config *plane_config) +{ + struct intel_framebuffer *fb = plane_config->fb; + + switch (fb->base.modifier) { + case DRM_FORMAT_MOD_LINEAR: + case I915_FORMAT_MOD_X_TILED: + case I915_FORMAT_MOD_Y_TILED: + case I915_FORMAT_MOD_4_TILED: + break; + default: + drm_dbg_kms(display->drm, "Unsupported modifier for initial FB: 0x%llx\n", + fb->base.modifier); + return NULL; + } + + return display->parent->initial_plane->alloc_obj(display->drm, plane_config); +} + +static void +intel_find_initial_plane_obj(struct intel_crtc *crtc, + struct intel_initial_plane_config plane_configs[]) +{ + struct intel_display *display = to_intel_display(crtc); + struct intel_initial_plane_config *plane_config = &plane_configs[crtc->pipe]; + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); + struct drm_framebuffer *fb; + struct i915_vma *vma; + int ret; + + /* + * TODO: + * Disable planes if get_initial_plane_config() failed. + * Make sure things work if the surface base is not page aligned. + */ + if (!plane_config->fb) + return; + + if (intel_alloc_initial_plane_obj(display, plane_config)) { + fb = &plane_config->fb->base; + vma = plane_config->vma; + } else { + const struct intel_plane_state *other_plane_state; + + other_plane_state = intel_reuse_initial_plane_obj(crtc, plane_configs); + if (!other_plane_state) + goto nofb; + + fb = other_plane_state->hw.fb; + vma = other_plane_state->ggtt_vma; + } + + plane_state->uapi.rotation = plane_config->rotation; + intel_fb_fill_view(to_intel_framebuffer(fb), + plane_state->uapi.rotation, &plane_state->view); + + ret = display->parent->initial_plane->setup(plane->base.state, plane_config, fb, vma); + if (ret) + goto nofb; + + plane_state->uapi.src_x = 0; + plane_state->uapi.src_y = 0; + plane_state->uapi.src_w = fb->width << 16; + plane_state->uapi.src_h = fb->height << 16; + + plane_state->uapi.crtc_x = 0; + plane_state->uapi.crtc_y = 0; + plane_state->uapi.crtc_w = fb->width; + plane_state->uapi.crtc_h = fb->height; + + plane_state->uapi.fb = fb; + drm_framebuffer_get(fb); + + plane_state->uapi.crtc = &crtc->base; + intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc); + + atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); + + return; + +nofb: + /* + * We've failed to reconstruct the BIOS FB. Current display state + * indicates that the primary plane is visible, but has a NULL FB, + * which will lead to problems later if we don't fix it up. The + * simplest solution is to just disable the primary plane now and + * pretend the BIOS never had it enabled. + */ + intel_plane_disable_noatomic(crtc, plane); +} + +static void plane_config_fini(struct intel_display *display, + struct intel_initial_plane_config *plane_config) +{ + if (plane_config->fb) { + struct drm_framebuffer *fb = &plane_config->fb->base; + + /* We may only have the stub and not a full framebuffer */ + if (drm_framebuffer_read_refcount(fb)) + drm_framebuffer_put(fb); + else + kfree(fb); + } + + display->parent->initial_plane->config_fini(plane_config); +} + +void intel_initial_plane_config(struct intel_display *display) +{ + struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; + struct intel_crtc *crtc; + + for_each_intel_crtc(display->drm, crtc) { + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + struct intel_initial_plane_config *plane_config = + &plane_configs[crtc->pipe]; + + if (!crtc_state->hw.active) + continue; + + /* + * Note that reserving the BIOS fb up front prevents us + * from stuffing other stolen allocations like the ring + * on top. This prevents some ugliness at boot time, and + * can even allow for smooth boot transitions if the BIOS + * fb is large enough for the active pipe configuration. + */ + display->funcs.display->get_initial_plane_config(crtc, plane_config); + + /* + * If the fb is shared between multiple heads, we'll + * just get the first one. + */ + intel_find_initial_plane_obj(crtc, plane_configs); + + if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) + intel_initial_plane_vblank_wait(crtc); + + plane_config_fini(display, plane_config); + } +} diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.h b/drivers/gpu/drm/i915/display/intel_initial_plane.h similarity index 60% rename from drivers/gpu/drm/i915/display/intel_plane_initial.h rename to drivers/gpu/drm/i915/display/intel_initial_plane.h index 5c315acda2101..5f9a347be8f0f 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.h +++ b/drivers/gpu/drm/i915/display/intel_initial_plane.h @@ -3,13 +3,13 @@ * Copyright © 2021 Intel Corporation */ -#ifndef __INTEL_PLANE_INITIAL_H__ -#define __INTEL_PLANE_INITIAL_H__ +#ifndef __INTEL_INITIAL_PLANE_H__ +#define __INTEL_INITIAL_PLANE_H__ struct intel_crtc; struct intel_display; void intel_initial_plane_config(struct intel_display *display); -void intel_plane_initial_vblank_wait(struct intel_crtc *crtc); +void intel_initial_plane_vblank_wait(struct intel_crtc *crtc); #endif diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 42284e9928f2f..5b41abe1c64d5 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -71,7 +71,6 @@ #include #include -#include "i915_irq.h" #include "intel_audio_regs.h" #include "intel_de.h" #include "intel_lpe_audio.h" diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index a67eb4f7f8975..6cdae03ee172c 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -31,6 +31,7 @@ #define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\ INTEL_LT_PHY_LANE0) #define MODE_DP 3 +#define MODE_HDMI_20 4 #define Q32_TO_INT(x) ((x) >> 32) #define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF) #define DCO_MIN_FREQ_MHZ 11850 @@ -1324,11 +1325,11 @@ intel_lt_phy_config_changed(struct intel_encoder *encoder, return true; } -static intel_wakeref_t intel_lt_phy_transaction_begin(struct intel_encoder *encoder) +static struct ref_tracker *intel_lt_phy_transaction_begin(struct intel_encoder *encoder) { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; intel_psr_pause(intel_dp); wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); @@ -1336,7 +1337,7 @@ static intel_wakeref_t intel_lt_phy_transaction_begin(struct intel_encoder *enco return wakeref; } -static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref) +static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, struct ref_tracker *wakeref) { struct intel_display *display = to_intel_display(encoder); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -1751,6 +1752,7 @@ int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(encoder); int clk; const struct intel_lt_phy_pll_state *lt_state = &crtc_state->dpll_hw_state.ltpll; @@ -1768,8 +1770,11 @@ intel_lt_phy_calc_port_clock(struct intel_encoder *encoder, rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, lt_state->config[0]); clk = intel_lt_phy_get_dp_clock(rate); - } else { + } else if (mode == MODE_HDMI_20) { clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state); + } else { + drm_WARN_ON(display->drm, "Unsupported LT PHY Mode!\n"); + clk = xe3plpd_lt_hdmi_252.clock; } return clk; @@ -1932,7 +1937,7 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); enum phy phy = intel_encoder_to_phy(encoder); enum port port = encoder->port; - intel_wakeref_t wakeref = 0; + struct ref_tracker *wakeref = 0; u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES ? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) | XE3PLPDP_LANE_PHY_PULSE_STATUS(1)) @@ -2060,7 +2065,7 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder) struct intel_display *display = to_intel_display(encoder); enum phy phy = intel_encoder_to_phy(encoder); enum port port = encoder->port; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES ? (XELPDP_LANE_PIPE_RESET(0) | @@ -2137,7 +2142,7 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, struct intel_display *display = to_intel_display(encoder); const struct intel_ddi_buf_trans *trans; u8 owned_lane_mask; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int n_entries, ln; struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -2207,13 +2212,18 @@ bool intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, const struct intel_lt_phy_pll_state *b) { - if (memcmp(&a->config, &b->config, sizeof(a->config)) != 0) - return false; - - if (memcmp(&a->data, &b->data, sizeof(a->data)) != 0) - return false; + /* + * With LT PHY values other than VDR0_CONFIG and VDR2_CONFIG are + * unreliable. They cannot always be read back since internally + * after power gating values are not restored back to the + * shadow VDR registers. Thus we do not compare the whole state + * just the two VDR registers. + */ + if (a->config[0] == b->config[0] && + a->config[2] == b->config[2]) + return true; - return true; + return false; } void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, @@ -2222,7 +2232,7 @@ void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, { u8 owned_lane_mask; u8 lane; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; int i, j, k; pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); @@ -2259,8 +2269,6 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state, struct intel_encoder *encoder; struct intel_lt_phy_pll_state pll_hw_state = {}; const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll; - int clock; - int i, j; if (DISPLAY_VER(display) < 35) return; @@ -2275,33 +2283,19 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state, encoder = intel_get_crtc_new_encoder(state, new_crtc_state); intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state); - clock = intel_lt_phy_calc_port_clock(encoder, new_crtc_state); dig_port = enc_to_dig_port(encoder); if (intel_tc_port_in_tbt_alt_mode(dig_port)) return; - INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.clock != clock, - "[CRTC:%d:%s] mismatch in LT PHY: Register CLOCK (expected %d, found %d)", + INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0], + "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)", crtc->base.base.id, crtc->base.name, - pll_sw_state->clock, pll_hw_state.clock); - - for (i = 0; i < 3; i++) { - INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[i] != pll_sw_state->config[i], - "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG%d: (expected 0x%04x, found 0x%04x)", - crtc->base.base.id, crtc->base.name, i, - pll_sw_state->config[i], pll_hw_state.config[i]); - } - - for (i = 0; i <= 12; i++) { - for (j = 3; j >= 0; j--) - INTEL_DISPLAY_STATE_WARN(display, - pll_hw_state.data[i][j] != - pll_sw_state->data[i][j], - "[CRTC:%d:%s] mismatch in LT PHY PLL DATA[%d][%d]: (expected 0x%04x, found 0x%04x)", - crtc->base.base.id, crtc->base.name, i, j, - pll_sw_state->data[i][j], pll_hw_state.data[i][j]); - } + pll_sw_state->config[0], pll_hw_state.config[0]); + INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2], + "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)", + crtc->base.base.id, crtc->base.name, + pll_sw_state->config[2], pll_hw_state.config[2]); } void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, @@ -2310,7 +2304,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); if (intel_tc_port_in_tbt_alt_mode(dig_port)) - intel_mtl_tbt_pll_enable(encoder, crtc_state); + intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); else intel_lt_phy_pll_enable(encoder, crtc_state); } @@ -2320,7 +2314,7 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) struct intel_digital_port *dig_port = enc_to_dig_port(encoder); if (intel_tc_port_in_tbt_alt_mode(dig_port)) - intel_mtl_tbt_pll_disable(encoder); + intel_mtl_tbt_pll_disable_clock(encoder); else intel_lt_phy_pll_disable(encoder); diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h index b7911acd7dcda..bf41858f1bc37 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h @@ -1,5 +1,5 @@ -/* SPDX-License-Identifier: MIT - * +/* SPDX-License-Identifier: MIT */ +/* * Copyright © 2025 Intel Corporation */ @@ -42,6 +42,4 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); -#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35) - #endif /* __INTEL_LT_PHY_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h index 98ccc069a69b9..37e46fb9abde4 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h @@ -1,5 +1,5 @@ -/* SPDX-License-Identifier: MIT - * +/* SPDX-License-Identifier: MIT */ +/* * Copyright © 2025 Intel Corporation */ diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 89aeb4fb340e6..457d608635364 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -105,7 +105,7 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, { struct intel_display *display = to_intel_display(encoder); struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; wakeref = intel_display_power_get_if_enabled(display, encoder->power_domain); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 0dcb0597879a2..d10cbf69a5f8e 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -940,7 +940,7 @@ void intel_modeset_setup_hw_state(struct intel_display *display, { struct intel_encoder *encoder; struct intel_crtc *crtc; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index b361a77cd235c..12a00121c274f 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state, verify_crtc_state(state, crtc); intel_dpll_state_verify(state, crtc); intel_mpllb_state_verify(state, crtc); - intel_cx0pll_state_verify(state, crtc); intel_lt_phy_pll_state_verify(state, crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_panic.c b/drivers/gpu/drm/i915/display/intel_panic.c deleted file mode 100644 index 7311ce4e8b6c3..0000000000000 --- a/drivers/gpu/drm/i915/display/intel_panic.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: MIT -/* Copyright © 2025 Intel Corporation */ - -#include - -#include "gem/i915_gem_object.h" -#include "intel_display_types.h" -#include "intel_fb.h" -#include "intel_panic.h" - -struct intel_panic *intel_panic_alloc(void) -{ - return i915_gem_object_alloc_panic(); -} - -int intel_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb) -{ - struct intel_framebuffer *fb = sb->private; - struct drm_gem_object *obj = intel_fb_bo(&fb->base); - - return i915_gem_object_panic_setup(panic, sb, obj, fb->panic_tiling); -} - -void intel_panic_finish(struct intel_panic *panic) -{ - return i915_gem_object_panic_finish(panic); -} diff --git a/drivers/gpu/drm/i915/display/intel_panic.h b/drivers/gpu/drm/i915/display/intel_panic.h deleted file mode 100644 index afb472e924aa7..0000000000000 --- a/drivers/gpu/drm/i915/display/intel_panic.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* Copyright © 2025 Intel Corporation */ - -#ifndef __INTEL_PANIC_H__ -#define __INTEL_PANIC_H__ - -struct drm_scanout_buffer; -struct intel_panic; - -struct intel_panic *intel_panic_alloc(void); -int intel_panic_setup(struct intel_panic *panic, struct drm_scanout_buffer *sb); -void intel_panic_finish(struct intel_panic *panic); - -#endif /* __INTEL_PANIC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c new file mode 100644 index 0000000000000..72ae553f79a4a --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_parent.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: MIT +/* Copyright © 2025 Intel Corporation */ + +/* + * Convenience wrapper functions to call the parent interface functions: + * + * - display->parent->SUBSTRUCT->FUNCTION() + * - display->parent->FUNCTION() + * + * All functions here should be named accordingly: + * + * - intel_parent_SUBSTRUCT_FUNCTION() + * - intel_parent_FUNCTION() + * + * These functions may use display driver specific types for parameters and + * return values, translating them to and from the generic types used in the + * function pointer interface. + */ + +#include +#include + +#include "intel_display_core.h" +#include "intel_parent.h" + +/* hdcp */ +ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display, + struct intel_hdcp_gsc_context *gsc_context, + void *msg_in, size_t msg_in_len, + void *msg_out, size_t msg_out_len) +{ + return display->parent->hdcp->gsc_msg_send(gsc_context, msg_in, msg_in_len, msg_out, msg_out_len); +} + +bool intel_parent_hdcp_gsc_check_status(struct intel_display *display) +{ + return display->parent->hdcp->gsc_check_status(display->drm); +} + +struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display) +{ + return display->parent->hdcp->gsc_context_alloc(display->drm); +} + +void intel_parent_hdcp_gsc_context_free(struct intel_display *display, + struct intel_hdcp_gsc_context *gsc_context) +{ + display->parent->hdcp->gsc_context_free(gsc_context); +} + +/* irq */ +bool intel_parent_irq_enabled(struct intel_display *display) +{ + return display->parent->irq->enabled(display->drm); +} + +void intel_parent_irq_synchronize(struct intel_display *display) +{ + display->parent->irq->synchronize(display->drm); +} + +/* panic */ +struct intel_panic *intel_parent_panic_alloc(struct intel_display *display) +{ + return display->parent->panic->alloc(); +} + +int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb) +{ + return display->parent->panic->setup(panic, sb); +} + +void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic) +{ + display->parent->panic->finish(panic); +} + +/* pc8 */ +void intel_parent_pc8_block(struct intel_display *display) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8)) + return; + + display->parent->pc8->block(display->drm); +} + +void intel_parent_pc8_unblock(struct intel_display *display) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->pc8)) + return; + + display->parent->pc8->unblock(display->drm); +} + +/* rps */ +bool intel_parent_rps_available(struct intel_display *display) +{ + return display->parent->rps; +} + +void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence) +{ + if (display->parent->rps) + display->parent->rps->boost_if_not_started(fence); +} + +void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive) +{ + if (display->parent->rps) + display->parent->rps->mark_interactive(display->drm, interactive); +} + +void intel_parent_rps_ilk_irq_handler(struct intel_display *display) +{ + if (display->parent->rps) + display->parent->rps->ilk_irq_handler(display->drm); +} + +/* stolen */ +int intel_parent_stolen_insert_node_in_range(struct intel_display *display, + struct intel_stolen_node *node, u64 size, + unsigned int align, u64 start, u64 end) +{ + return display->parent->stolen->insert_node_in_range(node, size, align, start, end); +} + +int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size, + unsigned int align) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->insert_node)) + return -ENODEV; + + return display->parent->stolen->insert_node(node, size, align); +} + +void intel_parent_stolen_remove_node(struct intel_display *display, + struct intel_stolen_node *node) +{ + display->parent->stolen->remove_node(node); +} + +bool intel_parent_stolen_initialized(struct intel_display *display) +{ + return display->parent->stolen->initialized(display->drm); +} + +bool intel_parent_stolen_node_allocated(struct intel_display *display, + const struct intel_stolen_node *node) +{ + return display->parent->stolen->node_allocated(node); +} + +u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node) +{ + return display->parent->stolen->node_offset(node); +} + +u64 intel_parent_stolen_area_address(struct intel_display *display) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_address)) + return 0; + + return display->parent->stolen->area_address(display->drm); +} + +u64 intel_parent_stolen_area_size(struct intel_display *display) +{ + if (drm_WARN_ON_ONCE(display->drm, !display->parent->stolen->area_size)) + return 0; + + return display->parent->stolen->area_size(display->drm); +} + +u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node) +{ + return display->parent->stolen->node_address(node); +} + +u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node) +{ + return display->parent->stolen->node_size(node); +} + +struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display) +{ + return display->parent->stolen->node_alloc(display->drm); +} + +void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node) +{ + display->parent->stolen->node_free(node); +} + +/* generic */ +void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence) +{ + if (display->parent->fence_priority_display) + display->parent->fence_priority_display(fence); +} + +bool intel_parent_has_auxccs(struct intel_display *display) +{ + return display->parent->has_auxccs && display->parent->has_auxccs(display->drm); +} + +bool intel_parent_has_fenced_regions(struct intel_display *display) +{ + return display->parent->has_fenced_regions && display->parent->has_fenced_regions(display->drm); +} + +bool intel_parent_vgpu_active(struct intel_display *display) +{ + return display->parent->vgpu_active && display->parent->vgpu_active(display->drm); +} diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h new file mode 100644 index 0000000000000..47cdc14f9aa28 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_parent.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2025 Intel Corporation */ + +#ifndef __INTEL_PARENT_H__ +#define __INTEL_PARENT_H__ + +#include + +struct dma_fence; +struct drm_scanout_buffer; +struct intel_display; +struct intel_hdcp_gsc_context; +struct intel_panic; +struct intel_stolen_node; + +/* hdcp */ +ssize_t intel_parent_hdcp_gsc_msg_send(struct intel_display *display, + struct intel_hdcp_gsc_context *gsc_context, + void *msg_in, size_t msg_in_len, + void *msg_out, size_t msg_out_len); +bool intel_parent_hdcp_gsc_check_status(struct intel_display *display); +struct intel_hdcp_gsc_context *intel_parent_hdcp_gsc_context_alloc(struct intel_display *display); +void intel_parent_hdcp_gsc_context_free(struct intel_display *display, + struct intel_hdcp_gsc_context *gsc_context); + +/* irq */ +bool intel_parent_irq_enabled(struct intel_display *display); +void intel_parent_irq_synchronize(struct intel_display *display); + +/* panic */ +struct intel_panic *intel_parent_panic_alloc(struct intel_display *display); +int intel_parent_panic_setup(struct intel_display *display, struct intel_panic *panic, struct drm_scanout_buffer *sb); +void intel_parent_panic_finish(struct intel_display *display, struct intel_panic *panic); + +/* pc8 */ +void intel_parent_pc8_block(struct intel_display *display); +void intel_parent_pc8_unblock(struct intel_display *display); + +/* rps */ +bool intel_parent_rps_available(struct intel_display *display); +void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence); +void intel_parent_rps_mark_interactive(struct intel_display *display, bool interactive); +void intel_parent_rps_ilk_irq_handler(struct intel_display *display); + +/* stolen */ +int intel_parent_stolen_insert_node_in_range(struct intel_display *display, + struct intel_stolen_node *node, u64 size, + unsigned int align, u64 start, u64 end); +int intel_parent_stolen_insert_node(struct intel_display *display, struct intel_stolen_node *node, u64 size, + unsigned int align); +void intel_parent_stolen_remove_node(struct intel_display *display, + struct intel_stolen_node *node); +bool intel_parent_stolen_initialized(struct intel_display *display); +bool intel_parent_stolen_node_allocated(struct intel_display *display, + const struct intel_stolen_node *node); +u32 intel_parent_stolen_node_offset(struct intel_display *display, struct intel_stolen_node *node); +u64 intel_parent_stolen_area_address(struct intel_display *display); +u64 intel_parent_stolen_area_size(struct intel_display *display); +u64 intel_parent_stolen_node_address(struct intel_display *display, struct intel_stolen_node *node); +u64 intel_parent_stolen_node_size(struct intel_display *display, const struct intel_stolen_node *node); +struct intel_stolen_node *intel_parent_stolen_node_alloc(struct intel_display *display); +void intel_parent_stolen_node_free(struct intel_display *display, const struct intel_stolen_node *node); + +/* generic */ +bool intel_parent_has_auxccs(struct intel_display *display); +bool intel_parent_has_fenced_regions(struct intel_display *display); +bool intel_parent_vgpu_active(struct intel_display *display); +void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence); + +#endif /* __INTEL_PARENT_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 1f27643412f13..57586c78582da 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -30,13 +30,12 @@ #include -#include "i915_drv.h" -#include "i915_irq.h" #include "intel_atomic.h" #include "intel_de.h" #include "intel_display_irq.h" #include "intel_display_regs.h" #include "intel_display_types.h" +#include "intel_parent.h" #include "intel_pipe_crc.h" #include "intel_pipe_crc_regs.h" @@ -589,7 +588,7 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) enum intel_display_power_domain power_domain; enum intel_pipe_crc_source source; enum pipe pipe = crtc->pipe; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u32 val = 0; /* shut up gcc */ int ret = 0; bool enable; @@ -658,7 +657,6 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) { struct intel_display *display = to_intel_display(crtc); - struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; enum pipe pipe = crtc->pipe; @@ -669,5 +667,5 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) intel_de_write(display, PIPE_CRC_CTL(display, pipe), 0); intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); - intel_synchronize_irq(dev_priv); + intel_parent_irq_synchronize(display); } diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index ab6a58530b396..3dc2ed52147f6 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -45,7 +45,6 @@ #include #include -#include "gem/i915_gem_object.h" #include "i9xx_plane_regs.h" #include "intel_cdclk.h" #include "intel_cursor.h" @@ -56,7 +55,7 @@ #include "intel_fb.h" #include "intel_fb_pin.h" #include "intel_fbdev.h" -#include "intel_panic.h" +#include "intel_parent.h" #include "intel_plane.h" #include "intel_psr.h" #include "skl_scaler.h" @@ -179,25 +178,29 @@ bool intel_plane_needs_physical(struct intel_plane *plane) DISPLAY_INFO(display)->cursor_needs_physical; } -bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, +bool intel_plane_can_async_flip(struct intel_plane *plane, + const struct drm_format_info *info, u64 modifier) { - if (intel_format_info_is_yuv_semiplanar(drm_format_info(format), modifier) || - format == DRM_FORMAT_C8) + if (intel_format_info_is_yuv_semiplanar(info, modifier) || + info->format == DRM_FORMAT_C8) return false; return plane->can_async_flip && plane->can_async_flip(modifier); } -bool intel_plane_format_mod_supported_async(struct drm_plane *plane, - u32 format, - u64 modifier) +bool intel_plane_format_mod_supported_async(struct drm_plane *_plane, + u32 format, u64 modifier) { - if (!plane->funcs->format_mod_supported(plane, format, modifier)) + struct intel_plane *plane = to_intel_plane(_plane); + const struct drm_format_info *info; + + if (!plane->base.funcs->format_mod_supported(&plane->base, format, modifier)) return false; - return intel_plane_can_async_flip(to_intel_plane(plane), - format, modifier); + info = drm_get_format_info(plane->base.dev, format, modifier); + + return intel_plane_can_async_flip(plane, info, modifier); } unsigned int intel_adjusted_rate(const struct drm_rect *src, @@ -651,11 +654,10 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state)) new_crtc_state->disable_cxsr = true; - if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) { + if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) new_crtc_state->do_async_flip = true; - new_crtc_state->async_flip_planes |= BIT(plane->id); - } else if (plane->need_async_flip_toggle_wa && - new_crtc_state->uapi.async_flip) { + + if (new_crtc_state->uapi.async_flip) { /* * On platforms with double buffered async flip bit we * set the bit already one frame early during the sync @@ -663,6 +665,9 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr * hardware will therefore be ready to perform a real * async flip during the next commit, without having * to wait yet another frame for the bit to latch. + * + * async_flip_planes bitmask is also used by selective + * fetch calculation to choose full frame update. */ new_crtc_state->async_flip_planes |= BIT(plane->id); } @@ -1235,8 +1240,7 @@ intel_prepare_plane_fb(struct drm_plane *_plane, goto unpin_fb; if (new_plane_state->uapi.fence) { - i915_gem_fence_wait_priority_display(new_plane_state->uapi.fence); - + intel_parent_fence_priority_display(display, new_plane_state->uapi.fence); intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc, new_plane_state->uapi.fence); } @@ -1330,33 +1334,33 @@ static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, u return offset; } -static void intel_panic_flush(struct drm_plane *plane) +static void intel_panic_flush(struct drm_plane *_plane) { - struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); - struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state); - struct intel_plane *iplane = to_intel_plane(plane); - struct intel_display *display = to_intel_display(iplane); - struct drm_framebuffer *fb = plane_state->hw.fb; - struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); + struct intel_plane *plane = to_intel_plane(_plane); + struct intel_display *display = to_intel_display(plane); + const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); + struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); + const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); + const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); - intel_panic_finish(intel_fb->panic); + intel_parent_panic_finish(display, fb->panic); if (crtc_state->enable_psr2_sel_fetch) { /* Force a full update for psr2 */ - intel_psr2_panic_force_full_update(display, crtc_state); + intel_psr2_panic_force_full_update(crtc_state); } /* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/ - if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { + if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { struct iosys_map map; intel_fbdev_get_map(display->fbdev.fbdev, &map); - drm_clflush_virt_range(map.vaddr, fb->pitches[0] * fb->height); + drm_clflush_virt_range(map.vaddr, fb->base.pitches[0] * fb->base.height); return; } - if (fb->modifier && iplane->disable_tiling) - iplane->disable_tiling(iplane); + if (fb->base.modifier != DRM_FORMAT_MOD_LINEAR && plane->disable_tiling) + plane->disable_tiling(plane); } static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width, @@ -1394,45 +1398,43 @@ static int intel_get_scanout_buffer(struct drm_plane *plane, { struct intel_plane_state *plane_state; struct drm_gem_object *obj; - struct drm_framebuffer *fb; - struct intel_framebuffer *intel_fb; + struct intel_framebuffer *fb; struct intel_display *display = to_intel_display(plane->dev); if (!plane->state || !plane->state->fb || !plane->state->visible) return -ENODEV; plane_state = to_intel_plane_state(plane->state); - fb = plane_state->hw.fb; - intel_fb = to_intel_framebuffer(fb); + fb = to_intel_framebuffer(plane_state->hw.fb); - obj = intel_fb_bo(fb); + obj = intel_fb_bo(&fb->base); if (!obj) return -ENODEV; - if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { + if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { intel_fbdev_get_map(display->fbdev.fbdev, &sb->map[0]); } else { int ret; /* Can't disable tiling if DPT is in use */ - if (intel_fb_uses_dpt(fb)) { - if (fb->format->cpp[0] != 4) + if (intel_fb_uses_dpt(&fb->base)) { + if (fb->base.format->cpp[0] != 4) return -EOPNOTSUPP; - intel_fb->panic_tiling = intel_get_tiling_func(fb->modifier); - if (!intel_fb->panic_tiling) + fb->panic_tiling = intel_get_tiling_func(fb->base.modifier); + if (!fb->panic_tiling) return -EOPNOTSUPP; } - sb->private = intel_fb; - ret = intel_panic_setup(intel_fb->panic, sb); + sb->private = fb; + ret = intel_parent_panic_setup(display, fb->panic, sb); if (ret) return ret; } - sb->width = fb->width; - sb->height = fb->height; + sb->width = fb->base.width; + sb->height = fb->base.height; /* Use the generic linear format, because tiling, RC, CCS, CC * will be disabled in disable_tiling() */ - sb->format = drm_format_info(fb->format->format); - sb->pitch[0] = fb->pitches[0]; + sb->format = drm_format_info(fb->base.format->format); + sb->pitch[0] = fb->base.pitches[0]; return 0; } @@ -1464,7 +1466,7 @@ void intel_plane_init_cursor_vblank_work(struct intel_plane_state *old_plane_sta old_plane_state->ggtt_vma == new_plane_state->ggtt_vma) return; - drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->uapi.crtc, + drm_vblank_work_init(&old_plane_state->unpin_work, old_plane_state->hw.crtc, intel_cursor_unpin_work); } diff --git a/drivers/gpu/drm/i915/display/intel_plane.h b/drivers/gpu/drm/i915/display/intel_plane.h index 4e99df9de3e89..5a8f2f3baab5f 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.h +++ b/drivers/gpu/drm/i915/display/intel_plane.h @@ -8,6 +8,7 @@ #include +struct drm_format_info; struct drm_plane; struct drm_property; struct drm_rect; @@ -21,7 +22,8 @@ enum plane_id; struct intel_plane * intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id); -bool intel_plane_can_async_flip(struct intel_plane *plane, u32 format, +bool intel_plane_can_async_flip(struct intel_plane *plane, + const struct drm_format_info *info, u64 modifier); unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c deleted file mode 100644 index a1de1ec564d1f..0000000000000 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ /dev/null @@ -1,440 +0,0 @@ -// SPDX-License-Identifier: MIT -/* - * Copyright © 2021 Intel Corporation - */ - -#include - -#include "gem/i915_gem_lmem.h" -#include "gem/i915_gem_region.h" -#include "i915_drv.h" -#include "intel_crtc.h" -#include "intel_display.h" -#include "intel_display_core.h" -#include "intel_display_types.h" -#include "intel_fb.h" -#include "intel_frontbuffer.h" -#include "intel_plane.h" -#include "intel_plane_initial.h" - -void intel_plane_initial_vblank_wait(struct intel_crtc *crtc) -{ - intel_crtc_wait_for_next_vblank(crtc); -} - -static bool -intel_reuse_initial_plane_obj(struct intel_crtc *this, - const struct intel_initial_plane_config plane_configs[], - struct drm_framebuffer **fb, - struct i915_vma **vma) -{ - struct intel_display *display = to_intel_display(this); - struct intel_crtc *crtc; - - for_each_intel_crtc(display->drm, crtc) { - struct intel_plane *plane = - to_intel_plane(crtc->base.primary); - const struct intel_plane_state *plane_state = - to_intel_plane_state(plane->base.state); - const struct intel_crtc_state *crtc_state = - to_intel_crtc_state(crtc->base.state); - - if (!crtc_state->uapi.active) - continue; - - if (!plane_state->ggtt_vma) - continue; - - if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) { - *fb = plane_state->hw.fb; - *vma = plane_state->ggtt_vma; - return true; - } - } - - return false; -} - -static enum intel_memory_type -initial_plane_memory_type(struct intel_display *display) -{ - struct drm_i915_private *i915 = to_i915(display->drm); - - if (display->platform.dgfx) - return INTEL_MEMORY_LOCAL; - else if (HAS_LMEMBAR_SMEM_STOLEN(i915)) - return INTEL_MEMORY_STOLEN_LOCAL; - else - return INTEL_MEMORY_STOLEN_SYSTEM; -} - -static bool -initial_plane_phys(struct intel_display *display, - struct intel_initial_plane_config *plane_config) -{ - struct drm_i915_private *i915 = to_i915(display->drm); - struct i915_ggtt *ggtt = to_gt(i915)->ggtt; - struct intel_memory_region *mem; - enum intel_memory_type mem_type; - bool is_present, is_local; - dma_addr_t dma_addr; - u32 base; - - mem_type = initial_plane_memory_type(display); - mem = intel_memory_region_by_type(i915, mem_type); - if (!mem) { - drm_dbg_kms(display->drm, - "Initial plane memory region (type %s) not initialized\n", - intel_memory_type_str(mem_type)); - return false; - } - - base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); - - dma_addr = intel_ggtt_read_entry(&ggtt->vm, base, &is_present, &is_local); - - if (!is_present) { - drm_err(display->drm, - "Initial plane FB PTE not present\n"); - return false; - } - - if (intel_memory_type_is_local(mem->type) != is_local) { - drm_err(display->drm, - "Initial plane FB PTE unsuitable for %s\n", - mem->region.name); - return false; - } - - if (dma_addr < mem->region.start || dma_addr > mem->region.end) { - drm_err(display->drm, - "Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n", - &dma_addr, mem->region.name, &mem->region.start, &mem->region.end); - return false; - } - - drm_dbg(display->drm, - "Using dma_addr=%pa, based on initial plane programming\n", - &dma_addr); - - plane_config->phys_base = dma_addr - mem->region.start; - plane_config->mem = mem; - - return true; -} - -static struct i915_vma * -initial_plane_vma(struct intel_display *display, - struct intel_initial_plane_config *plane_config) -{ - struct drm_i915_private *i915 = to_i915(display->drm); - struct intel_memory_region *mem; - struct drm_i915_gem_object *obj; - struct drm_mm_node orig_mm = {}; - struct i915_vma *vma; - resource_size_t phys_base; - unsigned int tiling; - u32 base, size; - u64 pinctl; - - if (plane_config->size == 0) - return NULL; - - if (!initial_plane_phys(display, plane_config)) - return NULL; - - phys_base = plane_config->phys_base; - mem = plane_config->mem; - - base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT); - size = round_up(plane_config->base + plane_config->size, - mem->min_page_size); - size -= base; - - /* - * If the FB is too big, just don't use it since fbdev is not very - * important and we should probably use that space with FBC or other - * features. - */ - if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && - mem == i915->mm.stolen_region && - size * 2 > i915->dsm.usable_size) { - drm_dbg_kms(display->drm, "Initial FB size exceeds half of stolen, discarding\n"); - return NULL; - } - - obj = i915_gem_object_create_region_at(mem, phys_base, size, - I915_BO_ALLOC_USER | - I915_BO_PREALLOC); - if (IS_ERR(obj)) { - drm_dbg_kms(display->drm, "Failed to preallocate initial FB in %s\n", - mem->region.name); - return NULL; - } - - /* - * Mark it WT ahead of time to avoid changing the - * cache_level during fbdev initialization. The - * unbind there would get stuck waiting for rcu. - */ - i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ? - I915_CACHE_WT : I915_CACHE_NONE); - - tiling = intel_fb_modifier_to_tiling(plane_config->fb->base.modifier); - - switch (tiling) { - case I915_TILING_NONE: - break; - case I915_TILING_X: - case I915_TILING_Y: - obj->tiling_and_stride = - plane_config->fb->base.pitches[0] | - tiling; - break; - default: - MISSING_CASE(tiling); - goto err_obj; - } - - /* - * MTL GOP likes to place the framebuffer high up in ggtt, - * which can cause problems for ggtt_reserve_guc_top(). - * Try to pin it to a low ggtt address instead to avoid that. - */ - base = 0; - - if (base != plane_config->base) { - struct i915_ggtt *ggtt = to_gt(i915)->ggtt; - int ret; - - /* - * Make sure the original and new locations - * can't overlap. That would corrupt the original - * PTEs which are still being used for scanout. - */ - ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &orig_mm, - size, plane_config->base, - I915_COLOR_UNEVICTABLE, PIN_NOEVICT); - if (ret) - goto err_obj; - } - - vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL); - if (IS_ERR(vma)) - goto err_obj; - -retry: - pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base; - if (!i915_gem_object_is_lmem(obj)) - pinctl |= PIN_MAPPABLE; - if (i915_vma_pin(vma, 0, 0, pinctl)) { - if (drm_mm_node_allocated(&orig_mm)) { - drm_mm_remove_node(&orig_mm); - /* - * Try again, but this time pin - * it to its original location. - */ - base = plane_config->base; - goto retry; - } - goto err_obj; - } - - if (i915_gem_object_is_tiled(obj) && - !i915_vma_is_map_and_fenceable(vma)) - goto err_obj; - - if (drm_mm_node_allocated(&orig_mm)) - drm_mm_remove_node(&orig_mm); - - drm_dbg_kms(display->drm, - "Initial plane fb bound to 0x%x in the ggtt (original 0x%x)\n", - i915_ggtt_offset(vma), plane_config->base); - - return vma; - -err_obj: - if (drm_mm_node_allocated(&orig_mm)) - drm_mm_remove_node(&orig_mm); - i915_gem_object_put(obj); - return NULL; -} - -static bool -intel_alloc_initial_plane_obj(struct intel_crtc *crtc, - struct intel_initial_plane_config *plane_config) -{ - struct intel_display *display = to_intel_display(crtc); - struct drm_mode_fb_cmd2 mode_cmd = {}; - struct drm_framebuffer *fb = &plane_config->fb->base; - struct i915_vma *vma; - - switch (fb->modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_4_TILED: - break; - default: - drm_dbg(display->drm, - "Unsupported modifier for initial FB: 0x%llx\n", - fb->modifier); - return false; - } - - vma = initial_plane_vma(display, plane_config); - if (!vma) - return false; - - mode_cmd.pixel_format = fb->format->format; - mode_cmd.width = fb->width; - mode_cmd.height = fb->height; - mode_cmd.pitches[0] = fb->pitches[0]; - mode_cmd.modifier[0] = fb->modifier; - mode_cmd.flags = DRM_MODE_FB_MODIFIERS; - - if (intel_framebuffer_init(to_intel_framebuffer(fb), - intel_bo_to_drm_bo(vma->obj), - fb->format, &mode_cmd)) { - drm_dbg_kms(display->drm, "intel fb init failed\n"); - goto err_vma; - } - - plane_config->vma = vma; - return true; - -err_vma: - i915_vma_put(vma); - return false; -} - -static void -intel_find_initial_plane_obj(struct intel_crtc *crtc, - struct intel_initial_plane_config plane_configs[]) -{ - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_initial_plane_config *plane_config = - &plane_configs[crtc->pipe]; - struct intel_plane *plane = - to_intel_plane(crtc->base.primary); - struct intel_plane_state *plane_state = - to_intel_plane_state(plane->base.state); - struct drm_framebuffer *fb; - struct i915_vma *vma; - - /* - * TODO: - * Disable planes if get_initial_plane_config() failed. - * Make sure things work if the surface base is not page aligned. - */ - if (!plane_config->fb) - return; - - if (intel_alloc_initial_plane_obj(crtc, plane_config)) { - fb = &plane_config->fb->base; - vma = plane_config->vma; - goto valid_fb; - } - - /* - * Failed to alloc the obj, check to see if we should share - * an fb with another CRTC instead - */ - if (intel_reuse_initial_plane_obj(crtc, plane_configs, &fb, &vma)) - goto valid_fb; - - /* - * We've failed to reconstruct the BIOS FB. Current display state - * indicates that the primary plane is visible, but has a NULL FB, - * which will lead to problems later if we don't fix it up. The - * simplest solution is to just disable the primary plane now and - * pretend the BIOS never had it enabled. - */ - intel_plane_disable_noatomic(crtc, plane); - - return; - -valid_fb: - plane_state->uapi.rotation = plane_config->rotation; - intel_fb_fill_view(to_intel_framebuffer(fb), - plane_state->uapi.rotation, &plane_state->view); - - __i915_vma_pin(vma); - plane_state->ggtt_vma = i915_vma_get(vma); - if (intel_plane_uses_fence(plane_state) && - i915_vma_pin_fence(vma) == 0 && vma->fence) - plane_state->flags |= PLANE_HAS_FENCE; - - plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma); - - plane_state->uapi.src_x = 0; - plane_state->uapi.src_y = 0; - plane_state->uapi.src_w = fb->width << 16; - plane_state->uapi.src_h = fb->height << 16; - - plane_state->uapi.crtc_x = 0; - plane_state->uapi.crtc_y = 0; - plane_state->uapi.crtc_w = fb->width; - plane_state->uapi.crtc_h = fb->height; - - if (fb->modifier != DRM_FORMAT_MOD_LINEAR) - dev_priv->preserve_bios_swizzle = true; - - plane_state->uapi.fb = fb; - drm_framebuffer_get(fb); - - plane_state->uapi.crtc = &crtc->base; - intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc); - - atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); -} - -static void plane_config_fini(struct intel_initial_plane_config *plane_config) -{ - if (plane_config->fb) { - struct drm_framebuffer *fb = &plane_config->fb->base; - - /* We may only have the stub and not a full framebuffer */ - if (drm_framebuffer_read_refcount(fb)) - drm_framebuffer_put(fb); - else - kfree(fb); - } - - if (plane_config->vma) - i915_vma_put(plane_config->vma); -} - -void intel_initial_plane_config(struct intel_display *display) -{ - struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; - struct intel_crtc *crtc; - - for_each_intel_crtc(display->drm, crtc) { - struct intel_initial_plane_config *plane_config = - &plane_configs[crtc->pipe]; - - if (!to_intel_crtc_state(crtc->base.state)->uapi.active) - continue; - - /* - * Note that reserving the BIOS fb up front prevents us - * from stuffing other stolen allocations like the ring - * on top. This prevents some ugliness at boot time, and - * can even allow for smooth boot transitions if the BIOS - * fb is large enough for the active pipe configuration. - */ - display->funcs.display->get_initial_plane_config(crtc, plane_config); - - /* - * If the fb is shared between multiple heads, we'll - * just get the first one. - */ - intel_find_initial_plane_obj(crtc, plane_configs); - - if (display->funcs.display->fixup_initial_plane_config(crtc, plane_config)) - intel_plane_initial_vblank_wait(crtc); - - plane_config_fini(plane_config); - } -} diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 25692a5477648..b217ec7aa7589 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -67,10 +67,10 @@ static const char *pps_name(struct intel_dp *intel_dp) return "PPS "; } -intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp) +struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; /* * See vlv_pps_reset_all() why we need a power domain reference here. @@ -81,8 +81,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp) return wakeref; } -intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, - intel_wakeref_t wakeref) +struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref) { struct intel_display *display = to_intel_display(intel_dp); @@ -697,12 +696,10 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp) void intel_pps_wait_power_cycle(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - if (!intel_dp_is_edp(intel_dp)) return; - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) wait_panel_power_cycle(intel_dp); } @@ -811,14 +808,13 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) void intel_pps_vdd_on(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - intel_wakeref_t wakeref; bool vdd; if (!intel_dp_is_edp(intel_dp)) return; vdd = false; - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) vdd = intel_pps_vdd_on_unlocked(intel_dp); INTEL_DISPLAY_STATE_WARN(display, !vdd, "[ENCODER:%d:%s] %s VDD already requested on\n", dp_to_dig_port(intel_dp)->base.base.base.id, @@ -873,8 +869,6 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) void intel_pps_vdd_off_sync(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - if (!intel_dp_is_edp(intel_dp)) return; @@ -883,7 +877,7 @@ void intel_pps_vdd_off_sync(struct intel_dp *intel_dp) * vdd might still be enabled due to the delayed vdd off. * Make sure vdd is actually turned off here. */ - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) intel_pps_vdd_off_sync_unlocked(intel_dp); } @@ -892,9 +886,8 @@ static void edp_panel_vdd_work(struct work_struct *__work) struct intel_pps *pps = container_of(to_delayed_work(__work), struct intel_pps, panel_vdd_work); struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps); - intel_wakeref_t wakeref; - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { if (!intel_dp->pps.want_panel_vdd) intel_pps_vdd_off_sync_unlocked(intel_dp); } @@ -952,12 +945,10 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync) void intel_pps_vdd_off(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - if (!intel_dp_is_edp(intel_dp)) return; - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) intel_pps_vdd_off_unlocked(intel_dp, false); } @@ -1026,12 +1017,10 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp) void intel_pps_on(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - if (!intel_dp_is_edp(intel_dp)) return; - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) intel_pps_on_unlocked(intel_dp); } @@ -1082,12 +1071,10 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp) void intel_pps_off(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - if (!intel_dp_is_edp(intel_dp)) return; - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) intel_pps_off_unlocked(intel_dp); } @@ -1095,7 +1082,6 @@ void intel_pps_off(struct intel_dp *intel_dp) void intel_pps_backlight_on(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - intel_wakeref_t wakeref; /* * If we enable the backlight right away following a panel power @@ -1105,7 +1091,7 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp) */ wait_backlight_on(intel_dp); - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); u32 pp; @@ -1121,12 +1107,11 @@ void intel_pps_backlight_on(struct intel_dp *intel_dp) void intel_pps_backlight_off(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - intel_wakeref_t wakeref; if (!intel_dp_is_edp(intel_dp)) return; - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); u32 pp; @@ -1149,11 +1134,10 @@ void intel_pps_backlight_power(struct intel_connector *connector, bool enable) { struct intel_display *display = to_intel_display(connector); struct intel_dp *intel_dp = intel_attached_dp(connector); - intel_wakeref_t wakeref; bool is_enabled; is_enabled = false; - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE; if (is_enabled == enable) return; @@ -1251,9 +1235,7 @@ void vlv_pps_pipe_init(struct intel_dp *intel_dp) /* Call on all DP, not just eDP */ void vlv_pps_pipe_reset(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) intel_dp->pps.vlv_active_pipe = vlv_active_pipe(intel_dp); } @@ -1329,9 +1311,7 @@ void vlv_pps_port_disable(struct intel_encoder *encoder, { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - intel_wakeref_t wakeref; - - with_intel_pps_lock(intel_dp, wakeref) + with_intel_pps_lock(intel_dp) intel_dp->pps.vlv_active_pipe = INVALID_PIPE; } @@ -1362,10 +1342,9 @@ static void pps_vdd_init(struct intel_dp *intel_dp) bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; bool have_power = false; - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { have_power = edp_have_panel_power(intel_dp) || edp_have_panel_vdd(intel_dp); } @@ -1692,12 +1671,11 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd void intel_pps_encoder_reset(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); - intel_wakeref_t wakeref; if (!intel_dp_is_edp(intel_dp)) return; - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { /* * Reinit the power sequencer also on the resume path, in case * BIOS did something nasty with it. @@ -1716,7 +1694,6 @@ void intel_pps_encoder_reset(struct intel_dp *intel_dp) bool intel_pps_init(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; bool ret; intel_dp->pps.initializing = true; @@ -1724,7 +1701,7 @@ bool intel_pps_init(struct intel_dp *intel_dp) pps_init_timestamps(intel_dp); - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { ret = pps_initial_setup(intel_dp); pps_init_delays(intel_dp); @@ -1760,9 +1737,7 @@ static void pps_init_late(struct intel_dp *intel_dp) void intel_pps_init_late(struct intel_dp *intel_dp) { - intel_wakeref_t wakeref; - - with_intel_pps_lock(intel_dp, wakeref) { + with_intel_pps_lock(intel_dp) { /* Reinit delays after per-panel info has been parsed from VBT */ pps_init_late(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_pps.h b/drivers/gpu/drm/i915/display/intel_pps.h index c83007152f07d..f7c96d75be457 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.h +++ b/drivers/gpu/drm/i915/display/intel_pps.h @@ -8,20 +8,22 @@ #include -#include "intel_wakeref.h" - enum pipe; struct intel_connector; struct intel_crtc_state; struct intel_display; struct intel_dp; struct intel_encoder; +struct ref_tracker; + +struct ref_tracker *intel_pps_lock(struct intel_dp *intel_dp); +struct ref_tracker *intel_pps_unlock(struct intel_dp *intel_dp, struct ref_tracker *wakeref); -intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp); -intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref); +#define __with_intel_pps_lock(dp, wf) \ + for (struct ref_tracker *(wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf))) -#define with_intel_pps_lock(dp, wf) \ - for ((wf) = intel_pps_lock(dp); (wf); (wf) = intel_pps_unlock((dp), (wf))) +#define with_intel_pps_lock(dp) \ + __with_intel_pps_lock((dp), __UNIQUE_ID(wakeref)) void intel_pps_backlight_on(struct intel_dp *intel_dp); void intel_pps_backlight_off(struct intel_dp *intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 08bca45739749..62208ffc51016 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -494,82 +494,37 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) return val; } -static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) -{ - u8 su_capability = 0; - - if (intel_dp->psr.sink_panel_replay_su_support) { - if (drm_dp_dpcd_read_byte(&intel_dp->aux, - DP_PANEL_REPLAY_CAP_CAPABILITY, - &su_capability) < 0) - return 0; - } else { - su_capability = intel_dp->psr_dpcd[1]; - } - - return su_capability; -} - -static unsigned int -intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) -{ - return intel_dp->psr.sink_panel_replay_su_support ? - DP_PANEL_REPLAY_CAP_X_GRANULARITY : - DP_PSR2_SU_X_GRANULARITY; -} - -static unsigned int -intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) -{ - return intel_dp->psr.sink_panel_replay_su_support ? - DP_PANEL_REPLAY_CAP_Y_GRANULARITY : - DP_PSR2_SU_Y_GRANULARITY; -} - -/* - * Note: Bits related to granularity are same in panel replay and psr - * registers. Rely on PSR definitions on these "common" bits. - */ -static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) +static void _psr_compute_su_granularity(struct intel_dp *intel_dp, + struct intel_connector *connector) { struct intel_display *display = to_intel_display(intel_dp); ssize_t r; - u16 w; + __le16 w; u8 y; - /* - * TODO: Do we need to take into account panel supporting both PSR and - * Panel replay? - */ - /* * If sink don't have specific granularity requirements set legacy * ones. */ - if (!(intel_dp_get_su_capability(intel_dp) & - DP_PSR2_SU_GRANULARITY_REQUIRED)) { + if (!(connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { /* As PSR2 HW sends full lines, we do not care about x granularity */ - w = 4; + w = cpu_to_le16(4); y = 4; goto exit; } - r = drm_dp_dpcd_read(&intel_dp->aux, - intel_dp_get_su_x_granularity_offset(intel_dp), - &w, 2); - if (r != 2) + r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, sizeof(w)); + if (r != sizeof(w)) drm_dbg_kms(display->drm, "Unable to read selective update x granularity\n"); /* * Spec says that if the value read is 0 the default granularity should * be used instead. */ - if (r != 2 || w == 0) - w = 4; + if (r != sizeof(w) || w == 0) + w = cpu_to_le16(4); - r = drm_dp_dpcd_read(&intel_dp->aux, - intel_dp_get_su_y_granularity_offset(intel_dp), - &y, 1); + r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); if (r != 1) { drm_dbg_kms(display->drm, "Unable to read selective update y granularity\n"); @@ -579,17 +534,17 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) y = 1; exit: - intel_dp->psr.su_w_granularity = w; - intel_dp->psr.su_y_granularity = y; + connector->dp.psr_caps.su_w_granularity = le16_to_cpu(w); + connector->dp.psr_caps.su_y_granularity = y; } static enum intel_panel_replay_dsc_support -compute_pr_dsc_support(struct intel_dp *intel_dp) +compute_pr_dsc_support(struct intel_connector *connector) { u8 pr_dsc_mode; u8 val; - val = intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; + val = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)]; pr_dsc_mode = REG_FIELD_GET8(DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK, val); switch (pr_dsc_mode) { @@ -621,7 +576,31 @@ static const char *panel_replay_dsc_support_str(enum intel_panel_replay_dsc_supp }; } -static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) +static void _panel_replay_compute_su_granularity(struct intel_connector *connector) +{ + u16 w; + u8 y; + + if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & + DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED)) { + w = 4; + y = 4; + goto exit; + } + + /* + * Spec says that if the value read is 0 the default granularity should + * be used instead. + */ + w = le16_to_cpu(*(__le16 *)&connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_X_GRANULARITY)]) ? : 4; + y = connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_Y_GRANULARITY)] ? : 1; + +exit: + connector->dp.panel_replay_caps.su_w_granularity = w; + connector->dp.panel_replay_caps.su_y_granularity = y; +} + +static void _panel_replay_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) { struct intel_display *display = to_intel_display(intel_dp); int ret; @@ -631,11 +610,12 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) return; ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PANEL_REPLAY_CAP_SUPPORT, - &intel_dp->pr_dpcd, sizeof(intel_dp->pr_dpcd)); + &connector->dp.panel_replay_caps.dpcd, + sizeof(connector->dp.panel_replay_caps.dpcd)); if (ret < 0) return; - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & DP_PANEL_REPLAY_SUPPORT)) return; @@ -646,7 +626,7 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) return; } - if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + if (!(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT)) { drm_dbg_kms(display->drm, "Panel doesn't support early transport, eDP Panel Replay not possible\n"); @@ -654,36 +634,40 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) } } + connector->dp.panel_replay_caps.support = true; intel_dp->psr.sink_panel_replay_support = true; - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & - DP_PANEL_REPLAY_SU_SUPPORT) - intel_dp->psr.sink_panel_replay_su_support = true; + if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + DP_PANEL_REPLAY_SU_SUPPORT) { + connector->dp.panel_replay_caps.su_support = true; - intel_dp->psr.sink_panel_replay_dsc_support = compute_pr_dsc_support(intel_dp); + _panel_replay_compute_su_granularity(connector); + } + + connector->dp.panel_replay_caps.dsc_support = compute_pr_dsc_support(connector); drm_dbg_kms(display->drm, "Panel replay %sis supported by panel (in DSC mode: %s)\n", - intel_dp->psr.sink_panel_replay_su_support ? + connector->dp.panel_replay_caps.su_support ? "selective_update " : "", - panel_replay_dsc_support_str(intel_dp->psr.sink_panel_replay_dsc_support)); + panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); } -static void _psr_init_dpcd(struct intel_dp *intel_dp) +static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) { struct intel_display *display = to_intel_display(intel_dp); int ret; - ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, - sizeof(intel_dp->psr_dpcd)); + ret = drm_dp_dpcd_read_data(&intel_dp->aux, DP_PSR_SUPPORT, connector->dp.psr_caps.dpcd, + sizeof(connector->dp.psr_caps.dpcd)); if (ret < 0) return; - if (!intel_dp->psr_dpcd[0]) + if (!connector->dp.psr_caps.dpcd[0]) return; drm_dbg_kms(display->drm, "eDP panel supports PSR version %x\n", - intel_dp->psr_dpcd[0]); + connector->dp.psr_caps.dpcd[0]); if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { drm_dbg_kms(display->drm, @@ -697,13 +681,14 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) return; } + connector->dp.psr_caps.support = true; intel_dp->psr.sink_support = true; - intel_dp->psr.sink_sync_latency = - intel_dp_get_sink_sync_latency(intel_dp); + + connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp); if (DISPLAY_VER(display) >= 9 && - intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { - bool y_req = intel_dp->psr_dpcd[1] & + connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { + bool y_req = connector->dp.psr_caps.dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; /* @@ -717,22 +702,21 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) * Y-coordinate requirement panels we would need to enable * GTC first. */ - intel_dp->psr.sink_psr2_support = y_req && + connector->dp.psr_caps.su_support = y_req && intel_alpm_aux_wake_supported(intel_dp); drm_dbg_kms(display->drm, "PSR2 %ssupported\n", - intel_dp->psr.sink_psr2_support ? "" : "not "); + connector->dp.psr_caps.su_support ? "" : "not "); } + + if (connector->dp.psr_caps.su_support) + _psr_compute_su_granularity(intel_dp, connector); } -void intel_psr_init_dpcd(struct intel_dp *intel_dp) +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) { - _psr_init_dpcd(intel_dp); + _psr_init_dpcd(intel_dp, connector); - _panel_replay_init_dpcd(intel_dp); - - if (intel_dp->psr.sink_psr2_support || - intel_dp->psr.sink_panel_replay_su_support) - intel_dp_get_su_granularity(intel_dp); + _panel_replay_init_dpcd(intel_dp, connector); } static void hsw_psr_setup_aux(struct intel_dp *intel_dp) @@ -772,8 +756,9 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) aux_ctl); } -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay) +static bool psr2_su_region_et_valid(struct intel_connector *connector, bool panel_replay) { + struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_display *display = to_intel_display(intel_dp); if (DISPLAY_VER(display) < 20 || !intel_dp_is_edp(intel_dp) || @@ -781,9 +766,9 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay return false; return panel_replay ? - intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; + connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; } static void _panel_replay_enable_sink(struct intel_dp *intel_dp, @@ -857,7 +842,12 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp, void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp) { - if (CAN_PANEL_REPLAY(intel_dp)) + /* + * NOTE: We might want to trigger mode set when + * disabling/enabling Panel Replay via debugfs interface to + * ensure this bit is cleared/set accordingly. + */ + if (CAN_PANEL_REPLAY(intel_dp) && panel_replay_global_enabled(intel_dp)) drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, DP_PANEL_REPLAY_ENABLE); } @@ -924,7 +914,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) * off-by-one issue that HW has in some cases. */ idle_frames = max(6, connector->panel.vbt.psr.idle_frames); - idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); + idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1); if (drm_WARN_ON(display->drm, idle_frames > 0xf)) idle_frames = 0xf; @@ -1019,10 +1009,11 @@ static int psr2_block_count(struct intel_dp *intel_dp) static u8 frames_before_su_entry(struct intel_dp *intel_dp) { + struct intel_connector *connector = intel_dp->attached_connector; u8 frames_before_su_entry; frames_before_su_entry = max_t(u8, - intel_dp->psr.sink_sync_latency + 1, + connector->dp.psr_caps.sync_latency + 1, 2); /* Entry setup frames must be at least 1 less than frames before SU entry */ @@ -1304,25 +1295,32 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return crtc_state->enable_psr2_sel_fetch = true; } -static bool psr2_granularity_check(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) +static bool psr2_granularity_check(struct intel_crtc_state *crtc_state, + struct intel_connector *connector) { + struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_display *display = to_intel_display(intel_dp); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; u16 y_granularity = 0; + u16 sink_y_granularity = crtc_state->has_panel_replay ? + connector->dp.panel_replay_caps.su_y_granularity : + connector->dp.psr_caps.su_y_granularity; + u16 sink_w_granularity = crtc_state->has_panel_replay ? + connector->dp.panel_replay_caps.su_w_granularity : + connector->dp.psr_caps.su_w_granularity; /* PSR2 HW only send full lines so we only need to validate the width */ - if (crtc_hdisplay % intel_dp->psr.su_w_granularity) + if (crtc_hdisplay % sink_w_granularity) return false; - if (crtc_vdisplay % intel_dp->psr.su_y_granularity) + if (crtc_vdisplay % sink_y_granularity) return false; /* HW tracking is only aligned to 4 lines */ if (!crtc_state->enable_psr2_sel_fetch) - return intel_dp->psr.su_y_granularity == 4; + return sink_y_granularity == 4; /* * adl_p and mtl platforms have 1 line granularity. @@ -1330,11 +1328,11 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp, * to match sink requirement if multiple of 4. */ if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) - y_granularity = intel_dp->psr.su_y_granularity; - else if (intel_dp->psr.su_y_granularity <= 2) + y_granularity = sink_y_granularity; + else if (sink_y_granularity <= 2) y_granularity = 4; - else if ((intel_dp->psr.su_y_granularity % 4) == 0) - y_granularity = intel_dp->psr.su_y_granularity; + else if ((sink_y_granularity % 4) == 0) + y_granularity = sink_y_granularity; if (y_granularity == 0 || crtc_vdisplay % y_granularity) return false; @@ -1372,16 +1370,18 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d } static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, + struct drm_connector_state *conn_state, const struct drm_display_mode *adjusted_mode) { struct intel_display *display = to_intel_display(intel_dp); - int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); + struct intel_connector *connector = to_intel_connector(conn_state->connector); + int psr_setup_time = drm_dp_psr_setup_time(connector->dp.psr_caps.dpcd); int entry_setup_frames = 0; if (psr_setup_time < 0) { drm_dbg_kms(display->drm, "PSR condition failed: Invalid PSR setup time (0x%02x)\n", - intel_dp->psr_dpcd[1]); + connector->dp.psr_caps.dpcd[1]); return -ETIME; } @@ -1522,14 +1522,16 @@ static bool alpm_config_valid(struct intel_dp *intel_dp, } static bool intel_psr2_config_valid(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(intel_dp); + struct intel_connector *connector = to_intel_connector(conn_state->connector); int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; - if (!intel_dp->psr.sink_psr2_support || display->params.enable_psr == 1) + if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1) return false; /* JSL and EHL only supports eDP 1.3 */ @@ -1621,9 +1623,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return true; } -static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) +static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_display *display = to_intel_display(intel_dp); if (HAS_PSR2_SEL_FETCH(display) && @@ -1640,7 +1644,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, goto unsupported; } - if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) + if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state, + conn_state)) goto unsupported; if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) { @@ -1653,11 +1658,11 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, if (DISPLAY_VER(display) < 14) goto unsupported; - if (!intel_dp->psr.sink_panel_replay_su_support) + if (!connector->dp.panel_replay_caps.su_support) goto unsupported; if (intel_dsc_enabled_on_link(crtc_state) && - intel_dp->psr.sink_panel_replay_dsc_support != + connector->dp.panel_replay_caps.dsc_support != INTEL_DP_PANEL_REPLAY_DSC_SELECTIVE_UPDATE) { drm_dbg_kms(display->drm, "Selective update with Panel Replay not enabled because it's not supported with DSC\n"); @@ -1671,14 +1676,14 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, goto unsupported; } - if (!psr2_granularity_check(intel_dp, crtc_state)) { + if (!psr2_granularity_check(crtc_state, connector)) { drm_dbg_kms(display->drm, "Selective update not enabled, SU granularity not compatible\n"); goto unsupported; } - crtc_state->enable_psr2_su_region_et = - psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay); + crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector, + crtc_state->has_panel_replay); return true; @@ -1688,7 +1693,8 @@ static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, } static bool _psr_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(intel_dp); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; @@ -1703,7 +1709,7 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, if (crtc_state->vrr.enable) return false; - entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, adjusted_mode); + entry_setup_frames = intel_psr_entry_setup_frames(intel_dp, conn_state, adjusted_mode); if (entry_setup_frames >= 0) { intel_dp->psr.entry_setup_frames = entry_setup_frames; @@ -1717,19 +1723,33 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, return true; } -static bool -_panel_replay_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) +static inline bool compute_link_off_after_as_sdp_when_pr_active(struct intel_connector *connector) +{ + return (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & + DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP); +} + +static inline bool compute_disable_as_sdp_when_pr_active(struct intel_connector *connector) +{ + return !(connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] & + DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR); +} + +static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) { - struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_dp *intel_dp = intel_attached_dp(connector); + struct intel_display *display = to_intel_display(intel_dp); struct intel_hdcp *hdcp = &connector->hdcp; if (!CAN_PANEL_REPLAY(intel_dp)) return false; + if (!connector->dp.panel_replay_caps.support) + return false; + if (!panel_replay_global_enabled(intel_dp)) { drm_dbg_kms(display->drm, "Panel Replay disabled by flag\n"); return false; @@ -1742,13 +1762,16 @@ _panel_replay_compute_config(struct intel_dp *intel_dp, } if (intel_dsc_enabled_on_link(crtc_state) && - intel_dp->psr.sink_panel_replay_dsc_support == + connector->dp.panel_replay_caps.dsc_support == INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED) { drm_dbg_kms(display->drm, "Panel Replay not enabled because it's not supported with DSC\n"); return false; } + crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector); + crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector); + if (!intel_dp_is_edp(intel_dp)) return true; @@ -1824,6 +1847,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, struct drm_connector_state *conn_state) { struct intel_display *display = to_intel_display(intel_dp); + struct intel_connector *connector = to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; if (!psr_global_enabled(intel_dp)) { @@ -1855,18 +1879,16 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, } /* Only used for state verification. */ - crtc_state->panel_replay_dsc_support = intel_dp->psr.sink_panel_replay_dsc_support; - crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp, - crtc_state, - conn_state); + crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support; + crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state); crtc_state->has_psr = crtc_state->has_panel_replay ? true : - _psr_compute_config(intel_dp, crtc_state); + _psr_compute_config(intel_dp, crtc_state, conn_state); if (!crtc_state->has_psr) return; - crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_sel_update_config_valid(crtc_state, conn_state); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -2701,7 +2723,7 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state, for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { struct drm_rect inter; - if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) + if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) continue; if (plane->id != PLANE_CURSOR) @@ -2734,7 +2756,7 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state if (plane_state->uapi.dst.y1 < 0 || plane_state->uapi.dst.x1 < 0 || plane_state->scaler_id >= 0 || - plane_state->uapi.rotation != DRM_MODE_ROTATE_0) + plane_state->hw.rotation != DRM_MODE_ROTATE_0) return false; return true; @@ -2749,7 +2771,8 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state */ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state) { - if (crtc_state->scaler_state.scaler_id >= 0) + if (crtc_state->scaler_state.scaler_id >= 0 || + crtc_state->async_flip_planes) return false; return true; @@ -2838,7 +2861,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, .x2 = INT_MAX }; - if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) + if (new_plane_state->hw.crtc != crtc_state->uapi.crtc) continue; if (!new_plane_state->uapi.visible && @@ -2937,7 +2960,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct drm_rect *sel_fetch_area, inter; struct intel_plane *linked = new_plane_state->planar_linked_plane; - if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || + if (new_plane_state->hw.crtc != crtc_state->uapi.crtc || !new_plane_state->uapi.visible) continue; @@ -2992,9 +3015,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, return 0; } -void intel_psr2_panic_force_full_update(struct intel_display *display, - struct intel_crtc_state *crtc_state) +void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state) { + struct intel_display *display = to_intel_display(crtc_state); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val = man_trk_ctl_enable_bit_get(display); @@ -4109,24 +4132,22 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); } -static void intel_psr_sink_capability(struct intel_dp *intel_dp, +static void intel_psr_sink_capability(struct intel_connector *connector, struct seq_file *m) { - struct intel_psr *psr = &intel_dp->psr; - seq_printf(m, "Sink support: PSR = %s", - str_yes_no(psr->sink_support)); + str_yes_no(connector->dp.psr_caps.support)); - if (psr->sink_support) - seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); - if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) + if (connector->dp.psr_caps.support) + seq_printf(m, " [0x%02x]", connector->dp.psr_caps.dpcd[0]); + if (connector->dp.psr_caps.dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) seq_printf(m, " (Early Transport)"); - seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay = %s", str_yes_no(connector->dp.panel_replay_caps.support)); seq_printf(m, ", Panel Replay Selective Update = %s", - str_yes_no(psr->sink_panel_replay_su_support)); + str_yes_no(connector->dp.panel_replay_caps.su_support)); seq_printf(m, ", Panel Replay DSC support = %s", - panel_replay_dsc_support_str(psr->sink_panel_replay_dsc_support)); - if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & + panel_replay_dsc_support_str(connector->dp.panel_replay_caps.dsc_support)); + if (connector->dp.panel_replay_caps.dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_SUPPORT)] & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) seq_printf(m, " (Early Transport)"); seq_printf(m, "\n"); @@ -4164,7 +4185,8 @@ static void intel_psr_print_mode(struct intel_dp *intel_dp, seq_printf(m, " %s\n", psr->no_psr_reason); } -static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) +static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp, + struct intel_connector *connector) { struct intel_display *display = to_intel_display(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; @@ -4173,9 +4195,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) bool enabled; u32 val, psr2_ctl; - intel_psr_sink_capability(intel_dp, m); + intel_psr_sink_capability(connector, m); - if (!(psr->sink_support || psr->sink_panel_replay_support)) + if (!(connector->dp.psr_caps.support || connector->dp.panel_replay_caps.support)) return 0; wakeref = intel_display_rpm_get(display); @@ -4289,7 +4311,7 @@ static int i915_edp_psr_status_show(struct seq_file *m, void *data) if (!intel_dp) return -ENODEV; - return intel_psr_status(m, intel_dp); + return intel_psr_status(m, intel_dp, intel_dp->attached_connector); } DEFINE_SHOW_ATTRIBUTE(i915_edp_psr_status); @@ -4423,7 +4445,7 @@ static int i915_psr_status_show(struct seq_file *m, void *data) struct intel_connector *connector = m->private; struct intel_dp *intel_dp = intel_attached_dp(connector); - return intel_psr_status(m, intel_dp); + return intel_psr_status(m, intel_dp, connector); } DEFINE_SHOW_ATTRIBUTE(i915_psr_status); diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 620b359288326..b41dc4d44ff29 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -28,7 +28,7 @@ struct intel_plane_state; bool intel_encoder_can_psr(struct intel_encoder *encoder); bool intel_psr_needs_aux_io_power(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); -void intel_psr_init_dpcd(struct intel_dp *intel_dp); +void intel_psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector); void intel_psr_panel_replay_enable_sink(struct intel_dp *intel_dp); void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc); @@ -59,8 +59,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); -void intel_psr2_panic_force_full_update(struct intel_display *display, - struct intel_crtc_state *crtc_state); +void intel_psr2_panic_force_full_update(const struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/soc/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c similarity index 96% rename from drivers/gpu/drm/i915/soc/intel_rom.c rename to drivers/gpu/drm/i915/display/intel_rom.c index 2f17dc856e7f3..c8f6153153103 100644 --- a/drivers/gpu/drm/i915/soc/intel_rom.c +++ b/drivers/gpu/drm/i915/display/intel_rom.c @@ -3,7 +3,10 @@ * Copyright © 2024 Intel Corporation */ -#include "i915_drv.h" +#include + +#include + #include "i915_reg.h" #include "intel_rom.h" @@ -41,7 +44,6 @@ static u16 spi_read16(struct intel_rom *rom, loff_t offset) struct intel_rom *intel_rom_spi(struct drm_device *drm) { - struct drm_i915_private *i915 = to_i915(drm); struct intel_rom *rom; u32 static_region; @@ -49,7 +51,7 @@ struct intel_rom *intel_rom_spi(struct drm_device *drm) if (!rom) return NULL; - rom->uncore = &i915->uncore; + rom->uncore = to_intel_uncore(drm); static_region = intel_uncore_read(rom->uncore, SPI_STATIC_REGIONS); static_region &= OPTIONROM_SPI_REGIONID_MASK; diff --git a/drivers/gpu/drm/i915/soc/intel_rom.h b/drivers/gpu/drm/i915/display/intel_rom.h similarity index 100% rename from drivers/gpu/drm/i915/soc/intel_rom.h rename to drivers/gpu/drm/i915/display/intel_rom.h diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 69b6873a6044a..6a65f92e8a031 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -462,7 +462,7 @@ vlv_sprite_get_hw_state(struct intel_plane *plane, struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; enum plane_id plane_id = plane->id; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); @@ -893,7 +893,7 @@ ivb_sprite_get_hw_state(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); @@ -1233,7 +1233,7 @@ g4x_sprite_get_hw_state(struct intel_plane *plane, { struct intel_display *display = to_intel_display(plane); enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; bool ret; power_domain = POWER_DOMAIN_PIPE(plane->pipe); @@ -1567,6 +1567,7 @@ static const struct drm_plane_funcs g4x_sprite_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = g4x_sprite_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static const struct drm_plane_funcs snb_sprite_funcs = { @@ -1576,6 +1577,7 @@ static const struct drm_plane_funcs snb_sprite_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = snb_sprite_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; static const struct drm_plane_funcs vlv_sprite_funcs = { @@ -1585,6 +1587,7 @@ static const struct drm_plane_funcs vlv_sprite_funcs = { .atomic_duplicate_state = intel_plane_duplicate_state, .atomic_destroy_state = intel_plane_destroy_state, .format_mod_supported = vlv_sprite_format_mod_supported, + .format_mod_supported_async = intel_plane_format_mod_supported_async, }; struct intel_plane * diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 1e21fd02685dd..064f572bbc850 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -51,7 +51,7 @@ struct intel_tc_port { const struct intel_tc_phy_ops *phy_ops; struct mutex lock; /* protects the TypeC port mode */ - intel_wakeref_t lock_wakeref; + struct ref_tracker *lock_wakeref; #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) enum intel_display_power_domain lock_power_domain; #endif @@ -182,7 +182,7 @@ bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port) intel_display_power_legacy_aux_domain(display, dig_port->aux_ch); } -static intel_wakeref_t +static struct ref_tracker * __tc_cold_block(struct intel_tc_port *tc, enum intel_display_power_domain *domain) { struct intel_display *display = to_intel_display(tc->dig_port); @@ -192,11 +192,11 @@ __tc_cold_block(struct intel_tc_port *tc, enum intel_display_power_domain *domai return intel_display_power_get(display, *domain); } -static intel_wakeref_t +static struct ref_tracker * tc_cold_block(struct intel_tc_port *tc) { enum intel_display_power_domain domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; wakeref = __tc_cold_block(tc, &domain); #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) @@ -207,7 +207,7 @@ tc_cold_block(struct intel_tc_port *tc) static void __tc_cold_unblock(struct intel_tc_port *tc, enum intel_display_power_domain domain, - intel_wakeref_t wakeref) + struct ref_tracker *wakeref) { struct intel_display *display = to_intel_display(tc->dig_port); @@ -215,7 +215,7 @@ __tc_cold_unblock(struct intel_tc_port *tc, enum intel_display_power_domain doma } static void -tc_cold_unblock(struct intel_tc_port *tc, intel_wakeref_t wakeref) +tc_cold_unblock(struct intel_tc_port *tc, struct ref_tracker *wakeref) { struct intel_display __maybe_unused *display = to_intel_display(tc->dig_port); enum intel_display_power_domain domain = tc_phy_cold_off_domain(tc); @@ -269,10 +269,9 @@ assert_tc_port_power_enabled(struct intel_tc_port *tc) static u32 get_lane_mask(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); - intel_wakeref_t wakeref; u32 lane_mask; - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) lane_mask = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); drm_WARN_ON(display->drm, lane_mask == 0xffffffff); @@ -296,7 +295,6 @@ get_pin_assignment(struct intel_tc_port *tc) struct intel_display *display = to_intel_display(tc->dig_port); enum tc_port tc_port = intel_encoder_to_tc(&tc->dig_port->base); enum intel_tc_pin_assignment pin_assignment; - intel_wakeref_t wakeref; i915_reg_t reg; u32 mask; u32 val; @@ -312,7 +310,7 @@ get_pin_assignment(struct intel_tc_port *tc) mask = DP_PIN_ASSIGNMENT_MASK(tc->phy_fia_idx); } - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) val = intel_de_read(display, reg); drm_WARN_ON(display->drm, val == 0xffffffff); @@ -527,12 +525,11 @@ static u32 icl_tc_phy_hpd_live_status(struct intel_tc_port *tc) struct intel_display *display = to_intel_display(tc->dig_port); struct intel_digital_port *dig_port = tc->dig_port; u32 isr_bit = display->hotplug.pch_hpd[dig_port->base.hpd_pin]; - intel_wakeref_t wakeref; u32 fia_isr; u32 pch_isr; u32 mask = 0; - with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) { + with_intel_display_power(display, tc_phy_cold_off_domain(tc)) { fia_isr = intel_de_read(display, PORT_TX_DFLEXDPSP(tc->phy_fia)); pch_isr = intel_de_read(display, SDEISR); } @@ -628,7 +625,7 @@ static bool icl_tc_phy_is_owned(struct intel_tc_port *tc) static void icl_tc_phy_get_hw_state(struct intel_tc_port *tc) { enum intel_display_power_domain domain; - intel_wakeref_t tc_cold_wref; + struct ref_tracker *tc_cold_wref; tc_cold_wref = __tc_cold_block(tc, &domain); @@ -774,10 +771,9 @@ tgl_tc_phy_cold_off_domain(struct intel_tc_port *tc) static void tgl_tc_phy_init(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); - intel_wakeref_t wakeref; u32 val; - with_intel_display_power(display, tc_phy_cold_off_domain(tc), wakeref) + with_intel_display_power(display, tc_phy_cold_off_domain(tc)) val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1)); drm_WARN_ON(display->drm, val == 0xffffffff); @@ -819,12 +815,11 @@ static u32 adlp_tc_phy_hpd_live_status(struct intel_tc_port *tc) enum hpd_pin hpd_pin = dig_port->base.hpd_pin; u32 cpu_isr_bits = display->hotplug.hpd[hpd_pin]; u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin]; - intel_wakeref_t wakeref; u32 cpu_isr; u32 pch_isr; u32 mask = 0; - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR); pch_isr = intel_de_read(display, SDEISR); } @@ -897,7 +892,7 @@ static void adlp_tc_phy_get_hw_state(struct intel_tc_port *tc) struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); - intel_wakeref_t port_wakeref; + struct ref_tracker *port_wakeref; port_wakeref = intel_display_power_get(display, port_power_domain); @@ -916,7 +911,7 @@ static bool adlp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes) struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); - intel_wakeref_t port_wakeref; + struct ref_tracker *port_wakeref; if (tc->mode == TC_PORT_TBT_ALT) { tc->lock_wakeref = tc_cold_block(tc); @@ -968,7 +963,7 @@ static void adlp_tc_phy_disconnect(struct intel_tc_port *tc) struct intel_display *display = to_intel_display(tc->dig_port); enum intel_display_power_domain port_power_domain = tc_port_power_domain(tc); - intel_wakeref_t port_wakeref; + struct ref_tracker *port_wakeref; port_wakeref = intel_display_power_get(display, port_power_domain); @@ -1015,12 +1010,11 @@ static u32 xelpdp_tc_phy_hpd_live_status(struct intel_tc_port *tc) enum hpd_pin hpd_pin = dig_port->base.hpd_pin; u32 pica_isr_bits = display->hotplug.hpd[hpd_pin]; u32 pch_isr_bit = display->hotplug.pch_hpd[hpd_pin]; - intel_wakeref_t wakeref; u32 pica_isr; u32 pch_isr; u32 mask = 0; - with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) { + with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE) { pica_isr = intel_de_read(display, PICAINTERRUPT_ISR); pch_isr = intel_de_read(display, SDEISR); } @@ -1175,7 +1169,7 @@ static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc) static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc) { struct intel_display *display = to_intel_display(tc->dig_port); - intel_wakeref_t tc_cold_wref; + struct ref_tracker *tc_cold_wref; enum intel_display_power_domain domain; tc_cold_wref = __tc_cold_block(tc, &domain); diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 671f357c65638..1b7cfe226ff8f 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -8,7 +8,6 @@ #include #include -#include "i915_drv.h" #include "intel_color.h" #include "intel_crtc.h" #include "intel_de.h" @@ -305,17 +304,17 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) */ #ifdef I915 static void intel_vblank_section_enter(struct intel_display *display) - __acquires(i915->uncore.lock) + __acquires(uncore->lock) { - struct drm_i915_private *i915 = to_i915(display->drm); - spin_lock(&i915->uncore.lock); + struct intel_uncore *uncore = to_intel_uncore(display->drm); + spin_lock(&uncore->lock); } static void intel_vblank_section_exit(struct intel_display *display) - __releases(i915->uncore.lock) + __releases(uncore->lock) { - struct drm_i915_private *i915 = to_i915(display->drm); - spin_unlock(&i915->uncore.lock); + struct intel_uncore *uncore = to_intel_uncore(display->drm); + spin_unlock(&uncore->lock); } #else static void intel_vblank_section_enter(struct intel_display *display) @@ -652,6 +651,34 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state, return pre_commit_crtc_state(old_crtc_state, new_crtc_state); } +static int vrr_vblank_start(const struct intel_crtc_state *crtc_state) +{ + bool is_push_sent = intel_vrr_is_push_sent(crtc_state); + int vblank_start; + + if (!crtc_state->vrr.dc_balance.enable) { + if (is_push_sent) + return intel_vrr_vmin_vblank_start(crtc_state); + else + return intel_vrr_vmax_vblank_start(crtc_state); + } + + if (is_push_sent) + vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state); + else + vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state); + + if (vblank_start >= 0) + return vblank_start; + + if (is_push_sent) + vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state); + else + vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state); + + return vblank_start; +} + void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, struct intel_vblank_evade_ctx *evade) @@ -678,10 +705,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) || new_crtc_state->update_m_n || new_crtc_state->update_lrr); - if (intel_vrr_is_push_sent(crtc_state)) - evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state); - else - evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state); + evade->vblank_start = vrr_vblank_start(crtc_state); vblank_delay = crtc_state->set_context_latency; } else { diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 70e31520c560a..57fda5824c9c1 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -554,7 +554,8 @@ struct child_device_config { u8 dvo_function; u8 dp_usb_type_c:1; /* 195+ */ u8 tbt:1; /* 209+ */ - u8 flags2_reserved:2; /* 195+ */ + u8 dedicated_external:1; /* 264+ */ + u8 dyn_port_over_tc:1; /* 264+ */ u8 dp_port_trace_length:4; /* 209+ */ u8 dp_gpio_index; /* 195+ */ u16 dp_gpio_pin_num; /* 195+ */ diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 0e727fc5e80c1..5493082f30a75 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -999,7 +999,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum intel_display_power_domain power_domain; - intel_wakeref_t wakeref; + struct ref_tracker *wakeref; u32 dss_ctl1, dss_ctl2; if (!intel_dsc_source_support(crtc_state)) @@ -1050,15 +1050,40 @@ void intel_vdsc_state_dump(struct drm_printer *p, int indent, drm_dsc_dump_config(p, indent, &crtc_state->dsc.config); } +static +int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display, + int pixel_rate, int htotal, + int dsc_horizontal_slices) +{ + int dsc_slice_bubbles; + u64 num; + + if (drm_WARN_ON(display->drm, !htotal)) + return pixel_rate; + + dsc_slice_bubbles = 14 * dsc_horizontal_slices; + num = mul_u32_u32(pixel_rate, (htotal + dsc_slice_bubbles)); + + return DIV_ROUND_UP_ULL(num, htotal); +} + int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); + int htotal = crtc_state->hw.adjusted_mode.crtc_htotal; + int dsc_slices = crtc_state->dsc.slice_count; + int pixel_rate; int min_cdclk; if (!crtc_state->dsc.compression_enable) return 0; + pixel_rate = intel_dsc_get_pixel_rate_with_dsc_bubbles(display, + crtc_state->pixel_rate, + htotal, + dsc_slices); + /* * When we decide to use only one VDSC engine, since * each VDSC operates with 1 ppc throughput, pixel clock @@ -1066,7 +1091,7 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) * If there 2 VDSC engines, then pixel clock can't be higher than * VDSC clock(cdclk) * 2 and so on. */ - min_cdclk = DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances); + min_cdclk = DIV_ROUND_UP(pixel_rate, num_vdsc_instances); if (crtc_state->joiner_pipes) { int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); @@ -1084,9 +1109,11 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits */ int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; - int min_cdclk_bj = - (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * - pixel_clock) / (2 * bigjoiner_interface_bits); + int adjusted_pixel_rate = + intel_dsc_get_pixel_rate_with_dsc_bubbles(display, pixel_clock, + htotal, dsc_slices); + int min_cdclk_bj = (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * + adjusted_pixel_rate) / (2 * bigjoiner_interface_bits); min_cdclk = max(min_cdclk, min_cdclk_bj); } diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 6e125564db34c..c45c4bbc3f957 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -9,12 +9,12 @@ #include #include +#include #include